; generated by Component: ARM Compiler 5.06 update 7 (build 960) Tool: ArmCC [4d365d]
; commandline ArmCC [--list --split_sections --debug -c --asm --interleave -o.\flash\obj\stm32f10x_dma.o --asm_dir=.\Flash\List\ --list_dir=.\Flash\List\ --depend=.\flash\obj\stm32f10x_dma.d --cpu=Cortex-M3 --apcs=interwork -O0 --diag_suppress=9931,870 -I..\..\Libraries\CMSIS\Device\ST\STM32F10x\Include -I..\..\Libraries\STM32F10x_StdPeriph_Driver\inc -I..\..\Libraries\STM32_USB-FS-Device_Driver\inc -I..\..\Libraries\CMSIS\Include -I..\..\User\bsp -I..\..\User\bsp\inc -I..\..\User\app\inc -I..\..\User -IC:\Users\w1619\AppData\Local\Arm\Packs\Keil\STM32F1xx_DFP\2.4.1\Device\Include -D__MICROLIB -D__UVISION_VERSION=538 -DSTM32F10X_HD -DUSE_STDPERIPH_DRIVER -DSTM32F10X_HD --omf_browse=.\flash\obj\stm32f10x_dma.crf ..\..\Libraries\STM32F10x_StdPeriph_Driver\src\stm32f10x_dma.c]
                          THUMB

                          AREA ||i.DMA_ClearFlag||, CODE, READONLY, ALIGN=2

                  DMA_ClearFlag PROC
;;;528      */
;;;529    void DMA_ClearFlag(uint32_t DMAy_FLAG)
000000  f0005180          AND      r1,r0,#0x10000000
;;;530    {
;;;531      /* Check the parameters */
;;;532      assert_param(IS_DMA_CLEAR_FLAG(DMAy_FLAG));
;;;533    
;;;534      /* Calculate the used DMAy */
;;;535      if ((DMAy_FLAG & FLAG_Mask) != (uint32_t)RESET)
000004  b111              CBZ      r1,|L1.12|
;;;536      {
;;;537        /* Clear the selected DMAy flags */
;;;538        DMA2->IFCR = DMAy_FLAG;
000006  4903              LDR      r1,|L1.20|
000008  6008              STR      r0,[r1,#0]
00000a  e001              B        |L1.16|
                  |L1.12|
;;;539      }
;;;540      else
;;;541      {
;;;542        /* Clear the selected DMAy flags */
;;;543        DMA1->IFCR = DMAy_FLAG;
00000c  4902              LDR      r1,|L1.24|
00000e  6048              STR      r0,[r1,#4]
                  |L1.16|
;;;544      }
;;;545    }
000010  4770              BX       lr
;;;546    
                          ENDP

000012  0000              DCW      0x0000
                  |L1.20|
                          DCD      0x40020404
                  |L1.24|
                          DCD      0x40020000

                          AREA ||i.DMA_ClearITPendingBit||, CODE, READONLY, ALIGN=2

                  DMA_ClearITPendingBit PROC
;;;689      */
;;;690    void DMA_ClearITPendingBit(uint32_t DMAy_IT)
000000  f0005180          AND      r1,r0,#0x10000000
;;;691    {
;;;692      /* Check the parameters */
;;;693      assert_param(IS_DMA_CLEAR_IT(DMAy_IT));
;;;694    
;;;695      /* Calculate the used DMAy */
;;;696      if ((DMAy_IT & FLAG_Mask) != (uint32_t)RESET)
000004  b111              CBZ      r1,|L2.12|
;;;697      {
;;;698        /* Clear the selected DMAy interrupt pending bits */
;;;699        DMA2->IFCR = DMAy_IT;
000006  4903              LDR      r1,|L2.20|
000008  6008              STR      r0,[r1,#0]
00000a  e001              B        |L2.16|
                  |L2.12|
;;;700      }
;;;701      else
;;;702      {
;;;703        /* Clear the selected DMAy interrupt pending bits */
;;;704        DMA1->IFCR = DMAy_IT;
00000c  4902              LDR      r1,|L2.24|
00000e  6048              STR      r0,[r1,#4]
                  |L2.16|
;;;705      }
;;;706    }
000010  4770              BX       lr
;;;707    
                          ENDP

000012  0000              DCW      0x0000
                  |L2.20|
                          DCD      0x40020404
                  |L2.24|
                          DCD      0x40020000

                          AREA ||i.DMA_Cmd||, CODE, READONLY, ALIGN=1

                  DMA_Cmd PROC
;;;299      */
;;;300    void DMA_Cmd(DMA_Channel_TypeDef* DMAy_Channelx, FunctionalState NewState)
000000  b121              CBZ      r1,|L3.12|
;;;301    {
;;;302      /* Check the parameters */
;;;303      assert_param(IS_DMA_ALL_PERIPH(DMAy_Channelx));
;;;304      assert_param(IS_FUNCTIONAL_STATE(NewState));
;;;305    
;;;306      if (NewState != DISABLE)
;;;307      {
;;;308        /* Enable the selected DMAy Channelx */
;;;309        DMAy_Channelx->CCR |= DMA_CCR1_EN;
000002  6802              LDR      r2,[r0,#0]
000004  f0420201          ORR      r2,r2,#1
000008  6002              STR      r2,[r0,#0]
00000a  e004              B        |L3.22|
                  |L3.12|
;;;310      }
;;;311      else
;;;312      {
;;;313        /* Disable the selected DMAy Channelx */
;;;314        DMAy_Channelx->CCR &= (uint16_t)(~DMA_CCR1_EN);
00000c  6802              LDR      r2,[r0,#0]
00000e  f64f73fe          MOV      r3,#0xfffe
000012  401a              ANDS     r2,r2,r3
000014  6002              STR      r2,[r0,#0]
                  |L3.22|
;;;315      }
;;;316    }
000016  4770              BX       lr
;;;317    
                          ENDP


                          AREA ||i.DMA_DeInit||, CODE, READONLY, ALIGN=2

                  DMA_DeInit PROC
;;;113      */
;;;114    void DMA_DeInit(DMA_Channel_TypeDef* DMAy_Channelx)
000000  6801              LDR      r1,[r0,#0]
;;;115    {
;;;116      /* Check the parameters */
;;;117      assert_param(IS_DMA_ALL_PERIPH(DMAy_Channelx));
;;;118      
;;;119      /* Disable the selected DMAy Channelx */
;;;120      DMAy_Channelx->CCR &= (uint16_t)(~DMA_CCR1_EN);
000002  f64f72fe          MOV      r2,#0xfffe
000006  4011              ANDS     r1,r1,r2
000008  6001              STR      r1,[r0,#0]
;;;121      
;;;122      /* Reset DMAy Channelx control register */
;;;123      DMAy_Channelx->CCR  = 0;
00000a  2100              MOVS     r1,#0
00000c  6001              STR      r1,[r0,#0]
;;;124      
;;;125      /* Reset DMAy Channelx remaining bytes register */
;;;126      DMAy_Channelx->CNDTR = 0;
00000e  6041              STR      r1,[r0,#4]
;;;127      
;;;128      /* Reset DMAy Channelx peripheral address register */
;;;129      DMAy_Channelx->CPAR  = 0;
000010  6081              STR      r1,[r0,#8]
;;;130      
;;;131      /* Reset DMAy Channelx memory address register */
;;;132      DMAy_Channelx->CMAR = 0;
000012  60c1              STR      r1,[r0,#0xc]
;;;133      
;;;134      if (DMAy_Channelx == DMA1_Channel1)
000014  494b              LDR      r1,|L4.324|
000016  4288              CMP      r0,r1
000018  d108              BNE      |L4.44|
;;;135      {
;;;136        /* Reset interrupt pending bits for DMA1 Channel1 */
;;;137        DMA1->IFCR |= DMA1_Channel1_IT_Mask;
00001a  494a              LDR      r1,|L4.324|
00001c  3908              SUBS     r1,r1,#8
00001e  6849              LDR      r1,[r1,#4]
000020  f041010f          ORR      r1,r1,#0xf
000024  4a47              LDR      r2,|L4.324|
000026  3a08              SUBS     r2,r2,#8
000028  6051              STR      r1,[r2,#4]
00002a  e08a              B        |L4.322|
                  |L4.44|
;;;138      }
;;;139      else if (DMAy_Channelx == DMA1_Channel2)
00002c  4945              LDR      r1,|L4.324|
00002e  3114              ADDS     r1,r1,#0x14
000030  4288              CMP      r0,r1
000032  d108              BNE      |L4.70|
;;;140      {
;;;141        /* Reset interrupt pending bits for DMA1 Channel2 */
;;;142        DMA1->IFCR |= DMA1_Channel2_IT_Mask;
000034  4943              LDR      r1,|L4.324|
000036  3908              SUBS     r1,r1,#8
000038  6849              LDR      r1,[r1,#4]
00003a  f04101f0          ORR      r1,r1,#0xf0
00003e  4a41              LDR      r2,|L4.324|
000040  3a08              SUBS     r2,r2,#8
000042  6051              STR      r1,[r2,#4]
000044  e07d              B        |L4.322|
                  |L4.70|
;;;143      }
;;;144      else if (DMAy_Channelx == DMA1_Channel3)
000046  493f              LDR      r1,|L4.324|
000048  3128              ADDS     r1,r1,#0x28
00004a  4288              CMP      r0,r1
00004c  d108              BNE      |L4.96|
;;;145      {
;;;146        /* Reset interrupt pending bits for DMA1 Channel3 */
;;;147        DMA1->IFCR |= DMA1_Channel3_IT_Mask;
00004e  493d              LDR      r1,|L4.324|
000050  3908              SUBS     r1,r1,#8
000052  6849              LDR      r1,[r1,#4]
000054  f4416170          ORR      r1,r1,#0xf00
000058  4a3a              LDR      r2,|L4.324|
00005a  3a08              SUBS     r2,r2,#8
00005c  6051              STR      r1,[r2,#4]
00005e  e070              B        |L4.322|
                  |L4.96|
;;;148      }
;;;149      else if (DMAy_Channelx == DMA1_Channel4)
000060  4938              LDR      r1,|L4.324|
000062  313c              ADDS     r1,r1,#0x3c
000064  4288              CMP      r0,r1
000066  d108              BNE      |L4.122|
;;;150      {
;;;151        /* Reset interrupt pending bits for DMA1 Channel4 */
;;;152        DMA1->IFCR |= DMA1_Channel4_IT_Mask;
000068  4936              LDR      r1,|L4.324|
00006a  3908              SUBS     r1,r1,#8
00006c  6849              LDR      r1,[r1,#4]
00006e  f4414170          ORR      r1,r1,#0xf000
000072  4a34              LDR      r2,|L4.324|
000074  3a08              SUBS     r2,r2,#8
000076  6051              STR      r1,[r2,#4]
000078  e063              B        |L4.322|
                  |L4.122|
;;;153      }
;;;154      else if (DMAy_Channelx == DMA1_Channel5)
00007a  4932              LDR      r1,|L4.324|
00007c  3150              ADDS     r1,r1,#0x50
00007e  4288              CMP      r0,r1
000080  d108              BNE      |L4.148|
;;;155      {
;;;156        /* Reset interrupt pending bits for DMA1 Channel5 */
;;;157        DMA1->IFCR |= DMA1_Channel5_IT_Mask;
000082  4930              LDR      r1,|L4.324|
000084  3908              SUBS     r1,r1,#8
000086  6849              LDR      r1,[r1,#4]
000088  f4412170          ORR      r1,r1,#0xf0000
00008c  4a2d              LDR      r2,|L4.324|
00008e  3a08              SUBS     r2,r2,#8
000090  6051              STR      r1,[r2,#4]
000092  e056              B        |L4.322|
                  |L4.148|
;;;158      }
;;;159      else if (DMAy_Channelx == DMA1_Channel6)
000094  492b              LDR      r1,|L4.324|
000096  3164              ADDS     r1,r1,#0x64
000098  4288              CMP      r0,r1
00009a  d108              BNE      |L4.174|
;;;160      {
;;;161        /* Reset interrupt pending bits for DMA1 Channel6 */
;;;162        DMA1->IFCR |= DMA1_Channel6_IT_Mask;
00009c  4929              LDR      r1,|L4.324|
00009e  3908              SUBS     r1,r1,#8
0000a0  6849              LDR      r1,[r1,#4]
0000a2  f4410170          ORR      r1,r1,#0xf00000
0000a6  4a27              LDR      r2,|L4.324|
0000a8  3a08              SUBS     r2,r2,#8
0000aa  6051              STR      r1,[r2,#4]
0000ac  e049              B        |L4.322|
                  |L4.174|
;;;163      }
;;;164      else if (DMAy_Channelx == DMA1_Channel7)
0000ae  4925              LDR      r1,|L4.324|
0000b0  3178              ADDS     r1,r1,#0x78
0000b2  4288              CMP      r0,r1
0000b4  d108              BNE      |L4.200|
;;;165      {
;;;166        /* Reset interrupt pending bits for DMA1 Channel7 */
;;;167        DMA1->IFCR |= DMA1_Channel7_IT_Mask;
0000b6  4923              LDR      r1,|L4.324|
0000b8  3908              SUBS     r1,r1,#8
0000ba  6849              LDR      r1,[r1,#4]
0000bc  f0416170          ORR      r1,r1,#0xf000000
0000c0  4a20              LDR      r2,|L4.324|
0000c2  3a08              SUBS     r2,r2,#8
0000c4  6051              STR      r1,[r2,#4]
0000c6  e03c              B        |L4.322|
                  |L4.200|
;;;168      }
;;;169      else if (DMAy_Channelx == DMA2_Channel1)
0000c8  491f              LDR      r1,|L4.328|
0000ca  4288              CMP      r0,r1
0000cc  d106              BNE      |L4.220|
;;;170      {
;;;171        /* Reset interrupt pending bits for DMA2 Channel1 */
;;;172        DMA2->IFCR |= DMA2_Channel1_IT_Mask;
0000ce  1f01              SUBS     r1,r0,#4
0000d0  6809              LDR      r1,[r1,#0]
0000d2  f041010f          ORR      r1,r1,#0xf
0000d6  1f02              SUBS     r2,r0,#4
0000d8  6011              STR      r1,[r2,#0]
0000da  e032              B        |L4.322|
                  |L4.220|
;;;173      }
;;;174      else if (DMAy_Channelx == DMA2_Channel2)
0000dc  491a              LDR      r1,|L4.328|
0000de  3114              ADDS     r1,r1,#0x14
0000e0  4288              CMP      r0,r1
0000e2  d108              BNE      |L4.246|
;;;175      {
;;;176        /* Reset interrupt pending bits for DMA2 Channel2 */
;;;177        DMA2->IFCR |= DMA2_Channel2_IT_Mask;
0000e4  4918              LDR      r1,|L4.328|
0000e6  1f09              SUBS     r1,r1,#4
0000e8  6809              LDR      r1,[r1,#0]
0000ea  f04101f0          ORR      r1,r1,#0xf0
0000ee  4a16              LDR      r2,|L4.328|
0000f0  1f12              SUBS     r2,r2,#4
0000f2  6011              STR      r1,[r2,#0]
0000f4  e025              B        |L4.322|
                  |L4.246|
;;;178      }
;;;179      else if (DMAy_Channelx == DMA2_Channel3)
0000f6  4914              LDR      r1,|L4.328|
0000f8  3128              ADDS     r1,r1,#0x28
0000fa  4288              CMP      r0,r1
0000fc  d108              BNE      |L4.272|
;;;180      {
;;;181        /* Reset interrupt pending bits for DMA2 Channel3 */
;;;182        DMA2->IFCR |= DMA2_Channel3_IT_Mask;
0000fe  4912              LDR      r1,|L4.328|
000100  1f09              SUBS     r1,r1,#4
000102  6809              LDR      r1,[r1,#0]
000104  f4416170          ORR      r1,r1,#0xf00
000108  4a0f              LDR      r2,|L4.328|
00010a  1f12              SUBS     r2,r2,#4
00010c  6011              STR      r1,[r2,#0]
00010e  e018              B        |L4.322|
                  |L4.272|
;;;183      }
;;;184      else if (DMAy_Channelx == DMA2_Channel4)
000110  490d              LDR      r1,|L4.328|
000112  313c              ADDS     r1,r1,#0x3c
000114  4288              CMP      r0,r1
000116  d108              BNE      |L4.298|
;;;185      {
;;;186        /* Reset interrupt pending bits for DMA2 Channel4 */
;;;187        DMA2->IFCR |= DMA2_Channel4_IT_Mask;
000118  490b              LDR      r1,|L4.328|
00011a  1f09              SUBS     r1,r1,#4
00011c  6809              LDR      r1,[r1,#0]
00011e  f4414170          ORR      r1,r1,#0xf000
000122  4a09              LDR      r2,|L4.328|
000124  1f12              SUBS     r2,r2,#4
000126  6011              STR      r1,[r2,#0]
000128  e00b              B        |L4.322|
                  |L4.298|
;;;188      }
;;;189      else
;;;190      { 
;;;191        if (DMAy_Channelx == DMA2_Channel5)
00012a  4907              LDR      r1,|L4.328|
00012c  3150              ADDS     r1,r1,#0x50
00012e  4288              CMP      r0,r1
000130  d107              BNE      |L4.322|
;;;192        {
;;;193          /* Reset interrupt pending bits for DMA2 Channel5 */
;;;194          DMA2->IFCR |= DMA2_Channel5_IT_Mask;
000132  4905              LDR      r1,|L4.328|
000134  1f09              SUBS     r1,r1,#4
000136  6809              LDR      r1,[r1,#0]
000138  f4412170          ORR      r1,r1,#0xf0000
00013c  4a02              LDR      r2,|L4.328|
00013e  1f12              SUBS     r2,r2,#4
000140  6011              STR      r1,[r2,#0]
                  |L4.322|
;;;195        }
;;;196      }
;;;197    }
000142  4770              BX       lr
;;;198    
                          ENDP

                  |L4.324|
                          DCD      0x40020008
                  |L4.328|
                          DCD      0x40020408

                          AREA ||i.DMA_GetCurrDataCounter||, CODE, READONLY, ALIGN=1

                  DMA_GetCurrDataCounter PROC
;;;376      */
;;;377    uint16_t DMA_GetCurrDataCounter(DMA_Channel_TypeDef* DMAy_Channelx)
000000  4601              MOV      r1,r0
;;;378    {
;;;379      /* Check the parameters */
;;;380      assert_param(IS_DMA_ALL_PERIPH(DMAy_Channelx));
;;;381      /* Return the number of remaining data units for DMAy Channelx */
;;;382      return ((uint16_t)(DMAy_Channelx->CNDTR));
000002  6848              LDR      r0,[r1,#4]
000004  b280              UXTH     r0,r0
;;;383    }
000006  4770              BX       lr
;;;384    
                          ENDP


                          AREA ||i.DMA_GetFlagStatus||, CODE, READONLY, ALIGN=2

                  DMA_GetFlagStatus PROC
;;;438      */
;;;439    FlagStatus DMA_GetFlagStatus(uint32_t DMAy_FLAG)
000000  4601              MOV      r1,r0
;;;440    {
;;;441      FlagStatus bitstatus = RESET;
000002  2000              MOVS     r0,#0
;;;442      uint32_t tmpreg = 0;
000004  2200              MOVS     r2,#0
;;;443      
;;;444      /* Check the parameters */
;;;445      assert_param(IS_DMA_GET_FLAG(DMAy_FLAG));
;;;446    
;;;447      /* Calculate the used DMAy */
;;;448      if ((DMAy_FLAG & FLAG_Mask) != (uint32_t)RESET)
000006  f0015380          AND      r3,r1,#0x10000000
00000a  b113              CBZ      r3,|L6.18|
;;;449      {
;;;450        /* Get DMA2 ISR register value */
;;;451        tmpreg = DMA2->ISR ;
00000c  4b05              LDR      r3,|L6.36|
00000e  681a              LDR      r2,[r3,#0]
000010  e001              B        |L6.22|
                  |L6.18|
;;;452      }
;;;453      else
;;;454      {
;;;455        /* Get DMA1 ISR register value */
;;;456        tmpreg = DMA1->ISR ;
000012  4b05              LDR      r3,|L6.40|
000014  681a              LDR      r2,[r3,#0]
                  |L6.22|
;;;457      }
;;;458    
;;;459      /* Check the status of the specified DMAy flag */
;;;460      if ((tmpreg & DMAy_FLAG) != (uint32_t)RESET)
000016  ea020301          AND      r3,r2,r1
00001a  b10b              CBZ      r3,|L6.32|
;;;461      {
;;;462        /* DMAy_FLAG is set */
;;;463        bitstatus = SET;
00001c  2001              MOVS     r0,#1
00001e  e000              B        |L6.34|
                  |L6.32|
;;;464      }
;;;465      else
;;;466      {
;;;467        /* DMAy_FLAG is reset */
;;;468        bitstatus = RESET;
000020  2000              MOVS     r0,#0
                  |L6.34|
;;;469      }
;;;470      
;;;471      /* Return the DMAy_FLAG status */
;;;472      return  bitstatus;
;;;473    }
000022  4770              BX       lr
;;;474    
                          ENDP

                  |L6.36|
                          DCD      0x40020400
                  |L6.40|
                          DCD      0x40020000

                          AREA ||i.DMA_GetITStatus||, CODE, READONLY, ALIGN=2

                  DMA_GetITStatus PROC
;;;600      */
;;;601    ITStatus DMA_GetITStatus(uint32_t DMAy_IT)
000000  4601              MOV      r1,r0
;;;602    {
;;;603      ITStatus bitstatus = RESET;
000002  2000              MOVS     r0,#0
;;;604      uint32_t tmpreg = 0;
000004  2200              MOVS     r2,#0
;;;605    
;;;606      /* Check the parameters */
;;;607      assert_param(IS_DMA_GET_IT(DMAy_IT));
;;;608    
;;;609      /* Calculate the used DMA */
;;;610      if ((DMAy_IT & FLAG_Mask) != (uint32_t)RESET)
000006  f0015380          AND      r3,r1,#0x10000000
00000a  b113              CBZ      r3,|L7.18|
;;;611      {
;;;612        /* Get DMA2 ISR register value */
;;;613        tmpreg = DMA2->ISR;
00000c  4b05              LDR      r3,|L7.36|
00000e  681a              LDR      r2,[r3,#0]
000010  e001              B        |L7.22|
                  |L7.18|
;;;614      }
;;;615      else
;;;616      {
;;;617        /* Get DMA1 ISR register value */
;;;618        tmpreg = DMA1->ISR;
000012  4b05              LDR      r3,|L7.40|
000014  681a              LDR      r2,[r3,#0]
                  |L7.22|
;;;619      }
;;;620    
;;;621      /* Check the status of the specified DMAy interrupt */
;;;622      if ((tmpreg & DMAy_IT) != (uint32_t)RESET)
000016  ea020301          AND      r3,r2,r1
00001a  b10b              CBZ      r3,|L7.32|
;;;623      {
;;;624        /* DMAy_IT is set */
;;;625        bitstatus = SET;
00001c  2001              MOVS     r0,#1
00001e  e000              B        |L7.34|
                  |L7.32|
;;;626      }
;;;627      else
;;;628      {
;;;629        /* DMAy_IT is reset */
;;;630        bitstatus = RESET;
000020  2000              MOVS     r0,#0
                  |L7.34|
;;;631      }
;;;632      /* Return the DMA_IT status */
;;;633      return  bitstatus;
;;;634    }
000022  4770              BX       lr
;;;635    
                          ENDP

                  |L7.36|
                          DCD      0x40020400
                  |L7.40|
                          DCD      0x40020000

                          AREA ||i.DMA_ITConfig||, CODE, READONLY, ALIGN=1

                  DMA_ITConfig PROC
;;;331      */
;;;332    void DMA_ITConfig(DMA_Channel_TypeDef* DMAy_Channelx, uint32_t DMA_IT, FunctionalState NewState)
000000  b11a              CBZ      r2,|L8.10|
;;;333    {
;;;334      /* Check the parameters */
;;;335      assert_param(IS_DMA_ALL_PERIPH(DMAy_Channelx));
;;;336      assert_param(IS_DMA_CONFIG_IT(DMA_IT));
;;;337      assert_param(IS_FUNCTIONAL_STATE(NewState));
;;;338      if (NewState != DISABLE)
;;;339      {
;;;340        /* Enable the selected DMA interrupts */
;;;341        DMAy_Channelx->CCR |= DMA_IT;
000002  6803              LDR      r3,[r0,#0]
000004  430b              ORRS     r3,r3,r1
000006  6003              STR      r3,[r0,#0]
000008  e002              B        |L8.16|
                  |L8.10|
;;;342      }
;;;343      else
;;;344      {
;;;345        /* Disable the selected DMA interrupts */
;;;346        DMAy_Channelx->CCR &= ~DMA_IT;
00000a  6803              LDR      r3,[r0,#0]
00000c  438b              BICS     r3,r3,r1
00000e  6003              STR      r3,[r0,#0]
                  |L8.16|
;;;347      }
;;;348    }
000010  4770              BX       lr
;;;349    
                          ENDP


                          AREA ||i.DMA_Init||, CODE, READONLY, ALIGN=1

                  DMA_Init PROC
;;;207      */
;;;208    void DMA_Init(DMA_Channel_TypeDef* DMAy_Channelx, DMA_InitTypeDef* DMA_InitStruct)
000000  b510              PUSH     {r4,lr}
;;;209    {
;;;210      uint32_t tmpreg = 0;
000002  2200              MOVS     r2,#0
;;;211    
;;;212      /* Check the parameters */
;;;213      assert_param(IS_DMA_ALL_PERIPH(DMAy_Channelx));
;;;214      assert_param(IS_DMA_DIR(DMA_InitStruct->DMA_DIR));
;;;215      assert_param(IS_DMA_BUFFER_SIZE(DMA_InitStruct->DMA_BufferSize));
;;;216      assert_param(IS_DMA_PERIPHERAL_INC_STATE(DMA_InitStruct->DMA_PeripheralInc));
;;;217      assert_param(IS_DMA_MEMORY_INC_STATE(DMA_InitStruct->DMA_MemoryInc));   
;;;218      assert_param(IS_DMA_PERIPHERAL_DATA_SIZE(DMA_InitStruct->DMA_PeripheralDataSize));
;;;219      assert_param(IS_DMA_MEMORY_DATA_SIZE(DMA_InitStruct->DMA_MemoryDataSize));
;;;220      assert_param(IS_DMA_MODE(DMA_InitStruct->DMA_Mode));
;;;221      assert_param(IS_DMA_PRIORITY(DMA_InitStruct->DMA_Priority));
;;;222      assert_param(IS_DMA_M2M_STATE(DMA_InitStruct->DMA_M2M));
;;;223    
;;;224    /*--------------------------- DMAy Channelx CCR Configuration -----------------*/
;;;225      /* Get the DMAy_Channelx CCR value */
;;;226      tmpreg = DMAy_Channelx->CCR;
000004  6802              LDR      r2,[r0,#0]
;;;227      /* Clear MEM2MEM, PL, MSIZE, PSIZE, MINC, PINC, CIRC and DIR bits */
;;;228      tmpreg &= CCR_CLEAR_Mask;
000006  f64773f0          MOV      r3,#0x7ff0
00000a  439a              BICS     r2,r2,r3
;;;229      /* Configure DMAy Channelx: data transfer, data size, priority level and mode */
;;;230      /* Set DIR bit according to DMA_DIR value */
;;;231      /* Set CIRC bit according to DMA_Mode value */
;;;232      /* Set PINC bit according to DMA_PeripheralInc value */
;;;233      /* Set MINC bit according to DMA_MemoryInc value */
;;;234      /* Set PSIZE bits according to DMA_PeripheralDataSize value */
;;;235      /* Set MSIZE bits according to DMA_MemoryDataSize value */
;;;236      /* Set PL bits according to DMA_Priority value */
;;;237      /* Set the MEM2MEM bit according to DMA_M2M value */
;;;238      tmpreg |= DMA_InitStruct->DMA_DIR | DMA_InitStruct->DMA_Mode |
00000c  6a0c              LDR      r4,[r1,#0x20]
00000e  688b              LDR      r3,[r1,#8]
000010  4323              ORRS     r3,r3,r4
000012  690c              LDR      r4,[r1,#0x10]
000014  4323              ORRS     r3,r3,r4
000016  694c              LDR      r4,[r1,#0x14]
000018  4323              ORRS     r3,r3,r4
00001a  698c              LDR      r4,[r1,#0x18]
00001c  4323              ORRS     r3,r3,r4
00001e  69cc              LDR      r4,[r1,#0x1c]
000020  4323              ORRS     r3,r3,r4
000022  6a4c              LDR      r4,[r1,#0x24]
000024  4323              ORRS     r3,r3,r4
000026  6a8c              LDR      r4,[r1,#0x28]
000028  4323              ORRS     r3,r3,r4
00002a  431a              ORRS     r2,r2,r3
;;;239                DMA_InitStruct->DMA_PeripheralInc | DMA_InitStruct->DMA_MemoryInc |
;;;240                DMA_InitStruct->DMA_PeripheralDataSize | DMA_InitStruct->DMA_MemoryDataSize |
;;;241                DMA_InitStruct->DMA_Priority | DMA_InitStruct->DMA_M2M;
;;;242    
;;;243      /* Write to DMAy Channelx CCR */
;;;244      DMAy_Channelx->CCR = tmpreg;
00002c  6002              STR      r2,[r0,#0]
;;;245    
;;;246    /*--------------------------- DMAy Channelx CNDTR Configuration ---------------*/
;;;247      /* Write to DMAy Channelx CNDTR */
;;;248      DMAy_Channelx->CNDTR = DMA_InitStruct->DMA_BufferSize;
00002e  68cb              LDR      r3,[r1,#0xc]
000030  6043              STR      r3,[r0,#4]
;;;249    
;;;250    /*--------------------------- DMAy Channelx CPAR Configuration ----------------*/
;;;251      /* Write to DMAy Channelx CPAR */
;;;252      DMAy_Channelx->CPAR = DMA_InitStruct->DMA_PeripheralBaseAddr;
000032  680b              LDR      r3,[r1,#0]
000034  6083              STR      r3,[r0,#8]
;;;253    
;;;254    /*--------------------------- DMAy Channelx CMAR Configuration ----------------*/
;;;255      /* Write to DMAy Channelx CMAR */
;;;256      DMAy_Channelx->CMAR = DMA_InitStruct->DMA_MemoryBaseAddr;
000036  684b              LDR      r3,[r1,#4]
000038  60c3              STR      r3,[r0,#0xc]
;;;257    }
00003a  bd10              POP      {r4,pc}
;;;258    
                          ENDP


                          AREA ||i.DMA_SetCurrDataCounter||, CODE, READONLY, ALIGN=1

                  DMA_SetCurrDataCounter PROC
;;;358      */
;;;359    void DMA_SetCurrDataCounter(DMA_Channel_TypeDef* DMAy_Channelx, uint16_t DataNumber)
000000  6041              STR      r1,[r0,#4]
;;;360    {
;;;361      /* Check the parameters */
;;;362      assert_param(IS_DMA_ALL_PERIPH(DMAy_Channelx));
;;;363      
;;;364    /*--------------------------- DMAy Channelx CNDTR Configuration ---------------*/
;;;365      /* Write to DMAy Channelx CNDTR */
;;;366      DMAy_Channelx->CNDTR = DataNumber;  
;;;367    }
000002  4770              BX       lr
;;;368    
                          ENDP


                          AREA ||i.DMA_StructInit||, CODE, READONLY, ALIGN=1

                  DMA_StructInit PROC
;;;264      */
;;;265    void DMA_StructInit(DMA_InitTypeDef* DMA_InitStruct)
000000  2100              MOVS     r1,#0
;;;266    {
;;;267    /*-------------- Reset DMA init structure parameters values ------------------*/
;;;268      /* Initialize the DMA_PeripheralBaseAddr member */
;;;269      DMA_InitStruct->DMA_PeripheralBaseAddr = 0;
000002  6001              STR      r1,[r0,#0]
;;;270      /* Initialize the DMA_MemoryBaseAddr member */
;;;271      DMA_InitStruct->DMA_MemoryBaseAddr = 0;
000004  6041              STR      r1,[r0,#4]
;;;272      /* Initialize the DMA_DIR member */
;;;273      DMA_InitStruct->DMA_DIR = DMA_DIR_PeripheralSRC;
000006  6081              STR      r1,[r0,#8]
;;;274      /* Initialize the DMA_BufferSize member */
;;;275      DMA_InitStruct->DMA_BufferSize = 0;
000008  60c1              STR      r1,[r0,#0xc]
;;;276      /* Initialize the DMA_PeripheralInc member */
;;;277      DMA_InitStruct->DMA_PeripheralInc = DMA_PeripheralInc_Disable;
00000a  6101              STR      r1,[r0,#0x10]
;;;278      /* Initialize the DMA_MemoryInc member */
;;;279      DMA_InitStruct->DMA_MemoryInc = DMA_MemoryInc_Disable;
00000c  6141              STR      r1,[r0,#0x14]
;;;280      /* Initialize the DMA_PeripheralDataSize member */
;;;281      DMA_InitStruct->DMA_PeripheralDataSize = DMA_PeripheralDataSize_Byte;
00000e  6181              STR      r1,[r0,#0x18]
;;;282      /* Initialize the DMA_MemoryDataSize member */
;;;283      DMA_InitStruct->DMA_MemoryDataSize = DMA_MemoryDataSize_Byte;
000010  61c1              STR      r1,[r0,#0x1c]
;;;284      /* Initialize the DMA_Mode member */
;;;285      DMA_InitStruct->DMA_Mode = DMA_Mode_Normal;
000012  6201              STR      r1,[r0,#0x20]
;;;286      /* Initialize the DMA_Priority member */
;;;287      DMA_InitStruct->DMA_Priority = DMA_Priority_Low;
000014  6241              STR      r1,[r0,#0x24]
;;;288      /* Initialize the DMA_M2M member */
;;;289      DMA_InitStruct->DMA_M2M = DMA_M2M_Disable;
000016  6281              STR      r1,[r0,#0x28]
;;;290    }
000018  4770              BX       lr
;;;291    
                          ENDP


;*** Start embedded assembler ***

#line 1 "..\\..\\Libraries\\STM32F10x_StdPeriph_Driver\\src\\stm32f10x_dma.c"
	AREA ||.rev16_text||, CODE
	THUMB
	EXPORT |__asm___15_stm32f10x_dma_c_e9b554c0____REV16|
#line 114 "..\\..\\Libraries\\CMSIS\\Include\\core_cmInstr.h"
|__asm___15_stm32f10x_dma_c_e9b554c0____REV16| PROC
#line 115

 rev16 r0, r0
 bx lr
	ENDP
	AREA ||.revsh_text||, CODE
	THUMB
	EXPORT |__asm___15_stm32f10x_dma_c_e9b554c0____REVSH|
#line 128
|__asm___15_stm32f10x_dma_c_e9b554c0____REVSH| PROC
#line 129

 revsh r0, r0
 bx lr
	ENDP

;*** End   embedded assembler ***
