; generated by Component: ARM Compiler 5.06 update 7 (build 960) Tool: ArmCC [4d365d]
; commandline ArmCC [--list --split_sections --debug -c --asm --interleave -o.\flash\obj\stm32f10x_dac.o --asm_dir=.\Flash\List\ --list_dir=.\Flash\List\ --depend=.\flash\obj\stm32f10x_dac.d --cpu=Cortex-M3 --apcs=interwork -O0 --diag_suppress=9931,870 -I..\..\Libraries\CMSIS\Device\ST\STM32F10x\Include -I..\..\Libraries\STM32F10x_StdPeriph_Driver\inc -I..\..\Libraries\STM32_USB-FS-Device_Driver\inc -I..\..\Libraries\CMSIS\Include -I..\..\User\bsp -I..\..\User\bsp\inc -I..\..\User\app\inc -I..\..\User -IC:\Users\w1619\AppData\Local\Arm\Packs\Keil\STM32F1xx_DFP\2.4.1\Device\Include -D__MICROLIB -D__UVISION_VERSION=538 -DSTM32F10X_HD -DUSE_STDPERIPH_DRIVER -DSTM32F10X_HD --omf_browse=.\flash\obj\stm32f10x_dac.crf ..\..\Libraries\STM32F10x_StdPeriph_Driver\src\stm32f10x_dac.c]
                          THUMB

                          AREA ||i.DAC_Cmd||, CODE, READONLY, ALIGN=2

                  DAC_Cmd PROC
;;;178      */
;;;179    void DAC_Cmd(uint32_t DAC_Channel, FunctionalState NewState)
000000  b139              CBZ      r1,|L1.18|
;;;180    {
;;;181      /* Check the parameters */
;;;182      assert_param(IS_DAC_CHANNEL(DAC_Channel));
;;;183      assert_param(IS_FUNCTIONAL_STATE(NewState));
;;;184      if (NewState != DISABLE)
;;;185      {
;;;186        /* Enable the selected DAC channel */
;;;187        DAC->CR |= (DAC_CR_EN1 << DAC_Channel);
000002  4a08              LDR      r2,|L1.36|
000004  6812              LDR      r2,[r2,#0]
000006  2301              MOVS     r3,#1
000008  4083              LSLS     r3,r3,r0
00000a  431a              ORRS     r2,r2,r3
00000c  4b05              LDR      r3,|L1.36|
00000e  601a              STR      r2,[r3,#0]
000010  e006              B        |L1.32|
                  |L1.18|
;;;188      }
;;;189      else
;;;190      {
;;;191        /* Disable the selected DAC channel */
;;;192        DAC->CR &= ~(DAC_CR_EN1 << DAC_Channel);
000012  4a04              LDR      r2,|L1.36|
000014  6812              LDR      r2,[r2,#0]
000016  2301              MOVS     r3,#1
000018  4083              LSLS     r3,r3,r0
00001a  439a              BICS     r2,r2,r3
00001c  4b01              LDR      r3,|L1.36|
00001e  601a              STR      r2,[r3,#0]
                  |L1.32|
;;;193      }
;;;194    }
000020  4770              BX       lr
;;;195    #if defined (STM32F10X_LD_VL) || defined (STM32F10X_MD_VL) || defined (STM32F10X_HD_VL)
                          ENDP

000022  0000              DCW      0x0000
                  |L1.36|
                          DCD      0x40007400

                          AREA ||i.DAC_DMACmd||, CODE, READONLY, ALIGN=2

                  DAC_DMACmd PROC
;;;238      */
;;;239    void DAC_DMACmd(uint32_t DAC_Channel, FunctionalState NewState)
000000  b141              CBZ      r1,|L2.20|
;;;240    {
;;;241      /* Check the parameters */
;;;242      assert_param(IS_DAC_CHANNEL(DAC_Channel));
;;;243      assert_param(IS_FUNCTIONAL_STATE(NewState));
;;;244      if (NewState != DISABLE)
;;;245      {
;;;246        /* Enable the selected DAC channel DMA request */
;;;247        DAC->CR |= (DAC_CR_DMAEN1 << DAC_Channel);
000002  4a09              LDR      r2,|L2.40|
000004  6812              LDR      r2,[r2,#0]
000006  f44f5380          MOV      r3,#0x1000
00000a  4083              LSLS     r3,r3,r0
00000c  431a              ORRS     r2,r2,r3
00000e  4b06              LDR      r3,|L2.40|
000010  601a              STR      r2,[r3,#0]
000012  e007              B        |L2.36|
                  |L2.20|
;;;248      }
;;;249      else
;;;250      {
;;;251        /* Disable the selected DAC channel DMA request */
;;;252        DAC->CR &= ~(DAC_CR_DMAEN1 << DAC_Channel);
000014  4a04              LDR      r2,|L2.40|
000016  6812              LDR      r2,[r2,#0]
000018  f44f5380          MOV      r3,#0x1000
00001c  4083              LSLS     r3,r3,r0
00001e  439a              BICS     r2,r2,r3
000020  4b01              LDR      r3,|L2.40|
000022  601a              STR      r2,[r3,#0]
                  |L2.36|
;;;253      }
;;;254    }
000024  4770              BX       lr
;;;255    
                          ENDP

000026  0000              DCW      0x0000
                  |L2.40|
                          DCD      0x40007400

                          AREA ||i.DAC_DeInit||, CODE, READONLY, ALIGN=1

                  DAC_DeInit PROC
;;;103      */
;;;104    void DAC_DeInit(void)
000000  b510              PUSH     {r4,lr}
;;;105    {
;;;106      /* Enable DAC reset state */
;;;107      RCC_APB1PeriphResetCmd(RCC_APB1Periph_DAC, ENABLE);
000002  2101              MOVS     r1,#1
000004  0748              LSLS     r0,r1,#29
000006  f7fffffe          BL       RCC_APB1PeriphResetCmd
;;;108      /* Release DAC from reset state */
;;;109      RCC_APB1PeriphResetCmd(RCC_APB1Periph_DAC, DISABLE);
00000a  2100              MOVS     r1,#0
00000c  f04f5000          MOV      r0,#0x20000000
000010  f7fffffe          BL       RCC_APB1PeriphResetCmd
;;;110    }
000014  bd10              POP      {r4,pc}
;;;111    
                          ENDP


                          AREA ||i.DAC_DualSoftwareTriggerCmd||, CODE, READONLY, ALIGN=2

                  DAC_DualSoftwareTriggerCmd PROC
;;;289      */
;;;290    void DAC_DualSoftwareTriggerCmd(FunctionalState NewState)
000000  b130              CBZ      r0,|L4.16|
;;;291    {
;;;292      /* Check the parameters */
;;;293      assert_param(IS_FUNCTIONAL_STATE(NewState));
;;;294      if (NewState != DISABLE)
;;;295      {
;;;296        /* Enable software trigger for both DAC channels */
;;;297        DAC->SWTRIGR |= DUAL_SWTRIG_SET ;
000002  4907              LDR      r1,|L4.32|
000004  6809              LDR      r1,[r1,#0]
000006  f0410103          ORR      r1,r1,#3
00000a  4a05              LDR      r2,|L4.32|
00000c  6011              STR      r1,[r2,#0]
00000e  e005              B        |L4.28|
                  |L4.16|
;;;298      }
;;;299      else
;;;300      {
;;;301        /* Disable software trigger for both DAC channels */
;;;302        DAC->SWTRIGR &= DUAL_SWTRIG_RESET;
000010  4903              LDR      r1,|L4.32|
000012  6809              LDR      r1,[r1,#0]
000014  f0210103          BIC      r1,r1,#3
000018  4a01              LDR      r2,|L4.32|
00001a  6011              STR      r1,[r2,#0]
                  |L4.28|
;;;303      }
;;;304    }
00001c  4770              BX       lr
;;;305    
                          ENDP

00001e  0000              DCW      0x0000
                  |L4.32|
                          DCD      0x40007404

                          AREA ||i.DAC_GetDataOutputValue||, CODE, READONLY, ALIGN=2

                  DAC_GetDataOutputValue PROC
;;;435      */
;;;436    uint16_t DAC_GetDataOutputValue(uint32_t DAC_Channel)
000000  b508              PUSH     {r3,lr}
;;;437    {
000002  4601              MOV      r1,r0
;;;438      __IO uint32_t tmp = 0;
000004  2000              MOVS     r0,#0
000006  9000              STR      r0,[sp,#0]
;;;439      
;;;440      /* Check the parameters */
;;;441      assert_param(IS_DAC_CHANNEL(DAC_Channel));
;;;442      
;;;443      tmp = (uint32_t) DAC_BASE ;
000008  4805              LDR      r0,|L5.32|
00000a  9000              STR      r0,[sp,#0]
;;;444      tmp += DOR_OFFSET + ((uint32_t)DAC_Channel >> 2);
00000c  202c              MOVS     r0,#0x2c
00000e  eb000091          ADD      r0,r0,r1,LSR #2
000012  9a00              LDR      r2,[sp,#0]
000014  4410              ADD      r0,r0,r2
000016  9000              STR      r0,[sp,#0]
;;;445      
;;;446      /* Returns the DAC channel data output register value */
;;;447      return (uint16_t) (*(__IO uint32_t*) tmp);
000018  9800              LDR      r0,[sp,#0]
00001a  6800              LDR      r0,[r0,#0]
00001c  b280              UXTH     r0,r0
;;;448    }
00001e  bd08              POP      {r3,pc}
;;;449    
                          ENDP

                  |L5.32|
                          DCD      0x40007400

                          AREA ||i.DAC_Init||, CODE, READONLY, ALIGN=2

                  DAC_Init PROC
;;;122      */
;;;123    void DAC_Init(uint32_t DAC_Channel, DAC_InitTypeDef* DAC_InitStruct)
000000  b530              PUSH     {r4,r5,lr}
;;;124    {
;;;125      uint32_t tmpreg1 = 0, tmpreg2 = 0;
000002  2200              MOVS     r2,#0
000004  2300              MOVS     r3,#0
;;;126      /* Check the DAC parameters */
;;;127      assert_param(IS_DAC_TRIGGER(DAC_InitStruct->DAC_Trigger));
;;;128      assert_param(IS_DAC_GENERATE_WAVE(DAC_InitStruct->DAC_WaveGeneration));
;;;129      assert_param(IS_DAC_LFSR_UNMASK_TRIANGLE_AMPLITUDE(DAC_InitStruct->DAC_LFSRUnmask_TriangleAmplitude));
;;;130      assert_param(IS_DAC_OUTPUT_BUFFER_STATE(DAC_InitStruct->DAC_OutputBuffer));
;;;131    /*---------------------------- DAC CR Configuration --------------------------*/
;;;132      /* Get the DAC CR value */
;;;133      tmpreg1 = DAC->CR;
000006  4c0a              LDR      r4,|L6.48|
000008  6822              LDR      r2,[r4,#0]
;;;134      /* Clear BOFFx, TENx, TSELx, WAVEx and MAMPx bits */
;;;135      tmpreg1 &= ~(CR_CLEAR_MASK << DAC_Channel);
00000a  f64074fe          MOV      r4,#0xffe
00000e  4084              LSLS     r4,r4,r0
000010  43a2              BICS     r2,r2,r4
;;;136      /* Configure for the selected DAC channel: buffer output, trigger, wave generation,
;;;137         mask/amplitude for wave generation */
;;;138      /* Set TSELx and TENx bits according to DAC_Trigger value */
;;;139      /* Set WAVEx bits according to DAC_WaveGeneration value */
;;;140      /* Set MAMPx bits according to DAC_LFSRUnmask_TriangleAmplitude value */ 
;;;141      /* Set BOFFx bit according to DAC_OutputBuffer value */   
;;;142      tmpreg2 = (DAC_InitStruct->DAC_Trigger | DAC_InitStruct->DAC_WaveGeneration |
000012  e9d14500          LDRD     r4,r5,[r1,#0]
000016  432c              ORRS     r4,r4,r5
000018  688d              LDR      r5,[r1,#8]
00001a  432c              ORRS     r4,r4,r5
00001c  68cd              LDR      r5,[r1,#0xc]
00001e  ea440305          ORR      r3,r4,r5
;;;143                 DAC_InitStruct->DAC_LFSRUnmask_TriangleAmplitude | DAC_InitStruct->DAC_OutputBuffer);
;;;144      /* Calculate CR register value depending on DAC_Channel */
;;;145      tmpreg1 |= tmpreg2 << DAC_Channel;
000022  fa03f400          LSL      r4,r3,r0
000026  4322              ORRS     r2,r2,r4
;;;146      /* Write to DAC CR */
;;;147      DAC->CR = tmpreg1;
000028  4c01              LDR      r4,|L6.48|
00002a  6022              STR      r2,[r4,#0]
;;;148    }
00002c  bd30              POP      {r4,r5,pc}
;;;149    
                          ENDP

00002e  0000              DCW      0x0000
                  |L6.48|
                          DCD      0x40007400

                          AREA ||i.DAC_SetChannel1Data||, CODE, READONLY, ALIGN=2

                  DAC_SetChannel1Data PROC
;;;347      */
;;;348    void DAC_SetChannel1Data(uint32_t DAC_Align, uint16_t Data)
000000  b508              PUSH     {r3,lr}
;;;349    {  
;;;350      __IO uint32_t tmp = 0;
000002  2200              MOVS     r2,#0
000004  9200              STR      r2,[sp,#0]
;;;351      
;;;352      /* Check the parameters */
;;;353      assert_param(IS_DAC_ALIGN(DAC_Align));
;;;354      assert_param(IS_DAC_DATA(Data));
;;;355      
;;;356      tmp = (uint32_t)DAC_BASE; 
000006  4a05              LDR      r2,|L7.28|
000008  9200              STR      r2,[sp,#0]
;;;357      tmp += DHR12R1_OFFSET + DAC_Align;
00000a  f1000208          ADD      r2,r0,#8
00000e  9b00              LDR      r3,[sp,#0]
000010  441a              ADD      r2,r2,r3
000012  9200              STR      r2,[sp,#0]
;;;358    
;;;359      /* Set the DAC channel1 selected data holding register */
;;;360      *(__IO uint32_t *) tmp = Data;
000014  9a00              LDR      r2,[sp,#0]
000016  6011              STR      r1,[r2,#0]
;;;361    }
000018  bd08              POP      {r3,pc}
;;;362    
                          ENDP

00001a  0000              DCW      0x0000
                  |L7.28|
                          DCD      0x40007400

                          AREA ||i.DAC_SetChannel2Data||, CODE, READONLY, ALIGN=2

                  DAC_SetChannel2Data PROC
;;;372      */
;;;373    void DAC_SetChannel2Data(uint32_t DAC_Align, uint16_t Data)
000000  b508              PUSH     {r3,lr}
;;;374    {
;;;375      __IO uint32_t tmp = 0;
000002  2200              MOVS     r2,#0
000004  9200              STR      r2,[sp,#0]
;;;376    
;;;377      /* Check the parameters */
;;;378      assert_param(IS_DAC_ALIGN(DAC_Align));
;;;379      assert_param(IS_DAC_DATA(Data));
;;;380      
;;;381      tmp = (uint32_t)DAC_BASE;
000006  4a05              LDR      r2,|L8.28|
000008  9200              STR      r2,[sp,#0]
;;;382      tmp += DHR12R2_OFFSET + DAC_Align;
00000a  f1000214          ADD      r2,r0,#0x14
00000e  9b00              LDR      r3,[sp,#0]
000010  441a              ADD      r2,r2,r3
000012  9200              STR      r2,[sp,#0]
;;;383    
;;;384      /* Set the DAC channel2 selected data holding register */
;;;385      *(__IO uint32_t *)tmp = Data;
000014  9a00              LDR      r2,[sp,#0]
000016  6011              STR      r1,[r2,#0]
;;;386    }
000018  bd08              POP      {r3,pc}
;;;387    
                          ENDP

00001a  0000              DCW      0x0000
                  |L8.28|
                          DCD      0x40007400

                          AREA ||i.DAC_SetDualChannelData||, CODE, READONLY, ALIGN=2

                  DAC_SetDualChannelData PROC
;;;401      */
;;;402    void DAC_SetDualChannelData(uint32_t DAC_Align, uint16_t Data2, uint16_t Data1)
000000  b530              PUSH     {r4,r5,lr}
;;;403    {
;;;404      uint32_t data = 0, tmp = 0;
000002  2400              MOVS     r4,#0
000004  2300              MOVS     r3,#0
;;;405      
;;;406      /* Check the parameters */
;;;407      assert_param(IS_DAC_ALIGN(DAC_Align));
;;;408      assert_param(IS_DAC_DATA(Data1));
;;;409      assert_param(IS_DAC_DATA(Data2));
;;;410      
;;;411      /* Calculate and set dual DAC data holding register value */
;;;412      if (DAC_Align == DAC_Align_8b_R)
000006  2808              CMP      r0,#8
000008  d102              BNE      |L9.16|
;;;413      {
;;;414        data = ((uint32_t)Data2 << 8) | Data1; 
00000a  ea422401          ORR      r4,r2,r1,LSL #8
00000e  e001              B        |L9.20|
                  |L9.16|
;;;415      }
;;;416      else
;;;417      {
;;;418        data = ((uint32_t)Data2 << 16) | Data1;
000010  ea424401          ORR      r4,r2,r1,LSL #16
                  |L9.20|
;;;419      }
;;;420      
;;;421      tmp = (uint32_t)DAC_BASE;
000014  4b02              LDR      r3,|L9.32|
;;;422      tmp += DHR12RD_OFFSET + DAC_Align;
000016  f1000520          ADD      r5,r0,#0x20
00001a  442b              ADD      r3,r3,r5
;;;423    
;;;424      /* Set the dual DAC selected data holding register */
;;;425      *(__IO uint32_t *)tmp = data;
00001c  601c              STR      r4,[r3,#0]
;;;426    }
00001e  bd30              POP      {r4,r5,pc}
;;;427    
                          ENDP

                  |L9.32|
                          DCD      0x40007400

                          AREA ||i.DAC_SoftwareTriggerCmd||, CODE, READONLY, ALIGN=2

                  DAC_SoftwareTriggerCmd PROC
;;;265      */
;;;266    void DAC_SoftwareTriggerCmd(uint32_t DAC_Channel, FunctionalState NewState)
000000  b510              PUSH     {r4,lr}
;;;267    {
;;;268      /* Check the parameters */
;;;269      assert_param(IS_DAC_CHANNEL(DAC_Channel));
;;;270      assert_param(IS_FUNCTIONAL_STATE(NewState));
;;;271      if (NewState != DISABLE)
000002  b141              CBZ      r1,|L10.22|
;;;272      {
;;;273        /* Enable software trigger for the selected DAC channel */
;;;274        DAC->SWTRIGR |= (uint32_t)DAC_SWTRIGR_SWTRIG1 << (DAC_Channel >> 4);
000004  4a08              LDR      r2,|L10.40|
000006  6812              LDR      r2,[r2,#0]
000008  0904              LSRS     r4,r0,#4
00000a  2301              MOVS     r3,#1
00000c  40a3              LSLS     r3,r3,r4
00000e  431a              ORRS     r2,r2,r3
000010  4b05              LDR      r3,|L10.40|
000012  601a              STR      r2,[r3,#0]
000014  e007              B        |L10.38|
                  |L10.22|
;;;275      }
;;;276      else
;;;277      {
;;;278        /* Disable software trigger for the selected DAC channel */
;;;279        DAC->SWTRIGR &= ~((uint32_t)DAC_SWTRIGR_SWTRIG1 << (DAC_Channel >> 4));
000016  4a04              LDR      r2,|L10.40|
000018  6812              LDR      r2,[r2,#0]
00001a  0904              LSRS     r4,r0,#4
00001c  2301              MOVS     r3,#1
00001e  40a3              LSLS     r3,r3,r4
000020  439a              BICS     r2,r2,r3
000022  4b01              LDR      r3,|L10.40|
000024  601a              STR      r2,[r3,#0]
                  |L10.38|
;;;280      }
;;;281    }
000026  bd10              POP      {r4,pc}
;;;282    
                          ENDP

                  |L10.40|
                          DCD      0x40007404

                          AREA ||i.DAC_StructInit||, CODE, READONLY, ALIGN=1

                  DAC_StructInit PROC
;;;155      */
;;;156    void DAC_StructInit(DAC_InitTypeDef* DAC_InitStruct)
000000  2100              MOVS     r1,#0
;;;157    {
;;;158    /*--------------- Reset DAC init structure parameters values -----------------*/
;;;159      /* Initialize the DAC_Trigger member */
;;;160      DAC_InitStruct->DAC_Trigger = DAC_Trigger_None;
000002  6001              STR      r1,[r0,#0]
;;;161      /* Initialize the DAC_WaveGeneration member */
;;;162      DAC_InitStruct->DAC_WaveGeneration = DAC_WaveGeneration_None;
000004  6041              STR      r1,[r0,#4]
;;;163      /* Initialize the DAC_LFSRUnmask_TriangleAmplitude member */
;;;164      DAC_InitStruct->DAC_LFSRUnmask_TriangleAmplitude = DAC_LFSRUnmask_Bit0;
000006  6081              STR      r1,[r0,#8]
;;;165      /* Initialize the DAC_OutputBuffer member */
;;;166      DAC_InitStruct->DAC_OutputBuffer = DAC_OutputBuffer_Enable;
000008  60c1              STR      r1,[r0,#0xc]
;;;167    }
00000a  4770              BX       lr
;;;168    
                          ENDP


                          AREA ||i.DAC_WaveGenerationCmd||, CODE, READONLY, ALIGN=2

                  DAC_WaveGenerationCmd PROC
;;;319      */
;;;320    void DAC_WaveGenerationCmd(uint32_t DAC_Channel, uint32_t DAC_Wave, FunctionalState NewState)
000000  b510              PUSH     {r4,lr}
;;;321    {
;;;322      /* Check the parameters */
;;;323      assert_param(IS_DAC_CHANNEL(DAC_Channel));
;;;324      assert_param(IS_DAC_WAVE(DAC_Wave)); 
;;;325      assert_param(IS_FUNCTIONAL_STATE(NewState));
;;;326      if (NewState != DISABLE)
000002  b13a              CBZ      r2,|L12.20|
;;;327      {
;;;328        /* Enable the selected wave generation for the selected DAC channel */
;;;329        DAC->CR |= DAC_Wave << DAC_Channel;
000004  4b07              LDR      r3,|L12.36|
000006  681b              LDR      r3,[r3,#0]
000008  fa01f400          LSL      r4,r1,r0
00000c  4323              ORRS     r3,r3,r4
00000e  4c05              LDR      r4,|L12.36|
000010  6023              STR      r3,[r4,#0]
000012  e006              B        |L12.34|
                  |L12.20|
;;;330      }
;;;331      else
;;;332      {
;;;333        /* Disable the selected wave generation for the selected DAC channel */
;;;334        DAC->CR &= ~(DAC_Wave << DAC_Channel);
000014  4b03              LDR      r3,|L12.36|
000016  681b              LDR      r3,[r3,#0]
000018  fa01f400          LSL      r4,r1,r0
00001c  43a3              BICS     r3,r3,r4
00001e  4c01              LDR      r4,|L12.36|
000020  6023              STR      r3,[r4,#0]
                  |L12.34|
;;;335      }
;;;336    }
000022  bd10              POP      {r4,pc}
;;;337    
                          ENDP

                  |L12.36|
                          DCD      0x40007400

;*** Start embedded assembler ***

#line 1 "..\\..\\Libraries\\STM32F10x_StdPeriph_Driver\\src\\stm32f10x_dac.c"
	AREA ||.rev16_text||, CODE
	THUMB
	EXPORT |__asm___15_stm32f10x_dac_c_4da4a0a9____REV16|
#line 114 "..\\..\\Libraries\\CMSIS\\Include\\core_cmInstr.h"
|__asm___15_stm32f10x_dac_c_4da4a0a9____REV16| PROC
#line 115

 rev16 r0, r0
 bx lr
	ENDP
	AREA ||.revsh_text||, CODE
	THUMB
	EXPORT |__asm___15_stm32f10x_dac_c_4da4a0a9____REVSH|
#line 128
|__asm___15_stm32f10x_dac_c_4da4a0a9____REVSH| PROC
#line 129

 revsh r0, r0
 bx lr
	ENDP

;*** End   embedded assembler ***
