© COPYRIGHT 2012 STMicroelectronics
+ *
+ * Licensed under MCD-ST Liberty SW License Agreement V2, (the "License");
+ * You may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at:
+ *
+ * http://www.st.com/software_license_agreement_liberty_v2
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ *
+ ******************************************************************************
+ */
+
+/** @addtogroup CMSIS
+ * @{
+ */
+
+/** @addtogroup stm32f10x_system
+ * @{
+ */
+
+/**
+ * @brief Define to prevent recursive inclusion
+ */
+#ifndef __SYSTEM_STM32F10X_H
+#define __SYSTEM_STM32F10X_H
+
+#ifdef __cplusplus
+ extern "C" {
+#endif
+
+/** @addtogroup STM32F10x_System_Includes
+ * @{
+ */
+
+/**
+ * @}
+ */
+
+
+/** @addtogroup STM32F10x_System_Exported_types
+ * @{
+ */
+
+extern uint32_t SystemCoreClock; /*!< System Clock Frequency (Core Clock) */
+
+/**
+ * @}
+ */
+
+/** @addtogroup STM32F10x_System_Exported_Constants
+ * @{
+ */
+
+/**
+ * @}
+ */
+
+/** @addtogroup STM32F10x_System_Exported_Macros
+ * @{
+ */
+
+/**
+ * @}
+ */
+
+/** @addtogroup STM32F10x_System_Exported_Functions
+ * @{
+ */
+
+extern void SystemInit(void);
+extern void SystemCoreClockUpdate(void);
+/**
+ * @}
+ */
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /*__SYSTEM_STM32F10X_H */
+
+/**
+ * @}
+ */
+
+/**
+ * @}
+ */
+/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
diff --git a/Libraries/CMSIS/Device/ST/STM32F10x/Release_Notes.html b/Libraries/CMSIS/Device/ST/STM32F10x/Release_Notes.html
new file mode 100644
index 0000000..47339ff
--- /dev/null
+++ b/Libraries/CMSIS/Device/ST/STM32F10x/Release_Notes.html
@@ -0,0 +1,289 @@
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
\ No newline at end of file
diff --git a/Libraries/CMSIS/Device/ST/STM32F10x/Source/Templates/TASKING/cstart_thumb2.asm b/Libraries/CMSIS/Device/ST/STM32F10x/Source/Templates/TASKING/cstart_thumb2.asm
new file mode 100644
index 0000000..f363bdd
--- /dev/null
+++ b/Libraries/CMSIS/Device/ST/STM32F10x/Source/Templates/TASKING/cstart_thumb2.asm
@@ -0,0 +1,140 @@
+
+
+;; NOTE: To allow the use of this file for both ARMv6M and ARMv7M,
+;; we will only use 16-bit Thumb intructions.
+
+ .extern _lc_ub_stack ; usr/sys mode stack pointer
+ .extern _lc_ue_stack ; symbol required by debugger
+ .extern _lc_ub_table ; ROM to RAM copy table
+ .extern main
+ .extern _Exit
+ .extern exit
+ .weak exit
+ .global __get_argcv
+ .weak __get_argcv
+ .extern __argcvbuf
+ .weak __argcvbuf
+ ;;.extern __init_hardware
+ .extern SystemInit
+
+ .if @defined('__PROF_ENABLE__')
+ .extern __prof_init
+ .endif
+ .if @defined('__POSIX__')
+ .extern posix_main
+ .extern _posix_boot_stack_top
+ .endif
+
+ .global _START
+
+ .section .text.cstart
+
+ .thumb
+_START:
+ ;; anticipate possible ROM/RAM remapping
+ ;; by loading the 'real' program address
+ ldr r1,=_Next
+ bx r1
+_Next:
+ ;; initialize the stack pointer
+ ldr r1,=_lc_ub_stack ; TODO: make this part of the vector table
+ mov sp,r1
+
+ ;; call a user function which initializes function.
+ bl SystemInit
+
+ ;; copy initialized sections from ROM to RAM
+ ;; and clear uninitialized data sections in RAM
+
+ ldr r3,=_lc_ub_table
+ movs r0,#0
+cploop:
+ ldr r4,[r3,#0] ; load type
+ ldr r5,[r3,#4] ; dst address
+ ldr r6,[r3,#8] ; src address
+ ldr r7,[r3,#12] ; size
+
+ cmp r4,#1
+ beq copy
+ cmp r4,#2
+ beq clear
+ b done
+
+copy:
+ subs r7,r7,#1
+ ldrb r1,[r6,r7]
+ strb r1,[r5,r7]
+ bne copy
+
+ adds r3,r3,#16
+ b cploop
+
+clear:
+ subs r7,r7,#1
+ strb r0,[r5,r7]
+ bne clear
+
+ adds r3,r3,#16
+ b cploop
+
+done:
+
+ .if @defined('__POSIX__')
+
+ ;; posix stack buffer for system upbringing
+ ldr r0,=_posix_boot_stack_top
+ ldr r0, [r0]
+ mov sp,r0
+
+ .else
+
+ ;; load r10 with end of USR/SYS stack, which is
+ ;; needed in case stack overflow checking is on
+ ;; NOTE: use 16-bit instructions only, for ARMv6M
+ ldr r0,=_lc_ue_stack
+ mov r10,r0
+
+ .endif
+
+ .if @defined('__PROF_ENABLE__')
+ bl __prof_init
+ .endif
+
+ .if @defined('__POSIX__')
+ ;; call posix_main with no arguments
+ bl posix_main
+ .else
+ ;; retrieve argc and argv (default argv[0]==NULL & argc==0)
+ bl __get_argcv
+ ldr r1,=__argcvbuf
+ ;; call main
+ bl main
+ .endif
+
+ ;; call exit using the return value from main()
+ ;; Note. Calling exit will also run all functions
+ ;; that were supplied through atexit().
+ bl exit
+
+__get_argcv: ; weak definition
+ movs r0,#0
+ bx lr
+
+ .ltorg
+ .endsec
+
+ .calls '_START', ' '
+ .calls '_START','__init_vector_table'
+ .if @defined('__PROF_ENABLE__')
+ .calls '_START','__prof_init'
+ .endif
+ .if @defined('__POSIX__')
+ .calls '_START','posix_main'
+ .else
+ .calls '_START','__get_argcv'
+ .calls '_START','main'
+ .endif
+ .calls '_START','exit'
+ .calls '_START','',0
+
+ .end
diff --git a/Libraries/CMSIS/Device/ST/STM32F10x/Source/Templates/TrueSTUDIO/startup_stm32f10x_cl.s b/Libraries/CMSIS/Device/ST/STM32F10x/Source/Templates/TrueSTUDIO/startup_stm32f10x_cl.s
new file mode 100644
index 0000000..fea24d8
--- /dev/null
+++ b/Libraries/CMSIS/Device/ST/STM32F10x/Source/Templates/TrueSTUDIO/startup_stm32f10x_cl.s
@@ -0,0 +1,479 @@
+/**
+ ******************************************************************************
+ * @file startup_stm32f10x_cl.s
+ * @author MCD Application Team
+ * @version V3.6.1
+ * @date 09-March-2012
+ * @brief STM32F10x Connectivity line Devices vector table for Atollic
+ * toolchain.
+ * This module performs:
+ * - Set the initial SP
+ * - Set the initial PC == Reset_Handler,
+ * - Set the vector table entries with the exceptions ISR
+ * address.
+ * - Configure the clock system
+ * - Branches to main in the C library (which eventually
+ * calls main()).
+ * After Reset the Cortex-M3 processor is in Thread mode,
+ * priority is Privileged, and the Stack is set to Main.
+ ******************************************************************************
+ * @attention
+ *
+ *
+
+
+
+
+
+
+
+
|
+
© COPYRIGHT 2012 STMicroelectronics
+ *
+ * Licensed under MCD-ST Liberty SW License Agreement V2, (the "License");
+ * You may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at:
+ *
+ * http://www.st.com/software_license_agreement_liberty_v2
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ *
+ ******************************************************************************
+ */
+
+ .syntax unified
+ .cpu cortex-m3
+ .fpu softvfp
+ .thumb
+
+.global g_pfnVectors
+.global Default_Handler
+
+/* start address for the initialization values of the .data section.
+defined in linker script */
+.word _sidata
+/* start address for the .data section. defined in linker script */
+.word _sdata
+/* end address for the .data section. defined in linker script */
+.word _edata
+/* start address for the .bss section. defined in linker script */
+.word _sbss
+/* end address for the .bss section. defined in linker script */
+.word _ebss
+
+.equ BootRAM, 0xF1E0F85F
+/**
+ * @brief This is the code that gets called when the processor first
+ * starts execution following a reset event. Only the absolutely
+ * necessary set is performed, after which the application
+ * supplied main() routine is called.
+ * @param None
+ * @retval : None
+*/
+
+ .section .text.Reset_Handler
+ .weak Reset_Handler
+ .type Reset_Handler, %function
+Reset_Handler:
+
+/* Copy the data segment initializers from flash to SRAM */
+ movs r1, #0
+ b LoopCopyDataInit
+
+CopyDataInit:
+ ldr r3, =_sidata
+ ldr r3, [r3, r1]
+ str r3, [r0, r1]
+ adds r1, r1, #4
+
+LoopCopyDataInit:
+ ldr r0, =_sdata
+ ldr r3, =_edata
+ adds r2, r0, r1
+ cmp r2, r3
+ bcc CopyDataInit
+ ldr r2, =_sbss
+ b LoopFillZerobss
+
+/* Zero fill the bss segment. */
+FillZerobss:
+ movs r3, #0
+ str r3, [r2], #4
+
+LoopFillZerobss:
+ ldr r3, = _ebss
+ cmp r2, r3
+ bcc FillZerobss
+
+/* Call the clock system intitialization function.*/
+ bl SystemInit
+/* Call static constructors */
+ bl __libc_init_array
+/* Call the application's entry point.*/
+ bl main
+ bx lr
+.size Reset_Handler, .-Reset_Handler
+
+/**
+ * @brief This is the code that gets called when the processor receives an
+ * unexpected interrupt. This simply enters an infinite loop, preserving
+ * the system state for examination by a debugger.
+ *
+ * @param None
+ * @retval : None
+*/
+ .section .text.Default_Handler,"ax",%progbits
+Default_Handler:
+Infinite_Loop:
+ b Infinite_Loop
+ .size Default_Handler, .-Default_Handler
+
+/******************************************************************************
+*
+* The minimal vector table for a Cortex M3. Note that the proper constructs
+* must be placed on this to ensure that it ends up at physical address
+* 0x0000.0000.
+*
+******************************************************************************/
+ .section .isr_vector,"a",%progbits
+ .type g_pfnVectors, %object
+ .size g_pfnVectors, .-g_pfnVectors
+
+
+g_pfnVectors:
+ .word _estack
+ .word Reset_Handler
+ .word NMI_Handler
+ .word HardFault_Handler
+ .word MemManage_Handler
+ .word BusFault_Handler
+ .word UsageFault_Handler
+ .word 0
+ .word 0
+ .word 0
+ .word 0
+ .word SVC_Handler
+ .word DebugMon_Handler
+ .word 0
+ .word PendSV_Handler
+ .word SysTick_Handler
+ .word WWDG_IRQHandler
+ .word PVD_IRQHandler
+ .word TAMPER_IRQHandler
+ .word RTC_IRQHandler
+ .word FLASH_IRQHandler
+ .word RCC_IRQHandler
+ .word EXTI0_IRQHandler
+ .word EXTI1_IRQHandler
+ .word EXTI2_IRQHandler
+ .word EXTI3_IRQHandler
+ .word EXTI4_IRQHandler
+ .word DMA1_Channel1_IRQHandler
+ .word DMA1_Channel2_IRQHandler
+ .word DMA1_Channel3_IRQHandler
+ .word DMA1_Channel4_IRQHandler
+ .word DMA1_Channel5_IRQHandler
+ .word DMA1_Channel6_IRQHandler
+ .word DMA1_Channel7_IRQHandler
+ .word ADC1_2_IRQHandler
+ .word CAN1_TX_IRQHandler
+ .word CAN1_RX0_IRQHandler
+ .word CAN1_RX1_IRQHandler
+ .word CAN1_SCE_IRQHandler
+ .word EXTI9_5_IRQHandler
+ .word TIM1_BRK_IRQHandler
+ .word TIM1_UP_IRQHandler
+ .word TIM1_TRG_COM_IRQHandler
+ .word TIM1_CC_IRQHandler
+ .word TIM2_IRQHandler
+ .word TIM3_IRQHandler
+ .word TIM4_IRQHandler
+ .word I2C1_EV_IRQHandler
+ .word I2C1_ER_IRQHandler
+ .word I2C2_EV_IRQHandler
+ .word I2C2_ER_IRQHandler
+ .word SPI1_IRQHandler
+ .word SPI2_IRQHandler
+ .word USART1_IRQHandler
+ .word USART2_IRQHandler
+ .word USART3_IRQHandler
+ .word EXTI15_10_IRQHandler
+ .word RTCAlarm_IRQHandler
+ .word OTG_FS_WKUP_IRQHandler
+ .word 0
+ .word 0
+ .word 0
+ .word 0
+ .word 0
+ .word 0
+ .word 0
+ .word TIM5_IRQHandler
+ .word SPI3_IRQHandler
+ .word UART4_IRQHandler
+ .word UART5_IRQHandler
+ .word TIM6_IRQHandler
+ .word TIM7_IRQHandler
+ .word DMA2_Channel1_IRQHandler
+ .word DMA2_Channel2_IRQHandler
+ .word DMA2_Channel3_IRQHandler
+ .word DMA2_Channel4_IRQHandler
+ .word DMA2_Channel5_IRQHandler
+ .word ETH_IRQHandler
+ .word ETH_WKUP_IRQHandler
+ .word CAN2_TX_IRQHandler
+ .word CAN2_RX0_IRQHandler
+ .word CAN2_RX1_IRQHandler
+ .word CAN2_SCE_IRQHandler
+ .word OTG_FS_IRQHandler
+ .word 0
+ .word 0
+ .word 0
+ .word 0
+ .word 0
+ .word 0
+ .word 0
+ .word 0
+ .word 0
+ .word 0
+ .word 0
+ .word 0
+ .word 0
+ .word 0
+ .word 0
+ .word 0
+ .word 0
+ .word 0
+ .word 0
+ .word 0
+ .word 0
+ .word 0
+ .word 0
+ .word 0
+ .word 0
+ .word 0
+ .word 0
+ .word 0
+ .word 0
+ .word 0
+ .word 0
+ .word 0
+ .word 0
+ .word 0
+ .word 0
+ .word 0
+ .word BootRAM /* @0x1E0. This is for boot in RAM mode for
+ STM32F10x Connectivity line Devices. */
+
+/*******************************************************************************
+*
+* Provide weak aliases for each Exception handler to the Default_Handler.
+* As they are weak aliases, any function with the same name will override
+* this definition.
+*
+*******************************************************************************/
+ .weak NMI_Handler
+ .thumb_set NMI_Handler,Default_Handler
+
+ .weak HardFault_Handler
+ .thumb_set HardFault_Handler,Default_Handler
+
+ .weak MemManage_Handler
+ .thumb_set MemManage_Handler,Default_Handler
+
+ .weak BusFault_Handler
+ .thumb_set BusFault_Handler,Default_Handler
+
+ .weak UsageFault_Handler
+ .thumb_set UsageFault_Handler,Default_Handler
+
+ .weak SVC_Handler
+ .thumb_set SVC_Handler,Default_Handler
+
+ .weak DebugMon_Handler
+ .thumb_set DebugMon_Handler,Default_Handler
+
+ .weak PendSV_Handler
+ .thumb_set PendSV_Handler,Default_Handler
+
+ .weak SysTick_Handler
+ .thumb_set SysTick_Handler,Default_Handler
+
+ .weak WWDG_IRQHandler
+ .thumb_set WWDG_IRQHandler,Default_Handler
+
+ .weak PVD_IRQHandler
+ .thumb_set PVD_IRQHandler,Default_Handler
+
+ .weak TAMPER_IRQHandler
+ .thumb_set TAMPER_IRQHandler,Default_Handler
+
+ .weak RTC_IRQHandler
+ .thumb_set RTC_IRQHandler,Default_Handler
+
+ .weak FLASH_IRQHandler
+ .thumb_set FLASH_IRQHandler,Default_Handler
+
+ .weak RCC_IRQHandler
+ .thumb_set RCC_IRQHandler,Default_Handler
+
+ .weak EXTI0_IRQHandler
+ .thumb_set EXTI0_IRQHandler,Default_Handler
+
+ .weak EXTI1_IRQHandler
+ .thumb_set EXTI1_IRQHandler,Default_Handler
+
+ .weak EXTI2_IRQHandler
+ .thumb_set EXTI2_IRQHandler,Default_Handler
+
+ .weak EXTI3_IRQHandler
+ .thumb_set EXTI3_IRQHandler,Default_Handler
+
+ .weak EXTI4_IRQHandler
+ .thumb_set EXTI4_IRQHandler,Default_Handler
+
+ .weak DMA1_Channel1_IRQHandler
+ .thumb_set DMA1_Channel1_IRQHandler,Default_Handler
+
+ .weak DMA1_Channel2_IRQHandler
+ .thumb_set DMA1_Channel2_IRQHandler,Default_Handler
+
+ .weak DMA1_Channel3_IRQHandler
+ .thumb_set DMA1_Channel3_IRQHandler,Default_Handler
+
+ .weak DMA1_Channel4_IRQHandler
+ .thumb_set DMA1_Channel4_IRQHandler,Default_Handler
+
+ .weak DMA1_Channel5_IRQHandler
+ .thumb_set DMA1_Channel5_IRQHandler,Default_Handler
+
+ .weak DMA1_Channel6_IRQHandler
+ .thumb_set DMA1_Channel6_IRQHandler,Default_Handler
+
+ .weak DMA1_Channel7_IRQHandler
+ .thumb_set DMA1_Channel7_IRQHandler,Default_Handler
+
+ .weak ADC1_2_IRQHandler
+ .thumb_set ADC1_2_IRQHandler,Default_Handler
+
+ .weak CAN1_TX_IRQHandler
+ .thumb_set CAN1_TX_IRQHandler,Default_Handler
+
+ .weak CAN1_RX0_IRQHandler
+ .thumb_set CAN1_RX0_IRQHandler,Default_Handler
+
+ .weak CAN1_RX1_IRQHandler
+ .thumb_set CAN1_RX1_IRQHandler,Default_Handler
+
+ .weak CAN1_SCE_IRQHandler
+ .thumb_set CAN1_SCE_IRQHandler,Default_Handler
+
+ .weak EXTI9_5_IRQHandler
+ .thumb_set EXTI9_5_IRQHandler,Default_Handler
+
+ .weak TIM1_BRK_IRQHandler
+ .thumb_set TIM1_BRK_IRQHandler,Default_Handler
+
+ .weak TIM1_UP_IRQHandler
+ .thumb_set TIM1_UP_IRQHandler,Default_Handler
+
+ .weak TIM1_TRG_COM_IRQHandler
+ .thumb_set TIM1_TRG_COM_IRQHandler,Default_Handler
+
+ .weak TIM1_CC_IRQHandler
+ .thumb_set TIM1_CC_IRQHandler,Default_Handler
+
+ .weak TIM2_IRQHandler
+ .thumb_set TIM2_IRQHandler,Default_Handler
+
+ .weak TIM3_IRQHandler
+ .thumb_set TIM3_IRQHandler,Default_Handler
+
+ .weak TIM4_IRQHandler
+ .thumb_set TIM4_IRQHandler,Default_Handler
+
+ .weak I2C1_EV_IRQHandler
+ .thumb_set I2C1_EV_IRQHandler,Default_Handler
+
+ .weak I2C1_ER_IRQHandler
+ .thumb_set I2C1_ER_IRQHandler,Default_Handler
+
+ .weak I2C2_EV_IRQHandler
+ .thumb_set I2C2_EV_IRQHandler,Default_Handler
+
+ .weak I2C2_ER_IRQHandler
+ .thumb_set I2C2_ER_IRQHandler,Default_Handler
+
+ .weak SPI1_IRQHandler
+ .thumb_set SPI1_IRQHandler,Default_Handler
+
+ .weak SPI2_IRQHandler
+ .thumb_set SPI2_IRQHandler,Default_Handler
+
+ .weak USART1_IRQHandler
+ .thumb_set USART1_IRQHandler,Default_Handler
+
+ .weak USART2_IRQHandler
+ .thumb_set USART2_IRQHandler,Default_Handler
+
+ .weak USART3_IRQHandler
+ .thumb_set USART3_IRQHandler,Default_Handler
+
+ .weak EXTI15_10_IRQHandler
+ .thumb_set EXTI15_10_IRQHandler,Default_Handler
+
+ .weak RTCAlarm_IRQHandler
+ .thumb_set RTCAlarm_IRQHandler,Default_Handler
+
+ .weak OTG_FS_WKUP_IRQHandler
+ .thumb_set OTG_FS_WKUP_IRQHandler,Default_Handler
+
+ .weak TIM5_IRQHandler
+ .thumb_set TIM5_IRQHandler,Default_Handler
+
+ .weak SPI3_IRQHandler
+ .thumb_set SPI3_IRQHandler,Default_Handler
+
+ .weak UART4_IRQHandler
+ .thumb_set UART4_IRQHandler,Default_Handler
+
+ .weak UART5_IRQHandler
+ .thumb_set UART5_IRQHandler,Default_Handler
+
+ .weak TIM6_IRQHandler
+ .thumb_set TIM6_IRQHandler,Default_Handler
+
+ .weak TIM7_IRQHandler
+ .thumb_set TIM7_IRQHandler,Default_Handler
+
+ .weak DMA2_Channel1_IRQHandler
+ .thumb_set DMA2_Channel1_IRQHandler,Default_Handler
+
+ .weak DMA2_Channel2_IRQHandler
+ .thumb_set DMA2_Channel2_IRQHandler,Default_Handler
+
+ .weak DMA2_Channel3_IRQHandler
+ .thumb_set DMA2_Channel3_IRQHandler,Default_Handler
+
+ .weak DMA2_Channel4_IRQHandler
+ .thumb_set DMA2_Channel4_IRQHandler,Default_Handler
+
+ .weak DMA2_Channel5_IRQHandler
+ .thumb_set DMA2_Channel5_IRQHandler,Default_Handler
+
+ .weak ETH_IRQHandler
+ .thumb_set ETH_IRQHandler,Default_Handler
+
+ .weak ETH_WKUP_IRQHandler
+ .thumb_set ETH_WKUP_IRQHandler,Default_Handler
+
+ .weak CAN2_TX_IRQHandler
+ .thumb_set CAN2_TX_IRQHandler,Default_Handler
+
+ .weak CAN2_RX0_IRQHandler
+ .thumb_set CAN2_RX0_IRQHandler,Default_Handler
+
+ .weak CAN2_RX1_IRQHandler
+ .thumb_set CAN2_RX1_IRQHandler,Default_Handler
+
+ .weak CAN2_SCE_IRQHandler
+ .thumb_set CAN2_SCE_IRQHandler,Default_Handler
+
+ .weak OTG_FS_IRQHandler
+ .thumb_set OTG_FS_IRQHandler ,Default_Handler
+
+/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
diff --git a/Libraries/CMSIS/Device/ST/STM32F10x/Source/Templates/TrueSTUDIO/startup_stm32f10x_hd.s b/Libraries/CMSIS/Device/ST/STM32F10x/Source/Templates/TrueSTUDIO/startup_stm32f10x_hd.s
new file mode 100644
index 0000000..7994bd6
--- /dev/null
+++ b/Libraries/CMSIS/Device/ST/STM32F10x/Source/Templates/TrueSTUDIO/startup_stm32f10x_hd.s
@@ -0,0 +1,475 @@
+/**
+ ******************************************************************************
+ * @file startup_stm32f10x_hd.s
+ * @author MCD Application Team
+ * @version V3.6.1
+ * @date 09-March-2012
+ * @brief STM32F10x High Density Devices vector table for Atollic toolchain.
+ * This module performs:
+ * - Set the initial SP
+ * - Set the initial PC == Reset_Handler,
+ * - Set the vector table entries with the exceptions ISR address,
+ * - Configure the clock system
+ * - Configure external SRAM mounted on STM3210E-EVAL board
+ * to be used as data memory (optional, to be enabled by user)
+ * - Branches to main in the C library (which eventually
+ * calls main()).
+ * After Reset the Cortex-M3 processor is in Thread mode,
+ * priority is Privileged, and the Stack is set to Main.
+ ******************************************************************************
+ * @attention
+ *
+ * © COPYRIGHT 2012 STMicroelectronics
+ *
+ * Licensed under MCD-ST Liberty SW License Agreement V2, (the "License");
+ * You may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at:
+ *
+ * http://www.st.com/software_license_agreement_liberty_v2
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ *
+ ******************************************************************************
+ */
+
+ .syntax unified
+ .cpu cortex-m3
+ .fpu softvfp
+ .thumb
+
+.global g_pfnVectors
+.global Default_Handler
+
+/* start address for the initialization values of the .data section.
+defined in linker script */
+.word _sidata
+/* start address for the .data section. defined in linker script */
+.word _sdata
+/* end address for the .data section. defined in linker script */
+.word _edata
+/* start address for the .bss section. defined in linker script */
+.word _sbss
+/* end address for the .bss section. defined in linker script */
+.word _ebss
+
+.equ BootRAM, 0xF1E0F85F
+/**
+ * @brief This is the code that gets called when the processor first
+ * starts execution following a reset event. Only the absolutely
+ * necessary set is performed, after which the application
+ * supplied main() routine is called.
+ * @param None
+ * @retval : None
+*/
+
+ .section .text.Reset_Handler
+ .weak Reset_Handler
+ .type Reset_Handler, %function
+Reset_Handler:
+
+/* Copy the data segment initializers from flash to SRAM */
+ movs r1, #0
+ b LoopCopyDataInit
+
+CopyDataInit:
+ ldr r3, =_sidata
+ ldr r3, [r3, r1]
+ str r3, [r0, r1]
+ adds r1, r1, #4
+
+LoopCopyDataInit:
+ ldr r0, =_sdata
+ ldr r3, =_edata
+ adds r2, r0, r1
+ cmp r2, r3
+ bcc CopyDataInit
+ ldr r2, =_sbss
+ b LoopFillZerobss
+/* Zero fill the bss segment. */
+FillZerobss:
+ movs r3, #0
+ str r3, [r2], #4
+
+LoopFillZerobss:
+ ldr r3, = _ebss
+ cmp r2, r3
+ bcc FillZerobss
+
+/* Call the clock system intitialization function.*/
+ bl SystemInit
+/* Call static constructors */
+ bl __libc_init_array
+/* Call the application's entry point.*/
+ bl main
+ bx lr
+.size Reset_Handler, .-Reset_Handler
+
+/**
+ * @brief This is the code that gets called when the processor receives an
+ * unexpected interrupt. This simply enters an infinite loop, preserving
+ * the system state for examination by a debugger.
+ *
+ * @param None
+ * @retval : None
+*/
+ .section .text.Default_Handler,"ax",%progbits
+Default_Handler:
+Infinite_Loop:
+ b Infinite_Loop
+ .size Default_Handler, .-Default_Handler
+/******************************************************************************
+*
+* The minimal vector table for a Cortex M3. Note that the proper constructs
+* must be placed on this to ensure that it ends up at physical address
+* 0x0000.0000.
+*
+******************************************************************************/
+ .section .isr_vector,"a",%progbits
+ .type g_pfnVectors, %object
+ .size g_pfnVectors, .-g_pfnVectors
+
+
+g_pfnVectors:
+ .word _estack
+ .word Reset_Handler
+ .word NMI_Handler
+ .word HardFault_Handler
+ .word MemManage_Handler
+ .word BusFault_Handler
+ .word UsageFault_Handler
+ .word 0
+ .word 0
+ .word 0
+ .word 0
+ .word SVC_Handler
+ .word DebugMon_Handler
+ .word 0
+ .word PendSV_Handler
+ .word SysTick_Handler
+ .word WWDG_IRQHandler
+ .word PVD_IRQHandler
+ .word TAMPER_IRQHandler
+ .word RTC_IRQHandler
+ .word FLASH_IRQHandler
+ .word RCC_IRQHandler
+ .word EXTI0_IRQHandler
+ .word EXTI1_IRQHandler
+ .word EXTI2_IRQHandler
+ .word EXTI3_IRQHandler
+ .word EXTI4_IRQHandler
+ .word DMA1_Channel1_IRQHandler
+ .word DMA1_Channel2_IRQHandler
+ .word DMA1_Channel3_IRQHandler
+ .word DMA1_Channel4_IRQHandler
+ .word DMA1_Channel5_IRQHandler
+ .word DMA1_Channel6_IRQHandler
+ .word DMA1_Channel7_IRQHandler
+ .word ADC1_2_IRQHandler
+ .word USB_HP_CAN1_TX_IRQHandler
+ .word USB_LP_CAN1_RX0_IRQHandler
+ .word CAN1_RX1_IRQHandler
+ .word CAN1_SCE_IRQHandler
+ .word EXTI9_5_IRQHandler
+ .word TIM1_BRK_IRQHandler
+ .word TIM1_UP_IRQHandler
+ .word TIM1_TRG_COM_IRQHandler
+ .word TIM1_CC_IRQHandler
+ .word TIM2_IRQHandler
+ .word TIM3_IRQHandler
+ .word TIM4_IRQHandler
+ .word I2C1_EV_IRQHandler
+ .word I2C1_ER_IRQHandler
+ .word I2C2_EV_IRQHandler
+ .word I2C2_ER_IRQHandler
+ .word SPI1_IRQHandler
+ .word SPI2_IRQHandler
+ .word USART1_IRQHandler
+ .word USART2_IRQHandler
+ .word USART3_IRQHandler
+ .word EXTI15_10_IRQHandler
+ .word RTCAlarm_IRQHandler
+ .word USBWakeUp_IRQHandler
+ .word TIM8_BRK_IRQHandler
+ .word TIM8_UP_IRQHandler
+ .word TIM8_TRG_COM_IRQHandler
+ .word TIM8_CC_IRQHandler
+ .word ADC3_IRQHandler
+ .word FSMC_IRQHandler
+ .word SDIO_IRQHandler
+ .word TIM5_IRQHandler
+ .word SPI3_IRQHandler
+ .word UART4_IRQHandler
+ .word UART5_IRQHandler
+ .word TIM6_IRQHandler
+ .word TIM7_IRQHandler
+ .word DMA2_Channel1_IRQHandler
+ .word DMA2_Channel2_IRQHandler
+ .word DMA2_Channel3_IRQHandler
+ .word DMA2_Channel4_5_IRQHandler
+ .word 0
+ .word 0
+ .word 0
+ .word 0
+ .word 0
+ .word 0
+ .word 0
+ .word 0
+ .word 0
+ .word 0
+ .word 0
+ .word 0
+ .word 0
+ .word 0
+ .word 0
+ .word 0
+ .word 0
+ .word 0
+ .word 0
+ .word 0
+ .word 0
+ .word 0
+ .word 0
+ .word 0
+ .word 0
+ .word 0
+ .word 0
+ .word 0
+ .word 0
+ .word 0
+ .word 0
+ .word 0
+ .word 0
+ .word 0
+ .word 0
+ .word 0
+ .word 0
+ .word 0
+ .word 0
+ .word 0
+ .word 0
+ .word 0
+ .word 0
+ .word 0
+ .word BootRAM /* @0x1E0. This is for boot in RAM mode for
+ STM32F10x High Density devices. */
+
+/*******************************************************************************
+*
+* Provide weak aliases for each Exception handler to the Default_Handler.
+* As they are weak aliases, any function with the same name will override
+* this definition.
+*
+*******************************************************************************/
+
+ .weak NMI_Handler
+ .thumb_set NMI_Handler,Default_Handler
+
+ .weak HardFault_Handler
+ .thumb_set HardFault_Handler,Default_Handler
+
+ .weak MemManage_Handler
+ .thumb_set MemManage_Handler,Default_Handler
+
+ .weak BusFault_Handler
+ .thumb_set BusFault_Handler,Default_Handler
+
+ .weak UsageFault_Handler
+ .thumb_set UsageFault_Handler,Default_Handler
+
+ .weak SVC_Handler
+ .thumb_set SVC_Handler,Default_Handler
+
+ .weak DebugMon_Handler
+ .thumb_set DebugMon_Handler,Default_Handler
+
+ .weak PendSV_Handler
+ .thumb_set PendSV_Handler,Default_Handler
+
+ .weak SysTick_Handler
+ .thumb_set SysTick_Handler,Default_Handler
+
+ .weak WWDG_IRQHandler
+ .thumb_set WWDG_IRQHandler,Default_Handler
+
+ .weak PVD_IRQHandler
+ .thumb_set PVD_IRQHandler,Default_Handler
+
+ .weak TAMPER_IRQHandler
+ .thumb_set TAMPER_IRQHandler,Default_Handler
+
+ .weak RTC_IRQHandler
+ .thumb_set RTC_IRQHandler,Default_Handler
+
+ .weak FLASH_IRQHandler
+ .thumb_set FLASH_IRQHandler,Default_Handler
+
+ .weak RCC_IRQHandler
+ .thumb_set RCC_IRQHandler,Default_Handler
+
+ .weak EXTI0_IRQHandler
+ .thumb_set EXTI0_IRQHandler,Default_Handler
+
+ .weak EXTI1_IRQHandler
+ .thumb_set EXTI1_IRQHandler,Default_Handler
+
+ .weak EXTI2_IRQHandler
+ .thumb_set EXTI2_IRQHandler,Default_Handler
+
+ .weak EXTI3_IRQHandler
+ .thumb_set EXTI3_IRQHandler,Default_Handler
+
+ .weak EXTI4_IRQHandler
+ .thumb_set EXTI4_IRQHandler,Default_Handler
+
+ .weak DMA1_Channel1_IRQHandler
+ .thumb_set DMA1_Channel1_IRQHandler,Default_Handler
+
+ .weak DMA1_Channel2_IRQHandler
+ .thumb_set DMA1_Channel2_IRQHandler,Default_Handler
+
+ .weak DMA1_Channel3_IRQHandler
+ .thumb_set DMA1_Channel3_IRQHandler,Default_Handler
+
+ .weak DMA1_Channel4_IRQHandler
+ .thumb_set DMA1_Channel4_IRQHandler,Default_Handler
+
+ .weak DMA1_Channel5_IRQHandler
+ .thumb_set DMA1_Channel5_IRQHandler,Default_Handler
+
+ .weak DMA1_Channel6_IRQHandler
+ .thumb_set DMA1_Channel6_IRQHandler,Default_Handler
+
+ .weak DMA1_Channel7_IRQHandler
+ .thumb_set DMA1_Channel7_IRQHandler,Default_Handler
+
+ .weak ADC1_2_IRQHandler
+ .thumb_set ADC1_2_IRQHandler,Default_Handler
+
+ .weak USB_HP_CAN1_TX_IRQHandler
+ .thumb_set USB_HP_CAN1_TX_IRQHandler,Default_Handler
+
+ .weak USB_LP_CAN1_RX0_IRQHandler
+ .thumb_set USB_LP_CAN1_RX0_IRQHandler,Default_Handler
+
+ .weak CAN1_RX1_IRQHandler
+ .thumb_set CAN1_RX1_IRQHandler,Default_Handler
+
+ .weak CAN1_SCE_IRQHandler
+ .thumb_set CAN1_SCE_IRQHandler,Default_Handler
+
+ .weak EXTI9_5_IRQHandler
+ .thumb_set EXTI9_5_IRQHandler,Default_Handler
+
+ .weak TIM1_BRK_IRQHandler
+ .thumb_set TIM1_BRK_IRQHandler,Default_Handler
+
+ .weak TIM1_UP_IRQHandler
+ .thumb_set TIM1_UP_IRQHandler,Default_Handler
+
+ .weak TIM1_TRG_COM_IRQHandler
+ .thumb_set TIM1_TRG_COM_IRQHandler,Default_Handler
+
+ .weak TIM1_CC_IRQHandler
+ .thumb_set TIM1_CC_IRQHandler,Default_Handler
+
+ .weak TIM2_IRQHandler
+ .thumb_set TIM2_IRQHandler,Default_Handler
+
+ .weak TIM3_IRQHandler
+ .thumb_set TIM3_IRQHandler,Default_Handler
+
+ .weak TIM4_IRQHandler
+ .thumb_set TIM4_IRQHandler,Default_Handler
+
+ .weak I2C1_EV_IRQHandler
+ .thumb_set I2C1_EV_IRQHandler,Default_Handler
+
+ .weak I2C1_ER_IRQHandler
+ .thumb_set I2C1_ER_IRQHandler,Default_Handler
+
+ .weak I2C2_EV_IRQHandler
+ .thumb_set I2C2_EV_IRQHandler,Default_Handler
+
+ .weak I2C2_ER_IRQHandler
+ .thumb_set I2C2_ER_IRQHandler,Default_Handler
+
+ .weak SPI1_IRQHandler
+ .thumb_set SPI1_IRQHandler,Default_Handler
+
+ .weak SPI2_IRQHandler
+ .thumb_set SPI2_IRQHandler,Default_Handler
+
+ .weak USART1_IRQHandler
+ .thumb_set USART1_IRQHandler,Default_Handler
+
+ .weak USART2_IRQHandler
+ .thumb_set USART2_IRQHandler,Default_Handler
+
+ .weak USART3_IRQHandler
+ .thumb_set USART3_IRQHandler,Default_Handler
+
+ .weak EXTI15_10_IRQHandler
+ .thumb_set EXTI15_10_IRQHandler,Default_Handler
+
+ .weak RTCAlarm_IRQHandler
+ .thumb_set RTCAlarm_IRQHandler,Default_Handler
+
+ .weak USBWakeUp_IRQHandler
+ .thumb_set USBWakeUp_IRQHandler,Default_Handler
+
+ .weak TIM8_BRK_IRQHandler
+ .thumb_set TIM8_BRK_IRQHandler,Default_Handler
+
+ .weak TIM8_UP_IRQHandler
+ .thumb_set TIM8_UP_IRQHandler,Default_Handler
+
+ .weak TIM8_TRG_COM_IRQHandler
+ .thumb_set TIM8_TRG_COM_IRQHandler,Default_Handler
+
+ .weak TIM8_CC_IRQHandler
+ .thumb_set TIM8_CC_IRQHandler,Default_Handler
+
+ .weak ADC3_IRQHandler
+ .thumb_set ADC3_IRQHandler,Default_Handler
+
+ .weak FSMC_IRQHandler
+ .thumb_set FSMC_IRQHandler,Default_Handler
+
+ .weak SDIO_IRQHandler
+ .thumb_set SDIO_IRQHandler,Default_Handler
+
+ .weak TIM5_IRQHandler
+ .thumb_set TIM5_IRQHandler,Default_Handler
+
+ .weak SPI3_IRQHandler
+ .thumb_set SPI3_IRQHandler,Default_Handler
+
+ .weak UART4_IRQHandler
+ .thumb_set UART4_IRQHandler,Default_Handler
+
+ .weak UART5_IRQHandler
+ .thumb_set UART5_IRQHandler,Default_Handler
+
+ .weak TIM6_IRQHandler
+ .thumb_set TIM6_IRQHandler,Default_Handler
+
+ .weak TIM7_IRQHandler
+ .thumb_set TIM7_IRQHandler,Default_Handler
+
+ .weak DMA2_Channel1_IRQHandler
+ .thumb_set DMA2_Channel1_IRQHandler,Default_Handler
+
+ .weak DMA2_Channel2_IRQHandler
+ .thumb_set DMA2_Channel2_IRQHandler,Default_Handler
+
+ .weak DMA2_Channel3_IRQHandler
+ .thumb_set DMA2_Channel3_IRQHandler,Default_Handler
+
+ .weak DMA2_Channel4_5_IRQHandler
+ .thumb_set DMA2_Channel4_5_IRQHandler,Default_Handler
+
+/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
diff --git a/Libraries/CMSIS/Device/ST/STM32F10x/Source/Templates/TrueSTUDIO/startup_stm32f10x_hd_vl.s b/Libraries/CMSIS/Device/ST/STM32F10x/Source/Templates/TrueSTUDIO/startup_stm32f10x_hd_vl.s
new file mode 100644
index 0000000..8deb6a2
--- /dev/null
+++ b/Libraries/CMSIS/Device/ST/STM32F10x/Source/Templates/TrueSTUDIO/startup_stm32f10x_hd_vl.s
@@ -0,0 +1,457 @@
+/**
+ ******************************************************************************
+ * @file startup_stm32f10x_hd_vl.s
+ * @author MCD Application Team
+ * @version V3.6.1
+ * @date 09-March-2012
+ * @brief STM32F10x High Density Value Line Devices vector table for Atollic
+ * toolchain.
+ * This module performs:
+ * - Set the initial SP
+ * - Set the initial PC == Reset_Handler,
+ * - Set the vector table entries with the exceptions ISR address
+ * - Configure the clock system
+ * - Configure external SRAM mounted on STM32100E-EVAL board
+ * to be used as data memory (optional, to be enabled by user)
+ * - Branches to main in the C library (which eventually
+ * calls main()).
+ * After Reset the Cortex-M3 processor is in Thread mode,
+ * priority is Privileged, and the Stack is set to Main.
+ ******************************************************************************
+ * @attention
+ *
+ * © COPYRIGHT 2012 STMicroelectronics
+ *
+ * Licensed under MCD-ST Liberty SW License Agreement V2, (the "License");
+ * You may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at:
+ *
+ * http://www.st.com/software_license_agreement_liberty_v2
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ *
+ ******************************************************************************
+ */
+
+ .syntax unified
+ .cpu cortex-m3
+ .fpu softvfp
+ .thumb
+
+.global g_pfnVectors
+.global Default_Handler
+
+/* start address for the initialization values of the .data section.
+defined in linker script */
+.word _sidata
+/* start address for the .data section. defined in linker script */
+.word _sdata
+/* end address for the .data section. defined in linker script */
+.word _edata
+/* start address for the .bss section. defined in linker script */
+.word _sbss
+/* end address for the .bss section. defined in linker script */
+.word _ebss
+
+.equ BootRAM, 0xF108F85F
+/**
+ * @brief This is the code that gets called when the processor first
+ * starts execution following a reset event. Only the absolutely
+ * necessary set is performed, after which the application
+ * supplied main() routine is called.
+ * @param None
+ * @retval : None
+*/
+
+ .section .text.Reset_Handler
+ .weak Reset_Handler
+ .type Reset_Handler, %function
+Reset_Handler:
+
+/* Copy the data segment initializers from flash to SRAM */
+ movs r1, #0
+ b LoopCopyDataInit
+
+CopyDataInit:
+ ldr r3, =_sidata
+ ldr r3, [r3, r1]
+ str r3, [r0, r1]
+ adds r1, r1, #4
+
+LoopCopyDataInit:
+ ldr r0, =_sdata
+ ldr r3, =_edata
+ adds r2, r0, r1
+ cmp r2, r3
+ bcc CopyDataInit
+ ldr r2, =_sbss
+ b LoopFillZerobss
+/* Zero fill the bss segment. */
+FillZerobss:
+ movs r3, #0
+ str r3, [r2], #4
+
+LoopFillZerobss:
+ ldr r3, = _ebss
+ cmp r2, r3
+ bcc FillZerobss
+
+/* Call the clock system intitialization function.*/
+ bl SystemInit
+/* Call static constructors */
+ bl __libc_init_array
+/* Call the application's entry point.*/
+ bl main
+ bx lr
+.size Reset_Handler, .-Reset_Handler
+
+/**
+ * @brief This is the code that gets called when the processor receives an
+ * unexpected interrupt. This simply enters an infinite loop, preserving
+ * the system state for examination by a debugger.
+ *
+ * @param None
+ * @retval : None
+*/
+ .section .text.Default_Handler,"ax",%progbits
+Default_Handler:
+Infinite_Loop:
+ b Infinite_Loop
+ .size Default_Handler, .-Default_Handler
+/******************************************************************************
+*
+* The minimal vector table for a Cortex M3. Note that the proper constructs
+* must be placed on this to ensure that it ends up at physical address
+* 0x0000.0000.
+*
+******************************************************************************/
+ .section .isr_vector,"a",%progbits
+ .type g_pfnVectors, %object
+ .size g_pfnVectors, .-g_pfnVectors
+
+
+g_pfnVectors:
+ .word _estack
+ .word Reset_Handler
+ .word NMI_Handler
+ .word HardFault_Handler
+ .word MemManage_Handler
+ .word BusFault_Handler
+ .word UsageFault_Handler
+ .word 0
+ .word 0
+ .word 0
+ .word 0
+ .word SVC_Handler
+ .word DebugMon_Handler
+ .word 0
+ .word PendSV_Handler
+ .word SysTick_Handler
+ .word WWDG_IRQHandler
+ .word PVD_IRQHandler
+ .word TAMPER_IRQHandler
+ .word RTC_IRQHandler
+ .word FLASH_IRQHandler
+ .word RCC_IRQHandler
+ .word EXTI0_IRQHandler
+ .word EXTI1_IRQHandler
+ .word EXTI2_IRQHandler
+ .word EXTI3_IRQHandler
+ .word EXTI4_IRQHandler
+ .word DMA1_Channel1_IRQHandler
+ .word DMA1_Channel2_IRQHandler
+ .word DMA1_Channel3_IRQHandler
+ .word DMA1_Channel4_IRQHandler
+ .word DMA1_Channel5_IRQHandler
+ .word DMA1_Channel6_IRQHandler
+ .word DMA1_Channel7_IRQHandler
+ .word ADC1_IRQHandler
+ .word 0
+ .word 0
+ .word 0
+ .word 0
+ .word EXTI9_5_IRQHandler
+ .word TIM1_BRK_TIM15_IRQHandler
+ .word TIM1_UP_TIM16_IRQHandler
+ .word TIM1_TRG_COM_TIM17_IRQHandler
+ .word TIM1_CC_IRQHandler
+ .word TIM2_IRQHandler
+ .word TIM3_IRQHandler
+ .word TIM4_IRQHandler
+ .word I2C1_EV_IRQHandler
+ .word I2C1_ER_IRQHandler
+ .word I2C2_EV_IRQHandler
+ .word I2C2_ER_IRQHandler
+ .word SPI1_IRQHandler
+ .word SPI2_IRQHandler
+ .word USART1_IRQHandler
+ .word USART2_IRQHandler
+ .word USART3_IRQHandler
+ .word EXTI15_10_IRQHandler
+ .word RTCAlarm_IRQHandler
+ .word CEC_IRQHandler
+ .word TIM12_IRQHandler
+ .word TIM13_IRQHandler
+ .word TIM14_IRQHandler
+ .word 0
+ .word 0
+ .word 0
+ .word 0
+ .word TIM5_IRQHandler
+ .word SPI3_IRQHandler
+ .word UART4_IRQHandler
+ .word UART5_IRQHandler
+ .word TIM6_DAC_IRQHandler
+ .word TIM7_IRQHandler
+ .word DMA2_Channel1_IRQHandler
+ .word DMA2_Channel2_IRQHandler
+ .word DMA2_Channel3_IRQHandler
+ .word DMA2_Channel4_5_IRQHandler
+ .word DMA2_Channel5_IRQHandler
+ .word 0
+ .word 0
+ .word 0
+ .word 0
+ .word 0
+ .word 0
+ .word 0
+ .word 0
+ .word 0
+ .word 0
+ .word 0
+ .word 0
+ .word 0
+ .word 0
+ .word 0
+ .word 0
+ .word 0
+ .word 0
+ .word 0
+ .word 0
+ .word 0
+ .word 0
+ .word 0
+ .word 0
+ .word 0
+ .word 0
+ .word 0
+ .word 0
+ .word 0
+ .word 0
+ .word 0
+ .word 0
+ .word 0
+ .word 0
+ .word 0
+ .word 0
+ .word 0
+ .word 0
+ .word 0
+ .word 0
+ .word 0
+ .word 0
+ .word 0
+ .word BootRAM /* @0x1E0. This is for boot in RAM mode for
+ STM32F10x High Density Value line devices. */
+
+/*******************************************************************************
+*
+* Provide weak aliases for each Exception handler to the Default_Handler.
+* As they are weak aliases, any function with the same name will override
+* this definition.
+*
+*******************************************************************************/
+
+
+ .weak NMI_Handler
+ .thumb_set NMI_Handler,Default_Handler
+
+ .weak HardFault_Handler
+ .thumb_set HardFault_Handler,Default_Handler
+
+ .weak MemManage_Handler
+ .thumb_set MemManage_Handler,Default_Handler
+
+ .weak BusFault_Handler
+ .thumb_set BusFault_Handler,Default_Handler
+
+ .weak UsageFault_Handler
+ .thumb_set UsageFault_Handler,Default_Handler
+
+ .weak SVC_Handler
+ .thumb_set SVC_Handler,Default_Handler
+
+ .weak DebugMon_Handler
+ .thumb_set DebugMon_Handler,Default_Handler
+
+ .weak PendSV_Handler
+ .thumb_set PendSV_Handler,Default_Handler
+
+ .weak SysTick_Handler
+ .thumb_set SysTick_Handler,Default_Handler
+
+ .weak WWDG_IRQHandler
+ .thumb_set WWDG_IRQHandler,Default_Handler
+
+ .weak PVD_IRQHandler
+ .thumb_set PVD_IRQHandler,Default_Handler
+
+ .weak TAMPER_IRQHandler
+ .thumb_set TAMPER_IRQHandler,Default_Handler
+
+ .weak RTC_IRQHandler
+ .thumb_set RTC_IRQHandler,Default_Handler
+
+ .weak FLASH_IRQHandler
+ .thumb_set FLASH_IRQHandler,Default_Handler
+
+ .weak RCC_IRQHandler
+ .thumb_set RCC_IRQHandler,Default_Handler
+
+ .weak EXTI0_IRQHandler
+ .thumb_set EXTI0_IRQHandler,Default_Handler
+
+ .weak EXTI1_IRQHandler
+ .thumb_set EXTI1_IRQHandler,Default_Handler
+
+ .weak EXTI2_IRQHandler
+ .thumb_set EXTI2_IRQHandler,Default_Handler
+
+ .weak EXTI3_IRQHandler
+ .thumb_set EXTI3_IRQHandler,Default_Handler
+
+ .weak EXTI4_IRQHandler
+ .thumb_set EXTI4_IRQHandler,Default_Handler
+
+ .weak DMA1_Channel1_IRQHandler
+ .thumb_set DMA1_Channel1_IRQHandler,Default_Handler
+
+ .weak DMA1_Channel2_IRQHandler
+ .thumb_set DMA1_Channel2_IRQHandler,Default_Handler
+
+ .weak DMA1_Channel3_IRQHandler
+ .thumb_set DMA1_Channel3_IRQHandler,Default_Handler
+
+ .weak DMA1_Channel4_IRQHandler
+ .thumb_set DMA1_Channel4_IRQHandler,Default_Handler
+
+ .weak DMA1_Channel5_IRQHandler
+ .thumb_set DMA1_Channel5_IRQHandler,Default_Handler
+
+ .weak DMA1_Channel6_IRQHandler
+ .thumb_set DMA1_Channel6_IRQHandler,Default_Handler
+
+ .weak DMA1_Channel7_IRQHandler
+ .thumb_set DMA1_Channel7_IRQHandler,Default_Handler
+
+ .weak ADC1_IRQHandler
+ .thumb_set ADC1_IRQHandler,Default_Handler
+
+ .weak EXTI9_5_IRQHandler
+ .thumb_set EXTI9_5_IRQHandler,Default_Handler
+
+ .weak TIM1_BRK_TIM15_IRQHandler
+ .thumb_set TIM1_BRK_TIM15_IRQHandler,Default_Handler
+
+ .weak TIM1_UP_TIM16_IRQHandler
+ .thumb_set TIM1_UP_TIM16_IRQHandler,Default_Handler
+
+ .weak TIM1_TRG_COM_TIM17_IRQHandler
+ .thumb_set TIM1_TRG_COM_TIM17_IRQHandler,Default_Handler
+
+ .weak TIM1_CC_IRQHandler
+ .thumb_set TIM1_CC_IRQHandler,Default_Handler
+
+ .weak TIM2_IRQHandler
+ .thumb_set TIM2_IRQHandler,Default_Handler
+
+ .weak TIM3_IRQHandler
+ .thumb_set TIM3_IRQHandler,Default_Handler
+
+ .weak TIM4_IRQHandler
+ .thumb_set TIM4_IRQHandler,Default_Handler
+
+ .weak I2C1_EV_IRQHandler
+ .thumb_set I2C1_EV_IRQHandler,Default_Handler
+
+ .weak I2C1_ER_IRQHandler
+ .thumb_set I2C1_ER_IRQHandler,Default_Handler
+
+ .weak I2C2_EV_IRQHandler
+ .thumb_set I2C2_EV_IRQHandler,Default_Handler
+
+ .weak I2C2_ER_IRQHandler
+ .thumb_set I2C2_ER_IRQHandler,Default_Handler
+
+ .weak SPI1_IRQHandler
+ .thumb_set SPI1_IRQHandler,Default_Handler
+
+ .weak SPI2_IRQHandler
+ .thumb_set SPI2_IRQHandler,Default_Handler
+
+ .weak USART1_IRQHandler
+ .thumb_set USART1_IRQHandler,Default_Handler
+
+ .weak USART2_IRQHandler
+ .thumb_set USART2_IRQHandler,Default_Handler
+
+ .weak USART3_IRQHandler
+ .thumb_set USART3_IRQHandler,Default_Handler
+
+ .weak EXTI15_10_IRQHandler
+ .thumb_set EXTI15_10_IRQHandler,Default_Handler
+
+ .weak RTCAlarm_IRQHandler
+ .thumb_set RTCAlarm_IRQHandler,Default_Handler
+
+ .weak CEC_IRQHandler
+ .thumb_set CEC_IRQHandler,Default_Handler
+
+ .weak TIM12_IRQHandler
+ .thumb_set TIM12_IRQHandler,Default_Handler
+
+ .weak TIM13_IRQHandler
+ .thumb_set TIM13_IRQHandler,Default_Handler
+
+ .weak TIM14_IRQHandler
+ .thumb_set TIM14_IRQHandler,Default_Handler
+
+ .weak TIM5_IRQHandler
+ .thumb_set TIM5_IRQHandler,Default_Handler
+
+ .weak SPI3_IRQHandler
+ .thumb_set SPI3_IRQHandler,Default_Handler
+
+ .weak UART4_IRQHandler
+ .thumb_set UART4_IRQHandler,Default_Handler
+
+ .weak UART5_IRQHandler
+ .thumb_set UART5_IRQHandler,Default_Handler
+
+ .weak TIM6_DAC_IRQHandler
+ .thumb_set TIM6_DAC_IRQHandler,Default_Handler
+
+ .weak TIM7_IRQHandler
+ .thumb_set TIM7_IRQHandler,Default_Handler
+
+ .weak DMA2_Channel1_IRQHandler
+ .thumb_set DMA2_Channel1_IRQHandler,Default_Handler
+
+ .weak DMA2_Channel2_IRQHandler
+ .thumb_set DMA2_Channel2_IRQHandler,Default_Handler
+
+ .weak DMA2_Channel3_IRQHandler
+ .thumb_set DMA2_Channel3_IRQHandler,Default_Handler
+
+ .weak DMA2_Channel4_5_IRQHandler
+ .thumb_set DMA2_Channel4_5_IRQHandler,Default_Handler
+
+ .weak DMA2_Channel5_IRQHandler
+ .thumb_set DMA2_Channel5_IRQHandler,Default_Handler
+
+/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
+
diff --git a/Libraries/CMSIS/Device/ST/STM32F10x/Source/Templates/TrueSTUDIO/startup_stm32f10x_ld.s b/Libraries/CMSIS/Device/ST/STM32F10x/Source/Templates/TrueSTUDIO/startup_stm32f10x_ld.s
new file mode 100644
index 0000000..19a6724
--- /dev/null
+++ b/Libraries/CMSIS/Device/ST/STM32F10x/Source/Templates/TrueSTUDIO/startup_stm32f10x_ld.s
@@ -0,0 +1,353 @@
+/**
+ ******************************************************************************
+ * @file startup_stm32f10x_ld.s
+ * @author MCD Application Team
+ * @version V3.6.1
+ * @date 09-March-2012
+ * @brief STM32F10x Low Density Devices vector table for Atollic toolchain.
+ * This module performs:
+ * - Set the initial SP
+ * - Set the initial PC == Reset_Handler,
+ * - Set the vector table entries with the exceptions ISR address.
+ * - Configure the clock system
+ * - Branches to main in the C library (which eventually
+ * calls main()).
+ * After Reset the Cortex-M3 processor is in Thread mode,
+ * priority is Privileged, and the Stack is set to Main.
+ ******************************************************************************
+ * @attention
+ *
+ * © COPYRIGHT 2012 STMicroelectronics
+ *
+ * Licensed under MCD-ST Liberty SW License Agreement V2, (the "License");
+ * You may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at:
+ *
+ * http://www.st.com/software_license_agreement_liberty_v2
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ *
+ ******************************************************************************
+ */
+
+ .syntax unified
+ .cpu cortex-m3
+ .fpu softvfp
+ .thumb
+
+.global g_pfnVectors
+.global Default_Handler
+
+/* start address for the initialization values of the .data section.
+defined in linker script */
+.word _sidata
+/* start address for the .data section. defined in linker script */
+.word _sdata
+/* end address for the .data section. defined in linker script */
+.word _edata
+/* start address for the .bss section. defined in linker script */
+.word _sbss
+/* end address for the .bss section. defined in linker script */
+.word _ebss
+
+.equ BootRAM, 0xF108F85F
+/**
+ * @brief This is the code that gets called when the processor first
+ * starts execution following a reset event. Only the absolutely
+ * necessary set is performed, after which the application
+ * supplied main() routine is called.
+ * @param None
+ * @retval : None
+*/
+
+ .section .text.Reset_Handler
+ .weak Reset_Handler
+ .type Reset_Handler, %function
+Reset_Handler:
+
+/* Copy the data segment initializers from flash to SRAM */
+ movs r1, #0
+ b LoopCopyDataInit
+
+CopyDataInit:
+ ldr r3, =_sidata
+ ldr r3, [r3, r1]
+ str r3, [r0, r1]
+ adds r1, r1, #4
+
+LoopCopyDataInit:
+ ldr r0, =_sdata
+ ldr r3, =_edata
+ adds r2, r0, r1
+ cmp r2, r3
+ bcc CopyDataInit
+ ldr r2, =_sbss
+ b LoopFillZerobss
+/* Zero fill the bss segment. */
+FillZerobss:
+ movs r3, #0
+ str r3, [r2], #4
+
+LoopFillZerobss:
+ ldr r3, = _ebss
+ cmp r2, r3
+ bcc FillZerobss
+
+/* Call the clock system intitialization function.*/
+ bl SystemInit
+/* Call static constructors */
+ bl __libc_init_array
+/* Call the application's entry point.*/
+ bl main
+ bx lr
+.size Reset_Handler, .-Reset_Handler
+
+/**
+ * @brief This is the code that gets called when the processor receives an
+ * unexpected interrupt. This simply enters an infinite loop, preserving
+ * the system state for examination by a debugger.
+ *
+ * @param None
+ * @retval : None
+*/
+ .section .text.Default_Handler,"ax",%progbits
+Default_Handler:
+Infinite_Loop:
+ b Infinite_Loop
+ .size Default_Handler, .-Default_Handler
+/******************************************************************************
+*
+* The minimal vector table for a Cortex M3. Note that the proper constructs
+* must be placed on this to ensure that it ends up at physical address
+* 0x0000.0000.
+*
+******************************************************************************/
+ .section .isr_vector,"a",%progbits
+ .type g_pfnVectors, %object
+ .size g_pfnVectors, .-g_pfnVectors
+
+
+g_pfnVectors:
+ .word _estack
+ .word Reset_Handler
+ .word NMI_Handler
+ .word HardFault_Handler
+ .word MemManage_Handler
+ .word BusFault_Handler
+ .word UsageFault_Handler
+ .word 0
+ .word 0
+ .word 0
+ .word 0
+ .word SVC_Handler
+ .word DebugMon_Handler
+ .word 0
+ .word PendSV_Handler
+ .word SysTick_Handler
+ .word WWDG_IRQHandler
+ .word PVD_IRQHandler
+ .word TAMPER_IRQHandler
+ .word RTC_IRQHandler
+ .word FLASH_IRQHandler
+ .word RCC_IRQHandler
+ .word EXTI0_IRQHandler
+ .word EXTI1_IRQHandler
+ .word EXTI2_IRQHandler
+ .word EXTI3_IRQHandler
+ .word EXTI4_IRQHandler
+ .word DMA1_Channel1_IRQHandler
+ .word DMA1_Channel2_IRQHandler
+ .word DMA1_Channel3_IRQHandler
+ .word DMA1_Channel4_IRQHandler
+ .word DMA1_Channel5_IRQHandler
+ .word DMA1_Channel6_IRQHandler
+ .word DMA1_Channel7_IRQHandler
+ .word ADC1_2_IRQHandler
+ .word USB_HP_CAN1_TX_IRQHandler
+ .word USB_LP_CAN1_RX0_IRQHandler
+ .word CAN1_RX1_IRQHandler
+ .word CAN1_SCE_IRQHandler
+ .word EXTI9_5_IRQHandler
+ .word TIM1_BRK_IRQHandler
+ .word TIM1_UP_IRQHandler
+ .word TIM1_TRG_COM_IRQHandler
+ .word TIM1_CC_IRQHandler
+ .word TIM2_IRQHandler
+ .word TIM3_IRQHandler
+ .word 0
+ .word I2C1_EV_IRQHandler
+ .word I2C1_ER_IRQHandler
+ .word 0
+ .word 0
+ .word SPI1_IRQHandler
+ .word 0
+ .word USART1_IRQHandler
+ .word USART2_IRQHandler
+ .word 0
+ .word EXTI15_10_IRQHandler
+ .word RTCAlarm_IRQHandler
+ .word USBWakeUp_IRQHandler
+ .word 0
+ .word 0
+ .word 0
+ .word 0
+ .word 0
+ .word 0
+ .word 0
+ .word BootRAM /* @0x108. This is for boot in RAM mode for
+ STM32F10x Low Density devices.*/
+
+/*******************************************************************************
+*
+* Provide weak aliases for each Exception handler to the Default_Handler.
+* As they are weak aliases, any function with the same name will override
+* this definition.
+*
+*******************************************************************************/
+
+ .weak NMI_Handler
+ .thumb_set NMI_Handler,Default_Handler
+
+ .weak HardFault_Handler
+ .thumb_set HardFault_Handler,Default_Handler
+
+ .weak MemManage_Handler
+ .thumb_set MemManage_Handler,Default_Handler
+
+ .weak BusFault_Handler
+ .thumb_set BusFault_Handler,Default_Handler
+
+ .weak UsageFault_Handler
+ .thumb_set UsageFault_Handler,Default_Handler
+
+ .weak SVC_Handler
+ .thumb_set SVC_Handler,Default_Handler
+
+ .weak DebugMon_Handler
+ .thumb_set DebugMon_Handler,Default_Handler
+
+ .weak PendSV_Handler
+ .thumb_set PendSV_Handler,Default_Handler
+
+ .weak SysTick_Handler
+ .thumb_set SysTick_Handler,Default_Handler
+
+ .weak WWDG_IRQHandler
+ .thumb_set WWDG_IRQHandler,Default_Handler
+
+ .weak PVD_IRQHandler
+ .thumb_set PVD_IRQHandler,Default_Handler
+
+ .weak TAMPER_IRQHandler
+ .thumb_set TAMPER_IRQHandler,Default_Handler
+
+ .weak RTC_IRQHandler
+ .thumb_set RTC_IRQHandler,Default_Handler
+
+ .weak FLASH_IRQHandler
+ .thumb_set FLASH_IRQHandler,Default_Handler
+
+ .weak RCC_IRQHandler
+ .thumb_set RCC_IRQHandler,Default_Handler
+
+ .weak EXTI0_IRQHandler
+ .thumb_set EXTI0_IRQHandler,Default_Handler
+
+ .weak EXTI1_IRQHandler
+ .thumb_set EXTI1_IRQHandler,Default_Handler
+
+ .weak EXTI2_IRQHandler
+ .thumb_set EXTI2_IRQHandler,Default_Handler
+
+ .weak EXTI3_IRQHandler
+ .thumb_set EXTI3_IRQHandler,Default_Handler
+
+ .weak EXTI4_IRQHandler
+ .thumb_set EXTI4_IRQHandler,Default_Handler
+
+ .weak DMA1_Channel1_IRQHandler
+ .thumb_set DMA1_Channel1_IRQHandler,Default_Handler
+
+ .weak DMA1_Channel2_IRQHandler
+ .thumb_set DMA1_Channel2_IRQHandler,Default_Handler
+
+ .weak DMA1_Channel3_IRQHandler
+ .thumb_set DMA1_Channel3_IRQHandler,Default_Handler
+
+ .weak DMA1_Channel4_IRQHandler
+ .thumb_set DMA1_Channel4_IRQHandler,Default_Handler
+
+ .weak DMA1_Channel5_IRQHandler
+ .thumb_set DMA1_Channel5_IRQHandler,Default_Handler
+
+ .weak DMA1_Channel6_IRQHandler
+ .thumb_set DMA1_Channel6_IRQHandler,Default_Handler
+
+ .weak DMA1_Channel7_IRQHandler
+ .thumb_set DMA1_Channel7_IRQHandler,Default_Handler
+
+ .weak ADC1_2_IRQHandler
+ .thumb_set ADC1_2_IRQHandler,Default_Handler
+
+ .weak USB_HP_CAN1_TX_IRQHandler
+ .thumb_set USB_HP_CAN1_TX_IRQHandler,Default_Handler
+
+ .weak USB_LP_CAN1_RX0_IRQHandler
+ .thumb_set USB_LP_CAN1_RX0_IRQHandler,Default_Handler
+
+ .weak CAN1_RX1_IRQHandler
+ .thumb_set CAN1_RX1_IRQHandler,Default_Handler
+
+ .weak CAN1_SCE_IRQHandler
+ .thumb_set CAN1_SCE_IRQHandler,Default_Handler
+
+ .weak EXTI9_5_IRQHandler
+ .thumb_set EXTI9_5_IRQHandler,Default_Handler
+
+ .weak TIM1_BRK_IRQHandler
+ .thumb_set TIM1_BRK_IRQHandler,Default_Handler
+
+ .weak TIM1_UP_IRQHandler
+ .thumb_set TIM1_UP_IRQHandler,Default_Handler
+
+ .weak TIM1_TRG_COM_IRQHandler
+ .thumb_set TIM1_TRG_COM_IRQHandler,Default_Handler
+
+ .weak TIM1_CC_IRQHandler
+ .thumb_set TIM1_CC_IRQHandler,Default_Handler
+
+ .weak TIM2_IRQHandler
+ .thumb_set TIM2_IRQHandler,Default_Handler
+
+ .weak TIM3_IRQHandler
+ .thumb_set TIM3_IRQHandler,Default_Handler
+
+ .weak I2C1_EV_IRQHandler
+ .thumb_set I2C1_EV_IRQHandler,Default_Handler
+
+ .weak I2C1_ER_IRQHandler
+ .thumb_set I2C1_ER_IRQHandler,Default_Handler
+
+ .weak SPI1_IRQHandler
+ .thumb_set SPI1_IRQHandler,Default_Handler
+
+ .weak USART1_IRQHandler
+ .thumb_set USART1_IRQHandler,Default_Handler
+
+ .weak USART2_IRQHandler
+ .thumb_set USART2_IRQHandler,Default_Handler
+
+ .weak EXTI15_10_IRQHandler
+ .thumb_set EXTI15_10_IRQHandler,Default_Handler
+
+ .weak RTCAlarm_IRQHandler
+ .thumb_set RTCAlarm_IRQHandler,Default_Handler
+
+ .weak USBWakeUp_IRQHandler
+ .thumb_set USBWakeUp_IRQHandler,Default_Handler
+
+/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
diff --git a/Libraries/CMSIS/Device/ST/STM32F10x/Source/Templates/TrueSTUDIO/startup_stm32f10x_ld_vl.s b/Libraries/CMSIS/Device/ST/STM32F10x/Source/Templates/TrueSTUDIO/startup_stm32f10x_ld_vl.s
new file mode 100644
index 0000000..a5f6850
--- /dev/null
+++ b/Libraries/CMSIS/Device/ST/STM32F10x/Source/Templates/TrueSTUDIO/startup_stm32f10x_ld_vl.s
@@ -0,0 +1,398 @@
+/**
+ ******************************************************************************
+ * @file startup_stm32f10x_ld_vl.s
+ * @author MCD Application Team
+ * @version V3.6.1
+ * @date 09-March-2012
+ * @brief STM32F10x Low Density Value Line Devices vector table for Atollic toolchain.
+ * This module performs:
+ * - Set the initial SP
+ * - Set the initial PC == Reset_Handler,
+ * - Set the vector table entries with the exceptions ISR address
+ * - Configure the clock system
+ * - Branches to main in the C library (which eventually
+ * calls main()).
+ * After Reset the Cortex-M3 processor is in Thread mode,
+ * priority is Privileged, and the Stack is set to Main.
+ ******************************************************************************
+ * @attention
+ *
+ * © COPYRIGHT 2012 STMicroelectronics
+ *
+ * Licensed under MCD-ST Liberty SW License Agreement V2, (the "License");
+ * You may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at:
+ *
+ * http://www.st.com/software_license_agreement_liberty_v2
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ *
+ ******************************************************************************
+ */
+
+ .syntax unified
+ .cpu cortex-m3
+ .fpu softvfp
+ .thumb
+
+.global g_pfnVectors
+.global Default_Handler
+
+/* start address for the initialization values of the .data section.
+defined in linker script */
+.word _sidata
+/* start address for the .data section. defined in linker script */
+.word _sdata
+/* end address for the .data section. defined in linker script */
+.word _edata
+/* start address for the .bss section. defined in linker script */
+.word _sbss
+/* end address for the .bss section. defined in linker script */
+.word _ebss
+
+.equ BootRAM, 0xF108F85F
+/**
+ * @brief This is the code that gets called when the processor first
+ * starts execution following a reset event. Only the absolutely
+ * necessary set is performed, after which the application
+ * supplied main() routine is called.
+ * @param None
+ * @retval : None
+*/
+
+ .section .text.Reset_Handler
+ .weak Reset_Handler
+ .type Reset_Handler, %function
+Reset_Handler:
+
+/* Copy the data segment initializers from flash to SRAM */
+ movs r1, #0
+ b LoopCopyDataInit
+
+CopyDataInit:
+ ldr r3, =_sidata
+ ldr r3, [r3, r1]
+ str r3, [r0, r1]
+ adds r1, r1, #4
+
+LoopCopyDataInit:
+ ldr r0, =_sdata
+ ldr r3, =_edata
+ adds r2, r0, r1
+ cmp r2, r3
+ bcc CopyDataInit
+ ldr r2, =_sbss
+ b LoopFillZerobss
+/* Zero fill the bss segment. */
+FillZerobss:
+ movs r3, #0
+ str r3, [r2], #4
+
+LoopFillZerobss:
+ ldr r3, = _ebss
+ cmp r2, r3
+ bcc FillZerobss
+
+/* Call the clock system intitialization function.*/
+ bl SystemInit
+/* Call static constructors */
+ bl __libc_init_array
+/* Call the application's entry point.*/
+ bl main
+ bx lr
+.size Reset_Handler, .-Reset_Handler
+
+/**
+ * @brief This is the code that gets called when the processor receives an
+ * unexpected interrupt. This simply enters an infinite loop, preserving
+ * the system state for examination by a debugger.
+ *
+ * @param None
+ * @retval : None
+*/
+ .section .text.Default_Handler,"ax",%progbits
+Default_Handler:
+Infinite_Loop:
+ b Infinite_Loop
+ .size Default_Handler, .-Default_Handler
+/******************************************************************************
+*
+* The minimal vector table for a Cortex M3. Note that the proper constructs
+* must be placed on this to ensure that it ends up at physical address
+* 0x0000.0000.
+*
+******************************************************************************/
+ .section .isr_vector,"a",%progbits
+ .type g_pfnVectors, %object
+ .size g_pfnVectors, .-g_pfnVectors
+
+
+g_pfnVectors:
+ .word _estack
+ .word Reset_Handler
+ .word NMI_Handler
+ .word HardFault_Handler
+ .word MemManage_Handler
+ .word BusFault_Handler
+ .word UsageFault_Handler
+ .word 0
+ .word 0
+ .word 0
+ .word 0
+ .word SVC_Handler
+ .word DebugMon_Handler
+ .word 0
+ .word PendSV_Handler
+ .word SysTick_Handler
+ .word WWDG_IRQHandler
+ .word PVD_IRQHandler
+ .word TAMPER_IRQHandler
+ .word RTC_IRQHandler
+ .word FLASH_IRQHandler
+ .word RCC_IRQHandler
+ .word EXTI0_IRQHandler
+ .word EXTI1_IRQHandler
+ .word EXTI2_IRQHandler
+ .word EXTI3_IRQHandler
+ .word EXTI4_IRQHandler
+ .word DMA1_Channel1_IRQHandler
+ .word DMA1_Channel2_IRQHandler
+ .word DMA1_Channel3_IRQHandler
+ .word DMA1_Channel4_IRQHandler
+ .word DMA1_Channel5_IRQHandler
+ .word DMA1_Channel6_IRQHandler
+ .word DMA1_Channel7_IRQHandler
+ .word ADC1_IRQHandler
+ .word 0
+ .word 0
+ .word 0
+ .word 0
+ .word EXTI9_5_IRQHandler
+ .word TIM1_BRK_TIM15_IRQHandler
+ .word TIM1_UP_TIM16_IRQHandler
+ .word TIM1_TRG_COM_TIM17_IRQHandler
+ .word TIM1_CC_IRQHandler
+ .word TIM2_IRQHandler
+ .word TIM3_IRQHandler
+ .word 0
+ .word I2C1_EV_IRQHandler
+ .word I2C1_ER_IRQHandler
+ .word 0
+ .word 0
+ .word SPI1_IRQHandler
+ .word 0
+ .word USART1_IRQHandler
+ .word USART2_IRQHandler
+ .word 0
+ .word EXTI15_10_IRQHandler
+ .word RTCAlarm_IRQHandler
+ .word CEC_IRQHandler
+ .word 0
+ .word 0
+ .word 0
+ .word 0
+ .word 0
+ .word 0
+ .word 0
+ .word 0
+ .word 0
+ .word 0
+ .word 0
+ .word TIM6_DAC_IRQHandler
+ .word TIM7_IRQHandler
+ .word 0
+ .word 0
+ .word 0
+ .word 0
+ .word 0
+ .word 0
+ .word 0
+ .word 0
+ .word 0
+ .word 0
+ .word 0
+ .word 0
+ .word 0
+ .word 0
+ .word 0
+ .word 0
+ .word 0
+ .word 0
+ .word 0
+ .word 0
+ .word 0
+ .word 0
+ .word 0
+ .word 0
+ .word 0
+ .word 0
+ .word 0
+ .word 0
+ .word 0
+ .word 0
+ .word 0
+ .word 0
+ .word 0
+ .word 0
+ .word 0
+ .word 0
+ .word 0
+ .word 0
+ .word 0
+ .word 0
+ .word 0
+ .word 0
+ .word 0
+ .word BootRAM /* @0x01CC. This is for boot in RAM mode for
+ STM32F10x Medium Value Line Density devices. */
+
+/*******************************************************************************
+*
+* Provide weak aliases for each Exception handler to the Default_Handler.
+* As they are weak aliases, any function with the same name will override
+* this definition.
+*
+*******************************************************************************/
+
+
+ .weak NMI_Handler
+ .thumb_set NMI_Handler,Default_Handler
+
+ .weak HardFault_Handler
+ .thumb_set HardFault_Handler,Default_Handler
+
+ .weak MemManage_Handler
+ .thumb_set MemManage_Handler,Default_Handler
+
+ .weak BusFault_Handler
+ .thumb_set BusFault_Handler,Default_Handler
+
+ .weak UsageFault_Handler
+ .thumb_set UsageFault_Handler,Default_Handler
+
+ .weak SVC_Handler
+ .thumb_set SVC_Handler,Default_Handler
+
+ .weak DebugMon_Handler
+ .thumb_set DebugMon_Handler,Default_Handler
+
+ .weak PendSV_Handler
+ .thumb_set PendSV_Handler,Default_Handler
+
+ .weak SysTick_Handler
+ .thumb_set SysTick_Handler,Default_Handler
+
+ .weak WWDG_IRQHandler
+ .thumb_set WWDG_IRQHandler,Default_Handler
+
+ .weak PVD_IRQHandler
+ .thumb_set PVD_IRQHandler,Default_Handler
+
+ .weak TAMPER_IRQHandler
+ .thumb_set TAMPER_IRQHandler,Default_Handler
+
+ .weak RTC_IRQHandler
+ .thumb_set RTC_IRQHandler,Default_Handler
+
+ .weak FLASH_IRQHandler
+ .thumb_set FLASH_IRQHandler,Default_Handler
+
+ .weak RCC_IRQHandler
+ .thumb_set RCC_IRQHandler,Default_Handler
+
+ .weak EXTI0_IRQHandler
+ .thumb_set EXTI0_IRQHandler,Default_Handler
+
+ .weak EXTI1_IRQHandler
+ .thumb_set EXTI1_IRQHandler,Default_Handler
+
+ .weak EXTI2_IRQHandler
+ .thumb_set EXTI2_IRQHandler,Default_Handler
+
+ .weak EXTI3_IRQHandler
+ .thumb_set EXTI3_IRQHandler,Default_Handler
+
+ .weak EXTI4_IRQHandler
+ .thumb_set EXTI4_IRQHandler,Default_Handler
+
+ .weak DMA1_Channel1_IRQHandler
+ .thumb_set DMA1_Channel1_IRQHandler,Default_Handler
+
+ .weak DMA1_Channel2_IRQHandler
+ .thumb_set DMA1_Channel2_IRQHandler,Default_Handler
+
+ .weak DMA1_Channel3_IRQHandler
+ .thumb_set DMA1_Channel3_IRQHandler,Default_Handler
+
+ .weak DMA1_Channel4_IRQHandler
+ .thumb_set DMA1_Channel4_IRQHandler,Default_Handler
+
+ .weak DMA1_Channel5_IRQHandler
+ .thumb_set DMA1_Channel5_IRQHandler,Default_Handler
+
+ .weak DMA1_Channel6_IRQHandler
+ .thumb_set DMA1_Channel6_IRQHandler,Default_Handler
+
+ .weak DMA1_Channel7_IRQHandler
+ .thumb_set DMA1_Channel7_IRQHandler,Default_Handler
+
+ .weak ADC1_IRQHandler
+ .thumb_set ADC1_IRQHandler,Default_Handler
+
+ .weak EXTI9_5_IRQHandler
+ .thumb_set EXTI9_5_IRQHandler,Default_Handler
+
+ .weak TIM1_BRK_TIM15_IRQHandler
+ .thumb_set TIM1_BRK_TIM15_IRQHandler,Default_Handler
+
+ .weak TIM1_UP_TIM16_IRQHandler
+ .thumb_set TIM1_UP_TIM16_IRQHandler,Default_Handler
+
+ .weak TIM1_TRG_COM_TIM17_IRQHandler
+ .thumb_set TIM1_TRG_COM_TIM17_IRQHandler,Default_Handler
+
+ .weak TIM1_CC_IRQHandler
+ .thumb_set TIM1_CC_IRQHandler,Default_Handler
+
+ .weak TIM2_IRQHandler
+ .thumb_set TIM2_IRQHandler,Default_Handler
+
+ .weak TIM3_IRQHandler
+ .thumb_set TIM3_IRQHandler,Default_Handler
+
+ .weak I2C1_EV_IRQHandler
+ .thumb_set I2C1_EV_IRQHandler,Default_Handler
+
+ .weak I2C1_ER_IRQHandler
+ .thumb_set I2C1_ER_IRQHandler,Default_Handler
+
+ .weak SPI1_IRQHandler
+ .thumb_set SPI1_IRQHandler,Default_Handler
+
+ .weak USART1_IRQHandler
+ .thumb_set USART1_IRQHandler,Default_Handler
+
+ .weak USART2_IRQHandler
+ .thumb_set USART2_IRQHandler,Default_Handler
+
+ .weak EXTI15_10_IRQHandler
+ .thumb_set EXTI15_10_IRQHandler,Default_Handler
+
+ .weak RTCAlarm_IRQHandler
+ .thumb_set RTCAlarm_IRQHandler,Default_Handler
+
+ .weak CEC_IRQHandler
+ .thumb_set CEC_IRQHandler,Default_Handler
+
+ .weak TIM6_DAC_IRQHandler
+ .thumb_set TIM6_DAC_IRQHandler,Default_Handler
+
+ .weak TIM7_IRQHandler
+ .thumb_set TIM7_IRQHandler,Default_Handler
+
+/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
+
diff --git a/Libraries/CMSIS/Device/ST/STM32F10x/Source/Templates/TrueSTUDIO/startup_stm32f10x_md.s b/Libraries/CMSIS/Device/ST/STM32F10x/Source/Templates/TrueSTUDIO/startup_stm32f10x_md.s
new file mode 100644
index 0000000..7e2f3f6
--- /dev/null
+++ b/Libraries/CMSIS/Device/ST/STM32F10x/Source/Templates/TrueSTUDIO/startup_stm32f10x_md.s
@@ -0,0 +1,369 @@
+/**
+ ******************************************************************************
+ * @file startup_stm32f10x_md.s
+ * @author MCD Application Team
+ * @version V3.6.1
+ * @date 09-March-2012
+ * @brief STM32F10x Medium Density Devices vector table for Atollic toolchain.
+ * This module performs:
+ * - Set the initial SP
+ * - Set the initial PC == Reset_Handler,
+ * - Set the vector table entries with the exceptions ISR address
+ * - Configure the clock system
+ * - Branches to main in the C library (which eventually
+ * calls main()).
+ * After Reset the Cortex-M3 processor is in Thread mode,
+ * priority is Privileged, and the Stack is set to Main.
+ ******************************************************************************
+ * @attention
+ *
+ * © COPYRIGHT 2012 STMicroelectronics
+ *
+ * Licensed under MCD-ST Liberty SW License Agreement V2, (the "License");
+ * You may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at:
+ *
+ * http://www.st.com/software_license_agreement_liberty_v2
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ *
+ ******************************************************************************
+ */
+
+ .syntax unified
+ .cpu cortex-m3
+ .fpu softvfp
+ .thumb
+
+.global g_pfnVectors
+.global Default_Handler
+
+/* start address for the initialization values of the .data section.
+defined in linker script */
+.word _sidata
+/* start address for the .data section. defined in linker script */
+.word _sdata
+/* end address for the .data section. defined in linker script */
+.word _edata
+/* start address for the .bss section. defined in linker script */
+.word _sbss
+/* end address for the .bss section. defined in linker script */
+.word _ebss
+
+.equ BootRAM, 0xF108F85F
+/**
+ * @brief This is the code that gets called when the processor first
+ * starts execution following a reset event. Only the absolutely
+ * necessary set is performed, after which the application
+ * supplied main() routine is called.
+ * @param None
+ * @retval : None
+*/
+
+ .section .text.Reset_Handler
+ .weak Reset_Handler
+ .type Reset_Handler, %function
+Reset_Handler:
+
+/* Copy the data segment initializers from flash to SRAM */
+ movs r1, #0
+ b LoopCopyDataInit
+
+CopyDataInit:
+ ldr r3, =_sidata
+ ldr r3, [r3, r1]
+ str r3, [r0, r1]
+ adds r1, r1, #4
+
+LoopCopyDataInit:
+ ldr r0, =_sdata
+ ldr r3, =_edata
+ adds r2, r0, r1
+ cmp r2, r3
+ bcc CopyDataInit
+ ldr r2, =_sbss
+ b LoopFillZerobss
+/* Zero fill the bss segment. */
+FillZerobss:
+ movs r3, #0
+ str r3, [r2], #4
+
+LoopFillZerobss:
+ ldr r3, = _ebss
+ cmp r2, r3
+ bcc FillZerobss
+
+/* Call the clock system intitialization function.*/
+ bl SystemInit
+/* Call static constructors */
+ bl __libc_init_array
+/* Call the application's entry point.*/
+ bl main
+ bx lr
+.size Reset_Handler, .-Reset_Handler
+
+/**
+ * @brief This is the code that gets called when the processor receives an
+ * unexpected interrupt. This simply enters an infinite loop, preserving
+ * the system state for examination by a debugger.
+ *
+ * @param None
+ * @retval : None
+*/
+ .section .text.Default_Handler,"ax",%progbits
+Default_Handler:
+Infinite_Loop:
+ b Infinite_Loop
+ .size Default_Handler, .-Default_Handler
+/******************************************************************************
+*
+* The minimal vector table for a Cortex M3. Note that the proper constructs
+* must be placed on this to ensure that it ends up at physical address
+* 0x0000.0000.
+*
+******************************************************************************/
+ .section .isr_vector,"a",%progbits
+ .type g_pfnVectors, %object
+ .size g_pfnVectors, .-g_pfnVectors
+
+
+g_pfnVectors:
+ .word _estack
+ .word Reset_Handler
+ .word NMI_Handler
+ .word HardFault_Handler
+ .word MemManage_Handler
+ .word BusFault_Handler
+ .word UsageFault_Handler
+ .word 0
+ .word 0
+ .word 0
+ .word 0
+ .word SVC_Handler
+ .word DebugMon_Handler
+ .word 0
+ .word PendSV_Handler
+ .word SysTick_Handler
+ .word WWDG_IRQHandler
+ .word PVD_IRQHandler
+ .word TAMPER_IRQHandler
+ .word RTC_IRQHandler
+ .word FLASH_IRQHandler
+ .word RCC_IRQHandler
+ .word EXTI0_IRQHandler
+ .word EXTI1_IRQHandler
+ .word EXTI2_IRQHandler
+ .word EXTI3_IRQHandler
+ .word EXTI4_IRQHandler
+ .word DMA1_Channel1_IRQHandler
+ .word DMA1_Channel2_IRQHandler
+ .word DMA1_Channel3_IRQHandler
+ .word DMA1_Channel4_IRQHandler
+ .word DMA1_Channel5_IRQHandler
+ .word DMA1_Channel6_IRQHandler
+ .word DMA1_Channel7_IRQHandler
+ .word ADC1_2_IRQHandler
+ .word USB_HP_CAN1_TX_IRQHandler
+ .word USB_LP_CAN1_RX0_IRQHandler
+ .word CAN1_RX1_IRQHandler
+ .word CAN1_SCE_IRQHandler
+ .word EXTI9_5_IRQHandler
+ .word TIM1_BRK_IRQHandler
+ .word TIM1_UP_IRQHandler
+ .word TIM1_TRG_COM_IRQHandler
+ .word TIM1_CC_IRQHandler
+ .word TIM2_IRQHandler
+ .word TIM3_IRQHandler
+ .word TIM4_IRQHandler
+ .word I2C1_EV_IRQHandler
+ .word I2C1_ER_IRQHandler
+ .word I2C2_EV_IRQHandler
+ .word I2C2_ER_IRQHandler
+ .word SPI1_IRQHandler
+ .word SPI2_IRQHandler
+ .word USART1_IRQHandler
+ .word USART2_IRQHandler
+ .word USART3_IRQHandler
+ .word EXTI15_10_IRQHandler
+ .word RTCAlarm_IRQHandler
+ .word USBWakeUp_IRQHandler
+ .word 0
+ .word 0
+ .word 0
+ .word 0
+ .word 0
+ .word 0
+ .word 0
+ .word BootRAM /* @0x108. This is for boot in RAM mode for
+ STM32F10x Medium Density devices. */
+
+/*******************************************************************************
+*
+* Provide weak aliases for each Exception handler to the Default_Handler.
+* As they are weak aliases, any function with the same name will override
+* this definition.
+*
+*******************************************************************************/
+
+ .weak NMI_Handler
+ .thumb_set NMI_Handler,Default_Handler
+
+ .weak HardFault_Handler
+ .thumb_set HardFault_Handler,Default_Handler
+
+ .weak MemManage_Handler
+ .thumb_set MemManage_Handler,Default_Handler
+
+ .weak BusFault_Handler
+ .thumb_set BusFault_Handler,Default_Handler
+
+ .weak UsageFault_Handler
+ .thumb_set UsageFault_Handler,Default_Handler
+
+ .weak SVC_Handler
+ .thumb_set SVC_Handler,Default_Handler
+
+ .weak DebugMon_Handler
+ .thumb_set DebugMon_Handler,Default_Handler
+
+ .weak PendSV_Handler
+ .thumb_set PendSV_Handler,Default_Handler
+
+ .weak SysTick_Handler
+ .thumb_set SysTick_Handler,Default_Handler
+
+ .weak WWDG_IRQHandler
+ .thumb_set WWDG_IRQHandler,Default_Handler
+
+ .weak PVD_IRQHandler
+ .thumb_set PVD_IRQHandler,Default_Handler
+
+ .weak TAMPER_IRQHandler
+ .thumb_set TAMPER_IRQHandler,Default_Handler
+
+ .weak RTC_IRQHandler
+ .thumb_set RTC_IRQHandler,Default_Handler
+
+ .weak FLASH_IRQHandler
+ .thumb_set FLASH_IRQHandler,Default_Handler
+
+ .weak RCC_IRQHandler
+ .thumb_set RCC_IRQHandler,Default_Handler
+
+ .weak EXTI0_IRQHandler
+ .thumb_set EXTI0_IRQHandler,Default_Handler
+
+ .weak EXTI1_IRQHandler
+ .thumb_set EXTI1_IRQHandler,Default_Handler
+
+ .weak EXTI2_IRQHandler
+ .thumb_set EXTI2_IRQHandler,Default_Handler
+
+ .weak EXTI3_IRQHandler
+ .thumb_set EXTI3_IRQHandler,Default_Handler
+
+ .weak EXTI4_IRQHandler
+ .thumb_set EXTI4_IRQHandler,Default_Handler
+
+ .weak DMA1_Channel1_IRQHandler
+ .thumb_set DMA1_Channel1_IRQHandler,Default_Handler
+
+ .weak DMA1_Channel2_IRQHandler
+ .thumb_set DMA1_Channel2_IRQHandler,Default_Handler
+
+ .weak DMA1_Channel3_IRQHandler
+ .thumb_set DMA1_Channel3_IRQHandler,Default_Handler
+
+ .weak DMA1_Channel4_IRQHandler
+ .thumb_set DMA1_Channel4_IRQHandler,Default_Handler
+
+ .weak DMA1_Channel5_IRQHandler
+ .thumb_set DMA1_Channel5_IRQHandler,Default_Handler
+
+ .weak DMA1_Channel6_IRQHandler
+ .thumb_set DMA1_Channel6_IRQHandler,Default_Handler
+
+ .weak DMA1_Channel7_IRQHandler
+ .thumb_set DMA1_Channel7_IRQHandler,Default_Handler
+
+ .weak ADC1_2_IRQHandler
+ .thumb_set ADC1_2_IRQHandler,Default_Handler
+
+ .weak USB_HP_CAN1_TX_IRQHandler
+ .thumb_set USB_HP_CAN1_TX_IRQHandler,Default_Handler
+
+ .weak USB_LP_CAN1_RX0_IRQHandler
+ .thumb_set USB_LP_CAN1_RX0_IRQHandler,Default_Handler
+
+ .weak CAN1_RX1_IRQHandler
+ .thumb_set CAN1_RX1_IRQHandler,Default_Handler
+
+ .weak CAN1_SCE_IRQHandler
+ .thumb_set CAN1_SCE_IRQHandler,Default_Handler
+
+ .weak EXTI9_5_IRQHandler
+ .thumb_set EXTI9_5_IRQHandler,Default_Handler
+
+ .weak TIM1_BRK_IRQHandler
+ .thumb_set TIM1_BRK_IRQHandler,Default_Handler
+
+ .weak TIM1_UP_IRQHandler
+ .thumb_set TIM1_UP_IRQHandler,Default_Handler
+
+ .weak TIM1_TRG_COM_IRQHandler
+ .thumb_set TIM1_TRG_COM_IRQHandler,Default_Handler
+
+ .weak TIM1_CC_IRQHandler
+ .thumb_set TIM1_CC_IRQHandler,Default_Handler
+
+ .weak TIM2_IRQHandler
+ .thumb_set TIM2_IRQHandler,Default_Handler
+
+ .weak TIM3_IRQHandler
+ .thumb_set TIM3_IRQHandler,Default_Handler
+
+ .weak TIM4_IRQHandler
+ .thumb_set TIM4_IRQHandler,Default_Handler
+
+ .weak I2C1_EV_IRQHandler
+ .thumb_set I2C1_EV_IRQHandler,Default_Handler
+
+ .weak I2C1_ER_IRQHandler
+ .thumb_set I2C1_ER_IRQHandler,Default_Handler
+
+ .weak I2C2_EV_IRQHandler
+ .thumb_set I2C2_EV_IRQHandler,Default_Handler
+
+ .weak I2C2_ER_IRQHandler
+ .thumb_set I2C2_ER_IRQHandler,Default_Handler
+
+ .weak SPI1_IRQHandler
+ .thumb_set SPI1_IRQHandler,Default_Handler
+
+ .weak SPI2_IRQHandler
+ .thumb_set SPI2_IRQHandler,Default_Handler
+
+ .weak USART1_IRQHandler
+ .thumb_set USART1_IRQHandler,Default_Handler
+
+ .weak USART2_IRQHandler
+ .thumb_set USART2_IRQHandler,Default_Handler
+
+ .weak USART3_IRQHandler
+ .thumb_set USART3_IRQHandler,Default_Handler
+
+ .weak EXTI15_10_IRQHandler
+ .thumb_set EXTI15_10_IRQHandler,Default_Handler
+
+ .weak RTCAlarm_IRQHandler
+ .thumb_set RTCAlarm_IRQHandler,Default_Handler
+
+ .weak USBWakeUp_IRQHandler
+ .thumb_set USBWakeUp_IRQHandler,Default_Handler
+
+/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
+
diff --git a/Libraries/CMSIS/Device/ST/STM32F10x/Source/Templates/TrueSTUDIO/startup_stm32f10x_md_vl.s b/Libraries/CMSIS/Device/ST/STM32F10x/Source/Templates/TrueSTUDIO/startup_stm32f10x_md_vl.s
new file mode 100644
index 0000000..2427331
--- /dev/null
+++ b/Libraries/CMSIS/Device/ST/STM32F10x/Source/Templates/TrueSTUDIO/startup_stm32f10x_md_vl.s
@@ -0,0 +1,414 @@
+/**
+ ******************************************************************************
+ * @file startup_stm32f10x_md_vl.s
+ * @author MCD Application Team
+ * @version V3.6.1
+ * @date 09-March-2012
+ * @brief STM32F10x Medium Density Value Line Devices vector table for Atollic
+ * toolchain.
+ * This module performs:
+ * - Set the initial SP
+ * - Set the initial PC == Reset_Handler,
+ * - Set the vector table entries with the exceptions ISR address
+ * - Configure the clock system
+ * - Branches to main in the C library (which eventually
+ * calls main()).
+ * After Reset the Cortex-M3 processor is in Thread mode,
+ * priority is Privileged, and the Stack is set to Main.
+ ******************************************************************************
+ * @attention
+ *
+ * © COPYRIGHT 2012 STMicroelectronics
+ *
+ * Licensed under MCD-ST Liberty SW License Agreement V2, (the "License");
+ * You may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at:
+ *
+ * http://www.st.com/software_license_agreement_liberty_v2
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ *
+ ******************************************************************************
+ */
+
+ .syntax unified
+ .cpu cortex-m3
+ .fpu softvfp
+ .thumb
+
+.global g_pfnVectors
+.global Default_Handler
+
+/* start address for the initialization values of the .data section.
+defined in linker script */
+.word _sidata
+/* start address for the .data section. defined in linker script */
+.word _sdata
+/* end address for the .data section. defined in linker script */
+.word _edata
+/* start address for the .bss section. defined in linker script */
+.word _sbss
+/* end address for the .bss section. defined in linker script */
+.word _ebss
+
+.equ BootRAM, 0xF108F85F
+/**
+ * @brief This is the code that gets called when the processor first
+ * starts execution following a reset event. Only the absolutely
+ * necessary set is performed, after which the application
+ * supplied main() routine is called.
+ * @param None
+ * @retval : None
+*/
+
+ .section .text.Reset_Handler
+ .weak Reset_Handler
+ .type Reset_Handler, %function
+Reset_Handler:
+
+/* Copy the data segment initializers from flash to SRAM */
+ movs r1, #0
+ b LoopCopyDataInit
+
+CopyDataInit:
+ ldr r3, =_sidata
+ ldr r3, [r3, r1]
+ str r3, [r0, r1]
+ adds r1, r1, #4
+
+LoopCopyDataInit:
+ ldr r0, =_sdata
+ ldr r3, =_edata
+ adds r2, r0, r1
+ cmp r2, r3
+ bcc CopyDataInit
+ ldr r2, =_sbss
+ b LoopFillZerobss
+/* Zero fill the bss segment. */
+FillZerobss:
+ movs r3, #0
+ str r3, [r2], #4
+
+LoopFillZerobss:
+ ldr r3, = _ebss
+ cmp r2, r3
+ bcc FillZerobss
+
+/* Call the clock system intitialization function.*/
+ bl SystemInit
+/* Call static constructors */
+ bl __libc_init_array
+/* Call the application's entry point.*/
+ bl main
+ bx lr
+.size Reset_Handler, .-Reset_Handler
+
+/**
+ * @brief This is the code that gets called when the processor receives an
+ * unexpected interrupt. This simply enters an infinite loop, preserving
+ * the system state for examination by a debugger.
+ *
+ * @param None
+ * @retval : None
+*/
+ .section .text.Default_Handler,"ax",%progbits
+Default_Handler:
+Infinite_Loop:
+ b Infinite_Loop
+ .size Default_Handler, .-Default_Handler
+/******************************************************************************
+*
+* The minimal vector table for a Cortex M3. Note that the proper constructs
+* must be placed on this to ensure that it ends up at physical address
+* 0x0000.0000.
+*
+******************************************************************************/
+ .section .isr_vector,"a",%progbits
+ .type g_pfnVectors, %object
+ .size g_pfnVectors, .-g_pfnVectors
+
+
+g_pfnVectors:
+ .word _estack
+ .word Reset_Handler
+ .word NMI_Handler
+ .word HardFault_Handler
+ .word MemManage_Handler
+ .word BusFault_Handler
+ .word UsageFault_Handler
+ .word 0
+ .word 0
+ .word 0
+ .word 0
+ .word SVC_Handler
+ .word DebugMon_Handler
+ .word 0
+ .word PendSV_Handler
+ .word SysTick_Handler
+ .word WWDG_IRQHandler
+ .word PVD_IRQHandler
+ .word TAMPER_IRQHandler
+ .word RTC_IRQHandler
+ .word FLASH_IRQHandler
+ .word RCC_IRQHandler
+ .word EXTI0_IRQHandler
+ .word EXTI1_IRQHandler
+ .word EXTI2_IRQHandler
+ .word EXTI3_IRQHandler
+ .word EXTI4_IRQHandler
+ .word DMA1_Channel1_IRQHandler
+ .word DMA1_Channel2_IRQHandler
+ .word DMA1_Channel3_IRQHandler
+ .word DMA1_Channel4_IRQHandler
+ .word DMA1_Channel5_IRQHandler
+ .word DMA1_Channel6_IRQHandler
+ .word DMA1_Channel7_IRQHandler
+ .word ADC1_IRQHandler
+ .word 0
+ .word 0
+ .word 0
+ .word 0
+ .word EXTI9_5_IRQHandler
+ .word TIM1_BRK_TIM15_IRQHandler
+ .word TIM1_UP_TIM16_IRQHandler
+ .word TIM1_TRG_COM_TIM17_IRQHandler
+ .word TIM1_CC_IRQHandler
+ .word TIM2_IRQHandler
+ .word TIM3_IRQHandler
+ .word TIM4_IRQHandler
+ .word I2C1_EV_IRQHandler
+ .word I2C1_ER_IRQHandler
+ .word I2C2_EV_IRQHandler
+ .word I2C2_ER_IRQHandler
+ .word SPI1_IRQHandler
+ .word SPI2_IRQHandler
+ .word USART1_IRQHandler
+ .word USART2_IRQHandler
+ .word USART3_IRQHandler
+ .word EXTI15_10_IRQHandler
+ .word RTCAlarm_IRQHandler
+ .word CEC_IRQHandler
+ .word 0
+ .word 0
+ .word 0
+ .word 0
+ .word 0
+ .word 0
+ .word 0
+ .word 0
+ .word 0
+ .word 0
+ .word 0
+ .word TIM6_DAC_IRQHandler
+ .word TIM7_IRQHandler
+ .word 0
+ .word 0
+ .word 0
+ .word 0
+ .word 0
+ .word 0
+ .word 0
+ .word 0
+ .word 0
+ .word 0
+ .word 0
+ .word 0
+ .word 0
+ .word 0
+ .word 0
+ .word 0
+ .word 0
+ .word 0
+ .word 0
+ .word 0
+ .word 0
+ .word 0
+ .word 0
+ .word 0
+ .word 0
+ .word 0
+ .word 0
+ .word 0
+ .word 0
+ .word 0
+ .word 0
+ .word 0
+ .word 0
+ .word 0
+ .word 0
+ .word 0
+ .word 0
+ .word 0
+ .word 0
+ .word 0
+ .word 0
+ .word 0
+ .word 0
+ .word BootRAM /* @0x01CC. This is for boot in RAM mode for
+ STM32F10x Medium Value Line Density devices. */
+
+/*******************************************************************************
+*
+* Provide weak aliases for each Exception handler to the Default_Handler.
+* As they are weak aliases, any function with the same name will override
+* this definition.
+*
+*******************************************************************************/
+
+
+ .weak NMI_Handler
+ .thumb_set NMI_Handler,Default_Handler
+
+ .weak HardFault_Handler
+ .thumb_set HardFault_Handler,Default_Handler
+
+ .weak MemManage_Handler
+ .thumb_set MemManage_Handler,Default_Handler
+
+ .weak BusFault_Handler
+ .thumb_set BusFault_Handler,Default_Handler
+
+ .weak UsageFault_Handler
+ .thumb_set UsageFault_Handler,Default_Handler
+
+ .weak SVC_Handler
+ .thumb_set SVC_Handler,Default_Handler
+
+ .weak DebugMon_Handler
+ .thumb_set DebugMon_Handler,Default_Handler
+
+ .weak PendSV_Handler
+ .thumb_set PendSV_Handler,Default_Handler
+
+ .weak SysTick_Handler
+ .thumb_set SysTick_Handler,Default_Handler
+
+ .weak WWDG_IRQHandler
+ .thumb_set WWDG_IRQHandler,Default_Handler
+
+ .weak PVD_IRQHandler
+ .thumb_set PVD_IRQHandler,Default_Handler
+
+ .weak TAMPER_IRQHandler
+ .thumb_set TAMPER_IRQHandler,Default_Handler
+
+ .weak RTC_IRQHandler
+ .thumb_set RTC_IRQHandler,Default_Handler
+
+ .weak FLASH_IRQHandler
+ .thumb_set FLASH_IRQHandler,Default_Handler
+
+ .weak RCC_IRQHandler
+ .thumb_set RCC_IRQHandler,Default_Handler
+
+ .weak EXTI0_IRQHandler
+ .thumb_set EXTI0_IRQHandler,Default_Handler
+
+ .weak EXTI1_IRQHandler
+ .thumb_set EXTI1_IRQHandler,Default_Handler
+
+ .weak EXTI2_IRQHandler
+ .thumb_set EXTI2_IRQHandler,Default_Handler
+
+ .weak EXTI3_IRQHandler
+ .thumb_set EXTI3_IRQHandler,Default_Handler
+
+ .weak EXTI4_IRQHandler
+ .thumb_set EXTI4_IRQHandler,Default_Handler
+
+ .weak DMA1_Channel1_IRQHandler
+ .thumb_set DMA1_Channel1_IRQHandler,Default_Handler
+
+ .weak DMA1_Channel2_IRQHandler
+ .thumb_set DMA1_Channel2_IRQHandler,Default_Handler
+
+ .weak DMA1_Channel3_IRQHandler
+ .thumb_set DMA1_Channel3_IRQHandler,Default_Handler
+
+ .weak DMA1_Channel4_IRQHandler
+ .thumb_set DMA1_Channel4_IRQHandler,Default_Handler
+
+ .weak DMA1_Channel5_IRQHandler
+ .thumb_set DMA1_Channel5_IRQHandler,Default_Handler
+
+ .weak DMA1_Channel6_IRQHandler
+ .thumb_set DMA1_Channel6_IRQHandler,Default_Handler
+
+ .weak DMA1_Channel7_IRQHandler
+ .thumb_set DMA1_Channel7_IRQHandler,Default_Handler
+
+ .weak ADC1_IRQHandler
+ .thumb_set ADC1_IRQHandler,Default_Handler
+
+ .weak EXTI9_5_IRQHandler
+ .thumb_set EXTI9_5_IRQHandler,Default_Handler
+
+ .weak TIM1_BRK_TIM15_IRQHandler
+ .thumb_set TIM1_BRK_TIM15_IRQHandler,Default_Handler
+
+ .weak TIM1_UP_TIM16_IRQHandler
+ .thumb_set TIM1_UP_TIM16_IRQHandler,Default_Handler
+
+ .weak TIM1_TRG_COM_TIM17_IRQHandler
+ .thumb_set TIM1_TRG_COM_TIM17_IRQHandler,Default_Handler
+
+ .weak TIM1_CC_IRQHandler
+ .thumb_set TIM1_CC_IRQHandler,Default_Handler
+
+ .weak TIM2_IRQHandler
+ .thumb_set TIM2_IRQHandler,Default_Handler
+
+ .weak TIM3_IRQHandler
+ .thumb_set TIM3_IRQHandler,Default_Handler
+
+ .weak TIM4_IRQHandler
+ .thumb_set TIM4_IRQHandler,Default_Handler
+
+ .weak I2C1_EV_IRQHandler
+ .thumb_set I2C1_EV_IRQHandler,Default_Handler
+
+ .weak I2C1_ER_IRQHandler
+ .thumb_set I2C1_ER_IRQHandler,Default_Handler
+
+ .weak I2C2_EV_IRQHandler
+ .thumb_set I2C2_EV_IRQHandler,Default_Handler
+
+ .weak I2C2_ER_IRQHandler
+ .thumb_set I2C2_ER_IRQHandler,Default_Handler
+
+ .weak SPI1_IRQHandler
+ .thumb_set SPI1_IRQHandler,Default_Handler
+
+ .weak SPI2_IRQHandler
+ .thumb_set SPI2_IRQHandler,Default_Handler
+
+ .weak USART1_IRQHandler
+ .thumb_set USART1_IRQHandler,Default_Handler
+
+ .weak USART2_IRQHandler
+ .thumb_set USART2_IRQHandler,Default_Handler
+
+ .weak USART3_IRQHandler
+ .thumb_set USART3_IRQHandler,Default_Handler
+
+ .weak EXTI15_10_IRQHandler
+ .thumb_set EXTI15_10_IRQHandler,Default_Handler
+
+ .weak RTCAlarm_IRQHandler
+ .thumb_set RTCAlarm_IRQHandler,Default_Handler
+
+ .weak CEC_IRQHandler
+ .thumb_set CEC_IRQHandler,Default_Handler
+
+ .weak TIM6_DAC_IRQHandler
+ .thumb_set TIM6_DAC_IRQHandler,Default_Handler
+
+ .weak TIM7_IRQHandler
+ .thumb_set TIM7_IRQHandler,Default_Handler
+
+/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
+
diff --git a/Libraries/CMSIS/Device/ST/STM32F10x/Source/Templates/TrueSTUDIO/startup_stm32f10x_xl.s b/Libraries/CMSIS/Device/ST/STM32F10x/Source/Templates/TrueSTUDIO/startup_stm32f10x_xl.s
new file mode 100644
index 0000000..366a965
--- /dev/null
+++ b/Libraries/CMSIS/Device/ST/STM32F10x/Source/Templates/TrueSTUDIO/startup_stm32f10x_xl.s
@@ -0,0 +1,473 @@
+/**
+ ******************************************************************************
+ * @file startup_stm32f10x_xl.s
+ * @author MCD Application Team
+ * @version V3.6.1
+ * @date 09-March-2012
+ * @brief STM32F10x XL-Density Devices vector table for TrueSTUDIO toolchain.
+ * This module performs:
+ * - Set the initial SP
+ * - Set the initial PC == Reset_Handler,
+ * - Set the vector table entries with the exceptions ISR address
+ * - Configure the clock system and the external SRAM mounted on
+ * STM3210E-EVAL board to be used as data memory (optional,
+ * to be enabled by user)
+ * - Branches to main in the C library (which eventually
+ * calls main()).
+ * After Reset the Cortex-M3 processor is in Thread mode,
+ * priority is Privileged, and the Stack is set to Main.
+ ******************************************************************************
+ * @attention
+ *
+ * © COPYRIGHT 2012 STMicroelectronics
+ *
+ * Licensed under MCD-ST Liberty SW License Agreement V2, (the "License");
+ * You may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at:
+ *
+ * http://www.st.com/software_license_agreement_liberty_v2
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ *
+ ******************************************************************************
+ */
+
+ .syntax unified
+ .cpu cortex-m3
+ .fpu softvfp
+ .thumb
+
+.global g_pfnVectors
+.global Default_Handler
+
+/* start address for the initialization values of the .data section.
+defined in linker script */
+.word _sidata
+/* start address for the .data section. defined in linker script */
+.word _sdata
+/* end address for the .data section. defined in linker script */
+.word _edata
+/* start address for the .bss section. defined in linker script */
+.word _sbss
+/* end address for the .bss section. defined in linker script */
+.word _ebss
+
+.equ BootRAM, 0xF1E0F85F
+/**
+ * @brief This is the code that gets called when the processor first
+ * starts execution following a reset event. Only the absolutely
+ * necessary set is performed, after which the application
+ * supplied main() routine is called.
+ * @param None
+ * @retval : None
+*/
+
+ .section .text.Reset_Handler
+ .weak Reset_Handler
+ .type Reset_Handler, %function
+Reset_Handler:
+
+/* Copy the data segment initializers from flash to SRAM */
+ movs r1, #0
+ b LoopCopyDataInit
+
+CopyDataInit:
+ ldr r3, =_sidata
+ ldr r3, [r3, r1]
+ str r3, [r0, r1]
+ adds r1, r1, #4
+
+LoopCopyDataInit:
+ ldr r0, =_sdata
+ ldr r3, =_edata
+ adds r2, r0, r1
+ cmp r2, r3
+ bcc CopyDataInit
+ ldr r2, =_sbss
+ b LoopFillZerobss
+/* Zero fill the bss segment. */
+FillZerobss:
+ movs r3, #0
+ str r3, [r2], #4
+
+LoopFillZerobss:
+ ldr r3, = _ebss
+ cmp r2, r3
+ bcc FillZerobss
+
+/* Call the clock system intitialization function.*/
+ bl SystemInit
+/* Call static constructors */
+ bl __libc_init_array
+/* Call the application's entry point.*/
+ bl main
+ bx lr
+.size Reset_Handler, .-Reset_Handler
+
+/**
+ * @brief This is the code that gets called when the processor receives an
+ * unexpected interrupt. This simply enters an infinite loop, preserving
+ * the system state for examination by a debugger.
+ * @param None
+ * @retval None
+*/
+ .section .text.Default_Handler,"ax",%progbits
+Default_Handler:
+Infinite_Loop:
+ b Infinite_Loop
+ .size Default_Handler, .-Default_Handler
+/******************************************************************************
+*
+* The minimal vector table for a Cortex M3. Note that the proper constructs
+* must be placed on this to ensure that it ends up at physical address
+* 0x0000.0000.
+*
+*******************************************************************************/
+ .section .isr_vector,"a",%progbits
+ .type g_pfnVectors, %object
+ .size g_pfnVectors, .-g_pfnVectors
+
+
+g_pfnVectors:
+ .word _estack
+ .word Reset_Handler
+ .word NMI_Handler
+ .word HardFault_Handler
+ .word MemManage_Handler
+ .word BusFault_Handler
+ .word UsageFault_Handler
+ .word 0
+ .word 0
+ .word 0
+ .word 0
+ .word SVC_Handler
+ .word DebugMon_Handler
+ .word 0
+ .word PendSV_Handler
+ .word SysTick_Handler
+ .word WWDG_IRQHandler
+ .word PVD_IRQHandler
+ .word TAMPER_IRQHandler
+ .word RTC_IRQHandler
+ .word FLASH_IRQHandler
+ .word RCC_IRQHandler
+ .word EXTI0_IRQHandler
+ .word EXTI1_IRQHandler
+ .word EXTI2_IRQHandler
+ .word EXTI3_IRQHandler
+ .word EXTI4_IRQHandler
+ .word DMA1_Channel1_IRQHandler
+ .word DMA1_Channel2_IRQHandler
+ .word DMA1_Channel3_IRQHandler
+ .word DMA1_Channel4_IRQHandler
+ .word DMA1_Channel5_IRQHandler
+ .word DMA1_Channel6_IRQHandler
+ .word DMA1_Channel7_IRQHandler
+ .word ADC1_2_IRQHandler
+ .word USB_HP_CAN1_TX_IRQHandler
+ .word USB_LP_CAN1_RX0_IRQHandler
+ .word CAN1_RX1_IRQHandler
+ .word CAN1_SCE_IRQHandler
+ .word EXTI9_5_IRQHandler
+ .word TIM1_BRK_TIM9_IRQHandler
+ .word TIM1_UP_TIM10_IRQHandler
+ .word TIM1_TRG_COM_TIM11_IRQHandler
+ .word TIM1_CC_IRQHandler
+ .word TIM2_IRQHandler
+ .word TIM3_IRQHandler
+ .word TIM4_IRQHandler
+ .word I2C1_EV_IRQHandler
+ .word I2C1_ER_IRQHandler
+ .word I2C2_EV_IRQHandler
+ .word I2C2_ER_IRQHandler
+ .word SPI1_IRQHandler
+ .word SPI2_IRQHandler
+ .word USART1_IRQHandler
+ .word USART2_IRQHandler
+ .word USART3_IRQHandler
+ .word EXTI15_10_IRQHandler
+ .word RTCAlarm_IRQHandler
+ .word USBWakeUp_IRQHandler
+ .word TIM8_BRK_TIM12_IRQHandler
+ .word TIM8_UP_TIM13_IRQHandler
+ .word TIM8_TRG_COM_TIM14_IRQHandler
+ .word TIM8_CC_IRQHandler
+ .word ADC3_IRQHandler
+ .word FSMC_IRQHandler
+ .word SDIO_IRQHandler
+ .word TIM5_IRQHandler
+ .word SPI3_IRQHandler
+ .word UART4_IRQHandler
+ .word UART5_IRQHandler
+ .word TIM6_IRQHandler
+ .word TIM7_IRQHandler
+ .word DMA2_Channel1_IRQHandler
+ .word DMA2_Channel2_IRQHandler
+ .word DMA2_Channel3_IRQHandler
+ .word DMA2_Channel4_5_IRQHandler
+ .word 0
+ .word 0
+ .word 0
+ .word 0
+ .word 0
+ .word 0
+ .word 0
+ .word 0
+ .word 0
+ .word 0
+ .word 0
+ .word 0
+ .word 0
+ .word 0
+ .word 0
+ .word 0
+ .word 0
+ .word 0
+ .word 0
+ .word 0
+ .word 0
+ .word 0
+ .word 0
+ .word 0
+ .word 0
+ .word 0
+ .word 0
+ .word 0
+ .word 0
+ .word 0
+ .word 0
+ .word 0
+ .word 0
+ .word 0
+ .word 0
+ .word 0
+ .word 0
+ .word 0
+ .word 0
+ .word 0
+ .word 0
+ .word 0
+ .word 0
+ .word 0
+ .word BootRAM /* @0x1E0. This is for boot in RAM mode for
+ STM32F10x XL-Density devices. */
+/*******************************************************************************
+*
+* Provide weak aliases for each Exception handler to the Default_Handler.
+* As they are weak aliases, any function with the same name will override
+* this definition.
+*
+*******************************************************************************/
+
+ .weak NMI_Handler
+ .thumb_set NMI_Handler,Default_Handler
+
+ .weak HardFault_Handler
+ .thumb_set HardFault_Handler,Default_Handler
+
+ .weak MemManage_Handler
+ .thumb_set MemManage_Handler,Default_Handler
+
+ .weak BusFault_Handler
+ .thumb_set BusFault_Handler,Default_Handler
+
+ .weak UsageFault_Handler
+ .thumb_set UsageFault_Handler,Default_Handler
+
+ .weak SVC_Handler
+ .thumb_set SVC_Handler,Default_Handler
+
+ .weak DebugMon_Handler
+ .thumb_set DebugMon_Handler,Default_Handler
+
+ .weak PendSV_Handler
+ .thumb_set PendSV_Handler,Default_Handler
+
+ .weak SysTick_Handler
+ .thumb_set SysTick_Handler,Default_Handler
+
+ .weak WWDG_IRQHandler
+ .thumb_set WWDG_IRQHandler,Default_Handler
+
+ .weak PVD_IRQHandler
+ .thumb_set PVD_IRQHandler,Default_Handler
+
+ .weak TAMPER_IRQHandler
+ .thumb_set TAMPER_IRQHandler,Default_Handler
+
+ .weak RTC_IRQHandler
+ .thumb_set RTC_IRQHandler,Default_Handler
+
+ .weak FLASH_IRQHandler
+ .thumb_set FLASH_IRQHandler,Default_Handler
+
+ .weak RCC_IRQHandler
+ .thumb_set RCC_IRQHandler,Default_Handler
+
+ .weak EXTI0_IRQHandler
+ .thumb_set EXTI0_IRQHandler,Default_Handler
+
+ .weak EXTI1_IRQHandler
+ .thumb_set EXTI1_IRQHandler,Default_Handler
+
+ .weak EXTI2_IRQHandler
+ .thumb_set EXTI2_IRQHandler,Default_Handler
+
+ .weak EXTI3_IRQHandler
+ .thumb_set EXTI3_IRQHandler,Default_Handler
+
+ .weak EXTI4_IRQHandler
+ .thumb_set EXTI4_IRQHandler,Default_Handler
+
+ .weak DMA1_Channel1_IRQHandler
+ .thumb_set DMA1_Channel1_IRQHandler,Default_Handler
+
+ .weak DMA1_Channel2_IRQHandler
+ .thumb_set DMA1_Channel2_IRQHandler,Default_Handler
+
+ .weak DMA1_Channel3_IRQHandler
+ .thumb_set DMA1_Channel3_IRQHandler,Default_Handler
+
+ .weak DMA1_Channel4_IRQHandler
+ .thumb_set DMA1_Channel4_IRQHandler,Default_Handler
+
+ .weak DMA1_Channel5_IRQHandler
+ .thumb_set DMA1_Channel5_IRQHandler,Default_Handler
+
+ .weak DMA1_Channel6_IRQHandler
+ .thumb_set DMA1_Channel6_IRQHandler,Default_Handler
+
+ .weak DMA1_Channel7_IRQHandler
+ .thumb_set DMA1_Channel7_IRQHandler,Default_Handler
+
+ .weak ADC1_2_IRQHandler
+ .thumb_set ADC1_2_IRQHandler,Default_Handler
+
+ .weak USB_HP_CAN1_TX_IRQHandler
+ .thumb_set USB_HP_CAN1_TX_IRQHandler,Default_Handler
+
+ .weak USB_LP_CAN1_RX0_IRQHandler
+ .thumb_set USB_LP_CAN1_RX0_IRQHandler,Default_Handler
+
+ .weak CAN1_RX1_IRQHandler
+ .thumb_set CAN1_RX1_IRQHandler,Default_Handler
+
+ .weak CAN1_SCE_IRQHandler
+ .thumb_set CAN1_SCE_IRQHandler,Default_Handler
+
+ .weak EXTI9_5_IRQHandler
+ .thumb_set EXTI9_5_IRQHandler,Default_Handler
+
+ .weak TIM1_BRK_TIM9_IRQHandler
+ .thumb_set TIM1_BRK_TIM9_IRQHandler,Default_Handler
+
+ .weak TIM1_UP_TIM10_IRQHandler
+ .thumb_set TIM1_UP_TIM10_IRQHandler,Default_Handler
+
+ .weak TIM1_TRG_COM_TIM11_IRQHandler
+ .thumb_set TIM1_TRG_COM_TIM11_IRQHandler,Default_Handler
+
+ .weak TIM1_CC_IRQHandler
+ .thumb_set TIM1_CC_IRQHandler,Default_Handler
+
+ .weak TIM2_IRQHandler
+ .thumb_set TIM2_IRQHandler,Default_Handler
+
+ .weak TIM3_IRQHandler
+ .thumb_set TIM3_IRQHandler,Default_Handler
+
+ .weak TIM4_IRQHandler
+ .thumb_set TIM4_IRQHandler,Default_Handler
+
+ .weak I2C1_EV_IRQHandler
+ .thumb_set I2C1_EV_IRQHandler,Default_Handler
+
+ .weak I2C1_ER_IRQHandler
+ .thumb_set I2C1_ER_IRQHandler,Default_Handler
+
+ .weak I2C2_EV_IRQHandler
+ .thumb_set I2C2_EV_IRQHandler,Default_Handler
+
+ .weak I2C2_ER_IRQHandler
+ .thumb_set I2C2_ER_IRQHandler,Default_Handler
+
+ .weak SPI1_IRQHandler
+ .thumb_set SPI1_IRQHandler,Default_Handler
+
+ .weak SPI2_IRQHandler
+ .thumb_set SPI2_IRQHandler,Default_Handler
+
+ .weak USART1_IRQHandler
+ .thumb_set USART1_IRQHandler,Default_Handler
+
+ .weak USART2_IRQHandler
+ .thumb_set USART2_IRQHandler,Default_Handler
+
+ .weak USART3_IRQHandler
+ .thumb_set USART3_IRQHandler,Default_Handler
+
+ .weak EXTI15_10_IRQHandler
+ .thumb_set EXTI15_10_IRQHandler,Default_Handler
+
+ .weak RTCAlarm_IRQHandler
+ .thumb_set RTCAlarm_IRQHandler,Default_Handler
+
+ .weak USBWakeUp_IRQHandler
+ .thumb_set USBWakeUp_IRQHandler,Default_Handler
+
+ .weak TIM8_BRK_TIM12_IRQHandler
+ .thumb_set TIM8_BRK_TIM12_IRQHandler,Default_Handler
+
+ .weak TIM8_UP_TIM13_IRQHandler
+ .thumb_set TIM8_UP_TIM13_IRQHandler,Default_Handler
+
+ .weak TIM8_TRG_COM_TIM14_IRQHandler
+ .thumb_set TIM8_TRG_COM_TIM14_IRQHandler,Default_Handler
+
+ .weak TIM8_CC_IRQHandler
+ .thumb_set TIM8_CC_IRQHandler,Default_Handler
+
+ .weak ADC3_IRQHandler
+ .thumb_set ADC3_IRQHandler,Default_Handler
+
+ .weak FSMC_IRQHandler
+ .thumb_set FSMC_IRQHandler,Default_Handler
+
+ .weak SDIO_IRQHandler
+ .thumb_set SDIO_IRQHandler,Default_Handler
+
+ .weak TIM5_IRQHandler
+ .thumb_set TIM5_IRQHandler,Default_Handler
+
+ .weak SPI3_IRQHandler
+ .thumb_set SPI3_IRQHandler,Default_Handler
+
+ .weak UART4_IRQHandler
+ .thumb_set UART4_IRQHandler,Default_Handler
+
+ .weak UART5_IRQHandler
+ .thumb_set UART5_IRQHandler,Default_Handler
+
+ .weak TIM6_IRQHandler
+ .thumb_set TIM6_IRQHandler,Default_Handler
+
+ .weak TIM7_IRQHandler
+ .thumb_set TIM7_IRQHandler,Default_Handler
+
+ .weak DMA2_Channel1_IRQHandler
+ .thumb_set DMA2_Channel1_IRQHandler,Default_Handler
+
+ .weak DMA2_Channel2_IRQHandler
+ .thumb_set DMA2_Channel2_IRQHandler,Default_Handler
+
+ .weak DMA2_Channel3_IRQHandler
+ .thumb_set DMA2_Channel3_IRQHandler,Default_Handler
+
+ .weak DMA2_Channel4_5_IRQHandler
+ .thumb_set DMA2_Channel4_5_IRQHandler,Default_Handler
+
+/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
diff --git a/Libraries/CMSIS/Device/ST/STM32F10x/Source/Templates/arm/startup_stm32f10x_cl.s b/Libraries/CMSIS/Device/ST/STM32F10x/Source/Templates/arm/startup_stm32f10x_cl.s
new file mode 100644
index 0000000..15a7768
--- /dev/null
+++ b/Libraries/CMSIS/Device/ST/STM32F10x/Source/Templates/arm/startup_stm32f10x_cl.s
@@ -0,0 +1,375 @@
+;******************** (C) COPYRIGHT 2012 STMicroelectronics ********************
+;* File Name : startup_stm32f10x_cl.s
+;* Author : MCD Application Team
+;* Version : V3.6.1
+;* Date : 09-March-2012
+;* Description : STM32F10x Connectivity line devices vector table for MDK-ARM
+;* toolchain.
+;* This module performs:
+;* - Set the initial SP
+;* - Set the initial PC == Reset_Handler
+;* - Set the vector table entries with the exceptions ISR address
+;* - Configure the clock system
+;* - Branches to __main in the C library (which eventually
+;* calls main()).
+;* After Reset the CortexM3 processor is in Thread mode,
+;* priority is Privileged, and the Stack is set to Main.
+;* <<< Use Configuration Wizard in Context Menu >>>
+;*******************************************************************************
+;
+; Licensed under MCD-ST Liberty SW License Agreement V2, (the "License");
+; You may not use this file except in compliance with the License.
+; You may obtain a copy of the License at:
+;
+; http://www.st.com/software_license_agreement_liberty_v2
+;
+; Unless required by applicable law or agreed to in writing, software
+; distributed under the License is distributed on an "AS IS" BASIS,
+; WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+; See the License for the specific language governing permissions and
+; limitations under the License.
+;
+;*******************************************************************************
+
+; Amount of memory (in bytes) allocated for Stack
+; Tailor this value to your application needs
+; © COPYRIGHT 2012 STMicroelectronics
+ *
+ * Licensed under MCD-ST Liberty SW License Agreement V2, (the "License");
+ * You may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at:
+ *
+ * http://www.st.com/software_license_agreement_liberty_v2
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ *
+ ******************************************************************************
+ */
+
+ .syntax unified
+ .cpu cortex-m3
+ .fpu softvfp
+ .thumb
+
+.global g_pfnVectors
+.global Default_Handler
+
+/* start address for the initialization values of the .data section.
+defined in linker script */
+.word _sidata
+/* start address for the .data section. defined in linker script */
+.word _sdata
+/* end address for the .data section. defined in linker script */
+.word _edata
+/* start address for the .bss section. defined in linker script */
+.word _sbss
+/* end address for the .bss section. defined in linker script */
+.word _ebss
+
+.equ BootRAM, 0xF1E0F85F
+/**
+ * @brief This is the code that gets called when the processor first
+ * starts execution following a reset event. Only the absolutely
+ * necessary set is performed, after which the application
+ * supplied main() routine is called.
+ * @param None
+ * @retval : None
+*/
+
+ .section .text.Reset_Handler
+ .weak Reset_Handler
+ .type Reset_Handler, %function
+Reset_Handler:
+
+/* Copy the data segment initializers from flash to SRAM */
+ movs r1, #0
+ b LoopCopyDataInit
+
+CopyDataInit:
+ ldr r3, =_sidata
+ ldr r3, [r3, r1]
+ str r3, [r0, r1]
+ adds r1, r1, #4
+
+LoopCopyDataInit:
+ ldr r0, =_sdata
+ ldr r3, =_edata
+ adds r2, r0, r1
+ cmp r2, r3
+ bcc CopyDataInit
+ ldr r2, =_sbss
+ b LoopFillZerobss
+
+/* Zero fill the bss segment. */
+FillZerobss:
+ movs r3, #0
+ str r3, [r2], #4
+
+LoopFillZerobss:
+ ldr r3, = _ebss
+ cmp r2, r3
+ bcc FillZerobss
+/* Call the clock system intitialization function.*/
+ bl SystemInit
+/* Call the application's entry point.*/
+ bl main
+ bx lr
+.size Reset_Handler, .-Reset_Handler
+
+/**
+ * @brief This is the code that gets called when the processor receives an
+ * unexpected interrupt. This simply enters an infinite loop, preserving
+ * the system state for examination by a debugger.
+ * @param None
+ * @retval None
+*/
+ .section .text.Default_Handler,"ax",%progbits
+Default_Handler:
+Infinite_Loop:
+ b Infinite_Loop
+ .size Default_Handler, .-Default_Handler
+
+/******************************************************************************
+*
+* The minimal vector table for a Cortex M3. Note that the proper constructs
+* must be placed on this to ensure that it ends up at physical address
+* 0x0000.0000.
+*
+*******************************************************************************/
+ .section .isr_vector,"a",%progbits
+ .type g_pfnVectors, %object
+ .size g_pfnVectors, .-g_pfnVectors
+
+
+g_pfnVectors:
+ .word _estack
+ .word Reset_Handler
+ .word NMI_Handler
+ .word HardFault_Handler
+ .word MemManage_Handler
+ .word BusFault_Handler
+ .word UsageFault_Handler
+ .word 0
+ .word 0
+ .word 0
+ .word 0
+ .word SVC_Handler
+ .word DebugMon_Handler
+ .word 0
+ .word PendSV_Handler
+ .word SysTick_Handler
+ .word WWDG_IRQHandler
+ .word PVD_IRQHandler
+ .word TAMPER_IRQHandler
+ .word RTC_IRQHandler
+ .word FLASH_IRQHandler
+ .word RCC_IRQHandler
+ .word EXTI0_IRQHandler
+ .word EXTI1_IRQHandler
+ .word EXTI2_IRQHandler
+ .word EXTI3_IRQHandler
+ .word EXTI4_IRQHandler
+ .word DMA1_Channel1_IRQHandler
+ .word DMA1_Channel2_IRQHandler
+ .word DMA1_Channel3_IRQHandler
+ .word DMA1_Channel4_IRQHandler
+ .word DMA1_Channel5_IRQHandler
+ .word DMA1_Channel6_IRQHandler
+ .word DMA1_Channel7_IRQHandler
+ .word ADC1_2_IRQHandler
+ .word CAN1_TX_IRQHandler
+ .word CAN1_RX0_IRQHandler
+ .word CAN1_RX1_IRQHandler
+ .word CAN1_SCE_IRQHandler
+ .word EXTI9_5_IRQHandler
+ .word TIM1_BRK_IRQHandler
+ .word TIM1_UP_IRQHandler
+ .word TIM1_TRG_COM_IRQHandler
+ .word TIM1_CC_IRQHandler
+ .word TIM2_IRQHandler
+ .word TIM3_IRQHandler
+ .word TIM4_IRQHandler
+ .word I2C1_EV_IRQHandler
+ .word I2C1_ER_IRQHandler
+ .word I2C2_EV_IRQHandler
+ .word I2C2_ER_IRQHandler
+ .word SPI1_IRQHandler
+ .word SPI2_IRQHandler
+ .word USART1_IRQHandler
+ .word USART2_IRQHandler
+ .word USART3_IRQHandler
+ .word EXTI15_10_IRQHandler
+ .word RTCAlarm_IRQHandler
+ .word OTG_FS_WKUP_IRQHandler
+ .word 0
+ .word 0
+ .word 0
+ .word 0
+ .word 0
+ .word 0
+ .word 0
+ .word TIM5_IRQHandler
+ .word SPI3_IRQHandler
+ .word UART4_IRQHandler
+ .word UART5_IRQHandler
+ .word TIM6_IRQHandler
+ .word TIM7_IRQHandler
+ .word DMA2_Channel1_IRQHandler
+ .word DMA2_Channel2_IRQHandler
+ .word DMA2_Channel3_IRQHandler
+ .word DMA2_Channel4_IRQHandler
+ .word DMA2_Channel5_IRQHandler
+ .word ETH_IRQHandler
+ .word ETH_WKUP_IRQHandler
+ .word CAN2_TX_IRQHandler
+ .word CAN2_RX0_IRQHandler
+ .word CAN2_RX1_IRQHandler
+ .word CAN2_SCE_IRQHandler
+ .word OTG_FS_IRQHandler
+ .word 0
+ .word 0
+ .word 0
+ .word 0
+ .word 0
+ .word 0
+ .word 0
+ .word 0
+ .word 0
+ .word 0
+ .word 0
+ .word 0
+ .word 0
+ .word 0
+ .word 0
+ .word 0
+ .word 0
+ .word 0
+ .word 0
+ .word 0
+ .word 0
+ .word 0
+ .word 0
+ .word 0
+ .word 0
+ .word 0
+ .word 0
+ .word 0
+ .word 0
+ .word 0
+ .word 0
+ .word 0
+ .word 0
+ .word 0
+ .word 0
+ .word 0
+ .word BootRAM /* @0x1E0. This is for boot in RAM mode for
+ STM32F10x Connectivity line Devices. */
+
+/*******************************************************************************
+*
+* Provide weak aliases for each Exception handler to the Default_Handler.
+* As they are weak aliases, any function with the same name will override
+* this definition.
+*
+*******************************************************************************/
+ .weak NMI_Handler
+ .thumb_set NMI_Handler,Default_Handler
+
+ .weak HardFault_Handler
+ .thumb_set HardFault_Handler,Default_Handler
+
+ .weak MemManage_Handler
+ .thumb_set MemManage_Handler,Default_Handler
+
+ .weak BusFault_Handler
+ .thumb_set BusFault_Handler,Default_Handler
+
+ .weak UsageFault_Handler
+ .thumb_set UsageFault_Handler,Default_Handler
+
+ .weak SVC_Handler
+ .thumb_set SVC_Handler,Default_Handler
+
+ .weak DebugMon_Handler
+ .thumb_set DebugMon_Handler,Default_Handler
+
+ .weak PendSV_Handler
+ .thumb_set PendSV_Handler,Default_Handler
+
+ .weak SysTick_Handler
+ .thumb_set SysTick_Handler,Default_Handler
+
+ .weak WWDG_IRQHandler
+ .thumb_set WWDG_IRQHandler,Default_Handler
+
+ .weak PVD_IRQHandler
+ .thumb_set PVD_IRQHandler,Default_Handler
+
+ .weak TAMPER_IRQHandler
+ .thumb_set TAMPER_IRQHandler,Default_Handler
+
+ .weak RTC_IRQHandler
+ .thumb_set RTC_IRQHandler,Default_Handler
+
+ .weak FLASH_IRQHandler
+ .thumb_set FLASH_IRQHandler,Default_Handler
+
+ .weak RCC_IRQHandler
+ .thumb_set RCC_IRQHandler,Default_Handler
+
+ .weak EXTI0_IRQHandler
+ .thumb_set EXTI0_IRQHandler,Default_Handler
+
+ .weak EXTI1_IRQHandler
+ .thumb_set EXTI1_IRQHandler,Default_Handler
+
+ .weak EXTI2_IRQHandler
+ .thumb_set EXTI2_IRQHandler,Default_Handler
+
+ .weak EXTI3_IRQHandler
+ .thumb_set EXTI3_IRQHandler,Default_Handler
+
+ .weak EXTI4_IRQHandler
+ .thumb_set EXTI4_IRQHandler,Default_Handler
+
+ .weak DMA1_Channel1_IRQHandler
+ .thumb_set DMA1_Channel1_IRQHandler,Default_Handler
+
+ .weak DMA1_Channel2_IRQHandler
+ .thumb_set DMA1_Channel2_IRQHandler,Default_Handler
+
+ .weak DMA1_Channel3_IRQHandler
+ .thumb_set DMA1_Channel3_IRQHandler,Default_Handler
+
+ .weak DMA1_Channel4_IRQHandler
+ .thumb_set DMA1_Channel4_IRQHandler,Default_Handler
+
+ .weak DMA1_Channel5_IRQHandler
+ .thumb_set DMA1_Channel5_IRQHandler,Default_Handler
+
+ .weak DMA1_Channel6_IRQHandler
+ .thumb_set DMA1_Channel6_IRQHandler,Default_Handler
+
+ .weak DMA1_Channel7_IRQHandler
+ .thumb_set DMA1_Channel7_IRQHandler,Default_Handler
+
+ .weak ADC1_2_IRQHandler
+ .thumb_set ADC1_2_IRQHandler,Default_Handler
+
+ .weak CAN1_TX_IRQHandler
+ .thumb_set CAN1_TX_IRQHandler,Default_Handler
+
+ .weak CAN1_RX0_IRQHandler
+ .thumb_set CAN1_RX0_IRQHandler,Default_Handler
+
+ .weak CAN1_RX1_IRQHandler
+ .thumb_set CAN1_RX1_IRQHandler,Default_Handler
+
+ .weak CAN1_SCE_IRQHandler
+ .thumb_set CAN1_SCE_IRQHandler,Default_Handler
+
+ .weak EXTI9_5_IRQHandler
+ .thumb_set EXTI9_5_IRQHandler,Default_Handler
+
+ .weak TIM1_BRK_IRQHandler
+ .thumb_set TIM1_BRK_IRQHandler,Default_Handler
+
+ .weak TIM1_UP_IRQHandler
+ .thumb_set TIM1_UP_IRQHandler,Default_Handler
+
+ .weak TIM1_TRG_COM_IRQHandler
+ .thumb_set TIM1_TRG_COM_IRQHandler,Default_Handler
+
+ .weak TIM1_CC_IRQHandler
+ .thumb_set TIM1_CC_IRQHandler,Default_Handler
+
+ .weak TIM2_IRQHandler
+ .thumb_set TIM2_IRQHandler,Default_Handler
+
+ .weak TIM3_IRQHandler
+ .thumb_set TIM3_IRQHandler,Default_Handler
+
+ .weak TIM4_IRQHandler
+ .thumb_set TIM4_IRQHandler,Default_Handler
+
+ .weak I2C1_EV_IRQHandler
+ .thumb_set I2C1_EV_IRQHandler,Default_Handler
+
+ .weak I2C1_ER_IRQHandler
+ .thumb_set I2C1_ER_IRQHandler,Default_Handler
+
+ .weak I2C2_EV_IRQHandler
+ .thumb_set I2C2_EV_IRQHandler,Default_Handler
+
+ .weak I2C2_ER_IRQHandler
+ .thumb_set I2C2_ER_IRQHandler,Default_Handler
+
+ .weak SPI1_IRQHandler
+ .thumb_set SPI1_IRQHandler,Default_Handler
+
+ .weak SPI2_IRQHandler
+ .thumb_set SPI2_IRQHandler,Default_Handler
+
+ .weak USART1_IRQHandler
+ .thumb_set USART1_IRQHandler,Default_Handler
+
+ .weak USART2_IRQHandler
+ .thumb_set USART2_IRQHandler,Default_Handler
+
+ .weak USART3_IRQHandler
+ .thumb_set USART3_IRQHandler,Default_Handler
+
+ .weak EXTI15_10_IRQHandler
+ .thumb_set EXTI15_10_IRQHandler,Default_Handler
+
+ .weak RTCAlarm_IRQHandler
+ .thumb_set RTCAlarm_IRQHandler,Default_Handler
+
+ .weak OTG_FS_WKUP_IRQHandler
+ .thumb_set OTG_FS_WKUP_IRQHandler,Default_Handler
+
+ .weak TIM5_IRQHandler
+ .thumb_set TIM5_IRQHandler,Default_Handler
+
+ .weak SPI3_IRQHandler
+ .thumb_set SPI3_IRQHandler,Default_Handler
+
+ .weak UART4_IRQHandler
+ .thumb_set UART4_IRQHandler,Default_Handler
+
+ .weak UART5_IRQHandler
+ .thumb_set UART5_IRQHandler,Default_Handler
+
+ .weak TIM6_IRQHandler
+ .thumb_set TIM6_IRQHandler,Default_Handler
+
+ .weak TIM7_IRQHandler
+ .thumb_set TIM7_IRQHandler,Default_Handler
+
+ .weak DMA2_Channel1_IRQHandler
+ .thumb_set DMA2_Channel1_IRQHandler,Default_Handler
+
+ .weak DMA2_Channel2_IRQHandler
+ .thumb_set DMA2_Channel2_IRQHandler,Default_Handler
+
+ .weak DMA2_Channel3_IRQHandler
+ .thumb_set DMA2_Channel3_IRQHandler,Default_Handler
+
+ .weak DMA2_Channel4_IRQHandler
+ .thumb_set DMA2_Channel4_IRQHandler,Default_Handler
+
+ .weak DMA2_Channel5_IRQHandler
+ .thumb_set DMA2_Channel5_IRQHandler,Default_Handler
+
+ .weak ETH_IRQHandler
+ .thumb_set ETH_IRQHandler,Default_Handler
+
+ .weak ETH_WKUP_IRQHandler
+ .thumb_set ETH_WKUP_IRQHandler,Default_Handler
+
+ .weak CAN2_TX_IRQHandler
+ .thumb_set CAN2_TX_IRQHandler,Default_Handler
+
+ .weak CAN2_RX0_IRQHandler
+ .thumb_set CAN2_RX0_IRQHandler,Default_Handler
+
+ .weak CAN2_RX1_IRQHandler
+ .thumb_set CAN2_RX1_IRQHandler,Default_Handler
+
+ .weak CAN2_SCE_IRQHandler
+ .thumb_set CAN2_SCE_IRQHandler,Default_Handler
+
+ .weak OTG_FS_IRQHandler
+ .thumb_set OTG_FS_IRQHandler ,Default_Handler
+
+/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
diff --git a/Libraries/CMSIS/Device/ST/STM32F10x/Source/Templates/gcc_ride7/startup_stm32f10x_hd.s b/Libraries/CMSIS/Device/ST/STM32F10x/Source/Templates/gcc_ride7/startup_stm32f10x_hd.s
new file mode 100644
index 0000000..f312d2f
--- /dev/null
+++ b/Libraries/CMSIS/Device/ST/STM32F10x/Source/Templates/gcc_ride7/startup_stm32f10x_hd.s
@@ -0,0 +1,471 @@
+/**
+ ******************************************************************************
+ * @file startup_stm32f10x_hd.s
+ * @author MCD Application Team
+ * @version V3.6.1
+ * @date 09-March-2012
+ * @brief STM32F10x High Density Devices vector table for RIDE7 toolchain.
+ * This module performs:
+ * - Set the initial SP
+ * - Set the initial PC == Reset_Handler,
+ * - Set the vector table entries with the exceptions ISR address
+ * - Configure the clock system and the external SRAM mounted on
+ * STM3210E-EVAL board to be used as data memory (optional,
+ * to be enabled by user)
+ * - Branches to main in the C library (which eventually
+ * calls main()).
+ * After Reset the Cortex-M3 processor is in Thread mode,
+ * priority is Privileged, and the Stack is set to Main.
+ ******************************************************************************
+ * @attention
+ *
+ * © COPYRIGHT 2012 STMicroelectronics
+ *
+ * Licensed under MCD-ST Liberty SW License Agreement V2, (the "License");
+ * You may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at:
+ *
+ * http://www.st.com/software_license_agreement_liberty_v2
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ *
+ ******************************************************************************
+ */
+
+ .syntax unified
+ .cpu cortex-m3
+ .fpu softvfp
+ .thumb
+
+.global g_pfnVectors
+.global Default_Handler
+
+/* start address for the initialization values of the .data section.
+defined in linker script */
+.word _sidata
+/* start address for the .data section. defined in linker script */
+.word _sdata
+/* end address for the .data section. defined in linker script */
+.word _edata
+/* start address for the .bss section. defined in linker script */
+.word _sbss
+/* end address for the .bss section. defined in linker script */
+.word _ebss
+/* stack used for SystemInit_ExtMemCtl; always internal RAM used */
+
+.equ BootRAM, 0xF1E0F85F
+/**
+ * @brief This is the code that gets called when the processor first
+ * starts execution following a reset event. Only the absolutely
+ * necessary set is performed, after which the application
+ * supplied main() routine is called.
+ * @param None
+ * @retval : None
+*/
+
+ .section .text.Reset_Handler
+ .weak Reset_Handler
+ .type Reset_Handler, %function
+Reset_Handler:
+
+/* Copy the data segment initializers from flash to SRAM */
+ movs r1, #0
+ b LoopCopyDataInit
+
+CopyDataInit:
+ ldr r3, =_sidata
+ ldr r3, [r3, r1]
+ str r3, [r0, r1]
+ adds r1, r1, #4
+
+LoopCopyDataInit:
+ ldr r0, =_sdata
+ ldr r3, =_edata
+ adds r2, r0, r1
+ cmp r2, r3
+ bcc CopyDataInit
+ ldr r2, =_sbss
+ b LoopFillZerobss
+/* Zero fill the bss segment. */
+FillZerobss:
+ movs r3, #0
+ str r3, [r2], #4
+
+LoopFillZerobss:
+ ldr r3, = _ebss
+ cmp r2, r3
+ bcc FillZerobss
+/* Call the clock system intitialization function.*/
+ bl SystemInit
+/* Call the application's entry point.*/
+ bl main
+ bx lr
+.size Reset_Handler, .-Reset_Handler
+
+/**
+ * @brief This is the code that gets called when the processor receives an
+ * unexpected interrupt. This simply enters an infinite loop, preserving
+ * the system state for examination by a debugger.
+ * @param None
+ * @retval None
+*/
+ .section .text.Default_Handler,"ax",%progbits
+Default_Handler:
+Infinite_Loop:
+ b Infinite_Loop
+ .size Default_Handler, .-Default_Handler
+/******************************************************************************
+*
+* The minimal vector table for a Cortex M3. Note that the proper constructs
+* must be placed on this to ensure that it ends up at physical address
+* 0x0000.0000.
+*
+*******************************************************************************/
+ .section .isr_vector,"a",%progbits
+ .type g_pfnVectors, %object
+ .size g_pfnVectors, .-g_pfnVectors
+
+
+g_pfnVectors:
+ .word _estack
+ .word Reset_Handler
+ .word NMI_Handler
+ .word HardFault_Handler
+ .word MemManage_Handler
+ .word BusFault_Handler
+ .word UsageFault_Handler
+ .word 0
+ .word 0
+ .word 0
+ .word 0
+ .word SVC_Handler
+ .word DebugMon_Handler
+ .word 0
+ .word PendSV_Handler
+ .word SysTick_Handler
+ .word WWDG_IRQHandler
+ .word PVD_IRQHandler
+ .word TAMPER_IRQHandler
+ .word RTC_IRQHandler
+ .word FLASH_IRQHandler
+ .word RCC_IRQHandler
+ .word EXTI0_IRQHandler
+ .word EXTI1_IRQHandler
+ .word EXTI2_IRQHandler
+ .word EXTI3_IRQHandler
+ .word EXTI4_IRQHandler
+ .word DMA1_Channel1_IRQHandler
+ .word DMA1_Channel2_IRQHandler
+ .word DMA1_Channel3_IRQHandler
+ .word DMA1_Channel4_IRQHandler
+ .word DMA1_Channel5_IRQHandler
+ .word DMA1_Channel6_IRQHandler
+ .word DMA1_Channel7_IRQHandler
+ .word ADC1_2_IRQHandler
+ .word USB_HP_CAN1_TX_IRQHandler
+ .word USB_LP_CAN1_RX0_IRQHandler
+ .word CAN1_RX1_IRQHandler
+ .word CAN1_SCE_IRQHandler
+ .word EXTI9_5_IRQHandler
+ .word TIM1_BRK_IRQHandler
+ .word TIM1_UP_IRQHandler
+ .word TIM1_TRG_COM_IRQHandler
+ .word TIM1_CC_IRQHandler
+ .word TIM2_IRQHandler
+ .word TIM3_IRQHandler
+ .word TIM4_IRQHandler
+ .word I2C1_EV_IRQHandler
+ .word I2C1_ER_IRQHandler
+ .word I2C2_EV_IRQHandler
+ .word I2C2_ER_IRQHandler
+ .word SPI1_IRQHandler
+ .word SPI2_IRQHandler
+ .word USART1_IRQHandler
+ .word USART2_IRQHandler
+ .word USART3_IRQHandler
+ .word EXTI15_10_IRQHandler
+ .word RTCAlarm_IRQHandler
+ .word USBWakeUp_IRQHandler
+ .word TIM8_BRK_IRQHandler
+ .word TIM8_UP_IRQHandler
+ .word TIM8_TRG_COM_IRQHandler
+ .word TIM8_CC_IRQHandler
+ .word ADC3_IRQHandler
+ .word FSMC_IRQHandler
+ .word SDIO_IRQHandler
+ .word TIM5_IRQHandler
+ .word SPI3_IRQHandler
+ .word UART4_IRQHandler
+ .word UART5_IRQHandler
+ .word TIM6_IRQHandler
+ .word TIM7_IRQHandler
+ .word DMA2_Channel1_IRQHandler
+ .word DMA2_Channel2_IRQHandler
+ .word DMA2_Channel3_IRQHandler
+ .word DMA2_Channel4_5_IRQHandler
+ .word 0
+ .word 0
+ .word 0
+ .word 0
+ .word 0
+ .word 0
+ .word 0
+ .word 0
+ .word 0
+ .word 0
+ .word 0
+ .word 0
+ .word 0
+ .word 0
+ .word 0
+ .word 0
+ .word 0
+ .word 0
+ .word 0
+ .word 0
+ .word 0
+ .word 0
+ .word 0
+ .word 0
+ .word 0
+ .word 0
+ .word 0
+ .word 0
+ .word 0
+ .word 0
+ .word 0
+ .word 0
+ .word 0
+ .word 0
+ .word 0
+ .word 0
+ .word 0
+ .word 0
+ .word 0
+ .word 0
+ .word 0
+ .word 0
+ .word 0
+ .word 0
+ .word BootRAM /* @0x1E0. This is for boot in RAM mode for
+ STM32F10x High Density devices. */
+/*******************************************************************************
+*
+* Provide weak aliases for each Exception handler to the Default_Handler.
+* As they are weak aliases, any function with the same name will override
+* this definition.
+*
+*******************************************************************************/
+
+ .weak NMI_Handler
+ .thumb_set NMI_Handler,Default_Handler
+
+ .weak HardFault_Handler
+ .thumb_set HardFault_Handler,Default_Handler
+
+ .weak MemManage_Handler
+ .thumb_set MemManage_Handler,Default_Handler
+
+ .weak BusFault_Handler
+ .thumb_set BusFault_Handler,Default_Handler
+
+ .weak UsageFault_Handler
+ .thumb_set UsageFault_Handler,Default_Handler
+
+ .weak SVC_Handler
+ .thumb_set SVC_Handler,Default_Handler
+
+ .weak DebugMon_Handler
+ .thumb_set DebugMon_Handler,Default_Handler
+
+ .weak PendSV_Handler
+ .thumb_set PendSV_Handler,Default_Handler
+
+ .weak SysTick_Handler
+ .thumb_set SysTick_Handler,Default_Handler
+
+ .weak WWDG_IRQHandler
+ .thumb_set WWDG_IRQHandler,Default_Handler
+
+ .weak PVD_IRQHandler
+ .thumb_set PVD_IRQHandler,Default_Handler
+
+ .weak TAMPER_IRQHandler
+ .thumb_set TAMPER_IRQHandler,Default_Handler
+
+ .weak RTC_IRQHandler
+ .thumb_set RTC_IRQHandler,Default_Handler
+
+ .weak FLASH_IRQHandler
+ .thumb_set FLASH_IRQHandler,Default_Handler
+
+ .weak RCC_IRQHandler
+ .thumb_set RCC_IRQHandler,Default_Handler
+
+ .weak EXTI0_IRQHandler
+ .thumb_set EXTI0_IRQHandler,Default_Handler
+
+ .weak EXTI1_IRQHandler
+ .thumb_set EXTI1_IRQHandler,Default_Handler
+
+ .weak EXTI2_IRQHandler
+ .thumb_set EXTI2_IRQHandler,Default_Handler
+
+ .weak EXTI3_IRQHandler
+ .thumb_set EXTI3_IRQHandler,Default_Handler
+
+ .weak EXTI4_IRQHandler
+ .thumb_set EXTI4_IRQHandler,Default_Handler
+
+ .weak DMA1_Channel1_IRQHandler
+ .thumb_set DMA1_Channel1_IRQHandler,Default_Handler
+
+ .weak DMA1_Channel2_IRQHandler
+ .thumb_set DMA1_Channel2_IRQHandler,Default_Handler
+
+ .weak DMA1_Channel3_IRQHandler
+ .thumb_set DMA1_Channel3_IRQHandler,Default_Handler
+
+ .weak DMA1_Channel4_IRQHandler
+ .thumb_set DMA1_Channel4_IRQHandler,Default_Handler
+
+ .weak DMA1_Channel5_IRQHandler
+ .thumb_set DMA1_Channel5_IRQHandler,Default_Handler
+
+ .weak DMA1_Channel6_IRQHandler
+ .thumb_set DMA1_Channel6_IRQHandler,Default_Handler
+
+ .weak DMA1_Channel7_IRQHandler
+ .thumb_set DMA1_Channel7_IRQHandler,Default_Handler
+
+ .weak ADC1_2_IRQHandler
+ .thumb_set ADC1_2_IRQHandler,Default_Handler
+
+ .weak USB_HP_CAN1_TX_IRQHandler
+ .thumb_set USB_HP_CAN1_TX_IRQHandler,Default_Handler
+
+ .weak USB_LP_CAN1_RX0_IRQHandler
+ .thumb_set USB_LP_CAN1_RX0_IRQHandler,Default_Handler
+
+ .weak CAN1_RX1_IRQHandler
+ .thumb_set CAN1_RX1_IRQHandler,Default_Handler
+
+ .weak CAN1_SCE_IRQHandler
+ .thumb_set CAN1_SCE_IRQHandler,Default_Handler
+
+ .weak EXTI9_5_IRQHandler
+ .thumb_set EXTI9_5_IRQHandler,Default_Handler
+
+ .weak TIM1_BRK_IRQHandler
+ .thumb_set TIM1_BRK_IRQHandler,Default_Handler
+
+ .weak TIM1_UP_IRQHandler
+ .thumb_set TIM1_UP_IRQHandler,Default_Handler
+
+ .weak TIM1_TRG_COM_IRQHandler
+ .thumb_set TIM1_TRG_COM_IRQHandler,Default_Handler
+
+ .weak TIM1_CC_IRQHandler
+ .thumb_set TIM1_CC_IRQHandler,Default_Handler
+
+ .weak TIM2_IRQHandler
+ .thumb_set TIM2_IRQHandler,Default_Handler
+
+ .weak TIM3_IRQHandler
+ .thumb_set TIM3_IRQHandler,Default_Handler
+
+ .weak TIM4_IRQHandler
+ .thumb_set TIM4_IRQHandler,Default_Handler
+
+ .weak I2C1_EV_IRQHandler
+ .thumb_set I2C1_EV_IRQHandler,Default_Handler
+
+ .weak I2C1_ER_IRQHandler
+ .thumb_set I2C1_ER_IRQHandler,Default_Handler
+
+ .weak I2C2_EV_IRQHandler
+ .thumb_set I2C2_EV_IRQHandler,Default_Handler
+
+ .weak I2C2_ER_IRQHandler
+ .thumb_set I2C2_ER_IRQHandler,Default_Handler
+
+ .weak SPI1_IRQHandler
+ .thumb_set SPI1_IRQHandler,Default_Handler
+
+ .weak SPI2_IRQHandler
+ .thumb_set SPI2_IRQHandler,Default_Handler
+
+ .weak USART1_IRQHandler
+ .thumb_set USART1_IRQHandler,Default_Handler
+
+ .weak USART2_IRQHandler
+ .thumb_set USART2_IRQHandler,Default_Handler
+
+ .weak USART3_IRQHandler
+ .thumb_set USART3_IRQHandler,Default_Handler
+
+ .weak EXTI15_10_IRQHandler
+ .thumb_set EXTI15_10_IRQHandler,Default_Handler
+
+ .weak RTCAlarm_IRQHandler
+ .thumb_set RTCAlarm_IRQHandler,Default_Handler
+
+ .weak USBWakeUp_IRQHandler
+ .thumb_set USBWakeUp_IRQHandler,Default_Handler
+
+ .weak TIM8_BRK_IRQHandler
+ .thumb_set TIM8_BRK_IRQHandler,Default_Handler
+
+ .weak TIM8_UP_IRQHandler
+ .thumb_set TIM8_UP_IRQHandler,Default_Handler
+
+ .weak TIM8_TRG_COM_IRQHandler
+ .thumb_set TIM8_TRG_COM_IRQHandler,Default_Handler
+
+ .weak TIM8_CC_IRQHandler
+ .thumb_set TIM8_CC_IRQHandler,Default_Handler
+
+ .weak ADC3_IRQHandler
+ .thumb_set ADC3_IRQHandler,Default_Handler
+
+ .weak FSMC_IRQHandler
+ .thumb_set FSMC_IRQHandler,Default_Handler
+
+ .weak SDIO_IRQHandler
+ .thumb_set SDIO_IRQHandler,Default_Handler
+
+ .weak TIM5_IRQHandler
+ .thumb_set TIM5_IRQHandler,Default_Handler
+
+ .weak SPI3_IRQHandler
+ .thumb_set SPI3_IRQHandler,Default_Handler
+
+ .weak UART4_IRQHandler
+ .thumb_set UART4_IRQHandler,Default_Handler
+
+ .weak UART5_IRQHandler
+ .thumb_set UART5_IRQHandler,Default_Handler
+
+ .weak TIM6_IRQHandler
+ .thumb_set TIM6_IRQHandler,Default_Handler
+
+ .weak TIM7_IRQHandler
+ .thumb_set TIM7_IRQHandler,Default_Handler
+
+ .weak DMA2_Channel1_IRQHandler
+ .thumb_set DMA2_Channel1_IRQHandler,Default_Handler
+
+ .weak DMA2_Channel2_IRQHandler
+ .thumb_set DMA2_Channel2_IRQHandler,Default_Handler
+
+ .weak DMA2_Channel3_IRQHandler
+ .thumb_set DMA2_Channel3_IRQHandler,Default_Handler
+
+ .weak DMA2_Channel4_5_IRQHandler
+ .thumb_set DMA2_Channel4_5_IRQHandler,Default_Handler
+
+/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
diff --git a/Libraries/CMSIS/Device/ST/STM32F10x/Source/Templates/gcc_ride7/startup_stm32f10x_hd_vl.s b/Libraries/CMSIS/Device/ST/STM32F10x/Source/Templates/gcc_ride7/startup_stm32f10x_hd_vl.s
new file mode 100644
index 0000000..d226209
--- /dev/null
+++ b/Libraries/CMSIS/Device/ST/STM32F10x/Source/Templates/gcc_ride7/startup_stm32f10x_hd_vl.s
@@ -0,0 +1,448 @@
+/**
+ ******************************************************************************
+ * @file startup_stm32f10x_hd_vl.s
+ * @author MCD Application Team
+ * @version V3.6.1
+ * @date 09-March-2012
+ * @brief STM32F10x High Density Value Line Devices vector table for RIDE7
+ * toolchain.
+ * This module performs:
+ * - Set the initial SP
+ * - Set the initial PC == Reset_Handler,
+ * - Set the vector table entries with the exceptions ISR address
+ * - Configure the clock system and the external SRAM mounted on
+ * STM32100E-EVAL board to be used as data memory (optional,
+ * to be enabled by user)
+ * - Branches to main in the C library (which eventually
+ * calls main()).
+ * After Reset the Cortex-M3 processor is in Thread mode,
+ * priority is Privileged, and the Stack is set to Main.
+ ******************************************************************************
+ * @attention
+ *
+ * © COPYRIGHT 2012 STMicroelectronics
+ *
+ * Licensed under MCD-ST Liberty SW License Agreement V2, (the "License");
+ * You may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at:
+ *
+ * http://www.st.com/software_license_agreement_liberty_v2
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ *
+ ******************************************************************************
+ */
+
+ .syntax unified
+ .cpu cortex-m3
+ .fpu softvfp
+ .thumb
+
+.global g_pfnVectors
+.global Default_Handler
+
+/* start address for the initialization values of the .data section.
+defined in linker script */
+.word _sidata
+/* start address for the .data section. defined in linker script */
+.word _sdata
+/* end address for the .data section. defined in linker script */
+.word _edata
+/* start address for the .bss section. defined in linker script */
+.word _sbss
+/* end address for the .bss section. defined in linker script */
+.word _ebss
+
+.equ BootRAM, 0xF108F85F
+/**
+ * @brief This is the code that gets called when the processor first
+ * starts execution following a reset event. Only the absolutely
+ * necessary set is performed, after which the application
+ * supplied main() routine is called.
+ * @param None
+ * @retval None
+*/
+
+ .section .text.Reset_Handler
+ .weak Reset_Handler
+ .type Reset_Handler, %function
+Reset_Handler:
+
+/* Copy the data segment initializers from flash to SRAM */
+ movs r1, #0
+ b LoopCopyDataInit
+
+CopyDataInit:
+ ldr r3, =_sidata
+ ldr r3, [r3, r1]
+ str r3, [r0, r1]
+ adds r1, r1, #4
+
+LoopCopyDataInit:
+ ldr r0, =_sdata
+ ldr r3, =_edata
+ adds r2, r0, r1
+ cmp r2, r3
+ bcc CopyDataInit
+ ldr r2, =_sbss
+ b LoopFillZerobss
+/* Zero fill the bss segment. */
+FillZerobss:
+ movs r3, #0
+ str r3, [r2], #4
+
+LoopFillZerobss:
+ ldr r3, = _ebss
+ cmp r2, r3
+ bcc FillZerobss
+/* Call the clock system intitialization function.*/
+ bl SystemInit
+/* Call the application's entry point.*/
+ bl main
+ bx lr
+.size Reset_Handler, .-Reset_Handler
+
+/**
+ * @brief This is the code that gets called when the processor receives an
+ * unexpected interrupt. This simply enters an infinite loop, preserving
+ * the system state for examination by a debugger.
+ * @param None
+ * @retval None
+*/
+ .section .text.Default_Handler,"ax",%progbits
+Default_Handler:
+Infinite_Loop:
+ b Infinite_Loop
+ .size Default_Handler, .-Default_Handler
+/******************************************************************************
+*
+* The minimal vector table for a Cortex M3. Note that the proper constructs
+* must be placed on this to ensure that it ends up at physical address
+* 0x0000.0000.
+*
+******************************************************************************/
+ .section .isr_vector,"a",%progbits
+ .type g_pfnVectors, %object
+ .size g_pfnVectors, .-g_pfnVectors
+
+g_pfnVectors:
+ .word _estack
+ .word Reset_Handler
+ .word NMI_Handler
+ .word HardFault_Handler
+ .word MemManage_Handler
+ .word BusFault_Handler
+ .word UsageFault_Handler
+ .word 0
+ .word 0
+ .word 0
+ .word 0
+ .word SVC_Handler
+ .word DebugMon_Handler
+ .word 0
+ .word PendSV_Handler
+ .word SysTick_Handler
+ .word WWDG_IRQHandler
+ .word PVD_IRQHandler
+ .word TAMPER_IRQHandler
+ .word RTC_IRQHandler
+ .word FLASH_IRQHandler
+ .word RCC_IRQHandler
+ .word EXTI0_IRQHandler
+ .word EXTI1_IRQHandler
+ .word EXTI2_IRQHandler
+ .word EXTI3_IRQHandler
+ .word EXTI4_IRQHandler
+ .word DMA1_Channel1_IRQHandler
+ .word DMA1_Channel2_IRQHandler
+ .word DMA1_Channel3_IRQHandler
+ .word DMA1_Channel4_IRQHandler
+ .word DMA1_Channel5_IRQHandler
+ .word DMA1_Channel6_IRQHandler
+ .word DMA1_Channel7_IRQHandler
+ .word ADC1_IRQHandler
+ .word 0
+ .word 0
+ .word 0
+ .word 0
+ .word EXTI9_5_IRQHandler
+ .word TIM1_BRK_TIM15_IRQHandler
+ .word TIM1_UP_TIM16_IRQHandler
+ .word TIM1_TRG_COM_TIM17_IRQHandler
+ .word TIM1_CC_IRQHandler
+ .word TIM2_IRQHandler
+ .word TIM3_IRQHandler
+ .word TIM4_IRQHandler
+ .word I2C1_EV_IRQHandler
+ .word I2C1_ER_IRQHandler
+ .word I2C2_EV_IRQHandler
+ .word I2C2_ER_IRQHandler
+ .word SPI1_IRQHandler
+ .word SPI2_IRQHandler
+ .word USART1_IRQHandler
+ .word USART2_IRQHandler
+ .word USART3_IRQHandler
+ .word EXTI15_10_IRQHandler
+ .word RTCAlarm_IRQHandler
+ .word CEC_IRQHandler
+ .word TIM12_IRQHandler
+ .word TIM13_IRQHandler
+ .word TIM14_IRQHandler
+ .word 0
+ .word 0
+ .word 0
+ .word 0
+ .word TIM5_IRQHandler
+ .word SPI3_IRQHandler
+ .word UART4_IRQHandler
+ .word UART5_IRQHandler
+ .word TIM6_DAC_IRQHandler
+ .word TIM7_IRQHandler
+ .word DMA2_Channel1_IRQHandler
+ .word DMA2_Channel2_IRQHandler
+ .word DMA2_Channel3_IRQHandler
+ .word DMA2_Channel4_5_IRQHandler
+ .word DMA2_Channel5_IRQHandler
+ .word 0
+ .word 0
+ .word 0
+ .word 0
+ .word 0
+ .word 0
+ .word 0
+ .word 0
+ .word 0
+ .word 0
+ .word 0
+ .word 0
+ .word 0
+ .word 0
+ .word 0
+ .word 0
+ .word 0
+ .word 0
+ .word 0
+ .word 0
+ .word 0
+ .word 0
+ .word 0
+ .word 0
+ .word 0
+ .word 0
+ .word 0
+ .word 0
+ .word 0
+ .word 0
+ .word 0
+ .word 0
+ .word 0
+ .word 0
+ .word 0
+ .word 0
+ .word 0
+ .word 0
+ .word 0
+ .word 0
+ .word 0
+ .word 0
+ .word 0
+ .word BootRAM /* @0x1E0. This is for boot in RAM mode for
+ STM32F10x High Density Value line devices. */
+
+/*******************************************************************************
+* Provide weak aliases for each Exception handler to the Default_Handler.
+* As they are weak aliases, any function with the same name will override
+* this definition.
+*******************************************************************************/
+
+ .weak NMI_Handler
+ .thumb_set NMI_Handler,Default_Handler
+
+ .weak HardFault_Handler
+ .thumb_set HardFault_Handler,Default_Handler
+
+ .weak MemManage_Handler
+ .thumb_set MemManage_Handler,Default_Handler
+
+ .weak BusFault_Handler
+ .thumb_set BusFault_Handler,Default_Handler
+
+ .weak UsageFault_Handler
+ .thumb_set UsageFault_Handler,Default_Handler
+
+ .weak SVC_Handler
+ .thumb_set SVC_Handler,Default_Handler
+
+ .weak DebugMon_Handler
+ .thumb_set DebugMon_Handler,Default_Handler
+
+ .weak PendSV_Handler
+ .thumb_set PendSV_Handler,Default_Handler
+
+ .weak SysTick_Handler
+ .thumb_set SysTick_Handler,Default_Handler
+
+ .weak WWDG_IRQHandler
+ .thumb_set WWDG_IRQHandler,Default_Handler
+
+ .weak PVD_IRQHandler
+ .thumb_set PVD_IRQHandler,Default_Handler
+
+ .weak TAMPER_IRQHandler
+ .thumb_set TAMPER_IRQHandler,Default_Handler
+
+ .weak RTC_IRQHandler
+ .thumb_set RTC_IRQHandler,Default_Handler
+
+ .weak FLASH_IRQHandler
+ .thumb_set FLASH_IRQHandler,Default_Handler
+
+ .weak RCC_IRQHandler
+ .thumb_set RCC_IRQHandler,Default_Handler
+
+ .weak EXTI0_IRQHandler
+ .thumb_set EXTI0_IRQHandler,Default_Handler
+
+ .weak EXTI1_IRQHandler
+ .thumb_set EXTI1_IRQHandler,Default_Handler
+
+ .weak EXTI2_IRQHandler
+ .thumb_set EXTI2_IRQHandler,Default_Handler
+
+ .weak EXTI3_IRQHandler
+ .thumb_set EXTI3_IRQHandler,Default_Handler
+
+ .weak EXTI4_IRQHandler
+ .thumb_set EXTI4_IRQHandler,Default_Handler
+
+ .weak DMA1_Channel1_IRQHandler
+ .thumb_set DMA1_Channel1_IRQHandler,Default_Handler
+
+ .weak DMA1_Channel2_IRQHandler
+ .thumb_set DMA1_Channel2_IRQHandler,Default_Handler
+
+ .weak DMA1_Channel3_IRQHandler
+ .thumb_set DMA1_Channel3_IRQHandler,Default_Handler
+
+ .weak DMA1_Channel4_IRQHandler
+ .thumb_set DMA1_Channel4_IRQHandler,Default_Handler
+
+ .weak DMA1_Channel5_IRQHandler
+ .thumb_set DMA1_Channel5_IRQHandler,Default_Handler
+
+ .weak DMA1_Channel6_IRQHandler
+ .thumb_set DMA1_Channel6_IRQHandler,Default_Handler
+
+ .weak DMA1_Channel7_IRQHandler
+ .thumb_set DMA1_Channel7_IRQHandler,Default_Handler
+
+ .weak ADC1_IRQHandler
+ .thumb_set ADC1_IRQHandler,Default_Handler
+
+ .weak EXTI9_5_IRQHandler
+ .thumb_set EXTI9_5_IRQHandler,Default_Handler
+
+ .weak TIM1_BRK_TIM15_IRQHandler
+ .thumb_set TIM1_BRK_TIM15_IRQHandler,Default_Handler
+
+ .weak TIM1_UP_TIM16_IRQHandler
+ .thumb_set TIM1_UP_TIM16_IRQHandler,Default_Handler
+
+ .weak TIM1_TRG_COM_TIM17_IRQHandler
+ .thumb_set TIM1_TRG_COM_TIM17_IRQHandler,Default_Handler
+
+ .weak TIM1_CC_IRQHandler
+ .thumb_set TIM1_CC_IRQHandler,Default_Handler
+
+ .weak TIM2_IRQHandler
+ .thumb_set TIM2_IRQHandler,Default_Handler
+
+ .weak TIM3_IRQHandler
+ .thumb_set TIM3_IRQHandler,Default_Handler
+
+ .weak TIM4_IRQHandler
+ .thumb_set TIM4_IRQHandler,Default_Handler
+
+ .weak I2C1_EV_IRQHandler
+ .thumb_set I2C1_EV_IRQHandler,Default_Handler
+
+ .weak I2C1_ER_IRQHandler
+ .thumb_set I2C1_ER_IRQHandler,Default_Handler
+
+ .weak I2C2_EV_IRQHandler
+ .thumb_set I2C2_EV_IRQHandler,Default_Handler
+
+ .weak I2C2_ER_IRQHandler
+ .thumb_set I2C2_ER_IRQHandler,Default_Handler
+
+ .weak SPI1_IRQHandler
+ .thumb_set SPI1_IRQHandler,Default_Handler
+
+ .weak SPI2_IRQHandler
+ .thumb_set SPI2_IRQHandler,Default_Handler
+
+ .weak USART1_IRQHandler
+ .thumb_set USART1_IRQHandler,Default_Handler
+
+ .weak USART2_IRQHandler
+ .thumb_set USART2_IRQHandler,Default_Handler
+
+ .weak USART3_IRQHandler
+ .thumb_set USART3_IRQHandler,Default_Handler
+
+ .weak EXTI15_10_IRQHandler
+ .thumb_set EXTI15_10_IRQHandler,Default_Handler
+
+ .weak RTCAlarm_IRQHandler
+ .thumb_set RTCAlarm_IRQHandler,Default_Handler
+
+ .weak CEC_IRQHandler
+ .thumb_set CEC_IRQHandler,Default_Handler
+
+ .weak TIM12_IRQHandler
+ .thumb_set TIM12_IRQHandler,Default_Handler
+
+ .weak TIM13_IRQHandler
+ .thumb_set TIM13_IRQHandler,Default_Handler
+
+ .weak TIM14_IRQHandler
+ .thumb_set TIM14_IRQHandler,Default_Handler
+
+ .weak TIM5_IRQHandler
+ .thumb_set TIM5_IRQHandler,Default_Handler
+
+ .weak SPI3_IRQHandler
+ .thumb_set SPI3_IRQHandler,Default_Handler
+
+ .weak UART4_IRQHandler
+ .thumb_set UART4_IRQHandler,Default_Handler
+
+ .weak UART5_IRQHandler
+ .thumb_set UART5_IRQHandler,Default_Handler
+
+ .weak TIM6_DAC_IRQHandler
+ .thumb_set TIM6_DAC_IRQHandler,Default_Handler
+
+ .weak TIM7_IRQHandler
+ .thumb_set TIM7_IRQHandler,Default_Handler
+
+ .weak DMA2_Channel1_IRQHandler
+ .thumb_set DMA2_Channel1_IRQHandler,Default_Handler
+
+ .weak DMA2_Channel2_IRQHandler
+ .thumb_set DMA2_Channel2_IRQHandler,Default_Handler
+
+ .weak DMA2_Channel3_IRQHandler
+ .thumb_set DMA2_Channel3_IRQHandler,Default_Handler
+
+ .weak DMA2_Channel4_5_IRQHandler
+ .thumb_set DMA2_Channel4_5_IRQHandler,Default_Handler
+
+ .weak DMA2_Channel5_IRQHandler
+ .thumb_set DMA2_Channel5_IRQHandler,Default_Handler
+
+/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
diff --git a/Libraries/CMSIS/Device/ST/STM32F10x/Source/Templates/gcc_ride7/startup_stm32f10x_ld.s b/Libraries/CMSIS/Device/ST/STM32F10x/Source/Templates/gcc_ride7/startup_stm32f10x_ld.s
new file mode 100644
index 0000000..e370a4c
--- /dev/null
+++ b/Libraries/CMSIS/Device/ST/STM32F10x/Source/Templates/gcc_ride7/startup_stm32f10x_ld.s
@@ -0,0 +1,349 @@
+/**
+ ******************************************************************************
+ * @file startup_stm32f10x_ld.s
+ * @author MCD Application Team
+ * @version V3.6.1
+ * @date 09-March-2012
+ * @brief STM32F10x Low Density Devices vector table for RIDE7 toolchain.
+ * This module performs:
+ * - Set the initial SP
+ * - Set the initial PC == Reset_Handler,
+ * - Set the vector table entries with the exceptions ISR address
+ * - Configure the clock system
+ * - Branches to main in the C library (which eventually
+ * calls main()).
+ * After Reset the Cortex-M3 processor is in Thread mode,
+ * priority is Privileged, and the Stack is set to Main.
+ ******************************************************************************
+ * @attention
+ *
+ * © COPYRIGHT 2012 STMicroelectronics
+ *
+ * Licensed under MCD-ST Liberty SW License Agreement V2, (the "License");
+ * You may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at:
+ *
+ * http://www.st.com/software_license_agreement_liberty_v2
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ *
+ ******************************************************************************
+ */
+
+ .syntax unified
+ .cpu cortex-m3
+ .fpu softvfp
+ .thumb
+
+.global g_pfnVectors
+.global Default_Handler
+
+/* start address for the initialization values of the .data section.
+defined in linker script */
+.word _sidata
+/* start address for the .data section. defined in linker script */
+.word _sdata
+/* end address for the .data section. defined in linker script */
+.word _edata
+/* start address for the .bss section. defined in linker script */
+.word _sbss
+/* end address for the .bss section. defined in linker script */
+.word _ebss
+
+.equ BootRAM, 0xF108F85F
+/**
+ * @brief This is the code that gets called when the processor first
+ * starts execution following a reset event. Only the absolutely
+ * necessary set is performed, after which the application
+ * supplied main() routine is called.
+ * @param None
+ * @retval : None
+*/
+
+ .section .text.Reset_Handler
+ .weak Reset_Handler
+ .type Reset_Handler, %function
+Reset_Handler:
+
+/* Copy the data segment initializers from flash to SRAM */
+ movs r1, #0
+ b LoopCopyDataInit
+
+CopyDataInit:
+ ldr r3, =_sidata
+ ldr r3, [r3, r1]
+ str r3, [r0, r1]
+ adds r1, r1, #4
+
+LoopCopyDataInit:
+ ldr r0, =_sdata
+ ldr r3, =_edata
+ adds r2, r0, r1
+ cmp r2, r3
+ bcc CopyDataInit
+ ldr r2, =_sbss
+ b LoopFillZerobss
+/* Zero fill the bss segment. */
+FillZerobss:
+ movs r3, #0
+ str r3, [r2], #4
+
+LoopFillZerobss:
+ ldr r3, = _ebss
+ cmp r2, r3
+ bcc FillZerobss
+/* Call the clock system intitialization function.*/
+ bl SystemInit
+/* Call the application's entry point.*/
+ bl main
+ bx lr
+.size Reset_Handler, .-Reset_Handler
+
+/**
+ * @brief This is the code that gets called when the processor receives an
+ * unexpected interrupt. This simply enters an infinite loop, preserving
+ * the system state for examination by a debugger.
+ * @param None
+ * @retval None
+*/
+ .section .text.Default_Handler,"ax",%progbits
+Default_Handler:
+Infinite_Loop:
+ b Infinite_Loop
+ .size Default_Handler, .-Default_Handler
+/******************************************************************************
+*
+* The minimal vector table for a Cortex M3. Note that the proper constructs
+* must be placed on this to ensure that it ends up at physical address
+* 0x0000.0000.
+*
+******************************************************************************/
+ .section .isr_vector,"a",%progbits
+ .type g_pfnVectors, %object
+ .size g_pfnVectors, .-g_pfnVectors
+
+
+g_pfnVectors:
+ .word _estack
+ .word Reset_Handler
+ .word NMI_Handler
+ .word HardFault_Handler
+ .word MemManage_Handler
+ .word BusFault_Handler
+ .word UsageFault_Handler
+ .word 0
+ .word 0
+ .word 0
+ .word 0
+ .word SVC_Handler
+ .word DebugMon_Handler
+ .word 0
+ .word PendSV_Handler
+ .word SysTick_Handler
+ .word WWDG_IRQHandler
+ .word PVD_IRQHandler
+ .word TAMPER_IRQHandler
+ .word RTC_IRQHandler
+ .word FLASH_IRQHandler
+ .word RCC_IRQHandler
+ .word EXTI0_IRQHandler
+ .word EXTI1_IRQHandler
+ .word EXTI2_IRQHandler
+ .word EXTI3_IRQHandler
+ .word EXTI4_IRQHandler
+ .word DMA1_Channel1_IRQHandler
+ .word DMA1_Channel2_IRQHandler
+ .word DMA1_Channel3_IRQHandler
+ .word DMA1_Channel4_IRQHandler
+ .word DMA1_Channel5_IRQHandler
+ .word DMA1_Channel6_IRQHandler
+ .word DMA1_Channel7_IRQHandler
+ .word ADC1_2_IRQHandler
+ .word USB_HP_CAN1_TX_IRQHandler
+ .word USB_LP_CAN1_RX0_IRQHandler
+ .word CAN1_RX1_IRQHandler
+ .word CAN1_SCE_IRQHandler
+ .word EXTI9_5_IRQHandler
+ .word TIM1_BRK_IRQHandler
+ .word TIM1_UP_IRQHandler
+ .word TIM1_TRG_COM_IRQHandler
+ .word TIM1_CC_IRQHandler
+ .word TIM2_IRQHandler
+ .word TIM3_IRQHandler
+ .word 0
+ .word I2C1_EV_IRQHandler
+ .word I2C1_ER_IRQHandler
+ .word 0
+ .word 0
+ .word SPI1_IRQHandler
+ .word 0
+ .word USART1_IRQHandler
+ .word USART2_IRQHandler
+ .word 0
+ .word EXTI15_10_IRQHandler
+ .word RTCAlarm_IRQHandler
+ .word USBWakeUp_IRQHandler
+ .word 0
+ .word 0
+ .word 0
+ .word 0
+ .word 0
+ .word 0
+ .word 0
+ .word BootRAM /* @0x108. This is for boot in RAM mode for
+ STM32F10x Low Density devices.*/
+
+/*******************************************************************************
+*
+* Provide weak aliases for each Exception handler to the Default_Handler.
+* As they are weak aliases, any function with the same name will override
+* this definition.
+*
+*******************************************************************************/
+
+ .weak NMI_Handler
+ .thumb_set NMI_Handler,Default_Handler
+
+ .weak HardFault_Handler
+ .thumb_set HardFault_Handler,Default_Handler
+
+ .weak MemManage_Handler
+ .thumb_set MemManage_Handler,Default_Handler
+
+ .weak BusFault_Handler
+ .thumb_set BusFault_Handler,Default_Handler
+
+ .weak UsageFault_Handler
+ .thumb_set UsageFault_Handler,Default_Handler
+
+ .weak SVC_Handler
+ .thumb_set SVC_Handler,Default_Handler
+
+ .weak DebugMon_Handler
+ .thumb_set DebugMon_Handler,Default_Handler
+
+ .weak PendSV_Handler
+ .thumb_set PendSV_Handler,Default_Handler
+
+ .weak SysTick_Handler
+ .thumb_set SysTick_Handler,Default_Handler
+
+ .weak WWDG_IRQHandler
+ .thumb_set WWDG_IRQHandler,Default_Handler
+
+ .weak PVD_IRQHandler
+ .thumb_set PVD_IRQHandler,Default_Handler
+
+ .weak TAMPER_IRQHandler
+ .thumb_set TAMPER_IRQHandler,Default_Handler
+
+ .weak RTC_IRQHandler
+ .thumb_set RTC_IRQHandler,Default_Handler
+
+ .weak FLASH_IRQHandler
+ .thumb_set FLASH_IRQHandler,Default_Handler
+
+ .weak RCC_IRQHandler
+ .thumb_set RCC_IRQHandler,Default_Handler
+
+ .weak EXTI0_IRQHandler
+ .thumb_set EXTI0_IRQHandler,Default_Handler
+
+ .weak EXTI1_IRQHandler
+ .thumb_set EXTI1_IRQHandler,Default_Handler
+
+ .weak EXTI2_IRQHandler
+ .thumb_set EXTI2_IRQHandler,Default_Handler
+
+ .weak EXTI3_IRQHandler
+ .thumb_set EXTI3_IRQHandler,Default_Handler
+
+ .weak EXTI4_IRQHandler
+ .thumb_set EXTI4_IRQHandler,Default_Handler
+
+ .weak DMA1_Channel1_IRQHandler
+ .thumb_set DMA1_Channel1_IRQHandler,Default_Handler
+
+ .weak DMA1_Channel2_IRQHandler
+ .thumb_set DMA1_Channel2_IRQHandler,Default_Handler
+
+ .weak DMA1_Channel3_IRQHandler
+ .thumb_set DMA1_Channel3_IRQHandler,Default_Handler
+
+ .weak DMA1_Channel4_IRQHandler
+ .thumb_set DMA1_Channel4_IRQHandler,Default_Handler
+
+ .weak DMA1_Channel5_IRQHandler
+ .thumb_set DMA1_Channel5_IRQHandler,Default_Handler
+
+ .weak DMA1_Channel6_IRQHandler
+ .thumb_set DMA1_Channel6_IRQHandler,Default_Handler
+
+ .weak DMA1_Channel7_IRQHandler
+ .thumb_set DMA1_Channel7_IRQHandler,Default_Handler
+
+ .weak ADC1_2_IRQHandler
+ .thumb_set ADC1_2_IRQHandler,Default_Handler
+
+ .weak USB_HP_CAN1_TX_IRQHandler
+ .thumb_set USB_HP_CAN1_TX_IRQHandler,Default_Handler
+
+ .weak USB_LP_CAN1_RX0_IRQHandler
+ .thumb_set USB_LP_CAN1_RX0_IRQHandler,Default_Handler
+
+ .weak CAN1_RX1_IRQHandler
+ .thumb_set CAN1_RX1_IRQHandler,Default_Handler
+
+ .weak CAN1_SCE_IRQHandler
+ .thumb_set CAN1_SCE_IRQHandler,Default_Handler
+
+ .weak EXTI9_5_IRQHandler
+ .thumb_set EXTI9_5_IRQHandler,Default_Handler
+
+ .weak TIM1_BRK_IRQHandler
+ .thumb_set TIM1_BRK_IRQHandler,Default_Handler
+
+ .weak TIM1_UP_IRQHandler
+ .thumb_set TIM1_UP_IRQHandler,Default_Handler
+
+ .weak TIM1_TRG_COM_IRQHandler
+ .thumb_set TIM1_TRG_COM_IRQHandler,Default_Handler
+
+ .weak TIM1_CC_IRQHandler
+ .thumb_set TIM1_CC_IRQHandler,Default_Handler
+
+ .weak TIM2_IRQHandler
+ .thumb_set TIM2_IRQHandler,Default_Handler
+
+ .weak TIM3_IRQHandler
+ .thumb_set TIM3_IRQHandler,Default_Handler
+
+ .weak I2C1_EV_IRQHandler
+ .thumb_set I2C1_EV_IRQHandler,Default_Handler
+
+ .weak I2C1_ER_IRQHandler
+ .thumb_set I2C1_ER_IRQHandler,Default_Handler
+
+ .weak SPI1_IRQHandler
+ .thumb_set SPI1_IRQHandler,Default_Handler
+
+ .weak USART1_IRQHandler
+ .thumb_set USART1_IRQHandler,Default_Handler
+
+ .weak USART2_IRQHandler
+ .thumb_set USART2_IRQHandler,Default_Handler
+
+ .weak EXTI15_10_IRQHandler
+ .thumb_set EXTI15_10_IRQHandler,Default_Handler
+
+ .weak RTCAlarm_IRQHandler
+ .thumb_set RTCAlarm_IRQHandler,Default_Handler
+
+ .weak USBWakeUp_IRQHandler
+ .thumb_set USBWakeUp_IRQHandler,Default_Handler
+
+/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
diff --git a/Libraries/CMSIS/Device/ST/STM32F10x/Source/Templates/gcc_ride7/startup_stm32f10x_ld_vl.s b/Libraries/CMSIS/Device/ST/STM32F10x/Source/Templates/gcc_ride7/startup_stm32f10x_ld_vl.s
new file mode 100644
index 0000000..cba97a4
--- /dev/null
+++ b/Libraries/CMSIS/Device/ST/STM32F10x/Source/Templates/gcc_ride7/startup_stm32f10x_ld_vl.s
@@ -0,0 +1,389 @@
+/**
+ ******************************************************************************
+ * @file startup_stm32f10x_ld_vl.s
+ * @author MCD Application Team
+ * @version V3.6.1
+ * @date 09-March-2012
+ * @brief STM32F10x Low Density Value Line Devices vector table for RIDE7
+ * toolchain.
+ * This module performs:
+ * - Set the initial SP
+ * - Set the initial PC == Reset_Handler,
+ * - Set the vector table entries with the exceptions ISR address
+ * - Configure the clock system
+ * - Branches to main in the C library (which eventually
+ * calls main()).
+ * After Reset the Cortex-M3 processor is in Thread mode,
+ * priority is Privileged, and the Stack is set to Main.
+ ******************************************************************************
+ * @attention
+ *
+ * © COPYRIGHT 2012 STMicroelectronics
+ *
+ * Licensed under MCD-ST Liberty SW License Agreement V2, (the "License");
+ * You may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at:
+ *
+ * http://www.st.com/software_license_agreement_liberty_v2
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ *
+ ******************************************************************************
+ */
+
+ .syntax unified
+ .cpu cortex-m3
+ .fpu softvfp
+ .thumb
+
+.global g_pfnVectors
+.global Default_Handler
+
+/* start address for the initialization values of the .data section.
+defined in linker script */
+.word _sidata
+/* start address for the .data section. defined in linker script */
+.word _sdata
+/* end address for the .data section. defined in linker script */
+.word _edata
+/* start address for the .bss section. defined in linker script */
+.word _sbss
+/* end address for the .bss section. defined in linker script */
+.word _ebss
+
+.equ BootRAM, 0xF108F85F
+/**
+ * @brief This is the code that gets called when the processor first
+ * starts execution following a reset event. Only the absolutely
+ * necessary set is performed, after which the application
+ * supplied main() routine is called.
+ * @param None
+ * @retval None
+*/
+
+ .section .text.Reset_Handler
+ .weak Reset_Handler
+ .type Reset_Handler, %function
+Reset_Handler:
+
+/* Copy the data segment initializers from flash to SRAM */
+ movs r1, #0
+ b LoopCopyDataInit
+
+CopyDataInit:
+ ldr r3, =_sidata
+ ldr r3, [r3, r1]
+ str r3, [r0, r1]
+ adds r1, r1, #4
+
+LoopCopyDataInit:
+ ldr r0, =_sdata
+ ldr r3, =_edata
+ adds r2, r0, r1
+ cmp r2, r3
+ bcc CopyDataInit
+ ldr r2, =_sbss
+ b LoopFillZerobss
+/* Zero fill the bss segment. */
+FillZerobss:
+ movs r3, #0
+ str r3, [r2], #4
+
+LoopFillZerobss:
+ ldr r3, = _ebss
+ cmp r2, r3
+ bcc FillZerobss
+/* Call the clock system intitialization function.*/
+ bl SystemInit
+/* Call the application's entry point.*/
+ bl main
+ bx lr
+.size Reset_Handler, .-Reset_Handler
+
+/**
+ * @brief This is the code that gets called when the processor receives an
+ * unexpected interrupt. This simply enters an infinite loop, preserving
+ * the system state for examination by a debugger.
+ * @param None
+ * @retval None
+*/
+ .section .text.Default_Handler,"ax",%progbits
+Default_Handler:
+Infinite_Loop:
+ b Infinite_Loop
+ .size Default_Handler, .-Default_Handler
+/******************************************************************************
+* The minimal vector table for a Cortex M3. Note that the proper constructs
+* must be placed on this to ensure that it ends up at physical address
+* 0x0000.0000.
+*
+******************************************************************************/
+ .section .isr_vector,"a",%progbits
+ .type g_pfnVectors, %object
+ .size g_pfnVectors, .-g_pfnVectors
+
+g_pfnVectors:
+ .word _estack
+ .word Reset_Handler
+ .word NMI_Handler
+ .word HardFault_Handler
+ .word MemManage_Handler
+ .word BusFault_Handler
+ .word UsageFault_Handler
+ .word 0
+ .word 0
+ .word 0
+ .word 0
+ .word SVC_Handler
+ .word DebugMon_Handler
+ .word 0
+ .word PendSV_Handler
+ .word SysTick_Handler
+ .word WWDG_IRQHandler
+ .word PVD_IRQHandler
+ .word TAMPER_IRQHandler
+ .word RTC_IRQHandler
+ .word FLASH_IRQHandler
+ .word RCC_IRQHandler
+ .word EXTI0_IRQHandler
+ .word EXTI1_IRQHandler
+ .word EXTI2_IRQHandler
+ .word EXTI3_IRQHandler
+ .word EXTI4_IRQHandler
+ .word DMA1_Channel1_IRQHandler
+ .word DMA1_Channel2_IRQHandler
+ .word DMA1_Channel3_IRQHandler
+ .word DMA1_Channel4_IRQHandler
+ .word DMA1_Channel5_IRQHandler
+ .word DMA1_Channel6_IRQHandler
+ .word DMA1_Channel7_IRQHandler
+ .word ADC1_IRQHandler
+ .word 0
+ .word 0
+ .word 0
+ .word 0
+ .word EXTI9_5_IRQHandler
+ .word TIM1_BRK_TIM15_IRQHandler
+ .word TIM1_UP_TIM16_IRQHandler
+ .word TIM1_TRG_COM_TIM17_IRQHandler
+ .word TIM1_CC_IRQHandler
+ .word TIM2_IRQHandler
+ .word TIM3_IRQHandler
+ .word 0
+ .word I2C1_EV_IRQHandler
+ .word I2C1_ER_IRQHandler
+ .word 0
+ .word 0
+ .word SPI1_IRQHandler
+ .word 0
+ .word USART1_IRQHandler
+ .word USART2_IRQHandler
+ .word 0
+ .word EXTI15_10_IRQHandler
+ .word RTCAlarm_IRQHandler
+ .word CEC_IRQHandler
+ .word 0
+ .word 0
+ .word 0
+ .word 0
+ .word 0
+ .word 0
+ .word 0
+ .word 0
+ .word 0
+ .word 0
+ .word 0
+ .word TIM6_DAC_IRQHandler
+ .word TIM7_IRQHandler
+ .word 0
+ .word 0
+ .word 0
+ .word 0
+ .word 0
+ .word 0
+ .word 0
+ .word 0
+ .word 0
+ .word 0
+ .word 0
+ .word 0
+ .word 0
+ .word 0
+ .word 0
+ .word 0
+ .word 0
+ .word 0
+ .word 0
+ .word 0
+ .word 0
+ .word 0
+ .word 0
+ .word 0
+ .word 0
+ .word 0
+ .word 0
+ .word 0
+ .word 0
+ .word 0
+ .word 0
+ .word 0
+ .word 0
+ .word 0
+ .word 0
+ .word 0
+ .word 0
+ .word 0
+ .word 0
+ .word 0
+ .word 0
+ .word 0
+ .word 0
+ .word BootRAM /* @0x01CC. This is for boot in RAM mode for
+ STM32F10x Low Density Value Line devices. */
+
+/*******************************************************************************
+* Provide weak aliases for each Exception handler to the Default_Handler.
+* As they are weak aliases, any function with the same name will override
+* this definition.
+*******************************************************************************/
+
+ .weak NMI_Handler
+ .thumb_set NMI_Handler,Default_Handler
+
+ .weak HardFault_Handler
+ .thumb_set HardFault_Handler,Default_Handler
+
+ .weak MemManage_Handler
+ .thumb_set MemManage_Handler,Default_Handler
+
+ .weak BusFault_Handler
+ .thumb_set BusFault_Handler,Default_Handler
+
+ .weak UsageFault_Handler
+ .thumb_set UsageFault_Handler,Default_Handler
+
+ .weak SVC_Handler
+ .thumb_set SVC_Handler,Default_Handler
+
+ .weak DebugMon_Handler
+ .thumb_set DebugMon_Handler,Default_Handler
+
+ .weak PendSV_Handler
+ .thumb_set PendSV_Handler,Default_Handler
+
+ .weak SysTick_Handler
+ .thumb_set SysTick_Handler,Default_Handler
+
+ .weak WWDG_IRQHandler
+ .thumb_set WWDG_IRQHandler,Default_Handler
+
+ .weak PVD_IRQHandler
+ .thumb_set PVD_IRQHandler,Default_Handler
+
+ .weak TAMPER_IRQHandler
+ .thumb_set TAMPER_IRQHandler,Default_Handler
+
+ .weak RTC_IRQHandler
+ .thumb_set RTC_IRQHandler,Default_Handler
+
+ .weak FLASH_IRQHandler
+ .thumb_set FLASH_IRQHandler,Default_Handler
+
+ .weak RCC_IRQHandler
+ .thumb_set RCC_IRQHandler,Default_Handler
+
+ .weak EXTI0_IRQHandler
+ .thumb_set EXTI0_IRQHandler,Default_Handler
+
+ .weak EXTI1_IRQHandler
+ .thumb_set EXTI1_IRQHandler,Default_Handler
+
+ .weak EXTI2_IRQHandler
+ .thumb_set EXTI2_IRQHandler,Default_Handler
+
+ .weak EXTI3_IRQHandler
+ .thumb_set EXTI3_IRQHandler,Default_Handler
+
+ .weak EXTI4_IRQHandler
+ .thumb_set EXTI4_IRQHandler,Default_Handler
+
+ .weak DMA1_Channel1_IRQHandler
+ .thumb_set DMA1_Channel1_IRQHandler,Default_Handler
+
+ .weak DMA1_Channel2_IRQHandler
+ .thumb_set DMA1_Channel2_IRQHandler,Default_Handler
+
+ .weak DMA1_Channel3_IRQHandler
+ .thumb_set DMA1_Channel3_IRQHandler,Default_Handler
+
+ .weak DMA1_Channel4_IRQHandler
+ .thumb_set DMA1_Channel4_IRQHandler,Default_Handler
+
+ .weak DMA1_Channel5_IRQHandler
+ .thumb_set DMA1_Channel5_IRQHandler,Default_Handler
+
+ .weak DMA1_Channel6_IRQHandler
+ .thumb_set DMA1_Channel6_IRQHandler,Default_Handler
+
+ .weak DMA1_Channel7_IRQHandler
+ .thumb_set DMA1_Channel7_IRQHandler,Default_Handler
+
+ .weak ADC1_IRQHandler
+ .thumb_set ADC1_IRQHandler,Default_Handler
+
+ .weak EXTI9_5_IRQHandler
+ .thumb_set EXTI9_5_IRQHandler,Default_Handler
+
+ .weak TIM1_BRK_TIM15_IRQHandler
+ .thumb_set TIM1_BRK_TIM15_IRQHandler,Default_Handler
+
+ .weak TIM1_UP_TIM16_IRQHandler
+ .thumb_set TIM1_UP_TIM16_IRQHandler,Default_Handler
+
+ .weak TIM1_TRG_COM_TIM17_IRQHandler
+ .thumb_set TIM1_TRG_COM_TIM17_IRQHandler,Default_Handler
+
+ .weak TIM1_CC_IRQHandler
+ .thumb_set TIM1_CC_IRQHandler,Default_Handler
+
+ .weak TIM2_IRQHandler
+ .thumb_set TIM2_IRQHandler,Default_Handler
+
+ .weak TIM3_IRQHandler
+ .thumb_set TIM3_IRQHandler,Default_Handler
+
+ .weak I2C1_EV_IRQHandler
+ .thumb_set I2C1_EV_IRQHandler,Default_Handler
+
+ .weak I2C1_ER_IRQHandler
+ .thumb_set I2C1_ER_IRQHandler,Default_Handler
+
+ .weak SPI1_IRQHandler
+ .thumb_set SPI1_IRQHandler,Default_Handler
+
+ .weak USART1_IRQHandler
+ .thumb_set USART1_IRQHandler,Default_Handler
+
+ .weak USART2_IRQHandler
+ .thumb_set USART2_IRQHandler,Default_Handler
+
+ .weak EXTI15_10_IRQHandler
+ .thumb_set EXTI15_10_IRQHandler,Default_Handler
+
+ .weak RTCAlarm_IRQHandler
+ .thumb_set RTCAlarm_IRQHandler,Default_Handler
+
+ .weak CEC_IRQHandler
+ .thumb_set CEC_IRQHandler,Default_Handler
+
+ .weak TIM6_DAC_IRQHandler
+ .thumb_set TIM6_DAC_IRQHandler,Default_Handler
+
+ .weak TIM7_IRQHandler
+ .thumb_set TIM7_IRQHandler,Default_Handler
+
+/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
diff --git a/Libraries/CMSIS/Device/ST/STM32F10x/Source/Templates/gcc_ride7/startup_stm32f10x_md.s b/Libraries/CMSIS/Device/ST/STM32F10x/Source/Templates/gcc_ride7/startup_stm32f10x_md.s
new file mode 100644
index 0000000..34c987d
--- /dev/null
+++ b/Libraries/CMSIS/Device/ST/STM32F10x/Source/Templates/gcc_ride7/startup_stm32f10x_md.s
@@ -0,0 +1,364 @@
+/**
+ ******************************************************************************
+ * @file startup_stm32f10x_md.s
+ * @author MCD Application Team
+ * @version V3.6.1
+ * @date 09-March-2012
+ * @brief STM32F10x Medium Density Devices vector table for RIDE7 toolchain.
+ * This module performs:
+ * - Set the initial SP
+ * - Set the initial PC == Reset_Handler,
+ * - Set the vector table entries with the exceptions ISR address
+ * - Configure the clock system
+ * - Branches to main in the C library (which eventually
+ * calls main()).
+ * After Reset the Cortex-M3 processor is in Thread mode,
+ * priority is Privileged, and the Stack is set to Main.
+ ******************************************************************************
+ * @attention
+ *
+ * © COPYRIGHT 2012 STMicroelectronics
+ *
+ * Licensed under MCD-ST Liberty SW License Agreement V2, (the "License");
+ * You may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at:
+ *
+ * http://www.st.com/software_license_agreement_liberty_v2
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ *
+ ******************************************************************************
+ */
+
+ .syntax unified
+ .cpu cortex-m3
+ .fpu softvfp
+ .thumb
+
+.global g_pfnVectors
+.global Default_Handler
+
+/* start address for the initialization values of the .data section.
+defined in linker script */
+.word _sidata
+/* start address for the .data section. defined in linker script */
+.word _sdata
+/* end address for the .data section. defined in linker script */
+.word _edata
+/* start address for the .bss section. defined in linker script */
+.word _sbss
+/* end address for the .bss section. defined in linker script */
+.word _ebss
+
+.equ BootRAM, 0xF108F85F
+/**
+ * @brief This is the code that gets called when the processor first
+ * starts execution following a reset event. Only the absolutely
+ * necessary set is performed, after which the application
+ * supplied main() routine is called.
+ * @param None
+ * @retval : None
+*/
+
+ .section .text.Reset_Handler
+ .weak Reset_Handler
+ .type Reset_Handler, %function
+Reset_Handler:
+
+/* Copy the data segment initializers from flash to SRAM */
+ movs r1, #0
+ b LoopCopyDataInit
+
+CopyDataInit:
+ ldr r3, =_sidata
+ ldr r3, [r3, r1]
+ str r3, [r0, r1]
+ adds r1, r1, #4
+
+LoopCopyDataInit:
+ ldr r0, =_sdata
+ ldr r3, =_edata
+ adds r2, r0, r1
+ cmp r2, r3
+ bcc CopyDataInit
+ ldr r2, =_sbss
+ b LoopFillZerobss
+/* Zero fill the bss segment. */
+FillZerobss:
+ movs r3, #0
+ str r3, [r2], #4
+
+LoopFillZerobss:
+ ldr r3, = _ebss
+ cmp r2, r3
+ bcc FillZerobss
+/* Call the clock system intitialization function.*/
+ bl SystemInit
+/* Call the application's entry point.*/
+ bl main
+ bx lr
+.size Reset_Handler, .-Reset_Handler
+
+/**
+ * @brief This is the code that gets called when the processor receives an
+ * unexpected interrupt. This simply enters an infinite loop, preserving
+ * the system state for examination by a debugger.
+ * @param None
+ * @retval None
+*/
+ .section .text.Default_Handler,"ax",%progbits
+Default_Handler:
+Infinite_Loop:
+ b Infinite_Loop
+ .size Default_Handler, .-Default_Handler
+/******************************************************************************
+*
+* The minimal vector table for a Cortex M3. Note that the proper constructs
+* must be placed on this to ensure that it ends up at physical address
+* 0x0000.0000.
+*
+******************************************************************************/
+ .section .isr_vector,"a",%progbits
+ .type g_pfnVectors, %object
+ .size g_pfnVectors, .-g_pfnVectors
+
+
+g_pfnVectors:
+ .word _estack
+ .word Reset_Handler
+ .word NMI_Handler
+ .word HardFault_Handler
+ .word MemManage_Handler
+ .word BusFault_Handler
+ .word UsageFault_Handler
+ .word 0
+ .word 0
+ .word 0
+ .word 0
+ .word SVC_Handler
+ .word DebugMon_Handler
+ .word 0
+ .word PendSV_Handler
+ .word SysTick_Handler
+ .word WWDG_IRQHandler
+ .word PVD_IRQHandler
+ .word TAMPER_IRQHandler
+ .word RTC_IRQHandler
+ .word FLASH_IRQHandler
+ .word RCC_IRQHandler
+ .word EXTI0_IRQHandler
+ .word EXTI1_IRQHandler
+ .word EXTI2_IRQHandler
+ .word EXTI3_IRQHandler
+ .word EXTI4_IRQHandler
+ .word DMA1_Channel1_IRQHandler
+ .word DMA1_Channel2_IRQHandler
+ .word DMA1_Channel3_IRQHandler
+ .word DMA1_Channel4_IRQHandler
+ .word DMA1_Channel5_IRQHandler
+ .word DMA1_Channel6_IRQHandler
+ .word DMA1_Channel7_IRQHandler
+ .word ADC1_2_IRQHandler
+ .word USB_HP_CAN1_TX_IRQHandler
+ .word USB_LP_CAN1_RX0_IRQHandler
+ .word CAN1_RX1_IRQHandler
+ .word CAN1_SCE_IRQHandler
+ .word EXTI9_5_IRQHandler
+ .word TIM1_BRK_IRQHandler
+ .word TIM1_UP_IRQHandler
+ .word TIM1_TRG_COM_IRQHandler
+ .word TIM1_CC_IRQHandler
+ .word TIM2_IRQHandler
+ .word TIM3_IRQHandler
+ .word TIM4_IRQHandler
+ .word I2C1_EV_IRQHandler
+ .word I2C1_ER_IRQHandler
+ .word I2C2_EV_IRQHandler
+ .word I2C2_ER_IRQHandler
+ .word SPI1_IRQHandler
+ .word SPI2_IRQHandler
+ .word USART1_IRQHandler
+ .word USART2_IRQHandler
+ .word USART3_IRQHandler
+ .word EXTI15_10_IRQHandler
+ .word RTCAlarm_IRQHandler
+ .word USBWakeUp_IRQHandler
+ .word 0
+ .word 0
+ .word 0
+ .word 0
+ .word 0
+ .word 0
+ .word 0
+ .word BootRAM /* @0x108. This is for boot in RAM mode for
+ STM32F10x Medium Density devices. */
+
+/*******************************************************************************
+*
+* Provide weak aliases for each Exception handler to the Default_Handler.
+* As they are weak aliases, any function with the same name will override
+* this definition.
+*
+*******************************************************************************/
+
+ .weak NMI_Handler
+ .thumb_set NMI_Handler,Default_Handler
+
+ .weak HardFault_Handler
+ .thumb_set HardFault_Handler,Default_Handler
+
+ .weak MemManage_Handler
+ .thumb_set MemManage_Handler,Default_Handler
+
+ .weak BusFault_Handler
+ .thumb_set BusFault_Handler,Default_Handler
+
+ .weak UsageFault_Handler
+ .thumb_set UsageFault_Handler,Default_Handler
+
+ .weak SVC_Handler
+ .thumb_set SVC_Handler,Default_Handler
+
+ .weak DebugMon_Handler
+ .thumb_set DebugMon_Handler,Default_Handler
+
+ .weak PendSV_Handler
+ .thumb_set PendSV_Handler,Default_Handler
+
+ .weak SysTick_Handler
+ .thumb_set SysTick_Handler,Default_Handler
+
+ .weak WWDG_IRQHandler
+ .thumb_set WWDG_IRQHandler,Default_Handler
+
+ .weak PVD_IRQHandler
+ .thumb_set PVD_IRQHandler,Default_Handler
+
+ .weak TAMPER_IRQHandler
+ .thumb_set TAMPER_IRQHandler,Default_Handler
+
+ .weak RTC_IRQHandler
+ .thumb_set RTC_IRQHandler,Default_Handler
+
+ .weak FLASH_IRQHandler
+ .thumb_set FLASH_IRQHandler,Default_Handler
+
+ .weak RCC_IRQHandler
+ .thumb_set RCC_IRQHandler,Default_Handler
+
+ .weak EXTI0_IRQHandler
+ .thumb_set EXTI0_IRQHandler,Default_Handler
+
+ .weak EXTI1_IRQHandler
+ .thumb_set EXTI1_IRQHandler,Default_Handler
+
+ .weak EXTI2_IRQHandler
+ .thumb_set EXTI2_IRQHandler,Default_Handler
+
+ .weak EXTI3_IRQHandler
+ .thumb_set EXTI3_IRQHandler,Default_Handler
+
+ .weak EXTI4_IRQHandler
+ .thumb_set EXTI4_IRQHandler,Default_Handler
+
+ .weak DMA1_Channel1_IRQHandler
+ .thumb_set DMA1_Channel1_IRQHandler,Default_Handler
+
+ .weak DMA1_Channel2_IRQHandler
+ .thumb_set DMA1_Channel2_IRQHandler,Default_Handler
+
+ .weak DMA1_Channel3_IRQHandler
+ .thumb_set DMA1_Channel3_IRQHandler,Default_Handler
+
+ .weak DMA1_Channel4_IRQHandler
+ .thumb_set DMA1_Channel4_IRQHandler,Default_Handler
+
+ .weak DMA1_Channel5_IRQHandler
+ .thumb_set DMA1_Channel5_IRQHandler,Default_Handler
+
+ .weak DMA1_Channel6_IRQHandler
+ .thumb_set DMA1_Channel6_IRQHandler,Default_Handler
+
+ .weak DMA1_Channel7_IRQHandler
+ .thumb_set DMA1_Channel7_IRQHandler,Default_Handler
+
+ .weak ADC1_2_IRQHandler
+ .thumb_set ADC1_2_IRQHandler,Default_Handler
+
+ .weak USB_HP_CAN1_TX_IRQHandler
+ .thumb_set USB_HP_CAN1_TX_IRQHandler,Default_Handler
+
+ .weak USB_LP_CAN1_RX0_IRQHandler
+ .thumb_set USB_LP_CAN1_RX0_IRQHandler,Default_Handler
+
+ .weak CAN1_RX1_IRQHandler
+ .thumb_set CAN1_RX1_IRQHandler,Default_Handler
+
+ .weak CAN1_SCE_IRQHandler
+ .thumb_set CAN1_SCE_IRQHandler,Default_Handler
+
+ .weak EXTI9_5_IRQHandler
+ .thumb_set EXTI9_5_IRQHandler,Default_Handler
+
+ .weak TIM1_BRK_IRQHandler
+ .thumb_set TIM1_BRK_IRQHandler,Default_Handler
+
+ .weak TIM1_UP_IRQHandler
+ .thumb_set TIM1_UP_IRQHandler,Default_Handler
+
+ .weak TIM1_TRG_COM_IRQHandler
+ .thumb_set TIM1_TRG_COM_IRQHandler,Default_Handler
+
+ .weak TIM1_CC_IRQHandler
+ .thumb_set TIM1_CC_IRQHandler,Default_Handler
+
+ .weak TIM2_IRQHandler
+ .thumb_set TIM2_IRQHandler,Default_Handler
+
+ .weak TIM3_IRQHandler
+ .thumb_set TIM3_IRQHandler,Default_Handler
+
+ .weak TIM4_IRQHandler
+ .thumb_set TIM4_IRQHandler,Default_Handler
+
+ .weak I2C1_EV_IRQHandler
+ .thumb_set I2C1_EV_IRQHandler,Default_Handler
+
+ .weak I2C1_ER_IRQHandler
+ .thumb_set I2C1_ER_IRQHandler,Default_Handler
+
+ .weak I2C2_EV_IRQHandler
+ .thumb_set I2C2_EV_IRQHandler,Default_Handler
+
+ .weak I2C2_ER_IRQHandler
+ .thumb_set I2C2_ER_IRQHandler,Default_Handler
+
+ .weak SPI1_IRQHandler
+ .thumb_set SPI1_IRQHandler,Default_Handler
+
+ .weak SPI2_IRQHandler
+ .thumb_set SPI2_IRQHandler,Default_Handler
+
+ .weak USART1_IRQHandler
+ .thumb_set USART1_IRQHandler,Default_Handler
+
+ .weak USART2_IRQHandler
+ .thumb_set USART2_IRQHandler,Default_Handler
+
+ .weak USART3_IRQHandler
+ .thumb_set USART3_IRQHandler,Default_Handler
+
+ .weak EXTI15_10_IRQHandler
+ .thumb_set EXTI15_10_IRQHandler,Default_Handler
+
+ .weak RTCAlarm_IRQHandler
+ .thumb_set RTCAlarm_IRQHandler,Default_Handler
+
+ .weak USBWakeUp_IRQHandler
+ .thumb_set USBWakeUp_IRQHandler,Default_Handler
+
+/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
diff --git a/Libraries/CMSIS/Device/ST/STM32F10x/Source/Templates/gcc_ride7/startup_stm32f10x_md_vl.s b/Libraries/CMSIS/Device/ST/STM32F10x/Source/Templates/gcc_ride7/startup_stm32f10x_md_vl.s
new file mode 100644
index 0000000..896bb79
--- /dev/null
+++ b/Libraries/CMSIS/Device/ST/STM32F10x/Source/Templates/gcc_ride7/startup_stm32f10x_md_vl.s
@@ -0,0 +1,405 @@
+/**
+ ******************************************************************************
+ * @file startup_stm32f10x_md_vl.s
+ * @author MCD Application Team
+ * @version V3.6.1
+ * @date 09-March-2012
+ * @brief STM32F10x Medium Density Value Line Devices vector table for RIDE7
+ * toolchain.
+ * This module performs:
+ * - Set the initial SP
+ * - Set the initial PC == Reset_Handler,
+ * - Set the vector table entries with the exceptions ISR address
+ * - Configure the clock system
+ * - Branches to main in the C library (which eventually
+ * calls main()).
+ * After Reset the Cortex-M3 processor is in Thread mode,
+ * priority is Privileged, and the Stack is set to Main.
+ ******************************************************************************
+ * @attention
+ *
+ * © COPYRIGHT 2012 STMicroelectronics
+ *
+ * Licensed under MCD-ST Liberty SW License Agreement V2, (the "License");
+ * You may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at:
+ *
+ * http://www.st.com/software_license_agreement_liberty_v2
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ *
+ ******************************************************************************
+ */
+
+ .syntax unified
+ .cpu cortex-m3
+ .fpu softvfp
+ .thumb
+
+.global g_pfnVectors
+.global Default_Handler
+
+/* start address for the initialization values of the .data section.
+defined in linker script */
+.word _sidata
+/* start address for the .data section. defined in linker script */
+.word _sdata
+/* end address for the .data section. defined in linker script */
+.word _edata
+/* start address for the .bss section. defined in linker script */
+.word _sbss
+/* end address for the .bss section. defined in linker script */
+.word _ebss
+
+.equ BootRAM, 0xF108F85F
+/**
+ * @brief This is the code that gets called when the processor first
+ * starts execution following a reset event. Only the absolutely
+ * necessary set is performed, after which the application
+ * supplied main() routine is called.
+ * @param None
+ * @retval None
+*/
+
+ .section .text.Reset_Handler
+ .weak Reset_Handler
+ .type Reset_Handler, %function
+Reset_Handler:
+
+/* Copy the data segment initializers from flash to SRAM */
+ movs r1, #0
+ b LoopCopyDataInit
+
+CopyDataInit:
+ ldr r3, =_sidata
+ ldr r3, [r3, r1]
+ str r3, [r0, r1]
+ adds r1, r1, #4
+
+LoopCopyDataInit:
+ ldr r0, =_sdata
+ ldr r3, =_edata
+ adds r2, r0, r1
+ cmp r2, r3
+ bcc CopyDataInit
+ ldr r2, =_sbss
+ b LoopFillZerobss
+/* Zero fill the bss segment. */
+FillZerobss:
+ movs r3, #0
+ str r3, [r2], #4
+
+LoopFillZerobss:
+ ldr r3, = _ebss
+ cmp r2, r3
+ bcc FillZerobss
+/* Call the clock system intitialization function.*/
+ bl SystemInit
+/* Call the application's entry point.*/
+ bl main
+ bx lr
+.size Reset_Handler, .-Reset_Handler
+
+/**
+ * @brief This is the code that gets called when the processor receives an
+ * unexpected interrupt. This simply enters an infinite loop, preserving
+ * the system state for examination by a debugger.
+ * @param None
+ * @retval None
+*/
+ .section .text.Default_Handler,"ax",%progbits
+Default_Handler:
+Infinite_Loop:
+ b Infinite_Loop
+ .size Default_Handler, .-Default_Handler
+/******************************************************************************
+*
+* The minimal vector table for a Cortex M3. Note that the proper constructs
+* must be placed on this to ensure that it ends up at physical address
+* 0x0000.0000.
+*
+******************************************************************************/
+ .section .isr_vector,"a",%progbits
+ .type g_pfnVectors, %object
+ .size g_pfnVectors, .-g_pfnVectors
+
+g_pfnVectors:
+ .word _estack
+ .word Reset_Handler
+ .word NMI_Handler
+ .word HardFault_Handler
+ .word MemManage_Handler
+ .word BusFault_Handler
+ .word UsageFault_Handler
+ .word 0
+ .word 0
+ .word 0
+ .word 0
+ .word SVC_Handler
+ .word DebugMon_Handler
+ .word 0
+ .word PendSV_Handler
+ .word SysTick_Handler
+ .word WWDG_IRQHandler
+ .word PVD_IRQHandler
+ .word TAMPER_IRQHandler
+ .word RTC_IRQHandler
+ .word FLASH_IRQHandler
+ .word RCC_IRQHandler
+ .word EXTI0_IRQHandler
+ .word EXTI1_IRQHandler
+ .word EXTI2_IRQHandler
+ .word EXTI3_IRQHandler
+ .word EXTI4_IRQHandler
+ .word DMA1_Channel1_IRQHandler
+ .word DMA1_Channel2_IRQHandler
+ .word DMA1_Channel3_IRQHandler
+ .word DMA1_Channel4_IRQHandler
+ .word DMA1_Channel5_IRQHandler
+ .word DMA1_Channel6_IRQHandler
+ .word DMA1_Channel7_IRQHandler
+ .word ADC1_IRQHandler
+ .word 0
+ .word 0
+ .word 0
+ .word 0
+ .word EXTI9_5_IRQHandler
+ .word TIM1_BRK_TIM15_IRQHandler
+ .word TIM1_UP_TIM16_IRQHandler
+ .word TIM1_TRG_COM_TIM17_IRQHandler
+ .word TIM1_CC_IRQHandler
+ .word TIM2_IRQHandler
+ .word TIM3_IRQHandler
+ .word TIM4_IRQHandler
+ .word I2C1_EV_IRQHandler
+ .word I2C1_ER_IRQHandler
+ .word I2C2_EV_IRQHandler
+ .word I2C2_ER_IRQHandler
+ .word SPI1_IRQHandler
+ .word SPI2_IRQHandler
+ .word USART1_IRQHandler
+ .word USART2_IRQHandler
+ .word USART3_IRQHandler
+ .word EXTI15_10_IRQHandler
+ .word RTCAlarm_IRQHandler
+ .word CEC_IRQHandler
+ .word 0
+ .word 0
+ .word 0
+ .word 0
+ .word 0
+ .word 0
+ .word 0
+ .word 0
+ .word 0
+ .word 0
+ .word 0
+ .word TIM6_DAC_IRQHandler
+ .word TIM7_IRQHandler
+ .word 0
+ .word 0
+ .word 0
+ .word 0
+ .word 0
+ .word 0
+ .word 0
+ .word 0
+ .word 0
+ .word 0
+ .word 0
+ .word 0
+ .word 0
+ .word 0
+ .word 0
+ .word 0
+ .word 0
+ .word 0
+ .word 0
+ .word 0
+ .word 0
+ .word 0
+ .word 0
+ .word 0
+ .word 0
+ .word 0
+ .word 0
+ .word 0
+ .word 0
+ .word 0
+ .word 0
+ .word 0
+ .word 0
+ .word 0
+ .word 0
+ .word 0
+ .word 0
+ .word 0
+ .word 0
+ .word 0
+ .word 0
+ .word 0
+ .word 0
+ .word BootRAM /* @0x01CC. This is for boot in RAM mode for
+ STM32F10x Medium Value Line Density devices. */
+
+/*******************************************************************************
+* Provide weak aliases for each Exception handler to the Default_Handler.
+* As they are weak aliases, any function with the same name will override
+* this definition.
+*******************************************************************************/
+
+ .weak NMI_Handler
+ .thumb_set NMI_Handler,Default_Handler
+
+ .weak HardFault_Handler
+ .thumb_set HardFault_Handler,Default_Handler
+
+ .weak MemManage_Handler
+ .thumb_set MemManage_Handler,Default_Handler
+
+ .weak BusFault_Handler
+ .thumb_set BusFault_Handler,Default_Handler
+
+ .weak UsageFault_Handler
+ .thumb_set UsageFault_Handler,Default_Handler
+
+ .weak SVC_Handler
+ .thumb_set SVC_Handler,Default_Handler
+
+ .weak DebugMon_Handler
+ .thumb_set DebugMon_Handler,Default_Handler
+
+ .weak PendSV_Handler
+ .thumb_set PendSV_Handler,Default_Handler
+
+ .weak SysTick_Handler
+ .thumb_set SysTick_Handler,Default_Handler
+
+ .weak WWDG_IRQHandler
+ .thumb_set WWDG_IRQHandler,Default_Handler
+
+ .weak PVD_IRQHandler
+ .thumb_set PVD_IRQHandler,Default_Handler
+
+ .weak TAMPER_IRQHandler
+ .thumb_set TAMPER_IRQHandler,Default_Handler
+
+ .weak RTC_IRQHandler
+ .thumb_set RTC_IRQHandler,Default_Handler
+
+ .weak FLASH_IRQHandler
+ .thumb_set FLASH_IRQHandler,Default_Handler
+
+ .weak RCC_IRQHandler
+ .thumb_set RCC_IRQHandler,Default_Handler
+
+ .weak EXTI0_IRQHandler
+ .thumb_set EXTI0_IRQHandler,Default_Handler
+
+ .weak EXTI1_IRQHandler
+ .thumb_set EXTI1_IRQHandler,Default_Handler
+
+ .weak EXTI2_IRQHandler
+ .thumb_set EXTI2_IRQHandler,Default_Handler
+
+ .weak EXTI3_IRQHandler
+ .thumb_set EXTI3_IRQHandler,Default_Handler
+
+ .weak EXTI4_IRQHandler
+ .thumb_set EXTI4_IRQHandler,Default_Handler
+
+ .weak DMA1_Channel1_IRQHandler
+ .thumb_set DMA1_Channel1_IRQHandler,Default_Handler
+
+ .weak DMA1_Channel2_IRQHandler
+ .thumb_set DMA1_Channel2_IRQHandler,Default_Handler
+
+ .weak DMA1_Channel3_IRQHandler
+ .thumb_set DMA1_Channel3_IRQHandler,Default_Handler
+
+ .weak DMA1_Channel4_IRQHandler
+ .thumb_set DMA1_Channel4_IRQHandler,Default_Handler
+
+ .weak DMA1_Channel5_IRQHandler
+ .thumb_set DMA1_Channel5_IRQHandler,Default_Handler
+
+ .weak DMA1_Channel6_IRQHandler
+ .thumb_set DMA1_Channel6_IRQHandler,Default_Handler
+
+ .weak DMA1_Channel7_IRQHandler
+ .thumb_set DMA1_Channel7_IRQHandler,Default_Handler
+
+ .weak ADC1_IRQHandler
+ .thumb_set ADC1_IRQHandler,Default_Handler
+
+ .weak EXTI9_5_IRQHandler
+ .thumb_set EXTI9_5_IRQHandler,Default_Handler
+
+ .weak TIM1_BRK_TIM15_IRQHandler
+ .thumb_set TIM1_BRK_TIM15_IRQHandler,Default_Handler
+
+ .weak TIM1_UP_TIM16_IRQHandler
+ .thumb_set TIM1_UP_TIM16_IRQHandler,Default_Handler
+
+ .weak TIM1_TRG_COM_TIM17_IRQHandler
+ .thumb_set TIM1_TRG_COM_TIM17_IRQHandler,Default_Handler
+
+ .weak TIM1_CC_IRQHandler
+ .thumb_set TIM1_CC_IRQHandler,Default_Handler
+
+ .weak TIM2_IRQHandler
+ .thumb_set TIM2_IRQHandler,Default_Handler
+
+ .weak TIM3_IRQHandler
+ .thumb_set TIM3_IRQHandler,Default_Handler
+
+ .weak TIM4_IRQHandler
+ .thumb_set TIM4_IRQHandler,Default_Handler
+
+ .weak I2C1_EV_IRQHandler
+ .thumb_set I2C1_EV_IRQHandler,Default_Handler
+
+ .weak I2C1_ER_IRQHandler
+ .thumb_set I2C1_ER_IRQHandler,Default_Handler
+
+ .weak I2C2_EV_IRQHandler
+ .thumb_set I2C2_EV_IRQHandler,Default_Handler
+
+ .weak I2C2_ER_IRQHandler
+ .thumb_set I2C2_ER_IRQHandler,Default_Handler
+
+ .weak SPI1_IRQHandler
+ .thumb_set SPI1_IRQHandler,Default_Handler
+
+ .weak SPI2_IRQHandler
+ .thumb_set SPI2_IRQHandler,Default_Handler
+
+ .weak USART1_IRQHandler
+ .thumb_set USART1_IRQHandler,Default_Handler
+
+ .weak USART2_IRQHandler
+ .thumb_set USART2_IRQHandler,Default_Handler
+
+ .weak USART3_IRQHandler
+ .thumb_set USART3_IRQHandler,Default_Handler
+
+ .weak EXTI15_10_IRQHandler
+ .thumb_set EXTI15_10_IRQHandler,Default_Handler
+
+ .weak RTCAlarm_IRQHandler
+ .thumb_set RTCAlarm_IRQHandler,Default_Handler
+
+ .weak CEC_IRQHandler
+ .thumb_set CEC_IRQHandler,Default_Handler
+
+ .weak TIM6_DAC_IRQHandler
+ .thumb_set TIM6_DAC_IRQHandler,Default_Handler
+
+ .weak TIM7_IRQHandler
+ .thumb_set TIM7_IRQHandler,Default_Handler
+
+/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
diff --git a/Libraries/CMSIS/Device/ST/STM32F10x/Source/Templates/gcc_ride7/startup_stm32f10x_xl.s b/Libraries/CMSIS/Device/ST/STM32F10x/Source/Templates/gcc_ride7/startup_stm32f10x_xl.s
new file mode 100644
index 0000000..a0fa498
--- /dev/null
+++ b/Libraries/CMSIS/Device/ST/STM32F10x/Source/Templates/gcc_ride7/startup_stm32f10x_xl.s
@@ -0,0 +1,471 @@
+/**
+ ******************************************************************************
+ * @file startup_stm32f10x_xl.s
+ * @author MCD Application Team
+ * @version V3.6.1
+ * @date 09-March-2012
+ * @brief STM32F10x XL-Density Devices vector table for RIDE7 toolchain.
+ * This module performs:
+ * - Set the initial SP
+ * - Set the initial PC == Reset_Handler,
+ * - Set the vector table entries with the exceptions ISR address
+ * - Configure the clock system and the external SRAM mounted on
+ * STM3210E-EVAL board to be used as data memory (optional,
+ * to be enabled by user)
+ * - Branches to main in the C library (which eventually
+ * calls main()).
+ * After Reset the Cortex-M3 processor is in Thread mode,
+ * priority is Privileged, and the Stack is set to Main.
+ ******************************************************************************
+ * @attention
+ *
+ * © COPYRIGHT 2012 STMicroelectronics
+ *
+ * Licensed under MCD-ST Liberty SW License Agreement V2, (the "License");
+ * You may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at:
+ *
+ * http://www.st.com/software_license_agreement_liberty_v2
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ *
+ ******************************************************************************
+ */
+
+ .syntax unified
+ .cpu cortex-m3
+ .fpu softvfp
+ .thumb
+
+.global g_pfnVectors
+.global Default_Handler
+
+/* start address for the initialization values of the .data section.
+defined in linker script */
+.word _sidata
+/* start address for the .data section. defined in linker script */
+.word _sdata
+/* end address for the .data section. defined in linker script */
+.word _edata
+/* start address for the .bss section. defined in linker script */
+.word _sbss
+/* end address for the .bss section. defined in linker script */
+.word _ebss
+/* stack used for SystemInit_ExtMemCtl; always internal RAM used */
+
+.equ BootRAM, 0xF1E0F85F
+/**
+ * @brief This is the code that gets called when the processor first
+ * starts execution following a reset event. Only the absolutely
+ * necessary set is performed, after which the application
+ * supplied main() routine is called.
+ * @param None
+ * @retval : None
+*/
+
+ .section .text.Reset_Handler
+ .weak Reset_Handler
+ .type Reset_Handler, %function
+Reset_Handler:
+
+/* Copy the data segment initializers from flash to SRAM */
+ movs r1, #0
+ b LoopCopyDataInit
+
+CopyDataInit:
+ ldr r3, =_sidata
+ ldr r3, [r3, r1]
+ str r3, [r0, r1]
+ adds r1, r1, #4
+
+LoopCopyDataInit:
+ ldr r0, =_sdata
+ ldr r3, =_edata
+ adds r2, r0, r1
+ cmp r2, r3
+ bcc CopyDataInit
+ ldr r2, =_sbss
+ b LoopFillZerobss
+/* Zero fill the bss segment. */
+FillZerobss:
+ movs r3, #0
+ str r3, [r2], #4
+
+LoopFillZerobss:
+ ldr r3, = _ebss
+ cmp r2, r3
+ bcc FillZerobss
+/* Call the clock system intitialization function.*/
+ bl SystemInit
+/* Call the application's entry point.*/
+ bl main
+ bx lr
+.size Reset_Handler, .-Reset_Handler
+
+/**
+ * @brief This is the code that gets called when the processor receives an
+ * unexpected interrupt. This simply enters an infinite loop, preserving
+ * the system state for examination by a debugger.
+ * @param None
+ * @retval None
+*/
+ .section .text.Default_Handler,"ax",%progbits
+Default_Handler:
+Infinite_Loop:
+ b Infinite_Loop
+ .size Default_Handler, .-Default_Handler
+/******************************************************************************
+*
+* The minimal vector table for a Cortex M3. Note that the proper constructs
+* must be placed on this to ensure that it ends up at physical address
+* 0x0000.0000.
+*
+*******************************************************************************/
+ .section .isr_vector,"a",%progbits
+ .type g_pfnVectors, %object
+ .size g_pfnVectors, .-g_pfnVectors
+
+
+g_pfnVectors:
+ .word _estack
+ .word Reset_Handler
+ .word NMI_Handler
+ .word HardFault_Handler
+ .word MemManage_Handler
+ .word BusFault_Handler
+ .word UsageFault_Handler
+ .word 0
+ .word 0
+ .word 0
+ .word 0
+ .word SVC_Handler
+ .word DebugMon_Handler
+ .word 0
+ .word PendSV_Handler
+ .word SysTick_Handler
+ .word WWDG_IRQHandler
+ .word PVD_IRQHandler
+ .word TAMPER_IRQHandler
+ .word RTC_IRQHandler
+ .word FLASH_IRQHandler
+ .word RCC_IRQHandler
+ .word EXTI0_IRQHandler
+ .word EXTI1_IRQHandler
+ .word EXTI2_IRQHandler
+ .word EXTI3_IRQHandler
+ .word EXTI4_IRQHandler
+ .word DMA1_Channel1_IRQHandler
+ .word DMA1_Channel2_IRQHandler
+ .word DMA1_Channel3_IRQHandler
+ .word DMA1_Channel4_IRQHandler
+ .word DMA1_Channel5_IRQHandler
+ .word DMA1_Channel6_IRQHandler
+ .word DMA1_Channel7_IRQHandler
+ .word ADC1_2_IRQHandler
+ .word USB_HP_CAN1_TX_IRQHandler
+ .word USB_LP_CAN1_RX0_IRQHandler
+ .word CAN1_RX1_IRQHandler
+ .word CAN1_SCE_IRQHandler
+ .word EXTI9_5_IRQHandler
+ .word TIM1_BRK_TIM9_IRQHandler
+ .word TIM1_UP_TIM10_IRQHandler
+ .word TIM1_TRG_COM_TIM11_IRQHandler
+ .word TIM1_CC_IRQHandler
+ .word TIM2_IRQHandler
+ .word TIM3_IRQHandler
+ .word TIM4_IRQHandler
+ .word I2C1_EV_IRQHandler
+ .word I2C1_ER_IRQHandler
+ .word I2C2_EV_IRQHandler
+ .word I2C2_ER_IRQHandler
+ .word SPI1_IRQHandler
+ .word SPI2_IRQHandler
+ .word USART1_IRQHandler
+ .word USART2_IRQHandler
+ .word USART3_IRQHandler
+ .word EXTI15_10_IRQHandler
+ .word RTCAlarm_IRQHandler
+ .word USBWakeUp_IRQHandler
+ .word TIM8_BRK_TIM12_IRQHandler
+ .word TIM8_UP_TIM13_IRQHandler
+ .word TIM8_TRG_COM_TIM14_IRQHandler
+ .word TIM8_CC_IRQHandler
+ .word ADC3_IRQHandler
+ .word FSMC_IRQHandler
+ .word SDIO_IRQHandler
+ .word TIM5_IRQHandler
+ .word SPI3_IRQHandler
+ .word UART4_IRQHandler
+ .word UART5_IRQHandler
+ .word TIM6_IRQHandler
+ .word TIM7_IRQHandler
+ .word DMA2_Channel1_IRQHandler
+ .word DMA2_Channel2_IRQHandler
+ .word DMA2_Channel3_IRQHandler
+ .word DMA2_Channel4_5_IRQHandler
+ .word 0
+ .word 0
+ .word 0
+ .word 0
+ .word 0
+ .word 0
+ .word 0
+ .word 0
+ .word 0
+ .word 0
+ .word 0
+ .word 0
+ .word 0
+ .word 0
+ .word 0
+ .word 0
+ .word 0
+ .word 0
+ .word 0
+ .word 0
+ .word 0
+ .word 0
+ .word 0
+ .word 0
+ .word 0
+ .word 0
+ .word 0
+ .word 0
+ .word 0
+ .word 0
+ .word 0
+ .word 0
+ .word 0
+ .word 0
+ .word 0
+ .word 0
+ .word 0
+ .word 0
+ .word 0
+ .word 0
+ .word 0
+ .word 0
+ .word 0
+ .word 0
+ .word BootRAM /* @0x1E0. This is for boot in RAM mode for
+ STM32F10x XL Density devices. */
+/*******************************************************************************
+*
+* Provide weak aliases for each Exception handler to the Default_Handler.
+* As they are weak aliases, any function with the same name will override
+* this definition.
+*
+*******************************************************************************/
+
+ .weak NMI_Handler
+ .thumb_set NMI_Handler,Default_Handler
+
+ .weak HardFault_Handler
+ .thumb_set HardFault_Handler,Default_Handler
+
+ .weak MemManage_Handler
+ .thumb_set MemManage_Handler,Default_Handler
+
+ .weak BusFault_Handler
+ .thumb_set BusFault_Handler,Default_Handler
+
+ .weak UsageFault_Handler
+ .thumb_set UsageFault_Handler,Default_Handler
+
+ .weak SVC_Handler
+ .thumb_set SVC_Handler,Default_Handler
+
+ .weak DebugMon_Handler
+ .thumb_set DebugMon_Handler,Default_Handler
+
+ .weak PendSV_Handler
+ .thumb_set PendSV_Handler,Default_Handler
+
+ .weak SysTick_Handler
+ .thumb_set SysTick_Handler,Default_Handler
+
+ .weak WWDG_IRQHandler
+ .thumb_set WWDG_IRQHandler,Default_Handler
+
+ .weak PVD_IRQHandler
+ .thumb_set PVD_IRQHandler,Default_Handler
+
+ .weak TAMPER_IRQHandler
+ .thumb_set TAMPER_IRQHandler,Default_Handler
+
+ .weak RTC_IRQHandler
+ .thumb_set RTC_IRQHandler,Default_Handler
+
+ .weak FLASH_IRQHandler
+ .thumb_set FLASH_IRQHandler,Default_Handler
+
+ .weak RCC_IRQHandler
+ .thumb_set RCC_IRQHandler,Default_Handler
+
+ .weak EXTI0_IRQHandler
+ .thumb_set EXTI0_IRQHandler,Default_Handler
+
+ .weak EXTI1_IRQHandler
+ .thumb_set EXTI1_IRQHandler,Default_Handler
+
+ .weak EXTI2_IRQHandler
+ .thumb_set EXTI2_IRQHandler,Default_Handler
+
+ .weak EXTI3_IRQHandler
+ .thumb_set EXTI3_IRQHandler,Default_Handler
+
+ .weak EXTI4_IRQHandler
+ .thumb_set EXTI4_IRQHandler,Default_Handler
+
+ .weak DMA1_Channel1_IRQHandler
+ .thumb_set DMA1_Channel1_IRQHandler,Default_Handler
+
+ .weak DMA1_Channel2_IRQHandler
+ .thumb_set DMA1_Channel2_IRQHandler,Default_Handler
+
+ .weak DMA1_Channel3_IRQHandler
+ .thumb_set DMA1_Channel3_IRQHandler,Default_Handler
+
+ .weak DMA1_Channel4_IRQHandler
+ .thumb_set DMA1_Channel4_IRQHandler,Default_Handler
+
+ .weak DMA1_Channel5_IRQHandler
+ .thumb_set DMA1_Channel5_IRQHandler,Default_Handler
+
+ .weak DMA1_Channel6_IRQHandler
+ .thumb_set DMA1_Channel6_IRQHandler,Default_Handler
+
+ .weak DMA1_Channel7_IRQHandler
+ .thumb_set DMA1_Channel7_IRQHandler,Default_Handler
+
+ .weak ADC1_2_IRQHandler
+ .thumb_set ADC1_2_IRQHandler,Default_Handler
+
+ .weak USB_HP_CAN1_TX_IRQHandler
+ .thumb_set USB_HP_CAN1_TX_IRQHandler,Default_Handler
+
+ .weak USB_LP_CAN1_RX0_IRQHandler
+ .thumb_set USB_LP_CAN1_RX0_IRQHandler,Default_Handler
+
+ .weak CAN1_RX1_IRQHandler
+ .thumb_set CAN1_RX1_IRQHandler,Default_Handler
+
+ .weak CAN1_SCE_IRQHandler
+ .thumb_set CAN1_SCE_IRQHandler,Default_Handler
+
+ .weak EXTI9_5_IRQHandler
+ .thumb_set EXTI9_5_IRQHandler,Default_Handler
+
+ .weak TIM1_BRK_TIM9_IRQHandler
+ .thumb_set TIM1_BRK_TIM9_IRQHandler,Default_Handler
+
+ .weak TIM1_UP_TIM10_IRQHandler
+ .thumb_set TIM1_UP_TIM10_IRQHandler,Default_Handler
+
+ .weak TIM1_TRG_COM_TIM11_IRQHandler
+ .thumb_set TIM1_TRG_COM_TIM11_IRQHandler,Default_Handler
+
+ .weak TIM1_CC_IRQHandler
+ .thumb_set TIM1_CC_IRQHandler,Default_Handler
+
+ .weak TIM2_IRQHandler
+ .thumb_set TIM2_IRQHandler,Default_Handler
+
+ .weak TIM3_IRQHandler
+ .thumb_set TIM3_IRQHandler,Default_Handler
+
+ .weak TIM4_IRQHandler
+ .thumb_set TIM4_IRQHandler,Default_Handler
+
+ .weak I2C1_EV_IRQHandler
+ .thumb_set I2C1_EV_IRQHandler,Default_Handler
+
+ .weak I2C1_ER_IRQHandler
+ .thumb_set I2C1_ER_IRQHandler,Default_Handler
+
+ .weak I2C2_EV_IRQHandler
+ .thumb_set I2C2_EV_IRQHandler,Default_Handler
+
+ .weak I2C2_ER_IRQHandler
+ .thumb_set I2C2_ER_IRQHandler,Default_Handler
+
+ .weak SPI1_IRQHandler
+ .thumb_set SPI1_IRQHandler,Default_Handler
+
+ .weak SPI2_IRQHandler
+ .thumb_set SPI2_IRQHandler,Default_Handler
+
+ .weak USART1_IRQHandler
+ .thumb_set USART1_IRQHandler,Default_Handler
+
+ .weak USART2_IRQHandler
+ .thumb_set USART2_IRQHandler,Default_Handler
+
+ .weak USART3_IRQHandler
+ .thumb_set USART3_IRQHandler,Default_Handler
+
+ .weak EXTI15_10_IRQHandler
+ .thumb_set EXTI15_10_IRQHandler,Default_Handler
+
+ .weak RTCAlarm_IRQHandler
+ .thumb_set RTCAlarm_IRQHandler,Default_Handler
+
+ .weak USBWakeUp_IRQHandler
+ .thumb_set USBWakeUp_IRQHandler,Default_Handler
+
+ .weak TIM8_BRK_TIM12_IRQHandler
+ .thumb_set TIM8_BRK_TIM12_IRQHandler,Default_Handler
+
+ .weak TIM8_UP_TIM13_IRQHandler
+ .thumb_set TIM8_UP_TIM13_IRQHandler,Default_Handler
+
+ .weak TIM8_TRG_COM_TIM14_IRQHandler
+ .thumb_set TIM8_TRG_COM_TIM14_IRQHandler,Default_Handler
+
+ .weak TIM8_CC_IRQHandler
+ .thumb_set TIM8_CC_IRQHandler,Default_Handler
+
+ .weak ADC3_IRQHandler
+ .thumb_set ADC3_IRQHandler,Default_Handler
+
+ .weak FSMC_IRQHandler
+ .thumb_set FSMC_IRQHandler,Default_Handler
+
+ .weak SDIO_IRQHandler
+ .thumb_set SDIO_IRQHandler,Default_Handler
+
+ .weak TIM5_IRQHandler
+ .thumb_set TIM5_IRQHandler,Default_Handler
+
+ .weak SPI3_IRQHandler
+ .thumb_set SPI3_IRQHandler,Default_Handler
+
+ .weak UART4_IRQHandler
+ .thumb_set UART4_IRQHandler,Default_Handler
+
+ .weak UART5_IRQHandler
+ .thumb_set UART5_IRQHandler,Default_Handler
+
+ .weak TIM6_IRQHandler
+ .thumb_set TIM6_IRQHandler,Default_Handler
+
+ .weak TIM7_IRQHandler
+ .thumb_set TIM7_IRQHandler,Default_Handler
+
+ .weak DMA2_Channel1_IRQHandler
+ .thumb_set DMA2_Channel1_IRQHandler,Default_Handler
+
+ .weak DMA2_Channel2_IRQHandler
+ .thumb_set DMA2_Channel2_IRQHandler,Default_Handler
+
+ .weak DMA2_Channel3_IRQHandler
+ .thumb_set DMA2_Channel3_IRQHandler,Default_Handler
+
+ .weak DMA2_Channel4_5_IRQHandler
+ .thumb_set DMA2_Channel4_5_IRQHandler,Default_Handler
+
+/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
diff --git a/Libraries/CMSIS/Device/ST/STM32F10x/Source/Templates/iar/startup_stm32f10x_cl.s b/Libraries/CMSIS/Device/ST/STM32F10x/Source/Templates/iar/startup_stm32f10x_cl.s
new file mode 100644
index 0000000..9c29765
--- /dev/null
+++ b/Libraries/CMSIS/Device/ST/STM32F10x/Source/Templates/iar/startup_stm32f10x_cl.s
@@ -0,0 +1,514 @@
+;******************** (C) COPYRIGHT 2012 STMicroelectronics *******************
+;* File Name : startup_stm32f10x_cl.s
+;* Author : MCD Application Team
+;* Version : V3.6.1
+;* Date : 09-March-2012
+;* Description : STM32F10x Connectivity line devices vector table for
+;* EWARM toolchain.
+;* This module performs:
+;* - Set the initial SP
+;* - Configure the clock system
+;* - Set the initial PC == __iar_program_start,
+;* - Set the vector table entries with the exceptions ISR
+;* address.
+;* After Reset the Cortex-M3 processor is in Thread mode,
+;* priority is Privileged, and the Stack is set to Main.
+;********************************************************************************
+;*
+;* Licensed under MCD-ST Liberty SW License Agreement V2, (the "License");
+;* You may not use this file except in compliance with the License.
+;* You may obtain a copy of the License at:
+;*
+;* http://www.st.com/software_license_agreement_liberty_v2
+;*
+;* Unless required by applicable law or agreed to in writing, software
+;* distributed under the License is distributed on an "AS IS" BASIS,
+;* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+;* See the License for the specific language governing permissions and
+;* limitations under the License.
+;*
+;*******************************************************************************
+;
+;
+; The modules in this file are included in the libraries, and may be replaced
+; by any user-defined modules that define the PUBLIC symbol _program_start or
+; a user defined start symbol.
+; To override the cstartup defined in the library, simply add your modified
+; version to the workbench project.
+;
+; The vector table is normally located at address 0.
+; When debugging in RAM, it can be located in RAM, aligned to at least 2^6.
+; The name "__vector_table" has special meaning for C-SPY:
+; it is where the SP start value is found, and the NVIC vector
+; table register (VTOR) is initialized to this address if != 0.
+;
+; Cortex-M version
+;
+
+ MODULE ?cstartup
+
+ ;; Forward declaration of sections.
+ SECTION CSTACK:DATA:NOROOT(3)
+
+ SECTION .intvec:CODE:NOROOT(2)
+
+ EXTERN __iar_program_start
+ EXTERN SystemInit
+ PUBLIC __vector_table
+
+ DATA
+__vector_table
+ DCD sfe(CSTACK)
+ DCD Reset_Handler ; Reset Handler
+ DCD NMI_Handler ; NMI Handler
+ DCD HardFault_Handler ; Hard Fault Handler
+ DCD MemManage_Handler ; MPU Fault Handler
+ DCD BusFault_Handler ; Bus Fault Handler
+ DCD UsageFault_Handler ; Usage Fault Handler
+ DCD 0 ; Reserved
+ DCD 0 ; Reserved
+ DCD 0 ; Reserved
+ DCD 0 ; Reserved
+ DCD SVC_Handler ; SVCall Handler
+ DCD DebugMon_Handler ; Debug Monitor Handler
+ DCD 0 ; Reserved
+ DCD PendSV_Handler ; PendSV Handler
+ DCD SysTick_Handler ; SysTick Handler
+
+ ; External Interrupts
+ DCD WWDG_IRQHandler ; Window Watchdog
+ DCD PVD_IRQHandler ; PVD through EXTI Line detect
+ DCD TAMPER_IRQHandler ; Tamper
+ DCD RTC_IRQHandler ; RTC
+ DCD FLASH_IRQHandler ; Flash
+ DCD RCC_IRQHandler ; RCC
+ DCD EXTI0_IRQHandler ; EXTI Line 0
+ DCD EXTI1_IRQHandler ; EXTI Line 1
+ DCD EXTI2_IRQHandler ; EXTI Line 2
+ DCD EXTI3_IRQHandler ; EXTI Line 3
+ DCD EXTI4_IRQHandler ; EXTI Line 4
+ DCD DMA1_Channel1_IRQHandler ; DMA1 Channel 1
+ DCD DMA1_Channel2_IRQHandler ; DMA1 Channel 2
+ DCD DMA1_Channel3_IRQHandler ; DMA1 Channel 3
+ DCD DMA1_Channel4_IRQHandler ; DMA1 Channel 4
+ DCD DMA1_Channel5_IRQHandler ; DMA1 Channel 5
+ DCD DMA1_Channel6_IRQHandler ; DMA1 Channel 6
+ DCD DMA1_Channel7_IRQHandler ; DMA1 Channel 7
+ DCD ADC1_2_IRQHandler ; ADC1 and ADC2
+ DCD CAN1_TX_IRQHandler ; CAN1 TX
+ DCD CAN1_RX0_IRQHandler ; CAN1 RX0
+ DCD CAN1_RX1_IRQHandler ; CAN1 RX1
+ DCD CAN1_SCE_IRQHandler ; CAN1 SCE
+ DCD EXTI9_5_IRQHandler ; EXTI Line 9..5
+ DCD TIM1_BRK_IRQHandler ; TIM1 Break
+ DCD TIM1_UP_IRQHandler ; TIM1 Update
+ DCD TIM1_TRG_COM_IRQHandler ; TIM1 Trigger and Commutation
+ DCD TIM1_CC_IRQHandler ; TIM1 Capture Compare
+ DCD TIM2_IRQHandler ; TIM2
+ DCD TIM3_IRQHandler ; TIM3
+ DCD TIM4_IRQHandler ; TIM4
+ DCD I2C1_EV_IRQHandler ; I2C1 Event
+ DCD I2C1_ER_IRQHandler ; I2C1 Error
+ DCD I2C2_EV_IRQHandler ; I2C2 Event
+ DCD I2C2_ER_IRQHandler ; I2C1 Error
+ DCD SPI1_IRQHandler ; SPI1
+ DCD SPI2_IRQHandler ; SPI2
+ DCD USART1_IRQHandler ; USART1
+ DCD USART2_IRQHandler ; USART2
+ DCD USART3_IRQHandler ; USART3
+ DCD EXTI15_10_IRQHandler ; EXTI Line 15..10
+ DCD RTCAlarm_IRQHandler ; RTC alarm through EXTI line
+ DCD OTG_FS_WKUP_IRQHandler ; USB OTG FS Wakeup through EXTI line
+ DCD 0 ; Reserved
+ DCD 0 ; Reserved
+ DCD 0 ; Reserved
+ DCD 0 ; Reserved
+ DCD 0 ; Reserved
+ DCD 0 ; Reserved
+ DCD 0 ; Reserved
+ DCD TIM5_IRQHandler ; TIM5
+ DCD SPI3_IRQHandler ; SPI3
+ DCD UART4_IRQHandler ; UART4
+ DCD UART5_IRQHandler ; UART5
+ DCD TIM6_IRQHandler ; TIM6
+ DCD TIM7_IRQHandler ; TIM7
+ DCD DMA2_Channel1_IRQHandler ; DMA2 Channel1
+ DCD DMA2_Channel2_IRQHandler ; DMA2 Channel2
+ DCD DMA2_Channel3_IRQHandler ; DMA2 Channel3
+ DCD DMA2_Channel4_IRQHandler ; DMA2 Channel4
+ DCD DMA2_Channel5_IRQHandler ; DMA2 Channel5
+ DCD ETH_IRQHandler ; Ethernet
+ DCD ETH_WKUP_IRQHandler ; Ethernet Wakeup through EXTI line
+ DCD CAN2_TX_IRQHandler ; CAN2 TX
+ DCD CAN2_RX0_IRQHandler ; CAN2 RX0
+ DCD CAN2_RX1_IRQHandler ; CAN2 RX1
+ DCD CAN2_SCE_IRQHandler ; CAN2 SCE
+ DCD OTG_FS_IRQHandler ; USB OTG FS
+
+;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
+;;
+;; Default interrupt handlers.
+;;
+ THUMB
+
+ PUBWEAK Reset_Handler
+ SECTION .text:CODE:REORDER(2)
+Reset_Handler
+ LDR R0, =SystemInit
+ BLX R0
+ LDR R0, =__iar_program_start
+ BX R0
+
+ PUBWEAK NMI_Handler
+ SECTION .text:CODE:REORDER(1)
+NMI_Handler
+ B NMI_Handler
+
+ PUBWEAK HardFault_Handler
+ SECTION .text:CODE:REORDER(1)
+HardFault_Handler
+ B HardFault_Handler
+
+ PUBWEAK MemManage_Handler
+ SECTION .text:CODE:REORDER(1)
+MemManage_Handler
+ B MemManage_Handler
+
+ PUBWEAK BusFault_Handler
+ SECTION .text:CODE:REORDER(1)
+BusFault_Handler
+ B BusFault_Handler
+
+ PUBWEAK UsageFault_Handler
+ SECTION .text:CODE:REORDER(1)
+UsageFault_Handler
+ B UsageFault_Handler
+
+ PUBWEAK SVC_Handler
+ SECTION .text:CODE:REORDER(1)
+SVC_Handler
+ B SVC_Handler
+
+ PUBWEAK DebugMon_Handler
+ SECTION .text:CODE:REORDER(1)
+DebugMon_Handler
+ B DebugMon_Handler
+
+ PUBWEAK PendSV_Handler
+ SECTION .text:CODE:REORDER(1)
+PendSV_Handler
+ B PendSV_Handler
+
+ PUBWEAK SysTick_Handler
+ SECTION .text:CODE:REORDER(1)
+SysTick_Handler
+ B SysTick_Handler
+
+ PUBWEAK WWDG_IRQHandler
+ SECTION .text:CODE:REORDER(1)
+WWDG_IRQHandler
+ B WWDG_IRQHandler
+
+ PUBWEAK PVD_IRQHandler
+ SECTION .text:CODE:REORDER(1)
+PVD_IRQHandler
+ B PVD_IRQHandler
+
+ PUBWEAK TAMPER_IRQHandler
+ SECTION .text:CODE:REORDER(1)
+TAMPER_IRQHandler
+ B TAMPER_IRQHandler
+
+ PUBWEAK RTC_IRQHandler
+ SECTION .text:CODE:REORDER(1)
+RTC_IRQHandler
+ B RTC_IRQHandler
+
+ PUBWEAK FLASH_IRQHandler
+ SECTION .text:CODE:REORDER(1)
+FLASH_IRQHandler
+ B FLASH_IRQHandler
+
+ PUBWEAK RCC_IRQHandler
+ SECTION .text:CODE:REORDER(1)
+RCC_IRQHandler
+ B RCC_IRQHandler
+
+ PUBWEAK EXTI0_IRQHandler
+ SECTION .text:CODE:REORDER(1)
+EXTI0_IRQHandler
+ B EXTI0_IRQHandler
+
+ PUBWEAK EXTI1_IRQHandler
+ SECTION .text:CODE:REORDER(1)
+EXTI1_IRQHandler
+ B EXTI1_IRQHandler
+
+ PUBWEAK EXTI2_IRQHandler
+ SECTION .text:CODE:REORDER(1)
+EXTI2_IRQHandler
+ B EXTI2_IRQHandler
+
+ PUBWEAK EXTI3_IRQHandler
+ SECTION .text:CODE:REORDER(1)
+EXTI3_IRQHandler
+ B EXTI3_IRQHandler
+
+
+ PUBWEAK EXTI4_IRQHandler
+ SECTION .text:CODE:REORDER(1)
+EXTI4_IRQHandler
+ B EXTI4_IRQHandler
+
+ PUBWEAK DMA1_Channel1_IRQHandler
+ SECTION .text:CODE:REORDER(1)
+DMA1_Channel1_IRQHandler
+ B DMA1_Channel1_IRQHandler
+
+ PUBWEAK DMA1_Channel2_IRQHandler
+ SECTION .text:CODE:REORDER(1)
+DMA1_Channel2_IRQHandler
+ B DMA1_Channel2_IRQHandler
+
+ PUBWEAK DMA1_Channel3_IRQHandler
+ SECTION .text:CODE:REORDER(1)
+DMA1_Channel3_IRQHandler
+ B DMA1_Channel3_IRQHandler
+
+ PUBWEAK DMA1_Channel4_IRQHandler
+ SECTION .text:CODE:REORDER(1)
+DMA1_Channel4_IRQHandler
+ B DMA1_Channel4_IRQHandler
+
+ PUBWEAK DMA1_Channel5_IRQHandler
+ SECTION .text:CODE:REORDER(1)
+DMA1_Channel5_IRQHandler
+ B DMA1_Channel5_IRQHandler
+
+ PUBWEAK DMA1_Channel6_IRQHandler
+ SECTION .text:CODE:REORDER(1)
+DMA1_Channel6_IRQHandler
+ B DMA1_Channel6_IRQHandler
+
+ PUBWEAK DMA1_Channel7_IRQHandler
+ SECTION .text:CODE:REORDER(1)
+DMA1_Channel7_IRQHandler
+ B DMA1_Channel7_IRQHandler
+
+ PUBWEAK ADC1_2_IRQHandler
+ SECTION .text:CODE:REORDER(1)
+ADC1_2_IRQHandler
+ B ADC1_2_IRQHandler
+
+ PUBWEAK CAN1_TX_IRQHandler
+ SECTION .text:CODE:REORDER(1)
+CAN1_TX_IRQHandler
+ B CAN1_TX_IRQHandler
+
+ PUBWEAK CAN1_RX0_IRQHandler
+ SECTION .text:CODE:REORDER(1)
+CAN1_RX0_IRQHandler
+ B CAN1_RX0_IRQHandler
+
+ PUBWEAK CAN1_RX1_IRQHandler
+ SECTION .text:CODE:REORDER(1)
+CAN1_RX1_IRQHandler
+ B CAN1_RX1_IRQHandler
+
+ PUBWEAK CAN1_SCE_IRQHandler
+ SECTION .text:CODE:REORDER(1)
+CAN1_SCE_IRQHandler
+ B CAN1_SCE_IRQHandler
+
+ PUBWEAK EXTI9_5_IRQHandler
+ SECTION .text:CODE:REORDER(1)
+EXTI9_5_IRQHandler
+ B EXTI9_5_IRQHandler
+
+ PUBWEAK TIM1_BRK_IRQHandler
+ SECTION .text:CODE:REORDER(1)
+TIM1_BRK_IRQHandler
+ B TIM1_BRK_IRQHandler
+
+ PUBWEAK TIM1_UP_IRQHandler
+ SECTION .text:CODE:REORDER(1)
+TIM1_UP_IRQHandler
+ B TIM1_UP_IRQHandler
+
+ PUBWEAK TIM1_TRG_COM_IRQHandler
+ SECTION .text:CODE:REORDER(1)
+TIM1_TRG_COM_IRQHandler
+ B TIM1_TRG_COM_IRQHandler
+
+ PUBWEAK TIM1_CC_IRQHandler
+ SECTION .text:CODE:REORDER(1)
+TIM1_CC_IRQHandler
+ B TIM1_CC_IRQHandler
+
+ PUBWEAK TIM2_IRQHandler
+ SECTION .text:CODE:REORDER(1)
+TIM2_IRQHandler
+ B TIM2_IRQHandler
+
+ PUBWEAK TIM3_IRQHandler
+ SECTION .text:CODE:REORDER(1)
+TIM3_IRQHandler
+ B TIM3_IRQHandler
+
+ PUBWEAK TIM4_IRQHandler
+ SECTION .text:CODE:REORDER(1)
+TIM4_IRQHandler
+ B TIM4_IRQHandler
+
+ PUBWEAK I2C1_EV_IRQHandler
+ SECTION .text:CODE:REORDER(1)
+I2C1_EV_IRQHandler
+ B I2C1_EV_IRQHandler
+
+ PUBWEAK I2C1_ER_IRQHandler
+ SECTION .text:CODE:REORDER(1)
+I2C1_ER_IRQHandler
+ B I2C1_ER_IRQHandler
+
+ PUBWEAK I2C2_EV_IRQHandler
+ SECTION .text:CODE:REORDER(1)
+I2C2_EV_IRQHandler
+ B I2C2_EV_IRQHandler
+
+ PUBWEAK I2C2_ER_IRQHandler
+ SECTION .text:CODE:REORDER(1)
+I2C2_ER_IRQHandler
+ B I2C2_ER_IRQHandler
+
+ PUBWEAK SPI1_IRQHandler
+ SECTION .text:CODE:REORDER(1)
+SPI1_IRQHandler
+ B SPI1_IRQHandler
+
+ PUBWEAK SPI2_IRQHandler
+ SECTION .text:CODE:REORDER(1)
+SPI2_IRQHandler
+ B SPI2_IRQHandler
+
+ PUBWEAK USART1_IRQHandler
+ SECTION .text:CODE:REORDER(1)
+USART1_IRQHandler
+ B USART1_IRQHandler
+
+ PUBWEAK USART2_IRQHandler
+ SECTION .text:CODE:REORDER(1)
+USART2_IRQHandler
+ B USART2_IRQHandler
+
+ PUBWEAK USART3_IRQHandler
+ SECTION .text:CODE:REORDER(1)
+USART3_IRQHandler
+ B USART3_IRQHandler
+
+ PUBWEAK EXTI15_10_IRQHandler
+ SECTION .text:CODE:REORDER(1)
+EXTI15_10_IRQHandler
+ B EXTI15_10_IRQHandler
+
+ PUBWEAK RTCAlarm_IRQHandler
+ SECTION .text:CODE:REORDER(1)
+RTCAlarm_IRQHandler
+ B RTCAlarm_IRQHandler
+
+ PUBWEAK OTG_FS_WKUP_IRQHandler
+ SECTION .text:CODE:REORDER(1)
+OTG_FS_WKUP_IRQHandler
+ B OTG_FS_WKUP_IRQHandler
+
+ PUBWEAK TIM5_IRQHandler
+ SECTION .text:CODE:REORDER(1)
+TIM5_IRQHandler
+ B TIM5_IRQHandler
+
+ PUBWEAK SPI3_IRQHandler
+ SECTION .text:CODE:REORDER(1)
+SPI3_IRQHandler
+ B SPI3_IRQHandler
+
+ PUBWEAK UART4_IRQHandler
+ SECTION .text:CODE:REORDER(1)
+UART4_IRQHandler
+ B UART4_IRQHandler
+
+ PUBWEAK UART5_IRQHandler
+ SECTION .text:CODE:REORDER(1)
+UART5_IRQHandler
+ B UART5_IRQHandler
+
+ PUBWEAK TIM6_IRQHandler
+ SECTION .text:CODE:REORDER(1)
+TIM6_IRQHandler
+ B TIM6_IRQHandler
+
+ PUBWEAK TIM7_IRQHandler
+ SECTION .text:CODE:REORDER(1)
+TIM7_IRQHandler
+ B TIM7_IRQHandler
+
+ PUBWEAK DMA2_Channel1_IRQHandler
+ SECTION .text:CODE:REORDER(1)
+DMA2_Channel1_IRQHandler
+ B DMA2_Channel1_IRQHandler
+
+ PUBWEAK DMA2_Channel2_IRQHandler
+ SECTION .text:CODE:REORDER(1)
+DMA2_Channel2_IRQHandler
+ B DMA2_Channel2_IRQHandler
+
+ PUBWEAK DMA2_Channel3_IRQHandler
+ SECTION .text:CODE:REORDER(1)
+DMA2_Channel3_IRQHandler
+ B DMA2_Channel3_IRQHandler
+
+ PUBWEAK DMA2_Channel4_IRQHandler
+ SECTION .text:CODE:REORDER(1)
+DMA2_Channel4_IRQHandler
+ B DMA2_Channel4_IRQHandler
+
+ PUBWEAK DMA2_Channel5_IRQHandler
+ SECTION .text:CODE:REORDER(1)
+DMA2_Channel5_IRQHandler
+ B DMA2_Channel5_IRQHandler
+
+ PUBWEAK ETH_IRQHandler
+ SECTION .text:CODE:REORDER(1)
+ETH_IRQHandler
+ B ETH_IRQHandler
+
+ PUBWEAK ETH_WKUP_IRQHandler
+ SECTION .text:CODE:REORDER(1)
+ETH_WKUP_IRQHandler
+ B ETH_WKUP_IRQHandler
+
+ PUBWEAK CAN2_TX_IRQHandler
+ SECTION .text:CODE:REORDER(1)
+CAN2_TX_IRQHandler
+ B CAN2_TX_IRQHandler
+
+ PUBWEAK CAN2_RX0_IRQHandler
+ SECTION .text:CODE:REORDER(1)
+CAN2_RX0_IRQHandler
+ B CAN2_RX0_IRQHandler
+
+ PUBWEAK CAN2_RX1_IRQHandler
+ SECTION .text:CODE:REORDER(1)
+CAN2_RX1_IRQHandler
+ B CAN2_RX1_IRQHandler
+
+ PUBWEAK CAN2_SCE_IRQHandler
+ SECTION .text:CODE:REORDER(1)
+CAN2_SCE_IRQHandler
+ B CAN2_SCE_IRQHandler
+
+ PUBWEAK OTG_FS_IRQHandler
+ SECTION .text:CODE:REORDER(1)
+OTG_FS_IRQHandler
+ B OTG_FS_IRQHandler
+
+ END
+/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
diff --git a/Libraries/CMSIS/Device/ST/STM32F10x/Source/Templates/iar/startup_stm32f10x_hd.s b/Libraries/CMSIS/Device/ST/STM32F10x/Source/Templates/iar/startup_stm32f10x_hd.s
new file mode 100644
index 0000000..4af1336
--- /dev/null
+++ b/Libraries/CMSIS/Device/ST/STM32F10x/Source/Templates/iar/startup_stm32f10x_hd.s
@@ -0,0 +1,503 @@
+;******************** (C) COPYRIGHT 2012 STMicroelectronics ********************
+;* File Name : startup_stm32f10x_hd.s
+;* Author : MCD Application Team
+;* Version : V3.6.1
+;* Date : 09-March-2012
+;* Description : STM32F10x High Density Devices vector table for EWARM
+;* toolchain.
+;* This module performs:
+;* - Set the initial SP
+;* - Configure the clock system and the external SRAM
+;* mounted on STM3210E-EVAL board to be used as data
+;* memory (optional, to be enabled by user)
+;* - Set the initial PC == __iar_program_start,
+;* - Set the vector table entries with the exceptions ISR address,
+;* After Reset the Cortex-M3 processor is in Thread mode,
+;* priority is Privileged, and the Stack is set to Main.
+;********************************************************************************
+;*
+;* Licensed under MCD-ST Liberty SW License Agreement V2, (the "License");
+;* You may not use this file except in compliance with the License.
+;* You may obtain a copy of the License at:
+;*
+;* http://www.st.com/software_license_agreement_liberty_v2
+;*
+;* Unless required by applicable law or agreed to in writing, software
+;* distributed under the License is distributed on an "AS IS" BASIS,
+;* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+;* See the License for the specific language governing permissions and
+;* limitations under the License.
+;*
+;*******************************************************************************
+;
+;
+; The modules in this file are included in the libraries, and may be replaced
+; by any user-defined modules that define the PUBLIC symbol _program_start or
+; a user defined start symbol.
+; To override the cstartup defined in the library, simply add your modified
+; version to the workbench project.
+;
+; The vector table is normally located at address 0.
+; When debugging in RAM, it can be located in RAM, aligned to at least 2^6.
+; The name "__vector_table" has special meaning for C-SPY:
+; it is where the SP start value is found, and the NVIC vector
+; table register (VTOR) is initialized to this address if != 0.
+;
+; Cortex-M version
+;
+
+ MODULE ?cstartup
+
+ ;; Forward declaration of sections.
+ SECTION CSTACK:DATA:NOROOT(3)
+
+ SECTION .intvec:CODE:NOROOT(2)
+
+ EXTERN __iar_program_start
+ EXTERN SystemInit
+ PUBLIC __vector_table
+
+ DATA
+
+__vector_table
+ DCD sfe(CSTACK)
+ DCD Reset_Handler ; Reset Handler
+ DCD NMI_Handler ; NMI Handler
+ DCD HardFault_Handler ; Hard Fault Handler
+ DCD MemManage_Handler ; MPU Fault Handler
+ DCD BusFault_Handler ; Bus Fault Handler
+ DCD UsageFault_Handler ; Usage Fault Handler
+ DCD 0 ; Reserved
+ DCD 0 ; Reserved
+ DCD 0 ; Reserved
+ DCD 0 ; Reserved
+ DCD SVC_Handler ; SVCall Handler
+ DCD DebugMon_Handler ; Debug Monitor Handler
+ DCD 0 ; Reserved
+ DCD PendSV_Handler ; PendSV Handler
+ DCD SysTick_Handler ; SysTick Handler
+
+ ; External Interrupts
+ DCD WWDG_IRQHandler ; Window Watchdog
+ DCD PVD_IRQHandler ; PVD through EXTI Line detect
+ DCD TAMPER_IRQHandler ; Tamper
+ DCD RTC_IRQHandler ; RTC
+ DCD FLASH_IRQHandler ; Flash
+ DCD RCC_IRQHandler ; RCC
+ DCD EXTI0_IRQHandler ; EXTI Line 0
+ DCD EXTI1_IRQHandler ; EXTI Line 1
+ DCD EXTI2_IRQHandler ; EXTI Line 2
+ DCD EXTI3_IRQHandler ; EXTI Line 3
+ DCD EXTI4_IRQHandler ; EXTI Line 4
+ DCD DMA1_Channel1_IRQHandler ; DMA1 Channel 1
+ DCD DMA1_Channel2_IRQHandler ; DMA1 Channel 2
+ DCD DMA1_Channel3_IRQHandler ; DMA1 Channel 3
+ DCD DMA1_Channel4_IRQHandler ; DMA1 Channel 4
+ DCD DMA1_Channel5_IRQHandler ; DMA1 Channel 5
+ DCD DMA1_Channel6_IRQHandler ; DMA1 Channel 6
+ DCD DMA1_Channel7_IRQHandler ; DMA1 Channel 7
+ DCD ADC1_2_IRQHandler ; ADC1 & ADC2
+ DCD USB_HP_CAN1_TX_IRQHandler ; USB High Priority or CAN1 TX
+ DCD USB_LP_CAN1_RX0_IRQHandler ; USB Low Priority or CAN1 RX0
+ DCD CAN1_RX1_IRQHandler ; CAN1 RX1
+ DCD CAN1_SCE_IRQHandler ; CAN1 SCE
+ DCD EXTI9_5_IRQHandler ; EXTI Line 9..5
+ DCD TIM1_BRK_IRQHandler ; TIM1 Break
+ DCD TIM1_UP_IRQHandler ; TIM1 Update
+ DCD TIM1_TRG_COM_IRQHandler ; TIM1 Trigger and Commutation
+ DCD TIM1_CC_IRQHandler ; TIM1 Capture Compare
+ DCD TIM2_IRQHandler ; TIM2
+ DCD TIM3_IRQHandler ; TIM3
+ DCD TIM4_IRQHandler ; TIM4
+ DCD I2C1_EV_IRQHandler ; I2C1 Event
+ DCD I2C1_ER_IRQHandler ; I2C1 Error
+ DCD I2C2_EV_IRQHandler ; I2C2 Event
+ DCD I2C2_ER_IRQHandler ; I2C2 Error
+ DCD SPI1_IRQHandler ; SPI1
+ DCD SPI2_IRQHandler ; SPI2
+ DCD USART1_IRQHandler ; USART1
+ DCD USART2_IRQHandler ; USART2
+ DCD USART3_IRQHandler ; USART3
+ DCD EXTI15_10_IRQHandler ; EXTI Line 15..10
+ DCD RTCAlarm_IRQHandler ; RTC Alarm through EXTI Line
+ DCD USBWakeUp_IRQHandler ; USB Wakeup from suspend
+ DCD TIM8_BRK_IRQHandler ; TIM8 Break
+ DCD TIM8_UP_IRQHandler ; TIM8 Update
+ DCD TIM8_TRG_COM_IRQHandler ; TIM8 Trigger and Commutation
+ DCD TIM8_CC_IRQHandler ; TIM8 Capture Compare
+ DCD ADC3_IRQHandler ; ADC3
+ DCD FSMC_IRQHandler ; FSMC
+ DCD SDIO_IRQHandler ; SDIO
+ DCD TIM5_IRQHandler ; TIM5
+ DCD SPI3_IRQHandler ; SPI3
+ DCD UART4_IRQHandler ; UART4
+ DCD UART5_IRQHandler ; UART5
+ DCD TIM6_IRQHandler ; TIM6
+ DCD TIM7_IRQHandler ; TIM7
+ DCD DMA2_Channel1_IRQHandler ; DMA2 Channel1
+ DCD DMA2_Channel2_IRQHandler ; DMA2 Channel2
+ DCD DMA2_Channel3_IRQHandler ; DMA2 Channel3
+ DCD DMA2_Channel4_5_IRQHandler ; DMA2 Channel4 & Channel5
+;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
+;;
+;; Default interrupt handlers.
+;;
+ THUMB
+
+ PUBWEAK Reset_Handler
+ SECTION .text:CODE:REORDER(2)
+Reset_Handler
+ LDR R0, =SystemInit
+ BLX R0
+ LDR R0, =__iar_program_start
+ BX R0
+
+ PUBWEAK NMI_Handler
+ SECTION .text:CODE:REORDER(1)
+NMI_Handler
+ B NMI_Handler
+
+ PUBWEAK HardFault_Handler
+ SECTION .text:CODE:REORDER(1)
+HardFault_Handler
+ B HardFault_Handler
+
+ PUBWEAK MemManage_Handler
+ SECTION .text:CODE:REORDER(1)
+MemManage_Handler
+ B MemManage_Handler
+
+ PUBWEAK BusFault_Handler
+ SECTION .text:CODE:REORDER(1)
+BusFault_Handler
+ B BusFault_Handler
+
+ PUBWEAK UsageFault_Handler
+ SECTION .text:CODE:REORDER(1)
+UsageFault_Handler
+ B UsageFault_Handler
+
+ PUBWEAK SVC_Handler
+ SECTION .text:CODE:REORDER(1)
+SVC_Handler
+ B SVC_Handler
+
+ PUBWEAK DebugMon_Handler
+ SECTION .text:CODE:REORDER(1)
+DebugMon_Handler
+ B DebugMon_Handler
+
+ PUBWEAK PendSV_Handler
+ SECTION .text:CODE:REORDER(1)
+PendSV_Handler
+ B PendSV_Handler
+
+ PUBWEAK SysTick_Handler
+ SECTION .text:CODE:REORDER(1)
+SysTick_Handler
+ B SysTick_Handler
+
+ PUBWEAK WWDG_IRQHandler
+ SECTION .text:CODE:REORDER(1)
+WWDG_IRQHandler
+ B WWDG_IRQHandler
+
+ PUBWEAK PVD_IRQHandler
+ SECTION .text:CODE:REORDER(1)
+PVD_IRQHandler
+ B PVD_IRQHandler
+
+ PUBWEAK TAMPER_IRQHandler
+ SECTION .text:CODE:REORDER(1)
+TAMPER_IRQHandler
+ B TAMPER_IRQHandler
+
+ PUBWEAK RTC_IRQHandler
+ SECTION .text:CODE:REORDER(1)
+RTC_IRQHandler
+ B RTC_IRQHandler
+
+ PUBWEAK FLASH_IRQHandler
+ SECTION .text:CODE:REORDER(1)
+FLASH_IRQHandler
+ B FLASH_IRQHandler
+
+ PUBWEAK RCC_IRQHandler
+ SECTION .text:CODE:REORDER(1)
+RCC_IRQHandler
+ B RCC_IRQHandler
+
+ PUBWEAK EXTI0_IRQHandler
+ SECTION .text:CODE:REORDER(1)
+EXTI0_IRQHandler
+ B EXTI0_IRQHandler
+
+ PUBWEAK EXTI1_IRQHandler
+ SECTION .text:CODE:REORDER(1)
+EXTI1_IRQHandler
+ B EXTI1_IRQHandler
+
+ PUBWEAK EXTI2_IRQHandler
+ SECTION .text:CODE:REORDER(1)
+EXTI2_IRQHandler
+ B EXTI2_IRQHandler
+
+ PUBWEAK EXTI3_IRQHandler
+ SECTION .text:CODE:REORDER(1)
+EXTI3_IRQHandler
+ B EXTI3_IRQHandler
+
+ PUBWEAK EXTI4_IRQHandler
+ SECTION .text:CODE:REORDER(1)
+EXTI4_IRQHandler
+ B EXTI4_IRQHandler
+
+ PUBWEAK DMA1_Channel1_IRQHandler
+ SECTION .text:CODE:REORDER(1)
+DMA1_Channel1_IRQHandler
+ B DMA1_Channel1_IRQHandler
+
+ PUBWEAK DMA1_Channel2_IRQHandler
+ SECTION .text:CODE:REORDER(1)
+DMA1_Channel2_IRQHandler
+ B DMA1_Channel2_IRQHandler
+
+ PUBWEAK DMA1_Channel3_IRQHandler
+ SECTION .text:CODE:REORDER(1)
+DMA1_Channel3_IRQHandler
+ B DMA1_Channel3_IRQHandler
+
+ PUBWEAK DMA1_Channel4_IRQHandler
+ SECTION .text:CODE:REORDER(1)
+DMA1_Channel4_IRQHandler
+ B DMA1_Channel4_IRQHandler
+
+ PUBWEAK DMA1_Channel5_IRQHandler
+ SECTION .text:CODE:REORDER(1)
+DMA1_Channel5_IRQHandler
+ B DMA1_Channel5_IRQHandler
+
+ PUBWEAK DMA1_Channel6_IRQHandler
+ SECTION .text:CODE:REORDER(1)
+DMA1_Channel6_IRQHandler
+ B DMA1_Channel6_IRQHandler
+
+ PUBWEAK DMA1_Channel7_IRQHandler
+ SECTION .text:CODE:REORDER(1)
+DMA1_Channel7_IRQHandler
+ B DMA1_Channel7_IRQHandler
+
+ PUBWEAK ADC1_2_IRQHandler
+ SECTION .text:CODE:REORDER(1)
+ADC1_2_IRQHandler
+ B ADC1_2_IRQHandler
+
+ PUBWEAK USB_HP_CAN1_TX_IRQHandler
+ SECTION .text:CODE:REORDER(1)
+USB_HP_CAN1_TX_IRQHandler
+ B USB_HP_CAN1_TX_IRQHandler
+
+ PUBWEAK USB_LP_CAN1_RX0_IRQHandler
+ SECTION .text:CODE:REORDER(1)
+USB_LP_CAN1_RX0_IRQHandler
+ B USB_LP_CAN1_RX0_IRQHandler
+
+ PUBWEAK CAN1_RX1_IRQHandler
+ SECTION .text:CODE:REORDER(1)
+CAN1_RX1_IRQHandler
+ B CAN1_RX1_IRQHandler
+
+ PUBWEAK CAN1_SCE_IRQHandler
+ SECTION .text:CODE:REORDER(1)
+CAN1_SCE_IRQHandler
+ B CAN1_SCE_IRQHandler
+
+ PUBWEAK EXTI9_5_IRQHandler
+ SECTION .text:CODE:REORDER(1)
+EXTI9_5_IRQHandler
+ B EXTI9_5_IRQHandler
+
+ PUBWEAK TIM1_BRK_IRQHandler
+ SECTION .text:CODE:REORDER(1)
+TIM1_BRK_IRQHandler
+ B TIM1_BRK_IRQHandler
+
+ PUBWEAK TIM1_UP_IRQHandler
+ SECTION .text:CODE:REORDER(1)
+TIM1_UP_IRQHandler
+ B TIM1_UP_IRQHandler
+
+ PUBWEAK TIM1_TRG_COM_IRQHandler
+ SECTION .text:CODE:REORDER(1)
+TIM1_TRG_COM_IRQHandler
+ B TIM1_TRG_COM_IRQHandler
+
+ PUBWEAK TIM1_CC_IRQHandler
+ SECTION .text:CODE:REORDER(1)
+TIM1_CC_IRQHandler
+ B TIM1_CC_IRQHandler
+
+ PUBWEAK TIM2_IRQHandler
+ SECTION .text:CODE:REORDER(1)
+TIM2_IRQHandler
+ B TIM2_IRQHandler
+
+ PUBWEAK TIM3_IRQHandler
+ SECTION .text:CODE:REORDER(1)
+TIM3_IRQHandler
+ B TIM3_IRQHandler
+
+ PUBWEAK TIM4_IRQHandler
+ SECTION .text:CODE:REORDER(1)
+TIM4_IRQHandler
+ B TIM4_IRQHandler
+
+ PUBWEAK I2C1_EV_IRQHandler
+ SECTION .text:CODE:REORDER(1)
+I2C1_EV_IRQHandler
+ B I2C1_EV_IRQHandler
+
+ PUBWEAK I2C1_ER_IRQHandler
+ SECTION .text:CODE:REORDER(1)
+I2C1_ER_IRQHandler
+ B I2C1_ER_IRQHandler
+
+ PUBWEAK I2C2_EV_IRQHandler
+ SECTION .text:CODE:REORDER(1)
+I2C2_EV_IRQHandler
+ B I2C2_EV_IRQHandler
+
+ PUBWEAK I2C2_ER_IRQHandler
+ SECTION .text:CODE:REORDER(1)
+I2C2_ER_IRQHandler
+ B I2C2_ER_IRQHandler
+
+ PUBWEAK SPI1_IRQHandler
+ SECTION .text:CODE:REORDER(1)
+SPI1_IRQHandler
+ B SPI1_IRQHandler
+
+ PUBWEAK SPI2_IRQHandler
+ SECTION .text:CODE:REORDER(1)
+SPI2_IRQHandler
+ B SPI2_IRQHandler
+
+ PUBWEAK USART1_IRQHandler
+ SECTION .text:CODE:REORDER(1)
+USART1_IRQHandler
+ B USART1_IRQHandler
+
+ PUBWEAK USART2_IRQHandler
+ SECTION .text:CODE:REORDER(1)
+USART2_IRQHandler
+ B USART2_IRQHandler
+
+ PUBWEAK USART3_IRQHandler
+ SECTION .text:CODE:REORDER(1)
+USART3_IRQHandler
+ B USART3_IRQHandler
+
+ PUBWEAK EXTI15_10_IRQHandler
+ SECTION .text:CODE:REORDER(1)
+EXTI15_10_IRQHandler
+ B EXTI15_10_IRQHandler
+
+ PUBWEAK RTCAlarm_IRQHandler
+ SECTION .text:CODE:REORDER(1)
+RTCAlarm_IRQHandler
+ B RTCAlarm_IRQHandler
+
+ PUBWEAK USBWakeUp_IRQHandler
+ SECTION .text:CODE:REORDER(1)
+USBWakeUp_IRQHandler
+ B USBWakeUp_IRQHandler
+
+ PUBWEAK TIM8_BRK_IRQHandler
+ SECTION .text:CODE:REORDER(1)
+TIM8_BRK_IRQHandler
+ B TIM8_BRK_IRQHandler
+
+ PUBWEAK TIM8_UP_IRQHandler
+ SECTION .text:CODE:REORDER(1)
+TIM8_UP_IRQHandler
+ B TIM8_UP_IRQHandler
+
+ PUBWEAK TIM8_TRG_COM_IRQHandler
+ SECTION .text:CODE:REORDER(1)
+TIM8_TRG_COM_IRQHandler
+ B TIM8_TRG_COM_IRQHandler
+
+ PUBWEAK TIM8_CC_IRQHandler
+ SECTION .text:CODE:REORDER(1)
+TIM8_CC_IRQHandler
+ B TIM8_CC_IRQHandler
+
+ PUBWEAK ADC3_IRQHandler
+ SECTION .text:CODE:REORDER(1)
+ADC3_IRQHandler
+ B ADC3_IRQHandler
+
+ PUBWEAK FSMC_IRQHandler
+ SECTION .text:CODE:REORDER(1)
+FSMC_IRQHandler
+ B FSMC_IRQHandler
+
+ PUBWEAK SDIO_IRQHandler
+ SECTION .text:CODE:REORDER(1)
+SDIO_IRQHandler
+ B SDIO_IRQHandler
+
+ PUBWEAK TIM5_IRQHandler
+ SECTION .text:CODE:REORDER(1)
+TIM5_IRQHandler
+ B TIM5_IRQHandler
+
+ PUBWEAK SPI3_IRQHandler
+ SECTION .text:CODE:REORDER(1)
+SPI3_IRQHandler
+ B SPI3_IRQHandler
+
+ PUBWEAK UART4_IRQHandler
+ SECTION .text:CODE:REORDER(1)
+UART4_IRQHandler
+ B UART4_IRQHandler
+
+ PUBWEAK UART5_IRQHandler
+ SECTION .text:CODE:REORDER(1)
+UART5_IRQHandler
+ B UART5_IRQHandler
+
+ PUBWEAK TIM6_IRQHandler
+ SECTION .text:CODE:REORDER(1)
+TIM6_IRQHandler
+ B TIM6_IRQHandler
+
+ PUBWEAK TIM7_IRQHandler
+ SECTION .text:CODE:REORDER(1)
+TIM7_IRQHandler
+ B TIM7_IRQHandler
+
+ PUBWEAK DMA2_Channel1_IRQHandler
+ SECTION .text:CODE:REORDER(1)
+DMA2_Channel1_IRQHandler
+ B DMA2_Channel1_IRQHandler
+
+ PUBWEAK DMA2_Channel2_IRQHandler
+ SECTION .text:CODE:REORDER(1)
+DMA2_Channel2_IRQHandler
+ B DMA2_Channel2_IRQHandler
+
+ PUBWEAK DMA2_Channel3_IRQHandler
+ SECTION .text:CODE:REORDER(1)
+DMA2_Channel3_IRQHandler
+ B DMA2_Channel3_IRQHandler
+
+ PUBWEAK DMA2_Channel4_5_IRQHandler
+ SECTION .text:CODE:REORDER(1)
+DMA2_Channel4_5_IRQHandler
+ B DMA2_Channel4_5_IRQHandler
+
+
+ END
+
+/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
diff --git a/Libraries/CMSIS/Device/ST/STM32F10x/Source/Templates/iar/startup_stm32f10x_hd_vl.s b/Libraries/CMSIS/Device/ST/STM32F10x/Source/Templates/iar/startup_stm32f10x_hd_vl.s
new file mode 100644
index 0000000..7390a93
--- /dev/null
+++ b/Libraries/CMSIS/Device/ST/STM32F10x/Source/Templates/iar/startup_stm32f10x_hd_vl.s
@@ -0,0 +1,468 @@
+;******************** (C) COPYRIGHT 2012 STMicroelectronics ********************
+;* File Name : startup_stm32f10x_hd_vl.s
+;* Author : MCD Application Team
+;* Version : V3.6.1
+;* Date : 09-March-2012
+;* Description : STM32F10x High Density Value Line Devices vector table
+;* for EWARM toolchain.
+;* This module performs:
+;* - Set the initial SP
+;* - Configure the clock system and the external SRAM
+;* mounted on STM32100E-EVAL board to be used as data
+;* memory (optional, to be enabled by user)
+;* - Set the initial PC == __iar_program_start,
+;* - Set the vector table entries with the exceptions ISR
+;* address.
+;* After Reset the Cortex-M3 processor is in Thread mode,
+;* priority is Privileged, and the Stack is set to Main.
+;********************************************************************************
+;*
+;* Licensed under MCD-ST Liberty SW License Agreement V2, (the "License");
+;* You may not use this file except in compliance with the License.
+;* You may obtain a copy of the License at:
+;*
+;* http://www.st.com/software_license_agreement_liberty_v2
+;*
+;* Unless required by applicable law or agreed to in writing, software
+;* distributed under the License is distributed on an "AS IS" BASIS,
+;* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+;* See the License for the specific language governing permissions and
+;* limitations under the License.
+;*
+;*******************************************************************************
+;
+;
+; The modules in this file are included in the libraries, and may be replaced
+; by any user-defined modules that define the PUBLIC symbol _program_start or
+; a user defined start symbol.
+; To override the cstartup defined in the library, simply add your modified
+; version to the workbench project.
+;
+; The vector table is normally located at address 0.
+; When debugging in RAM, it can be located in RAM, aligned to at least 2^6.
+; The name "__vector_table" has special meaning for C-SPY:
+; it is where the SP start value is found, and the NVIC vector
+; table register (VTOR) is initialized to this address if != 0.
+;
+; Cortex-M version
+;
+
+ MODULE ?cstartup
+
+ ;; Forward declaration of sections.
+ SECTION CSTACK:DATA:NOROOT(3)
+
+ SECTION .intvec:CODE:NOROOT(2)
+
+ EXTERN __iar_program_start
+ EXTERN SystemInit
+ PUBLIC __vector_table
+
+ DATA
+__vector_table
+ DCD sfe(CSTACK)
+ DCD Reset_Handler ; Reset Handler
+ DCD NMI_Handler ; NMI Handler
+ DCD HardFault_Handler ; Hard Fault Handler
+ DCD MemManage_Handler ; MPU Fault Handler
+ DCD BusFault_Handler ; Bus Fault Handler
+ DCD UsageFault_Handler ; Usage Fault Handler
+ DCD 0 ; Reserved
+ DCD 0 ; Reserved
+ DCD 0 ; Reserved
+ DCD 0 ; Reserved
+ DCD SVC_Handler ; SVCall Handler
+ DCD DebugMon_Handler ; Debug Monitor Handler
+ DCD 0 ; Reserved
+ DCD PendSV_Handler ; PendSV Handler
+ DCD SysTick_Handler ; SysTick Handler
+
+ ; External Interrupts
+ DCD WWDG_IRQHandler ; Window Watchdog
+ DCD PVD_IRQHandler ; PVD through EXTI Line detect
+ DCD TAMPER_IRQHandler ; Tamper
+ DCD RTC_IRQHandler ; RTC
+ DCD FLASH_IRQHandler ; Flash
+ DCD RCC_IRQHandler ; RCC
+ DCD EXTI0_IRQHandler ; EXTI Line 0
+ DCD EXTI1_IRQHandler ; EXTI Line 1
+ DCD EXTI2_IRQHandler ; EXTI Line 2
+ DCD EXTI3_IRQHandler ; EXTI Line 3
+ DCD EXTI4_IRQHandler ; EXTI Line 4
+ DCD DMA1_Channel1_IRQHandler ; DMA1 Channel 1
+ DCD DMA1_Channel2_IRQHandler ; DMA1 Channel 2
+ DCD DMA1_Channel3_IRQHandler ; DMA1 Channel 3
+ DCD DMA1_Channel4_IRQHandler ; DMA1 Channel 4
+ DCD DMA1_Channel5_IRQHandler ; DMA1 Channel 5
+ DCD DMA1_Channel6_IRQHandler ; DMA1 Channel 6
+ DCD DMA1_Channel7_IRQHandler ; DMA1 Channel 7
+ DCD ADC1_IRQHandler ; ADC1
+ DCD 0 ; Reserved
+ DCD 0 ; Reserved
+ DCD 0 ; Reserved
+ DCD 0 ; Reserved
+ DCD EXTI9_5_IRQHandler ; EXTI Line 9..5
+ DCD TIM1_BRK_TIM15_IRQHandler ; TIM1 Break and TIM15
+ DCD TIM1_UP_TIM16_IRQHandler ; TIM1 Update and TIM16
+ DCD TIM1_TRG_COM_TIM17_IRQHandler ; TIM1 Trigger and Commutation and TIM17
+ DCD TIM1_CC_IRQHandler ; TIM1 Capture Compare
+ DCD TIM2_IRQHandler ; TIM2
+ DCD TIM3_IRQHandler ; TIM3
+ DCD TIM4_IRQHandler ; TIM4
+ DCD I2C1_EV_IRQHandler ; I2C1 Event
+ DCD I2C1_ER_IRQHandler ; I2C1 Error
+ DCD I2C2_EV_IRQHandler ; I2C2 Event
+ DCD I2C2_ER_IRQHandler ; I2C2 Error
+ DCD SPI1_IRQHandler ; SPI1
+ DCD SPI2_IRQHandler ; SPI2
+ DCD USART1_IRQHandler ; USART1
+ DCD USART2_IRQHandler ; USART2
+ DCD USART3_IRQHandler ; USART3
+ DCD EXTI15_10_IRQHandler ; EXTI Line 15..10
+ DCD RTCAlarm_IRQHandler ; RTC Alarm through EXTI Line
+ DCD CEC_IRQHandler ; HDMI-CEC
+ DCD TIM12_IRQHandler ; TIM12
+ DCD TIM13_IRQHandler ; TIM13
+ DCD TIM14_IRQHandler ; TIM14
+ DCD 0 ; Reserved
+ DCD 0 ; Reserved
+ DCD 0 ; Reserved
+ DCD 0 ; Reserved
+ DCD TIM5_IRQHandler ; TIM5
+ DCD SPI3_IRQHandler ; SPI3
+ DCD UART4_IRQHandler ; UART4
+ DCD UART5_IRQHandler ; UART5
+ DCD TIM6_DAC_IRQHandler ; TIM6 and DAC underrun
+ DCD TIM7_IRQHandler ; TIM7
+ DCD DMA2_Channel1_IRQHandler ; DMA2 Channel1
+ DCD DMA2_Channel2_IRQHandler ; DMA2 Channel2
+ DCD DMA2_Channel3_IRQHandler ; DMA2 Channel3
+ DCD DMA2_Channel4_5_IRQHandler ; DMA2 Channel4 & Channel5
+ DCD DMA2_Channel5_IRQHandler ; DMA2 Channel5
+
+;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
+;;
+;; Default interrupt handlers.
+;;
+ THUMB
+
+ PUBWEAK Reset_Handler
+ SECTION .text:CODE:REORDER(2)
+Reset_Handler
+ LDR R0, =SystemInit
+ BLX R0
+ LDR R0, =__iar_program_start
+ BX R0
+
+ PUBWEAK NMI_Handler
+ SECTION .text:CODE:REORDER(1)
+NMI_Handler
+ B NMI_Handler
+
+ PUBWEAK HardFault_Handler
+ SECTION .text:CODE:REORDER(1)
+HardFault_Handler
+ B HardFault_Handler
+
+ PUBWEAK MemManage_Handler
+ SECTION .text:CODE:REORDER(1)
+MemManage_Handler
+ B MemManage_Handler
+
+ PUBWEAK BusFault_Handler
+ SECTION .text:CODE:REORDER(1)
+BusFault_Handler
+ B BusFault_Handler
+
+ PUBWEAK UsageFault_Handler
+ SECTION .text:CODE:REORDER(1)
+UsageFault_Handler
+ B UsageFault_Handler
+
+ PUBWEAK SVC_Handler
+ SECTION .text:CODE:REORDER(1)
+SVC_Handler
+ B SVC_Handler
+
+ PUBWEAK DebugMon_Handler
+ SECTION .text:CODE:REORDER(1)
+DebugMon_Handler
+ B DebugMon_Handler
+
+ PUBWEAK PendSV_Handler
+ SECTION .text:CODE:REORDER(1)
+PendSV_Handler
+ B PendSV_Handler
+
+ PUBWEAK SysTick_Handler
+ SECTION .text:CODE:REORDER(1)
+SysTick_Handler
+ B SysTick_Handler
+
+ PUBWEAK WWDG_IRQHandler
+ SECTION .text:CODE:REORDER(1)
+WWDG_IRQHandler
+ B WWDG_IRQHandler
+
+ PUBWEAK PVD_IRQHandler
+ SECTION .text:CODE:REORDER(1)
+PVD_IRQHandler
+ B PVD_IRQHandler
+
+ PUBWEAK TAMPER_IRQHandler
+ SECTION .text:CODE:REORDER(1)
+TAMPER_IRQHandler
+ B TAMPER_IRQHandler
+
+ PUBWEAK RTC_IRQHandler
+ SECTION .text:CODE:REORDER(1)
+RTC_IRQHandler
+ B RTC_IRQHandler
+
+ PUBWEAK FLASH_IRQHandler
+ SECTION .text:CODE:REORDER(1)
+FLASH_IRQHandler
+ B FLASH_IRQHandler
+
+ PUBWEAK RCC_IRQHandler
+ SECTION .text:CODE:REORDER(1)
+RCC_IRQHandler
+ B RCC_IRQHandler
+
+ PUBWEAK EXTI0_IRQHandler
+ SECTION .text:CODE:REORDER(1)
+EXTI0_IRQHandler
+ B EXTI0_IRQHandler
+
+ PUBWEAK EXTI1_IRQHandler
+ SECTION .text:CODE:REORDER(1)
+EXTI1_IRQHandler
+ B EXTI1_IRQHandler
+
+ PUBWEAK EXTI2_IRQHandler
+ SECTION .text:CODE:REORDER(1)
+EXTI2_IRQHandler
+ B EXTI2_IRQHandler
+
+ PUBWEAK EXTI3_IRQHandler
+ SECTION .text:CODE:REORDER(1)
+EXTI3_IRQHandler
+ B EXTI3_IRQHandler
+
+ PUBWEAK EXTI4_IRQHandler
+ SECTION .text:CODE:REORDER(1)
+EXTI4_IRQHandler
+ B EXTI4_IRQHandler
+
+ PUBWEAK DMA1_Channel1_IRQHandler
+ SECTION .text:CODE:REORDER(1)
+DMA1_Channel1_IRQHandler
+ B DMA1_Channel1_IRQHandler
+
+ PUBWEAK DMA1_Channel2_IRQHandler
+ SECTION .text:CODE:REORDER(1)
+DMA1_Channel2_IRQHandler
+ B DMA1_Channel2_IRQHandler
+
+ PUBWEAK DMA1_Channel3_IRQHandler
+ SECTION .text:CODE:REORDER(1)
+DMA1_Channel3_IRQHandler
+ B DMA1_Channel3_IRQHandler
+
+ PUBWEAK DMA1_Channel4_IRQHandler
+ SECTION .text:CODE:REORDER(1)
+DMA1_Channel4_IRQHandler
+ B DMA1_Channel4_IRQHandler
+
+ PUBWEAK DMA1_Channel5_IRQHandler
+ SECTION .text:CODE:REORDER(1)
+DMA1_Channel5_IRQHandler
+ B DMA1_Channel5_IRQHandler
+
+ PUBWEAK DMA1_Channel6_IRQHandler
+ SECTION .text:CODE:REORDER(1)
+DMA1_Channel6_IRQHandler
+ B DMA1_Channel6_IRQHandler
+
+ PUBWEAK DMA1_Channel7_IRQHandler
+ SECTION .text:CODE:REORDER(1)
+DMA1_Channel7_IRQHandler
+ B DMA1_Channel7_IRQHandler
+
+ PUBWEAK ADC1_IRQHandler
+ SECTION .text:CODE:REORDER(1)
+ADC1_IRQHandler
+ B ADC1_IRQHandler
+
+ PUBWEAK EXTI9_5_IRQHandler
+ SECTION .text:CODE:REORDER(1)
+EXTI9_5_IRQHandler
+ B EXTI9_5_IRQHandler
+
+ PUBWEAK TIM1_BRK_TIM15_IRQHandler
+ SECTION .text:CODE:REORDER(1)
+TIM1_BRK_TIM15_IRQHandler
+ B TIM1_BRK_TIM15_IRQHandler
+
+ PUBWEAK TIM1_UP_TIM16_IRQHandler
+ SECTION .text:CODE:REORDER(1)
+TIM1_UP_TIM16_IRQHandler
+ B TIM1_UP_TIM16_IRQHandler
+
+ PUBWEAK TIM1_TRG_COM_TIM17_IRQHandler
+ SECTION .text:CODE:REORDER(1)
+TIM1_TRG_COM_TIM17_IRQHandler
+ B TIM1_TRG_COM_TIM17_IRQHandler
+
+ PUBWEAK TIM1_CC_IRQHandler
+ SECTION .text:CODE:REORDER(1)
+TIM1_CC_IRQHandler
+ B TIM1_CC_IRQHandler
+
+ PUBWEAK TIM2_IRQHandler
+ SECTION .text:CODE:REORDER(1)
+TIM2_IRQHandler
+ B TIM2_IRQHandler
+
+ PUBWEAK TIM3_IRQHandler
+ SECTION .text:CODE:REORDER(1)
+TIM3_IRQHandler
+ B TIM3_IRQHandler
+
+ PUBWEAK TIM4_IRQHandler
+ SECTION .text:CODE:REORDER(1)
+TIM4_IRQHandler
+ B TIM4_IRQHandler
+
+ PUBWEAK I2C1_EV_IRQHandler
+ SECTION .text:CODE:REORDER(1)
+I2C1_EV_IRQHandler
+ B I2C1_EV_IRQHandler
+
+ PUBWEAK I2C1_ER_IRQHandler
+ SECTION .text:CODE:REORDER(1)
+I2C1_ER_IRQHandler
+ B I2C1_ER_IRQHandler
+
+ PUBWEAK I2C2_EV_IRQHandler
+ SECTION .text:CODE:REORDER(1)
+I2C2_EV_IRQHandler
+ B I2C2_EV_IRQHandler
+
+ PUBWEAK I2C2_ER_IRQHandler
+ SECTION .text:CODE:REORDER(1)
+I2C2_ER_IRQHandler
+ B I2C2_ER_IRQHandler
+
+ PUBWEAK SPI1_IRQHandler
+ SECTION .text:CODE:REORDER(1)
+SPI1_IRQHandler
+ B SPI1_IRQHandler
+
+ PUBWEAK SPI2_IRQHandler
+ SECTION .text:CODE:REORDER(1)
+SPI2_IRQHandler
+ B SPI2_IRQHandler
+
+ PUBWEAK USART1_IRQHandler
+ SECTION .text:CODE:REORDER(1)
+USART1_IRQHandler
+ B USART1_IRQHandler
+
+ PUBWEAK USART2_IRQHandler
+ SECTION .text:CODE:REORDER(1)
+USART2_IRQHandler
+ B USART2_IRQHandler
+
+ PUBWEAK USART3_IRQHandler
+ SECTION .text:CODE:REORDER(1)
+USART3_IRQHandler
+ B USART3_IRQHandler
+
+ PUBWEAK EXTI15_10_IRQHandler
+ SECTION .text:CODE:REORDER(1)
+EXTI15_10_IRQHandler
+ B EXTI15_10_IRQHandler
+
+ PUBWEAK RTCAlarm_IRQHandler
+ SECTION .text:CODE:REORDER(1)
+RTCAlarm_IRQHandler
+ B RTCAlarm_IRQHandler
+
+ PUBWEAK CEC_IRQHandler
+ SECTION .text:CODE:REORDER(1)
+CEC_IRQHandler
+ B CEC_IRQHandler
+
+ PUBWEAK TIM12_IRQHandler
+ SECTION .text:CODE:REORDER(1)
+TIM12_IRQHandler
+ B TIM12_IRQHandler
+
+ PUBWEAK TIM13_IRQHandler
+ SECTION .text:CODE:REORDER(1)
+TIM13_IRQHandler
+ B TIM13_IRQHandler
+
+ PUBWEAK TIM14_IRQHandler
+ SECTION .text:CODE:REORDER(1)
+TIM14_IRQHandler
+ B TIM14_IRQHandler
+
+ PUBWEAK TIM5_IRQHandler
+ SECTION .text:CODE:REORDER(1)
+TIM5_IRQHandler
+ B TIM5_IRQHandler
+
+ PUBWEAK SPI3_IRQHandler
+ SECTION .text:CODE:REORDER(1)
+SPI3_IRQHandler
+ B SPI3_IRQHandler
+
+ PUBWEAK UART4_IRQHandler
+ SECTION .text:CODE:REORDER(1)
+UART4_IRQHandler
+ B UART4_IRQHandler
+
+ PUBWEAK UART5_IRQHandler
+ SECTION .text:CODE:REORDER(1)
+UART5_IRQHandler
+ B UART5_IRQHandler
+
+ PUBWEAK TIM6_DAC_IRQHandler
+ SECTION .text:CODE:REORDER(1)
+TIM6_DAC_IRQHandler
+ B TIM6_DAC_IRQHandler
+
+ PUBWEAK TIM7_IRQHandler
+ SECTION .text:CODE:REORDER(1)
+TIM7_IRQHandler
+ B TIM7_IRQHandler
+
+ PUBWEAK DMA2_Channel1_IRQHandler
+ SECTION .text:CODE:REORDER(1)
+DMA2_Channel1_IRQHandler
+ B DMA2_Channel1_IRQHandler
+
+ PUBWEAK DMA2_Channel2_IRQHandler
+ SECTION .text:CODE:REORDER(1)
+DMA2_Channel2_IRQHandler
+ B DMA2_Channel2_IRQHandler
+
+ PUBWEAK DMA2_Channel3_IRQHandler
+ SECTION .text:CODE:REORDER(1)
+DMA2_Channel3_IRQHandler
+ B DMA2_Channel3_IRQHandler
+
+ PUBWEAK DMA2_Channel4_5_IRQHandler
+ SECTION .text:CODE:REORDER(1)
+DMA2_Channel4_5_IRQHandler
+ B DMA2_Channel4_5_IRQHandler
+
+ PUBWEAK DMA2_Channel5_IRQHandler
+ SECTION .text:CODE:REORDER(1)
+DMA2_Channel5_IRQHandler
+ B DMA2_Channel5_IRQHandler
+
+ END
+/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
diff --git a/Libraries/CMSIS/Device/ST/STM32F10x/Source/Templates/iar/startup_stm32f10x_ld.s b/Libraries/CMSIS/Device/ST/STM32F10x/Source/Templates/iar/startup_stm32f10x_ld.s
new file mode 100644
index 0000000..cfbaa95
--- /dev/null
+++ b/Libraries/CMSIS/Device/ST/STM32F10x/Source/Templates/iar/startup_stm32f10x_ld.s
@@ -0,0 +1,373 @@
+;******************** (C) COPYRIGHT 2012 STMicroelectronics ********************
+;* File Name : startup_stm32f10x_ld.s
+;* Author : MCD Application Team
+;* Version : V3.6.1
+;* Date : 09-March-2012
+;* Description : STM32F10x Low Density Devices vector table for EWARM
+;* toolchain.
+;* This module performs:
+;* - Set the initial SP
+;* - Configure the clock system
+;* - Set the initial PC == __iar_program_start,
+;* - Set the vector table entries with the exceptions ISR
+;* address.
+;* After Reset the Cortex-M3 processor is in Thread mode,
+;* priority is Privileged, and the Stack is set to Main.
+;********************************************************************************
+;*
+;* Licensed under MCD-ST Liberty SW License Agreement V2, (the "License");
+;* You may not use this file except in compliance with the License.
+;* You may obtain a copy of the License at:
+;*
+;* http://www.st.com/software_license_agreement_liberty_v2
+;*
+;* Unless required by applicable law or agreed to in writing, software
+;* distributed under the License is distributed on an "AS IS" BASIS,
+;* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+;* See the License for the specific language governing permissions and
+;* limitations under the License.
+;*
+;*******************************************************************************
+;
+;
+; The modules in this file are included in the libraries, and may be replaced
+; by any user-defined modules that define the PUBLIC symbol _program_start or
+; a user defined start symbol.
+; To override the cstartup defined in the library, simply add your modified
+; version to the workbench project.
+;
+; The vector table is normally located at address 0.
+; When debugging in RAM, it can be located in RAM, aligned to at least 2^6.
+; The name "__vector_table" has special meaning for C-SPY:
+; it is where the SP start value is found, and the NVIC vector
+; table register (VTOR) is initialized to this address if != 0.
+;
+; Cortex-M version
+;
+
+ MODULE ?cstartup
+
+ ;; Forward declaration of sections.
+ SECTION CSTACK:DATA:NOROOT(3)
+
+ SECTION .intvec:CODE:NOROOT(2)
+
+ EXTERN __iar_program_start
+ EXTERN SystemInit
+ PUBLIC __vector_table
+
+ DATA
+__vector_table
+ DCD sfe(CSTACK)
+ DCD Reset_Handler ; Reset Handler
+ DCD NMI_Handler ; NMI Handler
+ DCD HardFault_Handler ; Hard Fault Handler
+ DCD MemManage_Handler ; MPU Fault Handler
+ DCD BusFault_Handler ; Bus Fault Handler
+ DCD UsageFault_Handler ; Usage Fault Handler
+ DCD 0 ; Reserved
+ DCD 0 ; Reserved
+ DCD 0 ; Reserved
+ DCD 0 ; Reserved
+ DCD SVC_Handler ; SVCall Handler
+ DCD DebugMon_Handler ; Debug Monitor Handler
+ DCD 0 ; Reserved
+ DCD PendSV_Handler ; PendSV Handler
+ DCD SysTick_Handler ; SysTick Handler
+
+ ; External Interrupts
+ DCD WWDG_IRQHandler ; Window Watchdog
+ DCD PVD_IRQHandler ; PVD through EXTI Line detect
+ DCD TAMPER_IRQHandler ; Tamper
+ DCD RTC_IRQHandler ; RTC
+ DCD FLASH_IRQHandler ; Flash
+ DCD RCC_IRQHandler ; RCC
+ DCD EXTI0_IRQHandler ; EXTI Line 0
+ DCD EXTI1_IRQHandler ; EXTI Line 1
+ DCD EXTI2_IRQHandler ; EXTI Line 2
+ DCD EXTI3_IRQHandler ; EXTI Line 3
+ DCD EXTI4_IRQHandler ; EXTI Line 4
+ DCD DMA1_Channel1_IRQHandler ; DMA1 Channel 1
+ DCD DMA1_Channel2_IRQHandler ; DMA1 Channel 2
+ DCD DMA1_Channel3_IRQHandler ; DMA1 Channel 3
+ DCD DMA1_Channel4_IRQHandler ; DMA1 Channel 4
+ DCD DMA1_Channel5_IRQHandler ; DMA1 Channel 5
+ DCD DMA1_Channel6_IRQHandler ; DMA1 Channel 6
+ DCD DMA1_Channel7_IRQHandler ; DMA1 Channel 7
+ DCD ADC1_2_IRQHandler ; ADC1 & ADC2
+ DCD USB_HP_CAN1_TX_IRQHandler ; USB High Priority or CAN1 TX
+ DCD USB_LP_CAN1_RX0_IRQHandler ; USB Low Priority or CAN1 RX0
+ DCD CAN1_RX1_IRQHandler ; CAN1 RX1
+ DCD CAN1_SCE_IRQHandler ; CAN1 SCE
+ DCD EXTI9_5_IRQHandler ; EXTI Line 9..5
+ DCD TIM1_BRK_IRQHandler ; TIM1 Break
+ DCD TIM1_UP_IRQHandler ; TIM1 Update
+ DCD TIM1_TRG_COM_IRQHandler ; TIM1 Trigger and Commutation
+ DCD TIM1_CC_IRQHandler ; TIM1 Capture Compare
+ DCD TIM2_IRQHandler ; TIM2
+ DCD TIM3_IRQHandler ; TIM3
+ DCD 0 ; Reserved
+ DCD I2C1_EV_IRQHandler ; I2C1 Event
+ DCD I2C1_ER_IRQHandler ; I2C1 Error
+ DCD 0 ; Reserved
+ DCD 0 ; Reserved
+ DCD SPI1_IRQHandler ; SPI1
+ DCD 0 ; Reserved
+ DCD USART1_IRQHandler ; USART1
+ DCD USART2_IRQHandler ; USART2
+ DCD 0 ; Reserved
+ DCD EXTI15_10_IRQHandler ; EXTI Line 15..10
+ DCD RTCAlarm_IRQHandler ; RTC Alarm through EXTI Line
+ DCD USBWakeUp_IRQHandler ; USB Wakeup from suspend
+
+;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
+;;
+;; Default interrupt handlers.
+;;
+ THUMB
+
+ PUBWEAK Reset_Handler
+ SECTION .text:CODE:REORDER(2)
+Reset_Handler
+ LDR R0, =SystemInit
+ BLX R0
+ LDR R0, =__iar_program_start
+ BX R0
+
+ PUBWEAK NMI_Handler
+ SECTION .text:CODE:REORDER(1)
+NMI_Handler
+ B NMI_Handler
+
+ PUBWEAK HardFault_Handler
+ SECTION .text:CODE:REORDER(1)
+HardFault_Handler
+ B HardFault_Handler
+
+ PUBWEAK MemManage_Handler
+ SECTION .text:CODE:REORDER(1)
+MemManage_Handler
+ B MemManage_Handler
+
+ PUBWEAK BusFault_Handler
+ SECTION .text:CODE:REORDER(1)
+BusFault_Handler
+ B BusFault_Handler
+
+ PUBWEAK UsageFault_Handler
+ SECTION .text:CODE:REORDER(1)
+UsageFault_Handler
+ B UsageFault_Handler
+
+ PUBWEAK SVC_Handler
+ SECTION .text:CODE:REORDER(1)
+SVC_Handler
+ B SVC_Handler
+
+ PUBWEAK DebugMon_Handler
+ SECTION .text:CODE:REORDER(1)
+DebugMon_Handler
+ B DebugMon_Handler
+
+ PUBWEAK PendSV_Handler
+ SECTION .text:CODE:REORDER(1)
+PendSV_Handler
+ B PendSV_Handler
+
+ PUBWEAK SysTick_Handler
+ SECTION .text:CODE:REORDER(1)
+SysTick_Handler
+ B SysTick_Handler
+
+ PUBWEAK WWDG_IRQHandler
+ SECTION .text:CODE:REORDER(1)
+WWDG_IRQHandler
+ B WWDG_IRQHandler
+
+ PUBWEAK PVD_IRQHandler
+ SECTION .text:CODE:REORDER(1)
+PVD_IRQHandler
+ B PVD_IRQHandler
+
+ PUBWEAK TAMPER_IRQHandler
+ SECTION .text:CODE:REORDER(1)
+TAMPER_IRQHandler
+ B TAMPER_IRQHandler
+
+ PUBWEAK RTC_IRQHandler
+ SECTION .text:CODE:REORDER(1)
+RTC_IRQHandler
+ B RTC_IRQHandler
+
+ PUBWEAK FLASH_IRQHandler
+ SECTION .text:CODE:REORDER(1)
+FLASH_IRQHandler
+ B FLASH_IRQHandler
+
+ PUBWEAK RCC_IRQHandler
+ SECTION .text:CODE:REORDER(1)
+RCC_IRQHandler
+ B RCC_IRQHandler
+
+ PUBWEAK EXTI0_IRQHandler
+ SECTION .text:CODE:REORDER(1)
+EXTI0_IRQHandler
+ B EXTI0_IRQHandler
+
+ PUBWEAK EXTI1_IRQHandler
+ SECTION .text:CODE:REORDER(1)
+EXTI1_IRQHandler
+ B EXTI1_IRQHandler
+
+ PUBWEAK EXTI2_IRQHandler
+ SECTION .text:CODE:REORDER(1)
+EXTI2_IRQHandler
+ B EXTI2_IRQHandler
+
+ PUBWEAK EXTI3_IRQHandler
+ SECTION .text:CODE:REORDER(1)
+EXTI3_IRQHandler
+ B EXTI3_IRQHandler
+
+ PUBWEAK EXTI4_IRQHandler
+ SECTION .text:CODE:REORDER(1)
+EXTI4_IRQHandler
+ B EXTI4_IRQHandler
+
+ PUBWEAK DMA1_Channel1_IRQHandler
+ SECTION .text:CODE:REORDER(1)
+DMA1_Channel1_IRQHandler
+ B DMA1_Channel1_IRQHandler
+
+ PUBWEAK DMA1_Channel2_IRQHandler
+ SECTION .text:CODE:REORDER(1)
+DMA1_Channel2_IRQHandler
+ B DMA1_Channel2_IRQHandler
+
+ PUBWEAK DMA1_Channel3_IRQHandler
+ SECTION .text:CODE:REORDER(1)
+DMA1_Channel3_IRQHandler
+ B DMA1_Channel3_IRQHandler
+
+ PUBWEAK DMA1_Channel4_IRQHandler
+ SECTION .text:CODE:REORDER(1)
+DMA1_Channel4_IRQHandler
+ B DMA1_Channel4_IRQHandler
+
+ PUBWEAK DMA1_Channel5_IRQHandler
+ SECTION .text:CODE:REORDER(1)
+DMA1_Channel5_IRQHandler
+ B DMA1_Channel5_IRQHandler
+
+ PUBWEAK DMA1_Channel6_IRQHandler
+ SECTION .text:CODE:REORDER(1)
+DMA1_Channel6_IRQHandler
+ B DMA1_Channel6_IRQHandler
+
+ PUBWEAK DMA1_Channel7_IRQHandler
+ SECTION .text:CODE:REORDER(1)
+DMA1_Channel7_IRQHandler
+ B DMA1_Channel7_IRQHandler
+
+ PUBWEAK ADC1_2_IRQHandler
+ SECTION .text:CODE:REORDER(1)
+ADC1_2_IRQHandler
+ B ADC1_2_IRQHandler
+
+ PUBWEAK USB_HP_CAN1_TX_IRQHandler
+ SECTION .text:CODE:REORDER(1)
+USB_HP_CAN1_TX_IRQHandler
+ B USB_HP_CAN1_TX_IRQHandler
+
+ PUBWEAK USB_LP_CAN1_RX0_IRQHandler
+ SECTION .text:CODE:REORDER(1)
+USB_LP_CAN1_RX0_IRQHandler
+ B USB_LP_CAN1_RX0_IRQHandler
+
+ PUBWEAK CAN1_RX1_IRQHandler
+ SECTION .text:CODE:REORDER(1)
+CAN1_RX1_IRQHandler
+ B CAN1_RX1_IRQHandler
+
+ PUBWEAK CAN1_SCE_IRQHandler
+ SECTION .text:CODE:REORDER(1)
+CAN1_SCE_IRQHandler
+ B CAN1_SCE_IRQHandler
+
+ PUBWEAK EXTI9_5_IRQHandler
+ SECTION .text:CODE:REORDER(1)
+EXTI9_5_IRQHandler
+ B EXTI9_5_IRQHandler
+
+ PUBWEAK TIM1_BRK_IRQHandler
+ SECTION .text:CODE:REORDER(1)
+TIM1_BRK_IRQHandler
+ B TIM1_BRK_IRQHandler
+
+ PUBWEAK TIM1_UP_IRQHandler
+ SECTION .text:CODE:REORDER(1)
+TIM1_UP_IRQHandler
+ B TIM1_UP_IRQHandler
+
+ PUBWEAK TIM1_TRG_COM_IRQHandler
+ SECTION .text:CODE:REORDER(1)
+TIM1_TRG_COM_IRQHandler
+ B TIM1_TRG_COM_IRQHandler
+
+ PUBWEAK TIM1_CC_IRQHandler
+ SECTION .text:CODE:REORDER(1)
+TIM1_CC_IRQHandler
+ B TIM1_CC_IRQHandler
+
+ PUBWEAK TIM2_IRQHandler
+ SECTION .text:CODE:REORDER(1)
+TIM2_IRQHandler
+ B TIM2_IRQHandler
+
+ PUBWEAK TIM3_IRQHandler
+ SECTION .text:CODE:REORDER(1)
+TIM3_IRQHandler
+ B TIM3_IRQHandler
+
+ PUBWEAK I2C1_EV_IRQHandler
+ SECTION .text:CODE:REORDER(1)
+I2C1_EV_IRQHandler
+ B I2C1_EV_IRQHandler
+
+ PUBWEAK I2C1_ER_IRQHandler
+ SECTION .text:CODE:REORDER(1)
+I2C1_ER_IRQHandler
+ B I2C1_ER_IRQHandler
+
+ PUBWEAK SPI1_IRQHandler
+ SECTION .text:CODE:REORDER(1)
+SPI1_IRQHandler
+ B SPI1_IRQHandler
+
+ PUBWEAK USART1_IRQHandler
+ SECTION .text:CODE:REORDER(1)
+USART1_IRQHandler
+ B USART1_IRQHandler
+
+ PUBWEAK USART2_IRQHandler
+ SECTION .text:CODE:REORDER(1)
+USART2_IRQHandler
+ B USART2_IRQHandler
+
+ PUBWEAK EXTI15_10_IRQHandler
+ SECTION .text:CODE:REORDER(1)
+EXTI15_10_IRQHandler
+ B EXTI15_10_IRQHandler
+
+ PUBWEAK RTCAlarm_IRQHandler
+ SECTION .text:CODE:REORDER(1)
+RTCAlarm_IRQHandler
+ B RTCAlarm_IRQHandler
+
+ PUBWEAK USBWakeUp_IRQHandler
+ SECTION .text:CODE:REORDER(1)
+USBWakeUp_IRQHandler
+ B USBWakeUp_IRQHandler
+
+ END
+/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
diff --git a/Libraries/CMSIS/Device/ST/STM32F10x/Source/Templates/iar/startup_stm32f10x_ld_vl.s b/Libraries/CMSIS/Device/ST/STM32F10x/Source/Templates/iar/startup_stm32f10x_ld_vl.s
new file mode 100644
index 0000000..7cde5bb
--- /dev/null
+++ b/Libraries/CMSIS/Device/ST/STM32F10x/Source/Templates/iar/startup_stm32f10x_ld_vl.s
@@ -0,0 +1,376 @@
+;******************** (C) COPYRIGHT 2012 STMicroelectronics ********************
+;* File Name : startup_stm32f10x_ld_vl.s
+;* Author : MCD Application Team
+;* Version : V3.6.1
+;* Date : 09-March-2012
+;* Description : STM32F10x Low Density Value Line Devices vector table
+;* for EWARM toolchain.
+;* This module performs:
+;* - Set the initial SP
+;* - Configure the clock system
+;* - Set the initial PC == __iar_program_start,
+;* - Set the vector table entries with the exceptions ISR
+;* address.
+;* After Reset the Cortex-M3 processor is in Thread mode,
+;* priority is Privileged, and the Stack is set to Main.
+;********************************************************************************
+;*
+;* Licensed under MCD-ST Liberty SW License Agreement V2, (the "License");
+;* You may not use this file except in compliance with the License.
+;* You may obtain a copy of the License at:
+;*
+;* http://www.st.com/software_license_agreement_liberty_v2
+;*
+;* Unless required by applicable law or agreed to in writing, software
+;* distributed under the License is distributed on an "AS IS" BASIS,
+;* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+;* See the License for the specific language governing permissions and
+;* limitations under the License.
+;*
+;*******************************************************************************
+;
+;
+; The modules in this file are included in the libraries, and may be replaced
+; by any user-defined modules that define the PUBLIC symbol _program_start or
+; a user defined start symbol.
+; To override the cstartup defined in the library, simply add your modified
+; version to the workbench project.
+;
+; The vector table is normally located at address 0.
+; When debugging in RAM, it can be located in RAM, aligned to at least 2^6.
+; The name "__vector_table" has special meaning for C-SPY:
+; it is where the SP start value is found, and the NVIC vector
+; table register (VTOR) is initialized to this address if != 0.
+;
+; Cortex-M version
+;
+
+ MODULE ?cstartup
+
+ ;; Forward declaration of sections.
+ SECTION CSTACK:DATA:NOROOT(3)
+
+ SECTION .intvec:CODE:NOROOT(2)
+
+ EXTERN __iar_program_start
+ EXTERN SystemInit
+ PUBLIC __vector_table
+
+ DATA
+__vector_table
+ DCD sfe(CSTACK)
+ DCD Reset_Handler ; Reset Handler
+ DCD NMI_Handler ; NMI Handler
+ DCD HardFault_Handler ; Hard Fault Handler
+ DCD MemManage_Handler ; MPU Fault Handler
+ DCD BusFault_Handler ; Bus Fault Handler
+ DCD UsageFault_Handler ; Usage Fault Handler
+ DCD 0 ; Reserved
+ DCD 0 ; Reserved
+ DCD 0 ; Reserved
+ DCD 0 ; Reserved
+ DCD SVC_Handler ; SVCall Handler
+ DCD DebugMon_Handler ; Debug Monitor Handler
+ DCD 0 ; Reserved
+ DCD PendSV_Handler ; PendSV Handler
+ DCD SysTick_Handler ; SysTick Handler
+
+ ; External Interrupts
+ DCD WWDG_IRQHandler ; Window Watchdog
+ DCD PVD_IRQHandler ; PVD through EXTI Line detect
+ DCD TAMPER_IRQHandler ; Tamper
+ DCD RTC_IRQHandler ; RTC
+ DCD FLASH_IRQHandler ; Flash
+ DCD RCC_IRQHandler ; RCC
+ DCD EXTI0_IRQHandler ; EXTI Line 0
+ DCD EXTI1_IRQHandler ; EXTI Line 1
+ DCD EXTI2_IRQHandler ; EXTI Line 2
+ DCD EXTI3_IRQHandler ; EXTI Line 3
+ DCD EXTI4_IRQHandler ; EXTI Line 4
+ DCD DMA1_Channel1_IRQHandler ; DMA1 Channel 1
+ DCD DMA1_Channel2_IRQHandler ; DMA1 Channel 2
+ DCD DMA1_Channel3_IRQHandler ; DMA1 Channel 3
+ DCD DMA1_Channel4_IRQHandler ; DMA1 Channel 4
+ DCD DMA1_Channel5_IRQHandler ; DMA1 Channel 5
+ DCD DMA1_Channel6_IRQHandler ; DMA1 Channel 6
+ DCD DMA1_Channel7_IRQHandler ; DMA1 Channel 7
+ DCD ADC1_IRQHandler ; ADC1
+ DCD 0 ; Reserved
+ DCD 0 ; Reserved
+ DCD 0 ; Reserved
+ DCD 0 ; Reserved
+ DCD EXTI9_5_IRQHandler ; EXTI Line 9..5
+ DCD TIM1_BRK_TIM15_IRQHandler ; TIM1 Break and TIM15
+ DCD TIM1_UP_TIM16_IRQHandler ; TIM1 Update and TIM16
+ DCD TIM1_TRG_COM_TIM17_IRQHandler ; TIM1 Trigger and Commutation and TIM17
+ DCD TIM1_CC_IRQHandler ; TIM1 Capture Compare
+ DCD TIM2_IRQHandler ; TIM2
+ DCD TIM3_IRQHandler ; TIM3
+ DCD 0 ; Reserved
+ DCD I2C1_EV_IRQHandler ; I2C1 Event
+ DCD I2C1_ER_IRQHandler ; I2C1 Error
+ DCD 0 ; Reserved
+ DCD 0 ; Reserved
+ DCD SPI1_IRQHandler ; SPI1
+ DCD 0 ; Reserved
+ DCD USART1_IRQHandler ; USART1
+ DCD USART2_IRQHandler ; USART2
+ DCD 0 ; Reserved
+ DCD EXTI15_10_IRQHandler ; EXTI Line 15..10
+ DCD RTCAlarm_IRQHandler ; RTC Alarm through EXTI Line
+ DCD CEC_IRQHandler ; HDMI-CEC
+ DCD 0 ; Reserved
+ DCD 0 ; Reserved
+ DCD 0 ; Reserved
+ DCD 0 ; Reserved
+ DCD 0 ; Reserved
+ DCD 0 ; Reserved
+ DCD 0 ; Reserved
+ DCD 0 ; Reserved
+ DCD 0 ; Reserved
+ DCD 0 ; Reserved
+ DCD 0 ; Reserved
+ DCD TIM6_DAC_IRQHandler ; TIM6 and DAC underrun
+ DCD TIM7_IRQHandler ; TIM7
+
+;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
+;;
+;; Default interrupt handlers.
+;;
+ THUMB
+
+ PUBWEAK Reset_Handler
+ SECTION .text:CODE:REORDER(2)
+Reset_Handler
+ LDR R0, =SystemInit
+ BLX R0
+ LDR R0, =__iar_program_start
+ BX R0
+
+ PUBWEAK NMI_Handler
+ SECTION .text:CODE:REORDER(1)
+NMI_Handler
+ B NMI_Handler
+
+ PUBWEAK HardFault_Handler
+ SECTION .text:CODE:REORDER(1)
+HardFault_Handler
+ B HardFault_Handler
+
+ PUBWEAK MemManage_Handler
+ SECTION .text:CODE:REORDER(1)
+MemManage_Handler
+ B MemManage_Handler
+
+ PUBWEAK BusFault_Handler
+ SECTION .text:CODE:REORDER(1)
+BusFault_Handler
+ B BusFault_Handler
+
+ PUBWEAK UsageFault_Handler
+ SECTION .text:CODE:REORDER(1)
+UsageFault_Handler
+ B UsageFault_Handler
+
+ PUBWEAK SVC_Handler
+ SECTION .text:CODE:REORDER(1)
+SVC_Handler
+ B SVC_Handler
+
+ PUBWEAK DebugMon_Handler
+ SECTION .text:CODE:REORDER(1)
+DebugMon_Handler
+ B DebugMon_Handler
+
+ PUBWEAK PendSV_Handler
+ SECTION .text:CODE:REORDER(1)
+PendSV_Handler
+ B PendSV_Handler
+
+ PUBWEAK SysTick_Handler
+ SECTION .text:CODE:REORDER(1)
+SysTick_Handler
+ B SysTick_Handler
+
+ PUBWEAK WWDG_IRQHandler
+ SECTION .text:CODE:REORDER(1)
+WWDG_IRQHandler
+ B WWDG_IRQHandler
+
+ PUBWEAK PVD_IRQHandler
+ SECTION .text:CODE:REORDER(1)
+PVD_IRQHandler
+ B PVD_IRQHandler
+
+ PUBWEAK TAMPER_IRQHandler
+ SECTION .text:CODE:REORDER(1)
+TAMPER_IRQHandler
+ B TAMPER_IRQHandler
+
+ PUBWEAK RTC_IRQHandler
+ SECTION .text:CODE:REORDER(1)
+RTC_IRQHandler
+ B RTC_IRQHandler
+
+ PUBWEAK FLASH_IRQHandler
+ SECTION .text:CODE:REORDER(1)
+FLASH_IRQHandler
+ B FLASH_IRQHandler
+
+ PUBWEAK RCC_IRQHandler
+ SECTION .text:CODE:REORDER(1)
+RCC_IRQHandler
+ B RCC_IRQHandler
+
+ PUBWEAK EXTI0_IRQHandler
+ SECTION .text:CODE:REORDER(1)
+EXTI0_IRQHandler
+ B EXTI0_IRQHandler
+
+ PUBWEAK EXTI1_IRQHandler
+ SECTION .text:CODE:REORDER(1)
+EXTI1_IRQHandler
+ B EXTI1_IRQHandler
+
+ PUBWEAK EXTI2_IRQHandler
+ SECTION .text:CODE:REORDER(1)
+EXTI2_IRQHandler
+ B EXTI2_IRQHandler
+
+ PUBWEAK EXTI3_IRQHandler
+ SECTION .text:CODE:REORDER(1)
+EXTI3_IRQHandler
+ B EXTI3_IRQHandler
+
+ PUBWEAK EXTI4_IRQHandler
+ SECTION .text:CODE:REORDER(1)
+EXTI4_IRQHandler
+ B EXTI4_IRQHandler
+
+ PUBWEAK DMA1_Channel1_IRQHandler
+ SECTION .text:CODE:REORDER(1)
+DMA1_Channel1_IRQHandler
+ B DMA1_Channel1_IRQHandler
+
+ PUBWEAK DMA1_Channel2_IRQHandler
+ SECTION .text:CODE:REORDER(1)
+DMA1_Channel2_IRQHandler
+ B DMA1_Channel2_IRQHandler
+
+ PUBWEAK DMA1_Channel3_IRQHandler
+ SECTION .text:CODE:REORDER(1)
+DMA1_Channel3_IRQHandler
+ B DMA1_Channel3_IRQHandler
+
+ PUBWEAK DMA1_Channel4_IRQHandler
+ SECTION .text:CODE:REORDER(1)
+DMA1_Channel4_IRQHandler
+ B DMA1_Channel4_IRQHandler
+
+ PUBWEAK DMA1_Channel5_IRQHandler
+ SECTION .text:CODE:REORDER(1)
+DMA1_Channel5_IRQHandler
+ B DMA1_Channel5_IRQHandler
+
+ PUBWEAK DMA1_Channel6_IRQHandler
+ SECTION .text:CODE:REORDER(1)
+DMA1_Channel6_IRQHandler
+ B DMA1_Channel6_IRQHandler
+
+ PUBWEAK DMA1_Channel7_IRQHandler
+ SECTION .text:CODE:REORDER(1)
+DMA1_Channel7_IRQHandler
+ B DMA1_Channel7_IRQHandler
+
+ PUBWEAK ADC1_IRQHandler
+ SECTION .text:CODE:REORDER(1)
+ADC1_IRQHandler
+ B ADC1_IRQHandler
+
+ PUBWEAK EXTI9_5_IRQHandler
+ SECTION .text:CODE:REORDER(1)
+EXTI9_5_IRQHandler
+ B EXTI9_5_IRQHandler
+
+ PUBWEAK TIM1_BRK_TIM15_IRQHandler
+ SECTION .text:CODE:REORDER(1)
+TIM1_BRK_TIM15_IRQHandler
+ B TIM1_BRK_TIM15_IRQHandler
+
+ PUBWEAK TIM1_UP_TIM16_IRQHandler
+ SECTION .text:CODE:REORDER(1)
+TIM1_UP_TIM16_IRQHandler
+ B TIM1_UP_TIM16_IRQHandler
+
+ PUBWEAK TIM1_TRG_COM_TIM17_IRQHandler
+ SECTION .text:CODE:REORDER(1)
+TIM1_TRG_COM_TIM17_IRQHandler
+ B TIM1_TRG_COM_TIM17_IRQHandler
+
+ PUBWEAK TIM1_CC_IRQHandler
+ SECTION .text:CODE:REORDER(1)
+TIM1_CC_IRQHandler
+ B TIM1_CC_IRQHandler
+
+ PUBWEAK TIM2_IRQHandler
+ SECTION .text:CODE:REORDER(1)
+TIM2_IRQHandler
+ B TIM2_IRQHandler
+
+ PUBWEAK TIM3_IRQHandler
+ SECTION .text:CODE:REORDER(1)
+TIM3_IRQHandler
+ B TIM3_IRQHandler
+
+ PUBWEAK I2C1_EV_IRQHandler
+ SECTION .text:CODE:REORDER(1)
+I2C1_EV_IRQHandler
+ B I2C1_EV_IRQHandler
+
+ PUBWEAK I2C1_ER_IRQHandler
+ SECTION .text:CODE:REORDER(1)
+I2C1_ER_IRQHandler
+ B I2C1_ER_IRQHandler
+
+ PUBWEAK SPI1_IRQHandler
+ SECTION .text:CODE:REORDER(1)
+SPI1_IRQHandler
+ B SPI1_IRQHandler
+
+ PUBWEAK USART1_IRQHandler
+ SECTION .text:CODE:REORDER(1)
+USART1_IRQHandler
+ B USART1_IRQHandler
+
+ PUBWEAK USART2_IRQHandler
+ SECTION .text:CODE:REORDER(1)
+USART2_IRQHandler
+ B USART2_IRQHandler
+
+ PUBWEAK EXTI15_10_IRQHandler
+ SECTION .text:CODE:REORDER(1)
+EXTI15_10_IRQHandler
+ B EXTI15_10_IRQHandler
+
+ PUBWEAK RTCAlarm_IRQHandler
+ SECTION .text:CODE:REORDER(1)
+RTCAlarm_IRQHandler
+ B RTCAlarm_IRQHandler
+
+ PUBWEAK CEC_IRQHandler
+ SECTION .text:CODE:REORDER(1)
+CEC_IRQHandler
+ B CEC_IRQHandler
+
+ PUBWEAK TIM6_DAC_IRQHandler
+ SECTION .text:CODE:REORDER(1)
+TIM6_DAC_IRQHandler
+ B TIM6_DAC_IRQHandler
+
+ PUBWEAK TIM7_IRQHandler
+ SECTION .text:CODE:REORDER(1)
+TIM7_IRQHandler
+ B TIM7_IRQHandler
+
+ END
+/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
diff --git a/Libraries/CMSIS/Device/ST/STM32F10x/Source/Templates/iar/startup_stm32f10x_md.s b/Libraries/CMSIS/Device/ST/STM32F10x/Source/Templates/iar/startup_stm32f10x_md.s
new file mode 100644
index 0000000..db28cda
--- /dev/null
+++ b/Libraries/CMSIS/Device/ST/STM32F10x/Source/Templates/iar/startup_stm32f10x_md.s
@@ -0,0 +1,398 @@
+;******************** (C) COPYRIGHT 2012 STMicroelectronics ********************
+;* File Name : startup_stm32f10x_md.s
+;* Author : MCD Application Team
+;* Version : V3.6.1
+;* Date : 09-March-2012
+;* Description : STM32F10x Medium Density Devices vector table for
+;* EWARM toolchain.
+;* This module performs:
+;* - Set the initial SP
+;* - Configure the clock system
+;* - Set the initial PC == __iar_program_start,
+;* - Set the vector table entries with the exceptions ISR
+;* address.
+;* After Reset the Cortex-M3 processor is in Thread mode,
+;* priority is Privileged, and the Stack is set to Main.
+;********************************************************************************
+;*
+;* Licensed under MCD-ST Liberty SW License Agreement V2, (the "License");
+;* You may not use this file except in compliance with the License.
+;* You may obtain a copy of the License at:
+;*
+;* http://www.st.com/software_license_agreement_liberty_v2
+;*
+;* Unless required by applicable law or agreed to in writing, software
+;* distributed under the License is distributed on an "AS IS" BASIS,
+;* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+;* See the License for the specific language governing permissions and
+;* limitations under the License.
+;*
+;*******************************************************************************
+;
+;
+; The modules in this file are included in the libraries, and may be replaced
+; by any user-defined modules that define the PUBLIC symbol _program_start or
+; a user defined start symbol.
+; To override the cstartup defined in the library, simply add your modified
+; version to the workbench project.
+;
+; The vector table is normally located at address 0.
+; When debugging in RAM, it can be located in RAM, aligned to at least 2^6.
+; The name "__vector_table" has special meaning for C-SPY:
+; it is where the SP start value is found, and the NVIC vector
+; table register (VTOR) is initialized to this address if != 0.
+;
+; Cortex-M version
+;
+
+ MODULE ?cstartup
+
+ ;; Forward declaration of sections.
+ SECTION CSTACK:DATA:NOROOT(3)
+
+ SECTION .intvec:CODE:NOROOT(2)
+
+ EXTERN __iar_program_start
+ EXTERN SystemInit
+ PUBLIC __vector_table
+
+ DATA
+__vector_table
+ DCD sfe(CSTACK)
+ DCD Reset_Handler ; Reset Handler
+ DCD NMI_Handler ; NMI Handler
+ DCD HardFault_Handler ; Hard Fault Handler
+ DCD MemManage_Handler ; MPU Fault Handler
+ DCD BusFault_Handler ; Bus Fault Handler
+ DCD UsageFault_Handler ; Usage Fault Handler
+ DCD 0 ; Reserved
+ DCD 0 ; Reserved
+ DCD 0 ; Reserved
+ DCD 0 ; Reserved
+ DCD SVC_Handler ; SVCall Handler
+ DCD DebugMon_Handler ; Debug Monitor Handler
+ DCD 0 ; Reserved
+ DCD PendSV_Handler ; PendSV Handler
+ DCD SysTick_Handler ; SysTick Handler
+
+ ; External Interrupts
+ DCD WWDG_IRQHandler ; Window Watchdog
+ DCD PVD_IRQHandler ; PVD through EXTI Line detect
+ DCD TAMPER_IRQHandler ; Tamper
+ DCD RTC_IRQHandler ; RTC
+ DCD FLASH_IRQHandler ; Flash
+ DCD RCC_IRQHandler ; RCC
+ DCD EXTI0_IRQHandler ; EXTI Line 0
+ DCD EXTI1_IRQHandler ; EXTI Line 1
+ DCD EXTI2_IRQHandler ; EXTI Line 2
+ DCD EXTI3_IRQHandler ; EXTI Line 3
+ DCD EXTI4_IRQHandler ; EXTI Line 4
+ DCD DMA1_Channel1_IRQHandler ; DMA1 Channel 1
+ DCD DMA1_Channel2_IRQHandler ; DMA1 Channel 2
+ DCD DMA1_Channel3_IRQHandler ; DMA1 Channel 3
+ DCD DMA1_Channel4_IRQHandler ; DMA1 Channel 4
+ DCD DMA1_Channel5_IRQHandler ; DMA1 Channel 5
+ DCD DMA1_Channel6_IRQHandler ; DMA1 Channel 6
+ DCD DMA1_Channel7_IRQHandler ; DMA1 Channel 7
+ DCD ADC1_2_IRQHandler ; ADC1 & ADC2
+ DCD USB_HP_CAN1_TX_IRQHandler ; USB High Priority or CAN1 TX
+ DCD USB_LP_CAN1_RX0_IRQHandler ; USB Low Priority or CAN1 RX0
+ DCD CAN1_RX1_IRQHandler ; CAN1 RX1
+ DCD CAN1_SCE_IRQHandler ; CAN1 SCE
+ DCD EXTI9_5_IRQHandler ; EXTI Line 9..5
+ DCD TIM1_BRK_IRQHandler ; TIM1 Break
+ DCD TIM1_UP_IRQHandler ; TIM1 Update
+ DCD TIM1_TRG_COM_IRQHandler ; TIM1 Trigger and Commutation
+ DCD TIM1_CC_IRQHandler ; TIM1 Capture Compare
+ DCD TIM2_IRQHandler ; TIM2
+ DCD TIM3_IRQHandler ; TIM3
+ DCD TIM4_IRQHandler ; TIM4
+ DCD I2C1_EV_IRQHandler ; I2C1 Event
+ DCD I2C1_ER_IRQHandler ; I2C1 Error
+ DCD I2C2_EV_IRQHandler ; I2C2 Event
+ DCD I2C2_ER_IRQHandler ; I2C2 Error
+ DCD SPI1_IRQHandler ; SPI1
+ DCD SPI2_IRQHandler ; SPI2
+ DCD USART1_IRQHandler ; USART1
+ DCD USART2_IRQHandler ; USART2
+ DCD USART3_IRQHandler ; USART3
+ DCD EXTI15_10_IRQHandler ; EXTI Line 15..10
+ DCD RTCAlarm_IRQHandler ; RTC Alarm through EXTI Line
+ DCD USBWakeUp_IRQHandler ; USB Wakeup from suspend
+
+;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
+;;
+;; Default interrupt handlers.
+;;
+ THUMB
+
+ PUBWEAK Reset_Handler
+ SECTION .text:CODE:REORDER(2)
+Reset_Handler
+ LDR R0, =SystemInit
+ BLX R0
+ LDR R0, =__iar_program_start
+ BX R0
+
+ PUBWEAK NMI_Handler
+ SECTION .text:CODE:REORDER(1)
+NMI_Handler
+ B NMI_Handler
+
+ PUBWEAK HardFault_Handler
+ SECTION .text:CODE:REORDER(1)
+HardFault_Handler
+ B HardFault_Handler
+
+ PUBWEAK MemManage_Handler
+ SECTION .text:CODE:REORDER(1)
+MemManage_Handler
+ B MemManage_Handler
+
+ PUBWEAK BusFault_Handler
+ SECTION .text:CODE:REORDER(1)
+BusFault_Handler
+ B BusFault_Handler
+
+ PUBWEAK UsageFault_Handler
+ SECTION .text:CODE:REORDER(1)
+UsageFault_Handler
+ B UsageFault_Handler
+
+ PUBWEAK SVC_Handler
+ SECTION .text:CODE:REORDER(1)
+SVC_Handler
+ B SVC_Handler
+
+ PUBWEAK DebugMon_Handler
+ SECTION .text:CODE:REORDER(1)
+DebugMon_Handler
+ B DebugMon_Handler
+
+ PUBWEAK PendSV_Handler
+ SECTION .text:CODE:REORDER(1)
+PendSV_Handler
+ B PendSV_Handler
+
+ PUBWEAK SysTick_Handler
+ SECTION .text:CODE:REORDER(1)
+SysTick_Handler
+ B SysTick_Handler
+
+ PUBWEAK WWDG_IRQHandler
+ SECTION .text:CODE:REORDER(1)
+WWDG_IRQHandler
+ B WWDG_IRQHandler
+
+ PUBWEAK PVD_IRQHandler
+ SECTION .text:CODE:REORDER(1)
+PVD_IRQHandler
+ B PVD_IRQHandler
+
+ PUBWEAK TAMPER_IRQHandler
+ SECTION .text:CODE:REORDER(1)
+TAMPER_IRQHandler
+ B TAMPER_IRQHandler
+
+ PUBWEAK RTC_IRQHandler
+ SECTION .text:CODE:REORDER(1)
+RTC_IRQHandler
+ B RTC_IRQHandler
+
+ PUBWEAK FLASH_IRQHandler
+ SECTION .text:CODE:REORDER(1)
+FLASH_IRQHandler
+ B FLASH_IRQHandler
+
+ PUBWEAK RCC_IRQHandler
+ SECTION .text:CODE:REORDER(1)
+RCC_IRQHandler
+ B RCC_IRQHandler
+
+ PUBWEAK EXTI0_IRQHandler
+ SECTION .text:CODE:REORDER(1)
+EXTI0_IRQHandler
+ B EXTI0_IRQHandler
+
+ PUBWEAK EXTI1_IRQHandler
+ SECTION .text:CODE:REORDER(1)
+EXTI1_IRQHandler
+ B EXTI1_IRQHandler
+
+ PUBWEAK EXTI2_IRQHandler
+ SECTION .text:CODE:REORDER(1)
+EXTI2_IRQHandler
+ B EXTI2_IRQHandler
+
+ PUBWEAK EXTI3_IRQHandler
+ SECTION .text:CODE:REORDER(1)
+EXTI3_IRQHandler
+ B EXTI3_IRQHandler
+
+ PUBWEAK EXTI4_IRQHandler
+ SECTION .text:CODE:REORDER(1)
+EXTI4_IRQHandler
+ B EXTI4_IRQHandler
+
+ PUBWEAK DMA1_Channel1_IRQHandler
+ SECTION .text:CODE:REORDER(1)
+DMA1_Channel1_IRQHandler
+ B DMA1_Channel1_IRQHandler
+
+ PUBWEAK DMA1_Channel2_IRQHandler
+ SECTION .text:CODE:REORDER(1)
+DMA1_Channel2_IRQHandler
+ B DMA1_Channel2_IRQHandler
+
+ PUBWEAK DMA1_Channel3_IRQHandler
+ SECTION .text:CODE:REORDER(1)
+DMA1_Channel3_IRQHandler
+ B DMA1_Channel3_IRQHandler
+
+ PUBWEAK DMA1_Channel4_IRQHandler
+ SECTION .text:CODE:REORDER(1)
+DMA1_Channel4_IRQHandler
+ B DMA1_Channel4_IRQHandler
+
+ PUBWEAK DMA1_Channel5_IRQHandler
+ SECTION .text:CODE:REORDER(1)
+DMA1_Channel5_IRQHandler
+ B DMA1_Channel5_IRQHandler
+
+ PUBWEAK DMA1_Channel6_IRQHandler
+ SECTION .text:CODE:REORDER(1)
+DMA1_Channel6_IRQHandler
+ B DMA1_Channel6_IRQHandler
+
+ PUBWEAK DMA1_Channel7_IRQHandler
+ SECTION .text:CODE:REORDER(1)
+DMA1_Channel7_IRQHandler
+ B DMA1_Channel7_IRQHandler
+
+ PUBWEAK ADC1_2_IRQHandler
+ SECTION .text:CODE:REORDER(1)
+ADC1_2_IRQHandler
+ B ADC1_2_IRQHandler
+
+ PUBWEAK USB_HP_CAN1_TX_IRQHandler
+ SECTION .text:CODE:REORDER(1)
+USB_HP_CAN1_TX_IRQHandler
+ B USB_HP_CAN1_TX_IRQHandler
+
+ PUBWEAK USB_LP_CAN1_RX0_IRQHandler
+ SECTION .text:CODE:REORDER(1)
+USB_LP_CAN1_RX0_IRQHandler
+ B USB_LP_CAN1_RX0_IRQHandler
+
+ PUBWEAK CAN1_RX1_IRQHandler
+ SECTION .text:CODE:REORDER(1)
+CAN1_RX1_IRQHandler
+ B CAN1_RX1_IRQHandler
+
+ PUBWEAK CAN1_SCE_IRQHandler
+ SECTION .text:CODE:REORDER(1)
+CAN1_SCE_IRQHandler
+ B CAN1_SCE_IRQHandler
+
+ PUBWEAK EXTI9_5_IRQHandler
+ SECTION .text:CODE:REORDER(1)
+EXTI9_5_IRQHandler
+ B EXTI9_5_IRQHandler
+
+ PUBWEAK TIM1_BRK_IRQHandler
+ SECTION .text:CODE:REORDER(1)
+TIM1_BRK_IRQHandler
+ B TIM1_BRK_IRQHandler
+
+ PUBWEAK TIM1_UP_IRQHandler
+ SECTION .text:CODE:REORDER(1)
+TIM1_UP_IRQHandler
+ B TIM1_UP_IRQHandler
+
+ PUBWEAK TIM1_TRG_COM_IRQHandler
+ SECTION .text:CODE:REORDER(1)
+TIM1_TRG_COM_IRQHandler
+ B TIM1_TRG_COM_IRQHandler
+
+ PUBWEAK TIM1_CC_IRQHandler
+ SECTION .text:CODE:REORDER(1)
+TIM1_CC_IRQHandler
+ B TIM1_CC_IRQHandler
+
+ PUBWEAK TIM2_IRQHandler
+ SECTION .text:CODE:REORDER(1)
+TIM2_IRQHandler
+ B TIM2_IRQHandler
+
+ PUBWEAK TIM3_IRQHandler
+ SECTION .text:CODE:REORDER(1)
+TIM3_IRQHandler
+ B TIM3_IRQHandler
+
+ PUBWEAK TIM4_IRQHandler
+ SECTION .text:CODE:REORDER(1)
+TIM4_IRQHandler
+ B TIM4_IRQHandler
+
+ PUBWEAK I2C1_EV_IRQHandler
+ SECTION .text:CODE:REORDER(1)
+I2C1_EV_IRQHandler
+ B I2C1_EV_IRQHandler
+
+ PUBWEAK I2C1_ER_IRQHandler
+ SECTION .text:CODE:REORDER(1)
+I2C1_ER_IRQHandler
+ B I2C1_ER_IRQHandler
+
+ PUBWEAK I2C2_EV_IRQHandler
+ SECTION .text:CODE:REORDER(1)
+I2C2_EV_IRQHandler
+ B I2C2_EV_IRQHandler
+
+ PUBWEAK I2C2_ER_IRQHandler
+ SECTION .text:CODE:REORDER(1)
+I2C2_ER_IRQHandler
+ B I2C2_ER_IRQHandler
+
+ PUBWEAK SPI1_IRQHandler
+ SECTION .text:CODE:REORDER(1)
+SPI1_IRQHandler
+ B SPI1_IRQHandler
+
+ PUBWEAK SPI2_IRQHandler
+ SECTION .text:CODE:REORDER(1)
+SPI2_IRQHandler
+ B SPI2_IRQHandler
+
+ PUBWEAK USART1_IRQHandler
+ SECTION .text:CODE:REORDER(1)
+USART1_IRQHandler
+ B USART1_IRQHandler
+
+ PUBWEAK USART2_IRQHandler
+ SECTION .text:CODE:REORDER(1)
+USART2_IRQHandler
+ B USART2_IRQHandler
+
+ PUBWEAK USART3_IRQHandler
+ SECTION .text:CODE:REORDER(1)
+USART3_IRQHandler
+ B USART3_IRQHandler
+
+ PUBWEAK EXTI15_10_IRQHandler
+ SECTION .text:CODE:REORDER(1)
+EXTI15_10_IRQHandler
+ B EXTI15_10_IRQHandler
+
+ PUBWEAK RTCAlarm_IRQHandler
+ SECTION .text:CODE:REORDER(1)
+RTCAlarm_IRQHandler
+ B RTCAlarm_IRQHandler
+
+ PUBWEAK USBWakeUp_IRQHandler
+ SECTION .text:CODE:REORDER(1)
+USBWakeUp_IRQHandler
+ B USBWakeUp_IRQHandler
+
+ END
+/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
diff --git a/Libraries/CMSIS/Device/ST/STM32F10x/Source/Templates/iar/startup_stm32f10x_md_vl.s b/Libraries/CMSIS/Device/ST/STM32F10x/Source/Templates/iar/startup_stm32f10x_md_vl.s
new file mode 100644
index 0000000..b4af984
--- /dev/null
+++ b/Libraries/CMSIS/Device/ST/STM32F10x/Source/Templates/iar/startup_stm32f10x_md_vl.s
@@ -0,0 +1,401 @@
+;******************** (C) COPYRIGHT 2012 STMicroelectronics ********************
+;* File Name : startup_stm32f10x_md_vl.s
+;* Author : MCD Application Team
+;* Version : V3.6.1
+;* Date : 09-March-2012
+;* Description : STM32F10x Medium Density Value Line Devices vector table
+;* for EWARM toolchain.
+;* This module performs:
+;* - Set the initial SP
+;* - Configure the clock system
+;* - Set the initial PC == __iar_program_start,
+;* - Set the vector table entries with the exceptions ISR
+;* address.
+;* After Reset the Cortex-M3 processor is in Thread mode,
+;* priority is Privileged, and the Stack is set to Main.
+;********************************************************************************
+;*
+;* Licensed under MCD-ST Liberty SW License Agreement V2, (the "License");
+;* You may not use this file except in compliance with the License.
+;* You may obtain a copy of the License at:
+;*
+;* http://www.st.com/software_license_agreement_liberty_v2
+;*
+;* Unless required by applicable law or agreed to in writing, software
+;* distributed under the License is distributed on an "AS IS" BASIS,
+;* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+;* See the License for the specific language governing permissions and
+;* limitations under the License.
+;*
+;*******************************************************************************
+;
+;
+; The modules in this file are included in the libraries, and may be replaced
+; by any user-defined modules that define the PUBLIC symbol _program_start or
+; a user defined start symbol.
+; To override the cstartup defined in the library, simply add your modified
+; version to the workbench project.
+;
+; The vector table is normally located at address 0.
+; When debugging in RAM, it can be located in RAM, aligned to at least 2^6.
+; The name "__vector_table" has special meaning for C-SPY:
+; it is where the SP start value is found, and the NVIC vector
+; table register (VTOR) is initialized to this address if != 0.
+;
+; Cortex-M version
+;
+
+ MODULE ?cstartup
+
+ ;; Forward declaration of sections.
+ SECTION CSTACK:DATA:NOROOT(3)
+
+ SECTION .intvec:CODE:NOROOT(2)
+
+ EXTERN __iar_program_start
+ EXTERN SystemInit
+ PUBLIC __vector_table
+
+ DATA
+__vector_table
+ DCD sfe(CSTACK)
+ DCD Reset_Handler ; Reset Handler
+ DCD NMI_Handler ; NMI Handler
+ DCD HardFault_Handler ; Hard Fault Handler
+ DCD MemManage_Handler ; MPU Fault Handler
+ DCD BusFault_Handler ; Bus Fault Handler
+ DCD UsageFault_Handler ; Usage Fault Handler
+ DCD 0 ; Reserved
+ DCD 0 ; Reserved
+ DCD 0 ; Reserved
+ DCD 0 ; Reserved
+ DCD SVC_Handler ; SVCall Handler
+ DCD DebugMon_Handler ; Debug Monitor Handler
+ DCD 0 ; Reserved
+ DCD PendSV_Handler ; PendSV Handler
+ DCD SysTick_Handler ; SysTick Handler
+
+ ; External Interrupts
+ DCD WWDG_IRQHandler ; Window Watchdog
+ DCD PVD_IRQHandler ; PVD through EXTI Line detect
+ DCD TAMPER_IRQHandler ; Tamper
+ DCD RTC_IRQHandler ; RTC
+ DCD FLASH_IRQHandler ; Flash
+ DCD RCC_IRQHandler ; RCC
+ DCD EXTI0_IRQHandler ; EXTI Line 0
+ DCD EXTI1_IRQHandler ; EXTI Line 1
+ DCD EXTI2_IRQHandler ; EXTI Line 2
+ DCD EXTI3_IRQHandler ; EXTI Line 3
+ DCD EXTI4_IRQHandler ; EXTI Line 4
+ DCD DMA1_Channel1_IRQHandler ; DMA1 Channel 1
+ DCD DMA1_Channel2_IRQHandler ; DMA1 Channel 2
+ DCD DMA1_Channel3_IRQHandler ; DMA1 Channel 3
+ DCD DMA1_Channel4_IRQHandler ; DMA1 Channel 4
+ DCD DMA1_Channel5_IRQHandler ; DMA1 Channel 5
+ DCD DMA1_Channel6_IRQHandler ; DMA1 Channel 6
+ DCD DMA1_Channel7_IRQHandler ; DMA1 Channel 7
+ DCD ADC1_IRQHandler ; ADC1
+ DCD 0 ; Reserved
+ DCD 0 ; Reserved
+ DCD 0 ; Reserved
+ DCD 0 ; Reserved
+ DCD EXTI9_5_IRQHandler ; EXTI Line 9..5
+ DCD TIM1_BRK_TIM15_IRQHandler ; TIM1 Break and TIM15
+ DCD TIM1_UP_TIM16_IRQHandler ; TIM1 Update and TIM16
+ DCD TIM1_TRG_COM_TIM17_IRQHandler ; TIM1 Trigger and Commutation and TIM17
+ DCD TIM1_CC_IRQHandler ; TIM1 Capture Compare
+ DCD TIM2_IRQHandler ; TIM2
+ DCD TIM3_IRQHandler ; TIM3
+ DCD TIM4_IRQHandler ; TIM4
+ DCD I2C1_EV_IRQHandler ; I2C1 Event
+ DCD I2C1_ER_IRQHandler ; I2C1 Error
+ DCD I2C2_EV_IRQHandler ; I2C2 Event
+ DCD I2C2_ER_IRQHandler ; I2C2 Error
+ DCD SPI1_IRQHandler ; SPI1
+ DCD SPI2_IRQHandler ; SPI2
+ DCD USART1_IRQHandler ; USART1
+ DCD USART2_IRQHandler ; USART2
+ DCD USART3_IRQHandler ; USART3
+ DCD EXTI15_10_IRQHandler ; EXTI Line 15..10
+ DCD RTCAlarm_IRQHandler ; RTC Alarm through EXTI Line
+ DCD CEC_IRQHandler ; HDMI-CEC
+ DCD 0 ; Reserved
+ DCD 0 ; Reserved
+ DCD 0 ; Reserved
+ DCD 0 ; Reserved
+ DCD 0 ; Reserved
+ DCD 0 ; Reserved
+ DCD 0 ; Reserved
+ DCD 0 ; Reserved
+ DCD 0 ; Reserved
+ DCD 0 ; Reserved
+ DCD 0 ; Reserved
+ DCD TIM6_DAC_IRQHandler ; TIM6 and DAC underrun
+ DCD TIM7_IRQHandler ; TIM7
+
+;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
+;;
+;; Default interrupt handlers.
+;;
+ THUMB
+
+ PUBWEAK Reset_Handler
+ SECTION .text:CODE:REORDER(2)
+Reset_Handler
+ LDR R0, =SystemInit
+ BLX R0
+ LDR R0, =__iar_program_start
+ BX R0
+
+ PUBWEAK NMI_Handler
+ SECTION .text:CODE:REORDER(1)
+NMI_Handler
+ B NMI_Handler
+
+ PUBWEAK HardFault_Handler
+ SECTION .text:CODE:REORDER(1)
+HardFault_Handler
+ B HardFault_Handler
+
+ PUBWEAK MemManage_Handler
+ SECTION .text:CODE:REORDER(1)
+MemManage_Handler
+ B MemManage_Handler
+
+ PUBWEAK BusFault_Handler
+ SECTION .text:CODE:REORDER(1)
+BusFault_Handler
+ B BusFault_Handler
+
+ PUBWEAK UsageFault_Handler
+ SECTION .text:CODE:REORDER(1)
+UsageFault_Handler
+ B UsageFault_Handler
+
+ PUBWEAK SVC_Handler
+ SECTION .text:CODE:REORDER(1)
+SVC_Handler
+ B SVC_Handler
+
+ PUBWEAK DebugMon_Handler
+ SECTION .text:CODE:REORDER(1)
+DebugMon_Handler
+ B DebugMon_Handler
+
+ PUBWEAK PendSV_Handler
+ SECTION .text:CODE:REORDER(1)
+PendSV_Handler
+ B PendSV_Handler
+
+ PUBWEAK SysTick_Handler
+ SECTION .text:CODE:REORDER(1)
+SysTick_Handler
+ B SysTick_Handler
+
+ PUBWEAK WWDG_IRQHandler
+ SECTION .text:CODE:REORDER(1)
+WWDG_IRQHandler
+ B WWDG_IRQHandler
+
+ PUBWEAK PVD_IRQHandler
+ SECTION .text:CODE:REORDER(1)
+PVD_IRQHandler
+ B PVD_IRQHandler
+
+ PUBWEAK TAMPER_IRQHandler
+ SECTION .text:CODE:REORDER(1)
+TAMPER_IRQHandler
+ B TAMPER_IRQHandler
+
+ PUBWEAK RTC_IRQHandler
+ SECTION .text:CODE:REORDER(1)
+RTC_IRQHandler
+ B RTC_IRQHandler
+
+ PUBWEAK FLASH_IRQHandler
+ SECTION .text:CODE:REORDER(1)
+FLASH_IRQHandler
+ B FLASH_IRQHandler
+
+ PUBWEAK RCC_IRQHandler
+ SECTION .text:CODE:REORDER(1)
+RCC_IRQHandler
+ B RCC_IRQHandler
+
+ PUBWEAK EXTI0_IRQHandler
+ SECTION .text:CODE:REORDER(1)
+EXTI0_IRQHandler
+ B EXTI0_IRQHandler
+
+ PUBWEAK EXTI1_IRQHandler
+ SECTION .text:CODE:REORDER(1)
+EXTI1_IRQHandler
+ B EXTI1_IRQHandler
+
+ PUBWEAK EXTI2_IRQHandler
+ SECTION .text:CODE:REORDER(1)
+EXTI2_IRQHandler
+ B EXTI2_IRQHandler
+
+ PUBWEAK EXTI3_IRQHandler
+ SECTION .text:CODE:REORDER(1)
+EXTI3_IRQHandler
+ B EXTI3_IRQHandler
+
+ PUBWEAK EXTI4_IRQHandler
+ SECTION .text:CODE:REORDER(1)
+EXTI4_IRQHandler
+ B EXTI4_IRQHandler
+
+ PUBWEAK DMA1_Channel1_IRQHandler
+ SECTION .text:CODE:REORDER(1)
+DMA1_Channel1_IRQHandler
+ B DMA1_Channel1_IRQHandler
+
+ PUBWEAK DMA1_Channel2_IRQHandler
+ SECTION .text:CODE:REORDER(1)
+DMA1_Channel2_IRQHandler
+ B DMA1_Channel2_IRQHandler
+
+ PUBWEAK DMA1_Channel3_IRQHandler
+ SECTION .text:CODE:REORDER(1)
+DMA1_Channel3_IRQHandler
+ B DMA1_Channel3_IRQHandler
+
+ PUBWEAK DMA1_Channel4_IRQHandler
+ SECTION .text:CODE:REORDER(1)
+DMA1_Channel4_IRQHandler
+ B DMA1_Channel4_IRQHandler
+
+ PUBWEAK DMA1_Channel5_IRQHandler
+ SECTION .text:CODE:REORDER(1)
+DMA1_Channel5_IRQHandler
+ B DMA1_Channel5_IRQHandler
+
+ PUBWEAK DMA1_Channel6_IRQHandler
+ SECTION .text:CODE:REORDER(1)
+DMA1_Channel6_IRQHandler
+ B DMA1_Channel6_IRQHandler
+
+ PUBWEAK DMA1_Channel7_IRQHandler
+ SECTION .text:CODE:REORDER(1)
+DMA1_Channel7_IRQHandler
+ B DMA1_Channel7_IRQHandler
+
+ PUBWEAK ADC1_IRQHandler
+ SECTION .text:CODE:REORDER(1)
+ADC1_IRQHandler
+ B ADC1_IRQHandler
+
+ PUBWEAK EXTI9_5_IRQHandler
+ SECTION .text:CODE:REORDER(1)
+EXTI9_5_IRQHandler
+ B EXTI9_5_IRQHandler
+
+ PUBWEAK TIM1_BRK_TIM15_IRQHandler
+ SECTION .text:CODE:REORDER(1)
+TIM1_BRK_TIM15_IRQHandler
+ B TIM1_BRK_TIM15_IRQHandler
+
+ PUBWEAK TIM1_UP_TIM16_IRQHandler
+ SECTION .text:CODE:REORDER(1)
+TIM1_UP_TIM16_IRQHandler
+ B TIM1_UP_TIM16_IRQHandler
+
+ PUBWEAK TIM1_TRG_COM_TIM17_IRQHandler
+ SECTION .text:CODE:REORDER(1)
+TIM1_TRG_COM_TIM17_IRQHandler
+ B TIM1_TRG_COM_TIM17_IRQHandler
+
+ PUBWEAK TIM1_CC_IRQHandler
+ SECTION .text:CODE:REORDER(1)
+TIM1_CC_IRQHandler
+ B TIM1_CC_IRQHandler
+
+ PUBWEAK TIM2_IRQHandler
+ SECTION .text:CODE:REORDER(1)
+TIM2_IRQHandler
+ B TIM2_IRQHandler
+
+ PUBWEAK TIM3_IRQHandler
+ SECTION .text:CODE:REORDER(1)
+TIM3_IRQHandler
+ B TIM3_IRQHandler
+
+ PUBWEAK TIM4_IRQHandler
+ SECTION .text:CODE:REORDER(1)
+TIM4_IRQHandler
+ B TIM4_IRQHandler
+
+ PUBWEAK I2C1_EV_IRQHandler
+ SECTION .text:CODE:REORDER(1)
+I2C1_EV_IRQHandler
+ B I2C1_EV_IRQHandler
+
+ PUBWEAK I2C1_ER_IRQHandler
+ SECTION .text:CODE:REORDER(1)
+I2C1_ER_IRQHandler
+ B I2C1_ER_IRQHandler
+
+ PUBWEAK I2C2_EV_IRQHandler
+ SECTION .text:CODE:REORDER(1)
+I2C2_EV_IRQHandler
+ B I2C2_EV_IRQHandler
+
+ PUBWEAK I2C2_ER_IRQHandler
+ SECTION .text:CODE:REORDER(1)
+I2C2_ER_IRQHandler
+ B I2C2_ER_IRQHandler
+
+ PUBWEAK SPI1_IRQHandler
+ SECTION .text:CODE:REORDER(1)
+SPI1_IRQHandler
+ B SPI1_IRQHandler
+
+ PUBWEAK SPI2_IRQHandler
+ SECTION .text:CODE:REORDER(1)
+SPI2_IRQHandler
+ B SPI2_IRQHandler
+
+ PUBWEAK USART1_IRQHandler
+ SECTION .text:CODE:REORDER(1)
+USART1_IRQHandler
+ B USART1_IRQHandler
+
+ PUBWEAK USART2_IRQHandler
+ SECTION .text:CODE:REORDER(1)
+USART2_IRQHandler
+ B USART2_IRQHandler
+
+ PUBWEAK USART3_IRQHandler
+ SECTION .text:CODE:REORDER(1)
+USART3_IRQHandler
+ B USART3_IRQHandler
+
+ PUBWEAK EXTI15_10_IRQHandler
+ SECTION .text:CODE:REORDER(1)
+EXTI15_10_IRQHandler
+ B EXTI15_10_IRQHandler
+
+ PUBWEAK RTCAlarm_IRQHandler
+ SECTION .text:CODE:REORDER(1)
+RTCAlarm_IRQHandler
+ B RTCAlarm_IRQHandler
+
+ PUBWEAK CEC_IRQHandler
+ SECTION .text:CODE:REORDER(1)
+CEC_IRQHandler
+ B CEC_IRQHandler
+
+ PUBWEAK TIM6_DAC_IRQHandler
+ SECTION .text:CODE:REORDER(1)
+TIM6_DAC_IRQHandler
+ B TIM6_DAC_IRQHandler
+
+ PUBWEAK TIM7_IRQHandler
+ SECTION .text:CODE:REORDER(1)
+TIM7_IRQHandler
+ B TIM7_IRQHandler
+
+ END
+/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
diff --git a/Libraries/CMSIS/Device/ST/STM32F10x/Source/Templates/iar/startup_stm32f10x_xl.s b/Libraries/CMSIS/Device/ST/STM32F10x/Source/Templates/iar/startup_stm32f10x_xl.s
new file mode 100644
index 0000000..c85fb39
--- /dev/null
+++ b/Libraries/CMSIS/Device/ST/STM32F10x/Source/Templates/iar/startup_stm32f10x_xl.s
@@ -0,0 +1,503 @@
+;******************** (C) COPYRIGHT 2012 STMicroelectronics ********************
+;* File Name : startup_stm32f10x_xl.s
+;* Author : MCD Application Team
+;* Version : V3.6.1
+;* Date : 09-March-2012
+;* Description : STM32F10x XL-Density Devices vector table for EWARM
+;* toolchain.
+;* This module performs:
+;* - Set the initial SP
+;* - Configure the clock system and the external SRAM
+;* mounted on STM3210E-EVAL board to be used as data
+;* memory (optional, to be enabled by user)
+;* - Set the initial PC == __iar_program_start,
+;* - Set the vector table entries with the exceptions ISR address,
+;* After Reset the Cortex-M3 processor is in Thread mode,
+;* priority is Privileged, and the Stack is set to Main.
+;********************************************************************************
+;*
+;* Licensed under MCD-ST Liberty SW License Agreement V2, (the "License");
+;* You may not use this file except in compliance with the License.
+;* You may obtain a copy of the License at:
+;*
+;* http://www.st.com/software_license_agreement_liberty_v2
+;*
+;* Unless required by applicable law or agreed to in writing, software
+;* distributed under the License is distributed on an "AS IS" BASIS,
+;* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+;* See the License for the specific language governing permissions and
+;* limitations under the License.
+;*
+;*******************************************************************************
+;
+;
+; The modules in this file are included in the libraries, and may be replaced
+; by any user-defined modules that define the PUBLIC symbol _program_start or
+; a user defined start symbol.
+; To override the cstartup defined in the library, simply add your modified
+; version to the workbench project.
+;
+; The vector table is normally located at address 0.
+; When debugging in RAM, it can be located in RAM, aligned to at least 2^6.
+; The name "__vector_table" has special meaning for C-SPY:
+; it is where the SP start value is found, and the NVIC vector
+; table register (VTOR) is initialized to this address if != 0.
+;
+; Cortex-M version
+;
+
+ MODULE ?cstartup
+
+ ;; Forward declaration of sections.
+ SECTION CSTACK:DATA:NOROOT(3)
+
+ SECTION .intvec:CODE:NOROOT(2)
+
+ EXTERN __iar_program_start
+ EXTERN SystemInit
+ PUBLIC __vector_table
+
+ DATA
+
+__vector_table
+ DCD sfe(CSTACK)
+ DCD Reset_Handler ; Reset Handler
+ DCD NMI_Handler ; NMI Handler
+ DCD HardFault_Handler ; Hard Fault Handler
+ DCD MemManage_Handler ; MPU Fault Handler
+ DCD BusFault_Handler ; Bus Fault Handler
+ DCD UsageFault_Handler ; Usage Fault Handler
+ DCD 0 ; Reserved
+ DCD 0 ; Reserved
+ DCD 0 ; Reserved
+ DCD 0 ; Reserved
+ DCD SVC_Handler ; SVCall Handler
+ DCD DebugMon_Handler ; Debug Monitor Handler
+ DCD 0 ; Reserved
+ DCD PendSV_Handler ; PendSV Handler
+ DCD SysTick_Handler ; SysTick Handler
+
+ ; External Interrupts
+ DCD WWDG_IRQHandler ; Window Watchdog
+ DCD PVD_IRQHandler ; PVD through EXTI Line detect
+ DCD TAMPER_IRQHandler ; Tamper
+ DCD RTC_IRQHandler ; RTC
+ DCD FLASH_IRQHandler ; Flash
+ DCD RCC_IRQHandler ; RCC
+ DCD EXTI0_IRQHandler ; EXTI Line 0
+ DCD EXTI1_IRQHandler ; EXTI Line 1
+ DCD EXTI2_IRQHandler ; EXTI Line 2
+ DCD EXTI3_IRQHandler ; EXTI Line 3
+ DCD EXTI4_IRQHandler ; EXTI Line 4
+ DCD DMA1_Channel1_IRQHandler ; DMA1 Channel 1
+ DCD DMA1_Channel2_IRQHandler ; DMA1 Channel 2
+ DCD DMA1_Channel3_IRQHandler ; DMA1 Channel 3
+ DCD DMA1_Channel4_IRQHandler ; DMA1 Channel 4
+ DCD DMA1_Channel5_IRQHandler ; DMA1 Channel 5
+ DCD DMA1_Channel6_IRQHandler ; DMA1 Channel 6
+ DCD DMA1_Channel7_IRQHandler ; DMA1 Channel 7
+ DCD ADC1_2_IRQHandler ; ADC1 & ADC2
+ DCD USB_HP_CAN1_TX_IRQHandler ; USB High Priority or CAN1 TX
+ DCD USB_LP_CAN1_RX0_IRQHandler ; USB Low Priority or CAN1 RX0
+ DCD CAN1_RX1_IRQHandler ; CAN1 RX1
+ DCD CAN1_SCE_IRQHandler ; CAN1 SCE
+ DCD EXTI9_5_IRQHandler ; EXTI Line 9..5
+ DCD TIM1_BRK_TIM9_IRQHandler ; TIM1 Break and TIM9
+ DCD TIM1_UP_TIM10_IRQHandler ; TIM1 Update and TIM10
+ DCD TIM1_TRG_COM_TIM11_IRQHandler ; TIM1 Trigger and Commutation and TIM11
+ DCD TIM1_CC_IRQHandler ; TIM1 Capture Compare
+ DCD TIM2_IRQHandler ; TIM2
+ DCD TIM3_IRQHandler ; TIM3
+ DCD TIM4_IRQHandler ; TIM4
+ DCD I2C1_EV_IRQHandler ; I2C1 Event
+ DCD I2C1_ER_IRQHandler ; I2C1 Error
+ DCD I2C2_EV_IRQHandler ; I2C2 Event
+ DCD I2C2_ER_IRQHandler ; I2C2 Error
+ DCD SPI1_IRQHandler ; SPI1
+ DCD SPI2_IRQHandler ; SPI2
+ DCD USART1_IRQHandler ; USART1
+ DCD USART2_IRQHandler ; USART2
+ DCD USART3_IRQHandler ; USART3
+ DCD EXTI15_10_IRQHandler ; EXTI Line 15..10
+ DCD RTCAlarm_IRQHandler ; RTC Alarm through EXTI Line
+ DCD USBWakeUp_IRQHandler ; USB Wakeup from suspend
+ DCD TIM8_BRK_TIM12_IRQHandler ; TIM8 Break and TIM12
+ DCD TIM8_UP_TIM13_IRQHandler ; TIM8 Update and TIM13
+ DCD TIM8_TRG_COM_TIM14_IRQHandler ; TIM8 Trigger and Commutation and TIM14
+ DCD TIM8_CC_IRQHandler ; TIM8 Capture Compare
+ DCD ADC3_IRQHandler ; ADC3
+ DCD FSMC_IRQHandler ; FSMC
+ DCD SDIO_IRQHandler ; SDIO
+ DCD TIM5_IRQHandler ; TIM5
+ DCD SPI3_IRQHandler ; SPI3
+ DCD UART4_IRQHandler ; UART4
+ DCD UART5_IRQHandler ; UART5
+ DCD TIM6_IRQHandler ; TIM6
+ DCD TIM7_IRQHandler ; TIM7
+ DCD DMA2_Channel1_IRQHandler ; DMA2 Channel1
+ DCD DMA2_Channel2_IRQHandler ; DMA2 Channel2
+ DCD DMA2_Channel3_IRQHandler ; DMA2 Channel3
+ DCD DMA2_Channel4_5_IRQHandler ; DMA2 Channel4 & Channel5
+;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
+;;
+;; Default interrupt handlers.
+;;
+ THUMB
+
+ PUBWEAK Reset_Handler
+ SECTION .text:CODE:REORDER(2)
+Reset_Handler
+ LDR R0, =SystemInit
+ BLX R0
+ LDR R0, =__iar_program_start
+ BX R0
+
+ PUBWEAK NMI_Handler
+ SECTION .text:CODE:REORDER(1)
+NMI_Handler
+ B NMI_Handler
+
+ PUBWEAK HardFault_Handler
+ SECTION .text:CODE:REORDER(1)
+HardFault_Handler
+ B HardFault_Handler
+
+ PUBWEAK MemManage_Handler
+ SECTION .text:CODE:REORDER(1)
+MemManage_Handler
+ B MemManage_Handler
+
+ PUBWEAK BusFault_Handler
+ SECTION .text:CODE:REORDER(1)
+BusFault_Handler
+ B BusFault_Handler
+
+ PUBWEAK UsageFault_Handler
+ SECTION .text:CODE:REORDER(1)
+UsageFault_Handler
+ B UsageFault_Handler
+
+ PUBWEAK SVC_Handler
+ SECTION .text:CODE:REORDER(1)
+SVC_Handler
+ B SVC_Handler
+
+ PUBWEAK DebugMon_Handler
+ SECTION .text:CODE:REORDER(1)
+DebugMon_Handler
+ B DebugMon_Handler
+
+ PUBWEAK PendSV_Handler
+ SECTION .text:CODE:REORDER(1)
+PendSV_Handler
+ B PendSV_Handler
+
+ PUBWEAK SysTick_Handler
+ SECTION .text:CODE:REORDER(1)
+SysTick_Handler
+ B SysTick_Handler
+
+ PUBWEAK WWDG_IRQHandler
+ SECTION .text:CODE:REORDER(1)
+WWDG_IRQHandler
+ B WWDG_IRQHandler
+
+ PUBWEAK PVD_IRQHandler
+ SECTION .text:CODE:REORDER(1)
+PVD_IRQHandler
+ B PVD_IRQHandler
+
+ PUBWEAK TAMPER_IRQHandler
+ SECTION .text:CODE:REORDER(1)
+TAMPER_IRQHandler
+ B TAMPER_IRQHandler
+
+ PUBWEAK RTC_IRQHandler
+ SECTION .text:CODE:REORDER(1)
+RTC_IRQHandler
+ B RTC_IRQHandler
+
+ PUBWEAK FLASH_IRQHandler
+ SECTION .text:CODE:REORDER(1)
+FLASH_IRQHandler
+ B FLASH_IRQHandler
+
+ PUBWEAK RCC_IRQHandler
+ SECTION .text:CODE:REORDER(1)
+RCC_IRQHandler
+ B RCC_IRQHandler
+
+ PUBWEAK EXTI0_IRQHandler
+ SECTION .text:CODE:REORDER(1)
+EXTI0_IRQHandler
+ B EXTI0_IRQHandler
+
+ PUBWEAK EXTI1_IRQHandler
+ SECTION .text:CODE:REORDER(1)
+EXTI1_IRQHandler
+ B EXTI1_IRQHandler
+
+ PUBWEAK EXTI2_IRQHandler
+ SECTION .text:CODE:REORDER(1)
+EXTI2_IRQHandler
+ B EXTI2_IRQHandler
+
+ PUBWEAK EXTI3_IRQHandler
+ SECTION .text:CODE:REORDER(1)
+EXTI3_IRQHandler
+ B EXTI3_IRQHandler
+
+ PUBWEAK EXTI4_IRQHandler
+ SECTION .text:CODE:REORDER(1)
+EXTI4_IRQHandler
+ B EXTI4_IRQHandler
+
+ PUBWEAK DMA1_Channel1_IRQHandler
+ SECTION .text:CODE:REORDER(1)
+DMA1_Channel1_IRQHandler
+ B DMA1_Channel1_IRQHandler
+
+ PUBWEAK DMA1_Channel2_IRQHandler
+ SECTION .text:CODE:REORDER(1)
+DMA1_Channel2_IRQHandler
+ B DMA1_Channel2_IRQHandler
+
+ PUBWEAK DMA1_Channel3_IRQHandler
+ SECTION .text:CODE:REORDER(1)
+DMA1_Channel3_IRQHandler
+ B DMA1_Channel3_IRQHandler
+
+ PUBWEAK DMA1_Channel4_IRQHandler
+ SECTION .text:CODE:REORDER(1)
+DMA1_Channel4_IRQHandler
+ B DMA1_Channel4_IRQHandler
+
+ PUBWEAK DMA1_Channel5_IRQHandler
+ SECTION .text:CODE:REORDER(1)
+DMA1_Channel5_IRQHandler
+ B DMA1_Channel5_IRQHandler
+
+ PUBWEAK DMA1_Channel6_IRQHandler
+ SECTION .text:CODE:REORDER(1)
+DMA1_Channel6_IRQHandler
+ B DMA1_Channel6_IRQHandler
+
+ PUBWEAK DMA1_Channel7_IRQHandler
+ SECTION .text:CODE:REORDER(1)
+DMA1_Channel7_IRQHandler
+ B DMA1_Channel7_IRQHandler
+
+ PUBWEAK ADC1_2_IRQHandler
+ SECTION .text:CODE:REORDER(1)
+ADC1_2_IRQHandler
+ B ADC1_2_IRQHandler
+
+ PUBWEAK USB_HP_CAN1_TX_IRQHandler
+ SECTION .text:CODE:REORDER(1)
+USB_HP_CAN1_TX_IRQHandler
+ B USB_HP_CAN1_TX_IRQHandler
+
+ PUBWEAK USB_LP_CAN1_RX0_IRQHandler
+ SECTION .text:CODE:REORDER(1)
+USB_LP_CAN1_RX0_IRQHandler
+ B USB_LP_CAN1_RX0_IRQHandler
+
+ PUBWEAK CAN1_RX1_IRQHandler
+ SECTION .text:CODE:REORDER(1)
+CAN1_RX1_IRQHandler
+ B CAN1_RX1_IRQHandler
+
+ PUBWEAK CAN1_SCE_IRQHandler
+ SECTION .text:CODE:REORDER(1)
+CAN1_SCE_IRQHandler
+ B CAN1_SCE_IRQHandler
+
+ PUBWEAK EXTI9_5_IRQHandler
+ SECTION .text:CODE:REORDER(1)
+EXTI9_5_IRQHandler
+ B EXTI9_5_IRQHandler
+
+ PUBWEAK TIM1_BRK_TIM9_IRQHandler
+ SECTION .text:CODE:REORDER(1)
+TIM1_BRK_TIM9_IRQHandler
+ B TIM1_BRK_TIM9_IRQHandler
+
+ PUBWEAK TIM1_UP_TIM10_IRQHandler
+ SECTION .text:CODE:REORDER(1)
+TIM1_UP_TIM10_IRQHandler
+ B TIM1_UP_TIM10_IRQHandler
+
+ PUBWEAK TIM1_TRG_COM_TIM11_IRQHandler
+ SECTION .text:CODE:REORDER(1)
+TIM1_TRG_COM_TIM11_IRQHandler
+ B TIM1_TRG_COM_TIM11_IRQHandler
+
+ PUBWEAK TIM1_CC_IRQHandler
+ SECTION .text:CODE:REORDER(1)
+TIM1_CC_IRQHandler
+ B TIM1_CC_IRQHandler
+
+ PUBWEAK TIM2_IRQHandler
+ SECTION .text:CODE:REORDER(1)
+TIM2_IRQHandler
+ B TIM2_IRQHandler
+
+ PUBWEAK TIM3_IRQHandler
+ SECTION .text:CODE:REORDER(1)
+TIM3_IRQHandler
+ B TIM3_IRQHandler
+
+ PUBWEAK TIM4_IRQHandler
+ SECTION .text:CODE:REORDER(1)
+TIM4_IRQHandler
+ B TIM4_IRQHandler
+
+ PUBWEAK I2C1_EV_IRQHandler
+ SECTION .text:CODE:REORDER(1)
+I2C1_EV_IRQHandler
+ B I2C1_EV_IRQHandler
+
+ PUBWEAK I2C1_ER_IRQHandler
+ SECTION .text:CODE:REORDER(1)
+I2C1_ER_IRQHandler
+ B I2C1_ER_IRQHandler
+
+ PUBWEAK I2C2_EV_IRQHandler
+ SECTION .text:CODE:REORDER(1)
+I2C2_EV_IRQHandler
+ B I2C2_EV_IRQHandler
+
+ PUBWEAK I2C2_ER_IRQHandler
+ SECTION .text:CODE:REORDER(1)
+I2C2_ER_IRQHandler
+ B I2C2_ER_IRQHandler
+
+ PUBWEAK SPI1_IRQHandler
+ SECTION .text:CODE:REORDER(1)
+SPI1_IRQHandler
+ B SPI1_IRQHandler
+
+ PUBWEAK SPI2_IRQHandler
+ SECTION .text:CODE:REORDER(1)
+SPI2_IRQHandler
+ B SPI2_IRQHandler
+
+ PUBWEAK USART1_IRQHandler
+ SECTION .text:CODE:REORDER(1)
+USART1_IRQHandler
+ B USART1_IRQHandler
+
+ PUBWEAK USART2_IRQHandler
+ SECTION .text:CODE:REORDER(1)
+USART2_IRQHandler
+ B USART2_IRQHandler
+
+ PUBWEAK USART3_IRQHandler
+ SECTION .text:CODE:REORDER(1)
+USART3_IRQHandler
+ B USART3_IRQHandler
+
+ PUBWEAK EXTI15_10_IRQHandler
+ SECTION .text:CODE:REORDER(1)
+EXTI15_10_IRQHandler
+ B EXTI15_10_IRQHandler
+
+ PUBWEAK RTCAlarm_IRQHandler
+ SECTION .text:CODE:REORDER(1)
+RTCAlarm_IRQHandler
+ B RTCAlarm_IRQHandler
+
+ PUBWEAK USBWakeUp_IRQHandler
+ SECTION .text:CODE:REORDER(1)
+USBWakeUp_IRQHandler
+ B USBWakeUp_IRQHandler
+
+ PUBWEAK TIM8_BRK_TIM12_IRQHandler
+ SECTION .text:CODE:REORDER(1)
+TIM8_BRK_TIM12_IRQHandler
+ B TIM8_BRK_TIM12_IRQHandler
+
+ PUBWEAK TIM8_UP_TIM13_IRQHandler
+ SECTION .text:CODE:REORDER(1)
+TIM8_UP_TIM13_IRQHandler
+ B TIM8_UP_TIM13_IRQHandler
+
+ PUBWEAK TIM8_TRG_COM_TIM14_IRQHandler
+ SECTION .text:CODE:REORDER(1)
+TIM8_TRG_COM_TIM14_IRQHandler
+ B TIM8_TRG_COM_TIM14_IRQHandler
+
+ PUBWEAK TIM8_CC_IRQHandler
+ SECTION .text:CODE:REORDER(1)
+TIM8_CC_IRQHandler
+ B TIM8_CC_IRQHandler
+
+ PUBWEAK ADC3_IRQHandler
+ SECTION .text:CODE:REORDER(1)
+ADC3_IRQHandler
+ B ADC3_IRQHandler
+
+ PUBWEAK FSMC_IRQHandler
+ SECTION .text:CODE:REORDER(1)
+FSMC_IRQHandler
+ B FSMC_IRQHandler
+
+ PUBWEAK SDIO_IRQHandler
+ SECTION .text:CODE:REORDER(1)
+SDIO_IRQHandler
+ B SDIO_IRQHandler
+
+ PUBWEAK TIM5_IRQHandler
+ SECTION .text:CODE:REORDER(1)
+TIM5_IRQHandler
+ B TIM5_IRQHandler
+
+ PUBWEAK SPI3_IRQHandler
+ SECTION .text:CODE:REORDER(1)
+SPI3_IRQHandler
+ B SPI3_IRQHandler
+
+ PUBWEAK UART4_IRQHandler
+ SECTION .text:CODE:REORDER(1)
+UART4_IRQHandler
+ B UART4_IRQHandler
+
+ PUBWEAK UART5_IRQHandler
+ SECTION .text:CODE:REORDER(1)
+UART5_IRQHandler
+ B UART5_IRQHandler
+
+ PUBWEAK TIM6_IRQHandler
+ SECTION .text:CODE:REORDER(1)
+TIM6_IRQHandler
+ B TIM6_IRQHandler
+
+ PUBWEAK TIM7_IRQHandler
+ SECTION .text:CODE:REORDER(1)
+TIM7_IRQHandler
+ B TIM7_IRQHandler
+
+ PUBWEAK DMA2_Channel1_IRQHandler
+ SECTION .text:CODE:REORDER(1)
+DMA2_Channel1_IRQHandler
+ B DMA2_Channel1_IRQHandler
+
+ PUBWEAK DMA2_Channel2_IRQHandler
+ SECTION .text:CODE:REORDER(1)
+DMA2_Channel2_IRQHandler
+ B DMA2_Channel2_IRQHandler
+
+ PUBWEAK DMA2_Channel3_IRQHandler
+ SECTION .text:CODE:REORDER(1)
+DMA2_Channel3_IRQHandler
+ B DMA2_Channel3_IRQHandler
+
+ PUBWEAK DMA2_Channel4_5_IRQHandler
+ SECTION .text:CODE:REORDER(1)
+DMA2_Channel4_5_IRQHandler
+ B DMA2_Channel4_5_IRQHandler
+
+
+ END
+
+/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
diff --git a/Libraries/CMSIS/Device/ST/STM32F10x/Source/Templates/system_stm32f10x.c b/Libraries/CMSIS/Device/ST/STM32F10x/Source/Templates/system_stm32f10x.c
new file mode 100644
index 0000000..c0489e7
--- /dev/null
+++ b/Libraries/CMSIS/Device/ST/STM32F10x/Source/Templates/system_stm32f10x.c
@@ -0,0 +1,1100 @@
+/**
+ ******************************************************************************
+ * @file system_stm32f10x.c
+ * @author MCD Application Team
+ * @version V3.6.1
+ * @date 09-March-2012
+ * @brief CMSIS Cortex-M3 Device Peripheral Access Layer System Source File.
+ *
+ * 1. This file provides two functions and one global variable to be called from
+ * user application:
+ * - SystemInit(): Setups the system clock (System clock source, PLL Multiplier
+ * factors, AHB/APBx prescalers and Flash settings).
+ * This function is called at startup just after reset and
+ * before branch to main program. This call is made inside
+ * the "startup_stm32f10x_xx.s" file.
+ *
+ * - SystemCoreClock variable: Contains the core clock (HCLK), it can be used
+ * by the user application to setup the SysTick
+ * timer or configure other parameters.
+ *
+ * - SystemCoreClockUpdate(): Updates the variable SystemCoreClock and must
+ * be called whenever the core clock is changed
+ * during program execution.
+ *
+ * 2. After each device reset the HSI (8 MHz) is used as system clock source.
+ * Then SystemInit() function is called, in "startup_stm32f10x_xx.s" file, to
+ * configure the system clock before to branch to main program.
+ *
+ * 3. If the system clock source selected by user fails to startup, the SystemInit()
+ * function will do nothing and HSI still used as system clock source. User can
+ * add some code to deal with this issue inside the SetSysClock() function.
+ *
+ * 4. The default value of HSE crystal is set to 8 MHz (or 25 MHz, depedning on
+ * the product used), refer to "HSE_VALUE" define in "stm32f10x.h" file.
+ * When HSE is used as system clock source, directly or through PLL, and you
+ * are using different crystal you have to adapt the HSE value to your own
+ * configuration.
+ *
+ ******************************************************************************
+ * @attention
+ *
+ * © COPYRIGHT 2012 STMicroelectronics
+ *
+ * Licensed under MCD-ST Liberty SW License Agreement V2, (the "License");
+ * You may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at:
+ *
+ * http://www.st.com/software_license_agreement_liberty_v2
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ *
+ ******************************************************************************
+ */
+
+/** @addtogroup CMSIS
+ * @{
+ */
+
+/** @addtogroup stm32f10x_system
+ * @{
+ */
+
+/** @addtogroup STM32F10x_System_Private_Includes
+ * @{
+ */
+
+#include "stm32f10x.h"
+
+/**
+ * @}
+ */
+
+/** @addtogroup STM32F10x_System_Private_TypesDefinitions
+ * @{
+ */
+
+/**
+ * @}
+ */
+
+/** @addtogroup STM32F10x_System_Private_Defines
+ * @{
+ */
+
+/*!< Uncomment the line corresponding to the desired System clock (SYSCLK)
+ frequency (after reset the HSI is used as SYSCLK source)
+
+ IMPORTANT NOTE:
+ ==============
+ 1. After each device reset the HSI is used as System clock source.
+
+ 2. Please make sure that the selected System clock doesn't exceed your device's
+ maximum frequency.
+
+ 3. If none of the define below is enabled, the HSI is used as System clock
+ source.
+
+ 4. The System clock configuration functions provided within this file assume that:
+ - For Low, Medium and High density Value line devices an external 8MHz
+ crystal is used to drive the System clock.
+ - For Low, Medium and High density devices an external 8MHz crystal is
+ used to drive the System clock.
+ - For Connectivity line devices an external 25MHz crystal is used to drive
+ the System clock.
+ If you are using different crystal you have to adapt those functions accordingly.
+ */
+
+#if defined (STM32F10X_LD_VL) || (defined STM32F10X_MD_VL) || (defined STM32F10X_HD_VL)
+/* #define SYSCLK_FREQ_HSE HSE_VALUE */
+ #define SYSCLK_FREQ_24MHz 24000000
+#else
+/* #define SYSCLK_FREQ_HSE HSE_VALUE */
+/* #define SYSCLK_FREQ_24MHz 24000000 */
+/* #define SYSCLK_FREQ_36MHz 36000000 */
+/* #define SYSCLK_FREQ_48MHz 48000000 */
+/* #define SYSCLK_FREQ_56MHz 56000000 */
+#define SYSCLK_FREQ_72MHz 72000000
+#endif
+
+/*!< Uncomment the following line if you need to use external SRAM mounted
+ on STM3210E-EVAL board (STM32 High density and XL-density devices) or on
+ STM32100E-EVAL board (STM32 High-density value line devices) as data memory */
+#if defined (STM32F10X_HD) || (defined STM32F10X_XL) || (defined STM32F10X_HD_VL)
+/* #define DATA_IN_ExtSRAM */
+#endif
+
+/*!< Uncomment the following line if you need to relocate your vector Table in
+ Internal SRAM. */
+/* #define VECT_TAB_SRAM */
+#define VECT_TAB_OFFSET 0x0 /*!< Vector Table base offset field.
+ This value must be a multiple of 0x200. */
+
+
+/**
+ * @}
+ */
+
+/** @addtogroup STM32F10x_System_Private_Macros
+ * @{
+ */
+
+/**
+ * @}
+ */
+
+/** @addtogroup STM32F10x_System_Private_Variables
+ * @{
+ */
+
+/*******************************************************************************
+* Clock Definitions
+*******************************************************************************/
+#ifdef SYSCLK_FREQ_HSE
+ uint32_t SystemCoreClock = SYSCLK_FREQ_HSE; /*!< System Clock Frequency (Core Clock) */
+#elif defined SYSCLK_FREQ_24MHz
+ uint32_t SystemCoreClock = SYSCLK_FREQ_24MHz; /*!< System Clock Frequency (Core Clock) */
+#elif defined SYSCLK_FREQ_36MHz
+ uint32_t SystemCoreClock = SYSCLK_FREQ_36MHz; /*!< System Clock Frequency (Core Clock) */
+#elif defined SYSCLK_FREQ_48MHz
+ uint32_t SystemCoreClock = SYSCLK_FREQ_48MHz; /*!< System Clock Frequency (Core Clock) */
+#elif defined SYSCLK_FREQ_56MHz
+ uint32_t SystemCoreClock = SYSCLK_FREQ_56MHz; /*!< System Clock Frequency (Core Clock) */
+#elif defined SYSCLK_FREQ_72MHz
+ uint32_t SystemCoreClock = SYSCLK_FREQ_72MHz; /*!< System Clock Frequency (Core Clock) */
+#else /*!< HSI Selected as System Clock source */
+ uint32_t SystemCoreClock = HSI_VALUE; /*!< System Clock Frequency (Core Clock) */
+#endif
+
+__I uint8_t AHBPrescTable[16] = {0, 0, 0, 0, 0, 0, 0, 0, 1, 2, 3, 4, 6, 7, 8, 9};
+/**
+ * @}
+ */
+
+/** @addtogroup STM32F10x_System_Private_FunctionPrototypes
+ * @{
+ */
+
+static void SetSysClock(void);
+
+#ifdef SYSCLK_FREQ_HSE
+ static void SetSysClockToHSE(void);
+#elif defined SYSCLK_FREQ_24MHz
+ static void SetSysClockTo24(void);
+#elif defined SYSCLK_FREQ_36MHz
+ static void SetSysClockTo36(void);
+#elif defined SYSCLK_FREQ_48MHz
+ static void SetSysClockTo48(void);
+#elif defined SYSCLK_FREQ_56MHz
+ static void SetSysClockTo56(void);
+#elif defined SYSCLK_FREQ_72MHz
+ static void SetSysClockTo72(void);
+#endif
+
+#ifdef DATA_IN_ExtSRAM
+ static void SystemInit_ExtMemCtl(void);
+#endif /* DATA_IN_ExtSRAM */
+
+/**
+ * @}
+ */
+
+/** @addtogroup STM32F10x_System_Private_Functions
+ * @{
+ */
+
+/**
+ * @brief Setup the microcontroller system
+ * Initialize the Embedded Flash Interface, the PLL and update the
+ * SystemCoreClock variable.
+ * @note This function should be used only after reset.
+ * @param None
+ * @retval None
+ */
+void SystemInit (void)
+{
+ /* Reset the RCC clock configuration to the default reset state(for debug purpose) */
+ /* Set HSION bit */
+ RCC->CR |= (uint32_t)0x00000001;
+
+ /* Reset SW, HPRE, PPRE1, PPRE2, ADCPRE and MCO bits */
+#ifndef STM32F10X_CL
+ RCC->CFGR &= (uint32_t)0xF8FF0000;
+#else
+ RCC->CFGR &= (uint32_t)0xF0FF0000;
+#endif /* STM32F10X_CL */
+
+ /* Reset HSEON, CSSON and PLLON bits */
+ RCC->CR &= (uint32_t)0xFEF6FFFF;
+
+ /* Reset HSEBYP bit */
+ RCC->CR &= (uint32_t)0xFFFBFFFF;
+
+ /* Reset PLLSRC, PLLXTPRE, PLLMUL and USBPRE/OTGFSPRE bits */
+ RCC->CFGR &= (uint32_t)0xFF80FFFF;
+
+#ifdef STM32F10X_CL
+ /* Reset PLL2ON and PLL3ON bits */
+ RCC->CR &= (uint32_t)0xEBFFFFFF;
+
+ /* Disable all interrupts and clear pending bits */
+ RCC->CIR = 0x00FF0000;
+
+ /* Reset CFGR2 register */
+ RCC->CFGR2 = 0x00000000;
+#elif defined (STM32F10X_LD_VL) || defined (STM32F10X_MD_VL) || (defined STM32F10X_HD_VL)
+ /* Disable all interrupts and clear pending bits */
+ RCC->CIR = 0x009F0000;
+
+ /* Reset CFGR2 register */
+ RCC->CFGR2 = 0x00000000;
+#else
+ /* Disable all interrupts and clear pending bits */
+ RCC->CIR = 0x009F0000;
+#endif /* STM32F10X_CL */
+
+#if defined (STM32F10X_HD) || (defined STM32F10X_XL) || (defined STM32F10X_HD_VL)
+ #ifdef DATA_IN_ExtSRAM
+ SystemInit_ExtMemCtl();
+ #endif /* DATA_IN_ExtSRAM */
+#endif
+
+ /* Configure the System clock frequency, HCLK, PCLK2 and PCLK1 prescalers */
+ /* Configure the Flash Latency cycles and enable prefetch buffer */
+ SetSysClock();
+
+#ifdef VECT_TAB_SRAM
+ SCB->VTOR = SRAM_BASE | VECT_TAB_OFFSET; /* Vector Table Relocation in Internal SRAM. */
+#else
+ SCB->VTOR = FLASH_BASE | VECT_TAB_OFFSET; /* Vector Table Relocation in Internal FLASH. */
+#endif
+}
+
+/**
+ * @brief Update SystemCoreClock variable according to Clock Register Values.
+ * The SystemCoreClock variable contains the core clock (HCLK), it can
+ * be used by the user application to setup the SysTick timer or configure
+ * other parameters.
+ *
+ * @note Each time the core clock (HCLK) changes, this function must be called
+ * to update SystemCoreClock variable value. Otherwise, any configuration
+ * based on this variable will be incorrect.
+ *
+ * @note - The system frequency computed by this function is not the real
+ * frequency in the chip. It is calculated based on the predefined
+ * constant and the selected clock source:
+ *
+ * - If SYSCLK source is HSI, SystemCoreClock will contain the HSI_VALUE(*)
+ *
+ * - If SYSCLK source is HSE, SystemCoreClock will contain the HSE_VALUE(**)
+ *
+ * - If SYSCLK source is PLL, SystemCoreClock will contain the HSE_VALUE(**)
+ * or HSI_VALUE(*) multiplied by the PLL factors.
+ *
+ * (*) HSI_VALUE is a constant defined in stm32f1xx.h file (default value
+ * 8 MHz) but the real value may vary depending on the variations
+ * in voltage and temperature.
+ *
+ * (**) HSE_VALUE is a constant defined in stm32f1xx.h file (default value
+ * 8 MHz or 25 MHz, depending on the product used), user has to ensure
+ * that HSE_VALUE is same as the real frequency of the crystal used.
+ * Otherwise, this function may have wrong result.
+ *
+ * - The result of this function could be not correct when using fractional
+ * value for HSE crystal.
+ * @param None
+ * @retval None
+ */
+void SystemCoreClockUpdate (void)
+{
+ uint32_t tmp = 0, pllmull = 0, pllsource = 0;
+
+#ifdef STM32F10X_CL
+ uint32_t prediv1source = 0, prediv1factor = 0, prediv2factor = 0, pll2mull = 0;
+#endif /* STM32F10X_CL */
+
+#if defined (STM32F10X_LD_VL) || defined (STM32F10X_MD_VL) || (defined STM32F10X_HD_VL)
+ uint32_t prediv1factor = 0;
+#endif /* STM32F10X_LD_VL or STM32F10X_MD_VL or STM32F10X_HD_VL */
+
+ /* Get SYSCLK source -------------------------------------------------------*/
+ tmp = RCC->CFGR & RCC_CFGR_SWS;
+
+ switch (tmp)
+ {
+ case 0x00: /* HSI used as system clock */
+ SystemCoreClock = HSI_VALUE;
+ break;
+ case 0x04: /* HSE used as system clock */
+ SystemCoreClock = HSE_VALUE;
+ break;
+ case 0x08: /* PLL used as system clock */
+
+ /* Get PLL clock source and multiplication factor ----------------------*/
+ pllmull = RCC->CFGR & RCC_CFGR_PLLMULL;
+ pllsource = RCC->CFGR & RCC_CFGR_PLLSRC;
+
+#ifndef STM32F10X_CL
+ pllmull = ( pllmull >> 18) + 2;
+
+ if (pllsource == 0x00)
+ {
+ /* HSI oscillator clock divided by 2 selected as PLL clock entry */
+ SystemCoreClock = (HSI_VALUE >> 1) * pllmull;
+ }
+ else
+ {
+ #if defined (STM32F10X_LD_VL) || defined (STM32F10X_MD_VL) || (defined STM32F10X_HD_VL)
+ prediv1factor = (RCC->CFGR2 & RCC_CFGR2_PREDIV1) + 1;
+ /* HSE oscillator clock selected as PREDIV1 clock entry */
+ SystemCoreClock = (HSE_VALUE / prediv1factor) * pllmull;
+ #else
+ /* HSE selected as PLL clock entry */
+ if ((RCC->CFGR & RCC_CFGR_PLLXTPRE) != (uint32_t)RESET)
+ {/* HSE oscillator clock divided by 2 */
+ SystemCoreClock = (HSE_VALUE >> 1) * pllmull;
+ }
+ else
+ {
+ SystemCoreClock = HSE_VALUE * pllmull;
+ }
+ #endif
+ }
+#else
+ pllmull = pllmull >> 18;
+
+ if (pllmull != 0x0D)
+ {
+ pllmull += 2;
+ }
+ else
+ { /* PLL multiplication factor = PLL input clock * 6.5 */
+ pllmull = 13 / 2;
+ }
+
+ if (pllsource == 0x00)
+ {
+ /* HSI oscillator clock divided by 2 selected as PLL clock entry */
+ SystemCoreClock = (HSI_VALUE >> 1) * pllmull;
+ }
+ else
+ {/* PREDIV1 selected as PLL clock entry */
+
+ /* Get PREDIV1 clock source and division factor */
+ prediv1source = RCC->CFGR2 & RCC_CFGR2_PREDIV1SRC;
+ prediv1factor = (RCC->CFGR2 & RCC_CFGR2_PREDIV1) + 1;
+
+ if (prediv1source == 0)
+ {
+ /* HSE oscillator clock selected as PREDIV1 clock entry */
+ SystemCoreClock = (HSE_VALUE / prediv1factor) * pllmull;
+ }
+ else
+ {/* PLL2 clock selected as PREDIV1 clock entry */
+
+ /* Get PREDIV2 division factor and PLL2 multiplication factor */
+ prediv2factor = ((RCC->CFGR2 & RCC_CFGR2_PREDIV2) >> 4) + 1;
+ pll2mull = ((RCC->CFGR2 & RCC_CFGR2_PLL2MUL) >> 8 ) + 2;
+ SystemCoreClock = (((HSE_VALUE / prediv2factor) * pll2mull) / prediv1factor) * pllmull;
+ }
+ }
+#endif /* STM32F10X_CL */
+ break;
+
+ default:
+ SystemCoreClock = HSI_VALUE;
+ break;
+ }
+
+ /* Compute HCLK clock frequency ----------------*/
+ /* Get HCLK prescaler */
+ tmp = AHBPrescTable[((RCC->CFGR & RCC_CFGR_HPRE) >> 4)];
+ /* HCLK clock frequency */
+ SystemCoreClock >>= tmp;
+}
+
+/**
+ * @brief Configures the System clock frequency, HCLK, PCLK2 and PCLK1 prescalers.
+ * @param None
+ * @retval None
+ */
+static void SetSysClock(void)
+{
+#ifdef SYSCLK_FREQ_HSE
+ SetSysClockToHSE();
+#elif defined SYSCLK_FREQ_24MHz
+ SetSysClockTo24();
+#elif defined SYSCLK_FREQ_36MHz
+ SetSysClockTo36();
+#elif defined SYSCLK_FREQ_48MHz
+ SetSysClockTo48();
+#elif defined SYSCLK_FREQ_56MHz
+ SetSysClockTo56();
+#elif defined SYSCLK_FREQ_72MHz
+ SetSysClockTo72();
+#endif
+
+ /* If none of the define above is enabled, the HSI is used as System clock
+ source (default after reset) */
+}
+
+/**
+ * @brief Setup the external memory controller. Called in startup_stm32f10x.s
+ * before jump to __main
+ * @param None
+ * @retval None
+ */
+#ifdef DATA_IN_ExtSRAM
+/**
+ * @brief Setup the external memory controller.
+ * Called in startup_stm32f10x_xx.s/.c before jump to main.
+ * This function configures the external SRAM mounted on STM3210E-EVAL
+ * board (STM32 High density devices). This SRAM will be used as program
+ * data memory (including heap and stack).
+ * @param None
+ * @retval None
+ */
+void SystemInit_ExtMemCtl(void)
+{
+/*!< FSMC Bank1 NOR/SRAM3 is used for the STM3210E-EVAL, if another Bank is
+ required, then adjust the Register Addresses */
+
+ /* Enable FSMC clock */
+ RCC->AHBENR = 0x00000114;
+
+ /* Enable GPIOD, GPIOE, GPIOF and GPIOG clocks */
+ RCC->APB2ENR = 0x000001E0;
+
+/* --------------- SRAM Data lines, NOE and NWE configuration ---------------*/
+/*---------------- SRAM Address lines configuration -------------------------*/
+/*---------------- NOE and NWE configuration --------------------------------*/
+/*---------------- NE3 configuration ----------------------------------------*/
+/*---------------- NBL0, NBL1 configuration ---------------------------------*/
+
+ GPIOD->CRL = 0x44BB44BB;
+ GPIOD->CRH = 0xBBBBBBBB;
+
+ GPIOE->CRL = 0xB44444BB;
+ GPIOE->CRH = 0xBBBBBBBB;
+
+ GPIOF->CRL = 0x44BBBBBB;
+ GPIOF->CRH = 0xBBBB4444;
+
+ GPIOG->CRL = 0x44BBBBBB;
+ GPIOG->CRH = 0x44444B44;
+
+/*---------------- FSMC Configuration ---------------------------------------*/
+/*---------------- Enable FSMC Bank1_SRAM Bank ------------------------------*/
+
+ FSMC_Bank1->BTCR[4] = 0x00001011;
+ FSMC_Bank1->BTCR[5] = 0x00000200;
+}
+#endif /* DATA_IN_ExtSRAM */
+
+#ifdef SYSCLK_FREQ_HSE
+/**
+ * @brief Selects HSE as System clock source and configure HCLK, PCLK2
+ * and PCLK1 prescalers.
+ * @note This function should be used only after reset.
+ * @param None
+ * @retval None
+ */
+static void SetSysClockToHSE(void)
+{
+ __IO uint32_t StartUpCounter = 0, HSEStatus = 0;
+
+ /* SYSCLK, HCLK, PCLK2 and PCLK1 configuration ---------------------------*/
+ /* Enable HSE */
+ RCC->CR |= ((uint32_t)RCC_CR_HSEON);
+
+ /* Wait till HSE is ready and if Time out is reached exit */
+ do
+ {
+ HSEStatus = RCC->CR & RCC_CR_HSERDY;
+ StartUpCounter++;
+ } while((HSEStatus == 0) && (StartUpCounter != HSE_STARTUP_TIMEOUT));
+
+ if ((RCC->CR & RCC_CR_HSERDY) != RESET)
+ {
+ HSEStatus = (uint32_t)0x01;
+ }
+ else
+ {
+ HSEStatus = (uint32_t)0x00;
+ }
+
+ if (HSEStatus == (uint32_t)0x01)
+ {
+
+#if !defined STM32F10X_LD_VL && !defined STM32F10X_MD_VL && !defined STM32F10X_HD_VL
+ /* Enable Prefetch Buffer */
+ FLASH->ACR |= FLASH_ACR_PRFTBE;
+
+ /* Flash 0 wait state */
+ FLASH->ACR &= (uint32_t)((uint32_t)~FLASH_ACR_LATENCY);
+
+#ifndef STM32F10X_CL
+ FLASH->ACR |= (uint32_t)FLASH_ACR_LATENCY_0;
+#else
+ if (HSE_VALUE <= 24000000)
+ {
+ FLASH->ACR |= (uint32_t)FLASH_ACR_LATENCY_0;
+ }
+ else
+ {
+ FLASH->ACR |= (uint32_t)FLASH_ACR_LATENCY_1;
+ }
+#endif /* STM32F10X_CL */
+#endif
+
+ /* HCLK = SYSCLK */
+ RCC->CFGR |= (uint32_t)RCC_CFGR_HPRE_DIV1;
+
+ /* PCLK2 = HCLK */
+ RCC->CFGR |= (uint32_t)RCC_CFGR_PPRE2_DIV1;
+
+ /* PCLK1 = HCLK */
+ RCC->CFGR |= (uint32_t)RCC_CFGR_PPRE1_DIV1;
+
+ /* Select HSE as system clock source */
+ RCC->CFGR &= (uint32_t)((uint32_t)~(RCC_CFGR_SW));
+ RCC->CFGR |= (uint32_t)RCC_CFGR_SW_HSE;
+
+ /* Wait till HSE is used as system clock source */
+ while ((RCC->CFGR & (uint32_t)RCC_CFGR_SWS) != (uint32_t)0x04)
+ {
+ }
+ }
+ else
+ { /* If HSE fails to start-up, the application will have wrong clock
+ configuration. User can add here some code to deal with this error */
+ }
+}
+#elif defined SYSCLK_FREQ_24MHz
+/**
+ * @brief Sets System clock frequency to 24MHz and configure HCLK, PCLK2
+ * and PCLK1 prescalers.
+ * @note This function should be used only after reset.
+ * @param None
+ * @retval None
+ */
+static void SetSysClockTo24(void)
+{
+ __IO uint32_t StartUpCounter = 0, HSEStatus = 0;
+
+ /* SYSCLK, HCLK, PCLK2 and PCLK1 configuration ---------------------------*/
+ /* Enable HSE */
+ RCC->CR |= ((uint32_t)RCC_CR_HSEON);
+
+ /* Wait till HSE is ready and if Time out is reached exit */
+ do
+ {
+ HSEStatus = RCC->CR & RCC_CR_HSERDY;
+ StartUpCounter++;
+ } while((HSEStatus == 0) && (StartUpCounter != HSE_STARTUP_TIMEOUT));
+
+ if ((RCC->CR & RCC_CR_HSERDY) != RESET)
+ {
+ HSEStatus = (uint32_t)0x01;
+ }
+ else
+ {
+ HSEStatus = (uint32_t)0x00;
+ }
+
+ if (HSEStatus == (uint32_t)0x01)
+ {
+#if !defined STM32F10X_LD_VL && !defined STM32F10X_MD_VL && !defined STM32F10X_HD_VL
+ /* Enable Prefetch Buffer */
+ FLASH->ACR |= FLASH_ACR_PRFTBE;
+
+ /* Flash 0 wait state */
+ FLASH->ACR &= (uint32_t)((uint32_t)~FLASH_ACR_LATENCY);
+ FLASH->ACR |= (uint32_t)FLASH_ACR_LATENCY_0;
+#endif
+
+ /* HCLK = SYSCLK */
+ RCC->CFGR |= (uint32_t)RCC_CFGR_HPRE_DIV1;
+
+ /* PCLK2 = HCLK */
+ RCC->CFGR |= (uint32_t)RCC_CFGR_PPRE2_DIV1;
+
+ /* PCLK1 = HCLK */
+ RCC->CFGR |= (uint32_t)RCC_CFGR_PPRE1_DIV1;
+
+#ifdef STM32F10X_CL
+ /* Configure PLLs ------------------------------------------------------*/
+ /* PLL configuration: PLLCLK = PREDIV1 * 6 = 24 MHz */
+ RCC->CFGR &= (uint32_t)~(RCC_CFGR_PLLXTPRE | RCC_CFGR_PLLSRC | RCC_CFGR_PLLMULL);
+ RCC->CFGR |= (uint32_t)(RCC_CFGR_PLLXTPRE_PREDIV1 | RCC_CFGR_PLLSRC_PREDIV1 |
+ RCC_CFGR_PLLMULL6);
+
+ /* PLL2 configuration: PLL2CLK = (HSE / 5) * 8 = 40 MHz */
+ /* PREDIV1 configuration: PREDIV1CLK = PLL2 / 10 = 4 MHz */
+ RCC->CFGR2 &= (uint32_t)~(RCC_CFGR2_PREDIV2 | RCC_CFGR2_PLL2MUL |
+ RCC_CFGR2_PREDIV1 | RCC_CFGR2_PREDIV1SRC);
+ RCC->CFGR2 |= (uint32_t)(RCC_CFGR2_PREDIV2_DIV5 | RCC_CFGR2_PLL2MUL8 |
+ RCC_CFGR2_PREDIV1SRC_PLL2 | RCC_CFGR2_PREDIV1_DIV10);
+
+ /* Enable PLL2 */
+ RCC->CR |= RCC_CR_PLL2ON;
+ /* Wait till PLL2 is ready */
+ while((RCC->CR & RCC_CR_PLL2RDY) == 0)
+ {
+ }
+#elif defined (STM32F10X_LD_VL) || defined (STM32F10X_MD_VL) || defined (STM32F10X_HD_VL)
+ /* PLL configuration: = (HSE / 2) * 6 = 24 MHz */
+ RCC->CFGR &= (uint32_t)((uint32_t)~(RCC_CFGR_PLLSRC | RCC_CFGR_PLLXTPRE | RCC_CFGR_PLLMULL));
+ RCC->CFGR |= (uint32_t)(RCC_CFGR_PLLSRC_PREDIV1 | RCC_CFGR_PLLXTPRE_PREDIV1_Div2 | RCC_CFGR_PLLMULL6);
+#else
+ /* PLL configuration: = (HSE / 2) * 6 = 24 MHz */
+ RCC->CFGR &= (uint32_t)((uint32_t)~(RCC_CFGR_PLLSRC | RCC_CFGR_PLLXTPRE | RCC_CFGR_PLLMULL));
+ RCC->CFGR |= (uint32_t)(RCC_CFGR_PLLSRC_HSE | RCC_CFGR_PLLXTPRE_HSE_Div2 | RCC_CFGR_PLLMULL6);
+#endif /* STM32F10X_CL */
+
+ /* Enable PLL */
+ RCC->CR |= RCC_CR_PLLON;
+
+ /* Wait till PLL is ready */
+ while((RCC->CR & RCC_CR_PLLRDY) == 0)
+ {
+ }
+
+ /* Select PLL as system clock source */
+ RCC->CFGR &= (uint32_t)((uint32_t)~(RCC_CFGR_SW));
+ RCC->CFGR |= (uint32_t)RCC_CFGR_SW_PLL;
+
+ /* Wait till PLL is used as system clock source */
+ while ((RCC->CFGR & (uint32_t)RCC_CFGR_SWS) != (uint32_t)0x08)
+ {
+ }
+ }
+ else
+ { /* If HSE fails to start-up, the application will have wrong clock
+ configuration. User can add here some code to deal with this error */
+ }
+}
+#elif defined SYSCLK_FREQ_36MHz
+/**
+ * @brief Sets System clock frequency to 36MHz and configure HCLK, PCLK2
+ * and PCLK1 prescalers.
+ * @note This function should be used only after reset.
+ * @param None
+ * @retval None
+ */
+static void SetSysClockTo36(void)
+{
+ __IO uint32_t StartUpCounter = 0, HSEStatus = 0;
+
+ /* SYSCLK, HCLK, PCLK2 and PCLK1 configuration ---------------------------*/
+ /* Enable HSE */
+ RCC->CR |= ((uint32_t)RCC_CR_HSEON);
+
+ /* Wait till HSE is ready and if Time out is reached exit */
+ do
+ {
+ HSEStatus = RCC->CR & RCC_CR_HSERDY;
+ StartUpCounter++;
+ } while((HSEStatus == 0) && (StartUpCounter != HSE_STARTUP_TIMEOUT));
+
+ if ((RCC->CR & RCC_CR_HSERDY) != RESET)
+ {
+ HSEStatus = (uint32_t)0x01;
+ }
+ else
+ {
+ HSEStatus = (uint32_t)0x00;
+ }
+
+ if (HSEStatus == (uint32_t)0x01)
+ {
+ /* Enable Prefetch Buffer */
+ FLASH->ACR |= FLASH_ACR_PRFTBE;
+
+ /* Flash 1 wait state */
+ FLASH->ACR &= (uint32_t)((uint32_t)~FLASH_ACR_LATENCY);
+ FLASH->ACR |= (uint32_t)FLASH_ACR_LATENCY_1;
+
+ /* HCLK = SYSCLK */
+ RCC->CFGR |= (uint32_t)RCC_CFGR_HPRE_DIV1;
+
+ /* PCLK2 = HCLK */
+ RCC->CFGR |= (uint32_t)RCC_CFGR_PPRE2_DIV1;
+
+ /* PCLK1 = HCLK */
+ RCC->CFGR |= (uint32_t)RCC_CFGR_PPRE1_DIV1;
+
+#ifdef STM32F10X_CL
+ /* Configure PLLs ------------------------------------------------------*/
+
+ /* PLL configuration: PLLCLK = PREDIV1 * 9 = 36 MHz */
+ RCC->CFGR &= (uint32_t)~(RCC_CFGR_PLLXTPRE | RCC_CFGR_PLLSRC | RCC_CFGR_PLLMULL);
+ RCC->CFGR |= (uint32_t)(RCC_CFGR_PLLXTPRE_PREDIV1 | RCC_CFGR_PLLSRC_PREDIV1 |
+ RCC_CFGR_PLLMULL9);
+
+ /*!< PLL2 configuration: PLL2CLK = (HSE / 5) * 8 = 40 MHz */
+ /* PREDIV1 configuration: PREDIV1CLK = PLL2 / 10 = 4 MHz */
+
+ RCC->CFGR2 &= (uint32_t)~(RCC_CFGR2_PREDIV2 | RCC_CFGR2_PLL2MUL |
+ RCC_CFGR2_PREDIV1 | RCC_CFGR2_PREDIV1SRC);
+ RCC->CFGR2 |= (uint32_t)(RCC_CFGR2_PREDIV2_DIV5 | RCC_CFGR2_PLL2MUL8 |
+ RCC_CFGR2_PREDIV1SRC_PLL2 | RCC_CFGR2_PREDIV1_DIV10);
+
+ /* Enable PLL2 */
+ RCC->CR |= RCC_CR_PLL2ON;
+ /* Wait till PLL2 is ready */
+ while((RCC->CR & RCC_CR_PLL2RDY) == 0)
+ {
+ }
+
+#else
+ /* PLL configuration: PLLCLK = (HSE / 2) * 9 = 36 MHz */
+ RCC->CFGR &= (uint32_t)((uint32_t)~(RCC_CFGR_PLLSRC | RCC_CFGR_PLLXTPRE | RCC_CFGR_PLLMULL));
+ RCC->CFGR |= (uint32_t)(RCC_CFGR_PLLSRC_HSE | RCC_CFGR_PLLXTPRE_HSE_Div2 | RCC_CFGR_PLLMULL9);
+#endif /* STM32F10X_CL */
+
+ /* Enable PLL */
+ RCC->CR |= RCC_CR_PLLON;
+
+ /* Wait till PLL is ready */
+ while((RCC->CR & RCC_CR_PLLRDY) == 0)
+ {
+ }
+
+ /* Select PLL as system clock source */
+ RCC->CFGR &= (uint32_t)((uint32_t)~(RCC_CFGR_SW));
+ RCC->CFGR |= (uint32_t)RCC_CFGR_SW_PLL;
+
+ /* Wait till PLL is used as system clock source */
+ while ((RCC->CFGR & (uint32_t)RCC_CFGR_SWS) != (uint32_t)0x08)
+ {
+ }
+ }
+ else
+ { /* If HSE fails to start-up, the application will have wrong clock
+ configuration. User can add here some code to deal with this error */
+ }
+}
+#elif defined SYSCLK_FREQ_48MHz
+/**
+ * @brief Sets System clock frequency to 48MHz and configure HCLK, PCLK2
+ * and PCLK1 prescalers.
+ * @note This function should be used only after reset.
+ * @param None
+ * @retval None
+ */
+static void SetSysClockTo48(void)
+{
+ __IO uint32_t StartUpCounter = 0, HSEStatus = 0;
+
+ /* SYSCLK, HCLK, PCLK2 and PCLK1 configuration ---------------------------*/
+ /* Enable HSE */
+ RCC->CR |= ((uint32_t)RCC_CR_HSEON);
+
+ /* Wait till HSE is ready and if Time out is reached exit */
+ do
+ {
+ HSEStatus = RCC->CR & RCC_CR_HSERDY;
+ StartUpCounter++;
+ } while((HSEStatus == 0) && (StartUpCounter != HSE_STARTUP_TIMEOUT));
+
+ if ((RCC->CR & RCC_CR_HSERDY) != RESET)
+ {
+ HSEStatus = (uint32_t)0x01;
+ }
+ else
+ {
+ HSEStatus = (uint32_t)0x00;
+ }
+
+ if (HSEStatus == (uint32_t)0x01)
+ {
+ /* Enable Prefetch Buffer */
+ FLASH->ACR |= FLASH_ACR_PRFTBE;
+
+ /* Flash 1 wait state */
+ FLASH->ACR &= (uint32_t)((uint32_t)~FLASH_ACR_LATENCY);
+ FLASH->ACR |= (uint32_t)FLASH_ACR_LATENCY_1;
+
+ /* HCLK = SYSCLK */
+ RCC->CFGR |= (uint32_t)RCC_CFGR_HPRE_DIV1;
+
+ /* PCLK2 = HCLK */
+ RCC->CFGR |= (uint32_t)RCC_CFGR_PPRE2_DIV1;
+
+ /* PCLK1 = HCLK */
+ RCC->CFGR |= (uint32_t)RCC_CFGR_PPRE1_DIV2;
+
+#ifdef STM32F10X_CL
+ /* Configure PLLs ------------------------------------------------------*/
+ /* PLL2 configuration: PLL2CLK = (HSE / 5) * 8 = 40 MHz */
+ /* PREDIV1 configuration: PREDIV1CLK = PLL2 / 5 = 8 MHz */
+
+ RCC->CFGR2 &= (uint32_t)~(RCC_CFGR2_PREDIV2 | RCC_CFGR2_PLL2MUL |
+ RCC_CFGR2_PREDIV1 | RCC_CFGR2_PREDIV1SRC);
+ RCC->CFGR2 |= (uint32_t)(RCC_CFGR2_PREDIV2_DIV5 | RCC_CFGR2_PLL2MUL8 |
+ RCC_CFGR2_PREDIV1SRC_PLL2 | RCC_CFGR2_PREDIV1_DIV5);
+
+ /* Enable PLL2 */
+ RCC->CR |= RCC_CR_PLL2ON;
+ /* Wait till PLL2 is ready */
+ while((RCC->CR & RCC_CR_PLL2RDY) == 0)
+ {
+ }
+
+
+ /* PLL configuration: PLLCLK = PREDIV1 * 6 = 48 MHz */
+ RCC->CFGR &= (uint32_t)~(RCC_CFGR_PLLXTPRE | RCC_CFGR_PLLSRC | RCC_CFGR_PLLMULL);
+ RCC->CFGR |= (uint32_t)(RCC_CFGR_PLLXTPRE_PREDIV1 | RCC_CFGR_PLLSRC_PREDIV1 |
+ RCC_CFGR_PLLMULL6);
+#else
+ /* PLL configuration: PLLCLK = HSE * 6 = 48 MHz */
+ RCC->CFGR &= (uint32_t)((uint32_t)~(RCC_CFGR_PLLSRC | RCC_CFGR_PLLXTPRE | RCC_CFGR_PLLMULL));
+ RCC->CFGR |= (uint32_t)(RCC_CFGR_PLLSRC_HSE | RCC_CFGR_PLLMULL6);
+#endif /* STM32F10X_CL */
+
+ /* Enable PLL */
+ RCC->CR |= RCC_CR_PLLON;
+
+ /* Wait till PLL is ready */
+ while((RCC->CR & RCC_CR_PLLRDY) == 0)
+ {
+ }
+
+ /* Select PLL as system clock source */
+ RCC->CFGR &= (uint32_t)((uint32_t)~(RCC_CFGR_SW));
+ RCC->CFGR |= (uint32_t)RCC_CFGR_SW_PLL;
+
+ /* Wait till PLL is used as system clock source */
+ while ((RCC->CFGR & (uint32_t)RCC_CFGR_SWS) != (uint32_t)0x08)
+ {
+ }
+ }
+ else
+ { /* If HSE fails to start-up, the application will have wrong clock
+ configuration. User can add here some code to deal with this error */
+ }
+}
+
+#elif defined SYSCLK_FREQ_56MHz
+/**
+ * @brief Sets System clock frequency to 56MHz and configure HCLK, PCLK2
+ * and PCLK1 prescalers.
+ * @note This function should be used only after reset.
+ * @param None
+ * @retval None
+ */
+static void SetSysClockTo56(void)
+{
+ __IO uint32_t StartUpCounter = 0, HSEStatus = 0;
+
+ /* SYSCLK, HCLK, PCLK2 and PCLK1 configuration ---------------------------*/
+ /* Enable HSE */
+ RCC->CR |= ((uint32_t)RCC_CR_HSEON);
+
+ /* Wait till HSE is ready and if Time out is reached exit */
+ do
+ {
+ HSEStatus = RCC->CR & RCC_CR_HSERDY;
+ StartUpCounter++;
+ } while((HSEStatus == 0) && (StartUpCounter != HSE_STARTUP_TIMEOUT));
+
+ if ((RCC->CR & RCC_CR_HSERDY) != RESET)
+ {
+ HSEStatus = (uint32_t)0x01;
+ }
+ else
+ {
+ HSEStatus = (uint32_t)0x00;
+ }
+
+ if (HSEStatus == (uint32_t)0x01)
+ {
+ /* Enable Prefetch Buffer */
+ FLASH->ACR |= FLASH_ACR_PRFTBE;
+
+ /* Flash 2 wait state */
+ FLASH->ACR &= (uint32_t)((uint32_t)~FLASH_ACR_LATENCY);
+ FLASH->ACR |= (uint32_t)FLASH_ACR_LATENCY_2;
+
+ /* HCLK = SYSCLK */
+ RCC->CFGR |= (uint32_t)RCC_CFGR_HPRE_DIV1;
+
+ /* PCLK2 = HCLK */
+ RCC->CFGR |= (uint32_t)RCC_CFGR_PPRE2_DIV1;
+
+ /* PCLK1 = HCLK */
+ RCC->CFGR |= (uint32_t)RCC_CFGR_PPRE1_DIV2;
+
+#ifdef STM32F10X_CL
+ /* Configure PLLs ------------------------------------------------------*/
+ /* PLL2 configuration: PLL2CLK = (HSE / 5) * 8 = 40 MHz */
+ /* PREDIV1 configuration: PREDIV1CLK = PLL2 / 5 = 8 MHz */
+
+ RCC->CFGR2 &= (uint32_t)~(RCC_CFGR2_PREDIV2 | RCC_CFGR2_PLL2MUL |
+ RCC_CFGR2_PREDIV1 | RCC_CFGR2_PREDIV1SRC);
+ RCC->CFGR2 |= (uint32_t)(RCC_CFGR2_PREDIV2_DIV5 | RCC_CFGR2_PLL2MUL8 |
+ RCC_CFGR2_PREDIV1SRC_PLL2 | RCC_CFGR2_PREDIV1_DIV5);
+
+ /* Enable PLL2 */
+ RCC->CR |= RCC_CR_PLL2ON;
+ /* Wait till PLL2 is ready */
+ while((RCC->CR & RCC_CR_PLL2RDY) == 0)
+ {
+ }
+
+
+ /* PLL configuration: PLLCLK = PREDIV1 * 7 = 56 MHz */
+ RCC->CFGR &= (uint32_t)~(RCC_CFGR_PLLXTPRE | RCC_CFGR_PLLSRC | RCC_CFGR_PLLMULL);
+ RCC->CFGR |= (uint32_t)(RCC_CFGR_PLLXTPRE_PREDIV1 | RCC_CFGR_PLLSRC_PREDIV1 |
+ RCC_CFGR_PLLMULL7);
+#else
+ /* PLL configuration: PLLCLK = HSE * 7 = 56 MHz */
+ RCC->CFGR &= (uint32_t)((uint32_t)~(RCC_CFGR_PLLSRC | RCC_CFGR_PLLXTPRE | RCC_CFGR_PLLMULL));
+ RCC->CFGR |= (uint32_t)(RCC_CFGR_PLLSRC_HSE | RCC_CFGR_PLLMULL7);
+
+#endif /* STM32F10X_CL */
+
+ /* Enable PLL */
+ RCC->CR |= RCC_CR_PLLON;
+
+ /* Wait till PLL is ready */
+ while((RCC->CR & RCC_CR_PLLRDY) == 0)
+ {
+ }
+
+ /* Select PLL as system clock source */
+ RCC->CFGR &= (uint32_t)((uint32_t)~(RCC_CFGR_SW));
+ RCC->CFGR |= (uint32_t)RCC_CFGR_SW_PLL;
+
+ /* Wait till PLL is used as system clock source */
+ while ((RCC->CFGR & (uint32_t)RCC_CFGR_SWS) != (uint32_t)0x08)
+ {
+ }
+ }
+ else
+ { /* If HSE fails to start-up, the application will have wrong clock
+ configuration. User can add here some code to deal with this error */
+ }
+}
+
+#elif defined SYSCLK_FREQ_72MHz
+/**
+ * @brief Sets System clock frequency to 72MHz and configure HCLK, PCLK2
+ * and PCLK1 prescalers.
+ * @note This function should be used only after reset.
+ * @param None
+ * @retval None
+ */
+static void SetSysClockTo72(void)
+{
+ __IO uint32_t StartUpCounter = 0, HSEStatus = 0;
+
+ /* SYSCLK, HCLK, PCLK2 and PCLK1 configuration ---------------------------*/
+ /* Enable HSE */
+ RCC->CR |= ((uint32_t)RCC_CR_HSEON);
+
+ /* Wait till HSE is ready and if Time out is reached exit */
+ do
+ {
+ HSEStatus = RCC->CR & RCC_CR_HSERDY;
+ StartUpCounter++;
+ } while((HSEStatus == 0) && (StartUpCounter != HSE_STARTUP_TIMEOUT));
+
+ if ((RCC->CR & RCC_CR_HSERDY) != RESET)
+ {
+ HSEStatus = (uint32_t)0x01;
+ }
+ else
+ {
+ HSEStatus = (uint32_t)0x00;
+ }
+
+ if (HSEStatus == (uint32_t)0x01)
+ {
+ /* Enable Prefetch Buffer */
+ FLASH->ACR |= FLASH_ACR_PRFTBE;
+
+ /* Flash 2 wait state */
+ FLASH->ACR &= (uint32_t)((uint32_t)~FLASH_ACR_LATENCY);
+ FLASH->ACR |= (uint32_t)FLASH_ACR_LATENCY_2;
+
+
+ /* HCLK = SYSCLK */
+ RCC->CFGR |= (uint32_t)RCC_CFGR_HPRE_DIV1;
+
+ /* PCLK2 = HCLK */
+ RCC->CFGR |= (uint32_t)RCC_CFGR_PPRE2_DIV1;
+
+ /* PCLK1 = HCLK */
+ RCC->CFGR |= (uint32_t)RCC_CFGR_PPRE1_DIV2;
+
+#ifdef STM32F10X_CL
+ /* Configure PLLs ------------------------------------------------------*/
+ /* PLL2 configuration: PLL2CLK = (HSE / 5) * 8 = 40 MHz */
+ /* PREDIV1 configuration: PREDIV1CLK = PLL2 / 5 = 8 MHz */
+
+ RCC->CFGR2 &= (uint32_t)~(RCC_CFGR2_PREDIV2 | RCC_CFGR2_PLL2MUL |
+ RCC_CFGR2_PREDIV1 | RCC_CFGR2_PREDIV1SRC);
+ RCC->CFGR2 |= (uint32_t)(RCC_CFGR2_PREDIV2_DIV5 | RCC_CFGR2_PLL2MUL8 |
+ RCC_CFGR2_PREDIV1SRC_PLL2 | RCC_CFGR2_PREDIV1_DIV5);
+
+ /* Enable PLL2 */
+ RCC->CR |= RCC_CR_PLL2ON;
+ /* Wait till PLL2 is ready */
+ while((RCC->CR & RCC_CR_PLL2RDY) == 0)
+ {
+ }
+
+
+ /* PLL configuration: PLLCLK = PREDIV1 * 9 = 72 MHz */
+ RCC->CFGR &= (uint32_t)~(RCC_CFGR_PLLXTPRE | RCC_CFGR_PLLSRC | RCC_CFGR_PLLMULL);
+ RCC->CFGR |= (uint32_t)(RCC_CFGR_PLLXTPRE_PREDIV1 | RCC_CFGR_PLLSRC_PREDIV1 |
+ RCC_CFGR_PLLMULL9);
+#else
+ /* PLL configuration: PLLCLK = HSE * 9 = 72 MHz */
+ RCC->CFGR &= (uint32_t)((uint32_t)~(RCC_CFGR_PLLSRC | RCC_CFGR_PLLXTPRE |
+ RCC_CFGR_PLLMULL));
+ RCC->CFGR |= (uint32_t)(RCC_CFGR_PLLSRC_HSE | RCC_CFGR_PLLMULL9);
+#endif /* STM32F10X_CL */
+
+ /* Enable PLL */
+ RCC->CR |= RCC_CR_PLLON;
+
+ /* Wait till PLL is ready */
+ while((RCC->CR & RCC_CR_PLLRDY) == 0)
+ {
+ }
+
+ /* Select PLL as system clock source */
+ RCC->CFGR &= (uint32_t)((uint32_t)~(RCC_CFGR_SW));
+ RCC->CFGR |= (uint32_t)RCC_CFGR_SW_PLL;
+
+ /* Wait till PLL is used as system clock source */
+ while ((RCC->CFGR & (uint32_t)RCC_CFGR_SWS) != (uint32_t)0x08)
+ {
+ }
+ }
+ else
+ { /* If HSE fails to start-up, the application will have wrong clock
+ configuration. User can add here some code to deal with this error */
+ }
+}
+#endif
+
+/**
+ * @}
+ */
+
+/**
+ * @}
+ */
+
+/**
+ * @}
+ */
+/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
diff --git a/Libraries/CMSIS/Device/ST/STM32F30x/Include/stm32f30x.h b/Libraries/CMSIS/Device/ST/STM32F30x/Include/stm32f30x.h
new file mode 100644
index 0000000..c18f853
--- /dev/null
+++ b/Libraries/CMSIS/Device/ST/STM32F30x/Include/stm32f30x.h
@@ -0,0 +1,6205 @@
+/**
+ ******************************************************************************
+ * @file stm32f30x.h
+ * @author MCD Application Team
+ * @version V1.0.0
+ * @date 04-September-2012
+ * @brief CMSIS Cortex-M4 Device Peripheral Access Layer Header File.
+ * This file contains all the peripheral registers definitions, bits
+ * definitions and memory mapping for STM32F30x devices.
+ *
+ * The file is the unique include file that the application programmer
+ * is using in the C source code, usually in main.c. This file contains:
+ * - Configuration section that allows to select:
+ * - The device used in the target application
+ * - To use or not the peripherals drivers in application code(i.e.
+ * code will be based on direct access to peripherals registers
+ * rather than drivers API), this option is controlled by
+ * "#define USE_STDPERIPH_DRIVER"
+ * - To change few application-specific parameters such as the HSE
+ * crystal frequency
+ * - Data structures and the address mapping for all peripherals
+ * - Peripheral registers declarations and bits definition
+ * - Macros to access peripheral registers hardware
+ *
+ ******************************************************************************
+ * @attention
+ *
+ * © COPYRIGHT 2012 STMicroelectronics
+ *
+ * Licensed under MCD-ST Liberty SW License Agreement V2, (the "License");
+ * You may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at:
+ *
+ * http://www.st.com/software_license_agreement_liberty_v2
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ *
+ ******************************************************************************
+ */
+
+/** @addtogroup CMSIS
+ * @{
+ */
+
+/** @addtogroup stm32f30x
+ * @{
+ */
+
+#ifndef __STM32F30x_H
+#define __STM32F30x_H
+
+#ifdef __cplusplus
+ extern "C" {
+#endif /* __cplusplus */
+
+/** @addtogroup Library_configuration_section
+ * @{
+ */
+
+/* Uncomment the line below according to the target STM32 device used in your
+ application
+ */
+
+#if !defined (STM32F30X)
+ #define STM32F30X
+#endif
+
+/* Tip: To avoid modifying this file each time you need to switch between these
+ devices, you can define the device in your toolchain compiler preprocessor.
+ */
+
+#if !defined (STM32F30X)
+ #error "Please select first the target STM32F30X device used in your application (in stm32f30x.h file)"
+#endif
+
+#if !defined (USE_STDPERIPH_DRIVER)
+/**
+ * @brief Comment the line below if you will not use the peripherals drivers.
+ In this case, these drivers will not be included and the application code will
+ be based on direct access to peripherals registers
+ */
+ /*#define USE_STDPERIPH_DRIVER*/
+#endif /* USE_STDPERIPH_DRIVER */
+
+/**
+ * @brief In the following line adjust the value of External High Speed oscillator (HSE)
+ used in your application
+
+ Tip: To avoid modifying this file each time you need to use different HSE, you
+ can define the HSE value in your toolchain compiler preprocessor.
+ */
+#if !defined (HSE_VALUE)
+ #define HSE_VALUE ((uint32_t)8000000) /*!< Value of the External oscillator in Hz */
+#endif /* HSE_VALUE */
+
+/**
+ * @brief In the following line adjust the External High Speed oscillator (HSE) Startup
+ Timeout value
+ */
+#if !defined (HSE_STARTUP_TIMEOUT)
+ #define HSE_STARTUP_TIMEOUT ((uint16_t)0x0500) /*!< Time out for HSE start up */
+#endif /* HSE_STARTUP_TIMEOUT */
+
+/**
+ * @brief In the following line adjust the Internal High Speed oscillator (HSI) Startup
+ Timeout value
+ */
+#if !defined (HSI_STARTUP_TIMEOUT)
+ #define HSI_STARTUP_TIMEOUT ((uint16_t)0x0500) /*!< Time out for HSI start up */
+#endif /* HSI_STARTUP_TIMEOUT */
+
+#if !defined (HSI_VALUE)
+ #define HSI_VALUE ((uint32_t)8000000)
+#endif /* HSI_VALUE */ /*!< Value of the Internal High Speed oscillator in Hz.
+ The real value may vary depending on the variations
+ in voltage and temperature. */
+#if !defined (LSI_VALUE)
+ #define LSI_VALUE ((uint32_t)40000)
+#endif /* LSI_VALUE */ /*!< Value of the Internal Low Speed oscillator in Hz
+ The real value may vary depending on the variations
+ in voltage and temperature. */
+#if !defined (LSE_VALUE)
+ #define LSE_VALUE ((uint32_t)32768) /*!< Value of the External Low Speed oscillator in Hz */
+#endif /* LSE_VALUE */
+
+
+/**
+ * @brief STM32F30x Standard Peripherals Library version number V1.0.0
+ */
+#define __STM32F30X_STDPERIPH_VERSION_MAIN (0x01) /*!< [31:24] main version */
+#define __STM32F30X_STDPERIPH_VERSION_SUB1 (0x00) /*!< [23:16] sub1 version */
+#define __STM32F30X_STDPERIPH_VERSION_SUB2 (0x00) /*!< [15:8] sub2 version */
+#define __STM32F30X_STDPERIPH_VERSION_RC (0x00) /*!< [7:0] release candidate */
+#define __STM32F30X_STDPERIPH_VERSION ( (__STM32F30X_STDPERIPH_VERSION_MAIN << 24)\
+ |(__STM32F30X_STDPERIPH_VERSION_SUB1 << 16)\
+ |(__STM32F30X_STDPERIPH_VERSION_SUB2 << 8)\
+ |(__STM32F30X_STDPERIPH_VERSION_RC))
+
+/**
+ * @}
+ */
+
+/** @addtogroup Configuration_section_for_CMSIS
+ * @{
+ */
+
+/**
+ * @brief Configuration of the Cortex-M4 Processor and Core Peripherals
+ */
+#define __CM4_REV 0x0001 /*!< Core revision r0p1 */
+#define __MPU_PRESENT 1 /*!< STM32F30X provide an MPU */
+#define __NVIC_PRIO_BITS 4 /*!< STM32F30X uses 4 Bits for the Priority Levels */
+#define __Vendor_SysTickConfig 0 /*!< Set to 1 if different SysTick Config is used */
+#define __FPU_PRESENT 1 /*!< STM32F30X provide an FPU */
+
+
+/**
+ * @brief STM32F30X Interrupt Number Definition, according to the selected device
+ * in @ref Library_configuration_section
+ */
+typedef enum IRQn
+{
+/****** Cortex-M4 Processor Exceptions Numbers ****************************************************************/
+ NonMaskableInt_IRQn = -14, /*!< 2 Non Maskable Interrupt */
+ MemoryManagement_IRQn = -12, /*!< 4 Cortex-M4 Memory Management Interrupt */
+ BusFault_IRQn = -11, /*!< 5 Cortex-M4 Bus Fault Interrupt */
+ UsageFault_IRQn = -10, /*!< 6 Cortex-M4 Usage Fault Interrupt */
+ SVCall_IRQn = -5, /*!< 11 Cortex-M4 SV Call Interrupt */
+ DebugMonitor_IRQn = -4, /*!< 12 Cortex-M4 Debug Monitor Interrupt */
+ PendSV_IRQn = -2, /*!< 14 Cortex-M4 Pend SV Interrupt */
+ SysTick_IRQn = -1, /*!< 15 Cortex-M4 System Tick Interrupt */
+/****** STM32 specific Interrupt Numbers **********************************************************************/
+ WWDG_IRQn = 0, /*!< Window WatchDog Interrupt */
+ PVD_IRQn = 1, /*!< PVD through EXTI Line detection Interrupt */
+ TAMPER_STAMP_IRQn = 2, /*!< Tamper and TimeStamp interrupts */
+ RTC_WKUP_IRQn = 3, /*!< RTC Wakeup interrupt through the EXTI lines 17, 19 & 20 */
+ FLASH_IRQn = 4, /*!< FLASH global Interrupt */
+ RCC_IRQn = 5, /*!< RCC global Interrupt */
+ EXTI0_IRQn = 6, /*!< EXTI Line0 Interrupt */
+ EXTI1_IRQn = 7, /*!< EXTI Line1 Interrupt */
+ EXTI2_TS_IRQn = 8, /*!< EXTI Line2 Interrupt and Touch Sense Interrupt */
+ EXTI3_IRQn = 9, /*!< EXTI Line3 Interrupt */
+ EXTI4_IRQn = 10, /*!< EXTI Line4 Interrupt */
+ DMA1_Channel1_IRQn = 11, /*!< DMA1 Channel 1 Interrupt */
+ DMA1_Channel2_IRQn = 12, /*!< DMA1 Channel 2 Interrupt */
+ DMA1_Channel3_IRQn = 13, /*!< DMA1 Channel 3 Interrupt */
+ DMA1_Channel4_IRQn = 14, /*!< DMA1 Channel 4 Interrupt */
+ DMA1_Channel5_IRQn = 15, /*!< DMA1 Channel 5 Interrupt */
+ DMA1_Channel6_IRQn = 16, /*!< DMA1 Channel 6 Interrupt */
+ DMA1_Channel7_IRQn = 17, /*!< DMA1 Channel 7 Interrupt */
+ ADC1_2_IRQn = 18, /*!< ADC1 & ADC2 Interrupts */
+ USB_HP_CAN1_TX_IRQn = 19, /*!< USB Device High Priority or CAN1 TX Interrupts */
+ USB_LP_CAN1_RX0_IRQn = 20, /*!< USB Device Low Priority or CAN1 RX0 Interrupts */
+ CAN1_RX1_IRQn = 21, /*!< CAN1 RX1 Interrupt */
+ CAN1_SCE_IRQn = 22, /*!< CAN1 SCE Interrupt */
+ EXTI9_5_IRQn = 23, /*!< External Line[9:5] Interrupts */
+ TIM1_BRK_TIM15_IRQn = 24, /*!< TIM1 Break and TIM15 Interrupts */
+ TIM1_UP_TIM16_IRQn = 25, /*!< TIM1 Update and TIM16 Interrupts */
+ TIM1_TRG_COM_TIM17_IRQn = 26, /*!< TIM1 Trigger and Commutation and TIM17 Interrupt */
+ TIM1_CC_IRQn = 27, /*!< TIM1 Capture Compare Interrupt */
+ TIM2_IRQn = 28, /*!< TIM2 global Interrupt */
+ TIM3_IRQn = 29, /*!< TIM3 global Interrupt */
+ TIM4_IRQn = 30, /*!< TIM4 global Interrupt */
+ I2C1_EV_IRQn = 31, /*!< I2C1 Event Interrupt */
+ I2C1_ER_IRQn = 32, /*!< I2C1 Error Interrupt */
+ I2C2_EV_IRQn = 33, /*!< I2C2 Event Interrupt */
+ I2C2_ER_IRQn = 34, /*!< I2C2 Error Interrupt */
+ SPI1_IRQn = 35, /*!< SPI1 global Interrupt */
+ SPI2_IRQn = 36, /*!< SPI2 global Interrupt */
+ USART1_IRQn = 37, /*!< USART1 global Interrupt */
+ USART2_IRQn = 38, /*!< USART2 global Interrupt */
+ USART3_IRQn = 39, /*!< USART3 global Interrupt */
+ EXTI15_10_IRQn = 40, /*!< External Line[15:10] Interrupts */
+ RTC_Alarm_IRQn = 41, /*!< RTC Alarm (A and B) through EXTI Line Interrupt */
+ USBWakeUp_IRQn = 42, /*!< USB Wakeup Interrupt */
+ TIM8_BRK_IRQn = 43, /*!< TIM8 Break Interrupt */
+ TIM8_UP_IRQn = 44, /*!< TIM8 Update Interrupt */
+ TIM8_TRG_COM_IRQn = 45, /*!< TIM8 Trigger and Commutation Interrupt */
+ TIM8_CC_IRQn = 46, /*!< TIM8 Capture Compare Interrupt */
+ ADC3_IRQn = 47, /*!< ADC3 global Interrupt */
+ SPI3_IRQn = 51, /*!< SPI3 global Interrupt */
+ UART4_IRQn = 52, /*!< UART4 global Interrupt */
+ UART5_IRQn = 53, /*!< UART5 global Interrupt */
+ TIM6_DAC_IRQn = 54, /*!< TIM6 global and DAC1&2 underrun error interrupts */
+ TIM7_IRQn = 55, /*!< TIM7 global Interrupt */
+ DMA2_Channel1_IRQn = 56, /*!< DMA2 Channel 1 global Interrupt */
+ DMA2_Channel2_IRQn = 57, /*!< DMA2 Channel 2 global Interrupt */
+ DMA2_Channel3_IRQn = 58, /*!< DMA2 Channel 3 global Interrupt */
+ DMA2_Channel4_IRQn = 59, /*!< DMA2 Channel 4 global Interrupt */
+ DMA2_Channel5_IRQn = 60, /*!< DMA2 Channel 5 global Interrupt */
+ ADC4_IRQn = 61, /*!< ADC4 global Interrupt */
+ COMP1_2_3_IRQn = 64, /*!< COMP1, COMP2 and COMP3 global Interrupt */
+ COMP4_5_6_IRQn = 65, /*!< COMP5, COMP6 and COMP4 global Interrupt */
+ COMP7_IRQn = 66, /*!< COMP7 global Interrupt */
+ USB_HP_IRQn = 74, /*!< USB High Priority global Interrupt remap */
+ USB_LP_IRQn = 75, /*!< USB Low Priority global Interrupt remap */
+ USBWakeUp_RMP_IRQn = 76, /*!< USB Wakeup Interrupt remap */
+ FPU_IRQn = 81 /*!< Floating point Interrupt */
+} IRQn_Type;
+
+/**
+ * @}
+ */
+
+#include "core_cm4.h" /* Cortex-M4 processor and core peripherals */
+#include "system_stm32f30x.h" /* STM32F30x System Header */
+#include
+
+
\ No newline at end of file
diff --git a/Libraries/CMSIS/Device/ST/STM32F30x/Source/Templates/TrueSTUDIO/startup_stm32f30x.s b/Libraries/CMSIS/Device/ST/STM32F30x/Source/Templates/TrueSTUDIO/startup_stm32f30x.s
new file mode 100644
index 0000000..4acbed8
--- /dev/null
+++ b/Libraries/CMSIS/Device/ST/STM32F30x/Source/Templates/TrueSTUDIO/startup_stm32f30x.s
@@ -0,0 +1,469 @@
+/**
+ ******************************************************************************
+ * @file startup_stm32f30x.s
+ * @author MCD Application Team
+ * @version V1.0.0
+ * @date 04-September-2012
+ * @brief stm32f30x vector table for Atollic TrueSTUDIO toolchain.
+ * This module performs:
+ * - Set the initial SP
+ * - Set the initial PC == Reset_Handler,
+ * - Set the vector table entries with the exceptions ISR address,
+ * - Configure the clock system
+ * - Branches to main in the C library (which eventually
+ * calls main()).
+ * After Reset the Cortex-M4 processor is in Thread mode,
+ * priority is Privileged, and the Stack is set to Main.
+ ******************************************************************************
+ * @attention
+ *
+ *
+
+
+
+
+
+
+
+
|
+
© COPYRIGHT 2012 STMicroelectronics
+ *
+ * Licensed under MCD-ST Liberty SW License Agreement V2, (the "License");
+ * You may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at:
+ *
+ * http://www.st.com/software_license_agreement_liberty_v2
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ *
+ ******************************************************************************
+ */
+
+ .syntax unified
+ .cpu cortex-m4
+ .fpu softvfp
+ .thumb
+
+.global g_pfnVectors
+.global Default_Handler
+
+/* start address for the initialization values of the .data section.
+defined in linker script */
+.word _sidata
+/* start address for the .data section. defined in linker script */
+.word _sdata
+/* end address for the .data section. defined in linker script */
+.word _edata
+/* start address for the .bss section. defined in linker script */
+.word _sbss
+/* end address for the .bss section. defined in linker script */
+.word _ebss
+
+.equ BootRAM, 0xF1E0F85F
+/**
+ * @brief This is the code that gets called when the processor first
+ * starts execution following a reset event. Only the absolutely
+ * necessary set is performed, after which the application
+ * supplied main() routine is called.
+ * @param None
+ * @retval : None
+*/
+
+ .section .text.Reset_Handler
+ .weak Reset_Handler
+ .type Reset_Handler, %function
+Reset_Handler:
+
+/* Copy the data segment initializers from flash to SRAM */
+ movs r1, #0
+ b LoopCopyDataInit
+
+CopyDataInit:
+ ldr r3, =_sidata
+ ldr r3, [r3, r1]
+ str r3, [r0, r1]
+ adds r1, r1, #4
+
+LoopCopyDataInit:
+ ldr r0, =_sdata
+ ldr r3, =_edata
+ adds r2, r0, r1
+ cmp r2, r3
+ bcc CopyDataInit
+ ldr r2, =_sbss
+ b LoopFillZerobss
+/* Zero fill the bss segment. */
+FillZerobss:
+ movs r3, #0
+ str r3, [r2], #4
+
+LoopFillZerobss:
+ ldr r3, = _ebss
+ cmp r2, r3
+ bcc FillZerobss
+
+/* Call the clock system intitialization function.*/
+ bl SystemInit
+/* Call static constructors */
+ bl __libc_init_array
+/* Call the application's entry point.*/
+ bl main
+
+LoopForever:
+ b LoopForever
+
+.size Reset_Handler, .-Reset_Handler
+
+/**
+ * @brief This is the code that gets called when the processor receives an
+ * unexpected interrupt. This simply enters an infinite loop, preserving
+ * the system state for examination by a debugger.
+ *
+ * @param None
+ * @retval : None
+*/
+ .section .text.Default_Handler,"ax",%progbits
+Default_Handler:
+Infinite_Loop:
+ b Infinite_Loop
+ .size Default_Handler, .-Default_Handler
+/******************************************************************************
+*
+* The minimal vector table for a Cortex-M4. Note that the proper constructs
+* must be placed on this to ensure that it ends up at physical address
+* 0x0000.0000.
+*
+******************************************************************************/
+ .section .isr_vector,"a",%progbits
+ .type g_pfnVectors, %object
+ .size g_pfnVectors, .-g_pfnVectors
+
+
+g_pfnVectors:
+ .word _estack
+ .word Reset_Handler
+ .word NMI_Handler
+ .word HardFault_Handler
+ .word MemManage_Handler
+ .word BusFault_Handler
+ .word UsageFault_Handler
+ .word 0
+ .word 0
+ .word 0
+ .word 0
+ .word SVC_Handler
+ .word DebugMon_Handler
+ .word 0
+ .word PendSV_Handler
+ .word SysTick_Handler
+ .word WWDG_IRQHandler
+ .word PVD_IRQHandler
+ .word TAMPER_STAMP_IRQHandler
+ .word RTC_WKUP_IRQHandler
+ .word FLASH_IRQHandler
+ .word RCC_IRQHandler
+ .word EXTI0_IRQHandler
+ .word EXTI1_IRQHandler
+ .word EXTI2_TS_IRQHandler
+ .word EXTI3_IRQHandler
+ .word EXTI4_IRQHandler
+ .word DMA1_Channel1_IRQHandler
+ .word DMA1_Channel2_IRQHandler
+ .word DMA1_Channel3_IRQHandler
+ .word DMA1_Channel4_IRQHandler
+ .word DMA1_Channel5_IRQHandler
+ .word DMA1_Channel6_IRQHandler
+ .word DMA1_Channel7_IRQHandler
+ .word ADC1_2_IRQHandler
+ .word USB_HP_CAN1_TX_IRQHandler
+ .word USB_LP_CAN1_RX0_IRQHandler
+ .word CAN1_RX1_IRQHandler
+ .word CAN1_SCE_IRQHandler
+ .word EXTI9_5_IRQHandler
+ .word TIM1_BRK_TIM15_IRQHandler
+ .word TIM1_UP_TIM16_IRQHandler
+ .word TIM1_TRG_COM_TIM17_IRQHandler
+ .word TIM1_CC_IRQHandler
+ .word TIM2_IRQHandler
+ .word TIM3_IRQHandler
+ .word TIM4_IRQHandler
+ .word I2C1_EV_IRQHandler
+ .word I2C1_ER_IRQHandler
+ .word I2C2_EV_IRQHandler
+ .word I2C2_ER_IRQHandler
+ .word SPI1_IRQHandler
+ .word SPI2_IRQHandler
+ .word USART1_IRQHandler
+ .word USART2_IRQHandler
+ .word USART3_IRQHandler
+ .word EXTI15_10_IRQHandler
+ .word RTC_Alarm_IRQHandler
+ .word USBWakeUp_IRQHandler
+ .word TIM8_BRK_IRQHandler
+ .word TIM8_UP_IRQHandler
+ .word TIM8_TRG_COM_IRQHandler
+ .word TIM8_CC_IRQHandler
+ .word ADC3_IRQHandler
+ .word 0
+ .word 0
+ .word 0
+ .word SPI3_IRQHandler
+ .word UART4_IRQHandler
+ .word UART5_IRQHandler
+ .word TIM6_DAC_IRQHandler
+ .word TIM7_IRQHandler
+ .word DMA2_Channel1_IRQHandler
+ .word DMA2_Channel2_IRQHandler
+ .word DMA2_Channel3_IRQHandler
+ .word DMA2_Channel4_IRQHandler
+ .word DMA2_Channel5_IRQHandler
+ .word ADC4_IRQHandler
+ .word 0
+ .word 0
+ .word COMP1_2_3_IRQHandler
+ .word COMP4_5_6_IRQHandler
+ .word COMP7_IRQHandler
+ .word 0
+ .word 0
+ .word 0
+ .word 0
+ .word 0
+ .word 0
+ .word 0
+ .word USB_HP_IRQHandler
+ .word USB_LP_IRQHandler
+ .word USBWakeUp_RMP_IRQHandler
+ .word 0
+ .word 0
+ .word 0
+ .word 0
+ .word FPU_IRQHandler
+
+/*******************************************************************************
+*
+* Provide weak aliases for each Exception handler to the Default_Handler.
+* As they are weak aliases, any function with the same name will override
+* this definition.
+*
+*******************************************************************************/
+
+ .weak NMI_Handler
+ .thumb_set NMI_Handler,Default_Handler
+
+ .weak HardFault_Handler
+ .thumb_set HardFault_Handler,Default_Handler
+
+ .weak MemManage_Handler
+ .thumb_set MemManage_Handler,Default_Handler
+
+ .weak BusFault_Handler
+ .thumb_set BusFault_Handler,Default_Handler
+
+ .weak UsageFault_Handler
+ .thumb_set UsageFault_Handler,Default_Handler
+
+ .weak SVC_Handler
+ .thumb_set SVC_Handler,Default_Handler
+
+ .weak DebugMon_Handler
+ .thumb_set DebugMon_Handler,Default_Handler
+
+ .weak PendSV_Handler
+ .thumb_set PendSV_Handler,Default_Handler
+
+ .weak SysTick_Handler
+ .thumb_set SysTick_Handler,Default_Handler
+
+ .weak WWDG_IRQHandler
+ .thumb_set WWDG_IRQHandler,Default_Handler
+
+ .weak PVD_IRQHandler
+ .thumb_set PVD_IRQHandler,Default_Handler
+
+ .weak TAMPER_STAMP_IRQHandler
+ .thumb_set TAMPER_STAMP_IRQHandler,Default_Handler
+
+ .weak RTC_WKUP_IRQHandler
+ .thumb_set RTC_WKUP_IRQHandler,Default_Handler
+
+ .weak FLASH_IRQHandler
+ .thumb_set FLASH_IRQHandler,Default_Handler
+
+ .weak RCC_IRQHandler
+ .thumb_set RCC_IRQHandler,Default_Handler
+
+ .weak EXTI0_IRQHandler
+ .thumb_set EXTI0_IRQHandler,Default_Handler
+
+ .weak EXTI1_IRQHandler
+ .thumb_set EXTI1_IRQHandler,Default_Handler
+
+ .weak EXTI2_TS_IRQHandler
+ .thumb_set EXTI2_TS_IRQHandler,Default_Handler
+
+ .weak EXTI3_IRQHandler
+ .thumb_set EXTI3_IRQHandler,Default_Handler
+
+ .weak EXTI4_IRQHandler
+ .thumb_set EXTI4_IRQHandler,Default_Handler
+
+ .weak DMA1_Channel1_IRQHandler
+ .thumb_set DMA1_Channel1_IRQHandler,Default_Handler
+
+ .weak DMA1_Channel2_IRQHandler
+ .thumb_set DMA1_Channel2_IRQHandler,Default_Handler
+
+ .weak DMA1_Channel3_IRQHandler
+ .thumb_set DMA1_Channel3_IRQHandler,Default_Handler
+
+ .weak DMA1_Channel4_IRQHandler
+ .thumb_set DMA1_Channel4_IRQHandler,Default_Handler
+
+ .weak DMA1_Channel5_IRQHandler
+ .thumb_set DMA1_Channel5_IRQHandler,Default_Handler
+
+ .weak DMA1_Channel6_IRQHandler
+ .thumb_set DMA1_Channel6_IRQHandler,Default_Handler
+
+ .weak DMA1_Channel7_IRQHandler
+ .thumb_set DMA1_Channel7_IRQHandler,Default_Handler
+
+ .weak ADC1_2_IRQHandler
+ .thumb_set ADC1_2_IRQHandler,Default_Handler
+
+ .weak USB_HP_CAN1_TX_IRQHandler
+ .thumb_set USB_HP_CAN1_TX_IRQHandler,Default_Handler
+
+ .weak USB_LP_CAN1_RX0_IRQHandler
+ .thumb_set USB_LP_CAN1_RX0_IRQHandler,Default_Handler
+
+ .weak CAN1_RX1_IRQHandler
+ .thumb_set CAN1_RX1_IRQHandler,Default_Handler
+
+ .weak CAN1_SCE_IRQHandler
+ .thumb_set CAN1_SCE_IRQHandler,Default_Handler
+
+ .weak EXTI9_5_IRQHandler
+ .thumb_set EXTI9_5_IRQHandler,Default_Handler
+
+ .weak TIM1_BRK_TIM15_IRQHandler
+ .thumb_set TIM1_BRK_TIM15_IRQHandler,Default_Handler
+
+ .weak TIM1_UP_TIM16_IRQHandler
+ .thumb_set TIM1_UP_TIM16_IRQHandler,Default_Handler
+
+ .weak TIM1_TRG_COM_TIM17_IRQHandler
+ .thumb_set TIM1_TRG_COM_TIM17_IRQHandler,Default_Handler
+
+ .weak TIM1_CC_IRQHandler
+ .thumb_set TIM1_CC_IRQHandler,Default_Handler
+
+ .weak TIM2_IRQHandler
+ .thumb_set TIM2_IRQHandler,Default_Handler
+
+ .weak TIM3_IRQHandler
+ .thumb_set TIM3_IRQHandler,Default_Handler
+
+ .weak TIM4_IRQHandler
+ .thumb_set TIM4_IRQHandler,Default_Handler
+
+ .weak I2C1_EV_IRQHandler
+ .thumb_set I2C1_EV_IRQHandler,Default_Handler
+
+ .weak I2C1_ER_IRQHandler
+ .thumb_set I2C1_ER_IRQHandler,Default_Handler
+
+ .weak I2C2_EV_IRQHandler
+ .thumb_set I2C2_EV_IRQHandler,Default_Handler
+
+ .weak I2C2_ER_IRQHandler
+ .thumb_set I2C2_ER_IRQHandler,Default_Handler
+
+ .weak SPI1_IRQHandler
+ .thumb_set SPI1_IRQHandler,Default_Handler
+
+ .weak SPI2_IRQHandler
+ .thumb_set SPI2_IRQHandler,Default_Handler
+
+ .weak USART1_IRQHandler
+ .thumb_set USART1_IRQHandler,Default_Handler
+
+ .weak USART2_IRQHandler
+ .thumb_set USART2_IRQHandler,Default_Handler
+
+ .weak USART3_IRQHandler
+ .thumb_set USART3_IRQHandler,Default_Handler
+
+ .weak EXTI15_10_IRQHandler
+ .thumb_set EXTI15_10_IRQHandler,Default_Handler
+
+ .weak RTC_Alarm_IRQHandler
+ .thumb_set RTC_Alarm_IRQHandler,Default_Handler
+
+ .weak USBWakeUp_IRQHandler
+ .thumb_set USBWakeUp_IRQHandler,Default_Handler
+
+ .weak TIM8_BRK_IRQHandler
+ .thumb_set TIM8_BRK_IRQHandler,Default_Handler
+
+ .weak TIM8_UP_IRQHandler
+ .thumb_set TIM8_UP_IRQHandler,Default_Handler
+
+ .weak TIM8_TRG_COM_IRQHandler
+ .thumb_set TIM8_TRG_COM_IRQHandler,Default_Handler
+
+ .weak TIM8_CC_IRQHandler
+ .thumb_set TIM8_CC_IRQHandler,Default_Handler
+
+ .weak ADC3_IRQHandler
+ .thumb_set ADC3_IRQHandler,Default_Handler
+
+ .weak SPI3_IRQHandler
+ .thumb_set SPI3_IRQHandler,Default_Handler
+
+ .weak UART4_IRQHandler
+ .thumb_set UART4_IRQHandler,Default_Handler
+
+ .weak UART5_IRQHandler
+ .thumb_set UART5_IRQHandler,Default_Handler
+
+ .weak TIM6_DAC_IRQHandler
+ .thumb_set TIM6_DAC_IRQHandler,Default_Handler
+
+ .weak TIM7_IRQHandler
+ .thumb_set TIM7_IRQHandler,Default_Handler
+
+ .weak DMA2_Channel1_IRQHandler
+ .thumb_set DMA2_Channel1_IRQHandler,Default_Handler
+
+ .weak DMA2_Channel2_IRQHandler
+ .thumb_set DMA2_Channel2_IRQHandler,Default_Handler
+
+ .weak DMA2_Channel3_IRQHandler
+ .thumb_set DMA2_Channel3_IRQHandler,Default_Handler
+
+ .weak DMA2_Channel4_IRQHandler
+ .thumb_set DMA2_Channel4_IRQHandler,Default_Handler
+
+ .weak DMA2_Channel5_IRQHandler
+ .thumb_set DMA2_Channel5_IRQHandler,Default_Handler
+
+ .weak ADC4_IRQHandler
+ .thumb_set ADC4_IRQHandler,Default_Handler
+
+ .weak COMP1_2_3_IRQHandler
+ .thumb_set COMP1_2_3_IRQHandler,Default_Handler
+
+ .weak COMP4_5_6_IRQHandler
+ .thumb_set COMP4_5_6_IRQHandler,Default_Handler
+
+ .weak COMP7_IRQHandler
+ .thumb_set COMP7_IRQHandler,Default_Handler
+
+ .weak USB_HP_IRQHandler
+ .thumb_set USB_HP_IRQHandler,Default_Handler
+
+ .weak USB_LP_IRQHandler
+ .thumb_set USB_LP_IRQHandler,Default_Handler
+
+ .weak USBWakeUp_RMP_IRQHandler
+ .thumb_set USBWakeUp_RMP_IRQHandler,Default_Handler
+
+ .weak FPU_IRQHandler
+ .thumb_set FPU_IRQHandler,Default_Handler
+/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
diff --git a/Libraries/CMSIS/Device/ST/STM32F30x/Source/Templates/arm/startup_stm32f30x.s b/Libraries/CMSIS/Device/ST/STM32F30x/Source/Templates/arm/startup_stm32f30x.s
new file mode 100644
index 0000000..897368a
--- /dev/null
+++ b/Libraries/CMSIS/Device/ST/STM32F30x/Source/Templates/arm/startup_stm32f30x.s
@@ -0,0 +1,399 @@
+;******************** (C) COPYRIGHT 2012 STMicroelectronics ********************
+;* File Name : startup_stm32f30x.s
+;* Author : MCD Application Team
+;* Version : V1.0.0
+;* Date : 04-September-2012
+;* Description : STM32F30x devices vector table for MDK-ARM toolchain.
+;* This module performs:
+;* - Set the initial SP
+;* - Set the initial PC == Reset_Handler
+;* - Set the vector table entries with the exceptions ISR address
+;* - Branches to __main in the C library (which eventually
+;* calls main()).
+;* After Reset the CortexM4 processor is in Thread mode,
+;* priority is Privileged, and the Stack is set to Main.
+;* <<< Use Configuration Wizard in Context Menu >>>
+;*******************************************************************************
+;
+; Licensed under MCD-ST Liberty SW License Agreement V2, (the "License");
+; You may not use this file except in compliance with the License.
+; You may obtain a copy of the License at:
+;
+; http://www.st.com/software_license_agreement_liberty_v2
+;
+; Unless required by applicable law or agreed to in writing, software
+; distributed under the License is distributed on an "AS IS" BASIS,
+; WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+; See the License for the specific language governing permissions and
+; limitations under the License.
+;
+;*******************************************************************************
+
+; Amount of memory (in bytes) allocated for Stack
+; Tailor this value to your application needs
+; © COPYRIGHT 2012 STMicroelectronics
+ *
+ * Licensed under MCD-ST Liberty SW License Agreement V2, (the "License");
+ * You may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at:
+ *
+ * http://www.st.com/software_license_agreement_liberty_v2
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ *
+ ******************************************************************************
+ */
+
+ .syntax unified
+ .cpu cortex-m4
+ .fpu softvfp
+ .thumb
+
+.global g_pfnVectors
+.global Default_Handler
+
+/* start address for the initialization values of the .data section.
+defined in linker script */
+.word _sidata
+/* start address for the .data section. defined in linker script */
+.word _sdata
+/* end address for the .data section. defined in linker script */
+.word _edata
+/* start address for the .bss section. defined in linker script */
+.word _sbss
+/* end address for the .bss section. defined in linker script */
+.word _ebss
+/* stack used for SystemInit_ExtMemCtl; always internal RAM used */
+
+/**
+ * @brief This is the code that gets called when the processor first
+ * starts execution following a reset event. Only the absolutely
+ * necessary set is performed, after which the application
+ * supplied main() routine is called.
+ * @param None
+ * @retval : None
+*/
+
+ .section .text.Reset_Handler
+ .weak Reset_Handler
+ .type Reset_Handler, %function
+Reset_Handler:
+
+/* Copy the data segment initializers from flash to SRAM */
+ movs r1, #0
+ b LoopCopyDataInit
+
+CopyDataInit:
+ ldr r3, =_sidata
+ ldr r3, [r3, r1]
+ str r3, [r0, r1]
+ adds r1, r1, #4
+
+LoopCopyDataInit:
+ ldr r0, =_sdata
+ ldr r3, =_edata
+ adds r2, r0, r1
+ cmp r2, r3
+ bcc CopyDataInit
+ ldr r2, =_sbss
+ b LoopFillZerobss
+/* Zero fill the bss segment. */
+FillZerobss:
+ movs r3, #0
+ str r3, [r2], #4
+
+LoopFillZerobss:
+ ldr r3, = _ebss
+ cmp r2, r3
+ bcc FillZerobss
+
+/* Call the clock system intitialization function.*/
+ bl SystemInit
+/* Call the application's entry point.*/
+ bl main
+ bx lr
+.size Reset_Handler, .-Reset_Handler
+
+/**
+ * @brief This is the code that gets called when the processor receives an
+ * unexpected interrupt. This simply enters an infinite loop, preserving
+ * the system state for examination by a debugger.
+ * @param None
+ * @retval None
+*/
+ .section .text.Default_Handler,"ax",%progbits
+Default_Handler:
+Infinite_Loop:
+ b Infinite_Loop
+ .size Default_Handler, .-Default_Handler
+/******************************************************************************
+*
+* The minimal vector table for a Cortex M4. Note that the proper constructs
+* must be placed on this to ensure that it ends up at physical address
+* 0x0000.0000.
+*
+*******************************************************************************/
+ .section .isr_vector,"a",%progbits
+ .type g_pfnVectors, %object
+ .size g_pfnVectors, .-g_pfnVectors
+
+
+g_pfnVectors:
+ .word _estack
+ .word Reset_Handler
+ .word NMI_Handler
+ .word HardFault_Handler
+ .word MemManage_Handler
+ .word BusFault_Handler
+ .word UsageFault_Handler
+ .word 0
+ .word 0
+ .word 0
+ .word 0
+ .word SVC_Handler
+ .word DebugMon_Handler
+ .word 0
+ .word PendSV_Handler
+ .word SysTick_Handler
+ .word WWDG_IRQHandler
+ .word PVD_IRQHandler
+ .word TAMPER_STAMP_IRQHandler
+ .word RTC_WKUP_IRQHandler
+ .word FLASH_IRQHandler
+ .word RCC_IRQHandler
+ .word EXTI0_IRQHandler
+ .word EXTI1_IRQHandler
+ .word EXTI2_TS_IRQHandler
+ .word EXTI3_IRQHandler
+ .word EXTI4_IRQHandler
+ .word DMA1_Channel1_IRQHandler
+ .word DMA1_Channel2_IRQHandler
+ .word DMA1_Channel3_IRQHandler
+ .word DMA1_Channel4_IRQHandler
+ .word DMA1_Channel5_IRQHandler
+ .word DMA1_Channel6_IRQHandler
+ .word DMA1_Channel7_IRQHandler
+ .word ADC1_2_IRQHandler
+ .word USB_HP_CAN1_TX_IRQHandler
+ .word USB_LP_CAN1_RX0_IRQHandler
+ .word CAN1_RX1_IRQHandler
+ .word CAN1_SCE_IRQHandler
+ .word EXTI9_5_IRQHandler
+ .word TIM1_BRK_TIM15_IRQHandler
+ .word TIM1_UP_TIM16_IRQHandler
+ .word TIM1_TRG_COM_TIM17_IRQHandler
+ .word TIM1_CC_IRQHandler
+ .word TIM2_IRQHandler
+ .word TIM3_IRQHandler
+ .word TIM4_IRQHandler
+ .word I2C1_EV_IRQHandler
+ .word I2C1_ER_IRQHandler
+ .word I2C2_EV_IRQHandler
+ .word I2C2_ER_IRQHandler
+ .word SPI1_IRQHandler
+ .word SPI2_IRQHandler
+ .word USART1_IRQHandler
+ .word USART2_IRQHandler
+ .word USART3_IRQHandler
+ .word EXTI15_10_IRQHandler
+ .word RTC_Alarm_IRQHandler
+ .word USBWakeUp_IRQHandler
+ .word TIM8_BRK_IRQHandler
+ .word TIM8_UP_IRQHandler
+ .word TIM8_TRG_COM_IRQHandler
+ .word TIM8_CC_IRQHandler
+ .word ADC3_IRQHandler
+ .word 0
+ .word 0
+ .word 0
+ .word SPI3_IRQHandler
+ .word UART4_IRQHandler
+ .word UART5_IRQHandler
+ .word TIM6_DAC_IRQHandler
+ .word TIM7_IRQHandler
+ .word DMA2_Channel1_IRQHandler
+ .word DMA2_Channel2_IRQHandler
+ .word DMA2_Channel3_IRQHandler
+ .word DMA2_Channel4_IRQHandler
+ .word DMA2_Channel5_IRQHandler
+ .word ADC4_IRQHandler
+ .word 0
+ .word 0
+ .word COMP1_2_3_IRQHandler
+ .word COMP4_5_6_IRQHandler
+ .word COMP7_IRQHandler
+ .word 0
+ .word 0
+ .word 0
+ .word 0
+ .word 0
+ .word 0
+ .word 0
+ .word USB_HP_IRQHandler
+ .word USB_LP_IRQHandler
+ .word USBWakeUp_RMP_IRQHandler
+ .word 0
+ .word 0
+ .word 0
+ .word 0
+ .word FPU_IRQHandler
+
+/*******************************************************************************
+*
+* Provide weak aliases for each Exception handler to the Default_Handler.
+* As they are weak aliases, any function with the same name will override
+* this definition.
+*
+*******************************************************************************/
+
+ .weak NMI_Handler
+ .thumb_set NMI_Handler,Default_Handler
+
+ .weak HardFault_Handler
+ .thumb_set HardFault_Handler,Default_Handler
+
+ .weak MemManage_Handler
+ .thumb_set MemManage_Handler,Default_Handler
+
+ .weak BusFault_Handler
+ .thumb_set BusFault_Handler,Default_Handler
+
+ .weak UsageFault_Handler
+ .thumb_set UsageFault_Handler,Default_Handler
+
+ .weak SVC_Handler
+ .thumb_set SVC_Handler,Default_Handler
+
+ .weak DebugMon_Handler
+ .thumb_set DebugMon_Handler,Default_Handler
+
+ .weak PendSV_Handler
+ .thumb_set PendSV_Handler,Default_Handler
+
+ .weak SysTick_Handler
+ .thumb_set SysTick_Handler,Default_Handler
+
+ .weak WWDG_IRQHandler
+ .thumb_set WWDG_IRQHandler,Default_Handler
+
+ .weak PVD_IRQHandler
+ .thumb_set PVD_IRQHandler,Default_Handler
+
+ .weak TAMPER_STAMP_IRQHandler
+ .thumb_set TAMPER_STAMP_IRQHandler,Default_Handler
+
+ .weak RTC_WKUP_IRQHandler
+ .thumb_set RTC_WKUP_IRQHandler,Default_Handler
+
+ .weak FLASH_IRQHandler
+ .thumb_set FLASH_IRQHandler,Default_Handler
+
+ .weak RCC_IRQHandler
+ .thumb_set RCC_IRQHandler,Default_Handler
+
+ .weak EXTI0_IRQHandler
+ .thumb_set EXTI0_IRQHandler,Default_Handler
+
+ .weak EXTI1_IRQHandler
+ .thumb_set EXTI1_IRQHandler,Default_Handler
+
+ .weak EXTI2_TS_IRQHandler
+ .thumb_set EXTI2_TS_IRQHandler,Default_Handler
+
+ .weak EXTI3_IRQHandler
+ .thumb_set EXTI3_IRQHandler,Default_Handler
+
+ .weak EXTI4_IRQHandler
+ .thumb_set EXTI4_IRQHandler,Default_Handler
+
+ .weak DMA1_Channel1_IRQHandler
+ .thumb_set DMA1_Channel1_IRQHandler,Default_Handler
+
+ .weak DMA1_Channel2_IRQHandler
+ .thumb_set DMA1_Channel2_IRQHandler,Default_Handler
+
+ .weak DMA1_Channel3_IRQHandler
+ .thumb_set DMA1_Channel3_IRQHandler,Default_Handler
+
+ .weak DMA1_Channel4_IRQHandler
+ .thumb_set DMA1_Channel4_IRQHandler,Default_Handler
+
+ .weak DMA1_Channel5_IRQHandler
+ .thumb_set DMA1_Channel5_IRQHandler,Default_Handler
+
+ .weak DMA1_Channel6_IRQHandler
+ .thumb_set DMA1_Channel6_IRQHandler,Default_Handler
+
+ .weak DMA1_Channel7_IRQHandler
+ .thumb_set DMA1_Channel7_IRQHandler,Default_Handler
+
+ .weak ADC1_2_IRQHandler
+ .thumb_set ADC1_2_IRQHandler,Default_Handler
+
+ .weak USB_HP_CAN1_TX_IRQHandler
+ .thumb_set USB_HP_CAN1_TX_IRQHandler,Default_Handler
+
+ .weak USB_LP_CAN1_RX0_IRQHandler
+ .thumb_set USB_LP_CAN1_RX0_IRQHandler,Default_Handler
+
+ .weak CAN1_RX1_IRQHandler
+ .thumb_set CAN1_RX1_IRQHandler,Default_Handler
+
+ .weak CAN1_SCE_IRQHandler
+ .thumb_set CAN1_SCE_IRQHandler,Default_Handler
+
+ .weak EXTI9_5_IRQHandler
+ .thumb_set EXTI9_5_IRQHandler,Default_Handler
+
+ .weak TIM1_BRK_TIM15_IRQHandler
+ .thumb_set TIM1_BRK_TIM15_IRQHandler,Default_Handler
+
+ .weak TIM1_UP_TIM16_IRQHandler
+ .thumb_set TIM1_UP_TIM16_IRQHandler,Default_Handler
+
+ .weak TIM1_TRG_COM_TIM17_IRQHandler
+ .thumb_set TIM1_TRG_COM_TIM17_IRQHandler,Default_Handler
+
+ .weak TIM1_CC_IRQHandler
+ .thumb_set TIM1_CC_IRQHandler,Default_Handler
+
+ .weak TIM2_IRQHandler
+ .thumb_set TIM2_IRQHandler,Default_Handler
+
+ .weak TIM3_IRQHandler
+ .thumb_set TIM3_IRQHandler,Default_Handler
+
+ .weak TIM4_IRQHandler
+ .thumb_set TIM4_IRQHandler,Default_Handler
+
+ .weak I2C1_EV_IRQHandler
+ .thumb_set I2C1_EV_IRQHandler,Default_Handler
+
+ .weak I2C1_ER_IRQHandler
+ .thumb_set I2C1_ER_IRQHandler,Default_Handler
+
+ .weak I2C2_EV_IRQHandler
+ .thumb_set I2C2_EV_IRQHandler,Default_Handler
+
+ .weak I2C2_ER_IRQHandler
+ .thumb_set I2C2_ER_IRQHandler,Default_Handler
+
+ .weak SPI1_IRQHandler
+ .thumb_set SPI1_IRQHandler,Default_Handler
+
+ .weak SPI2_IRQHandler
+ .thumb_set SPI2_IRQHandler,Default_Handler
+
+ .weak USART1_IRQHandler
+ .thumb_set USART1_IRQHandler,Default_Handler
+
+ .weak USART2_IRQHandler
+ .thumb_set USART2_IRQHandler,Default_Handler
+
+ .weak USART3_IRQHandler
+ .thumb_set USART3_IRQHandler,Default_Handler
+
+ .weak EXTI15_10_IRQHandler
+ .thumb_set EXTI15_10_IRQHandler,Default_Handler
+
+ .weak RTC_Alarm_IRQHandler
+ .thumb_set RTC_Alarm_IRQHandler,Default_Handler
+
+ .weak USBWakeUp_IRQHandler
+ .thumb_set USBWakeUp_IRQHandler,Default_Handler
+
+ .weak TIM8_BRK_IRQHandler
+ .thumb_set TIM8_BRK_IRQHandler,Default_Handler
+
+ .weak TIM8_UP_IRQHandler
+ .thumb_set TIM8_UP_IRQHandler,Default_Handler
+
+ .weak TIM8_TRG_COM_IRQHandler
+ .thumb_set TIM8_TRG_COM_IRQHandler,Default_Handler
+
+ .weak TIM8_CC_IRQHandler
+ .thumb_set TIM8_CC_IRQHandler,Default_Handler
+
+ .weak ADC3_IRQHandler
+ .thumb_set ADC3_IRQHandler,Default_Handler
+
+ .weak SPI3_IRQHandler
+ .thumb_set SPI3_IRQHandler,Default_Handler
+
+ .weak UART4_IRQHandler
+ .thumb_set UART4_IRQHandler,Default_Handler
+
+ .weak UART5_IRQHandler
+ .thumb_set UART5_IRQHandler,Default_Handler
+
+ .weak TIM6_DAC_IRQHandler
+ .thumb_set TIM6_DAC_IRQHandler,Default_Handler
+
+ .weak TIM7_IRQHandler
+ .thumb_set TIM7_IRQHandler,Default_Handler
+
+ .weak DMA2_Channel1_IRQHandler
+ .thumb_set DMA2_Channel1_IRQHandler,Default_Handler
+
+ .weak DMA2_Channel2_IRQHandler
+ .thumb_set DMA2_Channel2_IRQHandler,Default_Handler
+
+ .weak DMA2_Channel3_IRQHandler
+ .thumb_set DMA2_Channel3_IRQHandler,Default_Handler
+
+ .weak DMA2_Channel4_IRQHandler
+ .thumb_set DMA2_Channel4_IRQHandler,Default_Handler
+
+ .weak DMA2_Channel5_IRQHandler
+ .thumb_set DMA2_Channel5_IRQHandler,Default_Handler
+
+ .weak ADC4_IRQHandler
+ .thumb_set ADC4_IRQHandler,Default_Handler
+
+ .weak COMP1_2_3_IRQHandler
+ .thumb_set COMP1_2_3_IRQHandler,Default_Handler
+
+ .weak COMP4_5_6_IRQHandler
+ .thumb_set COMP4_5_6_IRQHandler,Default_Handler
+
+ .weak COMP7_IRQHandler
+ .thumb_set COMP7_IRQHandler,Default_Handler
+
+ .weak USB_HP_IRQHandler
+ .thumb_set USB_HP_IRQHandler,Default_Handler
+
+ .weak USB_LP_IRQHandler
+ .thumb_set USB_LP_IRQHandler,Default_Handler
+
+ .weak USBWakeUp_RMP_IRQHandler
+ .thumb_set USBWakeUp_RMP_IRQHandler,Default_Handler
+
+ .weak FPU_IRQHandler
+ .thumb_set FPU_IRQHandler,Default_Handler
+/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
diff --git a/Libraries/CMSIS/Device/ST/STM32F30x/Source/Templates/iar/startup_stm32f30x.s b/Libraries/CMSIS/Device/ST/STM32F30x/Source/Templates/iar/startup_stm32f30x.s
new file mode 100644
index 0000000..d8db7d0
--- /dev/null
+++ b/Libraries/CMSIS/Device/ST/STM32F30x/Source/Templates/iar/startup_stm32f30x.s
@@ -0,0 +1,554 @@
+;/******************** (C) COPYRIGHT 2012 STMicroelectronics ********************
+;* File Name : startup_stm32f30x.s
+;* Author : MCD Application Team
+;* Version : V1.0.0
+;* Date : 04-Sptember-2012
+;* Description : STM32F30x devices vector table for EWARM toolchain.
+;* This module performs:
+;* - Set the initial SP
+;* - Set the initial PC == _iar_program_start,
+;* - Set the vector table entries with the exceptions ISR
+;* address.
+;* - Branches to main in the C library (which eventually
+;* calls main()).
+;* After Reset the Cortex-M4 processor is in Thread mode,
+;* priority is Privileged, and the Stack is set to Main.
+;********************************************************************************
+;*
+;* Licensed under MCD-ST Liberty SW License Agreement V2, (the "License");
+;* You may not use this file except in compliance with the License.
+;* You may obtain a copy of the License at:
+;*
+;* http://www.st.com/software_license_agreement_liberty_v2
+;*
+;* Unless required by applicable law or agreed to in writing, software
+;* distributed under the License is distributed on an "AS IS" BASIS,
+;* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+;* See the License for the specific language governing permissions and
+;* limitations under the License.
+;*
+;*******************************************************************************
+;
+;
+; The modules in this file are included in the libraries, and may be replaced
+; by any user-defined modules that define the PUBLIC symbol _program_start or
+; a user defined start symbol.
+; To override the cstartup defined in the library, simply add your modified
+; version to the workbench project.
+;
+; The vector table is normally located at address 0.
+; When debugging in RAM, it can be located in RAM, aligned to at least 2^6.
+; The name "__vector_table" has special meaning for C-SPY:
+; it is where the SP start value is found, and the NVIC vector
+; table register (VTOR) is initialized to this address if != 0.
+;
+; Cortex-M version
+;
+
+ MODULE ?cstartup
+
+ ;; Forward declaration of sections.
+ SECTION CSTACK:DATA:NOROOT(3)
+
+ SECTION .intvec:CODE:NOROOT(2)
+
+ EXTERN __iar_program_start
+ EXTERN SystemInit
+ PUBLIC __vector_table
+
+ DATA
+__vector_table
+ DCD sfe(CSTACK)
+ DCD Reset_Handler ; Reset Handler
+
+ DCD NMI_Handler ; NMI Handler
+ DCD HardFault_Handler ; Hard Fault Handler
+ DCD MemManage_Handler ; MPU Fault Handler
+ DCD BusFault_Handler ; Bus Fault Handler
+ DCD UsageFault_Handler ; Usage Fault Handler
+ DCD 0 ; Reserved
+ DCD 0 ; Reserved
+ DCD 0 ; Reserved
+ DCD 0 ; Reserved
+ DCD SVC_Handler ; SVCall Handler
+ DCD DebugMon_Handler ; Debug Monitor Handler
+ DCD 0 ; Reserved
+ DCD PendSV_Handler ; PendSV Handler
+ DCD SysTick_Handler ; SysTick Handler
+
+ ; External Interrupts
+ DCD WWDG_IRQHandler ; Window WatchDog
+ DCD PVD_IRQHandler ; PVD through EXTI Line detection
+ DCD TAMPER_STAMP_IRQHandler ; Tamper and TimeStamps through the EXTI line
+ DCD RTC_WKUP_IRQHandler ; RTC Wakeup through the EXTI line
+ DCD FLASH_IRQHandler ; FLASH
+ DCD RCC_IRQHandler ; RCC
+ DCD EXTI0_IRQHandler ; EXTI Line0
+ DCD EXTI1_IRQHandler ; EXTI Line1
+ DCD EXTI2_TS_IRQHandler ; EXTI Line2 and Touch Sense
+ DCD EXTI3_IRQHandler ; EXTI Line3
+ DCD EXTI4_IRQHandler ; EXTI Line4
+ DCD DMA1_Channel1_IRQHandler ; DMA1 Channel 1
+ DCD DMA1_Channel2_IRQHandler ; DMA1 Channel 2
+ DCD DMA1_Channel3_IRQHandler ; DMA1 Channel 3
+ DCD DMA1_Channel4_IRQHandler ; DMA1 Channel 4
+ DCD DMA1_Channel5_IRQHandler ; DMA1 Channel 5
+ DCD DMA1_Channel6_IRQHandler ; DMA1 Channel 6
+ DCD DMA1_Channel7_IRQHandler ; DMA1 Channel 7
+ DCD ADC1_2_IRQHandler ; ADC1 and ADC2
+ DCD USB_HP_CAN1_TX_IRQHandler ; USB Device High Priority or CAN1 TX
+ DCD USB_LP_CAN1_RX0_IRQHandler ; USB Device Low Priority or CAN1 RX0
+ DCD CAN1_RX1_IRQHandler ; CAN1 RX1
+ DCD CAN1_SCE_IRQHandler ; CAN1 SCE
+ DCD EXTI9_5_IRQHandler ; External Line[9:5]s
+ DCD TIM1_BRK_TIM15_IRQHandler ; TIM1 Break and TIM15
+ DCD TIM1_UP_TIM16_IRQHandler ; TIM1 Update and TIM16
+ DCD TIM1_TRG_COM_TIM17_IRQHandler ; TIM1 Trigger and Commutation and TIM17
+ DCD TIM1_CC_IRQHandler ; TIM1 Capture Compare
+ DCD TIM2_IRQHandler ; TIM2
+ DCD TIM3_IRQHandler ; TIM3
+ DCD TIM4_IRQHandler ; TIM4
+ DCD I2C1_EV_IRQHandler ; I2C1 Event
+ DCD I2C1_ER_IRQHandler ; I2C1 Error
+ DCD I2C2_EV_IRQHandler ; I2C2 Event
+ DCD I2C2_ER_IRQHandler ; I2C2 Error
+ DCD SPI1_IRQHandler ; SPI1
+ DCD SPI2_IRQHandler ; SPI2
+ DCD USART1_IRQHandler ; USART1
+ DCD USART2_IRQHandler ; USART2
+ DCD USART3_IRQHandler ; USART3
+ DCD EXTI15_10_IRQHandler ; External Line[15:10]s
+ DCD RTC_Alarm_IRQHandler ; RTC Alarm (A and B) through EXTI Line
+ DCD USBWakeUp_IRQHandler ; USB Wakeup through EXTI line
+ DCD TIM8_BRK_IRQHandler ; TIM8 Break
+ DCD TIM8_UP_IRQHandler ; TIM8 Update
+ DCD TIM8_TRG_COM_IRQHandler ; TIM8 Trigger and Commutation
+ DCD TIM8_CC_IRQHandler ; TIM8 Capture Compare
+ DCD ADC3_IRQHandler ; ADC3
+ DCD 0 ; Reserved
+ DCD 0 ; Reserved
+ DCD 0 ; Reserved
+ DCD SPI3_IRQHandler ; SPI3
+ DCD UART4_IRQHandler ; UART4
+ DCD UART5_IRQHandler ; UART5
+ DCD TIM6_DAC_IRQHandler ; TIM6 and DAC1&2 underrun errors
+ DCD TIM7_IRQHandler ; TIM7
+ DCD DMA2_Channel1_IRQHandler ; DMA2 Channel 1
+ DCD DMA2_Channel2_IRQHandler ; DMA2 Channel 2
+ DCD DMA2_Channel3_IRQHandler ; DMA2 Channel 3
+ DCD DMA2_Channel4_IRQHandler ; DMA2 Channel 4
+ DCD DMA2_Channel5_IRQHandler ; DMA2 Channel 5
+ DCD ADC4_IRQHandler ; ADC4
+ DCD 0 ; Reserved
+ DCD 0 ; Reserved
+ DCD COMP1_2_3_IRQHandler ; COMP1, COMP2 and COMP3
+ DCD COMP4_5_6_IRQHandler ; COMP4, COMP5 and COMP6
+ DCD COMP7_IRQHandler ; COMP7
+ DCD 0 ; Reserved
+ DCD 0 ; Reserved
+ DCD 0 ; Reserved
+ DCD 0 ; Reserved
+ DCD 0 ; Reserved
+ DCD 0 ; Reserved
+ DCD 0 ; Reserved
+ DCD USB_HP_IRQHandler ; USB High Priority remap
+ DCD USB_LP_IRQHandler ; USB Low Priority remap
+ DCD USBWakeUp_RMP_IRQHandler ; USB Wakeup remap through EXTI
+ DCD 0 ; Reserved
+ DCD 0 ; Reserved
+ DCD 0 ; Reserved
+ DCD 0 ; Reserved
+ DCD FPU_IRQHandler ; FPU
+
+;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
+;;
+;; Default interrupt handlers.
+;;
+ THUMB
+ PUBWEAK Reset_Handler
+ SECTION .text:CODE:REORDER(2)
+Reset_Handler
+
+ LDR R0, =SystemInit
+ BLX R0
+ LDR R0, =__iar_program_start
+ BX R0
+
+ PUBWEAK NMI_Handler
+ SECTION .text:CODE:REORDER(1)
+NMI_Handler
+ B NMI_Handler
+
+ PUBWEAK HardFault_Handler
+ SECTION .text:CODE:REORDER(1)
+HardFault_Handler
+ B HardFault_Handler
+
+ PUBWEAK MemManage_Handler
+ SECTION .text:CODE:REORDER(1)
+MemManage_Handler
+ B MemManage_Handler
+
+ PUBWEAK BusFault_Handler
+ SECTION .text:CODE:REORDER(1)
+BusFault_Handler
+ B BusFault_Handler
+
+ PUBWEAK UsageFault_Handler
+ SECTION .text:CODE:REORDER(1)
+UsageFault_Handler
+ B UsageFault_Handler
+
+ PUBWEAK SVC_Handler
+ SECTION .text:CODE:REORDER(1)
+SVC_Handler
+ B SVC_Handler
+
+ PUBWEAK DebugMon_Handler
+ SECTION .text:CODE:REORDER(1)
+DebugMon_Handler
+ B DebugMon_Handler
+
+ PUBWEAK PendSV_Handler
+ SECTION .text:CODE:REORDER(1)
+PendSV_Handler
+ B PendSV_Handler
+
+ PUBWEAK SysTick_Handler
+ SECTION .text:CODE:REORDER(1)
+SysTick_Handler
+ B SysTick_Handler
+
+ PUBWEAK WWDG_IRQHandler
+ SECTION .text:CODE:REORDER(1)
+WWDG_IRQHandler
+ B WWDG_IRQHandler
+
+ PUBWEAK PVD_IRQHandler
+ SECTION .text:CODE:REORDER(1)
+PVD_IRQHandler
+ B PVD_IRQHandler
+
+ PUBWEAK TAMPER_STAMP_IRQHandler
+ SECTION .text:CODE:REORDER(1)
+TAMPER_STAMP_IRQHandler
+ B TAMPER_STAMP_IRQHandler
+
+ PUBWEAK RTC_WKUP_IRQHandler
+ SECTION .text:CODE:REORDER(1)
+RTC_WKUP_IRQHandler
+ B RTC_WKUP_IRQHandler
+
+ PUBWEAK FLASH_IRQHandler
+ SECTION .text:CODE:REORDER(1)
+FLASH_IRQHandler
+ B FLASH_IRQHandler
+
+ PUBWEAK RCC_IRQHandler
+ SECTION .text:CODE:REORDER(1)
+RCC_IRQHandler
+ B RCC_IRQHandler
+
+ PUBWEAK EXTI0_IRQHandler
+ SECTION .text:CODE:REORDER(1)
+EXTI0_IRQHandler
+ B EXTI0_IRQHandler
+
+ PUBWEAK EXTI1_IRQHandler
+ SECTION .text:CODE:REORDER(1)
+EXTI1_IRQHandler
+ B EXTI1_IRQHandler
+
+ PUBWEAK EXTI2_TS_IRQHandler
+ SECTION .text:CODE:REORDER(1)
+EXTI2_TS_IRQHandler
+ B EXTI2_TS_IRQHandler
+
+ PUBWEAK EXTI3_IRQHandler
+ SECTION .text:CODE:REORDER(1)
+EXTI3_IRQHandler
+ B EXTI3_IRQHandler
+
+ PUBWEAK EXTI4_IRQHandler
+ SECTION .text:CODE:REORDER(1)
+EXTI4_IRQHandler
+ B EXTI4_IRQHandler
+
+ PUBWEAK DMA1_Channel1_IRQHandler
+ SECTION .text:CODE:REORDER(1)
+DMA1_Channel1_IRQHandler
+ B DMA1_Channel1_IRQHandler
+
+ PUBWEAK DMA1_Channel2_IRQHandler
+ SECTION .text:CODE:REORDER(1)
+DMA1_Channel2_IRQHandler
+ B DMA1_Channel2_IRQHandler
+
+ PUBWEAK DMA1_Channel3_IRQHandler
+ SECTION .text:CODE:REORDER(1)
+DMA1_Channel3_IRQHandler
+ B DMA1_Channel3_IRQHandler
+
+ PUBWEAK DMA1_Channel4_IRQHandler
+ SECTION .text:CODE:REORDER(1)
+DMA1_Channel4_IRQHandler
+ B DMA1_Channel4_IRQHandler
+
+ PUBWEAK DMA1_Channel5_IRQHandler
+ SECTION .text:CODE:REORDER(1)
+DMA1_Channel5_IRQHandler
+ B DMA1_Channel5_IRQHandler
+
+ PUBWEAK DMA1_Channel6_IRQHandler
+ SECTION .text:CODE:REORDER(1)
+DMA1_Channel6_IRQHandler
+ B DMA1_Channel6_IRQHandler
+
+ PUBWEAK DMA1_Channel7_IRQHandler
+ SECTION .text:CODE:REORDER(1)
+DMA1_Channel7_IRQHandler
+ B DMA1_Channel7_IRQHandler
+
+ PUBWEAK ADC1_2_IRQHandler
+ SECTION .text:CODE:REORDER(1)
+ADC1_2_IRQHandler
+ B ADC1_2_IRQHandler
+
+ PUBWEAK USB_HP_CAN1_TX_IRQHandler
+ SECTION .text:CODE:REORDER(1)
+USB_HP_CAN1_TX_IRQHandler
+ B USB_HP_CAN1_TX_IRQHandler
+
+ PUBWEAK USB_LP_CAN1_RX0_IRQHandler
+ SECTION .text:CODE:REORDER(1)
+USB_LP_CAN1_RX0_IRQHandler
+ B USB_LP_CAN1_RX0_IRQHandler
+
+ PUBWEAK CAN1_RX1_IRQHandler
+ SECTION .text:CODE:REORDER(1)
+CAN1_RX1_IRQHandler
+ B CAN1_RX1_IRQHandler
+
+ PUBWEAK CAN1_SCE_IRQHandler
+ SECTION .text:CODE:REORDER(1)
+CAN1_SCE_IRQHandler
+ B CAN1_SCE_IRQHandler
+
+ PUBWEAK EXTI9_5_IRQHandler
+ SECTION .text:CODE:REORDER(1)
+EXTI9_5_IRQHandler
+ B EXTI9_5_IRQHandler
+
+ PUBWEAK TIM1_BRK_TIM15_IRQHandler
+ SECTION .text:CODE:REORDER(1)
+TIM1_BRK_TIM15_IRQHandler
+ B TIM1_BRK_TIM15_IRQHandler
+
+ PUBWEAK TIM1_UP_TIM16_IRQHandler
+ SECTION .text:CODE:REORDER(1)
+TIM1_UP_TIM16_IRQHandler
+ B TIM1_UP_TIM16_IRQHandler
+
+ PUBWEAK TIM1_TRG_COM_TIM17_IRQHandler
+ SECTION .text:CODE:REORDER(1)
+TIM1_TRG_COM_TIM17_IRQHandler
+ B TIM1_TRG_COM_TIM17_IRQHandler
+
+ PUBWEAK TIM1_CC_IRQHandler
+ SECTION .text:CODE:REORDER(1)
+TIM1_CC_IRQHandler
+ B TIM1_CC_IRQHandler
+
+ PUBWEAK TIM2_IRQHandler
+ SECTION .text:CODE:REORDER(1)
+TIM2_IRQHandler
+ B TIM2_IRQHandler
+
+ PUBWEAK TIM3_IRQHandler
+ SECTION .text:CODE:REORDER(1)
+TIM3_IRQHandler
+ B TIM3_IRQHandler
+
+ PUBWEAK TIM4_IRQHandler
+ SECTION .text:CODE:REORDER(1)
+TIM4_IRQHandler
+ B TIM4_IRQHandler
+
+ PUBWEAK I2C1_EV_IRQHandler
+ SECTION .text:CODE:REORDER(1)
+I2C1_EV_IRQHandler
+ B I2C1_EV_IRQHandler
+
+ PUBWEAK I2C1_ER_IRQHandler
+ SECTION .text:CODE:REORDER(1)
+I2C1_ER_IRQHandler
+ B I2C1_ER_IRQHandler
+
+ PUBWEAK I2C2_EV_IRQHandler
+ SECTION .text:CODE:REORDER(1)
+I2C2_EV_IRQHandler
+ B I2C2_EV_IRQHandler
+
+ PUBWEAK I2C2_ER_IRQHandler
+ SECTION .text:CODE:REORDER(1)
+I2C2_ER_IRQHandler
+ B I2C2_ER_IRQHandler
+
+ PUBWEAK SPI1_IRQHandler
+ SECTION .text:CODE:REORDER(1)
+SPI1_IRQHandler
+ B SPI1_IRQHandler
+
+ PUBWEAK SPI2_IRQHandler
+ SECTION .text:CODE:REORDER(1)
+SPI2_IRQHandler
+ B SPI2_IRQHandler
+
+ PUBWEAK USART1_IRQHandler
+ SECTION .text:CODE:REORDER(1)
+USART1_IRQHandler
+ B USART1_IRQHandler
+
+ PUBWEAK USART2_IRQHandler
+ SECTION .text:CODE:REORDER(1)
+USART2_IRQHandler
+ B USART2_IRQHandler
+
+ PUBWEAK USART3_IRQHandler
+ SECTION .text:CODE:REORDER(1)
+USART3_IRQHandler
+ B USART3_IRQHandler
+
+ PUBWEAK EXTI15_10_IRQHandler
+ SECTION .text:CODE:REORDER(1)
+EXTI15_10_IRQHandler
+ B EXTI15_10_IRQHandler
+
+ PUBWEAK RTC_Alarm_IRQHandler
+ SECTION .text:CODE:REORDER(1)
+RTC_Alarm_IRQHandler
+ B RTC_Alarm_IRQHandler
+
+ PUBWEAK USBWakeUp_IRQHandler
+ SECTION .text:CODE:REORDER(1)
+USBWakeUp_IRQHandler
+ B USBWakeUp_IRQHandler
+
+ PUBWEAK TIM8_BRK_IRQHandler
+ SECTION .text:CODE:REORDER(1)
+TIM8_BRK_IRQHandler
+ B TIM8_BRK_IRQHandler
+
+ PUBWEAK TIM8_UP_IRQHandler
+ SECTION .text:CODE:REORDER(1)
+TIM8_UP_IRQHandler
+ B TIM8_UP_IRQHandler
+
+ PUBWEAK TIM8_TRG_COM_IRQHandler
+ SECTION .text:CODE:REORDER(1)
+TIM8_TRG_COM_IRQHandler
+ B TIM8_TRG_COM_IRQHandler
+
+ PUBWEAK TIM8_CC_IRQHandler
+ SECTION .text:CODE:REORDER(1)
+TIM8_CC_IRQHandler
+ B TIM8_CC_IRQHandler
+
+ PUBWEAK ADC3_IRQHandler
+ SECTION .text:CODE:REORDER(1)
+ADC3_IRQHandler
+ B ADC3_IRQHandler
+
+ PUBWEAK SPI3_IRQHandler
+ SECTION .text:CODE:REORDER(1)
+SPI3_IRQHandler
+ B SPI3_IRQHandler
+
+ PUBWEAK UART4_IRQHandler
+ SECTION .text:CODE:REORDER(1)
+UART4_IRQHandler
+ B UART4_IRQHandler
+
+ PUBWEAK UART5_IRQHandler
+ SECTION .text:CODE:REORDER(1)
+UART5_IRQHandler
+ B UART5_IRQHandler
+
+ PUBWEAK TIM6_DAC_IRQHandler
+ SECTION .text:CODE:REORDER(1)
+TIM6_DAC_IRQHandler
+ B TIM6_DAC_IRQHandler
+
+ PUBWEAK TIM7_IRQHandler
+ SECTION .text:CODE:REORDER(1)
+TIM7_IRQHandler
+ B TIM7_IRQHandler
+
+ PUBWEAK DMA2_Channel1_IRQHandler
+ SECTION .text:CODE:REORDER(1)
+DMA2_Channel1_IRQHandler
+ B DMA2_Channel1_IRQHandler
+
+ PUBWEAK DMA2_Channel2_IRQHandler
+ SECTION .text:CODE:REORDER(1)
+DMA2_Channel2_IRQHandler
+ B DMA2_Channel2_IRQHandler
+
+ PUBWEAK DMA2_Channel3_IRQHandler
+ SECTION .text:CODE:REORDER(1)
+DMA2_Channel3_IRQHandler
+ B DMA2_Channel3_IRQHandler
+
+ PUBWEAK DMA2_Channel4_IRQHandler
+ SECTION .text:CODE:REORDER(1)
+DMA2_Channel4_IRQHandler
+ B DMA2_Channel4_IRQHandler
+
+ PUBWEAK DMA2_Channel5_IRQHandler
+ SECTION .text:CODE:REORDER(1)
+DMA2_Channel5_IRQHandler
+ B DMA2_Channel5_IRQHandler
+
+
+ PUBWEAK ADC4_IRQHandler
+ SECTION .text:CODE:REORDER(1)
+ADC4_IRQHandler
+ B ADC4_IRQHandler
+
+ PUBWEAK COMP1_2_3_IRQHandler
+ SECTION .text:CODE:REORDER(1)
+COMP1_2_3_IRQHandler
+ B COMP1_2_3_IRQHandler
+
+ PUBWEAK COMP4_5_6_IRQHandler
+ SECTION .text:CODE:REORDER(1)
+COMP4_5_6_IRQHandler
+ B COMP4_5_6_IRQHandler
+
+ PUBWEAK COMP7_IRQHandler
+ SECTION .text:CODE:REORDER(1)
+COMP7_IRQHandler
+ B COMP7_IRQHandler
+
+ PUBWEAK USB_HP_IRQHandler
+ SECTION .text:CODE:REORDER(1)
+USB_HP_IRQHandler
+ B USB_HP_IRQHandler
+
+ PUBWEAK USB_LP_IRQHandler
+ SECTION .text:CODE:REORDER(1)
+USB_LP_IRQHandler
+ B USB_LP_IRQHandler
+
+ PUBWEAK USBWakeUp_RMP_IRQHandler
+ SECTION .text:CODE:REORDER(1)
+USBWakeUp_RMP_IRQHandler
+ B USBWakeUp_RMP_IRQHandler
+
+ PUBWEAK FPU_IRQHandler
+ SECTION .text:CODE:REORDER(1)
+FPU_IRQHandler
+ B FPU_IRQHandler
+
+ END
+/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
diff --git a/Libraries/CMSIS/Device/ST/STM32F30x/Source/Templates/system_stm32f30x.c b/Libraries/CMSIS/Device/ST/STM32F30x/Source/Templates/system_stm32f30x.c
new file mode 100644
index 0000000..831bd65
--- /dev/null
+++ b/Libraries/CMSIS/Device/ST/STM32F30x/Source/Templates/system_stm32f30x.c
@@ -0,0 +1,382 @@
+/**
+ ******************************************************************************
+ * @file system_stm32f30x.c
+ * @author MCD Application Team
+ * @version V1.0.0
+ * @date 04-September-2012
+ * @brief CMSIS Cortex-M4 Device Peripheral Access Layer System Source File.
+ * This file contains the system clock configuration for STM32F30x devices,
+ * and is generated by the clock configuration tool
+ * stm32f30x_Clock_Configuration_V1.0.0.xls
+ *
+ * 1. This file provides two functions and one global variable to be called from
+ * user application:
+ * - SystemInit(): Setups the system clock (System clock source, PLL Multiplier
+ * and Divider factors, AHB/APBx prescalers and Flash settings),
+ * depending on the configuration made in the clock xls tool.
+ * This function is called at startup just after reset and
+ * before branch to main program. This call is made inside
+ * the "startup_stm32f30x.s" file.
+ *
+ * - SystemCoreClock variable: Contains the core clock (HCLK), it can be used
+ * by the user application to setup the SysTick
+ * timer or configure other parameters.
+ *
+ * - SystemCoreClockUpdate(): Updates the variable SystemCoreClock and must
+ * be called whenever the core clock is changed
+ * during program execution.
+ *
+ * 2. After each device reset the HSI (8 MHz) is used as system clock source.
+ * Then SystemInit() function is called, in "startup_stm32f30x.s" file, to
+ * configure the system clock before to branch to main program.
+ *
+ * 3. If the system clock source selected by user fails to startup, the SystemInit()
+ * function will do nothing and HSI still used as system clock source. User can
+ * add some code to deal with this issue inside the SetSysClock() function.
+ *
+ * 4. The default value of HSE crystal is set to 8MHz, refer to "HSE_VALUE" define
+ * in "stm32f30x.h" file. When HSE is used as system clock source, directly or
+ * through PLL, and you are using different crystal you have to adapt the HSE
+ * value to your own configuration.
+ *
+ * 5. This file configures the system clock as follows:
+ *=============================================================================
+ * Supported STM32F30x device
+ *-----------------------------------------------------------------------------
+ * System Clock source | PLL (HSE)
+ *-----------------------------------------------------------------------------
+ * SYSCLK(Hz) | 72000000
+ *-----------------------------------------------------------------------------
+ * HCLK(Hz) | 72000000
+ *-----------------------------------------------------------------------------
+ * AHB Prescaler | 1
+ *-----------------------------------------------------------------------------
+ * APB2 Prescaler | 1
+ *-----------------------------------------------------------------------------
+ * APB1 Prescaler | 2
+ *-----------------------------------------------------------------------------
+ * HSE Frequency(Hz) | 8000000
+ *----------------------------------------------------------------------------
+ * PLLMUL | 9
+ *-----------------------------------------------------------------------------
+ * PREDIV | 1
+ *-----------------------------------------------------------------------------
+ * USB Clock | DISABLE
+ *-----------------------------------------------------------------------------
+ * Flash Latency(WS) | 2
+ *-----------------------------------------------------------------------------
+ * Prefetch Buffer | ON
+ *-----------------------------------------------------------------------------
+ *=============================================================================
+ ******************************************************************************
+ * @attention
+ *
+ * © COPYRIGHT 2012 STMicroelectronics
+ *
+ * Licensed under MCD-ST Liberty SW License Agreement V2, (the "License");
+ * You may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at:
+ *
+ * http://www.st.com/software_license_agreement_liberty_v2
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ *
+ ******************************************************************************
+ */
+/** @addtogroup CMSIS
+ * @{
+ */
+
+/** @addtogroup stm32f30x_system
+ * @{
+ */
+
+/** @addtogroup STM32F30x_System_Private_Includes
+ * @{
+ */
+
+#include "stm32f30x.h"
+
+/**
+ * @}
+ */
+
+/** @addtogroup STM32F30x_System_Private_TypesDefinitions
+ * @{
+ */
+
+/**
+ * @}
+ */
+
+/** @addtogroup STM32F30x_System_Private_Defines
+ * @{
+ */
+/*!< Uncomment the following line if you need to relocate your vector Table in
+ Internal SRAM. */
+/* #define VECT_TAB_SRAM */
+#define VECT_TAB_OFFSET 0x0 /*!< Vector Table base offset field.
+ This value must be a multiple of 0x200. */
+/**
+ * @}
+ */
+
+/** @addtogroup STM32F30x_System_Private_Macros
+ * @{
+ */
+
+/**
+ * @}
+ */
+
+/** @addtogroup STM32F30x_System_Private_Variables
+ * @{
+ */
+
+ uint32_t SystemCoreClock = 72000000;
+
+ __I uint8_t AHBPrescTable[16] = {0, 0, 0, 0, 0, 0, 0, 0, 1, 2, 3, 4, 6, 7, 8, 9};
+
+/**
+ * @}
+ */
+
+/** @addtogroup STM32F30x_System_Private_FunctionPrototypes
+ * @{
+ */
+
+static void SetSysClock(void);
+
+/**
+ * @}
+ */
+
+/** @addtogroup STM32F30x_System_Private_Functions
+ * @{
+ */
+
+/**
+ * @brief Setup the microcontroller system
+ * Initialize the Embedded Flash Interface, the PLL and update the
+ * SystemFrequency variable.
+ * @param None
+ * @retval None
+ */
+void SystemInit(void)
+{
+ /* FPU settings ------------------------------------------------------------*/
+ #if (__FPU_PRESENT == 1) && (__FPU_USED == 1)
+ SCB->CPACR |= ((3UL << 10*2)|(3UL << 11*2)); /* set CP10 and CP11 Full Access */
+ #endif
+
+ /* Reset the RCC clock configuration to the default reset state ------------*/
+ /* Set HSION bit */
+ RCC->CR |= (uint32_t)0x00000001;
+
+ /* Reset CFGR register */
+ RCC->CFGR &= 0xF87FC00C;
+
+ /* Reset HSEON, CSSON and PLLON bits */
+ RCC->CR &= (uint32_t)0xFEF6FFFF;
+
+ /* Reset HSEBYP bit */
+ RCC->CR &= (uint32_t)0xFFFBFFFF;
+
+ /* Reset PLLSRC, PLLXTPRE, PLLMUL and USBPRE bits */
+ RCC->CFGR &= (uint32_t)0xFF80FFFF;
+
+ /* Reset PREDIV1[3:0] bits */
+ RCC->CFGR2 &= (uint32_t)0xFFFFFFF0;
+
+ /* Reset USARTSW[1:0], I2CSW and TIMs bits */
+ RCC->CFGR3 &= (uint32_t)0xFF00FCCC;
+
+ /* Disable all interrupts */
+ RCC->CIR = 0x00000000;
+
+ /* Configure the System clock source, PLL Multiplier and Divider factors,
+ AHB/APBx prescalers and Flash settings ----------------------------------*/
+ SetSysClock();
+
+#ifdef VECT_TAB_SRAM
+ SCB->VTOR = SRAM_BASE | VECT_TAB_OFFSET; /* Vector Table Relocation in Internal SRAM. */
+#else
+ SCB->VTOR = FLASH_BASE | VECT_TAB_OFFSET; /* Vector Table Relocation in Internal FLASH. */
+#endif
+}
+
+/**
+ * @brief Update SystemCoreClock variable according to Clock Register Values.
+ * The SystemCoreClock variable contains the core clock (HCLK), it can
+ * be used by the user application to setup the SysTick timer or configure
+ * other parameters.
+ *
+ * @note Each time the core clock (HCLK) changes, this function must be called
+ * to update SystemCoreClock variable value. Otherwise, any configuration
+ * based on this variable will be incorrect.
+ *
+ * @note - The system frequency computed by this function is not the real
+ * frequency in the chip. It is calculated based on the predefined
+ * constant and the selected clock source:
+ *
+ * - If SYSCLK source is HSI, SystemCoreClock will contain the HSI_VALUE(*)
+ *
+ * - If SYSCLK source is HSE, SystemCoreClock will contain the HSE_VALUE(**)
+ *
+ * - If SYSCLK source is PLL, SystemCoreClock will contain the HSE_VALUE(**)
+ * or HSI_VALUE(*) multiplied/divided by the PLL factors.
+ *
+ * (*) HSI_VALUE is a constant defined in stm32f30x.h file (default value
+ * 8 MHz) but the real value may vary depending on the variations
+ * in voltage and temperature.
+ *
+ * (**) HSE_VALUE is a constant defined in stm32f30x.h file (default value
+ * 8 MHz), user has to ensure that HSE_VALUE is same as the real
+ * frequency of the crystal used. Otherwise, this function may
+ * have wrong result.
+ *
+ * - The result of this function could be not correct when using fractional
+ * value for HSE crystal.
+ *
+ * @param None
+ * @retval None
+ */
+void SystemCoreClockUpdate (void)
+{
+ uint32_t tmp = 0, pllmull = 0, pllsource = 0, prediv1factor = 0;
+
+ /* Get SYSCLK source -------------------------------------------------------*/
+ tmp = RCC->CFGR & RCC_CFGR_SWS;
+
+ switch (tmp)
+ {
+ case 0x00: /* HSI used as system clock */
+ SystemCoreClock = HSI_VALUE;
+ break;
+ case 0x04: /* HSE used as system clock */
+ SystemCoreClock = HSE_VALUE;
+ break;
+ case 0x08: /* PLL used as system clock */
+ /* Get PLL clock source and multiplication factor ----------------------*/
+ pllmull = RCC->CFGR & RCC_CFGR_PLLMULL;
+ pllsource = RCC->CFGR & RCC_CFGR_PLLSRC;
+ pllmull = ( pllmull >> 18) + 2;
+
+ if (pllsource == 0x00)
+ {
+ /* HSI oscillator clock divided by 2 selected as PLL clock entry */
+ SystemCoreClock = (HSI_VALUE >> 1) * pllmull;
+ }
+ else
+ {
+ prediv1factor = (RCC->CFGR2 & RCC_CFGR2_PREDIV1) + 1;
+ /* HSE oscillator clock selected as PREDIV1 clock entry */
+ SystemCoreClock = (HSE_VALUE / prediv1factor) * pllmull;
+ }
+ break;
+ default: /* HSI used as system clock */
+ SystemCoreClock = HSI_VALUE;
+ break;
+ }
+ /* Compute HCLK clock frequency ----------------*/
+ /* Get HCLK prescaler */
+ tmp = AHBPrescTable[((RCC->CFGR & RCC_CFGR_HPRE) >> 4)];
+ /* HCLK clock frequency */
+ SystemCoreClock >>= tmp;
+}
+
+/**
+ * @brief Configures the System clock source, PLL Multiplier and Divider factors,
+ * AHB/APBx prescalers and Flash settings
+ * @note This function should be called only once the RCC clock configuration
+ * is reset to the default reset state (done in SystemInit() function).
+ * @param None
+ * @retval None
+ */
+static void SetSysClock(void)
+{
+ __IO uint32_t StartUpCounter = 0, HSEStatus = 0;
+
+/******************************************************************************/
+/* PLL (clocked by HSE) used as System clock source */
+/******************************************************************************/
+
+ /* SYSCLK, HCLK, PCLK2 and PCLK1 configuration -----------*/
+ /* Enable HSE */
+ RCC->CR |= ((uint32_t)RCC_CR_HSEON);
+
+ /* Wait till HSE is ready and if Time out is reached exit */
+ do
+ {
+ HSEStatus = RCC->CR & RCC_CR_HSERDY;
+ StartUpCounter++;
+ } while((HSEStatus == 0) && (StartUpCounter != HSE_STARTUP_TIMEOUT));
+
+ if ((RCC->CR & RCC_CR_HSERDY) != RESET)
+ {
+ HSEStatus = (uint32_t)0x01;
+ }
+ else
+ {
+ HSEStatus = (uint32_t)0x00;
+ }
+
+ if (HSEStatus == (uint32_t)0x01)
+ {
+ /* Enable Prefetch Buffer and set Flash Latency */
+ FLASH->ACR = FLASH_ACR_PRFTBE | (uint32_t)FLASH_ACR_LATENCY_1;
+
+ /* HCLK = SYSCLK / 1 */
+ RCC->CFGR |= (uint32_t)RCC_CFGR_HPRE_DIV1;
+
+ /* PCLK2 = HCLK / 1 */
+ RCC->CFGR |= (uint32_t)RCC_CFGR_PPRE2_DIV1;
+
+ /* PCLK1 = HCLK / 2 */
+ RCC->CFGR |= (uint32_t)RCC_CFGR_PPRE1_DIV2;
+
+ /* PLL configuration */
+ RCC->CFGR &= (uint32_t)((uint32_t)~(RCC_CFGR_PLLSRC | RCC_CFGR_PLLXTPRE | RCC_CFGR_PLLMULL));
+ RCC->CFGR |= (uint32_t)(RCC_CFGR_PLLSRC_PREDIV1 | RCC_CFGR_PLLXTPRE_PREDIV1 | RCC_CFGR_PLLMULL9);
+
+ /* Enable PLL */
+ RCC->CR |= RCC_CR_PLLON;
+
+ /* Wait till PLL is ready */
+ while((RCC->CR & RCC_CR_PLLRDY) == 0)
+ {
+ }
+
+ /* Select PLL as system clock source */
+ RCC->CFGR &= (uint32_t)((uint32_t)~(RCC_CFGR_SW));
+ RCC->CFGR |= (uint32_t)RCC_CFGR_SW_PLL;
+
+ /* Wait till PLL is used as system clock source */
+ while ((RCC->CFGR & (uint32_t)RCC_CFGR_SWS) != (uint32_t)RCC_CFGR_SWS_PLL)
+ {
+ }
+ }
+ else
+ { /* If HSE fails to start-up, the application will have wrong clock
+ configuration. User can add here some code to deal with this error */
+ }
+}
+
+/**
+ * @}
+ */
+
+/**
+ * @}
+ */
+
+/**
+ * @}
+ */
+
+/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
+
diff --git a/Libraries/CMSIS/Device/ST/STM32F37x/Include/stm32f37x.h b/Libraries/CMSIS/Device/ST/STM32F37x/Include/stm32f37x.h
new file mode 100644
index 0000000..9cbd5ae
--- /dev/null
+++ b/Libraries/CMSIS/Device/ST/STM32F37x/Include/stm32f37x.h
@@ -0,0 +1,5438 @@
+/**
+ ******************************************************************************
+ * @file stm32f37x.h
+ * @author MCD Application Team
+ * @version V1.0.0
+ * @date 20-September-2012
+ * @brief CMSIS Cortex-M4 Device Peripheral Access Layer Header File.
+ * This file contains all the peripheral registers definitions, bits
+ * definitions and memory mapping for STM32F37x devices.
+ *
+ * The file is the unique include file that the application programmer
+ * is using in the C source code, usually in main.c. This file contains:
+ * - Configuration section that allows to select:
+ * - The device used in the target application
+ * - To use or not the peripherals drivers in application code(i.e.
+ * code will be based on direct access to peripherals registers
+ * rather than drivers API), this option is controlled by
+ * "#define USE_STDPERIPH_DRIVER"
+ * - To change few application-specific parameters such as the HSE
+ * crystal frequency
+ * - Data structures and the address mapping for all peripherals
+ * - Peripheral registers declarations and bits definition
+ * - Macros to access peripheral registers hardware
+ *
+ ******************************************************************************
+ * @attention
+ *
+ * THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS
+ * WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE
+ * TIME. AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY
+ * DIRECT, INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING
+ * FROM THE CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE
+ * CODING INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS.
+ *
+ * FOR MORE INFORMATION PLEASE READ CAREFULLY THE LICENSE AGREEMENT FILE
+ * LOCATED IN THE ROOT DIRECTORY OF THIS FIRMWARE PACKAGE.
+ *
+ * © COPYRIGHT 2012 STMicroelectronics
+ ******************************************************************************
+ */
+
+/** @addtogroup CMSIS
+ * @{
+ */
+
+/** @addtogroup stm32f37x
+ * @{
+ */
+
+#ifndef __STM32F37x_H
+#define __STM32F37x_H
+
+#ifdef __cplusplus
+ extern "C" {
+#endif /* __cplusplus */
+
+/** @addtogroup Library_configuration_section
+ * @{
+ */
+
+/* Uncomment the line below according to the target STM32 device used in your
+ application
+ */
+
+#if !defined (STM32F37X)
+ #define STM32F37X
+#endif
+
+/* Tip: To avoid modifying this file each time you need to switch between these
+ devices, you can define the device in your toolchain compiler preprocessor.
+ */
+
+#if !defined (STM32F37X)
+ #error "Please select first the target STM32F37X device used in your application (in stm32f37x.h file)"
+#endif
+
+#if !defined (USE_STDPERIPH_DRIVER)
+/**
+ * @brief Comment the line below if you will not use the peripherals drivers.
+ In this case, these drivers will not be included and the application code will
+ be based on direct access to peripherals registers
+ */
+ /*#define USE_STDPERIPH_DRIVER*/
+#endif /* USE_STDPERIPH_DRIVER */
+
+/**
+ * @brief In the following line adjust the value of External High Speed oscillator (HSE)
+ used in your application
+
+ Tip: To avoid modifying this file each time you need to use different HSE, you
+ can define the HSE value in your toolchain compiler preprocessor.
+ */
+#if !defined (HSE_VALUE)
+ #define HSE_VALUE ((uint32_t)8000000) /*!< Value of the External oscillator in Hz */
+#endif /* HSE_VALUE */
+/**
+ * @brief In the following line adjust the External High Speed oscillator (HSE) Startup
+ Timeout value
+ */
+#if !defined (HSE_STARTUP_TIMEOUT)
+ #define HSE_STARTUP_TIMEOUT ((uint16_t)0x0500) /*!< Time out for HSE start up */
+#endif /* HSE_STARTUP_TIMEOUT */
+/**
+ * @brief In the following line adjust the Internal High Speed oscillator (HSI) Startup
+ Timeout value
+ */
+#define HSI_STARTUP_TIMEOUT ((uint16_t)0x0500) /*!< Time out for HSI start up */
+
+#if !defined (HSI_VALUE)
+ #define HSI_VALUE ((uint32_t)8000000)
+#endif /* HSI_VALUE */ /*!< Value of the Internal High Speed oscillator in Hz.
+ The real value may vary depending on the variations
+ in voltage and temperature. */
+#if !defined (LSI_VALUE)
+ #define LSI_VALUE ((uint32_t)40000)
+#endif /* LSI_VALUE */ /*!< Value of the Internal Low Speed oscillator in Hz
+ The real value may vary depending on the variations
+ in voltage and temperature. */
+#if !defined (LSE_VALUE)
+ #define LSE_VALUE ((uint32_t)32768) /*!< Value of the External Low Speed oscillator in Hz */
+#endif /* LSE_VALUE */
+
+/**
+ * @brief STM32F37x Standard Peripherals Library version number V1.0.0
+ */
+#define __STM32F37X_STDPERIPH_VERSION_MAIN (0x01) /*!< [31:24] main version */
+#define __STM32F37X_STDPERIPH_VERSION_SUB1 (0x00) /*!< [23:16] sub1 version */
+#define __STM32F37X_STDPERIPH_VERSION_SUB2 (0x00) /*!< [15:8] sub2 version */
+#define __STM32F37X_STDPERIPH_VERSION_RC (0x00) /*!< [7:0] release candidate */
+#define __STM32F37X_STDPERIPH_VERSION ( (__STM32F37X_STDPERIPH_VERSION_MAIN << 24)\
+ |(__STM32F37X_STDPERIPH_VERSION_SUB1 << 16)\
+ |(__STM32F37X_STDPERIPH_VERSION_SUB2 << 8)\
+ |(__STM32F37X_STDPERIPH_VERSION_RC))
+
+/**
+ * @}
+ */
+
+/** @addtogroup Configuration_section_for_CMSIS
+ * @{
+ */
+
+/**
+ * @brief Configuration of the Cortex-M4 Processor and Core Peripherals
+ */
+#define __CM4_REV 0x0001 /*!< Core revision r0p1 */
+#define __MPU_PRESENT 1 /*!< STM32F37X provide an MPU */
+#define __NVIC_PRIO_BITS 4 /*!< STM32F37X uses 4 Bits for the Priority Levels */
+#define __Vendor_SysTickConfig 0 /*!< Set to 1 if different SysTick Config is used */
+#define __FPU_PRESENT 1 /*!< STM32F37X provide an FPU */
+
+
+/**
+ * @brief STM32F37X Interrupt Number Definition, according to the selected device
+ * in @ref Library_configuration_section
+ */
+typedef enum IRQn
+{
+/****** Cortex-M4 Processor Exceptions Numbers ****************************************************************/
+ NonMaskableInt_IRQn = -14, /*!< 2 Non Maskable Interrupt */
+ MemoryManagement_IRQn = -12, /*!< 4 Cortex-M4 Memory Management Interrupt */
+ BusFault_IRQn = -11, /*!< 5 Cortex-M4 Bus Fault Interrupt */
+ UsageFault_IRQn = -10, /*!< 6 Cortex-M4 Usage Fault Interrupt */
+ SVCall_IRQn = -5, /*!< 11 Cortex-M4 SV Call Interrupt */
+ DebugMonitor_IRQn = -4, /*!< 12 Cortex-M4 Debug Monitor Interrupt */
+ PendSV_IRQn = -2, /*!< 14 Cortex-M4 Pend SV Interrupt */
+ SysTick_IRQn = -1, /*!< 15 Cortex-M4 System Tick Interrupt */
+/****** STM32 specific Interrupt Numbers **********************************************************************/
+ WWDG_IRQn = 0, /*!< Window WatchDog Interrupt */
+ PVD_IRQn = 1, /*!< PVD through EXTI Line detection Interrupt */
+ TAMPER_STAMP_IRQn = 2, /*!< Tamper and TimeStamp interrupts through the EXTI line 19 */
+ RTC_WKUP_IRQn = 3, /*!< RTC Wakeup interrupt through the EXTI line 20 */
+ FLASH_IRQn = 4, /*!< FLASH global Interrupt */
+ RCC_IRQn = 5, /*!< RCC global Interrupt */
+ EXTI0_IRQn = 6, /*!< EXTI Line0 Interrupt */
+ EXTI1_IRQn = 7, /*!< EXTI Line1 Interrupt */
+ EXTI2_TS_IRQn = 8, /*!< EXTI Line2 Interrupt and Touch Sense Interrupt */
+ EXTI3_IRQn = 9, /*!< EXTI Line3 Interrupt */
+ EXTI4_IRQn = 10, /*!< EXTI Line4 Interrupt */
+ DMA1_Channel1_IRQn = 11, /*!< DMA1 Channel 1 Interrupt */
+ DMA1_Channel2_IRQn = 12, /*!< DMA1 Channel 2 Interrupt */
+ DMA1_Channel3_IRQn = 13, /*!< DMA1 Channel 3 Interrupt */
+ DMA1_Channel4_IRQn = 14, /*!< DMA1 Channel 4 Interrupt */
+ DMA1_Channel5_IRQn = 15, /*!< DMA1 Channel 5 Interrupt */
+ DMA1_Channel6_IRQn = 16, /*!< DMA1 Channel 6 Interrupt */
+ DMA1_Channel7_IRQn = 17, /*!< DMA1 Channel 7 Interrupt */
+ ADC1_IRQn = 18, /*!< ADC1 Interrupts */
+ CAN1_TX_IRQn = 19, /*!< CAN1 TX Interrupt */
+ CAN1_RX0_IRQn = 20, /*!< CAN1 RX0 Interrupt */
+ CAN1_RX1_IRQn = 21, /*!< CAN1 RX1 Interrupt */
+ CAN1_SCE_IRQn = 22, /*!< CAN1 SCE Interrupt */
+ EXTI9_5_IRQn = 23, /*!< External Line[9:5] Interrupts */
+ TIM15_IRQn = 24, /*!< TIM15 global Interrupt */
+ TIM16_IRQn = 25, /*!< TIM16 global Interrupt */
+ TIM17_IRQn = 26, /*!< TIM17 global Interrupt */
+ TIM18_DAC2_IRQn = 27, /*!< TIM18 global Interrupt and DAC2 underrun Interrupt */
+ TIM2_IRQn = 28, /*!< TIM2 global Interrupt */
+ TIM3_IRQn = 29, /*!< TIM3 global Interrupt */
+ TIM4_IRQn = 30, /*!< TIM4 global Interrupt */
+ I2C1_EV_IRQn = 31, /*!< I2C1 Event Interrupt */
+ I2C1_ER_IRQn = 32, /*!< I2C1 Error Interrupt */
+ I2C2_EV_IRQn = 33, /*!< I2C2 Event Interrupt */
+ I2C2_ER_IRQn = 34, /*!< I2C2 Error Interrupt */
+ SPI1_IRQn = 35, /*!< SPI1 global Interrupt */
+ SPI2_IRQn = 36, /*!< SPI2 global Interrupt */
+ USART1_IRQn = 37, /*!< USART1 global Interrupt */
+ USART2_IRQn = 38, /*!< USART2 global Interrupt */
+ USART3_IRQn = 39, /*!< USART3 global Interrupt */
+ EXTI15_10_IRQn = 40, /*!< External Line[15:10] Interrupts */
+ RTC_Alarm_IRQn = 41, /*!< RTC Alarm (A and B) through EXTI Line Interrupt */
+ CEC_IRQn = 42, /*!< CEC Interrupt */
+ TIM12_IRQn = 43, /*!< TIM12 global interrupt */
+ TIM13_IRQn = 44, /*!< TIM13 global interrupt */
+ TIM14_IRQn = 45, /*!< TIM14 global interrupt */
+ TIM5_IRQn = 50, /*!< TIM5 global Interrupt */
+ SPI3_IRQn = 51, /*!< SPI3 global Interrupt */
+ TIM6_DAC1_IRQn = 54, /*!< TIM6 global and DAC1 Cahnnel1 & Cahnnel2 underrun error Interrupts*/
+ TIM7_IRQn = 55, /*!< TIM7 global Interrupt */
+ DMA2_Channel1_IRQn = 56, /*!< DMA2 Channel 1 global Interrupt */
+ DMA2_Channel2_IRQn = 57, /*!< DMA2 Channel 2 global Interrupt */
+ DMA2_Channel3_IRQn = 58, /*!< DMA2 Channel 3 global Interrupt */
+ DMA2_Channel4_IRQn = 59, /*!< DMA2 Channel 4 global Interrupt */
+ DMA2_Channel5_IRQn = 60, /*!< DMA2 Channel 5 global Interrupt */
+ SDADC1_IRQn = 61, /*!< ADC Sigma Delta 1 global Interrupt */
+ SDADC2_IRQn = 62, /*!< ADC Sigma Delta 2 global Interrupt */
+ SDADC3_IRQn = 63, /*!< ADC Sigma Delta 1 global Interrupt */
+ COMP_IRQn = 64, /*!< COMP1 and COMP2 global Interrupt */
+ USB_HP_IRQn = 74, /*!< USB High Priority global Interrupt */
+ USB_LP_IRQn = 75, /*!< USB Low Priority global Interrupt */
+ USBWakeUp_IRQn = 76, /*!< USB Wakeup Interrupt */
+ TIM19_IRQn = 78, /*!< TIM19 global Interrupt */
+ FPU_IRQn = 81 /*!< Floating point Interrupt */
+} IRQn_Type;
+
+/**
+ * @}
+ */
+
+#include "core_cm4.h" /* Cortex-M4 processor and core peripherals */
+#include "system_stm32f37x.h" /* STM32F37x System Header */
+#include
+
+
\ No newline at end of file
diff --git a/Libraries/CMSIS/Device/ST/STM32F37x/Source/Templates/TrueSTUDIO/startup_stm32f37x.s b/Libraries/CMSIS/Device/ST/STM32F37x/Source/Templates/TrueSTUDIO/startup_stm32f37x.s
new file mode 100644
index 0000000..30da828
--- /dev/null
+++ b/Libraries/CMSIS/Device/ST/STM32F37x/Source/Templates/TrueSTUDIO/startup_stm32f37x.s
@@ -0,0 +1,463 @@
+/**
+ ******************************************************************************
+ * @file startup_stm32f37x.s
+ * @author MCD Application Team
+ * @version V1.0.0
+ * @date 20-September-2012
+ * @brief stm32f37x vector table for Atollic TrueSTUDIO toolchain.
+ * This module performs:
+ * - Set the initial SP
+ * - Set the initial PC == Reset_Handler,
+ * - Set the vector table entries with the exceptions ISR address,
+ * - Configure the clock system
+ * - Branches to main in the C library (which eventually
+ * calls main()).
+ * After Reset the Cortex-M4 processor is in Thread mode,
+ * priority is Privileged, and the Stack is set to Main.
+ ******************************************************************************
+ * @attention
+ *
+ *
+
+
+
+
+
+
+
+
|
+
© COPYRIGHT 2012 STMicroelectronics
+ *
+ * Licensed under MCD-ST Liberty SW License Agreement V2, (the "License");
+ * You may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at:
+ *
+ * http://www.st.com/software_license_agreement_liberty_v2
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ *
+ ******************************************************************************
+ */
+
+ .syntax unified
+ .cpu cortex-m4
+ .fpu softvfp
+ .thumb
+
+.global g_pfnVectors
+.global Default_Handler
+
+/* start address for the initialization values of the .data section.
+defined in linker script */
+.word _sidata
+/* start address for the .data section. defined in linker script */
+.word _sdata
+/* end address for the .data section. defined in linker script */
+.word _edata
+/* start address for the .bss section. defined in linker script */
+.word _sbss
+/* end address for the .bss section. defined in linker script */
+.word _ebss
+
+.equ BootRAM, 0xF1E0F85F
+/**
+ * @brief This is the code that gets called when the processor first
+ * starts execution following a reset event. Only the absolutely
+ * necessary set is performed, after which the application
+ * supplied main() routine is called.
+ * @param None
+ * @retval : None
+*/
+
+ .section .text.Reset_Handler
+ .weak Reset_Handler
+ .type Reset_Handler, %function
+Reset_Handler:
+
+/* Copy the data segment initializers from flash to SRAM */
+ movs r1, #0
+ b LoopCopyDataInit
+
+CopyDataInit:
+ ldr r3, =_sidata
+ ldr r3, [r3, r1]
+ str r3, [r0, r1]
+ adds r1, r1, #4
+
+LoopCopyDataInit:
+ ldr r0, =_sdata
+ ldr r3, =_edata
+ adds r2, r0, r1
+ cmp r2, r3
+ bcc CopyDataInit
+ ldr r2, =_sbss
+ b LoopFillZerobss
+/* Zero fill the bss segment. */
+FillZerobss:
+ movs r3, #0
+ str r3, [r2], #4
+
+LoopFillZerobss:
+ ldr r3, = _ebss
+ cmp r2, r3
+ bcc FillZerobss
+
+/* Call the clock system intitialization function.*/
+ bl SystemInit
+/* Call static constructors */
+ bl __libc_init_array
+/* Call the application's entry point.*/
+ bl main
+
+LoopForever:
+ b LoopForever
+
+.size Reset_Handler, .-Reset_Handler
+
+/**
+ * @brief This is the code that gets called when the processor receives an
+ * unexpected interrupt. This simply enters an infinite loop, preserving
+ * the system state for examination by a debugger.
+ *
+ * @param None
+ * @retval : None
+*/
+ .section .text.Default_Handler,"ax",%progbits
+Default_Handler:
+Infinite_Loop:
+ b Infinite_Loop
+ .size Default_Handler, .-Default_Handler
+/******************************************************************************
+*
+* The minimal vector table for a Cortex-M4. Note that the proper constructs
+* must be placed on this to ensure that it ends up at physical address
+* 0x0000.0000.
+*
+******************************************************************************/
+ .section .isr_vector,"a",%progbits
+ .type g_pfnVectors, %object
+ .size g_pfnVectors, .-g_pfnVectors
+
+
+g_pfnVectors:
+ .word _estack
+ .word Reset_Handler
+ .word NMI_Handler
+ .word HardFault_Handler
+ .word MemManage_Handler
+ .word BusFault_Handler
+ .word UsageFault_Handler
+ .word 0
+ .word 0
+ .word 0
+ .word 0
+ .word SVC_Handler
+ .word DebugMon_Handler
+ .word 0
+ .word PendSV_Handler
+ .word SysTick_Handler
+ .word WWDG_IRQHandler
+ .word PVD_IRQHandler
+ .word TAMPER_STAMP_IRQHandler
+ .word RTC_WKUP_IRQHandler
+ .word FLASH_IRQHandler
+ .word RCC_IRQHandler
+ .word EXTI0_IRQHandler
+ .word EXTI1_IRQHandler
+ .word EXTI2_TS_IRQHandler
+ .word EXTI3_IRQHandler
+ .word EXTI4_IRQHandler
+ .word DMA1_Channel1_IRQHandler
+ .word DMA1_Channel2_IRQHandler
+ .word DMA1_Channel3_IRQHandler
+ .word DMA1_Channel4_IRQHandler
+ .word DMA1_Channel5_IRQHandler
+ .word DMA1_Channel6_IRQHandler
+ .word DMA1_Channel7_IRQHandler
+ .word ADC1_IRQHandler
+ .word CAN1_TX_IRQHandler
+ .word CAN1_RX0_IRQHandler
+ .word CAN1_RX1_IRQHandler
+ .word CAN1_SCE_IRQHandler
+ .word EXTI9_5_IRQHandler
+ .word TIM15_IRQHandler
+ .word TIM16_IRQHandler
+ .word TIM17_IRQHandler
+ .word TIM18_DAC2_IRQHandler
+ .word TIM2_IRQHandler
+ .word TIM3_IRQHandler
+ .word TIM4_IRQHandler
+ .word I2C1_EV_IRQHandler
+ .word I2C1_ER_IRQHandler
+ .word I2C2_EV_IRQHandler
+ .word I2C2_ER_IRQHandler
+ .word SPI1_IRQHandler
+ .word SPI2_IRQHandler
+ .word USART1_IRQHandler
+ .word USART2_IRQHandler
+ .word USART3_IRQHandler
+ .word EXTI15_10_IRQHandler
+ .word RTC_Alarm_IRQHandler
+ .word CEC_IRQHandler
+ .word TIM12_IRQHandler
+ .word TIM13_IRQHandler
+ .word TIM14_IRQHandler
+ .word 0
+ .word 0
+ .word 0
+ .word 0
+ .word TIM5_IRQHandler
+ .word SPI3_IRQHandler
+ .word 0
+ .word 0
+ .word TIM6_DAC1_IRQHandler
+ .word TIM7_IRQHandler
+ .word DMA2_Channel1_IRQHandler
+ .word DMA2_Channel2_IRQHandler
+ .word DMA2_Channel3_IRQHandler
+ .word DMA2_Channel4_IRQHandler
+ .word DMA2_Channel5_IRQHandler
+ .word SDADC1_IRQHandler
+ .word SDADC2_IRQHandler
+ .word SDADC3_IRQHandler
+ .word COMP_IRQHandler
+ .word 0
+ .word 0
+ .word 0
+ .word 0
+ .word 0
+ .word 0
+ .word 0
+ .word 0
+ .word 0
+ .word USB_HP_IRQHandler
+ .word USB_LP_IRQHandler
+ .word USBWakeUp_IRQHandler
+ .word 0
+ .word TIM19_IRQHandler
+ .word 0
+ .word 0
+ .word FPU_IRQHandler
+
+/*******************************************************************************
+*
+* Provide weak aliases for each Exception handler to the Default_Handler.
+* As they are weak aliases, any function with the same name will override
+* this definition.
+*
+*******************************************************************************/
+
+ .weak NMI_Handler
+ .thumb_set NMI_Handler,Default_Handler
+
+ .weak HardFault_Handler
+ .thumb_set HardFault_Handler,Default_Handler
+
+ .weak MemManage_Handler
+ .thumb_set MemManage_Handler,Default_Handler
+
+ .weak BusFault_Handler
+ .thumb_set BusFault_Handler,Default_Handler
+
+ .weak UsageFault_Handler
+ .thumb_set UsageFault_Handler,Default_Handler
+
+ .weak SVC_Handler
+ .thumb_set SVC_Handler,Default_Handler
+
+ .weak DebugMon_Handler
+ .thumb_set DebugMon_Handler,Default_Handler
+
+ .weak PendSV_Handler
+ .thumb_set PendSV_Handler,Default_Handler
+
+ .weak SysTick_Handler
+ .thumb_set SysTick_Handler,Default_Handler
+
+ .weak WWDG_IRQHandler
+ .thumb_set WWDG_IRQHandler,Default_Handler
+
+ .weak PVD_IRQHandler
+ .thumb_set PVD_IRQHandler,Default_Handler
+
+ .weak TAMPER_STAMP_IRQHandler
+ .thumb_set TAMPER_STAMP_IRQHandler,Default_Handler
+
+ .weak RTC_WKUP_IRQHandler
+ .thumb_set RTC_WKUP_IRQHandler,Default_Handler
+
+ .weak FLASH_IRQHandler
+ .thumb_set FLASH_IRQHandler,Default_Handler
+
+ .weak RCC_IRQHandler
+ .thumb_set RCC_IRQHandler,Default_Handler
+
+ .weak EXTI0_IRQHandler
+ .thumb_set EXTI0_IRQHandler,Default_Handler
+
+ .weak EXTI1_IRQHandler
+ .thumb_set EXTI1_IRQHandler,Default_Handler
+
+ .weak EXTI2_TS_IRQHandler
+ .thumb_set EXTI2_TS_IRQHandler,Default_Handler
+
+ .weak EXTI3_IRQHandler
+ .thumb_set EXTI3_IRQHandler,Default_Handler
+
+ .weak EXTI4_IRQHandler
+ .thumb_set EXTI4_IRQHandler,Default_Handler
+
+ .weak DMA1_Channel1_IRQHandler
+ .thumb_set DMA1_Channel1_IRQHandler,Default_Handler
+
+ .weak DMA1_Channel2_IRQHandler
+ .thumb_set DMA1_Channel2_IRQHandler,Default_Handler
+
+ .weak DMA1_Channel3_IRQHandler
+ .thumb_set DMA1_Channel3_IRQHandler,Default_Handler
+
+ .weak DMA1_Channel4_IRQHandler
+ .thumb_set DMA1_Channel4_IRQHandler,Default_Handler
+
+ .weak DMA1_Channel5_IRQHandler
+ .thumb_set DMA1_Channel5_IRQHandler,Default_Handler
+
+ .weak DMA1_Channel6_IRQHandler
+ .thumb_set DMA1_Channel6_IRQHandler,Default_Handler
+
+ .weak DMA1_Channel7_IRQHandler
+ .thumb_set DMA1_Channel7_IRQHandler,Default_Handler
+
+ .weak ADC1_IRQHandler
+ .thumb_set ADC1_IRQHandler,Default_Handler
+
+ .weak CAN1_TX_IRQHandler
+ .thumb_set CAN1_TX_IRQHandler,Default_Handler
+
+ .weak CAN1_RX0_IRQHandler
+ .thumb_set CAN1_RX0_IRQHandler,Default_Handler
+
+ .weak CAN1_RX1_IRQHandler
+ .thumb_set CAN1_RX1_IRQHandler,Default_Handler
+
+ .weak CAN1_SCE_IRQHandler
+ .thumb_set CAN1_SCE_IRQHandler,Default_Handler
+
+ .weak EXTI9_5_IRQHandler
+ .thumb_set EXTI9_5_IRQHandler,Default_Handler
+
+ .weak TIM15_IRQHandler
+ .thumb_set TIM15_IRQHandler,Default_Handler
+
+ .weak TIM16_IRQHandler
+ .thumb_set TIM16_IRQHandler,Default_Handler
+
+ .weak TIM17_IRQHandler
+ .thumb_set TIM17_IRQHandler,Default_Handler
+
+ .weak TIM18_DAC2_IRQHandler
+ .thumb_set TIM18_DAC2_IRQHandler,Default_Handler
+
+ .weak TIM2_IRQHandler
+ .thumb_set TIM2_IRQHandler,Default_Handler
+
+ .weak TIM3_IRQHandler
+ .thumb_set TIM3_IRQHandler,Default_Handler
+
+ .weak TIM4_IRQHandler
+ .thumb_set TIM4_IRQHandler,Default_Handler
+
+ .weak I2C1_EV_IRQHandler
+ .thumb_set I2C1_EV_IRQHandler,Default_Handler
+
+ .weak I2C1_ER_IRQHandler
+ .thumb_set I2C1_ER_IRQHandler,Default_Handler
+
+ .weak I2C2_EV_IRQHandler
+ .thumb_set I2C2_EV_IRQHandler,Default_Handler
+
+ .weak I2C2_ER_IRQHandler
+ .thumb_set I2C2_ER_IRQHandler,Default_Handler
+
+ .weak SPI1_IRQHandler
+ .thumb_set SPI1_IRQHandler,Default_Handler
+
+ .weak SPI2_IRQHandler
+ .thumb_set SPI2_IRQHandler,Default_Handler
+
+ .weak USART1_IRQHandler
+ .thumb_set USART1_IRQHandler,Default_Handler
+
+ .weak USART2_IRQHandler
+ .thumb_set USART2_IRQHandler,Default_Handler
+
+ .weak USART3_IRQHandler
+ .thumb_set USART3_IRQHandler,Default_Handler
+
+ .weak EXTI15_10_IRQHandler
+ .thumb_set EXTI15_10_IRQHandler,Default_Handler
+
+ .weak RTC_Alarm_IRQHandler
+ .thumb_set RTC_Alarm_IRQHandler,Default_Handler
+
+ .weak CEC_IRQHandler
+ .thumb_set CEC_IRQHandler,Default_Handler
+
+ .weak TIM12_IRQHandler
+ .thumb_set TIM12_IRQHandler,Default_Handler
+
+ .weak TIM13_IRQHandler
+ .thumb_set TIM13_IRQHandler,Default_Handler
+
+ .weak TIM14_IRQHandler
+ .thumb_set TIM14_IRQHandler,Default_Handler
+
+ .weak TIM5_IRQHandler
+ .thumb_set TIM5_IRQHandler,Default_Handler
+
+ .weak SPI3_IRQHandler
+ .thumb_set SPI3_IRQHandler,Default_Handler
+
+ .weak TIM6_DAC1_IRQHandler
+ .thumb_set TIM6_DAC1_IRQHandler,Default_Handler
+
+ .weak TIM7_IRQHandler
+ .thumb_set TIM7_IRQHandler,Default_Handler
+
+ .weak DMA2_Channel1_IRQHandler
+ .thumb_set DMA2_Channel1_IRQHandler,Default_Handler
+
+ .weak DMA2_Channel2_IRQHandler
+ .thumb_set DMA2_Channel2_IRQHandler,Default_Handler
+
+ .weak DMA2_Channel3_IRQHandler
+ .thumb_set DMA2_Channel3_IRQHandler,Default_Handler
+
+ .weak DMA2_Channel4_IRQHandler
+ .thumb_set DMA2_Channel4_IRQHandler,Default_Handler
+
+ .weak DMA2_Channel5_IRQHandler
+ .thumb_set DMA2_Channel5_IRQHandler,Default_Handler
+
+ .weak SDADC1_IRQHandler
+ .thumb_set SDADC1_IRQHandler,Default_Handler
+
+ .weak SDADC2_IRQHandler
+ .thumb_set SDADC2_IRQHandler,Default_Handler
+
+ .weak SDADC3_IRQHandler
+ .thumb_set SDADC3_IRQHandler,Default_Handler
+
+ .weak COMP_IRQHandler
+ .thumb_set COMP_IRQHandler,Default_Handler
+
+ .weak USB_HP_IRQHandler
+ .thumb_set USB_HP_IRQHandler,Default_Handler
+
+ .weak USB_LP_IRQHandler
+ .thumb_set USB_LP_IRQHandler,Default_Handler
+
+ .weak USBWakeUp_IRQHandler
+ .thumb_set USBWakeUp_IRQHandler,Default_Handler
+
+ .weak TIM19_IRQHandler
+ .thumb_set TIM19_IRQHandler,Default_Handler
+
+ .weak FPU_IRQHandler
+ .thumb_set FPU_IRQHandler,Default_Handler
+/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
diff --git a/Libraries/CMSIS/Device/ST/STM32F37x/Source/Templates/arm/startup_stm32f37x.s b/Libraries/CMSIS/Device/ST/STM32F37x/Source/Templates/arm/startup_stm32f37x.s
new file mode 100644
index 0000000..6ca14f8
--- /dev/null
+++ b/Libraries/CMSIS/Device/ST/STM32F37x/Source/Templates/arm/startup_stm32f37x.s
@@ -0,0 +1,396 @@
+;******************** (C) COPYRIGHT 2012 STMicroelectronics ********************
+;* File Name : startup_stm32f37x.s
+;* Author : MCD Application Team
+;* Version : V1.0.0
+;* Date : 20-September-2012
+;* Description : STM32F37x devices vector table for MDK-ARM toolchain.
+;* This module performs:
+;* - Set the initial SP
+;* - Set the initial PC == Reset_Handler
+;* - Set the vector table entries with the exceptions ISR address
+;* - Branches to __main in the C library (which eventually
+;* calls main()).
+;* After Reset the CortexM4 processor is in Thread mode,
+;* priority is Privileged, and the Stack is set to Main.
+;* <<< Use Configuration Wizard in Context Menu >>>
+;*******************************************************************************
+; @attention
+;
+; Licensed under MCD-ST Liberty SW License Agreement V2, (the "License");
+; You may not use this file except in compliance with the License.
+; You may obtain a copy of the License at:
+;
+; http://www.st.com/software_license_agreement_liberty_v2
+;
+; Unless required by applicable law or agreed to in writing, software
+; distributed under the License is distributed on an "AS IS" BASIS,
+; WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+; See the License for the specific language governing permissions and
+; limitations under the License.
+;
+;*******************************************************************************
+;
+; Amount of memory (in bytes) allocated for Stack
+; Tailor this value to your application needs
+; © COPYRIGHT 2012 STMicroelectronics
+ *
+ * Licensed under MCD-ST Liberty SW License Agreement V2, (the "License");
+ * You may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at:
+ *
+ * http://www.st.com/software_license_agreement_liberty_v2
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ *
+ ******************************************************************************
+ */
+
+ .syntax unified
+ .cpu cortex-m4
+ .fpu softvfp
+ .thumb
+
+.global g_pfnVectors
+.global Default_Handler
+
+/* start address for the initialization values of the .data section.
+defined in linker script */
+.word _sidata
+/* start address for the .data section. defined in linker script */
+.word _sdata
+/* end address for the .data section. defined in linker script */
+.word _edata
+/* start address for the .bss section. defined in linker script */
+.word _sbss
+/* end address for the .bss section. defined in linker script */
+.word _ebss
+/* stack used for SystemInit_ExtMemCtl; always internal RAM used */
+
+/**
+ * @brief This is the code that gets called when the processor first
+ * starts execution following a reset event. Only the absolutely
+ * necessary set is performed, after which the application
+ * supplied main() routine is called.
+ * @param None
+ * @retval : None
+*/
+
+ .section .text.Reset_Handler
+ .weak Reset_Handler
+ .type Reset_Handler, %function
+Reset_Handler:
+
+/* Copy the data segment initializers from flash to SRAM */
+ movs r1, #0
+ b LoopCopyDataInit
+
+CopyDataInit:
+ ldr r3, =_sidata
+ ldr r3, [r3, r1]
+ str r3, [r0, r1]
+ adds r1, r1, #4
+
+LoopCopyDataInit:
+ ldr r0, =_sdata
+ ldr r3, =_edata
+ adds r2, r0, r1
+ cmp r2, r3
+ bcc CopyDataInit
+ ldr r2, =_sbss
+ b LoopFillZerobss
+/* Zero fill the bss segment. */
+FillZerobss:
+ movs r3, #0
+ str r3, [r2], #4
+
+LoopFillZerobss:
+ ldr r3, = _ebss
+ cmp r2, r3
+ bcc FillZerobss
+
+/* Call the clock system intitialization function.*/
+ bl SystemInit
+/* Call the application's entry point.*/
+ bl main
+ bx lr
+.size Reset_Handler, .-Reset_Handler
+
+/**
+ * @brief This is the code that gets called when the processor receives an
+ * unexpected interrupt. This simply enters an infinite loop, preserving
+ * the system state for examination by a debugger.
+ * @param None
+ * @retval None
+*/
+ .section .text.Default_Handler,"ax",%progbits
+Default_Handler:
+Infinite_Loop:
+ b Infinite_Loop
+ .size Default_Handler, .-Default_Handler
+/******************************************************************************
+*
+* The minimal vector table for a Cortex-M4. Note that the proper constructs
+* must be placed on this to ensure that it ends up at physical address
+* 0x0000.0000.
+*
+*******************************************************************************/
+ .section .isr_vector,"a",%progbits
+ .type g_pfnVectors, %object
+ .size g_pfnVectors, .-g_pfnVectors
+
+
+g_pfnVectors:
+ .word _estack
+ .word Reset_Handler
+ .word NMI_Handler
+ .word HardFault_Handler
+ .word MemManage_Handler
+ .word BusFault_Handler
+ .word UsageFault_Handler
+ .word 0
+ .word 0
+ .word 0
+ .word 0
+ .word SVC_Handler
+ .word DebugMon_Handler
+ .word 0
+ .word PendSV_Handler
+ .word SysTick_Handler
+
+ /* External Interrupts */
+ .word WWDG_IRQHandler /* Window WatchDog */
+ .word PVD_IRQHandler /* PVD through EXTI Line detection */
+ .word TAMPER_STAMP_IRQHandler /* Tamper and TimeStamps through the EXTI line */
+ .word RTC_WKUP_IRQHandler /* RTC Wakeup through the EXTI line */
+ .word FLASH_IRQHandler /* FLASH */
+ .word RCC_IRQHandler /* RCC */
+ .word EXTI0_IRQHandler /* EXTI Line0 */
+ .word EXTI1_IRQHandler /* EXTI Line1 */
+ .word EXTI2_TS_IRQHandler /* EXTI Line2 */
+ .word EXTI3_IRQHandler /* EXTI Line3 */
+ .word EXTI4_IRQHandler /* EXTI Line4 */
+ .word DMA1_Channel1_IRQHandler /* DMA1 Channel 1 */
+ .word DMA1_Channel2_IRQHandler /* DMA1 Channel 2 */
+ .word DMA1_Channel3_IRQHandler /* DMA1 Channel 3 */
+ .word DMA1_Channel4_IRQHandler /* DMA1 Channel 4 */
+ .word DMA1_Channel5_IRQHandler /* DMA1 Channel 5 */
+ .word DMA1_Channel6_IRQHandler /* DMA1 Channel 6 */
+ .word DMA1_Channel7_IRQHandler /* DMA1 Channel 7 */
+ .word ADC1_IRQHandler /* ADC1 */
+ .word CAN1_TX_IRQHandler /* CAN1 TX */
+ .word CAN1_RX0_IRQHandler /* CAN1 RX0 */
+ .word CAN1_RX1_IRQHandler /* CAN1 RX1 */
+ .word CAN1_SCE_IRQHandler /* CAN1 SCE */
+ .word EXTI9_5_IRQHandler /* External Line[9:5]s */
+ .word TIM15_IRQHandler /* TIM15 */
+ .word TIM16_IRQHandler /* TIM16 */
+ .word TIM17_IRQHandler /* TIM17 */
+ .word TIM18_DAC2_IRQHandler /* TIM18 and DAC2 */
+ .word TIM2_IRQHandler /* TIM2 */
+ .word TIM3_IRQHandler /* TIM3 */
+ .word TIM4_IRQHandler /* TIM4 */
+ .word I2C1_EV_IRQHandler /* I2C1 Event */
+ .word I2C1_ER_IRQHandler /* I2C1 Error */
+ .word I2C2_EV_IRQHandler /* I2C2 Event */
+ .word I2C2_ER_IRQHandler /* I2C2 Error */
+ .word SPI1_IRQHandler /* SPI1 */
+ .word SPI2_IRQHandler /* SPI2 */
+ .word USART1_IRQHandler /* USART1 */
+ .word USART2_IRQHandler /* USART2 */
+ .word USART3_IRQHandler /* USART3 */
+ .word EXTI15_10_IRQHandler /* External Line[15:10]s */
+ .word RTC_Alarm_IRQHandler /* RTC_Alarm_IRQHandler */
+ .word CEC_IRQHandler /* CEC */
+ .word TIM12_IRQHandler /* TIM12 */
+ .word TIM13_IRQHandler /* TIM13 */
+ .word TIM14_IRQHandler /* TIM14 */
+ .word 0 /* Reserved */
+ .word 0 /* Reserved */
+ .word 0 /* Reserved */
+ .word 0 /* Reserved */
+ .word TIM5_IRQHandler /* TIM5 */
+ .word SPI3_IRQHandler /* SPI3 */
+ .word 0 /* Reserved */
+ .word 0 /* Reserved */
+ .word TIM6_DAC1_IRQHandler /* TIM6 and DAC1 Channel1 & channel2 */
+ .word TIM7_IRQHandler /* TIM7 */
+ .word DMA2_Channel1_IRQHandler /* DMA2 Channel 1 */
+ .word DMA2_Channel2_IRQHandler /* DMA2 Channel 2 */
+ .word DMA2_Channel3_IRQHandler /* DMA2 Channel 3 */
+ .word DMA2_Channel4_IRQHandler /* DMA2 Channel 4 */
+ .word DMA2_Channel5_IRQHandler /* DMA2 Channel 5 */
+ .word SDADC1_IRQHandler /* SDADC1 */
+ .word SDADC2_IRQHandler /* SDADC2 */
+ .word SDADC3_IRQHandler /* SDADC3 */
+ .word COMP_IRQHandler /* COMP */
+ .word 0 /* Reserved */
+ .word 0 /* Reserved */
+ .word 0 /* Reserved */
+ .word 0 /* Reserved */
+ .word 0 /* Reserved */
+ .word 0 /* Reserved */
+ .word 0 /* Reserved */
+ .word 0 /* Reserved */
+ .word 0 /* Reserved */
+ .word USB_HP_IRQHandler /* USB High Priority */
+ .word USB_LP_IRQHandler /* USB Low Priority */
+ .word USBWakeUp_IRQHandler /* USB Wakeup */
+ .word 0 /* Resrved */
+ .word TIM19_IRQHandler /*TIM19 */
+ .word 0 /* Resrved */
+ .word FPU_IRQHandler /* FPU */
+
+
+/*******************************************************************************
+*
+* Provide weak aliases for each Exception handler to the Default_Handler.
+* As they are weak aliases, any function with the same name will override
+* this definition.
+*
+*******************************************************************************/
+ .weak NMI_Handler
+ .thumb_set NMI_Handler,Default_Handler
+
+ .weak HardFault_Handler
+ .thumb_set HardFault_Handler,Default_Handler
+
+ .weak MemManage_Handler
+ .thumb_set MemManage_Handler,Default_Handler
+
+ .weak BusFault_Handler
+ .thumb_set BusFault_Handler,Default_Handler
+
+ .weak UsageFault_Handler
+ .thumb_set UsageFault_Handler,Default_Handler
+
+ .weak SVC_Handler
+ .thumb_set SVC_Handler,Default_Handler
+
+ .weak DebugMon_Handler
+ .thumb_set DebugMon_Handler,Default_Handler
+
+ .weak PendSV_Handler
+ .thumb_set PendSV_Handler,Default_Handler
+
+ .weak SysTick_Handler
+ .thumb_set SysTick_Handler,Default_Handler
+
+ .weak WWDG_IRQHandler
+ .thumb_set WWDG_IRQHandler,Default_Handler
+
+ .weak PVD_IRQHandler
+ .thumb_set PVD_IRQHandler,Default_Handler
+
+ .weak TAMPER_STAMP_IRQHandler
+ .thumb_set TAMPER_STAMP_IRQHandler,Default_Handler
+
+ .weak RTC_WKUP_IRQHandler
+ .thumb_set RTC_WKUP_IRQHandler,Default_Handler
+
+ .weak FLASH_IRQHandler
+ .thumb_set FLASH_IRQHandler,Default_Handler
+
+ .weak RCC_IRQHandler
+ .thumb_set RCC_IRQHandler,Default_Handler
+
+ .weak EXTI0_IRQHandler
+ .thumb_set EXTI0_IRQHandler,Default_Handler
+
+ .weak EXTI1_IRQHandler
+ .thumb_set EXTI1_IRQHandler,Default_Handler
+
+ .weak EXTI2_TS_IRQHandler
+ .thumb_set EXTI2_TS_IRQHandler,Default_Handler
+
+ .weak EXTI3_IRQHandler
+ .thumb_set EXTI3_IRQHandler,Default_Handler
+
+ .weak EXTI4_IRQHandler
+ .thumb_set EXTI4_IRQHandler,Default_Handler
+
+ .weak DMA1_Channel1_IRQHandler
+ .thumb_set DMA1_Channel1_IRQHandler,Default_Handler
+
+ .weak DMA1_Channel2_IRQHandler
+ .thumb_set DMA1_Channel2_IRQHandler,Default_Handler
+
+ .weak DMA1_Channel3_IRQHandler
+ .thumb_set DMA1_Channel3_IRQHandler,Default_Handler
+
+ .weak DMA1_Channel4_IRQHandler
+ .thumb_set DMA1_Channel4_IRQHandler,Default_Handler
+
+ .weak DMA1_Channel5_IRQHandler
+ .thumb_set DMA1_Channel5_IRQHandler,Default_Handler
+
+ .weak DMA1_Channel6_IRQHandler
+ .thumb_set DMA1_Channel6_IRQHandler,Default_Handler
+
+ .weak DMA1_Channel7_IRQHandler
+ .thumb_set DMA1_Channel7_IRQHandler,Default_Handler
+
+ .weak ADC1_IRQHandler
+ .thumb_set ADC1_IRQHandler,Default_Handler
+
+ .weak CAN1_TX_IRQHandler
+ .thumb_set CAN1_TX_IRQHandler,Default_Handler
+
+ .weak CAN1_RX0_IRQHandler
+ .thumb_set CAN1_RX0_IRQHandler,Default_Handler
+
+ .weak CAN1_RX1_IRQHandler
+ .thumb_set CAN1_RX1_IRQHandler,Default_Handler
+
+ .weak CAN1_SCE_IRQHandler
+ .thumb_set CAN1_SCE_IRQHandler,Default_Handler
+
+ .weak EXTI9_5_IRQHandler
+ .thumb_set EXTI9_5_IRQHandler,Default_Handler
+
+ .weak TIM15_IRQHandler
+ .thumb_set TIM15_IRQHandler,Default_Handler
+
+ .weak TIM16_IRQHandler
+ .thumb_set TIM16_IRQHandler,Default_Handler
+
+ .weak TIM17_IRQHandler
+ .thumb_set TIM17_IRQHandler,Default_Handler
+
+ .weak TIM18_DAC2_IRQHandler
+ .thumb_set TIM18_DAC2_IRQHandler,Default_Handler
+
+ .weak TIM2_IRQHandler
+ .thumb_set TIM2_IRQHandler,Default_Handler
+
+ .weak TIM3_IRQHandler
+ .thumb_set TIM3_IRQHandler,Default_Handler
+
+ .weak TIM4_IRQHandler
+ .thumb_set TIM4_IRQHandler,Default_Handler
+
+ .weak I2C1_EV_IRQHandler
+ .thumb_set I2C1_EV_IRQHandler,Default_Handler
+
+ .weak I2C1_ER_IRQHandler
+ .thumb_set I2C1_ER_IRQHandler,Default_Handler
+
+ .weak I2C2_EV_IRQHandler
+ .thumb_set I2C2_EV_IRQHandler,Default_Handler
+
+ .weak I2C2_ER_IRQHandler
+ .thumb_set I2C2_ER_IRQHandler,Default_Handler
+
+ .weak SPI1_IRQHandler
+ .thumb_set SPI1_IRQHandler,Default_Handler
+
+ .weak SPI2_IRQHandler
+ .thumb_set SPI2_IRQHandler,Default_Handler
+
+ .weak USART1_IRQHandler
+ .thumb_set USART1_IRQHandler,Default_Handler
+
+ .weak USART2_IRQHandler
+ .thumb_set USART2_IRQHandler,Default_Handler
+
+ .weak USART3_IRQHandler
+ .thumb_set USART3_IRQHandler,Default_Handler
+
+ .weak EXTI15_10_IRQHandler
+ .thumb_set EXTI15_10_IRQHandler,Default_Handler
+
+ .weak RTC_Alarm_IRQHandler
+ .thumb_set RTC_Alarm_IRQHandler,Default_Handler
+
+ .weak CEC_IRQHandler
+ .thumb_set CEC_IRQHandler,Default_Handler
+
+ .weak TIM12_IRQHandler
+ .thumb_set TIM12_IRQHandler,Default_Handler
+
+ .weak TIM13_IRQHandler
+ .thumb_set TIM13_IRQHandler,Default_Handler
+
+ .weak TIM14_IRQHandler
+ .thumb_set TIM14_IRQHandler,Default_Handler
+
+ .weak TIM5_IRQHandler
+ .thumb_set TIM5_IRQHandler,Default_Handler
+
+ .weak SPI3_IRQHandler
+ .thumb_set SPI3_IRQHandler,Default_Handler
+
+ .weak TIM6_DAC1_IRQHandler
+ .thumb_set TIM6_DAC1_IRQHandler,Default_Handler
+
+ .weak TIM7_IRQHandler
+ .thumb_set TIM7_IRQHandler,Default_Handler
+
+ .weak DMA2_Channel1_IRQHandler
+ .thumb_set DMA2_Channel1_IRQHandler,Default_Handler
+
+ .weak DMA2_Channel2_IRQHandler
+ .thumb_set DMA2_Channel2_IRQHandler,Default_Handler
+
+ .weak DMA2_Channel3_IRQHandler
+ .thumb_set DMA2_Channel3_IRQHandler,Default_Handler
+
+ .weak DMA2_Channel4_IRQHandler
+ .thumb_set DMA2_Channel4_IRQHandler,Default_Handler
+
+ .weak DMA2_Channel5_IRQHandler
+ .thumb_set DMA2_Channel5_IRQHandler,Default_Handler
+
+ .weak SDADC1_IRQHandler
+ .thumb_set SDADC1_IRQHandler,Default_Handler
+
+ .weak SDADC2_IRQHandler
+ .thumb_set SDADC2_IRQHandler,Default_Handler
+
+ .weak SDADC3_IRQHandler
+ .thumb_set SDADC3_IRQHandler,Default_Handler
+
+ .weak COMP_IRQHandler
+ .thumb_set COMP_IRQHandler,Default_Handler
+
+ .weak USB_HP_IRQHandler
+ .thumb_set USB_HP_IRQHandler,Default_Handler
+
+ .weak USB_LP_IRQHandler
+ .thumb_set USB_LP_IRQHandler,Default_Handler
+
+ .weak USBWakeUp_IRQHandler
+ .thumb_set USBWakeUp_IRQHandler,Default_Handler
+
+ .weak TIM19_IRQHandler
+ .thumb_set TIM19_IRQHandler,Default_Handler
+
+ .weak FPU_IRQHandler
+ .thumb_set FPU_IRQHandler,Default_Handler
+
+
+/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
diff --git a/Libraries/CMSIS/Device/ST/STM32F37x/Source/Templates/iar/startup_stm32f37x.s b/Libraries/CMSIS/Device/ST/STM32F37x/Source/Templates/iar/startup_stm32f37x.s
new file mode 100644
index 0000000..211862e
--- /dev/null
+++ b/Libraries/CMSIS/Device/ST/STM32F37x/Source/Templates/iar/startup_stm32f37x.s
@@ -0,0 +1,542 @@
+;/******************** (C) COPYRIGHT 2012 STMicroelectronics ********************
+;* File Name : startup_stm32f37x.s
+;* Author : MCD Application Team
+;* Version : V1.0.0
+;* Date : 20-September-2012
+;* Description : STM32F37x Devices vector table for EWARM toolchain.
+;* This module performs:
+;* - Set the initial SP
+;* - Set the initial PC == iar_program_start,
+;* - Set the vector table entries with the exceptions ISR
+;* address.
+;* After Reset the Cortex-M4 processor is in Thread mode,
+;* priority is Privileged, and the Stack is set to Main.
+;*******************************************************************************
+; @attention
+;
+; Licensed under MCD-ST Liberty SW License Agreement V2, (the "License");
+; You may not use this file except in compliance with the License.
+; You may obtain a copy of the License at:
+;
+; http://www.st.com/software_license_agreement_liberty_v2
+;
+; Unless required by applicable law or agreed to in writing, software
+; distributed under the License is distributed on an "AS IS" BASIS,
+; WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+; See the License for the specific language governing permissions and
+; limitations under the License.
+;
+;*******************************************************************************
+;
+;
+; The modules in this file are included in the libraries, and may be replaced
+; by any user-defined modules that define the PUBLIC symbol _program_start or
+; a user defined start symbol.
+; To override the cstartup defined in the library, simply add your modified
+; version to the workbench project.
+;
+; The vector table is normally located at address 0.
+; When debugging in RAM, it can be located in RAM, aligned to at least 2^6.
+; The name "__vector_table" has special meaning for C-SPY:
+; it is where the SP start value is found, and the NVIC vector
+; table register (VTOR) is initialized to this address if != 0.
+;
+; Cortex-M version
+;
+
+ MODULE ?cstartup
+
+ ;; Forward declaration of sections.
+ SECTION CSTACK:DATA:NOROOT(3)
+
+ SECTION .intvec:CODE:NOROOT(2)
+
+ EXTERN __iar_program_start
+ EXTERN SystemInit
+ PUBLIC __vector_table
+
+ DATA
+__vector_table
+ DCD sfe(CSTACK)
+ DCD Reset_Handler ; Reset Handler
+
+ DCD NMI_Handler ; NMI Handler
+ DCD HardFault_Handler ; Hard Fault Handler
+ DCD MemManage_Handler ; MPU Fault Handler
+ DCD BusFault_Handler ; Bus Fault Handler
+ DCD UsageFault_Handler ; Usage Fault Handler
+ DCD 0 ; Reserved
+ DCD 0 ; Reserved
+ DCD 0 ; Reserved
+ DCD 0 ; Reserved
+ DCD SVC_Handler ; SVCall Handler
+ DCD DebugMon_Handler ; Debug Monitor Handler
+ DCD 0 ; Reserved
+ DCD PendSV_Handler ; PendSV Handler
+ DCD SysTick_Handler ; SysTick Handler
+
+ ; External Interrupts
+ DCD WWDG_IRQHandler ; Window WatchDog
+ DCD PVD_IRQHandler ; PVD through EXTI Line detection
+ DCD TAMPER_STAMP_IRQHandler ; Tamper and TimeStamps through the EXTI line
+ DCD RTC_WKUP_IRQHandler ; RTC Wakeup through the EXTI line
+ DCD FLASH_IRQHandler ; FLASH
+ DCD RCC_IRQHandler ; RCC
+ DCD EXTI0_IRQHandler ; EXTI Line0
+ DCD EXTI1_IRQHandler ; EXTI Line1
+ DCD EXTI2_TS_IRQHandler ; EXTI Line2 and Touch Sense controller
+ DCD EXTI3_IRQHandler ; EXTI Line3
+ DCD EXTI4_IRQHandler ; EXTI Line4
+ DCD DMA1_Channel1_IRQHandler ; DMA1 Channel 1
+ DCD DMA1_Channel2_IRQHandler ; DMA1 Channel 2
+ DCD DMA1_Channel3_IRQHandler ; DMA1 Channel 3
+ DCD DMA1_Channel4_IRQHandler ; DMA1 Channel 4
+ DCD DMA1_Channel5_IRQHandler ; DMA1 Channel 5
+ DCD DMA1_Channel6_IRQHandler ; DMA1 Channel 6
+ DCD DMA1_Channel7_IRQHandler ; DMA1 Channel 7
+ DCD ADC1_IRQHandler ; ADC1
+ DCD CAN1_TX_IRQHandler ; CAN1 TX
+ DCD CAN1_RX0_IRQHandler ; CAN1 RX0
+ DCD CAN1_RX1_IRQHandler ; CAN1 RX1
+ DCD CAN1_SCE_IRQHandler ; CAN1 SCE
+ DCD EXTI9_5_IRQHandler ; External Line[9:5]s
+ DCD TIM15_IRQHandler ; TIM15
+ DCD TIM16_IRQHandler ; TIM16
+ DCD TIM17_IRQHandler ; TIM17
+ DCD TIM18_DAC2_IRQHandler ; TIM18 and DAC2
+ DCD TIM2_IRQHandler ; TIM2
+ DCD TIM3_IRQHandler ; TIM3
+ DCD TIM4_IRQHandler ; TIM4
+ DCD I2C1_EV_IRQHandler ; I2C1 Event
+ DCD I2C1_ER_IRQHandler ; I2C1 Error
+ DCD I2C2_EV_IRQHandler ; I2C2 Event
+ DCD I2C2_ER_IRQHandler ; I2C2 Error
+ DCD SPI1_IRQHandler ; SPI1
+ DCD SPI2_IRQHandler ; SPI2
+ DCD USART1_IRQHandler ; USART1
+ DCD USART2_IRQHandler ; USART2
+ DCD USART3_IRQHandler ; USART3
+ DCD EXTI15_10_IRQHandler ; External Line[15:10]s
+ DCD RTC_Alarm_IRQHandler ; RTC Alarm (A and B) through EXTI Line
+ DCD CEC_IRQHandler ; CEC
+ DCD TIM12_IRQHandler ; TIM12
+ DCD TIM13_IRQHandler ; TIM13
+ DCD TIM14_IRQHandler ; TIM14
+ DCD 0 ; Reserved
+ DCD 0 ; Reserved
+ DCD 0 ; Reserved
+ DCD 0 ; Reserved
+ DCD TIM5_IRQHandler ; TIM5
+ DCD SPI3_IRQHandler ; SPI3
+ DCD 0 ; Reserved
+ DCD 0 ; Reserved
+ DCD TIM6_DAC1_IRQHandler ; TIM6 and DAC1 Channel1 & channel2
+ DCD TIM7_IRQHandler ; TIM7
+ DCD DMA2_Channel1_IRQHandler ; DMA2 Channel 1
+ DCD DMA2_Channel2_IRQHandler ; DMA2 Channel 2
+ DCD DMA2_Channel3_IRQHandler ; DMA2 Channel 3
+ DCD DMA2_Channel4_IRQHandler ; DMA2 Channel 4
+ DCD DMA2_Channel5_IRQHandler ; DMA2 Channel 5
+ DCD SDADC1_IRQHandler ; SDADC1
+ DCD SDADC2_IRQHandler ; SDADC2
+ DCD SDADC3_IRQHandler ; SDADC3
+ DCD COMP_IRQHandler ; COMP
+ DCD 0 ; Reserved
+ DCD 0 ; Reserved
+ DCD 0 ; Reserved
+ DCD 0 ; Reserved
+ DCD 0 ; Reserved
+ DCD 0 ; Reserved
+ DCD 0 ; Reserved
+ DCD 0 ; Reserved
+ DCD 0 ; Reserved
+ DCD USB_HP_IRQHandler ; USB High Priority
+ DCD USB_LP_IRQHandler ; USB Low Priority
+ DCD USBWakeUp_IRQHandler ; USB Wakeup
+ DCD 0 ; Reserved
+ DCD TIM19_IRQHandler ; TIM19
+ DCD 0 ; Reserved
+ DCD 0 ; Reserved
+ DCD FPU_IRQHandler ; FPU
+
+;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
+;;
+;; Default interrupt handlers.
+;;
+ THUMB
+ PUBWEAK Reset_Handler
+ SECTION .text:CODE:REORDER(2)
+Reset_Handler
+
+ LDR R0, =SystemInit
+ BLX R0
+ LDR R0, =__iar_program_start
+ BX R0
+
+ PUBWEAK NMI_Handler
+ SECTION .text:CODE:REORDER(1)
+NMI_Handler
+ B NMI_Handler
+
+ PUBWEAK HardFault_Handler
+ SECTION .text:CODE:REORDER(1)
+HardFault_Handler
+ B HardFault_Handler
+
+ PUBWEAK MemManage_Handler
+ SECTION .text:CODE:REORDER(1)
+MemManage_Handler
+ B MemManage_Handler
+
+ PUBWEAK BusFault_Handler
+ SECTION .text:CODE:REORDER(1)
+BusFault_Handler
+ B BusFault_Handler
+
+ PUBWEAK UsageFault_Handler
+ SECTION .text:CODE:REORDER(1)
+UsageFault_Handler
+ B UsageFault_Handler
+
+ PUBWEAK SVC_Handler
+ SECTION .text:CODE:REORDER(1)
+SVC_Handler
+ B SVC_Handler
+
+ PUBWEAK DebugMon_Handler
+ SECTION .text:CODE:REORDER(1)
+DebugMon_Handler
+ B DebugMon_Handler
+
+ PUBWEAK PendSV_Handler
+ SECTION .text:CODE:REORDER(1)
+PendSV_Handler
+ B PendSV_Handler
+
+ PUBWEAK SysTick_Handler
+ SECTION .text:CODE:REORDER(1)
+SysTick_Handler
+ B SysTick_Handler
+
+ PUBWEAK WWDG_IRQHandler
+ SECTION .text:CODE:REORDER(1)
+WWDG_IRQHandler
+ B WWDG_IRQHandler
+
+ PUBWEAK PVD_IRQHandler
+ SECTION .text:CODE:REORDER(1)
+PVD_IRQHandler
+ B PVD_IRQHandler
+
+ PUBWEAK TAMPER_STAMP_IRQHandler
+ SECTION .text:CODE:REORDER(1)
+TAMPER_STAMP_IRQHandler
+ B TAMPER_STAMP_IRQHandler
+
+ PUBWEAK RTC_WKUP_IRQHandler
+ SECTION .text:CODE:REORDER(1)
+RTC_WKUP_IRQHandler
+ B RTC_WKUP_IRQHandler
+
+ PUBWEAK FLASH_IRQHandler
+ SECTION .text:CODE:REORDER(1)
+FLASH_IRQHandler
+ B FLASH_IRQHandler
+
+ PUBWEAK RCC_IRQHandler
+ SECTION .text:CODE:REORDER(1)
+RCC_IRQHandler
+ B RCC_IRQHandler
+
+ PUBWEAK EXTI0_IRQHandler
+ SECTION .text:CODE:REORDER(1)
+EXTI0_IRQHandler
+ B EXTI0_IRQHandler
+
+ PUBWEAK EXTI1_IRQHandler
+ SECTION .text:CODE:REORDER(1)
+EXTI1_IRQHandler
+ B EXTI1_IRQHandler
+
+ PUBWEAK EXTI2_TS_IRQHandler
+ SECTION .text:CODE:REORDER(1)
+EXTI2_TS_IRQHandler
+ B EXTI2_TS_IRQHandler
+
+ PUBWEAK EXTI3_IRQHandler
+ SECTION .text:CODE:REORDER(1)
+EXTI3_IRQHandler
+ B EXTI3_IRQHandler
+
+ PUBWEAK EXTI4_IRQHandler
+ SECTION .text:CODE:REORDER(1)
+EXTI4_IRQHandler
+ B EXTI4_IRQHandler
+
+ PUBWEAK DMA1_Channel1_IRQHandler
+ SECTION .text:CODE:REORDER(1)
+DMA1_Channel1_IRQHandler
+ B DMA1_Channel1_IRQHandler
+
+ PUBWEAK DMA1_Channel2_IRQHandler
+ SECTION .text:CODE:REORDER(1)
+DMA1_Channel2_IRQHandler
+ B DMA1_Channel2_IRQHandler
+
+ PUBWEAK DMA1_Channel3_IRQHandler
+ SECTION .text:CODE:REORDER(1)
+DMA1_Channel3_IRQHandler
+ B DMA1_Channel3_IRQHandler
+
+ PUBWEAK DMA1_Channel4_IRQHandler
+ SECTION .text:CODE:REORDER(1)
+DMA1_Channel4_IRQHandler
+ B DMA1_Channel4_IRQHandler
+
+ PUBWEAK DMA1_Channel5_IRQHandler
+ SECTION .text:CODE:REORDER(1)
+DMA1_Channel5_IRQHandler
+ B DMA1_Channel5_IRQHandler
+
+ PUBWEAK DMA1_Channel6_IRQHandler
+ SECTION .text:CODE:REORDER(1)
+DMA1_Channel6_IRQHandler
+ B DMA1_Channel6_IRQHandler
+
+ PUBWEAK DMA1_Channel7_IRQHandler
+ SECTION .text:CODE:REORDER(1)
+DMA1_Channel7_IRQHandler
+ B DMA1_Channel7_IRQHandler
+
+ PUBWEAK ADC1_IRQHandler
+ SECTION .text:CODE:REORDER(1)
+ADC1_IRQHandler
+ B ADC1_IRQHandler
+
+ PUBWEAK CAN1_TX_IRQHandler
+ SECTION .text:CODE:REORDER(1)
+CAN1_TX_IRQHandler
+ B CAN1_TX_IRQHandler
+
+ PUBWEAK CAN1_RX0_IRQHandler
+ SECTION .text:CODE:REORDER(1)
+CAN1_RX0_IRQHandler
+ B CAN1_RX0_IRQHandler
+
+ PUBWEAK CAN1_RX1_IRQHandler
+ SECTION .text:CODE:REORDER(1)
+CAN1_RX1_IRQHandler
+ B CAN1_RX1_IRQHandler
+
+ PUBWEAK CAN1_SCE_IRQHandler
+ SECTION .text:CODE:REORDER(1)
+CAN1_SCE_IRQHandler
+ B CAN1_SCE_IRQHandler
+
+ PUBWEAK EXTI9_5_IRQHandler
+ SECTION .text:CODE:REORDER(1)
+EXTI9_5_IRQHandler
+ B EXTI9_5_IRQHandler
+
+ PUBWEAK TIM15_IRQHandler
+ SECTION .text:CODE:REORDER(1)
+TIM15_IRQHandler
+ B TIM15_IRQHandler
+
+ PUBWEAK TIM16_IRQHandler
+ SECTION .text:CODE:REORDER(1)
+TIM16_IRQHandler
+ B TIM16_IRQHandler
+
+ PUBWEAK TIM17_IRQHandler
+ SECTION .text:CODE:REORDER(1)
+TIM17_IRQHandler
+ B TIM17_IRQHandler
+
+ PUBWEAK TIM18_DAC2_IRQHandler
+ SECTION .text:CODE:REORDER(1)
+TIM18_DAC2_IRQHandler
+ B TIM18_DAC2_IRQHandler
+
+ PUBWEAK TIM2_IRQHandler
+ SECTION .text:CODE:REORDER(1)
+TIM2_IRQHandler
+ B TIM2_IRQHandler
+
+ PUBWEAK TIM3_IRQHandler
+ SECTION .text:CODE:REORDER(1)
+TIM3_IRQHandler
+ B TIM3_IRQHandler
+
+ PUBWEAK TIM4_IRQHandler
+ SECTION .text:CODE:REORDER(1)
+TIM4_IRQHandler
+ B TIM4_IRQHandler
+
+ PUBWEAK I2C1_EV_IRQHandler
+ SECTION .text:CODE:REORDER(1)
+I2C1_EV_IRQHandler
+ B I2C1_EV_IRQHandler
+
+ PUBWEAK I2C1_ER_IRQHandler
+ SECTION .text:CODE:REORDER(1)
+I2C1_ER_IRQHandler
+ B I2C1_ER_IRQHandler
+
+ PUBWEAK I2C2_EV_IRQHandler
+ SECTION .text:CODE:REORDER(1)
+I2C2_EV_IRQHandler
+ B I2C2_EV_IRQHandler
+
+ PUBWEAK I2C2_ER_IRQHandler
+ SECTION .text:CODE:REORDER(1)
+I2C2_ER_IRQHandler
+ B I2C2_ER_IRQHandler
+
+ PUBWEAK SPI1_IRQHandler
+ SECTION .text:CODE:REORDER(1)
+SPI1_IRQHandler
+ B SPI1_IRQHandler
+
+ PUBWEAK SPI2_IRQHandler
+ SECTION .text:CODE:REORDER(1)
+SPI2_IRQHandler
+ B SPI2_IRQHandler
+
+ PUBWEAK USART1_IRQHandler
+ SECTION .text:CODE:REORDER(1)
+USART1_IRQHandler
+ B USART1_IRQHandler
+
+ PUBWEAK USART2_IRQHandler
+ SECTION .text:CODE:REORDER(1)
+USART2_IRQHandler
+ B USART2_IRQHandler
+
+ PUBWEAK USART3_IRQHandler
+ SECTION .text:CODE:REORDER(1)
+USART3_IRQHandler
+ B USART3_IRQHandler
+
+ PUBWEAK EXTI15_10_IRQHandler
+ SECTION .text:CODE:REORDER(1)
+EXTI15_10_IRQHandler
+ B EXTI15_10_IRQHandler
+
+ PUBWEAK RTC_Alarm_IRQHandler
+ SECTION .text:CODE:REORDER(1)
+RTC_Alarm_IRQHandler
+ B RTC_Alarm_IRQHandler
+
+ PUBWEAK CEC_IRQHandler
+ SECTION .text:CODE:REORDER(1)
+CEC_IRQHandler
+ B CEC_IRQHandler
+
+ PUBWEAK TIM12_IRQHandler
+ SECTION .text:CODE:REORDER(1)
+TIM12_IRQHandler
+ B TIM12_IRQHandler
+
+ PUBWEAK TIM13_IRQHandler
+ SECTION .text:CODE:REORDER(1)
+TIM13_IRQHandler
+ B TIM13_IRQHandler
+
+ PUBWEAK TIM14_IRQHandler
+ SECTION .text:CODE:REORDER(1)
+TIM14_IRQHandler
+ B TIM14_IRQHandler
+
+ PUBWEAK TIM5_IRQHandler
+ SECTION .text:CODE:REORDER(1)
+TIM5_IRQHandler
+ B TIM5_IRQHandler
+
+ PUBWEAK SPI3_IRQHandler
+ SECTION .text:CODE:REORDER(1)
+SPI3_IRQHandler
+ B SPI3_IRQHandler
+
+ PUBWEAK TIM6_DAC1_IRQHandler
+ SECTION .text:CODE:REORDER(1)
+TIM6_DAC1_IRQHandler
+ B TIM6_DAC1_IRQHandler
+
+ PUBWEAK TIM7_IRQHandler
+ SECTION .text:CODE:REORDER(1)
+TIM7_IRQHandler
+ B TIM7_IRQHandler
+
+ PUBWEAK DMA2_Channel1_IRQHandler
+ SECTION .text:CODE:REORDER(1)
+DMA2_Channel1_IRQHandler
+ B DMA2_Channel1_IRQHandler
+
+ PUBWEAK DMA2_Channel2_IRQHandler
+ SECTION .text:CODE:REORDER(1)
+DMA2_Channel2_IRQHandler
+ B DMA2_Channel2_IRQHandler
+
+ PUBWEAK DMA2_Channel3_IRQHandler
+ SECTION .text:CODE:REORDER(1)
+DMA2_Channel3_IRQHandler
+ B DMA2_Channel3_IRQHandler
+
+ PUBWEAK DMA2_Channel4_IRQHandler
+ SECTION .text:CODE:REORDER(1)
+DMA2_Channel4_IRQHandler
+ B DMA2_Channel4_IRQHandler
+
+ PUBWEAK DMA2_Channel5_IRQHandler
+ SECTION .text:CODE:REORDER(1)
+DMA2_Channel5_IRQHandler
+ B DMA2_Channel5_IRQHandler
+
+ PUBWEAK SDADC1_IRQHandler
+ SECTION .text:CODE:REORDER(1)
+SDADC1_IRQHandler
+ B SDADC1_IRQHandler
+
+ PUBWEAK SDADC2_IRQHandler
+ SECTION .text:CODE:REORDER(1)
+SDADC2_IRQHandler
+ B SDADC2_IRQHandler
+
+ PUBWEAK SDADC3_IRQHandler
+ SECTION .text:CODE:REORDER(1)
+SDADC3_IRQHandler
+ B SDADC3_IRQHandler
+
+ PUBWEAK COMP_IRQHandler
+ SECTION .text:CODE:REORDER(1)
+COMP_IRQHandler
+ B COMP_IRQHandler
+
+ PUBWEAK USB_HP_IRQHandler
+ SECTION .text:CODE:REORDER(1)
+USB_HP_IRQHandler
+ B USB_HP_IRQHandler
+
+ PUBWEAK USB_LP_IRQHandler
+ SECTION .text:CODE:REORDER(1)
+USB_LP_IRQHandler
+ B USB_LP_IRQHandler
+
+ PUBWEAK USBWakeUp_IRQHandler
+ SECTION .text:CODE:REORDER(1)
+USBWakeUp_IRQHandler
+ B USBWakeUp_IRQHandler
+
+ PUBWEAK TIM19_IRQHandler
+ SECTION .text:CODE:REORDER(1)
+TIM19_IRQHandler
+ B TIM19_IRQHandler
+
+ PUBWEAK FPU_IRQHandler
+ SECTION .text:CODE:REORDER(1)
+FPU_IRQHandler
+ B FPU_IRQHandler
+
+ END
+;************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE*****
diff --git a/Libraries/CMSIS/Device/ST/STM32F37x/Source/Templates/system_stm32f37x.c b/Libraries/CMSIS/Device/ST/STM32F37x/Source/Templates/system_stm32f37x.c
new file mode 100644
index 0000000..f7add14
--- /dev/null
+++ b/Libraries/CMSIS/Device/ST/STM32F37x/Source/Templates/system_stm32f37x.c
@@ -0,0 +1,380 @@
+/**
+ ******************************************************************************
+ * @file system_stm32f37x.c
+ * @author MCD Application Team
+ * @version V1.0.0
+ * @date 20-September-2012
+ * @brief CMSIS Cortex-M4 Device Peripheral Access Layer System Source File.
+ * This file contains the system clock configuration for STM32F37x devices,
+ * and is generated by the clock configuration tool
+ * STM32f37x_Clock_Configuration_V1.0.0.xls
+ *
+ * 1. This file provides two functions and one global variable to be called from
+ * user application:
+ * - SystemInit(): Setups the system clock (System clock source, PLL Multiplier
+ * and Divider factors, AHB/APBx prescalers and Flash settings),
+ * depending on the configuration made in the clock xls tool.
+ * This function is called at startup just after reset and
+ * before branch to main program. This call is made inside
+ * the "startup_stm32f37x.s" file.
+ *
+ * - SystemCoreClock variable: Contains the core clock (HCLK), it can be used
+ * by the user application to setup the SysTick
+ * timer or configure other parameters.
+ *
+ * - SystemCoreClockUpdate(): Updates the variable SystemCoreClock and must
+ * be called whenever the core clock is changed
+ * during program execution.
+ *
+ * 2. After each device reset the HSI (8 MHz Range) is used as system clock source.
+ * Then SystemInit() function is called, in "startup_stm32f37x.s" file, to
+ * configure the system clock before to branch to main program.
+ *
+ * 3. If the system clock source selected by user fails to startup, the SystemInit()
+ * function will do nothing and HSI still used as system clock source. User can
+ * add some code to deal with this issue inside the SetSysClock() function.
+ *
+ * 4. The default value of HSE crystal is set to 8MHz, refer to "HSE_VALUE" defined
+ * in "stm32f37x.h" file. When HSE is used as system clock source, directly or
+ * through PLL, and you are using different crystal you have to adapt the HSE
+ * value to your own configuration.
+ *
+ * 5. This file configures the system clock as follows:
+ *=============================================================================
+ * Supported STM32F37x device
+ *=============================================================================
+ * System Clock source | PLL (HSE)
+ *-----------------------------------------------------------------------------
+ * SYSCLK(Hz) | 72000000
+ *-----------------------------------------------------------------------------
+ * HCLK(Hz) | 72000000
+ *-----------------------------------------------------------------------------
+ * AHB Prescaler | 1
+ *-----------------------------------------------------------------------------
+ * APB2 Prescaler | 1
+ *-----------------------------------------------------------------------------
+ * APB1 Prescaler | 2
+ *-----------------------------------------------------------------------------
+ * HSE Frequency(Hz) | 8000000
+ *----------------------------------------------------------------------------
+ * PLLMUL | 9
+ *-----------------------------------------------------------------------------
+ * PREDIV | 1
+ *-----------------------------------------------------------------------------
+ * USB Clock | DISABLE
+ *-----------------------------------------------------------------------------
+ * Flash Latency(WS) | 2
+ *-----------------------------------------------------------------------------
+ * Prefetch Buffer | ON
+ *-----------------------------------------------------------------------------
+ *=============================================================================
+ ******************************************************************************
+ * @attention
+ *
+ * © COPYRIGHT 2012 STMicroelectronics
+ *
+ * Licensed under MCD-ST Liberty SW License Agreement V2, (the "License");
+ * You may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at:
+ *
+ * http://www.st.com/software_license_agreement_liberty_v2
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ *
+ ******************************************************************************
+ */
+
+/** @addtogroup CMSIS
+ * @{
+ */
+
+/** @addtogroup STM32F37x_System
+ * @{
+ */
+
+/** @addtogroup STM32F37x_System_Private_Includes
+ * @{
+ */
+
+#include "stm32f37x.h"
+
+/**
+ * @}
+ */
+
+/** @addtogroup STM32F37x_System_Private_TypesDefinitions
+ * @{
+ */
+
+/**
+ * @}
+ */
+
+/** @addtogroup STM32F37x_System_Private_Defines
+ * @{
+ */
+
+/*!< Uncomment the following line if you need to relocate your vector Table in
+ Internal SRAM. */
+/* #define VECT_TAB_SRAM */
+#define VECT_TAB_OFFSET 0x0 /*!< Vector Table base offset field.
+ This value must be a multiple of 0x200. */
+/**
+ * @}
+ */
+
+/** @addtogroup STM32F37x_System_Private_Macros
+ * @{
+ */
+
+/**
+ * @}
+ */
+
+/** @addtogroup STM32F37x_System_Private_Variables
+ * @{
+ */
+uint32_t SystemCoreClock = 72000000;
+__I uint8_t AHBPrescTable[16] = {0, 0, 0, 0, 0, 0, 0, 0, 1, 2, 3, 4, 6, 7, 8, 9};
+
+/**
+ * @}
+ */
+
+/** @addtogroup STM32F37x_System_Private_FunctionPrototypes
+ * @{
+ */
+
+static void SetSysClock(void);
+
+/**
+ * @}
+ */
+
+/** @addtogroup STM32F37x_System_Private_Functions
+ * @{
+ */
+
+/**
+ * @brief Setup the microcontrollers system.
+ * Initialize the Embedded Flash Interface, the PLL and update the
+ * SystemCoreClock variable.
+ * @param None
+ * @retval None
+ */
+void SystemInit (void)
+{
+ /* FPU settings ------------------------------------------------------------*/
+ #if (__FPU_PRESENT == 1) && (__FPU_USED == 1)
+ SCB->CPACR |= ((3UL << 10*2)|(3UL << 11*2)); /* set CP10 and CP11 Full Access */
+ #endif
+
+ /* Set HSION bit */
+ RCC->CR |= (uint32_t)0x00000001;
+
+ /* Reset SW[1:0], HPRE[3:0], PPRE[2:0], ADCPRE, SDADCPRE and MCOSEL[2:0] bits */
+ RCC->CFGR &= (uint32_t)0x00FF0000;
+
+ /* Reset HSEON, CSSON and PLLON bits */
+ RCC->CR &= (uint32_t)0xFEF6FFFF;
+
+ /* Reset HSEBYP bit */
+ RCC->CR &= (uint32_t)0xFFFBFFFF;
+
+ /* Reset PLLSRC, PLLXTPRE, PLLMUL and USBPRE bits */
+ RCC->CFGR &= (uint32_t)0xFF80FFFF;
+
+ /* Reset PREDIV1[3:0] bits */
+ RCC->CFGR2 &= (uint32_t)0xFFFFFFF0;
+
+ /* Reset USARTSW[1:0], I2CSW and CECSW bits */
+ RCC->CFGR3 &= (uint32_t)0xFFF0F8C;
+
+ /* Disable all interrupts */
+ RCC->CIR = 0x00000000;
+
+/* Configure the System clock frequency, AHB/APBx prescalers and Flash settings */
+ SetSysClock();
+
+
+#ifdef VECT_TAB_SRAM
+ SCB->VTOR = SRAM_BASE | VECT_TAB_OFFSET; /* Vector Table Relocation in Internal SRAM. */
+#else
+ SCB->VTOR = FLASH_BASE | VECT_TAB_OFFSET; /* Vector Table Relocation in Internal FLASH. */
+#endif
+}
+
+/**
+ * @brief Update SystemCoreClock according to Clock Register Values
+ * The SystemCoreClock variable contains the core clock (HCLK), it can
+ * be used by the user application to setup the SysTick timer or configure
+ * other parameters.
+ *
+ * @note Each time the core clock (HCLK) changes, this function must be called
+ * to update SystemCoreClock variable value. Otherwise, any configuration
+ * based on this variable will be incorrect.
+ *
+ * @note - The system frequency computed by this function is not the real
+ * frequency in the chip. It is calculated based on the predefined
+ * constant and the selected clock source:
+ *
+ * - If SYSCLK source is HSI, SystemCoreClock will contain the HSI_VALUE(*)
+ *
+ * - If SYSCLK source is HSE, SystemCoreClock will contain the HSE_VALUE(**)
+ *
+ * - If SYSCLK source is PLL, SystemCoreClock will contain the HSE_VALUE(**)
+ * or HSI_VALUE(*) multiplied/divided by the PLL factors.
+ *
+ * (*) HSI_VALUE is a constant defined in stm32f37x.h file (default value
+ * 8 MHz) but the real value may vary depending on the variations
+ * in voltage and temperature.
+ *
+ * (**) HSE_VALUE is a constant defined in stm32f37x.h file (default value
+ * 8 MHz), user has to ensure that HSE_VALUE is same as the real
+ * frequency of the crystal used. Otherwise, this function may
+ * have wrong result.
+ *
+ * - The result of this function could be not correct when using fractional
+ * value for HSE crystal.
+ * @param None
+ * @retval None
+ */
+void SystemCoreClockUpdate (void)
+{
+ uint32_t tmp = 0, pllmull = 0, pllsource = 0, prediv1factor = 0;
+
+ /* Get SYSCLK source -------------------------------------------------------*/
+ tmp = RCC->CFGR & RCC_CFGR_SWS;
+
+ switch (tmp)
+ {
+ case 0x00: /* HSI used as system clock */
+ SystemCoreClock = HSI_VALUE;
+ break;
+ case 0x04: /* HSE used as system clock */
+ SystemCoreClock = HSE_VALUE;
+ break;
+ case 0x08: /* PLL used as system clock */
+ /* Get PLL clock source and multiplication factor ----------------------*/
+ pllmull = RCC->CFGR & RCC_CFGR_PLLMULL;
+ pllsource = RCC->CFGR & RCC_CFGR_PLLSRC;
+ pllmull = ( pllmull >> 18) + 2;
+
+ if (pllsource == 0x00)
+ {
+ /* HSI oscillator clock divided by 2 selected as PLL clock entry */
+ SystemCoreClock = (HSI_VALUE >> 1) * pllmull;
+ }
+ else
+ {
+ prediv1factor = (RCC->CFGR2 & RCC_CFGR2_PREDIV1) + 1;
+ /* HSE oscillator clock selected as PREDIV1 clock entry */
+ SystemCoreClock = (HSE_VALUE / prediv1factor) * pllmull;
+ }
+ break;
+ default: /* HSI used as system clock */
+ SystemCoreClock = HSI_VALUE;
+ break;
+ }
+ /* Compute HCLK clock frequency ----------------*/
+ /* Get HCLK prescaler */
+ tmp = AHBPrescTable[((RCC->CFGR & RCC_CFGR_HPRE) >> 4)];
+ /* HCLK clock frequency */
+ SystemCoreClock >>= tmp;
+}
+
+/**
+ * @brief Configures the System clock frequency, AHB/APBx prescalers and Flash
+ * settings.
+ * @note This function should be called only once the RCC clock configuration
+ * is reset to the default reset state (done in SystemInit() function).
+ * @param None
+ * @retval None
+ */
+static void SetSysClock(void)
+{
+ __IO uint32_t StartUpCounter = 0, HSEStatus = 0;
+
+/******************************************************************************/
+/* PLL (clocked by HSE) used as System clock source */
+/******************************************************************************/
+
+ /* SYSCLK, HCLK, PCLK2 and PCLK1 configuration -----------*/
+ /* Enable HSE */
+ RCC->CR |= ((uint32_t)RCC_CR_HSEON);
+
+ /* Wait till HSE is ready and if Time out is reached exit */
+ do
+ {
+ HSEStatus = RCC->CR & RCC_CR_HSERDY;
+ StartUpCounter++;
+ } while((HSEStatus == 0) && (StartUpCounter != HSE_STARTUP_TIMEOUT));
+
+ if ((RCC->CR & RCC_CR_HSERDY) != RESET)
+ {
+ HSEStatus = (uint32_t)0x01;
+ }
+ else
+ {
+ HSEStatus = (uint32_t)0x00;
+ }
+
+ if (HSEStatus == (uint32_t)0x01)
+ {
+ /* Enable Prefetch Buffer and set Flash Latency */
+ FLASH->ACR = FLASH_ACR_PRFTBE | (uint32_t)FLASH_ACR_LATENCY_1;
+
+ /* HCLK = SYSCLK / 1 */
+ RCC->CFGR |= (uint32_t)RCC_CFGR_HPRE_DIV1;
+
+ /* PCLK2 = HCLK / 1 */
+ RCC->CFGR |= (uint32_t)RCC_CFGR_PPRE2_DIV1;
+
+ /* PCLK1 = HCLK / 2 */
+ RCC->CFGR |= (uint32_t)RCC_CFGR_PPRE1_DIV2;
+
+ /* PLL configuration */
+ RCC->CFGR &= (uint32_t)((uint32_t)~(RCC_CFGR_PLLSRC | RCC_CFGR_PLLXTPRE | RCC_CFGR_PLLMULL));
+ RCC->CFGR |= (uint32_t)(RCC_CFGR_PLLSRC_PREDIV1 | RCC_CFGR_PLLXTPRE_PREDIV1 | RCC_CFGR_PLLMULL9);
+
+ /* Enable PLL */
+ RCC->CR |= RCC_CR_PLLON;
+
+ /* Wait till PLL is ready */
+ while((RCC->CR & RCC_CR_PLLRDY) == 0)
+ {
+ }
+
+ /* Select PLL as system clock source */
+ RCC->CFGR &= (uint32_t)((uint32_t)~(RCC_CFGR_SW));
+ RCC->CFGR |= (uint32_t)RCC_CFGR_SW_PLL;
+
+ /* Wait till PLL is used as system clock source */
+ while ((RCC->CFGR & (uint32_t)RCC_CFGR_SWS) != (uint32_t)RCC_CFGR_SWS_PLL)
+ {
+ }
+ }
+ else
+ { /* If HSE fails to start-up, the application will have wrong clock
+ configuration. User can add here some code to deal with this error */
+ }
+}
+
+/**
+ * @}
+ */
+
+/**
+ * @}
+ */
+
+/**
+ * @}
+ */
+
+/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
+
diff --git a/Libraries/CMSIS/Device/ST/STM32L1xx/Include/stm32l1xx.h b/Libraries/CMSIS/Device/ST/STM32L1xx/Include/stm32l1xx.h
new file mode 100644
index 0000000..df5adaa
--- /dev/null
+++ b/Libraries/CMSIS/Device/ST/STM32L1xx/Include/stm32l1xx.h
@@ -0,0 +1,6351 @@
+/**
+ ******************************************************************************
+ * @file stm32l1xx.h
+ * @author MCD Application Team
+ * @version V1.1.1
+ * @date 09-March-2012
+ * @brief CMSIS Cortex-M3 Device Peripheral Access Layer Header File.
+ * This file contains all the peripheral register's definitions, bits
+ * definitions and memory mapping for STM32L1xx High-, Medium-density
+ * and Medium-density Plus devices.
+ *
+ * The file is the unique include file that the application programmer
+ * is using in the C source code, usually in main.c. This file contains:
+ * - Configuration section that allows to select:
+ * - The device used in the target application
+ * - To use or not the peripherals drivers in application code(i.e.
+ * code will be based on direct access to peripherals registers
+ * rather than drivers API), this option is controlled by
+ * "#define USE_STDPERIPH_DRIVER"
+ * - To change few application-specific parameters such as the HSE
+ * crystal frequency
+ * - Data structures and the address mapping for all peripherals
+ * - Peripheral's registers declarations and bits definition
+ * - Macros to access peripherals registers hardware
+ *
+ ******************************************************************************
+ * @attention
+ *
+ * © COPYRIGHT 2012 STMicroelectronics
+ *
+ * Licensed under MCD-ST Liberty SW License Agreement V2, (the "License");
+ * You may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at:
+ *
+ * http://www.st.com/software_license_agreement_liberty_v2
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ *
+ ******************************************************************************
+ */
+
+/** @addtogroup CMSIS
+ * @{
+ */
+
+/** @addtogroup stm32l1xx
+ * @{
+ */
+
+#ifndef __STM32L1XX_H
+#define __STM32L1XX_H
+
+#ifdef __cplusplus
+ extern "C" {
+#endif
+
+/** @addtogroup Library_configuration_section
+ * @{
+ */
+
+/* Uncomment the line below according to the target STM32L device used in your
+ application
+ */
+
+#if !defined (STM32L1XX_MD) && !defined (STM32L1XX_MDP) && !defined (STM32L1XX_HD)
+ /* #define STM32L1XX_MD */ /*!< STM32L1XX_MD: STM32L Ultra Low Power Medium-density devices */
+ /* #define STM32L1XX_MDP */ /*!< STM32L1XX_MDP: STM32L Ultra Low Power Medium-density Plus devices */
+ #define STM32L1XX_HD /*!< STM32L1XX_HD: STM32L Ultra Low Power High-density devices */
+#endif
+/* Tip: To avoid modifying this file each time you need to switch between these
+ devices, you can define the device in your toolchain compiler preprocessor.
+
+ - Ultra Low Power Medium-density devices are STM32L151xx and STM32L152xx
+ microcontrollers where the Flash memory density ranges between 64 and 128 Kbytes.
+ - Ultra Low Power Medium-density Plus devices are STM32L151xx, STM32L152xx and
+ STM32L162xx microcontrollers where the Flash memory density is 256 Kbytes.
+ - Ultra Low Power High-density devices are STM32L151xx, STM32L152xx and STM32L162xx
+ microcontrollers where the Flash memory density is 384 Kbytes.
+ */
+
+#if !defined (STM32L1XX_MD) && !defined (STM32L1XX_MDP) && !defined (STM32L1XX_HD)
+ #error "Please select first the target STM32L1xx device used in your application (in stm32l1xx.h file)"
+#endif
+
+#if !defined USE_STDPERIPH_DRIVER
+/**
+ * @brief Comment the line below if you will not use the peripherals drivers.
+ In this case, these drivers will not be included and the application code will
+ be based on direct access to peripherals registers
+ */
+ /*#define USE_STDPERIPH_DRIVER*/
+#endif
+
+/**
+ * @brief In the following line adjust the value of External High Speed oscillator (HSE)
+ used in your application
+
+ Tip: To avoid modifying this file each time you need to use different HSE, you
+ can define the HSE value in your toolchain compiler preprocessor.
+ */
+#if !defined (HSE_VALUE)
+#define HSE_VALUE ((uint32_t)8000000) /*!< Value of the External oscillator in Hz */
+#endif
+
+/**
+ * @brief In the following line adjust the External High Speed oscillator (HSE) Startup
+ Timeout value
+ */
+#if !defined (HSE_STARTUP_TIMEOUT)
+#define HSE_STARTUP_TIMEOUT ((uint16_t)0x0500) /*!< Time out for HSE start up */
+#endif
+
+/**
+ * @brief In the following line adjust the Internal High Speed oscillator (HSI) Startup
+ Timeout value
+ */
+#if !defined (HSI_STARTUP_TIMEOUT)
+#define HSI_STARTUP_TIMEOUT ((uint16_t)0x0500) /*!< Time out for HSI start up */
+#endif
+
+#if !defined (HSI_VALUE)
+#define HSI_VALUE ((uint32_t)16000000) /*!< Value of the Internal High Speed oscillator in Hz.
+ The real value may vary depending on the variations
+ in voltage and temperature. */
+#endif
+
+#if !defined (LSI_VALUE)
+#define LSI_VALUE ((uint32_t)37000) /*!< Value of the Internal Low Speed oscillator in Hz
+ The real value may vary depending on the variations
+ in voltage and temperature. */
+#endif
+
+#if !defined (LSE_VALUE)
+#define LSE_VALUE ((uint32_t)32768) /*!< Value of the External Low Speed oscillator in Hz */
+#endif
+
+/**
+ * @brief STM32L1xx Standard Peripheral Library version number V1.1.1
+ */
+#define __STM32L1XX_STDPERIPH_VERSION_MAIN (0x01) /*!< [31:24] main version */
+#define __STM32L1XX_STDPERIPH_VERSION_SUB1 (0x01) /*!< [23:16] sub1 version */
+#define __STM32L1XX_STDPERIPH_VERSION_SUB2 (0x01) /*!< [15:8] sub2 version */
+#define __STM32L1XX_STDPERIPH_VERSION_RC (0x00) /*!< [7:0] release candidate */
+#define __STM32L1XX_STDPERIPH_VERSION ( (__STM32L1XX_STDPERIPH_VERSION_MAIN << 24)\
+ |(__STM32L1XX_STDPERIPH_VERSION_SUB1 << 16)\
+ |(__STM32L1XX_STDPERIPH_VERSION_SUB2 << 8)\
+ |(__STM32L1XX_STDPERIPH_VERSION_RC))
+
+/**
+ * @}
+ */
+
+/** @addtogroup Configuration_section_for_CMSIS
+ * @{
+ */
+
+/**
+ * @brief STM32L1xx Interrupt Number Definition, according to the selected device
+ * in @ref Library_configuration_section
+ */
+#define __CM3_REV 0x200 /*!< Cortex-M3 Revision r2p0 */
+#define __MPU_PRESENT 1 /*!< STM32L provides MPU */
+#define __NVIC_PRIO_BITS 4 /*!< STM32 uses 4 Bits for the Priority Levels */
+#define __Vendor_SysTickConfig 0 /*!< Set to 1 if different SysTick Config is used */
+
+/*!< Interrupt Number Definition */
+typedef enum IRQn
+{
+/****** Cortex-M3 Processor Exceptions Numbers ******************************************************/
+ NonMaskableInt_IRQn = -14, /*!< 2 Non Maskable Interrupt */
+ MemoryManagement_IRQn = -12, /*!< 4 Cortex-M3 Memory Management Interrupt */
+ BusFault_IRQn = -11, /*!< 5 Cortex-M3 Bus Fault Interrupt */
+ UsageFault_IRQn = -10, /*!< 6 Cortex-M3 Usage Fault Interrupt */
+ SVC_IRQn = -5, /*!< 11 Cortex-M3 SV Call Interrupt */
+ DebugMonitor_IRQn = -4, /*!< 12 Cortex-M3 Debug Monitor Interrupt */
+ PendSV_IRQn = -2, /*!< 14 Cortex-M3 Pend SV Interrupt */
+ SysTick_IRQn = -1, /*!< 15 Cortex-M3 System Tick Interrupt */
+
+/****** STM32L specific Interrupt Numbers ***********************************************************/
+ WWDG_IRQn = 0, /*!< Window WatchDog Interrupt */
+ PVD_IRQn = 1, /*!< PVD through EXTI Line detection Interrupt */
+ TAMPER_STAMP_IRQn = 2, /*!< Tamper and Time Stamp through EXTI Line Interrupts */
+ RTC_WKUP_IRQn = 3, /*!< RTC Wakeup Timer through EXTI Line Interrupt */
+ FLASH_IRQn = 4, /*!< FLASH global Interrupt */
+ RCC_IRQn = 5, /*!< RCC global Interrupt */
+ EXTI0_IRQn = 6, /*!< EXTI Line0 Interrupt */
+ EXTI1_IRQn = 7, /*!< EXTI Line1 Interrupt */
+ EXTI2_IRQn = 8, /*!< EXTI Line2 Interrupt */
+ EXTI3_IRQn = 9, /*!< EXTI Line3 Interrupt */
+ EXTI4_IRQn = 10, /*!< EXTI Line4 Interrupt */
+ DMA1_Channel1_IRQn = 11, /*!< DMA1 Channel 1 global Interrupt */
+ DMA1_Channel2_IRQn = 12, /*!< DMA1 Channel 2 global Interrupt */
+ DMA1_Channel3_IRQn = 13, /*!< DMA1 Channel 3 global Interrupt */
+ DMA1_Channel4_IRQn = 14, /*!< DMA1 Channel 4 global Interrupt */
+ DMA1_Channel5_IRQn = 15, /*!< DMA1 Channel 5 global Interrupt */
+ DMA1_Channel6_IRQn = 16, /*!< DMA1 Channel 6 global Interrupt */
+ DMA1_Channel7_IRQn = 17, /*!< DMA1 Channel 7 global Interrupt */
+ ADC1_IRQn = 18, /*!< ADC1 global Interrupt */
+ USB_HP_IRQn = 19, /*!< USB High Priority Interrupt */
+ USB_LP_IRQn = 20, /*!< USB Low Priority Interrupt */
+ DAC_IRQn = 21, /*!< DAC Interrupt */
+ COMP_IRQn = 22, /*!< Comparator through EXTI Line Interrupt */
+ EXTI9_5_IRQn = 23, /*!< External Line[9:5] Interrupts */
+ LCD_IRQn = 24, /*!< LCD Interrupt */
+ TIM9_IRQn = 25, /*!< TIM9 global Interrupt */
+ TIM10_IRQn = 26, /*!< TIM10 global Interrupt */
+ TIM11_IRQn = 27, /*!< TIM11 global Interrupt */
+ TIM2_IRQn = 28, /*!< TIM2 global Interrupt */
+ TIM3_IRQn = 29, /*!< TIM3 global Interrupt */
+ TIM4_IRQn = 30, /*!< TIM4 global Interrupt */
+ I2C1_EV_IRQn = 31, /*!< I2C1 Event Interrupt */
+ I2C1_ER_IRQn = 32, /*!< I2C1 Error Interrupt */
+ I2C2_EV_IRQn = 33, /*!< I2C2 Event Interrupt */
+ I2C2_ER_IRQn = 34, /*!< I2C2 Error Interrupt */
+ SPI1_IRQn = 35, /*!< SPI1 global Interrupt */
+ SPI2_IRQn = 36, /*!< SPI2 global Interrupt */
+ USART1_IRQn = 37, /*!< USART1 global Interrupt */
+ USART2_IRQn = 38, /*!< USART2 global Interrupt */
+ USART3_IRQn = 39, /*!< USART3 global Interrupt */
+ EXTI15_10_IRQn = 40, /*!< External Line[15:10] Interrupts */
+ RTC_Alarm_IRQn = 41, /*!< RTC Alarm through EXTI Line Interrupt */
+ USB_FS_WKUP_IRQn = 42, /*!< USB FS WakeUp from suspend through EXTI Line Interrupt */
+ TIM6_IRQn = 43, /*!< TIM6 global Interrupt */
+#ifdef STM32L1XX_MD
+ TIM7_IRQn = 44 /*!< TIM7 global Interrupt */
+#endif
+
+#ifdef STM32L1XX_MDP
+ TIM7_IRQn = 44, /*!< TIM7 global Interrupt */
+ TIM5_IRQn = 46, /*!< TIM5 global Interrupt */
+ SPI3_IRQn = 47, /*!< SPI3 global Interrupt */
+ DMA2_Channel1_IRQn = 50, /*!< DMA2 Channel 1 global Interrupt */
+ DMA2_Channel2_IRQn = 51, /*!< DMA2 Channel 2 global Interrupt */
+ DMA2_Channel3_IRQn = 52, /*!< DMA2 Channel 3 global Interrupt */
+ DMA2_Channel4_IRQn = 53, /*!< DMA2 Channel 4 global Interrupt */
+ DMA2_Channel5_IRQn = 54, /*!< DMA2 Channel 5 global Interrupt */
+ AES_IRQn = 55, /*!< AES global Interrupt */
+ COMP_ACQ_IRQn = 56 /*!< Comparator Channel Acquisition global Interrupt */
+#endif
+
+#ifdef STM32L1XX_HD
+ TIM7_IRQn = 44, /*!< TIM7 global Interrupt */
+ SDIO_IRQn = 45, /*!< SDIO global Interrupt */
+ TIM5_IRQn = 46, /*!< TIM5 global Interrupt */
+ SPI3_IRQn = 47, /*!< SPI3 global Interrupt */
+ UART4_IRQn = 48, /*!< UART4 global Interrupt */
+ UART5_IRQn = 49, /*!< UART5 global Interrupt */
+ DMA2_Channel1_IRQn = 50, /*!< DMA2 Channel 1 global Interrupt */
+ DMA2_Channel2_IRQn = 51, /*!< DMA2 Channel 2 global Interrupt */
+ DMA2_Channel3_IRQn = 52, /*!< DMA2 Channel 3 global Interrupt */
+ DMA2_Channel4_IRQn = 53, /*!< DMA2 Channel 4 global Interrupt */
+ DMA2_Channel5_IRQn = 54, /*!< DMA2 Channel 5 global Interrupt */
+ AES_IRQn = 55, /*!< AES global Interrupt */
+ COMP_ACQ_IRQn = 56 /*!< Comparator Channel Acquisition global Interrupt */
+#endif
+} IRQn_Type;
+
+/**
+ * @}
+ */
+
+#include "core_cm3.h"
+#include "system_stm32l1xx.h"
+#include
+
+
\ No newline at end of file
diff --git a/Libraries/CMSIS/Device/ST/STM32L1xx/Source/Templates/TASKING/cstart_thumb2.asm b/Libraries/CMSIS/Device/ST/STM32L1xx/Source/Templates/TASKING/cstart_thumb2.asm
new file mode 100644
index 0000000..85626cd
--- /dev/null
+++ b/Libraries/CMSIS/Device/ST/STM32L1xx/Source/Templates/TASKING/cstart_thumb2.asm
@@ -0,0 +1,140 @@
+
+
+;; NOTE: To allow the use of this file for both ARMv6M and ARMv7M,
+;; we will only use 16-bit Thumb intructions.
+
+ .extern _lc_ub_stack ; usr/sys mode stack pointer
+ .extern _lc_ue_stack ; symbol required by debugger
+ .extern _lc_ub_table ; ROM to RAM copy table
+ .extern main
+ .extern _Exit
+ .extern exit
+ .weak exit
+ .global __get_argcv
+ .weak __get_argcv
+ .extern __argcvbuf
+ .weak __argcvbuf
+ ;;.extern __init_hardware
+ .extern SystemInit
+
+ .if @defined('__PROF_ENABLE__')
+ .extern __prof_init
+ .endif
+ .if @defined('__POSIX__')
+ .extern posix_main
+ .extern _posix_boot_stack_top
+ .endif
+
+ .global _START
+
+ .section .text.cstart
+
+ .thumb
+_START:
+ ;; anticipate possible ROM/RAM remapping
+ ;; by loading the 'real' program address
+ ldr r1,=_Next
+ bx r1
+_Next:
+ ;; initialize the stack pointer
+ ldr r1,=_lc_ub_stack ; TODO: make this part of the vector table
+ mov sp,r1
+
+ ;; call a user function which initializes function.
+ bl SystemInit
+
+ ;; copy initialized sections from ROM to RAM
+ ;; and clear uninitialized data sections in RAM
+
+ ldr r3,=_lc_ub_table
+ movs r0,#0
+cploop:
+ ldr r4,[r3,#0] ; load type
+ ldr r5,[r3,#4] ; dst address
+ ldr r6,[r3,#8] ; src address
+ ldr r7,[r3,#12] ; size
+
+ cmp r4,#1
+ beq copy
+ cmp r4,#2
+ beq clear
+ b done
+
+copy:
+ subs r7,r7,#1
+ ldrb r1,[r6,r7]
+ strb r1,[r5,r7]
+ bne copy
+
+ adds r3,r3,#16
+ b cploop
+
+clear:
+ subs r7,r7,#1
+ strb r0,[r5,r7]
+ bne clear
+
+ adds r3,r3,#16
+ b cploop
+
+done:
+
+ .if @defined('__POSIX__')
+
+ ;; posix stack buffer for system upbringing
+ ldr r0,=_posix_boot_stack_top
+ ldr r0, [r0]
+ mov sp,r0
+
+ .else
+
+ ;; load r10 with end of USR/SYS stack, which is
+ ;; needed in case stack overflow checking is on
+ ;; NOTE: use 16-bit instructions only, for ARMv6M
+ ldr r0,=_lc_ue_stack
+ mov r10,r0
+
+ .endif
+
+ .if @defined('__PROF_ENABLE__')
+ bl __prof_init
+ .endif
+
+ .if @defined('__POSIX__')
+ ;; call posix_main with no arguments
+ bl posix_main
+ .else
+ ;; retrieve argc and argv (default argv[0]==NULL & argc==0)
+ bl __get_argcv
+ ldr r1,=__argcvbuf
+ ;; call main
+ bl main
+ .endif
+
+ ;; call exit using the return value from main()
+ ;; Note. Calling exit will also run all functions
+ ;; that were supplied through atexit().
+ bl exit
+
+__get_argcv: ; weak definition
+ movs r0,#0
+ bx lr
+
+ .ltorg
+ .endsec
+
+ .calls '_START', ' '
+ .calls '_START','__init_vector_table'
+ .if @defined('__PROF_ENABLE__')
+ .calls '_START','__prof_init'
+ .endif
+ .if @defined('__POSIX__')
+ .calls '_START','posix_main'
+ .else
+ .calls '_START','__get_argcv'
+ .calls '_START','main'
+ .endif
+ .calls '_START','exit'
+ .calls '_START','',0
+
+ .end
diff --git a/Libraries/CMSIS/Device/ST/STM32L1xx/Source/Templates/TrueSTUDIO/startup_stm32l1xx_hd.s b/Libraries/CMSIS/Device/ST/STM32L1xx/Source/Templates/TrueSTUDIO/startup_stm32l1xx_hd.s
new file mode 100644
index 0000000..45aefde
--- /dev/null
+++ b/Libraries/CMSIS/Device/ST/STM32L1xx/Source/Templates/TrueSTUDIO/startup_stm32l1xx_hd.s
@@ -0,0 +1,424 @@
+/**
+ ******************************************************************************
+ * @file startup_stm32l1xx_hd.s
+ * @author MCD Application Team
+ * @version V1.1.1
+ * @date 09-March-2012
+ * @brief STM32L1xx Ultra Low Power High-density Devices vector table for
+ * Atollic toolchain.
+ * This module performs:
+ * - Set the initial SP
+ * - Set the initial PC == Reset_Handler,
+ * - Set the vector table entries with the exceptions ISR address
+ * - Configure the clock system
+ * - Branches to main in the C library (which eventually
+ * calls main()).
+ * After Reset the Cortex-M3 processor is in Thread mode,
+ * priority is Privileged, and the Stack is set to Main.
+ ******************************************************************************
+ * @attention
+ *
+ *
+
+
+
+
+
+
+
+
|
+
© COPYRIGHT 2012 STMicroelectronics
+ *
+ * Licensed under MCD-ST Liberty SW License Agreement V2, (the "License");
+ * You may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at:
+ *
+ * http://www.st.com/software_license_agreement_liberty_v2
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ *
+ ******************************************************************************
+ */
+
+ .syntax unified
+ .cpu cortex-m3
+ .fpu softvfp
+ .thumb
+
+.global g_pfnVectors
+.global Default_Handler
+
+/* start address for the initialization values of the .data section.
+defined in linker script */
+.word _sidata
+/* start address for the .data section. defined in linker script */
+.word _sdata
+/* end address for the .data section. defined in linker script */
+.word _edata
+/* start address for the .bss section. defined in linker script */
+.word _sbss
+/* end address for the .bss section. defined in linker script */
+.word _ebss
+
+.equ BootRAM, 0xF108F85F
+/**
+ * @brief This is the code that gets called when the processor first
+ * starts execution following a reset event. Only the absolutely
+ * necessary set is performed, after which the application
+ * supplied main() routine is called.
+ * @param None
+ * @retval : None
+*/
+
+ .section .text.Reset_Handler
+ .weak Reset_Handler
+ .type Reset_Handler, %function
+Reset_Handler:
+
+/* Copy the data segment initializers from flash to SRAM */
+ movs r1, #0
+ b LoopCopyDataInit
+
+CopyDataInit:
+ ldr r3, =_sidata
+ ldr r3, [r3, r1]
+ str r3, [r0, r1]
+ adds r1, r1, #4
+
+LoopCopyDataInit:
+ ldr r0, =_sdata
+ ldr r3, =_edata
+ adds r2, r0, r1
+ cmp r2, r3
+ bcc CopyDataInit
+ ldr r2, =_sbss
+ b LoopFillZerobss
+/* Zero fill the bss segment. */
+FillZerobss:
+ movs r3, #0
+ str r3, [r2], #4
+
+LoopFillZerobss:
+ ldr r3, = _ebss
+ cmp r2, r3
+ bcc FillZerobss
+
+/* Call the clock system intitialization function.*/
+ bl SystemInit
+/* Call static constructors */
+ bl __libc_init_array
+/* Call the application's entry point.*/
+ bl main
+ bx lr
+.size Reset_Handler, .-Reset_Handler
+
+/**
+ * @brief This is the code that gets called when the processor receives an
+ * unexpected interrupt. This simply enters an infinite loop, preserving
+ * the system state for examination by a debugger.
+ *
+ * @param None
+ * @retval : None
+*/
+ .section .text.Default_Handler,"ax",%progbits
+Default_Handler:
+Infinite_Loop:
+ b Infinite_Loop
+ .size Default_Handler, .-Default_Handler
+/******************************************************************************
+*
+* The minimal vector table for a Cortex M3. Note that the proper constructs
+* must be placed on this to ensure that it ends up at physical address
+* 0x0000.0000.
+*
+******************************************************************************/
+ .section .isr_vector,"a",%progbits
+ .type g_pfnVectors, %object
+ .size g_pfnVectors, .-g_pfnVectors
+
+
+g_pfnVectors:
+ .word _estack
+ .word Reset_Handler
+ .word NMI_Handler
+ .word HardFault_Handler
+ .word MemManage_Handler
+ .word BusFault_Handler
+ .word UsageFault_Handler
+ .word 0
+ .word 0
+ .word 0
+ .word 0
+ .word SVC_Handler
+ .word DebugMon_Handler
+ .word 0
+ .word PendSV_Handler
+ .word SysTick_Handler
+ .word WWDG_IRQHandler
+ .word PVD_IRQHandler
+ .word TAMPER_STAMP_IRQHandler
+ .word RTC_WKUP_IRQHandler
+ .word FLASH_IRQHandler
+ .word RCC_IRQHandler
+ .word EXTI0_IRQHandler
+ .word EXTI1_IRQHandler
+ .word EXTI2_IRQHandler
+ .word EXTI3_IRQHandler
+ .word EXTI4_IRQHandler
+ .word DMA1_Channel1_IRQHandler
+ .word DMA1_Channel2_IRQHandler
+ .word DMA1_Channel3_IRQHandler
+ .word DMA1_Channel4_IRQHandler
+ .word DMA1_Channel5_IRQHandler
+ .word DMA1_Channel6_IRQHandler
+ .word DMA1_Channel7_IRQHandler
+ .word ADC1_IRQHandler
+ .word USB_HP_IRQHandler
+ .word USB_LP_IRQHandler
+ .word DAC_IRQHandler
+ .word COMP_IRQHandler
+ .word EXTI9_5_IRQHandler
+ .word LCD_IRQHandler
+ .word TIM9_IRQHandler
+ .word TIM10_IRQHandler
+ .word TIM11_IRQHandler
+ .word TIM2_IRQHandler
+ .word TIM3_IRQHandler
+ .word TIM4_IRQHandler
+ .word I2C1_EV_IRQHandler
+ .word I2C1_ER_IRQHandler
+ .word I2C2_EV_IRQHandler
+ .word I2C2_ER_IRQHandler
+ .word SPI1_IRQHandler
+ .word SPI2_IRQHandler
+ .word USART1_IRQHandler
+ .word USART2_IRQHandler
+ .word USART3_IRQHandler
+ .word EXTI15_10_IRQHandler
+ .word RTC_Alarm_IRQHandler
+ .word USB_FS_WKUP_IRQHandler
+ .word TIM6_IRQHandler
+ .word TIM7_IRQHandler
+ .word SDIO_IRQHandler
+ .word TIM5_IRQHandler
+ .word SPI3_IRQHandler
+ .word UART4_IRQHandler
+ .word UART5_IRQHandler
+ .word DMA2_Channel1_IRQHandler
+ .word DMA2_Channel2_IRQHandler
+ .word DMA2_Channel3_IRQHandler
+ .word DMA2_Channel4_IRQHandler
+ .word DMA2_Channel5_IRQHandler
+ .word AES_IRQHandler
+ .word COMP_ACQ_IRQHandler
+ .word 0
+ .word 0
+ .word 0
+ .word 0
+ .word 0
+ .word BootRAM /* @0x108. This is for boot in RAM mode for
+ STM32L15x ULtra Low Power High-density devices. */
+
+/*******************************************************************************
+*
+* Provide weak aliases for each Exception handler to the Default_Handler.
+* As they are weak aliases, any function with the same name will override
+* this definition.
+*
+*******************************************************************************/
+
+ .weak NMI_Handler
+ .thumb_set NMI_Handler,Default_Handler
+
+ .weak HardFault_Handler
+ .thumb_set HardFault_Handler,Default_Handler
+
+ .weak MemManage_Handler
+ .thumb_set MemManage_Handler,Default_Handler
+
+ .weak BusFault_Handler
+ .thumb_set BusFault_Handler,Default_Handler
+
+ .weak UsageFault_Handler
+ .thumb_set UsageFault_Handler,Default_Handler
+
+ .weak SVC_Handler
+ .thumb_set SVC_Handler,Default_Handler
+
+ .weak DebugMon_Handler
+ .thumb_set DebugMon_Handler,Default_Handler
+
+ .weak PendSV_Handler
+ .thumb_set PendSV_Handler,Default_Handler
+
+ .weak SysTick_Handler
+ .thumb_set SysTick_Handler,Default_Handler
+
+ .weak WWDG_IRQHandler
+ .thumb_set WWDG_IRQHandler,Default_Handler
+
+ .weak PVD_IRQHandler
+ .thumb_set PVD_IRQHandler,Default_Handler
+
+ .weak TAMPER_STAMP_IRQHandler
+ .thumb_set TAMPER_STAMP_IRQHandler,Default_Handler
+
+ .weak RTC_WKUP_IRQHandler
+ .thumb_set RTC_WKUP_IRQHandler,Default_Handler
+
+ .weak FLASH_IRQHandler
+ .thumb_set FLASH_IRQHandler,Default_Handler
+
+ .weak RCC_IRQHandler
+ .thumb_set RCC_IRQHandler,Default_Handler
+
+ .weak EXTI0_IRQHandler
+ .thumb_set EXTI0_IRQHandler,Default_Handler
+
+ .weak EXTI1_IRQHandler
+ .thumb_set EXTI1_IRQHandler,Default_Handler
+
+ .weak EXTI2_IRQHandler
+ .thumb_set EXTI2_IRQHandler,Default_Handler
+
+ .weak EXTI3_IRQHandler
+ .thumb_set EXTI3_IRQHandler,Default_Handler
+
+ .weak EXTI4_IRQHandler
+ .thumb_set EXTI4_IRQHandler,Default_Handler
+
+ .weak DMA1_Channel1_IRQHandler
+ .thumb_set DMA1_Channel1_IRQHandler,Default_Handler
+
+ .weak DMA1_Channel2_IRQHandler
+ .thumb_set DMA1_Channel2_IRQHandler,Default_Handler
+
+ .weak DMA1_Channel3_IRQHandler
+ .thumb_set DMA1_Channel3_IRQHandler,Default_Handler
+
+ .weak DMA1_Channel4_IRQHandler
+ .thumb_set DMA1_Channel4_IRQHandler,Default_Handler
+
+ .weak DMA1_Channel5_IRQHandler
+ .thumb_set DMA1_Channel5_IRQHandler,Default_Handler
+
+ .weak DMA1_Channel6_IRQHandler
+ .thumb_set DMA1_Channel6_IRQHandler,Default_Handler
+
+ .weak DMA1_Channel7_IRQHandler
+ .thumb_set DMA1_Channel7_IRQHandler,Default_Handler
+
+ .weak ADC1_IRQHandler
+ .thumb_set ADC1_IRQHandler,Default_Handler
+
+ .weak USB_HP_IRQHandler
+ .thumb_set USB_HP_IRQHandler,Default_Handler
+
+ .weak USB_LP_IRQHandler
+ .thumb_set USB_LP_IRQHandler,Default_Handler
+
+ .weak DAC_IRQHandler
+ .thumb_set DAC_IRQHandler,Default_Handler
+
+ .weak COMP_IRQHandler
+ .thumb_set COMP_IRQHandler,Default_Handler
+
+ .weak EXTI9_5_IRQHandler
+ .thumb_set EXTI9_5_IRQHandler,Default_Handler
+
+ .weak LCD_IRQHandler
+ .thumb_set LCD_IRQHandler,Default_Handler
+
+ .weak TIM9_IRQHandler
+ .thumb_set TIM9_IRQHandler,Default_Handler
+
+ .weak TIM10_IRQHandler
+ .thumb_set TIM10_IRQHandler,Default_Handler
+
+ .weak TIM11_IRQHandler
+ .thumb_set TIM11_IRQHandler,Default_Handler
+
+ .weak TIM2_IRQHandler
+ .thumb_set TIM2_IRQHandler,Default_Handler
+
+ .weak TIM3_IRQHandler
+ .thumb_set TIM3_IRQHandler,Default_Handler
+
+ .weak TIM4_IRQHandler
+ .thumb_set TIM4_IRQHandler,Default_Handler
+
+ .weak I2C1_EV_IRQHandler
+ .thumb_set I2C1_EV_IRQHandler,Default_Handler
+
+ .weak I2C1_ER_IRQHandler
+ .thumb_set I2C1_ER_IRQHandler,Default_Handler
+
+ .weak I2C2_EV_IRQHandler
+ .thumb_set I2C2_EV_IRQHandler,Default_Handler
+
+ .weak I2C2_ER_IRQHandler
+ .thumb_set I2C2_ER_IRQHandler,Default_Handler
+
+ .weak SPI1_IRQHandler
+ .thumb_set SPI1_IRQHandler,Default_Handler
+
+ .weak SPI2_IRQHandler
+ .thumb_set SPI2_IRQHandler,Default_Handler
+
+ .weak USART1_IRQHandler
+ .thumb_set USART1_IRQHandler,Default_Handler
+
+ .weak USART2_IRQHandler
+ .thumb_set USART2_IRQHandler,Default_Handler
+
+ .weak USART3_IRQHandler
+ .thumb_set USART3_IRQHandler,Default_Handler
+
+ .weak EXTI15_10_IRQHandler
+ .thumb_set EXTI15_10_IRQHandler,Default_Handler
+
+ .weak RTC_Alarm_IRQHandler
+ .thumb_set RTC_Alarm_IRQHandler,Default_Handler
+
+ .weak USB_FS_WKUP_IRQHandler
+ .thumb_set USB_FS_WKUP_IRQHandler,Default_Handler
+
+ .weak TIM6_IRQHandler
+ .thumb_set TIM6_IRQHandler,Default_Handler
+
+ .weak TIM7_IRQHandler
+ .thumb_set TIM7_IRQHandler,Default_Handler
+
+ .weak SDIO_IRQHandler
+ .thumb_set SDIO_IRQHandler,Default_Handler
+
+ .weak TIM5_IRQHandler
+ .thumb_set TIM5_IRQHandler,Default_Handler
+
+ .weak SPI3_IRQHandler
+ .thumb_set SPI3_IRQHandler,Default_Handler
+
+ .weak UART4_IRQHandler
+ .thumb_set UART4_IRQHandler,Default_Handler
+
+ .weak UART5_IRQHandler
+ .thumb_set UART5_IRQHandler,Default_Handler
+
+ .weak DMA2_Channel1_IRQHandler
+ .thumb_set DMA2_Channel1_IRQHandler,Default_Handler
+
+ .weak DMA2_Channel2_IRQHandler
+ .thumb_set DMA2_Channel2_IRQHandler,Default_Handler
+
+ .weak DMA2_Channel3_IRQHandler
+ .thumb_set DMA2_Channel3_IRQHandler,Default_Handler
+
+ .weak DMA2_Channel4_IRQHandler
+ .thumb_set DMA2_Channel4_IRQHandler,Default_Handler
+
+ .weak DMA2_Channel5_IRQHandler
+ .thumb_set DMA2_Channel5_IRQHandler,Default_Handler
+
+ .weak AES_IRQHandler
+ .thumb_set AES_IRQHandler,Default_Handler
+
+ .weak COMP_ACQ_IRQHandler
+ .thumb_set COMP_ACQ_IRQHandler,Default_Handler
+
+/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
+
diff --git a/Libraries/CMSIS/Device/ST/STM32L1xx/Source/Templates/TrueSTUDIO/startup_stm32l1xx_md.s b/Libraries/CMSIS/Device/ST/STM32L1xx/Source/Templates/TrueSTUDIO/startup_stm32l1xx_md.s
new file mode 100644
index 0000000..91a0c7d
--- /dev/null
+++ b/Libraries/CMSIS/Device/ST/STM32L1xx/Source/Templates/TrueSTUDIO/startup_stm32l1xx_md.s
@@ -0,0 +1,376 @@
+/**
+ ******************************************************************************
+ * @file startup_stm32l1xx_md.s
+ * @author MCD Application Team
+ * @version V1.1.1
+ * @date 09-March-2012
+ * @brief STM32L1xx Ultra Low Power Medium-density Devices vector table for
+ * Atollic toolchain.
+ * This module performs:
+ * - Set the initial SP
+ * - Set the initial PC == Reset_Handler,
+ * - Set the vector table entries with the exceptions ISR address
+ * - Configure the clock system
+ * - Branches to main in the C library (which eventually
+ * calls main()).
+ * After Reset the Cortex-M3 processor is in Thread mode,
+ * priority is Privileged, and the Stack is set to Main.
+ ******************************************************************************
+ * @attention
+ *
+ * © COPYRIGHT 2012 STMicroelectronics
+ *
+ * Licensed under MCD-ST Liberty SW License Agreement V2, (the "License");
+ * You may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at:
+ *
+ * http://www.st.com/software_license_agreement_liberty_v2
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ *
+ ******************************************************************************
+ */
+
+ .syntax unified
+ .cpu cortex-m3
+ .fpu softvfp
+ .thumb
+
+.global g_pfnVectors
+.global Default_Handler
+
+/* start address for the initialization values of the .data section.
+defined in linker script */
+.word _sidata
+/* start address for the .data section. defined in linker script */
+.word _sdata
+/* end address for the .data section. defined in linker script */
+.word _edata
+/* start address for the .bss section. defined in linker script */
+.word _sbss
+/* end address for the .bss section. defined in linker script */
+.word _ebss
+
+.equ BootRAM, 0xF108F85F
+/**
+ * @brief This is the code that gets called when the processor first
+ * starts execution following a reset event. Only the absolutely
+ * necessary set is performed, after which the application
+ * supplied main() routine is called.
+ * @param None
+ * @retval : None
+*/
+
+ .section .text.Reset_Handler
+ .weak Reset_Handler
+ .type Reset_Handler, %function
+Reset_Handler:
+
+/* Copy the data segment initializers from flash to SRAM */
+ movs r1, #0
+ b LoopCopyDataInit
+
+CopyDataInit:
+ ldr r3, =_sidata
+ ldr r3, [r3, r1]
+ str r3, [r0, r1]
+ adds r1, r1, #4
+
+LoopCopyDataInit:
+ ldr r0, =_sdata
+ ldr r3, =_edata
+ adds r2, r0, r1
+ cmp r2, r3
+ bcc CopyDataInit
+ ldr r2, =_sbss
+ b LoopFillZerobss
+/* Zero fill the bss segment. */
+FillZerobss:
+ movs r3, #0
+ str r3, [r2], #4
+
+LoopFillZerobss:
+ ldr r3, = _ebss
+ cmp r2, r3
+ bcc FillZerobss
+
+/* Call the clock system intitialization function.*/
+ bl SystemInit
+/* Call static constructors */
+ bl __libc_init_array
+/* Call the application's entry point.*/
+ bl main
+ bx lr
+.size Reset_Handler, .-Reset_Handler
+
+/**
+ * @brief This is the code that gets called when the processor receives an
+ * unexpected interrupt. This simply enters an infinite loop, preserving
+ * the system state for examination by a debugger.
+ *
+ * @param None
+ * @retval : None
+*/
+ .section .text.Default_Handler,"ax",%progbits
+Default_Handler:
+Infinite_Loop:
+ b Infinite_Loop
+ .size Default_Handler, .-Default_Handler
+/******************************************************************************
+*
+* The minimal vector table for a Cortex M3. Note that the proper constructs
+* must be placed on this to ensure that it ends up at physical address
+* 0x0000.0000.
+*
+******************************************************************************/
+ .section .isr_vector,"a",%progbits
+ .type g_pfnVectors, %object
+ .size g_pfnVectors, .-g_pfnVectors
+
+
+g_pfnVectors:
+ .word _estack
+ .word Reset_Handler
+ .word NMI_Handler
+ .word HardFault_Handler
+ .word MemManage_Handler
+ .word BusFault_Handler
+ .word UsageFault_Handler
+ .word 0
+ .word 0
+ .word 0
+ .word 0
+ .word SVC_Handler
+ .word DebugMon_Handler
+ .word 0
+ .word PendSV_Handler
+ .word SysTick_Handler
+ .word WWDG_IRQHandler
+ .word PVD_IRQHandler
+ .word TAMPER_STAMP_IRQHandler
+ .word RTC_WKUP_IRQHandler
+ .word FLASH_IRQHandler
+ .word RCC_IRQHandler
+ .word EXTI0_IRQHandler
+ .word EXTI1_IRQHandler
+ .word EXTI2_IRQHandler
+ .word EXTI3_IRQHandler
+ .word EXTI4_IRQHandler
+ .word DMA1_Channel1_IRQHandler
+ .word DMA1_Channel2_IRQHandler
+ .word DMA1_Channel3_IRQHandler
+ .word DMA1_Channel4_IRQHandler
+ .word DMA1_Channel5_IRQHandler
+ .word DMA1_Channel6_IRQHandler
+ .word DMA1_Channel7_IRQHandler
+ .word ADC1_IRQHandler
+ .word USB_HP_IRQHandler
+ .word USB_LP_IRQHandler
+ .word DAC_IRQHandler
+ .word COMP_IRQHandler
+ .word EXTI9_5_IRQHandler
+ .word LCD_IRQHandler
+ .word TIM9_IRQHandler
+ .word TIM10_IRQHandler
+ .word TIM11_IRQHandler
+ .word TIM2_IRQHandler
+ .word TIM3_IRQHandler
+ .word TIM4_IRQHandler
+ .word I2C1_EV_IRQHandler
+ .word I2C1_ER_IRQHandler
+ .word I2C2_EV_IRQHandler
+ .word I2C2_ER_IRQHandler
+ .word SPI1_IRQHandler
+ .word SPI2_IRQHandler
+ .word USART1_IRQHandler
+ .word USART2_IRQHandler
+ .word USART3_IRQHandler
+ .word EXTI15_10_IRQHandler
+ .word RTC_Alarm_IRQHandler
+ .word USB_FS_WKUP_IRQHandler
+ .word TIM6_IRQHandler
+ .word TIM7_IRQHandler
+ .word 0
+ .word 0
+ .word 0
+ .word 0
+ .word 0
+ .word BootRAM /* @0x108. This is for boot in RAM mode for
+ STM32L15x ULtra Low Power Medium-density devices. */
+
+/*******************************************************************************
+*
+* Provide weak aliases for each Exception handler to the Default_Handler.
+* As they are weak aliases, any function with the same name will override
+* this definition.
+*
+*******************************************************************************/
+
+ .weak NMI_Handler
+ .thumb_set NMI_Handler,Default_Handler
+
+ .weak HardFault_Handler
+ .thumb_set HardFault_Handler,Default_Handler
+
+ .weak MemManage_Handler
+ .thumb_set MemManage_Handler,Default_Handler
+
+ .weak BusFault_Handler
+ .thumb_set BusFault_Handler,Default_Handler
+
+ .weak UsageFault_Handler
+ .thumb_set UsageFault_Handler,Default_Handler
+
+ .weak SVC_Handler
+ .thumb_set SVC_Handler,Default_Handler
+
+ .weak DebugMon_Handler
+ .thumb_set DebugMon_Handler,Default_Handler
+
+ .weak PendSV_Handler
+ .thumb_set PendSV_Handler,Default_Handler
+
+ .weak SysTick_Handler
+ .thumb_set SysTick_Handler,Default_Handler
+
+ .weak WWDG_IRQHandler
+ .thumb_set WWDG_IRQHandler,Default_Handler
+
+ .weak PVD_IRQHandler
+ .thumb_set PVD_IRQHandler,Default_Handler
+
+ .weak TAMPER_STAMP_IRQHandler
+ .thumb_set TAMPER_STAMP_IRQHandler,Default_Handler
+
+ .weak RTC_WKUP_IRQHandler
+ .thumb_set RTC_WKUP_IRQHandler,Default_Handler
+
+ .weak FLASH_IRQHandler
+ .thumb_set FLASH_IRQHandler,Default_Handler
+
+ .weak RCC_IRQHandler
+ .thumb_set RCC_IRQHandler,Default_Handler
+
+ .weak EXTI0_IRQHandler
+ .thumb_set EXTI0_IRQHandler,Default_Handler
+
+ .weak EXTI1_IRQHandler
+ .thumb_set EXTI1_IRQHandler,Default_Handler
+
+ .weak EXTI2_IRQHandler
+ .thumb_set EXTI2_IRQHandler,Default_Handler
+
+ .weak EXTI3_IRQHandler
+ .thumb_set EXTI3_IRQHandler,Default_Handler
+
+ .weak EXTI4_IRQHandler
+ .thumb_set EXTI4_IRQHandler,Default_Handler
+
+ .weak DMA1_Channel1_IRQHandler
+ .thumb_set DMA1_Channel1_IRQHandler,Default_Handler
+
+ .weak DMA1_Channel2_IRQHandler
+ .thumb_set DMA1_Channel2_IRQHandler,Default_Handler
+
+ .weak DMA1_Channel3_IRQHandler
+ .thumb_set DMA1_Channel3_IRQHandler,Default_Handler
+
+ .weak DMA1_Channel4_IRQHandler
+ .thumb_set DMA1_Channel4_IRQHandler,Default_Handler
+
+ .weak DMA1_Channel5_IRQHandler
+ .thumb_set DMA1_Channel5_IRQHandler,Default_Handler
+
+ .weak DMA1_Channel6_IRQHandler
+ .thumb_set DMA1_Channel6_IRQHandler,Default_Handler
+
+ .weak DMA1_Channel7_IRQHandler
+ .thumb_set DMA1_Channel7_IRQHandler,Default_Handler
+
+ .weak ADC1_IRQHandler
+ .thumb_set ADC1_IRQHandler,Default_Handler
+
+ .weak USB_HP_IRQHandler
+ .thumb_set USB_HP_IRQHandler,Default_Handler
+
+ .weak USB_LP_IRQHandler
+ .thumb_set USB_LP_IRQHandler,Default_Handler
+
+ .weak DAC_IRQHandler
+ .thumb_set DAC_IRQHandler,Default_Handler
+
+ .weak COMP_IRQHandler
+ .thumb_set COMP_IRQHandler,Default_Handler
+
+ .weak EXTI9_5_IRQHandler
+ .thumb_set EXTI9_5_IRQHandler,Default_Handler
+
+ .weak LCD_IRQHandler
+ .thumb_set LCD_IRQHandler,Default_Handler
+
+ .weak TIM9_IRQHandler
+ .thumb_set TIM9_IRQHandler,Default_Handler
+
+ .weak TIM10_IRQHandler
+ .thumb_set TIM10_IRQHandler,Default_Handler
+
+ .weak TIM11_IRQHandler
+ .thumb_set TIM11_IRQHandler,Default_Handler
+
+ .weak TIM2_IRQHandler
+ .thumb_set TIM2_IRQHandler,Default_Handler
+
+ .weak TIM3_IRQHandler
+ .thumb_set TIM3_IRQHandler,Default_Handler
+
+ .weak TIM4_IRQHandler
+ .thumb_set TIM4_IRQHandler,Default_Handler
+
+ .weak I2C1_EV_IRQHandler
+ .thumb_set I2C1_EV_IRQHandler,Default_Handler
+
+ .weak I2C1_ER_IRQHandler
+ .thumb_set I2C1_ER_IRQHandler,Default_Handler
+
+ .weak I2C2_EV_IRQHandler
+ .thumb_set I2C2_EV_IRQHandler,Default_Handler
+
+ .weak I2C2_ER_IRQHandler
+ .thumb_set I2C2_ER_IRQHandler,Default_Handler
+
+ .weak SPI1_IRQHandler
+ .thumb_set SPI1_IRQHandler,Default_Handler
+
+ .weak SPI2_IRQHandler
+ .thumb_set SPI2_IRQHandler,Default_Handler
+
+ .weak USART1_IRQHandler
+ .thumb_set USART1_IRQHandler,Default_Handler
+
+ .weak USART2_IRQHandler
+ .thumb_set USART2_IRQHandler,Default_Handler
+
+ .weak USART3_IRQHandler
+ .thumb_set USART3_IRQHandler,Default_Handler
+
+ .weak EXTI15_10_IRQHandler
+ .thumb_set EXTI15_10_IRQHandler,Default_Handler
+
+ .weak RTC_Alarm_IRQHandler
+ .thumb_set RTC_Alarm_IRQHandler,Default_Handler
+
+ .weak USB_FS_WKUP_IRQHandler
+ .thumb_set USB_FS_WKUP_IRQHandler,Default_Handler
+
+ .weak TIM6_IRQHandler
+ .thumb_set TIM6_IRQHandler,Default_Handler
+
+ .weak TIM7_IRQHandler
+ .thumb_set TIM7_IRQHandler,Default_Handler
+
+/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
+
diff --git a/Libraries/CMSIS/Device/ST/STM32L1xx/Source/Templates/TrueSTUDIO/startup_stm32l1xx_mdp.s b/Libraries/CMSIS/Device/ST/STM32L1xx/Source/Templates/TrueSTUDIO/startup_stm32l1xx_mdp.s
new file mode 100644
index 0000000..cc8d06c
--- /dev/null
+++ b/Libraries/CMSIS/Device/ST/STM32L1xx/Source/Templates/TrueSTUDIO/startup_stm32l1xx_mdp.s
@@ -0,0 +1,415 @@
+/**
+ ******************************************************************************
+ * @file startup_stm32l1xx_mdp.s
+ * @author MCD Application Team
+ * @version V1.1.1
+ * @date 09-March-2012
+ * @brief STM32L1xx Ultra Low Power Medium-density Plus Devices vector table
+ * for Atollic toolchain.
+ * This module performs:
+ * - Set the initial SP
+ * - Set the initial PC == Reset_Handler,
+ * - Set the vector table entries with the exceptions ISR address
+ * - Configure the clock system
+ * - Branches to main in the C library (which eventually
+ * calls main()).
+ * After Reset the Cortex-M3 processor is in Thread mode,
+ * priority is Privileged, and the Stack is set to Main.
+ ******************************************************************************
+ * @attention
+ *
+ * © COPYRIGHT 2012 STMicroelectronics
+ *
+ * Licensed under MCD-ST Liberty SW License Agreement V2, (the "License");
+ * You may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at:
+ *
+ * http://www.st.com/software_license_agreement_liberty_v2
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ *
+ ******************************************************************************
+ */
+
+ .syntax unified
+ .cpu cortex-m3
+ .fpu softvfp
+ .thumb
+
+.global g_pfnVectors
+.global Default_Handler
+
+/* start address for the initialization values of the .data section.
+defined in linker script */
+.word _sidata
+/* start address for the .data section. defined in linker script */
+.word _sdata
+/* end address for the .data section. defined in linker script */
+.word _edata
+/* start address for the .bss section. defined in linker script */
+.word _sbss
+/* end address for the .bss section. defined in linker script */
+.word _ebss
+
+.equ BootRAM, 0xF108F85F
+/**
+ * @brief This is the code that gets called when the processor first
+ * starts execution following a reset event. Only the absolutely
+ * necessary set is performed, after which the application
+ * supplied main() routine is called.
+ * @param None
+ * @retval : None
+*/
+
+ .section .text.Reset_Handler
+ .weak Reset_Handler
+ .type Reset_Handler, %function
+Reset_Handler:
+
+/* Copy the data segment initializers from flash to SRAM */
+ movs r1, #0
+ b LoopCopyDataInit
+
+CopyDataInit:
+ ldr r3, =_sidata
+ ldr r3, [r3, r1]
+ str r3, [r0, r1]
+ adds r1, r1, #4
+
+LoopCopyDataInit:
+ ldr r0, =_sdata
+ ldr r3, =_edata
+ adds r2, r0, r1
+ cmp r2, r3
+ bcc CopyDataInit
+ ldr r2, =_sbss
+ b LoopFillZerobss
+/* Zero fill the bss segment. */
+FillZerobss:
+ movs r3, #0
+ str r3, [r2], #4
+
+LoopFillZerobss:
+ ldr r3, = _ebss
+ cmp r2, r3
+ bcc FillZerobss
+
+/* Call the clock system intitialization function.*/
+ bl SystemInit
+/* Call static constructors */
+ bl __libc_init_array
+/* Call the application's entry point.*/
+ bl main
+ bx lr
+.size Reset_Handler, .-Reset_Handler
+
+/**
+ * @brief This is the code that gets called when the processor receives an
+ * unexpected interrupt. This simply enters an infinite loop, preserving
+ * the system state for examination by a debugger.
+ *
+ * @param None
+ * @retval : None
+*/
+ .section .text.Default_Handler,"ax",%progbits
+Default_Handler:
+Infinite_Loop:
+ b Infinite_Loop
+ .size Default_Handler, .-Default_Handler
+/******************************************************************************
+*
+* The minimal vector table for a Cortex M3. Note that the proper constructs
+* must be placed on this to ensure that it ends up at physical address
+* 0x0000.0000.
+*
+******************************************************************************/
+ .section .isr_vector,"a",%progbits
+ .type g_pfnVectors, %object
+ .size g_pfnVectors, .-g_pfnVectors
+
+
+g_pfnVectors:
+ .word _estack
+ .word Reset_Handler
+ .word NMI_Handler
+ .word HardFault_Handler
+ .word MemManage_Handler
+ .word BusFault_Handler
+ .word UsageFault_Handler
+ .word 0
+ .word 0
+ .word 0
+ .word 0
+ .word SVC_Handler
+ .word DebugMon_Handler
+ .word 0
+ .word PendSV_Handler
+ .word SysTick_Handler
+ .word WWDG_IRQHandler
+ .word PVD_IRQHandler
+ .word TAMPER_STAMP_IRQHandler
+ .word RTC_WKUP_IRQHandler
+ .word FLASH_IRQHandler
+ .word RCC_IRQHandler
+ .word EXTI0_IRQHandler
+ .word EXTI1_IRQHandler
+ .word EXTI2_IRQHandler
+ .word EXTI3_IRQHandler
+ .word EXTI4_IRQHandler
+ .word DMA1_Channel1_IRQHandler
+ .word DMA1_Channel2_IRQHandler
+ .word DMA1_Channel3_IRQHandler
+ .word DMA1_Channel4_IRQHandler
+ .word DMA1_Channel5_IRQHandler
+ .word DMA1_Channel6_IRQHandler
+ .word DMA1_Channel7_IRQHandler
+ .word ADC1_IRQHandler
+ .word USB_HP_IRQHandler
+ .word USB_LP_IRQHandler
+ .word DAC_IRQHandler
+ .word COMP_IRQHandler
+ .word EXTI9_5_IRQHandler
+ .word LCD_IRQHandler
+ .word TIM9_IRQHandler
+ .word TIM10_IRQHandler
+ .word TIM11_IRQHandler
+ .word TIM2_IRQHandler
+ .word TIM3_IRQHandler
+ .word TIM4_IRQHandler
+ .word I2C1_EV_IRQHandler
+ .word I2C1_ER_IRQHandler
+ .word I2C2_EV_IRQHandler
+ .word I2C2_ER_IRQHandler
+ .word SPI1_IRQHandler
+ .word SPI2_IRQHandler
+ .word USART1_IRQHandler
+ .word USART2_IRQHandler
+ .word USART3_IRQHandler
+ .word EXTI15_10_IRQHandler
+ .word RTC_Alarm_IRQHandler
+ .word USB_FS_WKUP_IRQHandler
+ .word TIM6_IRQHandler
+ .word TIM7_IRQHandler
+ .word 0
+ .word TIM5_IRQHandler
+ .word SPI3_IRQHandler
+ .word 0
+ .word 0
+ .word DMA2_Channel1_IRQHandler
+ .word DMA2_Channel2_IRQHandler
+ .word DMA2_Channel3_IRQHandler
+ .word DMA2_Channel4_IRQHandler
+ .word DMA2_Channel5_IRQHandler
+ .word AES_IRQHandler
+ .word COMP_ACQ_IRQHandler
+ .word 0
+ .word 0
+ .word 0
+ .word 0
+ .word 0
+ .word BootRAM /* @0x108. This is for boot in RAM mode for
+ STM32L15x ULtra Low Power Medium-density devices. */
+
+/*******************************************************************************
+*
+* Provide weak aliases for each Exception handler to the Default_Handler.
+* As they are weak aliases, any function with the same name will override
+* this definition.
+*
+*******************************************************************************/
+
+ .weak NMI_Handler
+ .thumb_set NMI_Handler,Default_Handler
+
+ .weak HardFault_Handler
+ .thumb_set HardFault_Handler,Default_Handler
+
+ .weak MemManage_Handler
+ .thumb_set MemManage_Handler,Default_Handler
+
+ .weak BusFault_Handler
+ .thumb_set BusFault_Handler,Default_Handler
+
+ .weak UsageFault_Handler
+ .thumb_set UsageFault_Handler,Default_Handler
+
+ .weak SVC_Handler
+ .thumb_set SVC_Handler,Default_Handler
+
+ .weak DebugMon_Handler
+ .thumb_set DebugMon_Handler,Default_Handler
+
+ .weak PendSV_Handler
+ .thumb_set PendSV_Handler,Default_Handler
+
+ .weak SysTick_Handler
+ .thumb_set SysTick_Handler,Default_Handler
+
+ .weak WWDG_IRQHandler
+ .thumb_set WWDG_IRQHandler,Default_Handler
+
+ .weak PVD_IRQHandler
+ .thumb_set PVD_IRQHandler,Default_Handler
+
+ .weak TAMPER_STAMP_IRQHandler
+ .thumb_set TAMPER_STAMP_IRQHandler,Default_Handler
+
+ .weak RTC_WKUP_IRQHandler
+ .thumb_set RTC_WKUP_IRQHandler,Default_Handler
+
+ .weak FLASH_IRQHandler
+ .thumb_set FLASH_IRQHandler,Default_Handler
+
+ .weak RCC_IRQHandler
+ .thumb_set RCC_IRQHandler,Default_Handler
+
+ .weak EXTI0_IRQHandler
+ .thumb_set EXTI0_IRQHandler,Default_Handler
+
+ .weak EXTI1_IRQHandler
+ .thumb_set EXTI1_IRQHandler,Default_Handler
+
+ .weak EXTI2_IRQHandler
+ .thumb_set EXTI2_IRQHandler,Default_Handler
+
+ .weak EXTI3_IRQHandler
+ .thumb_set EXTI3_IRQHandler,Default_Handler
+
+ .weak EXTI4_IRQHandler
+ .thumb_set EXTI4_IRQHandler,Default_Handler
+
+ .weak DMA1_Channel1_IRQHandler
+ .thumb_set DMA1_Channel1_IRQHandler,Default_Handler
+
+ .weak DMA1_Channel2_IRQHandler
+ .thumb_set DMA1_Channel2_IRQHandler,Default_Handler
+
+ .weak DMA1_Channel3_IRQHandler
+ .thumb_set DMA1_Channel3_IRQHandler,Default_Handler
+
+ .weak DMA1_Channel4_IRQHandler
+ .thumb_set DMA1_Channel4_IRQHandler,Default_Handler
+
+ .weak DMA1_Channel5_IRQHandler
+ .thumb_set DMA1_Channel5_IRQHandler,Default_Handler
+
+ .weak DMA1_Channel6_IRQHandler
+ .thumb_set DMA1_Channel6_IRQHandler,Default_Handler
+
+ .weak DMA1_Channel7_IRQHandler
+ .thumb_set DMA1_Channel7_IRQHandler,Default_Handler
+
+ .weak ADC1_IRQHandler
+ .thumb_set ADC1_IRQHandler,Default_Handler
+
+ .weak USB_HP_IRQHandler
+ .thumb_set USB_HP_IRQHandler,Default_Handler
+
+ .weak USB_LP_IRQHandler
+ .thumb_set USB_LP_IRQHandler,Default_Handler
+
+ .weak DAC_IRQHandler
+ .thumb_set DAC_IRQHandler,Default_Handler
+
+ .weak COMP_IRQHandler
+ .thumb_set COMP_IRQHandler,Default_Handler
+
+ .weak EXTI9_5_IRQHandler
+ .thumb_set EXTI9_5_IRQHandler,Default_Handler
+
+ .weak LCD_IRQHandler
+ .thumb_set LCD_IRQHandler,Default_Handler
+
+ .weak TIM9_IRQHandler
+ .thumb_set TIM9_IRQHandler,Default_Handler
+
+ .weak TIM10_IRQHandler
+ .thumb_set TIM10_IRQHandler,Default_Handler
+
+ .weak TIM11_IRQHandler
+ .thumb_set TIM11_IRQHandler,Default_Handler
+
+ .weak TIM2_IRQHandler
+ .thumb_set TIM2_IRQHandler,Default_Handler
+
+ .weak TIM3_IRQHandler
+ .thumb_set TIM3_IRQHandler,Default_Handler
+
+ .weak TIM4_IRQHandler
+ .thumb_set TIM4_IRQHandler,Default_Handler
+
+ .weak I2C1_EV_IRQHandler
+ .thumb_set I2C1_EV_IRQHandler,Default_Handler
+
+ .weak I2C1_ER_IRQHandler
+ .thumb_set I2C1_ER_IRQHandler,Default_Handler
+
+ .weak I2C2_EV_IRQHandler
+ .thumb_set I2C2_EV_IRQHandler,Default_Handler
+
+ .weak I2C2_ER_IRQHandler
+ .thumb_set I2C2_ER_IRQHandler,Default_Handler
+
+ .weak SPI1_IRQHandler
+ .thumb_set SPI1_IRQHandler,Default_Handler
+
+ .weak SPI2_IRQHandler
+ .thumb_set SPI2_IRQHandler,Default_Handler
+
+ .weak USART1_IRQHandler
+ .thumb_set USART1_IRQHandler,Default_Handler
+
+ .weak USART2_IRQHandler
+ .thumb_set USART2_IRQHandler,Default_Handler
+
+ .weak USART3_IRQHandler
+ .thumb_set USART3_IRQHandler,Default_Handler
+
+ .weak EXTI15_10_IRQHandler
+ .thumb_set EXTI15_10_IRQHandler,Default_Handler
+
+ .weak RTC_Alarm_IRQHandler
+ .thumb_set RTC_Alarm_IRQHandler,Default_Handler
+
+ .weak USB_FS_WKUP_IRQHandler
+ .thumb_set USB_FS_WKUP_IRQHandler,Default_Handler
+
+ .weak TIM6_IRQHandler
+ .thumb_set TIM6_IRQHandler,Default_Handler
+
+ .weak TIM7_IRQHandler
+ .thumb_set TIM7_IRQHandler,Default_Handler
+
+ .weak TIM5_IRQHandler
+ .thumb_set TIM5_IRQHandler,Default_Handler
+
+ .weak SPI3_IRQHandler
+ .thumb_set SPI3_IRQHandler,Default_Handler
+
+ .weak DMA2_Channel1_IRQHandler
+ .thumb_set DMA2_Channel1_IRQHandler,Default_Handler
+
+ .weak DMA2_Channel2_IRQHandler
+ .thumb_set DMA2_Channel2_IRQHandler,Default_Handler
+
+ .weak DMA2_Channel3_IRQHandler
+ .thumb_set DMA2_Channel3_IRQHandler,Default_Handler
+
+ .weak DMA2_Channel4_IRQHandler
+ .thumb_set DMA2_Channel4_IRQHandler,Default_Handler
+
+ .weak DMA2_Channel5_IRQHandler
+ .thumb_set DMA2_Channel5_IRQHandler,Default_Handler
+
+ .weak AES_IRQHandler
+ .thumb_set AES_IRQHandler,Default_Handler
+
+ .weak COMP_ACQ_IRQHandler
+ .thumb_set COMP_ACQ_IRQHandler,Default_Handler
+
+/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
+
diff --git a/Libraries/CMSIS/Device/ST/STM32L1xx/Source/Templates/arm/startup_stm32l1xx_hd.s b/Libraries/CMSIS/Device/ST/STM32L1xx/Source/Templates/arm/startup_stm32l1xx_hd.s
new file mode 100644
index 0000000..c7d1e5e
--- /dev/null
+++ b/Libraries/CMSIS/Device/ST/STM32L1xx/Source/Templates/arm/startup_stm32l1xx_hd.s
@@ -0,0 +1,356 @@
+;******************** (C) COPYRIGHT 2012 STMicroelectronics ********************
+;* File Name : startup_stm32l1xx_hd.s
+;* Author : MCD Application Team
+;* Version : V1.1.1
+;* Date : 09-March-2012
+;* Description : STM32L1xx Ultra Low Power High-density Devices vector
+;* table for MDK-ARM toolchain.
+;* This module performs:
+;* - Set the initial SP
+;* - Set the initial PC == Reset_Handler
+;* - Set the vector table entries with the exceptions ISR address
+;* - Branches to __main in the C library (which eventually
+;* calls main()).
+;* After Reset the CortexM3 processor is in Thread mode,
+;* priority is Privileged, and the Stack is set to Main.
+;* <<< Use Configuration Wizard in Context Menu >>>
+;*******************************************************************************
+;
+; Licensed under MCD-ST Liberty SW License Agreement V2, (the "License");
+; You may not use this file except in compliance with the License.
+; You may obtain a copy of the License at:
+;
+; http://www.st.com/software_license_agreement_liberty_v2
+;
+; Unless required by applicable law or agreed to in writing, software
+; distributed under the License is distributed on an "AS IS" BASIS,
+; WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+; See the License for the specific language governing permissions and
+; limitations under the License.
+;
+;*******************************************************************************
+
+; Amount of memory (in bytes) allocated for Stack
+; Tailor this value to your application needs
+; © COPYRIGHT 2012 STMicroelectronics
+ *
+ * Licensed under MCD-ST Liberty SW License Agreement V2, (the "License");
+ * You may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at:
+ *
+ * http://www.st.com/software_license_agreement_liberty_v2
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ *
+ ******************************************************************************
+ */
+
+ .syntax unified
+ .cpu cortex-m3
+ .fpu softvfp
+ .thumb
+
+.global g_pfnVectors
+.global Default_Handler
+
+/* start address for the initialization values of the .data section.
+defined in linker script */
+.word _sidata
+/* start address for the .data section. defined in linker script */
+.word _sdata
+/* end address for the .data section. defined in linker script */
+.word _edata
+/* start address for the .bss section. defined in linker script */
+.word _sbss
+/* end address for the .bss section. defined in linker script */
+.word _ebss
+
+.equ BootRAM, 0xF108F85F
+/**
+ * @brief This is the code that gets called when the processor first
+ * starts execution following a reset event. Only the absolutely
+ * necessary set is performed, after which the application
+ * supplied main() routine is called.
+ * @param None
+ * @retval : None
+*/
+
+ .section .text.Reset_Handler
+ .weak Reset_Handler
+ .type Reset_Handler, %function
+Reset_Handler:
+
+/* Copy the data segment initializers from flash to SRAM */
+ movs r1, #0
+ b LoopCopyDataInit
+
+CopyDataInit:
+ ldr r3, =_sidata
+ ldr r3, [r3, r1]
+ str r3, [r0, r1]
+ adds r1, r1, #4
+
+LoopCopyDataInit:
+ ldr r0, =_sdata
+ ldr r3, =_edata
+ adds r2, r0, r1
+ cmp r2, r3
+ bcc CopyDataInit
+ ldr r2, =_sbss
+ b LoopFillZerobss
+/* Zero fill the bss segment. */
+FillZerobss:
+ movs r3, #0
+ str r3, [r2], #4
+
+LoopFillZerobss:
+ ldr r3, = _ebss
+ cmp r2, r3
+ bcc FillZerobss
+/* Call the clock system intitialization function.*/
+ bl SystemInit
+/* Call the application's entry point.*/
+ bl main
+ bx lr
+.size Reset_Handler, .-Reset_Handler
+
+/**
+ * @brief This is the code that gets called when the processor receives an
+ * unexpected interrupt. This simply enters an infinite loop, preserving
+ * the system state for examination by a debugger.
+ *
+ * @param None
+ * @retval None
+*/
+ .section .text.Default_Handler,"ax",%progbits
+Default_Handler:
+Infinite_Loop:
+ b Infinite_Loop
+ .size Default_Handler, .-Default_Handler
+/*******************************************************************************
+*
+* The minimal vector table for a Cortex M3. Note that the proper constructs
+* must be placed on this to ensure that it ends up at physical address
+* 0x0000.0000.
+*******************************************************************************/
+ .section .isr_vector,"a",%progbits
+ .type g_pfnVectors, %object
+ .size g_pfnVectors, .-g_pfnVectors
+
+
+g_pfnVectors:
+ .word _estack
+ .word Reset_Handler
+ .word NMI_Handler
+ .word HardFault_Handler
+ .word MemManage_Handler
+ .word BusFault_Handler
+ .word UsageFault_Handler
+ .word 0
+ .word 0
+ .word 0
+ .word 0
+ .word SVC_Handler
+ .word DebugMon_Handler
+ .word 0
+ .word PendSV_Handler
+ .word SysTick_Handler
+ .word WWDG_IRQHandler
+ .word PVD_IRQHandler
+ .word TAMPER_STAMP_IRQHandler
+ .word RTC_WKUP_IRQHandler
+ .word FLASH_IRQHandler
+ .word RCC_IRQHandler
+ .word EXTI0_IRQHandler
+ .word EXTI1_IRQHandler
+ .word EXTI2_IRQHandler
+ .word EXTI3_IRQHandler
+ .word EXTI4_IRQHandler
+ .word DMA1_Channel1_IRQHandler
+ .word DMA1_Channel2_IRQHandler
+ .word DMA1_Channel3_IRQHandler
+ .word DMA1_Channel4_IRQHandler
+ .word DMA1_Channel5_IRQHandler
+ .word DMA1_Channel6_IRQHandler
+ .word DMA1_Channel7_IRQHandler
+ .word ADC1_IRQHandler
+ .word USB_HP_IRQHandler
+ .word USB_LP_IRQHandler
+ .word DAC_IRQHandler
+ .word COMP_IRQHandler
+ .word EXTI9_5_IRQHandler
+ .word LCD_IRQHandler
+ .word TIM9_IRQHandler
+ .word TIM10_IRQHandler
+ .word TIM11_IRQHandler
+ .word TIM2_IRQHandler
+ .word TIM3_IRQHandler
+ .word TIM4_IRQHandler
+ .word I2C1_EV_IRQHandler
+ .word I2C1_ER_IRQHandler
+ .word I2C2_EV_IRQHandler
+ .word I2C2_ER_IRQHandler
+ .word SPI1_IRQHandler
+ .word SPI2_IRQHandler
+ .word USART1_IRQHandler
+ .word USART2_IRQHandler
+ .word USART3_IRQHandler
+ .word EXTI15_10_IRQHandler
+ .word RTC_Alarm_IRQHandler
+ .word USB_FS_WKUP_IRQHandler
+ .word TIM6_IRQHandler
+ .word TIM7_IRQHandler
+ .word SDIO_IRQHandler
+ .word TIM5_IRQHandler
+ .word SPI3_IRQHandler
+ .word UART4_IRQHandler
+ .word UART5_IRQHandler
+ .word DMA2_Channel1_IRQHandler
+ .word DMA2_Channel2_IRQHandler
+ .word DMA2_Channel3_IRQHandler
+ .word DMA2_Channel4_IRQHandler
+ .word DMA2_Channel5_IRQHandler
+ .word AES_IRQHandler
+ .word COMP_ACQ_IRQHandler
+ .word 0
+ .word 0
+ .word 0
+ .word 0
+ .word 0
+ .word BootRAM /* @0x108. This is for boot in RAM mode for
+ STM32L15x ULtra Low Power High-density devices. */
+
+/*******************************************************************************
+*
+* Provide weak aliases for each Exception handler to the Default_Handler.
+* As they are weak aliases, any function with the same name will override
+* this definition.
+*
+*******************************************************************************/
+
+ .weak NMI_Handler
+ .thumb_set NMI_Handler,Default_Handler
+
+ .weak HardFault_Handler
+ .thumb_set HardFault_Handler,Default_Handler
+
+ .weak MemManage_Handler
+ .thumb_set MemManage_Handler,Default_Handler
+
+ .weak BusFault_Handler
+ .thumb_set BusFault_Handler,Default_Handler
+
+ .weak UsageFault_Handler
+ .thumb_set UsageFault_Handler,Default_Handler
+
+ .weak SVC_Handler
+ .thumb_set SVC_Handler,Default_Handler
+
+ .weak DebugMon_Handler
+ .thumb_set DebugMon_Handler,Default_Handler
+
+ .weak PendSV_Handler
+ .thumb_set PendSV_Handler,Default_Handler
+
+ .weak SysTick_Handler
+ .thumb_set SysTick_Handler,Default_Handler
+
+ .weak WWDG_IRQHandler
+ .thumb_set WWDG_IRQHandler,Default_Handler
+
+ .weak PVD_IRQHandler
+ .thumb_set PVD_IRQHandler,Default_Handler
+
+ .weak TAMPER_STAMP_IRQHandler
+ .thumb_set TAMPER_STAMP_IRQHandler,Default_Handler
+
+ .weak RTC_WKUP_IRQHandler
+ .thumb_set RTC_WKUP_IRQHandler,Default_Handler
+
+ .weak FLASH_IRQHandler
+ .thumb_set FLASH_IRQHandler,Default_Handler
+
+ .weak RCC_IRQHandler
+ .thumb_set RCC_IRQHandler,Default_Handler
+
+ .weak EXTI0_IRQHandler
+ .thumb_set EXTI0_IRQHandler,Default_Handler
+
+ .weak EXTI1_IRQHandler
+ .thumb_set EXTI1_IRQHandler,Default_Handler
+
+ .weak EXTI2_IRQHandler
+ .thumb_set EXTI2_IRQHandler,Default_Handler
+
+ .weak EXTI3_IRQHandler
+ .thumb_set EXTI3_IRQHandler,Default_Handler
+
+ .weak EXTI4_IRQHandler
+ .thumb_set EXTI4_IRQHandler,Default_Handler
+
+ .weak DMA1_Channel1_IRQHandler
+ .thumb_set DMA1_Channel1_IRQHandler,Default_Handler
+
+ .weak DMA1_Channel2_IRQHandler
+ .thumb_set DMA1_Channel2_IRQHandler,Default_Handler
+
+ .weak DMA1_Channel3_IRQHandler
+ .thumb_set DMA1_Channel3_IRQHandler,Default_Handler
+
+ .weak DMA1_Channel4_IRQHandler
+ .thumb_set DMA1_Channel4_IRQHandler,Default_Handler
+
+ .weak DMA1_Channel5_IRQHandler
+ .thumb_set DMA1_Channel5_IRQHandler,Default_Handler
+
+ .weak DMA1_Channel6_IRQHandler
+ .thumb_set DMA1_Channel6_IRQHandler,Default_Handler
+
+ .weak DMA1_Channel7_IRQHandler
+ .thumb_set DMA1_Channel7_IRQHandler,Default_Handler
+
+ .weak ADC1_IRQHandler
+ .thumb_set ADC1_IRQHandler,Default_Handler
+
+ .weak USB_HP_IRQHandler
+ .thumb_set USB_HP_IRQHandler,Default_Handler
+
+ .weak USB_LP_IRQHandler
+ .thumb_set USB_LP_IRQHandler,Default_Handler
+
+ .weak DAC_IRQHandler
+ .thumb_set DAC_IRQHandler,Default_Handler
+
+ .weak COMP_IRQHandler
+ .thumb_set COMP_IRQHandler,Default_Handler
+
+ .weak EXTI9_5_IRQHandler
+ .thumb_set EXTI9_5_IRQHandler,Default_Handler
+
+ .weak LCD_IRQHandler
+ .thumb_set LCD_IRQHandler,Default_Handler
+
+ .weak TIM9_IRQHandler
+ .thumb_set TIM9_IRQHandler,Default_Handler
+
+ .weak TIM10_IRQHandler
+ .thumb_set TIM10_IRQHandler,Default_Handler
+
+ .weak TIM11_IRQHandler
+ .thumb_set TIM11_IRQHandler,Default_Handler
+
+ .weak TIM2_IRQHandler
+ .thumb_set TIM2_IRQHandler,Default_Handler
+
+ .weak TIM3_IRQHandler
+ .thumb_set TIM3_IRQHandler,Default_Handler
+
+ .weak TIM4_IRQHandler
+ .thumb_set TIM4_IRQHandler,Default_Handler
+
+ .weak I2C1_EV_IRQHandler
+ .thumb_set I2C1_EV_IRQHandler,Default_Handler
+
+ .weak I2C1_ER_IRQHandler
+ .thumb_set I2C1_ER_IRQHandler,Default_Handler
+
+ .weak I2C2_EV_IRQHandler
+ .thumb_set I2C2_EV_IRQHandler,Default_Handler
+
+ .weak I2C2_ER_IRQHandler
+ .thumb_set I2C2_ER_IRQHandler,Default_Handler
+
+ .weak SPI1_IRQHandler
+ .thumb_set SPI1_IRQHandler,Default_Handler
+
+ .weak SPI2_IRQHandler
+ .thumb_set SPI2_IRQHandler,Default_Handler
+
+ .weak USART1_IRQHandler
+ .thumb_set USART1_IRQHandler,Default_Handler
+
+ .weak USART2_IRQHandler
+ .thumb_set USART2_IRQHandler,Default_Handler
+
+ .weak USART3_IRQHandler
+ .thumb_set USART3_IRQHandler,Default_Handler
+
+ .weak EXTI15_10_IRQHandler
+ .thumb_set EXTI15_10_IRQHandler,Default_Handler
+
+ .weak RTC_Alarm_IRQHandler
+ .thumb_set RTC_Alarm_IRQHandler,Default_Handler
+
+ .weak USB_FS_WKUP_IRQHandler
+ .thumb_set USB_FS_WKUP_IRQHandler,Default_Handler
+
+ .weak TIM6_IRQHandler
+ .thumb_set TIM6_IRQHandler,Default_Handler
+
+ .weak TIM7_IRQHandler
+ .thumb_set TIM7_IRQHandler,Default_Handler
+
+ .weak SDIO_IRQHandler
+ .thumb_set SDIO_IRQHandler,Default_Handler
+
+ .weak TIM5_IRQHandler
+ .thumb_set TIM5_IRQHandler,Default_Handler
+
+ .weak SPI3_IRQHandler
+ .thumb_set SPI3_IRQHandler,Default_Handler
+
+ .weak UART4_IRQHandler
+ .thumb_set UART4_IRQHandler,Default_Handler
+
+ .weak UART5_IRQHandler
+ .thumb_set UART5_IRQHandler,Default_Handler
+
+ .weak DMA2_Channel1_IRQHandler
+ .thumb_set DMA2_Channel1_IRQHandler,Default_Handler
+
+ .weak DMA2_Channel2_IRQHandler
+ .thumb_set DMA2_Channel2_IRQHandler,Default_Handler
+
+ .weak DMA2_Channel3_IRQHandler
+ .thumb_set DMA2_Channel3_IRQHandler,Default_Handler
+
+ .weak DMA2_Channel4_IRQHandler
+ .thumb_set DMA2_Channel4_IRQHandler,Default_Handler
+
+ .weak DMA2_Channel5_IRQHandler
+ .thumb_set DMA2_Channel5_IRQHandler,Default_Handler
+
+ .weak AES_IRQHandler
+ .thumb_set AES_IRQHandler,Default_Handler
+
+ .weak COMP_ACQ_IRQHandler
+ .thumb_set COMP_ACQ_IRQHandler,Default_Handler
+
+/************************* (C) COPYRIGHT STMicroelectronics *****END OF FILE***/
+
diff --git a/Libraries/CMSIS/Device/ST/STM32L1xx/Source/Templates/gcc_ride7/startup_stm32l1xx_md.s b/Libraries/CMSIS/Device/ST/STM32L1xx/Source/Templates/gcc_ride7/startup_stm32l1xx_md.s
new file mode 100644
index 0000000..bd72ed0
--- /dev/null
+++ b/Libraries/CMSIS/Device/ST/STM32L1xx/Source/Templates/gcc_ride7/startup_stm32l1xx_md.s
@@ -0,0 +1,371 @@
+/**
+ ******************************************************************************
+ * @file startup_stm32l1xx_md.s
+ * @author MCD Application Team
+ * @version V1.1.1
+ * @date 09-March-2012
+ * @brief STM32L1xx Ultra Low Power Medium-density Devices vector table for
+ * RIDE7 toolchain.
+ * This module performs:
+ * - Set the initial SP
+ * - Set the initial PC == Reset_Handler,
+ * - Set the vector table entries with the exceptions ISR address
+ * - Branches to main in the C library (which eventually
+ * calls main()).
+ * After Reset the Cortex-M3 processor is in Thread mode,
+ * priority is Privileged, and the Stack is set to Main.
+ ******************************************************************************
+ * @attention
+ *
+ * © COPYRIGHT 2012 STMicroelectronics
+ *
+ * Licensed under MCD-ST Liberty SW License Agreement V2, (the "License");
+ * You may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at:
+ *
+ * http://www.st.com/software_license_agreement_liberty_v2
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ *
+ ******************************************************************************
+ */
+
+ .syntax unified
+ .cpu cortex-m3
+ .fpu softvfp
+ .thumb
+
+.global g_pfnVectors
+.global Default_Handler
+
+/* start address for the initialization values of the .data section.
+defined in linker script */
+.word _sidata
+/* start address for the .data section. defined in linker script */
+.word _sdata
+/* end address for the .data section. defined in linker script */
+.word _edata
+/* start address for the .bss section. defined in linker script */
+.word _sbss
+/* end address for the .bss section. defined in linker script */
+.word _ebss
+
+.equ BootRAM, 0xF108F85F
+/**
+ * @brief This is the code that gets called when the processor first
+ * starts execution following a reset event. Only the absolutely
+ * necessary set is performed, after which the application
+ * supplied main() routine is called.
+ * @param None
+ * @retval : None
+*/
+
+ .section .text.Reset_Handler
+ .weak Reset_Handler
+ .type Reset_Handler, %function
+Reset_Handler:
+
+/* Copy the data segment initializers from flash to SRAM */
+ movs r1, #0
+ b LoopCopyDataInit
+
+CopyDataInit:
+ ldr r3, =_sidata
+ ldr r3, [r3, r1]
+ str r3, [r0, r1]
+ adds r1, r1, #4
+
+LoopCopyDataInit:
+ ldr r0, =_sdata
+ ldr r3, =_edata
+ adds r2, r0, r1
+ cmp r2, r3
+ bcc CopyDataInit
+ ldr r2, =_sbss
+ b LoopFillZerobss
+/* Zero fill the bss segment. */
+FillZerobss:
+ movs r3, #0
+ str r3, [r2], #4
+
+LoopFillZerobss:
+ ldr r3, = _ebss
+ cmp r2, r3
+ bcc FillZerobss
+/* Call the clock system intitialization function.*/
+ bl SystemInit
+/* Call the application's entry point.*/
+ bl main
+ bx lr
+.size Reset_Handler, .-Reset_Handler
+
+/**
+ * @brief This is the code that gets called when the processor receives an
+ * unexpected interrupt. This simply enters an infinite loop, preserving
+ * the system state for examination by a debugger.
+ *
+ * @param None
+ * @retval None
+*/
+ .section .text.Default_Handler,"ax",%progbits
+Default_Handler:
+Infinite_Loop:
+ b Infinite_Loop
+ .size Default_Handler, .-Default_Handler
+/*******************************************************************************
+*
+* The minimal vector table for a Cortex M3. Note that the proper constructs
+* must be placed on this to ensure that it ends up at physical address
+* 0x0000.0000.
+*******************************************************************************/
+ .section .isr_vector,"a",%progbits
+ .type g_pfnVectors, %object
+ .size g_pfnVectors, .-g_pfnVectors
+
+
+g_pfnVectors:
+ .word _estack
+ .word Reset_Handler
+ .word NMI_Handler
+ .word HardFault_Handler
+ .word MemManage_Handler
+ .word BusFault_Handler
+ .word UsageFault_Handler
+ .word 0
+ .word 0
+ .word 0
+ .word 0
+ .word SVC_Handler
+ .word DebugMon_Handler
+ .word 0
+ .word PendSV_Handler
+ .word SysTick_Handler
+ .word WWDG_IRQHandler
+ .word PVD_IRQHandler
+ .word TAMPER_STAMP_IRQHandler
+ .word RTC_WKUP_IRQHandler
+ .word FLASH_IRQHandler
+ .word RCC_IRQHandler
+ .word EXTI0_IRQHandler
+ .word EXTI1_IRQHandler
+ .word EXTI2_IRQHandler
+ .word EXTI3_IRQHandler
+ .word EXTI4_IRQHandler
+ .word DMA1_Channel1_IRQHandler
+ .word DMA1_Channel2_IRQHandler
+ .word DMA1_Channel3_IRQHandler
+ .word DMA1_Channel4_IRQHandler
+ .word DMA1_Channel5_IRQHandler
+ .word DMA1_Channel6_IRQHandler
+ .word DMA1_Channel7_IRQHandler
+ .word ADC1_IRQHandler
+ .word USB_HP_IRQHandler
+ .word USB_LP_IRQHandler
+ .word DAC_IRQHandler
+ .word COMP_IRQHandler
+ .word EXTI9_5_IRQHandler
+ .word LCD_IRQHandler
+ .word TIM9_IRQHandler
+ .word TIM10_IRQHandler
+ .word TIM11_IRQHandler
+ .word TIM2_IRQHandler
+ .word TIM3_IRQHandler
+ .word TIM4_IRQHandler
+ .word I2C1_EV_IRQHandler
+ .word I2C1_ER_IRQHandler
+ .word I2C2_EV_IRQHandler
+ .word I2C2_ER_IRQHandler
+ .word SPI1_IRQHandler
+ .word SPI2_IRQHandler
+ .word USART1_IRQHandler
+ .word USART2_IRQHandler
+ .word USART3_IRQHandler
+ .word EXTI15_10_IRQHandler
+ .word RTC_Alarm_IRQHandler
+ .word USB_FS_WKUP_IRQHandler
+ .word TIM6_IRQHandler
+ .word TIM7_IRQHandler
+ .word 0
+ .word 0
+ .word 0
+ .word 0
+ .word 0
+ .word BootRAM /* @0x108. This is for boot in RAM mode for
+ STM32L15x ULtra Low Power Medium-density devices. */
+
+/*******************************************************************************
+*
+* Provide weak aliases for each Exception handler to the Default_Handler.
+* As they are weak aliases, any function with the same name will override
+* this definition.
+*
+*******************************************************************************/
+
+ .weak NMI_Handler
+ .thumb_set NMI_Handler,Default_Handler
+
+ .weak HardFault_Handler
+ .thumb_set HardFault_Handler,Default_Handler
+
+ .weak MemManage_Handler
+ .thumb_set MemManage_Handler,Default_Handler
+
+ .weak BusFault_Handler
+ .thumb_set BusFault_Handler,Default_Handler
+
+ .weak UsageFault_Handler
+ .thumb_set UsageFault_Handler,Default_Handler
+
+ .weak SVC_Handler
+ .thumb_set SVC_Handler,Default_Handler
+
+ .weak DebugMon_Handler
+ .thumb_set DebugMon_Handler,Default_Handler
+
+ .weak PendSV_Handler
+ .thumb_set PendSV_Handler,Default_Handler
+
+ .weak SysTick_Handler
+ .thumb_set SysTick_Handler,Default_Handler
+
+ .weak WWDG_IRQHandler
+ .thumb_set WWDG_IRQHandler,Default_Handler
+
+ .weak PVD_IRQHandler
+ .thumb_set PVD_IRQHandler,Default_Handler
+
+ .weak TAMPER_STAMP_IRQHandler
+ .thumb_set TAMPER_STAMP_IRQHandler,Default_Handler
+
+ .weak RTC_WKUP_IRQHandler
+ .thumb_set RTC_WKUP_IRQHandler,Default_Handler
+
+ .weak FLASH_IRQHandler
+ .thumb_set FLASH_IRQHandler,Default_Handler
+
+ .weak RCC_IRQHandler
+ .thumb_set RCC_IRQHandler,Default_Handler
+
+ .weak EXTI0_IRQHandler
+ .thumb_set EXTI0_IRQHandler,Default_Handler
+
+ .weak EXTI1_IRQHandler
+ .thumb_set EXTI1_IRQHandler,Default_Handler
+
+ .weak EXTI2_IRQHandler
+ .thumb_set EXTI2_IRQHandler,Default_Handler
+
+ .weak EXTI3_IRQHandler
+ .thumb_set EXTI3_IRQHandler,Default_Handler
+
+ .weak EXTI4_IRQHandler
+ .thumb_set EXTI4_IRQHandler,Default_Handler
+
+ .weak DMA1_Channel1_IRQHandler
+ .thumb_set DMA1_Channel1_IRQHandler,Default_Handler
+
+ .weak DMA1_Channel2_IRQHandler
+ .thumb_set DMA1_Channel2_IRQHandler,Default_Handler
+
+ .weak DMA1_Channel3_IRQHandler
+ .thumb_set DMA1_Channel3_IRQHandler,Default_Handler
+
+ .weak DMA1_Channel4_IRQHandler
+ .thumb_set DMA1_Channel4_IRQHandler,Default_Handler
+
+ .weak DMA1_Channel5_IRQHandler
+ .thumb_set DMA1_Channel5_IRQHandler,Default_Handler
+
+ .weak DMA1_Channel6_IRQHandler
+ .thumb_set DMA1_Channel6_IRQHandler,Default_Handler
+
+ .weak DMA1_Channel7_IRQHandler
+ .thumb_set DMA1_Channel7_IRQHandler,Default_Handler
+
+ .weak ADC1_IRQHandler
+ .thumb_set ADC1_IRQHandler,Default_Handler
+
+ .weak USB_HP_IRQHandler
+ .thumb_set USB_HP_IRQHandler,Default_Handler
+
+ .weak USB_LP_IRQHandler
+ .thumb_set USB_LP_IRQHandler,Default_Handler
+
+ .weak DAC_IRQHandler
+ .thumb_set DAC_IRQHandler,Default_Handler
+
+ .weak COMP_IRQHandler
+ .thumb_set COMP_IRQHandler,Default_Handler
+
+ .weak EXTI9_5_IRQHandler
+ .thumb_set EXTI9_5_IRQHandler,Default_Handler
+
+ .weak LCD_IRQHandler
+ .thumb_set LCD_IRQHandler,Default_Handler
+
+ .weak TIM9_IRQHandler
+ .thumb_set TIM9_IRQHandler,Default_Handler
+
+ .weak TIM10_IRQHandler
+ .thumb_set TIM10_IRQHandler,Default_Handler
+
+ .weak TIM11_IRQHandler
+ .thumb_set TIM11_IRQHandler,Default_Handler
+
+ .weak TIM2_IRQHandler
+ .thumb_set TIM2_IRQHandler,Default_Handler
+
+ .weak TIM3_IRQHandler
+ .thumb_set TIM3_IRQHandler,Default_Handler
+
+ .weak TIM4_IRQHandler
+ .thumb_set TIM4_IRQHandler,Default_Handler
+
+ .weak I2C1_EV_IRQHandler
+ .thumb_set I2C1_EV_IRQHandler,Default_Handler
+
+ .weak I2C1_ER_IRQHandler
+ .thumb_set I2C1_ER_IRQHandler,Default_Handler
+
+ .weak I2C2_EV_IRQHandler
+ .thumb_set I2C2_EV_IRQHandler,Default_Handler
+
+ .weak I2C2_ER_IRQHandler
+ .thumb_set I2C2_ER_IRQHandler,Default_Handler
+
+ .weak SPI1_IRQHandler
+ .thumb_set SPI1_IRQHandler,Default_Handler
+
+ .weak SPI2_IRQHandler
+ .thumb_set SPI2_IRQHandler,Default_Handler
+
+ .weak USART1_IRQHandler
+ .thumb_set USART1_IRQHandler,Default_Handler
+
+ .weak USART2_IRQHandler
+ .thumb_set USART2_IRQHandler,Default_Handler
+
+ .weak USART3_IRQHandler
+ .thumb_set USART3_IRQHandler,Default_Handler
+
+ .weak EXTI15_10_IRQHandler
+ .thumb_set EXTI15_10_IRQHandler,Default_Handler
+
+ .weak RTC_Alarm_IRQHandler
+ .thumb_set RTC_Alarm_IRQHandler,Default_Handler
+
+ .weak USB_FS_WKUP_IRQHandler
+ .thumb_set USB_FS_WKUP_IRQHandler,Default_Handler
+
+ .weak TIM6_IRQHandler
+ .thumb_set TIM6_IRQHandler,Default_Handler
+
+ .weak TIM7_IRQHandler
+ .thumb_set TIM7_IRQHandler,Default_Handler
+
+/************************* (C) COPYRIGHT STMicroelectronics *****END OF FILE***/
+
diff --git a/Libraries/CMSIS/Device/ST/STM32L1xx/Source/Templates/gcc_ride7/startup_stm32l1xx_mdp.s b/Libraries/CMSIS/Device/ST/STM32L1xx/Source/Templates/gcc_ride7/startup_stm32l1xx_mdp.s
new file mode 100644
index 0000000..d9f3587
--- /dev/null
+++ b/Libraries/CMSIS/Device/ST/STM32L1xx/Source/Templates/gcc_ride7/startup_stm32l1xx_mdp.s
@@ -0,0 +1,410 @@
+/**
+ ******************************************************************************
+ * @file startup_stm32l1xx_mdp.s
+ * @author MCD Application Team
+ * @version V1.1.1
+ * @date 09-March-2012
+ * @brief STM32L1xx Ultra Low Power Medium-density Plus Devices vector table
+ * for RIDE7 toolchain.
+ * This module performs:
+ * - Set the initial SP
+ * - Set the initial PC == Reset_Handler,
+ * - Set the vector table entries with the exceptions ISR address
+ * - Branches to main in the C library (which eventually
+ * calls main()).
+ * After Reset the Cortex-M3 processor is in Thread mode,
+ * priority is Privileged, and the Stack is set to Main.
+ ******************************************************************************
+ * @attention
+ *
+ * © COPYRIGHT 2012 STMicroelectronics
+ *
+ * Licensed under MCD-ST Liberty SW License Agreement V2, (the "License");
+ * You may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at:
+ *
+ * http://www.st.com/software_license_agreement_liberty_v2
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ *
+ ******************************************************************************
+ */
+
+ .syntax unified
+ .cpu cortex-m3
+ .fpu softvfp
+ .thumb
+
+.global g_pfnVectors
+.global Default_Handler
+
+/* start address for the initialization values of the .data section.
+defined in linker script */
+.word _sidata
+/* start address for the .data section. defined in linker script */
+.word _sdata
+/* end address for the .data section. defined in linker script */
+.word _edata
+/* start address for the .bss section. defined in linker script */
+.word _sbss
+/* end address for the .bss section. defined in linker script */
+.word _ebss
+
+.equ BootRAM, 0xF108F85F
+/**
+ * @brief This is the code that gets called when the processor first
+ * starts execution following a reset event. Only the absolutely
+ * necessary set is performed, after which the application
+ * supplied main() routine is called.
+ * @param None
+ * @retval : None
+*/
+
+ .section .text.Reset_Handler
+ .weak Reset_Handler
+ .type Reset_Handler, %function
+Reset_Handler:
+
+/* Copy the data segment initializers from flash to SRAM */
+ movs r1, #0
+ b LoopCopyDataInit
+
+CopyDataInit:
+ ldr r3, =_sidata
+ ldr r3, [r3, r1]
+ str r3, [r0, r1]
+ adds r1, r1, #4
+
+LoopCopyDataInit:
+ ldr r0, =_sdata
+ ldr r3, =_edata
+ adds r2, r0, r1
+ cmp r2, r3
+ bcc CopyDataInit
+ ldr r2, =_sbss
+ b LoopFillZerobss
+/* Zero fill the bss segment. */
+FillZerobss:
+ movs r3, #0
+ str r3, [r2], #4
+
+LoopFillZerobss:
+ ldr r3, = _ebss
+ cmp r2, r3
+ bcc FillZerobss
+/* Call the clock system intitialization function.*/
+ bl SystemInit
+/* Call the application's entry point.*/
+ bl main
+ bx lr
+.size Reset_Handler, .-Reset_Handler
+
+/**
+ * @brief This is the code that gets called when the processor receives an
+ * unexpected interrupt. This simply enters an infinite loop, preserving
+ * the system state for examination by a debugger.
+ *
+ * @param None
+ * @retval None
+*/
+ .section .text.Default_Handler,"ax",%progbits
+Default_Handler:
+Infinite_Loop:
+ b Infinite_Loop
+ .size Default_Handler, .-Default_Handler
+/*******************************************************************************
+*
+* The minimal vector table for a Cortex M3. Note that the proper constructs
+* must be placed on this to ensure that it ends up at physical address
+* 0x0000.0000.
+*******************************************************************************/
+ .section .isr_vector,"a",%progbits
+ .type g_pfnVectors, %object
+ .size g_pfnVectors, .-g_pfnVectors
+
+
+g_pfnVectors:
+ .word _estack
+ .word Reset_Handler
+ .word NMI_Handler
+ .word HardFault_Handler
+ .word MemManage_Handler
+ .word BusFault_Handler
+ .word UsageFault_Handler
+ .word 0
+ .word 0
+ .word 0
+ .word 0
+ .word SVC_Handler
+ .word DebugMon_Handler
+ .word 0
+ .word PendSV_Handler
+ .word SysTick_Handler
+ .word WWDG_IRQHandler
+ .word PVD_IRQHandler
+ .word TAMPER_STAMP_IRQHandler
+ .word RTC_WKUP_IRQHandler
+ .word FLASH_IRQHandler
+ .word RCC_IRQHandler
+ .word EXTI0_IRQHandler
+ .word EXTI1_IRQHandler
+ .word EXTI2_IRQHandler
+ .word EXTI3_IRQHandler
+ .word EXTI4_IRQHandler
+ .word DMA1_Channel1_IRQHandler
+ .word DMA1_Channel2_IRQHandler
+ .word DMA1_Channel3_IRQHandler
+ .word DMA1_Channel4_IRQHandler
+ .word DMA1_Channel5_IRQHandler
+ .word DMA1_Channel6_IRQHandler
+ .word DMA1_Channel7_IRQHandler
+ .word ADC1_IRQHandler
+ .word USB_HP_IRQHandler
+ .word USB_LP_IRQHandler
+ .word DAC_IRQHandler
+ .word COMP_IRQHandler
+ .word EXTI9_5_IRQHandler
+ .word LCD_IRQHandler
+ .word TIM9_IRQHandler
+ .word TIM10_IRQHandler
+ .word TIM11_IRQHandler
+ .word TIM2_IRQHandler
+ .word TIM3_IRQHandler
+ .word TIM4_IRQHandler
+ .word I2C1_EV_IRQHandler
+ .word I2C1_ER_IRQHandler
+ .word I2C2_EV_IRQHandler
+ .word I2C2_ER_IRQHandler
+ .word SPI1_IRQHandler
+ .word SPI2_IRQHandler
+ .word USART1_IRQHandler
+ .word USART2_IRQHandler
+ .word USART3_IRQHandler
+ .word EXTI15_10_IRQHandler
+ .word RTC_Alarm_IRQHandler
+ .word USB_FS_WKUP_IRQHandler
+ .word TIM6_IRQHandler
+ .word TIM7_IRQHandler
+ .word 0
+ .word TIM5_IRQHandler
+ .word SPI3_IRQHandler
+ .word 0
+ .word 0
+ .word DMA2_Channel1_IRQHandler
+ .word DMA2_Channel2_IRQHandler
+ .word DMA2_Channel3_IRQHandler
+ .word DMA2_Channel4_IRQHandler
+ .word DMA2_Channel5_IRQHandler
+ .word AES_IRQHandler
+ .word COMP_ACQ_IRQHandler
+ .word 0
+ .word 0
+ .word 0
+ .word 0
+ .word 0
+ .word BootRAM /* @0x108. This is for boot in RAM mode for
+ STM32L15x ULtra Low Power Medium-density Plus devices. */
+
+/*******************************************************************************
+*
+* Provide weak aliases for each Exception handler to the Default_Handler.
+* As they are weak aliases, any function with the same name will override
+* this definition.
+*
+*******************************************************************************/
+
+ .weak NMI_Handler
+ .thumb_set NMI_Handler,Default_Handler
+
+ .weak HardFault_Handler
+ .thumb_set HardFault_Handler,Default_Handler
+
+ .weak MemManage_Handler
+ .thumb_set MemManage_Handler,Default_Handler
+
+ .weak BusFault_Handler
+ .thumb_set BusFault_Handler,Default_Handler
+
+ .weak UsageFault_Handler
+ .thumb_set UsageFault_Handler,Default_Handler
+
+ .weak SVC_Handler
+ .thumb_set SVC_Handler,Default_Handler
+
+ .weak DebugMon_Handler
+ .thumb_set DebugMon_Handler,Default_Handler
+
+ .weak PendSV_Handler
+ .thumb_set PendSV_Handler,Default_Handler
+
+ .weak SysTick_Handler
+ .thumb_set SysTick_Handler,Default_Handler
+
+ .weak WWDG_IRQHandler
+ .thumb_set WWDG_IRQHandler,Default_Handler
+
+ .weak PVD_IRQHandler
+ .thumb_set PVD_IRQHandler,Default_Handler
+
+ .weak TAMPER_STAMP_IRQHandler
+ .thumb_set TAMPER_STAMP_IRQHandler,Default_Handler
+
+ .weak RTC_WKUP_IRQHandler
+ .thumb_set RTC_WKUP_IRQHandler,Default_Handler
+
+ .weak FLASH_IRQHandler
+ .thumb_set FLASH_IRQHandler,Default_Handler
+
+ .weak RCC_IRQHandler
+ .thumb_set RCC_IRQHandler,Default_Handler
+
+ .weak EXTI0_IRQHandler
+ .thumb_set EXTI0_IRQHandler,Default_Handler
+
+ .weak EXTI1_IRQHandler
+ .thumb_set EXTI1_IRQHandler,Default_Handler
+
+ .weak EXTI2_IRQHandler
+ .thumb_set EXTI2_IRQHandler,Default_Handler
+
+ .weak EXTI3_IRQHandler
+ .thumb_set EXTI3_IRQHandler,Default_Handler
+
+ .weak EXTI4_IRQHandler
+ .thumb_set EXTI4_IRQHandler,Default_Handler
+
+ .weak DMA1_Channel1_IRQHandler
+ .thumb_set DMA1_Channel1_IRQHandler,Default_Handler
+
+ .weak DMA1_Channel2_IRQHandler
+ .thumb_set DMA1_Channel2_IRQHandler,Default_Handler
+
+ .weak DMA1_Channel3_IRQHandler
+ .thumb_set DMA1_Channel3_IRQHandler,Default_Handler
+
+ .weak DMA1_Channel4_IRQHandler
+ .thumb_set DMA1_Channel4_IRQHandler,Default_Handler
+
+ .weak DMA1_Channel5_IRQHandler
+ .thumb_set DMA1_Channel5_IRQHandler,Default_Handler
+
+ .weak DMA1_Channel6_IRQHandler
+ .thumb_set DMA1_Channel6_IRQHandler,Default_Handler
+
+ .weak DMA1_Channel7_IRQHandler
+ .thumb_set DMA1_Channel7_IRQHandler,Default_Handler
+
+ .weak ADC1_IRQHandler
+ .thumb_set ADC1_IRQHandler,Default_Handler
+
+ .weak USB_HP_IRQHandler
+ .thumb_set USB_HP_IRQHandler,Default_Handler
+
+ .weak USB_LP_IRQHandler
+ .thumb_set USB_LP_IRQHandler,Default_Handler
+
+ .weak DAC_IRQHandler
+ .thumb_set DAC_IRQHandler,Default_Handler
+
+ .weak COMP_IRQHandler
+ .thumb_set COMP_IRQHandler,Default_Handler
+
+ .weak EXTI9_5_IRQHandler
+ .thumb_set EXTI9_5_IRQHandler,Default_Handler
+
+ .weak LCD_IRQHandler
+ .thumb_set LCD_IRQHandler,Default_Handler
+
+ .weak TIM9_IRQHandler
+ .thumb_set TIM9_IRQHandler,Default_Handler
+
+ .weak TIM10_IRQHandler
+ .thumb_set TIM10_IRQHandler,Default_Handler
+
+ .weak TIM11_IRQHandler
+ .thumb_set TIM11_IRQHandler,Default_Handler
+
+ .weak TIM2_IRQHandler
+ .thumb_set TIM2_IRQHandler,Default_Handler
+
+ .weak TIM3_IRQHandler
+ .thumb_set TIM3_IRQHandler,Default_Handler
+
+ .weak TIM4_IRQHandler
+ .thumb_set TIM4_IRQHandler,Default_Handler
+
+ .weak I2C1_EV_IRQHandler
+ .thumb_set I2C1_EV_IRQHandler,Default_Handler
+
+ .weak I2C1_ER_IRQHandler
+ .thumb_set I2C1_ER_IRQHandler,Default_Handler
+
+ .weak I2C2_EV_IRQHandler
+ .thumb_set I2C2_EV_IRQHandler,Default_Handler
+
+ .weak I2C2_ER_IRQHandler
+ .thumb_set I2C2_ER_IRQHandler,Default_Handler
+
+ .weak SPI1_IRQHandler
+ .thumb_set SPI1_IRQHandler,Default_Handler
+
+ .weak SPI2_IRQHandler
+ .thumb_set SPI2_IRQHandler,Default_Handler
+
+ .weak USART1_IRQHandler
+ .thumb_set USART1_IRQHandler,Default_Handler
+
+ .weak USART2_IRQHandler
+ .thumb_set USART2_IRQHandler,Default_Handler
+
+ .weak USART3_IRQHandler
+ .thumb_set USART3_IRQHandler,Default_Handler
+
+ .weak EXTI15_10_IRQHandler
+ .thumb_set EXTI15_10_IRQHandler,Default_Handler
+
+ .weak RTC_Alarm_IRQHandler
+ .thumb_set RTC_Alarm_IRQHandler,Default_Handler
+
+ .weak USB_FS_WKUP_IRQHandler
+ .thumb_set USB_FS_WKUP_IRQHandler,Default_Handler
+
+ .weak TIM6_IRQHandler
+ .thumb_set TIM6_IRQHandler,Default_Handler
+
+ .weak TIM7_IRQHandler
+ .thumb_set TIM7_IRQHandler,Default_Handler
+
+ .weak TIM5_IRQHandler
+ .thumb_set TIM5_IRQHandler,Default_Handler
+
+ .weak SPI3_IRQHandler
+ .thumb_set SPI3_IRQHandler,Default_Handler
+
+ .weak DMA2_Channel1_IRQHandler
+ .thumb_set DMA2_Channel1_IRQHandler,Default_Handler
+
+ .weak DMA2_Channel2_IRQHandler
+ .thumb_set DMA2_Channel2_IRQHandler,Default_Handler
+
+ .weak DMA2_Channel3_IRQHandler
+ .thumb_set DMA2_Channel3_IRQHandler,Default_Handler
+
+ .weak DMA2_Channel4_IRQHandler
+ .thumb_set DMA2_Channel4_IRQHandler,Default_Handler
+
+ .weak DMA2_Channel5_IRQHandler
+ .thumb_set DMA2_Channel5_IRQHandler,Default_Handler
+
+ .weak AES_IRQHandler
+ .thumb_set AES_IRQHandler,Default_Handler
+
+ .weak COMP_ACQ_IRQHandler
+ .thumb_set COMP_ACQ_IRQHandler,Default_Handler
+
+/************************* (C) COPYRIGHT STMicroelectronics *****END OF FILE***/
+
diff --git a/Libraries/CMSIS/Device/ST/STM32L1xx/Source/Templates/iar/startup_stm32l1xx_hd.s b/Libraries/CMSIS/Device/ST/STM32L1xx/Source/Templates/iar/startup_stm32l1xx_hd.s
new file mode 100644
index 0000000..a92913e
--- /dev/null
+++ b/Libraries/CMSIS/Device/ST/STM32L1xx/Source/Templates/iar/startup_stm32l1xx_hd.s
@@ -0,0 +1,544 @@
+;/******************** (C) COPYRIGHT 2012 STMicroelectronics ********************
+;* File Name : startup_stm32l1xx_hd.s
+;* Author : MCD Application Team
+;* Version : V1.1.1
+;* Date : 09-March-2012
+;* Description : STM32L1xx Ultra Low Power High-density Devices vector
+;* table for EWARM toolchain.
+;* This module performs:
+;* - Set the initial SP
+;* - Set the initial PC == __iar_program_start,
+;* - Set the vector table entries with the exceptions ISR
+;* address.
+;* After Reset the Cortex-M3 processor is in Thread mode,
+;* priority is Privileged, and the Stack is set to Main.
+;********************************************************************************
+;*
+;* Licensed under MCD-ST Liberty SW License Agreement V2, (the "License");
+;* You may not use this file except in compliance with the License.
+;* You may obtain a copy of the License at:
+;*
+;* http://www.st.com/software_license_agreement_liberty_v2
+;*
+;* Unless required by applicable law or agreed to in writing, software
+;* distributed under the License is distributed on an "AS IS" BASIS,
+;* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+;* See the License for the specific language governing permissions and
+;* limitations under the License.
+;*
+;*******************************************************************************/
+;
+;
+; The modules in this file are included in the libraries, and may be replaced
+; by any user-defined modules that define the PUBLIC symbol _program_start or
+; a user defined start symbol.
+; To override the cstartup defined in the library, simply add your modified
+; version to the workbench project.
+;
+; The vector table is normally located at address 0.
+; When debugging in RAM, it can be located in RAM, aligned to at least 2^6.
+; The name "__vector_table" has special meaning for C-SPY:
+; it is where the SP start value is found, and the NVIC vector
+; table register (VTOR) is initialized to this address if != 0.
+;
+; Cortex-M version
+;
+
+ MODULE ?cstartup
+
+ ;; Forward declaration of sections.
+ SECTION CSTACK:DATA:NOROOT(3)
+
+ SECTION .intvec:CODE:NOROOT(2)
+
+ EXTERN __iar_program_start
+ EXTERN SystemInit
+ PUBLIC __vector_table
+
+ DATA
+__vector_table
+ DCD sfe(CSTACK)
+ DCD Reset_Handler ; Reset Handler
+
+ DCD NMI_Handler ; NMI Handler
+ DCD HardFault_Handler ; Hard Fault Handler
+ DCD MemManage_Handler ; MPU Fault Handler
+ DCD BusFault_Handler ; Bus Fault Handler
+ DCD UsageFault_Handler ; Usage Fault Handler
+ DCD 0 ; Reserved
+ DCD 0 ; Reserved
+ DCD 0 ; Reserved
+ DCD 0 ; Reserved
+ DCD SVC_Handler ; SVCall Handler
+ DCD DebugMon_Handler ; Debug Monitor Handler
+ DCD 0 ; Reserved
+ DCD PendSV_Handler ; PendSV Handler
+ DCD SysTick_Handler ; SysTick Handler
+
+ ; External Interrupts
+ DCD WWDG_IRQHandler ; Window Watchdog
+ DCD PVD_IRQHandler ; PVD through EXTI Line detect
+ DCD TAMPER_STAMP_IRQHandler ; Tamper and Time Stamp
+ DCD RTC_WKUP_IRQHandler ; RTC Wakeup
+ DCD FLASH_IRQHandler ; FLASH
+ DCD RCC_IRQHandler ; RCC
+ DCD EXTI0_IRQHandler ; EXTI Line 0
+ DCD EXTI1_IRQHandler ; EXTI Line 1
+ DCD EXTI2_IRQHandler ; EXTI Line 2
+ DCD EXTI3_IRQHandler ; EXTI Line 3
+ DCD EXTI4_IRQHandler ; EXTI Line 4
+ DCD DMA1_Channel1_IRQHandler ; DMA1 Channel 1
+ DCD DMA1_Channel2_IRQHandler ; DMA1 Channel 2
+ DCD DMA1_Channel3_IRQHandler ; DMA1 Channel 3
+ DCD DMA1_Channel4_IRQHandler ; DMA1 Channel 4
+ DCD DMA1_Channel5_IRQHandler ; DMA1 Channel 5
+ DCD DMA1_Channel6_IRQHandler ; DMA1 Channel 6
+ DCD DMA1_Channel7_IRQHandler ; DMA1 Channel 7
+ DCD ADC1_IRQHandler ; ADC1
+ DCD USB_HP_IRQHandler ; USB High Priority
+ DCD USB_LP_IRQHandler ; USB Low Priority
+ DCD DAC_IRQHandler ; DAC
+ DCD COMP_IRQHandler ; COMP through EXTI Line
+ DCD EXTI9_5_IRQHandler ; EXTI Line 9..5
+ DCD LCD_IRQHandler ; LCD
+ DCD TIM9_IRQHandler ; TIM9
+ DCD TIM10_IRQHandler ; TIM10
+ DCD TIM11_IRQHandler ; TIM11
+ DCD TIM2_IRQHandler ; TIM2
+ DCD TIM3_IRQHandler ; TIM3
+ DCD TIM4_IRQHandler ; TIM4
+ DCD I2C1_EV_IRQHandler ; I2C1 Event
+ DCD I2C1_ER_IRQHandler ; I2C1 Error
+ DCD I2C2_EV_IRQHandler ; I2C2 Event
+ DCD I2C2_ER_IRQHandler ; I2C2 Error
+ DCD SPI1_IRQHandler ; SPI1
+ DCD SPI2_IRQHandler ; SPI2
+ DCD USART1_IRQHandler ; USART1
+ DCD USART2_IRQHandler ; USART2
+ DCD USART3_IRQHandler ; USART3
+ DCD EXTI15_10_IRQHandler ; EXTI Line 15..10
+ DCD RTC_Alarm_IRQHandler ; RTC Alarm through EXTI Line
+ DCD USB_FS_WKUP_IRQHandler ; USB FS Wakeup from suspend
+ DCD TIM6_IRQHandler ; TIM6
+ DCD TIM7_IRQHandler ; TIM7
+ DCD SDIO_IRQHandler ; SDIO
+ DCD TIM5_IRQHandler ; TIM5
+ DCD SPI3_IRQHandler ; SPI3
+ DCD UART4_IRQHandler ; UART4
+ DCD UART5_IRQHandler ; UART5
+ DCD DMA2_Channel1_IRQHandler ; DMA2 Channel 1
+ DCD DMA2_Channel2_IRQHandler ; DMA2 Channel 2
+ DCD DMA2_Channel3_IRQHandler ; DMA2 Channel 3
+ DCD DMA2_Channel4_IRQHandler ; DMA2 Channel 4
+ DCD DMA2_Channel5_IRQHandler ; DMA2 Channel 5
+ DCD AES_IRQHandler ; AES
+ DCD COMP_ACQ_IRQHandler ; Comparator Channel Acquisition
+
+;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
+;;
+;; Default interrupt handlers.
+;;
+ THUMB
+
+ PUBWEAK Reset_Handler
+ SECTION .text:CODE:REORDER(2)
+Reset_Handler
+ LDR R0, =SystemInit
+ BLX R0
+ LDR R0, =__iar_program_start
+ BX R0
+
+ PUBWEAK NMI_Handler
+ SECTION .text:CODE:REORDER(1)
+NMI_Handler
+ B NMI_Handler
+
+
+ PUBWEAK HardFault_Handler
+ SECTION .text:CODE:REORDER(1)
+HardFault_Handler
+ B HardFault_Handler
+
+
+ PUBWEAK MemManage_Handler
+ SECTION .text:CODE:REORDER(1)
+MemManage_Handler
+ B MemManage_Handler
+
+
+ PUBWEAK BusFault_Handler
+ SECTION .text:CODE:REORDER(1)
+BusFault_Handler
+ B BusFault_Handler
+
+
+ PUBWEAK UsageFault_Handler
+ SECTION .text:CODE:REORDER(1)
+UsageFault_Handler
+ B UsageFault_Handler
+
+
+ PUBWEAK SVC_Handler
+ SECTION .text:CODE:REORDER(1)
+SVC_Handler
+ B SVC_Handler
+
+
+ PUBWEAK DebugMon_Handler
+ SECTION .text:CODE:REORDER(1)
+DebugMon_Handler
+ B DebugMon_Handler
+
+
+ PUBWEAK PendSV_Handler
+ SECTION .text:CODE:REORDER(1)
+PendSV_Handler
+ B PendSV_Handler
+
+
+ PUBWEAK SysTick_Handler
+ SECTION .text:CODE:REORDER(1)
+SysTick_Handler
+ B SysTick_Handler
+
+
+ PUBWEAK WWDG_IRQHandler
+ SECTION .text:CODE:REORDER(1)
+WWDG_IRQHandler
+ B WWDG_IRQHandler
+
+
+ PUBWEAK PVD_IRQHandler
+ SECTION .text:CODE:REORDER(1)
+PVD_IRQHandler
+ B PVD_IRQHandler
+
+
+ PUBWEAK TAMPER_STAMP_IRQHandler
+ SECTION .text:CODE:REORDER(1)
+TAMPER_STAMP_IRQHandler
+ B TAMPER_STAMP_IRQHandler
+
+
+ PUBWEAK RTC_WKUP_IRQHandler
+ SECTION .text:CODE:REORDER(1)
+RTC_WKUP_IRQHandler
+ B RTC_WKUP_IRQHandler
+
+
+ PUBWEAK FLASH_IRQHandler
+ SECTION .text:CODE:REORDER(1)
+FLASH_IRQHandler
+ B FLASH_IRQHandler
+
+
+ PUBWEAK RCC_IRQHandler
+ SECTION .text:CODE:REORDER(1)
+RCC_IRQHandler
+ B RCC_IRQHandler
+
+
+ PUBWEAK EXTI0_IRQHandler
+ SECTION .text:CODE:REORDER(1)
+EXTI0_IRQHandler
+ B EXTI0_IRQHandler
+
+
+ PUBWEAK EXTI1_IRQHandler
+ SECTION .text:CODE:REORDER(1)
+EXTI1_IRQHandler
+ B EXTI1_IRQHandler
+
+
+ PUBWEAK EXTI2_IRQHandler
+ SECTION .text:CODE:REORDER(1)
+EXTI2_IRQHandler
+ B EXTI2_IRQHandler
+
+
+ PUBWEAK EXTI3_IRQHandler
+ SECTION .text:CODE:REORDER(1)
+EXTI3_IRQHandler
+ B EXTI3_IRQHandler
+
+
+ PUBWEAK EXTI4_IRQHandler
+ SECTION .text:CODE:REORDER(1)
+EXTI4_IRQHandler
+ B EXTI4_IRQHandler
+
+
+ PUBWEAK DMA1_Channel1_IRQHandler
+ SECTION .text:CODE:REORDER(1)
+DMA1_Channel1_IRQHandler
+ B DMA1_Channel1_IRQHandler
+
+
+ PUBWEAK DMA1_Channel2_IRQHandler
+ SECTION .text:CODE:REORDER(1)
+DMA1_Channel2_IRQHandler
+ B DMA1_Channel2_IRQHandler
+
+
+ PUBWEAK DMA1_Channel3_IRQHandler
+ SECTION .text:CODE:REORDER(1)
+DMA1_Channel3_IRQHandler
+ B DMA1_Channel3_IRQHandler
+
+
+ PUBWEAK DMA1_Channel4_IRQHandler
+ SECTION .text:CODE:REORDER(1)
+DMA1_Channel4_IRQHandler
+ B DMA1_Channel4_IRQHandler
+
+
+ PUBWEAK DMA1_Channel5_IRQHandler
+ SECTION .text:CODE:REORDER(1)
+DMA1_Channel5_IRQHandler
+ B DMA1_Channel5_IRQHandler
+
+
+ PUBWEAK DMA1_Channel6_IRQHandler
+ SECTION .text:CODE:REORDER(1)
+DMA1_Channel6_IRQHandler
+ B DMA1_Channel6_IRQHandler
+
+
+ PUBWEAK DMA1_Channel7_IRQHandler
+ SECTION .text:CODE:REORDER(1)
+DMA1_Channel7_IRQHandler
+ B DMA1_Channel7_IRQHandler
+
+
+ PUBWEAK ADC1_IRQHandler
+ SECTION .text:CODE:REORDER(1)
+ADC1_IRQHandler
+ B ADC1_IRQHandler
+
+
+ PUBWEAK USB_HP_IRQHandler
+ SECTION .text:CODE:REORDER(1)
+USB_HP_IRQHandler
+ B USB_HP_IRQHandler
+
+
+ PUBWEAK USB_LP_IRQHandler
+ SECTION .text:CODE:REORDER(1)
+USB_LP_IRQHandler
+ B USB_LP_IRQHandler
+
+
+ PUBWEAK DAC_IRQHandler
+ SECTION .text:CODE:REORDER(1)
+DAC_IRQHandler
+ B DAC_IRQHandler
+
+
+ PUBWEAK COMP_IRQHandler
+ SECTION .text:CODE:REORDER(1)
+COMP_IRQHandler
+ B COMP_IRQHandler
+
+
+ PUBWEAK EXTI9_5_IRQHandler
+ SECTION .text:CODE:REORDER(1)
+EXTI9_5_IRQHandler
+ B EXTI9_5_IRQHandler
+
+
+ PUBWEAK LCD_IRQHandler
+ SECTION .text:CODE:REORDER(1)
+LCD_IRQHandler
+ B LCD_IRQHandler
+
+
+ PUBWEAK TIM9_IRQHandler
+ SECTION .text:CODE:REORDER(1)
+TIM9_IRQHandler
+ B TIM9_IRQHandler
+
+
+ PUBWEAK TIM10_IRQHandler
+ SECTION .text:CODE:REORDER(1)
+TIM10_IRQHandler
+ B TIM10_IRQHandler
+
+
+ PUBWEAK TIM11_IRQHandler
+ SECTION .text:CODE:REORDER(1)
+TIM11_IRQHandler
+ B TIM11_IRQHandler
+
+
+ PUBWEAK TIM2_IRQHandler
+ SECTION .text:CODE:REORDER(1)
+TIM2_IRQHandler
+ B TIM2_IRQHandler
+
+
+ PUBWEAK TIM3_IRQHandler
+ SECTION .text:CODE:REORDER(1)
+TIM3_IRQHandler
+ B TIM3_IRQHandler
+
+
+ PUBWEAK TIM4_IRQHandler
+ SECTION .text:CODE:REORDER(1)
+TIM4_IRQHandler
+ B TIM4_IRQHandler
+
+
+ PUBWEAK I2C1_EV_IRQHandler
+ SECTION .text:CODE:REORDER(1)
+I2C1_EV_IRQHandler
+ B I2C1_EV_IRQHandler
+
+
+ PUBWEAK I2C1_ER_IRQHandler
+ SECTION .text:CODE:REORDER(1)
+I2C1_ER_IRQHandler
+ B I2C1_ER_IRQHandler
+
+
+ PUBWEAK I2C2_EV_IRQHandler
+ SECTION .text:CODE:REORDER(1)
+I2C2_EV_IRQHandler
+ B I2C2_EV_IRQHandler
+
+
+ PUBWEAK I2C2_ER_IRQHandler
+ SECTION .text:CODE:REORDER(1)
+I2C2_ER_IRQHandler
+ B I2C2_ER_IRQHandler
+
+
+ PUBWEAK SPI1_IRQHandler
+ SECTION .text:CODE:REORDER(1)
+SPI1_IRQHandler
+ B SPI1_IRQHandler
+
+
+ PUBWEAK SPI2_IRQHandler
+ SECTION .text:CODE:REORDER(1)
+SPI2_IRQHandler
+ B SPI2_IRQHandler
+
+
+ PUBWEAK USART1_IRQHandler
+ SECTION .text:CODE:REORDER(1)
+USART1_IRQHandler
+ B USART1_IRQHandler
+
+
+ PUBWEAK USART2_IRQHandler
+ SECTION .text:CODE:REORDER(1)
+USART2_IRQHandler
+ B USART2_IRQHandler
+
+
+ PUBWEAK USART3_IRQHandler
+ SECTION .text:CODE:REORDER(1)
+USART3_IRQHandler
+ B USART3_IRQHandler
+
+
+ PUBWEAK EXTI15_10_IRQHandler
+ SECTION .text:CODE:REORDER(1)
+EXTI15_10_IRQHandler
+ B EXTI15_10_IRQHandler
+
+
+ PUBWEAK RTC_Alarm_IRQHandler
+ SECTION .text:CODE:REORDER(1)
+RTC_Alarm_IRQHandler
+ B RTC_Alarm_IRQHandler
+
+
+ PUBWEAK USB_FS_WKUP_IRQHandler
+ SECTION .text:CODE:REORDER(1)
+USB_FS_WKUP_IRQHandler
+ B USB_FS_WKUP_IRQHandler
+
+
+ PUBWEAK TIM6_IRQHandler
+ SECTION .text:CODE:REORDER(1)
+TIM6_IRQHandler
+ B TIM6_IRQHandler
+
+
+ PUBWEAK TIM7_IRQHandler
+ SECTION .text:CODE:REORDER(1)
+TIM7_IRQHandler
+ B TIM7_IRQHandler
+
+ PUBWEAK SDIO_IRQHandler
+ SECTION .text:CODE:REORDER(1)
+SDIO_IRQHandler
+ B SDIO_IRQHandler
+
+
+ PUBWEAK TIM5_IRQHandler
+ SECTION .text:CODE:REORDER(1)
+TIM5_IRQHandler
+ B TIM5_IRQHandler
+
+ PUBWEAK SPI3_IRQHandler
+ SECTION .text:CODE:REORDER(1)
+SPI3_IRQHandler
+ B SPI3_IRQHandler
+
+
+ PUBWEAK UART4_IRQHandler
+ SECTION .text:CODE:REORDER(1)
+UART4_IRQHandler
+ B UART4_IRQHandler
+
+
+ PUBWEAK UART5_IRQHandler
+ SECTION .text:CODE:REORDER(1)
+UART5_IRQHandler
+ B UART5_IRQHandler
+
+ PUBWEAK DMA2_Channel1_IRQHandler
+ SECTION .text:CODE:REORDER(1)
+DMA2_Channel1_IRQHandler
+ B DMA2_Channel1_IRQHandler
+
+
+ PUBWEAK DMA2_Channel2_IRQHandler
+ SECTION .text:CODE:REORDER(1)
+DMA2_Channel2_IRQHandler
+ B DMA2_Channel2_IRQHandler
+
+
+ PUBWEAK DMA2_Channel3_IRQHandler
+ SECTION .text:CODE:REORDER(1)
+DMA2_Channel3_IRQHandler
+ B DMA2_Channel3_IRQHandler
+
+
+ PUBWEAK DMA2_Channel4_IRQHandler
+ SECTION .text:CODE:REORDER(1)
+DMA2_Channel4_IRQHandler
+ B DMA2_Channel4_IRQHandler
+
+
+ PUBWEAK DMA2_Channel5_IRQHandler
+ SECTION .text:CODE:REORDER(1)
+DMA2_Channel5_IRQHandler
+ B DMA2_Channel5_IRQHandler
+
+
+ PUBWEAK AES_IRQHandler
+ SECTION .text:CODE:REORDER(1)
+AES_IRQHandler
+ B AES_IRQHandler
+
+
+ PUBWEAK COMP_ACQ_IRQHandler
+ SECTION .text:CODE:REORDER(1)
+COMP_ACQ_IRQHandler
+ B COMP_ACQ_IRQHandler
+
+ END
+/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
diff --git a/Libraries/CMSIS/Device/ST/STM32L1xx/Source/Templates/iar/startup_stm32l1xx_md.s b/Libraries/CMSIS/Device/ST/STM32L1xx/Source/Templates/iar/startup_stm32l1xx_md.s
new file mode 100644
index 0000000..552b42d
--- /dev/null
+++ b/Libraries/CMSIS/Device/ST/STM32L1xx/Source/Templates/iar/startup_stm32l1xx_md.s
@@ -0,0 +1,463 @@
+;/******************** (C) COPYRIGHT 2012 STMicroelectronics ********************
+;* File Name : startup_stm32l1xx_md.s
+;* Author : MCD Application Team
+;* Version : V1.1.1
+;* Date : 09-March-2012
+;* Description : STM32L1xx Ultra Low Power Medium-density Devices vector
+;* table for EWARM toolchain.
+;* This module performs:
+;* - Set the initial SP
+;* - Set the initial PC == __iar_program_start,
+;* - Set the vector table entries with the exceptions ISR
+;* address.
+;* After Reset the Cortex-M3 processor is in Thread mode,
+;* priority is Privileged, and the Stack is set to Main.
+;********************************************************************************
+;*
+;* Licensed under MCD-ST Liberty SW License Agreement V2, (the "License");
+;* You may not use this file except in compliance with the License.
+;* You may obtain a copy of the License at:
+;*
+;* http://www.st.com/software_license_agreement_liberty_v2
+;*
+;* Unless required by applicable law or agreed to in writing, software
+;* distributed under the License is distributed on an "AS IS" BASIS,
+;* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+;* See the License for the specific language governing permissions and
+;* limitations under the License.
+;*
+;*******************************************************************************/
+;
+;
+; The modules in this file are included in the libraries, and may be replaced
+; by any user-defined modules that define the PUBLIC symbol _program_start or
+; a user defined start symbol.
+; To override the cstartup defined in the library, simply add your modified
+; version to the workbench project.
+;
+; The vector table is normally located at address 0.
+; When debugging in RAM, it can be located in RAM, aligned to at least 2^6.
+; The name "__vector_table" has special meaning for C-SPY:
+; it is where the SP start value is found, and the NVIC vector
+; table register (VTOR) is initialized to this address if != 0.
+;
+; Cortex-M version
+;
+
+ MODULE ?cstartup
+
+ ;; Forward declaration of sections.
+ SECTION CSTACK:DATA:NOROOT(3)
+
+ SECTION .intvec:CODE:NOROOT(2)
+
+ EXTERN __iar_program_start
+ EXTERN SystemInit
+ PUBLIC __vector_table
+
+ DATA
+__vector_table
+ DCD sfe(CSTACK)
+ DCD Reset_Handler ; Reset Handler
+
+ DCD NMI_Handler ; NMI Handler
+ DCD HardFault_Handler ; Hard Fault Handler
+ DCD MemManage_Handler ; MPU Fault Handler
+ DCD BusFault_Handler ; Bus Fault Handler
+ DCD UsageFault_Handler ; Usage Fault Handler
+ DCD 0 ; Reserved
+ DCD 0 ; Reserved
+ DCD 0 ; Reserved
+ DCD 0 ; Reserved
+ DCD SVC_Handler ; SVCall Handler
+ DCD DebugMon_Handler ; Debug Monitor Handler
+ DCD 0 ; Reserved
+ DCD PendSV_Handler ; PendSV Handler
+ DCD SysTick_Handler ; SysTick Handler
+
+ ; External Interrupts
+ DCD WWDG_IRQHandler ; Window Watchdog
+ DCD PVD_IRQHandler ; PVD through EXTI Line detect
+ DCD TAMPER_STAMP_IRQHandler ; Tamper and Time Stamp
+ DCD RTC_WKUP_IRQHandler ; RTC Wakeup
+ DCD FLASH_IRQHandler ; FLASH
+ DCD RCC_IRQHandler ; RCC
+ DCD EXTI0_IRQHandler ; EXTI Line 0
+ DCD EXTI1_IRQHandler ; EXTI Line 1
+ DCD EXTI2_IRQHandler ; EXTI Line 2
+ DCD EXTI3_IRQHandler ; EXTI Line 3
+ DCD EXTI4_IRQHandler ; EXTI Line 4
+ DCD DMA1_Channel1_IRQHandler ; DMA1 Channel 1
+ DCD DMA1_Channel2_IRQHandler ; DMA1 Channel 2
+ DCD DMA1_Channel3_IRQHandler ; DMA1 Channel 3
+ DCD DMA1_Channel4_IRQHandler ; DMA1 Channel 4
+ DCD DMA1_Channel5_IRQHandler ; DMA1 Channel 5
+ DCD DMA1_Channel6_IRQHandler ; DMA1 Channel 6
+ DCD DMA1_Channel7_IRQHandler ; DMA1 Channel 7
+ DCD ADC1_IRQHandler ; ADC1
+ DCD USB_HP_IRQHandler ; USB High Priority
+ DCD USB_LP_IRQHandler ; USB Low Priority
+ DCD DAC_IRQHandler ; DAC
+ DCD COMP_IRQHandler ; COMP through EXTI Line
+ DCD EXTI9_5_IRQHandler ; EXTI Line 9..5
+ DCD LCD_IRQHandler ; LCD
+ DCD TIM9_IRQHandler ; TIM9
+ DCD TIM10_IRQHandler ; TIM10
+ DCD TIM11_IRQHandler ; TIM11
+ DCD TIM2_IRQHandler ; TIM2
+ DCD TIM3_IRQHandler ; TIM3
+ DCD TIM4_IRQHandler ; TIM4
+ DCD I2C1_EV_IRQHandler ; I2C1 Event
+ DCD I2C1_ER_IRQHandler ; I2C1 Error
+ DCD I2C2_EV_IRQHandler ; I2C2 Event
+ DCD I2C2_ER_IRQHandler ; I2C2 Error
+ DCD SPI1_IRQHandler ; SPI1
+ DCD SPI2_IRQHandler ; SPI2
+ DCD USART1_IRQHandler ; USART1
+ DCD USART2_IRQHandler ; USART2
+ DCD USART3_IRQHandler ; USART3
+ DCD EXTI15_10_IRQHandler ; EXTI Line 15..10
+ DCD RTC_Alarm_IRQHandler ; RTC Alarm through EXTI Line
+ DCD USB_FS_WKUP_IRQHandler ; USB FS Wakeup from suspend
+ DCD TIM6_IRQHandler ; TIM6
+ DCD TIM7_IRQHandler ; TIM7
+
+;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
+;;
+;; Default interrupt handlers.
+;;
+ THUMB
+
+ PUBWEAK Reset_Handler
+ SECTION .text:CODE:REORDER(2)
+Reset_Handler
+ LDR R0, =SystemInit
+ BLX R0
+ LDR R0, =__iar_program_start
+ BX R0
+
+ PUBWEAK NMI_Handler
+ SECTION .text:CODE:REORDER(1)
+NMI_Handler
+ B NMI_Handler
+
+
+ PUBWEAK HardFault_Handler
+ SECTION .text:CODE:REORDER(1)
+HardFault_Handler
+ B HardFault_Handler
+
+
+ PUBWEAK MemManage_Handler
+ SECTION .text:CODE:REORDER(1)
+MemManage_Handler
+ B MemManage_Handler
+
+
+ PUBWEAK BusFault_Handler
+ SECTION .text:CODE:REORDER(1)
+BusFault_Handler
+ B BusFault_Handler
+
+
+ PUBWEAK UsageFault_Handler
+ SECTION .text:CODE:REORDER(1)
+UsageFault_Handler
+ B UsageFault_Handler
+
+
+ PUBWEAK SVC_Handler
+ SECTION .text:CODE:REORDER(1)
+SVC_Handler
+ B SVC_Handler
+
+
+ PUBWEAK DebugMon_Handler
+ SECTION .text:CODE:REORDER(1)
+DebugMon_Handler
+ B DebugMon_Handler
+
+
+ PUBWEAK PendSV_Handler
+ SECTION .text:CODE:REORDER(1)
+PendSV_Handler
+ B PendSV_Handler
+
+
+ PUBWEAK SysTick_Handler
+ SECTION .text:CODE:REORDER(1)
+SysTick_Handler
+ B SysTick_Handler
+
+
+ PUBWEAK WWDG_IRQHandler
+ SECTION .text:CODE:REORDER(1)
+WWDG_IRQHandler
+ B WWDG_IRQHandler
+
+
+ PUBWEAK PVD_IRQHandler
+ SECTION .text:CODE:REORDER(1)
+PVD_IRQHandler
+ B PVD_IRQHandler
+
+
+ PUBWEAK TAMPER_STAMP_IRQHandler
+ SECTION .text:CODE:REORDER(1)
+TAMPER_STAMP_IRQHandler
+ B TAMPER_STAMP_IRQHandler
+
+
+ PUBWEAK RTC_WKUP_IRQHandler
+ SECTION .text:CODE:REORDER(1)
+RTC_WKUP_IRQHandler
+ B RTC_WKUP_IRQHandler
+
+
+ PUBWEAK FLASH_IRQHandler
+ SECTION .text:CODE:REORDER(1)
+FLASH_IRQHandler
+ B FLASH_IRQHandler
+
+
+ PUBWEAK RCC_IRQHandler
+ SECTION .text:CODE:REORDER(1)
+RCC_IRQHandler
+ B RCC_IRQHandler
+
+
+ PUBWEAK EXTI0_IRQHandler
+ SECTION .text:CODE:REORDER(1)
+EXTI0_IRQHandler
+ B EXTI0_IRQHandler
+
+
+ PUBWEAK EXTI1_IRQHandler
+ SECTION .text:CODE:REORDER(1)
+EXTI1_IRQHandler
+ B EXTI1_IRQHandler
+
+
+ PUBWEAK EXTI2_IRQHandler
+ SECTION .text:CODE:REORDER(1)
+EXTI2_IRQHandler
+ B EXTI2_IRQHandler
+
+
+ PUBWEAK EXTI3_IRQHandler
+ SECTION .text:CODE:REORDER(1)
+EXTI3_IRQHandler
+ B EXTI3_IRQHandler
+
+
+ PUBWEAK EXTI4_IRQHandler
+ SECTION .text:CODE:REORDER(1)
+EXTI4_IRQHandler
+ B EXTI4_IRQHandler
+
+
+ PUBWEAK DMA1_Channel1_IRQHandler
+ SECTION .text:CODE:REORDER(1)
+DMA1_Channel1_IRQHandler
+ B DMA1_Channel1_IRQHandler
+
+
+ PUBWEAK DMA1_Channel2_IRQHandler
+ SECTION .text:CODE:REORDER(1)
+DMA1_Channel2_IRQHandler
+ B DMA1_Channel2_IRQHandler
+
+
+ PUBWEAK DMA1_Channel3_IRQHandler
+ SECTION .text:CODE:REORDER(1)
+DMA1_Channel3_IRQHandler
+ B DMA1_Channel3_IRQHandler
+
+
+ PUBWEAK DMA1_Channel4_IRQHandler
+ SECTION .text:CODE:REORDER(1)
+DMA1_Channel4_IRQHandler
+ B DMA1_Channel4_IRQHandler
+
+
+ PUBWEAK DMA1_Channel5_IRQHandler
+ SECTION .text:CODE:REORDER(1)
+DMA1_Channel5_IRQHandler
+ B DMA1_Channel5_IRQHandler
+
+
+ PUBWEAK DMA1_Channel6_IRQHandler
+ SECTION .text:CODE:REORDER(1)
+DMA1_Channel6_IRQHandler
+ B DMA1_Channel6_IRQHandler
+
+
+ PUBWEAK DMA1_Channel7_IRQHandler
+ SECTION .text:CODE:REORDER(1)
+DMA1_Channel7_IRQHandler
+ B DMA1_Channel7_IRQHandler
+
+
+ PUBWEAK ADC1_IRQHandler
+ SECTION .text:CODE:REORDER(1)
+ADC1_IRQHandler
+ B ADC1_IRQHandler
+
+
+ PUBWEAK USB_HP_IRQHandler
+ SECTION .text:CODE:REORDER(1)
+USB_HP_IRQHandler
+ B USB_HP_IRQHandler
+
+
+ PUBWEAK USB_LP_IRQHandler
+ SECTION .text:CODE:REORDER(1)
+USB_LP_IRQHandler
+ B USB_LP_IRQHandler
+
+
+ PUBWEAK DAC_IRQHandler
+ SECTION .text:CODE:REORDER(1)
+DAC_IRQHandler
+ B DAC_IRQHandler
+
+
+ PUBWEAK COMP_IRQHandler
+ SECTION .text:CODE:REORDER(1)
+COMP_IRQHandler
+ B COMP_IRQHandler
+
+
+ PUBWEAK EXTI9_5_IRQHandler
+ SECTION .text:CODE:REORDER(1)
+EXTI9_5_IRQHandler
+ B EXTI9_5_IRQHandler
+
+
+ PUBWEAK LCD_IRQHandler
+ SECTION .text:CODE:REORDER(1)
+LCD_IRQHandler
+ B LCD_IRQHandler
+
+
+ PUBWEAK TIM9_IRQHandler
+ SECTION .text:CODE:REORDER(1)
+TIM9_IRQHandler
+ B TIM9_IRQHandler
+
+
+ PUBWEAK TIM10_IRQHandler
+ SECTION .text:CODE:REORDER(1)
+TIM10_IRQHandler
+ B TIM10_IRQHandler
+
+
+ PUBWEAK TIM11_IRQHandler
+ SECTION .text:CODE:REORDER(1)
+TIM11_IRQHandler
+ B TIM11_IRQHandler
+
+
+ PUBWEAK TIM2_IRQHandler
+ SECTION .text:CODE:REORDER(1)
+TIM2_IRQHandler
+ B TIM2_IRQHandler
+
+
+ PUBWEAK TIM3_IRQHandler
+ SECTION .text:CODE:REORDER(1)
+TIM3_IRQHandler
+ B TIM3_IRQHandler
+
+
+ PUBWEAK TIM4_IRQHandler
+ SECTION .text:CODE:REORDER(1)
+TIM4_IRQHandler
+ B TIM4_IRQHandler
+
+
+ PUBWEAK I2C1_EV_IRQHandler
+ SECTION .text:CODE:REORDER(1)
+I2C1_EV_IRQHandler
+ B I2C1_EV_IRQHandler
+
+
+ PUBWEAK I2C1_ER_IRQHandler
+ SECTION .text:CODE:REORDER(1)
+I2C1_ER_IRQHandler
+ B I2C1_ER_IRQHandler
+
+
+ PUBWEAK I2C2_EV_IRQHandler
+ SECTION .text:CODE:REORDER(1)
+I2C2_EV_IRQHandler
+ B I2C2_EV_IRQHandler
+
+
+ PUBWEAK I2C2_ER_IRQHandler
+ SECTION .text:CODE:REORDER(1)
+I2C2_ER_IRQHandler
+ B I2C2_ER_IRQHandler
+
+
+ PUBWEAK SPI1_IRQHandler
+ SECTION .text:CODE:REORDER(1)
+SPI1_IRQHandler
+ B SPI1_IRQHandler
+
+
+ PUBWEAK SPI2_IRQHandler
+ SECTION .text:CODE:REORDER(1)
+SPI2_IRQHandler
+ B SPI2_IRQHandler
+
+
+ PUBWEAK USART1_IRQHandler
+ SECTION .text:CODE:REORDER(1)
+USART1_IRQHandler
+ B USART1_IRQHandler
+
+
+ PUBWEAK USART2_IRQHandler
+ SECTION .text:CODE:REORDER(1)
+USART2_IRQHandler
+ B USART2_IRQHandler
+
+
+ PUBWEAK USART3_IRQHandler
+ SECTION .text:CODE:REORDER(1)
+USART3_IRQHandler
+ B USART3_IRQHandler
+
+
+ PUBWEAK EXTI15_10_IRQHandler
+ SECTION .text:CODE:REORDER(1)
+EXTI15_10_IRQHandler
+ B EXTI15_10_IRQHandler
+
+
+ PUBWEAK RTC_Alarm_IRQHandler
+ SECTION .text:CODE:REORDER(1)
+RTC_Alarm_IRQHandler
+ B RTC_Alarm_IRQHandler
+
+
+ PUBWEAK USB_FS_WKUP_IRQHandler
+ SECTION .text:CODE:REORDER(1)
+USB_FS_WKUP_IRQHandler
+ B USB_FS_WKUP_IRQHandler
+
+
+ PUBWEAK TIM6_IRQHandler
+ SECTION .text:CODE:REORDER(1)
+TIM6_IRQHandler
+ B TIM6_IRQHandler
+
+
+ PUBWEAK TIM7_IRQHandler
+ SECTION .text:CODE:REORDER(1)
+TIM7_IRQHandler
+ B TIM7_IRQHandler
+
+ END
+/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
diff --git a/Libraries/CMSIS/Device/ST/STM32L1xx/Source/Templates/iar/startup_stm32l1xx_mdp.s b/Libraries/CMSIS/Device/ST/STM32L1xx/Source/Templates/iar/startup_stm32l1xx_mdp.s
new file mode 100644
index 0000000..cba4f98
--- /dev/null
+++ b/Libraries/CMSIS/Device/ST/STM32L1xx/Source/Templates/iar/startup_stm32l1xx_mdp.s
@@ -0,0 +1,520 @@
+;/******************** (C) COPYRIGHT 2012 STMicroelectronics ********************
+;* File Name : startup_stm32l1xx_mdp.s
+;* Author : MCD Application Team
+;* Version : V1.1.1
+;* Date : 09-March-2012
+;* Description : STM32L1xx Ultra Low Power Medium-density Plus Devices vector
+;* table for EWARM toolchain.
+;* This module performs:
+;* - Set the initial SP
+;* - Set the initial PC == __iar_program_start,
+;* - Set the vector table entries with the exceptions ISR
+;* address.
+;* After Reset the Cortex-M3 processor is in Thread mode,
+;* priority is Privileged, and the Stack is set to Main.
+;********************************************************************************
+;*
+;* Licensed under MCD-ST Liberty SW License Agreement V2, (the "License");
+;* You may not use this file except in compliance with the License.
+;* You may obtain a copy of the License at:
+;*
+;* http://www.st.com/software_license_agreement_liberty_v2
+;*
+;* Unless required by applicable law or agreed to in writing, software
+;* distributed under the License is distributed on an "AS IS" BASIS,
+;* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+;* See the License for the specific language governing permissions and
+;* limitations under the License.
+;*
+;*******************************************************************************/
+;
+;
+; The modules in this file are included in the libraries, and may be replaced
+; by any user-defined modules that define the PUBLIC symbol _program_start or
+; a user defined start symbol.
+; To override the cstartup defined in the library, simply add your modified
+; version to the workbench project.
+;
+; The vector table is normally located at address 0.
+; When debugging in RAM, it can be located in RAM, aligned to at least 2^6.
+; The name "__vector_table" has special meaning for C-SPY:
+; it is where the SP start value is found, and the NVIC vector
+; table register (VTOR) is initialized to this address if != 0.
+;
+; Cortex-M version
+;
+
+ MODULE ?cstartup
+
+ ;; Forward declaration of sections.
+ SECTION CSTACK:DATA:NOROOT(3)
+
+ SECTION .intvec:CODE:NOROOT(2)
+
+ EXTERN __iar_program_start
+ EXTERN SystemInit
+ PUBLIC __vector_table
+
+ DATA
+__vector_table
+ DCD sfe(CSTACK)
+ DCD Reset_Handler ; Reset Handler
+
+ DCD NMI_Handler ; NMI Handler
+ DCD HardFault_Handler ; Hard Fault Handler
+ DCD MemManage_Handler ; MPU Fault Handler
+ DCD BusFault_Handler ; Bus Fault Handler
+ DCD UsageFault_Handler ; Usage Fault Handler
+ DCD 0 ; Reserved
+ DCD 0 ; Reserved
+ DCD 0 ; Reserved
+ DCD 0 ; Reserved
+ DCD SVC_Handler ; SVCall Handler
+ DCD DebugMon_Handler ; Debug Monitor Handler
+ DCD 0 ; Reserved
+ DCD PendSV_Handler ; PendSV Handler
+ DCD SysTick_Handler ; SysTick Handler
+
+ ; External Interrupts
+ DCD WWDG_IRQHandler ; Window Watchdog
+ DCD PVD_IRQHandler ; PVD through EXTI Line detect
+ DCD TAMPER_STAMP_IRQHandler ; Tamper and Time Stamp
+ DCD RTC_WKUP_IRQHandler ; RTC Wakeup
+ DCD FLASH_IRQHandler ; FLASH
+ DCD RCC_IRQHandler ; RCC
+ DCD EXTI0_IRQHandler ; EXTI Line 0
+ DCD EXTI1_IRQHandler ; EXTI Line 1
+ DCD EXTI2_IRQHandler ; EXTI Line 2
+ DCD EXTI3_IRQHandler ; EXTI Line 3
+ DCD EXTI4_IRQHandler ; EXTI Line 4
+ DCD DMA1_Channel1_IRQHandler ; DMA1 Channel 1
+ DCD DMA1_Channel2_IRQHandler ; DMA1 Channel 2
+ DCD DMA1_Channel3_IRQHandler ; DMA1 Channel 3
+ DCD DMA1_Channel4_IRQHandler ; DMA1 Channel 4
+ DCD DMA1_Channel5_IRQHandler ; DMA1 Channel 5
+ DCD DMA1_Channel6_IRQHandler ; DMA1 Channel 6
+ DCD DMA1_Channel7_IRQHandler ; DMA1 Channel 7
+ DCD ADC1_IRQHandler ; ADC1
+ DCD USB_HP_IRQHandler ; USB High Priority
+ DCD USB_LP_IRQHandler ; USB Low Priority
+ DCD DAC_IRQHandler ; DAC
+ DCD COMP_IRQHandler ; COMP through EXTI Line
+ DCD EXTI9_5_IRQHandler ; EXTI Line 9..5
+ DCD LCD_IRQHandler ; LCD
+ DCD TIM9_IRQHandler ; TIM9
+ DCD TIM10_IRQHandler ; TIM10
+ DCD TIM11_IRQHandler ; TIM11
+ DCD TIM2_IRQHandler ; TIM2
+ DCD TIM3_IRQHandler ; TIM3
+ DCD TIM4_IRQHandler ; TIM4
+ DCD I2C1_EV_IRQHandler ; I2C1 Event
+ DCD I2C1_ER_IRQHandler ; I2C1 Error
+ DCD I2C2_EV_IRQHandler ; I2C2 Event
+ DCD I2C2_ER_IRQHandler ; I2C2 Error
+ DCD SPI1_IRQHandler ; SPI1
+ DCD SPI2_IRQHandler ; SPI2
+ DCD USART1_IRQHandler ; USART1
+ DCD USART2_IRQHandler ; USART2
+ DCD USART3_IRQHandler ; USART3
+ DCD EXTI15_10_IRQHandler ; EXTI Line 15..10
+ DCD RTC_Alarm_IRQHandler ; RTC Alarm through EXTI Line
+ DCD USB_FS_WKUP_IRQHandler ; USB FS Wakeup from suspend
+ DCD TIM6_IRQHandler ; TIM6
+ DCD TIM7_IRQHandler ; TIM7
+ DCD 0 ; Reserved
+ DCD TIM5_IRQHandler ; TIM5
+ DCD SPI3_IRQHandler ; SPI3
+ DCD 0 ; Reserved
+ DCD 0 ; Reserved
+ DCD DMA2_Channel1_IRQHandler ; DMA2 Channel 1
+ DCD DMA2_Channel2_IRQHandler ; DMA2 Channel 2
+ DCD DMA2_Channel3_IRQHandler ; DMA2 Channel 3
+ DCD DMA2_Channel4_IRQHandler ; DMA2 Channel 4
+ DCD DMA2_Channel5_IRQHandler ; DMA2 Channel 5
+ DCD AES_IRQHandler ; AES
+ DCD COMP_ACQ_IRQHandler ; Comparator Channel Acquisition
+
+;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
+;;
+;; Default interrupt handlers.
+;;
+ THUMB
+
+ PUBWEAK Reset_Handler
+ SECTION .text:CODE:REORDER(2)
+Reset_Handler
+ LDR R0, =SystemInit
+ BLX R0
+ LDR R0, =__iar_program_start
+ BX R0
+
+ PUBWEAK NMI_Handler
+ SECTION .text:CODE:REORDER(1)
+NMI_Handler
+ B NMI_Handler
+
+
+ PUBWEAK HardFault_Handler
+ SECTION .text:CODE:REORDER(1)
+HardFault_Handler
+ B HardFault_Handler
+
+
+ PUBWEAK MemManage_Handler
+ SECTION .text:CODE:REORDER(1)
+MemManage_Handler
+ B MemManage_Handler
+
+
+ PUBWEAK BusFault_Handler
+ SECTION .text:CODE:REORDER(1)
+BusFault_Handler
+ B BusFault_Handler
+
+
+ PUBWEAK UsageFault_Handler
+ SECTION .text:CODE:REORDER(1)
+UsageFault_Handler
+ B UsageFault_Handler
+
+
+ PUBWEAK SVC_Handler
+ SECTION .text:CODE:REORDER(1)
+SVC_Handler
+ B SVC_Handler
+
+
+ PUBWEAK DebugMon_Handler
+ SECTION .text:CODE:REORDER(1)
+DebugMon_Handler
+ B DebugMon_Handler
+
+
+ PUBWEAK PendSV_Handler
+ SECTION .text:CODE:REORDER(1)
+PendSV_Handler
+ B PendSV_Handler
+
+
+ PUBWEAK SysTick_Handler
+ SECTION .text:CODE:REORDER(1)
+SysTick_Handler
+ B SysTick_Handler
+
+
+ PUBWEAK WWDG_IRQHandler
+ SECTION .text:CODE:REORDER(1)
+WWDG_IRQHandler
+ B WWDG_IRQHandler
+
+
+ PUBWEAK PVD_IRQHandler
+ SECTION .text:CODE:REORDER(1)
+PVD_IRQHandler
+ B PVD_IRQHandler
+
+
+ PUBWEAK TAMPER_STAMP_IRQHandler
+ SECTION .text:CODE:REORDER(1)
+TAMPER_STAMP_IRQHandler
+ B TAMPER_STAMP_IRQHandler
+
+
+ PUBWEAK RTC_WKUP_IRQHandler
+ SECTION .text:CODE:REORDER(1)
+RTC_WKUP_IRQHandler
+ B RTC_WKUP_IRQHandler
+
+
+ PUBWEAK FLASH_IRQHandler
+ SECTION .text:CODE:REORDER(1)
+FLASH_IRQHandler
+ B FLASH_IRQHandler
+
+
+ PUBWEAK RCC_IRQHandler
+ SECTION .text:CODE:REORDER(1)
+RCC_IRQHandler
+ B RCC_IRQHandler
+
+
+ PUBWEAK EXTI0_IRQHandler
+ SECTION .text:CODE:REORDER(1)
+EXTI0_IRQHandler
+ B EXTI0_IRQHandler
+
+
+ PUBWEAK EXTI1_IRQHandler
+ SECTION .text:CODE:REORDER(1)
+EXTI1_IRQHandler
+ B EXTI1_IRQHandler
+
+
+ PUBWEAK EXTI2_IRQHandler
+ SECTION .text:CODE:REORDER(1)
+EXTI2_IRQHandler
+ B EXTI2_IRQHandler
+
+
+ PUBWEAK EXTI3_IRQHandler
+ SECTION .text:CODE:REORDER(1)
+EXTI3_IRQHandler
+ B EXTI3_IRQHandler
+
+
+ PUBWEAK EXTI4_IRQHandler
+ SECTION .text:CODE:REORDER(1)
+EXTI4_IRQHandler
+ B EXTI4_IRQHandler
+
+
+ PUBWEAK DMA1_Channel1_IRQHandler
+ SECTION .text:CODE:REORDER(1)
+DMA1_Channel1_IRQHandler
+ B DMA1_Channel1_IRQHandler
+
+
+ PUBWEAK DMA1_Channel2_IRQHandler
+ SECTION .text:CODE:REORDER(1)
+DMA1_Channel2_IRQHandler
+ B DMA1_Channel2_IRQHandler
+
+
+ PUBWEAK DMA1_Channel3_IRQHandler
+ SECTION .text:CODE:REORDER(1)
+DMA1_Channel3_IRQHandler
+ B DMA1_Channel3_IRQHandler
+
+
+ PUBWEAK DMA1_Channel4_IRQHandler
+ SECTION .text:CODE:REORDER(1)
+DMA1_Channel4_IRQHandler
+ B DMA1_Channel4_IRQHandler
+
+
+ PUBWEAK DMA1_Channel5_IRQHandler
+ SECTION .text:CODE:REORDER(1)
+DMA1_Channel5_IRQHandler
+ B DMA1_Channel5_IRQHandler
+
+
+ PUBWEAK DMA1_Channel6_IRQHandler
+ SECTION .text:CODE:REORDER(1)
+DMA1_Channel6_IRQHandler
+ B DMA1_Channel6_IRQHandler
+
+
+ PUBWEAK DMA1_Channel7_IRQHandler
+ SECTION .text:CODE:REORDER(1)
+DMA1_Channel7_IRQHandler
+ B DMA1_Channel7_IRQHandler
+
+
+ PUBWEAK ADC1_IRQHandler
+ SECTION .text:CODE:REORDER(1)
+ADC1_IRQHandler
+ B ADC1_IRQHandler
+
+
+ PUBWEAK USB_HP_IRQHandler
+ SECTION .text:CODE:REORDER(1)
+USB_HP_IRQHandler
+ B USB_HP_IRQHandler
+
+
+ PUBWEAK USB_LP_IRQHandler
+ SECTION .text:CODE:REORDER(1)
+USB_LP_IRQHandler
+ B USB_LP_IRQHandler
+
+
+ PUBWEAK DAC_IRQHandler
+ SECTION .text:CODE:REORDER(1)
+DAC_IRQHandler
+ B DAC_IRQHandler
+
+
+ PUBWEAK COMP_IRQHandler
+ SECTION .text:CODE:REORDER(1)
+COMP_IRQHandler
+ B COMP_IRQHandler
+
+
+ PUBWEAK EXTI9_5_IRQHandler
+ SECTION .text:CODE:REORDER(1)
+EXTI9_5_IRQHandler
+ B EXTI9_5_IRQHandler
+
+
+ PUBWEAK LCD_IRQHandler
+ SECTION .text:CODE:REORDER(1)
+LCD_IRQHandler
+ B LCD_IRQHandler
+
+
+ PUBWEAK TIM9_IRQHandler
+ SECTION .text:CODE:REORDER(1)
+TIM9_IRQHandler
+ B TIM9_IRQHandler
+
+
+ PUBWEAK TIM10_IRQHandler
+ SECTION .text:CODE:REORDER(1)
+TIM10_IRQHandler
+ B TIM10_IRQHandler
+
+
+ PUBWEAK TIM11_IRQHandler
+ SECTION .text:CODE:REORDER(1)
+TIM11_IRQHandler
+ B TIM11_IRQHandler
+
+
+ PUBWEAK TIM2_IRQHandler
+ SECTION .text:CODE:REORDER(1)
+TIM2_IRQHandler
+ B TIM2_IRQHandler
+
+
+ PUBWEAK TIM3_IRQHandler
+ SECTION .text:CODE:REORDER(1)
+TIM3_IRQHandler
+ B TIM3_IRQHandler
+
+
+ PUBWEAK TIM4_IRQHandler
+ SECTION .text:CODE:REORDER(1)
+TIM4_IRQHandler
+ B TIM4_IRQHandler
+
+
+ PUBWEAK I2C1_EV_IRQHandler
+ SECTION .text:CODE:REORDER(1)
+I2C1_EV_IRQHandler
+ B I2C1_EV_IRQHandler
+
+
+ PUBWEAK I2C1_ER_IRQHandler
+ SECTION .text:CODE:REORDER(1)
+I2C1_ER_IRQHandler
+ B I2C1_ER_IRQHandler
+
+
+ PUBWEAK I2C2_EV_IRQHandler
+ SECTION .text:CODE:REORDER(1)
+I2C2_EV_IRQHandler
+ B I2C2_EV_IRQHandler
+
+
+ PUBWEAK I2C2_ER_IRQHandler
+ SECTION .text:CODE:REORDER(1)
+I2C2_ER_IRQHandler
+ B I2C2_ER_IRQHandler
+
+
+ PUBWEAK SPI1_IRQHandler
+ SECTION .text:CODE:REORDER(1)
+SPI1_IRQHandler
+ B SPI1_IRQHandler
+
+
+ PUBWEAK SPI2_IRQHandler
+ SECTION .text:CODE:REORDER(1)
+SPI2_IRQHandler
+ B SPI2_IRQHandler
+
+
+ PUBWEAK USART1_IRQHandler
+ SECTION .text:CODE:REORDER(1)
+USART1_IRQHandler
+ B USART1_IRQHandler
+
+
+ PUBWEAK USART2_IRQHandler
+ SECTION .text:CODE:REORDER(1)
+USART2_IRQHandler
+ B USART2_IRQHandler
+
+
+ PUBWEAK USART3_IRQHandler
+ SECTION .text:CODE:REORDER(1)
+USART3_IRQHandler
+ B USART3_IRQHandler
+
+
+ PUBWEAK EXTI15_10_IRQHandler
+ SECTION .text:CODE:REORDER(1)
+EXTI15_10_IRQHandler
+ B EXTI15_10_IRQHandler
+
+
+ PUBWEAK RTC_Alarm_IRQHandler
+ SECTION .text:CODE:REORDER(1)
+RTC_Alarm_IRQHandler
+ B RTC_Alarm_IRQHandler
+
+
+ PUBWEAK USB_FS_WKUP_IRQHandler
+ SECTION .text:CODE:REORDER(1)
+USB_FS_WKUP_IRQHandler
+ B USB_FS_WKUP_IRQHandler
+
+
+ PUBWEAK TIM6_IRQHandler
+ SECTION .text:CODE:REORDER(1)
+TIM6_IRQHandler
+ B TIM6_IRQHandler
+
+
+ PUBWEAK TIM7_IRQHandler
+ SECTION .text:CODE:REORDER(1)
+TIM7_IRQHandler
+ B TIM7_IRQHandler
+
+ PUBWEAK TIM5_IRQHandler
+ SECTION .text:CODE:REORDER(1)
+TIM5_IRQHandler
+ B TIM5_IRQHandler
+
+ PUBWEAK SPI3_IRQHandler
+ SECTION .text:CODE:REORDER(1)
+SPI3_IRQHandler
+ B SPI3_IRQHandler
+
+ PUBWEAK DMA2_Channel1_IRQHandler
+ SECTION .text:CODE:REORDER(1)
+DMA2_Channel1_IRQHandler
+ B DMA2_Channel1_IRQHandler
+
+ PUBWEAK DMA2_Channel2_IRQHandler
+ SECTION .text:CODE:REORDER(1)
+DMA2_Channel2_IRQHandler
+ B DMA2_Channel2_IRQHandler
+
+ PUBWEAK DMA2_Channel3_IRQHandler
+ SECTION .text:CODE:REORDER(1)
+DMA2_Channel3_IRQHandler
+ B DMA2_Channel3_IRQHandler
+
+ PUBWEAK DMA2_Channel4_IRQHandler
+ SECTION .text:CODE:REORDER(1)
+DMA2_Channel4_IRQHandler
+ B DMA2_Channel4_IRQHandler
+
+ PUBWEAK DMA2_Channel5_IRQHandler
+ SECTION .text:CODE:REORDER(1)
+DMA2_Channel5_IRQHandler
+ B DMA2_Channel5_IRQHandler
+
+ PUBWEAK AES_IRQHandler
+ SECTION .text:CODE:REORDER(1)
+AES_IRQHandler
+ B AES_IRQHandler
+
+ PUBWEAK COMP_ACQ_IRQHandler
+ SECTION .text:CODE:REORDER(1)
+COMP_ACQ_IRQHandler
+ B COMP_ACQ_IRQHandler
+
+ END
+/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
diff --git a/Libraries/CMSIS/Device/ST/STM32L1xx/Source/Templates/system_stm32l1xx.c b/Libraries/CMSIS/Device/ST/STM32L1xx/Source/Templates/system_stm32l1xx.c
new file mode 100644
index 0000000..06528af
--- /dev/null
+++ b/Libraries/CMSIS/Device/ST/STM32L1xx/Source/Templates/system_stm32l1xx.c
@@ -0,0 +1,533 @@
+/**
+ ******************************************************************************
+ * @file system_stm32l1xx.c
+ * @author MCD Application Team
+ * @version V1.1.1
+ * @date 09-March-2012
+ * @brief CMSIS Cortex-M3 Device Peripheral Access Layer System Source File.
+ * This file contains the system clock configuration for STM32L1xx Ultra
+ * Low Power devices, and is generated by the clock configuration
+ * tool "STM32L1xx_Clock_Configuration_V1.1.0.xls".
+ *
+ * 1. This file provides two functions and one global variable to be called from
+ * user application:
+ * - SystemInit(): Setups the system clock (System clock source, PLL Multiplier
+ * and Divider factors, AHB/APBx prescalers and Flash settings),
+ * depending on the configuration made in the clock xls tool.
+ * This function is called at startup just after reset and
+ * before branch to main program. This call is made inside
+ * the "startup_stm32l1xx_xx.s" file.
+ *
+ * - SystemCoreClock variable: Contains the core clock (HCLK), it can be used
+ * by the user application to setup the SysTick
+ * timer or configure other parameters.
+ *
+ * - SystemCoreClockUpdate(): Updates the variable SystemCoreClock and must
+ * be called whenever the core clock is changed
+ * during program execution.
+ *
+ * 2. After each device reset the MSI (2.1 MHz Range) is used as system clock source.
+ * Then SystemInit() function is called, in "startup_stm32l1xx_xx.s" file, to
+ * configure the system clock before to branch to main program.
+ *
+ * 3. If the system clock source selected by user fails to startup, the SystemInit()
+ * function will do nothing and MSI still used as system clock source. User can
+ * add some code to deal with this issue inside the SetSysClock() function.
+ *
+ * 4. The default value of HSE crystal is set to 8MHz, refer to "HSE_VALUE" define
+ * in "stm32l1xx.h" file. When HSE is used as system clock source, directly or
+ * through PLL, and you are using different crystal you have to adapt the HSE
+ * value to your own configuration.
+ *
+ * 5. This file configures the system clock as follows:
+ *=============================================================================
+ * System Clock Configuration
+ *=============================================================================
+ * System Clock source | PLL(HSE)
+ *-----------------------------------------------------------------------------
+ * SYSCLK | 32000000 Hz
+ *-----------------------------------------------------------------------------
+ * HCLK | 32000000 Hz
+ *-----------------------------------------------------------------------------
+ * AHB Prescaler | 1
+ *-----------------------------------------------------------------------------
+ * APB1 Prescaler | 1
+ *-----------------------------------------------------------------------------
+ * APB2 Prescaler | 1
+ *-----------------------------------------------------------------------------
+ * HSE Frequency | 8000000 Hz
+ *-----------------------------------------------------------------------------
+ * PLL DIV | 3
+ *-----------------------------------------------------------------------------
+ * PLL MUL | 12
+ *-----------------------------------------------------------------------------
+ * VDD | 3.3 V
+ *-----------------------------------------------------------------------------
+ * Vcore | 1.8 V (Range 1)
+ *-----------------------------------------------------------------------------
+ * Flash Latency | 1 WS
+ *-----------------------------------------------------------------------------
+ * SDIO clock (SDIOCLK) | 48000000 Hz
+ *-----------------------------------------------------------------------------
+ * Require 48MHz for USB clock | Disabled
+ *-----------------------------------------------------------------------------
+ *=============================================================================
+ ******************************************************************************
+ * @attention
+ *
+ * © COPYRIGHT 2012 STMicroelectronics
+ *
+ * Licensed under MCD-ST Liberty SW License Agreement V2, (the "License");
+ * You may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at:
+ *
+ * http://www.st.com/software_license_agreement_liberty_v2
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ *
+ ******************************************************************************
+ */
+
+/** @addtogroup CMSIS
+ * @{
+ */
+
+/** @addtogroup stm32l1xx_system
+ * @{
+ */
+
+/** @addtogroup STM32L1xx_System_Private_Includes
+ * @{
+ */
+
+#include "stm32l1xx.h"
+
+/**
+ * @}
+ */
+
+/** @addtogroup STM32L1xx_System_Private_TypesDefinitions
+ * @{
+ */
+
+/**
+ * @}
+ */
+
+/** @addtogroup STM32L1xx_System_Private_Defines
+ * @{
+ */
+
+/*!< Uncomment the following line if you need to use external SRAM mounted
+ on STM32L152D_EVAL board as data memory */
+/* #define DATA_IN_ExtSRAM */
+
+/*!< Uncomment the following line if you need to relocate your vector Table in
+ Internal SRAM. */
+/* #define VECT_TAB_SRAM */
+#define VECT_TAB_OFFSET 0x0 /*!< Vector Table base offset field.
+ This value must be a multiple of 0x200. */
+/**
+ * @}
+ */
+
+/** @addtogroup STM32L1xx_System_Private_Macros
+ * @{
+ */
+
+/**
+ * @}
+ */
+
+/** @addtogroup STM32L1xx_System_Private_Variables
+ * @{
+ */
+uint32_t SystemCoreClock = 32000000;
+__I uint8_t PLLMulTable[9] = {3, 4, 6, 8, 12, 16, 24, 32, 48};
+__I uint8_t AHBPrescTable[16] = {0, 0, 0, 0, 0, 0, 0, 0, 1, 2, 3, 4, 6, 7, 8, 9};
+
+/**
+ * @}
+ */
+
+/** @addtogroup STM32L1xx_System_Private_FunctionPrototypes
+ * @{
+ */
+
+static void SetSysClock(void);
+#ifdef DATA_IN_ExtSRAM
+ static void SystemInit_ExtMemCtl(void);
+#endif /* DATA_IN_ExtSRAM */
+
+/**
+ * @}
+ */
+
+/** @addtogroup STM32L1xx_System_Private_Functions
+ * @{
+ */
+
+/**
+ * @brief Setup the microcontroller system.
+ * Initialize the Embedded Flash Interface, the PLL and update the
+ * SystemCoreClock variable.
+ * @param None
+ * @retval None
+ */
+void SystemInit (void)
+{
+ /*!< Set MSION bit */
+ RCC->CR |= (uint32_t)0x00000100;
+
+ /*!< Reset SW[1:0], HPRE[3:0], PPRE1[2:0], PPRE2[2:0], MCOSEL[2:0] and MCOPRE[2:0] bits */
+ RCC->CFGR &= (uint32_t)0x88FFC00C;
+
+ /*!< Reset HSION, HSEON, CSSON and PLLON bits */
+ RCC->CR &= (uint32_t)0xEEFEFFFE;
+
+ /*!< Reset HSEBYP bit */
+ RCC->CR &= (uint32_t)0xFFFBFFFF;
+
+ /*!< Reset PLLSRC, PLLMUL[3:0] and PLLDIV[1:0] bits */
+ RCC->CFGR &= (uint32_t)0xFF02FFFF;
+
+ /*!< Disable all interrupts */
+ RCC->CIR = 0x00000000;
+
+#ifdef DATA_IN_ExtSRAM
+ SystemInit_ExtMemCtl();
+#endif /* DATA_IN_ExtSRAM */
+
+ /* Configure the System clock frequency, AHB/APBx prescalers and Flash settings */
+ SetSysClock();
+
+#ifdef VECT_TAB_SRAM
+ SCB->VTOR = SRAM_BASE | VECT_TAB_OFFSET; /* Vector Table Relocation in Internal SRAM. */
+#else
+ SCB->VTOR = FLASH_BASE | VECT_TAB_OFFSET; /* Vector Table Relocation in Internal FLASH. */
+#endif
+}
+
+/**
+ * @brief Update SystemCoreClock according to Clock Register Values
+ * The SystemCoreClock variable contains the core clock (HCLK), it can
+ * be used by the user application to setup the SysTick timer or configure
+ * other parameters.
+ *
+ * @note Each time the core clock (HCLK) changes, this function must be called
+ * to update SystemCoreClock variable value. Otherwise, any configuration
+ * based on this variable will be incorrect.
+ *
+ * @note - The system frequency computed by this function is not the real
+ * frequency in the chip. It is calculated based on the predefined
+ * constant and the selected clock source:
+ *
+ * - If SYSCLK source is MSI, SystemCoreClock will contain the MSI
+ * value as defined by the MSI range.
+ *
+ * - If SYSCLK source is HSI, SystemCoreClock will contain the HSI_VALUE(*)
+ *
+ * - If SYSCLK source is HSE, SystemCoreClock will contain the HSE_VALUE(**)
+ *
+ * - If SYSCLK source is PLL, SystemCoreClock will contain the HSE_VALUE(**)
+ * or HSI_VALUE(*) multiplied/divided by the PLL factors.
+ *
+ * (*) HSI_VALUE is a constant defined in stm32l1xx.h file (default value
+ * 16 MHz) but the real value may vary depending on the variations
+ * in voltage and temperature.
+ *
+ * (**) HSE_VALUE is a constant defined in stm32l1xx.h file (default value
+ * 8 MHz), user has to ensure that HSE_VALUE is same as the real
+ * frequency of the crystal used. Otherwise, this function may
+ * have wrong result.
+ *
+ * - The result of this function could be not correct when using fractional
+ * value for HSE crystal.
+ * @param None
+ * @retval None
+ */
+void SystemCoreClockUpdate (void)
+{
+ uint32_t tmp = 0, pllmul = 0, plldiv = 0, pllsource = 0, msirange = 0;
+
+ /* Get SYSCLK source -------------------------------------------------------*/
+ tmp = RCC->CFGR & RCC_CFGR_SWS;
+
+ switch (tmp)
+ {
+ case 0x00: /* MSI used as system clock */
+ msirange = (RCC->ICSCR & RCC_ICSCR_MSIRANGE) >> 13;
+ SystemCoreClock = (32768 * (1 << (msirange + 1)));
+ break;
+ case 0x04: /* HSI used as system clock */
+ SystemCoreClock = HSI_VALUE;
+ break;
+ case 0x08: /* HSE used as system clock */
+ SystemCoreClock = HSE_VALUE;
+ break;
+ case 0x0C: /* PLL used as system clock */
+ /* Get PLL clock source and multiplication factor ----------------------*/
+ pllmul = RCC->CFGR & RCC_CFGR_PLLMUL;
+ plldiv = RCC->CFGR & RCC_CFGR_PLLDIV;
+ pllmul = PLLMulTable[(pllmul >> 18)];
+ plldiv = (plldiv >> 22) + 1;
+
+ pllsource = RCC->CFGR & RCC_CFGR_PLLSRC;
+
+ if (pllsource == 0x00)
+ {
+ /* HSI oscillator clock selected as PLL clock entry */
+ SystemCoreClock = (((HSI_VALUE) * pllmul) / plldiv);
+ }
+ else
+ {
+ /* HSE selected as PLL clock entry */
+ SystemCoreClock = (((HSE_VALUE) * pllmul) / plldiv);
+ }
+ break;
+ default: /* MSI used as system clock */
+ msirange = (RCC->ICSCR & RCC_ICSCR_MSIRANGE) >> 13;
+ SystemCoreClock = (32768 * (1 << (msirange + 1)));
+ break;
+ }
+ /* Compute HCLK clock frequency --------------------------------------------*/
+ /* Get HCLK prescaler */
+ tmp = AHBPrescTable[((RCC->CFGR & RCC_CFGR_HPRE) >> 4)];
+ /* HCLK clock frequency */
+ SystemCoreClock >>= tmp;
+}
+
+/**
+ * @brief Configures the System clock frequency, AHB/APBx prescalers and Flash
+ * settings.
+ * @note This function should be called only once the RCC clock configuration
+ * is reset to the default reset state (done in SystemInit() function).
+ * @param None
+ * @retval None
+ */
+static void SetSysClock(void)
+{
+ __IO uint32_t StartUpCounter = 0, HSEStatus = 0;
+
+ /* SYSCLK, HCLK, PCLK2 and PCLK1 configuration ---------------------------*/
+ /* Enable HSE */
+ RCC->CR |= ((uint32_t)RCC_CR_HSEON);
+
+ /* Wait till HSE is ready and if Time out is reached exit */
+ do
+ {
+ HSEStatus = RCC->CR & RCC_CR_HSERDY;
+ StartUpCounter++;
+ } while((HSEStatus == 0) && (StartUpCounter != HSE_STARTUP_TIMEOUT));
+
+ if ((RCC->CR & RCC_CR_HSERDY) != RESET)
+ {
+ HSEStatus = (uint32_t)0x01;
+ }
+ else
+ {
+ HSEStatus = (uint32_t)0x00;
+ }
+
+ if (HSEStatus == (uint32_t)0x01)
+ {
+ /* Enable 64-bit access */
+ FLASH->ACR |= FLASH_ACR_ACC64;
+
+ /* Enable Prefetch Buffer */
+ FLASH->ACR |= FLASH_ACR_PRFTEN;
+
+ /* Flash 1 wait state */
+ FLASH->ACR |= FLASH_ACR_LATENCY;
+
+ /* Power enable */
+ RCC->APB1ENR |= RCC_APB1ENR_PWREN;
+
+ /* Select the Voltage Range 1 (1.8 V) */
+ PWR->CR = PWR_CR_VOS_0;
+
+ /* Wait Until the Voltage Regulator is ready */
+ while((PWR->CSR & PWR_CSR_VOSF) != RESET)
+ {
+ }
+
+ /* HCLK = SYSCLK /1*/
+ RCC->CFGR |= (uint32_t)RCC_CFGR_HPRE_DIV1;
+
+ /* PCLK2 = HCLK /1*/
+ RCC->CFGR |= (uint32_t)RCC_CFGR_PPRE2_DIV1;
+
+ /* PCLK1 = HCLK /1*/
+ RCC->CFGR |= (uint32_t)RCC_CFGR_PPRE1_DIV1;
+
+ /* PLL configuration */
+ RCC->CFGR &= (uint32_t)((uint32_t)~(RCC_CFGR_PLLSRC | RCC_CFGR_PLLMUL |
+ RCC_CFGR_PLLDIV));
+ RCC->CFGR |= (uint32_t)(RCC_CFGR_PLLSRC_HSE | RCC_CFGR_PLLMUL12 | RCC_CFGR_PLLDIV3);
+
+ /* Enable PLL */
+ RCC->CR |= RCC_CR_PLLON;
+
+ /* Wait till PLL is ready */
+ while((RCC->CR & RCC_CR_PLLRDY) == 0)
+ {
+ }
+
+ /* Select PLL as system clock source */
+ RCC->CFGR &= (uint32_t)((uint32_t)~(RCC_CFGR_SW));
+ RCC->CFGR |= (uint32_t)RCC_CFGR_SW_PLL;
+
+ /* Wait till PLL is used as system clock source */
+ while ((RCC->CFGR & (uint32_t)RCC_CFGR_SWS) != (uint32_t)RCC_CFGR_SWS_PLL)
+ {
+ }
+ }
+ else
+ {
+ /* If HSE fails to start-up, the application will have wrong clock
+ configuration. User can add here some code to deal with this error */
+ }
+}
+
+#ifdef DATA_IN_ExtSRAM
+/**
+ * @brief Setup the external memory controller.
+ * Called in SystemInit() function before jump to main.
+ * This function configures the external SRAM mounted on STM32L152D_EVAL board
+ * This SRAM will be used as program data memory (including heap and stack).
+ * @param None
+ * @retval None
+ */
+void SystemInit_ExtMemCtl(void)
+{
+/*-- GPIOs Configuration -----------------------------------------------------*/
+/*
+ +-------------------+--------------------+------------------+------------------+
+ + SRAM pins assignment +
+ +-------------------+--------------------+------------------+------------------+
+ | PD0 <-> FSMC_D2 | PE0 <-> FSMC_NBL0 | PF0 <-> FSMC_A0 | PG0 <-> FSMC_A10 |
+ | PD1 <-> FSMC_D3 | PE1 <-> FSMC_NBL1 | PF1 <-> FSMC_A1 | PG1 <-> FSMC_A11 |
+ | PD4 <-> FSMC_NOE | PE7 <-> FSMC_D4 | PF2 <-> FSMC_A2 | PG2 <-> FSMC_A12 |
+ | PD5 <-> FSMC_NWE | PE8 <-> FSMC_D5 | PF3 <-> FSMC_A3 | PG3 <-> FSMC_A13 |
+ | PD8 <-> FSMC_D13 | PE9 <-> FSMC_D6 | PF4 <-> FSMC_A4 | PG4 <-> FSMC_A14 |
+ | PD9 <-> FSMC_D14 | PE10 <-> FSMC_D7 | PF5 <-> FSMC_A5 | PG5 <-> FSMC_A15 |
+ | PD10 <-> FSMC_D15 | PE11 <-> FSMC_D8 | PF12 <-> FSMC_A6 | PG10<-> FSMC_NE2 |
+ | PD11 <-> FSMC_A16 | PE12 <-> FSMC_D9 | PF13 <-> FSMC_A7 |------------------+
+ | PD12 <-> FSMC_A17 | PE13 <-> FSMC_D10 | PF14 <-> FSMC_A8 |
+ | PD13 <-> FSMC_A18 | PE14 <-> FSMC_D11 | PF15 <-> FSMC_A9 |
+ | PD14 <-> FSMC_D0 | PE15 <-> FSMC_D12 |------------------+
+ | PD15 <-> FSMC_D1 |--------------------+
+ +-------------------+
+*/
+
+ /* Enable GPIOD, GPIOE, GPIOF and GPIOG interface clock */
+ RCC->AHBENR = 0x000080D8;
+
+ /* Connect PDx pins to FSMC Alternate function */
+ GPIOD->AFR[0] = 0x00CC00CC;
+ GPIOD->AFR[1] = 0xCCCCCCCC;
+ /* Configure PDx pins in Alternate function mode */
+ GPIOD->MODER = 0xAAAA0A0A;
+ /* Configure PDx pins speed to 40 MHz */
+ GPIOD->OSPEEDR = 0xFFFF0F0F;
+ /* Configure PDx pins Output type to push-pull */
+ GPIOD->OTYPER = 0x00000000;
+ /* No pull-up, pull-down for PDx pins */
+ GPIOD->PUPDR = 0x00000000;
+
+ /* Connect PEx pins to FSMC Alternate function */
+ GPIOE->AFR[0] = 0xC00000CC;
+ GPIOE->AFR[1] = 0xCCCCCCCC;
+ /* Configure PEx pins in Alternate function mode */
+ GPIOE->MODER = 0xAAAA800A;
+ /* Configure PEx pins speed to 40 MHz */
+ GPIOE->OSPEEDR = 0xFFFFC00F;
+ /* Configure PEx pins Output type to push-pull */
+ GPIOE->OTYPER = 0x00000000;
+ /* No pull-up, pull-down for PEx pins */
+ GPIOE->PUPDR = 0x00000000;
+
+ /* Connect PFx pins to FSMC Alternate function */
+ GPIOF->AFR[0] = 0x00CCCCCC;
+ GPIOF->AFR[1] = 0xCCCC0000;
+ /* Configure PFx pins in Alternate function mode */
+ GPIOF->MODER = 0xAA000AAA;
+ /* Configure PFx pins speed to 40 MHz */
+ GPIOF->OSPEEDR = 0xFF000FFF;
+ /* Configure PFx pins Output type to push-pull */
+ GPIOF->OTYPER = 0x00000000;
+ /* No pull-up, pull-down for PFx pins */
+ GPIOF->PUPDR = 0x00000000;
+
+ /* Connect PGx pins to FSMC Alternate function */
+ GPIOG->AFR[0] = 0x00CCCCCC;
+ GPIOG->AFR[1] = 0x00000C00;
+ /* Configure PGx pins in Alternate function mode */
+ GPIOG->MODER = 0x00200AAA;
+ /* Configure PGx pins speed to 40 MHz */
+ GPIOG->OSPEEDR = 0x00300FFF;
+ /* Configure PGx pins Output type to push-pull */
+ GPIOG->OTYPER = 0x00000000;
+ /* No pull-up, pull-down for PGx pins */
+ GPIOG->PUPDR = 0x00000000;
+
+/*-- FSMC Configuration ------------------------------------------------------*/
+ /* Enable the FSMC interface clock */
+ RCC->AHBENR = 0x400080D8;
+
+ /* Configure and enable Bank1_SRAM3 */
+ FSMC_Bank1->BTCR[4] = 0x00001011;
+ FSMC_Bank1->BTCR[5] = 0x00000300;
+ FSMC_Bank1E->BWTR[4] = 0x0FFFFFFF;
+/*
+ Bank1_SRAM3 is configured as follow:
+
+ p.FSMC_AddressSetupTime = 0;
+ p.FSMC_AddressHoldTime = 0;
+ p.FSMC_DataSetupTime = 3;
+ p.FSMC_BusTurnAroundDuration = 0;
+ p.FSMC_CLKDivision = 0;
+ p.FSMC_DataLatency = 0;
+ p.FSMC_AccessMode = FSMC_AccessMode_A;
+
+ FSMC_NORSRAMInitStructure.FSMC_Bank = FSMC_Bank1_NORSRAM3;
+ FSMC_NORSRAMInitStructure.FSMC_DataAddressMux = FSMC_DataAddressMux_Disable;
+ FSMC_NORSRAMInitStructure.FSMC_MemoryType = FSMC_MemoryType_SRAM;
+ FSMC_NORSRAMInitStructure.FSMC_MemoryDataWidth = FSMC_MemoryDataWidth_16b;
+ FSMC_NORSRAMInitStructure.FSMC_BurstAccessMode = FSMC_BurstAccessMode_Disable;
+ FSMC_NORSRAMInitStructure.FSMC_AsynchronousWait = FSMC_AsynchronousWait_Disable;
+ FSMC_NORSRAMInitStructure.FSMC_WaitSignalPolarity = FSMC_WaitSignalPolarity_Low;
+ FSMC_NORSRAMInitStructure.FSMC_WrapMode = FSMC_WrapMode_Disable;
+ FSMC_NORSRAMInitStructure.FSMC_WaitSignalActive = FSMC_WaitSignalActive_BeforeWaitState;
+ FSMC_NORSRAMInitStructure.FSMC_WriteOperation = FSMC_WriteOperation_Enable;
+ FSMC_NORSRAMInitStructure.FSMC_WaitSignal = FSMC_WaitSignal_Disable;
+ FSMC_NORSRAMInitStructure.FSMC_ExtendedMode = FSMC_ExtendedMode_Disable;
+ FSMC_NORSRAMInitStructure.FSMC_WriteBurst = FSMC_WriteBurst_Disable;
+ FSMC_NORSRAMInitStructure.FSMC_ReadWriteTimingStruct = &p;
+ FSMC_NORSRAMInitStructure.FSMC_WriteTimingStruct = &p;
+
+ FSMC_NORSRAMInit(&FSMC_NORSRAMInitStructure);
+
+ FSMC_NORSRAMCmd(FSMC_Bank1_NORSRAM3, ENABLE);
+*/
+
+}
+#endif /* DATA_IN_ExtSRAM */
+
+/**
+ * @}
+ */
+
+/**
+ * @}
+ */
+
+/**
+ * @}
+ */
+
+/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
diff --git a/Libraries/CMSIS/Documentation/Core/html/CMSIS_CORE_Files.png b/Libraries/CMSIS/Documentation/Core/html/CMSIS_CORE_Files.png
new file mode 100644
index 0000000..a542159
Binary files /dev/null and b/Libraries/CMSIS/Documentation/Core/html/CMSIS_CORE_Files.png differ
diff --git a/Libraries/CMSIS/Documentation/Core/html/CMSIS_CORE_Files_user.png b/Libraries/CMSIS/Documentation/Core/html/CMSIS_CORE_Files_user.png
new file mode 100644
index 0000000..1cacaf2
Binary files /dev/null and b/Libraries/CMSIS/Documentation/Core/html/CMSIS_CORE_Files_user.png differ
diff --git a/Libraries/CMSIS/Documentation/Core/html/CMSIS_Logo_Final.png b/Libraries/CMSIS/Documentation/Core/html/CMSIS_Logo_Final.png
new file mode 100644
index 0000000..2056b7e
Binary files /dev/null and b/Libraries/CMSIS/Documentation/Core/html/CMSIS_Logo_Final.png differ
diff --git a/Libraries/CMSIS/Documentation/Core/html/_c_o_r_e__m_i_s_r_a__exceptions_pg.html b/Libraries/CMSIS/Documentation/Core/html/_c_o_r_e__m_i_s_r_a__exceptions_pg.html
new file mode 100644
index 0000000..be8279b
--- /dev/null
+++ b/Libraries/CMSIS/Documentation/Core/html/_c_o_r_e__m_i_s_r_a__exceptions_pg.html
@@ -0,0 +1,144 @@
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+  |
+
+
+ CMSIS-CORE
+ Version 3.01
+
+ CMSIS-CORE support for Cortex-M processor-based devices
+ |
+
+
+
+
+
+-
+
- Main Page +
- Usage and Description +
- Reference +
-
+ + ++
+
+
+ 
+
+
+
+
+
+
+
+
+
diff --git a/Libraries/CMSIS/Documentation/Core/html/_reg_map_pg.html b/Libraries/CMSIS/Documentation/Core/html/_reg_map_pg.html
new file mode 100644
index 0000000..bdf0347
--- /dev/null
+++ b/Libraries/CMSIS/Documentation/Core/html/_reg_map_pg.html
@@ -0,0 +1,305 @@
+
+
+
+
+
+
+
+
+MISRA-C:2004 Compliance Exceptions
+
+CMSIS-CORE uses the common coding rules for CMSIS components that are documented under Introduction .
+CMSIS-CORE violates the following MISRA-C:2004 rules:
+-
+
- Required Rule 8.5, object/function definition in header file.
+ Violated since function definitions in header files are used to allow 'inlining'.
+
-
+
- Required Rule 18.4, declaration of union type or object of union type: '{...}'.
+ Violated since unions are used for effective representation of core registers.
+
-
+
- Advisory Rule 19.7, Function-like macro defined.
+ Violated since function-like macros are used to allow more efficient code.
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+ |
+
+
+ CMSIS-CORE
+ Version 3.01
+
+ CMSIS-CORE support for Cortex-M processor-based devices
+ |
+
+
+
+
+
+-
+
- Main Page +
- Usage and Description +
- Reference +
-
+ + ++
+
+
+
+
+
+
+
+
+
+
+
+
diff --git a/Libraries/CMSIS/Documentation/Core/html/_templates_pg.html b/Libraries/CMSIS/Documentation/Core/html/_templates_pg.html
new file mode 100644
index 0000000..fbaf463
--- /dev/null
+++ b/Libraries/CMSIS/Documentation/Core/html/_templates_pg.html
@@ -0,0 +1,215 @@
+
+
+
+
+
+
+
+
+Register Mapping
+
+
+
+The table below associates some common register names used in CMSIS to the register names used in Technical Reference Manuals.
+| CMSIS Register Name | Cortex-M3 and Cortex-M4 | Cortex-M0 and Cortex-M0+ | Register Name |
|---|---|---|---|
| Nested Vectored Interrupt Controller (NVIC) Register Access | |||
| NVIC->ISER[] | NVIC_ISER0..7 | ISER | Interrupt Set-Enable Registers |
| NVIC->ICER[] | NVIC_ICER0..7 | ICER | Interrupt Clear-Enable Registers |
| NVIC->ISPR[] | NVIC_ISPR0..7 | ISPR | Interrupt Set-Pending Registers |
| NVIC->ICPR[] | NVIC_ICPR0..7 | ICPR | Interrupt Clear-Pending Registers |
| NVIC->IABR[] | NVIC_IABR0..7 | - | Interrupt Active Bit Register |
| NVIC->IP[] | NVIC_IPR0..59 | IPR0..7 | Interrupt Priority Register |
| NVIC->STIR | STIR | - | Software Triggered Interrupt Register |
| System Control Block (SCB) Register Access | |||
| SCB->CPUID | CPUID | CPUID | CPUID Base Register |
| SCB->ICSR | ICSR | ICSR | Interrupt Control and State Register |
| SCB->VTOR | VTOR | - | Vector Table Offset Register |
| SCB->AIRCR | AIRCR | AIRCR | Application Interrupt and Reset Control Register |
| SCB->SCR | SCR | SCR | System Control Register |
| SCB->CCR | CCR | CCR | Configuration and Control Register |
| SCB->SHP[] | SHPR1..3 | SHPR2..3 | System Handler Priority Registers |
| SCB->SHCSR | SHCSR | SHCSR | System Handler Control and State Register |
| SCB->CFSR | CFSR | - | Configurable Fault Status Registers |
| SCB->HFSR | HFSR | - | HardFault Status Register |
| SCB->DFSR | DFSR | - | Debug Fault Status Register |
| SCB->MMFAR | MMFAR | - | MemManage Fault Address Register |
| SCB->BFAR | BFAR | - | BusFault Address Register |
| SCB->AFSR | AFSR | - | Auxiliary Fault Status Register |
| SCB->PFR[] | ID_PFR0..1 | - | Processor Feature Registers |
| SCB->DFR | ID_DFR0 | - | Debug Feature Register |
| SCB->ADR | ID_AFR0 | - | Auxiliary Feature Register |
| SCB->MMFR[] | ID_MMFR0..3 | - | Memory Model Feature Registers |
| SCB->ISAR[] | ID_ISAR0..4 | - | Instruction Set Attributes Registers |
| SCB->CPACR | CPACR | - | Coprocessor Access Control Register |
| System Control and ID Registers not in the SCB (SCnSCB) Register Access | |||
| SCnSCB->ICTR | ICTR | - | Interrupt Controller Type Register |
| SCnSCB->ACTLR | ACTLR | - | Auxiliary Control Register |
| System Timer (SysTick) Control and Status Register Access | |||
| SysTick->CTRL | STCSR | SYST_CSR | SysTick Control and Status Register |
| SysTick->LOAD | STRVR | SYST_RVR | SysTick Reload Value Register |
| SysTick->VAL | STCVR | SYST_CVR | SysTick Current Value Register |
| SysTick->CALIB | STCR | SYST_CALIB | SysTick Calibaration Value Register |
| Data Watchpoint and Trace (DWT) Register Access | |||
| DWT->CTRL | DWT_CTRL | - | Control Register |
| DWT->CYCCNT | DWT_CYCCNT | - | Cycle Count Register |
| DWT->CPICNT | DWT_CPICNT | - | CPI Count Register |
| DWT->EXCCNT | DWT_EXCCNT | - | Exception Overhead Count Register |
| DWT->SLEEPCNT | DWT_SLEEPCNT | - | Sleep Count Register |
| DWT->LSUCNT | DWT_LSUCNT | - | LSU Count Register |
| DWT->FOLDCNT | DWT_FOLDCNT | - | Folded-instruction Count Register |
| DWT->PCSR | DWT_PCSR | - | Program Counter Sample Register |
| DWT->COMP0..3 | DWT_COMP0..3 | - | Comparator Register 0..3 |
| DWT->MASK0..3 | DWT_MASK0..3 | - | Mask Register 0..3 |
| DWT->FUNCTION0..3 | DWT_FUNCTION0..3 | - | Function Register 0..3 |
| Instrumentation Trace Macrocell (ITM) Register Access | |||
| ITM->PORT[] | ITM_STIM0..31 | - | Stimulus Port Registers |
| ITM->TER | ITM_TER | - | Trace Enable Register |
| ITM->TPR | ITM_TPR | - | ITM Trace Privilege Register |
| ITM->TCR | ITM_TCR | - | Trace Control Register |
| Trace Port Interface (TPIU) Register Access | |||
| TPI->SSPSR | TPIU_SSPR | - | Supported Parallel Port Size Register |
| TPI->CSPSR | TPIU_CSPSR | - | Current Parallel Port Size Register |
| TPI->ACPR | TPIU_ACPR | - | Asynchronous Clock Prescaler Register |
| TPI->SPPR | TPIU_SPPR | - | Selected Pin Protocol Register |
| TPI->FFSR | TPIU_FFSR | - | Formatter and Flush Status Register |
| TPI->FFCR | TPIU_FFCR | - | Formatter and Flush Control Register |
| TPI->FSCR | TPIU_FSCR | - | Formatter Synchronization Counter Register |
| TPI->TRIGGER | TRIGGER | - | TRIGGER |
| TPI->FIFO0 | FIFO data 0 | - | Integration ETM Data |
| TPI->ITATBCTR2 | ITATBCTR2 | - | ITATBCTR2 |
| TPI->ITATBCTR0 | ITATBCTR0 | - | ITATBCTR0 |
| TPI->FIFO1 | FIFO data 1 | - | Integration ITM Data |
| TPI->ITCTRL | TPIU_ITCTRL | - | Integration Mode Control |
| TPI->CLAIMSET | CLAIMSET | - | Claim tag set |
| TPI->CLAIMCLR | CLAIMCLR | - | Claim tag clear |
| TPI->DEVID | TPIU_DEVID | - | TPIU_DEVID |
| TPI->DEVTYPE | TPIU_DEVTYPE | - | TPIU_DEVTYPE |
| Memory Protection Unit (MPU) Register Access | |||
| MPU->TYPE | MPU_TYPE | - | MPU Type Register |
| MPU->CTRL | MPU_CTRL | - | MPU Control Register |
| MPU->RNR | MPU_RNR | - | MPU Region Number Register |
| MPU->RBAR | MPU_RBAR | - | MPU Region Base Address Register |
| MPU->RASR | MPU_RASR | - | MPU Region Attribute and Size Register |
| MPU->RBAR_A1..3 | MPU_RBAR_A1..3 | - | MPU alias Register |
| MPU->RSAR_A1..3 | MPU_RSAR_A1..3 | - | MPU alias Register |
| Floating Point Unit (FPU) Register Access [only Cortex-M4 with FPU] | |||
| FPU->FPCCR | FPCCR | - | FP Context Control Register |
| FPU->FPCAR | FPCAR | - | FP Context Address Register |
| FPU->FPDSCR | FPDSCR | - | FP Default Status Control Register |
| FPU->MVFR0..1 | MVFR0..1 | - | Media and VFP Feature Registers |
+
+
+
+
+
+
+
+
+
+
+
+
+
+ |
+
+
+ CMSIS-CORE
+ Version 3.01
+
+ CMSIS-CORE support for Cortex-M processor-based devices
+ |
+
+
+
+
+
+-
+
- Main Page +
- Usage and Description +
- Reference +
-
+ + ++
+
+
+
+
+
+
+
+
+
+
+
+
diff --git a/Libraries/CMSIS/Documentation/Core/html/_using__a_r_m_pg.html b/Libraries/CMSIS/Documentation/Core/html/_using__a_r_m_pg.html
new file mode 100644
index 0000000..a69504c
--- /dev/null
+++ b/Libraries/CMSIS/Documentation/Core/html/_using__a_r_m_pg.html
@@ -0,0 +1,167 @@
+
+
+
+
+
+
+
+
+Template Files
+
+
+
+
+
+
+
+ARM supplies CMSIS-CORE template files for the all supported Cortex-M processors and various compiler vendors. Refer to the list of Tested and Verified Toolchains for compliancy. These template files include the following:
+-
+
- Register names of the Core Peripherals and names of the Core Exception Vectors. +
- Functions to access core peripherals, special CPU instructions and SIMD instructions (for Cortex-M4) +
- Generic startup code and system configuration code. +
The detailed file structure of the CMSIS-CORE is shown in the following picture.
+
+
+
+
+
+CMSIS-CORE File Structure
+Template Files
+The CMSIS-CORE template files should be extended by the silicon vendor to reflect the actual device and device peripherals. Silicon vendors add in this context the:
+-
+
- Device Peripheral Access Layer that provides definitions for device-specific peripherals. +
- Access Functions for Peripherals (optional) that provides additional helper functions to access device-specific peripherals. +
- Interrupt vectors in the startup file that are device specific. +
| Template File | Description |
|---|---|
| ".\Device\_Template_Vendor\Vendor\Device\Source\ARM\startup_Device.s" | Startup file template for ARM C/C++ Compiler. |
| ".\Device\_Template_Vendor\Vendor\Device\Source\GCC\startup_Device.s" | Startup file template for GNU GCC ARM Embedded Compiler. |
| ".\Device\_Template_Vendor\Vendor\Device\Source\G++\startup_Device.s" | Startup file template for GNU Sourcery G++ Compiler. |
| ".\Device\_Template_Vendor\Vendor\Device\Source\IAR\startup_Device.s" | Startup file template for IAR C/C++ Compiler. |
| ".\Device\_Template_Vendor\Vendor\Device\Source\system_Device.c" | Generic system_Device.c file for system configuration (i.e. processor clock and memory bus system). |
| ".\Device\_Template_Vendor\Vendor\Device\Include\Device.h" | Generic device header file. Needs to be extended with the device-specific peripheral registers. Optionally functions that access the peripherals can be part of that file. |
| ".\Device\_Template_Vendor\Vendor\Device\Include\system_Device.h" | Generic system device configuration include file. |
In addition ARM provides the following core header files that do not need any modifications.
+| Core Header Files | Description |
|---|---|
| core_<cpu>.h | Defines the core peripherals and provides helper functions that access the core registers. This file is available for all supported processors:
|
| core_cmInstr.h | Defines intrinsic functions to access special Cortex-M instructions. |
| core_cmFunc.h | Defines functions to access the Cortex-M core peripherals. |
| core_cm4_simd.h | Defines intrinsic functions to access the Cortex-M4 SIMD instructions. |
+Adaption of Template Files to Devices
+Copy the complete folder including files and replace:
+-
+
- folder name 'Vendor' with the abbreviation for the device vendor e.g.: NXP. +
- folder name 'Device' with the specific device name e.g.: LPC17xx. +
- in the filenames 'Device' with the specific device name e.g.: LPC17xx. +
Each template file contains comments that start with ToDo: that describe a required modification. The template files contain placeholders:
+| Placeholder | Replaced with |
|---|---|
| <Device> | the specific device name or device family name; i.e. LPC17xx. |
| <DeviceInterrupt> | a specific interrupt name of the device; i.e. TIM1 for Timer 1. |
| <DeviceAbbreviation> | short name or abbreviation of the device family; i.e. LPC. |
| Cortex-M# | the specific Cortex-M processor name; i.e. Cortex-M3. |
The adaption of the template files is described in detail on the following pages:
+ +
+
+
+
+
+
+
+
+
+
+
+
+
+
+ |
+
+
+ CMSIS-CORE
+ Version 3.01
+
+ CMSIS-CORE support for Cortex-M processor-based devices
+ |
+
+
+
+
+
+-
+
- Main Page +
- Usage and Description +
- Reference +
-
+ + ++
+
+
+
+
+
+
+
+
+
+
+
+
diff --git a/Libraries/CMSIS/Documentation/Core/html/_using_pg.html b/Libraries/CMSIS/Documentation/Core/html/_using_pg.html
new file mode 100644
index 0000000..4e6a54b
--- /dev/null
+++ b/Libraries/CMSIS/Documentation/Core/html/_using_pg.html
@@ -0,0 +1,216 @@
+
+
+
+
+
+
+
+
+Using CMSIS with generic ARM Processors
+
+
+
+ARM provides CMSIS-CORE files for the supported ARM Processors and for various compiler vendors. These files can be used when standard ARM processors should be used in a project. The table below lists the folder and device names of the ARM processors.
+| Folder | Processor | Description |
|---|---|---|
| ".\Device\ARM\ARMCM0" | Cortex-M0 | Contains Include and Source template files configured for the Cortex-M0 processor. The device name is ARMCM0 and the name of the Device Header File <device.h> is <ARMCM0.h>. |
| ".\Device\ARM\ARMCM0plus" | Cortex-M0+ | Contains Include and Source template files configured for the Cortex-M0+ processor. The device name is ARMCM0plus and the name of the Device Header File <device.h> is <ARMCM0plus.h>. |
| ".\Device\ARM\ARMCM3" | Cortex-M3 | Contains Include and Source template files configured for the Cortex-M3 processor. The device name is ARMCM3 and the name of the Device Header File <device.h> is <ARMCM3.h>. |
| ".\Device\ARM\ARMCM4" | Cortex-M4 | Contains Include and Source template files configured for the Cortex-M4 processor. The device name is ARMCM4 and the name of the Device Header File <device.h> is <ARMCM4.h>. |
| ".\Device\ARM\ARMSC000" | SecurCore SC000 | Contains Include and Source template files configured for the SecurCore SC000 processor. The device name is ARMSC000 and the name of the Device Header File <device.h> is <ARMSC000.h>. |
| ".\Device\ARM\ARMSC300" | SecurCore SC300 | Contains Include and Source template files configured for the SecurCore SC300 processor. The device name is ARMSC300 and the name of the Device Header File <device.h> is <ARMSC300.h>. |
+Create generic Libraries with CMSIS
+The CMSIS Processor and Core Peripheral files allow also to create generic libraries. The CMSIS-DSP Libraries are an example for such a generic library.
+To build a generic Library set the define __CMSIS_GENERIC and include the relevant core_<cpu>.h CMSIS CPU & Core Access header file for the processor. The define __CMSIS_GENERIC disables device-dependent features such as the SysTick timer and the Interrupt System. Refer to Configuration of the Processor and Core Peripherals for a list of the available core_<cpu>.h header files.
+Example:
+The following code section shows the usage of the core_<cpu>.h header files to build a generic library for Cortex-M0, Cortex-M3, or Cortex-M4. To select the processor the source code uses the define CORTEX_M4, CORTEX_M3, or CORTEX_M0. By using this header file, the source code can access the functions for Core Register Access, Intrinsic Functions for CPU Instructions, Intrinsic Functions for SIMD Instructions [only Cortex-M4], and Debug Access.
+#define __CMSIS_GENERIC /* disable NVIC and Systick functions */ + +#if defined (CORTEX_M4) + #include "core_cm4.h" +#elif defined (CORTEX_M3) + #include "core_cm3.h" +#elif defined (CORTEX_M0) + #include "core_cm0.h" +#elif defined (CORTEX_M0PLUS) + #include "core_cm0plus.h" +#else + #error "Processor not specified or unsupported." +#endif +
+
+
+
+
+
+
+
+
+
+
+
+
+
+ |
+
+
+ CMSIS-CORE
+ Version 3.01
+
+ CMSIS-CORE support for Cortex-M processor-based devices
+ |
+
+
+
+
+
+-
+
- Main Page +
- Usage and Description +
- Reference +
-
+ + ++
+
+
+
+
+
+
+
+
+
+
+
+
diff --git a/Libraries/CMSIS/Documentation/Core/html/annotated.html b/Libraries/CMSIS/Documentation/Core/html/annotated.html
new file mode 100644
index 0000000..58ecef1
--- /dev/null
+++ b/Libraries/CMSIS/Documentation/Core/html/annotated.html
@@ -0,0 +1,152 @@
+
+
+
+
+
+
+
+
+Using CMSIS in Embedded Applications
+
+
+
+To use the CMSIS-CORE the following files are added to the embedded application:
+-
+
- Startup File startup_<device>.s with reset handler and exception vectors. +
- System Configuration Files system_<device>.c and system_<device>.h with general device configuration (i.e. for clock and BUS setup). +
- Device Header File <device.h> gives access to processor core and all peripherals. +
- Note:
- The files Startup File startup_<device>.s and System Configuration Files system_<device>.c and system_<device>.h may require application specific adaptations and therefore should be copied into the application project folder prior configuration. The Device Header File <device.h> is included in all source files that need device access and can be stored on a central include folder that is generic for all projects.
The Startup File startup_<device>.s is executed after reset and calls SystemInit. After the system initialization control is transferred to the C/C++ run-time library which performs initialization and calls the main function in the user code. In addition the Startup File startup_<device>.s contains all exception and interrupt vectors and implements a default function for every interrupt. It may also contain stack and heap configurations for the user application.
+The System Configuration Files system_<device>.c and system_<device>.h performs the setup for the processor clock. The variable SystemCoreClock indicates the CPU clock speed. System and Clock Configuration describes the minimum feature set. In addition the file may contain functions for the memory BUS setup and clock re-configuration.
+The Device Header File <device.h> is the central include file that the application programmer is using in the C source code. It provides the following features:
+-
+
- Peripheral Access provides a standardized register layout for all peripherals. Optionally functions for device-specific peripherals may be available. +
- Interrupts and Exceptions (NVIC) can be accessed with standardized symbols and functions for the Nested Interrupt Vector Controller (NVIC) are provided. +
- Intrinsic Functions for CPU Instructions allow to access special instructions, for example for activating sleep mode or the NOP instruction. +
- Intrinsic Functions for SIMD Instructions [only Cortex-M4] provide access to the DSP-oriented instructions. +
- Systick Timer (SYSTICK) function to configure and start a periodic timer interrupt. +
- Debug Access are functions that allow printf-style I/O via the CoreSight Debug Unit and ITM communication. +
+
+
+
+
+CMSIS-CORE User Files
The CMSIS-CORE are device specific. In addition, the Startup File startup_<device>.s is also compiler vendor specific. The various compiler vendor tool chains may provide folders that contain the CMSIS files for each supported device. Using CMSIS with generic ARM Processors explains how to use CMSIS-CORE for ARM processors.
+For example, the following files are provided in MDK-ARM to support the STM32F10x Connectivity Line device variants:
+| File | Description |
|---|---|
| ".\ARM\Startup\ST\STM32F10x\startup_stm32f10x_cl.s" | Startup File startup_<device>.s for the STM32F10x Connectivity Line device variants. |
| ".\ARM\Startup\ST\STM32F10x\system_stmf10x.c" | System Configuration Files system_<device>.c and system_<device>.h for the STM32F10x device families. |
| ".\ARM\INC\ST\STM32F10x\stm32f10x.h" | Device Header File <device.h> for the STM32F10x device families. |
| ".\ARM\INC\ST\STM32F10x\system_stm32f10x.h" | system_Device.h Template File for the STM32F10x device families. |
- Note:
- The silicon vendors create these device-specific CMSIS-CORE files based on Template Files provide by ARM.
Thereafter, the functions described under Reference can be used in the application.
+A typical example for using the CMSIS layer is provided below. The example is based on a STM32F10x Device.
+#include <stm32f10x.h> // File name depends on device used + +uint32_t volatile msTicks; // Counter for millisecond Interval + +void SysTick_Handler (void) { // SysTick Interrupt Handler + msTicks++; // Increment Counter +} + +void WaitForTick (void) { + uint32_t curTicks; + + curTicks = msTicks; // Save Current SysTick Value + while (msTicks == curTicks) { // Wait for next SysTick Interrupt + __WFE (); // Power-Down until next Event/Interrupt + } +} + +void TIM1_UP_IRQHandler (void) { // Timer Interrupt Handler + ; // Add user code here +} + +void timer1_init(int frequency) { // Set up Timer (device specific) + NVIC_SetPriority (TIM1_UP_IRQn, 1); // Set Timer priority + NVIC_EnableIRQ (TIM1_UP_IRQn); // Enable Timer Interrupt +} + + +void Device_Initialization (void) { // Configure & Initialize MCU + if (SysTick_Config (SystemCoreClock / 1000)) { // SysTick 1mSec + : // Handle Error + } + timer1_init (); // setup device-specific timer +} + + +// The processor clock is initialized by CMSIS startup + system file +void main (void) { // user application starts here + Device_Initialization (); // Configure & Initialize MCU + while (1) { // Endless Loop (the Super-Loop) + __disable_irq (); // Disable all interrupts + Get_InputValues (); // Read Values + __enable_irq (); // Enable all interrupts + Calculation_Response (); // Calculate Results + Output_Response (); // Output Results + WaitForTick (); // Synchronize to SysTick Timer + } +} +
+
+
+
+
+
+
+
+
+
+
+
+
+
+ |
+
+
+ CMSIS-CORE
+ Version 3.01
+
+ CMSIS-CORE support for Cortex-M processor-based devices
+ |
+
+
+
+
+
+
+-
+
- Main Page +
- Usage and Description +
- Reference +
-
+ + ++
+
+
+
+
+
+
+
+
+
+
+
+
diff --git a/Libraries/CMSIS/Documentation/Core/html/bc_s.png b/Libraries/CMSIS/Documentation/Core/html/bc_s.png
new file mode 100644
index 0000000..43f6f23
Binary files /dev/null and b/Libraries/CMSIS/Documentation/Core/html/bc_s.png differ
diff --git a/Libraries/CMSIS/Documentation/Core/html/check.png b/Libraries/CMSIS/Documentation/Core/html/check.png
new file mode 100644
index 0000000..094e59c
Binary files /dev/null and b/Libraries/CMSIS/Documentation/Core/html/check.png differ
diff --git a/Libraries/CMSIS/Documentation/Core/html/classes.html b/Libraries/CMSIS/Documentation/Core/html/classes.html
new file mode 100644
index 0000000..e60173d
--- /dev/null
+++ b/Libraries/CMSIS/Documentation/Core/html/classes.html
@@ -0,0 +1,160 @@
+
+
+
+
+
+
+
+
+Data Structures
+
+
+
+Here are the data structures with brief descriptions:
| APSR_Type | Union type to access the Application Program Status Register (APSR) |
| CONTROL_Type | Union type to access the Control Registers (CONTROL) |
| CoreDebug_Type | Structure type to access the Core Debug Register (CoreDebug) |
| DWT_Type | Structure type to access the Data Watchpoint and Trace Register (DWT) |
| FPU_Type | Structure type to access the Floating Point Unit (FPU) |
| IPSR_Type | Union type to access the Interrupt Program Status Register (IPSR) |
| ITM_Type | Structure type to access the Instrumentation Trace Macrocell Register (ITM) |
| MPU_Type | Structure type to access the Memory Protection Unit (MPU) |
| NVIC_Type | Structure type to access the Nested Vectored Interrupt Controller (NVIC) |
| SCB_Type | Structure type to access the System Control Block (SCB) |
| SCnSCB_Type | Structure type to access the System Control and ID Register not in the SCB |
| SysTick_Type | Structure type to access the System Timer (SysTick) |
| TPI_Type | Structure type to access the Trace Port Interface Register (TPI) |
| xPSR_Type | Union type to access the Special-Purpose Program Status Registers (xPSR) |
+
+
+
+
+
+
+
+
+
+
+
+
+
+ |
+
+
+ CMSIS-CORE
+ Version 3.01
+
+ CMSIS-CORE support for Cortex-M processor-based devices
+ |
+
+
+
+
+
+
+-
+
- Main Page +
- Usage and Description +
- Reference +
-
+ + ++
+
+
+
+
+
+
+
+
+
+
+
+
diff --git a/Libraries/CMSIS/Documentation/Core/html/closed.png b/Libraries/CMSIS/Documentation/Core/html/closed.png
new file mode 100644
index 0000000..09380f7
Binary files /dev/null and b/Libraries/CMSIS/Documentation/Core/html/closed.png differ
diff --git a/Libraries/CMSIS/Documentation/Core/html/cmsis.css b/Libraries/CMSIS/Documentation/Core/html/cmsis.css
new file mode 100644
index 0000000..a5c4b8d
--- /dev/null
+++ b/Libraries/CMSIS/Documentation/Core/html/cmsis.css
@@ -0,0 +1,957 @@
+/* The standard CSS for doxygen */
+
+body, table, div, p, dl {
+ font-family: Lucida Grande, Verdana, Geneva, Arial, sans-serif;
+ font-size: 12px;
+}
+
+/* CMSIS styles */
+
+.style1 {
+ text-align: center;
+}
+.style2 {
+ color: #0000FF;
+ font-weight: normal;
+}
+.style3 {
+ text-align: left;
+}
+.style4 {
+ color: #008000;
+}
+.style5 {
+ color: #0000FF;
+}
+.style6 {
+ color: #000000;
+ font-style:italic;
+}
+.mand {
+ color: #0000FF;
+}
+.opt {
+ color: #008000;
+}
+.cond {
+ color: #990000;
+}
+
+.choice
+{
+ background-color:#F7F9D0;
+}
+.seq
+{
+ background-color:#C9DECB;
+}
+.group1
+{
+ background-color:#F8F1F1;
+}
+.group2
+{
+ background-color:#DCEDEA;
+}
+
+
+ul ul {
+ list-style-type: disc;
+}
+
+ul ul ul {
+ list-style-type: disc;
+}
+
+ul.hierarchy {
+ color: green;
+}
+
+em {
+ color: #000000;
+ font-style:italic;
+}
+
+
+
+/* CMSIS Tables */
+table.cmtab1 {
+ padding: 4px;
+ border-collapse: collapse;
+ border: 1px solid #A3B4D7;
+ text-align: justify;
+ width:70%;
+}
+
+th.cmtab1 {
+ background: #EBEFF6;
+ font-weight: bold;
+ height: 28px;
+}
+
+td.cmtab1 {
+ padding:1px;
+ text-align: left;
+}
+
+table.cmtable {
+ border-collapse:collapse;
+ text-align: justify;
+}
+
+table.cmtable td, table.cmtable th {
+ border: 1px solid #2D4068;
+ padding: 3px 7px 2px;
+}
+
+table.cmtable th {
+ background-color: #EBEFF6;
+ border: 1px solid #2D4068;
+ font-size: 110%;
+ padding-bottom: 4px;
+ padding-top: 5px;
+ text-align:left;
+ height: 28px;
+}
+
+td.MonoTxt {
+ font-family:"Arial monospaced for SAP";
+}
+
+span.XML-Token
+{
+ azimuth: 180;
+ font-style:italic;
+ color:Maroon;
+ z-index:20;
+
+}
+
+/* @group Heading Levels */
+
+h1 {
+ font-size: 150%;
+}
+
+.title {
+ font-size: 150%;
+ font-weight: bold;
+ margin: 10px 2px;
+}
+
+h2 {
+ font-size: 120%;
+}
+
+h3 {
+ font-size: 100%;
+}
+
+dt {
+ font-weight: bold;
+}
+
+div.multicol {
+ -moz-column-gap: 1em;
+ -webkit-column-gap: 1em;
+ -moz-column-count: 3;
+ -webkit-column-count: 3;
+}
+
+p.startli, p.startdd, p.starttd {
+ margin-top: 2px;
+}
+
+p.endli {
+ margin-bottom: 0px;
+}
+
+p.enddd {
+ margin-bottom: 4px;
+}
+
+p.endtd {
+ margin-bottom: 2px;
+}
+
+/* @end */
+
+caption {
+ font-weight: bold;
+}
+
+span.legend {
+ font-size: 70%;
+ text-align: center;
+}
+
+h3.version {
+ font-size: 90%;
+ text-align: center;
+}
+
+div.qindex, div.navtab{
+ background-color: #EBEFF6;
+ border: 1px solid #A3B4D7;
+ text-align: center;
+ margin: 2px;
+ padding: 2px;
+}
+
+div.qindex, div.navpath {
+ width: 100%;
+ line-height: 140%;
+}
+
+div.navtab {
+ margin-right: 15px;
+}
+
+/* @group Link Styling */
+
+a {
+ color: #3D578C;
+ font-weight: normal;
+ text-decoration: none;
+}
+
+.contents a:visited {
+ color: #4665A2;
+}
+
+a:hover {
+ text-decoration: underline;
+}
+
+a.qindex {
+ font-weight: bold;
+}
+
+a.qindexHL {
+ font-weight: bold;
+ background-color: #9CAFD4;
+ color: #ffffff;
+ border: 1px double #869DCA;
+}
+
+.contents a.qindexHL:visited {
+ color: #ffffff;
+}
+
+a.el {
+ font-weight: bold;
+}
+
+a.elRef {
+}
+
+a.code {
+ color: #4665A2;
+}
+
+a.codeRef {
+ color: #4665A2;
+}
+
+/* @end */
+
+dl.el {
+ margin-left: -1cm;
+}
+
+.fragment {
+ font-family: monospace, fixed;
+ font-size: 105%;
+}
+
+pre.fragment {
+ border: 1px solid #C4CFE5;
+ background-color: #FBFCFD;
+ padding: 4px 6px;
+ margin: 4px 8px 4px 2px;
+ overflow: auto;
+ word-wrap: break-word;
+ font-size: 9pt;
+ line-height: 125%;
+}
+
+div.ah {
+ background-color: black;
+ font-weight: bold;
+ color: #ffffff;
+ margin-bottom: 3px;
+ margin-top: 3px;
+ padding: 0.2em;
+ border: solid thin #333;
+ border-radius: 0.5em;
+ -webkit-border-radius: .5em;
+ -moz-border-radius: .5em;
+ box-shadow: 2px 2px 3px #999;
+ -webkit-box-shadow: 2px 2px 3px #999;
+ -moz-box-shadow: rgba(0, 0, 0, 0.15) 2px 2px 2px;
+ background-image: -webkit-gradient(linear, left top, left bottom, from(#eee), to(#000),color-stop(0.3, #444));
+ background-image: -moz-linear-gradient(center top, #eee 0%, #444 40%, #000);
+}
+
+div.groupHeader {
+ margin-left: 16px;
+ margin-top: 12px;
+ font-weight: bold;
+}
+
+div.groupText {
+ margin-left: 16px;
+ font-style: italic;
+}
+
+body {
+ background: white;
+ color: black;
+ margin: 0;
+}
+
+div.contents {
+ margin-top: 10px;
+ margin-left: 10px;
+ margin-right: 5px;
+}
+
+td.indexkey {
+ background-color: #EBEFF6;
+ font-weight: bold;
+ border: 1px solid #C4CFE5;
+ margin: 2px 0px 2px 0;
+ padding: 2px 10px;
+}
+
+td.indexvalue {
+ background-color: #EBEFF6;
+ border: 1px solid #C4CFE5;
+ padding: 2px 10px;
+ margin: 2px 0px;
+}
+
+tr.memlist {
+ background-color: #EEF1F7;
+}
+
+p.formulaDsp {
+ text-align: center;
+}
+
+img.formulaDsp {
+
+}
+
+img.formulaInl {
+ vertical-align: middle;
+}
+
+div.center {
+ text-align: center;
+ margin-top: 0px;
+ margin-bottom: 0px;
+ padding: 0px;
+}
+
+div.center img {
+ border: 0px;
+}
+
+address.footer {
+ text-align: right;
+ padding-right: 12px;
+}
+
+img.footer {
+ border: 0px;
+ vertical-align: middle;
+}
+
+/* @group Code Colorization */
+
+span.keyword {
+ color: #008000
+}
+
+span.keywordtype {
+ color: #604020
+}
+
+span.keywordflow {
+ color: #e08000
+}
+
+span.comment {
+ color: #800000
+}
+
+span.preprocessor {
+ color: #806020
+}
+
+span.stringliteral {
+ color: #002080
+}
+
+span.charliteral {
+ color: #008080
+}
+
+span.vhdldigit {
+ color: #ff00ff
+}
+
+span.vhdlchar {
+ color: #000000
+}
+
+span.vhdlkeyword {
+ color: #700070
+}
+
+span.vhdllogic {
+ color: #ff0000
+}
+
+/* @end */
+
+/*
+.search {
+ color: #003399;
+ font-weight: bold;
+}
+
+form.search {
+ margin-bottom: 0px;
+ margin-top: 0px;
+}
+
+input.search {
+ font-size: 75%;
+ color: #000080;
+ font-weight: normal;
+ background-color: #e8eef2;
+}
+*/
+
+td.tiny {
+ font-size: 75%;
+}
+
+.dirtab {
+ padding: 4px;
+ border-collapse: collapse;
+ border: 1px solid #A3B4D7;
+}
+
+th.dirtab {
+ background: #EBEFF6;
+ font-weight: bold;
+}
+
+hr {
+ height: 0px;
+ border: none;
+ border-top: 1px solid #4A6AAA;
+}
+
+hr.footer {
+ height: 1px;
+}
+
+/* @group Member Descriptions */
+
+table.memberdecls {
+ border-spacing: 0px;
+ padding: 0px;
+}
+
+.mdescLeft, .mdescRight,
+.memItemLeft, .memItemRight,
+.memTemplItemLeft, .memTemplItemRight, .memTemplParams {
+ background-color: #F9FAFC;
+ border: none;
+ margin: 4px;
+ padding: 1px 0 0 8px;
+}
+
+.mdescLeft, .mdescRight {
+ padding: 0px 8px 4px 8px;
+ color: #555;
+}
+
+.memItemLeft, .memItemRight, .memTemplParams {
+ border-top: 1px solid #C4CFE5;
+}
+
+.memItemLeft, .memTemplItemLeft {
+ white-space: nowrap;
+}
+
+.memItemRight {
+ width: 100%;
+}
+
+.memTemplParams {
+ color: #4665A2;
+ white-space: nowrap;
+}
+
+/* @end */
+
+/* @group Member Details */
+
+/* Styles for detailed member documentation */
+
+.memtemplate {
+ font-size: 80%;
+ color: #4665A2;
+ font-weight: normal;
+ margin-left: 9px;
+}
+
+.memnav {
+ background-color: #EBEFF6;
+ border: 1px solid #A3B4D7;
+ text-align: center;
+ margin: 2px;
+ margin-right: 15px;
+ padding: 2px;
+}
+
+.mempage {
+ width: 100%;
+}
+
+.memitem {
+ padding: 0;
+ margin-bottom: 10px;
+ margin-right: 5px;
+}
+
+.memname {
+ white-space: nowrap;
+ font-weight: bold;
+ margin-left: 6px;
+}
+
+.memproto {
+ border-top: 1px solid #A8B8D9;
+ border-left: 1px solid #A8B8D9;
+ border-right: 1px solid #A8B8D9;
+ padding: 6px 0px 6px 0px;
+ color: #253555;
+ font-weight: bold;
+ text-shadow: 0px 1px 1px rgba(255, 255, 255, 0.9);
+ /* opera specific markup */
+ box-shadow: 5px 5px 5px rgba(0, 0, 0, 0.15);
+ border-top-right-radius: 8px;
+ border-top-left-radius: 8px;
+ /* firefox specific markup */
+ -moz-box-shadow: rgba(0, 0, 0, 0.15) 5px 5px 5px;
+ -moz-border-radius-topright: 8px;
+ -moz-border-radius-topleft: 8px;
+ /* webkit specific markup */
+ -webkit-box-shadow: 5px 5px 5px rgba(0, 0, 0, 0.15);
+ -webkit-border-top-right-radius: 8px;
+ -webkit-border-top-left-radius: 8px;
+ background-image:url('nav_f.png');
+ background-repeat:repeat-x;
+ background-color: #E2E8F2;
+
+}
+
+.memdoc {
+ border-bottom: 1px solid #A8B8D9;
+ border-left: 1px solid #A8B8D9;
+ border-right: 1px solid #A8B8D9;
+ padding: 2px 5px;
+ background-color: #FBFCFD;
+ border-top-width: 0;
+ /* opera specific markup */
+ border-bottom-left-radius: 8px;
+ border-bottom-right-radius: 8px;
+ box-shadow: 5px 5px 5px rgba(0, 0, 0, 0.15);
+ /* firefox specific markup */
+ -moz-border-radius-bottomleft: 8px;
+ -moz-border-radius-bottomright: 8px;
+ -moz-box-shadow: rgba(0, 0, 0, 0.15) 5px 5px 5px;
+ background-image: -moz-linear-gradient(center top, #FFFFFF 0%, #FFFFFF 60%, #F7F8FB 95%, #EEF1F7);
+ /* webkit specific markup */
+ -webkit-border-bottom-left-radius: 8px;
+ -webkit-border-bottom-right-radius: 8px;
+ -webkit-box-shadow: 5px 5px 5px rgba(0, 0, 0, 0.15);
+ background-image: -webkit-gradient(linear,center top,center bottom,from(#FFFFFF), color-stop(0.6,#FFFFFF), color-stop(0.60,#FFFFFF), color-stop(0.95,#F7F8FB), to(#EEF1F7));
+}
+
+.paramkey {
+ text-align: right;
+}
+
+.paramtype {
+ white-space: nowrap;
+}
+
+.paramname {
+ color: #602020;
+ white-space: nowrap;
+}
+.paramname em {
+ font-style: normal;
+}
+
+.params, .retval, .exception, .tparams {
+ border-spacing: 6px 2px;
+}
+
+.params .paramname, .retval .paramname {
+ font-weight: bold;
+ vertical-align: top;
+}
+
+.params .paramtype {
+ font-style: italic;
+ vertical-align: top;
+}
+
+.params .paramdir {
+ font-family: "courier new",courier,monospace;
+ vertical-align: top;
+}
+
+
+
+
+/* @end */
+
+/* @group Directory (tree) */
+
+/* for the tree view */
+
+.ftvtree {
+ font-family: sans-serif;
+ margin: 0px;
+}
+
+/* these are for tree view when used as main index */
+
+.directory {
+ font-size: 9pt;
+ font-weight: bold;
+ margin: 5px;
+}
+
+.directory h3 {
+ margin: 0px;
+ margin-top: 1em;
+ font-size: 11pt;
+}
+
+/*
+The following two styles can be used to replace the root node title
+with an image of your choice. Simply uncomment the next two styles,
+specify the name of your image and be sure to set 'height' to the
+proper pixel height of your image.
+*/
+
+/*
+.directory h3.swap {
+ height: 61px;
+ background-repeat: no-repeat;
+ background-image: url("yourimage.gif");
+}
+.directory h3.swap span {
+ display: none;
+}
+*/
+
+.directory > h3 {
+ margin-top: 0;
+}
+
+.directory p {
+ margin: 0px;
+ white-space: nowrap;
+}
+
+.directory div {
+ display: none;
+ margin: 0px;
+}
+
+.directory img {
+ vertical-align: -30%;
+}
+
+/* these are for tree view when not used as main index */
+
+.directory-alt {
+ font-size: 100%;
+ font-weight: bold;
+}
+
+.directory-alt h3 {
+ margin: 0px;
+ margin-top: 1em;
+ font-size: 11pt;
+}
+
+.directory-alt > h3 {
+ margin-top: 0;
+}
+
+.directory-alt p {
+ margin: 0px;
+ white-space: nowrap;
+}
+
+.directory-alt div {
+ display: none;
+ margin: 0px;
+}
+
+.directory-alt img {
+ vertical-align: -30%;
+}
+
+/* @end */
+
+div.dynheader {
+ margin-top: 8px;
+}
+
+address {
+ font-style: normal;
+ color: #2A3D61;
+}
+
+table.doxtable {
+ border-collapse:collapse;
+}
+
+table.doxtable td, table.doxtable th {
+ border: 1px solid #2D4068;
+ padding: 3px 7px 2px;
+}
+
+table.doxtable th {
+ background-color: #374F7F;
+ color: #FFFFFF;
+ font-size: 110%;
+ padding-bottom: 4px;
+ padding-top: 5px;
+ text-align:left;
+}
+
+.tabsearch {
+ top: 0px;
+ left: 10px;
+ height: 36px;
+ background-image: url('tab_b.png');
+ z-index: 101;
+ overflow: hidden;
+ font-size: 13px;
+}
+
+.navpath ul
+{
+ font-size: 11px;
+ background-image:url('tab_b.png');
+ background-repeat:repeat-x;
+ height:30px;
+ line-height:30px;
+ color:#8AA0CC;
+ border:solid 1px #C2CDE4;
+ overflow:hidden;
+ margin:0px;
+ padding:0px;
+}
+
+.navpath li
+{
+ list-style-type:none;
+ float:left;
+ padding-left:10px;
+ padding-right:15px;
+ background-image:url('bc_s.png');
+ background-repeat:no-repeat;
+ background-position:right;
+ color:#364D7C;
+}
+
+.navpath li.navelem a
+{
+ height:32px;
+ display:block;
+ text-decoration: none;
+ outline: none;
+}
+
+.navpath li.navelem a:hover
+{
+ color:#6884BD;
+}
+
+.navpath li.footer
+{
+ list-style-type:none;
+ float:right;
+ padding-left:10px;
+ padding-right:15px;
+ background-image:none;
+ background-repeat:no-repeat;
+ background-position:right;
+ color:#364D7C;
+ font-size: 8pt;
+}
+
+
+div.summary
+{
+ float: right;
+ font-size: 8pt;
+ padding-right: 5px;
+ width: 50%;
+ text-align: right;
+}
+
+div.summary a
+{
+ white-space: nowrap;
+}
+
+div.ingroups
+{
+ font-size: 8pt;
+ padding-left: 5px;
+ width: 50%;
+ text-align: left;
+}
+
+div.ingroups a
+{
+ white-space: nowrap;
+}
+
+div.header
+{
+ background-image:url('nav_h.png');
+ background-repeat:repeat-x;
+ background-color: #F9FAFC;
+ margin: 0px;
+ border-bottom: 1px solid #C4CFE5;
+}
+
+div.headertitle
+{
+ padding: 5px 5px 5px 10px;
+}
+
+dl
+{
+ padding: 0 0 0 10px;
+}
+
+dl.note, dl.warning, dl.attention, dl.pre, dl.post, dl.invariant, dl.deprecated, dl.todo, dl.test, dl.bug
+{
+ border-left:4px solid;
+ padding: 0 0 0 6px;
+}
+
+dl.note
+{
+ border-color: #D0C000;
+}
+
+dl.warning, dl.attention
+{
+ border-color: #FF0000;
+}
+
+dl.pre, dl.post, dl.invariant
+{
+ border-color: #00D000;
+}
+
+dl.deprecated
+{
+ border-color: #505050;
+}
+
+dl.todo
+{
+ border-color: #00C0E0;
+}
+
+dl.test
+{
+ border-color: #3030E0;
+}
+
+dl.bug
+{
+ border-color: #C08050;
+}
+
+#projectlogo
+{
+ text-align: center;
+ vertical-align: bottom;
+ border-collapse: separate;
+}
+
+#projectlogo img
+{
+ border: 0px none;
+}
+
+#projectname
+{
+ font: 200% Tahoma, Arial,sans-serif;
+ margin: 0px;
+ padding: 2px 0px;
+}
+
+#projectbrief
+{
+ font: 120% Tahoma, Arial,sans-serif;
+ margin: 0px;
+ padding: 0px;
+}
+
+#projectnumber
+{
+ font: 50% Tahoma, Arial,sans-serif;
+ margin: 0px;
+ padding: 0px;
+}
+
+#titlearea
+{
+ padding: 0px;
+ margin: 0px;
+ width: 100%;
+ border-bottom: 1px solid #5373B4;
+}
+
+.image
+{
+ text-align: center;
+}
+
+.dotgraph
+{
+ text-align: center;
+}
+
+.mscgraph
+{
+ text-align: center;
+}
+
+.caption
+{
+ font-weight: bold;
+}
+
diff --git a/Libraries/CMSIS/Documentation/Core/html/device_h_pg.html b/Libraries/CMSIS/Documentation/Core/html/device_h_pg.html
new file mode 100644
index 0000000..463bf6b
--- /dev/null
+++ b/Libraries/CMSIS/Documentation/Core/html/device_h_pg.html
@@ -0,0 +1,516 @@
+
+
+
+
+
+
+
+
+
+Data Structure Index
+
+
+
+
+
+
+
+
+
+
+
+
+
+ |
+
+
+ CMSIS-CORE
+ Version 3.01
+
+ CMSIS-CORE support for Cortex-M processor-based devices
+ |
+
+
+
+
+
+-
+
- Main Page +
- Usage and Description +
- Reference +
-
+ + ++
+
+
+
+
+
+
+
+
+
+
+
+
diff --git a/Libraries/CMSIS/Documentation/Core/html/doxygen.png b/Libraries/CMSIS/Documentation/Core/html/doxygen.png
new file mode 100644
index 0000000..b9ed6a7
Binary files /dev/null and b/Libraries/CMSIS/Documentation/Core/html/doxygen.png differ
diff --git a/Libraries/CMSIS/Documentation/Core/html/ftv2blank.png b/Libraries/CMSIS/Documentation/Core/html/ftv2blank.png
new file mode 100644
index 0000000..3b7a29c
Binary files /dev/null and b/Libraries/CMSIS/Documentation/Core/html/ftv2blank.png differ
diff --git a/Libraries/CMSIS/Documentation/Core/html/ftv2doc.png b/Libraries/CMSIS/Documentation/Core/html/ftv2doc.png
new file mode 100644
index 0000000..e4a4a81
Binary files /dev/null and b/Libraries/CMSIS/Documentation/Core/html/ftv2doc.png differ
diff --git a/Libraries/CMSIS/Documentation/Core/html/ftv2folderclosed.png b/Libraries/CMSIS/Documentation/Core/html/ftv2folderclosed.png
new file mode 100644
index 0000000..ad69f0d
Binary files /dev/null and b/Libraries/CMSIS/Documentation/Core/html/ftv2folderclosed.png differ
diff --git a/Libraries/CMSIS/Documentation/Core/html/ftv2folderopen.png b/Libraries/CMSIS/Documentation/Core/html/ftv2folderopen.png
new file mode 100644
index 0000000..a12e307
Binary files /dev/null and b/Libraries/CMSIS/Documentation/Core/html/ftv2folderopen.png differ
diff --git a/Libraries/CMSIS/Documentation/Core/html/ftv2lastnode.png b/Libraries/CMSIS/Documentation/Core/html/ftv2lastnode.png
new file mode 100644
index 0000000..3b7a29c
Binary files /dev/null and b/Libraries/CMSIS/Documentation/Core/html/ftv2lastnode.png differ
diff --git a/Libraries/CMSIS/Documentation/Core/html/ftv2link.png b/Libraries/CMSIS/Documentation/Core/html/ftv2link.png
new file mode 100644
index 0000000..e4a4a81
Binary files /dev/null and b/Libraries/CMSIS/Documentation/Core/html/ftv2link.png differ
diff --git a/Libraries/CMSIS/Documentation/Core/html/ftv2mlastnode.png b/Libraries/CMSIS/Documentation/Core/html/ftv2mlastnode.png
new file mode 100644
index 0000000..37dba19
Binary files /dev/null and b/Libraries/CMSIS/Documentation/Core/html/ftv2mlastnode.png differ
diff --git a/Libraries/CMSIS/Documentation/Core/html/ftv2mnode.png b/Libraries/CMSIS/Documentation/Core/html/ftv2mnode.png
new file mode 100644
index 0000000..37dba19
Binary files /dev/null and b/Libraries/CMSIS/Documentation/Core/html/ftv2mnode.png differ
diff --git a/Libraries/CMSIS/Documentation/Core/html/ftv2node.png b/Libraries/CMSIS/Documentation/Core/html/ftv2node.png
new file mode 100644
index 0000000..3b7a29c
Binary files /dev/null and b/Libraries/CMSIS/Documentation/Core/html/ftv2node.png differ
diff --git a/Libraries/CMSIS/Documentation/Core/html/ftv2plastnode.png b/Libraries/CMSIS/Documentation/Core/html/ftv2plastnode.png
new file mode 100644
index 0000000..0f94c47
Binary files /dev/null and b/Libraries/CMSIS/Documentation/Core/html/ftv2plastnode.png differ
diff --git a/Libraries/CMSIS/Documentation/Core/html/ftv2pnode.png b/Libraries/CMSIS/Documentation/Core/html/ftv2pnode.png
new file mode 100644
index 0000000..0f94c47
Binary files /dev/null and b/Libraries/CMSIS/Documentation/Core/html/ftv2pnode.png differ
diff --git a/Libraries/CMSIS/Documentation/Core/html/ftv2splitbar.png b/Libraries/CMSIS/Documentation/Core/html/ftv2splitbar.png
new file mode 100644
index 0000000..5a6a3ac
Binary files /dev/null and b/Libraries/CMSIS/Documentation/Core/html/ftv2splitbar.png differ
diff --git a/Libraries/CMSIS/Documentation/Core/html/ftv2vertline.png b/Libraries/CMSIS/Documentation/Core/html/ftv2vertline.png
new file mode 100644
index 0000000..3b7a29c
Binary files /dev/null and b/Libraries/CMSIS/Documentation/Core/html/ftv2vertline.png differ
diff --git a/Libraries/CMSIS/Documentation/Core/html/functions.html b/Libraries/CMSIS/Documentation/Core/html/functions.html
new file mode 100644
index 0000000..00189ad
--- /dev/null
+++ b/Libraries/CMSIS/Documentation/Core/html/functions.html
@@ -0,0 +1,629 @@
+
+
+
+
+
+
+
+
+Device Header File <device.h>
+
+
+
+
+
+
+
+
+
+
+
+
+
+The Device Header File <device.h> contains the following sections that are device specific:
+-
+
- Interrupt Number Definition provides interrupt numbers (IRQn) for all exceptions and interrupts of the device. +
- Configuration of the Processor and Core Peripherals reflect the features of the device. +
- Device Peripheral Access Layer provides definitions for the Peripheral Access to all device peripherals. It contains all data structures and the address mapping for device-specific peripherals. +
- Access Functions for Peripherals (optional) provide additional helper functions for peripherals that are useful for programming of these peripherals. Access Functions may be provided as inline functions or can be extern references to a device-specific library provided by the silicon vendor. +
Reference describes the standard features and functions of the Device Header File <device.h> in detail.
++Interrupt Number Definition
+Device Header File <device.h> contains the enumeration IRQn_Type that defines all exceptions and interrupts of the device.
+-
+
- Negative IRQn values represent processor core exceptions (internal interrupts). +
- Positive IRQn values represent device-specific exceptions (external interrupts). The first device-specific interrupt has the IRQn value 0. The IRQn values needs extension to reflect the device-specific interrupt vector table in the Startup File startup_<device>.s. +
Example:
+The following example shows the extension of the interrupt vector table for the LPC1100 device family.
+typedef enum IRQn +{ +/****** Cortex-M0 Processor Exceptions Numbers ***************************************************/ + NonMaskableInt_IRQn = -14, + HardFault_IRQn = -13, + SVCall_IRQn = -5, + PendSV_IRQn = -2, + SysTick_IRQn = -1, +/****** LPC11xx/LPC11Cxx Specific Interrupt Numbers **********************************************/ + WAKEUP0_IRQn = 0, + WAKEUP1_IRQn = 1, + WAKEUP2_IRQn = 2, + : : + : : + EINT1_IRQn = 30, + EINT0_IRQn = 31, +} IRQn_Type; +
+Configuration of the Processor and Core Peripherals
+The Device Header File <device.h> configures the Cortex-M or SecurCore processor and the core peripherals with #defines that are set prior to including the file core_<cpu>.h.
+The following tables list the #defines along with the possible values for each processor core. If these #defines are missing default values are used.
+core_cm0.h
+| #define | Value Range | Default | Description |
|---|---|---|---|
| __CM0_REV | 0x0000 | 0x0000 | Core revision number ([15:8] revision number, [7:0] patch number) |
| __NVIC_PRIO_BITS | 2 | 2 | Number of priority bits implemented in the NVIC (device specific) |
| __Vendor_SysTickConfig | 0 .. 1 | 0 | If this define is set to 1, then the default SysTick_Config function is excluded. In this case, the file device.h must contain a vendor specific implementation of this function. |
core_cm0plus.h
+| #define | Value Range | Default | Description |
|---|---|---|---|
| __CM0PLUS_REV | 0x0000 | 0x0000 | Core revision number ([15:8] revision number, [7:0] patch number) |
| __NVIC_PRIO_BITS | 2 | 2 | Number of priority bits implemented in the NVIC (device specific) |
| __Vendor_SysTickConfig | 0 .. 1 | 0 | If this define is set to 1, then the default SysTick_Config function is excluded. In this case, the file device.h must contain a vendor specific implementation of this function. |
core_cm3.h
+| #define | Value Range | Default | Description |
|---|---|---|---|
| __CM3_REV | 0x0101 | 0x0200 | 0x0200 | Core revision number ([15:8] revision number, [7:0] patch number) |
| __NVIC_PRIO_BITS | 2 .. 8 | 4 | Number of priority bits implemented in the NVIC (device specific) |
| __MPU_PRESENT | 0 .. 1 | 0 | Defines if a MPU is present or not |
| __Vendor_SysTickConfig | 0 .. 1 | 0 | If this define is set to 1, then the default SysTick_Config function is excluded. In this case, the file device.h must contain a vendor specific implementation of this function. |
core_cm4.h
+| #define | Value Range | Default | Description |
|---|---|---|---|
| __CM4_REV | 0x0000 | 0x0000 | Core revision number ([15:8] revision number, [7:0] patch number) |
| __NVIC_PRIO_BITS | 2 .. 8 | 4 | Number of priority bits implemented in the NVIC (device specific) |
| __MPU_PRESENT | 0 .. 1 | 0 | Defines if a MPU is present or not |
| __FPU_PRESENT | 0 .. 1 | 0 | Defines if a FPU is present or not |
| __Vendor_SysTickConfig | 0 .. 1 | 0 | If this define is set to 1, then the default SysTick_Config function is excluded. In this case, the file device.h must contain a vendor specific implementation of this function. |
core_sc000.h
+| #define | Value Range | Default | Description |
|---|---|---|---|
| __SC000_REV | 0x0000 | 0x0000 | Core revision number ([15:8] revision number, [7:0] patch number) |
| __NVIC_PRIO_BITS | 2 | 2 | Number of priority bits implemented in the NVIC (device specific) |
| __MPU_PRESENT | 0 .. 1 | 0 | Defines if a MPU is present or not |
| __Vendor_SysTickConfig | 0 .. 1 | 0 | If this define is set to 1, then the default SysTick_Config function is excluded. In this case, the file device.h must contain a vendor specific implementation of this function. |
core_sc300.h
+| #define | Value Range | Default | Description |
|---|---|---|---|
| __SC300_REV | 0x0000 | 0x0000 | Core revision number ([15:8] revision number, [7:0] patch number) |
| __NVIC_PRIO_BITS | 2 .. 8 | 4 | Number of priority bits implemented in the NVIC (device specific) |
| __MPU_PRESENT | 0 .. 1 | 0 | Defines if a MPU is present or not |
| __Vendor_SysTickConfig | 0 .. 1 | 0 | If this define is set to 1, then the default SysTick_Config function is excluded. In this case, the file device.h must contain a vendor specific implementation of this function. |
Example
+The following code exemplifies the configuration of the Cortex-M4 Processor and Core Peripherals.
+#define __CM4_REV 0x0001 /* Core revision r0p1 */ +#define __MPU_PRESENT 1 /* MPU present or not */ +#define __NVIC_PRIO_BITS 3 /* Number of Bits used for Priority Levels */ +#define __Vendor_SysTickConfig 0 /* Set to 1 if different SysTick Config is used */ +#define __FPU_PRESENT 1 /* FPU present or not */ +. +. +#include <core_cm4.h> /* Cortex-M4 processor and core peripherals */ +
+CMSIS Version and Processor Information
+Defines in the core_cpu.h file identify the version of the CMSIS-CORE and the processor used. The following shows the defines in the various core_cpu.h files that may be used in the Device Header File <device.h> to verify a minimum version or ensure that the right processor core is used.
+core_cm0.h
+#define __CM0_CMSIS_VERSION_MAIN (0x03) /* [31:16] CMSIS HAL main version */ +#define __CM0_CMSIS_VERSION_SUB (0x00) /* [15:0] CMSIS HAL sub version */ +#define __CM0_CMSIS_VERSION ((__CM0_CMSIS_VERSION_MAIN << 16) | \ + __CM0_CMSIS_VERSION_SUB ) /* CMSIS HAL version number */ +... +#define __CORTEX_M (0x00) /* Cortex-M Core */ +
core_cm0plus.h
+#define __CM0PLUS_CMSIS_VERSION_MAIN (0x03) /* [31:16] CMSIS HAL main version */ +#define __CM0PLUS_CMSIS_VERSION_SUB (0x00) /* [15:0] CMSIS HAL sub version */ +#define __CM0PLUS_CMSIS_VERSION ((__CM0P_CMSIS_VERSION_MAIN << 16) | \ + __CM0P_CMSIS_VERSION_SUB ) /* CMSIS HAL version number */ +... +#define __CORTEX_M (0x00) /* Cortex-M Core */ +
core_cm3.h
+#define __CM3_CMSIS_VERSION_MAIN (0x03) /* [31:16] CMSIS HAL main version */ +#define __CM3_CMSIS_VERSION_SUB (0x00) /* [15:0] CMSIS HAL sub version */ +#define __CM3_CMSIS_VERSION ((__CM3_CMSIS_VERSION_MAIN << 16) | \ + __CM3_CMSIS_VERSION_SUB ) /* CMSIS HAL version number */ +... +#define __CORTEX_M (0x03) /* Cortex-M Core */ +
core_cm4.h
+#define __CM4_CMSIS_VERSION_MAIN (0x03) /* [31:16] CMSIS HAL main version */ +#define __CM4_CMSIS_VERSION_SUB (0x00) /* [15:0] CMSIS HAL sub version */ +#define __CM4_CMSIS_VERSION ((__CM4_CMSIS_VERSION_MAIN << 16) | \ + __CM4_CMSIS_VERSION_SUB ) /* CMSIS HAL version number */ +... +#define __CORTEX_M (0x04) /* Cortex-M Core */ +
core_sc000.h
+#define __SC000_CMSIS_VERSION_MAIN (0x03) /* [31:16] CMSIS HAL main version */ +#define __SC000_CMSIS_VERSION_SUB (0x00) /* [15:0] CMSIS HAL sub version */ +#define __SC000_CMSIS_VERSION ((__SC000_CMSIS_VERSION_MAIN << 16) | \ + __SC000_CMSIS_VERSION_SUB ) /* CMSIS HAL version number */ +... +#define __CORTEX_SC (0) /* Cortex secure core */ +
core_sc300.h
+#define __SC300_CMSIS_VERSION_MAIN (0x03) /* [31:16] CMSIS HAL main version */ +#define __SC300_CMSIS_VERSION_SUB (0x00) /* [15:0] CMSIS HAL sub version */ +#define __SC300_CMSIS_VERSION ((__SC300_CMSIS_VERSION_MAIN << 16) | \ + __SC300_CMSIS_VERSION_SUB ) /* CMSIS HAL version number */ +... +#define __CORTEX_SC (300) /* Cortex secure core */ +
+Device Peripheral Access Layer
+The Device Header File <device.h> contains for each peripheral:
+-
+
- Register Layout Typedef +
- Base Address +
- Access Definitions +
The section Peripheral Access shows examples for peripheral definitions.
++Device.h Template File
+The silicon vendor needs to extend the Device.h template file with the CMSIS features described above. In addition the Device Header File <device.h> may contain functions to access device-specific peripherals. The system_Device.h Template File which is provided as part of the CMSIS specification is shown below.
+/**************************************************************************//**
+ * @file <Device>.h
+ * @brief CMSIS Cortex-M# Core Peripheral Access Layer Header File for
+ * Device <Device>
+ * @version V3.01
+ * @date 06. March 2012
+ *
+ * @note
+ * Copyright (C) 2010-2012 ARM Limited. All rights reserved.
+ *
+ * @par
+ * ARM Limited (ARM) is supplying this software for use with Cortex-M
+ * processor based microcontrollers. This file can be freely distributed
+ * within development tools that are supporting such ARM based processors.
+ *
+ * @par
+ * THIS SOFTWARE IS PROVIDED "AS IS". NO WARRANTIES, WHETHER EXPRESS, IMPLIED
+ * OR STATUTORY, INCLUDING, BUT NOT LIMITED TO, IMPLIED WARRANTIES OF
+ * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE APPLY TO THIS SOFTWARE.
+ * ARM SHALL NOT, IN ANY CIRCUMSTANCES, BE LIABLE FOR SPECIAL, INCIDENTAL, OR
+ * CONSEQUENTIAL DAMAGES, FOR ANY REASON WHATSOEVER.
+ *
+ ******************************************************************************/
+
+
+#ifndef <Device>_H /* ToDo: replace '<Device>' with your device name */
+#define <Device>_H
+
+#ifdef __cplusplus
+ extern "C" {
+#endif
+
+/* ToDo: replace '<Device>' with your device name; add your doxyGen comment */
+/** @addtogroup <Device>_Definitions <Device> Definitions
+ This file defines all structures and symbols for <Device>:
+ - registers and bitfields
+ - peripheral base address
+ - peripheral ID
+ - Peripheral definitions
+ @{
+*/
+
+
+/******************************************************************************/
+/* Processor and Core Peripherals */
+/******************************************************************************/
+/** @addtogroup <Device>_CMSIS Device CMSIS Definitions
+ Configuration of the Cortex-M# Processor and Core Peripherals
+ @{
+*/
+
+/*
+ * ==========================================================================
+ * ---------- Interrupt Number Definition -----------------------------------
+ * ==========================================================================
+ */
+
+typedef enum IRQn
+{
+/****** Cortex-M# Processor Exceptions Numbers ***************************************************/
+
+/* ToDo: use this Cortex interrupt numbers if your device is a CORTEX-M0 device */
+ NonMaskableInt_IRQn = -14, /*!< 2 Non Maskable Interrupt */
+ HardFault_IRQn = -13, /*!< 3 Hard Fault Interrupt */
+ SVCall_IRQn = -5, /*!< 11 SV Call Interrupt */
+ PendSV_IRQn = -2, /*!< 14 Pend SV Interrupt */
+ SysTick_IRQn = -1, /*!< 15 System Tick Interrupt */
+
+/* ToDo: use this Cortex interrupt numbers if your device is a CORTEX-M3 / Cortex-M4 device */
+ NonMaskableInt_IRQn = -14, /*!< 2 Non Maskable Interrupt */
+ MemoryManagement_IRQn = -12, /*!< 4 Memory Management Interrupt */
+ BusFault_IRQn = -11, /*!< 5 Bus Fault Interrupt */
+ UsageFault_IRQn = -10, /*!< 6 Usage Fault Interrupt */
+ SVCall_IRQn = -5, /*!< 11 SV Call Interrupt */
+ DebugMonitor_IRQn = -4, /*!< 12 Debug Monitor Interrupt */
+ PendSV_IRQn = -2, /*!< 14 Pend SV Interrupt */
+ SysTick_IRQn = -1, /*!< 15 System Tick Interrupt */
+
+/****** Device Specific Interrupt Numbers ********************************************************/
+/* ToDo: add here your device specific external interrupt numbers
+ according the interrupt handlers defined in startup_Device.s
+ eg.: Interrupt for Timer#1 TIM1_IRQHandler -> TIM1_IRQn */
+ <DeviceInterrupt>_IRQn = 0, /*!< Device Interrupt */
+} IRQn_Type;
+
+
+/*
+ * ==========================================================================
+ * ----------- Processor and Core Peripheral Section ------------------------
+ * ==========================================================================
+ */
+
+/* Configuration of the Cortex-M# Processor and Core Peripherals */
+/* ToDo: set the defines according your Device */
+/* ToDo: define the correct core revision
+ __CM0_REV if your device is a CORTEX-M0 device
+ __CM3_REV if your device is a CORTEX-M3 device
+ __CM4_REV if your device is a CORTEX-M4 device */
+#define __CM#_REV 0x0201 /*!< Core Revision r2p1 */
+#define __NVIC_PRIO_BITS 2 /*!< Number of Bits used for Priority Levels */
+#define __Vendor_SysTickConfig 0 /*!< Set to 1 if different SysTick Config is used */
+#define __MPU_PRESENT 0 /*!< MPU present or not */
+/* ToDo: define __FPU_PRESENT if your devise is a CORTEX-M4 */
+#define __FPU_PRESENT 0 /*!< FPU present or not */
+
+/*@}*/ /* end of group <Device>_CMSIS */
+
+
+/* ToDo: include the correct core_cm#.h file
+ core_cm0.h if your device is a CORTEX-M0 device
+ core_cm3.h if your device is a CORTEX-M3 device
+ core_cm4.h if your device is a CORTEX-M4 device */
+#include <core_cm#.h> /* Cortex-M# processor and core peripherals */
+/* ToDo: include your system_<Device>.h file
+ replace '<Device>' with your device name */
+#include "system_<Device>.h" /* <Device> System include file */
+
+
+/******************************************************************************/
+/* Device Specific Peripheral registers structures */
+/******************************************************************************/
+/** @addtogroup <Device>_Peripherals <Device> Peripherals
+ <Device> Device Specific Peripheral registers structures
+ @{
+*/
+
+#if defined ( __CC_ARM )
+#pragma anon_unions
+#endif
+
+/* ToDo: add here your device specific peripheral access structure typedefs
+ following is an example for a timer */
+
+/*------------- 16-bit Timer/Event Counter (TMR) -----------------------------*/
+/** @addtogroup <Device>_TMR <Device> 16-bit Timer/Event Counter (TMR)
+ @{
+*/
+typedef struct
+{
+ __IO uint32_t EN; /*!< Offset: 0x0000 Timer Enable Register */
+ __IO uint32_t RUN; /*!< Offset: 0x0004 Timer RUN Register */
+ __IO uint32_t CR; /*!< Offset: 0x0008 Timer Control Register */
+ __IO uint32_t MOD; /*!< Offset: 0x000C Timer Mode Register */
+ uint32_t RESERVED0[1];
+ __IO uint32_t ST; /*!< Offset: 0x0014 Timer Status Register */
+ __IO uint32_t IM; /*!< Offset: 0x0018 Interrupt Mask Register */
+ __IO uint32_t UC; /*!< Offset: 0x001C Timer Up Counter Register */
+ __IO uint32_t RG0 /*!< Offset: 0x0020 Timer Register */
+ uint32_t RESERVED1[2];
+ __IO uint32_t CP; /*!< Offset: 0x002C Capture register */
+} <DeviceAbbreviation>_TMR_TypeDef;
+/*@}*/ /* end of group <Device>_TMR */
+
+
+#if defined ( __CC_ARM )
+#pragma no_anon_unions
+#endif
+
+/*@}*/ /* end of group <Device>_Peripherals */
+
+
+/******************************************************************************/
+/* Peripheral memory map */
+/******************************************************************************/
+/* ToDo: add here your device peripherals base addresses
+ following is an example for timer */
+/** @addtogroup <Device>_MemoryMap <Device> Memory Mapping
+ @{
+*/
+
+/* Peripheral and SRAM base address */
+#define <DeviceAbbreviation>_FLASH_BASE (0x00000000UL) /*!< (FLASH ) Base Address */
+#define <DeviceAbbreviation>_SRAM_BASE (0x20000000UL) /*!< (SRAM ) Base Address */
+#define <DeviceAbbreviation>_PERIPH_BASE (0x40000000UL) /*!< (Peripheral) Base Address */
+
+/* Peripheral memory map */
+#define <DeviceAbbreviation>TIM0_BASE (<DeviceAbbreviation>_PERIPH_BASE) /*!< (Timer0 ) Base Address */
+#define <DeviceAbbreviation>TIM1_BASE (<DeviceAbbreviation>_PERIPH_BASE + 0x0800) /*!< (Timer1 ) Base Address */
+#define <DeviceAbbreviation>TIM2_BASE (<DeviceAbbreviation>_PERIPH_BASE + 0x1000) /*!< (Timer2 ) Base Address */
+/*@}*/ /* end of group <Device>_MemoryMap */
+
+
+/******************************************************************************/
+/* Peripheral declaration */
+/******************************************************************************/
+/* ToDo: add here your device peripherals pointer definitions
+ following is an example for timer */
+
+/** @addtogroup <Device>_PeripheralDecl <Device> Peripheral Declaration
+ @{
+*/
+
+#define <DeviceAbbreviation>_TIM0 ((<DeviceAbbreviation>_TMR_TypeDef *) <DeviceAbbreviation>TIM0_BASE)
+#define <DeviceAbbreviation>_TIM1 ((<DeviceAbbreviation>_TMR_TypeDef *) <DeviceAbbreviation>TIM0_BASE)
+#define <DeviceAbbreviation>_TIM2 ((<DeviceAbbreviation>_TMR_TypeDef *) <DeviceAbbreviation>TIM0_BASE)
+/*@}*/ /* end of group <Device>_PeripheralDecl */
+
+/*@}*/ /* end of group <Device>_Definitions */
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* <Device>_H */
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+ |
+
+
+ CMSIS-CORE
+ Version 3.01
+
+ CMSIS-CORE support for Cortex-M processor-based devices
+ |
+
+
+
+
+
+
+
+
+-
+
- Main Page +
- Usage and Description +
- Reference +
-
+ + ++
+
+
+
+
+
+
+
+
+
+
+
+
diff --git a/Libraries/CMSIS/Documentation/Core/html/functions_vars.html b/Libraries/CMSIS/Documentation/Core/html/functions_vars.html
new file mode 100644
index 0000000..91623ed
--- /dev/null
+++ b/Libraries/CMSIS/Documentation/Core/html/functions_vars.html
@@ -0,0 +1,629 @@
+
+
+
+
+
+
+Here is a list of all struct and union fields with links to the structures/unions they belong to:
+
+- _ -
-
+
- _reserved0 +: APSR_Type +, CONTROL_Type +, xPSR_Type +, IPSR_Type + +
- a -
-
+
- ACPR +: TPI_Type + +
- ACTLR +: SCnSCB_Type + +
- ADR +: SCB_Type + +
- AFSR +: SCB_Type + +
- AIRCR +: SCB_Type + +
- b -
-
+
- b +: APSR_Type +, IPSR_Type +, CONTROL_Type +, xPSR_Type + +
- BFAR +: SCB_Type + +
- c -
-
+
- C +: APSR_Type +, xPSR_Type + +
- CALIB +: SysTick_Type + +
- CCR +: SCB_Type + +
- CFSR +: SCB_Type + +
- CLAIMCLR +: TPI_Type + +
- CLAIMSET +: TPI_Type + +
- COMP0 +: DWT_Type + +
- COMP1 +: DWT_Type + +
- COMP2 +: DWT_Type + +
- COMP3 +: DWT_Type + +
- CPACR +: SCB_Type + +
- CPICNT +: DWT_Type + +
- CPUID +: SCB_Type + +
- CSPSR +: TPI_Type + +
- CTRL +: DWT_Type +, MPU_Type +, SysTick_Type + +
- CYCCNT +: DWT_Type + +
- d -
-
+
- DCRDR +: CoreDebug_Type + +
- DCRSR +: CoreDebug_Type + +
- DEMCR +: CoreDebug_Type + +
- DEVID +: TPI_Type + +
- DEVTYPE +: TPI_Type + +
- DFR +: SCB_Type + +
- DFSR +: SCB_Type + +
- DHCSR +: CoreDebug_Type + +
- e -
-
+
- EXCCNT +: DWT_Type + +
- f -
-
+
- FFCR +: TPI_Type + +
- FFSR +: TPI_Type + +
- FIFO0 +: TPI_Type + +
- FIFO1 +: TPI_Type + +
- FOLDCNT +: DWT_Type + +
- FPCA +: CONTROL_Type + +
- FPCAR +: FPU_Type + +
- FPCCR +: FPU_Type + +
- FPDSCR +: FPU_Type + +
- FSCR +: TPI_Type + +
- FUNCTION0 +: DWT_Type + +
- FUNCTION1 +: DWT_Type + +
- FUNCTION2 +: DWT_Type + +
- FUNCTION3 +: DWT_Type + +
- h -
-
+
- HFSR +: SCB_Type + +
- i -
-
+
- IABR +: NVIC_Type + +
- ICER +: NVIC_Type + +
- ICPR +: NVIC_Type + +
- ICSR +: SCB_Type + +
- ICTR +: SCnSCB_Type + +
- IP +: NVIC_Type + +
- ISAR +: SCB_Type + +
- ISER +: NVIC_Type + +
- ISPR +: NVIC_Type + +
- ISR +: IPSR_Type +, xPSR_Type + +
- IT +: xPSR_Type + +
- ITATBCTR0 +: TPI_Type + +
- ITATBCTR2 +: TPI_Type + +
- ITCTRL +: TPI_Type + +
- l -
-
+
- LOAD +: SysTick_Type + +
- LSUCNT +: DWT_Type + +
- m -
-
+
- MASK0 +: DWT_Type + +
- MASK1 +: DWT_Type + +
- MASK2 +: DWT_Type + +
- MASK3 +: DWT_Type + +
- MMFAR +: SCB_Type + +
- MMFR +: SCB_Type + +
- MVFR0 +: FPU_Type + +
- MVFR1 +: FPU_Type + +
- n -
-
+
- N +: APSR_Type +, xPSR_Type + +
- nPRIV +: CONTROL_Type + +
- p -
+ + +- q -
+ + +- r -
-
+
- RASR +: MPU_Type + +
- RASR_A1 +: MPU_Type + +
- RASR_A2 +: MPU_Type + +
- RASR_A3 +: MPU_Type + +
- RBAR +: MPU_Type + +
- RBAR_A1 +: MPU_Type + +
- RBAR_A2 +: MPU_Type + +
- RBAR_A3 +: MPU_Type + +
- RESERVED0 +: NVIC_Type +, SCB_Type +, SCnSCB_Type +, ITM_Type +, FPU_Type +, DWT_Type +, TPI_Type + +
- RESERVED1 +: ITM_Type +, DWT_Type +, TPI_Type + +
- RESERVED2 +: ITM_Type +, DWT_Type +, TPI_Type +, NVIC_Type + +
- RESERVED3 +: TPI_Type +, NVIC_Type + +
- RESERVED4 +: NVIC_Type +, TPI_Type + +
- RESERVED5 +: TPI_Type +, NVIC_Type + +
- RESERVED7 +: TPI_Type + +
- RNR +: MPU_Type + +
- RSERVED1 +: NVIC_Type + +
- s -
-
+
- SCR +: SCB_Type + +
- SHCSR +: SCB_Type + +
- SHP +: SCB_Type + +
- SLEEPCNT +: DWT_Type + +
- SPPR +: TPI_Type + +
- SPSEL +: CONTROL_Type + +
- SSPSR +: TPI_Type + +
- STIR +: NVIC_Type + +
- t -
-
+
- T +: xPSR_Type + +
- TCR +: ITM_Type + +
- TER +: ITM_Type + +
- TPR +: ITM_Type + +
- TRIGGER +: TPI_Type + +
- TYPE +: MPU_Type + +
- u -
+ + +- v -
-
+
- V +: APSR_Type +, xPSR_Type + +
- VAL +: SysTick_Type + +
- VTOR +: SCB_Type + +
- w -
-
+
- w +: APSR_Type +, CONTROL_Type +, xPSR_Type +, IPSR_Type + +
- z -
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+ |
+
+
+ CMSIS-CORE
+ Version 3.01
+
+ CMSIS-CORE support for Cortex-M processor-based devices
+ |
+
+
+
+
+
+
+
+
+-
+
- Main Page +
- Usage and Description +
- Reference +
-
+ + ++
+
+
+
+
+
+
+
+
+
+
+
+
diff --git a/Libraries/CMSIS/Documentation/Core/html/globals.html b/Libraries/CMSIS/Documentation/Core/html/globals.html
new file mode 100644
index 0000000..98b702d
--- /dev/null
+++ b/Libraries/CMSIS/Documentation/Core/html/globals.html
@@ -0,0 +1,605 @@
+
+
+
+
+
+
+
+
+- _ -
-
+
- _reserved0 +: APSR_Type +, CONTROL_Type +, xPSR_Type +, IPSR_Type + +
- a -
-
+
- ACPR +: TPI_Type + +
- ACTLR +: SCnSCB_Type + +
- ADR +: SCB_Type + +
- AFSR +: SCB_Type + +
- AIRCR +: SCB_Type + +
- b -
-
+
- b +: APSR_Type +, IPSR_Type +, CONTROL_Type +, xPSR_Type + +
- BFAR +: SCB_Type + +
- c -
-
+
- C +: APSR_Type +, xPSR_Type + +
- CALIB +: SysTick_Type + +
- CCR +: SCB_Type + +
- CFSR +: SCB_Type + +
- CLAIMCLR +: TPI_Type + +
- CLAIMSET +: TPI_Type + +
- COMP0 +: DWT_Type + +
- COMP1 +: DWT_Type + +
- COMP2 +: DWT_Type + +
- COMP3 +: DWT_Type + +
- CPACR +: SCB_Type + +
- CPICNT +: DWT_Type + +
- CPUID +: SCB_Type + +
- CSPSR +: TPI_Type + +
- CTRL +: DWT_Type +, MPU_Type +, SysTick_Type + +
- CYCCNT +: DWT_Type + +
- d -
-
+
- DCRDR +: CoreDebug_Type + +
- DCRSR +: CoreDebug_Type + +
- DEMCR +: CoreDebug_Type + +
- DEVID +: TPI_Type + +
- DEVTYPE +: TPI_Type + +
- DFR +: SCB_Type + +
- DFSR +: SCB_Type + +
- DHCSR +: CoreDebug_Type + +
- e -
-
+
- EXCCNT +: DWT_Type + +
- f -
-
+
- FFCR +: TPI_Type + +
- FFSR +: TPI_Type + +
- FIFO0 +: TPI_Type + +
- FIFO1 +: TPI_Type + +
- FOLDCNT +: DWT_Type + +
- FPCA +: CONTROL_Type + +
- FPCAR +: FPU_Type + +
- FPCCR +: FPU_Type + +
- FPDSCR +: FPU_Type + +
- FSCR +: TPI_Type + +
- FUNCTION0 +: DWT_Type + +
- FUNCTION1 +: DWT_Type + +
- FUNCTION2 +: DWT_Type + +
- FUNCTION3 +: DWT_Type + +
- h -
-
+
- HFSR +: SCB_Type + +
- i -
-
+
- IABR +: NVIC_Type + +
- ICER +: NVIC_Type + +
- ICPR +: NVIC_Type + +
- ICSR +: SCB_Type + +
- ICTR +: SCnSCB_Type + +
- IP +: NVIC_Type + +
- ISAR +: SCB_Type + +
- ISER +: NVIC_Type + +
- ISPR +: NVIC_Type + +
- ISR +: IPSR_Type +, xPSR_Type + +
- IT +: xPSR_Type + +
- ITATBCTR0 +: TPI_Type + +
- ITATBCTR2 +: TPI_Type + +
- ITCTRL +: TPI_Type + +
- l -
-
+
- LOAD +: SysTick_Type + +
- LSUCNT +: DWT_Type + +
- m -
-
+
- MASK0 +: DWT_Type + +
- MASK1 +: DWT_Type + +
- MASK2 +: DWT_Type + +
- MASK3 +: DWT_Type + +
- MMFAR +: SCB_Type + +
- MMFR +: SCB_Type + +
- MVFR0 +: FPU_Type + +
- MVFR1 +: FPU_Type + +
- n -
-
+
- N +: APSR_Type +, xPSR_Type + +
- nPRIV +: CONTROL_Type + +
- p -
+ + +- q -
+ + +- r -
-
+
- RASR +: MPU_Type + +
- RASR_A1 +: MPU_Type + +
- RASR_A2 +: MPU_Type + +
- RASR_A3 +: MPU_Type + +
- RBAR +: MPU_Type + +
- RBAR_A1 +: MPU_Type + +
- RBAR_A2 +: MPU_Type + +
- RBAR_A3 +: MPU_Type + +
- RESERVED0 +: NVIC_Type +, SCB_Type +, SCnSCB_Type +, ITM_Type +, FPU_Type +, DWT_Type +, TPI_Type + +
- RESERVED1 +: ITM_Type +, DWT_Type +, TPI_Type + +
- RESERVED2 +: ITM_Type +, DWT_Type +, TPI_Type +, NVIC_Type + +
- RESERVED3 +: TPI_Type +, NVIC_Type + +
- RESERVED4 +: NVIC_Type +, TPI_Type + +
- RESERVED5 +: TPI_Type +, NVIC_Type + +
- RESERVED7 +: TPI_Type + +
- RNR +: MPU_Type + +
- RSERVED1 +: NVIC_Type + +
- s -
-
+
- SCR +: SCB_Type + +
- SHCSR +: SCB_Type + +
- SHP +: SCB_Type + +
- SLEEPCNT +: DWT_Type + +
- SPPR +: TPI_Type + +
- SPSEL +: CONTROL_Type + +
- SSPSR +: TPI_Type + +
- STIR +: NVIC_Type + +
- t -
-
+
- T +: xPSR_Type + +
- TCR +: ITM_Type + +
- TER +: ITM_Type + +
- TPR +: ITM_Type + +
- TRIGGER +: TPI_Type + +
- TYPE +: MPU_Type + +
- u -
+ + +- v -
-
+
- V +: APSR_Type +, xPSR_Type + +
- VAL +: SysTick_Type + +
- VTOR +: SCB_Type + +
- w -
-
+
- w +: APSR_Type +, CONTROL_Type +, xPSR_Type +, IPSR_Type + +
- z -
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+ |
+
+
+ CMSIS-CORE
+ Version 3.01
+
+ CMSIS-CORE support for Cortex-M processor-based devices
+ |
+
+
+
+
+
+
+
+-
+
- Main Page +
- Usage and Description +
- Reference +
-
+ + ++
+
+
+
+
+
+
+
+
+
+
+
+
diff --git a/Libraries/CMSIS/Documentation/Core/html/globals_enum.html b/Libraries/CMSIS/Documentation/Core/html/globals_enum.html
new file mode 100644
index 0000000..1db4027
--- /dev/null
+++ b/Libraries/CMSIS/Documentation/Core/html/globals_enum.html
@@ -0,0 +1,140 @@
+
+
+
+
+
+
+Here is a list of all functions, variables, defines, enums, and typedefs with links to the files they belong to:
+
+- _ -
-
+
- __CLREX() +: Ref_cmInstr.txt + +
- __CLZ() +: Ref_cmInstr.txt + +
- __disable_fault_irq() +: Ref_CoreReg.txt + +
- __disable_irq() +: Ref_CoreReg.txt + +
- __DMB() +: Ref_cmInstr.txt + +
- __DSB() +: Ref_cmInstr.txt + +
- __enable_fault_irq() +: Ref_CoreReg.txt + +
- __enable_irq() +: Ref_CoreReg.txt + +
- __get_APSR() +: Ref_CoreReg.txt + +
- __get_BASEPRI() +: Ref_CoreReg.txt + +
- __get_CONTROL() +: Ref_CoreReg.txt + +
- __get_FAULTMASK() +: Ref_CoreReg.txt + +
- __get_FPSCR() +: Ref_CoreReg.txt + +
- __get_IPSR() +: Ref_CoreReg.txt + +
- __get_MSP() +: Ref_CoreReg.txt + +
- __get_PRIMASK() +: Ref_CoreReg.txt + +
- __get_PSP() +: Ref_CoreReg.txt + +
- __get_xPSR() +: Ref_CoreReg.txt + +
- __ISB() +: Ref_cmInstr.txt + +
- __LDREXB() +: Ref_cmInstr.txt + +
- __LDREXH() +: Ref_cmInstr.txt + +
- __LDREXW() +: Ref_cmInstr.txt + +
- __NOP() +: Ref_cmInstr.txt + +
- __PKHBT() +: Ref_cm4_simd.txt + +
- __PKHTB() +: Ref_cm4_simd.txt + +
- __QADD() +: Ref_cm4_simd.txt + +
- __QADD16() +: Ref_cm4_simd.txt + +
- __QADD8() +: Ref_cm4_simd.txt + +
- __QASX() +: Ref_cm4_simd.txt + +
- __QSAX() +: Ref_cm4_simd.txt + +
- __QSUB() +: Ref_cm4_simd.txt + +
- __QSUB16() +: Ref_cm4_simd.txt + +
- __QSUB8() +: Ref_cm4_simd.txt + +
- __RBIT() +: Ref_cmInstr.txt + +
- __REV() +: Ref_cmInstr.txt + +
- __REV16() +: Ref_cmInstr.txt + +
- __REVSH() +: Ref_cmInstr.txt + +
- __ROR() +: Ref_cmInstr.txt + +
- __SADD16() +: Ref_cm4_simd.txt + +
- __SADD8() +: Ref_cm4_simd.txt + +
- __SASX() +: Ref_cm4_simd.txt + +
- __SEL() +: Ref_cm4_simd.txt + +
- __set_BASEPRI() +: Ref_CoreReg.txt + +
- __set_CONTROL() +: Ref_CoreReg.txt + +
- __set_FAULTMASK() +: Ref_CoreReg.txt + +
- __set_FPSCR() +: Ref_CoreReg.txt + +
- __set_MSP() +: Ref_CoreReg.txt + +
- __set_PRIMASK() +: Ref_CoreReg.txt + +
- __set_PSP() +: Ref_CoreReg.txt + +
- __SEV() +: Ref_cmInstr.txt + +
- __SHADD16() +: Ref_cm4_simd.txt + +
- __SHADD8() +: Ref_cm4_simd.txt + +
- __SHASX() +: Ref_cm4_simd.txt + +
- __SHSAX() +: Ref_cm4_simd.txt + +
- __SHSUB16() +: Ref_cm4_simd.txt + +
- __SHSUB8() +: Ref_cm4_simd.txt + +
- __SMLAD() +: Ref_cm4_simd.txt + +
- __SMLADX() +: Ref_cm4_simd.txt + +
- __SMLALD() +: Ref_cm4_simd.txt + +
- __SMLALDX() +: Ref_cm4_simd.txt + +
- __SMLSD() +: Ref_cm4_simd.txt + +
- __SMLSDX() +: Ref_cm4_simd.txt + +
- __SMLSLD() +: Ref_cm4_simd.txt + +
- __SMLSLDX() +: Ref_cm4_simd.txt + +
- __SMUAD() +: Ref_cm4_simd.txt + +
- __SMUADX() +: Ref_cm4_simd.txt + +
- __SMUSD() +: Ref_cm4_simd.txt + +
- __SMUSDX() +: Ref_cm4_simd.txt + +
- __SSAT() +: Ref_cmInstr.txt + +
- __SSAT16() +: Ref_cm4_simd.txt + +
- __SSAX() +: Ref_cm4_simd.txt + +
- __SSUB16() +: Ref_cm4_simd.txt + +
- __SSUB8() +: Ref_cm4_simd.txt + +
- __STREXB() +: Ref_cmInstr.txt + +
- __STREXH() +: Ref_cmInstr.txt + +
- __STREXW() +: Ref_cmInstr.txt + +
- __SXTAB16() +: Ref_cm4_simd.txt + +
- __SXTB16() +: Ref_cm4_simd.txt + +
- __UADD16() +: Ref_cm4_simd.txt + +
- __UADD8() +: Ref_cm4_simd.txt + +
- __UASX() +: Ref_cm4_simd.txt + +
- __UHADD16() +: Ref_cm4_simd.txt + +
- __UHADD8() +: Ref_cm4_simd.txt + +
- __UHASX() +: Ref_cm4_simd.txt + +
- __UHSAX() +: Ref_cm4_simd.txt + +
- __UHSUB16() +: Ref_cm4_simd.txt + +
- __UHSUB8() +: Ref_cm4_simd.txt + +
- __UQADD16() +: Ref_cm4_simd.txt + +
- __UQADD8() +: Ref_cm4_simd.txt + +
- __UQASX() +: Ref_cm4_simd.txt + +
- __UQSAX() +: Ref_cm4_simd.txt + +
- __UQSUB16() +: Ref_cm4_simd.txt + +
- __UQSUB8() +: Ref_cm4_simd.txt + +
- __USAD8() +: Ref_cm4_simd.txt + +
- __USADA8() +: Ref_cm4_simd.txt + +
- __USAT() +: Ref_cmInstr.txt + +
- __USAT16() +: Ref_cm4_simd.txt + +
- __USAX() +: Ref_cm4_simd.txt + +
- __USUB16() +: Ref_cm4_simd.txt + +
- __USUB8() +: Ref_cm4_simd.txt + +
- __UXTAB16() +: Ref_cm4_simd.txt + +
- __UXTB16() +: Ref_cm4_simd.txt + +
- __WFE() +: Ref_cmInstr.txt + +
- __WFI() +: Ref_cmInstr.txt + +
- b -
-
+
- BusFault_IRQn +: Ref_NVIC.txt + +
- d -
-
+
- DebugMonitor_IRQn +: Ref_NVIC.txt + +
- h -
-
+
- HardFault_IRQn +: Ref_NVIC.txt + +
- i -
-
+
- IRQn_Type +: Ref_NVIC.txt + +
- ITM_CheckChar() +: Ref_Debug.txt + +
- ITM_ReceiveChar() +: Ref_Debug.txt + +
- ITM_RxBuffer +: Ref_Debug.txt + +
- ITM_SendChar() +: Ref_Debug.txt + +
- m -
-
+
- MemoryManagement_IRQn +: Ref_NVIC.txt + +
- n -
-
+
- NonMaskableInt_IRQn +: Ref_NVIC.txt + +
- NVIC_ClearPendingIRQ() +: Ref_NVIC.txt + +
- NVIC_DecodePriority() +: Ref_NVIC.txt + +
- NVIC_DisableIRQ() +: Ref_NVIC.txt + +
- NVIC_EnableIRQ() +: Ref_NVIC.txt + +
- NVIC_EncodePriority() +: Ref_NVIC.txt + +
- NVIC_GetActive() +: Ref_NVIC.txt + +
- NVIC_GetPendingIRQ() +: Ref_NVIC.txt + +
- NVIC_GetPriority() +: Ref_NVIC.txt + +
- NVIC_GetPriorityGrouping() +: Ref_NVIC.txt + +
- NVIC_SetPendingIRQ() +: Ref_NVIC.txt + +
- NVIC_SetPriority() +: Ref_NVIC.txt + +
- NVIC_SetPriorityGrouping() +: Ref_NVIC.txt + +
- NVIC_SystemReset() +: Ref_NVIC.txt + +
- p -
-
+
- PendSV_IRQn +: Ref_NVIC.txt + +
- PVD_STM_IRQn +: Ref_NVIC.txt + +
- s -
-
+
- SVCall_IRQn +: Ref_NVIC.txt + +
- SystemCoreClock +: Ref_SystemAndClock.txt + +
- SystemCoreClockUpdate() +: Ref_SystemAndClock.txt + +
- SystemInit() +: Ref_SystemAndClock.txt + +
- SysTick_Config() +: Ref_Systick.txt + +
- SysTick_IRQn +: Ref_NVIC.txt + +
- u -
-
+
- UsageFault_IRQn +: Ref_NVIC.txt + +
- w -
-
+
- WWDG_STM_IRQn +: Ref_NVIC.txt + +
+
+
+
+
+
+
+
+
+
+
+
+
+
+ |
+
+
+ CMSIS-CORE
+ Version 3.01
+
+ CMSIS-CORE support for Cortex-M processor-based devices
+ |
+
+
+
+
+
+
+-
+
- Main Page +
- Usage and Description +
- Reference +
-
+ + ++
+
+
+
+
+
+
+
+
+
+
+
+
diff --git a/Libraries/CMSIS/Documentation/Core/html/globals_eval.html b/Libraries/CMSIS/Documentation/Core/html/globals_eval.html
new file mode 100644
index 0000000..5260e40
--- /dev/null
+++ b/Libraries/CMSIS/Documentation/Core/html/globals_eval.html
@@ -0,0 +1,170 @@
+
+
+
+
+
+
+-
+
- IRQn_Type +: Ref_NVIC.txt + +
+
+
+
+
+
+
+
+
+
+
+
+
+
+ |
+
+
+ CMSIS-CORE
+ Version 3.01
+
+ CMSIS-CORE support for Cortex-M processor-based devices
+ |
+
+
+
+
+
+
+-
+
- Main Page +
- Usage and Description +
- Reference +
-
+ + ++
+
+
+
+
+
+
+
+
+
+
+
+
diff --git a/Libraries/CMSIS/Documentation/Core/html/globals_func.html b/Libraries/CMSIS/Documentation/Core/html/globals_func.html
new file mode 100644
index 0000000..2046327
--- /dev/null
+++ b/Libraries/CMSIS/Documentation/Core/html/globals_func.html
@@ -0,0 +1,528 @@
+
+
+
+
+
+
+-
+
- BusFault_IRQn +: Ref_NVIC.txt + +
- DebugMonitor_IRQn +: Ref_NVIC.txt + +
- HardFault_IRQn +: Ref_NVIC.txt + +
- MemoryManagement_IRQn +: Ref_NVIC.txt + +
- NonMaskableInt_IRQn +: Ref_NVIC.txt + +
- PendSV_IRQn +: Ref_NVIC.txt + +
- PVD_STM_IRQn +: Ref_NVIC.txt + +
- SVCall_IRQn +: Ref_NVIC.txt + +
- SysTick_IRQn +: Ref_NVIC.txt + +
- UsageFault_IRQn +: Ref_NVIC.txt + +
- WWDG_STM_IRQn +: Ref_NVIC.txt + +
+
+
+
+
+
+
+
+
+
+
+
+
+
+ |
+
+
+ CMSIS-CORE
+ Version 3.01
+
+ CMSIS-CORE support for Cortex-M processor-based devices
+ |
+
+
+
+
+
+
+
+-
+
- Main Page +
- Usage and Description +
- Reference +
-
+ + ++
+
+
+
+
+
+
+
+
+
+
+
+
diff --git a/Libraries/CMSIS/Documentation/Core/html/globals_vars.html b/Libraries/CMSIS/Documentation/Core/html/globals_vars.html
new file mode 100644
index 0000000..dab8d57
--- /dev/null
+++ b/Libraries/CMSIS/Documentation/Core/html/globals_vars.html
@@ -0,0 +1,143 @@
+
+
+
+
+
+
+
+
+- _ -
-
+
- __CLREX() +: Ref_cmInstr.txt + +
- __CLZ() +: Ref_cmInstr.txt + +
- __disable_fault_irq() +: Ref_CoreReg.txt + +
- __disable_irq() +: Ref_CoreReg.txt + +
- __DMB() +: Ref_cmInstr.txt + +
- __DSB() +: Ref_cmInstr.txt + +
- __enable_fault_irq() +: Ref_CoreReg.txt + +
- __enable_irq() +: Ref_CoreReg.txt + +
- __get_APSR() +: Ref_CoreReg.txt + +
- __get_BASEPRI() +: Ref_CoreReg.txt + +
- __get_CONTROL() +: Ref_CoreReg.txt + +
- __get_FAULTMASK() +: Ref_CoreReg.txt + +
- __get_FPSCR() +: Ref_CoreReg.txt + +
- __get_IPSR() +: Ref_CoreReg.txt + +
- __get_MSP() +: Ref_CoreReg.txt + +
- __get_PRIMASK() +: Ref_CoreReg.txt + +
- __get_PSP() +: Ref_CoreReg.txt + +
- __get_xPSR() +: Ref_CoreReg.txt + +
- __ISB() +: Ref_cmInstr.txt + +
- __LDREXB() +: Ref_cmInstr.txt + +
- __LDREXH() +: Ref_cmInstr.txt + +
- __LDREXW() +: Ref_cmInstr.txt + +
- __NOP() +: Ref_cmInstr.txt + +
- __PKHBT() +: Ref_cm4_simd.txt + +
- __PKHTB() +: Ref_cm4_simd.txt + +
- __QADD() +: Ref_cm4_simd.txt + +
- __QADD16() +: Ref_cm4_simd.txt + +
- __QADD8() +: Ref_cm4_simd.txt + +
- __QASX() +: Ref_cm4_simd.txt + +
- __QSAX() +: Ref_cm4_simd.txt + +
- __QSUB() +: Ref_cm4_simd.txt + +
- __QSUB16() +: Ref_cm4_simd.txt + +
- __QSUB8() +: Ref_cm4_simd.txt + +
- __RBIT() +: Ref_cmInstr.txt + +
- __REV() +: Ref_cmInstr.txt + +
- __REV16() +: Ref_cmInstr.txt + +
- __REVSH() +: Ref_cmInstr.txt + +
- __ROR() +: Ref_cmInstr.txt + +
- __SADD16() +: Ref_cm4_simd.txt + +
- __SADD8() +: Ref_cm4_simd.txt + +
- __SASX() +: Ref_cm4_simd.txt + +
- __SEL() +: Ref_cm4_simd.txt + +
- __set_BASEPRI() +: Ref_CoreReg.txt + +
- __set_CONTROL() +: Ref_CoreReg.txt + +
- __set_FAULTMASK() +: Ref_CoreReg.txt + +
- __set_FPSCR() +: Ref_CoreReg.txt + +
- __set_MSP() +: Ref_CoreReg.txt + +
- __set_PRIMASK() +: Ref_CoreReg.txt + +
- __set_PSP() +: Ref_CoreReg.txt + +
- __SEV() +: Ref_cmInstr.txt + +
- __SHADD16() +: Ref_cm4_simd.txt + +
- __SHADD8() +: Ref_cm4_simd.txt + +
- __SHASX() +: Ref_cm4_simd.txt + +
- __SHSAX() +: Ref_cm4_simd.txt + +
- __SHSUB16() +: Ref_cm4_simd.txt + +
- __SHSUB8() +: Ref_cm4_simd.txt + +
- __SMLAD() +: Ref_cm4_simd.txt + +
- __SMLADX() +: Ref_cm4_simd.txt + +
- __SMLALD() +: Ref_cm4_simd.txt + +
- __SMLALDX() +: Ref_cm4_simd.txt + +
- __SMLSD() +: Ref_cm4_simd.txt + +
- __SMLSDX() +: Ref_cm4_simd.txt + +
- __SMLSLD() +: Ref_cm4_simd.txt + +
- __SMLSLDX() +: Ref_cm4_simd.txt + +
- __SMUAD() +: Ref_cm4_simd.txt + +
- __SMUADX() +: Ref_cm4_simd.txt + +
- __SMUSD() +: Ref_cm4_simd.txt + +
- __SMUSDX() +: Ref_cm4_simd.txt + +
- __SSAT() +: Ref_cmInstr.txt + +
- __SSAT16() +: Ref_cm4_simd.txt + +
- __SSAX() +: Ref_cm4_simd.txt + +
- __SSUB16() +: Ref_cm4_simd.txt + +
- __SSUB8() +: Ref_cm4_simd.txt + +
- __STREXB() +: Ref_cmInstr.txt + +
- __STREXH() +: Ref_cmInstr.txt + +
- __STREXW() +: Ref_cmInstr.txt + +
- __SXTAB16() +: Ref_cm4_simd.txt + +
- __SXTB16() +: Ref_cm4_simd.txt + +
- __UADD16() +: Ref_cm4_simd.txt + +
- __UADD8() +: Ref_cm4_simd.txt + +
- __UASX() +: Ref_cm4_simd.txt + +
- __UHADD16() +: Ref_cm4_simd.txt + +
- __UHADD8() +: Ref_cm4_simd.txt + +
- __UHASX() +: Ref_cm4_simd.txt + +
- __UHSAX() +: Ref_cm4_simd.txt + +
- __UHSUB16() +: Ref_cm4_simd.txt + +
- __UHSUB8() +: Ref_cm4_simd.txt + +
- __UQADD16() +: Ref_cm4_simd.txt + +
- __UQADD8() +: Ref_cm4_simd.txt + +
- __UQASX() +: Ref_cm4_simd.txt + +
- __UQSAX() +: Ref_cm4_simd.txt + +
- __UQSUB16() +: Ref_cm4_simd.txt + +
- __UQSUB8() +: Ref_cm4_simd.txt + +
- __USAD8() +: Ref_cm4_simd.txt + +
- __USADA8() +: Ref_cm4_simd.txt + +
- __USAT() +: Ref_cmInstr.txt + +
- __USAT16() +: Ref_cm4_simd.txt + +
- __USAX() +: Ref_cm4_simd.txt + +
- __USUB16() +: Ref_cm4_simd.txt + +
- __USUB8() +: Ref_cm4_simd.txt + +
- __UXTAB16() +: Ref_cm4_simd.txt + +
- __UXTB16() +: Ref_cm4_simd.txt + +
- __WFE() +: Ref_cmInstr.txt + +
- __WFI() +: Ref_cmInstr.txt + +
- i -
-
+
- ITM_CheckChar() +: Ref_Debug.txt + +
- ITM_ReceiveChar() +: Ref_Debug.txt + +
- ITM_SendChar() +: Ref_Debug.txt + +
- n -
-
+
- NVIC_ClearPendingIRQ() +: Ref_NVIC.txt + +
- NVIC_DecodePriority() +: Ref_NVIC.txt + +
- NVIC_DisableIRQ() +: Ref_NVIC.txt + +
- NVIC_EnableIRQ() +: Ref_NVIC.txt + +
- NVIC_EncodePriority() +: Ref_NVIC.txt + +
- NVIC_GetActive() +: Ref_NVIC.txt + +
- NVIC_GetPendingIRQ() +: Ref_NVIC.txt + +
- NVIC_GetPriority() +: Ref_NVIC.txt + +
- NVIC_GetPriorityGrouping() +: Ref_NVIC.txt + +
- NVIC_SetPendingIRQ() +: Ref_NVIC.txt + +
- NVIC_SetPriority() +: Ref_NVIC.txt + +
- NVIC_SetPriorityGrouping() +: Ref_NVIC.txt + +
- NVIC_SystemReset() +: Ref_NVIC.txt + +
- s -
-
+
- SystemCoreClockUpdate() +: Ref_SystemAndClock.txt + +
- SystemInit() +: Ref_SystemAndClock.txt + +
- SysTick_Config() +: Ref_Systick.txt + +
+
+
+
+
+
+
+
+
+
+
+
+
+
+ |
+
+
+ CMSIS-CORE
+ Version 3.01
+
+ CMSIS-CORE support for Cortex-M processor-based devices
+ |
+
+
+
+
+
+
+-
+
- Main Page +
- Usage and Description +
- Reference +
-
+ + ++
+
+
+
+
+
+
+
+
+
+
+
+
diff --git a/Libraries/CMSIS/Documentation/Core/html/group___core___register__gr.html b/Libraries/CMSIS/Documentation/Core/html/group___core___register__gr.html
new file mode 100644
index 0000000..1974899
--- /dev/null
+++ b/Libraries/CMSIS/Documentation/Core/html/group___core___register__gr.html
@@ -0,0 +1,1148 @@
+
+
+
+
+
+
+-
+
- ITM_RxBuffer +: Ref_Debug.txt + +
- SystemCoreClock +: Ref_SystemAndClock.txt + +
+
+
+
+
+
+
+
+
+
+
+
+
+
+ |
+
+
+ CMSIS-CORE
+ Version 3.01
+
+ CMSIS-CORE support for Cortex-M processor-based devices
+ |
+
+
+
+
+
+-
+
- Main Page +
- Usage and Description +
- Reference +
-
+ + ++
+
+
+
+
+
+
+
+
+
+
+
+
diff --git a/Libraries/CMSIS/Documentation/Core/html/group___i_t_m___debug__gr.html b/Libraries/CMSIS/Documentation/Core/html/group___i_t_m___debug__gr.html
new file mode 100644
index 0000000..08890ab
--- /dev/null
+++ b/Libraries/CMSIS/Documentation/Core/html/group___i_t_m___debug__gr.html
@@ -0,0 +1,278 @@
+
+
+
+
+
+
+
+
+
+Core Register Access
+
+
+
++Functions | |
| uint32_t | __get_CONTROL (void) |
| Read the CONTROL register. | |
| void | __set_CONTROL (uint32_t control) |
| Set the CONTROL Register. | |
| uint32_t | __get_IPSR (void) |
| Read the IPSR register. | |
| uint32_t | __get_APSR (void) |
| Read the APSR register. | |
| uint32_t | __get_xPSR (void) |
| Read the xPSR register. | |
| uint32_t | __get_PSP (void) |
| Read the PSP register. | |
| void | __set_PSP (uint32_t topOfProcStack) |
| Set the PSP register. | |
| uint32_t | __get_MSP (void) |
| Read the MSP register. | |
| void | __set_MSP (uint32_t topOfMainStack) |
| Set the MSP register. | |
| uint32_t | __get_PRIMASK (void) |
| Read the PRIMASK register bit. | |
| void | __set_PRIMASK (uint32_t priMask) |
| Set the Priority Mask bit. | |
| uint32_t | __get_BASEPRI (void) |
| Read the BASEPRI register [not for Cortex-M0 variants]. | |
| void | __set_BASEPRI (uint32_t basePri) |
| Set the BASEPRI register [not for Cortex-M0 variants]. | |
| uint32_t | __get_FAULTMASK (void) |
| Read the FAULTMASK register [not for Cortex-M0 variants]. | |
| void | __set_FAULTMASK (uint32_t faultMask) |
| Set the FAULTMASK register [not for Cortex-M0 variants]. | |
| uint32_t | __get_FPSCR (void) |
| Read the FPSCR register [only for Cortex-M4]. | |
| void | __set_FPSCR (uint32_t fpscr) |
| Set the FPSC register [only for Cortex-M4]. | |
| void | __enable_irq (void) |
| Globally enables interrupts and configurable fault handlers. | |
| void | __disable_irq (void) |
| Globally disables interrupts and configurable fault handlers. | |
| void | __enable_fault_irq (void) |
| Enables interrupts and all fault handlers [not for Cortex-M0 variants]. | |
| void | __disable_fault_irq (void) |
| Disables interrupts and all fault handlers [not for Cortex-M0 variants]. | |
Description
+The following functions provide access to Cortex-M core registers.
+Function Documentation
+ +
+
+
+
+
+
+
+| void __disable_fault_irq | +( | +void | +) | ++ |
+
+The function disables interrupts and all fault handlers by setting the F-bit in the CPSR. The function uses the instruction CPSID f.
+- Remarks:
-
+
- not for Cortex-M0 variants. +
- Can be executed in privileged mode only. +
- An interrupt can enter pending state even if it is disabled. Disabling an interrupt only prevents the processor from taking that interrupt. +
- See also:
- +
+
+
+
+
+
+
+| void __disable_irq | +( | +void | +) | ++ |
+
+The function disables interrupts and all configurable fault handlers by setting the I-bit in the CPSR. The function uses the instruction CPSID i.
+- Remarks:
-
+
- Can be executed in privileged mode only. +
- Basically, it sets PRIMASK. +
- An interrupt can enter pending state even if it is disabled. Disabling an interrupt only prevents the processor from taking that interrupt. +
- See also:
- +
+
+
+
+
+
+
+| void __enable_fault_irq | +( | +void | +) | ++ |
+
+The function enables interrupts and all fault handlers by clearing the F-bit in the CPSR. The function uses the instruction CPSIE f.
+- Remarks:
-
+
- not for Cortex-M0 variants. +
- Can be executed in privileged mode only. +
- See also:
- +
+
+
+
+
+
+
+| void __enable_irq | +( | +void | +) | ++ |
+
+The function enables interrupts and all configurable fault handlers by clearing the I-bit in the CPSR. The function uses the instruction CPSIE i.
+- Remarks:
-
+
- Can be executed in privileged mode only. +
- Basically, it clears PRIMASK. +
- See also:
- +
+
+
+
+
+
+
+| uint32_t __get_APSR | +( | +void | +) | ++ |
+
+The function reads the Application Program Status Register (APSR) using the instruction MRS.
+
+ The APSR contains the current state of the condition flags from instructions executed previously. The APSR is essential for controlling conditional branches. The following flags are used:
-
+
- N (APSR[31]) (Negative flag)
-
+
- =1 The instruction result has a negative value (when interpreted as signed integer). +
- =0 The instruction result has a positive value or equal zero.
+
+
+
+ - Z (APSR[30]) (Zero flag)
-
+
- =1 The instruction result is zero. Or, after a compare instruction, when the two values are the same.
+
+
+
+ - =1 The instruction result is zero. Or, after a compare instruction, when the two values are the same.
- C (APSR[29]) (Carry or borrow flag)
-
+
- =1 For unsigned additions, if an unsigned overflow occurred. +
- =inverse of borrow output status For unsigned subtract operations.
+
+
+
+ - V (APSR[28]) (Overflow flag)
-
+
- =1 A signed overflow occurred (for signed additions or subtractions).
+
+
+
+ - =1 A signed overflow occurred (for signed additions or subtractions).
- Q (APSR[27]) (DSP overflow or saturation flag) [not Cortex-M0]
-
+
- This flag is a sticky flag. Saturating and certain mutliplying instructions can set the flag, but cannot clear it. +
- =1 When saturation or an overflow occurred.
+
+
+
+ - GE (APSR[19:16]) (Greater than or Equal flags) [not Cortex-M0]
-
+
- Can be set by the parallel add and subtract instructions. +
- Are used by the
SELinstruction to perform byte-based selection from two registers.
+
+
- Returns:
- APSR register value
- Remarks:
-
+
- Some instructions update all flags; some instructions update a subset of the flags. +
- If a flag is not updated, the original value is preserved. +
- Conditional instructions that are not executed have no effect on the flags. +
- The CMSIS does not provide a function to update this register. +
- See also:
- +
+
+
+
+
+
+
+| uint32_t __get_BASEPRI | +( | +void | +) | ++ |
+
+The function returns the Base Priority Mask register (BASEPRI) using the instruction MRS.
+
+ BASEPRI defines the minimum priority for exception processing. When BASEPRI is set to a non-zero value, it prevents the activation of all exceptions with the same or lower priority level as the BASEPRI value.
- Returns:
- BASEPRI register value
- Remarks:
-
+
- not for Cortex-M0 variants. +
- See also:
- +
+
+
+
+
+
+
+| uint32_t __get_CONTROL | +( | +void | +) | ++ |
+
+The function reads the CONTROL register value using the instruction MRS.
+
+ The CONTROL register controls the stack used and the privilege level for software execution when the processor is in thread mode and, if implemented, indicates whether the FPU state is active. This register uses the following bits:
+
-
+
- CONTROL[2] [only Cortex-M4]
-
+
- =0 FPU not active +
- =1 FPU active
+
+
+
+ - CONTROL[1]
-
+
- =0 In handler mode - MSP is selected. No alternate stack possible for handler mode. +
- =0 In thread mode - Default stack pointer MSP is used. +
- =1 In thread mode - Alternate stack pointer PSP is used.
+
+
+
+ - CONTROL[0] [not Cortex-M0]
-
+
- =0 In thread mode and privileged state. +
- =1 In thread mode and user state. +
+
- Returns:
- CONTROL register value
- Remarks:
-
+
- The processor can be in user state or privileged state when running in thread mode. +
- Exception handlers always run in privileged state. +
- On reset, the processor is in thread mode with privileged access rights. +
- See also:
- +
+
+
+
+
+
+
+| uint32_t __get_FAULTMASK | +( | +void | +) | ++ |
+
+The function reads the Fault Mask register (FAULTMASK) value using the instruction MRS.
+
+ FAULTMASK prevents activation of all exceptions except for the Non-Maskable Interrupt (NMI).
- Returns:
- FAULTMASK register value
- Remarks:
-
+
- not for Cortex-M0 variants. +
- Is cleared automatically upon exiting the exception handler, except when returning from the NMI handler. +
- See also:
- +
+
+
+
+
+
+
+| uint32_t __get_FPSCR | +( | +void | +) | ++ |
+
+The function reads the Floating-Point Status Control Register (FPSCR) value.
+
+ FPSCR provides all necessary User level controls of the floating-point system.
- Returns:
-
+
- FPSCR register value, when __FPU_PRESENT=1 +
- =0, when __FPU_PRESENT=0 +
- Remarks:
-
+
- Only for Cortex-M4. +
- See also:
- +
+
+
+
+
+
+
+| uint32_t __get_IPSR | +( | +void | +) | ++ |
+
+The function reads the Interrupt Program Status Register (IPSR) using the instruction MRS.
+
+ The ISPR contains the exception type number of the current Interrupt Service Routine (ISR). Each exception has an assocciated unique IRQn number. The following bits are used:
-
+
- ISR_NUMBER (IPSR[8:0])
-
+
- =0 Thread mode +
- =1 Reserved +
- =2 NMI +
- =3 HardFault +
- =4 MemManage +
- =5 BusFault +
- =6 UsageFault +
- =7-10 Reserved +
- =11 SVCall +
- =12 Reserved for Debug +
- =13 Reserved +
- =14 PendSV +
- =15 SysTick +
- =16 IRQ0 +
- ... +
- =n+15 IRQ(n-1) +
+
- Returns:
- ISPR register value
- Remarks:
-
+
- This register is read-only. +
- See also:
- +
+
+
+
+
+
+
+| uint32_t __get_MSP | +( | +void | +) | ++ |
+
+The function reads the Main Status Pointer (MSP) value using the instruction MRS.
+
+ Physically two different stack pointers (SP) exist:
-
+
- The Main Stack Pointer (MSP) is the default stack pointer after reset. It is also used when running exception handlers (handler mode). +
- The Process Stack Pointer (PSP), which can be used only in thread mode. +
Register R13 banks the SP. The SP selection is determined by the bit[1] of the CONTROL register:
+-
+
- =0 MSP is the current stack pointer. This is also the default SP. The initial value is loaded from the first 32-bit word of the vector table from the program memory. +
- =1 PSP is the current stack pointer. The initial value is undefined. +
- Returns:
- MSP Register value
- Remarks:
-
+
- Only one of the two SPs is visible at a time. +
- For many applications, the system can completely rely on the MSP. +
- The PSP is normally used in designs with an OS where the stack memory for OS Kernel must be separated from the application code. +
- See also:
- +
+
+
+
+
+
+
+| uint32_t __get_PRIMASK | +( | +void | +) | ++ |
+
+The function reads the Priority Mask register (PRIMASK) value using the instruction MRS.
+
+ PRIMASK is a 1-bit-wide interrupt mask register. When set, it blocks all interrupts apart from the non-maskable interrupt (NMI) and the hard fault exception. The PRIMASK prevents activation of all exceptions with configurable priority.
- Returns:
- PRIMASK register value
-
+
- =0 no effect +
- =1 prevents the activation of all exceptions with configurable priority +
- See also:
- +
+
+
+
+
+
+
+| uint32_t __get_PSP | +( | +void | +) | ++ |
+
+The function reads the Program Status Pointer (PSP) value using the instruction MRS.
+
+ Physically two different stack pointers (SP) exist:
-
+
- The Main Stack Pointer (MSP) is the default stack pointer after reset. It is also used when running exception handlers (handler mode). +
- The Process Stack Pointer (PSP), which can be used only in thread mode. +
Register R13 banks the SP. The SP selection is determined by the bit[1] of the CONTROL register:
+-
+
- =0 MSP is the current stack pointer. This is also the default SP. The initial value is loaded from the first 32-bit word of the vector table from the program memory. +
- =1 PSP is the current stack pointer. The initial value is undefined. +
- Returns:
- PSP register value
- Remarks:
-
+
- Only one of the two SPs is visible at a time. +
- For many applications, the system can completely rely on the MSP. +
- The PSP is normally used in designs with an OS where the stack memory for OS Kernel must be separated from the application code. +
- See also:
- +
+
+
+
+
+
+
+| uint32_t __get_xPSR | +( | +void | +) | ++ |
+
+The function reads the combined Program Status Register (xPSR) using the instruction MRS.
+
+ xPSR provides information about program execution and the APSR flags. It consists of the following PSRs:
-
+
- Application Program Status Register (APSR) +
- Interrupt Program Status Register (IPSR) +
- Execution Program Status Register (EPSR) +
In addition to the flags described in __get_APSR and __get_IPSR, the register provides the following flags:
+-
+
- IT (xPSR[26:25]) (If-Then condition instruction)
-
+
- Contains up to four instructions following an IT instruction. +
- Each instruction in the block is conditional. +
- The conditions for the instructions are either all the same, or some can be the inverse of others.
+
+
+
+ - T (xPSR[24]) (Thumb bit)
-
+
- =1 Indicates that that the processor is in Thumb state. +
- =0 Attempting to execute instructions when the T bit is 0 results in a fault or lockup. +
- The conditions for the instructions are either all the same, or some can be the inverse of others. +
+
- Returns:
- xPSR register value
- Remarks:
-
+
- The CMSIS does not provide functions that access EPSR. +
- See also:
- +
+
+
+
+
+
+
+| void __set_BASEPRI | +( | +uint32_t | +basePri | ) | ++ |
+
+The function sets the Base Priority Mask register (BASEPRI) value using the instruction MSR.
+
+ BASEPRI defines the minimum priority for exception processing. When BASEPRI is set to a non-zero value, it prevents the activation of all exceptions with the same or lower priority level as the BASEPRI value.
- Parameters:
-
+
+
+[in] basePri BASEPRI value to set
+
- Remarks:
-
+
- not for Cortex-M0 variants. +
- Cannot be set in user state. +
- Useful for changing the masking level or disabling the masking. +
- See also:
- +
+
+
+
+
+
+
+| void __set_CONTROL | +( | +uint32_t | +control | ) | ++ |
+
+The function sets the CONTROL register value using the instruction MSR.
+
+ The CONTROL register controls the stack used and the privilege level for software execution when the processor is in thread mode and, if implemented, indicates whether the FPU state is active. This register uses the following bits:
+
-
+
- CONTROL[2] [only Cortex-M4]
-
+
- =0 FPU not active +
- =1 FPU active
+
+
+
+ - CONTROL[1]
-
+
- Writeable only when the processor is in thread mode and privileged state (CONTROL[0]=0). +
- =0 In handler mode - MSP is selected. No alternate stack pointer possible for handler mode. +
- =0 In thread mode - Default stack pointer MSP is used. +
- =1 In thread mode - Alternate stack pointer PSP is used.
+
+
+
+ - CONTROL[0] [not writeable for Cortex-M0]
-
+
- Writeable only when the processor is in privileged state. +
- Can be used to switch the processor to user state (thread mode). +
- Once in user state, trigger an interrupt and change the state to privileged in the exception handler (the only way). +
- =0 In thread mode and privileged state. +
- =1 In thread mode and user state. +
+
- Parameters:
-
+
+
+[in] control CONTROL register value to set
+
- Remarks:
-
+
- The processor can be in user state or privileged state when running in thread mode. +
- Exception handlers always run in privileged state. +
- On reset, the processor is in thread mode with privileged access rights. +
- See also:
- +
+
+
+
+
+
+
+| void __set_FAULTMASK | +( | +uint32_t | +faultMask | ) | ++ |
+
+The function sets the Fault Mask register (FAULTMASK) value using the instruction MSR.
+
+ FAULTMASK prevents activation of all exceptions except for Non-Maskable Interrupt (NMI). FAULTMASK can be used to escalate a configurable fault handler (BusFault, usage fault, or memory management fault) to hard fault level without invoking a hard fault. This allows the fault handler to pretend to be the hard fault handler, whith the ability to:
-
+
- Mask BusFault by setting the BFHFNMIGN in the Configuration Control register. It can be used to test the bus system without causing a lockup. +
- Bypass the MPU, allowing accessing the MPU protected memory location without reprogramming the MPU to just carry out a few transfers for fixing faults. +
- Parameters:
-
+
+
+[in] faultMask FAULTMASK register value to set
+
- Remarks:
-
+
- not for Cortex-M0 variants. +
- Is cleared automatically upon exiting the exception handler, except when returning from the NMI handler. +
- When set, it changes the effective current priority level to -1, so that even the hard fault handler is blocked. +
- Can be used by fault handlers to change their priority to -1 to have access to some features for hard fault exceptions (see above). +
- When set, lockups can still be caused by incorrect or undefined instructions, or by using SVC in the wrong priority level. +
- See also:
- +
+
+
+
+
+
+
+| void __set_FPSCR | +( | +uint32_t | +fpscr | ) | ++ |
+
+The function sets the Floating-Point Status Control Register (FPSCR) value.
+
+ FPSCR provides all necessary User level control of the floating-point system.
+
-
+
- N (FPSC[31]) (Negative flag)
-
+
- =1 The instruction result has a negative value (when interpreted as signed integer). +
- =0 The instruction result has a positive value or equal zero.
+
+
+
+ - Z (FPSC[30]) (Zero flag)
-
+
- =1 The instruction result is zero. Or, after a compare instruction, when the two values are the same.
+
+
+
+ - =1 The instruction result is zero. Or, after a compare instruction, when the two values are the same.
- C (FPSC[29]) (Carry or borrow flag)
-
+
- =1 For unsigned additions, if an unsigned overflow occurred. +
- =inverse of borrow output status For unsigned subtract operations.
+
+
+
+ - V (FPSC[28]) (Overflow flag)
-
+
- =1 A signed overflow occurred (for signed additions or subtractions).
+
+
+
+ - =1 A signed overflow occurred (for signed additions or subtractions).
- AHP (FPSC[26]) (Alternative half-precision flag)
-
+
- =1 Alternative half-precision format selected. +
- =0 IEEE half-precision format selected.
+
+
+
+ - DN (FPSC[25]) (Default NaN mode control flag)
-
+
- =1 Any operation involving one or more NaNs returns the Default NaN. +
- =0 NaN operands propagate through to the output of a floating-point operation.
+
+
+
+ - FZ (FPSC[24]) (Flush-to-zero mode control flag)
-
+
- =1 Flush-to-zero mode enabled. +
- =0 Flush-to-zero mode disabled. Behavior of the floating-point system is fully compliant with the IEEE 754 standard.
+
+
+
+ - RMode (FPSC[23:22]) (Rounding Mode control flags)
-
+
- =0b00 Round to Nearest (RN) mode. +
- =0b01 Round towards Plus Infinity (RP) mode. +
- =0b10 Round towards Minus Infinity (RM) mode. +
- =0b11 Round towards Zero (RZ) mode. +
- The specified rounding mode is used by almost all floating-point instructions.
+
+
+
+ - IDC (FPSC[7]) (Input Denormal cumulative exception flags)
-
+
- See Cumulative exception bits (FPSC[4:0]).
+
+
+
+ - See Cumulative exception bits (FPSC[4:0]).
- IXC (FPSC[4]) (Inexact cumulative exception flag)
-
+
- =1 Exception occurred. +
- =0 Value has to be set explicitly. +
- Flag is not cleared automatically.
+
+
+
+ - UFC (FPSC[3]) (Underflow cumulative exception flag)
-
+
- =1 Exception occurred. +
- =0 Value has to be set explicitly. +
- Flag is not cleared automatically.
+
+
+
+ - OFC (FPSC[2]) (Overflow cumulative exception flag)
-
+
- =1 Exception occurred. +
- =0 Value has to be set explicitly. +
- Flag is not cleared automatically.
+
+
+
+ - DZC (FPSC[1]) (Division by Zero cumulative exception flag)
-
+
- =1 Exception occurred. +
- =0 Value has to be set explicitly. +
- Flag is not cleared automatically.
+
+
+
+ - IOC (FPSC[0]) (Invalid Operation cumulative exception flag)
-
+
- =1 Exception occurred. +
- =0 Value has to be set explicitly. +
- Flag is not cleared automatically. +
+
- Parameters:
-
+
+
+[in] fpscr FPSCR value to set
+
- Remarks:
-
+
- Only for Cortex-M4. +
- The variable __FPU_PRESENT has to be set to 1. +
- See also:
- +
+
+
+
+
+
+
+| void __set_MSP | +( | +uint32_t | +topOfMainStack | ) | ++ |
+
+The function sets the Main Status Pointer (MSP) value using the instruction MSR.
+
+ Physically two different stack pointers (SP) exist:
-
+
- The Main Stack Pointer (MSP) is the default stack pointer after reset. It is also used when running exception handlers (handler mode). +
- The Process Stack Pointer (PSP), which can be used only in thread mode. +
Register R13 banks the SP. The SP selection is determined by the bit[1] of the CONTROL register:
+-
+
- =0 MSP is the current stack pointer. This is also the default SP. The initial value is loaded from the first 32-bit word of the vector table from the program memory. +
- =1 PSP is the current stack pointer. The initial value is undefined. +
- Parameters:
-
+
+
+[in] topOfMainStack MSP value to set
+
- Remarks:
-
+
- Only one of the two SPs is visible at a time. +
- For many applications, the system can completely rely on the MSP. +
- The PSP is normally used in designs with an OS where the stack memory for OS Kernel must be separated from the application code. +
- See also:
- +
+
+
+
+
+
+
+| void __set_PRIMASK | +( | +uint32_t | +priMask | ) | ++ |
+
+The function sets the Priority Mask register (PRIMASK) value using the instruction MSR.
+
+ PRIMASK is a 1-bit-wide interrupt mask register. When set, it blocks all interrupts apart from the non-maskable interrupt (NMI) and the hard fault exception. The PRIMASK prevents activation of all exceptions with configurable priority.
- Parameters:
-
+
+
+[in] priMask Priority Mask -
+
- =0 no effect +
- =1 prevents the activation of all exceptions with configurable priority +
+
- Remarks:
-
+
- When set, PRIMASK effectively changes the current priority level to 0. This is the highest programmable level. +
- When set and a fault occurs, the hard fault handler will be executed. +
- Useful for temprorarily disabling all interrupts for timing critical tasks. +
- Does not have the ability to mask BusFault or bypass MPU. +
- See also:
- +
+
+
+
+
+
+| void __set_PSP | +( | +uint32_t | +topOfProcStack | ) | ++ |
+
+The function sets the Program Status Pointer (PSP) value using the instruction MSR.
+
+ Physically two different stack pointers (SP) exist:
-
+
- The Main Stack Pointer (MSP) is the default stack pointer after reset. It is also used when running exception handlers (handler mode). +
- The Process Stack Pointer (PSP), which can be used only in thread mode. +
Register R13 banks the SP. The SP selection is determined by the bit[1] of the CONTROL register:
+-
+
- =0 MSP is the current stack pointer. This is also the default SP. The initial value is loaded from the first 32-bit word of the vector table from the program memory. +
- =1 PSP is the current stack pointer. The initial value is undefined. +
- Parameters:
-
+
+
+[in] topOfProcStack PSP value to set
+
- Remarks:
-
+
- Only one of the two SPs is visible at a time. +
- For many applications, the system can completely rely on the MSP. +
- The PSP is normally used in designs with an OS where the stack memory for OS Kernel must be separated from the application code. +
- See also:
- +
+
+
+
+
+
+
+
+
+
+
+
+
+
+ |
+
+
+ CMSIS-CORE
+ Version 3.01
+
+ CMSIS-CORE support for Cortex-M processor-based devices
+ |
+
+
+
+
+
+-
+
- Main Page +
- Usage and Description +
- Reference +
-
+ + ++
+
+
+
+
+
+
+
+
+
+
+
+
+
diff --git a/Libraries/CMSIS/Documentation/Core/html/group___n_v_i_c__gr.html b/Libraries/CMSIS/Documentation/Core/html/group___n_v_i_c__gr.html
new file mode 100644
index 0000000..6d1c509
--- /dev/null
+++ b/Libraries/CMSIS/Documentation/Core/html/group___n_v_i_c__gr.html
@@ -0,0 +1,1033 @@
+
+
+
+
+
+
+
+
+
+
++Variables | |
| volatile int32_t | ITM_RxBuffer |
| external variable to receive characters | |
+Functions | |
| uint32_t | ITM_SendChar (uint32_t ch) |
| Transmits a character via channel 0. | |
| int32_t | ITM_ReceiveChar (void) |
| ITM Receive Character. | |
| int32_t | ITM_CheckChar (void) |
| ITM Check Character. | |
Description
+CMSIS provides additional debug functions to enlarge the Debug Access. Data can be transmitted via a certain global buffer variable towards the target system.
+The Cortex-M3 / Cortex-M4 incorporates the Instrumented Trace Macrocell (ITM) that provides together with the Serial Viewer Output (SVO) trace capabilities for the microcontroller system. The ITM has 32 communication channels; two ITM communication channels are used by CMSIS to output the following information:
+-
+
- ITM Channel 0: implements the ITM_SendChar function which can be used for printf-style output via the debug interface. +
-
+
- ITM Channel 31: is reserved for the RTOS kernel and can be used for kernel awareness debugging. +
- Remarks:
-
+
- ITM channels have 4 groups with 8 channels each, whereby each group can be configured for access rights in the Unprivileged level. +
- The ITM channel 0 can be enabled for the user task. +
- ITM channel 31 can be accessed only in Privileged mode from the RTOS kernel itself. The ITM channel 31 has been selected for the RTOS kernel because some kernels may use the Privileged level for program execution. +
+
+ITM Debug Support in uVision
+In a debug session, uVision uses the Debug (printf) Viewer window to display data.
+Direction: Microcontroller --> uVision:
+-
+
- Characters received via ITM communication channel 0 are written in a printf-style to the Debug (printf) Viewer window. +
Direction: uVision --> Microcontroller:
+-
+
- Check if ITM_RxBuffer variable is available (only performed once). +
- Read the character from the Debug (printf) Viewer window. +
- If ITM_RxBuffer is empty, write character to ITM_RxBuffer. +
- Note:
- The current solution does not use a buffer mechanism for transmitting the characters.
+
+Example:
+Example for the usage of the ITM Channel 31 for RTOS Kernels:
+// check if debugger connected and ITM channel enabled for tracing +if ((CoreDebug->DEMCR & CoreDebug_DEMCR_TRCENA) && + (ITM->TCR & ITM_TCR_ITMENA) && + (ITM->TER & (1UL >> 31))) { + + // transmit trace data + while (ITM->PORT31_U32 == 0); + ITM->PORT[31].u8 = task_id; // id of next task + while (ITM->PORT[31].u32 == 0); + ITM->PORT[31].u32 = task_status; // status information +} +
Variable Documentation
+ +
+
+
+
+
+
+| volatile int32_t ITM_RxBuffer | +
+
+
+Function Documentation
+ +
+
+
+
+
+
+
+| int32_t ITM_CheckChar | +( | +void | +) | ++ |
+
+This function reads the external variable ITM_RxBuffer and checks whether a character is available or not.
+- Returns:
-
+
- =0 - No character available +
- =1 - Character available +
+
+
+
+
+
+
+| int32_t ITM_ReceiveChar | +( | +void | +) | ++ |
+
+This function inputs a character via the external variable ITM_RxBuffer. It returns when no debugger is connected that has booked the output. It is blocking when a debugger is connected, but the previously sent character has not been transmitted.
+- Returns:
-
+
- Received character +
- =1 - No character received +
+
+
+
+
+
+| uint32_t ITM_SendChar | +( | +uint32_t | +ch | ) | ++ |
+
+This function transmits a character via the ITM channel 0. It returns when no debugger is connected that has booked the output. It is blocking when a debugger is connected, but the previously sent character has not been transmitted.
+- Parameters:
-
+
+
+[in] ch Character to transmit
+
- Returns:
- Character to transmit
+
+
+
+
+
+
+
+
+
+
+
+
+
+ |
+
+
+ CMSIS-CORE
+ Version 3.01
+
+ CMSIS-CORE support for Cortex-M processor-based devices
+ |
+
+
+
+
+
+-
+
- Main Page +
- Usage and Description +
- Reference +
-
+ + ++
+
+
+
+
+
+
+
+
+
+
+
+
diff --git a/Libraries/CMSIS/Documentation/Core/html/group___sys_tick__gr.html b/Libraries/CMSIS/Documentation/Core/html/group___sys_tick__gr.html
new file mode 100644
index 0000000..0c55ae9
--- /dev/null
+++ b/Libraries/CMSIS/Documentation/Core/html/group___sys_tick__gr.html
@@ -0,0 +1,196 @@
+
+
+
+
+
+
+
+
+
+Interrupts and Exceptions (NVIC)
+
+
+
+
+
+
+Describes programming of interrupts and exception functions. +More...
++Enumerations | |
| enum | IRQn_Type { + NonMaskableInt_IRQn = -14, + + HardFault_IRQn = -13, + + MemoryManagement_IRQn = -12, + + BusFault_IRQn = -11, + + UsageFault_IRQn = -10, + + SVCall_IRQn = -5, + + DebugMonitor_IRQn = -4, + + PendSV_IRQn = -2, + + SysTick_IRQn = -1, + + WWDG_STM_IRQn = 0, + + PVD_STM_IRQn = 1 + + } |
| Definition of IRQn numbers. More... | |
+Functions | |
| void | NVIC_SetPriorityGrouping (uint32_t PriorityGroup) |
| Set priority grouping [not for Cortex-M0 variants]. | |
| uint32_t | NVIC_GetPriorityGrouping (void) |
| Read the priority grouping [not for Cortex-M0 variants]. | |
| void | NVIC_EnableIRQ (IRQn_Type IRQn) |
| Enable an external interrupt. | |
| void | NVIC_DisableIRQ (IRQn_Type IRQn) |
| Disable an external interrupt. | |
| uint32_t | NVIC_GetPendingIRQ (IRQn_Type IRQn) |
| Get the pending interrupt. | |
| void | NVIC_SetPendingIRQ (IRQn_Type IRQn) |
| Set an interrupt to pending. | |
| void | NVIC_ClearPendingIRQ (IRQn_Type IRQn) |
| Clear an interrupt from pending. | |
| uint32_t | NVIC_GetActive (IRQn_Type IRQn) |
| Get the interrupt active status [not for Cortex-M0 variants]. | |
| void | NVIC_SetPriority (IRQn_Type IRQn, uint32_t priority) |
| Set the priority for an interrupt. | |
| uint32_t | NVIC_GetPriority (IRQn_Type IRQn) |
| Get the priority of an interrupt. | |
| uint32_t | NVIC_EncodePriority (uint32_t PriorityGroup, uint32_t PreemptPriority, uint32_t SubPriority) |
| Encodes Priority [not for Cortex-M0 variants]. | |
| void | NVIC_DecodePriority (uint32_t Priority, uint32_t PriorityGroup, uint32_t *pPreemptPriority, uint32_t *pSubPriority) |
| Decode the interrupt priority [not for Cortex-M0 variants]. | |
| void | NVIC_SystemReset (void) |
| Reset the system. | |
Description
+ARM provides a template file startup_device for each supported compiler. The file must be adapted by the silicon vendor to include interrupt vectors for all device-specific interrupt handlers. Each interrupt handler is defined as a weak function to an dummy handler. These interrupt handlers can be used directly in application software without being adapted by the programmer.
+The table below describes the core exception names and their availability in various Cortex-M cores.
+| Core Exception Name | IRQn Value | M0 | M0p | M3 | M4 | SC000 | SC300 | Description |
|---|---|---|---|---|---|---|---|---|
| NonMaskableInt_IRQn | -14 |
+
+ 
+ |
+
+
+ |
+
+
+ |
+
+
+ |
+
+
+ |
+
+
+ | Non Maskable Interrupt |
| HardFault_IRQn | -13 |
+
+
+ |
+
+
+ |
+
+
+ |
+
+
+ |
+
+
+ |
+
+
+ | Hard Fault Interrupt |
| MemoryManagement_IRQn | -12 |
+
+
+ |
+
+
+ |
+
+
+ | Memory Management Interrupt | |||
| BusFault_IRQn | -11 |
+
+
+ |
+
+
+ |
+
+
+ | Bus Fault Interrupt | |||
| UsageFault_IRQn | -10 |
+
+
+ |
+
+
+ |
+
+
+ | Usage Fault Interrupt | |||
| SVCall_IRQn | -5 |
+
+
+ |
+
+
+ |
+
+
+ |
+
+
+ |
+
+
+ |
+
+
+ | SV Call Interrupt |
| DebugMonitor_IRQn | -4 |
+
+
+ |
+
+
+ |
+
+
+ | Debug Monitor Interrupt | |||
| PendSV_IRQn | -2 |
+
+
+ |
+
+
+ |
+
+
+ |
+
+
+ |
+
+
+ |
+
+
+ | Pend SV Interrupt |
| SysTick_IRQn | -1 |
+
+
+ |
+
+
+ |
+
+
+ |
+
+
+ |
+
+
+ |
+
+
+ | System Tick Interrupt |
+For Cortex-M0 and Cortex-M0+
+The following exception names are fixed and define the start of the vector table for Cortex-M0 variants:
+__Vectors DCD __initial_sp ; Top of Stack + DCD Reset_Handler ; Reset Handler + DCD NMI_Handler ; NMI Handler + DCD HardFault_Handler ; Hard Fault Handler + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD SVC_Handler ; SVCall Handler + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD PendSV_Handler ; PendSV Handler + DCD SysTick_Handler ; SysTick Handler +
+For Cortex-M3
+The following exception names are fixed and define the start of the vector table for a Cortex-M3:
+__Vectors DCD __initial_sp ; Top of Stack + DCD Reset_Handler ; Reset Handler + DCD NMI_Handler ; NMI Handler + DCD HardFault_Handler ; Hard Fault Handler + DCD MemManage_Handler ; MPU Fault Handler + DCD BusFault_Handler ; Bus Fault Handler + DCD UsageFault_Handler ; Usage Fault Handler + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD SVC_Handler ; SVCall Handler + DCD DebugMon_Handler ; Debug Monitor Handler + DCD 0 ; Reserved + DCD PendSV_Handler ; PendSV Handler + DCD SysTick_Handler ; SysTick Handler +
+Example
+The following is an examples for device-specific interrupts:
+; External Interrupts + DCD WWDG_IRQHandler ; Window Watchdog + DCD PVD_IRQHandler ; PVD through EXTI Line detect + DCD TAMPER_IRQHandler ; Tamper +
Device-specific interrupts must have a dummy function that can be overwritten in user code. Below is an example for this dummy function.
+Default_Handler PROC + EXPORT WWDG_IRQHandler [WEAK] + EXPORT PVD_IRQHandler [WEAK] + EXPORT TAMPER_IRQHandler [WEAK] + : + : + WWDG_IRQHandler + PVD_IRQHandler + TAMPER_IRQHandler + : + : + B . + ENDP +
The user application may simply define an interrupt handler function by using the handler name as shown below.
+void WWDG_IRQHandler(void) +{ + ... +} +
+Code Example 1
+The code below shows the usage of the CMSIS NVIC functions NVIC_SetPriorityGrouping(), NVIC_GetPriorityGrouping(), NVIC_SetPriority(), NVIC_GetPriority(), NVIC_EncodePriority(), and NVIC_DecodePriority() with an LPC1700.
+#include "LPC17xx.h" + +uint32_t priorityGroup; /* Variables to store priority group and priority */ +uint32_t priority; +uint32_t preemptPriority; +uint32_t subPriority; + + +int main (void) { + + NVIC_SetPriorityGrouping(5); /* Set priority group to 5: + Bit[7..6] preempt priority Bits, + Bit[5..3] subpriority Bits + (valid for five priority bits) */ + + priorityGroup = NVIC_GetPriorityGrouping(); /* Get used priority grouping */ + + priority = NVIC_EncodePriority(priorityGroup, 1, 6); /* Encode priority with 6 for subpriority and 1 for preempt priority + Note: priority depends on the used priority grouping */ + + NVIC_SetPriority(UART0_IRQn, priority); /* Set new priority */ + + priority = NVIC_GetPriority(UART0_IRQn); /* Retrieve priority again */ + + NVIC_DecodePriority(priority, priorityGroup, &preemptPriority, &subPriority); + + while(1); +} +
+Code Example 2
+The code below shows the usage of the CMSIS NVIC functions NVIC_EnableIRQ(), NVIC_GetActive() with an LPC1700.
+#include "LPC17xx.h" + +uint32_t active; /* Variable to store interrupt active state */ + + +void TIMER0_IRQHandler(void) { /* Timer 0 interrupt handler */ + + if (LPC_TIM0->IR & (1 << 0)) { /* Check if interrupt for match channel 0 occured */ + LPC_TIM0->IR |= (1 << 0); /* Acknowledge interrupt for match channel 0 occured */ + } + active = NVIC_GetActive(TIMER0_IRQn); /* Get interrupt active state of timer 0 */ +} + + +int main (void) { + /* Set match channel register MR0 to 1 millisecond */ + LPC_TIM0->MR0 = (((SystemCoreClock / 1000) / 4) - 1); /* 1 ms? */ + + LPC_TIM0->MCR = (3 << 0); /* Enable interrupt and reset for match channel MR0 */ + + NVIC_EnableIRQ(TIMER0_IRQn); /* Enable NVIC interrupt for timer 0 */ + + LPC_TIM0->TCR = (1 << 0); /* Enable timer 0 */ + + while(1); +} +
Enumeration Type Documentation
+ +
+
+
+
+
+
+| enum IRQn_Type | +
+
+The core exception enumeration names for IRQn values are defined in the file device.h.
+Negative IRQn values represent processor core exceptions (internal interrupts). Positive IRQn values represent device-specific exceptions (external interrupts). The first device-specific interrupt has the IRQn value 0.
+The table below describes the core exception names and their availability in various Cortex-M cores.
+- Enumerator:
- +
Function Documentation
+ +
+
+
+
+
+
+
+| void NVIC_ClearPendingIRQ | +( | +IRQn_Type | +IRQn | ) | ++ |
+
+This function removes the pending state of the specified interrupt IRQn. IRQn cannot be a negative number.
+- Parameters:
-
+
+
+[in] IRQn Interrupt number
+
- Remarks:
-
+
- The registers that control the status of interrupts are called SETPEND and CLRPEND. +
- An interrupt can have the status pending though it is not active. +
- See also:
- +
+
+
+
+
+
+
+| void NVIC_DecodePriority | +( | +uint32_t | +Priority, | +
| + | + | uint32_t | +PriorityGroup, | +
| + | + | uint32_t * | +pPreemptPriority, | +
| + | + | uint32_t * | +pSubPriority | +
| + | ) | ++ |
+
+This function decodes an interrupt priority value with the priority group PriorityGroup to preemptive priority value pPreemptPriority and subpriority value pSubPriority. In case of a conflict between priority grouping and available priority bits (__NVIC_PRIO_BITS) the smallest possible priority group is set.
+- Parameters:
-
+
+
+[in] Priority Priority [in] PriorityGroup Priority group [out] *pPreemptPriority Preemptive priority value (starting from 0) [out] *pSubPriority Subpriority value (starting from 0)
+
- Remarks:
-
+
- not for Cortex-M0 variants. +
- See also:
- +
+
+
+
+
+
+
+| void NVIC_DisableIRQ | +( | +IRQn_Type | +IRQn | ) | ++ |
+
+This function disables the specified device-specific interrupt IRQn. IRQn cannot be a negative value.
+- Parameters:
-
+
+
+[in] IRQn Number of the external interrupt to disable
+
- Remarks:
-
+
- The registers that control the enabling and disabling of interrupts are called SETENA and CLRENA. +
- See also:
- +
+
+
+
+
+
+
+| void NVIC_EnableIRQ | +( | +IRQn_Type | +IRQn | ) | ++ |
+
+This function enables the specified device-specific interrupt IRQn. IRQn cannot be a negative value.
+- Parameters:
-
+
+
+[in] IRQn Interrupt number
+
- Remarks:
-
+
- The registers that control the enabling and disabling of interrupts are called SETENA and CLRENA. +
- The number of supported interrupts depends on the implementation of the chip designer and can be read form the Interrupt Controller Type Register (ICTR) in granularities of 32:
+ ICTR[4:0]-
+
- =0 - 32 interrupts supported +
- =1 - 64 interrupts supported +
- ... +
+
- See also:
- +
+
+
+
+
+
+
+| uint32_t NVIC_EncodePriority | +( | +uint32_t | +PriorityGroup, | +
| + | + | uint32_t | +PreemptPriority, | +
| + | + | uint32_t | +SubPriority | +
| + | ) | ++ |
+
+This function encodes the priority for an interrupt with the priority group PriorityGroup, preemptive priority value PreemptPriority, and subpriority value SubPriority. In case of a conflict between priority grouping and available priority bits (__NVIC_PRIO_BITS) the smallest possible priority group is set.
+- Parameters:
-
+
+
+[in] PriorityGroup Priority group [in] PreemptPriority Preemptive priority value (starting from 0) [in] SubPriority Subpriority value (starting from 0)
+
- Returns:
- Encoded priority for the interrupt
- Remarks:
-
+
- not for Cortex-M0 variants. +
- See also:
- +
+
+
+
+
+
+
+| uint32_t NVIC_GetActive | +( | +IRQn_Type | +IRQn | ) | ++ |
+
+This function reads the Interrupt Active Register (NVIC_IABR0-NVIC_IABR7) in NVIC and returns the active bit of the interrupt IRQn.
+- Parameters:
-
+
+
+[in] IRQn Interrupt number
+
- Returns:
-
+
- =0 Interrupt is not active +
- =1 Interrupt is active, or active and pending +
- Remarks:
-
+
- not for Cortex-M0 variants. +
- Each external interrupt has an active status bit. When the processor starts the interrupt handler the bit is set to 1 and cleared when the interrupt return is executed. +
- When an ISR is preempted and the processor executes anohter interrupt handler, the previous interrupt is still defined as active. +
- See also:
- +
+
+
+
+
+
+
+| uint32_t NVIC_GetPendingIRQ | +( | +IRQn_Type | +IRQn | ) | ++ |
+
+This function returns the pending status of the specified interrupt IRQn.
+- Parameters:
-
+
+
+[in] IRQn Interrupt number
+
- Returns:
-
+
- =0 Interrupt is not pending +
- =1 Interrupt is pending +
- Remarks:
-
+
- The registers that control the status of interrupts are called SETPEND and CLRPEND. +
- See also:
- +
+
+
+
+
+
+
+| uint32_t NVIC_GetPriority | +( | +IRQn_Type | +IRQn | ) | ++ |
+
+This function reads the priority for the specified interrupt IRQn. IRQn can can specify any device-specific (external) interrupt, or core (internal) interrupt.
+The returned priority value is automatically aligned to the implemented priority bits of the microcontroller.
+- Parameters:
-
+
+
+[in] IRQn Interrupt number
+
- Returns:
- Interrupt priority
- Remarks:
-
+
- Each external interrupt has an associated priority-level register. +
- Unimplemented bits are read as zero. +
- See also:
- +
+
+
+
+
+
+
+| uint32_t NVIC_GetPriorityGrouping | +( | +void | +) | ++ |
+
+This functuion returns the priority grouping (flag PRIGROUP in AIRCR[10:8]).
+- Returns:
- Priority grouping field
- Remarks:
-
+
- not for Cortex-M0 variants. +
- By default, priority group setting is zero. +
- See also:
- +
+
+
+
+
+
+
+| void NVIC_SetPendingIRQ | +( | +IRQn_Type | +IRQn | ) | ++ |
+
+This function sets the pending bit for the specified interrupt IRQn. IRQn cannot be a negative value.
+- Parameters:
-
+
+
+[in] IRQn Interrupt number
+
- Remarks:
-
+
- The registers that control the status of interrupts are called SETPEND and CLRPEND. +
- See also:
- +
+
+
+
+
+
+
+| void NVIC_SetPriority | +( | +IRQn_Type | +IRQn, | +
| + | + | uint32_t | +priority | +
| + | ) | ++ |
+
+Sets the priority for the interrupt specified by IRQn.IRQn can can specify any device-specific (external) interrupt, or core (internal) interrupt. The priority specifies the interrupt priority value, whereby lower values indicate a higher priority. The default priority is 0 for every interrupt. This is the highest possible priority.
+The priority cannot be set for every core interrupt. HardFault and NMI have a fixed (negative) priority that is higher than any configurable exception or interrupt.
+- Parameters:
-
+
+
+[in] IRQn Interrupt Number [in] priority Priority to set
+
- Remarks:
-
+
- The number of priority levels is configurable and depends on the implementation of the chip designer. To determine the number of bits implemented for interrupt priority-level registers, write 0xFF to one of the priority-level register, then read back the value. For example, if the minimum number of 3 bits have been implemented, the read-back value is 0xE0. +
- Writes to unimplemented bits are ignored. +
- For Cortex-M0:
-
+
- Dynamic switching of interrupt priority levels is not supported. The priority level of an interrupt should not be changed after it has been enabled. +
- Supports 0 to 192 priority levels. +
- Priority-level registers are 2 bit wide, occupying the two MSBs. Each Interrupt Priority Level Register is 1-byte wide. +
+ - For Cortex-M3 and Cortex-M4:
-
+
- Dynamic switching of interrupt priority levels is supported. +
- Supports 0 to 255 priority levels. +
- Priority-level registers have a maximum width of 8 bits and a minumum of 3 bits. Each register can be further devided into preempt priority level and subpriority level. +
+
- See also:
- +
+
+
+
+
+
+
+| void NVIC_SetPriorityGrouping | +( | +uint32_t | +PriorityGroup | ) | ++ |
+
+The function sets the priority grouping PriorityGroup using the required unlock sequence. PriorityGroup is assigned to the field PRIGROUP (register AIRCR[10:8]). This field determines the split of group priority from subpriority. Only values from 0..7 are used. In case of a conflict between priority grouping and available priority bits (__NVIC_PRIO_BITS), the smallest possible priority group is set.
+- Parameters:
-
+
+
+[in] PriorityGroup Priority group
+
- Remarks:
-
+
- not for Cortex-M0 variants. +
- By default, priority group setting is zero. +
- See also:
- +
+
+
+
+
+
+| void NVIC_SystemReset | +( | +void | +) | ++ |
+
+This function requests a system reset by setting the SYSRESETREQ flag in the AIRCR register.
+- Remarks:
-
+
- In most microcontroller designs, setting the SYSRESETREQ flag resets the processor and most parts of the system, but should not affect the debug system. +
- See also:
- +
+
+
+
+
+
+
+
+
+
+
+
+
+
+ |
+
+
+ CMSIS-CORE
+ Version 3.01
+
+ CMSIS-CORE support for Cortex-M processor-based devices
+ |
+
+
+
+
+
+-
+
- Main Page +
- Usage and Description +
- Reference +
-
+ + ++
+
+
+
+
+
+
+
+
+
+
+
+
diff --git a/Libraries/CMSIS/Documentation/Core/html/group__intrinsic___c_p_u__gr.html b/Libraries/CMSIS/Documentation/Core/html/group__intrinsic___c_p_u__gr.html
new file mode 100644
index 0000000..9935034
--- /dev/null
+++ b/Libraries/CMSIS/Documentation/Core/html/group__intrinsic___c_p_u__gr.html
@@ -0,0 +1,766 @@
+
+
+
+
+
+
+
+
+
+Systick Timer (SYSTICK)
+
+
+
+
+Initialize and start the SysTick timer. +More...
++Functions | |
| uint32_t | SysTick_Config (uint32_t ticks) |
| System Tick Timer Configuration. | |
Description
+The System Tick Time (SysTick) generates interrupt requests on a regular basis. This allows an OS to carry out context switching to support multiple tasking. For applications that do not require an OS, the SysTick can be used for time keeping, time measurement, or as an interrupt source for tasks that need to be executed regularly.
++Code Example
+The code below shows the usage of the function SysTick_Config() with an LPC1700.
+#include "LPC17xx.h" + +uint32_t msTicks = 0; /* Variable to store millisecond ticks */ + + +void SysTick_Handler(void) { /* SysTick interrupt Handler. + msTicks++; See startup file startup_LPC17xx.s for SysTick vector */ +} + + +int main (void) { + uint32_t returnCode; + + returnCode = SysTick_Config(SystemCoreClock / 1000); /* Configure SysTick to generate an interrupt every millisecond */ + + if (returnCode != 0) { /* Check return code for errors */ + // Error Handling + } + + while(1); +} +
Function Documentation
+ +
+
+
+
+
+
+| uint32_t SysTick_Config | +( | +uint32_t | +ticks | ) | ++ |
+
+Initialises and starts the System Tick Timer and its interrupt. After this call, the SysTick timer creates interrupts with the specified time interval. Counter is in free running mode to generate periodical interrupts.
+- Parameters:
-
+
+
+[in] ticks Number of ticks between two interrupts
+
- Returns:
- 0 - success +
- +1 - failure
- Note:
- When #define __Vendor_SysTickConfig is set to 1, the standard function SysTick_Config is excluded. In this case, the file device.h must contain a vendor specific implementation of this function.
+
+
+
+
+
+
+
+
+
+
+
+
+
+ |
+
+
+ CMSIS-CORE
+ Version 3.01
+
+ CMSIS-CORE support for Cortex-M processor-based devices
+ |
+
+
+
+
+
+-
+
- Main Page +
- Usage and Description +
- Reference +
-
+ + ++
+
+
+
+
+
+
+
+
+
+
+
+
diff --git a/Libraries/CMSIS/Documentation/Core/html/group__intrinsic___s_i_m_d__gr.html b/Libraries/CMSIS/Documentation/Core/html/group__intrinsic___s_i_m_d__gr.html
new file mode 100644
index 0000000..dc102cd
--- /dev/null
+++ b/Libraries/CMSIS/Documentation/Core/html/group__intrinsic___s_i_m_d__gr.html
@@ -0,0 +1,3079 @@
+
+
+
+
+
+
+
+
+
+Intrinsic Functions for CPU Instructions
+
+
+
++Functions | |
| void | __NOP (void) |
| No Operation. | |
| void | __WFI (void) |
| Wait For Interrupt. | |
| void | __WFE (void) |
| Wait For Event. | |
| void | __SEV (void) |
| Send Event. | |
| void | __ISB (void) |
| Instruction Synchronization Barrier. | |
| void | __DSB (void) |
| Data Synchronization Barrier. | |
| void | __DMB (void) |
| Data Memory Barrier. | |
| uint32_t | __REV (uint32_t value) |
| Reverse byte order (32 bit) | |
| uint32_t | __REV16 (uint32_t value) |
| Reverse byte order (16 bit) | |
| int32_t | __REVSH (int32_t value) |
| Reverse byte order in signed short value. | |
| uint32_t | __RBIT (uint32_t value) |
| Reverse bit order of value [not for Cortex-M0 variants]. | |
| uint32_t | __ROR (uint32_t value, uint32_t shift) |
| Rotate a value right by a number of bits. | |
| uint8_t | __LDREXB (volatile uint8_t *addr) |
| LDR Exclusive (8 bit) [not for Cortex-M0 variants]. | |
| uint16_t | __LDREXH (volatile uint16_t *addr) |
| LDR Exclusive (16 bit) [not for Cortex-M0 variants]. | |
| uint32_t | __LDREXW (volatile uint32_t *addr) |
| LDR Exclusive (32 bit) [not for Cortex-M0 variants]. | |
| uint32_t | __STREXB (uint8_t value, volatile uint8_t *addr) |
| STR Exclusive (8 bit) [not for Cortex-M0 variants]. | |
| uint32_t | __STREXH (uint16_t value, volatile uint16_t *addr) |
| STR Exclusive (16 bit) [not for Cortex-M0 variants]. | |
| uint32_t | __STREXW (uint32_t value, volatile uint32_t *addr) |
| STR Exclusive (32 bit) [not for Cortex-M0 variants]. | |
| void | __CLREX (void) |
| Remove the exclusive lock [not for Cortex-M0 variants]. | |
| uint32_t | __SSAT (unint32_t value, uint32_t sat) |
| Signed Saturate [not for Cortex-M0 variants]. | |
| uint32_t | __USAT (uint32_t value, uint32_t sat) |
| Unsigned Saturate [not for Cortex-M0 variants]. | |
| uint8_t | __CLZ (uint32_t value) |
| Count leading zeros [not for Cortex-M0 variants]. | |
Description
+The following functions generate specific Cortex-M instructions that cannot be directly accessed by the C/C++ Compiler.
+Function Documentation
+ +
+
+
+
+
+
+
+| void __CLREX | +( | +void | +) | ++ |
+
+This function removes the exclusive lock which is created by LDREX [not for Cortex-M0 variants].
+ +
+
+
+
+
+
+
+| uint8_t __CLZ | +( | +uint32_t | +value | ) | ++ |
+
+This function counts the number of leading zeros of a data value [not for Cortex-M0 variants].
+- Parameters:
-
+
+
+[in] value Value to count the leading zeros
+
- Returns:
- number of leading zeros in value
+
+
+
+
+
+
+| void __DMB | +( | +void | +) | ++ |
+
+This function ensures the apparent order of the explicit memory operations before and after the instruction, without ensuring their completion.
+ +
+
+
+
+
+
+
+| void __DSB | +( | +void | +) | ++ |
+
+This function acts as a special kind of Data Memory Barrier. It completes when all explicit memory accesses before this instruction complete.
+ +
+
+
+
+
+
+
+| void __ISB | +( | +void | +) | ++ |
+
+Instruction Synchronization Barrier flushes the pipeline in the processor, so that all instructions following the ISB are fetched from cache or memory, after the instruction has been completed.
+ +
+
+
+
+
+
+
+| uint8_t __LDREXB | +( | +volatile uint8_t * | +addr | ) | ++ |
+
+This function performs a exclusive LDR command for 8 bit value [not for Cortex-M0 variants].
+- Parameters:
-
+
+
+[in] *addr Pointer to data
+
- Returns:
- value of type uint8_t at (*addr)
+
+
+
+
+
+
+| uint16_t __LDREXH | +( | +volatile uint16_t * | +addr | ) | ++ |
+
+This function performs a exclusive LDR command for 16 bit values [not for Cortex-M0 variants].
+- Parameters:
-
+
+
+[in] *addr Pointer to data
+
- Returns:
- value of type uint16_t at (*addr)
+
+
+
+
+
+
+| uint32_t __LDREXW | +( | +volatile uint32_t * | +addr | ) | ++ |
+
+This function performs a exclusive LDR command for 32 bit values [not for Cortex-M0 variants].
+- Parameters:
-
+
+
+[in] *addr Pointer to data
+
- Returns:
- value of type uint32_t at (*addr)
+
+
+
+
+
+
+| void __NOP | +( | +void | +) | ++ |
+
+This function does nothing. This instruction can be used for code alignment purposes.
+ +
+
+
+
+
+
+
+| uint32_t __RBIT | +( | +uint32_t | +value | ) | ++ |
+
+This function reverses the bit order of the given value [not for Cortex-M0 variants].
+- Parameters:
-
+
+
+[in] value Value to reverse
+
- Returns:
- Reversed value
+
+
+
+
+
+
+| uint32_t __REV | +( | +uint32_t | +value | ) | ++ |
+
+This function reverses the byte order in integer value.
+- Parameters:
-
+
+
+[in] value Value to reverse
+
- Returns:
- Reversed value
+
+
+
+
+
+
+| uint32_t __REV16 | +( | +uint32_t | +value | ) | ++ |
+
+This function reverses the byte order in two unsigned short values.
+- Parameters:
-
+
+
+[in] value Value to reverse
+
- Returns:
- Reversed value
+
+
+
+
+
+
+| int32_t __REVSH | +( | +int32_t | +value | ) | ++ |
+
+This function reverses the byte order in a signed short value with sign extension to integer.
+- Parameters:
-
+
+
+[in] value Value to reverse
+
- Returns:
- Reversed value
+
+
+
+
+
+
+| uint32_t __ROR | +( | +uint32_t | +value, | +
| + | + | uint32_t | +shift | +
| + | ) | ++ |
+
+This function rotates a value right by a specified number of bits.
+- Parameters:
-
+
+
+[in] value Value to be shifted right [in] shift Number of bits in the range [1..31]
+
- Returns:
- Rotated value
+
+
+
+
+
+
+| void __SEV | +( | +void | +) | ++ |
+
+Send Event is a hint instruction. It causes an event to be signaled to the CPU.
+ +
+
+
+
+
+
+
+| uint32_t __SSAT | +( | +unint32_t | +value, | +
| + | + | uint32_t | +sat | +
| + | ) | ++ |
+
+This function saturates a signed value [not for Cortex-M0 variants].
+- Parameters:
-
+
+
+[in] value Value to be saturated [in] sat Bit position to saturate to [1..32]
+
- Returns:
- Saturated value
+
+
+
+
+
+
+| uint32_t __STREXB | +( | +uint8_t | +value, | +
| + | + | volatile uint8_t * | +addr | +
| + | ) | ++ |
+
+This function performs a exclusive STR command for 8 bit values [not for Cortex-M0 variants].
+- Parameters:
-
+
+
+[in] value Value to store [in] *addr Pointer to location
+
- Returns:
- 0 Function succeeded +
- +1 Function failed
+
+
+
+
+
+
+| uint32_t __STREXH | +( | +uint16_t | +value, | +
| + | + | volatile uint16_t * | +addr | +
| + | ) | ++ |
+
+This function performs a exclusive STR command for 16 bit values [not for Cortex-M0 variants].
+- Parameters:
-
+
+
+[in] value Value to store [in] *addr Pointer to location
+
- Returns:
- 0 Function succeeded +
- +1 Function failed
+
+
+
+
+
+
+| uint32_t __STREXW | +( | +uint32_t | +value, | +
| + | + | volatile uint32_t * | +addr | +
| + | ) | ++ |
+
+This function performs a exclusive STR command for 32 bit values [not for Cortex-M0 variants].
+- Parameters:
-
+
+
+[in] value Value to store [in] *addr Pointer to location
+
- Returns:
- 0 Function succeeded +
- +1 Function failed
+
+
+
+
+
+
+| uint32_t __USAT | +( | +uint32_t | +value, | +
| + | + | uint32_t | +sat | +
| + | ) | ++ |
+
+This function saturates an unsigned value [not for Cortex-M0 variants].
+- Parameters:
-
+
+
+[in] value Value to be saturated [in] sat Bit position to saturate to [0..31]
+
- Returns:
- Saturated value
+
+
+
+
+
+
+| void __WFE | +( | +void | +) | ++ |
+
+Wait For Event is a hint instruction that permits the processor to enter a low-power state until an events occurs:
+-
+
- If the event register is 0, then WFE suspends execution until one of the following events occurs:
-
+
- An exception, unless masked by the exception mask registers or the current priority level. +
- An exception enters the Pending state, if SEVONPEND in the System Control Register is set. +
- A Debug Entry request, if Debug is enabled. +
- An event signaled by a peripheral or another processor in a multiprocessor system using the SEV instruction. +
+
-
+
- If the event register is 1, then WFE clears it to 0 and returns immediately. +
+
+
+
+
+
+| void __WFI | +( | +void | +) | ++ |
+
+WFI is a hint instruction that suspends execution until one of the following events occurs:
+-
+
- A non-masked interrupt occurs and is taken. +
- An interrupt masked by PRIMASK becomes pending. +
- A Debug Entry request. +
+
+
+
+
+
+
+
+
+
+
+
+
+
+ |
+
+
+ CMSIS-CORE
+ Version 3.01
+
+ CMSIS-CORE support for Cortex-M processor-based devices
+ |
+
+
+
+
+
+-
+
- Main Page +
- Usage and Description +
- Reference +
-
+ + ++
+
+
+
+
+
+
+
+
+
+
+
+
diff --git a/Libraries/CMSIS/Documentation/Core/html/group__peripheral__gr.html b/Libraries/CMSIS/Documentation/Core/html/group__peripheral__gr.html
new file mode 100644
index 0000000..ffde56f
--- /dev/null
+++ b/Libraries/CMSIS/Documentation/Core/html/group__peripheral__gr.html
@@ -0,0 +1,231 @@
+
+
+
+
+
+
+
+
+
+Intrinsic Functions for SIMD Instructions [only Cortex-M4]
+
+
+
+
+Access to dedicated SIMD instructions. +More...
++Functions | |
| uint32_t | __SADD8 (uint32_t val1, uint32_t val2) |
| GE setting quad 8-bit signed addition. | |
| uint32_t | __QADD8 (uint32_t val1, uint32_t val2) |
| Q setting quad 8-bit saturating addition. | |
| uint32_t | __SHADD8 (uint32_t val1, uint32_t val2) |
| Quad 8-bit signed addition with halved results. | |
| uint32_t | __UADD8 (uint32_t val1, uint32_t val2) |
| GE setting quad 8-bit unsigned addition. | |
| uint32_t | __UQADD8 (uint32_t val1, uint32_t val2) |
| Quad 8-bit unsigned saturating addition. | |
| uint32_t | __UHADD8 (uint32_t val1, uint32_t val2) |
| Quad 8-bit unsigned addition with halved results. | |
| uint32_t | __SSUB8 (uint32_t val1, uint32_t val2) |
| GE setting quad 8-bit signed subtraction. | |
| uint32_t | __QSUB8 (uint32_t val1, uint32_t val2) |
| Q setting quad 8-bit saturating subtract. | |
| uint32_t | __SHSUB8 (uint32_t val1, uint32_t val2) |
| Quad 8-bit signed subtraction with halved results. | |
| uint32_t | __USUB8 (uint32_t val1, uint32_t val2) |
| GE setting quad 8-bit unsigned subtract. | |
| uint32_t | __UQSUB8 (uint32_t val1, uint32_t val2) |
| Quad 8-bit unsigned saturating subtraction. | |
| uint32_t | __UHSUB8 (uint32_t val1, uint32_t val2) |
| Quad 8-bit unsigned subtraction with halved results. | |
| uint32_t | __SADD16 (uint32_t val1, uint32_t val2) |
| GE setting dual 16-bit signed addition. | |
| uint32_t | __QADD16 (uint32_t val1, uint32_t val2) |
| Q setting dual 16-bit saturating addition. | |
| uint32_t | __SHADD16 (uint32_t val1, uint32_t val2) |
| Dual 16-bit signed addition with halved results. | |
| uint32_t | __UADD16 (uint32_t val1, uint32_t val2) |
| GE setting dual 16-bit unsigned addition. | |
| uint32_t | __UQADD16 (uint32_t val1, uint32_t val2) |
| Dual 16-bit unsigned saturating addition. | |
| uint32_t | __UHADD16 (uint32_t val1, uint32_t val2) |
| Dual 16-bit unsigned addition with halved results. | |
| uint32_t | __SSUB16 (uint32_t val1, uint32_t val2) |
| GE setting dual 16-bit signed subtraction. | |
| uint32_t | __QSUB16 (uint32_t val1, uint32_t val2) |
| Q setting dual 16-bit saturating subtract. | |
| uint32_t | __SHSUB16 (uint32_t val1, uint32_t val2) |
| Dual 16-bit signed subtraction with halved results. | |
| uint32_t | __USUB16 (uint32_t val1, uint32_t val2) |
| GE setting dual 16-bit unsigned subtract. | |
| uint32_t | __UQSUB16 (uint32_t val1, uint32_t val2) |
| Dual 16-bit unsigned saturating subtraction. | |
| uint32_t | __UHSUB16 (uint32_t val1, uint32_t val2) |
| Dual 16-bit unsigned subtraction with halved results. | |
| uint32_t | __SASX (uint32_t val1, uint32_t val2) |
| GE setting dual 16-bit addition and subtraction with exchange. | |
| uint32_t | __QASX (uint32_t val1, uint32_t val2) |
| Q setting dual 16-bit add and subtract with exchange. | |
| uint32_t | __SHASX (uint32_t val1, uint32_t val2) |
| Dual 16-bit signed addition and subtraction with halved results. | |
| uint32_t | __UASX (uint32_t val1, uint32_t val2) |
| GE setting dual 16-bit unsigned addition and subtraction with exchange. | |
| uint32_t | __UQASX (uint32_t val1, uint32_t val2) |
| Dual 16-bit unsigned saturating addition and subtraction with exchange. | |
| uint32_t | __UHASX (uint32_t val1, uint32_t val2) |
| Dual 16-bit unsigned addition and subtraction with halved results and exchange. | |
| uint32_t | __SSAX (uint32_t val1, uint32_t val2) |
| GE setting dual 16-bit signed subtraction and addition with exchange. | |
| uint32_t | __QSAX (uint32_t val1, uint32_t val2) |
| Q setting dual 16-bit subtract and add with exchange. | |
| uint32_t | __SHSAX (uint32_t val1, uint32_t val2) |
| Dual 16-bit signed subtraction and addition with halved results. | |
| uint32_t | __USAX (uint32_t val1, uint32_t val2) |
| GE setting dual 16-bit unsigned subtract and add with exchange. | |
| uint32_t | __UQSAX (uint32_t val1, uint32_t val2) |
| Dual 16-bit unsigned saturating subtraction and addition with exchange. | |
| uint32_t | __UHSAX (uint32_t val1, uint32_t val2) |
| Dual 16-bit unsigned subtraction and addition with halved results and exchange. | |
| uint32_t | __USAD8 (uint32_t val1, uint32_t val2) |
| Unsigned sum of quad 8-bit unsigned absolute difference. | |
| uint32_t | __USADA8 (uint32_t val1, uint32_t val2, uint32_t val3) |
| Unsigned sum of quad 8-bit unsigned absolute difference with 32-bit accumulate. | |
| uint32_t | __SSAT16 (uint32_t val1, const uint32_t val2) |
| Q setting dual 16-bit saturate. | |
| uint32_t | __USAT16 (uint32_t val1, const uint32_t val2) |
| Q setting dual 16-bit unsigned saturate. | |
| uint32_t | __UXTB16 (uint32_t val) |
| Dual extract 8-bits and zero-extend to 16-bits. | |
| uint32_t | __UXTAB16 (uint32_t val1, uint32_t val2) |
| Extracted 16-bit to 32-bit unsigned addition. | |
| uint32_t | __SXTB16 (uint32_t val) |
| Dual extract 8-bits and sign extend each to 16-bits. | |
| uint32_t | __SXTAB16 (uint32_t val1, uint32_t val2) |
| Dual extracted 8-bit to 16-bit signed addition. | |
| uint32_t | __SMUAD (uint32_t val1, uint32_t val2) |
| Q setting sum of dual 16-bit signed multiply. | |
| uint32_t | __SMUADX (uint32_t val1, uint32_t val2) |
| Q setting sum of dual 16-bit signed multiply with exchange. | |
| uint32_t | __SMLAD (uint32_t val1, uint32_t val2, uint32_t val3) |
| Q setting dual 16-bit signed multiply with single 32-bit accumulator. | |
| uint32_t | __SMLADX (uint32_t val1, uint32_t val2, uint32_t val3) |
| Q setting pre-exchanged dual 16-bit signed multiply with single 32-bit accumulator. | |
| uint64_t | __SMLALD (uint32_t val1, uint32_t val2, uint64_t val3) |
| Dual 16-bit signed multiply with single 64-bit accumulator. | |
| unsigned long long | __SMLALDX (uint32_t val1, uint32_t val2, unsigned long long val3) |
| Dual 16-bit signed multiply with exchange with single 64-bit accumulator. | |
| uint32_t | __SMUSD (uint32_t val1, uint32_t val2) |
| Dual 16-bit signed multiply returning difference. | |
| uint32_t | __SMUSDX (uint32_t val1, uint32_t val2) |
| Dual 16-bit signed multiply with exchange returning difference. | |
| uint32_t | __SMLSD (uint32_t val1, uint32_t val2, uint32_t val3) |
| Q setting dual 16-bit signed multiply subtract with 32-bit accumulate. | |
| uint32_t | __SMLSDX (uint32_t val1, uint32_t val2, uint32_t val3) |
| Q setting dual 16-bit signed multiply with exchange subtract with 32-bit accumulate. | |
| uint64_t | __SMLSLD (uint32_t val1, uint32_t val2, uint64_t val3) |
| Q setting dual 16-bit signed multiply subtract with 64-bit accumulate. | |
| unsigned long long | __SMLSLDX (uint32_t val1, uint32_t val2, unsigned long long val3) |
| Q setting dual 16-bit signed multiply with exchange subtract with 64-bit accumulate. | |
| uint32_t | __SEL (uint32_t val1, uint32_t val2) |
| Select bytes based on GE bits. | |
| uint32_t | __QADD (uint32_t val1, uint32_t val2) |
| Q setting saturating add. | |
| uint32_t | __QSUB (uint32_t val1, uint32_t val2) |
| Q setting saturating subtract. | |
| uint32_t | __PKHBT (uint32_t val1, uint32_t val2, uint32_t val3) |
| Halfword packing instruction. Combines bits[15:0] of val1 with bits[31:16] of val2 levitated with the val3. | |
| uint32_t | __PKHTB (uint32_t val1, uint32_t val2, uint32_t val3) |
| Halfword packing instruction. Combines bits[31:16] of val1 with bits[15:0] of val2 right-shifted with the val3. | |
Description
+Single Instruction Multiple Data (SIMD) extensions are provided only for Cortex-M4 cores to simplify development of application software. SIMD extensions increase the processing capability without materially increasing the power consumption. The SIMD extensions are completely transparent to the operating system (OS), allowing existing OS ports to be used.
+SIMD Features:
+-
+
- Simultaneous computation of 2x16-bit or 4x8-bit operands +
- Fractional arithmetic +
- User definable saturation modes (arbitrary word-width) +
- Dual 16x16 multiply-add/subtract 32x32 fractional MAC +
- Simultaneous 8/16-bit select operations +
- Performance up to 3.2 GOPS at 800MHz +
- Performance is achieved with a "near zero" increase in power consumption on a typical implementation +
Examples:
+Addition: Add two values using SIMD function
+uint32_t add_halfwords(uint32_t val1, uint32_t val2)
+{
+ return __SADD16(val1, val2);
+}
+Subtraction: Subtract two values using SIMD function
+uint32_t sub_halfwords(uint32_t val1, uint32_t val2)
+{
+ return __SSUB16(val1, val2);
+}
+Multiplication: Performing a multiplication using SIMD function
+uint32_t dual_mul_add_products(uint32_t val1, uint32_t val2)
+{
+ return __SMUAD(val1, val2);
+}
+Function Documentation
+ +
+
+
+
+
+
+
+| uint32_t __PKHBT | +( | +uint32_t | +val1, | +
| + | + | uint32_t | +val2, | +
| + | + | uint32_t | +val3 | +
| + | ) | ++ |
+
+Combine a halfword from one register with a halfword from another register. The second argument can be left-shifted before extraction of the halfword. The registers PC and SP are not allowed as arguments. This instruction does not change the flags.
+- Parameters:
-
+
+
+val1 first 16-bit operands val2 second 16-bit operands val3 value for left-shifting val2. Value range [0..31].
+
- Returns:
- the combination of halfwords.
- Operation:
res[15:0] = val1[15:0] + res[31:16] = val2[31:16]<<val3 +
+
+
+
+
+
+
+| uint32_t __PKHTB | +( | +uint32_t | +val1, | +
| + | + | uint32_t | +val2, | +
| + | + | uint32_t | +val3 | +
| + | ) | ++ |
+
+Combines a halfword from one register with a halfword from another register. The second argument can be right-shifted before extraction of the halfword. The registers PC and SP are not allowed as arguments. This instruction does not change the flags.
+- Parameters:
-
+
+
+val1 second 16-bit operands val2 first 16-bit operands val3 value for right-shifting val2. Value range [1..32].
+
- Returns:
- the combination of halfwords.
- Operation:
res[15:0] = val2[15:0]>>val3 + res[31:16] = val1[31:16] +
+
+
+
+
+
+
+| uint32_t __QADD | +( | +uint32_t | +val1, | +
| + | + | uint32_t | +val2 | +
| + | ) | ++ |
+
+This function enables you to obtain the saturating add of two integers.
+ The Q bit is set if the operation saturates.
- Parameters:
-
+
+
+val1 first summand of the saturating add operation. val2 second summand of the saturating add operation.
+
- Returns:
- the saturating addition of val1 and val2.
- Operation:
res[31:0] = SAT(val1 + SAT(val2 * 2)) +
+
+
+
+
+
+
+| uint32_t __QADD16 | +( | +uint32_t | +val1, | +
| + | + | uint32_t | +val2 | +
| + | ) | ++ |
+
+This function enables you to perform two 16-bit integer arithmetic additions in parallel, saturating the results to the 16-bit signed integer range -215 <= x <= 215 - 1.
+- Parameters:
-
+
+
+val1 first two 16-bit summands. val2 second two 16-bit summands.
+
- Returns:
-
+
- the saturated addition of the low halfwords, in the low halfword of the return value. +
- the saturated addition of the high halfwords, in the high halfword of the return value. +
- The returned results are saturated to the 16-bit signed integer range -215 <= x <= 215 - 1
- Operation:
res[15:0] = val1[15:0] + val2[15:0] + res[31:16] = val1[31:16] + val2[31:16] +
+
+
+
+
+
+
+| uint32_t __QADD8 | +( | +uint32_t | +val1, | +
| + | + | uint32_t | +val2 | +
| + | ) | ++ |
+
+This function enables you to perform four 8-bit integer additions, saturating the results to the 8-bit signed integer range -27 <= x <= 27 - 1.
+- Parameters:
-
+
+
+val1 first four 8-bit summands. val2 second four 8-bit summands.
+
- Returns:
-
+
- the saturated addition of the first byte of each operand in the first byte of the return value. +
- the saturated addition of the second byte of each operand in the second byte of the return value. +
- the saturated addition of the third byte of each operand in the third byte of the return value. +
- the saturated addition of the fourth byte of each operand in the fourth byte of the return value. +
- The returned results are saturated to the 16-bit signed integer range -27 <= x <= 27 - 1.
- Operation:
res[7:0] = val1[7:0] + val2[7:0] + res[15:8] = val1[15:8] + val2[15:8] + res[23:16] = val1[23:16] + val2[23:16] + res[31:24] = val1[31:24] + val2[31:24] +
+
+
+
+
+
+
+| uint32_t __QASX | +( | +uint32_t | +val1, | +
| + | + | uint32_t | +val2 | +
| + | ) | ++ |
+
+This function enables you to exchange the halfwords of the one operand, then add the high halfwords and subtract the low halfwords, saturating the results to the 16-bit signed integer range -215 <= x <= 215 - 1.
+- Parameters:
-
+
+
+val1 first operand for the subtraction in the low halfword, and the first operand for the addition in the high halfword. val2 second operand for the subtraction in the high halfword, and the second operand for the addition in the low halfword.
+
- Returns:
-
+
- the saturated subtraction of the high halfword in the second operand from the low halfword in the first operand, in the low halfword of the return value. +
- the saturated addition of the high halfword in the first operand and the low halfword in the second operand, in the high halfword of the return value. +
- The returned results are saturated to the 16-bit signed integer range -215 <= x <= 215 - 1.
- Operation:
res[15:0] = val1[15:0] - val2[31:16] + res[31:16] = val1[31:16] + val2[15:0] +
+
+
+
+
+
+
+| uint32_t __QSAX | +( | +uint32_t | +val1, | +
| + | + | uint32_t | +val2 | +
| + | ) | ++ |
+
+This function enables you to exchange the halfwords of one operand, then subtract the high halfwords and add the low halfwords, saturating the results to the 16-bit signed integer range -215 <= x <= 215 - 1.
+- Parameters:
-
+
+
+val1 first operand for the addition in the low halfword, and the first operand for the subtraction in the high halfword. val2 second operand for the addition in the high halfword, and the second operand for the subtraction in the low halfword.
+
- Returns:
-
+
- the saturated addition of the low halfword of the first operand and the high halfword of the second operand, in the low halfword of the return value. +
- the saturated subtraction of the low halfword of the second operand from the high halfword of the first operand, in the high halfword of the return value. +
- The returned results are saturated to the 16-bit signed integer range -215 <= x <= 215 - 1.
- Operation:
res[15:0] = val1[15:0] + val2[31:16] + res[31:16] = val1[31:16] - val2[15:0] +
+
+
+
+
+
+
+| uint32_t __QSUB | +( | +uint32_t | +val1, | +
| + | + | uint32_t | +val2 | +
| + | ) | ++ |
+
+This function enables you to obtain the saturating subtraction of two integers.
+ The Q bit is set if the operation saturates.
- Parameters:
-
+
+
+val1 minuend of the saturating subtraction operation. val2 subtrahend of the saturating subtraction operation.
+
- Returns:
- the saturating subtraction of val1 and val2.
- Operation:
res[31:0] = SAT(val1 - SAT(val2 * 2)) +
+
+
+
+
+
+
+| uint32_t __QSUB16 | +( | +uint32_t | +val1, | +
| + | + | uint32_t | +val2 | +
| + | ) | ++ |
+
+This function enables you to perform two 16-bit integer subtractions, saturating the results to the 16-bit signed integer range -215 <= x <= 215 - 1.
+- Parameters:
-
+
+
+val1 first two 16-bit operands. val2 second two 16-bit operands.
+
- Returns:
-
+
- the saturated subtraction of the low halfword in the second operand from the low halfword in the first operand, in the low halfword of the returned result. +
- the saturated subtraction of the high halfword in the second operand from the high halfword in the first operand, in the high halfword of the returned result. +
- The returned results are saturated to the 16-bit signed integer range -215 <= x <= 215 - 1.
- Operation:
res[15:0] = val1[15:0] - val2[15:0] + res[31:16] = val1[31:16] - val2[31:16] +
+
+
+
+
+
+
+| uint32_t __QSUB8 | +( | +uint32_t | +val1, | +
| + | + | uint32_t | +val2 | +
| + | ) | ++ |
+
+This function enables you to perform four 8-bit integer subtractions, saturating the results to the 8-bit signed integer range -27 <= x <= 27 - 1.
+- Parameters:
-
+
+
+val1 first four 8-bit operands. val2 second four 8-bit operands.
+
- Returns:
-
+
- the subtraction of the first byte in the second operand from the first byte in the first operand, in the first bytes of the return value. +
- the subtraction of the second byte in the second operand from the second byte in the first operand, in the second byte of the return value. +
- the subtraction of the third byte in the second operand from the third byte in the first operand, in the third byte of the return value. +
- the subtraction of the fourth byte in the second operand from the fourth byte in the first operand, in the fourth byte of the return value. +
- The returned results are saturated to the 8-bit signed integer range -27 <= x <= 27 - 1.
- Operation:
res[7:0] = val1[7:0] - val2[7:0] + res[15:8] = val1[15:8] - val2[15:8] + res[23:16] = val1[23:16] - val2[23:16] + res[31:24] = val1[31:24] - val2[31:24] +
+
+
+
+
+
+
+| uint32_t __SADD16 | +( | +uint32_t | +val1, | +
| + | + | uint32_t | +val2 | +
| + | ) | ++ |
+
+This function enables you to perform two 16-bit signed integer additions.
+ The GE bits in the APSR are set according to the results of the additions.
- Parameters:
-
+
+
+val1 first two 16-bit summands. val2 second two 16-bit summands.
+
- Returns:
-
+
- the addition of the low halfwords in the low halfword of the return value. +
- the addition of the high halfwords in the high halfword of the return value. +
- Each bit in APSR.GE is set or cleared for each byte in the return value, depending on the results of the operation.
- If res is the return value, then:
-
+
- if res[15:0] >= 0 then APSR.GE[1:0] = 11 else 00 +
- if res[31:16] >= 0 then APSR.GE[3:2] = 11 else 00 +
- Operation:
res[15:0] = val1[15:0] + val2[15:0] + res[31:16] = val1[31:16] + val2[31:16] +
+
+
+
+
+
+
+| uint32_t __SADD8 | +( | +uint32_t | +val1, | +
| + | + | uint32_t | +val2 | +
| + | ) | ++ |
+
+This function performs four 8-bit signed integer additions. The GE bits of the APSR are set according to the results of the additions.
+- Parameters:
-
+
+
+val1 first four 8-bit summands. val2 second four 8-bit summands.
+
- Returns:
-
+
- the addition of the first bytes from each operand, in the first byte of the return value. +
- the addition of the second bytes of each operand, in the second byte of the return value. +
- the addition of the third bytes of each operand, in the third byte of the return value. +
- the addition of the fourth bytes of each operand, in the fourth byte of the return value. +
- Each bit in APSR.GE is set or cleared for each byte in the return value, depending on the results of the operation.
- If res is the return value, then:
-
+
- if res[7:0] >= 0 then APSR.GE[0] = 1 else 0 +
- if res[15:8] >= 0 then APSR.GE[1] = 1 else 0 +
- if res[23:16] >= 0 then APSR.GE[2] = 1 else 0 +
- if res[31:24] >= 0 then APSR.GE[3] = 1 else 0 +
- Operation:
res[7:0] = val1[7:0] + val2[7:0] + res[15:8] = val1[15:8] + val2[15:8] + res[23:16] = val1[23:16] + val2[23:16] + res[31:24] = val1[31:24] + val2[31:24] +
+
+
+
+
+
+
+| uint32_t __SASX | +( | +uint32_t | +val1, | +
| + | + | uint32_t | +val2 | +
| + | ) | ++ |
+
+This function inserts an SASX instruction into the instruction stream generated by the compiler. It enables you to exchange the halfwords of the second operand, add the high halfwords and subtract the low halfwords.
+ The GE bits in the APRS are set according to the results.
- Parameters:
-
+
+
+val1 first operand for the subtraction in the low halfword, and the first operand for the addition in the high halfword. val2 second operand for the subtraction in the high halfword, and the second operand for the addition in the low halfword.
+
- Returns:
-
+
- the subtraction of the high halfword in the second operand from the low halfword in the first operand, in the low halfword of the return value. +
- the addition of the high halfword in the first operand and the low halfword in the second operand, in the high halfword of the return value. +
- Each bit in APSR.GE is set or cleared for each byte in the return value, depending on the results of the operation.
- If res is the return value, then:
-
+
- if res[15:0] >= 0 then APSR.GE[1:0] = 11 else 00 +
- if res[31:16] >= 0 then APSR.GE[3:2] = 11 else 00 +
- Operation:
res[15:0] = val1[15:0] - val2[31:16] + res[31:16] = val1[31:16] + val2[15:0] +
+
+
+
+
+
+
+| uint32_t __SEL | +( | +uint32_t | +val1, | +
| + | + | uint32_t | +val2 | +
| + | ) | ++ |
+
+This function inserts a SEL instruction into the instruction stream generated by the compiler. It enables you to select bytes from the input parameters, whereby the bytes that are selected depend upon the results of previous SIMD instruction function. The results of previous SIMD instruction function are represented by the Greater than or Equal flags in the Application Program Status Register (APSR). The __SEL function works equally well on both halfword and byte operand function results. This is because halfword operand operations set two (duplicate) GE bits per value.
+- Parameters:
-
+
+
+val1 four selectable 8-bit values. val2 four selectable 8-bit values.
+
- Returns:
- The function selects bytes from the input parameters and returns them in the return value, res, according to the following criteria:
-
+
- if APSR.GE[0] == 1 then res[7:0] = val1[7:0] else res[7:0] = val2[7:0] +
- if APSR.GE[1] == 1 then res[15:8] = val1[15:8] else res[15:8] = val2[15:8] +
- if APSR.GE[2] == 1 then res[23:16] = val1[23:16] else res[23:16] = val2[23:16] +
- if APSR.GE[3] == 1 then res[31;24] = val1[31:24] else res = val2[31:24] +
+
+
+
+
+
+
+| uint32_t __SHADD16 | +( | +uint32_t | +val1, | +
| + | + | uint32_t | +val2 | +
| + | ) | ++ |
+
+This function enables you to perform two signed 16-bit integer additions, halving the results.
+- Parameters:
-
+
+
+val1 first two 16-bit summands. val2 second two 16-bit summands.
+
- Returns:
-
+
- the halved addition of the low halfwords, in the low halfword of the return value. +
- the halved addition of the high halfwords, in the high halfword of the return value. +
- Operation:
res[15:0] = val1[15:0] + val2[15:0] >> 1 + res[31:16] = val1[31:16] + val2[31:16] >> 1 +
+
+
+
+
+
+
+| uint32_t __SHADD8 | +( | +uint32_t | +val1, | +
| + | + | uint32_t | +val2 | +
| + | ) | ++ |
+
+This function enables you to perform four signed 8-bit integer additions, halving the results.
+- Parameters:
-
+
+
+val1 first four 8-bit summands. val2 second four 8-bit summands.
+
- Returns:
-
+
- the halved addition of the first bytes from each operand, in the first byte of the return value. +
- the halved addition of the second bytes from each operand, in the second byte of the return value. +
- the halved addition of the third bytes from each operand, in the third byte of the return value. +
- the halved addition of the fourth bytes from each operand, in the fourth byte of the return value. +
- Operation:
res[7:0] = val1[7:0] + val2[7:0] >> 1 + res[15:8] = val1[15:8] + val2[15:8] >> 1 + res[23:16] = val1[23:16] + val2[23:16] >> 1 + res[31:24] = val1[31:24] + val2[31:24] >> 1 +
+
+
+
+
+
+
+| uint32_t __SHASX | +( | +uint32_t | +val1, | +
| + | + | uint32_t | +val2 | +
| + | ) | ++ |
+
+This function enables you to exchange the two halfwords of one operand, perform one signed 16-bit integer addition and one signed 16-bit subtraction, and halve the results.
+- Parameters:
-
+
+
+val1 first 16-bit operands. val2 second 16-bit operands.
+
- Returns:
-
+
- the halved subtraction of the high halfword in the second operand from the low halfword in the first operand, in the low halfword of the return value. +
- the halved subtraction of the low halfword in the second operand from the high halfword in the first operand, in the high halfword of the return value. +
- Operation:
res[15:0] = (val1[15:0] - val2[31:16]) >> 1 + res[31:16] = (val1[31:16] - val2[15:0] ) >> 1 +
+
+
+
+
+
+
+| uint32_t __SHSAX | +( | +uint32_t | +val1, | +
| + | + | uint32_t | +val2 | +
| + | ) | ++ |
+
+This function enables you to exchange the two halfwords of one operand, perform one signed 16-bit integer subtraction and one signed 16-bit addition, and halve the results.
+- Parameters:
-
+
+
+val1 first 16-bit operands. val2 second 16-bit operands.
+
- Returns:
-
+
- the halved addition of the low halfword in the first operand and the high halfword in the second operand, in the low halfword of the return value. +
- the halved subtraction of the low halfword in the second operand from the high halfword in the first operand, in the high halfword of the return value. +
- Operation:
res[15:0] = (val1[15:0] + val2[31:16]) >> 1 + res[31:16] = (val1[31:16] - val2[15:0] ) >> 1 +
+
+
+
+
+
+
+| uint32_t __SHSUB16 | +( | +uint32_t | +val1, | +
| + | + | uint32_t | +val2 | +
| + | ) | ++ |
+
+This function enables you to perform two signed 16-bit integer subtractions, halving the results.
+- Parameters:
-
+
+
+val1 first two 16-bit operands. val2 second two 16-bit operands.
+
- Returns:
-
+
- the halved subtraction of the low halfword in the second operand from the low halfword in the first operand, in the low halfword of the returned result. +
- the halved subtraction of the high halfword in the second operand from the high halfword in the first operand, in the high halfword of the returned result. +
- Operation:
res[15:0] = val1[15:0] - val2[15:0] >> 1 + res[31:16] = val1[31:16] - val2[31:16] >> 1 +
+
+
+
+
+
+
+| uint32_t __SHSUB8 | +( | +uint32_t | +val1, | +
| + | + | uint32_t | +val2 | +
| + | ) | ++ |
+
+This function enables you to perform four signed 8-bit integer subtractions, halving the results.
+- Parameters:
-
+
+
+val1 first four 8-bit operands. val2 second four 8-bit operands.
+
- Returns:
-
+
- the halved subtraction of the first byte in the second operand from the first byte in the first operand, in the first bytes of the return value. +
- the halved subtraction of the second byte in the second operand from the second byte in the first operand, in the second byte of the return value. +
- the halved subtraction of the third byte in the second operand from the third byte in the first operand, in the third byte of the return value. +
- the halved subtraction of the fourth byte in the second operand from the fourth byte in the first operand, in the fourth byte of the return value. +
- Operation:
res[7:0] = val1[7:0] - val2[7:0] >> 1 + res[15:8] = val1[15:8] - val2[15:8] >> 1 + res[23:16] = val1[23:16] - val2[23:16] >> 1 + res[31:24] = val1[31:24] - val2[31:24] >> 1 +
+
+
+
+
+
+
+| uint32_t __SMLAD | +( | +uint32_t | +val1, | +
| + | + | uint32_t | +val2, | +
| + | + | uint32_t | +val3 | +
| + | ) | ++ |
+
+This function enables you to perform two signed 16-bit multiplications, adding both results to a 32-bit accumulate operand.
+ The Q bit is set if the addition overflows. Overflow cannot occur during the multiplications.
- Parameters:
-
+
+
+val1 first 16-bit operands for each multiplication. val2 second 16-bit operands for each multiplication. val3 accumulate value.
+
- Returns:
- the product of each multiplication added to the accumulate value, as a 32-bit integer.
- Operation:
p1 = val1[15:0] * val2[15:0] + p2 = val1[31:16] * val2[31:16] + res[31:0] = p1 + p2 + val3[31:0] +
+
+
+
+
+
+
+| uint32_t __SMLADX | +( | +uint32_t | +val1, | +
| + | + | uint32_t | +val2, | +
| + | + | uint32_t | +val3 | +
| + | ) | ++ |
+
+This function enables you to perform two signed 16-bit multiplications with exchanged halfwords of the second operand, adding both results to a 32-bit accumulate operand.
+ The Q bit is set if the addition overflows. Overflow cannot occur during the multiplications.
- Parameters:
-
+
+
+val1 first 16-bit operands for each multiplication. val2 second 16-bit operands for each multiplication. val3 accumulate value.
+
- Returns:
- the product of each multiplication with exchanged halfwords of the second operand added to the accumulate value, as a 32-bit integer.
- Operation:
p1 = val1[15:0] * val2[31:16] + p2 = val1[31:16] * val2[15:0] + res[31:0] = p1 + p2 + val3[31:0] +
+
+
+
+
+
+
+| uint64_t __SMLALD | +( | +uint32_t | +val1, | +
| + | + | uint32_t | +val2, | +
| + | + | uint64_t | +val3 | +
| + | ) | ++ |
+
+This function enables you to perform two signed 16-bit multiplications, adding both results to a 64-bit accumulate operand. Overflow is only possible as a result of the 64-bit addition. This overflow is not detected if it occurs. Instead, the result wraps around modulo264.
+- Parameters:
-
+
+
+val1 first 16-bit operands for each multiplication. val2 second 16-bit operands for each multiplication. val3 accumulate value.
+
- Returns:
- the product of each multiplication added to the accumulate value.
- Operation:
p1 = val1[15:0] * val2[15:0] + p2 = val1[31:16] * val2[31:16] + sum = p1 + p2 + val3[63:32][31:0] + res[63:32] = sum[63:32] + res[31:0] = sum[31:0] +
+
+
+
+
+
+
+| unsigned long long __SMLALDX | +( | +uint32_t | +val1, | +
| + | + | uint32_t | +val2, | +
| + | + | unsigned long long | +val3 | +
| + | ) | ++ |
+
+This function enables you to exchange the halfwords of the second operand, and perform two signed 16-bit multiplications, adding both results to a 64-bit accumulate operand. Overflow is only possible as a result of the 64-bit addition. This overflow is not detected if it occurs. Instead, the result wraps around modulo264.
+- Parameters:
-
+
+
+val1 first 16-bit operands for each multiplication. val2 second 16-bit operands for each multiplication. val3 accumulate value.
+
- Returns:
- the product of each multiplication added to the accumulate value.
- Operation:
p1 = val1[15:0] * val2[31:16] + p2 = val1[31:16] * val2[15:0] + sum = p1 + p2 + val3[63:32][31:0] + res[63:32] = sum[63:32] + res[31:0] = sum[31:0] +
+
+
+
+
+
+
+| uint32_t __SMLSD | +( | +uint32_t | +val1, | +
| + | + | uint32_t | +val2, | +
| + | + | uint32_t | +val3 | +
| + | ) | ++ |
+
+This function enables you to perform two 16-bit signed multiplications, take the difference of the products, subtracting the high halfword product from the low halfword product, and add the difference to a 32-bit accumulate operand.
+ The Q bit is set if the accumulation overflows. Overflow cannot occur during the multiplications or the subtraction.
- Parameters:
-
+
+
+val1 first 16-bit operands for each multiplication. val2 second 16-bit operands for each multiplication. val3 accumulate value.
+
- Returns:
- the difference of the product of each multiplication, added to the accumulate value.
- Operation:
p1 = val1[15:0] * val2[15:0] + p2 = val1[31:16] * val2[31:16] + res[31:0] = p1 - p2 + val3[31:0] +
+
+
+
+
+
+
+| uint32_t __SMLSDX | +( | +uint32_t | +val1, | +
| + | + | uint32_t | +val2, | +
| + | + | uint32_t | +val3 | +
| + | ) | ++ |
+
+This function enables you to exchange the halfwords in the second operand, then perform two 16-bit signed multiplications. The difference of the products is added to a 32-bit accumulate operand.
+ The Q bit is set if the addition overflows. Overflow cannot occur during the multiplications or the subtraction.
- Parameters:
-
+
+
+val1 first 16-bit operands for each multiplication. val2 second 16-bit operands for each multiplication. val3 accumulate value.
+
- Returns:
- the difference of the product of each multiplication, added to the accumulate value.
- Operation:
p1 = val1[15:0] * val2[31:16] + p2 = val1[31:16] * val2[15:0] + res[31:0] = p1 - p2 + val3[31:0] +
+
+
+
+
+
+
+| uint64_t __SMLSLD | +( | +uint32_t | +val1, | +
| + | + | uint32_t | +val2, | +
| + | + | uint64_t | +val3 | +
| + | ) | ++ |
+
+This function It enables you to perform two 16-bit signed multiplications, take the difference of the products, subtracting the high halfword product from the low halfword product, and add the difference to a 64-bit accumulate operand. Overflow cannot occur during the multiplications or the subtraction. Overflow can occur as a result of the 64-bit addition, and this overflow is not detected. Instead, the result wraps round to modulo264.
+- Parameters:
-
+
+
+val1 first 16-bit operands for each multiplication. val2 second 16-bit operands for each multiplication. val3 accumulate value.
+
- Returns:
- the difference of the product of each multiplication, added to the accumulate value.
- Operation:
p1 = val1[15:0] * val2[15:0] + p2 = val1[31:16] * val2[31:16] + res[63:0] = p1 - p2 + val3[63:0] +
+
+
+
+
+
+
+| unsigned long long __SMLSLDX | +( | +uint32_t | +val1, | +
| + | + | uint32_t | +val2, | +
| + | + | unsigned long long | +val3 | +
| + | ) | ++ |
+
+This function enables you to exchange the halfwords of the second operand, perform two 16-bit multiplications, adding the difference of the products to a 64-bit accumulate operand. Overflow cannot occur during the multiplications or the subtraction. Overflow can occur as a result of the 64-bit addition, and this overflow is not detected. Instead, the result wraps round to modulo264.
+- Parameters:
-
+
+
+val1 first 16-bit operands for each multiplication. val2 second 16-bit operands for each multiplication. val3 accumulate value.
+
- Returns:
- the difference of the product of each multiplication, added to the accumulate value.
- Operation:
p1 = val1[15:0] * val2[31:16] + p2 = val1[31:16] * val2[15:0] + res[63:0] = p1 - p2 + val3[63:0] +
+
+
+
+
+
+
+| uint32_t __SMUAD | +( | +uint32_t | +val1, | +
| + | + | uint32_t | +val2 | +
| + | ) | ++ |
+
+This function enables you to perform two 16-bit signed multiplications, adding the products together.
+ The Q bit is set if the addition overflows.
- Parameters:
-
+
+
+val1 first 16-bit operands for each multiplication. val2 second 16-bit operands for each multiplication.
+
- Returns:
- the sum of the products of the two 16-bit signed multiplications.
- Operation:
p1 = val1[15:0] * val2[15:0] + p2 = val1[31:16] * val2[31:16] + res[31:0] = p1 + p2 +
+
+
+
+
+
+
+| uint32_t __SMUADX | +( | +uint32_t | +val1, | +
| + | + | uint32_t | +val2 | +
| + | ) | ++ |
+
+This function enables you to perform two 16-bit signed multiplications with exchanged halfwords of the second operand, adding the products together.
+ The Q bit is set if the addition overflows.
- Parameters:
-
+
+
+val1 first 16-bit operands for each multiplication. val2 second 16-bit operands for each multiplication.
+
- Returns:
- the sum of the products of the two 16-bit signed multiplications with exchanged halfwords of the second operand.
- Operation:
p1 = val1[15:0] * val2[31:16] + p2 = val1[31:16] * val2[15:0] + res[31:0] = p1 + p2 +
+
+
+
+
+
+
+| uint32_t __SMUSD | +( | +uint32_t | +val1, | +
| + | + | uint32_t | +val2 | +
| + | ) | ++ |
+
+This function enables you to perform two 16-bit signed multiplications, taking the difference of the products by subtracting the high halfword product from the low halfword product.
+- Parameters:
-
+
+
+val1 first 16-bit operands for each multiplication. val2 second 16-bit operands for each multiplication.
+
- Returns:
- the difference of the products of the two 16-bit signed multiplications.
- Operation:
p1 = val1[15:0] * val2[15:0] + p2 = val1[31:16] * val2[31:16] + res[31:0] = p1 - p2 +
+
+
+
+
+
+
+| uint32_t __SMUSDX | +( | +uint32_t | +val1, | +
| + | + | uint32_t | +val2 | +
| + | ) | ++ |
+
+This function enables you to perform two 16-bit signed multiplications, subtracting one of the products from the other. The halfwords of the second operand are exchanged before performing the arithmetic. This produces top * bottom and bottom * top multiplication.
+- Parameters:
-
+
+
+val1 first 16-bit operands for each multiplication. val2 second 16-bit operands for each multiplication.
+
- Returns:
- the difference of the products of the two 16-bit signed multiplications.
- Operation:
p1 = val1[15:0] * val2[31:16] + p2 = val1[31:16] * val2[15:0] + res[31:0] = p1 - p2 +
+
+
+
+
+
+
+| uint32_t __SSAT16 | +( | +uint32_t | +val1, | +
| + | + | const uint32_t | +val2 | +
| + | ) | ++ |
+
+This function enables you to saturate two signed 16-bit values to a selected signed range.
+ The Q bit is set if either operation saturates.
- Parameters:
-
+
+
+val1 two signed 16-bit values to be saturated. val2 bit position for saturation, an integral constant expression in the range 1 to 16.
+
- Returns:
- the sum of the absolute differences of the following bytes, added to the accumulation value:
-
+
- the signed saturation of the low halfword in val1, saturated to the bit position specified in val2 and returned in the low halfword of the return value. +
- the signed saturation of the high halfword in val1, saturated to the bit position specified in val2 and returned in the high halfword of the return value. +
- Operation:
Saturate halfwords in val1 to the signed range specified by the bit position in val2 +
+
+
+
+
+
+
+| uint32_t __SSAX | +( | +uint32_t | +val1, | +
| + | + | uint32_t | +val2 | +
| + | ) | ++ |
+
+This function enables you to exchange the two halfwords of one operand and perform one 16-bit integer subtraction and one 16-bit addition.
+ The GE bits in the APSR are set according to the results.
- Parameters:
-
+
+
+val1 first operand for the addition in the low halfword, and the first operand for the subtraction in the high halfword. val2 second operand for the addition in the high halfword, and the second operand for the subtraction in the low halfword.
+
- Returns:
-
+
- the addition of the low halfword in the first operand and the high halfword in the second operand, in the low halfword of the return value. +
- the subtraction of the low halfword in the second operand from the high halfword in the first operand, in the high halfword of the return value. +
- Each bit in APSR.GE is set or cleared for each byte in the return value, depending on the results of the operation.
- If res is the return value, then:
-
+
- if res[15:0] >= 0 then APSR.GE[1:0] = 11 else 00 +
- if res[31:16] >= 0 then APSR.GE[3:2] = 11 else 00 +
- Operation:
res[15:0] = val1[15:0] + val2[31:16] + res[31:16] = val1[31:16] - val2[15:0] +
+
+
+
+
+
+
+| uint32_t __SSUB16 | +( | +uint32_t | +val1, | +
| + | + | uint32_t | +val2 | +
| + | ) | ++ |
+
+This function enables you to perform two 16-bit signed integer subtractions.
+ The GE bits in the APSR are set according to the results.
- Parameters:
-
+
+
+val1 first two 16-bit operands of each subtraction. val2 second two 16-bit operands of each subtraction.
+
- Returns:
-
+
- the subtraction of the low halfword in the second operand from the low halfword in the first operand, in the low halfword of the return value. +
- the subtraction of the high halfword in the second operand from the high halfword in the first operand, in the high halfword of the return value. +
- Each bit in APSR.GE is set or cleared for each byte in the return value, depending on the results of the operation.
- If
-
+
- res is the return value, then: +
- if res[15:0] >= 0 then APSR.GE[1:0] = 11 else 00 +
- if res[31:16] >= 0 then APSR.GE[3:2] = 11 else 00 +
- Operation:
res[15:0] = val1[15:0] - val2[15:0] + res[31:16] = val1[31:16] - val2[31:16] +
+
+
+
+
+
+
+| uint32_t __SSUB8 | +( | +uint32_t | +val1, | +
| + | + | uint32_t | +val2 | +
| + | ) | ++ |
+
+This function enables you to perform four 8-bit signed integer subtractions.
+ The GE bits in the APSR are set according to the results.
- Parameters:
-
+
+
+val1 first four 8-bit operands of each subtraction. val2 second four 8-bit operands of each subtraction.
+
- Returns:
-
+
- the subtraction of the first byte in the second operand from the first byte in the first operand, in the first bytes of the return value. +
- the subtraction of the second byte in the second operand from the second byte in the first operand, in the second byte of the return value. +
- the subtraction of the third byte in the second operand from the third byte in the first operand, in the third byte of the return value. +
- the subtraction of the fourth byte in the second operand from the fourth byte in the first operand, in the fourth byte of the return value. +
- Each bit in APSR.GE is set or cleared for each byte in the return value, depending on
- the results of the operation.
- If res is the return value, then:
-
+
- if res[8:0] >= 0 then APSR.GE[0] = 1 else 0 +
- if res[15:8] >= 0 then APSR.GE[1] = 1 else 0 +
- if res[23:16] >= 0 then APSR.GE[2] = 1 else 0 +
- if res[31:24] >= 0 then APSR.GE[3] = 1 else 0 +
- Operation:
res[7:0] = val1[7:0] - val2[7:0] + res[15:8] = val1[15:8] - val2[15:8] + res[23:16] = val1[23:16] - val2[23:16] + res[31:24] = val1[31:24] - val2[31:24] +
+
+
+
+
+
+
+| uint32_t __SXTAB16 | +( | +uint32_t | +val1, | +
| + | + | uint32_t | +val2 | +
| + | ) | ++ |
+
+This function enables you to extract two 8-bit values from the second operand (at bit positions [7:0] and [23:16]), sign-extend them to 16-bits each, and add the results to the first operand.
+- Parameters:
-
+
+
+val1 values added to the zero-extended to 16-bit values. val2 two 8-bit values to be extracted and zero-extended.
+
- Returns:
- the addition of val1 and val2, where the 8-bit values in val2[7:0] and val2[23:16] have been extracted and sign-extended prior to the addition.
- Operation:
res[15:0] = val1[15:0] + SignExtended(val2[7:0]) + res[31:16] = val1[31:16] + SignExtended(val2[23:16]) +
+
+
+
+
+
+
+| uint32_t __SXTB16 | +( | +uint32_t | +val | ) | ++ |
+
+This function enables you to extract two 8-bit values from an operand and sign-extend them to 16 bits each.
+- Parameters:
-
+
+
+val two 8-bit values in val[7:0] and val[23:16] to be sign-extended.
+
- Returns:
- the 8-bit values sign-extended to 16-bit values.
-
+
- sign-extended value of val[7:0] in the low halfword of the return value. +
- sign-extended value of val[23:16] in the high halfword of the return value. +
- Operation:
res[15:0] = SignExtended(val[7:0] + res[31:16] = SignExtended(val[23:16] +
+
+
+
+
+
+
+| uint32_t __UADD16 | +( | +uint32_t | +val1, | +
| + | + | uint32_t | +val2 | +
| + | ) | ++ |
+
+This function enables you to perform two 16-bit unsigned integer additions.
+ The GE bits in the APSR are set according to the results.
- Parameters:
-
+
+
+val1 first two 16-bit summands for each addition. val2 second two 16-bit summands for each addition.
+
- Returns:
-
+
- the addition of the low halfwords in each operand, in the low halfword of the return value. +
- the addition of the high halfwords in each operand, in the high halfword of the return value. +
- Each bit in APSR.GE is set or cleared for each byte in the return value, depending on the results of the operation.
- If res is the return value, then:
-
+
- if res[15:0] >= 0x10000 then APSR.GE[0] = 11 else 00 +
- if res[31:16] >= 0x10000 then APSR.GE[1] = 11 else 00 +
- Operation:
res[15:0] = val1[15:0] + val2[15:0] + res[31:16] = val1[31:16] + val2[31:16] +
+
+
+
+
+
+
+| uint32_t __UADD8 | +( | +uint32_t | +val1, | +
| + | + | uint32_t | +val2 | +
| + | ) | ++ |
+
+This function enables you to perform four unsigned 8-bit integer additions. The GE bits of the APSR are set according to the results.
+- Parameters:
-
+
+
+val1 first four 8-bit summands for each addition. val2 second four 8-bit summands for each addition.
+
- Returns:
-
+
- the halved addition of the first bytes from each operand, in the first byte of the return value. +
- the halved addition of the second bytes from each operand, in the second byte of the return value. +
- the halved addition of the third bytes from each operand, in the third byte of the return value. +
- the halved addition of the fourth bytes from each operand, in the fourth byte of the return value. +
- Each bit in APSR.GE is set or cleared for each byte in the return value, depending on the results of the operation.
- If res is the return value, then:
-
+
- if res[7:0] >= 0x100 then APSR.GE[0] = 1 else 0 +
- if res[15:8] >= 0x100 then APSR.GE[1] = 1 else 0 +
- if res[23:16] >= 0x100 then APSR.GE[2] = 1 else 0 +
- if res[31:24] >= 0x100 then APSR.GE[3] = 1 else 0 +
- Operation:
res[7:0] = val1[7:0] + val2[7:0] + res[15:8] = val1[15:8] + val2[15:8] + res[23:16] = val1[23:16] + val2[23:16] + res[31:24] = val1[31:24] + val2[31:24] +
+
+
+
+
+
+
+| uint32_t __UASX | +( | +uint32_t | +val1, | +
| + | + | uint32_t | +val2 | +
| + | ) | ++ |
+
+This function enables you to exchange the two halfwords of the second operand, add the high halfwords and subtract the low halfwords.
+ The GE bits in the APSR are set according to the results.
- Parameters:
-
+
+
+val1 first operand for the subtraction in the low halfword, and the first operand for the addition in the high halfword. val2 second operand for the subtraction in the high halfword and the second operand for the addition in the low halfword.
+
- Returns:
-
+
- the subtraction of the high halfword in the second operand from the low halfword in the first operand, in the low halfword of the return value. +
- the addition of the high halfword in the first operand and the low halfword in the second operand, in the high halfword of the return value. +
- Each bit in APSR.GE is set or cleared for each byte in the return value, depending on the results of the operation.
- If res is the return value, then:
-
+
- if res[15:0] >= 0 then APSR.GE[1:0] = 11 else 00 +
- if res[31:16] >= 0x10000 then APSR.GE[3:2] = 11 else 00 +
- Operation:
res[15:0] = val1[15:0] - val2[31:16] + res[31:16] = val1[31:16] + val2[15:0] +
+
+
+
+
+
+
+| uint32_t __UHADD16 | +( | +uint32_t | +val1, | +
| + | + | uint32_t | +val2 | +
| + | ) | ++ |
+
+This function enables you to perform two unsigned 16-bit integer additions, halving the results.
+- Parameters:
-
+
+
+val1 first two 16-bit summands. val2 second two 16-bit summands.
+
- Returns:
-
+
- the halved addition of the low halfwords in each operand, in the low halfword of the return value. +
- the halved addition of the high halfwords in each operand, in the high halfword of the return value. +
- Operation:
res[15:0] = val1[15:0] + val2[15:0] >> 1 + res[31:16] = val1[31:16] + val2[31:16] >> 1 +
+
+
+
+
+
+
+| uint32_t __UHADD8 | +( | +uint32_t | +val1, | +
| + | + | uint32_t | +val2 | +
| + | ) | ++ |
+
+This function enables you to perform four unsigned 8-bit integer additions, halving the results.
+- Parameters:
-
+
+
+val1 first four 8-bit summands. val2 second four 8-bit summands.
+
- Returns:
-
+
- the halved addition of the first bytes in each operand, in the first byte of the return value. +
- the halved addition of the second bytes in each operand, in the second byte of the return value. +
- the halved addition of the third bytes in each operand, in the third byte of the return value. +
- the halved addition of the fourth bytes in each operand, in the fourth byte of the return value. +
- Operation:
res[7:0] = val1[7:0] + val2[7:0] >> 1 + res[15:8] = val1[15:8] + val2[15:8] >> 1 + res[23:16] = val1[23:16] + val2[23:16] >> 1 + res[31:24] = val1[31:24] + val2[31:24] >> 1 +
+
+
+
+
+
+
+| uint32_t __UHASX | +( | +uint32_t | +val1, | +
| + | + | uint32_t | +val2 | +
| + | ) | ++ |
+
+This function enables you to exchange the halfwords of the second operand, add the high halfwords and subtract the low halfwords, halving the results.
+- Parameters:
-
+
+
+val1 first operand for the subtraction in the low halfword, and the first operand for the addition in the high halfword. val2 second operand for the subtraction in the high halfword, and the second operand for the addition in the low halfword.
+
- Returns:
-
+
- the halved subtraction of the high halfword in the second operand from the low halfword in the first operand. +
- the halved addition of the high halfword in the first operand and the low halfword in the second operand. +
- Operation:
res[15:0] = (val1[15:0] - val2[31:16]) >> 1 + res[31:16] = (val1[31:16] + val2[15:0] ) >> 1 +
+
+
+
+
+
+
+| uint32_t __UHSAX | +( | +uint32_t | +val1, | +
| + | + | uint32_t | +val2 | +
| + | ) | ++ |
+
+This function enables you to exchange the halfwords of the second operand, subtract the high halfwords and add the low halfwords, halving the results.
+- Parameters:
-
+
+
+val1 first operand for the addition in the low halfword, and the first operand for the subtraction in the high halfword. val2 second operand for the addition in the high halfword, and the second operand for the subtraction in the low halfword.
+
- Returns:
-
+
- the halved addition of the high halfword in the second operand and the low halfword in the first operand, in the low halfword of the return value. +
- the halved subtraction of the low halfword in the second operand from the high halfword in the first operand, in the high halfword of the return value. +
- Operation:
res[15:0] = (val1[15:0] + val2[31:16]) >> 1 + res[31:16] = (val1[31:16] - val2[15:0] ) >> 1 +
+
+
+
+
+
+
+| uint32_t __UHSUB16 | +( | +uint32_t | +val1, | +
| + | + | uint32_t | +val2 | +
| + | ) | ++ |
+
+This function enables you to perform two unsigned 16-bit integer subtractions, halving the results.
+- Parameters:
-
+
+
+val1 first two 16-bit operands. val2 second two 16-bit operands.
+
- Returns:
-
+
- the halved subtraction of the low halfword in the second operand from the low halfword in the first operand, in the low halfword of the return value. +
- the halved subtraction of the high halfword in the second operand from the high halfword in the first operand, in the high halfword of the return value. +
- Operation:
res[15:0] = val1[15:0] - val2[15:0] >> 1 + res[31:16] = val1[31:16] - val2[31:16] >> 1 +
+
+
+
+
+
+
+| uint32_t __UHSUB8 | +( | +uint32_t | +val1, | +
| + | + | uint32_t | +val2 | +
| + | ) | ++ |
+
+This function enables you to perform four unsigned 8-bit integer subtractions, halving the results.
+- Parameters:
-
+
+
+val1 first four 8-bit operands. val2 second four 8-bit operands.
+
- Returns:
-
+
- the halved subtraction of the first byte in the second operand from the first byte in the first operand, in the first bytes of the return value. +
- the halved subtraction of the second byte in the second operand from the second byte in the first operand, in the second byte of the return value. +
- the halved subtraction of the third byte in the second operand from the third byte in the first operand, in the third byte of the return value. +
- the halved subtraction of the fourth byte in the second operand from the fourth byte in the first operand, in the fourth byte of the return value. +
- Operation:
res[7:0] = val1[7:0] - val2[7:0] >> 1 + res[15:8] = val1[15:8] - val2[15:8] >> 1 + res[23:16] = val1[23:16] - val2[23:16] >> 1 + res[31:24] = val1[31:24] - val2[31:24] >> 1 +
+
+
+
+
+
+
+| uint32_t __UQADD16 | +( | +uint32_t | +val1, | +
| + | + | uint32_t | +val2 | +
| + | ) | ++ |
+
+This function enables you to perform two unsigned 16-bit integer additions, saturating the results to the 16-bit unsigned integer range 0 < x < 216 - 1.
+- Parameters:
-
+
+
+val1 first two 16-bit summands. val2 second two 16-bit summands.
+
- Returns:
-
+
- the addition of the low halfword in the first operand and the low halfword in the second operand, in the low halfword of the return value. +
- the addition of the high halfword in the first operand and the high halfword in the second operand, in the high halfword of the return value. +
- The results are saturated to the 16-bit unsigned integer range 0 < x < 216 - 1.
- Operation:
res[15:0] = val1[15:0] + val2[15:0] + res[31:16] = val1[31:16] + val2[31:16] +
+
+
+
+
+
+
+| uint32_t __UQADD8 | +( | +uint32_t | +val1, | +
| + | + | uint32_t | +val2 | +
| + | ) | ++ |
+
+This function enables you to perform four unsigned 8-bit integer additions, saturating the results to the 8-bit unsigned integer range 0 < x < 28 - 1.
+- Parameters:
-
+
+
+val1 first four 8-bit summands. val2 second four 8-bit summands.
+
- Returns:
-
+
- the halved addition of the first bytes in each operand, in the first byte of the return value. +
- the halved addition of the second bytes in each operand, in the second byte of the return value. +
- the halved addition of the third bytes in each operand, in the third byte of the return value. +
- the halved addition of the fourth bytes in each operand, in the fourth byte of the return value. +
- The results are saturated to the 8-bit unsigned integer range 0 < x < 28 - 1.
- Operation:
res[7:0] = val1[7:0] + val2[7:0] + res[15:8] = val1[15:8] + val2[15:8] + res[23:16] = val1[23:16] + val2[23:16] + res[31:24] = val1[31:24] + val2[31:24] +
+
+
+
+
+
+
+| uint32_t __UQASX | +( | +uint32_t | +val1, | +
| + | + | uint32_t | +val2 | +
| + | ) | ++ |
+
+This function enables you to exchange the halfwords of the second operand and perform one unsigned 16-bit integer addition and one unsigned 16-bit subtraction, saturating the results to the 16-bit unsigned integer range 0 <= x <= 216 - 1.
+- Parameters:
-
+
+
+val1 first two 16-bit operands. val2 second two 16-bit operands.
+
- Returns:
-
+
- the subtraction of the high halfword in the second operand from the low halfword in the first operand, in the low halfword of the return value. +
- the subtraction of the low halfword in the second operand from the high halfword in the first operand, in the high halfword of the return value. +
- The results are saturated to the 16-bit unsigned integer range 0 <= x <= 216 - 1.
- Operation:
res[15:0] = val1[15:0] - val2[31:16] + res[31:16] = val1[31:16] + val2[15:0] +
+
+
+
+
+
+
+| uint32_t __UQSAX | +( | +uint32_t | +val1, | +
| + | + | uint32_t | +val2 | +
| + | ) | ++ |
+
+This function enables you to exchange the halfwords of the second operand and perform one unsigned 16-bit integer subtraction and one unsigned 16-bit addition, saturating the results to the 16-bit unsigned integer range 0 <= x <= 216 - 1.
+- Parameters:
-
+
+
+val1 first 16-bit operand for the addition in the low halfword, and the first 16-bit operand for the subtraction in the high halfword. val2 second 16-bit halfword for the addition in the high halfword, and the second 16-bit halfword for the subtraction in the low halfword.
+
- Returns:
-
+
- the addition of the low halfword in the first operand and the high halfword in the second operand, in the low halfword of the return value. +
- the subtraction of the low halfword in the second operand from the high halfword in the first operand, in the high halfword of the return value. +
- The results are saturated to the 16-bit unsigned integer range 0 <= x <= 216 - 1.
- Operation:
res[15:0] = val1[15:0] + val2[31:16] + res[31:16] = val1[31:16] - val2[15:0] +
+
+
+
+
+
+
+| uint32_t __UQSUB16 | +( | +uint32_t | +val1, | +
| + | + | uint32_t | +val2 | +
| + | ) | ++ |
+
+This function enables you to perform two unsigned 16-bit integer subtractions, saturating the results to the 16-bit unsigned integer range 0 < x < 216 - 1.
+- Parameters:
-
+
+
+val1 first two 16-bit operands for each subtraction. val2 second two 16-bit operands for each subtraction.
+
- Returns:
-
+
- the subtraction of the low halfword in the second operand from the low halfword in the first operand, in the low halfword of the return value. +
- the subtraction of the high halfword in the second operand from the high halfword in the first operand, in the high halfword of the return value. +
- The results are saturated to the 16-bit unsigned integer range 0 < x < 216 - 1.
- Operation:
res[15:0] = val1[15:0] - val2[15:0] + res[31:16] = val1[31:16] - val2[31:16] +
+
+
+
+
+
+
+| uint32_t __UQSUB8 | +( | +uint32_t | +val1, | +
| + | + | uint32_t | +val2 | +
| + | ) | ++ |
+
+This function enables you to perform four unsigned 8-bit integer subtractions, saturating the results to the 8-bit unsigned integer range 0 < x < 28 - 1.
+- Parameters:
-
+
+
+val1 first four 8-bit operands. val2 second four 8-bit operands.
+
- Returns:
-
+
- the subtraction of the first byte in the second operand from the first byte in the first operand, in the first bytes of the return value. +
- the subtraction of the second byte in the second operand from the second byte in the first operand, in the second byte of the return value. +
- the subtraction of the third byte in the second operand from the third byte in the first operand, in the third byte of the return value. +
- the subtraction of the fourth byte in the second operand from the fourth byte in the first operand, in the fourth byte of the return value. +
- The results are saturated to the 8-bit unsigned integer range 0 < x < 28 - 1.
- Operation:
res[7:0] = val1[7:0] - val2[7:0] + res[15:8] = val1[15:8] - val2[15:8] + res[23:16] = val1[23:16] - val2[23:16] + res[31:24] = val1[31:24] - val2[31:24] +
+
+
+
+
+
+
+| uint32_t __USAD8 | +( | +uint32_t | +val1, | +
| + | + | uint32_t | +val2 | +
| + | ) | ++ |
+
+This function enables you to perform four unsigned 8-bit subtractions, and add the absolute values of the differences together, returning the result as a single unsigned integer.
+- Parameters:
-
+
+
+val1 first four 8-bit operands for the subtractions. val2 second four 8-bit operands for the subtractions.
+
- Returns:
-
+
- the subtraction of the first byte in the second operand from the first byte in the first operand. +
- the subtraction of the second byte in the second operand from the second byte in the first operand. +
- the subtraction of the third byte in the second operand from the third byte in the first operand. +
- the subtraction of the fourth byte in the second operand from the fourth byte in the first operand. +
- The sum is returned as a single unsigned integer.
- Operation:
absdiff1 = val1[7:0] - val2[7:0] + absdiff2 = val1[15:8] - val2[15:8] + absdiff3 = val1[23:16] - val2[23:16] + absdiff4 = val1[31:24] - val2[31:24] + res[31:0] = absdiff1 + absdiff2 + absdiff3 + absdiff4 +
+
+
+
+
+
+
+| uint32_t __USADA8 | +( | +uint32_t | +val1, | +
| + | + | uint32_t | +val2, | +
| + | + | uint32_t | +val3 | +
| + | ) | ++ |
+
+This function enables you to perform four unsigned 8-bit subtractions, and add the absolute values of the differences to a 32-bit accumulate operand.
+- Parameters:
-
+
+
+val1 first four 8-bit operands for the subtractions. val2 second four 8-bit operands for the subtractions. val3 accumulation value.
+
- Returns:
- the sum of the absolute differences of the following bytes, added to the accumulation value:
-
+
- the subtraction of the first byte in the second operand from the first byte in the first operand. +
- the subtraction of the second byte in the second operand from the second byte in the first operand. +
- the subtraction of the third byte in the second operand from the third byte in the first operand. +
- the subtraction of the fourth byte in the second operand from the fourth byte in the first operand. +
- Operation:
absdiff1 = val1[7:0] - val2[7:0] + absdiff2 = val1[15:8] - val2[15:8] + absdiff3 = val1[23:16] - val2[23:16] + absdiff4 = val1[31:24] - val2[31:24] + sum = absdiff1 + absdiff2 + absdiff3 + absdiff4 + res[31:0] = sum[31:0] + val3[31:0] +
+
+
+
+
+
+
+| uint32_t __USAT16 | +( | +uint32_t | +val1, | +
| + | + | const uint32_t | +val2 | +
| + | ) | ++ |
+
+This function enables you to saturate two signed 16-bit values to a selected unsigned range.
+ The Q bit is set if either operation saturates.
- Parameters:
-
+
+
+val1 two 16-bit values that are to be saturated. val2 bit position for saturation, and must be an integral constant expression in the range 0 to 15.
+
- Returns:
- the saturation of the two signed 16-bit values, as non-negative values.
-
+
- the saturation of the low halfword in val1, saturated to the bit position specified in val2 and returned in the low halfword of the return value. +
- the saturation of the high halfword in val1, saturated to the bit position specified in val2 and returned in the high halfword of the return value. +
- Operation:
Saturate halfwords in val1 to the unsigned range specified by the bit position in val2 +
+
+
+
+
+
+
+| uint32_t __USAX | +( | +uint32_t | +val1, | +
| + | + | uint32_t | +val2 | +
| + | ) | ++ |
+
+This function enables you to exchange the halfwords of the second operand, subtract the high halfwords and add the low halfwords.
+ The GE bits in the APSR are set according to the results.
- Parameters:
-
+
+
+val1 first operand for the addition in the low halfword, and the first operand for the subtraction in the high halfword. val2 second operand for the addition in the high halfword, and the second operand for the subtraction in the low halfword.
+
- Returns:
-
+
- the addition of the low halfword in the first operand and the high halfword in the second operand, in the low halfword of the return value. +
- the subtraction of the low halfword in the second operand from the high halfword in the first operand, in the high halfword of the return value. +
- Each bit in APSR.GE is set or cleared for each byte in the return value, depending on the results of the operation.
- If res is the return value, then:
-
+
- if res[15:0] >= 0x10000 then APSR.GE[1:0] = 11 else 00 +
- if res[31:16] >= 0 then APSR.GE[3:2] = 11 else 00 +
- Operation:
res[15:0] = val1[15:0] + val2[31:16] + res[31:16] = val1[31:16] - val2[15:0] +
+
+
+
+
+
+
+| uint32_t __USUB16 | +( | +uint32_t | +val1, | +
| + | + | uint32_t | +val2 | +
| + | ) | ++ |
+
+This function enables you to perform two 16-bit unsigned integer subtractions.
+ The GE bits in the APSR are set according to the results.
- Parameters:
-
+
+
+val1 first two 16-bit operands. val2 second two 16-bit operands.
+
- Returns:
-
+
- the subtraction of the low halfword in the second operand from the low halfword in the first operand, in the low halfword of the return value. +
- the subtraction of the high halfword in the second operand from the high halfword in the first operand, in the high halfword of the return value. +
- Each bit in APSR.GE is set or cleared for each byte in the return value, depending on the results of the operation.
- If res is the return value, then:
-
+
- if res[15:0] >= 0 then APSR.GE[1:0] = 11 else 00 +
- if res[31:16] >= 0 then APSR.GE[3:2] = 11 else 00 +
- Operation:
res[15:0] = val1[15:0] - val2[15:0] + res[31:16] = val1[31:16] - val2[31:16] +
+
+
+
+
+
+
+| uint32_t __USUB8 | +( | +uint32_t | +val1, | +
| + | + | uint32_t | +val2 | +
| + | ) | ++ |
+
+This function enables you to perform four 8-bit unsigned integer subtractions. The GE bits in the APSR are set according to the results.
+- Parameters:
-
+
+
+val1 first four 8-bit operands. val2 second four 8-bit operands.
+
- Returns:
-
+
- the subtraction of the first byte in the second operand from the first byte in the first operand, in the first bytes of the return value. +
- the subtraction of the second byte in the second operand from the second byte in the first operand, in the second byte of the return value. +
- the subtraction of the third byte in the second operand from the third byte in the first operand, in the third byte of the return value. +
- the subtraction of the fourth byte in the second operand from the fourth byte in the first operand, in the fourth byte of the return value. +
- Each bit in APSR.GE is set or cleared for each byte in the return value, depending on the results of the operation.
- If res is the return value, then:
-
+
- if res[8:0] >= 0 then APSR.GE[0] = 1 else 0 +
- if res[15:8] >= 0 then APSR.GE[1] = 1 else 0 +
- if res[23:16] >= 0 then APSR.GE[2] = 1 else 0 +
- if res[31:24] >= 0 then APSR.GE[3] = 1 else 0 +
- Operation:
res[7:0] = val1[7:0] - val2[7:0] + res[15:8] = val1[15:8] - val2[15:8] + res[23:16] = val1[23:16] - val2[23:16] + res[31:24] = val1[31:24] - val2[31:24] +
+
+
+
+
+
+
+| uint32_t __UXTAB16 | +( | +uint32_t | +val1, | +
| + | + | uint32_t | +val2 | +
| + | ) | ++ |
+
+This function enables you to extract two 8-bit values from one operand, zero-extend them to 16 bits each, and add the results to two 16-bit values from another operand.
+- Parameters:
-
+
+
+val1 value added to the zero-extended to 16-bit values. val2 two 8-bit values to be extracted and zero-extended.
+
- Returns:
- the 8-bit values in val2, zero-extended to 16-bit values and added to val1.
- Operation:
res[15:0] = ZeroExt(val2[7:0] to 16 bits) + val1[15:0] + res[31:16] = ZeroExt(val2[31:16] to 16 bits) + val1[31:16] +
+
+
+
+
+
+| uint32_t __UXTB16 | +( | +uint32_t | +val | ) | ++ |
+
+This function enables you to extract two 8-bit values from an operand and zero-extend them to 16 bits each.
+- Parameters:
-
+
+
+val two 8-bit values in val[7:0] and val[23:16] to be sign-extended.
+
- Returns:
- the 8-bit values zero-extended to 16-bit values.
-
+
- zero-extended value of val[7:0] in the low halfword of the return value. +
- zero-extended value of val[23:16] in the high halfword of the return value. +
- Operation:
res[15:0] = ZeroExtended(val[7:0] ) + res[31:16] = ZeroExtended(val[23:16]) +
+
+
+
+
+
+
+
+
+
+
+
+
+
+ |
+
+
+ CMSIS-CORE
+ Version 3.01
+
+ CMSIS-CORE support for Cortex-M processor-based devices
+ |
+
+
+
+
+
+-
+
- Main Page +
- Usage and Description +
- Reference +
-
+ + ++
+
+
+
+
+
+
+
+
+
+
+
+
diff --git a/Libraries/CMSIS/Documentation/Core/html/group__system__init__gr.html b/Libraries/CMSIS/Documentation/Core/html/group__system__init__gr.html
new file mode 100644
index 0000000..c2fa9b3
--- /dev/null
+++ b/Libraries/CMSIS/Documentation/Core/html/group__system__init__gr.html
@@ -0,0 +1,228 @@
+
+
+
+
+
+
+
+
+Peripheral Access
+
+
+
+
+Describes naming conventions, requirements, and optional features for accessing peripherals. +More...
+Each peripheral provides a data type definition with a name that is composed of a prefix <device abbreviation>_ and the <peripheral name>_, for example LPC_UART for the device LPC and the peripheral UART. The intention is to avoid name collisions caused by short names. If more peripherals exist of the same type, identifiers have a postfix consisting of a digit or letter, for example LPC_UART0, LPC_UART1.
+-
+
- The data type definition uses the standard C data types from the ANSI C header file <stdint.h>. IO Type Qualifiers are used to specify the access to peripheral variables. IO Type Qualifiers are indented to be used for automatic generation of debug information of peripheral registers and are defined as shown below:
+#define __I volatile const + #define __O volatile + #define __IO volatile +
+
-
+
- The following typedef is an example for a UART. <device abbreviation>_UART_TypeDef: defines the generic register layout for all UART channels in a device.
+typedef struct +{ + union { + __I uint8_t RBR; /* Offset: 0x000 (R/ ) Receiver Buffer Register */ + __O uint8_t THR; /* Offset: 0x000 ( /W) Transmit Holding Register */ + __IO uint8_t DLL; /* Offset: 0x000 (R/W) Divisor Latch LSB */ + uint32_t RESERVED0; + }; + union { + __IO uint8_t DLM; /* Offset: 0x004 (R/W) Divisor Latch MSB */ + __IO uint32_t IER; /* Offset: 0x004 (R/W) Interrupt Enable Register */ + }; + union { + __I uint32_t IIR; /* Offset: 0x008 (R/ ) Interrupt ID Register */ + __O uint8_t FCR; /* Offset: 0x008 ( /W) FIFO Control Register */ + }; + __IO uint8_t LCR; /* Offset: 0x00C (R/W) Line Control Register */ + uint8_t RESERVED1[7]; + __I uint8_t LSR; /* Offset: 0x014 (R/ ) Line Status Register */ + uint8_t RESERVED2[7]; + __IO uint8_t SCR; /* Offset: 0x01C (R/W) Scratch Pad Register */ + uint8_t RESERVED3[3]; + __IO uint32_t ACR; /* Offset: 0x020 (R/W) Autobaud Control Register */ + __IO uint8_t ICR; /* Offset: 0x024 (R/W) IrDA Control Register */ + uint8_t RESERVED4[3]; + __IO uint8_t FDR; /* Offset: 0x028 (R/W) Fractional Divider Register */ + uint8_t RESERVED5[7]; + __IO uint8_t TER; /* Offset: 0x030 (R/W) Transmit Enable Register */ + uint8_t RESERVED6[39]; + __I uint8_t FIFOLVL; /* Offset: 0x058 (R/ ) FIFO Level Register */ +} LPC_UART_TypeDef; +
+
-
+
- To access the registers of the UART defined above, pointers to a register structure are defined. In this example <device abbreviation>_UART# are two pointers to UARTs defined with above register structure.
+#define LPC_UART2 ((LPC_UART_TypeDef *) LPC_UART2_BASE ) +#define LPC_UART3 ((LPC_UART_TypeDef *) LPC_UART3_BASE ) +
+
-
+
- The registers in the various UARTs can now be referred in the user code as shown below:
+LPC_UART1->DR // is the data register of UART1. +
+
+
+Minimal Requirements
+To access the peripheral registers and related function in a device, the files device.h and core_cm#.h define as a minimum:
+
+
-
+
- The Register Layout Typedef for each peripheral that defines all register names. RESERVED is used to introduce space into the structure for adjusting the addresses of the peripheral registers.
+
+ Example:typedef struct +{ + __IO uint32_t CTRL; /* Offset: 0x000 (R/W) SysTick Control and Status Register */ + __IO uint32_t LOAD; /* Offset: 0x004 (R/W) SysTick Reload Value Register */ + __IO uint32_t VAL; /* Offset: 0x008 (R/W) SysTick Current Value Register */ + __I uint32_t CALIB; /* Offset: 0x00C (R/ ) SysTick Calibration Register */ +} SysTick_Type; +
+
-
+
- Base Address for each peripheral (in case of multiple peripherals that use the same register layout typedef multiple base addresses are defined).
+
+ Example:#define SysTick_BASE (SCS_BASE + 0x0010) /* SysTick Base Address */ +
+
-
+
- Access Definitions for each peripheral. In case of multiple peripherals that are using the same register layout typdef, multiple access definitions exist (LPC_UART0, LPC_UART2).
+
+ Example:#define SysTick ((SysTick_Type *) Systick_BASE) /* SysTick access definition */ +
+
These definitions allow accessing peripheral registers with simple assignments.
+Example:
+
SysTick->CTRL = 0; +
+
+Optional Features
+Optionally, the file device.h may define:
+-
+
- #define constants, which simplify access to peripheral registers. These constants define bit-positions or other specific patterns that are required for programming peripheral registers. The identifiers start with <device abbreviation>_ and <peripheral name>_. It is recommended to use CAPITAL letters for such #define constants. +
-
+
- More complex functions (i.e. status query before a sending register is accessed). Again, these functions start with <device abbreviation>_ and <peripheral name>_. +
+
+
+
+
+
+
+
+
+
+
+
+
+
+ |
+
+
+ CMSIS-CORE
+ Version 3.01
+
+ CMSIS-CORE support for Cortex-M processor-based devices
+ |
+
+
+
+
+
+-
+
- Main Page +
- Usage and Description +
- Reference +
-
+ + ++
+
+
+
+
+
+
+
+
+
+
+
+
+
diff --git a/Libraries/CMSIS/Documentation/Core/html/index.html b/Libraries/CMSIS/Documentation/Core/html/index.html
new file mode 100644
index 0000000..0b4beec
--- /dev/null
+++ b/Libraries/CMSIS/Documentation/Core/html/index.html
@@ -0,0 +1,205 @@
+
+
+
+
+
+
+
+
++Variables | |
| uint32_t | SystemCoreClock |
| Variable to hold the system core clock value. | |
+Functions | |
| void | SystemInit (void) |
| Function to Initialize the system. | |
| void | SystemCoreClockUpdate (void) |
| Function to update the variable SystemCoreClock. | |
Description
+ARM provides a template file system_device.c that must be adapted by the silicon vendor to match their actual device. As a minimum requirement, this file must provide:
+-
+
- A device-specific system configuration function, SystemInit(). +
- A global variable that contains the system frequency, SystemCoreClock. +
The file configures the device and, typically, initializes the oscillator (PLL) that is part of the microcontroller device. This file might export other functions or variables that provide a more flexible configuration of the microcontroller system.
++Code Example
+The code below shows the usage of the variable SystemCoreClock and the functions SystemInit() and SystemCoreClockUpdate() with an LPC1700.
+#include "LPC17xx.h" + +uint32_t coreClock_1 = 0; /* Variables to store core clock values */ +uint32_t coreClock_2 = 0; + + +int main (void) { + + coreClock_1 = SystemCoreClock; /* Store value of predefined SystemCoreClock */ + + SystemCoreClockUpdate(); /* Update SystemCoreClock according to register settings */ + + coreClock_2 = SystemCoreClock; /* Store value of calculated SystemCoreClock */ + + if (coreClock_2 != coreClock_1) { /* Without changing the clock setting both core clock values should be the same */ + // Error Handling + } + + while(1); +} +
Variable Documentation
+ +
+
+
+
+
+
+| uint32_t SystemCoreClock | +
+
+Holds the system core clock, which is the system clock frequency supplied to the SysTick timer and the processor core clock. This variable can be used by debuggers to query the frequency of the debug timer or to configure the trace clock speed.
+- Attention:
- Compilers must be configured to avoid removing this variable in case the application program is not using it. Debugging systems require the variable to be physically present in memory so that it can be examined to configure the debugger.
Function Documentation
+ +
+
+
+
+
+
+
+| void SystemCoreClockUpdate | +( | +void | +) | ++ |
+
+Updates the variable SystemCoreClock and must be called whenever the core clock is changed during program execution. The function evaluates the clock register settings and calculates the current core clock.
+ +
+
+
+
+
+
+| void SystemInit | +( | +void | +) | ++ |
+
+Initializes the microcontroller system. Typically, this function configures the oscillator (PLL) that is part of the microcontroller device. For systems with a variable clock speed, it updates the variable SystemCoreClock. SystemInit is called from the file startup_device.
+ +
+
+
+
+
+
+
+
+
+
+
+
+
+
+ |
+
+
+ CMSIS-CORE
+ Version 3.01
+
+ CMSIS-CORE support for Cortex-M processor-based devices
+ |
+
+
+
+
+
+-
+
- Main Page +
- Usage and Description +
- Reference +
-
+ + ++
+
+
+
+
+
+
+
+
+
+
+
+
diff --git a/Libraries/CMSIS/Documentation/Core/html/installdox b/Libraries/CMSIS/Documentation/Core/html/installdox
new file mode 100644
index 0000000..edf5bbf
--- /dev/null
+++ b/Libraries/CMSIS/Documentation/Core/html/installdox
@@ -0,0 +1,112 @@
+#!/usr/bin/perl
+
+%subst = ( );
+$quiet = 0;
+
+while ( @ARGV ) {
+ $_ = shift @ARGV;
+ if ( s/^-// ) {
+ if ( /^l(.*)/ ) {
+ $v = ($1 eq "") ? shift @ARGV : $1;
+ ($v =~ /\/$/) || ($v .= "/");
+ $_ = $v;
+ if ( /(.+)\@(.+)/ ) {
+ if ( exists $subst{$1} ) {
+ $subst{$1} = $2;
+ } else {
+ print STDERR "Unknown tag file $1 given with option -l\n";
+ &usage();
+ }
+ } else {
+ print STDERR "Argument $_ is invalid for option -l\n";
+ &usage();
+ }
+ }
+ elsif ( /^q/ ) {
+ $quiet = 1;
+ }
+ elsif ( /^\?|^h/ ) {
+ &usage();
+ }
+ else {
+ print STDERR "Illegal option -$_\n";
+ &usage();
+ }
+ }
+ else {
+ push (@files, $_ );
+ }
+}
+
+foreach $sub (keys %subst)
+{
+ if ( $subst{$sub} eq "" )
+ {
+ print STDERR "No substitute given for tag file `$sub'\n";
+ &usage();
+ }
+ elsif ( ! $quiet && $sub ne "_doc" && $sub ne "_cgi" )
+ {
+ print "Substituting $subst{$sub} for each occurrence of tag file $sub\n";
+ }
+}
+
+if ( ! @files ) {
+ if (opendir(D,".")) {
+ foreach $file ( readdir(D) ) {
+ $match = ".html";
+ next if ( $file =~ /^\.\.?$/ );
+ ($file =~ /$match/) && (push @files, $file);
+ ($file =~ /\.svg/) && (push @files, $file);
+ ($file =~ "navtree.js") && (push @files, $file);
+ }
+ closedir(D);
+ }
+}
+
+if ( ! @files ) {
+ print STDERR "Warning: No input files given and none found!\n";
+}
+
+foreach $f (@files)
+{
+ if ( ! $quiet ) {
+ print "Editing: $f...\n";
+ }
+ $oldf = $f;
+ $f .= ".bak";
+ unless (rename $oldf,$f) {
+ print STDERR "Error: cannot rename file $oldf\n";
+ exit 1;
+ }
+ if (open(F,"<$f")) {
+ unless (open(G,">$oldf")) {
+ print STDERR "Error: opening file $oldf for writing\n";
+ exit 1;
+ }
+ if ($oldf ne "tree.js") {
+ while (
+
+
+
+Overview
+
+
+
+
+
+
+
+CMSIS-CORE implements the basic run-time system for a Cortex-M device and gives the user access to the processor core and the device peripherals. In detail it defines:
+-
+
- Hardware Abstraction Layer (HAL) for Cortex-M processor registers with standardized definitions for the SysTick, NVIC, System Control Block registers, MPU registers, FPU registers, and core access functions. +
- System exception names to interface to system exceptions without having compatibility issues. +
- Methods to organize header files that makes it easy to learn new Cortex-M microcontroller products and improve software portability. This includes naming conventions for device-specific interrupts. +
- Methods for system initialization to be used by each MCU vendor. For example, the standardized SystemInit() function is essential for configuring the clock system of the device. +
- Intrinsic functions used to generate CPU instructions that are not supported by standard C functions. +
- A variable to determine the system clock frequency which simplifies the setup the SysTick timer. +
+
This chapter provides details about the CMSIS-CORE and contains the following sections:
+-
+
- Using CMSIS in Embedded Applications describes the project setup and shows a simple program example. +
- Template Files describes the files of the CMSIS-CORE in detail and explains how to adapt template files provided by ARM to silicon vendor devices. +
- MISRA-C:2004 Compliance Exceptions describes the violations to the MISRA standard. +
- Reference describe the features and functions of the Device Header File <device.h> in detail. +
- Data Structures describe the data structures of the Device Header File <device.h> in detail. +
+
+Cortex-M Reference Manuals
+The Cortex-M Reference Manuals are generic user guides for devices that implement the various ARM Cortex-M processors. These manuals contain the programmers model and detailed information about the core peripherals.
+-
+
- Cortex-M0 Devices Generic User Guide +
- Cortex-M3 Devices Generic User Guide +
- Cortex-M4 Devices Generic User Guide +
+
+Tested and Verified Toolchains
+The CMSIS-CORE Template Files supplied by ARM have been tested and verified with the following toolchains:
+-
+
- ARM: MDK-ARM Version 4.13a (or greater) +
- GNU: GCC ARM Embedded 2011-q4-major (or greater) +
- GNU: Sourcery G++ Lite Edition for ARM 2010.09-51 (or greater) +
- IAR: IAR Embedded Workbench Kickstart Edition V6.10 (or greater) +
+
Revision History of CMSIS-CORE
+| Version | Description |
|---|---|
| V3.01 | Added support for Cortex-M0+ processor. + Integration of CMSIS DSP Library version 1.1.0 + |
| V3.00 | Added support for GNU GCC ARM Embedded Compiler. + Added function __ROR. + Added Register Mapping for TPIU, DWT. + Added support for SC000 and SC300 processors. + Corrected ITM_SendChar function. + Corrected the functions __STREXB, __STREXH, __STREXW for the GNU GCC compiler section. + Documentation restructured. |
| V2.10 | Updated documentation. + Updated CMSIS core include files. + Changed CMSIS/Device folder structure. + Added support for Cortex-M0, Cortex-M4 w/o FPU to CMSIS DSP library. + Reworked CMSIS DSP library examples. |
| V2.00 | Added support for Cortex-M4 processor. |
| V1.30 | Reworked Startup Concept. + Added additional Debug Functionality. + Changed folder structure. + Added doxygen comments. + Added definitions for bit. |
| V1.01 | Added support for Cortex-M0 processor. |
| V1.01 | Added intrinsic functions for __LDREXB, __LDREXH, __LDREXW, __STREXB, __STREXH, __STREXW, and __CLREX |
| V1.00 | Initial Release for Cortex-M3 processor. |
","
"]||[0,"",""];L.innerHTML=Q[1]+S+Q[2];while(Q[0]--){L=L.lastChild}if(!o.support.tbody){var R=/"&&!R?L.childNodes:[];for(var M=N.length-1;M>=0;--M){if(o.nodeName(N[M],"tbody")&&!N[M].childNodes.length){N[M].parentNode.removeChild(N[M])}}}if(!o.support.leadingWhitespace&&/^\s/.test(S)){L.insertBefore(K.createTextNode(S.match(/^\s*/)[0]),L.firstChild)}S=o.makeArray(L.childNodes)}if(S.nodeType){G.push(S)}else{G=o.merge(G,S)}});if(I){for(var J=0;G[J];J++){if(o.nodeName(G[J],"script")&&(!G[J].type||G[J].type.toLowerCase()==="text/javascript")){E.push(G[J].parentNode?G[J].parentNode.removeChild(G[J]):G[J])}else{if(G[J].nodeType===1){G.splice.apply(G,[J+1,0].concat(o.makeArray(G[J].getElementsByTagName("script"))))}I.appendChild(G[J])}}return E}return G},attr:function(J,G,K){if(!J||J.nodeType==3||J.nodeType==8){return g}var H=!o.isXMLDoc(J),L=K!==g;G=H&&o.props[G]||G;if(J.tagName){var F=/href|src|style/.test(G);if(G=="selected"&&J.parentNode){J.parentNode.selectedIndex}if(G in J&&H&&!F){if(L){if(G=="type"&&o.nodeName(J,"input")&&J.parentNode){throw"type property can't be changed"}J[G]=K}if(o.nodeName(J,"form")&&J.getAttributeNode(G)){return J.getAttributeNode(G).nodeValue}if(G=="tabIndex"){var I=J.getAttributeNode("tabIndex");return I&&I.specified?I.value:J.nodeName.match(/(button|input|object|select|textarea)/i)?0:J.nodeName.match(/^(a|area)$/i)&&J.href?0:g}return J[G]}if(!o.support.style&&H&&G=="style"){return o.attr(J.style,"cssText",K)}if(L){J.setAttribute(G,""+K)}var E=!o.support.hrefNormalized&&H&&F?J.getAttribute(G,2):J.getAttribute(G);return E===null?g:E}if(!o.support.opacity&&G=="opacity"){if(L){J.zoom=1;J.filter=(J.filter||"").replace(/alpha\([^)]*\)/,"")+(parseInt(K)+""=="NaN"?"":"alpha(opacity="+K*100+")")}return J.filter&&J.filter.indexOf("opacity=")>=0?(parseFloat(J.filter.match(/opacity=([^)]*)/)[1])/100)+"":""}G=G.replace(/-([a-z])/ig,function(M,N){return N.toUpperCase()});if(L){J[G]=K}return J[G]},trim:function(E){return(E||"").replace(/^\s+|\s+$/g,"")},makeArray:function(G){var E=[];if(G!=null){var F=G.length;if(F==null||typeof G==="string"||o.isFunction(G)||G.setInterval){E[0]=G}else{while(F){E[--F]=G[F]}}}return E},inArray:function(G,H){for(var E=0,F=H.length;E
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+