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Libraries/CMSIS/Include/core_cm4.h | 1757 ++++ Libraries/CMSIS/Include/core_cm4_simd.h | 649 ++ Libraries/CMSIS/Include/core_cmFunc.h | 616 ++ Libraries/CMSIS/Include/core_cmInstr.h | 618 ++ Libraries/CMSIS/Include/core_sc000.h | 798 ++ Libraries/CMSIS/Include/core_sc300.h | 1583 ++++ Libraries/CMSIS/README.txt | 37 + Libraries/CMSIS/RTOS/cmsis_os.h | 717 ++ Libraries/CMSIS/SVD/ARM_Sample.svd | 739 ++ Libraries/CMSIS/SVD/ARM_Sample_1_1.svd | 763 ++ Libraries/CMSIS/SVD/CMSIS-SVD_Schema_1_0.xsd | 274 + .../CMSIS/SVD/CMSIS-SVD_Schema_1_1_draft.xsd | 509 + Libraries/CMSIS/SVD/SVDConv.exe | Bin 0 -> 321536 bytes Libraries/CMSIS/index.html | 14 + .../Release_Notes.html | 340 + .../STM32F10x_StdPeriph_Driver/inc/misc.h | 226 + .../inc/stm32f10x_adc.h | 489 + .../inc/stm32f10x_bkp.h | 201 + .../inc/stm32f10x_can.h | 703 ++ .../inc/stm32f10x_cec.h | 216 + .../inc/stm32f10x_crc.h | 100 + .../inc/stm32f10x_dac.h | 323 + .../inc/stm32f10x_dbgmcu.h | 125 + .../inc/stm32f10x_dma.h | 445 + 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.../STM32_USB-FS-Device_Driver/src/usb_regs.c | 760 ++ .../STM32_USB-FS-Device_Driver/src/usb_sil.c | 103 + Project/MDK-ARM/.vscode/c_cpp_properties.json | 207 + Project/MDK-ARM/.vscode/keil-assistant.log | 18 + Project/MDK-ARM/.vscode/settings.json | 9 + Project/MDK-ARM/.vscode/uv4.log | 3 + Project/MDK-ARM/.vscode/uv4.log.lock | 1 + Project/MDK-ARM/CpuRAM.ini | 31 + Project/MDK-ARM/EventRecorderStub.scvd | 9 + Project/MDK-ARM/Flash/List/bsp.txt | 149 + Project/MDK-ARM/Flash/List/bsp_adc.txt | 0 Project/MDK-ARM/Flash/List/bsp_beep.txt | 323 + .../MDK-ARM/Flash/List/bsp_channel_realy.txt | 238 + .../MDK-ARM/Flash/List/bsp_digital_tube.txt | 1168 +++ Project/MDK-ARM/Flash/List/bsp_drv8880.txt | 565 ++ .../MDK-ARM/Flash/List/bsp_eeprom_24xx.txt | 367 + Project/MDK-ARM/Flash/List/bsp_fpga_power.txt | 158 + Project/MDK-ARM/Flash/List/bsp_i2c_gpio.txt | 505 + Project/MDK-ARM/Flash/List/bsp_key.txt | 748 ++ Project/MDK-ARM/Flash/List/bsp_led.txt | 969 ++ Project/MDK-ARM/Flash/List/bsp_res.txt | 349 + Project/MDK-ARM/Flash/List/bsp_step_moto.txt | 562 ++ Project/MDK-ARM/Flash/List/bsp_tim_pwm.txt | 1447 +++ Project/MDK-ARM/Flash/List/bsp_timer.txt | 1323 +++ Project/MDK-ARM/Flash/List/bsp_uart_fifo.txt | 1587 ++++ Project/MDK-ARM/Flash/List/bsp_usart_dma.txt | 555 ++ .../MDK-ARM/Flash/List/demo_i2c_eeprom.txt | 640 ++ Project/MDK-ARM/Flash/List/main.txt | 1673 ++++ Project/MDK-ARM/Flash/List/misc.txt | 249 + Project/MDK-ARM/Flash/List/stm32f10x_adc.txt | 1535 +++ .../MDK-ARM/Flash/List/stm32f10x_assert.txt | 29 + Project/MDK-ARM/Flash/List/stm32f10x_dac.txt | 522 + Project/MDK-ARM/Flash/List/stm32f10x_dma.txt | 744 ++ Project/MDK-ARM/Flash/List/stm32f10x_gpio.txt | 887 ++ Project/MDK-ARM/Flash/List/stm32f10x_it.txt | 197 + Project/MDK-ARM/Flash/List/stm32f10x_rcc.txt | 1392 +++ Project/MDK-ARM/Flash/List/stm32f10x_tim.txt | 4144 ++++++++ .../MDK-ARM/Flash/List/stm32f10x_usart.txt | 1316 +++ .../MDK-ARM/Flash/List/system_stm32f10x.txt | 582 ++ Project/MDK-ARM/Flash/Obj/output.hex | 1181 +++ Project/MDK-ARM/RTE/_Flash/RTE_Components.h | 21 + Project/MDK-ARM/keilkilll.bat | 27 + .../MDK-ARM/pemicro_connection_settings.ini | 3 + ...CNR的冲突副本 2019-01-09_22.44.23).microsoft | 1815 ++++ Project/MDK-ARM/project.uvgui.microsoft | 1762 ++++ Project/MDK-ARM/project.uvguix.28906 | 3799 ++++++++ Project/MDK-ARM/project.uvguix.Multi | 1941 ++++ Project/MDK-ARM/project.uvguix.Multi_Field_03 | 3511 +++++++ Project/MDK-ARM/project.uvguix.ShenJianxin | 1896 ++++ Project/MDK-ARM/project.uvguix.lianghao | 3799 ++++++++ Project/MDK-ARM/project.uvguix.w1619 | 1995 ++++ Project/MDK-ARM/project.uvguix.wangx | 1846 ++++ Project/MDK-ARM/project.uvopt | 955 ++ Project/MDK-ARM/project.uvoptx | 1060 +++ Project/MDK-ARM/project.uvproj.saved_uv4 | 1132 +++ Project/MDK-ARM/project.uvprojx | 1100 +++ Project/MDK-ARM/说明.txt | 9 + Project/bin_file/Update.bin | Bin 0 -> 18848 bytes User/app/inc/demo_i2c_eeprom.h | 22 + User/app/inc/main.h | 21 + User/app/src/demo_i2c_eeprom.c | 215 + User/app/src/main-MF-MC-Design03.c | 547 ++ User/app/src/main.c | 447 + User/bsp/bsp.c | 117 + User/bsp/bsp.h | 83 + User/bsp/inc/bsp_beep.h | 39 + User/bsp/inc/bsp_channel_realy.h | 29 + User/bsp/inc/bsp_digital_tube.h | 76 + User/bsp/inc/bsp_drv8880.h | 45 + User/bsp/inc/bsp_eeprom_24xx.h | 56 + User/bsp/inc/bsp_fpga_power.h | 29 + User/bsp/inc/bsp_i2c_gpio.h | 30 + User/bsp/inc/bsp_key.h | 177 + User/bsp/inc/bsp_led.h | 31 + User/bsp/inc/bsp_res.h | 41 + User/bsp/inc/bsp_step_moto.h | 50 + User/bsp/inc/bsp_tim_pwm.h | 29 + User/bsp/inc/bsp_timer.h | 55 + User/bsp/inc/bsp_usart_dma.h | 47 + User/bsp/src/bsp_adc.c | 93 + User/bsp/src/bsp_adc.h | 10 + User/bsp/src/bsp_beep.c | 189 + User/bsp/src/bsp_digital_tube.c | 454 + User/bsp/src/bsp_drv8880.c | 268 + User/bsp/src/bsp_eeprom_24xx.c | 236 + User/bsp/src/bsp_i2c_gpio.c | 305 + User/bsp/src/bsp_key.c | 496 + User/bsp/src/bsp_led.c | 445 + User/bsp/src/bsp_res.c | 162 + User/bsp/src/bsp_step_moto.c | 250 + User/bsp/src/bsp_tim_pwm.c | 671 ++ User/bsp/src/bsp_timer.c | 673 ++ User/bsp/src/bsp_usart_dma.c | 214 + User/bsp/stm32f10x_assert.c | 58 + User/bsp/stm32f10x_conf.h | 72 + User/bsp/stm32f10x_it.c | 217 + User/bsp/stm32f10x_it.h | 35 + User/bsp/system_stm32f10x.c | 1094 +++ User/bsp/system_stm32f10x.h | 98 + keilkill.bat | 30 + 624 files changed, 214375 insertions(+) create mode 100644 CLAUDE.md create mode 100644 Doc/01.例程功能说明.txt create mode 100644 Doc/02.开发环境说明.txt create mode 100644 Libraries/CMSIS/CMSIS END USER LICENCE AGREEMENT.pdf create mode 100644 Libraries/CMSIS/Device/ST/STM32F10x/Include/stm32f10x.h create mode 100644 Libraries/CMSIS/Device/ST/STM32F10x/Include/system_stm32f10x.h create mode 100644 Libraries/CMSIS/Device/ST/STM32F10x/Release_Notes.html create mode 100644 Libraries/CMSIS/Device/ST/STM32F10x/Source/Templates/TASKING/cstart_thumb2.asm create mode 100644 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User/bsp/src/bsp_key.c create mode 100644 User/bsp/src/bsp_led.c create mode 100644 User/bsp/src/bsp_res.c create mode 100644 User/bsp/src/bsp_step_moto.c create mode 100644 User/bsp/src/bsp_tim_pwm.c create mode 100644 User/bsp/src/bsp_timer.c create mode 100644 User/bsp/src/bsp_usart_dma.c create mode 100644 User/bsp/stm32f10x_assert.c create mode 100644 User/bsp/stm32f10x_conf.h create mode 100644 User/bsp/stm32f10x_it.c create mode 100644 User/bsp/stm32f10x_it.h create mode 100644 User/bsp/system_stm32f10x.c create mode 100644 User/bsp/system_stm32f10x.h create mode 100644 keilkill.bat diff --git a/CLAUDE.md b/CLAUDE.md new file mode 100644 index 0000000..21cf074 --- /dev/null +++ b/CLAUDE.md @@ -0,0 +1,119 @@ +# CLAUDE.md + +This file provides guidance to Claude Code (claude.ai/code) when working with code in this repository. + +## 项目概述 + +基于 **STM32F103ZET6**（ARM Cortex-M3，72MHz，512KB Flash，64KB SRAM）的 **MFT 步进电机控制器** 固件。应用程序通过 **DRV8880 驱动芯片** 控制步进电机，支持 UART 串口命令接口和数码管显示。 + +代码源自 **安富莱 STM32-V4** 开发板 BSP 模板。 + +## 内存布局 + +| 区域 | 地址范围 | 说明 | +|------|----------|------| +| Bootloader | 0x0800 0000 - 0x0800 7FFF | 32KB IAP 引导程序 | +| 应用程序 | 0x0800 8000 - 0x080F FFFF | 主固件（约 480KB） | +| SRAM1 | 0x2000 0000 - 0x2000 FFFF | 64KB 内部 RAM | + +**重要**：`main()` 中 `SCB->VTOR = 0x08008000` 设置应用程序的中断向量表偏移。 + +## 构建系统 + +这是一个 **Keil MDK / IAR EWARM** 项目，没有 Makefile 或 CMake。需要在 IDE 中构建： + +### Keil MDK +- 工程文件：`Project/MDK-ARM/project.uvprojx` +- 两个 Target：**Flash**（从内部 Flash 运行）和 **CpuRAM**（从 RAM 运行，用于调试） +- 输出文件：`Project/output(mdk).hex` +- VS Code C/C++ 配置在 `Project/MDK-ARM/.vscode/c_cpp_properties.json`，包含头文件路径和宏定义 + +### IAR EWARM +- 工作区：`Project/EWARMv6/Project.www` +- 输出文件：`Project/output(iar).hex` + +### 编译器宏定义 +- `USE_STDPERIPH_DRIVER` — 启用 ST 标准外设库 +- `STM32F10X_HD` — 大容量器件（512KB Flash） +- `VECT_TAB_SRAM` — 仅用于 RAM 调试目标 + +### 栈/堆大小 +在启动汇编文件中配置（`Stack_Size EQU 0x00008000`，`Heap_Size EQU 0x00000400`）。 + +## 代码架构 + +``` +Motor/ +├── Bootloader/ # IAP 引导程序（独立工程，基于 ST HAL 库） +│ ├── Drivers/ # BSP（LCD、LED、KEY、STMFLASH、数码管） +│ ├── Middlewares/ # 第三方库 +│ └── User/ # 引导程序应用代码 +├── Libraries/ # ST/ARM 提供的库（不要修改） +│ ├── CMSIS/ # ARM CMSIS 头文件 + startup_stm32f103xe.s +│ ├── STM32F10x_StdPeriph_Driver/ # 标准外设库 +│ └── STM32_USB-FS-Device_Driver/ # USB Device 库 +├── User/ # 应用源代码（主要工作区） +│ ├── app/ # 应用层 +│ │ ├── src/main.c # 入口、电机控制逻辑、UART 命令解析 +│ │ └── inc/main.h # 应用头文件 +│ └── bsp/ # 板级支持包（硬件抽象层） +│ ├── bsp.c/h # BSP 初始化、周期定时器（1ms/10ms）、空闲循环 +│ ├── src/ # BSP 驱动实现 +│ └── inc/ # BSP 驱动头文件 +├── Project/ # IDE 工程文件 + 构建输出 +│ ├── MDK-ARM/ # Keil MDK 工程 +│ ├── EWARMv6/ # IAR EWARM 工作区 +│ └── bin_file/ # 生成的二进制文件 +└── Doc/ # 文档（中文） +``` + +## 关键源文件 + +| 文件 | 功能 | +|------|------| +| `User/app/src/main.c` | 主入口、UART 命令解析、电机控制状态机 | +| `User/bsp/bsp.c` | 硬件初始化、周期任务分发 | +| `User/bsp/src/bsp_step_moto.c` | 步进电机控制（脉冲计数、启动/停止） | +| `User/bsp/src/bsp_drv8880.c` | DRV8880 电机驱动接口 | +| `User/bsp/src/bsp_tim_pwm.c` | 定时器 PWM 生成电机脉冲 | +| `User/bsp/src/bsp_usart_dma.c` | UART + DMA 串口通信 | +| `User/bsp/src/bsp_digital_tube.c` | 数码管（7 段）显示 | +| `User/bsp/src/bsp_key.c` | 按键扫描和键值处理 | +| `User/bsp/src/bsp_beep.c` | 蜂鸣器音调生成 | + +## UART 命令接口 + +通过 USART1（PA9/PA10，115200 波特率）通信。支持的命令： + +| 命令 | 功能 | +|------|------| +| `?` | 获取当前位置角度 | +| `s` | 停止电机 | +| `z` | 将当前位置设为零点 | +| `MF` | 打印系统信息 | +| `[r:频率:角度]` | 以指定转速旋转到绝对角度 | +| `[rr:频率:角度]` | 以指定转速旋转相对角度 | + +常量：`MAX_SPEED = 400`，`STEP_PER_LAP = 8461`（每转步数）。 + +## BSP 架构 + +BSP 采用周期定时器驱动模型： +- `bsp_RunPer1ms()` — 每 1ms 调用一次（数码管刷新） +- `bsp_RunPer10ms()` — 每 10ms 调用一次（按键扫描、蜂鸣器处理） +- `bsp_Idle()` — 在主循环空闲时调用 + +`bsp.h` 是所有 BSP 模块的统一入口。应用程序只需 `#include "bsp.h"`。 + +## Bootloader（独立工程） + +位于 `Bootloader/`，是一个基于 STM32 HAL 库的 IAP 引导程序（主应用使用 StdPeriph 库，两者不同）。通过 UART 接收固件并烧录到 0x08008000。作为独立的 Keil 工程构建，位于 `Bootloader/Projects/` 下。 + +## 注意事项 + +- 源文件使用 GBK/中文编码 — 在 UTF-8 编辑器中可能显示乱码 +- 工程中积累了多个用户的重复 `.uvgui` 文件 — 可忽略 +- `Bootloader/keilkill.bat` 用于清理 Keil 临时文件 +- `CopyHex_Flash.bat` 用于复制编译生成的 hex 文件 +- `Libraries/` 目录是厂商提供的代码，应避免修改 +- 主应用使用 StdPeriph 库；Bootloader 使用 HAL 库 — 两者是独立的代码体系 diff --git a/Doc/01.例程功能说明.txt b/Doc/01.例程功能说明.txt new file mode 100644 index 0000000..6c521f4 --- /dev/null +++ b/Doc/01.例程功能说明.txt @@ -0,0 +1,74 @@ +/* +********************************************************************************************************* +* +* STM32-V4 -̹˵ +* +* : V4-005_Դ̣ӲPWM +* +* Ƽ༭TABΪ4 Ķļ +* +********************************************************************************************************* +*/ + +1̼ + + ʾSTM32-V4尲װķΪԴʹPA8š + + ʵֹܣ + 1 K1K2K3ֱ𷢳ͬķ + 2 ͨҡҼԵڷƵʡ + ʾ: + 1. K1 - ʾ(̶Ƶ1.5KHz) + 2. K2 - 10 + 3. K3 - 3 + 4. ҡ - Ƶ - 100Hz + 5. ҡҼ - Ƶ + 100Hz + + Դ˵: + 1bsp_beep.c ǷļͨлԴԴ ԴҪʹTIMӲ + PWM + //#define BEEP_HAVE_POWER /* бʾԴֱͨGPIO, PWM */ + + 2bsp_tim_pwm.c ǶʱPWMļSetTIMOutPWM()GPIOΪPWM״̬ + void bsp_SetTIMOutPWM(GPIO_TypeDef* GPIOx, uint16_t GPIO_Pin, TIM_TypeDef* TIMx, uint8_t _ucChannel, + uint32_t _ulFreq, uint32_t _ulDutyCycle); + + 3bsp.c УҪÿ10msһBEEP_Pro()úƷʱ + void bsp_RunPer10ms(void) + { + bsp_KeyScan(); /* ÿ10msɨ谴һ */ + + BEEP_Pro(); /* ʱ */ + } + + 4 BEEP_KeyTone(); ǷʾĺƵʹ̶1.5KHz + BEEP_Start()ʼСúǷģ10msʱжϷPWMֹͣ + BEEP_Stop() ֹС + +2ִн + ʹUSBתRS232ߣӿRS232ӿڵUSBӿڡ SecureCRT + + Ǵڽִн + ************************************************************* + * : V4-005_Դ̣ӲPWM + * ̰汾 : 1.0 + * : 2015-08-30 + * ̼汾 : 3.6.1 + * CMSIS汾 : 3.01 + * + * QQ : 1295744630 + * Email : armfly@qq.com + * Copyright www.armfly.com + ************************************************************* + ʾ: + 1. K1 - ʾ(̶Ƶ1.5KHz) + 2. K2 - 10 + 3. K3 - 3 + 4. ҡ - Ƶ - 100Hz + 5. ҡҼ - Ƶ + 100Hz + Ƶ = 1500Hz + + +3޸ļ¼ +2015-08-30 V1.0 װ + diff --git a/Doc/02.开发环境说明.txt b/Doc/02.开发环境说明.txt new file mode 100644 index 0000000..38f49eb --- /dev/null +++ b/Doc/02.开发环境说明.txt @@ -0,0 +1,257 @@ +/* +********************************************************************************************************* +* +* STM32-V4 -˵ +* +* ڣ2015-08-30 +* +* Ƽ༭TABΪ4 Ķļ +* +********************************************************************************************************* +*/ + +1CPUڲԴ + CPUͺ : STM32F103ZET6 / LQFP-144 / ARM 32-bit Cortex-M3 + Ƶ : 72MHz + ڲFlash : 512KB + ڲSRAM : 64KB + ʱ : 11 + UART : 5 + SPI : 3 (2ɸΪI2S) + I2C : 2 + ADC : 312λADC + DAC : 2·12λDAC + CAN : 1 CAN 2.0B + SDIO : 1 + USB : USB2.0ȫ()ⲿPHY + +2FSMC洢ַ + CPUڲ FLASH 0x0800 0000 - 0x080F FFFF,512K(0x80000)ֽ + CPUڲ SRAM1 0x2000 0000 - 0x2000 FFFF,64K(0x10000)ֽ + + ⲿ NOR Flash 0x6400 0000 - 0x64FF FFFF,16M(0x1000000)ֽ + ⲿ SRAM 0x6800 0000 - 0x681F FFFF,1M(0x100000)ֽ + DM9000AоƬַ0x6C10 0000, 0x6C10 0008, ռ2˿ڵַ + TFT LCDַ 0x6C00 0000, 0x6C00 0002, ռ2˿ڵַ + OLEDַ 0x6C20 0000, 0x6C20 0002, ռ2˿ڵַ + ⲿ NAND Flash0x7000 0000, 128M(0xC800000)ֽ + + +3I2Cַ + ַ + 1 EEPROM AT24C128 0xA0 + 2 ƵCODECоƬWM8978 0x34 + 3 FMSi4704 0x22 + 4 MPU-6050 0xD0 + 5 նȴ BH1750FVI 0x46 + 6 ѹ BMP180 0xEE + 7 HMC5883L 0x3C õģ飬ѡ䡿 + +4 + --- DZ䣬ѡ + ȻSTM32ִ֧ISPس򣬵Dz֧ߵԡʹôأЧʼͣǿƼһ߿Чʡ + - ST-LINK V2 : ST˾ķس͵Ըٳ֧STM8STM32һSTM8S + STM32Ļ ǽ鹺J-Link + - J-LINK V8,V9 : Segger˾ķس͵Ըٳ֧ARMϵС + + USBתRS232ߡ--- + - ڴPCûӲˡǶڵƬڻǺõġĺ̶ܶҪͨڴӡϢ + - һHL-340ͺŵUSBתRS232ߡ֧WIN XP, WIN7 WIN8 ϵͳ + + + - 뻷 IAR EWARMv6 KEIL MDK uV4밴ѡ綼ϤƼʹKEIL MDK (uV4) + - SecureCRT : һĹǿijն˹ߣҪʾӴڴӡϢ + - UltraEdit : һԴ༭ + - SourceInsight : һԴ + +5͵Է + ˵̾ṩ KEIL IAṚֹÿ2TargetһFlashѲеģһCpuRAMеġ밴Ҫѡ + Ҫ޸Flashеijµ̣ѡCPU RAMС + >>>> Щ򣨱Գܴ޷޵RAMռִС + + Keil MDKV4.54 + - ִв˵ Project -> Open project \Project\MDK-ARM(uV4)\project.uvproj ǹļ + - ִв˵ Project -> Rebuild all target files ±еļ: + - ִв˵ Debug->Start/Stop Debug Session (Ctrl+F5) : + + ע1ѡCPU RAMʱʹLoadťسֱStart DebugɡΪLoadťרصFlashġ + ע2Keil MDKΪ˱ַ澯ҪC/C++ѡ --diag_suppress=870 + ע3Ϊ߱Чʡȱʡر˹ Output - Browse Information޷ʹҼҺ塣 + Ҫܣѡء + + IAR EWARMV6.30 + - ִв˵ File -> Open Workspace (򿪹ļ: Project\EWARMv6\Project.www) + - ִв˵ Project -> Rebuild All (±) + - ִв˵ Project -> Download and Debug(Ctrl+D) (װس) + +6ļ˵ +Libraries : ŵ3ṩĿԴ룬ЩһdzIJ֤Ĵ롣 + CMSIS : CMSISARM˾ҲͬоƬӦһܺģṩں衢ʵʱϵͳм豸֮ͨýӿڡ + STM32F10x_StdPeriph_Driver : STM32F10XϵMCUı׼̼Դ + STM32_USB-FS-Device_Driver : USB Device Library + +User : ûԼдԴ + bsp : 弶ְ֧Board Surport PacketҲӲײ. òڹ̼Ӧó֮䡣 + fonts : ŵֿⳣ + +project : Ÿ࿪ߵĹļеʱļHEXļڴļ + MDK-ARM(uV4) : KEIL˾MDK uVision 4ļ + EWARMv6 : IAR˾EWARM ļ + +7Դ˵ +Flash : TargetƣFlash CpuRAM + USER : main.c Լûó + BSP : 弶ְ֧Board Support Packet,Ӳײļ + CMSIS : CMSISIӿļ system_stm32f4xx.c + StdPeriph_Drivers: STM328SϵMCUĹ̼Դ + MDK-ARM : ļԴ,IAR EWARMv6 + Doc : һЩĵtxtļ + +8Դļ˵ + - main.c : û򣬴main()ļ + - stm32f1xx_it.c : джϷ ˼쳣ж⣬ǽISRŵԵģС + - stm32f10x_assert.c : ŶԺ һģ + - bsp.c : ײӲ򣨰Ӳʼں + - Ŀļ(ڴ).bat : ִɾOBJ,LISTļԴѹ + +9CеԤ ڹиģ + USE_STDPERIPH_DRIVER - űʾʹST˾ı׼ + VECT_TAB_SRAM - űʾжλCPUڲRAM CPUڲRAMеĹ̲Ҫӣ + +10Ѻջ + KEIL MDK, öѺջĴСͨ޸ļstart_stm32f10x_hd.s ļʵֵģ磺 + Stack_Size EQU 0x00008000 + Heap_Size EQU 0x00000400 + + IAR EWARM, ֱڹн޸ļ + - ˵ project -> options -> ѡLinker -> Configҳ -> Editť -> лCSTACK/HEAP + 磺 + CSTACK = 0x8000 + HEAP = 0x400 + +11Ŀļ + project 棬бõ hex ļû÷ֱ output(flash).hex CPUڲflash + \Project\output(mdk).hex - KEIL MDKõļλCPU ڲFlash + \Project\output(iar).hex - IARõļλCPU ڲFlash + \Project\MDK-ARM(uV4)\Flash\List\output.map - DZļıʽԲ鿴ÿĵַͿռ + +¼1 STM32-V4 GPIO + GPIO, һ140GPIOGPIOA C GPIOH ÿ16GPIOI ֻ12 + PA0/WKUP WKUPť -- K1 + PA1/DM9000AE_INT ̫оƬDM9000AEж + PA2/USART2_TX 2 + PA3/USART2_RX 2գGPRSģ + PA4/DAC_OU DAC1 + PA5/SPI1_SCK SPIʱ/DAC2 + PA6/SPI1_MISO SPIMISO + PA7/SPI1_MOSI SPIMOSI + PA8/IR_TX + PA9/USART1_TX 1ͣRS232 + PA10/USART1_RX 1գRS232 + PA11/USBDM ȫ(12Mbps)USBӿD- + PA12/USBDP ȫ(12Mbps)USBӿD+ + PA13/JTMS-SWDIO SWDԽӿ + PA14/JTCK-SWCLK SWDԽӿʱ + PA15/ESP8266_GPIO2 WIFIģIO + + PB0/IR_RX ңؽչ + PB1/LCD_PWM LCDƣRA8875ãRA8875ƣ + PB2-BOOT1/RS485_TXEN RS485ʹ + PB3/NRF24L01_CE NRF24L01ʹ + PB4/TRST/GPRS_TERM_ON WIFIԴ/GPRSģ鿪ź + PB5/TP_BUSY/VS1053_DREQ BUSY/VS1053BǷ + PB6/I2C1_SCL I2C1ʱӿ + PB7/I2C1_SDA I2C1ݿ + PB8/CANRX CAN + PB9/CANTX CAN + PB10/USART3_TX 3ͣRS485շоƬ + PB11/USART3_RX 3գRS485շоƬ + PB12/I2S2_WS I2SƵӿѡź + PB13/I2S2_CK I2SƵӿʱź + PB14/USB_PULLUPENBLE USBʹ + PB15/I2S2_SD WM8978¼ + + PC0/ADC123_IN10 ADC - ʾͨ1 + PC1/ADC123_IN11 ADC - ʾͨ2 + PC2/ ADC123_IN12/GPRS_RESET ADC/ESP8266ⲿӲλ + PC3/ ADC123_IN13/NRF24L01_CSN ADC/NRF24L01Ƭѡźѡ + PC4/ ADC12_IN14 ɵADC + PC5/ TP_INT жϣRA8875жϣ + PC6/I2S2_MCK I2SƵӿʱԴ + PC7/ SD_INSERT SD + PC8/SDIO_D0 SDIOD0 + PC9/SDIO_D1 SDIOD1 + PC10/SDIO_D2 SDIOD2 + PC11/SDIO_D3 SDIOD3 + PC12/SDIO_CK SDIOʱ + PC13/TAMPER K1//PS/2ʱӿ + PC14-OSC32_IN 32768Hzʱ + PC15-OSC32_OUT 32768Hzʱ + + PD0/ FSMC_D2 FSMCD2 + PD1/FSMC_D3 FSMCD3 + PD2/SDIO_CMD SDIO + PD3/JOY_D ҡ¼ + PD4/FSMC_NOE FSMC߶źţNʾЧOE = Output Enable + PD5/FSMC_NWE FSMCдźţNʾЧWE = Write Enable + PD6/FSMC_NWAIT FSMCߵȴź + PD7/FSMC_NCE2 FSMCƬѡNCE2 + PD8/FSMC_D13 FSMCD13 + PD9/FSMC_D14 FSMCD14 + PD10/FSMC_D15 FSMCD15 + PD11/FSMC_A16 FSMCַA16 + PD12/FSMC_A17 FSMCַA17 + PD13/FSMC_A18 FSMCַA18 + PD14/FSMC_D0 FSMCD0 + PD15/FSMC_D1 FSMCD1 + + PE0/FSMC_NBL0 FSMCֽѡźţSRAM + PE1/FSMC_NBL1 FSMCֽѡźţSRAM + PE2/CH376T_INT CH376TоƬжź + PE3/FSMC_A19 FSMCַA19 + PE4/FSMC_A20 FSMCַA20 + PE5/FSMC_A21 FSMCַA21 + PE6/FSMC_A22 FSMCַA22 + PE7/FSMC_D4 FSMCD4 + PE8/FSMC_D5 FSMCD5 + PE9/FSMC_D6 FSMCD6 + PE10/FSMC_D7 FSMCD7 + PE11/FSMC_D8 FSMCD8 + PE12/FSMC_D9 FSMCD9 + PE13/FSMC_D10 FSMCD10 + PE14/FSMC_D11 FSMCD11 + PE15/FSMC_D12 FSMCD12 + + PF0/FSMC_A0 FSMCַA0 + PF1/FSMC_A1 FSMCַA1 + PF2/FSMC_A2 FSMCַA2 + PF3/FSMC_A3 FSMCַA3 + PF4/FSMC_A4 FSMCַA4 + PF5/FSMC_A5 FSMCַA5 + PF6/MPU-6050_INT/NRF24L01_IRQ SPI (NRF24L01 / MPU-6050ж) + PF7/ESP8266_GPIO0/LED2 ESP8266ѡ״̬/LED2 + PF8/VS1053B_XDCS/LED3 VS1053BƬѡ/LED3 + PF9/VS1053B_XCS/LED4 VS1053BƬѡź/LED4 + PF10/CH376T_SCS CH376T SPIƬѡ + PF11/SF_CS/LED1 ƴFlashƬѡ/LED1 + PF12/FSMC_A6 FSMCַA6 + PF13/FSMC_A7 FSMCַA7 + PF14/FSMC_A8 FSMCַA8 + PF15/FSMC_A9 FSMCַA + + PG0/FSMC_A10 FSMCַA10 + PG1/FSMC_A11 FSMCַA11 + PG2/FSMC_A12 FSMCַA12 + PG3/FSMC_A13 FSMCַA13 + PG4/FSMC_A14 FSMCַA14 + PG5/FSMC_A15 FSMCַA15 + PG6/FSMC_INT2 NAND Flashæź + PG7/JOY_OK ҡOK + PG8/PS/2_DATA/DS18B20_DQ PS/2ӿ/DS18B20 + PG9/FSMC_NE2 FSMCƬѡNE2 + PG10/FSMC_NE3 FSMCƬѡNE3 + PG11/TP_NCS 3.5оƬƬѡRA8875SPIӿڵƬѡ + PG12/FSMC_NE4 FSMCƬѡNE4 + PG13/JOY_R ҡҼ + PG14/JOY_L ҡ + PG15/JOY_U ҡϼ \ No newline at end of file diff --git a/Libraries/CMSIS/CMSIS END USER LICENCE AGREEMENT.pdf b/Libraries/CMSIS/CMSIS END USER LICENCE AGREEMENT.pdf new file mode 100644 index 0000000000000000000000000000000000000000..c8feab483c7aee07b235b93666803151e052e8c7 GIT binary patch literal 46999 zcmaHyV{j%w@aALNwv&x*+jcg1W81cECmY+gZQI${PHz9WySlron@>|c-8J1`W}fQ# z4Y{JI_%9}UHhA)q^VuPI7-k|yB0D2XcwSxxRS$argNUKCp|zbEgQB4sz=??E->UL| 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QQc9AHn2Sr@P=oA$0ObL?h5!Hn literal 0 HcmV?d00001 diff --git a/Libraries/CMSIS/Device/ST/STM32F10x/Include/stm32f10x.h b/Libraries/CMSIS/Device/ST/STM32F10x/Include/stm32f10x.h new file mode 100644 index 0000000..2a6f12a --- /dev/null +++ b/Libraries/CMSIS/Device/ST/STM32F10x/Include/stm32f10x.h @@ -0,0 +1,8388 @@ +/** + ****************************************************************************** + * @file stm32f10x.h + * @author MCD Application Team + * @version V3.6.1 + * @date 09-March-2012 + * @brief CMSIS Cortex-M3 Device Peripheral Access Layer Header File. + * This file contains all the peripheral register's definitions, bits + * definitions and memory mapping for STM32F10x Connectivity line, + * High density, High density value line, Medium density, + * Medium density Value line, Low density, Low density Value line + * and XL-density devices. + * + * The file is the unique include file that the application programmer + * is using in the C source code, usually in main.c. This file contains: + * - Configuration section that allows to select: + * - The device used in the target application + * - To use or not the peripherals drivers in application code(i.e. + * code will be based on direct access to peripherals registers + * rather than drivers API), this option is controlled by + * "#define USE_STDPERIPH_DRIVER" + * - To change few application-specific parameters such as the HSE + * crystal frequency + * - Data structures and the address mapping for all peripherals + * - Peripheral's registers declarations and bits definition + * - Macros to access peripherals registers hardware + * + ****************************************************************************** + * @attention + * + *

© COPYRIGHT 2012 STMicroelectronics

+ * + * Licensed under MCD-ST Liberty SW License Agreement V2, (the "License"); + * You may not use this file except in compliance with the License. + * You may obtain a copy of the License at: + * + * http://www.st.com/software_license_agreement_liberty_v2 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, + * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + * + ****************************************************************************** + */ + +/** @addtogroup CMSIS + * @{ + */ + +/** @addtogroup stm32f10x + * @{ + */ + +#ifndef __STM32F10x_H +#define __STM32F10x_H + +#ifdef __cplusplus + extern "C" { +#endif /* __cplusplus */ + +/** @addtogroup Library_configuration_section + * @{ + */ + +/* Uncomment the line below according to the target STM32 device used in your + application + */ + +#if !defined (STM32F10X_LD) && !defined (STM32F10X_LD_VL) && !defined (STM32F10X_MD) && !defined (STM32F10X_MD_VL) && !defined (STM32F10X_HD) && !defined (STM32F10X_HD_VL) && !defined (STM32F10X_XL) && !defined (STM32F10X_CL) + /* #define STM32F10X_LD */ /*!< STM32F10X_LD: STM32 Low density devices */ + /* #define STM32F10X_LD_VL */ /*!< STM32F10X_LD_VL: STM32 Low density Value Line devices */ + /* #define STM32F10X_MD */ /*!< STM32F10X_MD: STM32 Medium density devices */ + /* #define STM32F10X_MD_VL */ /*!< STM32F10X_MD_VL: STM32 Medium density Value Line devices */ + /* #define STM32F10X_HD */ /*!< STM32F10X_HD: STM32 High density devices */ + /* #define STM32F10X_HD_VL */ /*!< STM32F10X_HD_VL: STM32 High density value line devices */ + /* #define STM32F10X_XL */ /*!< STM32F10X_XL: STM32 XL-density devices */ + /* #define STM32F10X_CL */ /*!< STM32F10X_CL: STM32 Connectivity line devices */ +#endif +/* Tip: To avoid modifying this file each time you need to switch between these + devices, you can define the device in your toolchain compiler preprocessor. + + - Low-density devices are STM32F101xx, STM32F102xx and STM32F103xx microcontrollers + where the Flash memory density ranges between 16 and 32 Kbytes. + - Low-density value line devices are STM32F100xx microcontrollers where the Flash + memory density ranges between 16 and 32 Kbytes. + - Medium-density devices are STM32F101xx, STM32F102xx and STM32F103xx microcontrollers + where the Flash memory density ranges between 64 and 128 Kbytes. + - Medium-density value line devices are STM32F100xx microcontrollers where the + Flash memory density ranges between 64 and 128 Kbytes. + - High-density devices are STM32F101xx and STM32F103xx microcontrollers where + the Flash memory density ranges between 256 and 512 Kbytes. + - High-density value line devices are STM32F100xx microcontrollers where the + Flash memory density ranges between 256 and 512 Kbytes. + - XL-density devices are STM32F101xx and STM32F103xx microcontrollers where + the Flash memory density ranges between 512 and 1024 Kbytes. + - Connectivity line devices are STM32F105xx and STM32F107xx microcontrollers. + */ + +#if !defined (STM32F10X_LD) && !defined (STM32F10X_LD_VL) && !defined (STM32F10X_MD) && !defined (STM32F10X_MD_VL) && !defined (STM32F10X_HD) && !defined (STM32F10X_HD_VL) && !defined (STM32F10X_XL) && !defined (STM32F10X_CL) + #error "Please select first the target STM32F10x device used in your application (in stm32f10x.h file)" +#endif + +#if !defined (USE_STDPERIPH_DRIVER) +/** + * @brief Comment the line below if you will not use the peripherals drivers. + In this case, these drivers will not be included and the application code will + be based on direct access to peripherals registers + */ + /*#define USE_STDPERIPH_DRIVER*/ +#endif /* USE_STDPERIPH_DRIVER */ + +/** + * @brief In the following line adjust the value of External High Speed oscillator (HSE) + used in your application + + Tip: To avoid modifying this file each time you need to use different HSE, you + can define the HSE value in your toolchain compiler preprocessor. + */ +#if !defined HSE_VALUE + #ifdef STM32F10X_CL + #define HSE_VALUE ((uint32_t)25000000) /*!< Value of the External oscillator in Hz */ + #else + #define HSE_VALUE ((uint32_t)8000000) /*!< Value of the External oscillator in Hz */ + #endif /* STM32F10X_CL */ +#endif /* HSE_VALUE */ + +/** + * @brief In the following line adjust the External High Speed oscillator (HSE) Startup + Timeout value + */ +#if !defined (HSE_STARTUP_TIMEOUT) + #define HSE_STARTUP_TIMEOUT ((uint16_t)0x0500) /*!< Time out for HSE start up */ +#endif /* HSE_STARTUP_TIMEOUT */ + +#if !defined (HSI_VALUE) + #define HSI_VALUE ((uint32_t)8000000) /*!< Value of the Internal oscillator in Hz*/ +#endif /* HSI_VALUE */ + +/** + * @brief STM32F10x Standard Peripheral Library version number + */ +#define __STM32F10X_STDPERIPH_VERSION_MAIN (0x03) /*!< [31:24] main version */ +#define __STM32F10X_STDPERIPH_VERSION_SUB1 (0x06) /*!< [23:16] sub1 version */ +#define __STM32F10X_STDPERIPH_VERSION_SUB2 (0x01) /*!< [15:8] sub2 version */ +#define __STM32F10X_STDPERIPH_VERSION_RC (0x00) /*!< [7:0] release candidate */ +#define __STM32F10X_STDPERIPH_VERSION ((__STM32F10X_STDPERIPH_VERSION_MAIN << 24)\ + |(__STM32F10X_STDPERIPH_VERSION_SUB1 << 16)\ + |(__STM32F10X_STDPERIPH_VERSION_SUB2 << 8)\ + |(__STM32F10X_STDPERIPH_VERSION_RC)) + +/** + * @} + */ + +/** @addtogroup Configuration_section_for_CMSIS + * @{ + */ + +/** + * @brief Configuration of the Cortex-M3 Processor and Core Peripherals + */ +#ifdef STM32F10X_XL + #define __MPU_PRESENT 1 /*!< STM32 XL-density devices provide an MPU */ +#else + #define __MPU_PRESENT 0 /*!< Other STM32 devices does not provide an MPU */ +#endif /* STM32F10X_XL */ +#define __CM3_REV 0x0200 /*!< Core Revision r2p0 */ +#define __NVIC_PRIO_BITS 4 /*!< STM32 uses 4 Bits for the Priority Levels */ +#define __Vendor_SysTickConfig 0 /*!< Set to 1 if different SysTick Config is used */ + +/** + * @brief STM32F10x Interrupt Number Definition, according to the selected device + * in @ref Library_configuration_section + */ +typedef enum IRQn +{ +/****** Cortex-M3 Processor Exceptions Numbers ***************************************************/ + NonMaskableInt_IRQn = -14, /*!< 2 Non Maskable Interrupt */ + MemoryManagement_IRQn = -12, /*!< 4 Cortex-M3 Memory Management Interrupt */ + BusFault_IRQn = -11, /*!< 5 Cortex-M3 Bus Fault Interrupt */ + UsageFault_IRQn = -10, /*!< 6 Cortex-M3 Usage Fault Interrupt */ + SVCall_IRQn = -5, /*!< 11 Cortex-M3 SV Call Interrupt */ + DebugMonitor_IRQn = -4, /*!< 12 Cortex-M3 Debug Monitor Interrupt */ + PendSV_IRQn = -2, /*!< 14 Cortex-M3 Pend SV Interrupt */ + SysTick_IRQn = -1, /*!< 15 Cortex-M3 System Tick Interrupt */ + +/****** STM32 specific Interrupt Numbers *********************************************************/ + WWDG_IRQn = 0, /*!< Window WatchDog Interrupt */ + PVD_IRQn = 1, /*!< PVD through EXTI Line detection Interrupt */ + TAMPER_IRQn = 2, /*!< Tamper Interrupt */ + RTC_IRQn = 3, /*!< RTC global Interrupt */ + FLASH_IRQn = 4, /*!< FLASH global Interrupt */ + RCC_IRQn = 5, /*!< RCC global Interrupt */ + EXTI0_IRQn = 6, /*!< EXTI Line0 Interrupt */ + EXTI1_IRQn = 7, /*!< EXTI Line1 Interrupt */ + EXTI2_IRQn = 8, /*!< EXTI Line2 Interrupt */ + EXTI3_IRQn = 9, /*!< EXTI Line3 Interrupt */ + EXTI4_IRQn = 10, /*!< EXTI Line4 Interrupt */ + DMA1_Channel1_IRQn = 11, /*!< DMA1 Channel 1 global Interrupt */ + DMA1_Channel2_IRQn = 12, /*!< DMA1 Channel 2 global Interrupt */ + DMA1_Channel3_IRQn = 13, /*!< DMA1 Channel 3 global Interrupt */ + DMA1_Channel4_IRQn = 14, /*!< DMA1 Channel 4 global Interrupt */ + DMA1_Channel5_IRQn = 15, /*!< DMA1 Channel 5 global Interrupt */ + DMA1_Channel6_IRQn = 16, /*!< DMA1 Channel 6 global Interrupt */ + DMA1_Channel7_IRQn = 17, /*!< DMA1 Channel 7 global Interrupt */ + +#ifdef STM32F10X_LD + ADC1_2_IRQn = 18, /*!< ADC1 and ADC2 global Interrupt */ + USB_HP_CAN1_TX_IRQn = 19, /*!< USB Device High Priority or CAN1 TX Interrupts */ + USB_LP_CAN1_RX0_IRQn = 20, /*!< USB Device Low Priority or CAN1 RX0 Interrupts */ + CAN1_RX1_IRQn = 21, /*!< CAN1 RX1 Interrupt */ + CAN1_SCE_IRQn = 22, /*!< CAN1 SCE Interrupt */ + EXTI9_5_IRQn = 23, /*!< External Line[9:5] Interrupts */ + TIM1_BRK_IRQn = 24, /*!< TIM1 Break Interrupt */ + TIM1_UP_IRQn = 25, /*!< TIM1 Update Interrupt */ + TIM1_TRG_COM_IRQn = 26, /*!< TIM1 Trigger and Commutation Interrupt */ + TIM1_CC_IRQn = 27, /*!< TIM1 Capture Compare Interrupt */ + TIM2_IRQn = 28, /*!< TIM2 global Interrupt */ + TIM3_IRQn = 29, /*!< TIM3 global Interrupt */ + I2C1_EV_IRQn = 31, /*!< I2C1 Event Interrupt */ + I2C1_ER_IRQn = 32, /*!< I2C1 Error Interrupt */ + SPI1_IRQn = 35, /*!< SPI1 global Interrupt */ + USART1_IRQn = 37, /*!< USART1 global Interrupt */ + USART2_IRQn = 38, /*!< USART2 global Interrupt */ + EXTI15_10_IRQn = 40, /*!< External Line[15:10] Interrupts */ + RTCAlarm_IRQn = 41, /*!< RTC Alarm through EXTI Line Interrupt */ + USBWakeUp_IRQn = 42 /*!< USB Device WakeUp from suspend through EXTI Line Interrupt */ +#endif /* STM32F10X_LD */ + +#ifdef STM32F10X_LD_VL + ADC1_IRQn = 18, /*!< ADC1 global Interrupt */ + EXTI9_5_IRQn = 23, /*!< External Line[9:5] Interrupts */ + TIM1_BRK_TIM15_IRQn = 24, /*!< TIM1 Break and TIM15 Interrupts */ + TIM1_UP_TIM16_IRQn = 25, /*!< TIM1 Update and TIM16 Interrupts */ + TIM1_TRG_COM_TIM17_IRQn = 26, /*!< TIM1 Trigger and Commutation and TIM17 Interrupt */ + TIM1_CC_IRQn = 27, /*!< TIM1 Capture Compare Interrupt */ + TIM2_IRQn = 28, /*!< TIM2 global Interrupt */ + TIM3_IRQn = 29, /*!< TIM3 global Interrupt */ + I2C1_EV_IRQn = 31, /*!< I2C1 Event Interrupt */ + I2C1_ER_IRQn = 32, /*!< I2C1 Error Interrupt */ + SPI1_IRQn = 35, /*!< SPI1 global Interrupt */ + USART1_IRQn = 37, /*!< USART1 global Interrupt */ + USART2_IRQn = 38, /*!< USART2 global Interrupt */ + EXTI15_10_IRQn = 40, /*!< External Line[15:10] Interrupts */ + RTCAlarm_IRQn = 41, /*!< RTC Alarm through EXTI Line Interrupt */ + CEC_IRQn = 42, /*!< HDMI-CEC Interrupt */ + TIM6_DAC_IRQn = 54, /*!< TIM6 and DAC underrun Interrupt */ + TIM7_IRQn = 55 /*!< TIM7 Interrupt */ +#endif /* STM32F10X_LD_VL */ + +#ifdef STM32F10X_MD + ADC1_2_IRQn = 18, /*!< ADC1 and ADC2 global Interrupt */ + USB_HP_CAN1_TX_IRQn = 19, /*!< USB Device High Priority or CAN1 TX Interrupts */ + USB_LP_CAN1_RX0_IRQn = 20, /*!< USB Device Low Priority or CAN1 RX0 Interrupts */ + CAN1_RX1_IRQn = 21, /*!< CAN1 RX1 Interrupt */ + CAN1_SCE_IRQn = 22, /*!< CAN1 SCE Interrupt */ + EXTI9_5_IRQn = 23, /*!< External Line[9:5] Interrupts */ + TIM1_BRK_IRQn = 24, /*!< TIM1 Break Interrupt */ + TIM1_UP_IRQn = 25, /*!< TIM1 Update Interrupt */ + TIM1_TRG_COM_IRQn = 26, /*!< TIM1 Trigger and Commutation Interrupt */ + TIM1_CC_IRQn = 27, /*!< TIM1 Capture Compare Interrupt */ + TIM2_IRQn = 28, /*!< TIM2 global Interrupt */ + TIM3_IRQn = 29, /*!< TIM3 global Interrupt */ + TIM4_IRQn = 30, /*!< TIM4 global Interrupt */ + I2C1_EV_IRQn = 31, /*!< I2C1 Event Interrupt */ + I2C1_ER_IRQn = 32, /*!< I2C1 Error Interrupt */ + I2C2_EV_IRQn = 33, /*!< I2C2 Event Interrupt */ + I2C2_ER_IRQn = 34, /*!< I2C2 Error Interrupt */ + SPI1_IRQn = 35, /*!< SPI1 global Interrupt */ + SPI2_IRQn = 36, /*!< SPI2 global Interrupt */ + USART1_IRQn = 37, /*!< USART1 global Interrupt */ + USART2_IRQn = 38, /*!< USART2 global Interrupt */ + USART3_IRQn = 39, /*!< USART3 global Interrupt */ + EXTI15_10_IRQn = 40, /*!< External Line[15:10] Interrupts */ + RTCAlarm_IRQn = 41, /*!< RTC Alarm through EXTI Line Interrupt */ + USBWakeUp_IRQn = 42 /*!< USB Device WakeUp from suspend through EXTI Line Interrupt */ +#endif /* STM32F10X_MD */ + +#ifdef STM32F10X_MD_VL + ADC1_IRQn = 18, /*!< ADC1 global Interrupt */ + EXTI9_5_IRQn = 23, /*!< External Line[9:5] Interrupts */ + TIM1_BRK_TIM15_IRQn = 24, /*!< TIM1 Break and TIM15 Interrupts */ + TIM1_UP_TIM16_IRQn = 25, /*!< TIM1 Update and TIM16 Interrupts */ + TIM1_TRG_COM_TIM17_IRQn = 26, /*!< TIM1 Trigger and Commutation and TIM17 Interrupt */ + TIM1_CC_IRQn = 27, /*!< TIM1 Capture Compare Interrupt */ + TIM2_IRQn = 28, /*!< TIM2 global Interrupt */ + TIM3_IRQn = 29, /*!< TIM3 global Interrupt */ + TIM4_IRQn = 30, /*!< TIM4 global Interrupt */ + I2C1_EV_IRQn = 31, /*!< I2C1 Event Interrupt */ + I2C1_ER_IRQn = 32, /*!< I2C1 Error Interrupt */ + I2C2_EV_IRQn = 33, /*!< I2C2 Event Interrupt */ + I2C2_ER_IRQn = 34, /*!< I2C2 Error Interrupt */ + SPI1_IRQn = 35, /*!< SPI1 global Interrupt */ + SPI2_IRQn = 36, /*!< SPI2 global Interrupt */ + USART1_IRQn = 37, /*!< USART1 global Interrupt */ + USART2_IRQn = 38, /*!< USART2 global Interrupt */ + USART3_IRQn = 39, /*!< USART3 global Interrupt */ + EXTI15_10_IRQn = 40, /*!< External Line[15:10] Interrupts */ + RTCAlarm_IRQn = 41, /*!< RTC Alarm through EXTI Line Interrupt */ + CEC_IRQn = 42, /*!< HDMI-CEC Interrupt */ + TIM6_DAC_IRQn = 54, /*!< TIM6 and DAC underrun Interrupt */ + TIM7_IRQn = 55 /*!< TIM7 Interrupt */ +#endif /* STM32F10X_MD_VL */ + +#ifdef STM32F10X_HD + ADC1_2_IRQn = 18, /*!< ADC1 and ADC2 global Interrupt */ + USB_HP_CAN1_TX_IRQn = 19, /*!< USB Device High Priority or CAN1 TX Interrupts */ + USB_LP_CAN1_RX0_IRQn = 20, /*!< USB Device Low Priority or CAN1 RX0 Interrupts */ + CAN1_RX1_IRQn = 21, /*!< CAN1 RX1 Interrupt */ + CAN1_SCE_IRQn = 22, /*!< CAN1 SCE Interrupt */ + EXTI9_5_IRQn = 23, /*!< External Line[9:5] Interrupts */ + TIM1_BRK_IRQn = 24, /*!< TIM1 Break Interrupt */ + TIM1_UP_IRQn = 25, /*!< TIM1 Update Interrupt */ + TIM1_TRG_COM_IRQn = 26, /*!< TIM1 Trigger and Commutation Interrupt */ + TIM1_CC_IRQn = 27, /*!< TIM1 Capture Compare Interrupt */ + TIM2_IRQn = 28, /*!< TIM2 global Interrupt */ + TIM3_IRQn = 29, /*!< TIM3 global Interrupt */ + TIM4_IRQn = 30, /*!< TIM4 global Interrupt */ + I2C1_EV_IRQn = 31, /*!< I2C1 Event Interrupt */ + I2C1_ER_IRQn = 32, /*!< I2C1 Error Interrupt */ + I2C2_EV_IRQn = 33, /*!< I2C2 Event Interrupt */ + I2C2_ER_IRQn = 34, /*!< I2C2 Error Interrupt */ + SPI1_IRQn = 35, /*!< SPI1 global Interrupt */ + SPI2_IRQn = 36, /*!< SPI2 global Interrupt */ + USART1_IRQn = 37, /*!< USART1 global Interrupt */ + USART2_IRQn = 38, /*!< USART2 global Interrupt */ + USART3_IRQn = 39, /*!< USART3 global Interrupt */ + EXTI15_10_IRQn = 40, /*!< External Line[15:10] Interrupts */ + RTCAlarm_IRQn = 41, /*!< RTC Alarm through EXTI Line Interrupt */ + USBWakeUp_IRQn = 42, /*!< USB Device WakeUp from suspend through EXTI Line Interrupt */ + TIM8_BRK_IRQn = 43, /*!< TIM8 Break Interrupt */ + TIM8_UP_IRQn = 44, /*!< TIM8 Update Interrupt */ + TIM8_TRG_COM_IRQn = 45, /*!< TIM8 Trigger and Commutation Interrupt */ + TIM8_CC_IRQn = 46, /*!< TIM8 Capture Compare Interrupt */ + ADC3_IRQn = 47, /*!< ADC3 global Interrupt */ + FSMC_IRQn = 48, /*!< FSMC global Interrupt */ + SDIO_IRQn = 49, /*!< SDIO global Interrupt */ + TIM5_IRQn = 50, /*!< TIM5 global Interrupt */ + SPI3_IRQn = 51, /*!< SPI3 global Interrupt */ + UART4_IRQn = 52, /*!< UART4 global Interrupt */ + UART5_IRQn = 53, /*!< UART5 global Interrupt */ + TIM6_IRQn = 54, /*!< TIM6 global Interrupt */ + TIM7_IRQn = 55, /*!< TIM7 global Interrupt */ + DMA2_Channel1_IRQn = 56, /*!< DMA2 Channel 1 global Interrupt */ + DMA2_Channel2_IRQn = 57, /*!< DMA2 Channel 2 global Interrupt */ + DMA2_Channel3_IRQn = 58, /*!< DMA2 Channel 3 global Interrupt */ + DMA2_Channel4_5_IRQn = 59 /*!< DMA2 Channel 4 and Channel 5 global Interrupt */ +#endif /* STM32F10X_HD */ + +#ifdef STM32F10X_HD_VL + ADC1_IRQn = 18, /*!< ADC1 global Interrupt */ + EXTI9_5_IRQn = 23, /*!< External Line[9:5] Interrupts */ + TIM1_BRK_TIM15_IRQn = 24, /*!< TIM1 Break and TIM15 Interrupts */ + TIM1_UP_TIM16_IRQn = 25, /*!< TIM1 Update and TIM16 Interrupts */ + TIM1_TRG_COM_TIM17_IRQn = 26, /*!< TIM1 Trigger and Commutation and TIM17 Interrupt */ + TIM1_CC_IRQn = 27, /*!< TIM1 Capture Compare Interrupt */ + TIM2_IRQn = 28, /*!< TIM2 global Interrupt */ + TIM3_IRQn = 29, /*!< TIM3 global Interrupt */ + TIM4_IRQn = 30, /*!< TIM4 global Interrupt */ + I2C1_EV_IRQn = 31, /*!< I2C1 Event Interrupt */ + I2C1_ER_IRQn = 32, /*!< I2C1 Error Interrupt */ + I2C2_EV_IRQn = 33, /*!< I2C2 Event Interrupt */ + I2C2_ER_IRQn = 34, /*!< I2C2 Error Interrupt */ + SPI1_IRQn = 35, /*!< SPI1 global Interrupt */ + SPI2_IRQn = 36, /*!< SPI2 global Interrupt */ + USART1_IRQn = 37, /*!< USART1 global Interrupt */ + USART2_IRQn = 38, /*!< USART2 global Interrupt */ + USART3_IRQn = 39, /*!< USART3 global Interrupt */ + EXTI15_10_IRQn = 40, /*!< External Line[15:10] Interrupts */ + RTCAlarm_IRQn = 41, /*!< RTC Alarm through EXTI Line Interrupt */ + CEC_IRQn = 42, /*!< HDMI-CEC Interrupt */ + TIM12_IRQn = 43, /*!< TIM12 global Interrupt */ + TIM13_IRQn = 44, /*!< TIM13 global Interrupt */ + TIM14_IRQn = 45, /*!< TIM14 global Interrupt */ + TIM5_IRQn = 50, /*!< TIM5 global Interrupt */ + SPI3_IRQn = 51, /*!< SPI3 global Interrupt */ + UART4_IRQn = 52, /*!< UART4 global Interrupt */ + UART5_IRQn = 53, /*!< UART5 global Interrupt */ + TIM6_DAC_IRQn = 54, /*!< TIM6 and DAC underrun Interrupt */ + TIM7_IRQn = 55, /*!< TIM7 Interrupt */ + DMA2_Channel1_IRQn = 56, /*!< DMA2 Channel 1 global Interrupt */ + DMA2_Channel2_IRQn = 57, /*!< DMA2 Channel 2 global Interrupt */ + DMA2_Channel3_IRQn = 58, /*!< DMA2 Channel 3 global Interrupt */ + DMA2_Channel4_5_IRQn = 59, /*!< DMA2 Channel 4 and Channel 5 global Interrupt */ + DMA2_Channel5_IRQn = 60 /*!< DMA2 Channel 5 global Interrupt (DMA2 Channel 5 is + mapped at position 60 only if the MISC_REMAP bit in + the AFIO_MAPR2 register is set) */ +#endif /* STM32F10X_HD_VL */ + +#ifdef STM32F10X_XL + ADC1_2_IRQn = 18, /*!< ADC1 and ADC2 global Interrupt */ + USB_HP_CAN1_TX_IRQn = 19, /*!< USB Device High Priority or CAN1 TX Interrupts */ + USB_LP_CAN1_RX0_IRQn = 20, /*!< USB Device Low Priority or CAN1 RX0 Interrupts */ + CAN1_RX1_IRQn = 21, /*!< CAN1 RX1 Interrupt */ + CAN1_SCE_IRQn = 22, /*!< CAN1 SCE Interrupt */ + EXTI9_5_IRQn = 23, /*!< External Line[9:5] Interrupts */ + TIM1_BRK_TIM9_IRQn = 24, /*!< TIM1 Break Interrupt and TIM9 global Interrupt */ + TIM1_UP_TIM10_IRQn = 25, /*!< TIM1 Update Interrupt and TIM10 global Interrupt */ + TIM1_TRG_COM_TIM11_IRQn = 26, /*!< TIM1 Trigger and Commutation Interrupt and TIM11 global interrupt */ + TIM1_CC_IRQn = 27, /*!< TIM1 Capture Compare Interrupt */ + TIM2_IRQn = 28, /*!< TIM2 global Interrupt */ + TIM3_IRQn = 29, /*!< TIM3 global Interrupt */ + TIM4_IRQn = 30, /*!< TIM4 global Interrupt */ + I2C1_EV_IRQn = 31, /*!< I2C1 Event Interrupt */ + I2C1_ER_IRQn = 32, /*!< I2C1 Error Interrupt */ + I2C2_EV_IRQn = 33, /*!< I2C2 Event Interrupt */ + I2C2_ER_IRQn = 34, /*!< I2C2 Error Interrupt */ + SPI1_IRQn = 35, /*!< SPI1 global Interrupt */ + SPI2_IRQn = 36, /*!< SPI2 global Interrupt */ + USART1_IRQn = 37, /*!< USART1 global Interrupt */ + USART2_IRQn = 38, /*!< USART2 global Interrupt */ + USART3_IRQn = 39, /*!< USART3 global Interrupt */ + EXTI15_10_IRQn = 40, /*!< External Line[15:10] Interrupts */ + RTCAlarm_IRQn = 41, /*!< RTC Alarm through EXTI Line Interrupt */ + USBWakeUp_IRQn = 42, /*!< USB Device WakeUp from suspend through EXTI Line Interrupt */ + TIM8_BRK_TIM12_IRQn = 43, /*!< TIM8 Break Interrupt and TIM12 global Interrupt */ + TIM8_UP_TIM13_IRQn = 44, /*!< TIM8 Update Interrupt and TIM13 global Interrupt */ + TIM8_TRG_COM_TIM14_IRQn = 45, /*!< TIM8 Trigger and Commutation Interrupt and TIM14 global interrupt */ + TIM8_CC_IRQn = 46, /*!< TIM8 Capture Compare Interrupt */ + ADC3_IRQn = 47, /*!< ADC3 global Interrupt */ + FSMC_IRQn = 48, /*!< FSMC global Interrupt */ + SDIO_IRQn = 49, /*!< SDIO global Interrupt */ + TIM5_IRQn = 50, /*!< TIM5 global Interrupt */ + SPI3_IRQn = 51, /*!< SPI3 global Interrupt */ + UART4_IRQn = 52, /*!< UART4 global Interrupt */ + UART5_IRQn = 53, /*!< UART5 global Interrupt */ + TIM6_IRQn = 54, /*!< TIM6 global Interrupt */ + TIM7_IRQn = 55, /*!< TIM7 global Interrupt */ + DMA2_Channel1_IRQn = 56, /*!< DMA2 Channel 1 global Interrupt */ + DMA2_Channel2_IRQn = 57, /*!< DMA2 Channel 2 global Interrupt */ + DMA2_Channel3_IRQn = 58, /*!< DMA2 Channel 3 global Interrupt */ + DMA2_Channel4_5_IRQn = 59 /*!< DMA2 Channel 4 and Channel 5 global Interrupt */ +#endif /* STM32F10X_XL */ + +#ifdef STM32F10X_CL + ADC1_2_IRQn = 18, /*!< ADC1 and ADC2 global Interrupt */ + CAN1_TX_IRQn = 19, /*!< USB Device High Priority or CAN1 TX Interrupts */ + CAN1_RX0_IRQn = 20, /*!< USB Device Low Priority or CAN1 RX0 Interrupts */ + CAN1_RX1_IRQn = 21, /*!< CAN1 RX1 Interrupt */ + CAN1_SCE_IRQn = 22, /*!< CAN1 SCE Interrupt */ + EXTI9_5_IRQn = 23, /*!< External Line[9:5] Interrupts */ + TIM1_BRK_IRQn = 24, /*!< TIM1 Break Interrupt */ + TIM1_UP_IRQn = 25, /*!< TIM1 Update Interrupt */ + TIM1_TRG_COM_IRQn = 26, /*!< TIM1 Trigger and Commutation Interrupt */ + TIM1_CC_IRQn = 27, /*!< TIM1 Capture Compare Interrupt */ + TIM2_IRQn = 28, /*!< TIM2 global Interrupt */ + TIM3_IRQn = 29, /*!< TIM3 global Interrupt */ + TIM4_IRQn = 30, /*!< TIM4 global Interrupt */ + I2C1_EV_IRQn = 31, /*!< I2C1 Event Interrupt */ + I2C1_ER_IRQn = 32, /*!< I2C1 Error Interrupt */ + I2C2_EV_IRQn = 33, /*!< I2C2 Event Interrupt */ + I2C2_ER_IRQn = 34, /*!< I2C2 Error Interrupt */ + SPI1_IRQn = 35, /*!< SPI1 global Interrupt */ + SPI2_IRQn = 36, /*!< SPI2 global Interrupt */ + USART1_IRQn = 37, /*!< USART1 global Interrupt */ + USART2_IRQn = 38, /*!< USART2 global Interrupt */ + USART3_IRQn = 39, /*!< USART3 global Interrupt */ + EXTI15_10_IRQn = 40, /*!< External Line[15:10] Interrupts */ + RTCAlarm_IRQn = 41, /*!< RTC Alarm through EXTI Line Interrupt */ + OTG_FS_WKUP_IRQn = 42, /*!< USB OTG FS WakeUp from suspend through EXTI Line Interrupt */ + TIM5_IRQn = 50, /*!< TIM5 global Interrupt */ + SPI3_IRQn = 51, /*!< SPI3 global Interrupt */ + UART4_IRQn = 52, /*!< UART4 global Interrupt */ + UART5_IRQn = 53, /*!< UART5 global Interrupt */ + TIM6_IRQn = 54, /*!< TIM6 global Interrupt */ + TIM7_IRQn = 55, /*!< TIM7 global Interrupt */ + DMA2_Channel1_IRQn = 56, /*!< DMA2 Channel 1 global Interrupt */ + DMA2_Channel2_IRQn = 57, /*!< DMA2 Channel 2 global Interrupt */ + DMA2_Channel3_IRQn = 58, /*!< DMA2 Channel 3 global Interrupt */ + DMA2_Channel4_IRQn = 59, /*!< DMA2 Channel 4 global Interrupt */ + DMA2_Channel5_IRQn = 60, /*!< DMA2 Channel 5 global Interrupt */ + ETH_IRQn = 61, /*!< Ethernet global Interrupt */ + ETH_WKUP_IRQn = 62, /*!< Ethernet Wakeup through EXTI line Interrupt */ + CAN2_TX_IRQn = 63, /*!< CAN2 TX Interrupt */ + CAN2_RX0_IRQn = 64, /*!< CAN2 RX0 Interrupt */ + CAN2_RX1_IRQn = 65, /*!< CAN2 RX1 Interrupt */ + CAN2_SCE_IRQn = 66, /*!< CAN2 SCE Interrupt */ + OTG_FS_IRQn = 67 /*!< USB OTG FS global Interrupt */ +#endif /* STM32F10X_CL */ +} IRQn_Type; + +/** + * @} + */ + +#include "core_cm3.h" +#include "system_stm32f10x.h" +#include + +/** @addtogroup Exported_types + * @{ + */ + +/*!< STM32F10x Standard Peripheral Library old types (maintained for legacy purpose) */ +typedef int32_t s32; +typedef int16_t s16; +typedef int8_t s8; + +typedef const int32_t sc32; /*!< Read Only */ +typedef const int16_t sc16; /*!< Read Only */ +typedef const int8_t sc8; /*!< Read Only */ + +typedef __IO int32_t vs32; +typedef __IO int16_t vs16; +typedef __IO int8_t vs8; + +typedef __I int32_t vsc32; /*!< Read Only */ +typedef __I int16_t vsc16; /*!< Read Only */ +typedef __I int8_t vsc8; /*!< Read Only */ + +typedef uint32_t u32; +typedef uint16_t u16; +typedef uint8_t u8; + +typedef const uint32_t uc32; /*!< Read Only */ +typedef const uint16_t uc16; /*!< Read Only */ +typedef const uint8_t uc8; /*!< Read Only */ + +typedef __IO uint32_t vu32; +typedef __IO uint16_t vu16; +typedef __IO uint8_t vu8; + +typedef __I uint32_t vuc32; /*!< Read Only */ +typedef __I uint16_t vuc16; /*!< Read Only */ +typedef __I uint8_t vuc8; /*!< Read Only */ + +typedef enum {RESET = 0, SET = !RESET} FlagStatus, ITStatus; + +typedef enum {DISABLE = 0, ENABLE = !DISABLE} FunctionalState; +#define IS_FUNCTIONAL_STATE(STATE) (((STATE) == DISABLE) || ((STATE) == ENABLE)) + +typedef enum {ERROR = 0, SUCCESS = !ERROR} ErrorStatus; + +/*!< STM32F10x Standard Peripheral Library old definitions (maintained for legacy purpose) */ +#define HSEStartUp_TimeOut HSE_STARTUP_TIMEOUT +#define HSE_Value HSE_VALUE +#define HSI_Value HSI_VALUE +/** + * @} + */ + +/** @addtogroup Peripheral_registers_structures + * @{ + */ + +/** + * @brief Analog to Digital Converter + */ + +typedef struct +{ + __IO uint32_t SR; + __IO uint32_t CR1; + __IO uint32_t CR2; + __IO uint32_t SMPR1; + __IO uint32_t SMPR2; + __IO uint32_t JOFR1; + __IO uint32_t JOFR2; + __IO uint32_t JOFR3; + __IO uint32_t JOFR4; + __IO uint32_t HTR; + __IO uint32_t LTR; + __IO uint32_t SQR1; + __IO uint32_t SQR2; + __IO uint32_t SQR3; + __IO uint32_t JSQR; + __IO uint32_t JDR1; + __IO uint32_t JDR2; + __IO uint32_t JDR3; + __IO uint32_t JDR4; + __IO uint32_t DR; +} ADC_TypeDef; + +/** + * @brief Backup Registers + */ + +typedef struct +{ + uint32_t RESERVED0; + __IO uint16_t DR1; + uint16_t RESERVED1; + __IO uint16_t DR2; + uint16_t RESERVED2; + __IO uint16_t DR3; + uint16_t RESERVED3; + __IO uint16_t DR4; + uint16_t RESERVED4; + __IO uint16_t DR5; + uint16_t RESERVED5; + __IO uint16_t DR6; + uint16_t RESERVED6; + __IO uint16_t DR7; + uint16_t RESERVED7; + __IO uint16_t DR8; + uint16_t RESERVED8; + __IO uint16_t DR9; + uint16_t RESERVED9; + __IO uint16_t DR10; + uint16_t RESERVED10; + __IO uint16_t RTCCR; + uint16_t RESERVED11; + __IO uint16_t CR; + uint16_t RESERVED12; + __IO uint16_t CSR; + uint16_t RESERVED13[5]; + __IO uint16_t DR11; + uint16_t RESERVED14; + __IO uint16_t DR12; + uint16_t RESERVED15; + __IO uint16_t DR13; + uint16_t RESERVED16; + __IO uint16_t DR14; + uint16_t RESERVED17; + __IO uint16_t DR15; + uint16_t RESERVED18; + __IO uint16_t DR16; + uint16_t RESERVED19; + __IO uint16_t DR17; + uint16_t RESERVED20; + __IO uint16_t DR18; + uint16_t RESERVED21; + __IO uint16_t DR19; + uint16_t RESERVED22; + __IO uint16_t DR20; + uint16_t RESERVED23; + __IO uint16_t DR21; + uint16_t RESERVED24; + __IO uint16_t DR22; + uint16_t RESERVED25; + __IO uint16_t DR23; + uint16_t RESERVED26; + __IO uint16_t DR24; + uint16_t RESERVED27; + __IO uint16_t DR25; + uint16_t RESERVED28; + __IO uint16_t DR26; + uint16_t RESERVED29; + __IO uint16_t DR27; + uint16_t RESERVED30; + __IO uint16_t DR28; + uint16_t RESERVED31; + __IO uint16_t DR29; + uint16_t RESERVED32; + __IO uint16_t DR30; + uint16_t RESERVED33; + __IO uint16_t DR31; + uint16_t RESERVED34; + __IO uint16_t DR32; + uint16_t RESERVED35; + __IO uint16_t DR33; + uint16_t RESERVED36; + __IO uint16_t DR34; + uint16_t RESERVED37; + __IO uint16_t DR35; + uint16_t RESERVED38; + __IO uint16_t DR36; + uint16_t RESERVED39; + __IO uint16_t DR37; + uint16_t RESERVED40; + __IO uint16_t DR38; + uint16_t RESERVED41; + __IO uint16_t DR39; + uint16_t RESERVED42; + __IO uint16_t DR40; + uint16_t RESERVED43; + __IO uint16_t DR41; + uint16_t RESERVED44; + __IO uint16_t DR42; + uint16_t RESERVED45; +} BKP_TypeDef; + +/** + * @brief Controller Area Network TxMailBox + */ + +typedef struct +{ + __IO uint32_t TIR; + __IO uint32_t TDTR; + __IO uint32_t TDLR; + __IO uint32_t TDHR; +} CAN_TxMailBox_TypeDef; + +/** + * @brief Controller Area Network FIFOMailBox + */ + +typedef struct +{ + __IO uint32_t RIR; + __IO uint32_t RDTR; + __IO uint32_t RDLR; + __IO uint32_t RDHR; +} CAN_FIFOMailBox_TypeDef; + +/** + * @brief Controller Area Network FilterRegister + */ + +typedef struct +{ + __IO uint32_t FR1; + __IO uint32_t FR2; +} CAN_FilterRegister_TypeDef; + +/** + * @brief Controller Area Network + */ + +typedef struct +{ + __IO uint32_t MCR; + __IO uint32_t MSR; + __IO uint32_t TSR; + __IO uint32_t RF0R; + __IO uint32_t RF1R; + __IO uint32_t IER; + __IO uint32_t ESR; + __IO uint32_t BTR; + uint32_t RESERVED0[88]; + CAN_TxMailBox_TypeDef sTxMailBox[3]; + CAN_FIFOMailBox_TypeDef sFIFOMailBox[2]; + uint32_t RESERVED1[12]; + __IO uint32_t FMR; + __IO uint32_t FM1R; + uint32_t RESERVED2; + __IO uint32_t FS1R; + uint32_t RESERVED3; + __IO uint32_t FFA1R; + uint32_t RESERVED4; + __IO uint32_t FA1R; + uint32_t RESERVED5[8]; +#ifndef STM32F10X_CL + CAN_FilterRegister_TypeDef sFilterRegister[14]; +#else + CAN_FilterRegister_TypeDef sFilterRegister[28]; +#endif /* STM32F10X_CL */ +} CAN_TypeDef; + +/** + * @brief Consumer Electronics Control (CEC) + */ +typedef struct +{ + __IO uint32_t CFGR; + __IO uint32_t OAR; + __IO uint32_t PRES; + __IO uint32_t ESR; + __IO uint32_t CSR; + __IO uint32_t TXD; + __IO uint32_t RXD; +} CEC_TypeDef; + +/** + * @brief CRC calculation unit + */ + +typedef struct +{ + __IO uint32_t DR; + __IO uint8_t IDR; + uint8_t RESERVED0; + uint16_t RESERVED1; + __IO uint32_t CR; +} CRC_TypeDef; + +/** + * @brief Digital to Analog Converter + */ + +typedef struct +{ + __IO uint32_t CR; + __IO uint32_t SWTRIGR; + __IO uint32_t DHR12R1; + __IO uint32_t DHR12L1; + __IO uint32_t DHR8R1; + __IO uint32_t DHR12R2; + __IO uint32_t DHR12L2; + __IO uint32_t DHR8R2; + __IO uint32_t DHR12RD; + __IO uint32_t DHR12LD; + __IO uint32_t DHR8RD; + __IO uint32_t DOR1; + __IO uint32_t DOR2; +#if defined (STM32F10X_LD_VL) || defined (STM32F10X_MD_VL) || defined (STM32F10X_HD_VL) + __IO uint32_t SR; +#endif +} DAC_TypeDef; + +/** + * @brief Debug MCU + */ + +typedef struct +{ + __IO uint32_t IDCODE; + __IO uint32_t CR; +}DBGMCU_TypeDef; + +/** + * @brief DMA Controller + */ + +typedef struct +{ + __IO uint32_t CCR; + __IO uint32_t CNDTR; + __IO uint32_t CPAR; + __IO uint32_t CMAR; +} DMA_Channel_TypeDef; + +typedef struct +{ + __IO uint32_t ISR; + __IO uint32_t IFCR; +} DMA_TypeDef; + +/** + * @brief Ethernet MAC + */ + +typedef struct +{ + __IO uint32_t MACCR; + __IO uint32_t MACFFR; + __IO uint32_t MACHTHR; + __IO uint32_t MACHTLR; + __IO uint32_t MACMIIAR; + __IO uint32_t MACMIIDR; + __IO uint32_t MACFCR; + __IO uint32_t MACVLANTR; /* 8 */ + uint32_t RESERVED0[2]; + __IO uint32_t MACRWUFFR; /* 11 */ + __IO uint32_t MACPMTCSR; + uint32_t RESERVED1[2]; + __IO uint32_t MACSR; /* 15 */ + __IO uint32_t MACIMR; + __IO uint32_t MACA0HR; + __IO uint32_t MACA0LR; + __IO uint32_t MACA1HR; + __IO uint32_t MACA1LR; + __IO uint32_t MACA2HR; + __IO uint32_t MACA2LR; + __IO uint32_t MACA3HR; + __IO uint32_t MACA3LR; /* 24 */ + uint32_t RESERVED2[40]; + __IO uint32_t MMCCR; /* 65 */ + __IO uint32_t MMCRIR; + __IO uint32_t MMCTIR; + __IO uint32_t MMCRIMR; + __IO uint32_t MMCTIMR; /* 69 */ + uint32_t RESERVED3[14]; + __IO uint32_t MMCTGFSCCR; /* 84 */ + __IO uint32_t MMCTGFMSCCR; + uint32_t RESERVED4[5]; + __IO uint32_t MMCTGFCR; + uint32_t RESERVED5[10]; + __IO uint32_t MMCRFCECR; + __IO uint32_t MMCRFAECR; + uint32_t RESERVED6[10]; + __IO uint32_t MMCRGUFCR; + uint32_t RESERVED7[334]; + __IO uint32_t PTPTSCR; + __IO uint32_t PTPSSIR; + __IO uint32_t PTPTSHR; + __IO uint32_t PTPTSLR; + __IO uint32_t PTPTSHUR; + __IO uint32_t PTPTSLUR; + __IO uint32_t PTPTSAR; + __IO uint32_t PTPTTHR; + __IO uint32_t PTPTTLR; + uint32_t RESERVED8[567]; + __IO uint32_t DMABMR; + __IO uint32_t DMATPDR; + __IO uint32_t DMARPDR; + __IO uint32_t DMARDLAR; + __IO uint32_t DMATDLAR; + __IO uint32_t DMASR; + __IO uint32_t DMAOMR; + __IO uint32_t DMAIER; + __IO uint32_t DMAMFBOCR; + uint32_t RESERVED9[9]; + __IO uint32_t DMACHTDR; + __IO uint32_t DMACHRDR; + __IO uint32_t DMACHTBAR; + __IO uint32_t DMACHRBAR; +} ETH_TypeDef; + +/** + * @brief External Interrupt/Event Controller + */ + +typedef struct +{ + __IO uint32_t IMR; + __IO uint32_t EMR; + __IO uint32_t RTSR; + __IO uint32_t FTSR; + __IO uint32_t SWIER; + __IO uint32_t PR; +} EXTI_TypeDef; + +/** + * @brief FLASH Registers + */ + +typedef struct +{ + __IO uint32_t ACR; + __IO uint32_t KEYR; + __IO uint32_t OPTKEYR; + __IO uint32_t SR; + __IO uint32_t CR; + __IO uint32_t AR; + __IO uint32_t RESERVED; + __IO uint32_t OBR; + __IO uint32_t WRPR; +#ifdef STM32F10X_XL + uint32_t RESERVED1[8]; + __IO uint32_t KEYR2; + uint32_t RESERVED2; + __IO uint32_t SR2; + __IO uint32_t CR2; + __IO uint32_t AR2; +#endif /* STM32F10X_XL */ +} FLASH_TypeDef; + +/** + * @brief Option Bytes Registers + */ + +typedef struct +{ + __IO uint16_t RDP; + __IO uint16_t USER; + __IO uint16_t Data0; + __IO uint16_t Data1; + __IO uint16_t WRP0; + __IO uint16_t WRP1; + __IO uint16_t WRP2; + __IO uint16_t WRP3; +} OB_TypeDef; + +/** + * @brief Flexible Static Memory Controller + */ + +typedef struct +{ + __IO uint32_t BTCR[8]; +} FSMC_Bank1_TypeDef; + +/** + * @brief Flexible Static Memory Controller Bank1E + */ + +typedef struct +{ + __IO uint32_t BWTR[7]; +} FSMC_Bank1E_TypeDef; + +/** + * @brief Flexible Static Memory Controller Bank2 + */ + +typedef struct +{ + __IO uint32_t PCR2; + __IO uint32_t SR2; + __IO uint32_t PMEM2; + __IO uint32_t PATT2; + uint32_t RESERVED0; + __IO uint32_t ECCR2; +} FSMC_Bank2_TypeDef; + +/** + * @brief Flexible Static Memory Controller Bank3 + */ + +typedef struct +{ + __IO uint32_t PCR3; + __IO uint32_t SR3; + __IO uint32_t PMEM3; + __IO uint32_t PATT3; + uint32_t RESERVED0; + __IO uint32_t ECCR3; +} FSMC_Bank3_TypeDef; + +/** + * @brief Flexible Static Memory Controller Bank4 + */ + +typedef struct +{ + __IO uint32_t PCR4; + __IO uint32_t SR4; + __IO uint32_t PMEM4; + __IO uint32_t PATT4; + __IO uint32_t PIO4; +} FSMC_Bank4_TypeDef; + +/** + * @brief General Purpose I/O + */ + +typedef struct +{ + __IO uint32_t CRL; + __IO uint32_t CRH; + __IO uint32_t IDR; + __IO uint32_t ODR; + __IO uint32_t BSRR; + __IO uint32_t BRR; + __IO uint32_t LCKR; +} GPIO_TypeDef; + +/** + * @brief Alternate Function I/O + */ + +typedef struct +{ + __IO uint32_t EVCR; + __IO uint32_t MAPR; + __IO uint32_t EXTICR[4]; + uint32_t RESERVED0; + __IO uint32_t MAPR2; +} AFIO_TypeDef; +/** + * @brief Inter Integrated Circuit Interface + */ + +typedef struct +{ + __IO uint16_t CR1; + uint16_t RESERVED0; + __IO uint16_t CR2; + uint16_t RESERVED1; + __IO uint16_t OAR1; + uint16_t RESERVED2; + __IO uint16_t OAR2; + uint16_t RESERVED3; + __IO uint16_t DR; + uint16_t RESERVED4; + __IO uint16_t SR1; + uint16_t RESERVED5; + __IO uint16_t SR2; + uint16_t RESERVED6; + __IO uint16_t CCR; + uint16_t RESERVED7; + __IO uint16_t TRISE; + uint16_t RESERVED8; +} I2C_TypeDef; + +/** + * @brief Independent WATCHDOG + */ + +typedef struct +{ + __IO uint32_t KR; + __IO uint32_t PR; + __IO uint32_t RLR; + __IO uint32_t SR; +} IWDG_TypeDef; + +/** + * @brief Power Control + */ + +typedef struct +{ + __IO uint32_t CR; + __IO uint32_t CSR; +} PWR_TypeDef; + +/** + * @brief Reset and Clock Control + */ + +typedef struct +{ + __IO uint32_t CR; + __IO uint32_t CFGR; + __IO uint32_t CIR; + __IO uint32_t APB2RSTR; + __IO uint32_t APB1RSTR; + __IO uint32_t AHBENR; + __IO uint32_t APB2ENR; + __IO uint32_t APB1ENR; + __IO uint32_t BDCR; + __IO uint32_t CSR; + +#ifdef STM32F10X_CL + __IO uint32_t AHBRSTR; + __IO uint32_t CFGR2; +#endif /* STM32F10X_CL */ + +#if defined (STM32F10X_LD_VL) || defined (STM32F10X_MD_VL) || defined (STM32F10X_HD_VL) + uint32_t RESERVED0; + __IO uint32_t CFGR2; +#endif /* STM32F10X_LD_VL || STM32F10X_MD_VL || STM32F10X_HD_VL */ +} RCC_TypeDef; + +/** + * @brief Real-Time Clock + */ + +typedef struct +{ + __IO uint16_t CRH; + uint16_t RESERVED0; + __IO uint16_t CRL; + uint16_t RESERVED1; + __IO uint16_t PRLH; + uint16_t RESERVED2; + __IO uint16_t PRLL; + uint16_t RESERVED3; + __IO uint16_t DIVH; + uint16_t RESERVED4; + __IO uint16_t DIVL; + uint16_t RESERVED5; + __IO uint16_t CNTH; + uint16_t RESERVED6; + __IO uint16_t CNTL; + uint16_t RESERVED7; + __IO uint16_t ALRH; + uint16_t RESERVED8; + __IO uint16_t ALRL; + uint16_t RESERVED9; +} RTC_TypeDef; + +/** + * @brief SD host Interface + */ + +typedef struct +{ + __IO uint32_t POWER; + __IO uint32_t CLKCR; + __IO uint32_t ARG; + __IO uint32_t CMD; + __I uint32_t RESPCMD; + __I uint32_t RESP1; + __I uint32_t RESP2; + __I uint32_t RESP3; + __I uint32_t RESP4; + __IO uint32_t DTIMER; + __IO uint32_t DLEN; + __IO uint32_t DCTRL; + __I uint32_t DCOUNT; + __I uint32_t STA; + __IO uint32_t ICR; + __IO uint32_t MASK; + uint32_t RESERVED0[2]; + __I uint32_t FIFOCNT; + uint32_t RESERVED1[13]; + __IO uint32_t FIFO; +} SDIO_TypeDef; + +/** + * @brief Serial Peripheral Interface + */ + +typedef struct +{ + __IO uint16_t CR1; + uint16_t RESERVED0; + __IO uint16_t CR2; + uint16_t RESERVED1; + __IO uint16_t SR; + uint16_t RESERVED2; + __IO uint16_t DR; + uint16_t RESERVED3; + __IO uint16_t CRCPR; + uint16_t RESERVED4; + __IO uint16_t RXCRCR; + uint16_t RESERVED5; + __IO uint16_t TXCRCR; + uint16_t RESERVED6; + __IO uint16_t I2SCFGR; + uint16_t RESERVED7; + __IO uint16_t I2SPR; + uint16_t RESERVED8; +} SPI_TypeDef; + +/** + * @brief TIM + */ + +typedef struct +{ + __IO uint16_t CR1; + uint16_t RESERVED0; + __IO uint16_t CR2; + uint16_t RESERVED1; + __IO uint16_t SMCR; + uint16_t RESERVED2; + __IO uint16_t DIER; + uint16_t RESERVED3; + __IO uint16_t SR; + uint16_t RESERVED4; + __IO uint16_t EGR; + uint16_t RESERVED5; + __IO uint16_t CCMR1; + uint16_t RESERVED6; + __IO uint16_t CCMR2; + uint16_t RESERVED7; + __IO uint16_t CCER; + uint16_t RESERVED8; + __IO uint16_t CNT; + uint16_t RESERVED9; + __IO uint16_t PSC; + uint16_t RESERVED10; + __IO uint16_t ARR; + uint16_t RESERVED11; + __IO uint16_t RCR; + uint16_t RESERVED12; + __IO uint16_t CCR1; + uint16_t RESERVED13; + __IO uint16_t CCR2; + uint16_t RESERVED14; + __IO uint16_t CCR3; + uint16_t RESERVED15; + __IO uint16_t CCR4; + uint16_t RESERVED16; + __IO uint16_t BDTR; + uint16_t RESERVED17; + __IO uint16_t DCR; + uint16_t RESERVED18; + __IO uint16_t DMAR; + uint16_t RESERVED19; +} TIM_TypeDef; + +/** + * @brief Universal Synchronous Asynchronous Receiver Transmitter + */ + +typedef struct +{ + __IO uint16_t SR; + uint16_t RESERVED0; + __IO uint16_t DR; + uint16_t RESERVED1; + __IO uint16_t BRR; + uint16_t RESERVED2; + __IO uint16_t CR1; + uint16_t RESERVED3; + __IO uint16_t CR2; + uint16_t RESERVED4; + __IO uint16_t CR3; + uint16_t RESERVED5; + __IO uint16_t GTPR; + uint16_t RESERVED6; +} USART_TypeDef; + +/** + * @brief Window WATCHDOG + */ + +typedef struct +{ + __IO uint32_t CR; + __IO uint32_t CFR; + __IO uint32_t SR; +} WWDG_TypeDef; + +/** + * @} + */ + +/** @addtogroup Peripheral_memory_map + * @{ + */ + + +#define FLASH_BASE ((uint32_t)0x08000000) /*!< FLASH base address in the alias region */ +#define SRAM_BASE ((uint32_t)0x20000000) /*!< SRAM base address in the alias region */ +#define PERIPH_BASE ((uint32_t)0x40000000) /*!< Peripheral base address in the alias region */ + +#define SRAM_BB_BASE ((uint32_t)0x22000000) /*!< SRAM base address in the bit-band region */ +#define PERIPH_BB_BASE ((uint32_t)0x42000000) /*!< Peripheral base address in the bit-band region */ + +#define FSMC_R_BASE ((uint32_t)0xA0000000) /*!< FSMC registers base address */ + +/*!< Peripheral memory map */ +#define APB1PERIPH_BASE PERIPH_BASE +#define APB2PERIPH_BASE (PERIPH_BASE + 0x10000) +#define AHBPERIPH_BASE (PERIPH_BASE + 0x20000) + +#define TIM2_BASE (APB1PERIPH_BASE + 0x0000) +#define TIM3_BASE (APB1PERIPH_BASE + 0x0400) +#define TIM4_BASE (APB1PERIPH_BASE + 0x0800) +#define TIM5_BASE (APB1PERIPH_BASE + 0x0C00) +#define TIM6_BASE (APB1PERIPH_BASE + 0x1000) +#define TIM7_BASE (APB1PERIPH_BASE + 0x1400) +#define TIM12_BASE (APB1PERIPH_BASE + 0x1800) +#define TIM13_BASE (APB1PERIPH_BASE + 0x1C00) +#define TIM14_BASE (APB1PERIPH_BASE + 0x2000) +#define RTC_BASE (APB1PERIPH_BASE + 0x2800) +#define WWDG_BASE (APB1PERIPH_BASE + 0x2C00) +#define IWDG_BASE (APB1PERIPH_BASE + 0x3000) +#define SPI2_BASE (APB1PERIPH_BASE + 0x3800) +#define SPI3_BASE (APB1PERIPH_BASE + 0x3C00) +#define USART2_BASE (APB1PERIPH_BASE + 0x4400) +#define USART3_BASE (APB1PERIPH_BASE + 0x4800) +#define UART4_BASE (APB1PERIPH_BASE + 0x4C00) +#define UART5_BASE (APB1PERIPH_BASE + 0x5000) +#define I2C1_BASE (APB1PERIPH_BASE + 0x5400) +#define I2C2_BASE (APB1PERIPH_BASE + 0x5800) +#define CAN1_BASE (APB1PERIPH_BASE + 0x6400) +#define CAN2_BASE (APB1PERIPH_BASE + 0x6800) +#define BKP_BASE (APB1PERIPH_BASE + 0x6C00) +#define PWR_BASE (APB1PERIPH_BASE + 0x7000) +#define DAC_BASE (APB1PERIPH_BASE + 0x7400) +#define CEC_BASE (APB1PERIPH_BASE + 0x7800) + +#define AFIO_BASE (APB2PERIPH_BASE + 0x0000) +#define EXTI_BASE (APB2PERIPH_BASE + 0x0400) +#define GPIOA_BASE (APB2PERIPH_BASE + 0x0800) +#define GPIOB_BASE (APB2PERIPH_BASE + 0x0C00) +#define GPIOC_BASE (APB2PERIPH_BASE + 0x1000) +#define GPIOD_BASE (APB2PERIPH_BASE + 0x1400) +#define GPIOE_BASE (APB2PERIPH_BASE + 0x1800) +#define GPIOF_BASE (APB2PERIPH_BASE + 0x1C00) +#define GPIOG_BASE (APB2PERIPH_BASE + 0x2000) +#define ADC1_BASE (APB2PERIPH_BASE + 0x2400) +#define ADC2_BASE (APB2PERIPH_BASE + 0x2800) +#define TIM1_BASE (APB2PERIPH_BASE + 0x2C00) +#define SPI1_BASE (APB2PERIPH_BASE + 0x3000) +#define TIM8_BASE (APB2PERIPH_BASE + 0x3400) +#define USART1_BASE (APB2PERIPH_BASE + 0x3800) +#define ADC3_BASE (APB2PERIPH_BASE + 0x3C00) +#define TIM15_BASE (APB2PERIPH_BASE + 0x4000) +#define TIM16_BASE (APB2PERIPH_BASE + 0x4400) +#define TIM17_BASE (APB2PERIPH_BASE + 0x4800) +#define TIM9_BASE (APB2PERIPH_BASE + 0x4C00) +#define TIM10_BASE (APB2PERIPH_BASE + 0x5000) +#define TIM11_BASE (APB2PERIPH_BASE + 0x5400) + +#define SDIO_BASE (PERIPH_BASE + 0x18000) + +#define DMA1_BASE (AHBPERIPH_BASE + 0x0000) +#define DMA1_Channel1_BASE (AHBPERIPH_BASE + 0x0008) +#define DMA1_Channel2_BASE (AHBPERIPH_BASE + 0x001C) +#define DMA1_Channel3_BASE (AHBPERIPH_BASE + 0x0030) +#define DMA1_Channel4_BASE (AHBPERIPH_BASE + 0x0044) +#define DMA1_Channel5_BASE (AHBPERIPH_BASE + 0x0058) +#define DMA1_Channel6_BASE (AHBPERIPH_BASE + 0x006C) +#define DMA1_Channel7_BASE (AHBPERIPH_BASE + 0x0080) +#define DMA2_BASE (AHBPERIPH_BASE + 0x0400) +#define DMA2_Channel1_BASE (AHBPERIPH_BASE + 0x0408) +#define DMA2_Channel2_BASE (AHBPERIPH_BASE + 0x041C) +#define DMA2_Channel3_BASE (AHBPERIPH_BASE + 0x0430) +#define DMA2_Channel4_BASE (AHBPERIPH_BASE + 0x0444) +#define DMA2_Channel5_BASE (AHBPERIPH_BASE + 0x0458) +#define RCC_BASE (AHBPERIPH_BASE + 0x1000) +#define CRC_BASE (AHBPERIPH_BASE + 0x3000) + +#define FLASH_R_BASE (AHBPERIPH_BASE + 0x2000) /*!< Flash registers base address */ +#define OB_BASE ((uint32_t)0x1FFFF800) /*!< Flash Option Bytes base address */ + +#define ETH_BASE (AHBPERIPH_BASE + 0x8000) +#define ETH_MAC_BASE (ETH_BASE) +#define ETH_MMC_BASE (ETH_BASE + 0x0100) +#define ETH_PTP_BASE (ETH_BASE + 0x0700) +#define ETH_DMA_BASE (ETH_BASE + 0x1000) + +#define FSMC_Bank1_R_BASE (FSMC_R_BASE + 0x0000) /*!< FSMC Bank1 registers base address */ +#define FSMC_Bank1E_R_BASE (FSMC_R_BASE + 0x0104) /*!< FSMC Bank1E registers base address */ +#define FSMC_Bank2_R_BASE (FSMC_R_BASE + 0x0060) /*!< FSMC Bank2 registers base address */ +#define FSMC_Bank3_R_BASE (FSMC_R_BASE + 0x0080) /*!< FSMC Bank3 registers base address */ +#define FSMC_Bank4_R_BASE (FSMC_R_BASE + 0x00A0) /*!< FSMC Bank4 registers base address */ + +#define DBGMCU_BASE ((uint32_t)0xE0042000) /*!< Debug MCU registers base address */ + +/** + * @} + */ + +/** @addtogroup Peripheral_declaration + * @{ + */ + +#define TIM2 ((TIM_TypeDef *) TIM2_BASE) +#define TIM3 ((TIM_TypeDef *) TIM3_BASE) +#define TIM4 ((TIM_TypeDef *) TIM4_BASE) +#define TIM5 ((TIM_TypeDef *) TIM5_BASE) +#define TIM6 ((TIM_TypeDef *) TIM6_BASE) +#define TIM7 ((TIM_TypeDef *) TIM7_BASE) +#define TIM12 ((TIM_TypeDef *) TIM12_BASE) +#define TIM13 ((TIM_TypeDef *) TIM13_BASE) +#define TIM14 ((TIM_TypeDef *) TIM14_BASE) +#define RTC ((RTC_TypeDef *) RTC_BASE) +#define WWDG ((WWDG_TypeDef *) WWDG_BASE) +#define IWDG ((IWDG_TypeDef *) IWDG_BASE) +#define SPI2 ((SPI_TypeDef *) SPI2_BASE) +#define SPI3 ((SPI_TypeDef *) SPI3_BASE) +#define USART2 ((USART_TypeDef *) USART2_BASE) +#define USART3 ((USART_TypeDef *) USART3_BASE) +#define UART4 ((USART_TypeDef *) UART4_BASE) +#define UART5 ((USART_TypeDef *) UART5_BASE) +#define I2C1 ((I2C_TypeDef *) I2C1_BASE) +#define I2C2 ((I2C_TypeDef *) I2C2_BASE) +#define CAN1 ((CAN_TypeDef *) CAN1_BASE) +#define CAN2 ((CAN_TypeDef *) CAN2_BASE) +#define BKP ((BKP_TypeDef *) BKP_BASE) +#define PWR ((PWR_TypeDef *) PWR_BASE) +#define DAC ((DAC_TypeDef *) DAC_BASE) +#define CEC ((CEC_TypeDef *) CEC_BASE) +#define AFIO ((AFIO_TypeDef *) AFIO_BASE) +#define EXTI ((EXTI_TypeDef *) EXTI_BASE) +#define GPIOA ((GPIO_TypeDef *) GPIOA_BASE) +#define GPIOB ((GPIO_TypeDef *) GPIOB_BASE) +#define GPIOC ((GPIO_TypeDef *) GPIOC_BASE) +#define GPIOD ((GPIO_TypeDef *) GPIOD_BASE) +#define GPIOE ((GPIO_TypeDef *) GPIOE_BASE) +#define GPIOF ((GPIO_TypeDef *) GPIOF_BASE) +#define GPIOG ((GPIO_TypeDef *) GPIOG_BASE) +#define ADC1 ((ADC_TypeDef *) ADC1_BASE) +#define ADC2 ((ADC_TypeDef *) ADC2_BASE) +#define TIM1 ((TIM_TypeDef *) TIM1_BASE) +#define SPI1 ((SPI_TypeDef *) SPI1_BASE) +#define TIM8 ((TIM_TypeDef *) TIM8_BASE) +#define USART1 ((USART_TypeDef *) USART1_BASE) +#define ADC3 ((ADC_TypeDef *) ADC3_BASE) +#define TIM15 ((TIM_TypeDef *) TIM15_BASE) +#define TIM16 ((TIM_TypeDef *) TIM16_BASE) +#define TIM17 ((TIM_TypeDef *) TIM17_BASE) +#define TIM9 ((TIM_TypeDef *) TIM9_BASE) +#define TIM10 ((TIM_TypeDef *) TIM10_BASE) +#define TIM11 ((TIM_TypeDef *) TIM11_BASE) +#define SDIO ((SDIO_TypeDef *) SDIO_BASE) +#define DMA1 ((DMA_TypeDef *) DMA1_BASE) +#define DMA2 ((DMA_TypeDef *) DMA2_BASE) +#define DMA1_Channel1 ((DMA_Channel_TypeDef *) DMA1_Channel1_BASE) +#define DMA1_Channel2 ((DMA_Channel_TypeDef *) DMA1_Channel2_BASE) +#define DMA1_Channel3 ((DMA_Channel_TypeDef *) DMA1_Channel3_BASE) +#define DMA1_Channel4 ((DMA_Channel_TypeDef *) DMA1_Channel4_BASE) +#define DMA1_Channel5 ((DMA_Channel_TypeDef *) DMA1_Channel5_BASE) +#define DMA1_Channel6 ((DMA_Channel_TypeDef *) DMA1_Channel6_BASE) +#define DMA1_Channel7 ((DMA_Channel_TypeDef *) DMA1_Channel7_BASE) +#define DMA2_Channel1 ((DMA_Channel_TypeDef *) DMA2_Channel1_BASE) +#define DMA2_Channel2 ((DMA_Channel_TypeDef *) DMA2_Channel2_BASE) +#define DMA2_Channel3 ((DMA_Channel_TypeDef *) DMA2_Channel3_BASE) +#define DMA2_Channel4 ((DMA_Channel_TypeDef *) DMA2_Channel4_BASE) +#define DMA2_Channel5 ((DMA_Channel_TypeDef *) DMA2_Channel5_BASE) +#define RCC ((RCC_TypeDef *) RCC_BASE) +#define CRC ((CRC_TypeDef *) CRC_BASE) +#define FLASH ((FLASH_TypeDef *) FLASH_R_BASE) +#define OB ((OB_TypeDef *) OB_BASE) +#define ETH ((ETH_TypeDef *) ETH_BASE) +#define FSMC_Bank1 ((FSMC_Bank1_TypeDef *) FSMC_Bank1_R_BASE) +#define FSMC_Bank1E ((FSMC_Bank1E_TypeDef *) FSMC_Bank1E_R_BASE) +#define FSMC_Bank2 ((FSMC_Bank2_TypeDef *) FSMC_Bank2_R_BASE) +#define FSMC_Bank3 ((FSMC_Bank3_TypeDef *) FSMC_Bank3_R_BASE) +#define FSMC_Bank4 ((FSMC_Bank4_TypeDef *) FSMC_Bank4_R_BASE) +#define DBGMCU ((DBGMCU_TypeDef *) DBGMCU_BASE) + +/** + * @} + */ + +/** @addtogroup Exported_constants + * @{ + */ + + /** @addtogroup Peripheral_Registers_Bits_Definition + * @{ + */ + +/******************************************************************************/ +/* Peripheral Registers_Bits_Definition */ +/******************************************************************************/ + +/******************************************************************************/ +/* */ +/* CRC calculation unit */ +/* */ +/******************************************************************************/ + +/******************* Bit definition for CRC_DR register *********************/ +#define CRC_DR_DR ((uint32_t)0xFFFFFFFF) /*!< Data register bits */ + + +/******************* Bit definition for CRC_IDR register ********************/ +#define CRC_IDR_IDR ((uint8_t)0xFF) /*!< General-purpose 8-bit data register bits */ + + +/******************** Bit definition for CRC_CR register ********************/ +#define CRC_CR_RESET ((uint8_t)0x01) /*!< RESET bit */ + +/******************************************************************************/ +/* */ +/* Power Control */ +/* */ +/******************************************************************************/ + +/******************** Bit definition for PWR_CR register ********************/ +#define PWR_CR_LPDS ((uint16_t)0x0001) /*!< Low-Power Deepsleep */ +#define PWR_CR_PDDS ((uint16_t)0x0002) /*!< Power Down Deepsleep */ +#define PWR_CR_CWUF ((uint16_t)0x0004) /*!< Clear Wakeup Flag */ +#define PWR_CR_CSBF ((uint16_t)0x0008) /*!< Clear Standby Flag */ +#define PWR_CR_PVDE ((uint16_t)0x0010) /*!< Power Voltage Detector Enable */ + +#define PWR_CR_PLS ((uint16_t)0x00E0) /*!< PLS[2:0] bits (PVD Level Selection) */ +#define PWR_CR_PLS_0 ((uint16_t)0x0020) /*!< Bit 0 */ +#define PWR_CR_PLS_1 ((uint16_t)0x0040) /*!< Bit 1 */ +#define PWR_CR_PLS_2 ((uint16_t)0x0080) /*!< Bit 2 */ + +/*!< PVD level configuration */ +#define PWR_CR_PLS_2V2 ((uint16_t)0x0000) /*!< PVD level 2.2V */ +#define PWR_CR_PLS_2V3 ((uint16_t)0x0020) /*!< PVD level 2.3V */ +#define PWR_CR_PLS_2V4 ((uint16_t)0x0040) /*!< PVD level 2.4V */ +#define PWR_CR_PLS_2V5 ((uint16_t)0x0060) /*!< PVD level 2.5V */ +#define PWR_CR_PLS_2V6 ((uint16_t)0x0080) /*!< PVD level 2.6V */ +#define PWR_CR_PLS_2V7 ((uint16_t)0x00A0) /*!< PVD level 2.7V */ +#define PWR_CR_PLS_2V8 ((uint16_t)0x00C0) /*!< PVD level 2.8V */ +#define PWR_CR_PLS_2V9 ((uint16_t)0x00E0) /*!< PVD level 2.9V */ + +#define PWR_CR_DBP ((uint16_t)0x0100) /*!< Disable Backup Domain write protection */ + + +/******************* Bit definition for PWR_CSR register ********************/ +#define PWR_CSR_WUF ((uint16_t)0x0001) /*!< Wakeup Flag */ +#define PWR_CSR_SBF ((uint16_t)0x0002) /*!< Standby Flag */ +#define PWR_CSR_PVDO ((uint16_t)0x0004) /*!< PVD Output */ +#define PWR_CSR_EWUP ((uint16_t)0x0100) /*!< Enable WKUP pin */ + +/******************************************************************************/ +/* */ +/* Backup registers */ +/* */ +/******************************************************************************/ + +/******************* Bit definition for BKP_DR1 register ********************/ +#define BKP_DR1_D ((uint16_t)0xFFFF) /*!< Backup data */ + +/******************* Bit definition for BKP_DR2 register ********************/ +#define BKP_DR2_D ((uint16_t)0xFFFF) /*!< Backup data */ + +/******************* Bit definition for BKP_DR3 register ********************/ +#define BKP_DR3_D ((uint16_t)0xFFFF) /*!< Backup data */ + +/******************* Bit definition for BKP_DR4 register ********************/ +#define BKP_DR4_D ((uint16_t)0xFFFF) /*!< Backup data */ + +/******************* Bit definition for BKP_DR5 register ********************/ +#define BKP_DR5_D ((uint16_t)0xFFFF) /*!< Backup data */ + +/******************* Bit definition for BKP_DR6 register ********************/ +#define BKP_DR6_D ((uint16_t)0xFFFF) /*!< Backup data */ + +/******************* Bit definition for BKP_DR7 register ********************/ +#define BKP_DR7_D ((uint16_t)0xFFFF) /*!< Backup data */ + +/******************* Bit definition for BKP_DR8 register ********************/ +#define BKP_DR8_D ((uint16_t)0xFFFF) /*!< Backup data */ + +/******************* Bit definition for BKP_DR9 register ********************/ +#define BKP_DR9_D ((uint16_t)0xFFFF) /*!< Backup data */ + +/******************* Bit definition for BKP_DR10 register *******************/ +#define BKP_DR10_D ((uint16_t)0xFFFF) /*!< Backup data */ + +/******************* Bit definition for BKP_DR11 register *******************/ +#define BKP_DR11_D ((uint16_t)0xFFFF) /*!< Backup data */ + +/******************* Bit definition for BKP_DR12 register *******************/ +#define BKP_DR12_D ((uint16_t)0xFFFF) /*!< Backup data */ + +/******************* Bit definition for BKP_DR13 register *******************/ +#define BKP_DR13_D ((uint16_t)0xFFFF) /*!< Backup data */ + +/******************* Bit definition for BKP_DR14 register *******************/ +#define BKP_DR14_D ((uint16_t)0xFFFF) /*!< Backup data */ + +/******************* Bit definition for BKP_DR15 register *******************/ +#define BKP_DR15_D ((uint16_t)0xFFFF) /*!< Backup data */ + +/******************* Bit definition for BKP_DR16 register *******************/ +#define BKP_DR16_D ((uint16_t)0xFFFF) /*!< Backup data */ + +/******************* Bit definition for BKP_DR17 register *******************/ +#define BKP_DR17_D ((uint16_t)0xFFFF) /*!< Backup data */ + +/****************** Bit definition for BKP_DR18 register ********************/ +#define BKP_DR18_D ((uint16_t)0xFFFF) /*!< Backup data */ + +/******************* Bit definition for BKP_DR19 register *******************/ +#define BKP_DR19_D ((uint16_t)0xFFFF) /*!< Backup data */ + +/******************* Bit definition for BKP_DR20 register *******************/ +#define BKP_DR20_D ((uint16_t)0xFFFF) /*!< Backup data */ + +/******************* Bit definition for BKP_DR21 register *******************/ +#define BKP_DR21_D ((uint16_t)0xFFFF) /*!< Backup data */ + +/******************* Bit definition for BKP_DR22 register *******************/ +#define BKP_DR22_D ((uint16_t)0xFFFF) /*!< Backup data */ + +/******************* Bit definition for BKP_DR23 register *******************/ +#define BKP_DR23_D ((uint16_t)0xFFFF) /*!< Backup data */ + +/******************* Bit definition for BKP_DR24 register *******************/ +#define BKP_DR24_D ((uint16_t)0xFFFF) /*!< Backup data */ + +/******************* Bit definition for BKP_DR25 register *******************/ +#define BKP_DR25_D ((uint16_t)0xFFFF) /*!< Backup data */ + +/******************* Bit definition for BKP_DR26 register *******************/ +#define BKP_DR26_D ((uint16_t)0xFFFF) /*!< Backup data */ + +/******************* Bit definition for BKP_DR27 register *******************/ +#define BKP_DR27_D ((uint16_t)0xFFFF) /*!< Backup data */ + +/******************* Bit definition for BKP_DR28 register *******************/ +#define BKP_DR28_D ((uint16_t)0xFFFF) /*!< Backup data */ + +/******************* Bit definition for BKP_DR29 register *******************/ +#define BKP_DR29_D ((uint16_t)0xFFFF) /*!< Backup data */ + +/******************* Bit definition for BKP_DR30 register *******************/ +#define BKP_DR30_D ((uint16_t)0xFFFF) /*!< Backup data */ + +/******************* Bit definition for BKP_DR31 register *******************/ +#define BKP_DR31_D ((uint16_t)0xFFFF) /*!< Backup data */ + +/******************* Bit definition for BKP_DR32 register *******************/ +#define BKP_DR32_D ((uint16_t)0xFFFF) /*!< Backup data */ + +/******************* Bit definition for BKP_DR33 register *******************/ +#define BKP_DR33_D ((uint16_t)0xFFFF) /*!< Backup data */ + +/******************* Bit definition for BKP_DR34 register *******************/ +#define BKP_DR34_D ((uint16_t)0xFFFF) /*!< Backup data */ + +/******************* Bit definition for BKP_DR35 register *******************/ +#define BKP_DR35_D ((uint16_t)0xFFFF) /*!< Backup data */ + +/******************* Bit definition for BKP_DR36 register *******************/ +#define BKP_DR36_D ((uint16_t)0xFFFF) /*!< Backup data */ + +/******************* Bit definition for BKP_DR37 register *******************/ +#define BKP_DR37_D ((uint16_t)0xFFFF) /*!< Backup data */ + +/******************* Bit definition for BKP_DR38 register *******************/ +#define BKP_DR38_D ((uint16_t)0xFFFF) /*!< Backup data */ + +/******************* Bit definition for BKP_DR39 register *******************/ +#define BKP_DR39_D ((uint16_t)0xFFFF) /*!< Backup data */ + +/******************* Bit definition for BKP_DR40 register *******************/ +#define BKP_DR40_D ((uint16_t)0xFFFF) /*!< Backup data */ + +/******************* Bit definition for BKP_DR41 register *******************/ +#define BKP_DR41_D ((uint16_t)0xFFFF) /*!< Backup data */ + +/******************* Bit definition for BKP_DR42 register *******************/ +#define BKP_DR42_D ((uint16_t)0xFFFF) /*!< Backup data */ + +/****************** Bit definition for BKP_RTCCR register *******************/ +#define BKP_RTCCR_CAL ((uint16_t)0x007F) /*!< Calibration value */ +#define BKP_RTCCR_CCO ((uint16_t)0x0080) /*!< Calibration Clock Output */ +#define BKP_RTCCR_ASOE ((uint16_t)0x0100) /*!< Alarm or Second Output Enable */ +#define BKP_RTCCR_ASOS ((uint16_t)0x0200) /*!< Alarm or Second Output Selection */ + +/******************** Bit definition for BKP_CR register ********************/ +#define BKP_CR_TPE ((uint8_t)0x01) /*!< TAMPER pin enable */ +#define BKP_CR_TPAL ((uint8_t)0x02) /*!< TAMPER pin active level */ + +/******************* Bit definition for BKP_CSR register ********************/ +#define BKP_CSR_CTE ((uint16_t)0x0001) /*!< Clear Tamper event */ +#define BKP_CSR_CTI ((uint16_t)0x0002) /*!< Clear Tamper Interrupt */ +#define BKP_CSR_TPIE ((uint16_t)0x0004) /*!< TAMPER Pin interrupt enable */ +#define BKP_CSR_TEF ((uint16_t)0x0100) /*!< Tamper Event Flag */ +#define BKP_CSR_TIF ((uint16_t)0x0200) /*!< Tamper Interrupt Flag */ + +/******************************************************************************/ +/* */ +/* Reset and Clock Control */ +/* */ +/******************************************************************************/ + +/******************** Bit definition for RCC_CR register ********************/ +#define RCC_CR_HSION ((uint32_t)0x00000001) /*!< Internal High Speed clock enable */ +#define RCC_CR_HSIRDY ((uint32_t)0x00000002) /*!< Internal High Speed clock ready flag */ +#define RCC_CR_HSITRIM ((uint32_t)0x000000F8) /*!< Internal High Speed clock trimming */ +#define RCC_CR_HSICAL ((uint32_t)0x0000FF00) /*!< Internal High Speed clock Calibration */ +#define RCC_CR_HSEON ((uint32_t)0x00010000) /*!< External High Speed clock enable */ +#define RCC_CR_HSERDY ((uint32_t)0x00020000) /*!< External High Speed clock ready flag */ +#define RCC_CR_HSEBYP ((uint32_t)0x00040000) /*!< External High Speed clock Bypass */ +#define RCC_CR_CSSON ((uint32_t)0x00080000) /*!< Clock Security System enable */ +#define RCC_CR_PLLON ((uint32_t)0x01000000) /*!< PLL enable */ +#define RCC_CR_PLLRDY ((uint32_t)0x02000000) /*!< PLL clock ready flag */ + +#ifdef STM32F10X_CL + #define RCC_CR_PLL2ON ((uint32_t)0x04000000) /*!< PLL2 enable */ + #define RCC_CR_PLL2RDY ((uint32_t)0x08000000) /*!< PLL2 clock ready flag */ + #define RCC_CR_PLL3ON ((uint32_t)0x10000000) /*!< PLL3 enable */ + #define RCC_CR_PLL3RDY ((uint32_t)0x20000000) /*!< PLL3 clock ready flag */ +#endif /* STM32F10X_CL */ + +/******************* Bit definition for RCC_CFGR register *******************/ +/*!< SW configuration */ +#define RCC_CFGR_SW ((uint32_t)0x00000003) /*!< SW[1:0] bits (System clock Switch) */ +#define RCC_CFGR_SW_0 ((uint32_t)0x00000001) /*!< Bit 0 */ +#define RCC_CFGR_SW_1 ((uint32_t)0x00000002) /*!< Bit 1 */ + +#define RCC_CFGR_SW_HSI ((uint32_t)0x00000000) /*!< HSI selected as system clock */ +#define RCC_CFGR_SW_HSE ((uint32_t)0x00000001) /*!< HSE selected as system clock */ +#define RCC_CFGR_SW_PLL ((uint32_t)0x00000002) /*!< PLL selected as system clock */ + +/*!< SWS configuration */ +#define RCC_CFGR_SWS ((uint32_t)0x0000000C) /*!< SWS[1:0] bits (System Clock Switch Status) */ +#define RCC_CFGR_SWS_0 ((uint32_t)0x00000004) /*!< Bit 0 */ +#define RCC_CFGR_SWS_1 ((uint32_t)0x00000008) /*!< Bit 1 */ + +#define RCC_CFGR_SWS_HSI ((uint32_t)0x00000000) /*!< HSI oscillator used as system clock */ +#define RCC_CFGR_SWS_HSE ((uint32_t)0x00000004) /*!< HSE oscillator used as system clock */ +#define RCC_CFGR_SWS_PLL ((uint32_t)0x00000008) /*!< PLL used as system clock */ + +/*!< HPRE configuration */ +#define RCC_CFGR_HPRE ((uint32_t)0x000000F0) /*!< HPRE[3:0] bits (AHB prescaler) */ +#define RCC_CFGR_HPRE_0 ((uint32_t)0x00000010) /*!< Bit 0 */ +#define RCC_CFGR_HPRE_1 ((uint32_t)0x00000020) /*!< Bit 1 */ +#define RCC_CFGR_HPRE_2 ((uint32_t)0x00000040) /*!< Bit 2 */ +#define RCC_CFGR_HPRE_3 ((uint32_t)0x00000080) /*!< Bit 3 */ + +#define RCC_CFGR_HPRE_DIV1 ((uint32_t)0x00000000) /*!< SYSCLK not divided */ +#define RCC_CFGR_HPRE_DIV2 ((uint32_t)0x00000080) /*!< SYSCLK divided by 2 */ +#define RCC_CFGR_HPRE_DIV4 ((uint32_t)0x00000090) /*!< SYSCLK divided by 4 */ +#define RCC_CFGR_HPRE_DIV8 ((uint32_t)0x000000A0) /*!< SYSCLK divided by 8 */ +#define RCC_CFGR_HPRE_DIV16 ((uint32_t)0x000000B0) /*!< SYSCLK divided by 16 */ +#define RCC_CFGR_HPRE_DIV64 ((uint32_t)0x000000C0) /*!< SYSCLK divided by 64 */ +#define RCC_CFGR_HPRE_DIV128 ((uint32_t)0x000000D0) /*!< SYSCLK divided by 128 */ +#define RCC_CFGR_HPRE_DIV256 ((uint32_t)0x000000E0) /*!< SYSCLK divided by 256 */ +#define RCC_CFGR_HPRE_DIV512 ((uint32_t)0x000000F0) /*!< SYSCLK divided by 512 */ + +/*!< PPRE1 configuration */ +#define RCC_CFGR_PPRE1 ((uint32_t)0x00000700) /*!< PRE1[2:0] bits (APB1 prescaler) */ +#define RCC_CFGR_PPRE1_0 ((uint32_t)0x00000100) /*!< Bit 0 */ +#define RCC_CFGR_PPRE1_1 ((uint32_t)0x00000200) /*!< Bit 1 */ +#define RCC_CFGR_PPRE1_2 ((uint32_t)0x00000400) /*!< Bit 2 */ + +#define RCC_CFGR_PPRE1_DIV1 ((uint32_t)0x00000000) /*!< HCLK not divided */ +#define RCC_CFGR_PPRE1_DIV2 ((uint32_t)0x00000400) /*!< HCLK divided by 2 */ +#define RCC_CFGR_PPRE1_DIV4 ((uint32_t)0x00000500) /*!< HCLK divided by 4 */ +#define RCC_CFGR_PPRE1_DIV8 ((uint32_t)0x00000600) /*!< HCLK divided by 8 */ +#define RCC_CFGR_PPRE1_DIV16 ((uint32_t)0x00000700) /*!< HCLK divided by 16 */ + +/*!< PPRE2 configuration */ +#define RCC_CFGR_PPRE2 ((uint32_t)0x00003800) /*!< PRE2[2:0] bits (APB2 prescaler) */ +#define RCC_CFGR_PPRE2_0 ((uint32_t)0x00000800) /*!< Bit 0 */ +#define RCC_CFGR_PPRE2_1 ((uint32_t)0x00001000) /*!< Bit 1 */ +#define RCC_CFGR_PPRE2_2 ((uint32_t)0x00002000) /*!< Bit 2 */ + +#define RCC_CFGR_PPRE2_DIV1 ((uint32_t)0x00000000) /*!< HCLK not divided */ +#define RCC_CFGR_PPRE2_DIV2 ((uint32_t)0x00002000) /*!< HCLK divided by 2 */ +#define RCC_CFGR_PPRE2_DIV4 ((uint32_t)0x00002800) /*!< HCLK divided by 4 */ +#define RCC_CFGR_PPRE2_DIV8 ((uint32_t)0x00003000) /*!< HCLK divided by 8 */ +#define RCC_CFGR_PPRE2_DIV16 ((uint32_t)0x00003800) /*!< HCLK divided by 16 */ + +/*!< ADCPPRE configuration */ +#define RCC_CFGR_ADCPRE ((uint32_t)0x0000C000) /*!< ADCPRE[1:0] bits (ADC prescaler) */ +#define RCC_CFGR_ADCPRE_0 ((uint32_t)0x00004000) /*!< Bit 0 */ +#define RCC_CFGR_ADCPRE_1 ((uint32_t)0x00008000) /*!< Bit 1 */ + +#define RCC_CFGR_ADCPRE_DIV2 ((uint32_t)0x00000000) /*!< PCLK2 divided by 2 */ +#define RCC_CFGR_ADCPRE_DIV4 ((uint32_t)0x00004000) /*!< PCLK2 divided by 4 */ +#define RCC_CFGR_ADCPRE_DIV6 ((uint32_t)0x00008000) /*!< PCLK2 divided by 6 */ +#define RCC_CFGR_ADCPRE_DIV8 ((uint32_t)0x0000C000) /*!< PCLK2 divided by 8 */ + +#define RCC_CFGR_PLLSRC ((uint32_t)0x00010000) /*!< PLL entry clock source */ + +#define RCC_CFGR_PLLXTPRE ((uint32_t)0x00020000) /*!< HSE divider for PLL entry */ + +/*!< PLLMUL configuration */ +#define RCC_CFGR_PLLMULL ((uint32_t)0x003C0000) /*!< PLLMUL[3:0] bits (PLL multiplication factor) */ +#define RCC_CFGR_PLLMULL_0 ((uint32_t)0x00040000) /*!< Bit 0 */ +#define RCC_CFGR_PLLMULL_1 ((uint32_t)0x00080000) /*!< Bit 1 */ +#define RCC_CFGR_PLLMULL_2 ((uint32_t)0x00100000) /*!< Bit 2 */ +#define RCC_CFGR_PLLMULL_3 ((uint32_t)0x00200000) /*!< Bit 3 */ + +#ifdef STM32F10X_CL + #define RCC_CFGR_PLLSRC_HSI_Div2 ((uint32_t)0x00000000) /*!< HSI clock divided by 2 selected as PLL entry clock source */ + #define RCC_CFGR_PLLSRC_PREDIV1 ((uint32_t)0x00010000) /*!< PREDIV1 clock selected as PLL entry clock source */ + + #define RCC_CFGR_PLLXTPRE_PREDIV1 ((uint32_t)0x00000000) /*!< PREDIV1 clock not divided for PLL entry */ + #define RCC_CFGR_PLLXTPRE_PREDIV1_Div2 ((uint32_t)0x00020000) /*!< PREDIV1 clock divided by 2 for PLL entry */ + + #define RCC_CFGR_PLLMULL4 ((uint32_t)0x00080000) /*!< PLL input clock * 4 */ + #define RCC_CFGR_PLLMULL5 ((uint32_t)0x000C0000) /*!< PLL input clock * 5 */ + #define RCC_CFGR_PLLMULL6 ((uint32_t)0x00100000) /*!< PLL input clock * 6 */ + #define RCC_CFGR_PLLMULL7 ((uint32_t)0x00140000) /*!< PLL input clock * 7 */ + #define RCC_CFGR_PLLMULL8 ((uint32_t)0x00180000) /*!< PLL input clock * 8 */ + #define RCC_CFGR_PLLMULL9 ((uint32_t)0x001C0000) /*!< PLL input clock * 9 */ + #define RCC_CFGR_PLLMULL6_5 ((uint32_t)0x00340000) /*!< PLL input clock * 6.5 */ + + #define RCC_CFGR_OTGFSPRE ((uint32_t)0x00400000) /*!< USB OTG FS prescaler */ + +/*!< MCO configuration */ + #define RCC_CFGR_MCO ((uint32_t)0x0F000000) /*!< MCO[3:0] bits (Microcontroller Clock Output) */ + #define RCC_CFGR_MCO_0 ((uint32_t)0x01000000) /*!< Bit 0 */ + #define RCC_CFGR_MCO_1 ((uint32_t)0x02000000) /*!< Bit 1 */ + #define RCC_CFGR_MCO_2 ((uint32_t)0x04000000) /*!< Bit 2 */ + #define RCC_CFGR_MCO_3 ((uint32_t)0x08000000) /*!< Bit 3 */ + + #define RCC_CFGR_MCO_NOCLOCK ((uint32_t)0x00000000) /*!< No clock */ + #define RCC_CFGR_MCO_SYSCLK ((uint32_t)0x04000000) /*!< System clock selected as MCO source */ + #define RCC_CFGR_MCO_HSI ((uint32_t)0x05000000) /*!< HSI clock selected as MCO source */ + #define RCC_CFGR_MCO_HSE ((uint32_t)0x06000000) /*!< HSE clock selected as MCO source */ + #define RCC_CFGR_MCO_PLLCLK_Div2 ((uint32_t)0x07000000) /*!< PLL clock divided by 2 selected as MCO source */ + #define RCC_CFGR_MCO_PLL2CLK ((uint32_t)0x08000000) /*!< PLL2 clock selected as MCO source*/ + #define RCC_CFGR_MCO_PLL3CLK_Div2 ((uint32_t)0x09000000) /*!< PLL3 clock divided by 2 selected as MCO source*/ + #define RCC_CFGR_MCO_Ext_HSE ((uint32_t)0x0A000000) /*!< XT1 external 3-25 MHz oscillator clock selected as MCO source */ + #define RCC_CFGR_MCO_PLL3CLK ((uint32_t)0x0B000000) /*!< PLL3 clock selected as MCO source */ +#elif defined (STM32F10X_LD_VL) || defined (STM32F10X_MD_VL) || defined (STM32F10X_HD_VL) + #define RCC_CFGR_PLLSRC_HSI_Div2 ((uint32_t)0x00000000) /*!< HSI clock divided by 2 selected as PLL entry clock source */ + #define RCC_CFGR_PLLSRC_PREDIV1 ((uint32_t)0x00010000) /*!< PREDIV1 clock selected as PLL entry clock source */ + + #define RCC_CFGR_PLLXTPRE_PREDIV1 ((uint32_t)0x00000000) /*!< PREDIV1 clock not divided for PLL entry */ + #define RCC_CFGR_PLLXTPRE_PREDIV1_Div2 ((uint32_t)0x00020000) /*!< PREDIV1 clock divided by 2 for PLL entry */ + + #define RCC_CFGR_PLLMULL2 ((uint32_t)0x00000000) /*!< PLL input clock*2 */ + #define RCC_CFGR_PLLMULL3 ((uint32_t)0x00040000) /*!< PLL input clock*3 */ + #define RCC_CFGR_PLLMULL4 ((uint32_t)0x00080000) /*!< PLL input clock*4 */ + #define RCC_CFGR_PLLMULL5 ((uint32_t)0x000C0000) /*!< PLL input clock*5 */ + #define RCC_CFGR_PLLMULL6 ((uint32_t)0x00100000) /*!< PLL input clock*6 */ + #define RCC_CFGR_PLLMULL7 ((uint32_t)0x00140000) /*!< PLL input clock*7 */ + #define RCC_CFGR_PLLMULL8 ((uint32_t)0x00180000) /*!< PLL input clock*8 */ + #define RCC_CFGR_PLLMULL9 ((uint32_t)0x001C0000) /*!< PLL input clock*9 */ + #define RCC_CFGR_PLLMULL10 ((uint32_t)0x00200000) /*!< PLL input clock10 */ + #define RCC_CFGR_PLLMULL11 ((uint32_t)0x00240000) /*!< PLL input clock*11 */ + #define RCC_CFGR_PLLMULL12 ((uint32_t)0x00280000) /*!< PLL input clock*12 */ + #define RCC_CFGR_PLLMULL13 ((uint32_t)0x002C0000) /*!< PLL input clock*13 */ + #define RCC_CFGR_PLLMULL14 ((uint32_t)0x00300000) /*!< PLL input clock*14 */ + #define RCC_CFGR_PLLMULL15 ((uint32_t)0x00340000) /*!< PLL input clock*15 */ + #define RCC_CFGR_PLLMULL16 ((uint32_t)0x00380000) /*!< PLL input clock*16 */ + +/*!< MCO configuration */ + #define RCC_CFGR_MCO ((uint32_t)0x07000000) /*!< MCO[2:0] bits (Microcontroller Clock Output) */ + #define RCC_CFGR_MCO_0 ((uint32_t)0x01000000) /*!< Bit 0 */ + #define RCC_CFGR_MCO_1 ((uint32_t)0x02000000) /*!< Bit 1 */ + #define RCC_CFGR_MCO_2 ((uint32_t)0x04000000) /*!< Bit 2 */ + + #define RCC_CFGR_MCO_NOCLOCK ((uint32_t)0x00000000) /*!< No clock */ + #define RCC_CFGR_MCO_SYSCLK ((uint32_t)0x04000000) /*!< System clock selected as MCO source */ + #define RCC_CFGR_MCO_HSI ((uint32_t)0x05000000) /*!< HSI clock selected as MCO source */ + #define RCC_CFGR_MCO_HSE ((uint32_t)0x06000000) /*!< HSE clock selected as MCO source */ + #define RCC_CFGR_MCO_PLL ((uint32_t)0x07000000) /*!< PLL clock divided by 2 selected as MCO source */ +#else + #define RCC_CFGR_PLLSRC_HSI_Div2 ((uint32_t)0x00000000) /*!< HSI clock divided by 2 selected as PLL entry clock source */ + #define RCC_CFGR_PLLSRC_HSE ((uint32_t)0x00010000) /*!< HSE clock selected as PLL entry clock source */ + + #define RCC_CFGR_PLLXTPRE_HSE ((uint32_t)0x00000000) /*!< HSE clock not divided for PLL entry */ + #define RCC_CFGR_PLLXTPRE_HSE_Div2 ((uint32_t)0x00020000) /*!< HSE clock divided by 2 for PLL entry */ + + #define RCC_CFGR_PLLMULL2 ((uint32_t)0x00000000) /*!< PLL input clock*2 */ + #define RCC_CFGR_PLLMULL3 ((uint32_t)0x00040000) /*!< PLL input clock*3 */ + #define RCC_CFGR_PLLMULL4 ((uint32_t)0x00080000) /*!< PLL input clock*4 */ + #define RCC_CFGR_PLLMULL5 ((uint32_t)0x000C0000) /*!< PLL input clock*5 */ + #define RCC_CFGR_PLLMULL6 ((uint32_t)0x00100000) /*!< PLL input clock*6 */ + #define RCC_CFGR_PLLMULL7 ((uint32_t)0x00140000) /*!< PLL input clock*7 */ + #define RCC_CFGR_PLLMULL8 ((uint32_t)0x00180000) /*!< PLL input clock*8 */ + #define RCC_CFGR_PLLMULL9 ((uint32_t)0x001C0000) /*!< PLL input clock*9 */ + #define RCC_CFGR_PLLMULL10 ((uint32_t)0x00200000) /*!< PLL input clock10 */ + #define RCC_CFGR_PLLMULL11 ((uint32_t)0x00240000) /*!< PLL input clock*11 */ + #define RCC_CFGR_PLLMULL12 ((uint32_t)0x00280000) /*!< PLL input clock*12 */ + #define RCC_CFGR_PLLMULL13 ((uint32_t)0x002C0000) /*!< PLL input clock*13 */ + #define RCC_CFGR_PLLMULL14 ((uint32_t)0x00300000) /*!< PLL input clock*14 */ + #define RCC_CFGR_PLLMULL15 ((uint32_t)0x00340000) /*!< PLL input clock*15 */ + #define RCC_CFGR_PLLMULL16 ((uint32_t)0x00380000) /*!< PLL input clock*16 */ + #define RCC_CFGR_USBPRE ((uint32_t)0x00400000) /*!< USB Device prescaler */ + +/*!< MCO configuration */ + #define RCC_CFGR_MCO ((uint32_t)0x07000000) /*!< MCO[2:0] bits (Microcontroller Clock Output) */ + #define RCC_CFGR_MCO_0 ((uint32_t)0x01000000) /*!< Bit 0 */ + #define RCC_CFGR_MCO_1 ((uint32_t)0x02000000) /*!< Bit 1 */ + #define RCC_CFGR_MCO_2 ((uint32_t)0x04000000) /*!< Bit 2 */ + + #define RCC_CFGR_MCO_NOCLOCK ((uint32_t)0x00000000) /*!< No clock */ + #define RCC_CFGR_MCO_SYSCLK ((uint32_t)0x04000000) /*!< System clock selected as MCO source */ + #define RCC_CFGR_MCO_HSI ((uint32_t)0x05000000) /*!< HSI clock selected as MCO source */ + #define RCC_CFGR_MCO_HSE ((uint32_t)0x06000000) /*!< HSE clock selected as MCO source */ + #define RCC_CFGR_MCO_PLL ((uint32_t)0x07000000) /*!< PLL clock divided by 2 selected as MCO source */ +#endif /* STM32F10X_CL */ + +/*!<****************** Bit definition for RCC_CIR register ********************/ +#define RCC_CIR_LSIRDYF ((uint32_t)0x00000001) /*!< LSI Ready Interrupt flag */ +#define RCC_CIR_LSERDYF ((uint32_t)0x00000002) /*!< LSE Ready Interrupt flag */ +#define RCC_CIR_HSIRDYF ((uint32_t)0x00000004) /*!< HSI Ready Interrupt flag */ +#define RCC_CIR_HSERDYF ((uint32_t)0x00000008) /*!< HSE Ready Interrupt flag */ +#define RCC_CIR_PLLRDYF ((uint32_t)0x00000010) /*!< PLL Ready Interrupt flag */ +#define RCC_CIR_CSSF ((uint32_t)0x00000080) /*!< Clock Security System Interrupt flag */ +#define RCC_CIR_LSIRDYIE ((uint32_t)0x00000100) /*!< LSI Ready Interrupt Enable */ +#define RCC_CIR_LSERDYIE ((uint32_t)0x00000200) /*!< LSE Ready Interrupt Enable */ +#define RCC_CIR_HSIRDYIE ((uint32_t)0x00000400) /*!< HSI Ready Interrupt Enable */ +#define RCC_CIR_HSERDYIE ((uint32_t)0x00000800) /*!< HSE Ready Interrupt Enable */ +#define RCC_CIR_PLLRDYIE ((uint32_t)0x00001000) /*!< PLL Ready Interrupt Enable */ +#define RCC_CIR_LSIRDYC ((uint32_t)0x00010000) /*!< LSI Ready Interrupt Clear */ +#define RCC_CIR_LSERDYC ((uint32_t)0x00020000) /*!< LSE Ready Interrupt Clear */ +#define RCC_CIR_HSIRDYC ((uint32_t)0x00040000) /*!< HSI Ready Interrupt Clear */ +#define RCC_CIR_HSERDYC ((uint32_t)0x00080000) /*!< HSE Ready Interrupt Clear */ +#define RCC_CIR_PLLRDYC ((uint32_t)0x00100000) /*!< PLL Ready Interrupt Clear */ +#define RCC_CIR_CSSC ((uint32_t)0x00800000) /*!< Clock Security System Interrupt Clear */ + +#ifdef STM32F10X_CL + #define RCC_CIR_PLL2RDYF ((uint32_t)0x00000020) /*!< PLL2 Ready Interrupt flag */ + #define RCC_CIR_PLL3RDYF ((uint32_t)0x00000040) /*!< PLL3 Ready Interrupt flag */ + #define RCC_CIR_PLL2RDYIE ((uint32_t)0x00002000) /*!< PLL2 Ready Interrupt Enable */ + #define RCC_CIR_PLL3RDYIE ((uint32_t)0x00004000) /*!< PLL3 Ready Interrupt Enable */ + #define RCC_CIR_PLL2RDYC ((uint32_t)0x00200000) /*!< PLL2 Ready Interrupt Clear */ + #define RCC_CIR_PLL3RDYC ((uint32_t)0x00400000) /*!< PLL3 Ready Interrupt Clear */ +#endif /* STM32F10X_CL */ + +/***************** Bit definition for RCC_APB2RSTR register *****************/ +#define RCC_APB2RSTR_AFIORST ((uint32_t)0x00000001) /*!< Alternate Function I/O reset */ +#define RCC_APB2RSTR_IOPARST ((uint32_t)0x00000004) /*!< I/O port A reset */ +#define RCC_APB2RSTR_IOPBRST ((uint32_t)0x00000008) /*!< I/O port B reset */ +#define RCC_APB2RSTR_IOPCRST ((uint32_t)0x00000010) /*!< I/O port C reset */ +#define RCC_APB2RSTR_IOPDRST ((uint32_t)0x00000020) /*!< I/O port D reset */ +#define RCC_APB2RSTR_ADC1RST ((uint32_t)0x00000200) /*!< ADC 1 interface reset */ + +#if !defined (STM32F10X_LD_VL) && !defined (STM32F10X_MD_VL) && !defined (STM32F10X_HD_VL) +#define RCC_APB2RSTR_ADC2RST ((uint32_t)0x00000400) /*!< ADC 2 interface reset */ +#endif + +#define RCC_APB2RSTR_TIM1RST ((uint32_t)0x00000800) /*!< TIM1 Timer reset */ +#define RCC_APB2RSTR_SPI1RST ((uint32_t)0x00001000) /*!< SPI 1 reset */ +#define RCC_APB2RSTR_USART1RST ((uint32_t)0x00004000) /*!< USART1 reset */ + +#if defined (STM32F10X_LD_VL) || defined (STM32F10X_MD_VL) || defined (STM32F10X_HD_VL) +#define RCC_APB2RSTR_TIM15RST ((uint32_t)0x00010000) /*!< TIM15 Timer reset */ +#define RCC_APB2RSTR_TIM16RST ((uint32_t)0x00020000) /*!< TIM16 Timer reset */ +#define RCC_APB2RSTR_TIM17RST ((uint32_t)0x00040000) /*!< TIM17 Timer reset */ +#endif + +#if !defined (STM32F10X_LD) && !defined (STM32F10X_LD_VL) + #define RCC_APB2RSTR_IOPERST ((uint32_t)0x00000040) /*!< I/O port E reset */ +#endif /* STM32F10X_LD && STM32F10X_LD_VL */ + +#if defined (STM32F10X_HD) || defined (STM32F10X_XL) + #define RCC_APB2RSTR_IOPFRST ((uint32_t)0x00000080) /*!< I/O port F reset */ + #define RCC_APB2RSTR_IOPGRST ((uint32_t)0x00000100) /*!< I/O port G reset */ + #define RCC_APB2RSTR_TIM8RST ((uint32_t)0x00002000) /*!< TIM8 Timer reset */ + #define RCC_APB2RSTR_ADC3RST ((uint32_t)0x00008000) /*!< ADC3 interface reset */ +#endif + +#if defined (STM32F10X_HD_VL) + #define RCC_APB2RSTR_IOPFRST ((uint32_t)0x00000080) /*!< I/O port F reset */ + #define RCC_APB2RSTR_IOPGRST ((uint32_t)0x00000100) /*!< I/O port G reset */ +#endif + +#ifdef STM32F10X_XL + #define RCC_APB2RSTR_TIM9RST ((uint32_t)0x00080000) /*!< TIM9 Timer reset */ + #define RCC_APB2RSTR_TIM10RST ((uint32_t)0x00100000) /*!< TIM10 Timer reset */ + #define RCC_APB2RSTR_TIM11RST ((uint32_t)0x00200000) /*!< TIM11 Timer reset */ +#endif /* STM32F10X_XL */ + +/***************** Bit definition for RCC_APB1RSTR register *****************/ +#define RCC_APB1RSTR_TIM2RST ((uint32_t)0x00000001) /*!< Timer 2 reset */ +#define RCC_APB1RSTR_TIM3RST ((uint32_t)0x00000002) /*!< Timer 3 reset */ +#define RCC_APB1RSTR_WWDGRST ((uint32_t)0x00000800) /*!< Window Watchdog reset */ +#define RCC_APB1RSTR_USART2RST ((uint32_t)0x00020000) /*!< USART 2 reset */ +#define RCC_APB1RSTR_I2C1RST ((uint32_t)0x00200000) /*!< I2C 1 reset */ + +#if !defined (STM32F10X_LD_VL) && !defined (STM32F10X_MD_VL) && !defined (STM32F10X_HD_VL) +#define RCC_APB1RSTR_CAN1RST ((uint32_t)0x02000000) /*!< CAN1 reset */ +#endif + +#define RCC_APB1RSTR_BKPRST ((uint32_t)0x08000000) /*!< Backup interface reset */ +#define RCC_APB1RSTR_PWRRST ((uint32_t)0x10000000) /*!< Power interface reset */ + +#if !defined (STM32F10X_LD) && !defined (STM32F10X_LD_VL) + #define RCC_APB1RSTR_TIM4RST ((uint32_t)0x00000004) /*!< Timer 4 reset */ + #define RCC_APB1RSTR_SPI2RST ((uint32_t)0x00004000) /*!< SPI 2 reset */ + #define RCC_APB1RSTR_USART3RST ((uint32_t)0x00040000) /*!< USART 3 reset */ + #define RCC_APB1RSTR_I2C2RST ((uint32_t)0x00400000) /*!< I2C 2 reset */ +#endif /* STM32F10X_LD && STM32F10X_LD_VL */ + +#if defined (STM32F10X_HD) || defined (STM32F10X_MD) || defined (STM32F10X_LD) || defined (STM32F10X_XL) + #define RCC_APB1RSTR_USBRST ((uint32_t)0x00800000) /*!< USB Device reset */ +#endif + +#if defined (STM32F10X_HD) || defined (STM32F10X_CL) || defined (STM32F10X_XL) + #define RCC_APB1RSTR_TIM5RST ((uint32_t)0x00000008) /*!< Timer 5 reset */ + #define RCC_APB1RSTR_TIM6RST ((uint32_t)0x00000010) /*!< Timer 6 reset */ + #define RCC_APB1RSTR_TIM7RST ((uint32_t)0x00000020) /*!< Timer 7 reset */ + #define RCC_APB1RSTR_SPI3RST ((uint32_t)0x00008000) /*!< SPI 3 reset */ + #define RCC_APB1RSTR_UART4RST ((uint32_t)0x00080000) /*!< UART 4 reset */ + #define RCC_APB1RSTR_UART5RST ((uint32_t)0x00100000) /*!< UART 5 reset */ + #define RCC_APB1RSTR_DACRST ((uint32_t)0x20000000) /*!< DAC interface reset */ +#endif + +#if defined (STM32F10X_LD_VL) || defined (STM32F10X_MD_VL) || defined (STM32F10X_HD_VL) + #define RCC_APB1RSTR_TIM6RST ((uint32_t)0x00000010) /*!< Timer 6 reset */ + #define RCC_APB1RSTR_TIM7RST ((uint32_t)0x00000020) /*!< Timer 7 reset */ + #define RCC_APB1RSTR_DACRST ((uint32_t)0x20000000) /*!< DAC interface reset */ + #define RCC_APB1RSTR_CECRST ((uint32_t)0x40000000) /*!< CEC interface reset */ +#endif + +#if defined (STM32F10X_HD_VL) + #define RCC_APB1RSTR_TIM5RST ((uint32_t)0x00000008) /*!< Timer 5 reset */ + #define RCC_APB1RSTR_TIM12RST ((uint32_t)0x00000040) /*!< TIM12 Timer reset */ + #define RCC_APB1RSTR_TIM13RST ((uint32_t)0x00000080) /*!< TIM13 Timer reset */ + #define RCC_APB1RSTR_TIM14RST ((uint32_t)0x00000100) /*!< TIM14 Timer reset */ + #define RCC_APB1RSTR_SPI3RST ((uint32_t)0x00008000) /*!< SPI 3 reset */ + #define RCC_APB1RSTR_UART4RST ((uint32_t)0x00080000) /*!< UART 4 reset */ + #define RCC_APB1RSTR_UART5RST ((uint32_t)0x00100000) /*!< UART 5 reset */ +#endif + +#ifdef STM32F10X_CL + #define RCC_APB1RSTR_CAN2RST ((uint32_t)0x04000000) /*!< CAN2 reset */ +#endif /* STM32F10X_CL */ + +#ifdef STM32F10X_XL + #define RCC_APB1RSTR_TIM12RST ((uint32_t)0x00000040) /*!< TIM12 Timer reset */ + #define RCC_APB1RSTR_TIM13RST ((uint32_t)0x00000080) /*!< TIM13 Timer reset */ + #define RCC_APB1RSTR_TIM14RST ((uint32_t)0x00000100) /*!< TIM14 Timer reset */ +#endif /* STM32F10X_XL */ + +/****************** Bit definition for RCC_AHBENR register ******************/ +#define RCC_AHBENR_DMA1EN ((uint16_t)0x0001) /*!< DMA1 clock enable */ +#define RCC_AHBENR_SRAMEN ((uint16_t)0x0004) /*!< SRAM interface clock enable */ +#define RCC_AHBENR_FLITFEN ((uint16_t)0x0010) /*!< FLITF clock enable */ +#define RCC_AHBENR_CRCEN ((uint16_t)0x0040) /*!< CRC clock enable */ + +#if defined (STM32F10X_HD) || defined (STM32F10X_XL) || defined (STM32F10X_CL) || defined (STM32F10X_HD_VL) + #define RCC_AHBENR_DMA2EN ((uint16_t)0x0002) /*!< DMA2 clock enable */ +#endif + +#if defined (STM32F10X_HD) || defined (STM32F10X_XL) + #define RCC_AHBENR_FSMCEN ((uint16_t)0x0100) /*!< FSMC clock enable */ + #define RCC_AHBENR_SDIOEN ((uint16_t)0x0400) /*!< SDIO clock enable */ +#endif + +#if defined (STM32F10X_HD_VL) + #define RCC_AHBENR_FSMCEN ((uint16_t)0x0100) /*!< FSMC clock enable */ +#endif + +#ifdef STM32F10X_CL + #define RCC_AHBENR_OTGFSEN ((uint32_t)0x00001000) /*!< USB OTG FS clock enable */ + #define RCC_AHBENR_ETHMACEN ((uint32_t)0x00004000) /*!< ETHERNET MAC clock enable */ + #define RCC_AHBENR_ETHMACTXEN ((uint32_t)0x00008000) /*!< ETHERNET MAC Tx clock enable */ + #define RCC_AHBENR_ETHMACRXEN ((uint32_t)0x00010000) /*!< ETHERNET MAC Rx clock enable */ +#endif /* STM32F10X_CL */ + +/****************** Bit definition for RCC_APB2ENR register *****************/ +#define RCC_APB2ENR_AFIOEN ((uint32_t)0x00000001) /*!< Alternate Function I/O clock enable */ +#define RCC_APB2ENR_IOPAEN ((uint32_t)0x00000004) /*!< I/O port A clock enable */ +#define RCC_APB2ENR_IOPBEN ((uint32_t)0x00000008) /*!< I/O port B clock enable */ +#define RCC_APB2ENR_IOPCEN ((uint32_t)0x00000010) /*!< I/O port C clock enable */ +#define RCC_APB2ENR_IOPDEN ((uint32_t)0x00000020) /*!< I/O port D clock enable */ +#define RCC_APB2ENR_ADC1EN ((uint32_t)0x00000200) /*!< ADC 1 interface clock enable */ + +#if !defined (STM32F10X_LD_VL) && !defined (STM32F10X_MD_VL) && !defined (STM32F10X_HD_VL) +#define RCC_APB2ENR_ADC2EN ((uint32_t)0x00000400) /*!< ADC 2 interface clock enable */ +#endif + +#define RCC_APB2ENR_TIM1EN ((uint32_t)0x00000800) /*!< TIM1 Timer clock enable */ +#define RCC_APB2ENR_SPI1EN ((uint32_t)0x00001000) /*!< SPI 1 clock enable */ +#define RCC_APB2ENR_USART1EN ((uint32_t)0x00004000) /*!< USART1 clock enable */ + +#if defined (STM32F10X_LD_VL) || defined (STM32F10X_MD_VL) || defined (STM32F10X_HD_VL) +#define RCC_APB2ENR_TIM15EN ((uint32_t)0x00010000) /*!< TIM15 Timer clock enable */ +#define RCC_APB2ENR_TIM16EN ((uint32_t)0x00020000) /*!< TIM16 Timer clock enable */ +#define RCC_APB2ENR_TIM17EN ((uint32_t)0x00040000) /*!< TIM17 Timer clock enable */ +#endif + +#if !defined (STM32F10X_LD) && !defined (STM32F10X_LD_VL) + #define RCC_APB2ENR_IOPEEN ((uint32_t)0x00000040) /*!< I/O port E clock enable */ +#endif /* STM32F10X_LD && STM32F10X_LD_VL */ + +#if defined (STM32F10X_HD) || defined (STM32F10X_XL) + #define RCC_APB2ENR_IOPFEN ((uint32_t)0x00000080) /*!< I/O port F clock enable */ + #define RCC_APB2ENR_IOPGEN ((uint32_t)0x00000100) /*!< I/O port G clock enable */ + #define RCC_APB2ENR_TIM8EN ((uint32_t)0x00002000) /*!< TIM8 Timer clock enable */ + #define RCC_APB2ENR_ADC3EN ((uint32_t)0x00008000) /*!< DMA1 clock enable */ +#endif + +#if defined (STM32F10X_HD_VL) + #define RCC_APB2ENR_IOPFEN ((uint32_t)0x00000080) /*!< I/O port F clock enable */ + #define RCC_APB2ENR_IOPGEN ((uint32_t)0x00000100) /*!< I/O port G clock enable */ +#endif + +#ifdef STM32F10X_XL + #define RCC_APB2ENR_TIM9EN ((uint32_t)0x00080000) /*!< TIM9 Timer clock enable */ + #define RCC_APB2ENR_TIM10EN ((uint32_t)0x00100000) /*!< TIM10 Timer clock enable */ + #define RCC_APB2ENR_TIM11EN ((uint32_t)0x00200000) /*!< TIM11 Timer clock enable */ +#endif + +/***************** Bit definition for RCC_APB1ENR register ******************/ +#define RCC_APB1ENR_TIM2EN ((uint32_t)0x00000001) /*!< Timer 2 clock enabled*/ +#define RCC_APB1ENR_TIM3EN ((uint32_t)0x00000002) /*!< Timer 3 clock enable */ +#define RCC_APB1ENR_WWDGEN ((uint32_t)0x00000800) /*!< Window Watchdog clock enable */ +#define RCC_APB1ENR_USART2EN ((uint32_t)0x00020000) /*!< USART 2 clock enable */ +#define RCC_APB1ENR_I2C1EN ((uint32_t)0x00200000) /*!< I2C 1 clock enable */ + +#if !defined (STM32F10X_LD_VL) && !defined (STM32F10X_MD_VL) && !defined (STM32F10X_HD_VL) +#define RCC_APB1ENR_CAN1EN ((uint32_t)0x02000000) /*!< CAN1 clock enable */ +#endif + +#define RCC_APB1ENR_BKPEN ((uint32_t)0x08000000) /*!< Backup interface clock enable */ +#define RCC_APB1ENR_PWREN ((uint32_t)0x10000000) /*!< Power interface clock enable */ + +#if !defined (STM32F10X_LD) && !defined (STM32F10X_LD_VL) + #define RCC_APB1ENR_TIM4EN ((uint32_t)0x00000004) /*!< Timer 4 clock enable */ + #define RCC_APB1ENR_SPI2EN ((uint32_t)0x00004000) /*!< SPI 2 clock enable */ + #define RCC_APB1ENR_USART3EN ((uint32_t)0x00040000) /*!< USART 3 clock enable */ + #define RCC_APB1ENR_I2C2EN ((uint32_t)0x00400000) /*!< I2C 2 clock enable */ +#endif /* STM32F10X_LD && STM32F10X_LD_VL */ + +#if defined (STM32F10X_HD) || defined (STM32F10X_MD) || defined (STM32F10X_LD) + #define RCC_APB1ENR_USBEN ((uint32_t)0x00800000) /*!< USB Device clock enable */ +#endif + +#if defined (STM32F10X_HD) || defined (STM32F10X_CL) + #define RCC_APB1ENR_TIM5EN ((uint32_t)0x00000008) /*!< Timer 5 clock enable */ + #define RCC_APB1ENR_TIM6EN ((uint32_t)0x00000010) /*!< Timer 6 clock enable */ + #define RCC_APB1ENR_TIM7EN ((uint32_t)0x00000020) /*!< Timer 7 clock enable */ + #define RCC_APB1ENR_SPI3EN ((uint32_t)0x00008000) /*!< SPI 3 clock enable */ + #define RCC_APB1ENR_UART4EN ((uint32_t)0x00080000) /*!< UART 4 clock enable */ + #define RCC_APB1ENR_UART5EN ((uint32_t)0x00100000) /*!< UART 5 clock enable */ + #define RCC_APB1ENR_DACEN ((uint32_t)0x20000000) /*!< DAC interface clock enable */ +#endif + +#if defined (STM32F10X_LD_VL) || defined (STM32F10X_MD_VL) || defined (STM32F10X_HD_VL) + #define RCC_APB1ENR_TIM6EN ((uint32_t)0x00000010) /*!< Timer 6 clock enable */ + #define RCC_APB1ENR_TIM7EN ((uint32_t)0x00000020) /*!< Timer 7 clock enable */ + #define RCC_APB1ENR_DACEN ((uint32_t)0x20000000) /*!< DAC interface clock enable */ + #define RCC_APB1ENR_CECEN ((uint32_t)0x40000000) /*!< CEC interface clock enable */ +#endif + +#ifdef STM32F10X_HD_VL + #define RCC_APB1ENR_TIM5EN ((uint32_t)0x00000008) /*!< Timer 5 clock enable */ + #define RCC_APB1ENR_TIM12EN ((uint32_t)0x00000040) /*!< TIM12 Timer clock enable */ + #define RCC_APB1ENR_TIM13EN ((uint32_t)0x00000080) /*!< TIM13 Timer clock enable */ + #define RCC_APB1ENR_TIM14EN ((uint32_t)0x00000100) /*!< TIM14 Timer clock enable */ + #define RCC_APB1ENR_SPI3EN ((uint32_t)0x00008000) /*!< SPI 3 clock enable */ + #define RCC_APB1ENR_UART4EN ((uint32_t)0x00080000) /*!< UART 4 clock enable */ + #define RCC_APB1ENR_UART5EN ((uint32_t)0x00100000) /*!< UART 5 clock enable */ +#endif /* STM32F10X_HD_VL */ + +#ifdef STM32F10X_CL + #define RCC_APB1ENR_CAN2EN ((uint32_t)0x04000000) /*!< CAN2 clock enable */ +#endif /* STM32F10X_CL */ + +#ifdef STM32F10X_XL + #define RCC_APB1ENR_TIM12EN ((uint32_t)0x00000040) /*!< TIM12 Timer clock enable */ + #define RCC_APB1ENR_TIM13EN ((uint32_t)0x00000080) /*!< TIM13 Timer clock enable */ + #define RCC_APB1ENR_TIM14EN ((uint32_t)0x00000100) /*!< TIM14 Timer clock enable */ +#endif /* STM32F10X_XL */ + +/******************* Bit definition for RCC_BDCR register *******************/ +#define RCC_BDCR_LSEON ((uint32_t)0x00000001) /*!< External Low Speed oscillator enable */ +#define RCC_BDCR_LSERDY ((uint32_t)0x00000002) /*!< External Low Speed oscillator Ready */ +#define RCC_BDCR_LSEBYP ((uint32_t)0x00000004) /*!< External Low Speed oscillator Bypass */ + +#define RCC_BDCR_RTCSEL ((uint32_t)0x00000300) /*!< RTCSEL[1:0] bits (RTC clock source selection) */ +#define RCC_BDCR_RTCSEL_0 ((uint32_t)0x00000100) /*!< Bit 0 */ +#define RCC_BDCR_RTCSEL_1 ((uint32_t)0x00000200) /*!< Bit 1 */ + +/*!< RTC congiguration */ +#define RCC_BDCR_RTCSEL_NOCLOCK ((uint32_t)0x00000000) /*!< No clock */ +#define RCC_BDCR_RTCSEL_LSE ((uint32_t)0x00000100) /*!< LSE oscillator clock used as RTC clock */ +#define RCC_BDCR_RTCSEL_LSI ((uint32_t)0x00000200) /*!< LSI oscillator clock used as RTC clock */ +#define RCC_BDCR_RTCSEL_HSE ((uint32_t)0x00000300) /*!< HSE oscillator clock divided by 128 used as RTC clock */ + +#define RCC_BDCR_RTCEN ((uint32_t)0x00008000) /*!< RTC clock enable */ +#define RCC_BDCR_BDRST ((uint32_t)0x00010000) /*!< Backup domain software reset */ + +/******************* Bit definition for RCC_CSR register ********************/ +#define RCC_CSR_LSION ((uint32_t)0x00000001) /*!< Internal Low Speed oscillator enable */ +#define RCC_CSR_LSIRDY ((uint32_t)0x00000002) /*!< Internal Low Speed oscillator Ready */ +#define RCC_CSR_RMVF ((uint32_t)0x01000000) /*!< Remove reset flag */ +#define RCC_CSR_PINRSTF ((uint32_t)0x04000000) /*!< PIN reset flag */ +#define RCC_CSR_PORRSTF ((uint32_t)0x08000000) /*!< POR/PDR reset flag */ +#define RCC_CSR_SFTRSTF ((uint32_t)0x10000000) /*!< Software Reset flag */ +#define RCC_CSR_IWDGRSTF ((uint32_t)0x20000000) /*!< Independent Watchdog reset flag */ +#define RCC_CSR_WWDGRSTF ((uint32_t)0x40000000) /*!< Window watchdog reset flag */ +#define RCC_CSR_LPWRRSTF ((uint32_t)0x80000000) /*!< Low-Power reset flag */ + +#ifdef STM32F10X_CL +/******************* Bit definition for RCC_AHBRSTR register ****************/ + #define RCC_AHBRSTR_OTGFSRST ((uint32_t)0x00001000) /*!< USB OTG FS reset */ + #define RCC_AHBRSTR_ETHMACRST ((uint32_t)0x00004000) /*!< ETHERNET MAC reset */ + +/******************* Bit definition for RCC_CFGR2 register ******************/ +/*!< PREDIV1 configuration */ + #define RCC_CFGR2_PREDIV1 ((uint32_t)0x0000000F) /*!< PREDIV1[3:0] bits */ + #define RCC_CFGR2_PREDIV1_0 ((uint32_t)0x00000001) /*!< Bit 0 */ + #define RCC_CFGR2_PREDIV1_1 ((uint32_t)0x00000002) /*!< Bit 1 */ + #define RCC_CFGR2_PREDIV1_2 ((uint32_t)0x00000004) /*!< Bit 2 */ + #define RCC_CFGR2_PREDIV1_3 ((uint32_t)0x00000008) /*!< Bit 3 */ + + #define RCC_CFGR2_PREDIV1_DIV1 ((uint32_t)0x00000000) /*!< PREDIV1 input clock not divided */ + #define RCC_CFGR2_PREDIV1_DIV2 ((uint32_t)0x00000001) /*!< PREDIV1 input clock divided by 2 */ + #define RCC_CFGR2_PREDIV1_DIV3 ((uint32_t)0x00000002) /*!< PREDIV1 input clock divided by 3 */ + #define RCC_CFGR2_PREDIV1_DIV4 ((uint32_t)0x00000003) /*!< PREDIV1 input clock divided by 4 */ + #define RCC_CFGR2_PREDIV1_DIV5 ((uint32_t)0x00000004) /*!< PREDIV1 input clock divided by 5 */ + #define RCC_CFGR2_PREDIV1_DIV6 ((uint32_t)0x00000005) /*!< PREDIV1 input clock divided by 6 */ + #define RCC_CFGR2_PREDIV1_DIV7 ((uint32_t)0x00000006) /*!< PREDIV1 input clock divided by 7 */ + #define RCC_CFGR2_PREDIV1_DIV8 ((uint32_t)0x00000007) /*!< PREDIV1 input clock divided by 8 */ + #define RCC_CFGR2_PREDIV1_DIV9 ((uint32_t)0x00000008) /*!< PREDIV1 input clock divided by 9 */ + #define RCC_CFGR2_PREDIV1_DIV10 ((uint32_t)0x00000009) /*!< PREDIV1 input clock divided by 10 */ + #define RCC_CFGR2_PREDIV1_DIV11 ((uint32_t)0x0000000A) /*!< PREDIV1 input clock divided by 11 */ + #define RCC_CFGR2_PREDIV1_DIV12 ((uint32_t)0x0000000B) /*!< PREDIV1 input clock divided by 12 */ + #define RCC_CFGR2_PREDIV1_DIV13 ((uint32_t)0x0000000C) /*!< PREDIV1 input clock divided by 13 */ + #define RCC_CFGR2_PREDIV1_DIV14 ((uint32_t)0x0000000D) /*!< PREDIV1 input clock divided by 14 */ + #define RCC_CFGR2_PREDIV1_DIV15 ((uint32_t)0x0000000E) /*!< PREDIV1 input clock divided by 15 */ + #define RCC_CFGR2_PREDIV1_DIV16 ((uint32_t)0x0000000F) /*!< PREDIV1 input clock divided by 16 */ + +/*!< PREDIV2 configuration */ + #define RCC_CFGR2_PREDIV2 ((uint32_t)0x000000F0) /*!< PREDIV2[3:0] bits */ + #define RCC_CFGR2_PREDIV2_0 ((uint32_t)0x00000010) /*!< Bit 0 */ + #define RCC_CFGR2_PREDIV2_1 ((uint32_t)0x00000020) /*!< Bit 1 */ + #define RCC_CFGR2_PREDIV2_2 ((uint32_t)0x00000040) /*!< Bit 2 */ + #define RCC_CFGR2_PREDIV2_3 ((uint32_t)0x00000080) /*!< Bit 3 */ + + #define RCC_CFGR2_PREDIV2_DIV1 ((uint32_t)0x00000000) /*!< PREDIV2 input clock not divided */ + #define RCC_CFGR2_PREDIV2_DIV2 ((uint32_t)0x00000010) /*!< PREDIV2 input clock divided by 2 */ + #define RCC_CFGR2_PREDIV2_DIV3 ((uint32_t)0x00000020) /*!< PREDIV2 input clock divided by 3 */ + #define RCC_CFGR2_PREDIV2_DIV4 ((uint32_t)0x00000030) /*!< PREDIV2 input clock divided by 4 */ + #define RCC_CFGR2_PREDIV2_DIV5 ((uint32_t)0x00000040) /*!< PREDIV2 input clock divided by 5 */ + #define RCC_CFGR2_PREDIV2_DIV6 ((uint32_t)0x00000050) /*!< PREDIV2 input clock divided by 6 */ + #define RCC_CFGR2_PREDIV2_DIV7 ((uint32_t)0x00000060) /*!< PREDIV2 input clock divided by 7 */ + #define RCC_CFGR2_PREDIV2_DIV8 ((uint32_t)0x00000070) /*!< PREDIV2 input clock divided by 8 */ + #define RCC_CFGR2_PREDIV2_DIV9 ((uint32_t)0x00000080) /*!< PREDIV2 input clock divided by 9 */ + #define RCC_CFGR2_PREDIV2_DIV10 ((uint32_t)0x00000090) /*!< PREDIV2 input clock divided by 10 */ + #define RCC_CFGR2_PREDIV2_DIV11 ((uint32_t)0x000000A0) /*!< PREDIV2 input clock divided by 11 */ + #define RCC_CFGR2_PREDIV2_DIV12 ((uint32_t)0x000000B0) /*!< PREDIV2 input clock divided by 12 */ + #define RCC_CFGR2_PREDIV2_DIV13 ((uint32_t)0x000000C0) /*!< PREDIV2 input clock divided by 13 */ + #define RCC_CFGR2_PREDIV2_DIV14 ((uint32_t)0x000000D0) /*!< PREDIV2 input clock divided by 14 */ + #define RCC_CFGR2_PREDIV2_DIV15 ((uint32_t)0x000000E0) /*!< PREDIV2 input clock divided by 15 */ + #define RCC_CFGR2_PREDIV2_DIV16 ((uint32_t)0x000000F0) /*!< PREDIV2 input clock divided by 16 */ + +/*!< PLL2MUL configuration */ + #define RCC_CFGR2_PLL2MUL ((uint32_t)0x00000F00) /*!< PLL2MUL[3:0] bits */ + #define RCC_CFGR2_PLL2MUL_0 ((uint32_t)0x00000100) /*!< Bit 0 */ + #define RCC_CFGR2_PLL2MUL_1 ((uint32_t)0x00000200) /*!< Bit 1 */ + #define RCC_CFGR2_PLL2MUL_2 ((uint32_t)0x00000400) /*!< Bit 2 */ + #define RCC_CFGR2_PLL2MUL_3 ((uint32_t)0x00000800) /*!< Bit 3 */ + + #define RCC_CFGR2_PLL2MUL8 ((uint32_t)0x00000600) /*!< PLL2 input clock * 8 */ + #define RCC_CFGR2_PLL2MUL9 ((uint32_t)0x00000700) /*!< PLL2 input clock * 9 */ + #define RCC_CFGR2_PLL2MUL10 ((uint32_t)0x00000800) /*!< PLL2 input clock * 10 */ + #define RCC_CFGR2_PLL2MUL11 ((uint32_t)0x00000900) /*!< PLL2 input clock * 11 */ + #define RCC_CFGR2_PLL2MUL12 ((uint32_t)0x00000A00) /*!< PLL2 input clock * 12 */ + #define RCC_CFGR2_PLL2MUL13 ((uint32_t)0x00000B00) /*!< PLL2 input clock * 13 */ + #define RCC_CFGR2_PLL2MUL14 ((uint32_t)0x00000C00) /*!< PLL2 input clock * 14 */ + #define RCC_CFGR2_PLL2MUL16 ((uint32_t)0x00000E00) /*!< PLL2 input clock * 16 */ + #define RCC_CFGR2_PLL2MUL20 ((uint32_t)0x00000F00) /*!< PLL2 input clock * 20 */ + +/*!< PLL3MUL configuration */ + #define RCC_CFGR2_PLL3MUL ((uint32_t)0x0000F000) /*!< PLL3MUL[3:0] bits */ + #define RCC_CFGR2_PLL3MUL_0 ((uint32_t)0x00001000) /*!< Bit 0 */ + #define RCC_CFGR2_PLL3MUL_1 ((uint32_t)0x00002000) /*!< Bit 1 */ + #define RCC_CFGR2_PLL3MUL_2 ((uint32_t)0x00004000) /*!< Bit 2 */ + #define RCC_CFGR2_PLL3MUL_3 ((uint32_t)0x00008000) /*!< Bit 3 */ + + #define RCC_CFGR2_PLL3MUL8 ((uint32_t)0x00006000) /*!< PLL3 input clock * 8 */ + #define RCC_CFGR2_PLL3MUL9 ((uint32_t)0x00007000) /*!< PLL3 input clock * 9 */ + #define RCC_CFGR2_PLL3MUL10 ((uint32_t)0x00008000) /*!< PLL3 input clock * 10 */ + #define RCC_CFGR2_PLL3MUL11 ((uint32_t)0x00009000) /*!< PLL3 input clock * 11 */ + #define RCC_CFGR2_PLL3MUL12 ((uint32_t)0x0000A000) /*!< PLL3 input clock * 12 */ + #define RCC_CFGR2_PLL3MUL13 ((uint32_t)0x0000B000) /*!< PLL3 input clock * 13 */ + #define RCC_CFGR2_PLL3MUL14 ((uint32_t)0x0000C000) /*!< PLL3 input clock * 14 */ + #define RCC_CFGR2_PLL3MUL16 ((uint32_t)0x0000E000) /*!< PLL3 input clock * 16 */ + #define RCC_CFGR2_PLL3MUL20 ((uint32_t)0x0000F000) /*!< PLL3 input clock * 20 */ + + #define RCC_CFGR2_PREDIV1SRC ((uint32_t)0x00010000) /*!< PREDIV1 entry clock source */ + #define RCC_CFGR2_PREDIV1SRC_PLL2 ((uint32_t)0x00010000) /*!< PLL2 selected as PREDIV1 entry clock source */ + #define RCC_CFGR2_PREDIV1SRC_HSE ((uint32_t)0x00000000) /*!< HSE selected as PREDIV1 entry clock source */ + #define RCC_CFGR2_I2S2SRC ((uint32_t)0x00020000) /*!< I2S2 entry clock source */ + #define RCC_CFGR2_I2S3SRC ((uint32_t)0x00040000) /*!< I2S3 clock source */ +#endif /* STM32F10X_CL */ + +#if defined (STM32F10X_LD_VL) || defined (STM32F10X_MD_VL) || defined (STM32F10X_HD_VL) +/******************* Bit definition for RCC_CFGR2 register ******************/ +/*!< PREDIV1 configuration */ + #define RCC_CFGR2_PREDIV1 ((uint32_t)0x0000000F) /*!< PREDIV1[3:0] bits */ + #define RCC_CFGR2_PREDIV1_0 ((uint32_t)0x00000001) /*!< Bit 0 */ + #define RCC_CFGR2_PREDIV1_1 ((uint32_t)0x00000002) /*!< Bit 1 */ + #define RCC_CFGR2_PREDIV1_2 ((uint32_t)0x00000004) /*!< Bit 2 */ + #define RCC_CFGR2_PREDIV1_3 ((uint32_t)0x00000008) /*!< Bit 3 */ + + #define RCC_CFGR2_PREDIV1_DIV1 ((uint32_t)0x00000000) /*!< PREDIV1 input clock not divided */ + #define RCC_CFGR2_PREDIV1_DIV2 ((uint32_t)0x00000001) /*!< PREDIV1 input clock divided by 2 */ + #define RCC_CFGR2_PREDIV1_DIV3 ((uint32_t)0x00000002) /*!< PREDIV1 input clock divided by 3 */ + #define RCC_CFGR2_PREDIV1_DIV4 ((uint32_t)0x00000003) /*!< PREDIV1 input clock divided by 4 */ + #define RCC_CFGR2_PREDIV1_DIV5 ((uint32_t)0x00000004) /*!< PREDIV1 input clock divided by 5 */ + #define RCC_CFGR2_PREDIV1_DIV6 ((uint32_t)0x00000005) /*!< PREDIV1 input clock divided by 6 */ + #define RCC_CFGR2_PREDIV1_DIV7 ((uint32_t)0x00000006) /*!< PREDIV1 input clock divided by 7 */ + #define RCC_CFGR2_PREDIV1_DIV8 ((uint32_t)0x00000007) /*!< PREDIV1 input clock divided by 8 */ + #define RCC_CFGR2_PREDIV1_DIV9 ((uint32_t)0x00000008) /*!< PREDIV1 input clock divided by 9 */ + #define RCC_CFGR2_PREDIV1_DIV10 ((uint32_t)0x00000009) /*!< PREDIV1 input clock divided by 10 */ + #define RCC_CFGR2_PREDIV1_DIV11 ((uint32_t)0x0000000A) /*!< PREDIV1 input clock divided by 11 */ + #define RCC_CFGR2_PREDIV1_DIV12 ((uint32_t)0x0000000B) /*!< PREDIV1 input clock divided by 12 */ + #define RCC_CFGR2_PREDIV1_DIV13 ((uint32_t)0x0000000C) /*!< PREDIV1 input clock divided by 13 */ + #define RCC_CFGR2_PREDIV1_DIV14 ((uint32_t)0x0000000D) /*!< PREDIV1 input clock divided by 14 */ + #define RCC_CFGR2_PREDIV1_DIV15 ((uint32_t)0x0000000E) /*!< PREDIV1 input clock divided by 15 */ + #define RCC_CFGR2_PREDIV1_DIV16 ((uint32_t)0x0000000F) /*!< PREDIV1 input clock divided by 16 */ +#endif + +/******************************************************************************/ +/* */ +/* General Purpose and Alternate Function I/O */ +/* */ +/******************************************************************************/ + +/******************* Bit definition for GPIO_CRL register *******************/ +#define GPIO_CRL_MODE ((uint32_t)0x33333333) /*!< Port x mode bits */ + +#define GPIO_CRL_MODE0 ((uint32_t)0x00000003) /*!< MODE0[1:0] bits (Port x mode bits, pin 0) */ +#define GPIO_CRL_MODE0_0 ((uint32_t)0x00000001) /*!< Bit 0 */ +#define GPIO_CRL_MODE0_1 ((uint32_t)0x00000002) /*!< Bit 1 */ + +#define GPIO_CRL_MODE1 ((uint32_t)0x00000030) /*!< MODE1[1:0] bits (Port x mode bits, pin 1) */ +#define GPIO_CRL_MODE1_0 ((uint32_t)0x00000010) /*!< Bit 0 */ +#define GPIO_CRL_MODE1_1 ((uint32_t)0x00000020) /*!< Bit 1 */ + +#define GPIO_CRL_MODE2 ((uint32_t)0x00000300) /*!< MODE2[1:0] bits (Port x mode bits, pin 2) */ +#define GPIO_CRL_MODE2_0 ((uint32_t)0x00000100) /*!< Bit 0 */ +#define GPIO_CRL_MODE2_1 ((uint32_t)0x00000200) /*!< Bit 1 */ + +#define GPIO_CRL_MODE3 ((uint32_t)0x00003000) /*!< MODE3[1:0] bits (Port x mode bits, pin 3) */ +#define GPIO_CRL_MODE3_0 ((uint32_t)0x00001000) /*!< Bit 0 */ +#define GPIO_CRL_MODE3_1 ((uint32_t)0x00002000) /*!< Bit 1 */ + +#define GPIO_CRL_MODE4 ((uint32_t)0x00030000) /*!< MODE4[1:0] bits (Port x mode bits, pin 4) */ +#define GPIO_CRL_MODE4_0 ((uint32_t)0x00010000) /*!< Bit 0 */ +#define GPIO_CRL_MODE4_1 ((uint32_t)0x00020000) /*!< Bit 1 */ + +#define GPIO_CRL_MODE5 ((uint32_t)0x00300000) /*!< MODE5[1:0] bits (Port x mode bits, pin 5) */ +#define GPIO_CRL_MODE5_0 ((uint32_t)0x00100000) /*!< Bit 0 */ +#define GPIO_CRL_MODE5_1 ((uint32_t)0x00200000) /*!< Bit 1 */ + +#define GPIO_CRL_MODE6 ((uint32_t)0x03000000) /*!< MODE6[1:0] bits (Port x mode bits, pin 6) */ +#define GPIO_CRL_MODE6_0 ((uint32_t)0x01000000) /*!< Bit 0 */ +#define GPIO_CRL_MODE6_1 ((uint32_t)0x02000000) /*!< Bit 1 */ + +#define GPIO_CRL_MODE7 ((uint32_t)0x30000000) /*!< MODE7[1:0] bits (Port x mode bits, pin 7) */ +#define GPIO_CRL_MODE7_0 ((uint32_t)0x10000000) /*!< Bit 0 */ +#define GPIO_CRL_MODE7_1 ((uint32_t)0x20000000) /*!< Bit 1 */ + +#define GPIO_CRL_CNF ((uint32_t)0xCCCCCCCC) /*!< Port x configuration bits */ + +#define GPIO_CRL_CNF0 ((uint32_t)0x0000000C) /*!< CNF0[1:0] bits (Port x configuration bits, pin 0) */ +#define GPIO_CRL_CNF0_0 ((uint32_t)0x00000004) /*!< Bit 0 */ +#define GPIO_CRL_CNF0_1 ((uint32_t)0x00000008) /*!< Bit 1 */ + +#define GPIO_CRL_CNF1 ((uint32_t)0x000000C0) /*!< CNF1[1:0] bits (Port x configuration bits, pin 1) */ +#define GPIO_CRL_CNF1_0 ((uint32_t)0x00000040) /*!< Bit 0 */ +#define GPIO_CRL_CNF1_1 ((uint32_t)0x00000080) /*!< Bit 1 */ + +#define GPIO_CRL_CNF2 ((uint32_t)0x00000C00) /*!< CNF2[1:0] bits (Port x configuration bits, pin 2) */ +#define GPIO_CRL_CNF2_0 ((uint32_t)0x00000400) /*!< Bit 0 */ +#define GPIO_CRL_CNF2_1 ((uint32_t)0x00000800) /*!< Bit 1 */ + +#define GPIO_CRL_CNF3 ((uint32_t)0x0000C000) /*!< CNF3[1:0] bits (Port x configuration bits, pin 3) */ +#define GPIO_CRL_CNF3_0 ((uint32_t)0x00004000) /*!< Bit 0 */ +#define GPIO_CRL_CNF3_1 ((uint32_t)0x00008000) /*!< Bit 1 */ + +#define GPIO_CRL_CNF4 ((uint32_t)0x000C0000) /*!< CNF4[1:0] bits (Port x configuration bits, pin 4) */ +#define GPIO_CRL_CNF4_0 ((uint32_t)0x00040000) /*!< Bit 0 */ +#define GPIO_CRL_CNF4_1 ((uint32_t)0x00080000) /*!< Bit 1 */ + +#define GPIO_CRL_CNF5 ((uint32_t)0x00C00000) /*!< CNF5[1:0] bits (Port x configuration bits, pin 5) */ +#define GPIO_CRL_CNF5_0 ((uint32_t)0x00400000) /*!< Bit 0 */ +#define GPIO_CRL_CNF5_1 ((uint32_t)0x00800000) /*!< Bit 1 */ + +#define GPIO_CRL_CNF6 ((uint32_t)0x0C000000) /*!< CNF6[1:0] bits (Port x configuration bits, pin 6) */ +#define GPIO_CRL_CNF6_0 ((uint32_t)0x04000000) /*!< Bit 0 */ +#define GPIO_CRL_CNF6_1 ((uint32_t)0x08000000) /*!< Bit 1 */ + +#define GPIO_CRL_CNF7 ((uint32_t)0xC0000000) /*!< CNF7[1:0] bits (Port x configuration bits, pin 7) */ +#define GPIO_CRL_CNF7_0 ((uint32_t)0x40000000) /*!< Bit 0 */ +#define GPIO_CRL_CNF7_1 ((uint32_t)0x80000000) /*!< Bit 1 */ + +/******************* Bit definition for GPIO_CRH register *******************/ +#define GPIO_CRH_MODE ((uint32_t)0x33333333) /*!< Port x mode bits */ + +#define GPIO_CRH_MODE8 ((uint32_t)0x00000003) /*!< MODE8[1:0] bits (Port x mode bits, pin 8) */ +#define GPIO_CRH_MODE8_0 ((uint32_t)0x00000001) /*!< Bit 0 */ +#define GPIO_CRH_MODE8_1 ((uint32_t)0x00000002) /*!< Bit 1 */ + +#define GPIO_CRH_MODE9 ((uint32_t)0x00000030) /*!< MODE9[1:0] bits (Port x mode bits, pin 9) */ +#define GPIO_CRH_MODE9_0 ((uint32_t)0x00000010) /*!< Bit 0 */ +#define GPIO_CRH_MODE9_1 ((uint32_t)0x00000020) /*!< Bit 1 */ + +#define GPIO_CRH_MODE10 ((uint32_t)0x00000300) /*!< MODE10[1:0] bits (Port x mode bits, pin 10) */ +#define GPIO_CRH_MODE10_0 ((uint32_t)0x00000100) /*!< Bit 0 */ +#define GPIO_CRH_MODE10_1 ((uint32_t)0x00000200) /*!< Bit 1 */ + +#define GPIO_CRH_MODE11 ((uint32_t)0x00003000) /*!< MODE11[1:0] bits (Port x mode bits, pin 11) */ +#define GPIO_CRH_MODE11_0 ((uint32_t)0x00001000) /*!< Bit 0 */ +#define GPIO_CRH_MODE11_1 ((uint32_t)0x00002000) /*!< Bit 1 */ + +#define GPIO_CRH_MODE12 ((uint32_t)0x00030000) /*!< MODE12[1:0] bits (Port x mode bits, pin 12) */ +#define GPIO_CRH_MODE12_0 ((uint32_t)0x00010000) /*!< Bit 0 */ +#define GPIO_CRH_MODE12_1 ((uint32_t)0x00020000) /*!< Bit 1 */ + +#define GPIO_CRH_MODE13 ((uint32_t)0x00300000) /*!< MODE13[1:0] bits (Port x mode bits, pin 13) */ +#define GPIO_CRH_MODE13_0 ((uint32_t)0x00100000) /*!< Bit 0 */ +#define GPIO_CRH_MODE13_1 ((uint32_t)0x00200000) /*!< Bit 1 */ + +#define GPIO_CRH_MODE14 ((uint32_t)0x03000000) /*!< MODE14[1:0] bits (Port x mode bits, pin 14) */ +#define GPIO_CRH_MODE14_0 ((uint32_t)0x01000000) /*!< Bit 0 */ +#define GPIO_CRH_MODE14_1 ((uint32_t)0x02000000) /*!< Bit 1 */ + +#define GPIO_CRH_MODE15 ((uint32_t)0x30000000) /*!< MODE15[1:0] bits (Port x mode bits, pin 15) */ +#define GPIO_CRH_MODE15_0 ((uint32_t)0x10000000) /*!< Bit 0 */ +#define GPIO_CRH_MODE15_1 ((uint32_t)0x20000000) /*!< Bit 1 */ + +#define GPIO_CRH_CNF ((uint32_t)0xCCCCCCCC) /*!< Port x configuration bits */ + +#define GPIO_CRH_CNF8 ((uint32_t)0x0000000C) /*!< CNF8[1:0] bits (Port x configuration bits, pin 8) */ +#define GPIO_CRH_CNF8_0 ((uint32_t)0x00000004) /*!< Bit 0 */ +#define GPIO_CRH_CNF8_1 ((uint32_t)0x00000008) /*!< Bit 1 */ + +#define GPIO_CRH_CNF9 ((uint32_t)0x000000C0) /*!< CNF9[1:0] bits (Port x configuration bits, pin 9) */ +#define GPIO_CRH_CNF9_0 ((uint32_t)0x00000040) /*!< Bit 0 */ +#define GPIO_CRH_CNF9_1 ((uint32_t)0x00000080) /*!< Bit 1 */ + +#define GPIO_CRH_CNF10 ((uint32_t)0x00000C00) /*!< CNF10[1:0] bits (Port x configuration bits, pin 10) */ +#define GPIO_CRH_CNF10_0 ((uint32_t)0x00000400) /*!< Bit 0 */ +#define GPIO_CRH_CNF10_1 ((uint32_t)0x00000800) /*!< Bit 1 */ + +#define GPIO_CRH_CNF11 ((uint32_t)0x0000C000) /*!< CNF11[1:0] bits (Port x configuration bits, pin 11) */ +#define GPIO_CRH_CNF11_0 ((uint32_t)0x00004000) /*!< Bit 0 */ +#define GPIO_CRH_CNF11_1 ((uint32_t)0x00008000) /*!< Bit 1 */ + +#define GPIO_CRH_CNF12 ((uint32_t)0x000C0000) /*!< CNF12[1:0] bits (Port x configuration bits, pin 12) */ +#define GPIO_CRH_CNF12_0 ((uint32_t)0x00040000) /*!< Bit 0 */ +#define GPIO_CRH_CNF12_1 ((uint32_t)0x00080000) /*!< Bit 1 */ + +#define GPIO_CRH_CNF13 ((uint32_t)0x00C00000) /*!< CNF13[1:0] bits (Port x configuration bits, pin 13) */ +#define GPIO_CRH_CNF13_0 ((uint32_t)0x00400000) /*!< Bit 0 */ +#define GPIO_CRH_CNF13_1 ((uint32_t)0x00800000) /*!< Bit 1 */ + +#define GPIO_CRH_CNF14 ((uint32_t)0x0C000000) /*!< CNF14[1:0] bits (Port x configuration bits, pin 14) */ +#define GPIO_CRH_CNF14_0 ((uint32_t)0x04000000) /*!< Bit 0 */ +#define GPIO_CRH_CNF14_1 ((uint32_t)0x08000000) /*!< Bit 1 */ + +#define GPIO_CRH_CNF15 ((uint32_t)0xC0000000) /*!< CNF15[1:0] bits (Port x configuration bits, pin 15) */ +#define GPIO_CRH_CNF15_0 ((uint32_t)0x40000000) /*!< Bit 0 */ +#define GPIO_CRH_CNF15_1 ((uint32_t)0x80000000) /*!< Bit 1 */ + +/*!<****************** Bit definition for GPIO_IDR register *******************/ +#define GPIO_IDR_IDR0 ((uint16_t)0x0001) /*!< Port input data, bit 0 */ +#define GPIO_IDR_IDR1 ((uint16_t)0x0002) /*!< Port input data, bit 1 */ +#define GPIO_IDR_IDR2 ((uint16_t)0x0004) /*!< Port input data, bit 2 */ +#define GPIO_IDR_IDR3 ((uint16_t)0x0008) /*!< Port input data, bit 3 */ +#define GPIO_IDR_IDR4 ((uint16_t)0x0010) /*!< Port input data, bit 4 */ +#define GPIO_IDR_IDR5 ((uint16_t)0x0020) /*!< Port input data, bit 5 */ +#define GPIO_IDR_IDR6 ((uint16_t)0x0040) /*!< Port input data, bit 6 */ +#define GPIO_IDR_IDR7 ((uint16_t)0x0080) /*!< Port input data, bit 7 */ +#define GPIO_IDR_IDR8 ((uint16_t)0x0100) /*!< Port input data, bit 8 */ +#define GPIO_IDR_IDR9 ((uint16_t)0x0200) /*!< Port input data, bit 9 */ +#define GPIO_IDR_IDR10 ((uint16_t)0x0400) /*!< Port input data, bit 10 */ +#define GPIO_IDR_IDR11 ((uint16_t)0x0800) /*!< Port input data, bit 11 */ +#define GPIO_IDR_IDR12 ((uint16_t)0x1000) /*!< Port input data, bit 12 */ +#define GPIO_IDR_IDR13 ((uint16_t)0x2000) /*!< Port input data, bit 13 */ +#define GPIO_IDR_IDR14 ((uint16_t)0x4000) /*!< Port input data, bit 14 */ +#define GPIO_IDR_IDR15 ((uint16_t)0x8000) /*!< Port input data, bit 15 */ + +/******************* Bit definition for GPIO_ODR register *******************/ +#define GPIO_ODR_ODR0 ((uint16_t)0x0001) /*!< Port output data, bit 0 */ +#define GPIO_ODR_ODR1 ((uint16_t)0x0002) /*!< Port output data, bit 1 */ +#define GPIO_ODR_ODR2 ((uint16_t)0x0004) /*!< Port output data, bit 2 */ +#define GPIO_ODR_ODR3 ((uint16_t)0x0008) /*!< Port output data, bit 3 */ +#define GPIO_ODR_ODR4 ((uint16_t)0x0010) /*!< Port output data, bit 4 */ +#define GPIO_ODR_ODR5 ((uint16_t)0x0020) /*!< Port output data, bit 5 */ +#define GPIO_ODR_ODR6 ((uint16_t)0x0040) /*!< Port output data, bit 6 */ +#define GPIO_ODR_ODR7 ((uint16_t)0x0080) /*!< Port output data, bit 7 */ +#define GPIO_ODR_ODR8 ((uint16_t)0x0100) /*!< Port output data, bit 8 */ +#define GPIO_ODR_ODR9 ((uint16_t)0x0200) /*!< Port output data, bit 9 */ +#define GPIO_ODR_ODR10 ((uint16_t)0x0400) /*!< Port output data, bit 10 */ +#define GPIO_ODR_ODR11 ((uint16_t)0x0800) /*!< Port output data, bit 11 */ +#define GPIO_ODR_ODR12 ((uint16_t)0x1000) /*!< Port output data, bit 12 */ +#define GPIO_ODR_ODR13 ((uint16_t)0x2000) /*!< Port output data, bit 13 */ +#define GPIO_ODR_ODR14 ((uint16_t)0x4000) /*!< Port output data, bit 14 */ +#define GPIO_ODR_ODR15 ((uint16_t)0x8000) /*!< Port output data, bit 15 */ + +/****************** Bit definition for GPIO_BSRR register *******************/ +#define GPIO_BSRR_BS0 ((uint32_t)0x00000001) /*!< Port x Set bit 0 */ +#define GPIO_BSRR_BS1 ((uint32_t)0x00000002) /*!< Port x Set bit 1 */ +#define GPIO_BSRR_BS2 ((uint32_t)0x00000004) /*!< Port x Set bit 2 */ +#define GPIO_BSRR_BS3 ((uint32_t)0x00000008) /*!< Port x Set bit 3 */ +#define GPIO_BSRR_BS4 ((uint32_t)0x00000010) /*!< Port x Set bit 4 */ +#define GPIO_BSRR_BS5 ((uint32_t)0x00000020) /*!< Port x Set bit 5 */ +#define GPIO_BSRR_BS6 ((uint32_t)0x00000040) /*!< Port x Set bit 6 */ +#define GPIO_BSRR_BS7 ((uint32_t)0x00000080) /*!< Port x Set bit 7 */ +#define GPIO_BSRR_BS8 ((uint32_t)0x00000100) /*!< Port x Set bit 8 */ +#define GPIO_BSRR_BS9 ((uint32_t)0x00000200) /*!< Port x Set bit 9 */ +#define GPIO_BSRR_BS10 ((uint32_t)0x00000400) /*!< Port x Set bit 10 */ +#define GPIO_BSRR_BS11 ((uint32_t)0x00000800) /*!< Port x Set bit 11 */ +#define GPIO_BSRR_BS12 ((uint32_t)0x00001000) /*!< Port x Set bit 12 */ +#define GPIO_BSRR_BS13 ((uint32_t)0x00002000) /*!< Port x Set bit 13 */ +#define GPIO_BSRR_BS14 ((uint32_t)0x00004000) /*!< Port x Set bit 14 */ +#define GPIO_BSRR_BS15 ((uint32_t)0x00008000) /*!< Port x Set bit 15 */ + +#define GPIO_BSRR_BR0 ((uint32_t)0x00010000) /*!< Port x Reset bit 0 */ +#define GPIO_BSRR_BR1 ((uint32_t)0x00020000) /*!< Port x Reset bit 1 */ +#define GPIO_BSRR_BR2 ((uint32_t)0x00040000) /*!< Port x Reset bit 2 */ +#define GPIO_BSRR_BR3 ((uint32_t)0x00080000) /*!< Port x Reset bit 3 */ +#define GPIO_BSRR_BR4 ((uint32_t)0x00100000) /*!< Port x Reset bit 4 */ +#define GPIO_BSRR_BR5 ((uint32_t)0x00200000) /*!< Port x Reset bit 5 */ +#define GPIO_BSRR_BR6 ((uint32_t)0x00400000) /*!< Port x Reset bit 6 */ +#define GPIO_BSRR_BR7 ((uint32_t)0x00800000) /*!< Port x Reset bit 7 */ +#define GPIO_BSRR_BR8 ((uint32_t)0x01000000) /*!< Port x Reset bit 8 */ +#define GPIO_BSRR_BR9 ((uint32_t)0x02000000) /*!< Port x Reset bit 9 */ +#define GPIO_BSRR_BR10 ((uint32_t)0x04000000) /*!< Port x Reset bit 10 */ +#define GPIO_BSRR_BR11 ((uint32_t)0x08000000) /*!< Port x Reset bit 11 */ +#define GPIO_BSRR_BR12 ((uint32_t)0x10000000) /*!< Port x Reset bit 12 */ +#define GPIO_BSRR_BR13 ((uint32_t)0x20000000) /*!< Port x Reset bit 13 */ +#define GPIO_BSRR_BR14 ((uint32_t)0x40000000) /*!< Port x Reset bit 14 */ +#define GPIO_BSRR_BR15 ((uint32_t)0x80000000) /*!< Port x Reset bit 15 */ + +/******************* Bit definition for GPIO_BRR register *******************/ +#define GPIO_BRR_BR0 ((uint16_t)0x0001) /*!< Port x Reset bit 0 */ +#define GPIO_BRR_BR1 ((uint16_t)0x0002) /*!< Port x Reset bit 1 */ +#define GPIO_BRR_BR2 ((uint16_t)0x0004) /*!< Port x Reset bit 2 */ +#define GPIO_BRR_BR3 ((uint16_t)0x0008) /*!< Port x Reset bit 3 */ +#define GPIO_BRR_BR4 ((uint16_t)0x0010) /*!< Port x Reset bit 4 */ +#define GPIO_BRR_BR5 ((uint16_t)0x0020) /*!< Port x Reset bit 5 */ +#define GPIO_BRR_BR6 ((uint16_t)0x0040) /*!< Port x Reset bit 6 */ +#define GPIO_BRR_BR7 ((uint16_t)0x0080) /*!< Port x Reset bit 7 */ +#define GPIO_BRR_BR8 ((uint16_t)0x0100) /*!< Port x Reset bit 8 */ +#define GPIO_BRR_BR9 ((uint16_t)0x0200) /*!< Port x Reset bit 9 */ +#define GPIO_BRR_BR10 ((uint16_t)0x0400) /*!< Port x Reset bit 10 */ +#define GPIO_BRR_BR11 ((uint16_t)0x0800) /*!< Port x Reset bit 11 */ +#define GPIO_BRR_BR12 ((uint16_t)0x1000) /*!< Port x Reset bit 12 */ +#define GPIO_BRR_BR13 ((uint16_t)0x2000) /*!< Port x Reset bit 13 */ +#define GPIO_BRR_BR14 ((uint16_t)0x4000) /*!< Port x Reset bit 14 */ +#define GPIO_BRR_BR15 ((uint16_t)0x8000) /*!< Port x Reset bit 15 */ + +/****************** Bit definition for GPIO_LCKR register *******************/ +#define GPIO_LCKR_LCK0 ((uint32_t)0x00000001) /*!< Port x Lock bit 0 */ +#define GPIO_LCKR_LCK1 ((uint32_t)0x00000002) /*!< Port x Lock bit 1 */ +#define GPIO_LCKR_LCK2 ((uint32_t)0x00000004) /*!< Port x Lock bit 2 */ +#define GPIO_LCKR_LCK3 ((uint32_t)0x00000008) /*!< Port x Lock bit 3 */ +#define GPIO_LCKR_LCK4 ((uint32_t)0x00000010) /*!< Port x Lock bit 4 */ +#define GPIO_LCKR_LCK5 ((uint32_t)0x00000020) /*!< Port x Lock bit 5 */ +#define GPIO_LCKR_LCK6 ((uint32_t)0x00000040) /*!< Port x Lock bit 6 */ +#define GPIO_LCKR_LCK7 ((uint32_t)0x00000080) /*!< Port x Lock bit 7 */ +#define GPIO_LCKR_LCK8 ((uint32_t)0x00000100) /*!< Port x Lock bit 8 */ +#define GPIO_LCKR_LCK9 ((uint32_t)0x00000200) /*!< Port x Lock bit 9 */ +#define GPIO_LCKR_LCK10 ((uint32_t)0x00000400) /*!< Port x Lock bit 10 */ +#define GPIO_LCKR_LCK11 ((uint32_t)0x00000800) /*!< Port x Lock bit 11 */ +#define GPIO_LCKR_LCK12 ((uint32_t)0x00001000) /*!< Port x Lock bit 12 */ +#define GPIO_LCKR_LCK13 ((uint32_t)0x00002000) /*!< Port x Lock bit 13 */ +#define GPIO_LCKR_LCK14 ((uint32_t)0x00004000) /*!< Port x Lock bit 14 */ +#define GPIO_LCKR_LCK15 ((uint32_t)0x00008000) /*!< Port x Lock bit 15 */ +#define GPIO_LCKR_LCKK ((uint32_t)0x00010000) /*!< Lock key */ + +/*----------------------------------------------------------------------------*/ + +/****************** Bit definition for AFIO_EVCR register *******************/ +#define AFIO_EVCR_PIN ((uint8_t)0x0F) /*!< PIN[3:0] bits (Pin selection) */ +#define AFIO_EVCR_PIN_0 ((uint8_t)0x01) /*!< Bit 0 */ +#define AFIO_EVCR_PIN_1 ((uint8_t)0x02) /*!< Bit 1 */ +#define AFIO_EVCR_PIN_2 ((uint8_t)0x04) /*!< Bit 2 */ +#define AFIO_EVCR_PIN_3 ((uint8_t)0x08) /*!< Bit 3 */ + +/*!< PIN configuration */ +#define AFIO_EVCR_PIN_PX0 ((uint8_t)0x00) /*!< Pin 0 selected */ +#define AFIO_EVCR_PIN_PX1 ((uint8_t)0x01) /*!< Pin 1 selected */ +#define AFIO_EVCR_PIN_PX2 ((uint8_t)0x02) /*!< Pin 2 selected */ +#define AFIO_EVCR_PIN_PX3 ((uint8_t)0x03) /*!< Pin 3 selected */ +#define AFIO_EVCR_PIN_PX4 ((uint8_t)0x04) /*!< Pin 4 selected */ +#define AFIO_EVCR_PIN_PX5 ((uint8_t)0x05) /*!< Pin 5 selected */ +#define AFIO_EVCR_PIN_PX6 ((uint8_t)0x06) /*!< Pin 6 selected */ +#define AFIO_EVCR_PIN_PX7 ((uint8_t)0x07) /*!< Pin 7 selected */ +#define AFIO_EVCR_PIN_PX8 ((uint8_t)0x08) /*!< Pin 8 selected */ +#define AFIO_EVCR_PIN_PX9 ((uint8_t)0x09) /*!< Pin 9 selected */ +#define AFIO_EVCR_PIN_PX10 ((uint8_t)0x0A) /*!< Pin 10 selected */ +#define AFIO_EVCR_PIN_PX11 ((uint8_t)0x0B) /*!< Pin 11 selected */ +#define AFIO_EVCR_PIN_PX12 ((uint8_t)0x0C) /*!< Pin 12 selected */ +#define AFIO_EVCR_PIN_PX13 ((uint8_t)0x0D) /*!< Pin 13 selected */ +#define AFIO_EVCR_PIN_PX14 ((uint8_t)0x0E) /*!< Pin 14 selected */ +#define AFIO_EVCR_PIN_PX15 ((uint8_t)0x0F) /*!< Pin 15 selected */ + +#define AFIO_EVCR_PORT ((uint8_t)0x70) /*!< PORT[2:0] bits (Port selection) */ +#define AFIO_EVCR_PORT_0 ((uint8_t)0x10) /*!< Bit 0 */ +#define AFIO_EVCR_PORT_1 ((uint8_t)0x20) /*!< Bit 1 */ +#define AFIO_EVCR_PORT_2 ((uint8_t)0x40) /*!< Bit 2 */ + +/*!< PORT configuration */ +#define AFIO_EVCR_PORT_PA ((uint8_t)0x00) /*!< Port A selected */ +#define AFIO_EVCR_PORT_PB ((uint8_t)0x10) /*!< Port B selected */ +#define AFIO_EVCR_PORT_PC ((uint8_t)0x20) /*!< Port C selected */ +#define AFIO_EVCR_PORT_PD ((uint8_t)0x30) /*!< Port D selected */ +#define AFIO_EVCR_PORT_PE ((uint8_t)0x40) /*!< Port E selected */ + +#define AFIO_EVCR_EVOE ((uint8_t)0x80) /*!< Event Output Enable */ + +/****************** Bit definition for AFIO_MAPR register *******************/ +#define AFIO_MAPR_SPI1_REMAP ((uint32_t)0x00000001) /*!< SPI1 remapping */ +#define AFIO_MAPR_I2C1_REMAP ((uint32_t)0x00000002) /*!< I2C1 remapping */ +#define AFIO_MAPR_USART1_REMAP ((uint32_t)0x00000004) /*!< USART1 remapping */ +#define AFIO_MAPR_USART2_REMAP ((uint32_t)0x00000008) /*!< USART2 remapping */ + +#define AFIO_MAPR_USART3_REMAP ((uint32_t)0x00000030) /*!< USART3_REMAP[1:0] bits (USART3 remapping) */ +#define AFIO_MAPR_USART3_REMAP_0 ((uint32_t)0x00000010) /*!< Bit 0 */ +#define AFIO_MAPR_USART3_REMAP_1 ((uint32_t)0x00000020) /*!< Bit 1 */ + +/* USART3_REMAP configuration */ +#define AFIO_MAPR_USART3_REMAP_NOREMAP ((uint32_t)0x00000000) /*!< No remap (TX/PB10, RX/PB11, CK/PB12, CTS/PB13, RTS/PB14) */ +#define AFIO_MAPR_USART3_REMAP_PARTIALREMAP ((uint32_t)0x00000010) /*!< Partial remap (TX/PC10, RX/PC11, CK/PC12, CTS/PB13, RTS/PB14) */ +#define AFIO_MAPR_USART3_REMAP_FULLREMAP ((uint32_t)0x00000030) /*!< Full remap (TX/PD8, RX/PD9, CK/PD10, CTS/PD11, RTS/PD12) */ + +#define AFIO_MAPR_TIM1_REMAP ((uint32_t)0x000000C0) /*!< TIM1_REMAP[1:0] bits (TIM1 remapping) */ +#define AFIO_MAPR_TIM1_REMAP_0 ((uint32_t)0x00000040) /*!< Bit 0 */ +#define AFIO_MAPR_TIM1_REMAP_1 ((uint32_t)0x00000080) /*!< Bit 1 */ + +/*!< TIM1_REMAP configuration */ +#define AFIO_MAPR_TIM1_REMAP_NOREMAP ((uint32_t)0x00000000) /*!< No remap (ETR/PA12, CH1/PA8, CH2/PA9, CH3/PA10, CH4/PA11, BKIN/PB12, CH1N/PB13, CH2N/PB14, CH3N/PB15) */ +#define AFIO_MAPR_TIM1_REMAP_PARTIALREMAP ((uint32_t)0x00000040) /*!< Partial remap (ETR/PA12, CH1/PA8, CH2/PA9, CH3/PA10, CH4/PA11, BKIN/PA6, CH1N/PA7, CH2N/PB0, CH3N/PB1) */ +#define AFIO_MAPR_TIM1_REMAP_FULLREMAP ((uint32_t)0x000000C0) /*!< Full remap (ETR/PE7, CH1/PE9, CH2/PE11, CH3/PE13, CH4/PE14, BKIN/PE15, CH1N/PE8, CH2N/PE10, CH3N/PE12) */ + +#define AFIO_MAPR_TIM2_REMAP ((uint32_t)0x00000300) /*!< TIM2_REMAP[1:0] bits (TIM2 remapping) */ +#define AFIO_MAPR_TIM2_REMAP_0 ((uint32_t)0x00000100) /*!< Bit 0 */ +#define AFIO_MAPR_TIM2_REMAP_1 ((uint32_t)0x00000200) /*!< Bit 1 */ + +/*!< TIM2_REMAP configuration */ +#define AFIO_MAPR_TIM2_REMAP_NOREMAP ((uint32_t)0x00000000) /*!< No remap (CH1/ETR/PA0, CH2/PA1, CH3/PA2, CH4/PA3) */ +#define AFIO_MAPR_TIM2_REMAP_PARTIALREMAP1 ((uint32_t)0x00000100) /*!< Partial remap (CH1/ETR/PA15, CH2/PB3, CH3/PA2, CH4/PA3) */ +#define AFIO_MAPR_TIM2_REMAP_PARTIALREMAP2 ((uint32_t)0x00000200) /*!< Partial remap (CH1/ETR/PA0, CH2/PA1, CH3/PB10, CH4/PB11) */ +#define AFIO_MAPR_TIM2_REMAP_FULLREMAP ((uint32_t)0x00000300) /*!< Full remap (CH1/ETR/PA15, CH2/PB3, CH3/PB10, CH4/PB11) */ + +#define AFIO_MAPR_TIM3_REMAP ((uint32_t)0x00000C00) /*!< TIM3_REMAP[1:0] bits (TIM3 remapping) */ +#define AFIO_MAPR_TIM3_REMAP_0 ((uint32_t)0x00000400) /*!< Bit 0 */ +#define AFIO_MAPR_TIM3_REMAP_1 ((uint32_t)0x00000800) /*!< Bit 1 */ + +/*!< TIM3_REMAP configuration */ +#define AFIO_MAPR_TIM3_REMAP_NOREMAP ((uint32_t)0x00000000) /*!< No remap (CH1/PA6, CH2/PA7, CH3/PB0, CH4/PB1) */ +#define AFIO_MAPR_TIM3_REMAP_PARTIALREMAP ((uint32_t)0x00000800) /*!< Partial remap (CH1/PB4, CH2/PB5, CH3/PB0, CH4/PB1) */ +#define AFIO_MAPR_TIM3_REMAP_FULLREMAP ((uint32_t)0x00000C00) /*!< Full remap (CH1/PC6, CH2/PC7, CH3/PC8, CH4/PC9) */ + +#define AFIO_MAPR_TIM4_REMAP ((uint32_t)0x00001000) /*!< TIM4_REMAP bit (TIM4 remapping) */ + +#define AFIO_MAPR_CAN_REMAP ((uint32_t)0x00006000) /*!< CAN_REMAP[1:0] bits (CAN Alternate function remapping) */ +#define AFIO_MAPR_CAN_REMAP_0 ((uint32_t)0x00002000) /*!< Bit 0 */ +#define AFIO_MAPR_CAN_REMAP_1 ((uint32_t)0x00004000) /*!< Bit 1 */ + +/*!< CAN_REMAP configuration */ +#define AFIO_MAPR_CAN_REMAP_REMAP1 ((uint32_t)0x00000000) /*!< CANRX mapped to PA11, CANTX mapped to PA12 */ +#define AFIO_MAPR_CAN_REMAP_REMAP2 ((uint32_t)0x00004000) /*!< CANRX mapped to PB8, CANTX mapped to PB9 */ +#define AFIO_MAPR_CAN_REMAP_REMAP3 ((uint32_t)0x00006000) /*!< CANRX mapped to PD0, CANTX mapped to PD1 */ + +#define AFIO_MAPR_PD01_REMAP ((uint32_t)0x00008000) /*!< Port D0/Port D1 mapping on OSC_IN/OSC_OUT */ +#define AFIO_MAPR_TIM5CH4_IREMAP ((uint32_t)0x00010000) /*!< TIM5 Channel4 Internal Remap */ +#define AFIO_MAPR_ADC1_ETRGINJ_REMAP ((uint32_t)0x00020000) /*!< ADC 1 External Trigger Injected Conversion remapping */ +#define AFIO_MAPR_ADC1_ETRGREG_REMAP ((uint32_t)0x00040000) /*!< ADC 1 External Trigger Regular Conversion remapping */ +#define AFIO_MAPR_ADC2_ETRGINJ_REMAP ((uint32_t)0x00080000) /*!< ADC 2 External Trigger Injected Conversion remapping */ +#define AFIO_MAPR_ADC2_ETRGREG_REMAP ((uint32_t)0x00100000) /*!< ADC 2 External Trigger Regular Conversion remapping */ + +/*!< SWJ_CFG configuration */ +#define AFIO_MAPR_SWJ_CFG ((uint32_t)0x07000000) /*!< SWJ_CFG[2:0] bits (Serial Wire JTAG configuration) */ +#define AFIO_MAPR_SWJ_CFG_0 ((uint32_t)0x01000000) /*!< Bit 0 */ +#define AFIO_MAPR_SWJ_CFG_1 ((uint32_t)0x02000000) /*!< Bit 1 */ +#define AFIO_MAPR_SWJ_CFG_2 ((uint32_t)0x04000000) /*!< Bit 2 */ + +#define AFIO_MAPR_SWJ_CFG_RESET ((uint32_t)0x00000000) /*!< Full SWJ (JTAG-DP + SW-DP) : Reset State */ +#define AFIO_MAPR_SWJ_CFG_NOJNTRST ((uint32_t)0x01000000) /*!< Full SWJ (JTAG-DP + SW-DP) but without JNTRST */ +#define AFIO_MAPR_SWJ_CFG_JTAGDISABLE ((uint32_t)0x02000000) /*!< JTAG-DP Disabled and SW-DP Enabled */ +#define AFIO_MAPR_SWJ_CFG_DISABLE ((uint32_t)0x04000000) /*!< JTAG-DP Disabled and SW-DP Disabled */ + +#ifdef STM32F10X_CL +/*!< ETH_REMAP configuration */ + #define AFIO_MAPR_ETH_REMAP ((uint32_t)0x00200000) /*!< SPI3_REMAP bit (Ethernet MAC I/O remapping) */ + +/*!< CAN2_REMAP configuration */ + #define AFIO_MAPR_CAN2_REMAP ((uint32_t)0x00400000) /*!< CAN2_REMAP bit (CAN2 I/O remapping) */ + +/*!< MII_RMII_SEL configuration */ + #define AFIO_MAPR_MII_RMII_SEL ((uint32_t)0x00800000) /*!< MII_RMII_SEL bit (Ethernet MII or RMII selection) */ + +/*!< SPI3_REMAP configuration */ + #define AFIO_MAPR_SPI3_REMAP ((uint32_t)0x10000000) /*!< SPI3_REMAP bit (SPI3 remapping) */ + +/*!< TIM2ITR1_IREMAP configuration */ + #define AFIO_MAPR_TIM2ITR1_IREMAP ((uint32_t)0x20000000) /*!< TIM2ITR1_IREMAP bit (TIM2 internal trigger 1 remapping) */ + +/*!< PTP_PPS_REMAP configuration */ + #define AFIO_MAPR_PTP_PPS_REMAP ((uint32_t)0x40000000) /*!< PTP_PPS_REMAP bit (Ethernet PTP PPS remapping) */ +#endif + +/***************** Bit definition for AFIO_EXTICR1 register *****************/ +#define AFIO_EXTICR1_EXTI0 ((uint16_t)0x000F) /*!< EXTI 0 configuration */ +#define AFIO_EXTICR1_EXTI1 ((uint16_t)0x00F0) /*!< EXTI 1 configuration */ +#define AFIO_EXTICR1_EXTI2 ((uint16_t)0x0F00) /*!< EXTI 2 configuration */ +#define AFIO_EXTICR1_EXTI3 ((uint16_t)0xF000) /*!< EXTI 3 configuration */ + +/*!< EXTI0 configuration */ +#define AFIO_EXTICR1_EXTI0_PA ((uint16_t)0x0000) /*!< PA[0] pin */ +#define AFIO_EXTICR1_EXTI0_PB ((uint16_t)0x0001) /*!< PB[0] pin */ +#define AFIO_EXTICR1_EXTI0_PC ((uint16_t)0x0002) /*!< PC[0] pin */ +#define AFIO_EXTICR1_EXTI0_PD ((uint16_t)0x0003) /*!< PD[0] pin */ +#define AFIO_EXTICR1_EXTI0_PE ((uint16_t)0x0004) /*!< PE[0] pin */ +#define AFIO_EXTICR1_EXTI0_PF ((uint16_t)0x0005) /*!< PF[0] pin */ +#define AFIO_EXTICR1_EXTI0_PG ((uint16_t)0x0006) /*!< PG[0] pin */ + +/*!< EXTI1 configuration */ +#define AFIO_EXTICR1_EXTI1_PA ((uint16_t)0x0000) /*!< PA[1] pin */ +#define AFIO_EXTICR1_EXTI1_PB ((uint16_t)0x0010) /*!< PB[1] pin */ +#define AFIO_EXTICR1_EXTI1_PC ((uint16_t)0x0020) /*!< PC[1] pin */ +#define AFIO_EXTICR1_EXTI1_PD ((uint16_t)0x0030) /*!< PD[1] pin */ +#define AFIO_EXTICR1_EXTI1_PE ((uint16_t)0x0040) /*!< PE[1] pin */ +#define AFIO_EXTICR1_EXTI1_PF ((uint16_t)0x0050) /*!< PF[1] pin */ +#define AFIO_EXTICR1_EXTI1_PG ((uint16_t)0x0060) /*!< PG[1] pin */ + +/*!< EXTI2 configuration */ +#define AFIO_EXTICR1_EXTI2_PA ((uint16_t)0x0000) /*!< PA[2] pin */ +#define AFIO_EXTICR1_EXTI2_PB ((uint16_t)0x0100) /*!< PB[2] pin */ +#define AFIO_EXTICR1_EXTI2_PC ((uint16_t)0x0200) /*!< PC[2] pin */ +#define AFIO_EXTICR1_EXTI2_PD ((uint16_t)0x0300) /*!< PD[2] pin */ +#define AFIO_EXTICR1_EXTI2_PE ((uint16_t)0x0400) /*!< PE[2] pin */ +#define AFIO_EXTICR1_EXTI2_PF ((uint16_t)0x0500) /*!< PF[2] pin */ +#define AFIO_EXTICR1_EXTI2_PG ((uint16_t)0x0600) /*!< PG[2] pin */ + +/*!< EXTI3 configuration */ +#define AFIO_EXTICR1_EXTI3_PA ((uint16_t)0x0000) /*!< PA[3] pin */ +#define AFIO_EXTICR1_EXTI3_PB ((uint16_t)0x1000) /*!< PB[3] pin */ +#define AFIO_EXTICR1_EXTI3_PC ((uint16_t)0x2000) /*!< PC[3] pin */ +#define AFIO_EXTICR1_EXTI3_PD ((uint16_t)0x3000) /*!< PD[3] pin */ +#define AFIO_EXTICR1_EXTI3_PE ((uint16_t)0x4000) /*!< PE[3] pin */ +#define AFIO_EXTICR1_EXTI3_PF ((uint16_t)0x5000) /*!< PF[3] pin */ +#define AFIO_EXTICR1_EXTI3_PG ((uint16_t)0x6000) /*!< PG[3] pin */ + +/***************** Bit definition for AFIO_EXTICR2 register *****************/ +#define AFIO_EXTICR2_EXTI4 ((uint16_t)0x000F) /*!< EXTI 4 configuration */ +#define AFIO_EXTICR2_EXTI5 ((uint16_t)0x00F0) /*!< EXTI 5 configuration */ +#define AFIO_EXTICR2_EXTI6 ((uint16_t)0x0F00) /*!< EXTI 6 configuration */ +#define AFIO_EXTICR2_EXTI7 ((uint16_t)0xF000) /*!< EXTI 7 configuration */ + +/*!< EXTI4 configuration */ +#define AFIO_EXTICR2_EXTI4_PA ((uint16_t)0x0000) /*!< PA[4] pin */ +#define AFIO_EXTICR2_EXTI4_PB ((uint16_t)0x0001) /*!< PB[4] pin */ +#define AFIO_EXTICR2_EXTI4_PC ((uint16_t)0x0002) /*!< PC[4] pin */ +#define AFIO_EXTICR2_EXTI4_PD ((uint16_t)0x0003) /*!< PD[4] pin */ +#define AFIO_EXTICR2_EXTI4_PE ((uint16_t)0x0004) /*!< PE[4] pin */ +#define AFIO_EXTICR2_EXTI4_PF ((uint16_t)0x0005) /*!< PF[4] pin */ +#define AFIO_EXTICR2_EXTI4_PG ((uint16_t)0x0006) /*!< PG[4] pin */ + +/* EXTI5 configuration */ +#define AFIO_EXTICR2_EXTI5_PA ((uint16_t)0x0000) /*!< PA[5] pin */ +#define AFIO_EXTICR2_EXTI5_PB ((uint16_t)0x0010) /*!< PB[5] pin */ +#define AFIO_EXTICR2_EXTI5_PC ((uint16_t)0x0020) /*!< PC[5] pin */ +#define AFIO_EXTICR2_EXTI5_PD ((uint16_t)0x0030) /*!< PD[5] pin */ +#define AFIO_EXTICR2_EXTI5_PE ((uint16_t)0x0040) /*!< PE[5] pin */ +#define AFIO_EXTICR2_EXTI5_PF ((uint16_t)0x0050) /*!< PF[5] pin */ +#define AFIO_EXTICR2_EXTI5_PG ((uint16_t)0x0060) /*!< PG[5] pin */ + +/*!< EXTI6 configuration */ +#define AFIO_EXTICR2_EXTI6_PA ((uint16_t)0x0000) /*!< PA[6] pin */ +#define AFIO_EXTICR2_EXTI6_PB ((uint16_t)0x0100) /*!< PB[6] pin */ +#define AFIO_EXTICR2_EXTI6_PC ((uint16_t)0x0200) /*!< PC[6] pin */ +#define AFIO_EXTICR2_EXTI6_PD ((uint16_t)0x0300) /*!< PD[6] pin */ +#define AFIO_EXTICR2_EXTI6_PE ((uint16_t)0x0400) /*!< PE[6] pin */ +#define AFIO_EXTICR2_EXTI6_PF ((uint16_t)0x0500) /*!< PF[6] pin */ +#define AFIO_EXTICR2_EXTI6_PG ((uint16_t)0x0600) /*!< PG[6] pin */ + +/*!< EXTI7 configuration */ +#define AFIO_EXTICR2_EXTI7_PA ((uint16_t)0x0000) /*!< PA[7] pin */ +#define AFIO_EXTICR2_EXTI7_PB ((uint16_t)0x1000) /*!< PB[7] pin */ +#define AFIO_EXTICR2_EXTI7_PC ((uint16_t)0x2000) /*!< PC[7] pin */ +#define AFIO_EXTICR2_EXTI7_PD ((uint16_t)0x3000) /*!< PD[7] pin */ +#define AFIO_EXTICR2_EXTI7_PE ((uint16_t)0x4000) /*!< PE[7] pin */ +#define AFIO_EXTICR2_EXTI7_PF ((uint16_t)0x5000) /*!< PF[7] pin */ +#define AFIO_EXTICR2_EXTI7_PG ((uint16_t)0x6000) /*!< PG[7] pin */ + +/***************** Bit definition for AFIO_EXTICR3 register *****************/ +#define AFIO_EXTICR3_EXTI8 ((uint16_t)0x000F) /*!< EXTI 8 configuration */ +#define AFIO_EXTICR3_EXTI9 ((uint16_t)0x00F0) /*!< EXTI 9 configuration */ +#define AFIO_EXTICR3_EXTI10 ((uint16_t)0x0F00) /*!< EXTI 10 configuration */ +#define AFIO_EXTICR3_EXTI11 ((uint16_t)0xF000) /*!< EXTI 11 configuration */ + +/*!< EXTI8 configuration */ +#define AFIO_EXTICR3_EXTI8_PA ((uint16_t)0x0000) /*!< PA[8] pin */ +#define AFIO_EXTICR3_EXTI8_PB ((uint16_t)0x0001) /*!< PB[8] pin */ +#define AFIO_EXTICR3_EXTI8_PC ((uint16_t)0x0002) /*!< PC[8] pin */ +#define AFIO_EXTICR3_EXTI8_PD ((uint16_t)0x0003) /*!< PD[8] pin */ +#define AFIO_EXTICR3_EXTI8_PE ((uint16_t)0x0004) /*!< PE[8] pin */ +#define AFIO_EXTICR3_EXTI8_PF ((uint16_t)0x0005) /*!< PF[8] pin */ +#define AFIO_EXTICR3_EXTI8_PG ((uint16_t)0x0006) /*!< PG[8] pin */ + +/*!< EXTI9 configuration */ +#define AFIO_EXTICR3_EXTI9_PA ((uint16_t)0x0000) /*!< PA[9] pin */ +#define AFIO_EXTICR3_EXTI9_PB ((uint16_t)0x0010) /*!< PB[9] pin */ +#define AFIO_EXTICR3_EXTI9_PC ((uint16_t)0x0020) /*!< PC[9] pin */ +#define AFIO_EXTICR3_EXTI9_PD ((uint16_t)0x0030) /*!< PD[9] pin */ +#define AFIO_EXTICR3_EXTI9_PE ((uint16_t)0x0040) /*!< PE[9] pin */ +#define AFIO_EXTICR3_EXTI9_PF ((uint16_t)0x0050) /*!< PF[9] pin */ +#define AFIO_EXTICR3_EXTI9_PG ((uint16_t)0x0060) /*!< PG[9] pin */ + +/*!< EXTI10 configuration */ +#define AFIO_EXTICR3_EXTI10_PA ((uint16_t)0x0000) /*!< PA[10] pin */ +#define AFIO_EXTICR3_EXTI10_PB ((uint16_t)0x0100) /*!< PB[10] pin */ +#define AFIO_EXTICR3_EXTI10_PC ((uint16_t)0x0200) /*!< PC[10] pin */ +#define AFIO_EXTICR3_EXTI10_PD ((uint16_t)0x0300) /*!< PD[10] pin */ +#define AFIO_EXTICR3_EXTI10_PE ((uint16_t)0x0400) /*!< PE[10] pin */ +#define AFIO_EXTICR3_EXTI10_PF ((uint16_t)0x0500) /*!< PF[10] pin */ +#define AFIO_EXTICR3_EXTI10_PG ((uint16_t)0x0600) /*!< PG[10] pin */ + +/*!< EXTI11 configuration */ +#define AFIO_EXTICR3_EXTI11_PA ((uint16_t)0x0000) /*!< PA[11] pin */ +#define AFIO_EXTICR3_EXTI11_PB ((uint16_t)0x1000) /*!< PB[11] pin */ +#define AFIO_EXTICR3_EXTI11_PC ((uint16_t)0x2000) /*!< PC[11] pin */ +#define AFIO_EXTICR3_EXTI11_PD ((uint16_t)0x3000) /*!< PD[11] pin */ +#define AFIO_EXTICR3_EXTI11_PE ((uint16_t)0x4000) /*!< PE[11] pin */ +#define AFIO_EXTICR3_EXTI11_PF ((uint16_t)0x5000) /*!< PF[11] pin */ +#define AFIO_EXTICR3_EXTI11_PG ((uint16_t)0x6000) /*!< PG[11] pin */ + +/***************** Bit definition for AFIO_EXTICR4 register *****************/ +#define AFIO_EXTICR4_EXTI12 ((uint16_t)0x000F) /*!< EXTI 12 configuration */ +#define AFIO_EXTICR4_EXTI13 ((uint16_t)0x00F0) /*!< EXTI 13 configuration */ +#define AFIO_EXTICR4_EXTI14 ((uint16_t)0x0F00) /*!< EXTI 14 configuration */ +#define AFIO_EXTICR4_EXTI15 ((uint16_t)0xF000) /*!< EXTI 15 configuration */ + +/* EXTI12 configuration */ +#define AFIO_EXTICR4_EXTI12_PA ((uint16_t)0x0000) /*!< PA[12] pin */ +#define AFIO_EXTICR4_EXTI12_PB ((uint16_t)0x0001) /*!< PB[12] pin */ +#define AFIO_EXTICR4_EXTI12_PC ((uint16_t)0x0002) /*!< PC[12] pin */ +#define AFIO_EXTICR4_EXTI12_PD ((uint16_t)0x0003) /*!< PD[12] pin */ +#define AFIO_EXTICR4_EXTI12_PE ((uint16_t)0x0004) /*!< PE[12] pin */ +#define AFIO_EXTICR4_EXTI12_PF ((uint16_t)0x0005) /*!< PF[12] pin */ +#define AFIO_EXTICR4_EXTI12_PG ((uint16_t)0x0006) /*!< PG[12] pin */ + +/* EXTI13 configuration */ +#define AFIO_EXTICR4_EXTI13_PA ((uint16_t)0x0000) /*!< PA[13] pin */ +#define AFIO_EXTICR4_EXTI13_PB ((uint16_t)0x0010) /*!< PB[13] pin */ +#define AFIO_EXTICR4_EXTI13_PC ((uint16_t)0x0020) /*!< PC[13] pin */ +#define AFIO_EXTICR4_EXTI13_PD ((uint16_t)0x0030) /*!< PD[13] pin */ +#define AFIO_EXTICR4_EXTI13_PE ((uint16_t)0x0040) /*!< PE[13] pin */ +#define AFIO_EXTICR4_EXTI13_PF ((uint16_t)0x0050) /*!< PF[13] pin */ +#define AFIO_EXTICR4_EXTI13_PG ((uint16_t)0x0060) /*!< PG[13] pin */ + +/*!< EXTI14 configuration */ +#define AFIO_EXTICR4_EXTI14_PA ((uint16_t)0x0000) /*!< PA[14] pin */ +#define AFIO_EXTICR4_EXTI14_PB ((uint16_t)0x0100) /*!< PB[14] pin */ +#define AFIO_EXTICR4_EXTI14_PC ((uint16_t)0x0200) /*!< PC[14] pin */ +#define AFIO_EXTICR4_EXTI14_PD ((uint16_t)0x0300) /*!< PD[14] pin */ +#define AFIO_EXTICR4_EXTI14_PE ((uint16_t)0x0400) /*!< PE[14] pin */ +#define AFIO_EXTICR4_EXTI14_PF ((uint16_t)0x0500) /*!< PF[14] pin */ +#define AFIO_EXTICR4_EXTI14_PG ((uint16_t)0x0600) /*!< PG[14] pin */ + +/*!< EXTI15 configuration */ +#define AFIO_EXTICR4_EXTI15_PA ((uint16_t)0x0000) /*!< PA[15] pin */ +#define AFIO_EXTICR4_EXTI15_PB ((uint16_t)0x1000) /*!< PB[15] pin */ +#define AFIO_EXTICR4_EXTI15_PC ((uint16_t)0x2000) /*!< PC[15] pin */ +#define AFIO_EXTICR4_EXTI15_PD ((uint16_t)0x3000) /*!< PD[15] pin */ +#define AFIO_EXTICR4_EXTI15_PE ((uint16_t)0x4000) /*!< PE[15] pin */ +#define AFIO_EXTICR4_EXTI15_PF ((uint16_t)0x5000) /*!< PF[15] pin */ +#define AFIO_EXTICR4_EXTI15_PG ((uint16_t)0x6000) /*!< PG[15] pin */ + +#if defined (STM32F10X_LD_VL) || defined (STM32F10X_MD_VL) || defined (STM32F10X_HD_VL) +/****************** Bit definition for AFIO_MAPR2 register ******************/ +#define AFIO_MAPR2_TIM15_REMAP ((uint32_t)0x00000001) /*!< TIM15 remapping */ +#define AFIO_MAPR2_TIM16_REMAP ((uint32_t)0x00000002) /*!< TIM16 remapping */ +#define AFIO_MAPR2_TIM17_REMAP ((uint32_t)0x00000004) /*!< TIM17 remapping */ +#define AFIO_MAPR2_CEC_REMAP ((uint32_t)0x00000008) /*!< CEC remapping */ +#define AFIO_MAPR2_TIM1_DMA_REMAP ((uint32_t)0x00000010) /*!< TIM1_DMA remapping */ +#endif + +#ifdef STM32F10X_HD_VL +#define AFIO_MAPR2_TIM13_REMAP ((uint32_t)0x00000100) /*!< TIM13 remapping */ +#define AFIO_MAPR2_TIM14_REMAP ((uint32_t)0x00000200) /*!< TIM14 remapping */ +#define AFIO_MAPR2_FSMC_NADV_REMAP ((uint32_t)0x00000400) /*!< FSMC NADV remapping */ +#define AFIO_MAPR2_TIM67_DAC_DMA_REMAP ((uint32_t)0x00000800) /*!< TIM6/TIM7 and DAC DMA remapping */ +#define AFIO_MAPR2_TIM12_REMAP ((uint32_t)0x00001000) /*!< TIM12 remapping */ +#define AFIO_MAPR2_MISC_REMAP ((uint32_t)0x00002000) /*!< Miscellaneous remapping */ +#endif + +#ifdef STM32F10X_XL +/****************** Bit definition for AFIO_MAPR2 register ******************/ +#define AFIO_MAPR2_TIM9_REMAP ((uint32_t)0x00000020) /*!< TIM9 remapping */ +#define AFIO_MAPR2_TIM10_REMAP ((uint32_t)0x00000040) /*!< TIM10 remapping */ +#define AFIO_MAPR2_TIM11_REMAP ((uint32_t)0x00000080) /*!< TIM11 remapping */ +#define AFIO_MAPR2_TIM13_REMAP ((uint32_t)0x00000100) /*!< TIM13 remapping */ +#define AFIO_MAPR2_TIM14_REMAP ((uint32_t)0x00000200) /*!< TIM14 remapping */ +#define AFIO_MAPR2_FSMC_NADV_REMAP ((uint32_t)0x00000400) /*!< FSMC NADV remapping */ +#endif + +/******************************************************************************/ +/* */ +/* SystemTick */ +/* */ +/******************************************************************************/ + +/***************** Bit definition for SysTick_CTRL register *****************/ +#define SysTick_CTRL_ENABLE ((uint32_t)0x00000001) /*!< Counter enable */ +#define SysTick_CTRL_TICKINT ((uint32_t)0x00000002) /*!< Counting down to 0 pends the SysTick handler */ +#define SysTick_CTRL_CLKSOURCE ((uint32_t)0x00000004) /*!< Clock source */ +#define SysTick_CTRL_COUNTFLAG ((uint32_t)0x00010000) /*!< Count Flag */ + +/***************** Bit definition for SysTick_LOAD register *****************/ +#define SysTick_LOAD_RELOAD ((uint32_t)0x00FFFFFF) /*!< Value to load into the SysTick Current Value Register when the counter reaches 0 */ + +/***************** Bit definition for SysTick_VAL register ******************/ +#define SysTick_VAL_CURRENT ((uint32_t)0x00FFFFFF) /*!< Current value at the time the register is accessed */ + +/***************** Bit definition for SysTick_CALIB register ****************/ +#define SysTick_CALIB_TENMS ((uint32_t)0x00FFFFFF) /*!< Reload value to use for 10ms timing */ +#define SysTick_CALIB_SKEW ((uint32_t)0x40000000) /*!< Calibration value is not exactly 10 ms */ +#define SysTick_CALIB_NOREF ((uint32_t)0x80000000) /*!< The reference clock is not provided */ + +/******************************************************************************/ +/* */ +/* Nested Vectored Interrupt Controller */ +/* */ +/******************************************************************************/ + +/****************** Bit definition for NVIC_ISER register *******************/ +#define NVIC_ISER_SETENA ((uint32_t)0xFFFFFFFF) /*!< Interrupt set enable bits */ +#define NVIC_ISER_SETENA_0 ((uint32_t)0x00000001) /*!< bit 0 */ +#define NVIC_ISER_SETENA_1 ((uint32_t)0x00000002) /*!< bit 1 */ +#define NVIC_ISER_SETENA_2 ((uint32_t)0x00000004) /*!< bit 2 */ +#define NVIC_ISER_SETENA_3 ((uint32_t)0x00000008) /*!< bit 3 */ +#define NVIC_ISER_SETENA_4 ((uint32_t)0x00000010) /*!< bit 4 */ +#define NVIC_ISER_SETENA_5 ((uint32_t)0x00000020) /*!< bit 5 */ +#define NVIC_ISER_SETENA_6 ((uint32_t)0x00000040) /*!< bit 6 */ +#define NVIC_ISER_SETENA_7 ((uint32_t)0x00000080) /*!< bit 7 */ +#define NVIC_ISER_SETENA_8 ((uint32_t)0x00000100) /*!< bit 8 */ +#define NVIC_ISER_SETENA_9 ((uint32_t)0x00000200) /*!< bit 9 */ +#define NVIC_ISER_SETENA_10 ((uint32_t)0x00000400) /*!< bit 10 */ +#define NVIC_ISER_SETENA_11 ((uint32_t)0x00000800) /*!< bit 11 */ +#define NVIC_ISER_SETENA_12 ((uint32_t)0x00001000) /*!< bit 12 */ +#define NVIC_ISER_SETENA_13 ((uint32_t)0x00002000) /*!< bit 13 */ +#define NVIC_ISER_SETENA_14 ((uint32_t)0x00004000) /*!< bit 14 */ +#define NVIC_ISER_SETENA_15 ((uint32_t)0x00008000) /*!< bit 15 */ +#define NVIC_ISER_SETENA_16 ((uint32_t)0x00010000) /*!< bit 16 */ +#define NVIC_ISER_SETENA_17 ((uint32_t)0x00020000) /*!< bit 17 */ +#define NVIC_ISER_SETENA_18 ((uint32_t)0x00040000) /*!< bit 18 */ +#define NVIC_ISER_SETENA_19 ((uint32_t)0x00080000) /*!< bit 19 */ +#define NVIC_ISER_SETENA_20 ((uint32_t)0x00100000) /*!< bit 20 */ +#define NVIC_ISER_SETENA_21 ((uint32_t)0x00200000) /*!< bit 21 */ +#define NVIC_ISER_SETENA_22 ((uint32_t)0x00400000) /*!< bit 22 */ +#define NVIC_ISER_SETENA_23 ((uint32_t)0x00800000) /*!< bit 23 */ +#define NVIC_ISER_SETENA_24 ((uint32_t)0x01000000) /*!< bit 24 */ +#define NVIC_ISER_SETENA_25 ((uint32_t)0x02000000) /*!< bit 25 */ +#define NVIC_ISER_SETENA_26 ((uint32_t)0x04000000) /*!< bit 26 */ +#define NVIC_ISER_SETENA_27 ((uint32_t)0x08000000) /*!< bit 27 */ +#define NVIC_ISER_SETENA_28 ((uint32_t)0x10000000) /*!< bit 28 */ +#define NVIC_ISER_SETENA_29 ((uint32_t)0x20000000) /*!< bit 29 */ +#define NVIC_ISER_SETENA_30 ((uint32_t)0x40000000) /*!< bit 30 */ +#define NVIC_ISER_SETENA_31 ((uint32_t)0x80000000) /*!< bit 31 */ + +/****************** Bit definition for NVIC_ICER register *******************/ +#define NVIC_ICER_CLRENA ((uint32_t)0xFFFFFFFF) /*!< Interrupt clear-enable bits */ +#define NVIC_ICER_CLRENA_0 ((uint32_t)0x00000001) /*!< bit 0 */ +#define NVIC_ICER_CLRENA_1 ((uint32_t)0x00000002) /*!< bit 1 */ +#define NVIC_ICER_CLRENA_2 ((uint32_t)0x00000004) /*!< bit 2 */ +#define NVIC_ICER_CLRENA_3 ((uint32_t)0x00000008) /*!< bit 3 */ +#define NVIC_ICER_CLRENA_4 ((uint32_t)0x00000010) /*!< bit 4 */ +#define NVIC_ICER_CLRENA_5 ((uint32_t)0x00000020) /*!< bit 5 */ +#define NVIC_ICER_CLRENA_6 ((uint32_t)0x00000040) /*!< bit 6 */ +#define NVIC_ICER_CLRENA_7 ((uint32_t)0x00000080) /*!< bit 7 */ +#define NVIC_ICER_CLRENA_8 ((uint32_t)0x00000100) /*!< bit 8 */ +#define NVIC_ICER_CLRENA_9 ((uint32_t)0x00000200) /*!< bit 9 */ +#define NVIC_ICER_CLRENA_10 ((uint32_t)0x00000400) /*!< bit 10 */ +#define NVIC_ICER_CLRENA_11 ((uint32_t)0x00000800) /*!< bit 11 */ +#define NVIC_ICER_CLRENA_12 ((uint32_t)0x00001000) /*!< bit 12 */ +#define NVIC_ICER_CLRENA_13 ((uint32_t)0x00002000) /*!< bit 13 */ +#define NVIC_ICER_CLRENA_14 ((uint32_t)0x00004000) /*!< bit 14 */ +#define NVIC_ICER_CLRENA_15 ((uint32_t)0x00008000) /*!< bit 15 */ +#define NVIC_ICER_CLRENA_16 ((uint32_t)0x00010000) /*!< bit 16 */ +#define NVIC_ICER_CLRENA_17 ((uint32_t)0x00020000) /*!< bit 17 */ +#define NVIC_ICER_CLRENA_18 ((uint32_t)0x00040000) /*!< bit 18 */ +#define NVIC_ICER_CLRENA_19 ((uint32_t)0x00080000) /*!< bit 19 */ +#define NVIC_ICER_CLRENA_20 ((uint32_t)0x00100000) /*!< bit 20 */ +#define NVIC_ICER_CLRENA_21 ((uint32_t)0x00200000) /*!< bit 21 */ +#define NVIC_ICER_CLRENA_22 ((uint32_t)0x00400000) /*!< bit 22 */ +#define NVIC_ICER_CLRENA_23 ((uint32_t)0x00800000) /*!< bit 23 */ +#define NVIC_ICER_CLRENA_24 ((uint32_t)0x01000000) /*!< bit 24 */ +#define NVIC_ICER_CLRENA_25 ((uint32_t)0x02000000) /*!< bit 25 */ +#define NVIC_ICER_CLRENA_26 ((uint32_t)0x04000000) /*!< bit 26 */ +#define NVIC_ICER_CLRENA_27 ((uint32_t)0x08000000) /*!< bit 27 */ +#define NVIC_ICER_CLRENA_28 ((uint32_t)0x10000000) /*!< bit 28 */ +#define NVIC_ICER_CLRENA_29 ((uint32_t)0x20000000) /*!< bit 29 */ +#define NVIC_ICER_CLRENA_30 ((uint32_t)0x40000000) /*!< bit 30 */ +#define NVIC_ICER_CLRENA_31 ((uint32_t)0x80000000) /*!< bit 31 */ + +/****************** Bit definition for NVIC_ISPR register *******************/ +#define NVIC_ISPR_SETPEND ((uint32_t)0xFFFFFFFF) /*!< Interrupt set-pending bits */ +#define NVIC_ISPR_SETPEND_0 ((uint32_t)0x00000001) /*!< bit 0 */ +#define NVIC_ISPR_SETPEND_1 ((uint32_t)0x00000002) /*!< bit 1 */ +#define NVIC_ISPR_SETPEND_2 ((uint32_t)0x00000004) /*!< bit 2 */ +#define NVIC_ISPR_SETPEND_3 ((uint32_t)0x00000008) /*!< bit 3 */ +#define NVIC_ISPR_SETPEND_4 ((uint32_t)0x00000010) /*!< bit 4 */ +#define NVIC_ISPR_SETPEND_5 ((uint32_t)0x00000020) /*!< bit 5 */ +#define NVIC_ISPR_SETPEND_6 ((uint32_t)0x00000040) /*!< bit 6 */ +#define NVIC_ISPR_SETPEND_7 ((uint32_t)0x00000080) /*!< bit 7 */ +#define NVIC_ISPR_SETPEND_8 ((uint32_t)0x00000100) /*!< bit 8 */ +#define NVIC_ISPR_SETPEND_9 ((uint32_t)0x00000200) /*!< bit 9 */ +#define NVIC_ISPR_SETPEND_10 ((uint32_t)0x00000400) /*!< bit 10 */ +#define NVIC_ISPR_SETPEND_11 ((uint32_t)0x00000800) /*!< bit 11 */ +#define NVIC_ISPR_SETPEND_12 ((uint32_t)0x00001000) /*!< bit 12 */ +#define NVIC_ISPR_SETPEND_13 ((uint32_t)0x00002000) /*!< bit 13 */ +#define NVIC_ISPR_SETPEND_14 ((uint32_t)0x00004000) /*!< bit 14 */ +#define NVIC_ISPR_SETPEND_15 ((uint32_t)0x00008000) /*!< bit 15 */ +#define NVIC_ISPR_SETPEND_16 ((uint32_t)0x00010000) /*!< bit 16 */ +#define NVIC_ISPR_SETPEND_17 ((uint32_t)0x00020000) /*!< bit 17 */ +#define NVIC_ISPR_SETPEND_18 ((uint32_t)0x00040000) /*!< bit 18 */ +#define NVIC_ISPR_SETPEND_19 ((uint32_t)0x00080000) /*!< bit 19 */ +#define NVIC_ISPR_SETPEND_20 ((uint32_t)0x00100000) /*!< bit 20 */ +#define NVIC_ISPR_SETPEND_21 ((uint32_t)0x00200000) /*!< bit 21 */ +#define NVIC_ISPR_SETPEND_22 ((uint32_t)0x00400000) /*!< bit 22 */ +#define NVIC_ISPR_SETPEND_23 ((uint32_t)0x00800000) /*!< bit 23 */ +#define NVIC_ISPR_SETPEND_24 ((uint32_t)0x01000000) /*!< bit 24 */ +#define NVIC_ISPR_SETPEND_25 ((uint32_t)0x02000000) /*!< bit 25 */ +#define NVIC_ISPR_SETPEND_26 ((uint32_t)0x04000000) /*!< bit 26 */ +#define NVIC_ISPR_SETPEND_27 ((uint32_t)0x08000000) /*!< bit 27 */ +#define NVIC_ISPR_SETPEND_28 ((uint32_t)0x10000000) /*!< bit 28 */ +#define NVIC_ISPR_SETPEND_29 ((uint32_t)0x20000000) /*!< bit 29 */ +#define NVIC_ISPR_SETPEND_30 ((uint32_t)0x40000000) /*!< bit 30 */ +#define NVIC_ISPR_SETPEND_31 ((uint32_t)0x80000000) /*!< bit 31 */ + +/****************** Bit definition for NVIC_ICPR register *******************/ +#define NVIC_ICPR_CLRPEND ((uint32_t)0xFFFFFFFF) /*!< Interrupt clear-pending bits */ +#define NVIC_ICPR_CLRPEND_0 ((uint32_t)0x00000001) /*!< bit 0 */ +#define NVIC_ICPR_CLRPEND_1 ((uint32_t)0x00000002) /*!< bit 1 */ +#define NVIC_ICPR_CLRPEND_2 ((uint32_t)0x00000004) /*!< bit 2 */ +#define NVIC_ICPR_CLRPEND_3 ((uint32_t)0x00000008) /*!< bit 3 */ +#define NVIC_ICPR_CLRPEND_4 ((uint32_t)0x00000010) /*!< bit 4 */ +#define NVIC_ICPR_CLRPEND_5 ((uint32_t)0x00000020) /*!< bit 5 */ +#define NVIC_ICPR_CLRPEND_6 ((uint32_t)0x00000040) /*!< bit 6 */ +#define NVIC_ICPR_CLRPEND_7 ((uint32_t)0x00000080) /*!< bit 7 */ +#define NVIC_ICPR_CLRPEND_8 ((uint32_t)0x00000100) /*!< bit 8 */ +#define NVIC_ICPR_CLRPEND_9 ((uint32_t)0x00000200) /*!< bit 9 */ +#define NVIC_ICPR_CLRPEND_10 ((uint32_t)0x00000400) /*!< bit 10 */ +#define NVIC_ICPR_CLRPEND_11 ((uint32_t)0x00000800) /*!< bit 11 */ +#define NVIC_ICPR_CLRPEND_12 ((uint32_t)0x00001000) /*!< bit 12 */ +#define NVIC_ICPR_CLRPEND_13 ((uint32_t)0x00002000) /*!< bit 13 */ +#define NVIC_ICPR_CLRPEND_14 ((uint32_t)0x00004000) /*!< bit 14 */ +#define NVIC_ICPR_CLRPEND_15 ((uint32_t)0x00008000) /*!< bit 15 */ +#define NVIC_ICPR_CLRPEND_16 ((uint32_t)0x00010000) /*!< bit 16 */ +#define NVIC_ICPR_CLRPEND_17 ((uint32_t)0x00020000) /*!< bit 17 */ +#define NVIC_ICPR_CLRPEND_18 ((uint32_t)0x00040000) /*!< bit 18 */ +#define NVIC_ICPR_CLRPEND_19 ((uint32_t)0x00080000) /*!< bit 19 */ +#define NVIC_ICPR_CLRPEND_20 ((uint32_t)0x00100000) /*!< bit 20 */ +#define NVIC_ICPR_CLRPEND_21 ((uint32_t)0x00200000) /*!< bit 21 */ +#define NVIC_ICPR_CLRPEND_22 ((uint32_t)0x00400000) /*!< bit 22 */ +#define NVIC_ICPR_CLRPEND_23 ((uint32_t)0x00800000) /*!< bit 23 */ +#define NVIC_ICPR_CLRPEND_24 ((uint32_t)0x01000000) /*!< bit 24 */ +#define NVIC_ICPR_CLRPEND_25 ((uint32_t)0x02000000) /*!< bit 25 */ +#define NVIC_ICPR_CLRPEND_26 ((uint32_t)0x04000000) /*!< bit 26 */ +#define NVIC_ICPR_CLRPEND_27 ((uint32_t)0x08000000) /*!< bit 27 */ +#define NVIC_ICPR_CLRPEND_28 ((uint32_t)0x10000000) /*!< bit 28 */ +#define NVIC_ICPR_CLRPEND_29 ((uint32_t)0x20000000) /*!< bit 29 */ +#define NVIC_ICPR_CLRPEND_30 ((uint32_t)0x40000000) /*!< bit 30 */ +#define NVIC_ICPR_CLRPEND_31 ((uint32_t)0x80000000) /*!< bit 31 */ + +/****************** Bit definition for NVIC_IABR register *******************/ +#define NVIC_IABR_ACTIVE ((uint32_t)0xFFFFFFFF) /*!< Interrupt active flags */ +#define NVIC_IABR_ACTIVE_0 ((uint32_t)0x00000001) /*!< bit 0 */ +#define NVIC_IABR_ACTIVE_1 ((uint32_t)0x00000002) /*!< bit 1 */ +#define NVIC_IABR_ACTIVE_2 ((uint32_t)0x00000004) /*!< bit 2 */ +#define NVIC_IABR_ACTIVE_3 ((uint32_t)0x00000008) /*!< bit 3 */ +#define NVIC_IABR_ACTIVE_4 ((uint32_t)0x00000010) /*!< bit 4 */ +#define NVIC_IABR_ACTIVE_5 ((uint32_t)0x00000020) /*!< bit 5 */ +#define NVIC_IABR_ACTIVE_6 ((uint32_t)0x00000040) /*!< bit 6 */ +#define NVIC_IABR_ACTIVE_7 ((uint32_t)0x00000080) /*!< bit 7 */ +#define NVIC_IABR_ACTIVE_8 ((uint32_t)0x00000100) /*!< bit 8 */ +#define NVIC_IABR_ACTIVE_9 ((uint32_t)0x00000200) /*!< bit 9 */ +#define NVIC_IABR_ACTIVE_10 ((uint32_t)0x00000400) /*!< bit 10 */ +#define NVIC_IABR_ACTIVE_11 ((uint32_t)0x00000800) /*!< bit 11 */ +#define NVIC_IABR_ACTIVE_12 ((uint32_t)0x00001000) /*!< bit 12 */ +#define NVIC_IABR_ACTIVE_13 ((uint32_t)0x00002000) /*!< bit 13 */ +#define NVIC_IABR_ACTIVE_14 ((uint32_t)0x00004000) /*!< bit 14 */ +#define NVIC_IABR_ACTIVE_15 ((uint32_t)0x00008000) /*!< bit 15 */ +#define NVIC_IABR_ACTIVE_16 ((uint32_t)0x00010000) /*!< bit 16 */ +#define NVIC_IABR_ACTIVE_17 ((uint32_t)0x00020000) /*!< bit 17 */ +#define NVIC_IABR_ACTIVE_18 ((uint32_t)0x00040000) /*!< bit 18 */ +#define NVIC_IABR_ACTIVE_19 ((uint32_t)0x00080000) /*!< bit 19 */ +#define NVIC_IABR_ACTIVE_20 ((uint32_t)0x00100000) /*!< bit 20 */ +#define NVIC_IABR_ACTIVE_21 ((uint32_t)0x00200000) /*!< bit 21 */ +#define NVIC_IABR_ACTIVE_22 ((uint32_t)0x00400000) /*!< bit 22 */ +#define NVIC_IABR_ACTIVE_23 ((uint32_t)0x00800000) /*!< bit 23 */ +#define NVIC_IABR_ACTIVE_24 ((uint32_t)0x01000000) /*!< bit 24 */ +#define NVIC_IABR_ACTIVE_25 ((uint32_t)0x02000000) /*!< bit 25 */ +#define NVIC_IABR_ACTIVE_26 ((uint32_t)0x04000000) /*!< bit 26 */ +#define NVIC_IABR_ACTIVE_27 ((uint32_t)0x08000000) /*!< bit 27 */ +#define NVIC_IABR_ACTIVE_28 ((uint32_t)0x10000000) /*!< bit 28 */ +#define NVIC_IABR_ACTIVE_29 ((uint32_t)0x20000000) /*!< bit 29 */ +#define NVIC_IABR_ACTIVE_30 ((uint32_t)0x40000000) /*!< bit 30 */ +#define NVIC_IABR_ACTIVE_31 ((uint32_t)0x80000000) /*!< bit 31 */ + +/****************** Bit definition for NVIC_PRI0 register *******************/ +#define NVIC_IPR0_PRI_0 ((uint32_t)0x000000FF) /*!< Priority of interrupt 0 */ +#define NVIC_IPR0_PRI_1 ((uint32_t)0x0000FF00) /*!< Priority of interrupt 1 */ +#define NVIC_IPR0_PRI_2 ((uint32_t)0x00FF0000) /*!< Priority of interrupt 2 */ +#define NVIC_IPR0_PRI_3 ((uint32_t)0xFF000000) /*!< Priority of interrupt 3 */ + +/****************** Bit definition for NVIC_PRI1 register *******************/ +#define NVIC_IPR1_PRI_4 ((uint32_t)0x000000FF) /*!< Priority of interrupt 4 */ +#define NVIC_IPR1_PRI_5 ((uint32_t)0x0000FF00) /*!< Priority of interrupt 5 */ +#define NVIC_IPR1_PRI_6 ((uint32_t)0x00FF0000) /*!< Priority of interrupt 6 */ +#define NVIC_IPR1_PRI_7 ((uint32_t)0xFF000000) /*!< Priority of interrupt 7 */ + +/****************** Bit definition for NVIC_PRI2 register *******************/ +#define NVIC_IPR2_PRI_8 ((uint32_t)0x000000FF) /*!< Priority of interrupt 8 */ +#define NVIC_IPR2_PRI_9 ((uint32_t)0x0000FF00) /*!< Priority of interrupt 9 */ +#define NVIC_IPR2_PRI_10 ((uint32_t)0x00FF0000) /*!< Priority of interrupt 10 */ +#define NVIC_IPR2_PRI_11 ((uint32_t)0xFF000000) /*!< Priority of interrupt 11 */ + +/****************** Bit definition for NVIC_PRI3 register *******************/ +#define NVIC_IPR3_PRI_12 ((uint32_t)0x000000FF) /*!< Priority of interrupt 12 */ +#define NVIC_IPR3_PRI_13 ((uint32_t)0x0000FF00) /*!< Priority of interrupt 13 */ +#define NVIC_IPR3_PRI_14 ((uint32_t)0x00FF0000) /*!< Priority of interrupt 14 */ +#define NVIC_IPR3_PRI_15 ((uint32_t)0xFF000000) /*!< Priority of interrupt 15 */ + +/****************** Bit definition for NVIC_PRI4 register *******************/ +#define NVIC_IPR4_PRI_16 ((uint32_t)0x000000FF) /*!< Priority of interrupt 16 */ +#define NVIC_IPR4_PRI_17 ((uint32_t)0x0000FF00) /*!< Priority of interrupt 17 */ +#define NVIC_IPR4_PRI_18 ((uint32_t)0x00FF0000) /*!< Priority of interrupt 18 */ +#define NVIC_IPR4_PRI_19 ((uint32_t)0xFF000000) /*!< Priority of interrupt 19 */ + +/****************** Bit definition for NVIC_PRI5 register *******************/ +#define NVIC_IPR5_PRI_20 ((uint32_t)0x000000FF) /*!< Priority of interrupt 20 */ +#define NVIC_IPR5_PRI_21 ((uint32_t)0x0000FF00) /*!< Priority of interrupt 21 */ +#define NVIC_IPR5_PRI_22 ((uint32_t)0x00FF0000) /*!< Priority of interrupt 22 */ +#define NVIC_IPR5_PRI_23 ((uint32_t)0xFF000000) /*!< Priority of interrupt 23 */ + +/****************** Bit definition for NVIC_PRI6 register *******************/ +#define NVIC_IPR6_PRI_24 ((uint32_t)0x000000FF) /*!< Priority of interrupt 24 */ +#define NVIC_IPR6_PRI_25 ((uint32_t)0x0000FF00) /*!< Priority of interrupt 25 */ +#define NVIC_IPR6_PRI_26 ((uint32_t)0x00FF0000) /*!< Priority of interrupt 26 */ +#define NVIC_IPR6_PRI_27 ((uint32_t)0xFF000000) /*!< Priority of interrupt 27 */ + +/****************** Bit definition for NVIC_PRI7 register *******************/ +#define NVIC_IPR7_PRI_28 ((uint32_t)0x000000FF) /*!< Priority of interrupt 28 */ +#define NVIC_IPR7_PRI_29 ((uint32_t)0x0000FF00) /*!< Priority of interrupt 29 */ +#define NVIC_IPR7_PRI_30 ((uint32_t)0x00FF0000) /*!< Priority of interrupt 30 */ +#define NVIC_IPR7_PRI_31 ((uint32_t)0xFF000000) /*!< Priority of interrupt 31 */ + +/****************** Bit definition for SCB_CPUID register *******************/ +#define SCB_CPUID_REVISION ((uint32_t)0x0000000F) /*!< Implementation defined revision number */ +#define SCB_CPUID_PARTNO ((uint32_t)0x0000FFF0) /*!< Number of processor within family */ +#define SCB_CPUID_Constant ((uint32_t)0x000F0000) /*!< Reads as 0x0F */ +#define SCB_CPUID_VARIANT ((uint32_t)0x00F00000) /*!< Implementation defined variant number */ +#define SCB_CPUID_IMPLEMENTER ((uint32_t)0xFF000000) /*!< Implementer code. ARM is 0x41 */ + +/******************* Bit definition for SCB_ICSR register *******************/ +#define SCB_ICSR_VECTACTIVE ((uint32_t)0x000001FF) /*!< Active ISR number field */ +#define SCB_ICSR_RETTOBASE ((uint32_t)0x00000800) /*!< All active exceptions minus the IPSR_current_exception yields the empty set */ +#define SCB_ICSR_VECTPENDING ((uint32_t)0x003FF000) /*!< Pending ISR number field */ +#define SCB_ICSR_ISRPENDING ((uint32_t)0x00400000) /*!< Interrupt pending flag */ +#define SCB_ICSR_ISRPREEMPT ((uint32_t)0x00800000) /*!< It indicates that a pending interrupt becomes active in the next running cycle */ +#define SCB_ICSR_PENDSTCLR ((uint32_t)0x02000000) /*!< Clear pending SysTick bit */ +#define SCB_ICSR_PENDSTSET ((uint32_t)0x04000000) /*!< Set pending SysTick bit */ +#define SCB_ICSR_PENDSVCLR ((uint32_t)0x08000000) /*!< Clear pending pendSV bit */ +#define SCB_ICSR_PENDSVSET ((uint32_t)0x10000000) /*!< Set pending pendSV bit */ +#define SCB_ICSR_NMIPENDSET ((uint32_t)0x80000000) /*!< Set pending NMI bit */ + +/******************* Bit definition for SCB_VTOR register *******************/ +#define SCB_VTOR_TBLOFF ((uint32_t)0x1FFFFF80) /*!< Vector table base offset field */ +#define SCB_VTOR_TBLBASE ((uint32_t)0x20000000) /*!< Table base in code(0) or RAM(1) */ + +/*!<***************** Bit definition for SCB_AIRCR register *******************/ +#define SCB_AIRCR_VECTRESET ((uint32_t)0x00000001) /*!< System Reset bit */ +#define SCB_AIRCR_VECTCLRACTIVE ((uint32_t)0x00000002) /*!< Clear active vector bit */ +#define SCB_AIRCR_SYSRESETREQ ((uint32_t)0x00000004) /*!< Requests chip control logic to generate a reset */ + +#define SCB_AIRCR_PRIGROUP ((uint32_t)0x00000700) /*!< PRIGROUP[2:0] bits (Priority group) */ +#define SCB_AIRCR_PRIGROUP_0 ((uint32_t)0x00000100) /*!< Bit 0 */ +#define SCB_AIRCR_PRIGROUP_1 ((uint32_t)0x00000200) /*!< Bit 1 */ +#define SCB_AIRCR_PRIGROUP_2 ((uint32_t)0x00000400) /*!< Bit 2 */ + +/* prority group configuration */ +#define SCB_AIRCR_PRIGROUP0 ((uint32_t)0x00000000) /*!< Priority group=0 (7 bits of pre-emption priority, 1 bit of subpriority) */ +#define SCB_AIRCR_PRIGROUP1 ((uint32_t)0x00000100) /*!< Priority group=1 (6 bits of pre-emption priority, 2 bits of subpriority) */ +#define SCB_AIRCR_PRIGROUP2 ((uint32_t)0x00000200) /*!< Priority group=2 (5 bits of pre-emption priority, 3 bits of subpriority) */ +#define SCB_AIRCR_PRIGROUP3 ((uint32_t)0x00000300) /*!< Priority group=3 (4 bits of pre-emption priority, 4 bits of subpriority) */ +#define SCB_AIRCR_PRIGROUP4 ((uint32_t)0x00000400) /*!< Priority group=4 (3 bits of pre-emption priority, 5 bits of subpriority) */ +#define SCB_AIRCR_PRIGROUP5 ((uint32_t)0x00000500) /*!< Priority group=5 (2 bits of pre-emption priority, 6 bits of subpriority) */ +#define SCB_AIRCR_PRIGROUP6 ((uint32_t)0x00000600) /*!< Priority group=6 (1 bit of pre-emption priority, 7 bits of subpriority) */ +#define SCB_AIRCR_PRIGROUP7 ((uint32_t)0x00000700) /*!< Priority group=7 (no pre-emption priority, 8 bits of subpriority) */ + +#define SCB_AIRCR_ENDIANESS ((uint32_t)0x00008000) /*!< Data endianness bit */ +#define SCB_AIRCR_VECTKEY ((uint32_t)0xFFFF0000) /*!< Register key (VECTKEY) - Reads as 0xFA05 (VECTKEYSTAT) */ + +/******************* Bit definition for SCB_SCR register ********************/ +#define SCB_SCR_SLEEPONEXIT ((uint8_t)0x02) /*!< Sleep on exit bit */ +#define SCB_SCR_SLEEPDEEP ((uint8_t)0x04) /*!< Sleep deep bit */ +#define SCB_SCR_SEVONPEND ((uint8_t)0x10) /*!< Wake up from WFE */ + +/******************** Bit definition for SCB_CCR register *******************/ +#define SCB_CCR_NONBASETHRDENA ((uint16_t)0x0001) /*!< Thread mode can be entered from any level in Handler mode by controlled return value */ +#define SCB_CCR_USERSETMPEND ((uint16_t)0x0002) /*!< Enables user code to write the Software Trigger Interrupt register to trigger (pend) a Main exception */ +#define SCB_CCR_UNALIGN_TRP ((uint16_t)0x0008) /*!< Trap for unaligned access */ +#define SCB_CCR_DIV_0_TRP ((uint16_t)0x0010) /*!< Trap on Divide by 0 */ +#define SCB_CCR_BFHFNMIGN ((uint16_t)0x0100) /*!< Handlers running at priority -1 and -2 */ +#define SCB_CCR_STKALIGN ((uint16_t)0x0200) /*!< On exception entry, the SP used prior to the exception is adjusted to be 8-byte aligned */ + +/******************* Bit definition for SCB_SHPR register ********************/ +#define SCB_SHPR_PRI_N ((uint32_t)0x000000FF) /*!< Priority of system handler 4,8, and 12. Mem Manage, reserved and Debug Monitor */ +#define SCB_SHPR_PRI_N1 ((uint32_t)0x0000FF00) /*!< Priority of system handler 5,9, and 13. Bus Fault, reserved and reserved */ +#define SCB_SHPR_PRI_N2 ((uint32_t)0x00FF0000) /*!< Priority of system handler 6,10, and 14. Usage Fault, reserved and PendSV */ +#define SCB_SHPR_PRI_N3 ((uint32_t)0xFF000000) /*!< Priority of system handler 7,11, and 15. Reserved, SVCall and SysTick */ + +/****************** Bit definition for SCB_SHCSR register *******************/ +#define SCB_SHCSR_MEMFAULTACT ((uint32_t)0x00000001) /*!< MemManage is active */ +#define SCB_SHCSR_BUSFAULTACT ((uint32_t)0x00000002) /*!< BusFault is active */ +#define SCB_SHCSR_USGFAULTACT ((uint32_t)0x00000008) /*!< UsageFault is active */ +#define SCB_SHCSR_SVCALLACT ((uint32_t)0x00000080) /*!< SVCall is active */ +#define SCB_SHCSR_MONITORACT ((uint32_t)0x00000100) /*!< Monitor is active */ +#define SCB_SHCSR_PENDSVACT ((uint32_t)0x00000400) /*!< PendSV is active */ +#define SCB_SHCSR_SYSTICKACT ((uint32_t)0x00000800) /*!< SysTick is active */ +#define SCB_SHCSR_USGFAULTPENDED ((uint32_t)0x00001000) /*!< Usage Fault is pended */ +#define SCB_SHCSR_MEMFAULTPENDED ((uint32_t)0x00002000) /*!< MemManage is pended */ +#define SCB_SHCSR_BUSFAULTPENDED ((uint32_t)0x00004000) /*!< Bus Fault is pended */ +#define SCB_SHCSR_SVCALLPENDED ((uint32_t)0x00008000) /*!< SVCall is pended */ +#define SCB_SHCSR_MEMFAULTENA ((uint32_t)0x00010000) /*!< MemManage enable */ +#define SCB_SHCSR_BUSFAULTENA ((uint32_t)0x00020000) /*!< Bus Fault enable */ +#define SCB_SHCSR_USGFAULTENA ((uint32_t)0x00040000) /*!< UsageFault enable */ + +/******************* Bit definition for SCB_CFSR register *******************/ +/*!< MFSR */ +#define SCB_CFSR_IACCVIOL ((uint32_t)0x00000001) /*!< Instruction access violation */ +#define SCB_CFSR_DACCVIOL ((uint32_t)0x00000002) /*!< Data access violation */ +#define SCB_CFSR_MUNSTKERR ((uint32_t)0x00000008) /*!< Unstacking error */ +#define SCB_CFSR_MSTKERR ((uint32_t)0x00000010) /*!< Stacking error */ +#define SCB_CFSR_MMARVALID ((uint32_t)0x00000080) /*!< Memory Manage Address Register address valid flag */ +/*!< BFSR */ +#define SCB_CFSR_IBUSERR ((uint32_t)0x00000100) /*!< Instruction bus error flag */ +#define SCB_CFSR_PRECISERR ((uint32_t)0x00000200) /*!< Precise data bus error */ +#define SCB_CFSR_IMPRECISERR ((uint32_t)0x00000400) /*!< Imprecise data bus error */ +#define SCB_CFSR_UNSTKERR ((uint32_t)0x00000800) /*!< Unstacking error */ +#define SCB_CFSR_STKERR ((uint32_t)0x00001000) /*!< Stacking error */ +#define SCB_CFSR_BFARVALID ((uint32_t)0x00008000) /*!< Bus Fault Address Register address valid flag */ +/*!< UFSR */ +#define SCB_CFSR_UNDEFINSTR ((uint32_t)0x00010000) /*!< The processor attempt to execute an undefined instruction */ +#define SCB_CFSR_INVSTATE ((uint32_t)0x00020000) /*!< Invalid combination of EPSR and instruction */ +#define SCB_CFSR_INVPC ((uint32_t)0x00040000) /*!< Attempt to load EXC_RETURN into pc illegally */ +#define SCB_CFSR_NOCP ((uint32_t)0x00080000) /*!< Attempt to use a coprocessor instruction */ +#define SCB_CFSR_UNALIGNED ((uint32_t)0x01000000) /*!< Fault occurs when there is an attempt to make an unaligned memory access */ +#define SCB_CFSR_DIVBYZERO ((uint32_t)0x02000000) /*!< Fault occurs when SDIV or DIV instruction is used with a divisor of 0 */ + +/******************* Bit definition for SCB_HFSR register *******************/ +#define SCB_HFSR_VECTTBL ((uint32_t)0x00000002) /*!< Fault occurs because of vector table read on exception processing */ +#define SCB_HFSR_FORCED ((uint32_t)0x40000000) /*!< Hard Fault activated when a configurable Fault was received and cannot activate */ +#define SCB_HFSR_DEBUGEVT ((uint32_t)0x80000000) /*!< Fault related to debug */ + +/******************* Bit definition for SCB_DFSR register *******************/ +#define SCB_DFSR_HALTED ((uint8_t)0x01) /*!< Halt request flag */ +#define SCB_DFSR_BKPT ((uint8_t)0x02) /*!< BKPT flag */ +#define SCB_DFSR_DWTTRAP ((uint8_t)0x04) /*!< Data Watchpoint and Trace (DWT) flag */ +#define SCB_DFSR_VCATCH ((uint8_t)0x08) /*!< Vector catch flag */ +#define SCB_DFSR_EXTERNAL ((uint8_t)0x10) /*!< External debug request flag */ + +/******************* Bit definition for SCB_MMFAR register ******************/ +#define SCB_MMFAR_ADDRESS ((uint32_t)0xFFFFFFFF) /*!< Mem Manage fault address field */ + +/******************* Bit definition for SCB_BFAR register *******************/ +#define SCB_BFAR_ADDRESS ((uint32_t)0xFFFFFFFF) /*!< Bus fault address field */ + +/******************* Bit definition for SCB_afsr register *******************/ +#define SCB_AFSR_IMPDEF ((uint32_t)0xFFFFFFFF) /*!< Implementation defined */ + +/******************************************************************************/ +/* */ +/* External Interrupt/Event Controller */ +/* */ +/******************************************************************************/ + +/******************* Bit definition for EXTI_IMR register *******************/ +#define EXTI_IMR_MR0 ((uint32_t)0x00000001) /*!< Interrupt Mask on line 0 */ +#define EXTI_IMR_MR1 ((uint32_t)0x00000002) /*!< Interrupt Mask on line 1 */ +#define EXTI_IMR_MR2 ((uint32_t)0x00000004) /*!< Interrupt Mask on line 2 */ +#define EXTI_IMR_MR3 ((uint32_t)0x00000008) /*!< Interrupt Mask on line 3 */ +#define EXTI_IMR_MR4 ((uint32_t)0x00000010) /*!< Interrupt Mask on line 4 */ +#define EXTI_IMR_MR5 ((uint32_t)0x00000020) /*!< Interrupt Mask on line 5 */ +#define EXTI_IMR_MR6 ((uint32_t)0x00000040) /*!< Interrupt Mask on line 6 */ +#define EXTI_IMR_MR7 ((uint32_t)0x00000080) /*!< Interrupt Mask on line 7 */ +#define EXTI_IMR_MR8 ((uint32_t)0x00000100) /*!< Interrupt Mask on line 8 */ +#define EXTI_IMR_MR9 ((uint32_t)0x00000200) /*!< Interrupt Mask on line 9 */ +#define EXTI_IMR_MR10 ((uint32_t)0x00000400) /*!< Interrupt Mask on line 10 */ +#define EXTI_IMR_MR11 ((uint32_t)0x00000800) /*!< Interrupt Mask on line 11 */ +#define EXTI_IMR_MR12 ((uint32_t)0x00001000) /*!< Interrupt Mask on line 12 */ +#define EXTI_IMR_MR13 ((uint32_t)0x00002000) /*!< Interrupt Mask on line 13 */ +#define EXTI_IMR_MR14 ((uint32_t)0x00004000) /*!< Interrupt Mask on line 14 */ +#define EXTI_IMR_MR15 ((uint32_t)0x00008000) /*!< Interrupt Mask on line 15 */ +#define EXTI_IMR_MR16 ((uint32_t)0x00010000) /*!< Interrupt Mask on line 16 */ +#define EXTI_IMR_MR17 ((uint32_t)0x00020000) /*!< Interrupt Mask on line 17 */ +#define EXTI_IMR_MR18 ((uint32_t)0x00040000) /*!< Interrupt Mask on line 18 */ +#define EXTI_IMR_MR19 ((uint32_t)0x00080000) /*!< Interrupt Mask on line 19 */ + +/******************* Bit definition for EXTI_EMR register *******************/ +#define EXTI_EMR_MR0 ((uint32_t)0x00000001) /*!< Event Mask on line 0 */ +#define EXTI_EMR_MR1 ((uint32_t)0x00000002) /*!< Event Mask on line 1 */ +#define EXTI_EMR_MR2 ((uint32_t)0x00000004) /*!< Event Mask on line 2 */ +#define EXTI_EMR_MR3 ((uint32_t)0x00000008) /*!< Event Mask on line 3 */ +#define EXTI_EMR_MR4 ((uint32_t)0x00000010) /*!< Event Mask on line 4 */ +#define EXTI_EMR_MR5 ((uint32_t)0x00000020) /*!< Event Mask on line 5 */ +#define EXTI_EMR_MR6 ((uint32_t)0x00000040) /*!< Event Mask on line 6 */ +#define EXTI_EMR_MR7 ((uint32_t)0x00000080) /*!< Event Mask on line 7 */ +#define EXTI_EMR_MR8 ((uint32_t)0x00000100) /*!< Event Mask on line 8 */ +#define EXTI_EMR_MR9 ((uint32_t)0x00000200) /*!< Event Mask on line 9 */ +#define EXTI_EMR_MR10 ((uint32_t)0x00000400) /*!< Event Mask on line 10 */ +#define EXTI_EMR_MR11 ((uint32_t)0x00000800) /*!< Event Mask on line 11 */ +#define EXTI_EMR_MR12 ((uint32_t)0x00001000) /*!< Event Mask on line 12 */ +#define EXTI_EMR_MR13 ((uint32_t)0x00002000) /*!< Event Mask on line 13 */ +#define EXTI_EMR_MR14 ((uint32_t)0x00004000) /*!< Event Mask on line 14 */ +#define EXTI_EMR_MR15 ((uint32_t)0x00008000) /*!< Event Mask on line 15 */ +#define EXTI_EMR_MR16 ((uint32_t)0x00010000) /*!< Event Mask on line 16 */ +#define EXTI_EMR_MR17 ((uint32_t)0x00020000) /*!< Event Mask on line 17 */ +#define EXTI_EMR_MR18 ((uint32_t)0x00040000) /*!< Event Mask on line 18 */ +#define EXTI_EMR_MR19 ((uint32_t)0x00080000) /*!< Event Mask on line 19 */ + +/****************** Bit definition for EXTI_RTSR register *******************/ +#define EXTI_RTSR_TR0 ((uint32_t)0x00000001) /*!< Rising trigger event configuration bit of line 0 */ +#define EXTI_RTSR_TR1 ((uint32_t)0x00000002) /*!< Rising trigger event configuration bit of line 1 */ +#define EXTI_RTSR_TR2 ((uint32_t)0x00000004) /*!< Rising trigger event configuration bit of line 2 */ +#define EXTI_RTSR_TR3 ((uint32_t)0x00000008) /*!< Rising trigger event configuration bit of line 3 */ +#define EXTI_RTSR_TR4 ((uint32_t)0x00000010) /*!< Rising trigger event configuration bit of line 4 */ +#define EXTI_RTSR_TR5 ((uint32_t)0x00000020) /*!< Rising trigger event configuration bit of line 5 */ +#define EXTI_RTSR_TR6 ((uint32_t)0x00000040) /*!< Rising trigger event configuration bit of line 6 */ +#define EXTI_RTSR_TR7 ((uint32_t)0x00000080) /*!< Rising trigger event configuration bit of line 7 */ +#define EXTI_RTSR_TR8 ((uint32_t)0x00000100) /*!< Rising trigger event configuration bit of line 8 */ +#define EXTI_RTSR_TR9 ((uint32_t)0x00000200) /*!< Rising trigger event configuration bit of line 9 */ +#define EXTI_RTSR_TR10 ((uint32_t)0x00000400) /*!< Rising trigger event configuration bit of line 10 */ +#define EXTI_RTSR_TR11 ((uint32_t)0x00000800) /*!< Rising trigger event configuration bit of line 11 */ +#define EXTI_RTSR_TR12 ((uint32_t)0x00001000) /*!< Rising trigger event configuration bit of line 12 */ +#define EXTI_RTSR_TR13 ((uint32_t)0x00002000) /*!< Rising trigger event configuration bit of line 13 */ +#define EXTI_RTSR_TR14 ((uint32_t)0x00004000) /*!< Rising trigger event configuration bit of line 14 */ +#define EXTI_RTSR_TR15 ((uint32_t)0x00008000) /*!< Rising trigger event configuration bit of line 15 */ +#define EXTI_RTSR_TR16 ((uint32_t)0x00010000) /*!< Rising trigger event configuration bit of line 16 */ +#define EXTI_RTSR_TR17 ((uint32_t)0x00020000) /*!< Rising trigger event configuration bit of line 17 */ +#define EXTI_RTSR_TR18 ((uint32_t)0x00040000) /*!< Rising trigger event configuration bit of line 18 */ +#define EXTI_RTSR_TR19 ((uint32_t)0x00080000) /*!< Rising trigger event configuration bit of line 19 */ + +/****************** Bit definition for EXTI_FTSR register *******************/ +#define EXTI_FTSR_TR0 ((uint32_t)0x00000001) /*!< Falling trigger event configuration bit of line 0 */ +#define EXTI_FTSR_TR1 ((uint32_t)0x00000002) /*!< Falling trigger event configuration bit of line 1 */ +#define EXTI_FTSR_TR2 ((uint32_t)0x00000004) /*!< Falling trigger event configuration bit of line 2 */ +#define EXTI_FTSR_TR3 ((uint32_t)0x00000008) /*!< Falling trigger event configuration bit of line 3 */ +#define EXTI_FTSR_TR4 ((uint32_t)0x00000010) /*!< Falling trigger event configuration bit of line 4 */ +#define EXTI_FTSR_TR5 ((uint32_t)0x00000020) /*!< Falling trigger event configuration bit of line 5 */ +#define EXTI_FTSR_TR6 ((uint32_t)0x00000040) /*!< Falling trigger event configuration bit of line 6 */ +#define EXTI_FTSR_TR7 ((uint32_t)0x00000080) /*!< Falling trigger event configuration bit of line 7 */ +#define EXTI_FTSR_TR8 ((uint32_t)0x00000100) /*!< Falling trigger event configuration bit of line 8 */ +#define EXTI_FTSR_TR9 ((uint32_t)0x00000200) /*!< Falling trigger event configuration bit of line 9 */ +#define EXTI_FTSR_TR10 ((uint32_t)0x00000400) /*!< Falling trigger event configuration bit of line 10 */ +#define EXTI_FTSR_TR11 ((uint32_t)0x00000800) /*!< Falling trigger event configuration bit of line 11 */ +#define EXTI_FTSR_TR12 ((uint32_t)0x00001000) /*!< Falling trigger event configuration bit of line 12 */ +#define EXTI_FTSR_TR13 ((uint32_t)0x00002000) /*!< Falling trigger event configuration bit of line 13 */ +#define EXTI_FTSR_TR14 ((uint32_t)0x00004000) /*!< Falling trigger event configuration bit of line 14 */ +#define EXTI_FTSR_TR15 ((uint32_t)0x00008000) /*!< Falling trigger event configuration bit of line 15 */ +#define EXTI_FTSR_TR16 ((uint32_t)0x00010000) /*!< Falling trigger event configuration bit of line 16 */ +#define EXTI_FTSR_TR17 ((uint32_t)0x00020000) /*!< Falling trigger event configuration bit of line 17 */ +#define EXTI_FTSR_TR18 ((uint32_t)0x00040000) /*!< Falling trigger event configuration bit of line 18 */ +#define EXTI_FTSR_TR19 ((uint32_t)0x00080000) /*!< Falling trigger event configuration bit of line 19 */ + +/****************** Bit definition for EXTI_SWIER register ******************/ +#define EXTI_SWIER_SWIER0 ((uint32_t)0x00000001) /*!< Software Interrupt on line 0 */ +#define EXTI_SWIER_SWIER1 ((uint32_t)0x00000002) /*!< Software Interrupt on line 1 */ +#define EXTI_SWIER_SWIER2 ((uint32_t)0x00000004) /*!< Software Interrupt on line 2 */ +#define EXTI_SWIER_SWIER3 ((uint32_t)0x00000008) /*!< Software Interrupt on line 3 */ +#define EXTI_SWIER_SWIER4 ((uint32_t)0x00000010) /*!< Software Interrupt on line 4 */ +#define EXTI_SWIER_SWIER5 ((uint32_t)0x00000020) /*!< Software Interrupt on line 5 */ +#define EXTI_SWIER_SWIER6 ((uint32_t)0x00000040) /*!< Software Interrupt on line 6 */ +#define EXTI_SWIER_SWIER7 ((uint32_t)0x00000080) /*!< Software Interrupt on line 7 */ +#define EXTI_SWIER_SWIER8 ((uint32_t)0x00000100) /*!< Software Interrupt on line 8 */ +#define EXTI_SWIER_SWIER9 ((uint32_t)0x00000200) /*!< Software Interrupt on line 9 */ +#define EXTI_SWIER_SWIER10 ((uint32_t)0x00000400) /*!< Software Interrupt on line 10 */ +#define EXTI_SWIER_SWIER11 ((uint32_t)0x00000800) /*!< Software Interrupt on line 11 */ +#define EXTI_SWIER_SWIER12 ((uint32_t)0x00001000) /*!< Software Interrupt on line 12 */ +#define EXTI_SWIER_SWIER13 ((uint32_t)0x00002000) /*!< Software Interrupt on line 13 */ +#define EXTI_SWIER_SWIER14 ((uint32_t)0x00004000) /*!< Software Interrupt on line 14 */ +#define EXTI_SWIER_SWIER15 ((uint32_t)0x00008000) /*!< Software Interrupt on line 15 */ +#define EXTI_SWIER_SWIER16 ((uint32_t)0x00010000) /*!< Software Interrupt on line 16 */ +#define EXTI_SWIER_SWIER17 ((uint32_t)0x00020000) /*!< Software Interrupt on line 17 */ +#define EXTI_SWIER_SWIER18 ((uint32_t)0x00040000) /*!< Software Interrupt on line 18 */ +#define EXTI_SWIER_SWIER19 ((uint32_t)0x00080000) /*!< Software Interrupt on line 19 */ + +/******************* Bit definition for EXTI_PR register ********************/ +#define EXTI_PR_PR0 ((uint32_t)0x00000001) /*!< Pending bit for line 0 */ +#define EXTI_PR_PR1 ((uint32_t)0x00000002) /*!< Pending bit for line 1 */ +#define EXTI_PR_PR2 ((uint32_t)0x00000004) /*!< Pending bit for line 2 */ +#define EXTI_PR_PR3 ((uint32_t)0x00000008) /*!< Pending bit for line 3 */ +#define EXTI_PR_PR4 ((uint32_t)0x00000010) /*!< Pending bit for line 4 */ +#define EXTI_PR_PR5 ((uint32_t)0x00000020) /*!< Pending bit for line 5 */ +#define EXTI_PR_PR6 ((uint32_t)0x00000040) /*!< Pending bit for line 6 */ +#define EXTI_PR_PR7 ((uint32_t)0x00000080) /*!< Pending bit for line 7 */ +#define EXTI_PR_PR8 ((uint32_t)0x00000100) /*!< Pending bit for line 8 */ +#define EXTI_PR_PR9 ((uint32_t)0x00000200) /*!< Pending bit for line 9 */ +#define EXTI_PR_PR10 ((uint32_t)0x00000400) /*!< Pending bit for line 10 */ +#define EXTI_PR_PR11 ((uint32_t)0x00000800) /*!< Pending bit for line 11 */ +#define EXTI_PR_PR12 ((uint32_t)0x00001000) /*!< Pending bit for line 12 */ +#define EXTI_PR_PR13 ((uint32_t)0x00002000) /*!< Pending bit for line 13 */ +#define EXTI_PR_PR14 ((uint32_t)0x00004000) /*!< Pending bit for line 14 */ +#define EXTI_PR_PR15 ((uint32_t)0x00008000) /*!< Pending bit for line 15 */ +#define EXTI_PR_PR16 ((uint32_t)0x00010000) /*!< Pending bit for line 16 */ +#define EXTI_PR_PR17 ((uint32_t)0x00020000) /*!< Pending bit for line 17 */ +#define EXTI_PR_PR18 ((uint32_t)0x00040000) /*!< Pending bit for line 18 */ +#define EXTI_PR_PR19 ((uint32_t)0x00080000) /*!< Pending bit for line 19 */ + +/******************************************************************************/ +/* */ +/* DMA Controller */ +/* */ +/******************************************************************************/ + +/******************* Bit definition for DMA_ISR register ********************/ +#define DMA_ISR_GIF1 ((uint32_t)0x00000001) /*!< Channel 1 Global interrupt flag */ +#define DMA_ISR_TCIF1 ((uint32_t)0x00000002) /*!< Channel 1 Transfer Complete flag */ +#define DMA_ISR_HTIF1 ((uint32_t)0x00000004) /*!< Channel 1 Half Transfer flag */ +#define DMA_ISR_TEIF1 ((uint32_t)0x00000008) /*!< Channel 1 Transfer Error flag */ +#define DMA_ISR_GIF2 ((uint32_t)0x00000010) /*!< Channel 2 Global interrupt flag */ +#define DMA_ISR_TCIF2 ((uint32_t)0x00000020) /*!< Channel 2 Transfer Complete flag */ +#define DMA_ISR_HTIF2 ((uint32_t)0x00000040) /*!< Channel 2 Half Transfer flag */ +#define DMA_ISR_TEIF2 ((uint32_t)0x00000080) /*!< Channel 2 Transfer Error flag */ +#define DMA_ISR_GIF3 ((uint32_t)0x00000100) /*!< Channel 3 Global interrupt flag */ +#define DMA_ISR_TCIF3 ((uint32_t)0x00000200) /*!< Channel 3 Transfer Complete flag */ +#define DMA_ISR_HTIF3 ((uint32_t)0x00000400) /*!< Channel 3 Half Transfer flag */ +#define DMA_ISR_TEIF3 ((uint32_t)0x00000800) /*!< Channel 3 Transfer Error flag */ +#define DMA_ISR_GIF4 ((uint32_t)0x00001000) /*!< Channel 4 Global interrupt flag */ +#define DMA_ISR_TCIF4 ((uint32_t)0x00002000) /*!< Channel 4 Transfer Complete flag */ +#define DMA_ISR_HTIF4 ((uint32_t)0x00004000) /*!< Channel 4 Half Transfer flag */ +#define DMA_ISR_TEIF4 ((uint32_t)0x00008000) /*!< Channel 4 Transfer Error flag */ +#define DMA_ISR_GIF5 ((uint32_t)0x00010000) /*!< Channel 5 Global interrupt flag */ +#define DMA_ISR_TCIF5 ((uint32_t)0x00020000) /*!< Channel 5 Transfer Complete flag */ +#define DMA_ISR_HTIF5 ((uint32_t)0x00040000) /*!< Channel 5 Half Transfer flag */ +#define DMA_ISR_TEIF5 ((uint32_t)0x00080000) /*!< Channel 5 Transfer Error flag */ +#define DMA_ISR_GIF6 ((uint32_t)0x00100000) /*!< Channel 6 Global interrupt flag */ +#define DMA_ISR_TCIF6 ((uint32_t)0x00200000) /*!< Channel 6 Transfer Complete flag */ +#define DMA_ISR_HTIF6 ((uint32_t)0x00400000) /*!< Channel 6 Half Transfer flag */ +#define DMA_ISR_TEIF6 ((uint32_t)0x00800000) /*!< Channel 6 Transfer Error flag */ +#define DMA_ISR_GIF7 ((uint32_t)0x01000000) /*!< Channel 7 Global interrupt flag */ +#define DMA_ISR_TCIF7 ((uint32_t)0x02000000) /*!< Channel 7 Transfer Complete flag */ +#define DMA_ISR_HTIF7 ((uint32_t)0x04000000) /*!< Channel 7 Half Transfer flag */ +#define DMA_ISR_TEIF7 ((uint32_t)0x08000000) /*!< Channel 7 Transfer Error flag */ + +/******************* Bit definition for DMA_IFCR register *******************/ +#define DMA_IFCR_CGIF1 ((uint32_t)0x00000001) /*!< Channel 1 Global interrupt clear */ +#define DMA_IFCR_CTCIF1 ((uint32_t)0x00000002) /*!< Channel 1 Transfer Complete clear */ +#define DMA_IFCR_CHTIF1 ((uint32_t)0x00000004) /*!< Channel 1 Half Transfer clear */ +#define DMA_IFCR_CTEIF1 ((uint32_t)0x00000008) /*!< Channel 1 Transfer Error clear */ +#define DMA_IFCR_CGIF2 ((uint32_t)0x00000010) /*!< Channel 2 Global interrupt clear */ +#define DMA_IFCR_CTCIF2 ((uint32_t)0x00000020) /*!< Channel 2 Transfer Complete clear */ +#define DMA_IFCR_CHTIF2 ((uint32_t)0x00000040) /*!< Channel 2 Half Transfer clear */ +#define DMA_IFCR_CTEIF2 ((uint32_t)0x00000080) /*!< Channel 2 Transfer Error clear */ +#define DMA_IFCR_CGIF3 ((uint32_t)0x00000100) /*!< Channel 3 Global interrupt clear */ +#define DMA_IFCR_CTCIF3 ((uint32_t)0x00000200) /*!< Channel 3 Transfer Complete clear */ +#define DMA_IFCR_CHTIF3 ((uint32_t)0x00000400) /*!< Channel 3 Half Transfer clear */ +#define DMA_IFCR_CTEIF3 ((uint32_t)0x00000800) /*!< Channel 3 Transfer Error clear */ +#define DMA_IFCR_CGIF4 ((uint32_t)0x00001000) /*!< Channel 4 Global interrupt clear */ +#define DMA_IFCR_CTCIF4 ((uint32_t)0x00002000) /*!< Channel 4 Transfer Complete clear */ +#define DMA_IFCR_CHTIF4 ((uint32_t)0x00004000) /*!< Channel 4 Half Transfer clear */ +#define DMA_IFCR_CTEIF4 ((uint32_t)0x00008000) /*!< Channel 4 Transfer Error clear */ +#define DMA_IFCR_CGIF5 ((uint32_t)0x00010000) /*!< Channel 5 Global interrupt clear */ +#define DMA_IFCR_CTCIF5 ((uint32_t)0x00020000) /*!< Channel 5 Transfer Complete clear */ +#define DMA_IFCR_CHTIF5 ((uint32_t)0x00040000) /*!< Channel 5 Half Transfer clear */ +#define DMA_IFCR_CTEIF5 ((uint32_t)0x00080000) /*!< Channel 5 Transfer Error clear */ +#define DMA_IFCR_CGIF6 ((uint32_t)0x00100000) /*!< Channel 6 Global interrupt clear */ +#define DMA_IFCR_CTCIF6 ((uint32_t)0x00200000) /*!< Channel 6 Transfer Complete clear */ +#define DMA_IFCR_CHTIF6 ((uint32_t)0x00400000) /*!< Channel 6 Half Transfer clear */ +#define DMA_IFCR_CTEIF6 ((uint32_t)0x00800000) /*!< Channel 6 Transfer Error clear */ +#define DMA_IFCR_CGIF7 ((uint32_t)0x01000000) /*!< Channel 7 Global interrupt clear */ +#define DMA_IFCR_CTCIF7 ((uint32_t)0x02000000) /*!< Channel 7 Transfer Complete clear */ +#define DMA_IFCR_CHTIF7 ((uint32_t)0x04000000) /*!< Channel 7 Half Transfer clear */ +#define DMA_IFCR_CTEIF7 ((uint32_t)0x08000000) /*!< Channel 7 Transfer Error clear */ + +/******************* Bit definition for DMA_CCR1 register *******************/ +#define DMA_CCR1_EN ((uint16_t)0x0001) /*!< Channel enable*/ +#define DMA_CCR1_TCIE ((uint16_t)0x0002) /*!< Transfer complete interrupt enable */ +#define DMA_CCR1_HTIE ((uint16_t)0x0004) /*!< Half Transfer interrupt enable */ +#define DMA_CCR1_TEIE ((uint16_t)0x0008) /*!< Transfer error interrupt enable */ +#define DMA_CCR1_DIR ((uint16_t)0x0010) /*!< Data transfer direction */ +#define DMA_CCR1_CIRC ((uint16_t)0x0020) /*!< Circular mode */ +#define DMA_CCR1_PINC ((uint16_t)0x0040) /*!< Peripheral increment mode */ +#define DMA_CCR1_MINC ((uint16_t)0x0080) /*!< Memory increment mode */ + +#define DMA_CCR1_PSIZE ((uint16_t)0x0300) /*!< PSIZE[1:0] bits (Peripheral size) */ +#define DMA_CCR1_PSIZE_0 ((uint16_t)0x0100) /*!< Bit 0 */ +#define DMA_CCR1_PSIZE_1 ((uint16_t)0x0200) /*!< Bit 1 */ + +#define DMA_CCR1_MSIZE ((uint16_t)0x0C00) /*!< MSIZE[1:0] bits (Memory size) */ +#define DMA_CCR1_MSIZE_0 ((uint16_t)0x0400) /*!< Bit 0 */ +#define DMA_CCR1_MSIZE_1 ((uint16_t)0x0800) /*!< Bit 1 */ + +#define DMA_CCR1_PL ((uint16_t)0x3000) /*!< PL[1:0] bits(Channel Priority level) */ +#define DMA_CCR1_PL_0 ((uint16_t)0x1000) /*!< Bit 0 */ +#define DMA_CCR1_PL_1 ((uint16_t)0x2000) /*!< Bit 1 */ + +#define DMA_CCR1_MEM2MEM ((uint16_t)0x4000) /*!< Memory to memory mode */ + +/******************* Bit definition for DMA_CCR2 register *******************/ +#define DMA_CCR2_EN ((uint16_t)0x0001) /*!< Channel enable */ +#define DMA_CCR2_TCIE ((uint16_t)0x0002) /*!< Transfer complete interrupt enable */ +#define DMA_CCR2_HTIE ((uint16_t)0x0004) /*!< Half Transfer interrupt enable */ +#define DMA_CCR2_TEIE ((uint16_t)0x0008) /*!< Transfer error interrupt enable */ +#define DMA_CCR2_DIR ((uint16_t)0x0010) /*!< Data transfer direction */ +#define DMA_CCR2_CIRC ((uint16_t)0x0020) /*!< Circular mode */ +#define DMA_CCR2_PINC ((uint16_t)0x0040) /*!< Peripheral increment mode */ +#define DMA_CCR2_MINC ((uint16_t)0x0080) /*!< Memory increment mode */ + +#define DMA_CCR2_PSIZE ((uint16_t)0x0300) /*!< PSIZE[1:0] bits (Peripheral size) */ +#define DMA_CCR2_PSIZE_0 ((uint16_t)0x0100) /*!< Bit 0 */ +#define DMA_CCR2_PSIZE_1 ((uint16_t)0x0200) /*!< Bit 1 */ + +#define DMA_CCR2_MSIZE ((uint16_t)0x0C00) /*!< MSIZE[1:0] bits (Memory size) */ +#define DMA_CCR2_MSIZE_0 ((uint16_t)0x0400) /*!< Bit 0 */ +#define DMA_CCR2_MSIZE_1 ((uint16_t)0x0800) /*!< Bit 1 */ + +#define DMA_CCR2_PL ((uint16_t)0x3000) /*!< PL[1:0] bits (Channel Priority level) */ +#define DMA_CCR2_PL_0 ((uint16_t)0x1000) /*!< Bit 0 */ +#define DMA_CCR2_PL_1 ((uint16_t)0x2000) /*!< Bit 1 */ + +#define DMA_CCR2_MEM2MEM ((uint16_t)0x4000) /*!< Memory to memory mode */ + +/******************* Bit definition for DMA_CCR3 register *******************/ +#define DMA_CCR3_EN ((uint16_t)0x0001) /*!< Channel enable */ +#define DMA_CCR3_TCIE ((uint16_t)0x0002) /*!< Transfer complete interrupt enable */ +#define DMA_CCR3_HTIE ((uint16_t)0x0004) /*!< Half Transfer interrupt enable */ +#define DMA_CCR3_TEIE ((uint16_t)0x0008) /*!< Transfer error interrupt enable */ +#define DMA_CCR3_DIR ((uint16_t)0x0010) /*!< Data transfer direction */ +#define DMA_CCR3_CIRC ((uint16_t)0x0020) /*!< Circular mode */ +#define DMA_CCR3_PINC ((uint16_t)0x0040) /*!< Peripheral increment mode */ +#define DMA_CCR3_MINC ((uint16_t)0x0080) /*!< Memory increment mode */ + +#define DMA_CCR3_PSIZE ((uint16_t)0x0300) /*!< PSIZE[1:0] bits (Peripheral size) */ +#define DMA_CCR3_PSIZE_0 ((uint16_t)0x0100) /*!< Bit 0 */ +#define DMA_CCR3_PSIZE_1 ((uint16_t)0x0200) /*!< Bit 1 */ + +#define DMA_CCR3_MSIZE ((uint16_t)0x0C00) /*!< MSIZE[1:0] bits (Memory size) */ +#define DMA_CCR3_MSIZE_0 ((uint16_t)0x0400) /*!< Bit 0 */ +#define DMA_CCR3_MSIZE_1 ((uint16_t)0x0800) /*!< Bit 1 */ + +#define DMA_CCR3_PL ((uint16_t)0x3000) /*!< PL[1:0] bits (Channel Priority level) */ +#define DMA_CCR3_PL_0 ((uint16_t)0x1000) /*!< Bit 0 */ +#define DMA_CCR3_PL_1 ((uint16_t)0x2000) /*!< Bit 1 */ + +#define DMA_CCR3_MEM2MEM ((uint16_t)0x4000) /*!< Memory to memory mode */ + +/*!<****************** Bit definition for DMA_CCR4 register *******************/ +#define DMA_CCR4_EN ((uint16_t)0x0001) /*!< Channel enable */ +#define DMA_CCR4_TCIE ((uint16_t)0x0002) /*!< Transfer complete interrupt enable */ +#define DMA_CCR4_HTIE ((uint16_t)0x0004) /*!< Half Transfer interrupt enable */ +#define DMA_CCR4_TEIE ((uint16_t)0x0008) /*!< Transfer error interrupt enable */ +#define DMA_CCR4_DIR ((uint16_t)0x0010) /*!< Data transfer direction */ +#define DMA_CCR4_CIRC ((uint16_t)0x0020) /*!< Circular mode */ +#define DMA_CCR4_PINC ((uint16_t)0x0040) /*!< Peripheral increment mode */ +#define DMA_CCR4_MINC ((uint16_t)0x0080) /*!< Memory increment mode */ + +#define DMA_CCR4_PSIZE ((uint16_t)0x0300) /*!< PSIZE[1:0] bits (Peripheral size) */ +#define DMA_CCR4_PSIZE_0 ((uint16_t)0x0100) /*!< Bit 0 */ +#define DMA_CCR4_PSIZE_1 ((uint16_t)0x0200) /*!< Bit 1 */ + +#define DMA_CCR4_MSIZE ((uint16_t)0x0C00) /*!< MSIZE[1:0] bits (Memory size) */ +#define DMA_CCR4_MSIZE_0 ((uint16_t)0x0400) /*!< Bit 0 */ +#define DMA_CCR4_MSIZE_1 ((uint16_t)0x0800) /*!< Bit 1 */ + +#define DMA_CCR4_PL ((uint16_t)0x3000) /*!< PL[1:0] bits (Channel Priority level) */ +#define DMA_CCR4_PL_0 ((uint16_t)0x1000) /*!< Bit 0 */ +#define DMA_CCR4_PL_1 ((uint16_t)0x2000) /*!< Bit 1 */ + +#define DMA_CCR4_MEM2MEM ((uint16_t)0x4000) /*!< Memory to memory mode */ + +/****************** Bit definition for DMA_CCR5 register *******************/ +#define DMA_CCR5_EN ((uint16_t)0x0001) /*!< Channel enable */ +#define DMA_CCR5_TCIE ((uint16_t)0x0002) /*!< Transfer complete interrupt enable */ +#define DMA_CCR5_HTIE ((uint16_t)0x0004) /*!< Half Transfer interrupt enable */ +#define DMA_CCR5_TEIE ((uint16_t)0x0008) /*!< Transfer error interrupt enable */ +#define DMA_CCR5_DIR ((uint16_t)0x0010) /*!< Data transfer direction */ +#define DMA_CCR5_CIRC ((uint16_t)0x0020) /*!< Circular mode */ +#define DMA_CCR5_PINC ((uint16_t)0x0040) /*!< Peripheral increment mode */ +#define DMA_CCR5_MINC ((uint16_t)0x0080) /*!< Memory increment mode */ + +#define DMA_CCR5_PSIZE ((uint16_t)0x0300) /*!< PSIZE[1:0] bits (Peripheral size) */ +#define DMA_CCR5_PSIZE_0 ((uint16_t)0x0100) /*!< Bit 0 */ +#define DMA_CCR5_PSIZE_1 ((uint16_t)0x0200) /*!< Bit 1 */ + +#define DMA_CCR5_MSIZE ((uint16_t)0x0C00) /*!< MSIZE[1:0] bits (Memory size) */ +#define DMA_CCR5_MSIZE_0 ((uint16_t)0x0400) /*!< Bit 0 */ +#define DMA_CCR5_MSIZE_1 ((uint16_t)0x0800) /*!< Bit 1 */ + +#define DMA_CCR5_PL ((uint16_t)0x3000) /*!< PL[1:0] bits (Channel Priority level) */ +#define DMA_CCR5_PL_0 ((uint16_t)0x1000) /*!< Bit 0 */ +#define DMA_CCR5_PL_1 ((uint16_t)0x2000) /*!< Bit 1 */ + +#define DMA_CCR5_MEM2MEM ((uint16_t)0x4000) /*!< Memory to memory mode enable */ + +/******************* Bit definition for DMA_CCR6 register *******************/ +#define DMA_CCR6_EN ((uint16_t)0x0001) /*!< Channel enable */ +#define DMA_CCR6_TCIE ((uint16_t)0x0002) /*!< Transfer complete interrupt enable */ +#define DMA_CCR6_HTIE ((uint16_t)0x0004) /*!< Half Transfer interrupt enable */ +#define DMA_CCR6_TEIE ((uint16_t)0x0008) /*!< Transfer error interrupt enable */ +#define DMA_CCR6_DIR ((uint16_t)0x0010) /*!< Data transfer direction */ +#define DMA_CCR6_CIRC ((uint16_t)0x0020) /*!< Circular mode */ +#define DMA_CCR6_PINC ((uint16_t)0x0040) /*!< Peripheral increment mode */ +#define DMA_CCR6_MINC ((uint16_t)0x0080) /*!< Memory increment mode */ + +#define DMA_CCR6_PSIZE ((uint16_t)0x0300) /*!< PSIZE[1:0] bits (Peripheral size) */ +#define DMA_CCR6_PSIZE_0 ((uint16_t)0x0100) /*!< Bit 0 */ +#define DMA_CCR6_PSIZE_1 ((uint16_t)0x0200) /*!< Bit 1 */ + +#define DMA_CCR6_MSIZE ((uint16_t)0x0C00) /*!< MSIZE[1:0] bits (Memory size) */ +#define DMA_CCR6_MSIZE_0 ((uint16_t)0x0400) /*!< Bit 0 */ +#define DMA_CCR6_MSIZE_1 ((uint16_t)0x0800) /*!< Bit 1 */ + +#define DMA_CCR6_PL ((uint16_t)0x3000) /*!< PL[1:0] bits (Channel Priority level) */ +#define DMA_CCR6_PL_0 ((uint16_t)0x1000) /*!< Bit 0 */ +#define DMA_CCR6_PL_1 ((uint16_t)0x2000) /*!< Bit 1 */ + +#define DMA_CCR6_MEM2MEM ((uint16_t)0x4000) /*!< Memory to memory mode */ + +/******************* Bit definition for DMA_CCR7 register *******************/ +#define DMA_CCR7_EN ((uint16_t)0x0001) /*!< Channel enable */ +#define DMA_CCR7_TCIE ((uint16_t)0x0002) /*!< Transfer complete interrupt enable */ +#define DMA_CCR7_HTIE ((uint16_t)0x0004) /*!< Half Transfer interrupt enable */ +#define DMA_CCR7_TEIE ((uint16_t)0x0008) /*!< Transfer error interrupt enable */ +#define DMA_CCR7_DIR ((uint16_t)0x0010) /*!< Data transfer direction */ +#define DMA_CCR7_CIRC ((uint16_t)0x0020) /*!< Circular mode */ +#define DMA_CCR7_PINC ((uint16_t)0x0040) /*!< Peripheral increment mode */ +#define DMA_CCR7_MINC ((uint16_t)0x0080) /*!< Memory increment mode */ + +#define DMA_CCR7_PSIZE , ((uint16_t)0x0300) /*!< PSIZE[1:0] bits (Peripheral size) */ +#define DMA_CCR7_PSIZE_0 ((uint16_t)0x0100) /*!< Bit 0 */ +#define DMA_CCR7_PSIZE_1 ((uint16_t)0x0200) /*!< Bit 1 */ + +#define DMA_CCR7_MSIZE ((uint16_t)0x0C00) /*!< MSIZE[1:0] bits (Memory size) */ +#define DMA_CCR7_MSIZE_0 ((uint16_t)0x0400) /*!< Bit 0 */ +#define DMA_CCR7_MSIZE_1 ((uint16_t)0x0800) /*!< Bit 1 */ + +#define DMA_CCR7_PL ((uint16_t)0x3000) /*!< PL[1:0] bits (Channel Priority level) */ +#define DMA_CCR7_PL_0 ((uint16_t)0x1000) /*!< Bit 0 */ +#define DMA_CCR7_PL_1 ((uint16_t)0x2000) /*!< Bit 1 */ + +#define DMA_CCR7_MEM2MEM ((uint16_t)0x4000) /*!< Memory to memory mode enable */ + +/****************** Bit definition for DMA_CNDTR1 register ******************/ +#define DMA_CNDTR1_NDT ((uint16_t)0xFFFF) /*!< Number of data to Transfer */ + +/****************** Bit definition for DMA_CNDTR2 register ******************/ +#define DMA_CNDTR2_NDT ((uint16_t)0xFFFF) /*!< Number of data to Transfer */ + +/****************** Bit definition for DMA_CNDTR3 register ******************/ +#define DMA_CNDTR3_NDT ((uint16_t)0xFFFF) /*!< Number of data to Transfer */ + +/****************** Bit definition for DMA_CNDTR4 register ******************/ +#define DMA_CNDTR4_NDT ((uint16_t)0xFFFF) /*!< Number of data to Transfer */ + +/****************** Bit definition for DMA_CNDTR5 register ******************/ +#define DMA_CNDTR5_NDT ((uint16_t)0xFFFF) /*!< Number of data to Transfer */ + +/****************** Bit definition for DMA_CNDTR6 register ******************/ +#define DMA_CNDTR6_NDT ((uint16_t)0xFFFF) /*!< Number of data to Transfer */ + +/****************** Bit definition for DMA_CNDTR7 register ******************/ +#define DMA_CNDTR7_NDT ((uint16_t)0xFFFF) /*!< Number of data to Transfer */ + +/****************** Bit definition for DMA_CPAR1 register *******************/ +#define DMA_CPAR1_PA ((uint32_t)0xFFFFFFFF) /*!< Peripheral Address */ + +/****************** Bit definition for DMA_CPAR2 register *******************/ +#define DMA_CPAR2_PA ((uint32_t)0xFFFFFFFF) /*!< Peripheral Address */ + +/****************** Bit definition for DMA_CPAR3 register *******************/ +#define DMA_CPAR3_PA ((uint32_t)0xFFFFFFFF) /*!< Peripheral Address */ + + +/****************** Bit definition for DMA_CPAR4 register *******************/ +#define DMA_CPAR4_PA ((uint32_t)0xFFFFFFFF) /*!< Peripheral Address */ + +/****************** Bit definition for DMA_CPAR5 register *******************/ +#define DMA_CPAR5_PA ((uint32_t)0xFFFFFFFF) /*!< Peripheral Address */ + +/****************** Bit definition for DMA_CPAR6 register *******************/ +#define DMA_CPAR6_PA ((uint32_t)0xFFFFFFFF) /*!< Peripheral Address */ + + +/****************** Bit definition for DMA_CPAR7 register *******************/ +#define DMA_CPAR7_PA ((uint32_t)0xFFFFFFFF) /*!< Peripheral Address */ + +/****************** Bit definition for DMA_CMAR1 register *******************/ +#define DMA_CMAR1_MA ((uint32_t)0xFFFFFFFF) /*!< Memory Address */ + +/****************** Bit definition for DMA_CMAR2 register *******************/ +#define DMA_CMAR2_MA ((uint32_t)0xFFFFFFFF) /*!< Memory Address */ + +/****************** Bit definition for DMA_CMAR3 register *******************/ +#define DMA_CMAR3_MA ((uint32_t)0xFFFFFFFF) /*!< Memory Address */ + + +/****************** Bit definition for DMA_CMAR4 register *******************/ +#define DMA_CMAR4_MA ((uint32_t)0xFFFFFFFF) /*!< Memory Address */ + +/****************** Bit definition for DMA_CMAR5 register *******************/ +#define DMA_CMAR5_MA ((uint32_t)0xFFFFFFFF) /*!< Memory Address */ + +/****************** Bit definition for DMA_CMAR6 register *******************/ +#define DMA_CMAR6_MA ((uint32_t)0xFFFFFFFF) /*!< Memory Address */ + +/****************** Bit definition for DMA_CMAR7 register *******************/ +#define DMA_CMAR7_MA ((uint32_t)0xFFFFFFFF) /*!< Memory Address */ + +/******************************************************************************/ +/* */ +/* Analog to Digital Converter */ +/* */ +/******************************************************************************/ + +/******************** Bit definition for ADC_SR register ********************/ +#define ADC_SR_AWD ((uint8_t)0x01) /*!< Analog watchdog flag */ +#define ADC_SR_EOC ((uint8_t)0x02) /*!< End of conversion */ +#define ADC_SR_JEOC ((uint8_t)0x04) /*!< Injected channel end of conversion */ +#define ADC_SR_JSTRT ((uint8_t)0x08) /*!< Injected channel Start flag */ +#define ADC_SR_STRT ((uint8_t)0x10) /*!< Regular channel Start flag */ + +/******************* Bit definition for ADC_CR1 register ********************/ +#define ADC_CR1_AWDCH ((uint32_t)0x0000001F) /*!< AWDCH[4:0] bits (Analog watchdog channel select bits) */ +#define ADC_CR1_AWDCH_0 ((uint32_t)0x00000001) /*!< Bit 0 */ +#define ADC_CR1_AWDCH_1 ((uint32_t)0x00000002) /*!< Bit 1 */ +#define ADC_CR1_AWDCH_2 ((uint32_t)0x00000004) /*!< Bit 2 */ +#define ADC_CR1_AWDCH_3 ((uint32_t)0x00000008) /*!< Bit 3 */ +#define ADC_CR1_AWDCH_4 ((uint32_t)0x00000010) /*!< Bit 4 */ + +#define ADC_CR1_EOCIE ((uint32_t)0x00000020) /*!< Interrupt enable for EOC */ +#define ADC_CR1_AWDIE ((uint32_t)0x00000040) /*!< Analog Watchdog interrupt enable */ +#define ADC_CR1_JEOCIE ((uint32_t)0x00000080) /*!< Interrupt enable for injected channels */ +#define ADC_CR1_SCAN ((uint32_t)0x00000100) /*!< Scan mode */ +#define ADC_CR1_AWDSGL ((uint32_t)0x00000200) /*!< Enable the watchdog on a single channel in scan mode */ +#define ADC_CR1_JAUTO ((uint32_t)0x00000400) /*!< Automatic injected group conversion */ +#define ADC_CR1_DISCEN ((uint32_t)0x00000800) /*!< Discontinuous mode on regular channels */ +#define ADC_CR1_JDISCEN ((uint32_t)0x00001000) /*!< Discontinuous mode on injected channels */ + +#define ADC_CR1_DISCNUM ((uint32_t)0x0000E000) /*!< DISCNUM[2:0] bits (Discontinuous mode channel count) */ +#define ADC_CR1_DISCNUM_0 ((uint32_t)0x00002000) /*!< Bit 0 */ +#define ADC_CR1_DISCNUM_1 ((uint32_t)0x00004000) /*!< Bit 1 */ +#define ADC_CR1_DISCNUM_2 ((uint32_t)0x00008000) /*!< Bit 2 */ + +#define ADC_CR1_DUALMOD ((uint32_t)0x000F0000) /*!< DUALMOD[3:0] bits (Dual mode selection) */ +#define ADC_CR1_DUALMOD_0 ((uint32_t)0x00010000) /*!< Bit 0 */ +#define ADC_CR1_DUALMOD_1 ((uint32_t)0x00020000) /*!< Bit 1 */ +#define ADC_CR1_DUALMOD_2 ((uint32_t)0x00040000) /*!< Bit 2 */ +#define ADC_CR1_DUALMOD_3 ((uint32_t)0x00080000) /*!< Bit 3 */ + +#define ADC_CR1_JAWDEN ((uint32_t)0x00400000) /*!< Analog watchdog enable on injected channels */ +#define ADC_CR1_AWDEN ((uint32_t)0x00800000) /*!< Analog watchdog enable on regular channels */ + + +/******************* Bit definition for ADC_CR2 register ********************/ +#define ADC_CR2_ADON ((uint32_t)0x00000001) /*!< A/D Converter ON / OFF */ +#define ADC_CR2_CONT ((uint32_t)0x00000002) /*!< Continuous Conversion */ +#define ADC_CR2_CAL ((uint32_t)0x00000004) /*!< A/D Calibration */ +#define ADC_CR2_RSTCAL ((uint32_t)0x00000008) /*!< Reset Calibration */ +#define ADC_CR2_DMA ((uint32_t)0x00000100) /*!< Direct Memory access mode */ +#define ADC_CR2_ALIGN ((uint32_t)0x00000800) /*!< Data Alignment */ + +#define ADC_CR2_JEXTSEL ((uint32_t)0x00007000) /*!< JEXTSEL[2:0] bits (External event select for injected group) */ +#define ADC_CR2_JEXTSEL_0 ((uint32_t)0x00001000) /*!< Bit 0 */ +#define ADC_CR2_JEXTSEL_1 ((uint32_t)0x00002000) /*!< Bit 1 */ +#define ADC_CR2_JEXTSEL_2 ((uint32_t)0x00004000) /*!< Bit 2 */ + +#define ADC_CR2_JEXTTRIG ((uint32_t)0x00008000) /*!< External Trigger Conversion mode for injected channels */ + +#define ADC_CR2_EXTSEL ((uint32_t)0x000E0000) /*!< EXTSEL[2:0] bits (External Event Select for regular group) */ +#define ADC_CR2_EXTSEL_0 ((uint32_t)0x00020000) /*!< Bit 0 */ +#define ADC_CR2_EXTSEL_1 ((uint32_t)0x00040000) /*!< Bit 1 */ +#define ADC_CR2_EXTSEL_2 ((uint32_t)0x00080000) /*!< Bit 2 */ + +#define ADC_CR2_EXTTRIG ((uint32_t)0x00100000) /*!< External Trigger Conversion mode for regular channels */ +#define ADC_CR2_JSWSTART ((uint32_t)0x00200000) /*!< Start Conversion of injected channels */ +#define ADC_CR2_SWSTART ((uint32_t)0x00400000) /*!< Start Conversion of regular channels */ +#define ADC_CR2_TSVREFE ((uint32_t)0x00800000) /*!< Temperature Sensor and VREFINT Enable */ + +/****************** Bit definition for ADC_SMPR1 register *******************/ +#define ADC_SMPR1_SMP10 ((uint32_t)0x00000007) /*!< SMP10[2:0] bits (Channel 10 Sample time selection) */ +#define ADC_SMPR1_SMP10_0 ((uint32_t)0x00000001) /*!< Bit 0 */ +#define ADC_SMPR1_SMP10_1 ((uint32_t)0x00000002) /*!< Bit 1 */ +#define ADC_SMPR1_SMP10_2 ((uint32_t)0x00000004) /*!< Bit 2 */ + +#define ADC_SMPR1_SMP11 ((uint32_t)0x00000038) /*!< SMP11[2:0] bits (Channel 11 Sample time selection) */ +#define ADC_SMPR1_SMP11_0 ((uint32_t)0x00000008) /*!< Bit 0 */ +#define ADC_SMPR1_SMP11_1 ((uint32_t)0x00000010) /*!< Bit 1 */ +#define ADC_SMPR1_SMP11_2 ((uint32_t)0x00000020) /*!< Bit 2 */ + +#define ADC_SMPR1_SMP12 ((uint32_t)0x000001C0) /*!< SMP12[2:0] bits (Channel 12 Sample time selection) */ +#define ADC_SMPR1_SMP12_0 ((uint32_t)0x00000040) /*!< Bit 0 */ +#define ADC_SMPR1_SMP12_1 ((uint32_t)0x00000080) /*!< Bit 1 */ +#define ADC_SMPR1_SMP12_2 ((uint32_t)0x00000100) /*!< Bit 2 */ + +#define ADC_SMPR1_SMP13 ((uint32_t)0x00000E00) /*!< SMP13[2:0] bits (Channel 13 Sample time selection) */ +#define ADC_SMPR1_SMP13_0 ((uint32_t)0x00000200) /*!< Bit 0 */ +#define ADC_SMPR1_SMP13_1 ((uint32_t)0x00000400) /*!< Bit 1 */ +#define ADC_SMPR1_SMP13_2 ((uint32_t)0x00000800) /*!< Bit 2 */ + +#define ADC_SMPR1_SMP14 ((uint32_t)0x00007000) /*!< SMP14[2:0] bits (Channel 14 Sample time selection) */ +#define ADC_SMPR1_SMP14_0 ((uint32_t)0x00001000) /*!< Bit 0 */ +#define ADC_SMPR1_SMP14_1 ((uint32_t)0x00002000) /*!< Bit 1 */ +#define ADC_SMPR1_SMP14_2 ((uint32_t)0x00004000) /*!< Bit 2 */ + +#define ADC_SMPR1_SMP15 ((uint32_t)0x00038000) /*!< SMP15[2:0] bits (Channel 15 Sample time selection) */ +#define ADC_SMPR1_SMP15_0 ((uint32_t)0x00008000) /*!< Bit 0 */ +#define ADC_SMPR1_SMP15_1 ((uint32_t)0x00010000) /*!< Bit 1 */ +#define ADC_SMPR1_SMP15_2 ((uint32_t)0x00020000) /*!< Bit 2 */ + +#define ADC_SMPR1_SMP16 ((uint32_t)0x001C0000) /*!< SMP16[2:0] bits (Channel 16 Sample time selection) */ +#define ADC_SMPR1_SMP16_0 ((uint32_t)0x00040000) /*!< Bit 0 */ +#define ADC_SMPR1_SMP16_1 ((uint32_t)0x00080000) /*!< Bit 1 */ +#define ADC_SMPR1_SMP16_2 ((uint32_t)0x00100000) /*!< Bit 2 */ + +#define ADC_SMPR1_SMP17 ((uint32_t)0x00E00000) /*!< SMP17[2:0] bits (Channel 17 Sample time selection) */ +#define ADC_SMPR1_SMP17_0 ((uint32_t)0x00200000) /*!< Bit 0 */ +#define ADC_SMPR1_SMP17_1 ((uint32_t)0x00400000) /*!< Bit 1 */ +#define ADC_SMPR1_SMP17_2 ((uint32_t)0x00800000) /*!< Bit 2 */ + +/****************** Bit definition for ADC_SMPR2 register *******************/ +#define ADC_SMPR2_SMP0 ((uint32_t)0x00000007) /*!< SMP0[2:0] bits (Channel 0 Sample time selection) */ +#define ADC_SMPR2_SMP0_0 ((uint32_t)0x00000001) /*!< Bit 0 */ +#define ADC_SMPR2_SMP0_1 ((uint32_t)0x00000002) /*!< Bit 1 */ +#define ADC_SMPR2_SMP0_2 ((uint32_t)0x00000004) /*!< Bit 2 */ + +#define ADC_SMPR2_SMP1 ((uint32_t)0x00000038) /*!< SMP1[2:0] bits (Channel 1 Sample time selection) */ +#define ADC_SMPR2_SMP1_0 ((uint32_t)0x00000008) /*!< Bit 0 */ +#define ADC_SMPR2_SMP1_1 ((uint32_t)0x00000010) /*!< Bit 1 */ +#define ADC_SMPR2_SMP1_2 ((uint32_t)0x00000020) /*!< Bit 2 */ + +#define ADC_SMPR2_SMP2 ((uint32_t)0x000001C0) /*!< SMP2[2:0] bits (Channel 2 Sample time selection) */ +#define ADC_SMPR2_SMP2_0 ((uint32_t)0x00000040) /*!< Bit 0 */ +#define ADC_SMPR2_SMP2_1 ((uint32_t)0x00000080) /*!< Bit 1 */ +#define ADC_SMPR2_SMP2_2 ((uint32_t)0x00000100) /*!< Bit 2 */ + +#define ADC_SMPR2_SMP3 ((uint32_t)0x00000E00) /*!< SMP3[2:0] bits (Channel 3 Sample time selection) */ +#define ADC_SMPR2_SMP3_0 ((uint32_t)0x00000200) /*!< Bit 0 */ +#define ADC_SMPR2_SMP3_1 ((uint32_t)0x00000400) /*!< Bit 1 */ +#define ADC_SMPR2_SMP3_2 ((uint32_t)0x00000800) /*!< Bit 2 */ + +#define ADC_SMPR2_SMP4 ((uint32_t)0x00007000) /*!< SMP4[2:0] bits (Channel 4 Sample time selection) */ +#define ADC_SMPR2_SMP4_0 ((uint32_t)0x00001000) /*!< Bit 0 */ +#define ADC_SMPR2_SMP4_1 ((uint32_t)0x00002000) /*!< Bit 1 */ +#define ADC_SMPR2_SMP4_2 ((uint32_t)0x00004000) /*!< Bit 2 */ + +#define ADC_SMPR2_SMP5 ((uint32_t)0x00038000) /*!< SMP5[2:0] bits (Channel 5 Sample time selection) */ +#define ADC_SMPR2_SMP5_0 ((uint32_t)0x00008000) /*!< Bit 0 */ +#define ADC_SMPR2_SMP5_1 ((uint32_t)0x00010000) /*!< Bit 1 */ +#define ADC_SMPR2_SMP5_2 ((uint32_t)0x00020000) /*!< Bit 2 */ + +#define ADC_SMPR2_SMP6 ((uint32_t)0x001C0000) /*!< SMP6[2:0] bits (Channel 6 Sample time selection) */ +#define ADC_SMPR2_SMP6_0 ((uint32_t)0x00040000) /*!< Bit 0 */ +#define ADC_SMPR2_SMP6_1 ((uint32_t)0x00080000) /*!< Bit 1 */ +#define ADC_SMPR2_SMP6_2 ((uint32_t)0x00100000) /*!< Bit 2 */ + +#define ADC_SMPR2_SMP7 ((uint32_t)0x00E00000) /*!< SMP7[2:0] bits (Channel 7 Sample time selection) */ +#define ADC_SMPR2_SMP7_0 ((uint32_t)0x00200000) /*!< Bit 0 */ +#define ADC_SMPR2_SMP7_1 ((uint32_t)0x00400000) /*!< Bit 1 */ +#define ADC_SMPR2_SMP7_2 ((uint32_t)0x00800000) /*!< Bit 2 */ + +#define ADC_SMPR2_SMP8 ((uint32_t)0x07000000) /*!< SMP8[2:0] bits (Channel 8 Sample time selection) */ +#define ADC_SMPR2_SMP8_0 ((uint32_t)0x01000000) /*!< Bit 0 */ +#define ADC_SMPR2_SMP8_1 ((uint32_t)0x02000000) /*!< Bit 1 */ +#define ADC_SMPR2_SMP8_2 ((uint32_t)0x04000000) /*!< Bit 2 */ + +#define ADC_SMPR2_SMP9 ((uint32_t)0x38000000) /*!< SMP9[2:0] bits (Channel 9 Sample time selection) */ +#define ADC_SMPR2_SMP9_0 ((uint32_t)0x08000000) /*!< Bit 0 */ +#define ADC_SMPR2_SMP9_1 ((uint32_t)0x10000000) /*!< Bit 1 */ +#define ADC_SMPR2_SMP9_2 ((uint32_t)0x20000000) /*!< Bit 2 */ + +/****************** Bit definition for ADC_JOFR1 register *******************/ +#define ADC_JOFR1_JOFFSET1 ((uint16_t)0x0FFF) /*!< Data offset for injected channel 1 */ + +/****************** Bit definition for ADC_JOFR2 register *******************/ +#define ADC_JOFR2_JOFFSET2 ((uint16_t)0x0FFF) /*!< Data offset for injected channel 2 */ + +/****************** Bit definition for ADC_JOFR3 register *******************/ +#define ADC_JOFR3_JOFFSET3 ((uint16_t)0x0FFF) /*!< Data offset for injected channel 3 */ + +/****************** Bit definition for ADC_JOFR4 register *******************/ +#define ADC_JOFR4_JOFFSET4 ((uint16_t)0x0FFF) /*!< Data offset for injected channel 4 */ + +/******************* Bit definition for ADC_HTR register ********************/ +#define ADC_HTR_HT ((uint16_t)0x0FFF) /*!< Analog watchdog high threshold */ + +/******************* Bit definition for ADC_LTR register ********************/ +#define ADC_LTR_LT ((uint16_t)0x0FFF) /*!< Analog watchdog low threshold */ + +/******************* Bit definition for ADC_SQR1 register *******************/ +#define ADC_SQR1_SQ13 ((uint32_t)0x0000001F) /*!< SQ13[4:0] bits (13th conversion in regular sequence) */ +#define ADC_SQR1_SQ13_0 ((uint32_t)0x00000001) /*!< Bit 0 */ +#define ADC_SQR1_SQ13_1 ((uint32_t)0x00000002) /*!< Bit 1 */ +#define ADC_SQR1_SQ13_2 ((uint32_t)0x00000004) /*!< Bit 2 */ +#define ADC_SQR1_SQ13_3 ((uint32_t)0x00000008) /*!< Bit 3 */ +#define ADC_SQR1_SQ13_4 ((uint32_t)0x00000010) /*!< Bit 4 */ + +#define ADC_SQR1_SQ14 ((uint32_t)0x000003E0) /*!< SQ14[4:0] bits (14th conversion in regular sequence) */ +#define ADC_SQR1_SQ14_0 ((uint32_t)0x00000020) /*!< Bit 0 */ +#define ADC_SQR1_SQ14_1 ((uint32_t)0x00000040) /*!< Bit 1 */ +#define ADC_SQR1_SQ14_2 ((uint32_t)0x00000080) /*!< Bit 2 */ +#define ADC_SQR1_SQ14_3 ((uint32_t)0x00000100) /*!< Bit 3 */ +#define ADC_SQR1_SQ14_4 ((uint32_t)0x00000200) /*!< Bit 4 */ + +#define ADC_SQR1_SQ15 ((uint32_t)0x00007C00) /*!< SQ15[4:0] bits (15th conversion in regular sequence) */ +#define ADC_SQR1_SQ15_0 ((uint32_t)0x00000400) /*!< Bit 0 */ +#define ADC_SQR1_SQ15_1 ((uint32_t)0x00000800) /*!< Bit 1 */ +#define ADC_SQR1_SQ15_2 ((uint32_t)0x00001000) /*!< Bit 2 */ +#define ADC_SQR1_SQ15_3 ((uint32_t)0x00002000) /*!< Bit 3 */ +#define ADC_SQR1_SQ15_4 ((uint32_t)0x00004000) /*!< Bit 4 */ + +#define ADC_SQR1_SQ16 ((uint32_t)0x000F8000) /*!< SQ16[4:0] bits (16th conversion in regular sequence) */ +#define ADC_SQR1_SQ16_0 ((uint32_t)0x00008000) /*!< Bit 0 */ +#define ADC_SQR1_SQ16_1 ((uint32_t)0x00010000) /*!< Bit 1 */ +#define ADC_SQR1_SQ16_2 ((uint32_t)0x00020000) /*!< Bit 2 */ +#define ADC_SQR1_SQ16_3 ((uint32_t)0x00040000) /*!< Bit 3 */ +#define ADC_SQR1_SQ16_4 ((uint32_t)0x00080000) /*!< Bit 4 */ + +#define ADC_SQR1_L ((uint32_t)0x00F00000) /*!< L[3:0] bits (Regular channel sequence length) */ +#define ADC_SQR1_L_0 ((uint32_t)0x00100000) /*!< Bit 0 */ +#define ADC_SQR1_L_1 ((uint32_t)0x00200000) /*!< Bit 1 */ +#define ADC_SQR1_L_2 ((uint32_t)0x00400000) /*!< Bit 2 */ +#define ADC_SQR1_L_3 ((uint32_t)0x00800000) /*!< Bit 3 */ + +/******************* Bit definition for ADC_SQR2 register *******************/ +#define ADC_SQR2_SQ7 ((uint32_t)0x0000001F) /*!< SQ7[4:0] bits (7th conversion in regular sequence) */ +#define ADC_SQR2_SQ7_0 ((uint32_t)0x00000001) /*!< Bit 0 */ +#define ADC_SQR2_SQ7_1 ((uint32_t)0x00000002) /*!< Bit 1 */ +#define ADC_SQR2_SQ7_2 ((uint32_t)0x00000004) /*!< Bit 2 */ +#define ADC_SQR2_SQ7_3 ((uint32_t)0x00000008) /*!< Bit 3 */ +#define ADC_SQR2_SQ7_4 ((uint32_t)0x00000010) /*!< Bit 4 */ + +#define ADC_SQR2_SQ8 ((uint32_t)0x000003E0) /*!< SQ8[4:0] bits (8th conversion in regular sequence) */ +#define ADC_SQR2_SQ8_0 ((uint32_t)0x00000020) /*!< Bit 0 */ +#define ADC_SQR2_SQ8_1 ((uint32_t)0x00000040) /*!< Bit 1 */ +#define ADC_SQR2_SQ8_2 ((uint32_t)0x00000080) /*!< Bit 2 */ +#define ADC_SQR2_SQ8_3 ((uint32_t)0x00000100) /*!< Bit 3 */ +#define ADC_SQR2_SQ8_4 ((uint32_t)0x00000200) /*!< Bit 4 */ + +#define ADC_SQR2_SQ9 ((uint32_t)0x00007C00) /*!< SQ9[4:0] bits (9th conversion in regular sequence) */ +#define ADC_SQR2_SQ9_0 ((uint32_t)0x00000400) /*!< Bit 0 */ +#define ADC_SQR2_SQ9_1 ((uint32_t)0x00000800) /*!< Bit 1 */ +#define ADC_SQR2_SQ9_2 ((uint32_t)0x00001000) /*!< Bit 2 */ +#define ADC_SQR2_SQ9_3 ((uint32_t)0x00002000) /*!< Bit 3 */ +#define ADC_SQR2_SQ9_4 ((uint32_t)0x00004000) /*!< Bit 4 */ + +#define ADC_SQR2_SQ10 ((uint32_t)0x000F8000) /*!< SQ10[4:0] bits (10th conversion in regular sequence) */ +#define ADC_SQR2_SQ10_0 ((uint32_t)0x00008000) /*!< Bit 0 */ +#define ADC_SQR2_SQ10_1 ((uint32_t)0x00010000) /*!< Bit 1 */ +#define ADC_SQR2_SQ10_2 ((uint32_t)0x00020000) /*!< Bit 2 */ +#define ADC_SQR2_SQ10_3 ((uint32_t)0x00040000) /*!< Bit 3 */ +#define ADC_SQR2_SQ10_4 ((uint32_t)0x00080000) /*!< Bit 4 */ + +#define ADC_SQR2_SQ11 ((uint32_t)0x01F00000) /*!< SQ11[4:0] bits (11th conversion in regular sequence) */ +#define ADC_SQR2_SQ11_0 ((uint32_t)0x00100000) /*!< Bit 0 */ +#define ADC_SQR2_SQ11_1 ((uint32_t)0x00200000) /*!< Bit 1 */ +#define ADC_SQR2_SQ11_2 ((uint32_t)0x00400000) /*!< Bit 2 */ +#define ADC_SQR2_SQ11_3 ((uint32_t)0x00800000) /*!< Bit 3 */ +#define ADC_SQR2_SQ11_4 ((uint32_t)0x01000000) /*!< Bit 4 */ + +#define ADC_SQR2_SQ12 ((uint32_t)0x3E000000) /*!< SQ12[4:0] bits (12th conversion in regular sequence) */ +#define ADC_SQR2_SQ12_0 ((uint32_t)0x02000000) /*!< Bit 0 */ +#define ADC_SQR2_SQ12_1 ((uint32_t)0x04000000) /*!< Bit 1 */ +#define ADC_SQR2_SQ12_2 ((uint32_t)0x08000000) /*!< Bit 2 */ +#define ADC_SQR2_SQ12_3 ((uint32_t)0x10000000) /*!< Bit 3 */ +#define ADC_SQR2_SQ12_4 ((uint32_t)0x20000000) /*!< Bit 4 */ + +/******************* Bit definition for ADC_SQR3 register *******************/ +#define ADC_SQR3_SQ1 ((uint32_t)0x0000001F) /*!< SQ1[4:0] bits (1st conversion in regular sequence) */ +#define ADC_SQR3_SQ1_0 ((uint32_t)0x00000001) /*!< Bit 0 */ +#define ADC_SQR3_SQ1_1 ((uint32_t)0x00000002) /*!< Bit 1 */ +#define ADC_SQR3_SQ1_2 ((uint32_t)0x00000004) /*!< Bit 2 */ +#define ADC_SQR3_SQ1_3 ((uint32_t)0x00000008) /*!< Bit 3 */ +#define ADC_SQR3_SQ1_4 ((uint32_t)0x00000010) /*!< Bit 4 */ + +#define ADC_SQR3_SQ2 ((uint32_t)0x000003E0) /*!< SQ2[4:0] bits (2nd conversion in regular sequence) */ +#define ADC_SQR3_SQ2_0 ((uint32_t)0x00000020) /*!< Bit 0 */ +#define ADC_SQR3_SQ2_1 ((uint32_t)0x00000040) /*!< Bit 1 */ +#define ADC_SQR3_SQ2_2 ((uint32_t)0x00000080) /*!< Bit 2 */ +#define ADC_SQR3_SQ2_3 ((uint32_t)0x00000100) /*!< Bit 3 */ +#define ADC_SQR3_SQ2_4 ((uint32_t)0x00000200) /*!< Bit 4 */ + +#define ADC_SQR3_SQ3 ((uint32_t)0x00007C00) /*!< SQ3[4:0] bits (3rd conversion in regular sequence) */ +#define ADC_SQR3_SQ3_0 ((uint32_t)0x00000400) /*!< Bit 0 */ +#define ADC_SQR3_SQ3_1 ((uint32_t)0x00000800) /*!< Bit 1 */ +#define ADC_SQR3_SQ3_2 ((uint32_t)0x00001000) /*!< Bit 2 */ +#define ADC_SQR3_SQ3_3 ((uint32_t)0x00002000) /*!< Bit 3 */ +#define ADC_SQR3_SQ3_4 ((uint32_t)0x00004000) /*!< Bit 4 */ + +#define ADC_SQR3_SQ4 ((uint32_t)0x000F8000) /*!< SQ4[4:0] bits (4th conversion in regular sequence) */ +#define ADC_SQR3_SQ4_0 ((uint32_t)0x00008000) /*!< Bit 0 */ +#define ADC_SQR3_SQ4_1 ((uint32_t)0x00010000) /*!< Bit 1 */ +#define ADC_SQR3_SQ4_2 ((uint32_t)0x00020000) /*!< Bit 2 */ +#define ADC_SQR3_SQ4_3 ((uint32_t)0x00040000) /*!< Bit 3 */ +#define ADC_SQR3_SQ4_4 ((uint32_t)0x00080000) /*!< Bit 4 */ + +#define ADC_SQR3_SQ5 ((uint32_t)0x01F00000) /*!< SQ5[4:0] bits (5th conversion in regular sequence) */ +#define ADC_SQR3_SQ5_0 ((uint32_t)0x00100000) /*!< Bit 0 */ +#define ADC_SQR3_SQ5_1 ((uint32_t)0x00200000) /*!< Bit 1 */ +#define ADC_SQR3_SQ5_2 ((uint32_t)0x00400000) /*!< Bit 2 */ +#define ADC_SQR3_SQ5_3 ((uint32_t)0x00800000) /*!< Bit 3 */ +#define ADC_SQR3_SQ5_4 ((uint32_t)0x01000000) /*!< Bit 4 */ + +#define ADC_SQR3_SQ6 ((uint32_t)0x3E000000) /*!< SQ6[4:0] bits (6th conversion in regular sequence) */ +#define ADC_SQR3_SQ6_0 ((uint32_t)0x02000000) /*!< Bit 0 */ +#define ADC_SQR3_SQ6_1 ((uint32_t)0x04000000) /*!< Bit 1 */ +#define ADC_SQR3_SQ6_2 ((uint32_t)0x08000000) /*!< Bit 2 */ +#define ADC_SQR3_SQ6_3 ((uint32_t)0x10000000) /*!< Bit 3 */ +#define ADC_SQR3_SQ6_4 ((uint32_t)0x20000000) /*!< Bit 4 */ + +/******************* Bit definition for ADC_JSQR register *******************/ +#define ADC_JSQR_JSQ1 ((uint32_t)0x0000001F) /*!< JSQ1[4:0] bits (1st conversion in injected sequence) */ +#define ADC_JSQR_JSQ1_0 ((uint32_t)0x00000001) /*!< Bit 0 */ +#define ADC_JSQR_JSQ1_1 ((uint32_t)0x00000002) /*!< Bit 1 */ +#define ADC_JSQR_JSQ1_2 ((uint32_t)0x00000004) /*!< Bit 2 */ +#define ADC_JSQR_JSQ1_3 ((uint32_t)0x00000008) /*!< Bit 3 */ +#define ADC_JSQR_JSQ1_4 ((uint32_t)0x00000010) /*!< Bit 4 */ + +#define ADC_JSQR_JSQ2 ((uint32_t)0x000003E0) /*!< JSQ2[4:0] bits (2nd conversion in injected sequence) */ +#define ADC_JSQR_JSQ2_0 ((uint32_t)0x00000020) /*!< Bit 0 */ +#define ADC_JSQR_JSQ2_1 ((uint32_t)0x00000040) /*!< Bit 1 */ +#define ADC_JSQR_JSQ2_2 ((uint32_t)0x00000080) /*!< Bit 2 */ +#define ADC_JSQR_JSQ2_3 ((uint32_t)0x00000100) /*!< Bit 3 */ +#define ADC_JSQR_JSQ2_4 ((uint32_t)0x00000200) /*!< Bit 4 */ + +#define ADC_JSQR_JSQ3 ((uint32_t)0x00007C00) /*!< JSQ3[4:0] bits (3rd conversion in injected sequence) */ +#define ADC_JSQR_JSQ3_0 ((uint32_t)0x00000400) /*!< Bit 0 */ +#define ADC_JSQR_JSQ3_1 ((uint32_t)0x00000800) /*!< Bit 1 */ +#define ADC_JSQR_JSQ3_2 ((uint32_t)0x00001000) /*!< Bit 2 */ +#define ADC_JSQR_JSQ3_3 ((uint32_t)0x00002000) /*!< Bit 3 */ +#define ADC_JSQR_JSQ3_4 ((uint32_t)0x00004000) /*!< Bit 4 */ + +#define ADC_JSQR_JSQ4 ((uint32_t)0x000F8000) /*!< JSQ4[4:0] bits (4th conversion in injected sequence) */ +#define ADC_JSQR_JSQ4_0 ((uint32_t)0x00008000) /*!< Bit 0 */ +#define ADC_JSQR_JSQ4_1 ((uint32_t)0x00010000) /*!< Bit 1 */ +#define ADC_JSQR_JSQ4_2 ((uint32_t)0x00020000) /*!< Bit 2 */ +#define ADC_JSQR_JSQ4_3 ((uint32_t)0x00040000) /*!< Bit 3 */ +#define ADC_JSQR_JSQ4_4 ((uint32_t)0x00080000) /*!< Bit 4 */ + +#define ADC_JSQR_JL ((uint32_t)0x00300000) /*!< JL[1:0] bits (Injected Sequence length) */ +#define ADC_JSQR_JL_0 ((uint32_t)0x00100000) /*!< Bit 0 */ +#define ADC_JSQR_JL_1 ((uint32_t)0x00200000) /*!< Bit 1 */ + +/******************* Bit definition for ADC_JDR1 register *******************/ +#define ADC_JDR1_JDATA ((uint16_t)0xFFFF) /*!< Injected data */ + +/******************* Bit definition for ADC_JDR2 register *******************/ +#define ADC_JDR2_JDATA ((uint16_t)0xFFFF) /*!< Injected data */ + +/******************* Bit definition for ADC_JDR3 register *******************/ +#define ADC_JDR3_JDATA ((uint16_t)0xFFFF) /*!< Injected data */ + +/******************* Bit definition for ADC_JDR4 register *******************/ +#define ADC_JDR4_JDATA ((uint16_t)0xFFFF) /*!< Injected data */ + +/******************** Bit definition for ADC_DR register ********************/ +#define ADC_DR_DATA ((uint32_t)0x0000FFFF) /*!< Regular data */ +#define ADC_DR_ADC2DATA ((uint32_t)0xFFFF0000) /*!< ADC2 data */ + +/******************************************************************************/ +/* */ +/* Digital to Analog Converter */ +/* */ +/******************************************************************************/ + +/******************** Bit definition for DAC_CR register ********************/ +#define DAC_CR_EN1 ((uint32_t)0x00000001) /*!< DAC channel1 enable */ +#define DAC_CR_BOFF1 ((uint32_t)0x00000002) /*!< DAC channel1 output buffer disable */ +#define DAC_CR_TEN1 ((uint32_t)0x00000004) /*!< DAC channel1 Trigger enable */ + +#define DAC_CR_TSEL1 ((uint32_t)0x00000038) /*!< TSEL1[2:0] (DAC channel1 Trigger selection) */ +#define DAC_CR_TSEL1_0 ((uint32_t)0x00000008) /*!< Bit 0 */ +#define DAC_CR_TSEL1_1 ((uint32_t)0x00000010) /*!< Bit 1 */ +#define DAC_CR_TSEL1_2 ((uint32_t)0x00000020) /*!< Bit 2 */ + +#define DAC_CR_WAVE1 ((uint32_t)0x000000C0) /*!< WAVE1[1:0] (DAC channel1 noise/triangle wave generation enable) */ +#define DAC_CR_WAVE1_0 ((uint32_t)0x00000040) /*!< Bit 0 */ +#define DAC_CR_WAVE1_1 ((uint32_t)0x00000080) /*!< Bit 1 */ + +#define DAC_CR_MAMP1 ((uint32_t)0x00000F00) /*!< MAMP1[3:0] (DAC channel1 Mask/Amplitude selector) */ +#define DAC_CR_MAMP1_0 ((uint32_t)0x00000100) /*!< Bit 0 */ +#define DAC_CR_MAMP1_1 ((uint32_t)0x00000200) /*!< Bit 1 */ +#define DAC_CR_MAMP1_2 ((uint32_t)0x00000400) /*!< Bit 2 */ +#define DAC_CR_MAMP1_3 ((uint32_t)0x00000800) /*!< Bit 3 */ + +#define DAC_CR_DMAEN1 ((uint32_t)0x00001000) /*!< DAC channel1 DMA enable */ +#define DAC_CR_EN2 ((uint32_t)0x00010000) /*!< DAC channel2 enable */ +#define DAC_CR_BOFF2 ((uint32_t)0x00020000) /*!< DAC channel2 output buffer disable */ +#define DAC_CR_TEN2 ((uint32_t)0x00040000) /*!< DAC channel2 Trigger enable */ + +#define DAC_CR_TSEL2 ((uint32_t)0x00380000) /*!< TSEL2[2:0] (DAC channel2 Trigger selection) */ +#define DAC_CR_TSEL2_0 ((uint32_t)0x00080000) /*!< Bit 0 */ +#define DAC_CR_TSEL2_1 ((uint32_t)0x00100000) /*!< Bit 1 */ +#define DAC_CR_TSEL2_2 ((uint32_t)0x00200000) /*!< Bit 2 */ + +#define DAC_CR_WAVE2 ((uint32_t)0x00C00000) /*!< WAVE2[1:0] (DAC channel2 noise/triangle wave generation enable) */ +#define DAC_CR_WAVE2_0 ((uint32_t)0x00400000) /*!< Bit 0 */ +#define DAC_CR_WAVE2_1 ((uint32_t)0x00800000) /*!< Bit 1 */ + +#define DAC_CR_MAMP2 ((uint32_t)0x0F000000) /*!< MAMP2[3:0] (DAC channel2 Mask/Amplitude selector) */ +#define DAC_CR_MAMP2_0 ((uint32_t)0x01000000) /*!< Bit 0 */ +#define DAC_CR_MAMP2_1 ((uint32_t)0x02000000) /*!< Bit 1 */ +#define DAC_CR_MAMP2_2 ((uint32_t)0x04000000) /*!< Bit 2 */ +#define DAC_CR_MAMP2_3 ((uint32_t)0x08000000) /*!< Bit 3 */ + +#define DAC_CR_DMAEN2 ((uint32_t)0x10000000) /*!< DAC channel2 DMA enabled */ + +#if defined (STM32F10X_LD_VL) || defined (STM32F10X_MD_VL) || defined (STM32F10X_HD_VL) + #define DAC_CR_DMAUDRIE1 ((uint32_t)0x00002000) /*!< DAC channel1 DMA underrun interrupt enable */ + #define DAC_CR_DMAUDRIE2 ((uint32_t)0x20000000) /*!< DAC channel2 DMA underrun interrupt enable */ +#endif + +/***************** Bit definition for DAC_SWTRIGR register ******************/ +#define DAC_SWTRIGR_SWTRIG1 ((uint8_t)0x01) /*!< DAC channel1 software trigger */ +#define DAC_SWTRIGR_SWTRIG2 ((uint8_t)0x02) /*!< DAC channel2 software trigger */ + +/***************** Bit definition for DAC_DHR12R1 register ******************/ +#define DAC_DHR12R1_DACC1DHR ((uint16_t)0x0FFF) /*!< DAC channel1 12-bit Right aligned data */ + +/***************** Bit definition for DAC_DHR12L1 register ******************/ +#define DAC_DHR12L1_DACC1DHR ((uint16_t)0xFFF0) /*!< DAC channel1 12-bit Left aligned data */ + +/****************** Bit definition for DAC_DHR8R1 register ******************/ +#define DAC_DHR8R1_DACC1DHR ((uint8_t)0xFF) /*!< DAC channel1 8-bit Right aligned data */ + +/***************** Bit definition for DAC_DHR12R2 register ******************/ +#define DAC_DHR12R2_DACC2DHR ((uint16_t)0x0FFF) /*!< DAC channel2 12-bit Right aligned data */ + +/***************** Bit definition for DAC_DHR12L2 register ******************/ +#define DAC_DHR12L2_DACC2DHR ((uint16_t)0xFFF0) /*!< DAC channel2 12-bit Left aligned data */ + +/****************** Bit definition for DAC_DHR8R2 register ******************/ +#define DAC_DHR8R2_DACC2DHR ((uint8_t)0xFF) /*!< DAC channel2 8-bit Right aligned data */ + +/***************** Bit definition for DAC_DHR12RD register ******************/ +#define DAC_DHR12RD_DACC1DHR ((uint32_t)0x00000FFF) /*!< DAC channel1 12-bit Right aligned data */ +#define DAC_DHR12RD_DACC2DHR ((uint32_t)0x0FFF0000) /*!< DAC channel2 12-bit Right aligned data */ + +/***************** Bit definition for DAC_DHR12LD register ******************/ +#define DAC_DHR12LD_DACC1DHR ((uint32_t)0x0000FFF0) /*!< DAC channel1 12-bit Left aligned data */ +#define DAC_DHR12LD_DACC2DHR ((uint32_t)0xFFF00000) /*!< DAC channel2 12-bit Left aligned data */ + +/****************** Bit definition for DAC_DHR8RD register ******************/ +#define DAC_DHR8RD_DACC1DHR ((uint16_t)0x00FF) /*!< DAC channel1 8-bit Right aligned data */ +#define DAC_DHR8RD_DACC2DHR ((uint16_t)0xFF00) /*!< DAC channel2 8-bit Right aligned data */ + +/******************* Bit definition for DAC_DOR1 register *******************/ +#define DAC_DOR1_DACC1DOR ((uint16_t)0x0FFF) /*!< DAC channel1 data output */ + +/******************* Bit definition for DAC_DOR2 register *******************/ +#define DAC_DOR2_DACC2DOR ((uint16_t)0x0FFF) /*!< DAC channel2 data output */ + +/******************** Bit definition for DAC_SR register ********************/ +#define DAC_SR_DMAUDR1 ((uint32_t)0x00002000) /*!< DAC channel1 DMA underrun flag */ +#define DAC_SR_DMAUDR2 ((uint32_t)0x20000000) /*!< DAC channel2 DMA underrun flag */ + +/******************************************************************************/ +/* */ +/* CEC */ +/* */ +/******************************************************************************/ +/******************** Bit definition for CEC_CFGR register ******************/ +#define CEC_CFGR_PE ((uint16_t)0x0001) /*!< Peripheral Enable */ +#define CEC_CFGR_IE ((uint16_t)0x0002) /*!< Interrupt Enable */ +#define CEC_CFGR_BTEM ((uint16_t)0x0004) /*!< Bit Timing Error Mode */ +#define CEC_CFGR_BPEM ((uint16_t)0x0008) /*!< Bit Period Error Mode */ + +/******************** Bit definition for CEC_OAR register ******************/ +#define CEC_OAR_OA ((uint16_t)0x000F) /*!< OA[3:0]: Own Address */ +#define CEC_OAR_OA_0 ((uint16_t)0x0001) /*!< Bit 0 */ +#define CEC_OAR_OA_1 ((uint16_t)0x0002) /*!< Bit 1 */ +#define CEC_OAR_OA_2 ((uint16_t)0x0004) /*!< Bit 2 */ +#define CEC_OAR_OA_3 ((uint16_t)0x0008) /*!< Bit 3 */ + +/******************** Bit definition for CEC_PRES register ******************/ +#define CEC_PRES_PRES ((uint16_t)0x3FFF) /*!< Prescaler Counter Value */ + +/******************** Bit definition for CEC_ESR register ******************/ +#define CEC_ESR_BTE ((uint16_t)0x0001) /*!< Bit Timing Error */ +#define CEC_ESR_BPE ((uint16_t)0x0002) /*!< Bit Period Error */ +#define CEC_ESR_RBTFE ((uint16_t)0x0004) /*!< Rx Block Transfer Finished Error */ +#define CEC_ESR_SBE ((uint16_t)0x0008) /*!< Start Bit Error */ +#define CEC_ESR_ACKE ((uint16_t)0x0010) /*!< Block Acknowledge Error */ +#define CEC_ESR_LINE ((uint16_t)0x0020) /*!< Line Error */ +#define CEC_ESR_TBTFE ((uint16_t)0x0040) /*!< Tx Block Transfer Finished Error */ + +/******************** Bit definition for CEC_CSR register ******************/ +#define CEC_CSR_TSOM ((uint16_t)0x0001) /*!< Tx Start Of Message */ +#define CEC_CSR_TEOM ((uint16_t)0x0002) /*!< Tx End Of Message */ +#define CEC_CSR_TERR ((uint16_t)0x0004) /*!< Tx Error */ +#define CEC_CSR_TBTRF ((uint16_t)0x0008) /*!< Tx Byte Transfer Request or Block Transfer Finished */ +#define CEC_CSR_RSOM ((uint16_t)0x0010) /*!< Rx Start Of Message */ +#define CEC_CSR_REOM ((uint16_t)0x0020) /*!< Rx End Of Message */ +#define CEC_CSR_RERR ((uint16_t)0x0040) /*!< Rx Error */ +#define CEC_CSR_RBTF ((uint16_t)0x0080) /*!< Rx Block Transfer Finished */ + +/******************** Bit definition for CEC_TXD register ******************/ +#define CEC_TXD_TXD ((uint16_t)0x00FF) /*!< Tx Data register */ + +/******************** Bit definition for CEC_RXD register ******************/ +#define CEC_RXD_RXD ((uint16_t)0x00FF) /*!< Rx Data register */ + +/******************************************************************************/ +/* */ +/* TIM */ +/* */ +/******************************************************************************/ + +/******************* Bit definition for TIM_CR1 register ********************/ +#define TIM_CR1_CEN ((uint16_t)0x0001) /*!< Counter enable */ +#define TIM_CR1_UDIS ((uint16_t)0x0002) /*!< Update disable */ +#define TIM_CR1_URS ((uint16_t)0x0004) /*!< Update request source */ +#define TIM_CR1_OPM ((uint16_t)0x0008) /*!< One pulse mode */ +#define TIM_CR1_DIR ((uint16_t)0x0010) /*!< Direction */ + +#define TIM_CR1_CMS ((uint16_t)0x0060) /*!< CMS[1:0] bits (Center-aligned mode selection) */ +#define TIM_CR1_CMS_0 ((uint16_t)0x0020) /*!< Bit 0 */ +#define TIM_CR1_CMS_1 ((uint16_t)0x0040) /*!< Bit 1 */ + +#define TIM_CR1_ARPE ((uint16_t)0x0080) /*!< Auto-reload preload enable */ + +#define TIM_CR1_CKD ((uint16_t)0x0300) /*!< CKD[1:0] bits (clock division) */ +#define TIM_CR1_CKD_0 ((uint16_t)0x0100) /*!< Bit 0 */ +#define TIM_CR1_CKD_1 ((uint16_t)0x0200) /*!< Bit 1 */ + +/******************* Bit definition for TIM_CR2 register ********************/ +#define TIM_CR2_CCPC ((uint16_t)0x0001) /*!< Capture/Compare Preloaded Control */ +#define TIM_CR2_CCUS ((uint16_t)0x0004) /*!< Capture/Compare Control Update Selection */ +#define TIM_CR2_CCDS ((uint16_t)0x0008) /*!< Capture/Compare DMA Selection */ + +#define TIM_CR2_MMS ((uint16_t)0x0070) /*!< MMS[2:0] bits (Master Mode Selection) */ +#define TIM_CR2_MMS_0 ((uint16_t)0x0010) /*!< Bit 0 */ +#define TIM_CR2_MMS_1 ((uint16_t)0x0020) /*!< Bit 1 */ +#define TIM_CR2_MMS_2 ((uint16_t)0x0040) /*!< Bit 2 */ + +#define TIM_CR2_TI1S ((uint16_t)0x0080) /*!< TI1 Selection */ +#define TIM_CR2_OIS1 ((uint16_t)0x0100) /*!< Output Idle state 1 (OC1 output) */ +#define TIM_CR2_OIS1N ((uint16_t)0x0200) /*!< Output Idle state 1 (OC1N output) */ +#define TIM_CR2_OIS2 ((uint16_t)0x0400) /*!< Output Idle state 2 (OC2 output) */ +#define TIM_CR2_OIS2N ((uint16_t)0x0800) /*!< Output Idle state 2 (OC2N output) */ +#define TIM_CR2_OIS3 ((uint16_t)0x1000) /*!< Output Idle state 3 (OC3 output) */ +#define TIM_CR2_OIS3N ((uint16_t)0x2000) /*!< Output Idle state 3 (OC3N output) */ +#define TIM_CR2_OIS4 ((uint16_t)0x4000) /*!< Output Idle state 4 (OC4 output) */ + +/******************* Bit definition for TIM_SMCR register *******************/ +#define TIM_SMCR_SMS ((uint16_t)0x0007) /*!< SMS[2:0] bits (Slave mode selection) */ +#define TIM_SMCR_SMS_0 ((uint16_t)0x0001) /*!< Bit 0 */ +#define TIM_SMCR_SMS_1 ((uint16_t)0x0002) /*!< Bit 1 */ +#define TIM_SMCR_SMS_2 ((uint16_t)0x0004) /*!< Bit 2 */ + +#define TIM_SMCR_TS ((uint16_t)0x0070) /*!< TS[2:0] bits (Trigger selection) */ +#define TIM_SMCR_TS_0 ((uint16_t)0x0010) /*!< Bit 0 */ +#define TIM_SMCR_TS_1 ((uint16_t)0x0020) /*!< Bit 1 */ +#define TIM_SMCR_TS_2 ((uint16_t)0x0040) /*!< Bit 2 */ + +#define TIM_SMCR_MSM ((uint16_t)0x0080) /*!< Master/slave mode */ + +#define TIM_SMCR_ETF ((uint16_t)0x0F00) /*!< ETF[3:0] bits (External trigger filter) */ +#define TIM_SMCR_ETF_0 ((uint16_t)0x0100) /*!< Bit 0 */ +#define TIM_SMCR_ETF_1 ((uint16_t)0x0200) /*!< Bit 1 */ +#define TIM_SMCR_ETF_2 ((uint16_t)0x0400) /*!< Bit 2 */ +#define TIM_SMCR_ETF_3 ((uint16_t)0x0800) /*!< Bit 3 */ + +#define TIM_SMCR_ETPS ((uint16_t)0x3000) /*!< ETPS[1:0] bits (External trigger prescaler) */ +#define TIM_SMCR_ETPS_0 ((uint16_t)0x1000) /*!< Bit 0 */ +#define TIM_SMCR_ETPS_1 ((uint16_t)0x2000) /*!< Bit 1 */ + +#define TIM_SMCR_ECE ((uint16_t)0x4000) /*!< External clock enable */ +#define TIM_SMCR_ETP ((uint16_t)0x8000) /*!< External trigger polarity */ + +/******************* Bit definition for TIM_DIER register *******************/ +#define TIM_DIER_UIE ((uint16_t)0x0001) /*!< Update interrupt enable */ +#define TIM_DIER_CC1IE ((uint16_t)0x0002) /*!< Capture/Compare 1 interrupt enable */ +#define TIM_DIER_CC2IE ((uint16_t)0x0004) /*!< Capture/Compare 2 interrupt enable */ +#define TIM_DIER_CC3IE ((uint16_t)0x0008) /*!< Capture/Compare 3 interrupt enable */ +#define TIM_DIER_CC4IE ((uint16_t)0x0010) /*!< Capture/Compare 4 interrupt enable */ +#define TIM_DIER_COMIE ((uint16_t)0x0020) /*!< COM interrupt enable */ +#define TIM_DIER_TIE ((uint16_t)0x0040) /*!< Trigger interrupt enable */ +#define TIM_DIER_BIE ((uint16_t)0x0080) /*!< Break interrupt enable */ +#define TIM_DIER_UDE ((uint16_t)0x0100) /*!< Update DMA request enable */ +#define TIM_DIER_CC1DE ((uint16_t)0x0200) /*!< Capture/Compare 1 DMA request enable */ +#define TIM_DIER_CC2DE ((uint16_t)0x0400) /*!< Capture/Compare 2 DMA request enable */ +#define TIM_DIER_CC3DE ((uint16_t)0x0800) /*!< Capture/Compare 3 DMA request enable */ +#define TIM_DIER_CC4DE ((uint16_t)0x1000) /*!< Capture/Compare 4 DMA request enable */ +#define TIM_DIER_COMDE ((uint16_t)0x2000) /*!< COM DMA request enable */ +#define TIM_DIER_TDE ((uint16_t)0x4000) /*!< Trigger DMA request enable */ + +/******************** Bit definition for TIM_SR register ********************/ +#define TIM_SR_UIF ((uint16_t)0x0001) /*!< Update interrupt Flag */ +#define TIM_SR_CC1IF ((uint16_t)0x0002) /*!< Capture/Compare 1 interrupt Flag */ +#define TIM_SR_CC2IF ((uint16_t)0x0004) /*!< Capture/Compare 2 interrupt Flag */ +#define TIM_SR_CC3IF ((uint16_t)0x0008) /*!< Capture/Compare 3 interrupt Flag */ +#define TIM_SR_CC4IF ((uint16_t)0x0010) /*!< Capture/Compare 4 interrupt Flag */ +#define TIM_SR_COMIF ((uint16_t)0x0020) /*!< COM interrupt Flag */ +#define TIM_SR_TIF ((uint16_t)0x0040) /*!< Trigger interrupt Flag */ +#define TIM_SR_BIF ((uint16_t)0x0080) /*!< Break interrupt Flag */ +#define TIM_SR_CC1OF ((uint16_t)0x0200) /*!< Capture/Compare 1 Overcapture Flag */ +#define TIM_SR_CC2OF ((uint16_t)0x0400) /*!< Capture/Compare 2 Overcapture Flag */ +#define TIM_SR_CC3OF ((uint16_t)0x0800) /*!< Capture/Compare 3 Overcapture Flag */ +#define TIM_SR_CC4OF ((uint16_t)0x1000) /*!< Capture/Compare 4 Overcapture Flag */ + +/******************* Bit definition for TIM_EGR register ********************/ +#define TIM_EGR_UG ((uint8_t)0x01) /*!< Update Generation */ +#define TIM_EGR_CC1G ((uint8_t)0x02) /*!< Capture/Compare 1 Generation */ +#define TIM_EGR_CC2G ((uint8_t)0x04) /*!< Capture/Compare 2 Generation */ +#define TIM_EGR_CC3G ((uint8_t)0x08) /*!< Capture/Compare 3 Generation */ +#define TIM_EGR_CC4G ((uint8_t)0x10) /*!< Capture/Compare 4 Generation */ +#define TIM_EGR_COMG ((uint8_t)0x20) /*!< Capture/Compare Control Update Generation */ +#define TIM_EGR_TG ((uint8_t)0x40) /*!< Trigger Generation */ +#define TIM_EGR_BG ((uint8_t)0x80) /*!< Break Generation */ + +/****************** Bit definition for TIM_CCMR1 register *******************/ +#define TIM_CCMR1_CC1S ((uint16_t)0x0003) /*!< CC1S[1:0] bits (Capture/Compare 1 Selection) */ +#define TIM_CCMR1_CC1S_0 ((uint16_t)0x0001) /*!< Bit 0 */ +#define TIM_CCMR1_CC1S_1 ((uint16_t)0x0002) /*!< Bit 1 */ + +#define TIM_CCMR1_OC1FE ((uint16_t)0x0004) /*!< Output Compare 1 Fast enable */ +#define TIM_CCMR1_OC1PE ((uint16_t)0x0008) /*!< Output Compare 1 Preload enable */ + +#define TIM_CCMR1_OC1M ((uint16_t)0x0070) /*!< OC1M[2:0] bits (Output Compare 1 Mode) */ +#define TIM_CCMR1_OC1M_0 ((uint16_t)0x0010) /*!< Bit 0 */ +#define TIM_CCMR1_OC1M_1 ((uint16_t)0x0020) /*!< Bit 1 */ +#define TIM_CCMR1_OC1M_2 ((uint16_t)0x0040) /*!< Bit 2 */ + +#define TIM_CCMR1_OC1CE ((uint16_t)0x0080) /*!< Output Compare 1Clear Enable */ + +#define TIM_CCMR1_CC2S ((uint16_t)0x0300) /*!< CC2S[1:0] bits (Capture/Compare 2 Selection) */ +#define TIM_CCMR1_CC2S_0 ((uint16_t)0x0100) /*!< Bit 0 */ +#define TIM_CCMR1_CC2S_1 ((uint16_t)0x0200) /*!< Bit 1 */ + +#define TIM_CCMR1_OC2FE ((uint16_t)0x0400) /*!< Output Compare 2 Fast enable */ +#define TIM_CCMR1_OC2PE ((uint16_t)0x0800) /*!< Output Compare 2 Preload enable */ + +#define TIM_CCMR1_OC2M ((uint16_t)0x7000) /*!< OC2M[2:0] bits (Output Compare 2 Mode) */ +#define TIM_CCMR1_OC2M_0 ((uint16_t)0x1000) /*!< Bit 0 */ +#define TIM_CCMR1_OC2M_1 ((uint16_t)0x2000) /*!< Bit 1 */ +#define TIM_CCMR1_OC2M_2 ((uint16_t)0x4000) /*!< Bit 2 */ + +#define TIM_CCMR1_OC2CE ((uint16_t)0x8000) /*!< Output Compare 2 Clear Enable */ + +/*----------------------------------------------------------------------------*/ + +#define TIM_CCMR1_IC1PSC ((uint16_t)0x000C) /*!< IC1PSC[1:0] bits (Input Capture 1 Prescaler) */ +#define TIM_CCMR1_IC1PSC_0 ((uint16_t)0x0004) /*!< Bit 0 */ +#define TIM_CCMR1_IC1PSC_1 ((uint16_t)0x0008) /*!< Bit 1 */ + +#define TIM_CCMR1_IC1F ((uint16_t)0x00F0) /*!< IC1F[3:0] bits (Input Capture 1 Filter) */ +#define TIM_CCMR1_IC1F_0 ((uint16_t)0x0010) /*!< Bit 0 */ +#define TIM_CCMR1_IC1F_1 ((uint16_t)0x0020) /*!< Bit 1 */ +#define TIM_CCMR1_IC1F_2 ((uint16_t)0x0040) /*!< Bit 2 */ +#define TIM_CCMR1_IC1F_3 ((uint16_t)0x0080) /*!< Bit 3 */ + +#define TIM_CCMR1_IC2PSC ((uint16_t)0x0C00) /*!< IC2PSC[1:0] bits (Input Capture 2 Prescaler) */ +#define TIM_CCMR1_IC2PSC_0 ((uint16_t)0x0400) /*!< Bit 0 */ +#define TIM_CCMR1_IC2PSC_1 ((uint16_t)0x0800) /*!< Bit 1 */ + +#define TIM_CCMR1_IC2F ((uint16_t)0xF000) /*!< IC2F[3:0] bits (Input Capture 2 Filter) */ +#define TIM_CCMR1_IC2F_0 ((uint16_t)0x1000) /*!< Bit 0 */ +#define TIM_CCMR1_IC2F_1 ((uint16_t)0x2000) /*!< Bit 1 */ +#define TIM_CCMR1_IC2F_2 ((uint16_t)0x4000) /*!< Bit 2 */ +#define TIM_CCMR1_IC2F_3 ((uint16_t)0x8000) /*!< Bit 3 */ + +/****************** Bit definition for TIM_CCMR2 register *******************/ +#define TIM_CCMR2_CC3S ((uint16_t)0x0003) /*!< CC3S[1:0] bits (Capture/Compare 3 Selection) */ +#define TIM_CCMR2_CC3S_0 ((uint16_t)0x0001) /*!< Bit 0 */ +#define TIM_CCMR2_CC3S_1 ((uint16_t)0x0002) /*!< Bit 1 */ + +#define TIM_CCMR2_OC3FE ((uint16_t)0x0004) /*!< Output Compare 3 Fast enable */ +#define TIM_CCMR2_OC3PE ((uint16_t)0x0008) /*!< Output Compare 3 Preload enable */ + +#define TIM_CCMR2_OC3M ((uint16_t)0x0070) /*!< OC3M[2:0] bits (Output Compare 3 Mode) */ +#define TIM_CCMR2_OC3M_0 ((uint16_t)0x0010) /*!< Bit 0 */ +#define TIM_CCMR2_OC3M_1 ((uint16_t)0x0020) /*!< Bit 1 */ +#define TIM_CCMR2_OC3M_2 ((uint16_t)0x0040) /*!< Bit 2 */ + +#define TIM_CCMR2_OC3CE ((uint16_t)0x0080) /*!< Output Compare 3 Clear Enable */ + +#define TIM_CCMR2_CC4S ((uint16_t)0x0300) /*!< CC4S[1:0] bits (Capture/Compare 4 Selection) */ +#define TIM_CCMR2_CC4S_0 ((uint16_t)0x0100) /*!< Bit 0 */ +#define TIM_CCMR2_CC4S_1 ((uint16_t)0x0200) /*!< Bit 1 */ + +#define TIM_CCMR2_OC4FE ((uint16_t)0x0400) /*!< Output Compare 4 Fast enable */ +#define TIM_CCMR2_OC4PE ((uint16_t)0x0800) /*!< Output Compare 4 Preload enable */ + +#define TIM_CCMR2_OC4M ((uint16_t)0x7000) /*!< OC4M[2:0] bits (Output Compare 4 Mode) */ +#define TIM_CCMR2_OC4M_0 ((uint16_t)0x1000) /*!< Bit 0 */ +#define TIM_CCMR2_OC4M_1 ((uint16_t)0x2000) /*!< Bit 1 */ +#define TIM_CCMR2_OC4M_2 ((uint16_t)0x4000) /*!< Bit 2 */ + +#define TIM_CCMR2_OC4CE ((uint16_t)0x8000) /*!< Output Compare 4 Clear Enable */ + +/*----------------------------------------------------------------------------*/ + +#define TIM_CCMR2_IC3PSC ((uint16_t)0x000C) /*!< IC3PSC[1:0] bits (Input Capture 3 Prescaler) */ +#define TIM_CCMR2_IC3PSC_0 ((uint16_t)0x0004) /*!< Bit 0 */ +#define TIM_CCMR2_IC3PSC_1 ((uint16_t)0x0008) /*!< Bit 1 */ + +#define TIM_CCMR2_IC3F ((uint16_t)0x00F0) /*!< IC3F[3:0] bits (Input Capture 3 Filter) */ +#define TIM_CCMR2_IC3F_0 ((uint16_t)0x0010) /*!< Bit 0 */ +#define TIM_CCMR2_IC3F_1 ((uint16_t)0x0020) /*!< Bit 1 */ +#define TIM_CCMR2_IC3F_2 ((uint16_t)0x0040) /*!< Bit 2 */ +#define TIM_CCMR2_IC3F_3 ((uint16_t)0x0080) /*!< Bit 3 */ + +#define TIM_CCMR2_IC4PSC ((uint16_t)0x0C00) /*!< IC4PSC[1:0] bits (Input Capture 4 Prescaler) */ +#define TIM_CCMR2_IC4PSC_0 ((uint16_t)0x0400) /*!< Bit 0 */ +#define TIM_CCMR2_IC4PSC_1 ((uint16_t)0x0800) /*!< Bit 1 */ + +#define TIM_CCMR2_IC4F ((uint16_t)0xF000) /*!< IC4F[3:0] bits (Input Capture 4 Filter) */ +#define TIM_CCMR2_IC4F_0 ((uint16_t)0x1000) /*!< Bit 0 */ +#define TIM_CCMR2_IC4F_1 ((uint16_t)0x2000) /*!< Bit 1 */ +#define TIM_CCMR2_IC4F_2 ((uint16_t)0x4000) /*!< Bit 2 */ +#define TIM_CCMR2_IC4F_3 ((uint16_t)0x8000) /*!< Bit 3 */ + +/******************* Bit definition for TIM_CCER register *******************/ +#define TIM_CCER_CC1E ((uint16_t)0x0001) /*!< Capture/Compare 1 output enable */ +#define TIM_CCER_CC1P ((uint16_t)0x0002) /*!< Capture/Compare 1 output Polarity */ +#define TIM_CCER_CC1NE ((uint16_t)0x0004) /*!< Capture/Compare 1 Complementary output enable */ +#define TIM_CCER_CC1NP ((uint16_t)0x0008) /*!< Capture/Compare 1 Complementary output Polarity */ +#define TIM_CCER_CC2E ((uint16_t)0x0010) /*!< Capture/Compare 2 output enable */ +#define TIM_CCER_CC2P ((uint16_t)0x0020) /*!< Capture/Compare 2 output Polarity */ +#define TIM_CCER_CC2NE ((uint16_t)0x0040) /*!< Capture/Compare 2 Complementary output enable */ +#define TIM_CCER_CC2NP ((uint16_t)0x0080) /*!< Capture/Compare 2 Complementary output Polarity */ +#define TIM_CCER_CC3E ((uint16_t)0x0100) /*!< Capture/Compare 3 output enable */ +#define TIM_CCER_CC3P ((uint16_t)0x0200) /*!< Capture/Compare 3 output Polarity */ +#define TIM_CCER_CC3NE ((uint16_t)0x0400) /*!< Capture/Compare 3 Complementary output enable */ +#define TIM_CCER_CC3NP ((uint16_t)0x0800) /*!< Capture/Compare 3 Complementary output Polarity */ +#define TIM_CCER_CC4E ((uint16_t)0x1000) /*!< Capture/Compare 4 output enable */ +#define TIM_CCER_CC4P ((uint16_t)0x2000) /*!< Capture/Compare 4 output Polarity */ +#define TIM_CCER_CC4NP ((uint16_t)0x8000) /*!< Capture/Compare 4 Complementary output Polarity */ + +/******************* Bit definition for TIM_CNT register ********************/ +#define TIM_CNT_CNT ((uint16_t)0xFFFF) /*!< Counter Value */ + +/******************* Bit definition for TIM_PSC register ********************/ +#define TIM_PSC_PSC ((uint16_t)0xFFFF) /*!< Prescaler Value */ + +/******************* Bit definition for TIM_ARR register ********************/ +#define TIM_ARR_ARR ((uint16_t)0xFFFF) /*!< actual auto-reload Value */ + +/******************* Bit definition for TIM_RCR register ********************/ +#define TIM_RCR_REP ((uint8_t)0xFF) /*!< Repetition Counter Value */ + +/******************* Bit definition for TIM_CCR1 register *******************/ +#define TIM_CCR1_CCR1 ((uint16_t)0xFFFF) /*!< Capture/Compare 1 Value */ + +/******************* Bit definition for TIM_CCR2 register *******************/ +#define TIM_CCR2_CCR2 ((uint16_t)0xFFFF) /*!< Capture/Compare 2 Value */ + +/******************* Bit definition for TIM_CCR3 register *******************/ +#define TIM_CCR3_CCR3 ((uint16_t)0xFFFF) /*!< Capture/Compare 3 Value */ + +/******************* Bit definition for TIM_CCR4 register *******************/ +#define TIM_CCR4_CCR4 ((uint16_t)0xFFFF) /*!< Capture/Compare 4 Value */ + +/******************* Bit definition for TIM_BDTR register *******************/ +#define TIM_BDTR_DTG ((uint16_t)0x00FF) /*!< DTG[0:7] bits (Dead-Time Generator set-up) */ +#define TIM_BDTR_DTG_0 ((uint16_t)0x0001) /*!< Bit 0 */ +#define TIM_BDTR_DTG_1 ((uint16_t)0x0002) /*!< Bit 1 */ +#define TIM_BDTR_DTG_2 ((uint16_t)0x0004) /*!< Bit 2 */ +#define TIM_BDTR_DTG_3 ((uint16_t)0x0008) /*!< Bit 3 */ +#define TIM_BDTR_DTG_4 ((uint16_t)0x0010) /*!< Bit 4 */ +#define TIM_BDTR_DTG_5 ((uint16_t)0x0020) /*!< Bit 5 */ +#define TIM_BDTR_DTG_6 ((uint16_t)0x0040) /*!< Bit 6 */ +#define TIM_BDTR_DTG_7 ((uint16_t)0x0080) /*!< Bit 7 */ + +#define TIM_BDTR_LOCK ((uint16_t)0x0300) /*!< LOCK[1:0] bits (Lock Configuration) */ +#define TIM_BDTR_LOCK_0 ((uint16_t)0x0100) /*!< Bit 0 */ +#define TIM_BDTR_LOCK_1 ((uint16_t)0x0200) /*!< Bit 1 */ + +#define TIM_BDTR_OSSI ((uint16_t)0x0400) /*!< Off-State Selection for Idle mode */ +#define TIM_BDTR_OSSR ((uint16_t)0x0800) /*!< Off-State Selection for Run mode */ +#define TIM_BDTR_BKE ((uint16_t)0x1000) /*!< Break enable */ +#define TIM_BDTR_BKP ((uint16_t)0x2000) /*!< Break Polarity */ +#define TIM_BDTR_AOE ((uint16_t)0x4000) /*!< Automatic Output enable */ +#define TIM_BDTR_MOE ((uint16_t)0x8000) /*!< Main Output enable */ + +/******************* Bit definition for TIM_DCR register ********************/ +#define TIM_DCR_DBA ((uint16_t)0x001F) /*!< DBA[4:0] bits (DMA Base Address) */ +#define TIM_DCR_DBA_0 ((uint16_t)0x0001) /*!< Bit 0 */ +#define TIM_DCR_DBA_1 ((uint16_t)0x0002) /*!< Bit 1 */ +#define TIM_DCR_DBA_2 ((uint16_t)0x0004) /*!< Bit 2 */ +#define TIM_DCR_DBA_3 ((uint16_t)0x0008) /*!< Bit 3 */ +#define TIM_DCR_DBA_4 ((uint16_t)0x0010) /*!< Bit 4 */ + +#define TIM_DCR_DBL ((uint16_t)0x1F00) /*!< DBL[4:0] bits (DMA Burst Length) */ +#define TIM_DCR_DBL_0 ((uint16_t)0x0100) /*!< Bit 0 */ +#define TIM_DCR_DBL_1 ((uint16_t)0x0200) /*!< Bit 1 */ +#define TIM_DCR_DBL_2 ((uint16_t)0x0400) /*!< Bit 2 */ +#define TIM_DCR_DBL_3 ((uint16_t)0x0800) /*!< Bit 3 */ +#define TIM_DCR_DBL_4 ((uint16_t)0x1000) /*!< Bit 4 */ + +/******************* Bit definition for TIM_DMAR register *******************/ +#define TIM_DMAR_DMAB ((uint16_t)0xFFFF) /*!< DMA register for burst accesses */ + +/******************************************************************************/ +/* */ +/* Real-Time Clock */ +/* */ +/******************************************************************************/ + +/******************* Bit definition for RTC_CRH register ********************/ +#define RTC_CRH_SECIE ((uint8_t)0x01) /*!< Second Interrupt Enable */ +#define RTC_CRH_ALRIE ((uint8_t)0x02) /*!< Alarm Interrupt Enable */ +#define RTC_CRH_OWIE ((uint8_t)0x04) /*!< OverfloW Interrupt Enable */ + +/******************* Bit definition for RTC_CRL register ********************/ +#define RTC_CRL_SECF ((uint8_t)0x01) /*!< Second Flag */ +#define RTC_CRL_ALRF ((uint8_t)0x02) /*!< Alarm Flag */ +#define RTC_CRL_OWF ((uint8_t)0x04) /*!< OverfloW Flag */ +#define RTC_CRL_RSF ((uint8_t)0x08) /*!< Registers Synchronized Flag */ +#define RTC_CRL_CNF ((uint8_t)0x10) /*!< Configuration Flag */ +#define RTC_CRL_RTOFF ((uint8_t)0x20) /*!< RTC operation OFF */ + +/******************* Bit definition for RTC_PRLH register *******************/ +#define RTC_PRLH_PRL ((uint16_t)0x000F) /*!< RTC Prescaler Reload Value High */ + +/******************* Bit definition for RTC_PRLL register *******************/ +#define RTC_PRLL_PRL ((uint16_t)0xFFFF) /*!< RTC Prescaler Reload Value Low */ + +/******************* Bit definition for RTC_DIVH register *******************/ +#define RTC_DIVH_RTC_DIV ((uint16_t)0x000F) /*!< RTC Clock Divider High */ + +/******************* Bit definition for RTC_DIVL register *******************/ +#define RTC_DIVL_RTC_DIV ((uint16_t)0xFFFF) /*!< RTC Clock Divider Low */ + +/******************* Bit definition for RTC_CNTH register *******************/ +#define RTC_CNTH_RTC_CNT ((uint16_t)0xFFFF) /*!< RTC Counter High */ + +/******************* Bit definition for RTC_CNTL register *******************/ +#define RTC_CNTL_RTC_CNT ((uint16_t)0xFFFF) /*!< RTC Counter Low */ + +/******************* Bit definition for RTC_ALRH register *******************/ +#define RTC_ALRH_RTC_ALR ((uint16_t)0xFFFF) /*!< RTC Alarm High */ + +/******************* Bit definition for RTC_ALRL register *******************/ +#define RTC_ALRL_RTC_ALR ((uint16_t)0xFFFF) /*!< RTC Alarm Low */ + +/******************************************************************************/ +/* */ +/* Independent WATCHDOG */ +/* */ +/******************************************************************************/ + +/******************* Bit definition for IWDG_KR register ********************/ +#define IWDG_KR_KEY ((uint16_t)0xFFFF) /*!< Key value (write only, read 0000h) */ + +/******************* Bit definition for IWDG_PR register ********************/ +#define IWDG_PR_PR ((uint8_t)0x07) /*!< PR[2:0] (Prescaler divider) */ +#define IWDG_PR_PR_0 ((uint8_t)0x01) /*!< Bit 0 */ +#define IWDG_PR_PR_1 ((uint8_t)0x02) /*!< Bit 1 */ +#define IWDG_PR_PR_2 ((uint8_t)0x04) /*!< Bit 2 */ + +/******************* Bit definition for IWDG_RLR register *******************/ +#define IWDG_RLR_RL ((uint16_t)0x0FFF) /*!< Watchdog counter reload value */ + +/******************* Bit definition for IWDG_SR register ********************/ +#define IWDG_SR_PVU ((uint8_t)0x01) /*!< Watchdog prescaler value update */ +#define IWDG_SR_RVU ((uint8_t)0x02) /*!< Watchdog counter reload value update */ + +/******************************************************************************/ +/* */ +/* Window WATCHDOG */ +/* */ +/******************************************************************************/ + +/******************* Bit definition for WWDG_CR register ********************/ +#define WWDG_CR_T ((uint8_t)0x7F) /*!< T[6:0] bits (7-Bit counter (MSB to LSB)) */ +#define WWDG_CR_T0 ((uint8_t)0x01) /*!< Bit 0 */ +#define WWDG_CR_T1 ((uint8_t)0x02) /*!< Bit 1 */ +#define WWDG_CR_T2 ((uint8_t)0x04) /*!< Bit 2 */ +#define WWDG_CR_T3 ((uint8_t)0x08) /*!< Bit 3 */ +#define WWDG_CR_T4 ((uint8_t)0x10) /*!< Bit 4 */ +#define WWDG_CR_T5 ((uint8_t)0x20) /*!< Bit 5 */ +#define WWDG_CR_T6 ((uint8_t)0x40) /*!< Bit 6 */ + +#define WWDG_CR_WDGA ((uint8_t)0x80) /*!< Activation bit */ + +/******************* Bit definition for WWDG_CFR register *******************/ +#define WWDG_CFR_W ((uint16_t)0x007F) /*!< W[6:0] bits (7-bit window value) */ +#define WWDG_CFR_W0 ((uint16_t)0x0001) /*!< Bit 0 */ +#define WWDG_CFR_W1 ((uint16_t)0x0002) /*!< Bit 1 */ +#define WWDG_CFR_W2 ((uint16_t)0x0004) /*!< Bit 2 */ +#define WWDG_CFR_W3 ((uint16_t)0x0008) /*!< Bit 3 */ +#define WWDG_CFR_W4 ((uint16_t)0x0010) /*!< Bit 4 */ +#define WWDG_CFR_W5 ((uint16_t)0x0020) /*!< Bit 5 */ +#define WWDG_CFR_W6 ((uint16_t)0x0040) /*!< Bit 6 */ + +#define WWDG_CFR_WDGTB ((uint16_t)0x0180) /*!< WDGTB[1:0] bits (Timer Base) */ +#define WWDG_CFR_WDGTB0 ((uint16_t)0x0080) /*!< Bit 0 */ +#define WWDG_CFR_WDGTB1 ((uint16_t)0x0100) /*!< Bit 1 */ + +#define WWDG_CFR_EWI ((uint16_t)0x0200) /*!< Early Wakeup Interrupt */ + +/******************* Bit definition for WWDG_SR register ********************/ +#define WWDG_SR_EWIF ((uint8_t)0x01) /*!< Early Wakeup Interrupt Flag */ + +/******************************************************************************/ +/* */ +/* Flexible Static Memory Controller */ +/* */ +/******************************************************************************/ + +/****************** Bit definition for FSMC_BCR1 register *******************/ +#define FSMC_BCR1_MBKEN ((uint32_t)0x00000001) /*!< Memory bank enable bit */ +#define FSMC_BCR1_MUXEN ((uint32_t)0x00000002) /*!< Address/data multiplexing enable bit */ + +#define FSMC_BCR1_MTYP ((uint32_t)0x0000000C) /*!< MTYP[1:0] bits (Memory type) */ +#define FSMC_BCR1_MTYP_0 ((uint32_t)0x00000004) /*!< Bit 0 */ +#define FSMC_BCR1_MTYP_1 ((uint32_t)0x00000008) /*!< Bit 1 */ + +#define FSMC_BCR1_MWID ((uint32_t)0x00000030) /*!< MWID[1:0] bits (Memory data bus width) */ +#define FSMC_BCR1_MWID_0 ((uint32_t)0x00000010) /*!< Bit 0 */ +#define FSMC_BCR1_MWID_1 ((uint32_t)0x00000020) /*!< Bit 1 */ + +#define FSMC_BCR1_FACCEN ((uint32_t)0x00000040) /*!< Flash access enable */ +#define FSMC_BCR1_BURSTEN ((uint32_t)0x00000100) /*!< Burst enable bit */ +#define FSMC_BCR1_WAITPOL ((uint32_t)0x00000200) /*!< Wait signal polarity bit */ +#define FSMC_BCR1_WRAPMOD ((uint32_t)0x00000400) /*!< Wrapped burst mode support */ +#define FSMC_BCR1_WAITCFG ((uint32_t)0x00000800) /*!< Wait timing configuration */ +#define FSMC_BCR1_WREN ((uint32_t)0x00001000) /*!< Write enable bit */ +#define FSMC_BCR1_WAITEN ((uint32_t)0x00002000) /*!< Wait enable bit */ +#define FSMC_BCR1_EXTMOD ((uint32_t)0x00004000) /*!< Extended mode enable */ +#define FSMC_BCR1_ASYNCWAIT ((uint32_t)0x00008000) /*!< Asynchronous wait */ +#define FSMC_BCR1_CBURSTRW ((uint32_t)0x00080000) /*!< Write burst enable */ + +/****************** Bit definition for FSMC_BCR2 register *******************/ +#define FSMC_BCR2_MBKEN ((uint32_t)0x00000001) /*!< Memory bank enable bit */ +#define FSMC_BCR2_MUXEN ((uint32_t)0x00000002) /*!< Address/data multiplexing enable bit */ + +#define FSMC_BCR2_MTYP ((uint32_t)0x0000000C) /*!< MTYP[1:0] bits (Memory type) */ +#define FSMC_BCR2_MTYP_0 ((uint32_t)0x00000004) /*!< Bit 0 */ +#define FSMC_BCR2_MTYP_1 ((uint32_t)0x00000008) /*!< Bit 1 */ + +#define FSMC_BCR2_MWID ((uint32_t)0x00000030) /*!< MWID[1:0] bits (Memory data bus width) */ +#define FSMC_BCR2_MWID_0 ((uint32_t)0x00000010) /*!< Bit 0 */ +#define FSMC_BCR2_MWID_1 ((uint32_t)0x00000020) /*!< Bit 1 */ + +#define FSMC_BCR2_FACCEN ((uint32_t)0x00000040) /*!< Flash access enable */ +#define FSMC_BCR2_BURSTEN ((uint32_t)0x00000100) /*!< Burst enable bit */ +#define FSMC_BCR2_WAITPOL ((uint32_t)0x00000200) /*!< Wait signal polarity bit */ +#define FSMC_BCR2_WRAPMOD ((uint32_t)0x00000400) /*!< Wrapped burst mode support */ +#define FSMC_BCR2_WAITCFG ((uint32_t)0x00000800) /*!< Wait timing configuration */ +#define FSMC_BCR2_WREN ((uint32_t)0x00001000) /*!< Write enable bit */ +#define FSMC_BCR2_WAITEN ((uint32_t)0x00002000) /*!< Wait enable bit */ +#define FSMC_BCR2_EXTMOD ((uint32_t)0x00004000) /*!< Extended mode enable */ +#define FSMC_BCR2_ASYNCWAIT ((uint32_t)0x00008000) /*!< Asynchronous wait */ +#define FSMC_BCR2_CBURSTRW ((uint32_t)0x00080000) /*!< Write burst enable */ + +/****************** Bit definition for FSMC_BCR3 register *******************/ +#define FSMC_BCR3_MBKEN ((uint32_t)0x00000001) /*!< Memory bank enable bit */ +#define FSMC_BCR3_MUXEN ((uint32_t)0x00000002) /*!< Address/data multiplexing enable bit */ + +#define FSMC_BCR3_MTYP ((uint32_t)0x0000000C) /*!< MTYP[1:0] bits (Memory type) */ +#define FSMC_BCR3_MTYP_0 ((uint32_t)0x00000004) /*!< Bit 0 */ +#define FSMC_BCR3_MTYP_1 ((uint32_t)0x00000008) /*!< Bit 1 */ + +#define FSMC_BCR3_MWID ((uint32_t)0x00000030) /*!< MWID[1:0] bits (Memory data bus width) */ +#define FSMC_BCR3_MWID_0 ((uint32_t)0x00000010) /*!< Bit 0 */ +#define FSMC_BCR3_MWID_1 ((uint32_t)0x00000020) /*!< Bit 1 */ + +#define FSMC_BCR3_FACCEN ((uint32_t)0x00000040) /*!< Flash access enable */ +#define FSMC_BCR3_BURSTEN ((uint32_t)0x00000100) /*!< Burst enable bit */ +#define FSMC_BCR3_WAITPOL ((uint32_t)0x00000200) /*!< Wait signal polarity bit. */ +#define FSMC_BCR3_WRAPMOD ((uint32_t)0x00000400) /*!< Wrapped burst mode support */ +#define FSMC_BCR3_WAITCFG ((uint32_t)0x00000800) /*!< Wait timing configuration */ +#define FSMC_BCR3_WREN ((uint32_t)0x00001000) /*!< Write enable bit */ +#define FSMC_BCR3_WAITEN ((uint32_t)0x00002000) /*!< Wait enable bit */ +#define FSMC_BCR3_EXTMOD ((uint32_t)0x00004000) /*!< Extended mode enable */ +#define FSMC_BCR3_ASYNCWAIT ((uint32_t)0x00008000) /*!< Asynchronous wait */ +#define FSMC_BCR3_CBURSTRW ((uint32_t)0x00080000) /*!< Write burst enable */ + +/****************** Bit definition for FSMC_BCR4 register *******************/ +#define FSMC_BCR4_MBKEN ((uint32_t)0x00000001) /*!< Memory bank enable bit */ +#define FSMC_BCR4_MUXEN ((uint32_t)0x00000002) /*!< Address/data multiplexing enable bit */ + +#define FSMC_BCR4_MTYP ((uint32_t)0x0000000C) /*!< MTYP[1:0] bits (Memory type) */ +#define FSMC_BCR4_MTYP_0 ((uint32_t)0x00000004) /*!< Bit 0 */ +#define FSMC_BCR4_MTYP_1 ((uint32_t)0x00000008) /*!< Bit 1 */ + +#define FSMC_BCR4_MWID ((uint32_t)0x00000030) /*!< MWID[1:0] bits (Memory data bus width) */ +#define FSMC_BCR4_MWID_0 ((uint32_t)0x00000010) /*!< Bit 0 */ +#define FSMC_BCR4_MWID_1 ((uint32_t)0x00000020) /*!< Bit 1 */ + +#define FSMC_BCR4_FACCEN ((uint32_t)0x00000040) /*!< Flash access enable */ +#define FSMC_BCR4_BURSTEN ((uint32_t)0x00000100) /*!< Burst enable bit */ +#define FSMC_BCR4_WAITPOL ((uint32_t)0x00000200) /*!< Wait signal polarity bit */ +#define FSMC_BCR4_WRAPMOD ((uint32_t)0x00000400) /*!< Wrapped burst mode support */ +#define FSMC_BCR4_WAITCFG ((uint32_t)0x00000800) /*!< Wait timing configuration */ +#define FSMC_BCR4_WREN ((uint32_t)0x00001000) /*!< Write enable bit */ +#define FSMC_BCR4_WAITEN ((uint32_t)0x00002000) /*!< Wait enable bit */ +#define FSMC_BCR4_EXTMOD ((uint32_t)0x00004000) /*!< Extended mode enable */ +#define FSMC_BCR4_ASYNCWAIT ((uint32_t)0x00008000) /*!< Asynchronous wait */ +#define FSMC_BCR4_CBURSTRW ((uint32_t)0x00080000) /*!< Write burst enable */ + +/****************** Bit definition for FSMC_BTR1 register ******************/ +#define FSMC_BTR1_ADDSET ((uint32_t)0x0000000F) /*!< ADDSET[3:0] bits (Address setup phase duration) */ +#define FSMC_BTR1_ADDSET_0 ((uint32_t)0x00000001) /*!< Bit 0 */ +#define FSMC_BTR1_ADDSET_1 ((uint32_t)0x00000002) /*!< Bit 1 */ +#define FSMC_BTR1_ADDSET_2 ((uint32_t)0x00000004) /*!< Bit 2 */ +#define FSMC_BTR1_ADDSET_3 ((uint32_t)0x00000008) /*!< Bit 3 */ + +#define FSMC_BTR1_ADDHLD ((uint32_t)0x000000F0) /*!< ADDHLD[3:0] bits (Address-hold phase duration) */ +#define FSMC_BTR1_ADDHLD_0 ((uint32_t)0x00000010) /*!< Bit 0 */ +#define FSMC_BTR1_ADDHLD_1 ((uint32_t)0x00000020) /*!< Bit 1 */ +#define FSMC_BTR1_ADDHLD_2 ((uint32_t)0x00000040) /*!< Bit 2 */ +#define FSMC_BTR1_ADDHLD_3 ((uint32_t)0x00000080) /*!< Bit 3 */ + +#define FSMC_BTR1_DATAST ((uint32_t)0x0000FF00) /*!< DATAST [3:0] bits (Data-phase duration) */ +#define FSMC_BTR1_DATAST_0 ((uint32_t)0x00000100) /*!< Bit 0 */ +#define FSMC_BTR1_DATAST_1 ((uint32_t)0x00000200) /*!< Bit 1 */ +#define FSMC_BTR1_DATAST_2 ((uint32_t)0x00000400) /*!< Bit 2 */ +#define FSMC_BTR1_DATAST_3 ((uint32_t)0x00000800) /*!< Bit 3 */ +#define FSMC_BTR1_DATAST_4 ((uint32_t)0x00001000) /*!< Bit 4 */ +#define FSMC_BTR1_DATAST_5 ((uint32_t)0x00002000) /*!< Bit 5 */ +#define FSMC_BTR1_DATAST_6 ((uint32_t)0x00004000) /*!< Bit 6 */ +#define FSMC_BTR1_DATAST_7 ((uint32_t)0x00008000) /*!< Bit 7 */ + +#define FSMC_BTR1_BUSTURN ((uint32_t)0x000F0000) /*!< BUSTURN[3:0] bits (Bus turnaround phase duration) */ +#define FSMC_BTR1_BUSTURN_0 ((uint32_t)0x00010000) /*!< Bit 0 */ +#define FSMC_BTR1_BUSTURN_1 ((uint32_t)0x00020000) /*!< Bit 1 */ +#define FSMC_BTR1_BUSTURN_2 ((uint32_t)0x00040000) /*!< Bit 2 */ +#define FSMC_BTR1_BUSTURN_3 ((uint32_t)0x00080000) /*!< Bit 3 */ + +#define FSMC_BTR1_CLKDIV ((uint32_t)0x00F00000) /*!< CLKDIV[3:0] bits (Clock divide ratio) */ +#define FSMC_BTR1_CLKDIV_0 ((uint32_t)0x00100000) /*!< Bit 0 */ +#define FSMC_BTR1_CLKDIV_1 ((uint32_t)0x00200000) /*!< Bit 1 */ +#define FSMC_BTR1_CLKDIV_2 ((uint32_t)0x00400000) /*!< Bit 2 */ +#define FSMC_BTR1_CLKDIV_3 ((uint32_t)0x00800000) /*!< Bit 3 */ + +#define FSMC_BTR1_DATLAT ((uint32_t)0x0F000000) /*!< DATLA[3:0] bits (Data latency) */ +#define FSMC_BTR1_DATLAT_0 ((uint32_t)0x01000000) /*!< Bit 0 */ +#define FSMC_BTR1_DATLAT_1 ((uint32_t)0x02000000) /*!< Bit 1 */ +#define FSMC_BTR1_DATLAT_2 ((uint32_t)0x04000000) /*!< Bit 2 */ +#define FSMC_BTR1_DATLAT_3 ((uint32_t)0x08000000) /*!< Bit 3 */ + +#define FSMC_BTR1_ACCMOD ((uint32_t)0x30000000) /*!< ACCMOD[1:0] bits (Access mode) */ +#define FSMC_BTR1_ACCMOD_0 ((uint32_t)0x10000000) /*!< Bit 0 */ +#define FSMC_BTR1_ACCMOD_1 ((uint32_t)0x20000000) /*!< Bit 1 */ + +/****************** Bit definition for FSMC_BTR2 register *******************/ +#define FSMC_BTR2_ADDSET ((uint32_t)0x0000000F) /*!< ADDSET[3:0] bits (Address setup phase duration) */ +#define FSMC_BTR2_ADDSET_0 ((uint32_t)0x00000001) /*!< Bit 0 */ +#define FSMC_BTR2_ADDSET_1 ((uint32_t)0x00000002) /*!< Bit 1 */ +#define FSMC_BTR2_ADDSET_2 ((uint32_t)0x00000004) /*!< Bit 2 */ +#define FSMC_BTR2_ADDSET_3 ((uint32_t)0x00000008) /*!< Bit 3 */ + +#define FSMC_BTR2_ADDHLD ((uint32_t)0x000000F0) /*!< ADDHLD[3:0] bits (Address-hold phase duration) */ +#define FSMC_BTR2_ADDHLD_0 ((uint32_t)0x00000010) /*!< Bit 0 */ +#define FSMC_BTR2_ADDHLD_1 ((uint32_t)0x00000020) /*!< Bit 1 */ +#define FSMC_BTR2_ADDHLD_2 ((uint32_t)0x00000040) /*!< Bit 2 */ +#define FSMC_BTR2_ADDHLD_3 ((uint32_t)0x00000080) /*!< Bit 3 */ + +#define FSMC_BTR2_DATAST ((uint32_t)0x0000FF00) /*!< DATAST [3:0] bits (Data-phase duration) */ +#define FSMC_BTR2_DATAST_0 ((uint32_t)0x00000100) /*!< Bit 0 */ +#define FSMC_BTR2_DATAST_1 ((uint32_t)0x00000200) /*!< Bit 1 */ +#define FSMC_BTR2_DATAST_2 ((uint32_t)0x00000400) /*!< Bit 2 */ +#define FSMC_BTR2_DATAST_3 ((uint32_t)0x00000800) /*!< Bit 3 */ +#define FSMC_BTR2_DATAST_4 ((uint32_t)0x00001000) /*!< Bit 4 */ +#define FSMC_BTR2_DATAST_5 ((uint32_t)0x00002000) /*!< Bit 5 */ +#define FSMC_BTR2_DATAST_6 ((uint32_t)0x00004000) /*!< Bit 6 */ +#define FSMC_BTR2_DATAST_7 ((uint32_t)0x00008000) /*!< Bit 7 */ + +#define FSMC_BTR2_BUSTURN ((uint32_t)0x000F0000) /*!< BUSTURN[3:0] bits (Bus turnaround phase duration) */ +#define FSMC_BTR2_BUSTURN_0 ((uint32_t)0x00010000) /*!< Bit 0 */ +#define FSMC_BTR2_BUSTURN_1 ((uint32_t)0x00020000) /*!< Bit 1 */ +#define FSMC_BTR2_BUSTURN_2 ((uint32_t)0x00040000) /*!< Bit 2 */ +#define FSMC_BTR2_BUSTURN_3 ((uint32_t)0x00080000) /*!< Bit 3 */ + +#define FSMC_BTR2_CLKDIV ((uint32_t)0x00F00000) /*!< CLKDIV[3:0] bits (Clock divide ratio) */ +#define FSMC_BTR2_CLKDIV_0 ((uint32_t)0x00100000) /*!< Bit 0 */ +#define FSMC_BTR2_CLKDIV_1 ((uint32_t)0x00200000) /*!< Bit 1 */ +#define FSMC_BTR2_CLKDIV_2 ((uint32_t)0x00400000) /*!< Bit 2 */ +#define FSMC_BTR2_CLKDIV_3 ((uint32_t)0x00800000) /*!< Bit 3 */ + +#define FSMC_BTR2_DATLAT ((uint32_t)0x0F000000) /*!< DATLA[3:0] bits (Data latency) */ +#define FSMC_BTR2_DATLAT_0 ((uint32_t)0x01000000) /*!< Bit 0 */ +#define FSMC_BTR2_DATLAT_1 ((uint32_t)0x02000000) /*!< Bit 1 */ +#define FSMC_BTR2_DATLAT_2 ((uint32_t)0x04000000) /*!< Bit 2 */ +#define FSMC_BTR2_DATLAT_3 ((uint32_t)0x08000000) /*!< Bit 3 */ + +#define FSMC_BTR2_ACCMOD ((uint32_t)0x30000000) /*!< ACCMOD[1:0] bits (Access mode) */ +#define FSMC_BTR2_ACCMOD_0 ((uint32_t)0x10000000) /*!< Bit 0 */ +#define FSMC_BTR2_ACCMOD_1 ((uint32_t)0x20000000) /*!< Bit 1 */ + +/******************* Bit definition for FSMC_BTR3 register *******************/ +#define FSMC_BTR3_ADDSET ((uint32_t)0x0000000F) /*!< ADDSET[3:0] bits (Address setup phase duration) */ +#define FSMC_BTR3_ADDSET_0 ((uint32_t)0x00000001) /*!< Bit 0 */ +#define FSMC_BTR3_ADDSET_1 ((uint32_t)0x00000002) /*!< Bit 1 */ +#define FSMC_BTR3_ADDSET_2 ((uint32_t)0x00000004) /*!< Bit 2 */ +#define FSMC_BTR3_ADDSET_3 ((uint32_t)0x00000008) /*!< Bit 3 */ + +#define FSMC_BTR3_ADDHLD ((uint32_t)0x000000F0) /*!< ADDHLD[3:0] bits (Address-hold phase duration) */ +#define FSMC_BTR3_ADDHLD_0 ((uint32_t)0x00000010) /*!< Bit 0 */ +#define FSMC_BTR3_ADDHLD_1 ((uint32_t)0x00000020) /*!< Bit 1 */ +#define FSMC_BTR3_ADDHLD_2 ((uint32_t)0x00000040) /*!< Bit 2 */ +#define FSMC_BTR3_ADDHLD_3 ((uint32_t)0x00000080) /*!< Bit 3 */ + +#define FSMC_BTR3_DATAST ((uint32_t)0x0000FF00) /*!< DATAST [3:0] bits (Data-phase duration) */ +#define FSMC_BTR3_DATAST_0 ((uint32_t)0x00000100) /*!< Bit 0 */ +#define FSMC_BTR3_DATAST_1 ((uint32_t)0x00000200) /*!< Bit 1 */ +#define FSMC_BTR3_DATAST_2 ((uint32_t)0x00000400) /*!< Bit 2 */ +#define FSMC_BTR3_DATAST_3 ((uint32_t)0x00000800) /*!< Bit 3 */ +#define FSMC_BTR3_DATAST_4 ((uint32_t)0x00001000) /*!< Bit 4 */ +#define FSMC_BTR3_DATAST_5 ((uint32_t)0x00002000) /*!< Bit 5 */ +#define FSMC_BTR3_DATAST_6 ((uint32_t)0x00004000) /*!< Bit 6 */ +#define FSMC_BTR3_DATAST_7 ((uint32_t)0x00008000) /*!< Bit 7 */ + +#define FSMC_BTR3_BUSTURN ((uint32_t)0x000F0000) /*!< BUSTURN[3:0] bits (Bus turnaround phase duration) */ +#define FSMC_BTR3_BUSTURN_0 ((uint32_t)0x00010000) /*!< Bit 0 */ +#define FSMC_BTR3_BUSTURN_1 ((uint32_t)0x00020000) /*!< Bit 1 */ +#define FSMC_BTR3_BUSTURN_2 ((uint32_t)0x00040000) /*!< Bit 2 */ +#define FSMC_BTR3_BUSTURN_3 ((uint32_t)0x00080000) /*!< Bit 3 */ + +#define FSMC_BTR3_CLKDIV ((uint32_t)0x00F00000) /*!< CLKDIV[3:0] bits (Clock divide ratio) */ +#define FSMC_BTR3_CLKDIV_0 ((uint32_t)0x00100000) /*!< Bit 0 */ +#define FSMC_BTR3_CLKDIV_1 ((uint32_t)0x00200000) /*!< Bit 1 */ +#define FSMC_BTR3_CLKDIV_2 ((uint32_t)0x00400000) /*!< Bit 2 */ +#define FSMC_BTR3_CLKDIV_3 ((uint32_t)0x00800000) /*!< Bit 3 */ + +#define FSMC_BTR3_DATLAT ((uint32_t)0x0F000000) /*!< DATLA[3:0] bits (Data latency) */ +#define FSMC_BTR3_DATLAT_0 ((uint32_t)0x01000000) /*!< Bit 0 */ +#define FSMC_BTR3_DATLAT_1 ((uint32_t)0x02000000) /*!< Bit 1 */ +#define FSMC_BTR3_DATLAT_2 ((uint32_t)0x04000000) /*!< Bit 2 */ +#define FSMC_BTR3_DATLAT_3 ((uint32_t)0x08000000) /*!< Bit 3 */ + +#define FSMC_BTR3_ACCMOD ((uint32_t)0x30000000) /*!< ACCMOD[1:0] bits (Access mode) */ +#define FSMC_BTR3_ACCMOD_0 ((uint32_t)0x10000000) /*!< Bit 0 */ +#define FSMC_BTR3_ACCMOD_1 ((uint32_t)0x20000000) /*!< Bit 1 */ + +/****************** Bit definition for FSMC_BTR4 register *******************/ +#define FSMC_BTR4_ADDSET ((uint32_t)0x0000000F) /*!< ADDSET[3:0] bits (Address setup phase duration) */ +#define FSMC_BTR4_ADDSET_0 ((uint32_t)0x00000001) /*!< Bit 0 */ +#define FSMC_BTR4_ADDSET_1 ((uint32_t)0x00000002) /*!< Bit 1 */ +#define FSMC_BTR4_ADDSET_2 ((uint32_t)0x00000004) /*!< Bit 2 */ +#define FSMC_BTR4_ADDSET_3 ((uint32_t)0x00000008) /*!< Bit 3 */ + +#define FSMC_BTR4_ADDHLD ((uint32_t)0x000000F0) /*!< ADDHLD[3:0] bits (Address-hold phase duration) */ +#define FSMC_BTR4_ADDHLD_0 ((uint32_t)0x00000010) /*!< Bit 0 */ +#define FSMC_BTR4_ADDHLD_1 ((uint32_t)0x00000020) /*!< Bit 1 */ +#define FSMC_BTR4_ADDHLD_2 ((uint32_t)0x00000040) /*!< Bit 2 */ +#define FSMC_BTR4_ADDHLD_3 ((uint32_t)0x00000080) /*!< Bit 3 */ + +#define FSMC_BTR4_DATAST ((uint32_t)0x0000FF00) /*!< DATAST [3:0] bits (Data-phase duration) */ +#define FSMC_BTR4_DATAST_0 ((uint32_t)0x00000100) /*!< Bit 0 */ +#define FSMC_BTR4_DATAST_1 ((uint32_t)0x00000200) /*!< Bit 1 */ +#define FSMC_BTR4_DATAST_2 ((uint32_t)0x00000400) /*!< Bit 2 */ +#define FSMC_BTR4_DATAST_3 ((uint32_t)0x00000800) /*!< Bit 3 */ +#define FSMC_BTR4_DATAST_4 ((uint32_t)0x00001000) /*!< Bit 4 */ +#define FSMC_BTR4_DATAST_5 ((uint32_t)0x00002000) /*!< Bit 5 */ +#define FSMC_BTR4_DATAST_6 ((uint32_t)0x00004000) /*!< Bit 6 */ +#define FSMC_BTR4_DATAST_7 ((uint32_t)0x00008000) /*!< Bit 7 */ + +#define FSMC_BTR4_BUSTURN ((uint32_t)0x000F0000) /*!< BUSTURN[3:0] bits (Bus turnaround phase duration) */ +#define FSMC_BTR4_BUSTURN_0 ((uint32_t)0x00010000) /*!< Bit 0 */ +#define FSMC_BTR4_BUSTURN_1 ((uint32_t)0x00020000) /*!< Bit 1 */ +#define FSMC_BTR4_BUSTURN_2 ((uint32_t)0x00040000) /*!< Bit 2 */ +#define FSMC_BTR4_BUSTURN_3 ((uint32_t)0x00080000) /*!< Bit 3 */ + +#define FSMC_BTR4_CLKDIV ((uint32_t)0x00F00000) /*!< CLKDIV[3:0] bits (Clock divide ratio) */ +#define FSMC_BTR4_CLKDIV_0 ((uint32_t)0x00100000) /*!< Bit 0 */ +#define FSMC_BTR4_CLKDIV_1 ((uint32_t)0x00200000) /*!< Bit 1 */ +#define FSMC_BTR4_CLKDIV_2 ((uint32_t)0x00400000) /*!< Bit 2 */ +#define FSMC_BTR4_CLKDIV_3 ((uint32_t)0x00800000) /*!< Bit 3 */ + +#define FSMC_BTR4_DATLAT ((uint32_t)0x0F000000) /*!< DATLA[3:0] bits (Data latency) */ +#define FSMC_BTR4_DATLAT_0 ((uint32_t)0x01000000) /*!< Bit 0 */ +#define FSMC_BTR4_DATLAT_1 ((uint32_t)0x02000000) /*!< Bit 1 */ +#define FSMC_BTR4_DATLAT_2 ((uint32_t)0x04000000) /*!< Bit 2 */ +#define FSMC_BTR4_DATLAT_3 ((uint32_t)0x08000000) /*!< Bit 3 */ + +#define FSMC_BTR4_ACCMOD ((uint32_t)0x30000000) /*!< ACCMOD[1:0] bits (Access mode) */ +#define FSMC_BTR4_ACCMOD_0 ((uint32_t)0x10000000) /*!< Bit 0 */ +#define FSMC_BTR4_ACCMOD_1 ((uint32_t)0x20000000) /*!< Bit 1 */ + +/****************** Bit definition for FSMC_BWTR1 register ******************/ +#define FSMC_BWTR1_ADDSET ((uint32_t)0x0000000F) /*!< ADDSET[3:0] bits (Address setup phase duration) */ +#define FSMC_BWTR1_ADDSET_0 ((uint32_t)0x00000001) /*!< Bit 0 */ +#define FSMC_BWTR1_ADDSET_1 ((uint32_t)0x00000002) /*!< Bit 1 */ +#define FSMC_BWTR1_ADDSET_2 ((uint32_t)0x00000004) /*!< Bit 2 */ +#define FSMC_BWTR1_ADDSET_3 ((uint32_t)0x00000008) /*!< Bit 3 */ + +#define FSMC_BWTR1_ADDHLD ((uint32_t)0x000000F0) /*!< ADDHLD[3:0] bits (Address-hold phase duration) */ +#define FSMC_BWTR1_ADDHLD_0 ((uint32_t)0x00000010) /*!< Bit 0 */ +#define FSMC_BWTR1_ADDHLD_1 ((uint32_t)0x00000020) /*!< Bit 1 */ +#define FSMC_BWTR1_ADDHLD_2 ((uint32_t)0x00000040) /*!< Bit 2 */ +#define FSMC_BWTR1_ADDHLD_3 ((uint32_t)0x00000080) /*!< Bit 3 */ + +#define FSMC_BWTR1_DATAST ((uint32_t)0x0000FF00) /*!< DATAST [3:0] bits (Data-phase duration) */ +#define FSMC_BWTR1_DATAST_0 ((uint32_t)0x00000100) /*!< Bit 0 */ +#define FSMC_BWTR1_DATAST_1 ((uint32_t)0x00000200) /*!< Bit 1 */ +#define FSMC_BWTR1_DATAST_2 ((uint32_t)0x00000400) /*!< Bit 2 */ +#define FSMC_BWTR1_DATAST_3 ((uint32_t)0x00000800) /*!< Bit 3 */ +#define FSMC_BWTR1_DATAST_4 ((uint32_t)0x00001000) /*!< Bit 4 */ +#define FSMC_BWTR1_DATAST_5 ((uint32_t)0x00002000) /*!< Bit 5 */ +#define FSMC_BWTR1_DATAST_6 ((uint32_t)0x00004000) /*!< Bit 6 */ +#define FSMC_BWTR1_DATAST_7 ((uint32_t)0x00008000) /*!< Bit 7 */ + +#define FSMC_BWTR1_CLKDIV ((uint32_t)0x00F00000) /*!< CLKDIV[3:0] bits (Clock divide ratio) */ +#define FSMC_BWTR1_CLKDIV_0 ((uint32_t)0x00100000) /*!< Bit 0 */ +#define FSMC_BWTR1_CLKDIV_1 ((uint32_t)0x00200000) /*!< Bit 1 */ +#define FSMC_BWTR1_CLKDIV_2 ((uint32_t)0x00400000) /*!< Bit 2 */ +#define FSMC_BWTR1_CLKDIV_3 ((uint32_t)0x00800000) /*!< Bit 3 */ + +#define FSMC_BWTR1_DATLAT ((uint32_t)0x0F000000) /*!< DATLA[3:0] bits (Data latency) */ +#define FSMC_BWTR1_DATLAT_0 ((uint32_t)0x01000000) /*!< Bit 0 */ +#define FSMC_BWTR1_DATLAT_1 ((uint32_t)0x02000000) /*!< Bit 1 */ +#define FSMC_BWTR1_DATLAT_2 ((uint32_t)0x04000000) /*!< Bit 2 */ +#define FSMC_BWTR1_DATLAT_3 ((uint32_t)0x08000000) /*!< Bit 3 */ + +#define FSMC_BWTR1_ACCMOD ((uint32_t)0x30000000) /*!< ACCMOD[1:0] bits (Access mode) */ +#define FSMC_BWTR1_ACCMOD_0 ((uint32_t)0x10000000) /*!< Bit 0 */ +#define FSMC_BWTR1_ACCMOD_1 ((uint32_t)0x20000000) /*!< Bit 1 */ + +/****************** Bit definition for FSMC_BWTR2 register ******************/ +#define FSMC_BWTR2_ADDSET ((uint32_t)0x0000000F) /*!< ADDSET[3:0] bits (Address setup phase duration) */ +#define FSMC_BWTR2_ADDSET_0 ((uint32_t)0x00000001) /*!< Bit 0 */ +#define FSMC_BWTR2_ADDSET_1 ((uint32_t)0x00000002) /*!< Bit 1 */ +#define FSMC_BWTR2_ADDSET_2 ((uint32_t)0x00000004) /*!< Bit 2 */ +#define FSMC_BWTR2_ADDSET_3 ((uint32_t)0x00000008) /*!< Bit 3 */ + +#define FSMC_BWTR2_ADDHLD ((uint32_t)0x000000F0) /*!< ADDHLD[3:0] bits (Address-hold phase duration) */ +#define FSMC_BWTR2_ADDHLD_0 ((uint32_t)0x00000010) /*!< Bit 0 */ +#define FSMC_BWTR2_ADDHLD_1 ((uint32_t)0x00000020) /*!< Bit 1 */ +#define FSMC_BWTR2_ADDHLD_2 ((uint32_t)0x00000040) /*!< Bit 2 */ +#define FSMC_BWTR2_ADDHLD_3 ((uint32_t)0x00000080) /*!< Bit 3 */ + +#define FSMC_BWTR2_DATAST ((uint32_t)0x0000FF00) /*!< DATAST [3:0] bits (Data-phase duration) */ +#define FSMC_BWTR2_DATAST_0 ((uint32_t)0x00000100) /*!< Bit 0 */ +#define FSMC_BWTR2_DATAST_1 ((uint32_t)0x00000200) /*!< Bit 1 */ +#define FSMC_BWTR2_DATAST_2 ((uint32_t)0x00000400) /*!< Bit 2 */ +#define FSMC_BWTR2_DATAST_3 ((uint32_t)0x00000800) /*!< Bit 3 */ +#define FSMC_BWTR2_DATAST_4 ((uint32_t)0x00001000) /*!< Bit 4 */ +#define FSMC_BWTR2_DATAST_5 ((uint32_t)0x00002000) /*!< Bit 5 */ +#define FSMC_BWTR2_DATAST_6 ((uint32_t)0x00004000) /*!< Bit 6 */ +#define FSMC_BWTR2_DATAST_7 ((uint32_t)0x00008000) /*!< Bit 7 */ + +#define FSMC_BWTR2_CLKDIV ((uint32_t)0x00F00000) /*!< CLKDIV[3:0] bits (Clock divide ratio) */ +#define FSMC_BWTR2_CLKDIV_0 ((uint32_t)0x00100000) /*!< Bit 0 */ +#define FSMC_BWTR2_CLKDIV_1 ((uint32_t)0x00200000) /*!< Bit 1*/ +#define FSMC_BWTR2_CLKDIV_2 ((uint32_t)0x00400000) /*!< Bit 2 */ +#define FSMC_BWTR2_CLKDIV_3 ((uint32_t)0x00800000) /*!< Bit 3 */ + +#define FSMC_BWTR2_DATLAT ((uint32_t)0x0F000000) /*!< DATLA[3:0] bits (Data latency) */ +#define FSMC_BWTR2_DATLAT_0 ((uint32_t)0x01000000) /*!< Bit 0 */ +#define FSMC_BWTR2_DATLAT_1 ((uint32_t)0x02000000) /*!< Bit 1 */ +#define FSMC_BWTR2_DATLAT_2 ((uint32_t)0x04000000) /*!< Bit 2 */ +#define FSMC_BWTR2_DATLAT_3 ((uint32_t)0x08000000) /*!< Bit 3 */ + +#define FSMC_BWTR2_ACCMOD ((uint32_t)0x30000000) /*!< ACCMOD[1:0] bits (Access mode) */ +#define FSMC_BWTR2_ACCMOD_0 ((uint32_t)0x10000000) /*!< Bit 0 */ +#define FSMC_BWTR2_ACCMOD_1 ((uint32_t)0x20000000) /*!< Bit 1 */ + +/****************** Bit definition for FSMC_BWTR3 register ******************/ +#define FSMC_BWTR3_ADDSET ((uint32_t)0x0000000F) /*!< ADDSET[3:0] bits (Address setup phase duration) */ +#define FSMC_BWTR3_ADDSET_0 ((uint32_t)0x00000001) /*!< Bit 0 */ +#define FSMC_BWTR3_ADDSET_1 ((uint32_t)0x00000002) /*!< Bit 1 */ +#define FSMC_BWTR3_ADDSET_2 ((uint32_t)0x00000004) /*!< Bit 2 */ +#define FSMC_BWTR3_ADDSET_3 ((uint32_t)0x00000008) /*!< Bit 3 */ + +#define FSMC_BWTR3_ADDHLD ((uint32_t)0x000000F0) /*!< ADDHLD[3:0] bits (Address-hold phase duration) */ +#define FSMC_BWTR3_ADDHLD_0 ((uint32_t)0x00000010) /*!< Bit 0 */ +#define FSMC_BWTR3_ADDHLD_1 ((uint32_t)0x00000020) /*!< Bit 1 */ +#define FSMC_BWTR3_ADDHLD_2 ((uint32_t)0x00000040) /*!< Bit 2 */ +#define FSMC_BWTR3_ADDHLD_3 ((uint32_t)0x00000080) /*!< Bit 3 */ + +#define FSMC_BWTR3_DATAST ((uint32_t)0x0000FF00) /*!< DATAST [3:0] bits (Data-phase duration) */ +#define FSMC_BWTR3_DATAST_0 ((uint32_t)0x00000100) /*!< Bit 0 */ +#define FSMC_BWTR3_DATAST_1 ((uint32_t)0x00000200) /*!< Bit 1 */ +#define FSMC_BWTR3_DATAST_2 ((uint32_t)0x00000400) /*!< Bit 2 */ +#define FSMC_BWTR3_DATAST_3 ((uint32_t)0x00000800) /*!< Bit 3 */ +#define FSMC_BWTR3_DATAST_4 ((uint32_t)0x00001000) /*!< Bit 4 */ +#define FSMC_BWTR3_DATAST_5 ((uint32_t)0x00002000) /*!< Bit 5 */ +#define FSMC_BWTR3_DATAST_6 ((uint32_t)0x00004000) /*!< Bit 6 */ +#define FSMC_BWTR3_DATAST_7 ((uint32_t)0x00008000) /*!< Bit 7 */ + +#define FSMC_BWTR3_CLKDIV ((uint32_t)0x00F00000) /*!< CLKDIV[3:0] bits (Clock divide ratio) */ +#define FSMC_BWTR3_CLKDIV_0 ((uint32_t)0x00100000) /*!< Bit 0 */ +#define FSMC_BWTR3_CLKDIV_1 ((uint32_t)0x00200000) /*!< Bit 1 */ +#define FSMC_BWTR3_CLKDIV_2 ((uint32_t)0x00400000) /*!< Bit 2 */ +#define FSMC_BWTR3_CLKDIV_3 ((uint32_t)0x00800000) /*!< Bit 3 */ + +#define FSMC_BWTR3_DATLAT ((uint32_t)0x0F000000) /*!< DATLA[3:0] bits (Data latency) */ +#define FSMC_BWTR3_DATLAT_0 ((uint32_t)0x01000000) /*!< Bit 0 */ +#define FSMC_BWTR3_DATLAT_1 ((uint32_t)0x02000000) /*!< Bit 1 */ +#define FSMC_BWTR3_DATLAT_2 ((uint32_t)0x04000000) /*!< Bit 2 */ +#define FSMC_BWTR3_DATLAT_3 ((uint32_t)0x08000000) /*!< Bit 3 */ + +#define FSMC_BWTR3_ACCMOD ((uint32_t)0x30000000) /*!< ACCMOD[1:0] bits (Access mode) */ +#define FSMC_BWTR3_ACCMOD_0 ((uint32_t)0x10000000) /*!< Bit 0 */ +#define FSMC_BWTR3_ACCMOD_1 ((uint32_t)0x20000000) /*!< Bit 1 */ + +/****************** Bit definition for FSMC_BWTR4 register ******************/ +#define FSMC_BWTR4_ADDSET ((uint32_t)0x0000000F) /*!< ADDSET[3:0] bits (Address setup phase duration) */ +#define FSMC_BWTR4_ADDSET_0 ((uint32_t)0x00000001) /*!< Bit 0 */ +#define FSMC_BWTR4_ADDSET_1 ((uint32_t)0x00000002) /*!< Bit 1 */ +#define FSMC_BWTR4_ADDSET_2 ((uint32_t)0x00000004) /*!< Bit 2 */ +#define FSMC_BWTR4_ADDSET_3 ((uint32_t)0x00000008) /*!< Bit 3 */ + +#define FSMC_BWTR4_ADDHLD ((uint32_t)0x000000F0) /*!< ADDHLD[3:0] bits (Address-hold phase duration) */ +#define FSMC_BWTR4_ADDHLD_0 ((uint32_t)0x00000010) /*!< Bit 0 */ +#define FSMC_BWTR4_ADDHLD_1 ((uint32_t)0x00000020) /*!< Bit 1 */ +#define FSMC_BWTR4_ADDHLD_2 ((uint32_t)0x00000040) /*!< Bit 2 */ +#define FSMC_BWTR4_ADDHLD_3 ((uint32_t)0x00000080) /*!< Bit 3 */ + +#define FSMC_BWTR4_DATAST ((uint32_t)0x0000FF00) /*!< DATAST [3:0] bits (Data-phase duration) */ +#define FSMC_BWTR4_DATAST_0 ((uint32_t)0x00000100) /*!< Bit 0 */ +#define FSMC_BWTR4_DATAST_1 ((uint32_t)0x00000200) /*!< Bit 1 */ +#define FSMC_BWTR4_DATAST_2 ((uint32_t)0x00000400) /*!< Bit 2 */ +#define FSMC_BWTR4_DATAST_3 ((uint32_t)0x00000800) /*!< Bit 3 */ +#define FSMC_BWTR4_DATAST_4 ((uint32_t)0x00001000) /*!< Bit 4 */ +#define FSMC_BWTR4_DATAST_5 ((uint32_t)0x00002000) /*!< Bit 5 */ +#define FSMC_BWTR4_DATAST_6 ((uint32_t)0x00004000) /*!< Bit 6 */ +#define FSMC_BWTR4_DATAST_7 ((uint32_t)0x00008000) /*!< Bit 7 */ + +#define FSMC_BWTR4_CLKDIV ((uint32_t)0x00F00000) /*!< CLKDIV[3:0] bits (Clock divide ratio) */ +#define FSMC_BWTR4_CLKDIV_0 ((uint32_t)0x00100000) /*!< Bit 0 */ +#define FSMC_BWTR4_CLKDIV_1 ((uint32_t)0x00200000) /*!< Bit 1 */ +#define FSMC_BWTR4_CLKDIV_2 ((uint32_t)0x00400000) /*!< Bit 2 */ +#define FSMC_BWTR4_CLKDIV_3 ((uint32_t)0x00800000) /*!< Bit 3 */ + +#define FSMC_BWTR4_DATLAT ((uint32_t)0x0F000000) /*!< DATLA[3:0] bits (Data latency) */ +#define FSMC_BWTR4_DATLAT_0 ((uint32_t)0x01000000) /*!< Bit 0 */ +#define FSMC_BWTR4_DATLAT_1 ((uint32_t)0x02000000) /*!< Bit 1 */ +#define FSMC_BWTR4_DATLAT_2 ((uint32_t)0x04000000) /*!< Bit 2 */ +#define FSMC_BWTR4_DATLAT_3 ((uint32_t)0x08000000) /*!< Bit 3 */ + +#define FSMC_BWTR4_ACCMOD ((uint32_t)0x30000000) /*!< ACCMOD[1:0] bits (Access mode) */ +#define FSMC_BWTR4_ACCMOD_0 ((uint32_t)0x10000000) /*!< Bit 0 */ +#define FSMC_BWTR4_ACCMOD_1 ((uint32_t)0x20000000) /*!< Bit 1 */ + +/****************** Bit definition for FSMC_PCR2 register *******************/ +#define FSMC_PCR2_PWAITEN ((uint32_t)0x00000002) /*!< Wait feature enable bit */ +#define FSMC_PCR2_PBKEN ((uint32_t)0x00000004) /*!< PC Card/NAND Flash memory bank enable bit */ +#define FSMC_PCR2_PTYP ((uint32_t)0x00000008) /*!< Memory type */ + +#define FSMC_PCR2_PWID ((uint32_t)0x00000030) /*!< PWID[1:0] bits (NAND Flash databus width) */ +#define FSMC_PCR2_PWID_0 ((uint32_t)0x00000010) /*!< Bit 0 */ +#define FSMC_PCR2_PWID_1 ((uint32_t)0x00000020) /*!< Bit 1 */ + +#define FSMC_PCR2_ECCEN ((uint32_t)0x00000040) /*!< ECC computation logic enable bit */ + +#define FSMC_PCR2_TCLR ((uint32_t)0x00001E00) /*!< TCLR[3:0] bits (CLE to RE delay) */ +#define FSMC_PCR2_TCLR_0 ((uint32_t)0x00000200) /*!< Bit 0 */ +#define FSMC_PCR2_TCLR_1 ((uint32_t)0x00000400) /*!< Bit 1 */ +#define FSMC_PCR2_TCLR_2 ((uint32_t)0x00000800) /*!< Bit 2 */ +#define FSMC_PCR2_TCLR_3 ((uint32_t)0x00001000) /*!< Bit 3 */ + +#define FSMC_PCR2_TAR ((uint32_t)0x0001E000) /*!< TAR[3:0] bits (ALE to RE delay) */ +#define FSMC_PCR2_TAR_0 ((uint32_t)0x00002000) /*!< Bit 0 */ +#define FSMC_PCR2_TAR_1 ((uint32_t)0x00004000) /*!< Bit 1 */ +#define FSMC_PCR2_TAR_2 ((uint32_t)0x00008000) /*!< Bit 2 */ +#define FSMC_PCR2_TAR_3 ((uint32_t)0x00010000) /*!< Bit 3 */ + +#define FSMC_PCR2_ECCPS ((uint32_t)0x000E0000) /*!< ECCPS[1:0] bits (ECC page size) */ +#define FSMC_PCR2_ECCPS_0 ((uint32_t)0x00020000) /*!< Bit 0 */ +#define FSMC_PCR2_ECCPS_1 ((uint32_t)0x00040000) /*!< Bit 1 */ +#define FSMC_PCR2_ECCPS_2 ((uint32_t)0x00080000) /*!< Bit 2 */ + +/****************** Bit definition for FSMC_PCR3 register *******************/ +#define FSMC_PCR3_PWAITEN ((uint32_t)0x00000002) /*!< Wait feature enable bit */ +#define FSMC_PCR3_PBKEN ((uint32_t)0x00000004) /*!< PC Card/NAND Flash memory bank enable bit */ +#define FSMC_PCR3_PTYP ((uint32_t)0x00000008) /*!< Memory type */ + +#define FSMC_PCR3_PWID ((uint32_t)0x00000030) /*!< PWID[1:0] bits (NAND Flash databus width) */ +#define FSMC_PCR3_PWID_0 ((uint32_t)0x00000010) /*!< Bit 0 */ +#define FSMC_PCR3_PWID_1 ((uint32_t)0x00000020) /*!< Bit 1 */ + +#define FSMC_PCR3_ECCEN ((uint32_t)0x00000040) /*!< ECC computation logic enable bit */ + +#define FSMC_PCR3_TCLR ((uint32_t)0x00001E00) /*!< TCLR[3:0] bits (CLE to RE delay) */ +#define FSMC_PCR3_TCLR_0 ((uint32_t)0x00000200) /*!< Bit 0 */ +#define FSMC_PCR3_TCLR_1 ((uint32_t)0x00000400) /*!< Bit 1 */ +#define FSMC_PCR3_TCLR_2 ((uint32_t)0x00000800) /*!< Bit 2 */ +#define FSMC_PCR3_TCLR_3 ((uint32_t)0x00001000) /*!< Bit 3 */ + +#define FSMC_PCR3_TAR ((uint32_t)0x0001E000) /*!< TAR[3:0] bits (ALE to RE delay) */ +#define FSMC_PCR3_TAR_0 ((uint32_t)0x00002000) /*!< Bit 0 */ +#define FSMC_PCR3_TAR_1 ((uint32_t)0x00004000) /*!< Bit 1 */ +#define FSMC_PCR3_TAR_2 ((uint32_t)0x00008000) /*!< Bit 2 */ +#define FSMC_PCR3_TAR_3 ((uint32_t)0x00010000) /*!< Bit 3 */ + +#define FSMC_PCR3_ECCPS ((uint32_t)0x000E0000) /*!< ECCPS[2:0] bits (ECC page size) */ +#define FSMC_PCR3_ECCPS_0 ((uint32_t)0x00020000) /*!< Bit 0 */ +#define FSMC_PCR3_ECCPS_1 ((uint32_t)0x00040000) /*!< Bit 1 */ +#define FSMC_PCR3_ECCPS_2 ((uint32_t)0x00080000) /*!< Bit 2 */ + +/****************** Bit definition for FSMC_PCR4 register *******************/ +#define FSMC_PCR4_PWAITEN ((uint32_t)0x00000002) /*!< Wait feature enable bit */ +#define FSMC_PCR4_PBKEN ((uint32_t)0x00000004) /*!< PC Card/NAND Flash memory bank enable bit */ +#define FSMC_PCR4_PTYP ((uint32_t)0x00000008) /*!< Memory type */ + +#define FSMC_PCR4_PWID ((uint32_t)0x00000030) /*!< PWID[1:0] bits (NAND Flash databus width) */ +#define FSMC_PCR4_PWID_0 ((uint32_t)0x00000010) /*!< Bit 0 */ +#define FSMC_PCR4_PWID_1 ((uint32_t)0x00000020) /*!< Bit 1 */ + +#define FSMC_PCR4_ECCEN ((uint32_t)0x00000040) /*!< ECC computation logic enable bit */ + +#define FSMC_PCR4_TCLR ((uint32_t)0x00001E00) /*!< TCLR[3:0] bits (CLE to RE delay) */ +#define FSMC_PCR4_TCLR_0 ((uint32_t)0x00000200) /*!< Bit 0 */ +#define FSMC_PCR4_TCLR_1 ((uint32_t)0x00000400) /*!< Bit 1 */ +#define FSMC_PCR4_TCLR_2 ((uint32_t)0x00000800) /*!< Bit 2 */ +#define FSMC_PCR4_TCLR_3 ((uint32_t)0x00001000) /*!< Bit 3 */ + +#define FSMC_PCR4_TAR ((uint32_t)0x0001E000) /*!< TAR[3:0] bits (ALE to RE delay) */ +#define FSMC_PCR4_TAR_0 ((uint32_t)0x00002000) /*!< Bit 0 */ +#define FSMC_PCR4_TAR_1 ((uint32_t)0x00004000) /*!< Bit 1 */ +#define FSMC_PCR4_TAR_2 ((uint32_t)0x00008000) /*!< Bit 2 */ +#define FSMC_PCR4_TAR_3 ((uint32_t)0x00010000) /*!< Bit 3 */ + +#define FSMC_PCR4_ECCPS ((uint32_t)0x000E0000) /*!< ECCPS[2:0] bits (ECC page size) */ +#define FSMC_PCR4_ECCPS_0 ((uint32_t)0x00020000) /*!< Bit 0 */ +#define FSMC_PCR4_ECCPS_1 ((uint32_t)0x00040000) /*!< Bit 1 */ +#define FSMC_PCR4_ECCPS_2 ((uint32_t)0x00080000) /*!< Bit 2 */ + +/******************* Bit definition for FSMC_SR2 register *******************/ +#define FSMC_SR2_IRS ((uint8_t)0x01) /*!< Interrupt Rising Edge status */ +#define FSMC_SR2_ILS ((uint8_t)0x02) /*!< Interrupt Level status */ +#define FSMC_SR2_IFS ((uint8_t)0x04) /*!< Interrupt Falling Edge status */ +#define FSMC_SR2_IREN ((uint8_t)0x08) /*!< Interrupt Rising Edge detection Enable bit */ +#define FSMC_SR2_ILEN ((uint8_t)0x10) /*!< Interrupt Level detection Enable bit */ +#define FSMC_SR2_IFEN ((uint8_t)0x20) /*!< Interrupt Falling Edge detection Enable bit */ +#define FSMC_SR2_FEMPT ((uint8_t)0x40) /*!< FIFO empty */ + +/******************* Bit definition for FSMC_SR3 register *******************/ +#define FSMC_SR3_IRS ((uint8_t)0x01) /*!< Interrupt Rising Edge status */ +#define FSMC_SR3_ILS ((uint8_t)0x02) /*!< Interrupt Level status */ +#define FSMC_SR3_IFS ((uint8_t)0x04) /*!< Interrupt Falling Edge status */ +#define FSMC_SR3_IREN ((uint8_t)0x08) /*!< Interrupt Rising Edge detection Enable bit */ +#define FSMC_SR3_ILEN ((uint8_t)0x10) /*!< Interrupt Level detection Enable bit */ +#define FSMC_SR3_IFEN ((uint8_t)0x20) /*!< Interrupt Falling Edge detection Enable bit */ +#define FSMC_SR3_FEMPT ((uint8_t)0x40) /*!< FIFO empty */ + +/******************* Bit definition for FSMC_SR4 register *******************/ +#define FSMC_SR4_IRS ((uint8_t)0x01) /*!< Interrupt Rising Edge status */ +#define FSMC_SR4_ILS ((uint8_t)0x02) /*!< Interrupt Level status */ +#define FSMC_SR4_IFS ((uint8_t)0x04) /*!< Interrupt Falling Edge status */ +#define FSMC_SR4_IREN ((uint8_t)0x08) /*!< Interrupt Rising Edge detection Enable bit */ +#define FSMC_SR4_ILEN ((uint8_t)0x10) /*!< Interrupt Level detection Enable bit */ +#define FSMC_SR4_IFEN ((uint8_t)0x20) /*!< Interrupt Falling Edge detection Enable bit */ +#define FSMC_SR4_FEMPT ((uint8_t)0x40) /*!< FIFO empty */ + +/****************** Bit definition for FSMC_PMEM2 register ******************/ +#define FSMC_PMEM2_MEMSET2 ((uint32_t)0x000000FF) /*!< MEMSET2[7:0] bits (Common memory 2 setup time) */ +#define FSMC_PMEM2_MEMSET2_0 ((uint32_t)0x00000001) /*!< Bit 0 */ +#define FSMC_PMEM2_MEMSET2_1 ((uint32_t)0x00000002) /*!< Bit 1 */ +#define FSMC_PMEM2_MEMSET2_2 ((uint32_t)0x00000004) /*!< Bit 2 */ +#define FSMC_PMEM2_MEMSET2_3 ((uint32_t)0x00000008) /*!< Bit 3 */ +#define FSMC_PMEM2_MEMSET2_4 ((uint32_t)0x00000010) /*!< Bit 4 */ +#define FSMC_PMEM2_MEMSET2_5 ((uint32_t)0x00000020) /*!< Bit 5 */ +#define FSMC_PMEM2_MEMSET2_6 ((uint32_t)0x00000040) /*!< Bit 6 */ +#define FSMC_PMEM2_MEMSET2_7 ((uint32_t)0x00000080) /*!< Bit 7 */ + +#define FSMC_PMEM2_MEMWAIT2 ((uint32_t)0x0000FF00) /*!< MEMWAIT2[7:0] bits (Common memory 2 wait time) */ +#define FSMC_PMEM2_MEMWAIT2_0 ((uint32_t)0x00000100) /*!< Bit 0 */ +#define FSMC_PMEM2_MEMWAIT2_1 ((uint32_t)0x00000200) /*!< Bit 1 */ +#define FSMC_PMEM2_MEMWAIT2_2 ((uint32_t)0x00000400) /*!< Bit 2 */ +#define FSMC_PMEM2_MEMWAIT2_3 ((uint32_t)0x00000800) /*!< Bit 3 */ +#define FSMC_PMEM2_MEMWAIT2_4 ((uint32_t)0x00001000) /*!< Bit 4 */ +#define FSMC_PMEM2_MEMWAIT2_5 ((uint32_t)0x00002000) /*!< Bit 5 */ +#define FSMC_PMEM2_MEMWAIT2_6 ((uint32_t)0x00004000) /*!< Bit 6 */ +#define FSMC_PMEM2_MEMWAIT2_7 ((uint32_t)0x00008000) /*!< Bit 7 */ + +#define FSMC_PMEM2_MEMHOLD2 ((uint32_t)0x00FF0000) /*!< MEMHOLD2[7:0] bits (Common memory 2 hold time) */ +#define FSMC_PMEM2_MEMHOLD2_0 ((uint32_t)0x00010000) /*!< Bit 0 */ +#define FSMC_PMEM2_MEMHOLD2_1 ((uint32_t)0x00020000) /*!< Bit 1 */ +#define FSMC_PMEM2_MEMHOLD2_2 ((uint32_t)0x00040000) /*!< Bit 2 */ +#define FSMC_PMEM2_MEMHOLD2_3 ((uint32_t)0x00080000) /*!< Bit 3 */ +#define FSMC_PMEM2_MEMHOLD2_4 ((uint32_t)0x00100000) /*!< Bit 4 */ +#define FSMC_PMEM2_MEMHOLD2_5 ((uint32_t)0x00200000) /*!< Bit 5 */ +#define FSMC_PMEM2_MEMHOLD2_6 ((uint32_t)0x00400000) /*!< Bit 6 */ +#define FSMC_PMEM2_MEMHOLD2_7 ((uint32_t)0x00800000) /*!< Bit 7 */ + +#define FSMC_PMEM2_MEMHIZ2 ((uint32_t)0xFF000000) /*!< MEMHIZ2[7:0] bits (Common memory 2 databus HiZ time) */ +#define FSMC_PMEM2_MEMHIZ2_0 ((uint32_t)0x01000000) /*!< Bit 0 */ +#define FSMC_PMEM2_MEMHIZ2_1 ((uint32_t)0x02000000) /*!< Bit 1 */ +#define FSMC_PMEM2_MEMHIZ2_2 ((uint32_t)0x04000000) /*!< Bit 2 */ +#define FSMC_PMEM2_MEMHIZ2_3 ((uint32_t)0x08000000) /*!< Bit 3 */ +#define FSMC_PMEM2_MEMHIZ2_4 ((uint32_t)0x10000000) /*!< Bit 4 */ +#define FSMC_PMEM2_MEMHIZ2_5 ((uint32_t)0x20000000) /*!< Bit 5 */ +#define FSMC_PMEM2_MEMHIZ2_6 ((uint32_t)0x40000000) /*!< Bit 6 */ +#define FSMC_PMEM2_MEMHIZ2_7 ((uint32_t)0x80000000) /*!< Bit 7 */ + +/****************** Bit definition for FSMC_PMEM3 register ******************/ +#define FSMC_PMEM3_MEMSET3 ((uint32_t)0x000000FF) /*!< MEMSET3[7:0] bits (Common memory 3 setup time) */ +#define FSMC_PMEM3_MEMSET3_0 ((uint32_t)0x00000001) /*!< Bit 0 */ +#define FSMC_PMEM3_MEMSET3_1 ((uint32_t)0x00000002) /*!< Bit 1 */ +#define FSMC_PMEM3_MEMSET3_2 ((uint32_t)0x00000004) /*!< Bit 2 */ +#define FSMC_PMEM3_MEMSET3_3 ((uint32_t)0x00000008) /*!< Bit 3 */ +#define FSMC_PMEM3_MEMSET3_4 ((uint32_t)0x00000010) /*!< Bit 4 */ +#define FSMC_PMEM3_MEMSET3_5 ((uint32_t)0x00000020) /*!< Bit 5 */ +#define FSMC_PMEM3_MEMSET3_6 ((uint32_t)0x00000040) /*!< Bit 6 */ +#define FSMC_PMEM3_MEMSET3_7 ((uint32_t)0x00000080) /*!< Bit 7 */ + +#define FSMC_PMEM3_MEMWAIT3 ((uint32_t)0x0000FF00) /*!< MEMWAIT3[7:0] bits (Common memory 3 wait time) */ +#define FSMC_PMEM3_MEMWAIT3_0 ((uint32_t)0x00000100) /*!< Bit 0 */ +#define FSMC_PMEM3_MEMWAIT3_1 ((uint32_t)0x00000200) /*!< Bit 1 */ +#define FSMC_PMEM3_MEMWAIT3_2 ((uint32_t)0x00000400) /*!< Bit 2 */ +#define FSMC_PMEM3_MEMWAIT3_3 ((uint32_t)0x00000800) /*!< Bit 3 */ +#define FSMC_PMEM3_MEMWAIT3_4 ((uint32_t)0x00001000) /*!< Bit 4 */ +#define FSMC_PMEM3_MEMWAIT3_5 ((uint32_t)0x00002000) /*!< Bit 5 */ +#define FSMC_PMEM3_MEMWAIT3_6 ((uint32_t)0x00004000) /*!< Bit 6 */ +#define FSMC_PMEM3_MEMWAIT3_7 ((uint32_t)0x00008000) /*!< Bit 7 */ + +#define FSMC_PMEM3_MEMHOLD3 ((uint32_t)0x00FF0000) /*!< MEMHOLD3[7:0] bits (Common memory 3 hold time) */ +#define FSMC_PMEM3_MEMHOLD3_0 ((uint32_t)0x00010000) /*!< Bit 0 */ +#define FSMC_PMEM3_MEMHOLD3_1 ((uint32_t)0x00020000) /*!< Bit 1 */ +#define FSMC_PMEM3_MEMHOLD3_2 ((uint32_t)0x00040000) /*!< Bit 2 */ +#define FSMC_PMEM3_MEMHOLD3_3 ((uint32_t)0x00080000) /*!< Bit 3 */ +#define FSMC_PMEM3_MEMHOLD3_4 ((uint32_t)0x00100000) /*!< Bit 4 */ +#define FSMC_PMEM3_MEMHOLD3_5 ((uint32_t)0x00200000) /*!< Bit 5 */ +#define FSMC_PMEM3_MEMHOLD3_6 ((uint32_t)0x00400000) /*!< Bit 6 */ +#define FSMC_PMEM3_MEMHOLD3_7 ((uint32_t)0x00800000) /*!< Bit 7 */ + +#define FSMC_PMEM3_MEMHIZ3 ((uint32_t)0xFF000000) /*!< MEMHIZ3[7:0] bits (Common memory 3 databus HiZ time) */ +#define FSMC_PMEM3_MEMHIZ3_0 ((uint32_t)0x01000000) /*!< Bit 0 */ +#define FSMC_PMEM3_MEMHIZ3_1 ((uint32_t)0x02000000) /*!< Bit 1 */ +#define FSMC_PMEM3_MEMHIZ3_2 ((uint32_t)0x04000000) /*!< Bit 2 */ +#define FSMC_PMEM3_MEMHIZ3_3 ((uint32_t)0x08000000) /*!< Bit 3 */ +#define FSMC_PMEM3_MEMHIZ3_4 ((uint32_t)0x10000000) /*!< Bit 4 */ +#define FSMC_PMEM3_MEMHIZ3_5 ((uint32_t)0x20000000) /*!< Bit 5 */ +#define FSMC_PMEM3_MEMHIZ3_6 ((uint32_t)0x40000000) /*!< Bit 6 */ +#define FSMC_PMEM3_MEMHIZ3_7 ((uint32_t)0x80000000) /*!< Bit 7 */ + +/****************** Bit definition for FSMC_PMEM4 register ******************/ +#define FSMC_PMEM4_MEMSET4 ((uint32_t)0x000000FF) /*!< MEMSET4[7:0] bits (Common memory 4 setup time) */ +#define FSMC_PMEM4_MEMSET4_0 ((uint32_t)0x00000001) /*!< Bit 0 */ +#define FSMC_PMEM4_MEMSET4_1 ((uint32_t)0x00000002) /*!< Bit 1 */ +#define FSMC_PMEM4_MEMSET4_2 ((uint32_t)0x00000004) /*!< Bit 2 */ +#define FSMC_PMEM4_MEMSET4_3 ((uint32_t)0x00000008) /*!< Bit 3 */ +#define FSMC_PMEM4_MEMSET4_4 ((uint32_t)0x00000010) /*!< Bit 4 */ +#define FSMC_PMEM4_MEMSET4_5 ((uint32_t)0x00000020) /*!< Bit 5 */ +#define FSMC_PMEM4_MEMSET4_6 ((uint32_t)0x00000040) /*!< Bit 6 */ +#define FSMC_PMEM4_MEMSET4_7 ((uint32_t)0x00000080) /*!< Bit 7 */ + +#define FSMC_PMEM4_MEMWAIT4 ((uint32_t)0x0000FF00) /*!< MEMWAIT4[7:0] bits (Common memory 4 wait time) */ +#define FSMC_PMEM4_MEMWAIT4_0 ((uint32_t)0x00000100) /*!< Bit 0 */ +#define FSMC_PMEM4_MEMWAIT4_1 ((uint32_t)0x00000200) /*!< Bit 1 */ +#define FSMC_PMEM4_MEMWAIT4_2 ((uint32_t)0x00000400) /*!< Bit 2 */ +#define FSMC_PMEM4_MEMWAIT4_3 ((uint32_t)0x00000800) /*!< Bit 3 */ +#define FSMC_PMEM4_MEMWAIT4_4 ((uint32_t)0x00001000) /*!< Bit 4 */ +#define FSMC_PMEM4_MEMWAIT4_5 ((uint32_t)0x00002000) /*!< Bit 5 */ +#define FSMC_PMEM4_MEMWAIT4_6 ((uint32_t)0x00004000) /*!< Bit 6 */ +#define FSMC_PMEM4_MEMWAIT4_7 ((uint32_t)0x00008000) /*!< Bit 7 */ + +#define FSMC_PMEM4_MEMHOLD4 ((uint32_t)0x00FF0000) /*!< MEMHOLD4[7:0] bits (Common memory 4 hold time) */ +#define FSMC_PMEM4_MEMHOLD4_0 ((uint32_t)0x00010000) /*!< Bit 0 */ +#define FSMC_PMEM4_MEMHOLD4_1 ((uint32_t)0x00020000) /*!< Bit 1 */ +#define FSMC_PMEM4_MEMHOLD4_2 ((uint32_t)0x00040000) /*!< Bit 2 */ +#define FSMC_PMEM4_MEMHOLD4_3 ((uint32_t)0x00080000) /*!< Bit 3 */ +#define FSMC_PMEM4_MEMHOLD4_4 ((uint32_t)0x00100000) /*!< Bit 4 */ +#define FSMC_PMEM4_MEMHOLD4_5 ((uint32_t)0x00200000) /*!< Bit 5 */ +#define FSMC_PMEM4_MEMHOLD4_6 ((uint32_t)0x00400000) /*!< Bit 6 */ +#define FSMC_PMEM4_MEMHOLD4_7 ((uint32_t)0x00800000) /*!< Bit 7 */ + +#define FSMC_PMEM4_MEMHIZ4 ((uint32_t)0xFF000000) /*!< MEMHIZ4[7:0] bits (Common memory 4 databus HiZ time) */ +#define FSMC_PMEM4_MEMHIZ4_0 ((uint32_t)0x01000000) /*!< Bit 0 */ +#define FSMC_PMEM4_MEMHIZ4_1 ((uint32_t)0x02000000) /*!< Bit 1 */ +#define FSMC_PMEM4_MEMHIZ4_2 ((uint32_t)0x04000000) /*!< Bit 2 */ +#define FSMC_PMEM4_MEMHIZ4_3 ((uint32_t)0x08000000) /*!< Bit 3 */ +#define FSMC_PMEM4_MEMHIZ4_4 ((uint32_t)0x10000000) /*!< Bit 4 */ +#define FSMC_PMEM4_MEMHIZ4_5 ((uint32_t)0x20000000) /*!< Bit 5 */ +#define FSMC_PMEM4_MEMHIZ4_6 ((uint32_t)0x40000000) /*!< Bit 6 */ +#define FSMC_PMEM4_MEMHIZ4_7 ((uint32_t)0x80000000) /*!< Bit 7 */ + +/****************** Bit definition for FSMC_PATT2 register ******************/ +#define FSMC_PATT2_ATTSET2 ((uint32_t)0x000000FF) /*!< ATTSET2[7:0] bits (Attribute memory 2 setup time) */ +#define FSMC_PATT2_ATTSET2_0 ((uint32_t)0x00000001) /*!< Bit 0 */ +#define FSMC_PATT2_ATTSET2_1 ((uint32_t)0x00000002) /*!< Bit 1 */ +#define FSMC_PATT2_ATTSET2_2 ((uint32_t)0x00000004) /*!< Bit 2 */ +#define FSMC_PATT2_ATTSET2_3 ((uint32_t)0x00000008) /*!< Bit 3 */ +#define FSMC_PATT2_ATTSET2_4 ((uint32_t)0x00000010) /*!< Bit 4 */ +#define FSMC_PATT2_ATTSET2_5 ((uint32_t)0x00000020) /*!< Bit 5 */ +#define FSMC_PATT2_ATTSET2_6 ((uint32_t)0x00000040) /*!< Bit 6 */ +#define FSMC_PATT2_ATTSET2_7 ((uint32_t)0x00000080) /*!< Bit 7 */ + +#define FSMC_PATT2_ATTWAIT2 ((uint32_t)0x0000FF00) /*!< ATTWAIT2[7:0] bits (Attribute memory 2 wait time) */ +#define FSMC_PATT2_ATTWAIT2_0 ((uint32_t)0x00000100) /*!< Bit 0 */ +#define FSMC_PATT2_ATTWAIT2_1 ((uint32_t)0x00000200) /*!< Bit 1 */ +#define FSMC_PATT2_ATTWAIT2_2 ((uint32_t)0x00000400) /*!< Bit 2 */ +#define FSMC_PATT2_ATTWAIT2_3 ((uint32_t)0x00000800) /*!< Bit 3 */ +#define FSMC_PATT2_ATTWAIT2_4 ((uint32_t)0x00001000) /*!< Bit 4 */ +#define FSMC_PATT2_ATTWAIT2_5 ((uint32_t)0x00002000) /*!< Bit 5 */ +#define FSMC_PATT2_ATTWAIT2_6 ((uint32_t)0x00004000) /*!< Bit 6 */ +#define FSMC_PATT2_ATTWAIT2_7 ((uint32_t)0x00008000) /*!< Bit 7 */ + +#define FSMC_PATT2_ATTHOLD2 ((uint32_t)0x00FF0000) /*!< ATTHOLD2[7:0] bits (Attribute memory 2 hold time) */ +#define FSMC_PATT2_ATTHOLD2_0 ((uint32_t)0x00010000) /*!< Bit 0 */ +#define FSMC_PATT2_ATTHOLD2_1 ((uint32_t)0x00020000) /*!< Bit 1 */ +#define FSMC_PATT2_ATTHOLD2_2 ((uint32_t)0x00040000) /*!< Bit 2 */ +#define FSMC_PATT2_ATTHOLD2_3 ((uint32_t)0x00080000) /*!< Bit 3 */ +#define FSMC_PATT2_ATTHOLD2_4 ((uint32_t)0x00100000) /*!< Bit 4 */ +#define FSMC_PATT2_ATTHOLD2_5 ((uint32_t)0x00200000) /*!< Bit 5 */ +#define FSMC_PATT2_ATTHOLD2_6 ((uint32_t)0x00400000) /*!< Bit 6 */ +#define FSMC_PATT2_ATTHOLD2_7 ((uint32_t)0x00800000) /*!< Bit 7 */ + +#define FSMC_PATT2_ATTHIZ2 ((uint32_t)0xFF000000) /*!< ATTHIZ2[7:0] bits (Attribute memory 2 databus HiZ time) */ +#define FSMC_PATT2_ATTHIZ2_0 ((uint32_t)0x01000000) /*!< Bit 0 */ +#define FSMC_PATT2_ATTHIZ2_1 ((uint32_t)0x02000000) /*!< Bit 1 */ +#define FSMC_PATT2_ATTHIZ2_2 ((uint32_t)0x04000000) /*!< Bit 2 */ +#define FSMC_PATT2_ATTHIZ2_3 ((uint32_t)0x08000000) /*!< Bit 3 */ +#define FSMC_PATT2_ATTHIZ2_4 ((uint32_t)0x10000000) /*!< Bit 4 */ +#define FSMC_PATT2_ATTHIZ2_5 ((uint32_t)0x20000000) /*!< Bit 5 */ +#define FSMC_PATT2_ATTHIZ2_6 ((uint32_t)0x40000000) /*!< Bit 6 */ +#define FSMC_PATT2_ATTHIZ2_7 ((uint32_t)0x80000000) /*!< Bit 7 */ + +/****************** Bit definition for FSMC_PATT3 register ******************/ +#define FSMC_PATT3_ATTSET3 ((uint32_t)0x000000FF) /*!< ATTSET3[7:0] bits (Attribute memory 3 setup time) */ +#define FSMC_PATT3_ATTSET3_0 ((uint32_t)0x00000001) /*!< Bit 0 */ +#define FSMC_PATT3_ATTSET3_1 ((uint32_t)0x00000002) /*!< Bit 1 */ +#define FSMC_PATT3_ATTSET3_2 ((uint32_t)0x00000004) /*!< Bit 2 */ +#define FSMC_PATT3_ATTSET3_3 ((uint32_t)0x00000008) /*!< Bit 3 */ +#define FSMC_PATT3_ATTSET3_4 ((uint32_t)0x00000010) /*!< Bit 4 */ +#define FSMC_PATT3_ATTSET3_5 ((uint32_t)0x00000020) /*!< Bit 5 */ +#define FSMC_PATT3_ATTSET3_6 ((uint32_t)0x00000040) /*!< Bit 6 */ +#define FSMC_PATT3_ATTSET3_7 ((uint32_t)0x00000080) /*!< Bit 7 */ + +#define FSMC_PATT3_ATTWAIT3 ((uint32_t)0x0000FF00) /*!< ATTWAIT3[7:0] bits (Attribute memory 3 wait time) */ +#define FSMC_PATT3_ATTWAIT3_0 ((uint32_t)0x00000100) /*!< Bit 0 */ +#define FSMC_PATT3_ATTWAIT3_1 ((uint32_t)0x00000200) /*!< Bit 1 */ +#define FSMC_PATT3_ATTWAIT3_2 ((uint32_t)0x00000400) /*!< Bit 2 */ +#define FSMC_PATT3_ATTWAIT3_3 ((uint32_t)0x00000800) /*!< Bit 3 */ +#define FSMC_PATT3_ATTWAIT3_4 ((uint32_t)0x00001000) /*!< Bit 4 */ +#define FSMC_PATT3_ATTWAIT3_5 ((uint32_t)0x00002000) /*!< Bit 5 */ +#define FSMC_PATT3_ATTWAIT3_6 ((uint32_t)0x00004000) /*!< Bit 6 */ +#define FSMC_PATT3_ATTWAIT3_7 ((uint32_t)0x00008000) /*!< Bit 7 */ + +#define FSMC_PATT3_ATTHOLD3 ((uint32_t)0x00FF0000) /*!< ATTHOLD3[7:0] bits (Attribute memory 3 hold time) */ +#define FSMC_PATT3_ATTHOLD3_0 ((uint32_t)0x00010000) /*!< Bit 0 */ +#define FSMC_PATT3_ATTHOLD3_1 ((uint32_t)0x00020000) /*!< Bit 1 */ +#define FSMC_PATT3_ATTHOLD3_2 ((uint32_t)0x00040000) /*!< Bit 2 */ +#define FSMC_PATT3_ATTHOLD3_3 ((uint32_t)0x00080000) /*!< Bit 3 */ +#define FSMC_PATT3_ATTHOLD3_4 ((uint32_t)0x00100000) /*!< Bit 4 */ +#define FSMC_PATT3_ATTHOLD3_5 ((uint32_t)0x00200000) /*!< Bit 5 */ +#define FSMC_PATT3_ATTHOLD3_6 ((uint32_t)0x00400000) /*!< Bit 6 */ +#define FSMC_PATT3_ATTHOLD3_7 ((uint32_t)0x00800000) /*!< Bit 7 */ + +#define FSMC_PATT3_ATTHIZ3 ((uint32_t)0xFF000000) /*!< ATTHIZ3[7:0] bits (Attribute memory 3 databus HiZ time) */ +#define FSMC_PATT3_ATTHIZ3_0 ((uint32_t)0x01000000) /*!< Bit 0 */ +#define FSMC_PATT3_ATTHIZ3_1 ((uint32_t)0x02000000) /*!< Bit 1 */ +#define FSMC_PATT3_ATTHIZ3_2 ((uint32_t)0x04000000) /*!< Bit 2 */ +#define FSMC_PATT3_ATTHIZ3_3 ((uint32_t)0x08000000) /*!< Bit 3 */ +#define FSMC_PATT3_ATTHIZ3_4 ((uint32_t)0x10000000) /*!< Bit 4 */ +#define FSMC_PATT3_ATTHIZ3_5 ((uint32_t)0x20000000) /*!< Bit 5 */ +#define FSMC_PATT3_ATTHIZ3_6 ((uint32_t)0x40000000) /*!< Bit 6 */ +#define FSMC_PATT3_ATTHIZ3_7 ((uint32_t)0x80000000) /*!< Bit 7 */ + +/****************** Bit definition for FSMC_PATT4 register ******************/ +#define FSMC_PATT4_ATTSET4 ((uint32_t)0x000000FF) /*!< ATTSET4[7:0] bits (Attribute memory 4 setup time) */ +#define FSMC_PATT4_ATTSET4_0 ((uint32_t)0x00000001) /*!< Bit 0 */ +#define FSMC_PATT4_ATTSET4_1 ((uint32_t)0x00000002) /*!< Bit 1 */ +#define FSMC_PATT4_ATTSET4_2 ((uint32_t)0x00000004) /*!< Bit 2 */ +#define FSMC_PATT4_ATTSET4_3 ((uint32_t)0x00000008) /*!< Bit 3 */ +#define FSMC_PATT4_ATTSET4_4 ((uint32_t)0x00000010) /*!< Bit 4 */ +#define FSMC_PATT4_ATTSET4_5 ((uint32_t)0x00000020) /*!< Bit 5 */ +#define FSMC_PATT4_ATTSET4_6 ((uint32_t)0x00000040) /*!< Bit 6 */ +#define FSMC_PATT4_ATTSET4_7 ((uint32_t)0x00000080) /*!< Bit 7 */ + +#define FSMC_PATT4_ATTWAIT4 ((uint32_t)0x0000FF00) /*!< ATTWAIT4[7:0] bits (Attribute memory 4 wait time) */ +#define FSMC_PATT4_ATTWAIT4_0 ((uint32_t)0x00000100) /*!< Bit 0 */ +#define FSMC_PATT4_ATTWAIT4_1 ((uint32_t)0x00000200) /*!< Bit 1 */ +#define FSMC_PATT4_ATTWAIT4_2 ((uint32_t)0x00000400) /*!< Bit 2 */ +#define FSMC_PATT4_ATTWAIT4_3 ((uint32_t)0x00000800) /*!< Bit 3 */ +#define FSMC_PATT4_ATTWAIT4_4 ((uint32_t)0x00001000) /*!< Bit 4 */ +#define FSMC_PATT4_ATTWAIT4_5 ((uint32_t)0x00002000) /*!< Bit 5 */ +#define FSMC_PATT4_ATTWAIT4_6 ((uint32_t)0x00004000) /*!< Bit 6 */ +#define FSMC_PATT4_ATTWAIT4_7 ((uint32_t)0x00008000) /*!< Bit 7 */ + +#define FSMC_PATT4_ATTHOLD4 ((uint32_t)0x00FF0000) /*!< ATTHOLD4[7:0] bits (Attribute memory 4 hold time) */ +#define FSMC_PATT4_ATTHOLD4_0 ((uint32_t)0x00010000) /*!< Bit 0 */ +#define FSMC_PATT4_ATTHOLD4_1 ((uint32_t)0x00020000) /*!< Bit 1 */ +#define FSMC_PATT4_ATTHOLD4_2 ((uint32_t)0x00040000) /*!< Bit 2 */ +#define FSMC_PATT4_ATTHOLD4_3 ((uint32_t)0x00080000) /*!< Bit 3 */ +#define FSMC_PATT4_ATTHOLD4_4 ((uint32_t)0x00100000) /*!< Bit 4 */ +#define FSMC_PATT4_ATTHOLD4_5 ((uint32_t)0x00200000) /*!< Bit 5 */ +#define FSMC_PATT4_ATTHOLD4_6 ((uint32_t)0x00400000) /*!< Bit 6 */ +#define FSMC_PATT4_ATTHOLD4_7 ((uint32_t)0x00800000) /*!< Bit 7 */ + +#define FSMC_PATT4_ATTHIZ4 ((uint32_t)0xFF000000) /*!< ATTHIZ4[7:0] bits (Attribute memory 4 databus HiZ time) */ +#define FSMC_PATT4_ATTHIZ4_0 ((uint32_t)0x01000000) /*!< Bit 0 */ +#define FSMC_PATT4_ATTHIZ4_1 ((uint32_t)0x02000000) /*!< Bit 1 */ +#define FSMC_PATT4_ATTHIZ4_2 ((uint32_t)0x04000000) /*!< Bit 2 */ +#define FSMC_PATT4_ATTHIZ4_3 ((uint32_t)0x08000000) /*!< Bit 3 */ +#define FSMC_PATT4_ATTHIZ4_4 ((uint32_t)0x10000000) /*!< Bit 4 */ +#define FSMC_PATT4_ATTHIZ4_5 ((uint32_t)0x20000000) /*!< Bit 5 */ +#define FSMC_PATT4_ATTHIZ4_6 ((uint32_t)0x40000000) /*!< Bit 6 */ +#define FSMC_PATT4_ATTHIZ4_7 ((uint32_t)0x80000000) /*!< Bit 7 */ + +/****************** Bit definition for FSMC_PIO4 register *******************/ +#define FSMC_PIO4_IOSET4 ((uint32_t)0x000000FF) /*!< IOSET4[7:0] bits (I/O 4 setup time) */ +#define FSMC_PIO4_IOSET4_0 ((uint32_t)0x00000001) /*!< Bit 0 */ +#define FSMC_PIO4_IOSET4_1 ((uint32_t)0x00000002) /*!< Bit 1 */ +#define FSMC_PIO4_IOSET4_2 ((uint32_t)0x00000004) /*!< Bit 2 */ +#define FSMC_PIO4_IOSET4_3 ((uint32_t)0x00000008) /*!< Bit 3 */ +#define FSMC_PIO4_IOSET4_4 ((uint32_t)0x00000010) /*!< Bit 4 */ +#define FSMC_PIO4_IOSET4_5 ((uint32_t)0x00000020) /*!< Bit 5 */ +#define FSMC_PIO4_IOSET4_6 ((uint32_t)0x00000040) /*!< Bit 6 */ +#define FSMC_PIO4_IOSET4_7 ((uint32_t)0x00000080) /*!< Bit 7 */ + +#define FSMC_PIO4_IOWAIT4 ((uint32_t)0x0000FF00) /*!< IOWAIT4[7:0] bits (I/O 4 wait time) */ +#define FSMC_PIO4_IOWAIT4_0 ((uint32_t)0x00000100) /*!< Bit 0 */ +#define FSMC_PIO4_IOWAIT4_1 ((uint32_t)0x00000200) /*!< Bit 1 */ +#define FSMC_PIO4_IOWAIT4_2 ((uint32_t)0x00000400) /*!< Bit 2 */ +#define FSMC_PIO4_IOWAIT4_3 ((uint32_t)0x00000800) /*!< Bit 3 */ +#define FSMC_PIO4_IOWAIT4_4 ((uint32_t)0x00001000) /*!< Bit 4 */ +#define FSMC_PIO4_IOWAIT4_5 ((uint32_t)0x00002000) /*!< Bit 5 */ +#define FSMC_PIO4_IOWAIT4_6 ((uint32_t)0x00004000) /*!< Bit 6 */ +#define FSMC_PIO4_IOWAIT4_7 ((uint32_t)0x00008000) /*!< Bit 7 */ + +#define FSMC_PIO4_IOHOLD4 ((uint32_t)0x00FF0000) /*!< IOHOLD4[7:0] bits (I/O 4 hold time) */ +#define FSMC_PIO4_IOHOLD4_0 ((uint32_t)0x00010000) /*!< Bit 0 */ +#define FSMC_PIO4_IOHOLD4_1 ((uint32_t)0x00020000) /*!< Bit 1 */ +#define FSMC_PIO4_IOHOLD4_2 ((uint32_t)0x00040000) /*!< Bit 2 */ +#define FSMC_PIO4_IOHOLD4_3 ((uint32_t)0x00080000) /*!< Bit 3 */ +#define FSMC_PIO4_IOHOLD4_4 ((uint32_t)0x00100000) /*!< Bit 4 */ +#define FSMC_PIO4_IOHOLD4_5 ((uint32_t)0x00200000) /*!< Bit 5 */ +#define FSMC_PIO4_IOHOLD4_6 ((uint32_t)0x00400000) /*!< Bit 6 */ +#define FSMC_PIO4_IOHOLD4_7 ((uint32_t)0x00800000) /*!< Bit 7 */ + +#define FSMC_PIO4_IOHIZ4 ((uint32_t)0xFF000000) /*!< IOHIZ4[7:0] bits (I/O 4 databus HiZ time) */ +#define FSMC_PIO4_IOHIZ4_0 ((uint32_t)0x01000000) /*!< Bit 0 */ +#define FSMC_PIO4_IOHIZ4_1 ((uint32_t)0x02000000) /*!< Bit 1 */ +#define FSMC_PIO4_IOHIZ4_2 ((uint32_t)0x04000000) /*!< Bit 2 */ +#define FSMC_PIO4_IOHIZ4_3 ((uint32_t)0x08000000) /*!< Bit 3 */ +#define FSMC_PIO4_IOHIZ4_4 ((uint32_t)0x10000000) /*!< Bit 4 */ +#define FSMC_PIO4_IOHIZ4_5 ((uint32_t)0x20000000) /*!< Bit 5 */ +#define FSMC_PIO4_IOHIZ4_6 ((uint32_t)0x40000000) /*!< Bit 6 */ +#define FSMC_PIO4_IOHIZ4_7 ((uint32_t)0x80000000) /*!< Bit 7 */ + +/****************** Bit definition for FSMC_ECCR2 register ******************/ +#define FSMC_ECCR2_ECC2 ((uint32_t)0xFFFFFFFF) /*!< ECC result */ + +/****************** Bit definition for FSMC_ECCR3 register ******************/ +#define FSMC_ECCR3_ECC3 ((uint32_t)0xFFFFFFFF) /*!< ECC result */ + +/******************************************************************************/ +/* */ +/* SD host Interface */ +/* */ +/******************************************************************************/ + +/****************** Bit definition for SDIO_POWER register ******************/ +#define SDIO_POWER_PWRCTRL ((uint8_t)0x03) /*!< PWRCTRL[1:0] bits (Power supply control bits) */ +#define SDIO_POWER_PWRCTRL_0 ((uint8_t)0x01) /*!< Bit 0 */ +#define SDIO_POWER_PWRCTRL_1 ((uint8_t)0x02) /*!< Bit 1 */ + +/****************** Bit definition for SDIO_CLKCR register ******************/ +#define SDIO_CLKCR_CLKDIV ((uint16_t)0x00FF) /*!< Clock divide factor */ +#define SDIO_CLKCR_CLKEN ((uint16_t)0x0100) /*!< Clock enable bit */ +#define SDIO_CLKCR_PWRSAV ((uint16_t)0x0200) /*!< Power saving configuration bit */ +#define SDIO_CLKCR_BYPASS ((uint16_t)0x0400) /*!< Clock divider bypass enable bit */ + +#define SDIO_CLKCR_WIDBUS ((uint16_t)0x1800) /*!< WIDBUS[1:0] bits (Wide bus mode enable bit) */ +#define SDIO_CLKCR_WIDBUS_0 ((uint16_t)0x0800) /*!< Bit 0 */ +#define SDIO_CLKCR_WIDBUS_1 ((uint16_t)0x1000) /*!< Bit 1 */ + +#define SDIO_CLKCR_NEGEDGE ((uint16_t)0x2000) /*!< SDIO_CK dephasing selection bit */ +#define SDIO_CLKCR_HWFC_EN ((uint16_t)0x4000) /*!< HW Flow Control enable */ + +/******************* Bit definition for SDIO_ARG register *******************/ +#define SDIO_ARG_CMDARG ((uint32_t)0xFFFFFFFF) /*!< Command argument */ + +/******************* Bit definition for SDIO_CMD register *******************/ +#define SDIO_CMD_CMDINDEX ((uint16_t)0x003F) /*!< Command Index */ + +#define SDIO_CMD_WAITRESP ((uint16_t)0x00C0) /*!< WAITRESP[1:0] bits (Wait for response bits) */ +#define SDIO_CMD_WAITRESP_0 ((uint16_t)0x0040) /*!< Bit 0 */ +#define SDIO_CMD_WAITRESP_1 ((uint16_t)0x0080) /*!< Bit 1 */ + +#define SDIO_CMD_WAITINT ((uint16_t)0x0100) /*!< CPSM Waits for Interrupt Request */ +#define SDIO_CMD_WAITPEND ((uint16_t)0x0200) /*!< CPSM Waits for ends of data transfer (CmdPend internal signal) */ +#define SDIO_CMD_CPSMEN ((uint16_t)0x0400) /*!< Command path state machine (CPSM) Enable bit */ +#define SDIO_CMD_SDIOSUSPEND ((uint16_t)0x0800) /*!< SD I/O suspend command */ +#define SDIO_CMD_ENCMDCOMPL ((uint16_t)0x1000) /*!< Enable CMD completion */ +#define SDIO_CMD_NIEN ((uint16_t)0x2000) /*!< Not Interrupt Enable */ +#define SDIO_CMD_CEATACMD ((uint16_t)0x4000) /*!< CE-ATA command */ + +/***************** Bit definition for SDIO_RESPCMD register *****************/ +#define SDIO_RESPCMD_RESPCMD ((uint8_t)0x3F) /*!< Response command index */ + +/****************** Bit definition for SDIO_RESP0 register ******************/ +#define SDIO_RESP0_CARDSTATUS0 ((uint32_t)0xFFFFFFFF) /*!< Card Status */ + +/****************** Bit definition for SDIO_RESP1 register ******************/ +#define SDIO_RESP1_CARDSTATUS1 ((uint32_t)0xFFFFFFFF) /*!< Card Status */ + +/****************** Bit definition for SDIO_RESP2 register ******************/ +#define SDIO_RESP2_CARDSTATUS2 ((uint32_t)0xFFFFFFFF) /*!< Card Status */ + +/****************** Bit definition for SDIO_RESP3 register ******************/ +#define SDIO_RESP3_CARDSTATUS3 ((uint32_t)0xFFFFFFFF) /*!< Card Status */ + +/****************** Bit definition for SDIO_RESP4 register ******************/ +#define SDIO_RESP4_CARDSTATUS4 ((uint32_t)0xFFFFFFFF) /*!< Card Status */ + +/****************** Bit definition for SDIO_DTIMER register *****************/ +#define SDIO_DTIMER_DATATIME ((uint32_t)0xFFFFFFFF) /*!< Data timeout period. */ + +/****************** Bit definition for SDIO_DLEN register *******************/ +#define SDIO_DLEN_DATALENGTH ((uint32_t)0x01FFFFFF) /*!< Data length value */ + +/****************** Bit definition for SDIO_DCTRL register ******************/ +#define SDIO_DCTRL_DTEN ((uint16_t)0x0001) /*!< Data transfer enabled bit */ +#define SDIO_DCTRL_DTDIR ((uint16_t)0x0002) /*!< Data transfer direction selection */ +#define SDIO_DCTRL_DTMODE ((uint16_t)0x0004) /*!< Data transfer mode selection */ +#define SDIO_DCTRL_DMAEN ((uint16_t)0x0008) /*!< DMA enabled bit */ + +#define SDIO_DCTRL_DBLOCKSIZE ((uint16_t)0x00F0) /*!< DBLOCKSIZE[3:0] bits (Data block size) */ +#define SDIO_DCTRL_DBLOCKSIZE_0 ((uint16_t)0x0010) /*!< Bit 0 */ +#define SDIO_DCTRL_DBLOCKSIZE_1 ((uint16_t)0x0020) /*!< Bit 1 */ +#define SDIO_DCTRL_DBLOCKSIZE_2 ((uint16_t)0x0040) /*!< Bit 2 */ +#define SDIO_DCTRL_DBLOCKSIZE_3 ((uint16_t)0x0080) /*!< Bit 3 */ + +#define SDIO_DCTRL_RWSTART ((uint16_t)0x0100) /*!< Read wait start */ +#define SDIO_DCTRL_RWSTOP ((uint16_t)0x0200) /*!< Read wait stop */ +#define SDIO_DCTRL_RWMOD ((uint16_t)0x0400) /*!< Read wait mode */ +#define SDIO_DCTRL_SDIOEN ((uint16_t)0x0800) /*!< SD I/O enable functions */ + +/****************** Bit definition for SDIO_DCOUNT register *****************/ +#define SDIO_DCOUNT_DATACOUNT ((uint32_t)0x01FFFFFF) /*!< Data count value */ + +/****************** Bit definition for SDIO_STA register ********************/ +#define SDIO_STA_CCRCFAIL ((uint32_t)0x00000001) /*!< Command response received (CRC check failed) */ +#define SDIO_STA_DCRCFAIL ((uint32_t)0x00000002) /*!< Data block sent/received (CRC check failed) */ +#define SDIO_STA_CTIMEOUT ((uint32_t)0x00000004) /*!< Command response timeout */ +#define SDIO_STA_DTIMEOUT ((uint32_t)0x00000008) /*!< Data timeout */ +#define SDIO_STA_TXUNDERR ((uint32_t)0x00000010) /*!< Transmit FIFO underrun error */ +#define SDIO_STA_RXOVERR ((uint32_t)0x00000020) /*!< Received FIFO overrun error */ +#define SDIO_STA_CMDREND ((uint32_t)0x00000040) /*!< Command response received (CRC check passed) */ +#define SDIO_STA_CMDSENT ((uint32_t)0x00000080) /*!< Command sent (no response required) */ +#define SDIO_STA_DATAEND ((uint32_t)0x00000100) /*!< Data end (data counter, SDIDCOUNT, is zero) */ +#define SDIO_STA_STBITERR ((uint32_t)0x00000200) /*!< Start bit not detected on all data signals in wide bus mode */ +#define SDIO_STA_DBCKEND ((uint32_t)0x00000400) /*!< Data block sent/received (CRC check passed) */ +#define SDIO_STA_CMDACT ((uint32_t)0x00000800) /*!< Command transfer in progress */ +#define SDIO_STA_TXACT ((uint32_t)0x00001000) /*!< Data transmit in progress */ +#define SDIO_STA_RXACT ((uint32_t)0x00002000) /*!< Data receive in progress */ +#define SDIO_STA_TXFIFOHE ((uint32_t)0x00004000) /*!< Transmit FIFO Half Empty: at least 8 words can be written into the FIFO */ +#define SDIO_STA_RXFIFOHF ((uint32_t)0x00008000) /*!< Receive FIFO Half Full: there are at least 8 words in the FIFO */ +#define SDIO_STA_TXFIFOF ((uint32_t)0x00010000) /*!< Transmit FIFO full */ +#define SDIO_STA_RXFIFOF ((uint32_t)0x00020000) /*!< Receive FIFO full */ +#define SDIO_STA_TXFIFOE ((uint32_t)0x00040000) /*!< Transmit FIFO empty */ +#define SDIO_STA_RXFIFOE ((uint32_t)0x00080000) /*!< Receive FIFO empty */ +#define SDIO_STA_TXDAVL ((uint32_t)0x00100000) /*!< Data available in transmit FIFO */ +#define SDIO_STA_RXDAVL ((uint32_t)0x00200000) /*!< Data available in receive FIFO */ +#define SDIO_STA_SDIOIT ((uint32_t)0x00400000) /*!< SDIO interrupt received */ +#define SDIO_STA_CEATAEND ((uint32_t)0x00800000) /*!< CE-ATA command completion signal received for CMD61 */ + +/******************* Bit definition for SDIO_ICR register *******************/ +#define SDIO_ICR_CCRCFAILC ((uint32_t)0x00000001) /*!< CCRCFAIL flag clear bit */ +#define SDIO_ICR_DCRCFAILC ((uint32_t)0x00000002) /*!< DCRCFAIL flag clear bit */ +#define SDIO_ICR_CTIMEOUTC ((uint32_t)0x00000004) /*!< CTIMEOUT flag clear bit */ +#define SDIO_ICR_DTIMEOUTC ((uint32_t)0x00000008) /*!< DTIMEOUT flag clear bit */ +#define SDIO_ICR_TXUNDERRC ((uint32_t)0x00000010) /*!< TXUNDERR flag clear bit */ +#define SDIO_ICR_RXOVERRC ((uint32_t)0x00000020) /*!< RXOVERR flag clear bit */ +#define SDIO_ICR_CMDRENDC ((uint32_t)0x00000040) /*!< CMDREND flag clear bit */ +#define SDIO_ICR_CMDSENTC ((uint32_t)0x00000080) /*!< CMDSENT flag clear bit */ +#define SDIO_ICR_DATAENDC ((uint32_t)0x00000100) /*!< DATAEND flag clear bit */ +#define SDIO_ICR_STBITERRC ((uint32_t)0x00000200) /*!< STBITERR flag clear bit */ +#define SDIO_ICR_DBCKENDC ((uint32_t)0x00000400) /*!< DBCKEND flag clear bit */ +#define SDIO_ICR_SDIOITC ((uint32_t)0x00400000) /*!< SDIOIT flag clear bit */ +#define SDIO_ICR_CEATAENDC ((uint32_t)0x00800000) /*!< CEATAEND flag clear bit */ + +/****************** Bit definition for SDIO_MASK register *******************/ +#define SDIO_MASK_CCRCFAILIE ((uint32_t)0x00000001) /*!< Command CRC Fail Interrupt Enable */ +#define SDIO_MASK_DCRCFAILIE ((uint32_t)0x00000002) /*!< Data CRC Fail Interrupt Enable */ +#define SDIO_MASK_CTIMEOUTIE ((uint32_t)0x00000004) /*!< Command TimeOut Interrupt Enable */ +#define SDIO_MASK_DTIMEOUTIE ((uint32_t)0x00000008) /*!< Data TimeOut Interrupt Enable */ +#define SDIO_MASK_TXUNDERRIE ((uint32_t)0x00000010) /*!< Tx FIFO UnderRun Error Interrupt Enable */ +#define SDIO_MASK_RXOVERRIE ((uint32_t)0x00000020) /*!< Rx FIFO OverRun Error Interrupt Enable */ +#define SDIO_MASK_CMDRENDIE ((uint32_t)0x00000040) /*!< Command Response Received Interrupt Enable */ +#define SDIO_MASK_CMDSENTIE ((uint32_t)0x00000080) /*!< Command Sent Interrupt Enable */ +#define SDIO_MASK_DATAENDIE ((uint32_t)0x00000100) /*!< Data End Interrupt Enable */ +#define SDIO_MASK_STBITERRIE ((uint32_t)0x00000200) /*!< Start Bit Error Interrupt Enable */ +#define SDIO_MASK_DBCKENDIE ((uint32_t)0x00000400) /*!< Data Block End Interrupt Enable */ +#define SDIO_MASK_CMDACTIE ((uint32_t)0x00000800) /*!< Command Acting Interrupt Enable */ +#define SDIO_MASK_TXACTIE ((uint32_t)0x00001000) /*!< Data Transmit Acting Interrupt Enable */ +#define SDIO_MASK_RXACTIE ((uint32_t)0x00002000) /*!< Data receive acting interrupt enabled */ +#define SDIO_MASK_TXFIFOHEIE ((uint32_t)0x00004000) /*!< Tx FIFO Half Empty interrupt Enable */ +#define SDIO_MASK_RXFIFOHFIE ((uint32_t)0x00008000) /*!< Rx FIFO Half Full interrupt Enable */ +#define SDIO_MASK_TXFIFOFIE ((uint32_t)0x00010000) /*!< Tx FIFO Full interrupt Enable */ +#define SDIO_MASK_RXFIFOFIE ((uint32_t)0x00020000) /*!< Rx FIFO Full interrupt Enable */ +#define SDIO_MASK_TXFIFOEIE ((uint32_t)0x00040000) /*!< Tx FIFO Empty interrupt Enable */ +#define SDIO_MASK_RXFIFOEIE ((uint32_t)0x00080000) /*!< Rx FIFO Empty interrupt Enable */ +#define SDIO_MASK_TXDAVLIE ((uint32_t)0x00100000) /*!< Data available in Tx FIFO interrupt Enable */ +#define SDIO_MASK_RXDAVLIE ((uint32_t)0x00200000) /*!< Data available in Rx FIFO interrupt Enable */ +#define SDIO_MASK_SDIOITIE ((uint32_t)0x00400000) /*!< SDIO Mode Interrupt Received interrupt Enable */ +#define SDIO_MASK_CEATAENDIE ((uint32_t)0x00800000) /*!< CE-ATA command completion signal received Interrupt Enable */ + +/***************** Bit definition for SDIO_FIFOCNT register *****************/ +#define SDIO_FIFOCNT_FIFOCOUNT ((uint32_t)0x00FFFFFF) /*!< Remaining number of words to be written to or read from the FIFO */ + +/****************** Bit definition for SDIO_FIFO register *******************/ +#define SDIO_FIFO_FIFODATA ((uint32_t)0xFFFFFFFF) /*!< Receive and transmit FIFO data */ + +/******************************************************************************/ +/* */ +/* USB Device FS */ +/* */ +/******************************************************************************/ + +/*!< Endpoint-specific registers */ +/******************* Bit definition for USB_EP0R register *******************/ +#define USB_EP0R_EA ((uint16_t)0x000F) /*!< Endpoint Address */ + +#define USB_EP0R_STAT_TX ((uint16_t)0x0030) /*!< STAT_TX[1:0] bits (Status bits, for transmission transfers) */ +#define USB_EP0R_STAT_TX_0 ((uint16_t)0x0010) /*!< Bit 0 */ +#define USB_EP0R_STAT_TX_1 ((uint16_t)0x0020) /*!< Bit 1 */ + +#define USB_EP0R_DTOG_TX ((uint16_t)0x0040) /*!< Data Toggle, for transmission transfers */ +#define USB_EP0R_CTR_TX ((uint16_t)0x0080) /*!< Correct Transfer for transmission */ +#define USB_EP0R_EP_KIND ((uint16_t)0x0100) /*!< Endpoint Kind */ + +#define USB_EP0R_EP_TYPE ((uint16_t)0x0600) /*!< EP_TYPE[1:0] bits (Endpoint type) */ +#define USB_EP0R_EP_TYPE_0 ((uint16_t)0x0200) /*!< Bit 0 */ +#define USB_EP0R_EP_TYPE_1 ((uint16_t)0x0400) /*!< Bit 1 */ + +#define USB_EP0R_SETUP ((uint16_t)0x0800) /*!< Setup transaction completed */ + +#define USB_EP0R_STAT_RX ((uint16_t)0x3000) /*!< STAT_RX[1:0] bits (Status bits, for reception transfers) */ +#define USB_EP0R_STAT_RX_0 ((uint16_t)0x1000) /*!< Bit 0 */ +#define USB_EP0R_STAT_RX_1 ((uint16_t)0x2000) /*!< Bit 1 */ + +#define USB_EP0R_DTOG_RX ((uint16_t)0x4000) /*!< Data Toggle, for reception transfers */ +#define USB_EP0R_CTR_RX ((uint16_t)0x8000) /*!< Correct Transfer for reception */ + +/******************* Bit definition for USB_EP1R register *******************/ +#define USB_EP1R_EA ((uint16_t)0x000F) /*!< Endpoint Address */ + +#define USB_EP1R_STAT_TX ((uint16_t)0x0030) /*!< STAT_TX[1:0] bits (Status bits, for transmission transfers) */ +#define USB_EP1R_STAT_TX_0 ((uint16_t)0x0010) /*!< Bit 0 */ +#define USB_EP1R_STAT_TX_1 ((uint16_t)0x0020) /*!< Bit 1 */ + +#define USB_EP1R_DTOG_TX ((uint16_t)0x0040) /*!< Data Toggle, for transmission transfers */ +#define USB_EP1R_CTR_TX ((uint16_t)0x0080) /*!< Correct Transfer for transmission */ +#define USB_EP1R_EP_KIND ((uint16_t)0x0100) /*!< Endpoint Kind */ + +#define USB_EP1R_EP_TYPE ((uint16_t)0x0600) /*!< EP_TYPE[1:0] bits (Endpoint type) */ +#define USB_EP1R_EP_TYPE_0 ((uint16_t)0x0200) /*!< Bit 0 */ +#define USB_EP1R_EP_TYPE_1 ((uint16_t)0x0400) /*!< Bit 1 */ + +#define USB_EP1R_SETUP ((uint16_t)0x0800) /*!< Setup transaction completed */ + +#define USB_EP1R_STAT_RX ((uint16_t)0x3000) /*!< STAT_RX[1:0] bits (Status bits, for reception transfers) */ +#define USB_EP1R_STAT_RX_0 ((uint16_t)0x1000) /*!< Bit 0 */ +#define USB_EP1R_STAT_RX_1 ((uint16_t)0x2000) /*!< Bit 1 */ + +#define USB_EP1R_DTOG_RX ((uint16_t)0x4000) /*!< Data Toggle, for reception transfers */ +#define USB_EP1R_CTR_RX ((uint16_t)0x8000) /*!< Correct Transfer for reception */ + +/******************* Bit definition for USB_EP2R register *******************/ +#define USB_EP2R_EA ((uint16_t)0x000F) /*!< Endpoint Address */ + +#define USB_EP2R_STAT_TX ((uint16_t)0x0030) /*!< STAT_TX[1:0] bits (Status bits, for transmission transfers) */ +#define USB_EP2R_STAT_TX_0 ((uint16_t)0x0010) /*!< Bit 0 */ +#define USB_EP2R_STAT_TX_1 ((uint16_t)0x0020) /*!< Bit 1 */ + +#define USB_EP2R_DTOG_TX ((uint16_t)0x0040) /*!< Data Toggle, for transmission transfers */ +#define USB_EP2R_CTR_TX ((uint16_t)0x0080) /*!< Correct Transfer for transmission */ +#define USB_EP2R_EP_KIND ((uint16_t)0x0100) /*!< Endpoint Kind */ + +#define USB_EP2R_EP_TYPE ((uint16_t)0x0600) /*!< EP_TYPE[1:0] bits (Endpoint type) */ +#define USB_EP2R_EP_TYPE_0 ((uint16_t)0x0200) /*!< Bit 0 */ +#define USB_EP2R_EP_TYPE_1 ((uint16_t)0x0400) /*!< Bit 1 */ + +#define USB_EP2R_SETUP ((uint16_t)0x0800) /*!< Setup transaction completed */ + +#define USB_EP2R_STAT_RX ((uint16_t)0x3000) /*!< STAT_RX[1:0] bits (Status bits, for reception transfers) */ +#define USB_EP2R_STAT_RX_0 ((uint16_t)0x1000) /*!< Bit 0 */ +#define USB_EP2R_STAT_RX_1 ((uint16_t)0x2000) /*!< Bit 1 */ + +#define USB_EP2R_DTOG_RX ((uint16_t)0x4000) /*!< Data Toggle, for reception transfers */ +#define USB_EP2R_CTR_RX ((uint16_t)0x8000) /*!< Correct Transfer for reception */ + +/******************* Bit definition for USB_EP3R register *******************/ +#define USB_EP3R_EA ((uint16_t)0x000F) /*!< Endpoint Address */ + +#define USB_EP3R_STAT_TX ((uint16_t)0x0030) /*!< STAT_TX[1:0] bits (Status bits, for transmission transfers) */ +#define USB_EP3R_STAT_TX_0 ((uint16_t)0x0010) /*!< Bit 0 */ +#define USB_EP3R_STAT_TX_1 ((uint16_t)0x0020) /*!< Bit 1 */ + +#define USB_EP3R_DTOG_TX ((uint16_t)0x0040) /*!< Data Toggle, for transmission transfers */ +#define USB_EP3R_CTR_TX ((uint16_t)0x0080) /*!< Correct Transfer for transmission */ +#define USB_EP3R_EP_KIND ((uint16_t)0x0100) /*!< Endpoint Kind */ + +#define USB_EP3R_EP_TYPE ((uint16_t)0x0600) /*!< EP_TYPE[1:0] bits (Endpoint type) */ +#define USB_EP3R_EP_TYPE_0 ((uint16_t)0x0200) /*!< Bit 0 */ +#define USB_EP3R_EP_TYPE_1 ((uint16_t)0x0400) /*!< Bit 1 */ + +#define USB_EP3R_SETUP ((uint16_t)0x0800) /*!< Setup transaction completed */ + +#define USB_EP3R_STAT_RX ((uint16_t)0x3000) /*!< STAT_RX[1:0] bits (Status bits, for reception transfers) */ +#define USB_EP3R_STAT_RX_0 ((uint16_t)0x1000) /*!< Bit 0 */ +#define USB_EP3R_STAT_RX_1 ((uint16_t)0x2000) /*!< Bit 1 */ + +#define USB_EP3R_DTOG_RX ((uint16_t)0x4000) /*!< Data Toggle, for reception transfers */ +#define USB_EP3R_CTR_RX ((uint16_t)0x8000) /*!< Correct Transfer for reception */ + +/******************* Bit definition for USB_EP4R register *******************/ +#define USB_EP4R_EA ((uint16_t)0x000F) /*!< Endpoint Address */ + +#define USB_EP4R_STAT_TX ((uint16_t)0x0030) /*!< STAT_TX[1:0] bits (Status bits, for transmission transfers) */ +#define USB_EP4R_STAT_TX_0 ((uint16_t)0x0010) /*!< Bit 0 */ +#define USB_EP4R_STAT_TX_1 ((uint16_t)0x0020) /*!< Bit 1 */ + +#define USB_EP4R_DTOG_TX ((uint16_t)0x0040) /*!< Data Toggle, for transmission transfers */ +#define USB_EP4R_CTR_TX ((uint16_t)0x0080) /*!< Correct Transfer for transmission */ +#define USB_EP4R_EP_KIND ((uint16_t)0x0100) /*!< Endpoint Kind */ + +#define USB_EP4R_EP_TYPE ((uint16_t)0x0600) /*!< EP_TYPE[1:0] bits (Endpoint type) */ +#define USB_EP4R_EP_TYPE_0 ((uint16_t)0x0200) /*!< Bit 0 */ +#define USB_EP4R_EP_TYPE_1 ((uint16_t)0x0400) /*!< Bit 1 */ + +#define USB_EP4R_SETUP ((uint16_t)0x0800) /*!< Setup transaction completed */ + +#define USB_EP4R_STAT_RX ((uint16_t)0x3000) /*!< STAT_RX[1:0] bits (Status bits, for reception transfers) */ +#define USB_EP4R_STAT_RX_0 ((uint16_t)0x1000) /*!< Bit 0 */ +#define USB_EP4R_STAT_RX_1 ((uint16_t)0x2000) /*!< Bit 1 */ + +#define USB_EP4R_DTOG_RX ((uint16_t)0x4000) /*!< Data Toggle, for reception transfers */ +#define USB_EP4R_CTR_RX ((uint16_t)0x8000) /*!< Correct Transfer for reception */ + +/******************* Bit definition for USB_EP5R register *******************/ +#define USB_EP5R_EA ((uint16_t)0x000F) /*!< Endpoint Address */ + +#define USB_EP5R_STAT_TX ((uint16_t)0x0030) /*!< STAT_TX[1:0] bits (Status bits, for transmission transfers) */ +#define USB_EP5R_STAT_TX_0 ((uint16_t)0x0010) /*!< Bit 0 */ +#define USB_EP5R_STAT_TX_1 ((uint16_t)0x0020) /*!< Bit 1 */ + +#define USB_EP5R_DTOG_TX ((uint16_t)0x0040) /*!< Data Toggle, for transmission transfers */ +#define USB_EP5R_CTR_TX ((uint16_t)0x0080) /*!< Correct Transfer for transmission */ +#define USB_EP5R_EP_KIND ((uint16_t)0x0100) /*!< Endpoint Kind */ + +#define USB_EP5R_EP_TYPE ((uint16_t)0x0600) /*!< EP_TYPE[1:0] bits (Endpoint type) */ +#define USB_EP5R_EP_TYPE_0 ((uint16_t)0x0200) /*!< Bit 0 */ +#define USB_EP5R_EP_TYPE_1 ((uint16_t)0x0400) /*!< Bit 1 */ + +#define USB_EP5R_SETUP ((uint16_t)0x0800) /*!< Setup transaction completed */ + +#define USB_EP5R_STAT_RX ((uint16_t)0x3000) /*!< STAT_RX[1:0] bits (Status bits, for reception transfers) */ +#define USB_EP5R_STAT_RX_0 ((uint16_t)0x1000) /*!< Bit 0 */ +#define USB_EP5R_STAT_RX_1 ((uint16_t)0x2000) /*!< Bit 1 */ + +#define USB_EP5R_DTOG_RX ((uint16_t)0x4000) /*!< Data Toggle, for reception transfers */ +#define USB_EP5R_CTR_RX ((uint16_t)0x8000) /*!< Correct Transfer for reception */ + +/******************* Bit definition for USB_EP6R register *******************/ +#define USB_EP6R_EA ((uint16_t)0x000F) /*!< Endpoint Address */ + +#define USB_EP6R_STAT_TX ((uint16_t)0x0030) /*!< STAT_TX[1:0] bits (Status bits, for transmission transfers) */ +#define USB_EP6R_STAT_TX_0 ((uint16_t)0x0010) /*!< Bit 0 */ +#define USB_EP6R_STAT_TX_1 ((uint16_t)0x0020) /*!< Bit 1 */ + +#define USB_EP6R_DTOG_TX ((uint16_t)0x0040) /*!< Data Toggle, for transmission transfers */ +#define USB_EP6R_CTR_TX ((uint16_t)0x0080) /*!< Correct Transfer for transmission */ +#define USB_EP6R_EP_KIND ((uint16_t)0x0100) /*!< Endpoint Kind */ + +#define USB_EP6R_EP_TYPE ((uint16_t)0x0600) /*!< EP_TYPE[1:0] bits (Endpoint type) */ +#define USB_EP6R_EP_TYPE_0 ((uint16_t)0x0200) /*!< Bit 0 */ +#define USB_EP6R_EP_TYPE_1 ((uint16_t)0x0400) /*!< Bit 1 */ + +#define USB_EP6R_SETUP ((uint16_t)0x0800) /*!< Setup transaction completed */ + +#define USB_EP6R_STAT_RX ((uint16_t)0x3000) /*!< STAT_RX[1:0] bits (Status bits, for reception transfers) */ +#define USB_EP6R_STAT_RX_0 ((uint16_t)0x1000) /*!< Bit 0 */ +#define USB_EP6R_STAT_RX_1 ((uint16_t)0x2000) /*!< Bit 1 */ + +#define USB_EP6R_DTOG_RX ((uint16_t)0x4000) /*!< Data Toggle, for reception transfers */ +#define USB_EP6R_CTR_RX ((uint16_t)0x8000) /*!< Correct Transfer for reception */ + +/******************* Bit definition for USB_EP7R register *******************/ +#define USB_EP7R_EA ((uint16_t)0x000F) /*!< Endpoint Address */ + +#define USB_EP7R_STAT_TX ((uint16_t)0x0030) /*!< STAT_TX[1:0] bits (Status bits, for transmission transfers) */ +#define USB_EP7R_STAT_TX_0 ((uint16_t)0x0010) /*!< Bit 0 */ +#define USB_EP7R_STAT_TX_1 ((uint16_t)0x0020) /*!< Bit 1 */ + +#define USB_EP7R_DTOG_TX ((uint16_t)0x0040) /*!< Data Toggle, for transmission transfers */ +#define USB_EP7R_CTR_TX ((uint16_t)0x0080) /*!< Correct Transfer for transmission */ +#define USB_EP7R_EP_KIND ((uint16_t)0x0100) /*!< Endpoint Kind */ + +#define USB_EP7R_EP_TYPE ((uint16_t)0x0600) /*!< EP_TYPE[1:0] bits (Endpoint type) */ +#define USB_EP7R_EP_TYPE_0 ((uint16_t)0x0200) /*!< Bit 0 */ +#define USB_EP7R_EP_TYPE_1 ((uint16_t)0x0400) /*!< Bit 1 */ + +#define USB_EP7R_SETUP ((uint16_t)0x0800) /*!< Setup transaction completed */ + +#define USB_EP7R_STAT_RX ((uint16_t)0x3000) /*!< STAT_RX[1:0] bits (Status bits, for reception transfers) */ +#define USB_EP7R_STAT_RX_0 ((uint16_t)0x1000) /*!< Bit 0 */ +#define USB_EP7R_STAT_RX_1 ((uint16_t)0x2000) /*!< Bit 1 */ + +#define USB_EP7R_DTOG_RX ((uint16_t)0x4000) /*!< Data Toggle, for reception transfers */ +#define USB_EP7R_CTR_RX ((uint16_t)0x8000) /*!< Correct Transfer for reception */ + +/*!< Common registers */ +/******************* Bit definition for USB_CNTR register *******************/ +#define USB_CNTR_FRES ((uint16_t)0x0001) /*!< Force USB Reset */ +#define USB_CNTR_PDWN ((uint16_t)0x0002) /*!< Power down */ +#define USB_CNTR_LP_MODE ((uint16_t)0x0004) /*!< Low-power mode */ +#define USB_CNTR_FSUSP ((uint16_t)0x0008) /*!< Force suspend */ +#define USB_CNTR_RESUME ((uint16_t)0x0010) /*!< Resume request */ +#define USB_CNTR_ESOFM ((uint16_t)0x0100) /*!< Expected Start Of Frame Interrupt Mask */ +#define USB_CNTR_SOFM ((uint16_t)0x0200) /*!< Start Of Frame Interrupt Mask */ +#define USB_CNTR_RESETM ((uint16_t)0x0400) /*!< RESET Interrupt Mask */ +#define USB_CNTR_SUSPM ((uint16_t)0x0800) /*!< Suspend mode Interrupt Mask */ +#define USB_CNTR_WKUPM ((uint16_t)0x1000) /*!< Wakeup Interrupt Mask */ +#define USB_CNTR_ERRM ((uint16_t)0x2000) /*!< Error Interrupt Mask */ +#define USB_CNTR_PMAOVRM ((uint16_t)0x4000) /*!< Packet Memory Area Over / Underrun Interrupt Mask */ +#define USB_CNTR_CTRM ((uint16_t)0x8000) /*!< Correct Transfer Interrupt Mask */ + +/******************* Bit definition for USB_ISTR register *******************/ +#define USB_ISTR_EP_ID ((uint16_t)0x000F) /*!< Endpoint Identifier */ +#define USB_ISTR_DIR ((uint16_t)0x0010) /*!< Direction of transaction */ +#define USB_ISTR_ESOF ((uint16_t)0x0100) /*!< Expected Start Of Frame */ +#define USB_ISTR_SOF ((uint16_t)0x0200) /*!< Start Of Frame */ +#define USB_ISTR_RESET ((uint16_t)0x0400) /*!< USB RESET request */ +#define USB_ISTR_SUSP ((uint16_t)0x0800) /*!< Suspend mode request */ +#define USB_ISTR_WKUP ((uint16_t)0x1000) /*!< Wake up */ +#define USB_ISTR_ERR ((uint16_t)0x2000) /*!< Error */ +#define USB_ISTR_PMAOVR ((uint16_t)0x4000) /*!< Packet Memory Area Over / Underrun */ +#define USB_ISTR_CTR ((uint16_t)0x8000) /*!< Correct Transfer */ + +/******************* Bit definition for USB_FNR register ********************/ +#define USB_FNR_FN ((uint16_t)0x07FF) /*!< Frame Number */ +#define USB_FNR_LSOF ((uint16_t)0x1800) /*!< Lost SOF */ +#define USB_FNR_LCK ((uint16_t)0x2000) /*!< Locked */ +#define USB_FNR_RXDM ((uint16_t)0x4000) /*!< Receive Data - Line Status */ +#define USB_FNR_RXDP ((uint16_t)0x8000) /*!< Receive Data + Line Status */ + +/****************** Bit definition for USB_DADDR register *******************/ +#define USB_DADDR_ADD ((uint8_t)0x7F) /*!< ADD[6:0] bits (Device Address) */ +#define USB_DADDR_ADD0 ((uint8_t)0x01) /*!< Bit 0 */ +#define USB_DADDR_ADD1 ((uint8_t)0x02) /*!< Bit 1 */ +#define USB_DADDR_ADD2 ((uint8_t)0x04) /*!< Bit 2 */ +#define USB_DADDR_ADD3 ((uint8_t)0x08) /*!< Bit 3 */ +#define USB_DADDR_ADD4 ((uint8_t)0x10) /*!< Bit 4 */ +#define USB_DADDR_ADD5 ((uint8_t)0x20) /*!< Bit 5 */ +#define USB_DADDR_ADD6 ((uint8_t)0x40) /*!< Bit 6 */ + +#define USB_DADDR_EF ((uint8_t)0x80) /*!< Enable Function */ + +/****************** Bit definition for USB_BTABLE register ******************/ +#define USB_BTABLE_BTABLE ((uint16_t)0xFFF8) /*!< Buffer Table */ + +/*!< Buffer descriptor table */ +/***************** Bit definition for USB_ADDR0_TX register *****************/ +#define USB_ADDR0_TX_ADDR0_TX ((uint16_t)0xFFFE) /*!< Transmission Buffer Address 0 */ + +/***************** Bit definition for USB_ADDR1_TX register *****************/ +#define USB_ADDR1_TX_ADDR1_TX ((uint16_t)0xFFFE) /*!< Transmission Buffer Address 1 */ + +/***************** Bit definition for USB_ADDR2_TX register *****************/ +#define USB_ADDR2_TX_ADDR2_TX ((uint16_t)0xFFFE) /*!< Transmission Buffer Address 2 */ + +/***************** Bit definition for USB_ADDR3_TX register *****************/ +#define USB_ADDR3_TX_ADDR3_TX ((uint16_t)0xFFFE) /*!< Transmission Buffer Address 3 */ + +/***************** Bit definition for USB_ADDR4_TX register *****************/ +#define USB_ADDR4_TX_ADDR4_TX ((uint16_t)0xFFFE) /*!< Transmission Buffer Address 4 */ + +/***************** Bit definition for USB_ADDR5_TX register *****************/ +#define USB_ADDR5_TX_ADDR5_TX ((uint16_t)0xFFFE) /*!< Transmission Buffer Address 5 */ + +/***************** Bit definition for USB_ADDR6_TX register *****************/ +#define USB_ADDR6_TX_ADDR6_TX ((uint16_t)0xFFFE) /*!< Transmission Buffer Address 6 */ + +/***************** Bit definition for USB_ADDR7_TX register *****************/ +#define USB_ADDR7_TX_ADDR7_TX ((uint16_t)0xFFFE) /*!< Transmission Buffer Address 7 */ + +/*----------------------------------------------------------------------------*/ + +/***************** Bit definition for USB_COUNT0_TX register ****************/ +#define USB_COUNT0_TX_COUNT0_TX ((uint16_t)0x03FF) /*!< Transmission Byte Count 0 */ + +/***************** Bit definition for USB_COUNT1_TX register ****************/ +#define USB_COUNT1_TX_COUNT1_TX ((uint16_t)0x03FF) /*!< Transmission Byte Count 1 */ + +/***************** Bit definition for USB_COUNT2_TX register ****************/ +#define USB_COUNT2_TX_COUNT2_TX ((uint16_t)0x03FF) /*!< Transmission Byte Count 2 */ + +/***************** Bit definition for USB_COUNT3_TX register ****************/ +#define USB_COUNT3_TX_COUNT3_TX ((uint16_t)0x03FF) /*!< Transmission Byte Count 3 */ + +/***************** Bit definition for USB_COUNT4_TX register ****************/ +#define USB_COUNT4_TX_COUNT4_TX ((uint16_t)0x03FF) /*!< Transmission Byte Count 4 */ + +/***************** Bit definition for USB_COUNT5_TX register ****************/ +#define USB_COUNT5_TX_COUNT5_TX ((uint16_t)0x03FF) /*!< Transmission Byte Count 5 */ + +/***************** Bit definition for USB_COUNT6_TX register ****************/ +#define USB_COUNT6_TX_COUNT6_TX ((uint16_t)0x03FF) /*!< Transmission Byte Count 6 */ + +/***************** Bit definition for USB_COUNT7_TX register ****************/ +#define USB_COUNT7_TX_COUNT7_TX ((uint16_t)0x03FF) /*!< Transmission Byte Count 7 */ + +/*----------------------------------------------------------------------------*/ + +/**************** Bit definition for USB_COUNT0_TX_0 register ***************/ +#define USB_COUNT0_TX_0_COUNT0_TX_0 ((uint32_t)0x000003FF) /*!< Transmission Byte Count 0 (low) */ + +/**************** Bit definition for USB_COUNT0_TX_1 register ***************/ +#define USB_COUNT0_TX_1_COUNT0_TX_1 ((uint32_t)0x03FF0000) /*!< Transmission Byte Count 0 (high) */ + +/**************** Bit definition for USB_COUNT1_TX_0 register ***************/ +#define USB_COUNT1_TX_0_COUNT1_TX_0 ((uint32_t)0x000003FF) /*!< Transmission Byte Count 1 (low) */ + +/**************** Bit definition for USB_COUNT1_TX_1 register ***************/ +#define USB_COUNT1_TX_1_COUNT1_TX_1 ((uint32_t)0x03FF0000) /*!< Transmission Byte Count 1 (high) */ + +/**************** Bit definition for USB_COUNT2_TX_0 register ***************/ +#define USB_COUNT2_TX_0_COUNT2_TX_0 ((uint32_t)0x000003FF) /*!< Transmission Byte Count 2 (low) */ + +/**************** Bit definition for USB_COUNT2_TX_1 register ***************/ +#define USB_COUNT2_TX_1_COUNT2_TX_1 ((uint32_t)0x03FF0000) /*!< Transmission Byte Count 2 (high) */ + +/**************** Bit definition for USB_COUNT3_TX_0 register ***************/ +#define USB_COUNT3_TX_0_COUNT3_TX_0 ((uint16_t)0x000003FF) /*!< Transmission Byte Count 3 (low) */ + +/**************** Bit definition for USB_COUNT3_TX_1 register ***************/ +#define USB_COUNT3_TX_1_COUNT3_TX_1 ((uint16_t)0x03FF0000) /*!< Transmission Byte Count 3 (high) */ + +/**************** Bit definition for USB_COUNT4_TX_0 register ***************/ +#define USB_COUNT4_TX_0_COUNT4_TX_0 ((uint32_t)0x000003FF) /*!< Transmission Byte Count 4 (low) */ + +/**************** Bit definition for USB_COUNT4_TX_1 register ***************/ +#define USB_COUNT4_TX_1_COUNT4_TX_1 ((uint32_t)0x03FF0000) /*!< Transmission Byte Count 4 (high) */ + +/**************** Bit definition for USB_COUNT5_TX_0 register ***************/ +#define USB_COUNT5_TX_0_COUNT5_TX_0 ((uint32_t)0x000003FF) /*!< Transmission Byte Count 5 (low) */ + +/**************** Bit definition for USB_COUNT5_TX_1 register ***************/ +#define USB_COUNT5_TX_1_COUNT5_TX_1 ((uint32_t)0x03FF0000) /*!< Transmission Byte Count 5 (high) */ + +/**************** Bit definition for USB_COUNT6_TX_0 register ***************/ +#define USB_COUNT6_TX_0_COUNT6_TX_0 ((uint32_t)0x000003FF) /*!< Transmission Byte Count 6 (low) */ + +/**************** Bit definition for USB_COUNT6_TX_1 register ***************/ +#define USB_COUNT6_TX_1_COUNT6_TX_1 ((uint32_t)0x03FF0000) /*!< Transmission Byte Count 6 (high) */ + +/**************** Bit definition for USB_COUNT7_TX_0 register ***************/ +#define USB_COUNT7_TX_0_COUNT7_TX_0 ((uint32_t)0x000003FF) /*!< Transmission Byte Count 7 (low) */ + +/**************** Bit definition for USB_COUNT7_TX_1 register ***************/ +#define USB_COUNT7_TX_1_COUNT7_TX_1 ((uint32_t)0x03FF0000) /*!< Transmission Byte Count 7 (high) */ + +/*----------------------------------------------------------------------------*/ + +/***************** Bit definition for USB_ADDR0_RX register *****************/ +#define USB_ADDR0_RX_ADDR0_RX ((uint16_t)0xFFFE) /*!< Reception Buffer Address 0 */ + +/***************** Bit definition for USB_ADDR1_RX register *****************/ +#define USB_ADDR1_RX_ADDR1_RX ((uint16_t)0xFFFE) /*!< Reception Buffer Address 1 */ + +/***************** Bit definition for USB_ADDR2_RX register *****************/ +#define USB_ADDR2_RX_ADDR2_RX ((uint16_t)0xFFFE) /*!< Reception Buffer Address 2 */ + +/***************** Bit definition for USB_ADDR3_RX register *****************/ +#define USB_ADDR3_RX_ADDR3_RX ((uint16_t)0xFFFE) /*!< Reception Buffer Address 3 */ + +/***************** Bit definition for USB_ADDR4_RX register *****************/ +#define USB_ADDR4_RX_ADDR4_RX ((uint16_t)0xFFFE) /*!< Reception Buffer Address 4 */ + +/***************** Bit definition for USB_ADDR5_RX register *****************/ +#define USB_ADDR5_RX_ADDR5_RX ((uint16_t)0xFFFE) /*!< Reception Buffer Address 5 */ + +/***************** Bit definition for USB_ADDR6_RX register *****************/ +#define USB_ADDR6_RX_ADDR6_RX ((uint16_t)0xFFFE) /*!< Reception Buffer Address 6 */ + +/***************** Bit definition for USB_ADDR7_RX register *****************/ +#define USB_ADDR7_RX_ADDR7_RX ((uint16_t)0xFFFE) /*!< Reception Buffer Address 7 */ + +/*----------------------------------------------------------------------------*/ + +/***************** Bit definition for USB_COUNT0_RX register ****************/ +#define USB_COUNT0_RX_COUNT0_RX ((uint16_t)0x03FF) /*!< Reception Byte Count */ + +#define USB_COUNT0_RX_NUM_BLOCK ((uint16_t)0x7C00) /*!< NUM_BLOCK[4:0] bits (Number of blocks) */ +#define USB_COUNT0_RX_NUM_BLOCK_0 ((uint16_t)0x0400) /*!< Bit 0 */ +#define USB_COUNT0_RX_NUM_BLOCK_1 ((uint16_t)0x0800) /*!< Bit 1 */ +#define USB_COUNT0_RX_NUM_BLOCK_2 ((uint16_t)0x1000) /*!< Bit 2 */ +#define USB_COUNT0_RX_NUM_BLOCK_3 ((uint16_t)0x2000) /*!< Bit 3 */ +#define USB_COUNT0_RX_NUM_BLOCK_4 ((uint16_t)0x4000) /*!< Bit 4 */ + +#define USB_COUNT0_RX_BLSIZE ((uint16_t)0x8000) /*!< BLock SIZE */ + +/***************** Bit definition for USB_COUNT1_RX register ****************/ +#define USB_COUNT1_RX_COUNT1_RX ((uint16_t)0x03FF) /*!< Reception Byte Count */ + +#define USB_COUNT1_RX_NUM_BLOCK ((uint16_t)0x7C00) /*!< NUM_BLOCK[4:0] bits (Number of blocks) */ +#define USB_COUNT1_RX_NUM_BLOCK_0 ((uint16_t)0x0400) /*!< Bit 0 */ +#define USB_COUNT1_RX_NUM_BLOCK_1 ((uint16_t)0x0800) /*!< Bit 1 */ +#define USB_COUNT1_RX_NUM_BLOCK_2 ((uint16_t)0x1000) /*!< Bit 2 */ +#define USB_COUNT1_RX_NUM_BLOCK_3 ((uint16_t)0x2000) /*!< Bit 3 */ +#define USB_COUNT1_RX_NUM_BLOCK_4 ((uint16_t)0x4000) /*!< Bit 4 */ + +#define USB_COUNT1_RX_BLSIZE ((uint16_t)0x8000) /*!< BLock SIZE */ + +/***************** Bit definition for USB_COUNT2_RX register ****************/ +#define USB_COUNT2_RX_COUNT2_RX ((uint16_t)0x03FF) /*!< Reception Byte Count */ + +#define USB_COUNT2_RX_NUM_BLOCK ((uint16_t)0x7C00) /*!< NUM_BLOCK[4:0] bits (Number of blocks) */ +#define USB_COUNT2_RX_NUM_BLOCK_0 ((uint16_t)0x0400) /*!< Bit 0 */ +#define USB_COUNT2_RX_NUM_BLOCK_1 ((uint16_t)0x0800) /*!< Bit 1 */ +#define USB_COUNT2_RX_NUM_BLOCK_2 ((uint16_t)0x1000) /*!< Bit 2 */ +#define USB_COUNT2_RX_NUM_BLOCK_3 ((uint16_t)0x2000) /*!< Bit 3 */ +#define USB_COUNT2_RX_NUM_BLOCK_4 ((uint16_t)0x4000) /*!< Bit 4 */ + +#define USB_COUNT2_RX_BLSIZE ((uint16_t)0x8000) /*!< BLock SIZE */ + +/***************** Bit definition for USB_COUNT3_RX register ****************/ +#define USB_COUNT3_RX_COUNT3_RX ((uint16_t)0x03FF) /*!< Reception Byte Count */ + +#define USB_COUNT3_RX_NUM_BLOCK ((uint16_t)0x7C00) /*!< NUM_BLOCK[4:0] bits (Number of blocks) */ +#define USB_COUNT3_RX_NUM_BLOCK_0 ((uint16_t)0x0400) /*!< Bit 0 */ +#define USB_COUNT3_RX_NUM_BLOCK_1 ((uint16_t)0x0800) /*!< Bit 1 */ +#define USB_COUNT3_RX_NUM_BLOCK_2 ((uint16_t)0x1000) /*!< Bit 2 */ +#define USB_COUNT3_RX_NUM_BLOCK_3 ((uint16_t)0x2000) /*!< Bit 3 */ +#define USB_COUNT3_RX_NUM_BLOCK_4 ((uint16_t)0x4000) /*!< Bit 4 */ + +#define USB_COUNT3_RX_BLSIZE ((uint16_t)0x8000) /*!< BLock SIZE */ + +/***************** Bit definition for USB_COUNT4_RX register ****************/ +#define USB_COUNT4_RX_COUNT4_RX ((uint16_t)0x03FF) /*!< Reception Byte Count */ + +#define USB_COUNT4_RX_NUM_BLOCK ((uint16_t)0x7C00) /*!< NUM_BLOCK[4:0] bits (Number of blocks) */ +#define USB_COUNT4_RX_NUM_BLOCK_0 ((uint16_t)0x0400) /*!< Bit 0 */ +#define USB_COUNT4_RX_NUM_BLOCK_1 ((uint16_t)0x0800) /*!< Bit 1 */ +#define USB_COUNT4_RX_NUM_BLOCK_2 ((uint16_t)0x1000) /*!< Bit 2 */ +#define USB_COUNT4_RX_NUM_BLOCK_3 ((uint16_t)0x2000) /*!< Bit 3 */ +#define USB_COUNT4_RX_NUM_BLOCK_4 ((uint16_t)0x4000) /*!< Bit 4 */ + +#define USB_COUNT4_RX_BLSIZE ((uint16_t)0x8000) /*!< BLock SIZE */ + +/***************** Bit definition for USB_COUNT5_RX register ****************/ +#define USB_COUNT5_RX_COUNT5_RX ((uint16_t)0x03FF) /*!< Reception Byte Count */ + +#define USB_COUNT5_RX_NUM_BLOCK ((uint16_t)0x7C00) /*!< NUM_BLOCK[4:0] bits (Number of blocks) */ +#define USB_COUNT5_RX_NUM_BLOCK_0 ((uint16_t)0x0400) /*!< Bit 0 */ +#define USB_COUNT5_RX_NUM_BLOCK_1 ((uint16_t)0x0800) /*!< Bit 1 */ +#define USB_COUNT5_RX_NUM_BLOCK_2 ((uint16_t)0x1000) /*!< Bit 2 */ +#define USB_COUNT5_RX_NUM_BLOCK_3 ((uint16_t)0x2000) /*!< Bit 3 */ +#define USB_COUNT5_RX_NUM_BLOCK_4 ((uint16_t)0x4000) /*!< Bit 4 */ + +#define USB_COUNT5_RX_BLSIZE ((uint16_t)0x8000) /*!< BLock SIZE */ + +/***************** Bit definition for USB_COUNT6_RX register ****************/ +#define USB_COUNT6_RX_COUNT6_RX ((uint16_t)0x03FF) /*!< Reception Byte Count */ + +#define USB_COUNT6_RX_NUM_BLOCK ((uint16_t)0x7C00) /*!< NUM_BLOCK[4:0] bits (Number of blocks) */ +#define USB_COUNT6_RX_NUM_BLOCK_0 ((uint16_t)0x0400) /*!< Bit 0 */ +#define USB_COUNT6_RX_NUM_BLOCK_1 ((uint16_t)0x0800) /*!< Bit 1 */ +#define USB_COUNT6_RX_NUM_BLOCK_2 ((uint16_t)0x1000) /*!< Bit 2 */ +#define USB_COUNT6_RX_NUM_BLOCK_3 ((uint16_t)0x2000) /*!< Bit 3 */ +#define USB_COUNT6_RX_NUM_BLOCK_4 ((uint16_t)0x4000) /*!< Bit 4 */ + +#define USB_COUNT6_RX_BLSIZE ((uint16_t)0x8000) /*!< BLock SIZE */ + +/***************** Bit definition for USB_COUNT7_RX register ****************/ +#define USB_COUNT7_RX_COUNT7_RX ((uint16_t)0x03FF) /*!< Reception Byte Count */ + +#define USB_COUNT7_RX_NUM_BLOCK ((uint16_t)0x7C00) /*!< NUM_BLOCK[4:0] bits (Number of blocks) */ +#define USB_COUNT7_RX_NUM_BLOCK_0 ((uint16_t)0x0400) /*!< Bit 0 */ +#define USB_COUNT7_RX_NUM_BLOCK_1 ((uint16_t)0x0800) /*!< Bit 1 */ +#define USB_COUNT7_RX_NUM_BLOCK_2 ((uint16_t)0x1000) /*!< Bit 2 */ +#define USB_COUNT7_RX_NUM_BLOCK_3 ((uint16_t)0x2000) /*!< Bit 3 */ +#define USB_COUNT7_RX_NUM_BLOCK_4 ((uint16_t)0x4000) /*!< Bit 4 */ + +#define USB_COUNT7_RX_BLSIZE ((uint16_t)0x8000) /*!< BLock SIZE */ + +/*----------------------------------------------------------------------------*/ + +/**************** Bit definition for USB_COUNT0_RX_0 register ***************/ +#define USB_COUNT0_RX_0_COUNT0_RX_0 ((uint32_t)0x000003FF) /*!< Reception Byte Count (low) */ + +#define USB_COUNT0_RX_0_NUM_BLOCK_0 ((uint32_t)0x00007C00) /*!< NUM_BLOCK_0[4:0] bits (Number of blocks) (low) */ +#define USB_COUNT0_RX_0_NUM_BLOCK_0_0 ((uint32_t)0x00000400) /*!< Bit 0 */ +#define USB_COUNT0_RX_0_NUM_BLOCK_0_1 ((uint32_t)0x00000800) /*!< Bit 1 */ +#define USB_COUNT0_RX_0_NUM_BLOCK_0_2 ((uint32_t)0x00001000) /*!< Bit 2 */ +#define USB_COUNT0_RX_0_NUM_BLOCK_0_3 ((uint32_t)0x00002000) /*!< Bit 3 */ +#define USB_COUNT0_RX_0_NUM_BLOCK_0_4 ((uint32_t)0x00004000) /*!< Bit 4 */ + +#define USB_COUNT0_RX_0_BLSIZE_0 ((uint32_t)0x00008000) /*!< BLock SIZE (low) */ + +/**************** Bit definition for USB_COUNT0_RX_1 register ***************/ +#define USB_COUNT0_RX_1_COUNT0_RX_1 ((uint32_t)0x03FF0000) /*!< Reception Byte Count (high) */ + +#define USB_COUNT0_RX_1_NUM_BLOCK_1 ((uint32_t)0x7C000000) /*!< NUM_BLOCK_1[4:0] bits (Number of blocks) (high) */ +#define USB_COUNT0_RX_1_NUM_BLOCK_1_0 ((uint32_t)0x04000000) /*!< Bit 1 */ +#define USB_COUNT0_RX_1_NUM_BLOCK_1_1 ((uint32_t)0x08000000) /*!< Bit 1 */ +#define USB_COUNT0_RX_1_NUM_BLOCK_1_2 ((uint32_t)0x10000000) /*!< Bit 2 */ +#define USB_COUNT0_RX_1_NUM_BLOCK_1_3 ((uint32_t)0x20000000) /*!< Bit 3 */ +#define USB_COUNT0_RX_1_NUM_BLOCK_1_4 ((uint32_t)0x40000000) /*!< Bit 4 */ + +#define USB_COUNT0_RX_1_BLSIZE_1 ((uint32_t)0x80000000) /*!< BLock SIZE (high) */ + +/**************** Bit definition for USB_COUNT1_RX_0 register ***************/ +#define USB_COUNT1_RX_0_COUNT1_RX_0 ((uint32_t)0x000003FF) /*!< Reception Byte Count (low) */ + +#define USB_COUNT1_RX_0_NUM_BLOCK_0 ((uint32_t)0x00007C00) /*!< NUM_BLOCK_0[4:0] bits (Number of blocks) (low) */ +#define USB_COUNT1_RX_0_NUM_BLOCK_0_0 ((uint32_t)0x00000400) /*!< Bit 0 */ +#define USB_COUNT1_RX_0_NUM_BLOCK_0_1 ((uint32_t)0x00000800) /*!< Bit 1 */ +#define USB_COUNT1_RX_0_NUM_BLOCK_0_2 ((uint32_t)0x00001000) /*!< Bit 2 */ +#define USB_COUNT1_RX_0_NUM_BLOCK_0_3 ((uint32_t)0x00002000) /*!< Bit 3 */ +#define USB_COUNT1_RX_0_NUM_BLOCK_0_4 ((uint32_t)0x00004000) /*!< Bit 4 */ + +#define USB_COUNT1_RX_0_BLSIZE_0 ((uint32_t)0x00008000) /*!< BLock SIZE (low) */ + +/**************** Bit definition for USB_COUNT1_RX_1 register ***************/ +#define USB_COUNT1_RX_1_COUNT1_RX_1 ((uint32_t)0x03FF0000) /*!< Reception Byte Count (high) */ + +#define USB_COUNT1_RX_1_NUM_BLOCK_1 ((uint32_t)0x7C000000) /*!< NUM_BLOCK_1[4:0] bits (Number of blocks) (high) */ +#define USB_COUNT1_RX_1_NUM_BLOCK_1_0 ((uint32_t)0x04000000) /*!< Bit 0 */ +#define USB_COUNT1_RX_1_NUM_BLOCK_1_1 ((uint32_t)0x08000000) /*!< Bit 1 */ +#define USB_COUNT1_RX_1_NUM_BLOCK_1_2 ((uint32_t)0x10000000) /*!< Bit 2 */ +#define USB_COUNT1_RX_1_NUM_BLOCK_1_3 ((uint32_t)0x20000000) /*!< Bit 3 */ +#define USB_COUNT1_RX_1_NUM_BLOCK_1_4 ((uint32_t)0x40000000) /*!< Bit 4 */ + +#define USB_COUNT1_RX_1_BLSIZE_1 ((uint32_t)0x80000000) /*!< BLock SIZE (high) */ + +/**************** Bit definition for USB_COUNT2_RX_0 register ***************/ +#define USB_COUNT2_RX_0_COUNT2_RX_0 ((uint32_t)0x000003FF) /*!< Reception Byte Count (low) */ + +#define USB_COUNT2_RX_0_NUM_BLOCK_0 ((uint32_t)0x00007C00) /*!< NUM_BLOCK_0[4:0] bits (Number of blocks) (low) */ +#define USB_COUNT2_RX_0_NUM_BLOCK_0_0 ((uint32_t)0x00000400) /*!< Bit 0 */ +#define USB_COUNT2_RX_0_NUM_BLOCK_0_1 ((uint32_t)0x00000800) /*!< Bit 1 */ +#define USB_COUNT2_RX_0_NUM_BLOCK_0_2 ((uint32_t)0x00001000) /*!< Bit 2 */ +#define USB_COUNT2_RX_0_NUM_BLOCK_0_3 ((uint32_t)0x00002000) /*!< Bit 3 */ +#define USB_COUNT2_RX_0_NUM_BLOCK_0_4 ((uint32_t)0x00004000) /*!< Bit 4 */ + +#define USB_COUNT2_RX_0_BLSIZE_0 ((uint32_t)0x00008000) /*!< BLock SIZE (low) */ + +/**************** Bit definition for USB_COUNT2_RX_1 register ***************/ +#define USB_COUNT2_RX_1_COUNT2_RX_1 ((uint32_t)0x03FF0000) /*!< Reception Byte Count (high) */ + +#define USB_COUNT2_RX_1_NUM_BLOCK_1 ((uint32_t)0x7C000000) /*!< NUM_BLOCK_1[4:0] bits (Number of blocks) (high) */ +#define USB_COUNT2_RX_1_NUM_BLOCK_1_0 ((uint32_t)0x04000000) /*!< Bit 0 */ +#define USB_COUNT2_RX_1_NUM_BLOCK_1_1 ((uint32_t)0x08000000) /*!< Bit 1 */ +#define USB_COUNT2_RX_1_NUM_BLOCK_1_2 ((uint32_t)0x10000000) /*!< Bit 2 */ +#define USB_COUNT2_RX_1_NUM_BLOCK_1_3 ((uint32_t)0x20000000) /*!< Bit 3 */ +#define USB_COUNT2_RX_1_NUM_BLOCK_1_4 ((uint32_t)0x40000000) /*!< Bit 4 */ + +#define USB_COUNT2_RX_1_BLSIZE_1 ((uint32_t)0x80000000) /*!< BLock SIZE (high) */ + +/**************** Bit definition for USB_COUNT3_RX_0 register ***************/ +#define USB_COUNT3_RX_0_COUNT3_RX_0 ((uint32_t)0x000003FF) /*!< Reception Byte Count (low) */ + +#define USB_COUNT3_RX_0_NUM_BLOCK_0 ((uint32_t)0x00007C00) /*!< NUM_BLOCK_0[4:0] bits (Number of blocks) (low) */ +#define USB_COUNT3_RX_0_NUM_BLOCK_0_0 ((uint32_t)0x00000400) /*!< Bit 0 */ +#define USB_COUNT3_RX_0_NUM_BLOCK_0_1 ((uint32_t)0x00000800) /*!< Bit 1 */ +#define USB_COUNT3_RX_0_NUM_BLOCK_0_2 ((uint32_t)0x00001000) /*!< Bit 2 */ +#define USB_COUNT3_RX_0_NUM_BLOCK_0_3 ((uint32_t)0x00002000) /*!< Bit 3 */ +#define USB_COUNT3_RX_0_NUM_BLOCK_0_4 ((uint32_t)0x00004000) /*!< Bit 4 */ + +#define USB_COUNT3_RX_0_BLSIZE_0 ((uint32_t)0x00008000) /*!< BLock SIZE (low) */ + +/**************** Bit definition for USB_COUNT3_RX_1 register ***************/ +#define USB_COUNT3_RX_1_COUNT3_RX_1 ((uint32_t)0x03FF0000) /*!< Reception Byte Count (high) */ + +#define USB_COUNT3_RX_1_NUM_BLOCK_1 ((uint32_t)0x7C000000) /*!< NUM_BLOCK_1[4:0] bits (Number of blocks) (high) */ +#define USB_COUNT3_RX_1_NUM_BLOCK_1_0 ((uint32_t)0x04000000) /*!< Bit 0 */ +#define USB_COUNT3_RX_1_NUM_BLOCK_1_1 ((uint32_t)0x08000000) /*!< Bit 1 */ +#define USB_COUNT3_RX_1_NUM_BLOCK_1_2 ((uint32_t)0x10000000) /*!< Bit 2 */ +#define USB_COUNT3_RX_1_NUM_BLOCK_1_3 ((uint32_t)0x20000000) /*!< Bit 3 */ +#define USB_COUNT3_RX_1_NUM_BLOCK_1_4 ((uint32_t)0x40000000) /*!< Bit 4 */ + +#define USB_COUNT3_RX_1_BLSIZE_1 ((uint32_t)0x80000000) /*!< BLock SIZE (high) */ + +/**************** Bit definition for USB_COUNT4_RX_0 register ***************/ +#define USB_COUNT4_RX_0_COUNT4_RX_0 ((uint32_t)0x000003FF) /*!< Reception Byte Count (low) */ + +#define USB_COUNT4_RX_0_NUM_BLOCK_0 ((uint32_t)0x00007C00) /*!< NUM_BLOCK_0[4:0] bits (Number of blocks) (low) */ +#define USB_COUNT4_RX_0_NUM_BLOCK_0_0 ((uint32_t)0x00000400) /*!< Bit 0 */ +#define USB_COUNT4_RX_0_NUM_BLOCK_0_1 ((uint32_t)0x00000800) /*!< Bit 1 */ +#define USB_COUNT4_RX_0_NUM_BLOCK_0_2 ((uint32_t)0x00001000) /*!< Bit 2 */ +#define USB_COUNT4_RX_0_NUM_BLOCK_0_3 ((uint32_t)0x00002000) /*!< Bit 3 */ +#define USB_COUNT4_RX_0_NUM_BLOCK_0_4 ((uint32_t)0x00004000) /*!< Bit 4 */ + +#define USB_COUNT4_RX_0_BLSIZE_0 ((uint32_t)0x00008000) /*!< BLock SIZE (low) */ + +/**************** Bit definition for USB_COUNT4_RX_1 register ***************/ +#define USB_COUNT4_RX_1_COUNT4_RX_1 ((uint32_t)0x03FF0000) /*!< Reception Byte Count (high) */ + +#define USB_COUNT4_RX_1_NUM_BLOCK_1 ((uint32_t)0x7C000000) /*!< NUM_BLOCK_1[4:0] bits (Number of blocks) (high) */ +#define USB_COUNT4_RX_1_NUM_BLOCK_1_0 ((uint32_t)0x04000000) /*!< Bit 0 */ +#define USB_COUNT4_RX_1_NUM_BLOCK_1_1 ((uint32_t)0x08000000) /*!< Bit 1 */ +#define USB_COUNT4_RX_1_NUM_BLOCK_1_2 ((uint32_t)0x10000000) /*!< Bit 2 */ +#define USB_COUNT4_RX_1_NUM_BLOCK_1_3 ((uint32_t)0x20000000) /*!< Bit 3 */ +#define USB_COUNT4_RX_1_NUM_BLOCK_1_4 ((uint32_t)0x40000000) /*!< Bit 4 */ + +#define USB_COUNT4_RX_1_BLSIZE_1 ((uint32_t)0x80000000) /*!< BLock SIZE (high) */ + +/**************** Bit definition for USB_COUNT5_RX_0 register ***************/ +#define USB_COUNT5_RX_0_COUNT5_RX_0 ((uint32_t)0x000003FF) /*!< Reception Byte Count (low) */ + +#define USB_COUNT5_RX_0_NUM_BLOCK_0 ((uint32_t)0x00007C00) /*!< NUM_BLOCK_0[4:0] bits (Number of blocks) (low) */ +#define USB_COUNT5_RX_0_NUM_BLOCK_0_0 ((uint32_t)0x00000400) /*!< Bit 0 */ +#define USB_COUNT5_RX_0_NUM_BLOCK_0_1 ((uint32_t)0x00000800) /*!< Bit 1 */ +#define USB_COUNT5_RX_0_NUM_BLOCK_0_2 ((uint32_t)0x00001000) /*!< Bit 2 */ +#define USB_COUNT5_RX_0_NUM_BLOCK_0_3 ((uint32_t)0x00002000) /*!< Bit 3 */ +#define USB_COUNT5_RX_0_NUM_BLOCK_0_4 ((uint32_t)0x00004000) /*!< Bit 4 */ + +#define USB_COUNT5_RX_0_BLSIZE_0 ((uint32_t)0x00008000) /*!< BLock SIZE (low) */ + +/**************** Bit definition for USB_COUNT5_RX_1 register ***************/ +#define USB_COUNT5_RX_1_COUNT5_RX_1 ((uint32_t)0x03FF0000) /*!< Reception Byte Count (high) */ + +#define USB_COUNT5_RX_1_NUM_BLOCK_1 ((uint32_t)0x7C000000) /*!< NUM_BLOCK_1[4:0] bits (Number of blocks) (high) */ +#define USB_COUNT5_RX_1_NUM_BLOCK_1_0 ((uint32_t)0x04000000) /*!< Bit 0 */ +#define USB_COUNT5_RX_1_NUM_BLOCK_1_1 ((uint32_t)0x08000000) /*!< Bit 1 */ +#define USB_COUNT5_RX_1_NUM_BLOCK_1_2 ((uint32_t)0x10000000) /*!< Bit 2 */ +#define USB_COUNT5_RX_1_NUM_BLOCK_1_3 ((uint32_t)0x20000000) /*!< Bit 3 */ +#define USB_COUNT5_RX_1_NUM_BLOCK_1_4 ((uint32_t)0x40000000) /*!< Bit 4 */ + +#define USB_COUNT5_RX_1_BLSIZE_1 ((uint32_t)0x80000000) /*!< BLock SIZE (high) */ + +/*************** Bit definition for USB_COUNT6_RX_0 register ***************/ +#define USB_COUNT6_RX_0_COUNT6_RX_0 ((uint32_t)0x000003FF) /*!< Reception Byte Count (low) */ + +#define USB_COUNT6_RX_0_NUM_BLOCK_0 ((uint32_t)0x00007C00) /*!< NUM_BLOCK_0[4:0] bits (Number of blocks) (low) */ +#define USB_COUNT6_RX_0_NUM_BLOCK_0_0 ((uint32_t)0x00000400) /*!< Bit 0 */ +#define USB_COUNT6_RX_0_NUM_BLOCK_0_1 ((uint32_t)0x00000800) /*!< Bit 1 */ +#define USB_COUNT6_RX_0_NUM_BLOCK_0_2 ((uint32_t)0x00001000) /*!< Bit 2 */ +#define USB_COUNT6_RX_0_NUM_BLOCK_0_3 ((uint32_t)0x00002000) /*!< Bit 3 */ +#define USB_COUNT6_RX_0_NUM_BLOCK_0_4 ((uint32_t)0x00004000) /*!< Bit 4 */ + +#define USB_COUNT6_RX_0_BLSIZE_0 ((uint32_t)0x00008000) /*!< BLock SIZE (low) */ + +/**************** Bit definition for USB_COUNT6_RX_1 register ***************/ +#define USB_COUNT6_RX_1_COUNT6_RX_1 ((uint32_t)0x03FF0000) /*!< Reception Byte Count (high) */ + +#define USB_COUNT6_RX_1_NUM_BLOCK_1 ((uint32_t)0x7C000000) /*!< NUM_BLOCK_1[4:0] bits (Number of blocks) (high) */ +#define USB_COUNT6_RX_1_NUM_BLOCK_1_0 ((uint32_t)0x04000000) /*!< Bit 0 */ +#define USB_COUNT6_RX_1_NUM_BLOCK_1_1 ((uint32_t)0x08000000) /*!< Bit 1 */ +#define USB_COUNT6_RX_1_NUM_BLOCK_1_2 ((uint32_t)0x10000000) /*!< Bit 2 */ +#define USB_COUNT6_RX_1_NUM_BLOCK_1_3 ((uint32_t)0x20000000) /*!< Bit 3 */ +#define USB_COUNT6_RX_1_NUM_BLOCK_1_4 ((uint32_t)0x40000000) /*!< Bit 4 */ + +#define USB_COUNT6_RX_1_BLSIZE_1 ((uint32_t)0x80000000) /*!< BLock SIZE (high) */ + +/*************** Bit definition for USB_COUNT7_RX_0 register ****************/ +#define USB_COUNT7_RX_0_COUNT7_RX_0 ((uint32_t)0x000003FF) /*!< Reception Byte Count (low) */ + +#define USB_COUNT7_RX_0_NUM_BLOCK_0 ((uint32_t)0x00007C00) /*!< NUM_BLOCK_0[4:0] bits (Number of blocks) (low) */ +#define USB_COUNT7_RX_0_NUM_BLOCK_0_0 ((uint32_t)0x00000400) /*!< Bit 0 */ +#define USB_COUNT7_RX_0_NUM_BLOCK_0_1 ((uint32_t)0x00000800) /*!< Bit 1 */ +#define USB_COUNT7_RX_0_NUM_BLOCK_0_2 ((uint32_t)0x00001000) /*!< Bit 2 */ +#define USB_COUNT7_RX_0_NUM_BLOCK_0_3 ((uint32_t)0x00002000) /*!< Bit 3 */ +#define USB_COUNT7_RX_0_NUM_BLOCK_0_4 ((uint32_t)0x00004000) /*!< Bit 4 */ + +#define USB_COUNT7_RX_0_BLSIZE_0 ((uint32_t)0x00008000) /*!< BLock SIZE (low) */ + +/*************** Bit definition for USB_COUNT7_RX_1 register ****************/ +#define USB_COUNT7_RX_1_COUNT7_RX_1 ((uint32_t)0x03FF0000) /*!< Reception Byte Count (high) */ + +#define USB_COUNT7_RX_1_NUM_BLOCK_1 ((uint32_t)0x7C000000) /*!< NUM_BLOCK_1[4:0] bits (Number of blocks) (high) */ +#define USB_COUNT7_RX_1_NUM_BLOCK_1_0 ((uint32_t)0x04000000) /*!< Bit 0 */ +#define USB_COUNT7_RX_1_NUM_BLOCK_1_1 ((uint32_t)0x08000000) /*!< Bit 1 */ +#define USB_COUNT7_RX_1_NUM_BLOCK_1_2 ((uint32_t)0x10000000) /*!< Bit 2 */ +#define USB_COUNT7_RX_1_NUM_BLOCK_1_3 ((uint32_t)0x20000000) /*!< Bit 3 */ +#define USB_COUNT7_RX_1_NUM_BLOCK_1_4 ((uint32_t)0x40000000) /*!< Bit 4 */ + +#define USB_COUNT7_RX_1_BLSIZE_1 ((uint32_t)0x80000000) /*!< BLock SIZE (high) */ + +/******************************************************************************/ +/* */ +/* Controller Area Network */ +/* */ +/******************************************************************************/ + +/*!< CAN control and status registers */ +/******************* Bit definition for CAN_MCR register ********************/ +#define CAN_MCR_INRQ ((uint16_t)0x0001) /*!< Initialization Request */ +#define CAN_MCR_SLEEP ((uint16_t)0x0002) /*!< Sleep Mode Request */ +#define CAN_MCR_TXFP ((uint16_t)0x0004) /*!< Transmit FIFO Priority */ +#define CAN_MCR_RFLM ((uint16_t)0x0008) /*!< Receive FIFO Locked Mode */ +#define CAN_MCR_NART ((uint16_t)0x0010) /*!< No Automatic Retransmission */ +#define CAN_MCR_AWUM ((uint16_t)0x0020) /*!< Automatic Wakeup Mode */ +#define CAN_MCR_ABOM ((uint16_t)0x0040) /*!< Automatic Bus-Off Management */ +#define CAN_MCR_TTCM ((uint16_t)0x0080) /*!< Time Triggered Communication Mode */ +#define CAN_MCR_RESET ((uint16_t)0x8000) /*!< CAN software master reset */ + +/******************* Bit definition for CAN_MSR register ********************/ +#define CAN_MSR_INAK ((uint16_t)0x0001) /*!< Initialization Acknowledge */ +#define CAN_MSR_SLAK ((uint16_t)0x0002) /*!< Sleep Acknowledge */ +#define CAN_MSR_ERRI ((uint16_t)0x0004) /*!< Error Interrupt */ +#define CAN_MSR_WKUI ((uint16_t)0x0008) /*!< Wakeup Interrupt */ +#define CAN_MSR_SLAKI ((uint16_t)0x0010) /*!< Sleep Acknowledge Interrupt */ +#define CAN_MSR_TXM ((uint16_t)0x0100) /*!< Transmit Mode */ +#define CAN_MSR_RXM ((uint16_t)0x0200) /*!< Receive Mode */ +#define CAN_MSR_SAMP ((uint16_t)0x0400) /*!< Last Sample Point */ +#define CAN_MSR_RX ((uint16_t)0x0800) /*!< CAN Rx Signal */ + +/******************* Bit definition for CAN_TSR register ********************/ +#define CAN_TSR_RQCP0 ((uint32_t)0x00000001) /*!< Request Completed Mailbox0 */ +#define CAN_TSR_TXOK0 ((uint32_t)0x00000002) /*!< Transmission OK of Mailbox0 */ +#define CAN_TSR_ALST0 ((uint32_t)0x00000004) /*!< Arbitration Lost for Mailbox0 */ +#define CAN_TSR_TERR0 ((uint32_t)0x00000008) /*!< Transmission Error of Mailbox0 */ +#define CAN_TSR_ABRQ0 ((uint32_t)0x00000080) /*!< Abort Request for Mailbox0 */ +#define CAN_TSR_RQCP1 ((uint32_t)0x00000100) /*!< Request Completed Mailbox1 */ +#define CAN_TSR_TXOK1 ((uint32_t)0x00000200) /*!< Transmission OK of Mailbox1 */ +#define CAN_TSR_ALST1 ((uint32_t)0x00000400) /*!< Arbitration Lost for Mailbox1 */ +#define CAN_TSR_TERR1 ((uint32_t)0x00000800) /*!< Transmission Error of Mailbox1 */ +#define CAN_TSR_ABRQ1 ((uint32_t)0x00008000) /*!< Abort Request for Mailbox 1 */ +#define CAN_TSR_RQCP2 ((uint32_t)0x00010000) /*!< Request Completed Mailbox2 */ +#define CAN_TSR_TXOK2 ((uint32_t)0x00020000) /*!< Transmission OK of Mailbox 2 */ +#define CAN_TSR_ALST2 ((uint32_t)0x00040000) /*!< Arbitration Lost for mailbox 2 */ +#define CAN_TSR_TERR2 ((uint32_t)0x00080000) /*!< Transmission Error of Mailbox 2 */ +#define CAN_TSR_ABRQ2 ((uint32_t)0x00800000) /*!< Abort Request for Mailbox 2 */ +#define CAN_TSR_CODE ((uint32_t)0x03000000) /*!< Mailbox Code */ + +#define CAN_TSR_TME ((uint32_t)0x1C000000) /*!< TME[2:0] bits */ +#define CAN_TSR_TME0 ((uint32_t)0x04000000) /*!< Transmit Mailbox 0 Empty */ +#define CAN_TSR_TME1 ((uint32_t)0x08000000) /*!< Transmit Mailbox 1 Empty */ +#define CAN_TSR_TME2 ((uint32_t)0x10000000) /*!< Transmit Mailbox 2 Empty */ + +#define CAN_TSR_LOW ((uint32_t)0xE0000000) /*!< LOW[2:0] bits */ +#define CAN_TSR_LOW0 ((uint32_t)0x20000000) /*!< Lowest Priority Flag for Mailbox 0 */ +#define CAN_TSR_LOW1 ((uint32_t)0x40000000) /*!< Lowest Priority Flag for Mailbox 1 */ +#define CAN_TSR_LOW2 ((uint32_t)0x80000000) /*!< Lowest Priority Flag for Mailbox 2 */ + +/******************* Bit definition for CAN_RF0R register *******************/ +#define CAN_RF0R_FMP0 ((uint8_t)0x03) /*!< FIFO 0 Message Pending */ +#define CAN_RF0R_FULL0 ((uint8_t)0x08) /*!< FIFO 0 Full */ +#define CAN_RF0R_FOVR0 ((uint8_t)0x10) /*!< FIFO 0 Overrun */ +#define CAN_RF0R_RFOM0 ((uint8_t)0x20) /*!< Release FIFO 0 Output Mailbox */ + +/******************* Bit definition for CAN_RF1R register *******************/ +#define CAN_RF1R_FMP1 ((uint8_t)0x03) /*!< FIFO 1 Message Pending */ +#define CAN_RF1R_FULL1 ((uint8_t)0x08) /*!< FIFO 1 Full */ +#define CAN_RF1R_FOVR1 ((uint8_t)0x10) /*!< FIFO 1 Overrun */ +#define CAN_RF1R_RFOM1 ((uint8_t)0x20) /*!< Release FIFO 1 Output Mailbox */ + +/******************** Bit definition for CAN_IER register *******************/ +#define CAN_IER_TMEIE ((uint32_t)0x00000001) /*!< Transmit Mailbox Empty Interrupt Enable */ +#define CAN_IER_FMPIE0 ((uint32_t)0x00000002) /*!< FIFO Message Pending Interrupt Enable */ +#define CAN_IER_FFIE0 ((uint32_t)0x00000004) /*!< FIFO Full Interrupt Enable */ +#define CAN_IER_FOVIE0 ((uint32_t)0x00000008) /*!< FIFO Overrun Interrupt Enable */ +#define CAN_IER_FMPIE1 ((uint32_t)0x00000010) /*!< FIFO Message Pending Interrupt Enable */ +#define CAN_IER_FFIE1 ((uint32_t)0x00000020) /*!< FIFO Full Interrupt Enable */ +#define CAN_IER_FOVIE1 ((uint32_t)0x00000040) /*!< FIFO Overrun Interrupt Enable */ +#define CAN_IER_EWGIE ((uint32_t)0x00000100) /*!< Error Warning Interrupt Enable */ +#define CAN_IER_EPVIE ((uint32_t)0x00000200) /*!< Error Passive Interrupt Enable */ +#define CAN_IER_BOFIE ((uint32_t)0x00000400) /*!< Bus-Off Interrupt Enable */ +#define CAN_IER_LECIE ((uint32_t)0x00000800) /*!< Last Error Code Interrupt Enable */ +#define CAN_IER_ERRIE ((uint32_t)0x00008000) /*!< Error Interrupt Enable */ +#define CAN_IER_WKUIE ((uint32_t)0x00010000) /*!< Wakeup Interrupt Enable */ +#define CAN_IER_SLKIE ((uint32_t)0x00020000) /*!< Sleep Interrupt Enable */ + +/******************** Bit definition for CAN_ESR register *******************/ +#define CAN_ESR_EWGF ((uint32_t)0x00000001) /*!< Error Warning Flag */ +#define CAN_ESR_EPVF ((uint32_t)0x00000002) /*!< Error Passive Flag */ +#define CAN_ESR_BOFF ((uint32_t)0x00000004) /*!< Bus-Off Flag */ + +#define CAN_ESR_LEC ((uint32_t)0x00000070) /*!< LEC[2:0] bits (Last Error Code) */ +#define CAN_ESR_LEC_0 ((uint32_t)0x00000010) /*!< Bit 0 */ +#define CAN_ESR_LEC_1 ((uint32_t)0x00000020) /*!< Bit 1 */ +#define CAN_ESR_LEC_2 ((uint32_t)0x00000040) /*!< Bit 2 */ + +#define CAN_ESR_TEC ((uint32_t)0x00FF0000) /*!< Least significant byte of the 9-bit Transmit Error Counter */ +#define CAN_ESR_REC ((uint32_t)0xFF000000) /*!< Receive Error Counter */ + +/******************* Bit definition for CAN_BTR register ********************/ +#define CAN_BTR_BRP ((uint32_t)0x000003FF) /*!< Baud Rate Prescaler */ +#define CAN_BTR_TS1 ((uint32_t)0x000F0000) /*!< Time Segment 1 */ +#define CAN_BTR_TS2 ((uint32_t)0x00700000) /*!< Time Segment 2 */ +#define CAN_BTR_SJW ((uint32_t)0x03000000) /*!< Resynchronization Jump Width */ +#define CAN_BTR_LBKM ((uint32_t)0x40000000) /*!< Loop Back Mode (Debug) */ +#define CAN_BTR_SILM ((uint32_t)0x80000000) /*!< Silent Mode */ + +/*!< Mailbox registers */ +/****************** Bit definition for CAN_TI0R register ********************/ +#define CAN_TI0R_TXRQ ((uint32_t)0x00000001) /*!< Transmit Mailbox Request */ +#define CAN_TI0R_RTR ((uint32_t)0x00000002) /*!< Remote Transmission Request */ +#define CAN_TI0R_IDE ((uint32_t)0x00000004) /*!< Identifier Extension */ +#define CAN_TI0R_EXID ((uint32_t)0x001FFFF8) /*!< Extended Identifier */ +#define CAN_TI0R_STID ((uint32_t)0xFFE00000) /*!< Standard Identifier or Extended Identifier */ + +/****************** Bit definition for CAN_TDT0R register *******************/ +#define CAN_TDT0R_DLC ((uint32_t)0x0000000F) /*!< Data Length Code */ +#define CAN_TDT0R_TGT ((uint32_t)0x00000100) /*!< Transmit Global Time */ +#define CAN_TDT0R_TIME ((uint32_t)0xFFFF0000) /*!< Message Time Stamp */ + +/****************** Bit definition for CAN_TDL0R register *******************/ +#define CAN_TDL0R_DATA0 ((uint32_t)0x000000FF) /*!< Data byte 0 */ +#define CAN_TDL0R_DATA1 ((uint32_t)0x0000FF00) /*!< Data byte 1 */ +#define CAN_TDL0R_DATA2 ((uint32_t)0x00FF0000) /*!< Data byte 2 */ +#define CAN_TDL0R_DATA3 ((uint32_t)0xFF000000) /*!< Data byte 3 */ + +/****************** Bit definition for CAN_TDH0R register *******************/ +#define CAN_TDH0R_DATA4 ((uint32_t)0x000000FF) /*!< Data byte 4 */ +#define CAN_TDH0R_DATA5 ((uint32_t)0x0000FF00) /*!< Data byte 5 */ +#define CAN_TDH0R_DATA6 ((uint32_t)0x00FF0000) /*!< Data byte 6 */ +#define CAN_TDH0R_DATA7 ((uint32_t)0xFF000000) /*!< Data byte 7 */ + +/******************* Bit definition for CAN_TI1R register *******************/ +#define CAN_TI1R_TXRQ ((uint32_t)0x00000001) /*!< Transmit Mailbox Request */ +#define CAN_TI1R_RTR ((uint32_t)0x00000002) /*!< Remote Transmission Request */ +#define CAN_TI1R_IDE ((uint32_t)0x00000004) /*!< Identifier Extension */ +#define CAN_TI1R_EXID ((uint32_t)0x001FFFF8) /*!< Extended Identifier */ +#define CAN_TI1R_STID ((uint32_t)0xFFE00000) /*!< Standard Identifier or Extended Identifier */ + +/******************* Bit definition for CAN_TDT1R register ******************/ +#define CAN_TDT1R_DLC ((uint32_t)0x0000000F) /*!< Data Length Code */ +#define CAN_TDT1R_TGT ((uint32_t)0x00000100) /*!< Transmit Global Time */ +#define CAN_TDT1R_TIME ((uint32_t)0xFFFF0000) /*!< Message Time Stamp */ + +/******************* Bit definition for CAN_TDL1R register ******************/ +#define CAN_TDL1R_DATA0 ((uint32_t)0x000000FF) /*!< Data byte 0 */ +#define CAN_TDL1R_DATA1 ((uint32_t)0x0000FF00) /*!< Data byte 1 */ +#define CAN_TDL1R_DATA2 ((uint32_t)0x00FF0000) /*!< Data byte 2 */ +#define CAN_TDL1R_DATA3 ((uint32_t)0xFF000000) /*!< Data byte 3 */ + +/******************* Bit definition for CAN_TDH1R register ******************/ +#define CAN_TDH1R_DATA4 ((uint32_t)0x000000FF) /*!< Data byte 4 */ +#define CAN_TDH1R_DATA5 ((uint32_t)0x0000FF00) /*!< Data byte 5 */ +#define CAN_TDH1R_DATA6 ((uint32_t)0x00FF0000) /*!< Data byte 6 */ +#define CAN_TDH1R_DATA7 ((uint32_t)0xFF000000) /*!< Data byte 7 */ + +/******************* Bit definition for CAN_TI2R register *******************/ +#define CAN_TI2R_TXRQ ((uint32_t)0x00000001) /*!< Transmit Mailbox Request */ +#define CAN_TI2R_RTR ((uint32_t)0x00000002) /*!< Remote Transmission Request */ +#define CAN_TI2R_IDE ((uint32_t)0x00000004) /*!< Identifier Extension */ +#define CAN_TI2R_EXID ((uint32_t)0x001FFFF8) /*!< Extended identifier */ +#define CAN_TI2R_STID ((uint32_t)0xFFE00000) /*!< Standard Identifier or Extended Identifier */ + +/******************* Bit definition for CAN_TDT2R register ******************/ +#define CAN_TDT2R_DLC ((uint32_t)0x0000000F) /*!< Data Length Code */ +#define CAN_TDT2R_TGT ((uint32_t)0x00000100) /*!< Transmit Global Time */ +#define CAN_TDT2R_TIME ((uint32_t)0xFFFF0000) /*!< Message Time Stamp */ + +/******************* Bit definition for CAN_TDL2R register ******************/ +#define CAN_TDL2R_DATA0 ((uint32_t)0x000000FF) /*!< Data byte 0 */ +#define CAN_TDL2R_DATA1 ((uint32_t)0x0000FF00) /*!< Data byte 1 */ +#define CAN_TDL2R_DATA2 ((uint32_t)0x00FF0000) /*!< Data byte 2 */ +#define CAN_TDL2R_DATA3 ((uint32_t)0xFF000000) /*!< Data byte 3 */ + +/******************* Bit definition for CAN_TDH2R register ******************/ +#define CAN_TDH2R_DATA4 ((uint32_t)0x000000FF) /*!< Data byte 4 */ +#define CAN_TDH2R_DATA5 ((uint32_t)0x0000FF00) /*!< Data byte 5 */ +#define CAN_TDH2R_DATA6 ((uint32_t)0x00FF0000) /*!< Data byte 6 */ +#define CAN_TDH2R_DATA7 ((uint32_t)0xFF000000) /*!< Data byte 7 */ + +/******************* Bit definition for CAN_RI0R register *******************/ +#define CAN_RI0R_RTR ((uint32_t)0x00000002) /*!< Remote Transmission Request */ +#define CAN_RI0R_IDE ((uint32_t)0x00000004) /*!< Identifier Extension */ +#define CAN_RI0R_EXID ((uint32_t)0x001FFFF8) /*!< Extended Identifier */ +#define CAN_RI0R_STID ((uint32_t)0xFFE00000) /*!< Standard Identifier or Extended Identifier */ + +/******************* Bit definition for CAN_RDT0R register ******************/ +#define CAN_RDT0R_DLC ((uint32_t)0x0000000F) /*!< Data Length Code */ +#define CAN_RDT0R_FMI ((uint32_t)0x0000FF00) /*!< Filter Match Index */ +#define CAN_RDT0R_TIME ((uint32_t)0xFFFF0000) /*!< Message Time Stamp */ + +/******************* Bit definition for CAN_RDL0R register ******************/ +#define CAN_RDL0R_DATA0 ((uint32_t)0x000000FF) /*!< Data byte 0 */ +#define CAN_RDL0R_DATA1 ((uint32_t)0x0000FF00) /*!< Data byte 1 */ +#define CAN_RDL0R_DATA2 ((uint32_t)0x00FF0000) /*!< Data byte 2 */ +#define CAN_RDL0R_DATA3 ((uint32_t)0xFF000000) /*!< Data byte 3 */ + +/******************* Bit definition for CAN_RDH0R register ******************/ +#define CAN_RDH0R_DATA4 ((uint32_t)0x000000FF) /*!< Data byte 4 */ +#define CAN_RDH0R_DATA5 ((uint32_t)0x0000FF00) /*!< Data byte 5 */ +#define CAN_RDH0R_DATA6 ((uint32_t)0x00FF0000) /*!< Data byte 6 */ +#define CAN_RDH0R_DATA7 ((uint32_t)0xFF000000) /*!< Data byte 7 */ + +/******************* Bit definition for CAN_RI1R register *******************/ +#define CAN_RI1R_RTR ((uint32_t)0x00000002) /*!< Remote Transmission Request */ +#define CAN_RI1R_IDE ((uint32_t)0x00000004) /*!< Identifier Extension */ +#define CAN_RI1R_EXID ((uint32_t)0x001FFFF8) /*!< Extended identifier */ +#define CAN_RI1R_STID ((uint32_t)0xFFE00000) /*!< Standard Identifier or Extended Identifier */ + +/******************* Bit definition for CAN_RDT1R register ******************/ +#define CAN_RDT1R_DLC ((uint32_t)0x0000000F) /*!< Data Length Code */ +#define CAN_RDT1R_FMI ((uint32_t)0x0000FF00) /*!< Filter Match Index */ +#define CAN_RDT1R_TIME ((uint32_t)0xFFFF0000) /*!< Message Time Stamp */ + +/******************* Bit definition for CAN_RDL1R register ******************/ +#define CAN_RDL1R_DATA0 ((uint32_t)0x000000FF) /*!< Data byte 0 */ +#define CAN_RDL1R_DATA1 ((uint32_t)0x0000FF00) /*!< Data byte 1 */ +#define CAN_RDL1R_DATA2 ((uint32_t)0x00FF0000) /*!< Data byte 2 */ +#define CAN_RDL1R_DATA3 ((uint32_t)0xFF000000) /*!< Data byte 3 */ + +/******************* Bit definition for CAN_RDH1R register ******************/ +#define CAN_RDH1R_DATA4 ((uint32_t)0x000000FF) /*!< Data byte 4 */ +#define CAN_RDH1R_DATA5 ((uint32_t)0x0000FF00) /*!< Data byte 5 */ +#define CAN_RDH1R_DATA6 ((uint32_t)0x00FF0000) /*!< Data byte 6 */ +#define CAN_RDH1R_DATA7 ((uint32_t)0xFF000000) /*!< Data byte 7 */ + +/*!< CAN filter registers */ +/******************* Bit definition for CAN_FMR register ********************/ +#define CAN_FMR_FINIT ((uint8_t)0x01) /*!< Filter Init Mode */ + +/******************* Bit definition for CAN_FM1R register *******************/ +#define CAN_FM1R_FBM ((uint16_t)0x3FFF) /*!< Filter Mode */ +#define CAN_FM1R_FBM0 ((uint16_t)0x0001) /*!< Filter Init Mode bit 0 */ +#define CAN_FM1R_FBM1 ((uint16_t)0x0002) /*!< Filter Init Mode bit 1 */ +#define CAN_FM1R_FBM2 ((uint16_t)0x0004) /*!< Filter Init Mode bit 2 */ +#define CAN_FM1R_FBM3 ((uint16_t)0x0008) /*!< Filter Init Mode bit 3 */ +#define CAN_FM1R_FBM4 ((uint16_t)0x0010) /*!< Filter Init Mode bit 4 */ +#define CAN_FM1R_FBM5 ((uint16_t)0x0020) /*!< Filter Init Mode bit 5 */ +#define CAN_FM1R_FBM6 ((uint16_t)0x0040) /*!< Filter Init Mode bit 6 */ +#define CAN_FM1R_FBM7 ((uint16_t)0x0080) /*!< Filter Init Mode bit 7 */ +#define CAN_FM1R_FBM8 ((uint16_t)0x0100) /*!< Filter Init Mode bit 8 */ +#define CAN_FM1R_FBM9 ((uint16_t)0x0200) /*!< Filter Init Mode bit 9 */ +#define CAN_FM1R_FBM10 ((uint16_t)0x0400) /*!< Filter Init Mode bit 10 */ +#define CAN_FM1R_FBM11 ((uint16_t)0x0800) /*!< Filter Init Mode bit 11 */ +#define CAN_FM1R_FBM12 ((uint16_t)0x1000) /*!< Filter Init Mode bit 12 */ +#define CAN_FM1R_FBM13 ((uint16_t)0x2000) /*!< Filter Init Mode bit 13 */ + +/******************* Bit definition for CAN_FS1R register *******************/ +#define CAN_FS1R_FSC ((uint16_t)0x3FFF) /*!< Filter Scale Configuration */ +#define CAN_FS1R_FSC0 ((uint16_t)0x0001) /*!< Filter Scale Configuration bit 0 */ +#define CAN_FS1R_FSC1 ((uint16_t)0x0002) /*!< Filter Scale Configuration bit 1 */ +#define CAN_FS1R_FSC2 ((uint16_t)0x0004) /*!< Filter Scale Configuration bit 2 */ +#define CAN_FS1R_FSC3 ((uint16_t)0x0008) /*!< Filter Scale Configuration bit 3 */ +#define CAN_FS1R_FSC4 ((uint16_t)0x0010) /*!< Filter Scale Configuration bit 4 */ +#define CAN_FS1R_FSC5 ((uint16_t)0x0020) /*!< Filter Scale Configuration bit 5 */ +#define CAN_FS1R_FSC6 ((uint16_t)0x0040) /*!< Filter Scale Configuration bit 6 */ +#define CAN_FS1R_FSC7 ((uint16_t)0x0080) /*!< Filter Scale Configuration bit 7 */ +#define CAN_FS1R_FSC8 ((uint16_t)0x0100) /*!< Filter Scale Configuration bit 8 */ +#define CAN_FS1R_FSC9 ((uint16_t)0x0200) /*!< Filter Scale Configuration bit 9 */ +#define CAN_FS1R_FSC10 ((uint16_t)0x0400) /*!< Filter Scale Configuration bit 10 */ +#define CAN_FS1R_FSC11 ((uint16_t)0x0800) /*!< Filter Scale Configuration bit 11 */ +#define CAN_FS1R_FSC12 ((uint16_t)0x1000) /*!< Filter Scale Configuration bit 12 */ +#define CAN_FS1R_FSC13 ((uint16_t)0x2000) /*!< Filter Scale Configuration bit 13 */ + +/****************** Bit definition for CAN_FFA1R register *******************/ +#define CAN_FFA1R_FFA ((uint16_t)0x3FFF) /*!< Filter FIFO Assignment */ +#define CAN_FFA1R_FFA0 ((uint16_t)0x0001) /*!< Filter FIFO Assignment for Filter 0 */ +#define CAN_FFA1R_FFA1 ((uint16_t)0x0002) /*!< Filter FIFO Assignment for Filter 1 */ +#define CAN_FFA1R_FFA2 ((uint16_t)0x0004) /*!< Filter FIFO Assignment for Filter 2 */ +#define CAN_FFA1R_FFA3 ((uint16_t)0x0008) /*!< Filter FIFO Assignment for Filter 3 */ +#define CAN_FFA1R_FFA4 ((uint16_t)0x0010) /*!< Filter FIFO Assignment for Filter 4 */ +#define CAN_FFA1R_FFA5 ((uint16_t)0x0020) /*!< Filter FIFO Assignment for Filter 5 */ +#define CAN_FFA1R_FFA6 ((uint16_t)0x0040) /*!< Filter FIFO Assignment for Filter 6 */ +#define CAN_FFA1R_FFA7 ((uint16_t)0x0080) /*!< Filter FIFO Assignment for Filter 7 */ +#define CAN_FFA1R_FFA8 ((uint16_t)0x0100) /*!< Filter FIFO Assignment for Filter 8 */ +#define CAN_FFA1R_FFA9 ((uint16_t)0x0200) /*!< Filter FIFO Assignment for Filter 9 */ +#define CAN_FFA1R_FFA10 ((uint16_t)0x0400) /*!< Filter FIFO Assignment for Filter 10 */ +#define CAN_FFA1R_FFA11 ((uint16_t)0x0800) /*!< Filter FIFO Assignment for Filter 11 */ +#define CAN_FFA1R_FFA12 ((uint16_t)0x1000) /*!< Filter FIFO Assignment for Filter 12 */ +#define CAN_FFA1R_FFA13 ((uint16_t)0x2000) /*!< Filter FIFO Assignment for Filter 13 */ + +/******************* Bit definition for CAN_FA1R register *******************/ +#define CAN_FA1R_FACT ((uint16_t)0x3FFF) /*!< Filter Active */ +#define CAN_FA1R_FACT0 ((uint16_t)0x0001) /*!< Filter 0 Active */ +#define CAN_FA1R_FACT1 ((uint16_t)0x0002) /*!< Filter 1 Active */ +#define CAN_FA1R_FACT2 ((uint16_t)0x0004) /*!< Filter 2 Active */ +#define CAN_FA1R_FACT3 ((uint16_t)0x0008) /*!< Filter 3 Active */ +#define CAN_FA1R_FACT4 ((uint16_t)0x0010) /*!< Filter 4 Active */ +#define CAN_FA1R_FACT5 ((uint16_t)0x0020) /*!< Filter 5 Active */ +#define CAN_FA1R_FACT6 ((uint16_t)0x0040) /*!< Filter 6 Active */ +#define CAN_FA1R_FACT7 ((uint16_t)0x0080) /*!< Filter 7 Active */ +#define CAN_FA1R_FACT8 ((uint16_t)0x0100) /*!< Filter 8 Active */ +#define CAN_FA1R_FACT9 ((uint16_t)0x0200) /*!< Filter 9 Active */ +#define CAN_FA1R_FACT10 ((uint16_t)0x0400) /*!< Filter 10 Active */ +#define CAN_FA1R_FACT11 ((uint16_t)0x0800) /*!< Filter 11 Active */ +#define CAN_FA1R_FACT12 ((uint16_t)0x1000) /*!< Filter 12 Active */ +#define CAN_FA1R_FACT13 ((uint16_t)0x2000) /*!< Filter 13 Active */ + +/******************* Bit definition for CAN_F0R1 register *******************/ +#define CAN_F0R1_FB0 ((uint32_t)0x00000001) /*!< Filter bit 0 */ +#define CAN_F0R1_FB1 ((uint32_t)0x00000002) /*!< Filter bit 1 */ +#define CAN_F0R1_FB2 ((uint32_t)0x00000004) /*!< Filter bit 2 */ +#define CAN_F0R1_FB3 ((uint32_t)0x00000008) /*!< Filter bit 3 */ +#define CAN_F0R1_FB4 ((uint32_t)0x00000010) /*!< Filter bit 4 */ +#define CAN_F0R1_FB5 ((uint32_t)0x00000020) /*!< Filter bit 5 */ +#define CAN_F0R1_FB6 ((uint32_t)0x00000040) /*!< Filter bit 6 */ +#define CAN_F0R1_FB7 ((uint32_t)0x00000080) /*!< Filter bit 7 */ +#define CAN_F0R1_FB8 ((uint32_t)0x00000100) /*!< Filter bit 8 */ +#define CAN_F0R1_FB9 ((uint32_t)0x00000200) /*!< Filter bit 9 */ +#define CAN_F0R1_FB10 ((uint32_t)0x00000400) /*!< Filter bit 10 */ +#define CAN_F0R1_FB11 ((uint32_t)0x00000800) /*!< Filter bit 11 */ +#define CAN_F0R1_FB12 ((uint32_t)0x00001000) /*!< Filter bit 12 */ +#define CAN_F0R1_FB13 ((uint32_t)0x00002000) /*!< Filter bit 13 */ +#define CAN_F0R1_FB14 ((uint32_t)0x00004000) /*!< Filter bit 14 */ +#define CAN_F0R1_FB15 ((uint32_t)0x00008000) /*!< Filter bit 15 */ +#define CAN_F0R1_FB16 ((uint32_t)0x00010000) /*!< Filter bit 16 */ +#define CAN_F0R1_FB17 ((uint32_t)0x00020000) /*!< Filter bit 17 */ +#define CAN_F0R1_FB18 ((uint32_t)0x00040000) /*!< Filter bit 18 */ +#define CAN_F0R1_FB19 ((uint32_t)0x00080000) /*!< Filter bit 19 */ +#define CAN_F0R1_FB20 ((uint32_t)0x00100000) /*!< Filter bit 20 */ +#define CAN_F0R1_FB21 ((uint32_t)0x00200000) /*!< Filter bit 21 */ +#define CAN_F0R1_FB22 ((uint32_t)0x00400000) /*!< Filter bit 22 */ +#define CAN_F0R1_FB23 ((uint32_t)0x00800000) /*!< Filter bit 23 */ +#define CAN_F0R1_FB24 ((uint32_t)0x01000000) /*!< Filter bit 24 */ +#define CAN_F0R1_FB25 ((uint32_t)0x02000000) /*!< Filter bit 25 */ +#define CAN_F0R1_FB26 ((uint32_t)0x04000000) /*!< Filter bit 26 */ +#define CAN_F0R1_FB27 ((uint32_t)0x08000000) /*!< Filter bit 27 */ +#define CAN_F0R1_FB28 ((uint32_t)0x10000000) /*!< Filter bit 28 */ +#define CAN_F0R1_FB29 ((uint32_t)0x20000000) /*!< Filter bit 29 */ +#define CAN_F0R1_FB30 ((uint32_t)0x40000000) /*!< Filter bit 30 */ +#define CAN_F0R1_FB31 ((uint32_t)0x80000000) /*!< Filter bit 31 */ + +/******************* Bit definition for CAN_F1R1 register *******************/ +#define CAN_F1R1_FB0 ((uint32_t)0x00000001) /*!< Filter bit 0 */ +#define CAN_F1R1_FB1 ((uint32_t)0x00000002) /*!< Filter bit 1 */ +#define CAN_F1R1_FB2 ((uint32_t)0x00000004) /*!< Filter bit 2 */ +#define CAN_F1R1_FB3 ((uint32_t)0x00000008) /*!< Filter bit 3 */ +#define CAN_F1R1_FB4 ((uint32_t)0x00000010) /*!< Filter bit 4 */ +#define CAN_F1R1_FB5 ((uint32_t)0x00000020) /*!< Filter bit 5 */ +#define CAN_F1R1_FB6 ((uint32_t)0x00000040) /*!< Filter bit 6 */ +#define CAN_F1R1_FB7 ((uint32_t)0x00000080) /*!< Filter bit 7 */ +#define CAN_F1R1_FB8 ((uint32_t)0x00000100) /*!< Filter bit 8 */ +#define CAN_F1R1_FB9 ((uint32_t)0x00000200) /*!< Filter bit 9 */ +#define CAN_F1R1_FB10 ((uint32_t)0x00000400) /*!< Filter bit 10 */ +#define CAN_F1R1_FB11 ((uint32_t)0x00000800) /*!< Filter bit 11 */ +#define CAN_F1R1_FB12 ((uint32_t)0x00001000) /*!< Filter bit 12 */ +#define CAN_F1R1_FB13 ((uint32_t)0x00002000) /*!< Filter bit 13 */ +#define CAN_F1R1_FB14 ((uint32_t)0x00004000) /*!< Filter bit 14 */ +#define CAN_F1R1_FB15 ((uint32_t)0x00008000) /*!< Filter bit 15 */ +#define CAN_F1R1_FB16 ((uint32_t)0x00010000) /*!< Filter bit 16 */ +#define CAN_F1R1_FB17 ((uint32_t)0x00020000) /*!< Filter bit 17 */ +#define CAN_F1R1_FB18 ((uint32_t)0x00040000) /*!< Filter bit 18 */ +#define CAN_F1R1_FB19 ((uint32_t)0x00080000) /*!< Filter bit 19 */ +#define CAN_F1R1_FB20 ((uint32_t)0x00100000) /*!< Filter bit 20 */ +#define CAN_F1R1_FB21 ((uint32_t)0x00200000) /*!< Filter bit 21 */ +#define CAN_F1R1_FB22 ((uint32_t)0x00400000) /*!< Filter bit 22 */ +#define CAN_F1R1_FB23 ((uint32_t)0x00800000) /*!< Filter bit 23 */ +#define CAN_F1R1_FB24 ((uint32_t)0x01000000) /*!< Filter bit 24 */ +#define CAN_F1R1_FB25 ((uint32_t)0x02000000) /*!< Filter bit 25 */ +#define CAN_F1R1_FB26 ((uint32_t)0x04000000) /*!< Filter bit 26 */ +#define CAN_F1R1_FB27 ((uint32_t)0x08000000) /*!< Filter bit 27 */ +#define CAN_F1R1_FB28 ((uint32_t)0x10000000) /*!< Filter bit 28 */ +#define CAN_F1R1_FB29 ((uint32_t)0x20000000) /*!< Filter bit 29 */ +#define CAN_F1R1_FB30 ((uint32_t)0x40000000) /*!< Filter bit 30 */ +#define CAN_F1R1_FB31 ((uint32_t)0x80000000) /*!< Filter bit 31 */ + +/******************* Bit definition for CAN_F2R1 register *******************/ +#define CAN_F2R1_FB0 ((uint32_t)0x00000001) /*!< Filter bit 0 */ +#define CAN_F2R1_FB1 ((uint32_t)0x00000002) /*!< Filter bit 1 */ +#define CAN_F2R1_FB2 ((uint32_t)0x00000004) /*!< Filter bit 2 */ +#define CAN_F2R1_FB3 ((uint32_t)0x00000008) /*!< Filter bit 3 */ +#define CAN_F2R1_FB4 ((uint32_t)0x00000010) /*!< Filter bit 4 */ +#define CAN_F2R1_FB5 ((uint32_t)0x00000020) /*!< Filter bit 5 */ +#define CAN_F2R1_FB6 ((uint32_t)0x00000040) /*!< Filter bit 6 */ +#define CAN_F2R1_FB7 ((uint32_t)0x00000080) /*!< Filter bit 7 */ +#define CAN_F2R1_FB8 ((uint32_t)0x00000100) /*!< Filter bit 8 */ +#define CAN_F2R1_FB9 ((uint32_t)0x00000200) /*!< Filter bit 9 */ +#define CAN_F2R1_FB10 ((uint32_t)0x00000400) /*!< Filter bit 10 */ +#define CAN_F2R1_FB11 ((uint32_t)0x00000800) /*!< Filter bit 11 */ +#define CAN_F2R1_FB12 ((uint32_t)0x00001000) /*!< Filter bit 12 */ +#define CAN_F2R1_FB13 ((uint32_t)0x00002000) /*!< Filter bit 13 */ +#define CAN_F2R1_FB14 ((uint32_t)0x00004000) /*!< Filter bit 14 */ +#define CAN_F2R1_FB15 ((uint32_t)0x00008000) /*!< Filter bit 15 */ +#define CAN_F2R1_FB16 ((uint32_t)0x00010000) /*!< Filter bit 16 */ +#define CAN_F2R1_FB17 ((uint32_t)0x00020000) /*!< Filter bit 17 */ +#define CAN_F2R1_FB18 ((uint32_t)0x00040000) /*!< Filter bit 18 */ +#define CAN_F2R1_FB19 ((uint32_t)0x00080000) /*!< Filter bit 19 */ +#define CAN_F2R1_FB20 ((uint32_t)0x00100000) /*!< Filter bit 20 */ +#define CAN_F2R1_FB21 ((uint32_t)0x00200000) /*!< Filter bit 21 */ +#define CAN_F2R1_FB22 ((uint32_t)0x00400000) /*!< Filter bit 22 */ +#define CAN_F2R1_FB23 ((uint32_t)0x00800000) /*!< Filter bit 23 */ +#define CAN_F2R1_FB24 ((uint32_t)0x01000000) /*!< Filter bit 24 */ +#define CAN_F2R1_FB25 ((uint32_t)0x02000000) /*!< Filter bit 25 */ +#define CAN_F2R1_FB26 ((uint32_t)0x04000000) /*!< Filter bit 26 */ +#define CAN_F2R1_FB27 ((uint32_t)0x08000000) /*!< Filter bit 27 */ +#define CAN_F2R1_FB28 ((uint32_t)0x10000000) /*!< Filter bit 28 */ +#define CAN_F2R1_FB29 ((uint32_t)0x20000000) /*!< Filter bit 29 */ +#define CAN_F2R1_FB30 ((uint32_t)0x40000000) /*!< Filter bit 30 */ +#define CAN_F2R1_FB31 ((uint32_t)0x80000000) /*!< Filter bit 31 */ + +/******************* Bit definition for CAN_F3R1 register *******************/ +#define CAN_F3R1_FB0 ((uint32_t)0x00000001) /*!< Filter bit 0 */ +#define CAN_F3R1_FB1 ((uint32_t)0x00000002) /*!< Filter bit 1 */ +#define CAN_F3R1_FB2 ((uint32_t)0x00000004) /*!< Filter bit 2 */ +#define CAN_F3R1_FB3 ((uint32_t)0x00000008) /*!< Filter bit 3 */ +#define CAN_F3R1_FB4 ((uint32_t)0x00000010) /*!< Filter bit 4 */ +#define CAN_F3R1_FB5 ((uint32_t)0x00000020) /*!< Filter bit 5 */ +#define CAN_F3R1_FB6 ((uint32_t)0x00000040) /*!< Filter bit 6 */ +#define CAN_F3R1_FB7 ((uint32_t)0x00000080) /*!< Filter bit 7 */ +#define CAN_F3R1_FB8 ((uint32_t)0x00000100) /*!< Filter bit 8 */ +#define CAN_F3R1_FB9 ((uint32_t)0x00000200) /*!< Filter bit 9 */ +#define CAN_F3R1_FB10 ((uint32_t)0x00000400) /*!< Filter bit 10 */ +#define CAN_F3R1_FB11 ((uint32_t)0x00000800) /*!< Filter bit 11 */ +#define CAN_F3R1_FB12 ((uint32_t)0x00001000) /*!< Filter bit 12 */ +#define CAN_F3R1_FB13 ((uint32_t)0x00002000) /*!< Filter bit 13 */ +#define CAN_F3R1_FB14 ((uint32_t)0x00004000) /*!< Filter bit 14 */ +#define CAN_F3R1_FB15 ((uint32_t)0x00008000) /*!< Filter bit 15 */ +#define CAN_F3R1_FB16 ((uint32_t)0x00010000) /*!< Filter bit 16 */ +#define CAN_F3R1_FB17 ((uint32_t)0x00020000) /*!< Filter bit 17 */ +#define CAN_F3R1_FB18 ((uint32_t)0x00040000) /*!< Filter bit 18 */ +#define CAN_F3R1_FB19 ((uint32_t)0x00080000) /*!< Filter bit 19 */ +#define CAN_F3R1_FB20 ((uint32_t)0x00100000) /*!< Filter bit 20 */ +#define CAN_F3R1_FB21 ((uint32_t)0x00200000) /*!< Filter bit 21 */ +#define CAN_F3R1_FB22 ((uint32_t)0x00400000) /*!< Filter bit 22 */ +#define CAN_F3R1_FB23 ((uint32_t)0x00800000) /*!< Filter bit 23 */ +#define CAN_F3R1_FB24 ((uint32_t)0x01000000) /*!< Filter bit 24 */ +#define CAN_F3R1_FB25 ((uint32_t)0x02000000) /*!< Filter bit 25 */ +#define CAN_F3R1_FB26 ((uint32_t)0x04000000) /*!< Filter bit 26 */ +#define CAN_F3R1_FB27 ((uint32_t)0x08000000) /*!< Filter bit 27 */ +#define CAN_F3R1_FB28 ((uint32_t)0x10000000) /*!< Filter bit 28 */ +#define CAN_F3R1_FB29 ((uint32_t)0x20000000) /*!< Filter bit 29 */ +#define CAN_F3R1_FB30 ((uint32_t)0x40000000) /*!< Filter bit 30 */ +#define CAN_F3R1_FB31 ((uint32_t)0x80000000) /*!< Filter bit 31 */ + +/******************* Bit definition for CAN_F4R1 register *******************/ +#define CAN_F4R1_FB0 ((uint32_t)0x00000001) /*!< Filter bit 0 */ +#define CAN_F4R1_FB1 ((uint32_t)0x00000002) /*!< Filter bit 1 */ +#define CAN_F4R1_FB2 ((uint32_t)0x00000004) /*!< Filter bit 2 */ +#define CAN_F4R1_FB3 ((uint32_t)0x00000008) /*!< Filter bit 3 */ +#define CAN_F4R1_FB4 ((uint32_t)0x00000010) /*!< Filter bit 4 */ +#define CAN_F4R1_FB5 ((uint32_t)0x00000020) /*!< Filter bit 5 */ +#define CAN_F4R1_FB6 ((uint32_t)0x00000040) /*!< Filter bit 6 */ +#define CAN_F4R1_FB7 ((uint32_t)0x00000080) /*!< Filter bit 7 */ +#define CAN_F4R1_FB8 ((uint32_t)0x00000100) /*!< Filter bit 8 */ +#define CAN_F4R1_FB9 ((uint32_t)0x00000200) /*!< Filter bit 9 */ +#define CAN_F4R1_FB10 ((uint32_t)0x00000400) /*!< Filter bit 10 */ +#define CAN_F4R1_FB11 ((uint32_t)0x00000800) /*!< Filter bit 11 */ +#define CAN_F4R1_FB12 ((uint32_t)0x00001000) /*!< Filter bit 12 */ +#define CAN_F4R1_FB13 ((uint32_t)0x00002000) /*!< Filter bit 13 */ +#define CAN_F4R1_FB14 ((uint32_t)0x00004000) /*!< Filter bit 14 */ +#define CAN_F4R1_FB15 ((uint32_t)0x00008000) /*!< Filter bit 15 */ +#define CAN_F4R1_FB16 ((uint32_t)0x00010000) /*!< Filter bit 16 */ +#define CAN_F4R1_FB17 ((uint32_t)0x00020000) /*!< Filter bit 17 */ +#define CAN_F4R1_FB18 ((uint32_t)0x00040000) /*!< Filter bit 18 */ +#define CAN_F4R1_FB19 ((uint32_t)0x00080000) /*!< Filter bit 19 */ +#define CAN_F4R1_FB20 ((uint32_t)0x00100000) /*!< Filter bit 20 */ +#define CAN_F4R1_FB21 ((uint32_t)0x00200000) /*!< Filter bit 21 */ +#define CAN_F4R1_FB22 ((uint32_t)0x00400000) /*!< Filter bit 22 */ +#define CAN_F4R1_FB23 ((uint32_t)0x00800000) /*!< Filter bit 23 */ +#define CAN_F4R1_FB24 ((uint32_t)0x01000000) /*!< Filter bit 24 */ +#define CAN_F4R1_FB25 ((uint32_t)0x02000000) /*!< Filter bit 25 */ +#define CAN_F4R1_FB26 ((uint32_t)0x04000000) /*!< Filter bit 26 */ +#define CAN_F4R1_FB27 ((uint32_t)0x08000000) /*!< Filter bit 27 */ +#define CAN_F4R1_FB28 ((uint32_t)0x10000000) /*!< Filter bit 28 */ +#define CAN_F4R1_FB29 ((uint32_t)0x20000000) /*!< Filter bit 29 */ +#define CAN_F4R1_FB30 ((uint32_t)0x40000000) /*!< Filter bit 30 */ +#define CAN_F4R1_FB31 ((uint32_t)0x80000000) /*!< Filter bit 31 */ + +/******************* Bit definition for CAN_F5R1 register *******************/ +#define CAN_F5R1_FB0 ((uint32_t)0x00000001) /*!< Filter bit 0 */ +#define CAN_F5R1_FB1 ((uint32_t)0x00000002) /*!< Filter bit 1 */ +#define CAN_F5R1_FB2 ((uint32_t)0x00000004) /*!< Filter bit 2 */ +#define CAN_F5R1_FB3 ((uint32_t)0x00000008) /*!< Filter bit 3 */ +#define CAN_F5R1_FB4 ((uint32_t)0x00000010) /*!< Filter bit 4 */ +#define CAN_F5R1_FB5 ((uint32_t)0x00000020) /*!< Filter bit 5 */ +#define CAN_F5R1_FB6 ((uint32_t)0x00000040) /*!< Filter bit 6 */ +#define CAN_F5R1_FB7 ((uint32_t)0x00000080) /*!< Filter bit 7 */ +#define CAN_F5R1_FB8 ((uint32_t)0x00000100) /*!< Filter bit 8 */ +#define CAN_F5R1_FB9 ((uint32_t)0x00000200) /*!< Filter bit 9 */ +#define CAN_F5R1_FB10 ((uint32_t)0x00000400) /*!< Filter bit 10 */ +#define CAN_F5R1_FB11 ((uint32_t)0x00000800) /*!< Filter bit 11 */ +#define CAN_F5R1_FB12 ((uint32_t)0x00001000) /*!< Filter bit 12 */ +#define CAN_F5R1_FB13 ((uint32_t)0x00002000) /*!< Filter bit 13 */ +#define CAN_F5R1_FB14 ((uint32_t)0x00004000) /*!< Filter bit 14 */ +#define CAN_F5R1_FB15 ((uint32_t)0x00008000) /*!< Filter bit 15 */ +#define CAN_F5R1_FB16 ((uint32_t)0x00010000) /*!< Filter bit 16 */ +#define CAN_F5R1_FB17 ((uint32_t)0x00020000) /*!< Filter bit 17 */ +#define CAN_F5R1_FB18 ((uint32_t)0x00040000) /*!< Filter bit 18 */ +#define CAN_F5R1_FB19 ((uint32_t)0x00080000) /*!< Filter bit 19 */ +#define CAN_F5R1_FB20 ((uint32_t)0x00100000) /*!< Filter bit 20 */ +#define CAN_F5R1_FB21 ((uint32_t)0x00200000) /*!< Filter bit 21 */ +#define CAN_F5R1_FB22 ((uint32_t)0x00400000) /*!< Filter bit 22 */ +#define CAN_F5R1_FB23 ((uint32_t)0x00800000) /*!< Filter bit 23 */ +#define CAN_F5R1_FB24 ((uint32_t)0x01000000) /*!< Filter bit 24 */ +#define CAN_F5R1_FB25 ((uint32_t)0x02000000) /*!< Filter bit 25 */ +#define CAN_F5R1_FB26 ((uint32_t)0x04000000) /*!< Filter bit 26 */ +#define CAN_F5R1_FB27 ((uint32_t)0x08000000) /*!< Filter bit 27 */ +#define CAN_F5R1_FB28 ((uint32_t)0x10000000) /*!< Filter bit 28 */ +#define CAN_F5R1_FB29 ((uint32_t)0x20000000) /*!< Filter bit 29 */ +#define CAN_F5R1_FB30 ((uint32_t)0x40000000) /*!< Filter bit 30 */ +#define CAN_F5R1_FB31 ((uint32_t)0x80000000) /*!< Filter bit 31 */ + +/******************* Bit definition for CAN_F6R1 register *******************/ +#define CAN_F6R1_FB0 ((uint32_t)0x00000001) /*!< Filter bit 0 */ +#define CAN_F6R1_FB1 ((uint32_t)0x00000002) /*!< Filter bit 1 */ +#define CAN_F6R1_FB2 ((uint32_t)0x00000004) /*!< Filter bit 2 */ +#define CAN_F6R1_FB3 ((uint32_t)0x00000008) /*!< Filter bit 3 */ +#define CAN_F6R1_FB4 ((uint32_t)0x00000010) /*!< Filter bit 4 */ +#define CAN_F6R1_FB5 ((uint32_t)0x00000020) /*!< Filter bit 5 */ +#define CAN_F6R1_FB6 ((uint32_t)0x00000040) /*!< Filter bit 6 */ +#define CAN_F6R1_FB7 ((uint32_t)0x00000080) /*!< Filter bit 7 */ +#define CAN_F6R1_FB8 ((uint32_t)0x00000100) /*!< Filter bit 8 */ +#define CAN_F6R1_FB9 ((uint32_t)0x00000200) /*!< Filter bit 9 */ +#define CAN_F6R1_FB10 ((uint32_t)0x00000400) /*!< Filter bit 10 */ +#define CAN_F6R1_FB11 ((uint32_t)0x00000800) /*!< Filter bit 11 */ +#define CAN_F6R1_FB12 ((uint32_t)0x00001000) /*!< Filter bit 12 */ +#define CAN_F6R1_FB13 ((uint32_t)0x00002000) /*!< Filter bit 13 */ +#define CAN_F6R1_FB14 ((uint32_t)0x00004000) /*!< Filter bit 14 */ +#define CAN_F6R1_FB15 ((uint32_t)0x00008000) /*!< Filter bit 15 */ +#define CAN_F6R1_FB16 ((uint32_t)0x00010000) /*!< Filter bit 16 */ +#define CAN_F6R1_FB17 ((uint32_t)0x00020000) /*!< Filter bit 17 */ +#define CAN_F6R1_FB18 ((uint32_t)0x00040000) /*!< Filter bit 18 */ +#define CAN_F6R1_FB19 ((uint32_t)0x00080000) /*!< Filter bit 19 */ +#define CAN_F6R1_FB20 ((uint32_t)0x00100000) /*!< Filter bit 20 */ +#define CAN_F6R1_FB21 ((uint32_t)0x00200000) /*!< Filter bit 21 */ +#define CAN_F6R1_FB22 ((uint32_t)0x00400000) /*!< Filter bit 22 */ +#define CAN_F6R1_FB23 ((uint32_t)0x00800000) /*!< Filter bit 23 */ +#define CAN_F6R1_FB24 ((uint32_t)0x01000000) /*!< Filter bit 24 */ +#define CAN_F6R1_FB25 ((uint32_t)0x02000000) /*!< Filter bit 25 */ +#define CAN_F6R1_FB26 ((uint32_t)0x04000000) /*!< Filter bit 26 */ +#define CAN_F6R1_FB27 ((uint32_t)0x08000000) /*!< Filter bit 27 */ +#define CAN_F6R1_FB28 ((uint32_t)0x10000000) /*!< Filter bit 28 */ +#define CAN_F6R1_FB29 ((uint32_t)0x20000000) /*!< Filter bit 29 */ +#define CAN_F6R1_FB30 ((uint32_t)0x40000000) /*!< Filter bit 30 */ +#define CAN_F6R1_FB31 ((uint32_t)0x80000000) /*!< Filter bit 31 */ + +/******************* Bit definition for CAN_F7R1 register *******************/ +#define CAN_F7R1_FB0 ((uint32_t)0x00000001) /*!< Filter bit 0 */ +#define CAN_F7R1_FB1 ((uint32_t)0x00000002) /*!< Filter bit 1 */ +#define CAN_F7R1_FB2 ((uint32_t)0x00000004) /*!< Filter bit 2 */ +#define CAN_F7R1_FB3 ((uint32_t)0x00000008) /*!< Filter bit 3 */ +#define CAN_F7R1_FB4 ((uint32_t)0x00000010) /*!< Filter bit 4 */ +#define CAN_F7R1_FB5 ((uint32_t)0x00000020) /*!< Filter bit 5 */ +#define CAN_F7R1_FB6 ((uint32_t)0x00000040) /*!< Filter bit 6 */ +#define CAN_F7R1_FB7 ((uint32_t)0x00000080) /*!< Filter bit 7 */ +#define CAN_F7R1_FB8 ((uint32_t)0x00000100) /*!< Filter bit 8 */ +#define CAN_F7R1_FB9 ((uint32_t)0x00000200) /*!< Filter bit 9 */ +#define CAN_F7R1_FB10 ((uint32_t)0x00000400) /*!< Filter bit 10 */ +#define CAN_F7R1_FB11 ((uint32_t)0x00000800) /*!< Filter bit 11 */ +#define CAN_F7R1_FB12 ((uint32_t)0x00001000) /*!< Filter bit 12 */ +#define CAN_F7R1_FB13 ((uint32_t)0x00002000) /*!< Filter bit 13 */ +#define CAN_F7R1_FB14 ((uint32_t)0x00004000) /*!< Filter bit 14 */ +#define CAN_F7R1_FB15 ((uint32_t)0x00008000) /*!< Filter bit 15 */ +#define CAN_F7R1_FB16 ((uint32_t)0x00010000) /*!< Filter bit 16 */ +#define CAN_F7R1_FB17 ((uint32_t)0x00020000) /*!< Filter bit 17 */ +#define CAN_F7R1_FB18 ((uint32_t)0x00040000) /*!< Filter bit 18 */ +#define CAN_F7R1_FB19 ((uint32_t)0x00080000) /*!< Filter bit 19 */ +#define CAN_F7R1_FB20 ((uint32_t)0x00100000) /*!< Filter bit 20 */ +#define CAN_F7R1_FB21 ((uint32_t)0x00200000) /*!< Filter bit 21 */ +#define CAN_F7R1_FB22 ((uint32_t)0x00400000) /*!< Filter bit 22 */ +#define CAN_F7R1_FB23 ((uint32_t)0x00800000) /*!< Filter bit 23 */ +#define CAN_F7R1_FB24 ((uint32_t)0x01000000) /*!< Filter bit 24 */ +#define CAN_F7R1_FB25 ((uint32_t)0x02000000) /*!< Filter bit 25 */ +#define CAN_F7R1_FB26 ((uint32_t)0x04000000) /*!< Filter bit 26 */ +#define CAN_F7R1_FB27 ((uint32_t)0x08000000) /*!< Filter bit 27 */ +#define CAN_F7R1_FB28 ((uint32_t)0x10000000) /*!< Filter bit 28 */ +#define CAN_F7R1_FB29 ((uint32_t)0x20000000) /*!< Filter bit 29 */ +#define CAN_F7R1_FB30 ((uint32_t)0x40000000) /*!< Filter bit 30 */ +#define CAN_F7R1_FB31 ((uint32_t)0x80000000) /*!< Filter bit 31 */ + +/******************* Bit definition for CAN_F8R1 register *******************/ +#define CAN_F8R1_FB0 ((uint32_t)0x00000001) /*!< Filter bit 0 */ +#define CAN_F8R1_FB1 ((uint32_t)0x00000002) /*!< Filter bit 1 */ +#define CAN_F8R1_FB2 ((uint32_t)0x00000004) /*!< Filter bit 2 */ +#define CAN_F8R1_FB3 ((uint32_t)0x00000008) /*!< Filter bit 3 */ +#define CAN_F8R1_FB4 ((uint32_t)0x00000010) /*!< Filter bit 4 */ +#define CAN_F8R1_FB5 ((uint32_t)0x00000020) /*!< Filter bit 5 */ +#define CAN_F8R1_FB6 ((uint32_t)0x00000040) /*!< Filter bit 6 */ +#define CAN_F8R1_FB7 ((uint32_t)0x00000080) /*!< Filter bit 7 */ +#define CAN_F8R1_FB8 ((uint32_t)0x00000100) /*!< Filter bit 8 */ +#define CAN_F8R1_FB9 ((uint32_t)0x00000200) /*!< Filter bit 9 */ +#define CAN_F8R1_FB10 ((uint32_t)0x00000400) /*!< Filter bit 10 */ +#define CAN_F8R1_FB11 ((uint32_t)0x00000800) /*!< Filter bit 11 */ +#define CAN_F8R1_FB12 ((uint32_t)0x00001000) /*!< Filter bit 12 */ +#define CAN_F8R1_FB13 ((uint32_t)0x00002000) /*!< Filter bit 13 */ +#define CAN_F8R1_FB14 ((uint32_t)0x00004000) /*!< Filter bit 14 */ +#define CAN_F8R1_FB15 ((uint32_t)0x00008000) /*!< Filter bit 15 */ +#define CAN_F8R1_FB16 ((uint32_t)0x00010000) /*!< Filter bit 16 */ +#define CAN_F8R1_FB17 ((uint32_t)0x00020000) /*!< Filter bit 17 */ +#define CAN_F8R1_FB18 ((uint32_t)0x00040000) /*!< Filter bit 18 */ +#define CAN_F8R1_FB19 ((uint32_t)0x00080000) /*!< Filter bit 19 */ +#define CAN_F8R1_FB20 ((uint32_t)0x00100000) /*!< Filter bit 20 */ +#define CAN_F8R1_FB21 ((uint32_t)0x00200000) /*!< Filter bit 21 */ +#define CAN_F8R1_FB22 ((uint32_t)0x00400000) /*!< Filter bit 22 */ +#define CAN_F8R1_FB23 ((uint32_t)0x00800000) /*!< Filter bit 23 */ +#define CAN_F8R1_FB24 ((uint32_t)0x01000000) /*!< Filter bit 24 */ +#define CAN_F8R1_FB25 ((uint32_t)0x02000000) /*!< Filter bit 25 */ +#define CAN_F8R1_FB26 ((uint32_t)0x04000000) /*!< Filter bit 26 */ +#define CAN_F8R1_FB27 ((uint32_t)0x08000000) /*!< Filter bit 27 */ +#define CAN_F8R1_FB28 ((uint32_t)0x10000000) /*!< Filter bit 28 */ +#define CAN_F8R1_FB29 ((uint32_t)0x20000000) /*!< Filter bit 29 */ +#define CAN_F8R1_FB30 ((uint32_t)0x40000000) /*!< Filter bit 30 */ +#define CAN_F8R1_FB31 ((uint32_t)0x80000000) /*!< Filter bit 31 */ + +/******************* Bit definition for CAN_F9R1 register *******************/ +#define CAN_F9R1_FB0 ((uint32_t)0x00000001) /*!< Filter bit 0 */ +#define CAN_F9R1_FB1 ((uint32_t)0x00000002) /*!< Filter bit 1 */ +#define CAN_F9R1_FB2 ((uint32_t)0x00000004) /*!< Filter bit 2 */ +#define CAN_F9R1_FB3 ((uint32_t)0x00000008) /*!< Filter bit 3 */ +#define CAN_F9R1_FB4 ((uint32_t)0x00000010) /*!< Filter bit 4 */ +#define CAN_F9R1_FB5 ((uint32_t)0x00000020) /*!< Filter bit 5 */ +#define CAN_F9R1_FB6 ((uint32_t)0x00000040) /*!< Filter bit 6 */ +#define CAN_F9R1_FB7 ((uint32_t)0x00000080) /*!< Filter bit 7 */ +#define CAN_F9R1_FB8 ((uint32_t)0x00000100) /*!< Filter bit 8 */ +#define CAN_F9R1_FB9 ((uint32_t)0x00000200) /*!< Filter bit 9 */ +#define CAN_F9R1_FB10 ((uint32_t)0x00000400) /*!< Filter bit 10 */ +#define CAN_F9R1_FB11 ((uint32_t)0x00000800) /*!< Filter bit 11 */ +#define CAN_F9R1_FB12 ((uint32_t)0x00001000) /*!< Filter bit 12 */ +#define CAN_F9R1_FB13 ((uint32_t)0x00002000) /*!< Filter bit 13 */ +#define CAN_F9R1_FB14 ((uint32_t)0x00004000) /*!< Filter bit 14 */ +#define CAN_F9R1_FB15 ((uint32_t)0x00008000) /*!< Filter bit 15 */ +#define CAN_F9R1_FB16 ((uint32_t)0x00010000) /*!< Filter bit 16 */ +#define CAN_F9R1_FB17 ((uint32_t)0x00020000) /*!< Filter bit 17 */ +#define CAN_F9R1_FB18 ((uint32_t)0x00040000) /*!< Filter bit 18 */ +#define CAN_F9R1_FB19 ((uint32_t)0x00080000) /*!< Filter bit 19 */ +#define CAN_F9R1_FB20 ((uint32_t)0x00100000) /*!< Filter bit 20 */ +#define CAN_F9R1_FB21 ((uint32_t)0x00200000) /*!< Filter bit 21 */ +#define CAN_F9R1_FB22 ((uint32_t)0x00400000) /*!< Filter bit 22 */ +#define CAN_F9R1_FB23 ((uint32_t)0x00800000) /*!< Filter bit 23 */ +#define CAN_F9R1_FB24 ((uint32_t)0x01000000) /*!< Filter bit 24 */ +#define CAN_F9R1_FB25 ((uint32_t)0x02000000) /*!< Filter bit 25 */ +#define CAN_F9R1_FB26 ((uint32_t)0x04000000) /*!< Filter bit 26 */ +#define CAN_F9R1_FB27 ((uint32_t)0x08000000) /*!< Filter bit 27 */ +#define CAN_F9R1_FB28 ((uint32_t)0x10000000) /*!< Filter bit 28 */ +#define CAN_F9R1_FB29 ((uint32_t)0x20000000) /*!< Filter bit 29 */ +#define CAN_F9R1_FB30 ((uint32_t)0x40000000) /*!< Filter bit 30 */ +#define CAN_F9R1_FB31 ((uint32_t)0x80000000) /*!< Filter bit 31 */ + +/******************* Bit definition for CAN_F10R1 register ******************/ +#define CAN_F10R1_FB0 ((uint32_t)0x00000001) /*!< Filter bit 0 */ +#define CAN_F10R1_FB1 ((uint32_t)0x00000002) /*!< Filter bit 1 */ +#define CAN_F10R1_FB2 ((uint32_t)0x00000004) /*!< Filter bit 2 */ +#define CAN_F10R1_FB3 ((uint32_t)0x00000008) /*!< Filter bit 3 */ +#define CAN_F10R1_FB4 ((uint32_t)0x00000010) /*!< Filter bit 4 */ +#define CAN_F10R1_FB5 ((uint32_t)0x00000020) /*!< Filter bit 5 */ +#define CAN_F10R1_FB6 ((uint32_t)0x00000040) /*!< Filter bit 6 */ +#define CAN_F10R1_FB7 ((uint32_t)0x00000080) /*!< Filter bit 7 */ +#define CAN_F10R1_FB8 ((uint32_t)0x00000100) /*!< Filter bit 8 */ +#define CAN_F10R1_FB9 ((uint32_t)0x00000200) /*!< Filter bit 9 */ +#define CAN_F10R1_FB10 ((uint32_t)0x00000400) /*!< Filter bit 10 */ +#define CAN_F10R1_FB11 ((uint32_t)0x00000800) /*!< Filter bit 11 */ +#define CAN_F10R1_FB12 ((uint32_t)0x00001000) /*!< Filter bit 12 */ +#define CAN_F10R1_FB13 ((uint32_t)0x00002000) /*!< Filter bit 13 */ +#define CAN_F10R1_FB14 ((uint32_t)0x00004000) /*!< Filter bit 14 */ +#define CAN_F10R1_FB15 ((uint32_t)0x00008000) /*!< Filter bit 15 */ +#define CAN_F10R1_FB16 ((uint32_t)0x00010000) /*!< Filter bit 16 */ +#define CAN_F10R1_FB17 ((uint32_t)0x00020000) /*!< Filter bit 17 */ +#define CAN_F10R1_FB18 ((uint32_t)0x00040000) /*!< Filter bit 18 */ +#define CAN_F10R1_FB19 ((uint32_t)0x00080000) /*!< Filter bit 19 */ +#define CAN_F10R1_FB20 ((uint32_t)0x00100000) /*!< Filter bit 20 */ +#define CAN_F10R1_FB21 ((uint32_t)0x00200000) /*!< Filter bit 21 */ +#define CAN_F10R1_FB22 ((uint32_t)0x00400000) /*!< Filter bit 22 */ +#define CAN_F10R1_FB23 ((uint32_t)0x00800000) /*!< Filter bit 23 */ +#define CAN_F10R1_FB24 ((uint32_t)0x01000000) /*!< Filter bit 24 */ +#define CAN_F10R1_FB25 ((uint32_t)0x02000000) /*!< Filter bit 25 */ +#define CAN_F10R1_FB26 ((uint32_t)0x04000000) /*!< Filter bit 26 */ +#define CAN_F10R1_FB27 ((uint32_t)0x08000000) /*!< Filter bit 27 */ +#define CAN_F10R1_FB28 ((uint32_t)0x10000000) /*!< Filter bit 28 */ +#define CAN_F10R1_FB29 ((uint32_t)0x20000000) /*!< Filter bit 29 */ +#define CAN_F10R1_FB30 ((uint32_t)0x40000000) /*!< Filter bit 30 */ +#define CAN_F10R1_FB31 ((uint32_t)0x80000000) /*!< Filter bit 31 */ + +/******************* Bit definition for CAN_F11R1 register ******************/ +#define CAN_F11R1_FB0 ((uint32_t)0x00000001) /*!< Filter bit 0 */ +#define CAN_F11R1_FB1 ((uint32_t)0x00000002) /*!< Filter bit 1 */ +#define CAN_F11R1_FB2 ((uint32_t)0x00000004) /*!< Filter bit 2 */ +#define CAN_F11R1_FB3 ((uint32_t)0x00000008) /*!< Filter bit 3 */ +#define CAN_F11R1_FB4 ((uint32_t)0x00000010) /*!< Filter bit 4 */ +#define CAN_F11R1_FB5 ((uint32_t)0x00000020) /*!< Filter bit 5 */ +#define CAN_F11R1_FB6 ((uint32_t)0x00000040) /*!< Filter bit 6 */ +#define CAN_F11R1_FB7 ((uint32_t)0x00000080) /*!< Filter bit 7 */ +#define CAN_F11R1_FB8 ((uint32_t)0x00000100) /*!< Filter bit 8 */ +#define CAN_F11R1_FB9 ((uint32_t)0x00000200) /*!< Filter bit 9 */ +#define CAN_F11R1_FB10 ((uint32_t)0x00000400) /*!< Filter bit 10 */ +#define CAN_F11R1_FB11 ((uint32_t)0x00000800) /*!< Filter bit 11 */ +#define CAN_F11R1_FB12 ((uint32_t)0x00001000) /*!< Filter bit 12 */ +#define CAN_F11R1_FB13 ((uint32_t)0x00002000) /*!< Filter bit 13 */ +#define CAN_F11R1_FB14 ((uint32_t)0x00004000) /*!< Filter bit 14 */ +#define CAN_F11R1_FB15 ((uint32_t)0x00008000) /*!< Filter bit 15 */ +#define CAN_F11R1_FB16 ((uint32_t)0x00010000) /*!< Filter bit 16 */ +#define CAN_F11R1_FB17 ((uint32_t)0x00020000) /*!< Filter bit 17 */ +#define CAN_F11R1_FB18 ((uint32_t)0x00040000) /*!< Filter bit 18 */ +#define CAN_F11R1_FB19 ((uint32_t)0x00080000) /*!< Filter bit 19 */ +#define CAN_F11R1_FB20 ((uint32_t)0x00100000) /*!< Filter bit 20 */ +#define CAN_F11R1_FB21 ((uint32_t)0x00200000) /*!< Filter bit 21 */ +#define CAN_F11R1_FB22 ((uint32_t)0x00400000) /*!< Filter bit 22 */ +#define CAN_F11R1_FB23 ((uint32_t)0x00800000) /*!< Filter bit 23 */ +#define CAN_F11R1_FB24 ((uint32_t)0x01000000) /*!< Filter bit 24 */ +#define CAN_F11R1_FB25 ((uint32_t)0x02000000) /*!< Filter bit 25 */ +#define CAN_F11R1_FB26 ((uint32_t)0x04000000) /*!< Filter bit 26 */ +#define CAN_F11R1_FB27 ((uint32_t)0x08000000) /*!< Filter bit 27 */ +#define CAN_F11R1_FB28 ((uint32_t)0x10000000) /*!< Filter bit 28 */ +#define CAN_F11R1_FB29 ((uint32_t)0x20000000) /*!< Filter bit 29 */ +#define CAN_F11R1_FB30 ((uint32_t)0x40000000) /*!< Filter bit 30 */ +#define CAN_F11R1_FB31 ((uint32_t)0x80000000) /*!< Filter bit 31 */ + +/******************* Bit definition for CAN_F12R1 register ******************/ +#define CAN_F12R1_FB0 ((uint32_t)0x00000001) /*!< Filter bit 0 */ +#define CAN_F12R1_FB1 ((uint32_t)0x00000002) /*!< Filter bit 1 */ +#define CAN_F12R1_FB2 ((uint32_t)0x00000004) /*!< Filter bit 2 */ +#define CAN_F12R1_FB3 ((uint32_t)0x00000008) /*!< Filter bit 3 */ +#define CAN_F12R1_FB4 ((uint32_t)0x00000010) /*!< Filter bit 4 */ +#define CAN_F12R1_FB5 ((uint32_t)0x00000020) /*!< Filter bit 5 */ +#define CAN_F12R1_FB6 ((uint32_t)0x00000040) /*!< Filter bit 6 */ +#define CAN_F12R1_FB7 ((uint32_t)0x00000080) /*!< Filter bit 7 */ +#define CAN_F12R1_FB8 ((uint32_t)0x00000100) /*!< Filter bit 8 */ +#define CAN_F12R1_FB9 ((uint32_t)0x00000200) /*!< Filter bit 9 */ +#define CAN_F12R1_FB10 ((uint32_t)0x00000400) /*!< Filter bit 10 */ +#define CAN_F12R1_FB11 ((uint32_t)0x00000800) /*!< Filter bit 11 */ +#define CAN_F12R1_FB12 ((uint32_t)0x00001000) /*!< Filter bit 12 */ +#define CAN_F12R1_FB13 ((uint32_t)0x00002000) /*!< Filter bit 13 */ +#define CAN_F12R1_FB14 ((uint32_t)0x00004000) /*!< Filter bit 14 */ +#define CAN_F12R1_FB15 ((uint32_t)0x00008000) /*!< Filter bit 15 */ +#define CAN_F12R1_FB16 ((uint32_t)0x00010000) /*!< Filter bit 16 */ +#define CAN_F12R1_FB17 ((uint32_t)0x00020000) /*!< Filter bit 17 */ +#define CAN_F12R1_FB18 ((uint32_t)0x00040000) /*!< Filter bit 18 */ +#define CAN_F12R1_FB19 ((uint32_t)0x00080000) /*!< Filter bit 19 */ +#define CAN_F12R1_FB20 ((uint32_t)0x00100000) /*!< Filter bit 20 */ +#define CAN_F12R1_FB21 ((uint32_t)0x00200000) /*!< Filter bit 21 */ +#define CAN_F12R1_FB22 ((uint32_t)0x00400000) /*!< Filter bit 22 */ +#define CAN_F12R1_FB23 ((uint32_t)0x00800000) /*!< Filter bit 23 */ +#define CAN_F12R1_FB24 ((uint32_t)0x01000000) /*!< Filter bit 24 */ +#define CAN_F12R1_FB25 ((uint32_t)0x02000000) /*!< Filter bit 25 */ +#define CAN_F12R1_FB26 ((uint32_t)0x04000000) /*!< Filter bit 26 */ +#define CAN_F12R1_FB27 ((uint32_t)0x08000000) /*!< Filter bit 27 */ +#define CAN_F12R1_FB28 ((uint32_t)0x10000000) /*!< Filter bit 28 */ +#define CAN_F12R1_FB29 ((uint32_t)0x20000000) /*!< Filter bit 29 */ +#define CAN_F12R1_FB30 ((uint32_t)0x40000000) /*!< Filter bit 30 */ +#define CAN_F12R1_FB31 ((uint32_t)0x80000000) /*!< Filter bit 31 */ + +/******************* Bit definition for CAN_F13R1 register ******************/ +#define CAN_F13R1_FB0 ((uint32_t)0x00000001) /*!< Filter bit 0 */ +#define CAN_F13R1_FB1 ((uint32_t)0x00000002) /*!< Filter bit 1 */ +#define CAN_F13R1_FB2 ((uint32_t)0x00000004) /*!< Filter bit 2 */ +#define CAN_F13R1_FB3 ((uint32_t)0x00000008) /*!< Filter bit 3 */ +#define CAN_F13R1_FB4 ((uint32_t)0x00000010) /*!< Filter bit 4 */ +#define CAN_F13R1_FB5 ((uint32_t)0x00000020) /*!< Filter bit 5 */ +#define CAN_F13R1_FB6 ((uint32_t)0x00000040) /*!< Filter bit 6 */ +#define CAN_F13R1_FB7 ((uint32_t)0x00000080) /*!< Filter bit 7 */ +#define CAN_F13R1_FB8 ((uint32_t)0x00000100) /*!< Filter bit 8 */ +#define CAN_F13R1_FB9 ((uint32_t)0x00000200) /*!< Filter bit 9 */ +#define CAN_F13R1_FB10 ((uint32_t)0x00000400) /*!< Filter bit 10 */ +#define CAN_F13R1_FB11 ((uint32_t)0x00000800) /*!< Filter bit 11 */ +#define CAN_F13R1_FB12 ((uint32_t)0x00001000) /*!< Filter bit 12 */ +#define CAN_F13R1_FB13 ((uint32_t)0x00002000) /*!< Filter bit 13 */ +#define CAN_F13R1_FB14 ((uint32_t)0x00004000) /*!< Filter bit 14 */ +#define CAN_F13R1_FB15 ((uint32_t)0x00008000) /*!< Filter bit 15 */ +#define CAN_F13R1_FB16 ((uint32_t)0x00010000) /*!< Filter bit 16 */ +#define CAN_F13R1_FB17 ((uint32_t)0x00020000) /*!< Filter bit 17 */ +#define CAN_F13R1_FB18 ((uint32_t)0x00040000) /*!< Filter bit 18 */ +#define CAN_F13R1_FB19 ((uint32_t)0x00080000) /*!< Filter bit 19 */ +#define CAN_F13R1_FB20 ((uint32_t)0x00100000) /*!< Filter bit 20 */ +#define CAN_F13R1_FB21 ((uint32_t)0x00200000) /*!< Filter bit 21 */ +#define CAN_F13R1_FB22 ((uint32_t)0x00400000) /*!< Filter bit 22 */ +#define CAN_F13R1_FB23 ((uint32_t)0x00800000) /*!< Filter bit 23 */ +#define CAN_F13R1_FB24 ((uint32_t)0x01000000) /*!< Filter bit 24 */ +#define CAN_F13R1_FB25 ((uint32_t)0x02000000) /*!< Filter bit 25 */ +#define CAN_F13R1_FB26 ((uint32_t)0x04000000) /*!< Filter bit 26 */ +#define CAN_F13R1_FB27 ((uint32_t)0x08000000) /*!< Filter bit 27 */ +#define CAN_F13R1_FB28 ((uint32_t)0x10000000) /*!< Filter bit 28 */ +#define CAN_F13R1_FB29 ((uint32_t)0x20000000) /*!< Filter bit 29 */ +#define CAN_F13R1_FB30 ((uint32_t)0x40000000) /*!< Filter bit 30 */ +#define CAN_F13R1_FB31 ((uint32_t)0x80000000) /*!< Filter bit 31 */ + +/******************* Bit definition for CAN_F0R2 register *******************/ +#define CAN_F0R2_FB0 ((uint32_t)0x00000001) /*!< Filter bit 0 */ +#define CAN_F0R2_FB1 ((uint32_t)0x00000002) /*!< Filter bit 1 */ +#define CAN_F0R2_FB2 ((uint32_t)0x00000004) /*!< Filter bit 2 */ +#define CAN_F0R2_FB3 ((uint32_t)0x00000008) /*!< Filter bit 3 */ +#define CAN_F0R2_FB4 ((uint32_t)0x00000010) /*!< Filter bit 4 */ +#define CAN_F0R2_FB5 ((uint32_t)0x00000020) /*!< Filter bit 5 */ +#define CAN_F0R2_FB6 ((uint32_t)0x00000040) /*!< Filter bit 6 */ +#define CAN_F0R2_FB7 ((uint32_t)0x00000080) /*!< Filter bit 7 */ +#define CAN_F0R2_FB8 ((uint32_t)0x00000100) /*!< Filter bit 8 */ +#define CAN_F0R2_FB9 ((uint32_t)0x00000200) /*!< Filter bit 9 */ +#define CAN_F0R2_FB10 ((uint32_t)0x00000400) /*!< Filter bit 10 */ +#define CAN_F0R2_FB11 ((uint32_t)0x00000800) /*!< Filter bit 11 */ +#define CAN_F0R2_FB12 ((uint32_t)0x00001000) /*!< Filter bit 12 */ +#define CAN_F0R2_FB13 ((uint32_t)0x00002000) /*!< Filter bit 13 */ +#define CAN_F0R2_FB14 ((uint32_t)0x00004000) /*!< Filter bit 14 */ +#define CAN_F0R2_FB15 ((uint32_t)0x00008000) /*!< Filter bit 15 */ +#define CAN_F0R2_FB16 ((uint32_t)0x00010000) /*!< Filter bit 16 */ +#define CAN_F0R2_FB17 ((uint32_t)0x00020000) /*!< Filter bit 17 */ +#define CAN_F0R2_FB18 ((uint32_t)0x00040000) /*!< Filter bit 18 */ +#define CAN_F0R2_FB19 ((uint32_t)0x00080000) /*!< Filter bit 19 */ +#define CAN_F0R2_FB20 ((uint32_t)0x00100000) /*!< Filter bit 20 */ +#define CAN_F0R2_FB21 ((uint32_t)0x00200000) /*!< Filter bit 21 */ +#define CAN_F0R2_FB22 ((uint32_t)0x00400000) /*!< Filter bit 22 */ +#define CAN_F0R2_FB23 ((uint32_t)0x00800000) /*!< Filter bit 23 */ +#define CAN_F0R2_FB24 ((uint32_t)0x01000000) /*!< Filter bit 24 */ +#define CAN_F0R2_FB25 ((uint32_t)0x02000000) /*!< Filter bit 25 */ +#define CAN_F0R2_FB26 ((uint32_t)0x04000000) /*!< Filter bit 26 */ +#define CAN_F0R2_FB27 ((uint32_t)0x08000000) /*!< Filter bit 27 */ +#define CAN_F0R2_FB28 ((uint32_t)0x10000000) /*!< Filter bit 28 */ +#define CAN_F0R2_FB29 ((uint32_t)0x20000000) /*!< Filter bit 29 */ +#define CAN_F0R2_FB30 ((uint32_t)0x40000000) /*!< Filter bit 30 */ +#define CAN_F0R2_FB31 ((uint32_t)0x80000000) /*!< Filter bit 31 */ + +/******************* Bit definition for CAN_F1R2 register *******************/ +#define CAN_F1R2_FB0 ((uint32_t)0x00000001) /*!< Filter bit 0 */ +#define CAN_F1R2_FB1 ((uint32_t)0x00000002) /*!< Filter bit 1 */ +#define CAN_F1R2_FB2 ((uint32_t)0x00000004) /*!< Filter bit 2 */ +#define CAN_F1R2_FB3 ((uint32_t)0x00000008) /*!< Filter bit 3 */ +#define CAN_F1R2_FB4 ((uint32_t)0x00000010) /*!< Filter bit 4 */ +#define CAN_F1R2_FB5 ((uint32_t)0x00000020) /*!< Filter bit 5 */ +#define CAN_F1R2_FB6 ((uint32_t)0x00000040) /*!< Filter bit 6 */ +#define CAN_F1R2_FB7 ((uint32_t)0x00000080) /*!< Filter bit 7 */ +#define CAN_F1R2_FB8 ((uint32_t)0x00000100) /*!< Filter bit 8 */ +#define CAN_F1R2_FB9 ((uint32_t)0x00000200) /*!< Filter bit 9 */ +#define CAN_F1R2_FB10 ((uint32_t)0x00000400) /*!< Filter bit 10 */ +#define CAN_F1R2_FB11 ((uint32_t)0x00000800) /*!< Filter bit 11 */ +#define CAN_F1R2_FB12 ((uint32_t)0x00001000) /*!< Filter bit 12 */ +#define CAN_F1R2_FB13 ((uint32_t)0x00002000) /*!< Filter bit 13 */ +#define CAN_F1R2_FB14 ((uint32_t)0x00004000) /*!< Filter bit 14 */ +#define CAN_F1R2_FB15 ((uint32_t)0x00008000) /*!< Filter bit 15 */ +#define CAN_F1R2_FB16 ((uint32_t)0x00010000) /*!< Filter bit 16 */ +#define CAN_F1R2_FB17 ((uint32_t)0x00020000) /*!< Filter bit 17 */ +#define CAN_F1R2_FB18 ((uint32_t)0x00040000) /*!< Filter bit 18 */ +#define CAN_F1R2_FB19 ((uint32_t)0x00080000) /*!< Filter bit 19 */ +#define CAN_F1R2_FB20 ((uint32_t)0x00100000) /*!< Filter bit 20 */ +#define CAN_F1R2_FB21 ((uint32_t)0x00200000) /*!< Filter bit 21 */ +#define CAN_F1R2_FB22 ((uint32_t)0x00400000) /*!< Filter bit 22 */ +#define CAN_F1R2_FB23 ((uint32_t)0x00800000) /*!< Filter bit 23 */ +#define CAN_F1R2_FB24 ((uint32_t)0x01000000) /*!< Filter bit 24 */ +#define CAN_F1R2_FB25 ((uint32_t)0x02000000) /*!< Filter bit 25 */ +#define CAN_F1R2_FB26 ((uint32_t)0x04000000) /*!< Filter bit 26 */ +#define CAN_F1R2_FB27 ((uint32_t)0x08000000) /*!< Filter bit 27 */ +#define CAN_F1R2_FB28 ((uint32_t)0x10000000) /*!< Filter bit 28 */ +#define CAN_F1R2_FB29 ((uint32_t)0x20000000) /*!< Filter bit 29 */ +#define CAN_F1R2_FB30 ((uint32_t)0x40000000) /*!< Filter bit 30 */ +#define CAN_F1R2_FB31 ((uint32_t)0x80000000) /*!< Filter bit 31 */ + +/******************* Bit definition for CAN_F2R2 register *******************/ +#define CAN_F2R2_FB0 ((uint32_t)0x00000001) /*!< Filter bit 0 */ +#define CAN_F2R2_FB1 ((uint32_t)0x00000002) /*!< Filter bit 1 */ +#define CAN_F2R2_FB2 ((uint32_t)0x00000004) /*!< Filter bit 2 */ +#define CAN_F2R2_FB3 ((uint32_t)0x00000008) /*!< Filter bit 3 */ +#define CAN_F2R2_FB4 ((uint32_t)0x00000010) /*!< Filter bit 4 */ +#define CAN_F2R2_FB5 ((uint32_t)0x00000020) /*!< Filter bit 5 */ +#define CAN_F2R2_FB6 ((uint32_t)0x00000040) /*!< Filter bit 6 */ +#define CAN_F2R2_FB7 ((uint32_t)0x00000080) /*!< Filter bit 7 */ +#define CAN_F2R2_FB8 ((uint32_t)0x00000100) /*!< Filter bit 8 */ +#define CAN_F2R2_FB9 ((uint32_t)0x00000200) /*!< Filter bit 9 */ +#define CAN_F2R2_FB10 ((uint32_t)0x00000400) /*!< Filter bit 10 */ +#define CAN_F2R2_FB11 ((uint32_t)0x00000800) /*!< Filter bit 11 */ +#define CAN_F2R2_FB12 ((uint32_t)0x00001000) /*!< Filter bit 12 */ +#define CAN_F2R2_FB13 ((uint32_t)0x00002000) /*!< Filter bit 13 */ +#define CAN_F2R2_FB14 ((uint32_t)0x00004000) /*!< Filter bit 14 */ +#define CAN_F2R2_FB15 ((uint32_t)0x00008000) /*!< Filter bit 15 */ +#define CAN_F2R2_FB16 ((uint32_t)0x00010000) /*!< Filter bit 16 */ +#define CAN_F2R2_FB17 ((uint32_t)0x00020000) /*!< Filter bit 17 */ +#define CAN_F2R2_FB18 ((uint32_t)0x00040000) /*!< Filter bit 18 */ +#define CAN_F2R2_FB19 ((uint32_t)0x00080000) /*!< Filter bit 19 */ +#define CAN_F2R2_FB20 ((uint32_t)0x00100000) /*!< Filter bit 20 */ +#define CAN_F2R2_FB21 ((uint32_t)0x00200000) /*!< Filter bit 21 */ +#define CAN_F2R2_FB22 ((uint32_t)0x00400000) /*!< Filter bit 22 */ +#define CAN_F2R2_FB23 ((uint32_t)0x00800000) /*!< Filter bit 23 */ +#define CAN_F2R2_FB24 ((uint32_t)0x01000000) /*!< Filter bit 24 */ +#define CAN_F2R2_FB25 ((uint32_t)0x02000000) /*!< Filter bit 25 */ +#define CAN_F2R2_FB26 ((uint32_t)0x04000000) /*!< Filter bit 26 */ +#define CAN_F2R2_FB27 ((uint32_t)0x08000000) /*!< Filter bit 27 */ +#define CAN_F2R2_FB28 ((uint32_t)0x10000000) /*!< Filter bit 28 */ +#define CAN_F2R2_FB29 ((uint32_t)0x20000000) /*!< Filter bit 29 */ +#define CAN_F2R2_FB30 ((uint32_t)0x40000000) /*!< Filter bit 30 */ +#define CAN_F2R2_FB31 ((uint32_t)0x80000000) /*!< Filter bit 31 */ + +/******************* Bit definition for CAN_F3R2 register *******************/ +#define CAN_F3R2_FB0 ((uint32_t)0x00000001) /*!< Filter bit 0 */ +#define CAN_F3R2_FB1 ((uint32_t)0x00000002) /*!< Filter bit 1 */ +#define CAN_F3R2_FB2 ((uint32_t)0x00000004) /*!< Filter bit 2 */ +#define CAN_F3R2_FB3 ((uint32_t)0x00000008) /*!< Filter bit 3 */ +#define CAN_F3R2_FB4 ((uint32_t)0x00000010) /*!< Filter bit 4 */ +#define CAN_F3R2_FB5 ((uint32_t)0x00000020) /*!< Filter bit 5 */ +#define CAN_F3R2_FB6 ((uint32_t)0x00000040) /*!< Filter bit 6 */ +#define CAN_F3R2_FB7 ((uint32_t)0x00000080) /*!< Filter bit 7 */ +#define CAN_F3R2_FB8 ((uint32_t)0x00000100) /*!< Filter bit 8 */ +#define CAN_F3R2_FB9 ((uint32_t)0x00000200) /*!< Filter bit 9 */ +#define CAN_F3R2_FB10 ((uint32_t)0x00000400) /*!< Filter bit 10 */ +#define CAN_F3R2_FB11 ((uint32_t)0x00000800) /*!< Filter bit 11 */ +#define CAN_F3R2_FB12 ((uint32_t)0x00001000) /*!< Filter bit 12 */ +#define CAN_F3R2_FB13 ((uint32_t)0x00002000) /*!< Filter bit 13 */ +#define CAN_F3R2_FB14 ((uint32_t)0x00004000) /*!< Filter bit 14 */ +#define CAN_F3R2_FB15 ((uint32_t)0x00008000) /*!< Filter bit 15 */ +#define CAN_F3R2_FB16 ((uint32_t)0x00010000) /*!< Filter bit 16 */ +#define CAN_F3R2_FB17 ((uint32_t)0x00020000) /*!< Filter bit 17 */ +#define CAN_F3R2_FB18 ((uint32_t)0x00040000) /*!< Filter bit 18 */ +#define CAN_F3R2_FB19 ((uint32_t)0x00080000) /*!< Filter bit 19 */ +#define CAN_F3R2_FB20 ((uint32_t)0x00100000) /*!< Filter bit 20 */ +#define CAN_F3R2_FB21 ((uint32_t)0x00200000) /*!< Filter bit 21 */ +#define CAN_F3R2_FB22 ((uint32_t)0x00400000) /*!< Filter bit 22 */ +#define CAN_F3R2_FB23 ((uint32_t)0x00800000) /*!< Filter bit 23 */ +#define CAN_F3R2_FB24 ((uint32_t)0x01000000) /*!< Filter bit 24 */ +#define CAN_F3R2_FB25 ((uint32_t)0x02000000) /*!< Filter bit 25 */ +#define CAN_F3R2_FB26 ((uint32_t)0x04000000) /*!< Filter bit 26 */ +#define CAN_F3R2_FB27 ((uint32_t)0x08000000) /*!< Filter bit 27 */ +#define CAN_F3R2_FB28 ((uint32_t)0x10000000) /*!< Filter bit 28 */ +#define CAN_F3R2_FB29 ((uint32_t)0x20000000) /*!< Filter bit 29 */ +#define CAN_F3R2_FB30 ((uint32_t)0x40000000) /*!< Filter bit 30 */ +#define CAN_F3R2_FB31 ((uint32_t)0x80000000) /*!< Filter bit 31 */ + +/******************* Bit definition for CAN_F4R2 register *******************/ +#define CAN_F4R2_FB0 ((uint32_t)0x00000001) /*!< Filter bit 0 */ +#define CAN_F4R2_FB1 ((uint32_t)0x00000002) /*!< Filter bit 1 */ +#define CAN_F4R2_FB2 ((uint32_t)0x00000004) /*!< Filter bit 2 */ +#define CAN_F4R2_FB3 ((uint32_t)0x00000008) /*!< Filter bit 3 */ +#define CAN_F4R2_FB4 ((uint32_t)0x00000010) /*!< Filter bit 4 */ +#define CAN_F4R2_FB5 ((uint32_t)0x00000020) /*!< Filter bit 5 */ +#define CAN_F4R2_FB6 ((uint32_t)0x00000040) /*!< Filter bit 6 */ +#define CAN_F4R2_FB7 ((uint32_t)0x00000080) /*!< Filter bit 7 */ +#define CAN_F4R2_FB8 ((uint32_t)0x00000100) /*!< Filter bit 8 */ +#define CAN_F4R2_FB9 ((uint32_t)0x00000200) /*!< Filter bit 9 */ +#define CAN_F4R2_FB10 ((uint32_t)0x00000400) /*!< Filter bit 10 */ +#define CAN_F4R2_FB11 ((uint32_t)0x00000800) /*!< Filter bit 11 */ +#define CAN_F4R2_FB12 ((uint32_t)0x00001000) /*!< Filter bit 12 */ +#define CAN_F4R2_FB13 ((uint32_t)0x00002000) /*!< Filter bit 13 */ +#define CAN_F4R2_FB14 ((uint32_t)0x00004000) /*!< Filter bit 14 */ +#define CAN_F4R2_FB15 ((uint32_t)0x00008000) /*!< Filter bit 15 */ +#define CAN_F4R2_FB16 ((uint32_t)0x00010000) /*!< Filter bit 16 */ +#define CAN_F4R2_FB17 ((uint32_t)0x00020000) /*!< Filter bit 17 */ +#define CAN_F4R2_FB18 ((uint32_t)0x00040000) /*!< Filter bit 18 */ +#define CAN_F4R2_FB19 ((uint32_t)0x00080000) /*!< Filter bit 19 */ +#define CAN_F4R2_FB20 ((uint32_t)0x00100000) /*!< Filter bit 20 */ +#define CAN_F4R2_FB21 ((uint32_t)0x00200000) /*!< Filter bit 21 */ +#define CAN_F4R2_FB22 ((uint32_t)0x00400000) /*!< Filter bit 22 */ +#define CAN_F4R2_FB23 ((uint32_t)0x00800000) /*!< Filter bit 23 */ +#define CAN_F4R2_FB24 ((uint32_t)0x01000000) /*!< Filter bit 24 */ +#define CAN_F4R2_FB25 ((uint32_t)0x02000000) /*!< Filter bit 25 */ +#define CAN_F4R2_FB26 ((uint32_t)0x04000000) /*!< Filter bit 26 */ +#define CAN_F4R2_FB27 ((uint32_t)0x08000000) /*!< Filter bit 27 */ +#define CAN_F4R2_FB28 ((uint32_t)0x10000000) /*!< Filter bit 28 */ +#define CAN_F4R2_FB29 ((uint32_t)0x20000000) /*!< Filter bit 29 */ +#define CAN_F4R2_FB30 ((uint32_t)0x40000000) /*!< Filter bit 30 */ +#define CAN_F4R2_FB31 ((uint32_t)0x80000000) /*!< Filter bit 31 */ + +/******************* Bit definition for CAN_F5R2 register *******************/ +#define CAN_F5R2_FB0 ((uint32_t)0x00000001) /*!< Filter bit 0 */ +#define CAN_F5R2_FB1 ((uint32_t)0x00000002) /*!< Filter bit 1 */ +#define CAN_F5R2_FB2 ((uint32_t)0x00000004) /*!< Filter bit 2 */ +#define CAN_F5R2_FB3 ((uint32_t)0x00000008) /*!< Filter bit 3 */ +#define CAN_F5R2_FB4 ((uint32_t)0x00000010) /*!< Filter bit 4 */ +#define CAN_F5R2_FB5 ((uint32_t)0x00000020) /*!< Filter bit 5 */ +#define CAN_F5R2_FB6 ((uint32_t)0x00000040) /*!< Filter bit 6 */ +#define CAN_F5R2_FB7 ((uint32_t)0x00000080) /*!< Filter bit 7 */ +#define CAN_F5R2_FB8 ((uint32_t)0x00000100) /*!< Filter bit 8 */ +#define CAN_F5R2_FB9 ((uint32_t)0x00000200) /*!< Filter bit 9 */ +#define CAN_F5R2_FB10 ((uint32_t)0x00000400) /*!< Filter bit 10 */ +#define CAN_F5R2_FB11 ((uint32_t)0x00000800) /*!< Filter bit 11 */ +#define CAN_F5R2_FB12 ((uint32_t)0x00001000) /*!< Filter bit 12 */ +#define CAN_F5R2_FB13 ((uint32_t)0x00002000) /*!< Filter bit 13 */ +#define CAN_F5R2_FB14 ((uint32_t)0x00004000) /*!< Filter bit 14 */ +#define CAN_F5R2_FB15 ((uint32_t)0x00008000) /*!< Filter bit 15 */ +#define CAN_F5R2_FB16 ((uint32_t)0x00010000) /*!< Filter bit 16 */ +#define CAN_F5R2_FB17 ((uint32_t)0x00020000) /*!< Filter bit 17 */ +#define CAN_F5R2_FB18 ((uint32_t)0x00040000) /*!< Filter bit 18 */ +#define CAN_F5R2_FB19 ((uint32_t)0x00080000) /*!< Filter bit 19 */ +#define CAN_F5R2_FB20 ((uint32_t)0x00100000) /*!< Filter bit 20 */ +#define CAN_F5R2_FB21 ((uint32_t)0x00200000) /*!< Filter bit 21 */ +#define CAN_F5R2_FB22 ((uint32_t)0x00400000) /*!< Filter bit 22 */ +#define CAN_F5R2_FB23 ((uint32_t)0x00800000) /*!< Filter bit 23 */ +#define CAN_F5R2_FB24 ((uint32_t)0x01000000) /*!< Filter bit 24 */ +#define CAN_F5R2_FB25 ((uint32_t)0x02000000) /*!< Filter bit 25 */ +#define CAN_F5R2_FB26 ((uint32_t)0x04000000) /*!< Filter bit 26 */ +#define CAN_F5R2_FB27 ((uint32_t)0x08000000) /*!< Filter bit 27 */ +#define CAN_F5R2_FB28 ((uint32_t)0x10000000) /*!< Filter bit 28 */ +#define CAN_F5R2_FB29 ((uint32_t)0x20000000) /*!< Filter bit 29 */ +#define CAN_F5R2_FB30 ((uint32_t)0x40000000) /*!< Filter bit 30 */ +#define CAN_F5R2_FB31 ((uint32_t)0x80000000) /*!< Filter bit 31 */ + +/******************* Bit definition for CAN_F6R2 register *******************/ +#define CAN_F6R2_FB0 ((uint32_t)0x00000001) /*!< Filter bit 0 */ +#define CAN_F6R2_FB1 ((uint32_t)0x00000002) /*!< Filter bit 1 */ +#define CAN_F6R2_FB2 ((uint32_t)0x00000004) /*!< Filter bit 2 */ +#define CAN_F6R2_FB3 ((uint32_t)0x00000008) /*!< Filter bit 3 */ +#define CAN_F6R2_FB4 ((uint32_t)0x00000010) /*!< Filter bit 4 */ +#define CAN_F6R2_FB5 ((uint32_t)0x00000020) /*!< Filter bit 5 */ +#define CAN_F6R2_FB6 ((uint32_t)0x00000040) /*!< Filter bit 6 */ +#define CAN_F6R2_FB7 ((uint32_t)0x00000080) /*!< Filter bit 7 */ +#define CAN_F6R2_FB8 ((uint32_t)0x00000100) /*!< Filter bit 8 */ +#define CAN_F6R2_FB9 ((uint32_t)0x00000200) /*!< Filter bit 9 */ +#define CAN_F6R2_FB10 ((uint32_t)0x00000400) /*!< Filter bit 10 */ +#define CAN_F6R2_FB11 ((uint32_t)0x00000800) /*!< Filter bit 11 */ +#define CAN_F6R2_FB12 ((uint32_t)0x00001000) /*!< Filter bit 12 */ +#define CAN_F6R2_FB13 ((uint32_t)0x00002000) /*!< Filter bit 13 */ +#define CAN_F6R2_FB14 ((uint32_t)0x00004000) /*!< Filter bit 14 */ +#define CAN_F6R2_FB15 ((uint32_t)0x00008000) /*!< Filter bit 15 */ +#define CAN_F6R2_FB16 ((uint32_t)0x00010000) /*!< Filter bit 16 */ +#define CAN_F6R2_FB17 ((uint32_t)0x00020000) /*!< Filter bit 17 */ +#define CAN_F6R2_FB18 ((uint32_t)0x00040000) /*!< Filter bit 18 */ +#define CAN_F6R2_FB19 ((uint32_t)0x00080000) /*!< Filter bit 19 */ +#define CAN_F6R2_FB20 ((uint32_t)0x00100000) /*!< Filter bit 20 */ +#define CAN_F6R2_FB21 ((uint32_t)0x00200000) /*!< Filter bit 21 */ +#define CAN_F6R2_FB22 ((uint32_t)0x00400000) /*!< Filter bit 22 */ +#define CAN_F6R2_FB23 ((uint32_t)0x00800000) /*!< Filter bit 23 */ +#define CAN_F6R2_FB24 ((uint32_t)0x01000000) /*!< Filter bit 24 */ +#define CAN_F6R2_FB25 ((uint32_t)0x02000000) /*!< Filter bit 25 */ +#define CAN_F6R2_FB26 ((uint32_t)0x04000000) /*!< Filter bit 26 */ +#define CAN_F6R2_FB27 ((uint32_t)0x08000000) /*!< Filter bit 27 */ +#define CAN_F6R2_FB28 ((uint32_t)0x10000000) /*!< Filter bit 28 */ +#define CAN_F6R2_FB29 ((uint32_t)0x20000000) /*!< Filter bit 29 */ +#define CAN_F6R2_FB30 ((uint32_t)0x40000000) /*!< Filter bit 30 */ +#define CAN_F6R2_FB31 ((uint32_t)0x80000000) /*!< Filter bit 31 */ + +/******************* Bit definition for CAN_F7R2 register *******************/ +#define CAN_F7R2_FB0 ((uint32_t)0x00000001) /*!< Filter bit 0 */ +#define CAN_F7R2_FB1 ((uint32_t)0x00000002) /*!< Filter bit 1 */ +#define CAN_F7R2_FB2 ((uint32_t)0x00000004) /*!< Filter bit 2 */ +#define CAN_F7R2_FB3 ((uint32_t)0x00000008) /*!< Filter bit 3 */ +#define CAN_F7R2_FB4 ((uint32_t)0x00000010) /*!< Filter bit 4 */ +#define CAN_F7R2_FB5 ((uint32_t)0x00000020) /*!< Filter bit 5 */ +#define CAN_F7R2_FB6 ((uint32_t)0x00000040) /*!< Filter bit 6 */ +#define CAN_F7R2_FB7 ((uint32_t)0x00000080) /*!< Filter bit 7 */ +#define CAN_F7R2_FB8 ((uint32_t)0x00000100) /*!< Filter bit 8 */ +#define CAN_F7R2_FB9 ((uint32_t)0x00000200) /*!< Filter bit 9 */ +#define CAN_F7R2_FB10 ((uint32_t)0x00000400) /*!< Filter bit 10 */ +#define CAN_F7R2_FB11 ((uint32_t)0x00000800) /*!< Filter bit 11 */ +#define CAN_F7R2_FB12 ((uint32_t)0x00001000) /*!< Filter bit 12 */ +#define CAN_F7R2_FB13 ((uint32_t)0x00002000) /*!< Filter bit 13 */ +#define CAN_F7R2_FB14 ((uint32_t)0x00004000) /*!< Filter bit 14 */ +#define CAN_F7R2_FB15 ((uint32_t)0x00008000) /*!< Filter bit 15 */ +#define CAN_F7R2_FB16 ((uint32_t)0x00010000) /*!< Filter bit 16 */ +#define CAN_F7R2_FB17 ((uint32_t)0x00020000) /*!< Filter bit 17 */ +#define CAN_F7R2_FB18 ((uint32_t)0x00040000) /*!< Filter bit 18 */ +#define CAN_F7R2_FB19 ((uint32_t)0x00080000) /*!< Filter bit 19 */ +#define CAN_F7R2_FB20 ((uint32_t)0x00100000) /*!< Filter bit 20 */ +#define CAN_F7R2_FB21 ((uint32_t)0x00200000) /*!< Filter bit 21 */ +#define CAN_F7R2_FB22 ((uint32_t)0x00400000) /*!< Filter bit 22 */ +#define CAN_F7R2_FB23 ((uint32_t)0x00800000) /*!< Filter bit 23 */ +#define CAN_F7R2_FB24 ((uint32_t)0x01000000) /*!< Filter bit 24 */ +#define CAN_F7R2_FB25 ((uint32_t)0x02000000) /*!< Filter bit 25 */ +#define CAN_F7R2_FB26 ((uint32_t)0x04000000) /*!< Filter bit 26 */ +#define CAN_F7R2_FB27 ((uint32_t)0x08000000) /*!< Filter bit 27 */ +#define CAN_F7R2_FB28 ((uint32_t)0x10000000) /*!< Filter bit 28 */ +#define CAN_F7R2_FB29 ((uint32_t)0x20000000) /*!< Filter bit 29 */ +#define CAN_F7R2_FB30 ((uint32_t)0x40000000) /*!< Filter bit 30 */ +#define CAN_F7R2_FB31 ((uint32_t)0x80000000) /*!< Filter bit 31 */ + +/******************* Bit definition for CAN_F8R2 register *******************/ +#define CAN_F8R2_FB0 ((uint32_t)0x00000001) /*!< Filter bit 0 */ +#define CAN_F8R2_FB1 ((uint32_t)0x00000002) /*!< Filter bit 1 */ +#define CAN_F8R2_FB2 ((uint32_t)0x00000004) /*!< Filter bit 2 */ +#define CAN_F8R2_FB3 ((uint32_t)0x00000008) /*!< Filter bit 3 */ +#define CAN_F8R2_FB4 ((uint32_t)0x00000010) /*!< Filter bit 4 */ +#define CAN_F8R2_FB5 ((uint32_t)0x00000020) /*!< Filter bit 5 */ +#define CAN_F8R2_FB6 ((uint32_t)0x00000040) /*!< Filter bit 6 */ +#define CAN_F8R2_FB7 ((uint32_t)0x00000080) /*!< Filter bit 7 */ +#define CAN_F8R2_FB8 ((uint32_t)0x00000100) /*!< Filter bit 8 */ +#define CAN_F8R2_FB9 ((uint32_t)0x00000200) /*!< Filter bit 9 */ +#define CAN_F8R2_FB10 ((uint32_t)0x00000400) /*!< Filter bit 10 */ +#define CAN_F8R2_FB11 ((uint32_t)0x00000800) /*!< Filter bit 11 */ +#define CAN_F8R2_FB12 ((uint32_t)0x00001000) /*!< Filter bit 12 */ +#define CAN_F8R2_FB13 ((uint32_t)0x00002000) /*!< Filter bit 13 */ +#define CAN_F8R2_FB14 ((uint32_t)0x00004000) /*!< Filter bit 14 */ +#define CAN_F8R2_FB15 ((uint32_t)0x00008000) /*!< Filter bit 15 */ +#define CAN_F8R2_FB16 ((uint32_t)0x00010000) /*!< Filter bit 16 */ +#define CAN_F8R2_FB17 ((uint32_t)0x00020000) /*!< Filter bit 17 */ +#define CAN_F8R2_FB18 ((uint32_t)0x00040000) /*!< Filter bit 18 */ +#define CAN_F8R2_FB19 ((uint32_t)0x00080000) /*!< Filter bit 19 */ +#define CAN_F8R2_FB20 ((uint32_t)0x00100000) /*!< Filter bit 20 */ +#define CAN_F8R2_FB21 ((uint32_t)0x00200000) /*!< Filter bit 21 */ +#define CAN_F8R2_FB22 ((uint32_t)0x00400000) /*!< Filter bit 22 */ +#define CAN_F8R2_FB23 ((uint32_t)0x00800000) /*!< Filter bit 23 */ +#define CAN_F8R2_FB24 ((uint32_t)0x01000000) /*!< Filter bit 24 */ +#define CAN_F8R2_FB25 ((uint32_t)0x02000000) /*!< Filter bit 25 */ +#define CAN_F8R2_FB26 ((uint32_t)0x04000000) /*!< Filter bit 26 */ +#define CAN_F8R2_FB27 ((uint32_t)0x08000000) /*!< Filter bit 27 */ +#define CAN_F8R2_FB28 ((uint32_t)0x10000000) /*!< Filter bit 28 */ +#define CAN_F8R2_FB29 ((uint32_t)0x20000000) /*!< Filter bit 29 */ +#define CAN_F8R2_FB30 ((uint32_t)0x40000000) /*!< Filter bit 30 */ +#define CAN_F8R2_FB31 ((uint32_t)0x80000000) /*!< Filter bit 31 */ + +/******************* Bit definition for CAN_F9R2 register *******************/ +#define CAN_F9R2_FB0 ((uint32_t)0x00000001) /*!< Filter bit 0 */ +#define CAN_F9R2_FB1 ((uint32_t)0x00000002) /*!< Filter bit 1 */ +#define CAN_F9R2_FB2 ((uint32_t)0x00000004) /*!< Filter bit 2 */ +#define CAN_F9R2_FB3 ((uint32_t)0x00000008) /*!< Filter bit 3 */ +#define CAN_F9R2_FB4 ((uint32_t)0x00000010) /*!< Filter bit 4 */ +#define CAN_F9R2_FB5 ((uint32_t)0x00000020) /*!< Filter bit 5 */ +#define CAN_F9R2_FB6 ((uint32_t)0x00000040) /*!< Filter bit 6 */ +#define CAN_F9R2_FB7 ((uint32_t)0x00000080) /*!< Filter bit 7 */ +#define CAN_F9R2_FB8 ((uint32_t)0x00000100) /*!< Filter bit 8 */ +#define CAN_F9R2_FB9 ((uint32_t)0x00000200) /*!< Filter bit 9 */ +#define CAN_F9R2_FB10 ((uint32_t)0x00000400) /*!< Filter bit 10 */ +#define CAN_F9R2_FB11 ((uint32_t)0x00000800) /*!< Filter bit 11 */ +#define CAN_F9R2_FB12 ((uint32_t)0x00001000) /*!< Filter bit 12 */ +#define CAN_F9R2_FB13 ((uint32_t)0x00002000) /*!< Filter bit 13 */ +#define CAN_F9R2_FB14 ((uint32_t)0x00004000) /*!< Filter bit 14 */ +#define CAN_F9R2_FB15 ((uint32_t)0x00008000) /*!< Filter bit 15 */ +#define CAN_F9R2_FB16 ((uint32_t)0x00010000) /*!< Filter bit 16 */ +#define CAN_F9R2_FB17 ((uint32_t)0x00020000) /*!< Filter bit 17 */ +#define CAN_F9R2_FB18 ((uint32_t)0x00040000) /*!< Filter bit 18 */ +#define CAN_F9R2_FB19 ((uint32_t)0x00080000) /*!< Filter bit 19 */ +#define CAN_F9R2_FB20 ((uint32_t)0x00100000) /*!< Filter bit 20 */ +#define CAN_F9R2_FB21 ((uint32_t)0x00200000) /*!< Filter bit 21 */ +#define CAN_F9R2_FB22 ((uint32_t)0x00400000) /*!< Filter bit 22 */ +#define CAN_F9R2_FB23 ((uint32_t)0x00800000) /*!< Filter bit 23 */ +#define CAN_F9R2_FB24 ((uint32_t)0x01000000) /*!< Filter bit 24 */ +#define CAN_F9R2_FB25 ((uint32_t)0x02000000) /*!< Filter bit 25 */ +#define CAN_F9R2_FB26 ((uint32_t)0x04000000) /*!< Filter bit 26 */ +#define CAN_F9R2_FB27 ((uint32_t)0x08000000) /*!< Filter bit 27 */ +#define CAN_F9R2_FB28 ((uint32_t)0x10000000) /*!< Filter bit 28 */ +#define CAN_F9R2_FB29 ((uint32_t)0x20000000) /*!< Filter bit 29 */ +#define CAN_F9R2_FB30 ((uint32_t)0x40000000) /*!< Filter bit 30 */ +#define CAN_F9R2_FB31 ((uint32_t)0x80000000) /*!< Filter bit 31 */ + +/******************* Bit definition for CAN_F10R2 register ******************/ +#define CAN_F10R2_FB0 ((uint32_t)0x00000001) /*!< Filter bit 0 */ +#define CAN_F10R2_FB1 ((uint32_t)0x00000002) /*!< Filter bit 1 */ +#define CAN_F10R2_FB2 ((uint32_t)0x00000004) /*!< Filter bit 2 */ +#define CAN_F10R2_FB3 ((uint32_t)0x00000008) /*!< Filter bit 3 */ +#define CAN_F10R2_FB4 ((uint32_t)0x00000010) /*!< Filter bit 4 */ +#define CAN_F10R2_FB5 ((uint32_t)0x00000020) /*!< Filter bit 5 */ +#define CAN_F10R2_FB6 ((uint32_t)0x00000040) /*!< Filter bit 6 */ +#define CAN_F10R2_FB7 ((uint32_t)0x00000080) /*!< Filter bit 7 */ +#define CAN_F10R2_FB8 ((uint32_t)0x00000100) /*!< Filter bit 8 */ +#define CAN_F10R2_FB9 ((uint32_t)0x00000200) /*!< Filter bit 9 */ +#define CAN_F10R2_FB10 ((uint32_t)0x00000400) /*!< Filter bit 10 */ +#define CAN_F10R2_FB11 ((uint32_t)0x00000800) /*!< Filter bit 11 */ +#define CAN_F10R2_FB12 ((uint32_t)0x00001000) /*!< Filter bit 12 */ +#define CAN_F10R2_FB13 ((uint32_t)0x00002000) /*!< Filter bit 13 */ +#define CAN_F10R2_FB14 ((uint32_t)0x00004000) /*!< Filter bit 14 */ +#define CAN_F10R2_FB15 ((uint32_t)0x00008000) /*!< Filter bit 15 */ +#define CAN_F10R2_FB16 ((uint32_t)0x00010000) /*!< Filter bit 16 */ +#define CAN_F10R2_FB17 ((uint32_t)0x00020000) /*!< Filter bit 17 */ +#define CAN_F10R2_FB18 ((uint32_t)0x00040000) /*!< Filter bit 18 */ +#define CAN_F10R2_FB19 ((uint32_t)0x00080000) /*!< Filter bit 19 */ +#define CAN_F10R2_FB20 ((uint32_t)0x00100000) /*!< Filter bit 20 */ +#define CAN_F10R2_FB21 ((uint32_t)0x00200000) /*!< Filter bit 21 */ +#define CAN_F10R2_FB22 ((uint32_t)0x00400000) /*!< Filter bit 22 */ +#define CAN_F10R2_FB23 ((uint32_t)0x00800000) /*!< Filter bit 23 */ +#define CAN_F10R2_FB24 ((uint32_t)0x01000000) /*!< Filter bit 24 */ +#define CAN_F10R2_FB25 ((uint32_t)0x02000000) /*!< Filter bit 25 */ +#define CAN_F10R2_FB26 ((uint32_t)0x04000000) /*!< Filter bit 26 */ +#define CAN_F10R2_FB27 ((uint32_t)0x08000000) /*!< Filter bit 27 */ +#define CAN_F10R2_FB28 ((uint32_t)0x10000000) /*!< Filter bit 28 */ +#define CAN_F10R2_FB29 ((uint32_t)0x20000000) /*!< Filter bit 29 */ +#define CAN_F10R2_FB30 ((uint32_t)0x40000000) /*!< Filter bit 30 */ +#define CAN_F10R2_FB31 ((uint32_t)0x80000000) /*!< Filter bit 31 */ + +/******************* Bit definition for CAN_F11R2 register ******************/ +#define CAN_F11R2_FB0 ((uint32_t)0x00000001) /*!< Filter bit 0 */ +#define CAN_F11R2_FB1 ((uint32_t)0x00000002) /*!< Filter bit 1 */ +#define CAN_F11R2_FB2 ((uint32_t)0x00000004) /*!< Filter bit 2 */ +#define CAN_F11R2_FB3 ((uint32_t)0x00000008) /*!< Filter bit 3 */ +#define CAN_F11R2_FB4 ((uint32_t)0x00000010) /*!< Filter bit 4 */ +#define CAN_F11R2_FB5 ((uint32_t)0x00000020) /*!< Filter bit 5 */ +#define CAN_F11R2_FB6 ((uint32_t)0x00000040) /*!< Filter bit 6 */ +#define CAN_F11R2_FB7 ((uint32_t)0x00000080) /*!< Filter bit 7 */ +#define CAN_F11R2_FB8 ((uint32_t)0x00000100) /*!< Filter bit 8 */ +#define CAN_F11R2_FB9 ((uint32_t)0x00000200) /*!< Filter bit 9 */ +#define CAN_F11R2_FB10 ((uint32_t)0x00000400) /*!< Filter bit 10 */ +#define CAN_F11R2_FB11 ((uint32_t)0x00000800) /*!< Filter bit 11 */ +#define CAN_F11R2_FB12 ((uint32_t)0x00001000) /*!< Filter bit 12 */ +#define CAN_F11R2_FB13 ((uint32_t)0x00002000) /*!< Filter bit 13 */ +#define CAN_F11R2_FB14 ((uint32_t)0x00004000) /*!< Filter bit 14 */ +#define CAN_F11R2_FB15 ((uint32_t)0x00008000) /*!< Filter bit 15 */ +#define CAN_F11R2_FB16 ((uint32_t)0x00010000) /*!< Filter bit 16 */ +#define CAN_F11R2_FB17 ((uint32_t)0x00020000) /*!< Filter bit 17 */ +#define CAN_F11R2_FB18 ((uint32_t)0x00040000) /*!< Filter bit 18 */ +#define CAN_F11R2_FB19 ((uint32_t)0x00080000) /*!< Filter bit 19 */ +#define CAN_F11R2_FB20 ((uint32_t)0x00100000) /*!< Filter bit 20 */ +#define CAN_F11R2_FB21 ((uint32_t)0x00200000) /*!< Filter bit 21 */ +#define CAN_F11R2_FB22 ((uint32_t)0x00400000) /*!< Filter bit 22 */ +#define CAN_F11R2_FB23 ((uint32_t)0x00800000) /*!< Filter bit 23 */ +#define CAN_F11R2_FB24 ((uint32_t)0x01000000) /*!< Filter bit 24 */ +#define CAN_F11R2_FB25 ((uint32_t)0x02000000) /*!< Filter bit 25 */ +#define CAN_F11R2_FB26 ((uint32_t)0x04000000) /*!< Filter bit 26 */ +#define CAN_F11R2_FB27 ((uint32_t)0x08000000) /*!< Filter bit 27 */ +#define CAN_F11R2_FB28 ((uint32_t)0x10000000) /*!< Filter bit 28 */ +#define CAN_F11R2_FB29 ((uint32_t)0x20000000) /*!< Filter bit 29 */ +#define CAN_F11R2_FB30 ((uint32_t)0x40000000) /*!< Filter bit 30 */ +#define CAN_F11R2_FB31 ((uint32_t)0x80000000) /*!< Filter bit 31 */ + +/******************* Bit definition for CAN_F12R2 register ******************/ +#define CAN_F12R2_FB0 ((uint32_t)0x00000001) /*!< Filter bit 0 */ +#define CAN_F12R2_FB1 ((uint32_t)0x00000002) /*!< Filter bit 1 */ +#define CAN_F12R2_FB2 ((uint32_t)0x00000004) /*!< Filter bit 2 */ +#define CAN_F12R2_FB3 ((uint32_t)0x00000008) /*!< Filter bit 3 */ +#define CAN_F12R2_FB4 ((uint32_t)0x00000010) /*!< Filter bit 4 */ +#define CAN_F12R2_FB5 ((uint32_t)0x00000020) /*!< Filter bit 5 */ +#define CAN_F12R2_FB6 ((uint32_t)0x00000040) /*!< Filter bit 6 */ +#define CAN_F12R2_FB7 ((uint32_t)0x00000080) /*!< Filter bit 7 */ +#define CAN_F12R2_FB8 ((uint32_t)0x00000100) /*!< Filter bit 8 */ +#define CAN_F12R2_FB9 ((uint32_t)0x00000200) /*!< Filter bit 9 */ +#define CAN_F12R2_FB10 ((uint32_t)0x00000400) /*!< Filter bit 10 */ +#define CAN_F12R2_FB11 ((uint32_t)0x00000800) /*!< Filter bit 11 */ +#define CAN_F12R2_FB12 ((uint32_t)0x00001000) /*!< Filter bit 12 */ +#define CAN_F12R2_FB13 ((uint32_t)0x00002000) /*!< Filter bit 13 */ +#define CAN_F12R2_FB14 ((uint32_t)0x00004000) /*!< Filter bit 14 */ +#define CAN_F12R2_FB15 ((uint32_t)0x00008000) /*!< Filter bit 15 */ +#define CAN_F12R2_FB16 ((uint32_t)0x00010000) /*!< Filter bit 16 */ +#define CAN_F12R2_FB17 ((uint32_t)0x00020000) /*!< Filter bit 17 */ +#define CAN_F12R2_FB18 ((uint32_t)0x00040000) /*!< Filter bit 18 */ +#define CAN_F12R2_FB19 ((uint32_t)0x00080000) /*!< Filter bit 19 */ +#define CAN_F12R2_FB20 ((uint32_t)0x00100000) /*!< Filter bit 20 */ +#define CAN_F12R2_FB21 ((uint32_t)0x00200000) /*!< Filter bit 21 */ +#define CAN_F12R2_FB22 ((uint32_t)0x00400000) /*!< Filter bit 22 */ +#define CAN_F12R2_FB23 ((uint32_t)0x00800000) /*!< Filter bit 23 */ +#define CAN_F12R2_FB24 ((uint32_t)0x01000000) /*!< Filter bit 24 */ +#define CAN_F12R2_FB25 ((uint32_t)0x02000000) /*!< Filter bit 25 */ +#define CAN_F12R2_FB26 ((uint32_t)0x04000000) /*!< Filter bit 26 */ +#define CAN_F12R2_FB27 ((uint32_t)0x08000000) /*!< Filter bit 27 */ +#define CAN_F12R2_FB28 ((uint32_t)0x10000000) /*!< Filter bit 28 */ +#define CAN_F12R2_FB29 ((uint32_t)0x20000000) /*!< Filter bit 29 */ +#define CAN_F12R2_FB30 ((uint32_t)0x40000000) /*!< Filter bit 30 */ +#define CAN_F12R2_FB31 ((uint32_t)0x80000000) /*!< Filter bit 31 */ + +/******************* Bit definition for CAN_F13R2 register ******************/ +#define CAN_F13R2_FB0 ((uint32_t)0x00000001) /*!< Filter bit 0 */ +#define CAN_F13R2_FB1 ((uint32_t)0x00000002) /*!< Filter bit 1 */ +#define CAN_F13R2_FB2 ((uint32_t)0x00000004) /*!< Filter bit 2 */ +#define CAN_F13R2_FB3 ((uint32_t)0x00000008) /*!< Filter bit 3 */ +#define CAN_F13R2_FB4 ((uint32_t)0x00000010) /*!< Filter bit 4 */ +#define CAN_F13R2_FB5 ((uint32_t)0x00000020) /*!< Filter bit 5 */ +#define CAN_F13R2_FB6 ((uint32_t)0x00000040) /*!< Filter bit 6 */ +#define CAN_F13R2_FB7 ((uint32_t)0x00000080) /*!< Filter bit 7 */ +#define CAN_F13R2_FB8 ((uint32_t)0x00000100) /*!< Filter bit 8 */ +#define CAN_F13R2_FB9 ((uint32_t)0x00000200) /*!< Filter bit 9 */ +#define CAN_F13R2_FB10 ((uint32_t)0x00000400) /*!< Filter bit 10 */ +#define CAN_F13R2_FB11 ((uint32_t)0x00000800) /*!< Filter bit 11 */ +#define CAN_F13R2_FB12 ((uint32_t)0x00001000) /*!< Filter bit 12 */ +#define CAN_F13R2_FB13 ((uint32_t)0x00002000) /*!< Filter bit 13 */ +#define CAN_F13R2_FB14 ((uint32_t)0x00004000) /*!< Filter bit 14 */ +#define CAN_F13R2_FB15 ((uint32_t)0x00008000) /*!< Filter bit 15 */ +#define CAN_F13R2_FB16 ((uint32_t)0x00010000) /*!< Filter bit 16 */ +#define CAN_F13R2_FB17 ((uint32_t)0x00020000) /*!< Filter bit 17 */ +#define CAN_F13R2_FB18 ((uint32_t)0x00040000) /*!< Filter bit 18 */ +#define CAN_F13R2_FB19 ((uint32_t)0x00080000) /*!< Filter bit 19 */ +#define CAN_F13R2_FB20 ((uint32_t)0x00100000) /*!< Filter bit 20 */ +#define CAN_F13R2_FB21 ((uint32_t)0x00200000) /*!< Filter bit 21 */ +#define CAN_F13R2_FB22 ((uint32_t)0x00400000) /*!< Filter bit 22 */ +#define CAN_F13R2_FB23 ((uint32_t)0x00800000) /*!< Filter bit 23 */ +#define CAN_F13R2_FB24 ((uint32_t)0x01000000) /*!< Filter bit 24 */ +#define CAN_F13R2_FB25 ((uint32_t)0x02000000) /*!< Filter bit 25 */ +#define CAN_F13R2_FB26 ((uint32_t)0x04000000) /*!< Filter bit 26 */ +#define CAN_F13R2_FB27 ((uint32_t)0x08000000) /*!< Filter bit 27 */ +#define CAN_F13R2_FB28 ((uint32_t)0x10000000) /*!< Filter bit 28 */ +#define CAN_F13R2_FB29 ((uint32_t)0x20000000) /*!< Filter bit 29 */ +#define CAN_F13R2_FB30 ((uint32_t)0x40000000) /*!< Filter bit 30 */ +#define CAN_F13R2_FB31 ((uint32_t)0x80000000) /*!< Filter bit 31 */ + +/******************************************************************************/ +/* */ +/* Serial Peripheral Interface */ +/* */ +/******************************************************************************/ + +/******************* Bit definition for SPI_CR1 register ********************/ +#define SPI_CR1_CPHA ((uint16_t)0x0001) /*!< Clock Phase */ +#define SPI_CR1_CPOL ((uint16_t)0x0002) /*!< Clock Polarity */ +#define SPI_CR1_MSTR ((uint16_t)0x0004) /*!< Master Selection */ + +#define SPI_CR1_BR ((uint16_t)0x0038) /*!< BR[2:0] bits (Baud Rate Control) */ +#define SPI_CR1_BR_0 ((uint16_t)0x0008) /*!< Bit 0 */ +#define SPI_CR1_BR_1 ((uint16_t)0x0010) /*!< Bit 1 */ +#define SPI_CR1_BR_2 ((uint16_t)0x0020) /*!< Bit 2 */ + +#define SPI_CR1_SPE ((uint16_t)0x0040) /*!< SPI Enable */ +#define SPI_CR1_LSBFIRST ((uint16_t)0x0080) /*!< Frame Format */ +#define SPI_CR1_SSI ((uint16_t)0x0100) /*!< Internal slave select */ +#define SPI_CR1_SSM ((uint16_t)0x0200) /*!< Software slave management */ +#define SPI_CR1_RXONLY ((uint16_t)0x0400) /*!< Receive only */ +#define SPI_CR1_DFF ((uint16_t)0x0800) /*!< Data Frame Format */ +#define SPI_CR1_CRCNEXT ((uint16_t)0x1000) /*!< Transmit CRC next */ +#define SPI_CR1_CRCEN ((uint16_t)0x2000) /*!< Hardware CRC calculation enable */ +#define SPI_CR1_BIDIOE ((uint16_t)0x4000) /*!< Output enable in bidirectional mode */ +#define SPI_CR1_BIDIMODE ((uint16_t)0x8000) /*!< Bidirectional data mode enable */ + +/******************* Bit definition for SPI_CR2 register ********************/ +#define SPI_CR2_RXDMAEN ((uint8_t)0x01) /*!< Rx Buffer DMA Enable */ +#define SPI_CR2_TXDMAEN ((uint8_t)0x02) /*!< Tx Buffer DMA Enable */ +#define SPI_CR2_SSOE ((uint8_t)0x04) /*!< SS Output Enable */ +#define SPI_CR2_ERRIE ((uint8_t)0x20) /*!< Error Interrupt Enable */ +#define SPI_CR2_RXNEIE ((uint8_t)0x40) /*!< RX buffer Not Empty Interrupt Enable */ +#define SPI_CR2_TXEIE ((uint8_t)0x80) /*!< Tx buffer Empty Interrupt Enable */ + +/******************** Bit definition for SPI_SR register ********************/ +#define SPI_SR_RXNE ((uint8_t)0x01) /*!< Receive buffer Not Empty */ +#define SPI_SR_TXE ((uint8_t)0x02) /*!< Transmit buffer Empty */ +#define SPI_SR_CHSIDE ((uint8_t)0x04) /*!< Channel side */ +#define SPI_SR_UDR ((uint8_t)0x08) /*!< Underrun flag */ +#define SPI_SR_CRCERR ((uint8_t)0x10) /*!< CRC Error flag */ +#define SPI_SR_MODF ((uint8_t)0x20) /*!< Mode fault */ +#define SPI_SR_OVR ((uint8_t)0x40) /*!< Overrun flag */ +#define SPI_SR_BSY ((uint8_t)0x80) /*!< Busy flag */ + +/******************** Bit definition for SPI_DR register ********************/ +#define SPI_DR_DR ((uint16_t)0xFFFF) /*!< Data Register */ + +/******************* Bit definition for SPI_CRCPR register ******************/ +#define SPI_CRCPR_CRCPOLY ((uint16_t)0xFFFF) /*!< CRC polynomial register */ + +/****************** Bit definition for SPI_RXCRCR register ******************/ +#define SPI_RXCRCR_RXCRC ((uint16_t)0xFFFF) /*!< Rx CRC Register */ + +/****************** Bit definition for SPI_TXCRCR register ******************/ +#define SPI_TXCRCR_TXCRC ((uint16_t)0xFFFF) /*!< Tx CRC Register */ + +/****************** Bit definition for SPI_I2SCFGR register *****************/ +#define SPI_I2SCFGR_CHLEN ((uint16_t)0x0001) /*!< Channel length (number of bits per audio channel) */ + +#define SPI_I2SCFGR_DATLEN ((uint16_t)0x0006) /*!< DATLEN[1:0] bits (Data length to be transferred) */ +#define SPI_I2SCFGR_DATLEN_0 ((uint16_t)0x0002) /*!< Bit 0 */ +#define SPI_I2SCFGR_DATLEN_1 ((uint16_t)0x0004) /*!< Bit 1 */ + +#define SPI_I2SCFGR_CKPOL ((uint16_t)0x0008) /*!< steady state clock polarity */ + +#define SPI_I2SCFGR_I2SSTD ((uint16_t)0x0030) /*!< I2SSTD[1:0] bits (I2S standard selection) */ +#define SPI_I2SCFGR_I2SSTD_0 ((uint16_t)0x0010) /*!< Bit 0 */ +#define SPI_I2SCFGR_I2SSTD_1 ((uint16_t)0x0020) /*!< Bit 1 */ + +#define SPI_I2SCFGR_PCMSYNC ((uint16_t)0x0080) /*!< PCM frame synchronization */ + +#define SPI_I2SCFGR_I2SCFG ((uint16_t)0x0300) /*!< I2SCFG[1:0] bits (I2S configuration mode) */ +#define SPI_I2SCFGR_I2SCFG_0 ((uint16_t)0x0100) /*!< Bit 0 */ +#define SPI_I2SCFGR_I2SCFG_1 ((uint16_t)0x0200) /*!< Bit 1 */ + +#define SPI_I2SCFGR_I2SE ((uint16_t)0x0400) /*!< I2S Enable */ +#define SPI_I2SCFGR_I2SMOD ((uint16_t)0x0800) /*!< I2S mode selection */ + +/****************** Bit definition for SPI_I2SPR register *******************/ +#define SPI_I2SPR_I2SDIV ((uint16_t)0x00FF) /*!< I2S Linear prescaler */ +#define SPI_I2SPR_ODD ((uint16_t)0x0100) /*!< Odd factor for the prescaler */ +#define SPI_I2SPR_MCKOE ((uint16_t)0x0200) /*!< Master Clock Output Enable */ + +/******************************************************************************/ +/* */ +/* Inter-integrated Circuit Interface */ +/* */ +/******************************************************************************/ + +/******************* Bit definition for I2C_CR1 register ********************/ +#define I2C_CR1_PE ((uint16_t)0x0001) /*!< Peripheral Enable */ +#define I2C_CR1_SMBUS ((uint16_t)0x0002) /*!< SMBus Mode */ +#define I2C_CR1_SMBTYPE ((uint16_t)0x0008) /*!< SMBus Type */ +#define I2C_CR1_ENARP ((uint16_t)0x0010) /*!< ARP Enable */ +#define I2C_CR1_ENPEC ((uint16_t)0x0020) /*!< PEC Enable */ +#define I2C_CR1_ENGC ((uint16_t)0x0040) /*!< General Call Enable */ +#define I2C_CR1_NOSTRETCH ((uint16_t)0x0080) /*!< Clock Stretching Disable (Slave mode) */ +#define I2C_CR1_START ((uint16_t)0x0100) /*!< Start Generation */ +#define I2C_CR1_STOP ((uint16_t)0x0200) /*!< Stop Generation */ +#define I2C_CR1_ACK ((uint16_t)0x0400) /*!< Acknowledge Enable */ +#define I2C_CR1_POS ((uint16_t)0x0800) /*!< Acknowledge/PEC Position (for data reception) */ +#define I2C_CR1_PEC ((uint16_t)0x1000) /*!< Packet Error Checking */ +#define I2C_CR1_ALERT ((uint16_t)0x2000) /*!< SMBus Alert */ +#define I2C_CR1_SWRST ((uint16_t)0x8000) /*!< Software Reset */ + +/******************* Bit definition for I2C_CR2 register ********************/ +#define I2C_CR2_FREQ ((uint16_t)0x003F) /*!< FREQ[5:0] bits (Peripheral Clock Frequency) */ +#define I2C_CR2_FREQ_0 ((uint16_t)0x0001) /*!< Bit 0 */ +#define I2C_CR2_FREQ_1 ((uint16_t)0x0002) /*!< Bit 1 */ +#define I2C_CR2_FREQ_2 ((uint16_t)0x0004) /*!< Bit 2 */ +#define I2C_CR2_FREQ_3 ((uint16_t)0x0008) /*!< Bit 3 */ +#define I2C_CR2_FREQ_4 ((uint16_t)0x0010) /*!< Bit 4 */ +#define I2C_CR2_FREQ_5 ((uint16_t)0x0020) /*!< Bit 5 */ + +#define I2C_CR2_ITERREN ((uint16_t)0x0100) /*!< Error Interrupt Enable */ +#define I2C_CR2_ITEVTEN ((uint16_t)0x0200) /*!< Event Interrupt Enable */ +#define I2C_CR2_ITBUFEN ((uint16_t)0x0400) /*!< Buffer Interrupt Enable */ +#define I2C_CR2_DMAEN ((uint16_t)0x0800) /*!< DMA Requests Enable */ +#define I2C_CR2_LAST ((uint16_t)0x1000) /*!< DMA Last Transfer */ + +/******************* Bit definition for I2C_OAR1 register *******************/ +#define I2C_OAR1_ADD1_7 ((uint16_t)0x00FE) /*!< Interface Address */ +#define I2C_OAR1_ADD8_9 ((uint16_t)0x0300) /*!< Interface Address */ + +#define I2C_OAR1_ADD0 ((uint16_t)0x0001) /*!< Bit 0 */ +#define I2C_OAR1_ADD1 ((uint16_t)0x0002) /*!< Bit 1 */ +#define I2C_OAR1_ADD2 ((uint16_t)0x0004) /*!< Bit 2 */ +#define I2C_OAR1_ADD3 ((uint16_t)0x0008) /*!< Bit 3 */ +#define I2C_OAR1_ADD4 ((uint16_t)0x0010) /*!< Bit 4 */ +#define I2C_OAR1_ADD5 ((uint16_t)0x0020) /*!< Bit 5 */ +#define I2C_OAR1_ADD6 ((uint16_t)0x0040) /*!< Bit 6 */ +#define I2C_OAR1_ADD7 ((uint16_t)0x0080) /*!< Bit 7 */ +#define I2C_OAR1_ADD8 ((uint16_t)0x0100) /*!< Bit 8 */ +#define I2C_OAR1_ADD9 ((uint16_t)0x0200) /*!< Bit 9 */ + +#define I2C_OAR1_ADDMODE ((uint16_t)0x8000) /*!< Addressing Mode (Slave mode) */ + +/******************* Bit definition for I2C_OAR2 register *******************/ +#define I2C_OAR2_ENDUAL ((uint8_t)0x01) /*!< Dual addressing mode enable */ +#define I2C_OAR2_ADD2 ((uint8_t)0xFE) /*!< Interface address */ + +/******************** Bit definition for I2C_DR register ********************/ +#define I2C_DR_DR ((uint8_t)0xFF) /*!< 8-bit Data Register */ + +/******************* Bit definition for I2C_SR1 register ********************/ +#define I2C_SR1_SB ((uint16_t)0x0001) /*!< Start Bit (Master mode) */ +#define I2C_SR1_ADDR ((uint16_t)0x0002) /*!< Address sent (master mode)/matched (slave mode) */ +#define I2C_SR1_BTF ((uint16_t)0x0004) /*!< Byte Transfer Finished */ +#define I2C_SR1_ADD10 ((uint16_t)0x0008) /*!< 10-bit header sent (Master mode) */ +#define I2C_SR1_STOPF ((uint16_t)0x0010) /*!< Stop detection (Slave mode) */ +#define I2C_SR1_RXNE ((uint16_t)0x0040) /*!< Data Register not Empty (receivers) */ +#define I2C_SR1_TXE ((uint16_t)0x0080) /*!< Data Register Empty (transmitters) */ +#define I2C_SR1_BERR ((uint16_t)0x0100) /*!< Bus Error */ +#define I2C_SR1_ARLO ((uint16_t)0x0200) /*!< Arbitration Lost (master mode) */ +#define I2C_SR1_AF ((uint16_t)0x0400) /*!< Acknowledge Failure */ +#define I2C_SR1_OVR ((uint16_t)0x0800) /*!< Overrun/Underrun */ +#define I2C_SR1_PECERR ((uint16_t)0x1000) /*!< PEC Error in reception */ +#define I2C_SR1_TIMEOUT ((uint16_t)0x4000) /*!< Timeout or Tlow Error */ +#define I2C_SR1_SMBALERT ((uint16_t)0x8000) /*!< SMBus Alert */ + +/******************* Bit definition for I2C_SR2 register ********************/ +#define I2C_SR2_MSL ((uint16_t)0x0001) /*!< Master/Slave */ +#define I2C_SR2_BUSY ((uint16_t)0x0002) /*!< Bus Busy */ +#define I2C_SR2_TRA ((uint16_t)0x0004) /*!< Transmitter/Receiver */ +#define I2C_SR2_GENCALL ((uint16_t)0x0010) /*!< General Call Address (Slave mode) */ +#define I2C_SR2_SMBDEFAULT ((uint16_t)0x0020) /*!< SMBus Device Default Address (Slave mode) */ +#define I2C_SR2_SMBHOST ((uint16_t)0x0040) /*!< SMBus Host Header (Slave mode) */ +#define I2C_SR2_DUALF ((uint16_t)0x0080) /*!< Dual Flag (Slave mode) */ +#define I2C_SR2_PEC ((uint16_t)0xFF00) /*!< Packet Error Checking Register */ + +/******************* Bit definition for I2C_CCR register ********************/ +#define I2C_CCR_CCR ((uint16_t)0x0FFF) /*!< Clock Control Register in Fast/Standard mode (Master mode) */ +#define I2C_CCR_DUTY ((uint16_t)0x4000) /*!< Fast Mode Duty Cycle */ +#define I2C_CCR_FS ((uint16_t)0x8000) /*!< I2C Master Mode Selection */ + +/****************** Bit definition for I2C_TRISE register *******************/ +#define I2C_TRISE_TRISE ((uint8_t)0x3F) /*!< Maximum Rise Time in Fast/Standard mode (Master mode) */ + +/******************************************************************************/ +/* */ +/* Universal Synchronous Asynchronous Receiver Transmitter */ +/* */ +/******************************************************************************/ + +/******************* Bit definition for USART_SR register *******************/ +#define USART_SR_PE ((uint16_t)0x0001) /*!< Parity Error */ +#define USART_SR_FE ((uint16_t)0x0002) /*!< Framing Error */ +#define USART_SR_NE ((uint16_t)0x0004) /*!< Noise Error Flag */ +#define USART_SR_ORE ((uint16_t)0x0008) /*!< OverRun Error */ +#define USART_SR_IDLE ((uint16_t)0x0010) /*!< IDLE line detected */ +#define USART_SR_RXNE ((uint16_t)0x0020) /*!< Read Data Register Not Empty */ +#define USART_SR_TC ((uint16_t)0x0040) /*!< Transmission Complete */ +#define USART_SR_TXE ((uint16_t)0x0080) /*!< Transmit Data Register Empty */ +#define USART_SR_LBD ((uint16_t)0x0100) /*!< LIN Break Detection Flag */ +#define USART_SR_CTS ((uint16_t)0x0200) /*!< CTS Flag */ + +/******************* Bit definition for USART_DR register *******************/ +#define USART_DR_DR ((uint16_t)0x01FF) /*!< Data value */ + +/****************** Bit definition for USART_BRR register *******************/ +#define USART_BRR_DIV_Fraction ((uint16_t)0x000F) /*!< Fraction of USARTDIV */ +#define USART_BRR_DIV_Mantissa ((uint16_t)0xFFF0) /*!< Mantissa of USARTDIV */ + +/****************** Bit definition for USART_CR1 register *******************/ +#define USART_CR1_SBK ((uint16_t)0x0001) /*!< Send Break */ +#define USART_CR1_RWU ((uint16_t)0x0002) /*!< Receiver wakeup */ +#define USART_CR1_RE ((uint16_t)0x0004) /*!< Receiver Enable */ +#define USART_CR1_TE ((uint16_t)0x0008) /*!< Transmitter Enable */ +#define USART_CR1_IDLEIE ((uint16_t)0x0010) /*!< IDLE Interrupt Enable */ +#define USART_CR1_RXNEIE ((uint16_t)0x0020) /*!< RXNE Interrupt Enable */ +#define USART_CR1_TCIE ((uint16_t)0x0040) /*!< Transmission Complete Interrupt Enable */ +#define USART_CR1_TXEIE ((uint16_t)0x0080) /*!< PE Interrupt Enable */ +#define USART_CR1_PEIE ((uint16_t)0x0100) /*!< PE Interrupt Enable */ +#define USART_CR1_PS ((uint16_t)0x0200) /*!< Parity Selection */ +#define USART_CR1_PCE ((uint16_t)0x0400) /*!< Parity Control Enable */ +#define USART_CR1_WAKE ((uint16_t)0x0800) /*!< Wakeup method */ +#define USART_CR1_M ((uint16_t)0x1000) /*!< Word length */ +#define USART_CR1_UE ((uint16_t)0x2000) /*!< USART Enable */ +#define USART_CR1_OVER8 ((uint16_t)0x8000) /*!< USART Oversmapling 8-bits */ + +/****************** Bit definition for USART_CR2 register *******************/ +#define USART_CR2_ADD ((uint16_t)0x000F) /*!< Address of the USART node */ +#define USART_CR2_LBDL ((uint16_t)0x0020) /*!< LIN Break Detection Length */ +#define USART_CR2_LBDIE ((uint16_t)0x0040) /*!< LIN Break Detection Interrupt Enable */ +#define USART_CR2_LBCL ((uint16_t)0x0100) /*!< Last Bit Clock pulse */ +#define USART_CR2_CPHA ((uint16_t)0x0200) /*!< Clock Phase */ +#define USART_CR2_CPOL ((uint16_t)0x0400) /*!< Clock Polarity */ +#define USART_CR2_CLKEN ((uint16_t)0x0800) /*!< Clock Enable */ + +#define USART_CR2_STOP ((uint16_t)0x3000) /*!< STOP[1:0] bits (STOP bits) */ +#define USART_CR2_STOP_0 ((uint16_t)0x1000) /*!< Bit 0 */ +#define USART_CR2_STOP_1 ((uint16_t)0x2000) /*!< Bit 1 */ + +#define USART_CR2_LINEN ((uint16_t)0x4000) /*!< LIN mode enable */ + +/****************** Bit definition for USART_CR3 register *******************/ +#define USART_CR3_EIE ((uint16_t)0x0001) /*!< Error Interrupt Enable */ +#define USART_CR3_IREN ((uint16_t)0x0002) /*!< IrDA mode Enable */ +#define USART_CR3_IRLP ((uint16_t)0x0004) /*!< IrDA Low-Power */ +#define USART_CR3_HDSEL ((uint16_t)0x0008) /*!< Half-Duplex Selection */ +#define USART_CR3_NACK ((uint16_t)0x0010) /*!< Smartcard NACK enable */ +#define USART_CR3_SCEN ((uint16_t)0x0020) /*!< Smartcard mode enable */ +#define USART_CR3_DMAR ((uint16_t)0x0040) /*!< DMA Enable Receiver */ +#define USART_CR3_DMAT ((uint16_t)0x0080) /*!< DMA Enable Transmitter */ +#define USART_CR3_RTSE ((uint16_t)0x0100) /*!< RTS Enable */ +#define USART_CR3_CTSE ((uint16_t)0x0200) /*!< CTS Enable */ +#define USART_CR3_CTSIE ((uint16_t)0x0400) /*!< CTS Interrupt Enable */ +#define USART_CR3_ONEBIT ((uint16_t)0x0800) /*!< One Bit method */ + +/****************** Bit definition for USART_GTPR register ******************/ +#define USART_GTPR_PSC ((uint16_t)0x00FF) /*!< PSC[7:0] bits (Prescaler value) */ +#define USART_GTPR_PSC_0 ((uint16_t)0x0001) /*!< Bit 0 */ +#define USART_GTPR_PSC_1 ((uint16_t)0x0002) /*!< Bit 1 */ +#define USART_GTPR_PSC_2 ((uint16_t)0x0004) /*!< Bit 2 */ +#define USART_GTPR_PSC_3 ((uint16_t)0x0008) /*!< Bit 3 */ +#define USART_GTPR_PSC_4 ((uint16_t)0x0010) /*!< Bit 4 */ +#define USART_GTPR_PSC_5 ((uint16_t)0x0020) /*!< Bit 5 */ +#define USART_GTPR_PSC_6 ((uint16_t)0x0040) /*!< Bit 6 */ +#define USART_GTPR_PSC_7 ((uint16_t)0x0080) /*!< Bit 7 */ + +#define USART_GTPR_GT ((uint16_t)0xFF00) /*!< Guard time value */ + +/******************************************************************************/ +/* */ +/* Debug MCU */ +/* */ +/******************************************************************************/ + +/**************** Bit definition for DBGMCU_IDCODE register *****************/ +#define DBGMCU_IDCODE_DEV_ID ((uint32_t)0x00000FFF) /*!< Device Identifier */ + +#define DBGMCU_IDCODE_REV_ID ((uint32_t)0xFFFF0000) /*!< REV_ID[15:0] bits (Revision Identifier) */ +#define DBGMCU_IDCODE_REV_ID_0 ((uint32_t)0x00010000) /*!< Bit 0 */ +#define DBGMCU_IDCODE_REV_ID_1 ((uint32_t)0x00020000) /*!< Bit 1 */ +#define DBGMCU_IDCODE_REV_ID_2 ((uint32_t)0x00040000) /*!< Bit 2 */ +#define DBGMCU_IDCODE_REV_ID_3 ((uint32_t)0x00080000) /*!< Bit 3 */ +#define DBGMCU_IDCODE_REV_ID_4 ((uint32_t)0x00100000) /*!< Bit 4 */ +#define DBGMCU_IDCODE_REV_ID_5 ((uint32_t)0x00200000) /*!< Bit 5 */ +#define DBGMCU_IDCODE_REV_ID_6 ((uint32_t)0x00400000) /*!< Bit 6 */ +#define DBGMCU_IDCODE_REV_ID_7 ((uint32_t)0x00800000) /*!< Bit 7 */ +#define DBGMCU_IDCODE_REV_ID_8 ((uint32_t)0x01000000) /*!< Bit 8 */ +#define DBGMCU_IDCODE_REV_ID_9 ((uint32_t)0x02000000) /*!< Bit 9 */ +#define DBGMCU_IDCODE_REV_ID_10 ((uint32_t)0x04000000) /*!< Bit 10 */ +#define DBGMCU_IDCODE_REV_ID_11 ((uint32_t)0x08000000) /*!< Bit 11 */ +#define DBGMCU_IDCODE_REV_ID_12 ((uint32_t)0x10000000) /*!< Bit 12 */ +#define DBGMCU_IDCODE_REV_ID_13 ((uint32_t)0x20000000) /*!< Bit 13 */ +#define DBGMCU_IDCODE_REV_ID_14 ((uint32_t)0x40000000) /*!< Bit 14 */ +#define DBGMCU_IDCODE_REV_ID_15 ((uint32_t)0x80000000) /*!< Bit 15 */ + +/****************** Bit definition for DBGMCU_CR register *******************/ +#define DBGMCU_CR_DBG_SLEEP ((uint32_t)0x00000001) /*!< Debug Sleep Mode */ +#define DBGMCU_CR_DBG_STOP ((uint32_t)0x00000002) /*!< Debug Stop Mode */ +#define DBGMCU_CR_DBG_STANDBY ((uint32_t)0x00000004) /*!< Debug Standby mode */ +#define DBGMCU_CR_TRACE_IOEN ((uint32_t)0x00000020) /*!< Trace Pin Assignment Control */ + +#define DBGMCU_CR_TRACE_MODE ((uint32_t)0x000000C0) /*!< TRACE_MODE[1:0] bits (Trace Pin Assignment Control) */ +#define DBGMCU_CR_TRACE_MODE_0 ((uint32_t)0x00000040) /*!< Bit 0 */ +#define DBGMCU_CR_TRACE_MODE_1 ((uint32_t)0x00000080) /*!< Bit 1 */ + +#define DBGMCU_CR_DBG_IWDG_STOP ((uint32_t)0x00000100) /*!< Debug Independent Watchdog stopped when Core is halted */ +#define DBGMCU_CR_DBG_WWDG_STOP ((uint32_t)0x00000200) /*!< Debug Window Watchdog stopped when Core is halted */ +#define DBGMCU_CR_DBG_TIM1_STOP ((uint32_t)0x00000400) /*!< TIM1 counter stopped when core is halted */ +#define DBGMCU_CR_DBG_TIM2_STOP ((uint32_t)0x00000800) /*!< TIM2 counter stopped when core is halted */ +#define DBGMCU_CR_DBG_TIM3_STOP ((uint32_t)0x00001000) /*!< TIM3 counter stopped when core is halted */ +#define DBGMCU_CR_DBG_TIM4_STOP ((uint32_t)0x00002000) /*!< TIM4 counter stopped when core is halted */ +#define DBGMCU_CR_DBG_CAN1_STOP ((uint32_t)0x00004000) /*!< Debug CAN1 stopped when Core is halted */ +#define DBGMCU_CR_DBG_I2C1_SMBUS_TIMEOUT ((uint32_t)0x00008000) /*!< SMBUS timeout mode stopped when Core is halted */ +#define DBGMCU_CR_DBG_I2C2_SMBUS_TIMEOUT ((uint32_t)0x00010000) /*!< SMBUS timeout mode stopped when Core is halted */ +#define DBGMCU_CR_DBG_TIM8_STOP ((uint32_t)0x00020000) /*!< TIM8 counter stopped when core is halted */ +#define DBGMCU_CR_DBG_TIM5_STOP ((uint32_t)0x00040000) /*!< TIM5 counter stopped when core is halted */ +#define DBGMCU_CR_DBG_TIM6_STOP ((uint32_t)0x00080000) /*!< TIM6 counter stopped when core is halted */ +#define DBGMCU_CR_DBG_TIM7_STOP ((uint32_t)0x00100000) /*!< TIM7 counter stopped when core is halted */ +#define DBGMCU_CR_DBG_CAN2_STOP ((uint32_t)0x00200000) /*!< Debug CAN2 stopped when Core is halted */ +#define DBGMCU_CR_DBG_TIM15_STOP ((uint32_t)0x00400000) /*!< Debug TIM15 stopped when Core is halted */ +#define DBGMCU_CR_DBG_TIM16_STOP ((uint32_t)0x00800000) /*!< Debug TIM16 stopped when Core is halted */ +#define DBGMCU_CR_DBG_TIM17_STOP ((uint32_t)0x01000000) /*!< Debug TIM17 stopped when Core is halted */ +#define DBGMCU_CR_DBG_TIM12_STOP ((uint32_t)0x02000000) /*!< Debug TIM12 stopped when Core is halted */ +#define DBGMCU_CR_DBG_TIM13_STOP ((uint32_t)0x04000000) /*!< Debug TIM13 stopped when Core is halted */ +#define DBGMCU_CR_DBG_TIM14_STOP ((uint32_t)0x08000000) /*!< Debug TIM14 stopped when Core is halted */ +#define DBGMCU_CR_DBG_TIM9_STOP ((uint32_t)0x10000000) /*!< Debug TIM9 stopped when Core is halted */ +#define DBGMCU_CR_DBG_TIM10_STOP ((uint32_t)0x20000000) /*!< Debug TIM10 stopped when Core is halted */ +#define DBGMCU_CR_DBG_TIM11_STOP ((uint32_t)0x40000000) /*!< Debug TIM11 stopped when Core is halted */ + +/******************************************************************************/ +/* */ +/* FLASH and Option Bytes Registers */ +/* */ +/******************************************************************************/ + +/******************* Bit definition for FLASH_ACR register ******************/ +#define FLASH_ACR_LATENCY ((uint8_t)0x03) /*!< LATENCY[2:0] bits (Latency) */ +#define FLASH_ACR_LATENCY_0 ((uint8_t)0x00) /*!< Bit 0 */ +#define FLASH_ACR_LATENCY_1 ((uint8_t)0x01) /*!< Bit 0 */ +#define FLASH_ACR_LATENCY_2 ((uint8_t)0x02) /*!< Bit 1 */ + +#define FLASH_ACR_HLFCYA ((uint8_t)0x08) /*!< Flash Half Cycle Access Enable */ +#define FLASH_ACR_PRFTBE ((uint8_t)0x10) /*!< Prefetch Buffer Enable */ +#define FLASH_ACR_PRFTBS ((uint8_t)0x20) /*!< Prefetch Buffer Status */ + +/****************** Bit definition for FLASH_KEYR register ******************/ +#define FLASH_KEYR_FKEYR ((uint32_t)0xFFFFFFFF) /*!< FPEC Key */ + +/****************** FLASH Keys **********************************************/ +#define RDP_Key ((uint16_t)0x00A5) +#define FLASH_KEY1 ((uint32_t)0x45670123) +#define FLASH_KEY2 ((uint32_t)0xCDEF89AB) + +/***************** Bit definition for FLASH_OPTKEYR register ****************/ +#define FLASH_OPTKEYR_OPTKEYR ((uint32_t)0xFFFFFFFF) /*!< Option Byte Key */ + +/****************** Bit definition for FLASH_SR register *******************/ +#define FLASH_SR_BSY ((uint8_t)0x01) /*!< Busy */ +#define FLASH_SR_PGERR ((uint8_t)0x04) /*!< Programming Error */ +#define FLASH_SR_WRPRTERR ((uint8_t)0x10) /*!< Write Protection Error */ +#define FLASH_SR_EOP ((uint8_t)0x20) /*!< End of operation */ + +/******************* Bit definition for FLASH_CR register *******************/ +#define FLASH_CR_PG ((uint16_t)0x0001) /*!< Programming */ +#define FLASH_CR_PER ((uint16_t)0x0002) /*!< Page Erase */ +#define FLASH_CR_MER ((uint16_t)0x0004) /*!< Mass Erase */ +#define FLASH_CR_OPTPG ((uint16_t)0x0010) /*!< Option Byte Programming */ +#define FLASH_CR_OPTER ((uint16_t)0x0020) /*!< Option Byte Erase */ +#define FLASH_CR_STRT ((uint16_t)0x0040) /*!< Start */ +#define FLASH_CR_LOCK ((uint16_t)0x0080) /*!< Lock */ +#define FLASH_CR_OPTWRE ((uint16_t)0x0200) /*!< Option Bytes Write Enable */ +#define FLASH_CR_ERRIE ((uint16_t)0x0400) /*!< Error Interrupt Enable */ +#define FLASH_CR_EOPIE ((uint16_t)0x1000) /*!< End of operation interrupt enable */ + +/******************* Bit definition for FLASH_AR register *******************/ +#define FLASH_AR_FAR ((uint32_t)0xFFFFFFFF) /*!< Flash Address */ + +/****************** Bit definition for FLASH_OBR register *******************/ +#define FLASH_OBR_OPTERR ((uint16_t)0x0001) /*!< Option Byte Error */ +#define FLASH_OBR_RDPRT ((uint16_t)0x0002) /*!< Read protection */ + +#define FLASH_OBR_USER ((uint16_t)0x03FC) /*!< User Option Bytes */ +#define FLASH_OBR_WDG_SW ((uint16_t)0x0004) /*!< WDG_SW */ +#define FLASH_OBR_nRST_STOP ((uint16_t)0x0008) /*!< nRST_STOP */ +#define FLASH_OBR_nRST_STDBY ((uint16_t)0x0010) /*!< nRST_STDBY */ +#define FLASH_OBR_BFB2 ((uint16_t)0x0020) /*!< BFB2 */ + +/****************** Bit definition for FLASH_WRPR register ******************/ +#define FLASH_WRPR_WRP ((uint32_t)0xFFFFFFFF) /*!< Write Protect */ + +/*----------------------------------------------------------------------------*/ + +/****************** Bit definition for FLASH_RDP register *******************/ +#define FLASH_RDP_RDP ((uint32_t)0x000000FF) /*!< Read protection option byte */ +#define FLASH_RDP_nRDP ((uint32_t)0x0000FF00) /*!< Read protection complemented option byte */ + +/****************** Bit definition for FLASH_USER register ******************/ +#define FLASH_USER_USER ((uint32_t)0x00FF0000) /*!< User option byte */ +#define FLASH_USER_nUSER ((uint32_t)0xFF000000) /*!< User complemented option byte */ + +/****************** Bit definition for FLASH_Data0 register *****************/ +#define FLASH_Data0_Data0 ((uint32_t)0x000000FF) /*!< User data storage option byte */ +#define FLASH_Data0_nData0 ((uint32_t)0x0000FF00) /*!< User data storage complemented option byte */ + +/****************** Bit definition for FLASH_Data1 register *****************/ +#define FLASH_Data1_Data1 ((uint32_t)0x00FF0000) /*!< User data storage option byte */ +#define FLASH_Data1_nData1 ((uint32_t)0xFF000000) /*!< User data storage complemented option byte */ + +/****************** Bit definition for FLASH_WRP0 register ******************/ +#define FLASH_WRP0_WRP0 ((uint32_t)0x000000FF) /*!< Flash memory write protection option bytes */ +#define FLASH_WRP0_nWRP0 ((uint32_t)0x0000FF00) /*!< Flash memory write protection complemented option bytes */ + +/****************** Bit definition for FLASH_WRP1 register ******************/ +#define FLASH_WRP1_WRP1 ((uint32_t)0x00FF0000) /*!< Flash memory write protection option bytes */ +#define FLASH_WRP1_nWRP1 ((uint32_t)0xFF000000) /*!< Flash memory write protection complemented option bytes */ + +/****************** Bit definition for FLASH_WRP2 register ******************/ +#define FLASH_WRP2_WRP2 ((uint32_t)0x000000FF) /*!< Flash memory write protection option bytes */ +#define FLASH_WRP2_nWRP2 ((uint32_t)0x0000FF00) /*!< Flash memory write protection complemented option bytes */ + +/****************** Bit definition for FLASH_WRP3 register ******************/ +#define FLASH_WRP3_WRP3 ((uint32_t)0x00FF0000) /*!< Flash memory write protection option bytes */ +#define FLASH_WRP3_nWRP3 ((uint32_t)0xFF000000) /*!< Flash memory write protection complemented option bytes */ + +#ifdef STM32F10X_CL +/******************************************************************************/ +/* Ethernet MAC Registers bits definitions */ +/******************************************************************************/ +/* Bit definition for Ethernet MAC Control Register register */ +#define ETH_MACCR_WD ((uint32_t)0x00800000) /* Watchdog disable */ +#define ETH_MACCR_JD ((uint32_t)0x00400000) /* Jabber disable */ +#define ETH_MACCR_IFG ((uint32_t)0x000E0000) /* Inter-frame gap */ + #define ETH_MACCR_IFG_96Bit ((uint32_t)0x00000000) /* Minimum IFG between frames during transmission is 96Bit */ + #define ETH_MACCR_IFG_88Bit ((uint32_t)0x00020000) /* Minimum IFG between frames during transmission is 88Bit */ + #define ETH_MACCR_IFG_80Bit ((uint32_t)0x00040000) /* Minimum IFG between frames during transmission is 80Bit */ + #define ETH_MACCR_IFG_72Bit ((uint32_t)0x00060000) /* Minimum IFG between frames during transmission is 72Bit */ + #define ETH_MACCR_IFG_64Bit ((uint32_t)0x00080000) /* Minimum IFG between frames during transmission is 64Bit */ + #define ETH_MACCR_IFG_56Bit ((uint32_t)0x000A0000) /* Minimum IFG between frames during transmission is 56Bit */ + #define ETH_MACCR_IFG_48Bit ((uint32_t)0x000C0000) /* Minimum IFG between frames during transmission is 48Bit */ + #define ETH_MACCR_IFG_40Bit ((uint32_t)0x000E0000) /* Minimum IFG between frames during transmission is 40Bit */ +#define ETH_MACCR_CSD ((uint32_t)0x00010000) /* Carrier sense disable (during transmission) */ +#define ETH_MACCR_FES ((uint32_t)0x00004000) /* Fast ethernet speed */ +#define ETH_MACCR_ROD ((uint32_t)0x00002000) /* Receive own disable */ +#define ETH_MACCR_LM ((uint32_t)0x00001000) /* loopback mode */ +#define ETH_MACCR_DM ((uint32_t)0x00000800) /* Duplex mode */ +#define ETH_MACCR_IPCO ((uint32_t)0x00000400) /* IP Checksum offload */ +#define ETH_MACCR_RD ((uint32_t)0x00000200) /* Retry disable */ +#define ETH_MACCR_APCS ((uint32_t)0x00000080) /* Automatic Pad/CRC stripping */ +#define ETH_MACCR_BL ((uint32_t)0x00000060) /* Back-off limit: random integer number (r) of slot time delays before rescheduling + a transmission attempt during retries after a collision: 0 =< r <2^k */ + #define ETH_MACCR_BL_10 ((uint32_t)0x00000000) /* k = min (n, 10) */ + #define ETH_MACCR_BL_8 ((uint32_t)0x00000020) /* k = min (n, 8) */ + #define ETH_MACCR_BL_4 ((uint32_t)0x00000040) /* k = min (n, 4) */ + #define ETH_MACCR_BL_1 ((uint32_t)0x00000060) /* k = min (n, 1) */ +#define ETH_MACCR_DC ((uint32_t)0x00000010) /* Defferal check */ +#define ETH_MACCR_TE ((uint32_t)0x00000008) /* Transmitter enable */ +#define ETH_MACCR_RE ((uint32_t)0x00000004) /* Receiver enable */ + +/* Bit definition for Ethernet MAC Frame Filter Register */ +#define ETH_MACFFR_RA ((uint32_t)0x80000000) /* Receive all */ +#define ETH_MACFFR_HPF ((uint32_t)0x00000400) /* Hash or perfect filter */ +#define ETH_MACFFR_SAF ((uint32_t)0x00000200) /* Source address filter enable */ +#define ETH_MACFFR_SAIF ((uint32_t)0x00000100) /* SA inverse filtering */ +#define ETH_MACFFR_PCF ((uint32_t)0x000000C0) /* Pass control frames: 3 cases */ + #define ETH_MACFFR_PCF_BlockAll ((uint32_t)0x00000040) /* MAC filters all control frames from reaching the application */ + #define ETH_MACFFR_PCF_ForwardAll ((uint32_t)0x00000080) /* MAC forwards all control frames to application even if they fail the Address Filter */ + #define ETH_MACFFR_PCF_ForwardPassedAddrFilter ((uint32_t)0x000000C0) /* MAC forwards control frames that pass the Address Filter. */ +#define ETH_MACFFR_BFD ((uint32_t)0x00000020) /* Broadcast frame disable */ +#define ETH_MACFFR_PAM ((uint32_t)0x00000010) /* Pass all mutlicast */ +#define ETH_MACFFR_DAIF ((uint32_t)0x00000008) /* DA Inverse filtering */ +#define ETH_MACFFR_HM ((uint32_t)0x00000004) /* Hash multicast */ +#define ETH_MACFFR_HU ((uint32_t)0x00000002) /* Hash unicast */ +#define ETH_MACFFR_PM ((uint32_t)0x00000001) /* Promiscuous mode */ + +/* Bit definition for Ethernet MAC Hash Table High Register */ +#define ETH_MACHTHR_HTH ((uint32_t)0xFFFFFFFF) /* Hash table high */ + +/* Bit definition for Ethernet MAC Hash Table Low Register */ +#define ETH_MACHTLR_HTL ((uint32_t)0xFFFFFFFF) /* Hash table low */ + +/* Bit definition for Ethernet MAC MII Address Register */ +#define ETH_MACMIIAR_PA ((uint32_t)0x0000F800) /* Physical layer address */ +#define ETH_MACMIIAR_MR ((uint32_t)0x000007C0) /* MII register in the selected PHY */ +#define ETH_MACMIIAR_CR ((uint32_t)0x0000001C) /* CR clock range: 6 cases */ + #define ETH_MACMIIAR_CR_Div42 ((uint32_t)0x00000000) /* HCLK:60-72 MHz; MDC clock= HCLK/42 */ + #define ETH_MACMIIAR_CR_Div16 ((uint32_t)0x00000008) /* HCLK:20-35 MHz; MDC clock= HCLK/16 */ + #define ETH_MACMIIAR_CR_Div26 ((uint32_t)0x0000000C) /* HCLK:35-60 MHz; MDC clock= HCLK/26 */ +#define ETH_MACMIIAR_MW ((uint32_t)0x00000002) /* MII write */ +#define ETH_MACMIIAR_MB ((uint32_t)0x00000001) /* MII busy */ + +/* Bit definition for Ethernet MAC MII Data Register */ +#define ETH_MACMIIDR_MD ((uint32_t)0x0000FFFF) /* MII data: read/write data from/to PHY */ + +/* Bit definition for Ethernet MAC Flow Control Register */ +#define ETH_MACFCR_PT ((uint32_t)0xFFFF0000) /* Pause time */ +#define ETH_MACFCR_ZQPD ((uint32_t)0x00000080) /* Zero-quanta pause disable */ +#define ETH_MACFCR_PLT ((uint32_t)0x00000030) /* Pause low threshold: 4 cases */ + #define ETH_MACFCR_PLT_Minus4 ((uint32_t)0x00000000) /* Pause time minus 4 slot times */ + #define ETH_MACFCR_PLT_Minus28 ((uint32_t)0x00000010) /* Pause time minus 28 slot times */ + #define ETH_MACFCR_PLT_Minus144 ((uint32_t)0x00000020) /* Pause time minus 144 slot times */ + #define ETH_MACFCR_PLT_Minus256 ((uint32_t)0x00000030) /* Pause time minus 256 slot times */ +#define ETH_MACFCR_UPFD ((uint32_t)0x00000008) /* Unicast pause frame detect */ +#define ETH_MACFCR_RFCE ((uint32_t)0x00000004) /* Receive flow control enable */ +#define ETH_MACFCR_TFCE ((uint32_t)0x00000002) /* Transmit flow control enable */ +#define ETH_MACFCR_FCBBPA ((uint32_t)0x00000001) /* Flow control busy/backpressure activate */ + +/* Bit definition for Ethernet MAC VLAN Tag Register */ +#define ETH_MACVLANTR_VLANTC ((uint32_t)0x00010000) /* 12-bit VLAN tag comparison */ +#define ETH_MACVLANTR_VLANTI ((uint32_t)0x0000FFFF) /* VLAN tag identifier (for receive frames) */ + +/* Bit definition for Ethernet MAC Remote Wake-UpFrame Filter Register */ +#define ETH_MACRWUFFR_D ((uint32_t)0xFFFFFFFF) /* Wake-up frame filter register data */ +/* Eight sequential Writes to this address (offset 0x28) will write all Wake-UpFrame Filter Registers. + Eight sequential Reads from this address (offset 0x28) will read all Wake-UpFrame Filter Registers. */ +/* Wake-UpFrame Filter Reg0 : Filter 0 Byte Mask + Wake-UpFrame Filter Reg1 : Filter 1 Byte Mask + Wake-UpFrame Filter Reg2 : Filter 2 Byte Mask + Wake-UpFrame Filter Reg3 : Filter 3 Byte Mask + Wake-UpFrame Filter Reg4 : RSVD - Filter3 Command - RSVD - Filter2 Command - + RSVD - Filter1 Command - RSVD - Filter0 Command + Wake-UpFrame Filter Re5 : Filter3 Offset - Filter2 Offset - Filter1 Offset - Filter0 Offset + Wake-UpFrame Filter Re6 : Filter1 CRC16 - Filter0 CRC16 + Wake-UpFrame Filter Re7 : Filter3 CRC16 - Filter2 CRC16 */ + +/* Bit definition for Ethernet MAC PMT Control and Status Register */ +#define ETH_MACPMTCSR_WFFRPR ((uint32_t)0x80000000) /* Wake-Up Frame Filter Register Pointer Reset */ +#define ETH_MACPMTCSR_GU ((uint32_t)0x00000200) /* Global Unicast */ +#define ETH_MACPMTCSR_WFR ((uint32_t)0x00000040) /* Wake-Up Frame Received */ +#define ETH_MACPMTCSR_MPR ((uint32_t)0x00000020) /* Magic Packet Received */ +#define ETH_MACPMTCSR_WFE ((uint32_t)0x00000004) /* Wake-Up Frame Enable */ +#define ETH_MACPMTCSR_MPE ((uint32_t)0x00000002) /* Magic Packet Enable */ +#define ETH_MACPMTCSR_PD ((uint32_t)0x00000001) /* Power Down */ + +/* Bit definition for Ethernet MAC Status Register */ +#define ETH_MACSR_TSTS ((uint32_t)0x00000200) /* Time stamp trigger status */ +#define ETH_MACSR_MMCTS ((uint32_t)0x00000040) /* MMC transmit status */ +#define ETH_MACSR_MMMCRS ((uint32_t)0x00000020) /* MMC receive status */ +#define ETH_MACSR_MMCS ((uint32_t)0x00000010) /* MMC status */ +#define ETH_MACSR_PMTS ((uint32_t)0x00000008) /* PMT status */ + +/* Bit definition for Ethernet MAC Interrupt Mask Register */ +#define ETH_MACIMR_TSTIM ((uint32_t)0x00000200) /* Time stamp trigger interrupt mask */ +#define ETH_MACIMR_PMTIM ((uint32_t)0x00000008) /* PMT interrupt mask */ + +/* Bit definition for Ethernet MAC Address0 High Register */ +#define ETH_MACA0HR_MACA0H ((uint32_t)0x0000FFFF) /* MAC address0 high */ + +/* Bit definition for Ethernet MAC Address0 Low Register */ +#define ETH_MACA0LR_MACA0L ((uint32_t)0xFFFFFFFF) /* MAC address0 low */ + +/* Bit definition for Ethernet MAC Address1 High Register */ +#define ETH_MACA1HR_AE ((uint32_t)0x80000000) /* Address enable */ +#define ETH_MACA1HR_SA ((uint32_t)0x40000000) /* Source address */ +#define ETH_MACA1HR_MBC ((uint32_t)0x3F000000) /* Mask byte control: bits to mask for comparison of the MAC Address bytes */ + #define ETH_MACA1HR_MBC_HBits15_8 ((uint32_t)0x20000000) /* Mask MAC Address high reg bits [15:8] */ + #define ETH_MACA1HR_MBC_HBits7_0 ((uint32_t)0x10000000) /* Mask MAC Address high reg bits [7:0] */ + #define ETH_MACA1HR_MBC_LBits31_24 ((uint32_t)0x08000000) /* Mask MAC Address low reg bits [31:24] */ + #define ETH_MACA1HR_MBC_LBits23_16 ((uint32_t)0x04000000) /* Mask MAC Address low reg bits [23:16] */ + #define ETH_MACA1HR_MBC_LBits15_8 ((uint32_t)0x02000000) /* Mask MAC Address low reg bits [15:8] */ + #define ETH_MACA1HR_MBC_LBits7_0 ((uint32_t)0x01000000) /* Mask MAC Address low reg bits [7:0] */ +#define ETH_MACA1HR_MACA1H ((uint32_t)0x0000FFFF) /* MAC address1 high */ + +/* Bit definition for Ethernet MAC Address1 Low Register */ +#define ETH_MACA1LR_MACA1L ((uint32_t)0xFFFFFFFF) /* MAC address1 low */ + +/* Bit definition for Ethernet MAC Address2 High Register */ +#define ETH_MACA2HR_AE ((uint32_t)0x80000000) /* Address enable */ +#define ETH_MACA2HR_SA ((uint32_t)0x40000000) /* Source address */ +#define ETH_MACA2HR_MBC ((uint32_t)0x3F000000) /* Mask byte control */ + #define ETH_MACA2HR_MBC_HBits15_8 ((uint32_t)0x20000000) /* Mask MAC Address high reg bits [15:8] */ + #define ETH_MACA2HR_MBC_HBits7_0 ((uint32_t)0x10000000) /* Mask MAC Address high reg bits [7:0] */ + #define ETH_MACA2HR_MBC_LBits31_24 ((uint32_t)0x08000000) /* Mask MAC Address low reg bits [31:24] */ + #define ETH_MACA2HR_MBC_LBits23_16 ((uint32_t)0x04000000) /* Mask MAC Address low reg bits [23:16] */ + #define ETH_MACA2HR_MBC_LBits15_8 ((uint32_t)0x02000000) /* Mask MAC Address low reg bits [15:8] */ + #define ETH_MACA2HR_MBC_LBits7_0 ((uint32_t)0x01000000) /* Mask MAC Address low reg bits [70] */ +#define ETH_MACA2HR_MACA2H ((uint32_t)0x0000FFFF) /* MAC address1 high */ + +/* Bit definition for Ethernet MAC Address2 Low Register */ +#define ETH_MACA2LR_MACA2L ((uint32_t)0xFFFFFFFF) /* MAC address2 low */ + +/* Bit definition for Ethernet MAC Address3 High Register */ +#define ETH_MACA3HR_AE ((uint32_t)0x80000000) /* Address enable */ +#define ETH_MACA3HR_SA ((uint32_t)0x40000000) /* Source address */ +#define ETH_MACA3HR_MBC ((uint32_t)0x3F000000) /* Mask byte control */ + #define ETH_MACA3HR_MBC_HBits15_8 ((uint32_t)0x20000000) /* Mask MAC Address high reg bits [15:8] */ + #define ETH_MACA3HR_MBC_HBits7_0 ((uint32_t)0x10000000) /* Mask MAC Address high reg bits [7:0] */ + #define ETH_MACA3HR_MBC_LBits31_24 ((uint32_t)0x08000000) /* Mask MAC Address low reg bits [31:24] */ + #define ETH_MACA3HR_MBC_LBits23_16 ((uint32_t)0x04000000) /* Mask MAC Address low reg bits [23:16] */ + #define ETH_MACA3HR_MBC_LBits15_8 ((uint32_t)0x02000000) /* Mask MAC Address low reg bits [15:8] */ + #define ETH_MACA3HR_MBC_LBits7_0 ((uint32_t)0x01000000) /* Mask MAC Address low reg bits [70] */ +#define ETH_MACA3HR_MACA3H ((uint32_t)0x0000FFFF) /* MAC address3 high */ + +/* Bit definition for Ethernet MAC Address3 Low Register */ +#define ETH_MACA3LR_MACA3L ((uint32_t)0xFFFFFFFF) /* MAC address3 low */ + +/******************************************************************************/ +/* Ethernet MMC Registers bits definition */ +/******************************************************************************/ + +/* Bit definition for Ethernet MMC Contol Register */ +#define ETH_MMCCR_MCF ((uint32_t)0x00000008) /* MMC Counter Freeze */ +#define ETH_MMCCR_ROR ((uint32_t)0x00000004) /* Reset on Read */ +#define ETH_MMCCR_CSR ((uint32_t)0x00000002) /* Counter Stop Rollover */ +#define ETH_MMCCR_CR ((uint32_t)0x00000001) /* Counters Reset */ + +/* Bit definition for Ethernet MMC Receive Interrupt Register */ +#define ETH_MMCRIR_RGUFS ((uint32_t)0x00020000) /* Set when Rx good unicast frames counter reaches half the maximum value */ +#define ETH_MMCRIR_RFAES ((uint32_t)0x00000040) /* Set when Rx alignment error counter reaches half the maximum value */ +#define ETH_MMCRIR_RFCES ((uint32_t)0x00000020) /* Set when Rx crc error counter reaches half the maximum value */ + +/* Bit definition for Ethernet MMC Transmit Interrupt Register */ +#define ETH_MMCTIR_TGFS ((uint32_t)0x00200000) /* Set when Tx good frame count counter reaches half the maximum value */ +#define ETH_MMCTIR_TGFMSCS ((uint32_t)0x00008000) /* Set when Tx good multi col counter reaches half the maximum value */ +#define ETH_MMCTIR_TGFSCS ((uint32_t)0x00004000) /* Set when Tx good single col counter reaches half the maximum value */ + +/* Bit definition for Ethernet MMC Receive Interrupt Mask Register */ +#define ETH_MMCRIMR_RGUFM ((uint32_t)0x00020000) /* Mask the interrupt when Rx good unicast frames counter reaches half the maximum value */ +#define ETH_MMCRIMR_RFAEM ((uint32_t)0x00000040) /* Mask the interrupt when when Rx alignment error counter reaches half the maximum value */ +#define ETH_MMCRIMR_RFCEM ((uint32_t)0x00000020) /* Mask the interrupt when Rx crc error counter reaches half the maximum value */ + +/* Bit definition for Ethernet MMC Transmit Interrupt Mask Register */ +#define ETH_MMCTIMR_TGFM ((uint32_t)0x00200000) /* Mask the interrupt when Tx good frame count counter reaches half the maximum value */ +#define ETH_MMCTIMR_TGFMSCM ((uint32_t)0x00008000) /* Mask the interrupt when Tx good multi col counter reaches half the maximum value */ +#define ETH_MMCTIMR_TGFSCM ((uint32_t)0x00004000) /* Mask the interrupt when Tx good single col counter reaches half the maximum value */ + +/* Bit definition for Ethernet MMC Transmitted Good Frames after Single Collision Counter Register */ +#define ETH_MMCTGFSCCR_TGFSCC ((uint32_t)0xFFFFFFFF) /* Number of successfully transmitted frames after a single collision in Half-duplex mode. */ + +/* Bit definition for Ethernet MMC Transmitted Good Frames after More than a Single Collision Counter Register */ +#define ETH_MMCTGFMSCCR_TGFMSCC ((uint32_t)0xFFFFFFFF) /* Number of successfully transmitted frames after more than a single collision in Half-duplex mode. */ + +/* Bit definition for Ethernet MMC Transmitted Good Frames Counter Register */ +#define ETH_MMCTGFCR_TGFC ((uint32_t)0xFFFFFFFF) /* Number of good frames transmitted. */ + +/* Bit definition for Ethernet MMC Received Frames with CRC Error Counter Register */ +#define ETH_MMCRFCECR_RFCEC ((uint32_t)0xFFFFFFFF) /* Number of frames received with CRC error. */ + +/* Bit definition for Ethernet MMC Received Frames with Alignement Error Counter Register */ +#define ETH_MMCRFAECR_RFAEC ((uint32_t)0xFFFFFFFF) /* Number of frames received with alignment (dribble) error */ + +/* Bit definition for Ethernet MMC Received Good Unicast Frames Counter Register */ +#define ETH_MMCRGUFCR_RGUFC ((uint32_t)0xFFFFFFFF) /* Number of good unicast frames received. */ + +/******************************************************************************/ +/* Ethernet PTP Registers bits definition */ +/******************************************************************************/ + +/* Bit definition for Ethernet PTP Time Stamp Contol Register */ +#define ETH_PTPTSCR_TSARU ((uint32_t)0x00000020) /* Addend register update */ +#define ETH_PTPTSCR_TSITE ((uint32_t)0x00000010) /* Time stamp interrupt trigger enable */ +#define ETH_PTPTSCR_TSSTU ((uint32_t)0x00000008) /* Time stamp update */ +#define ETH_PTPTSCR_TSSTI ((uint32_t)0x00000004) /* Time stamp initialize */ +#define ETH_PTPTSCR_TSFCU ((uint32_t)0x00000002) /* Time stamp fine or coarse update */ +#define ETH_PTPTSCR_TSE ((uint32_t)0x00000001) /* Time stamp enable */ + +/* Bit definition for Ethernet PTP Sub-Second Increment Register */ +#define ETH_PTPSSIR_STSSI ((uint32_t)0x000000FF) /* System time Sub-second increment value */ + +/* Bit definition for Ethernet PTP Time Stamp High Register */ +#define ETH_PTPTSHR_STS ((uint32_t)0xFFFFFFFF) /* System Time second */ + +/* Bit definition for Ethernet PTP Time Stamp Low Register */ +#define ETH_PTPTSLR_STPNS ((uint32_t)0x80000000) /* System Time Positive or negative time */ +#define ETH_PTPTSLR_STSS ((uint32_t)0x7FFFFFFF) /* System Time sub-seconds */ + +/* Bit definition for Ethernet PTP Time Stamp High Update Register */ +#define ETH_PTPTSHUR_TSUS ((uint32_t)0xFFFFFFFF) /* Time stamp update seconds */ + +/* Bit definition for Ethernet PTP Time Stamp Low Update Register */ +#define ETH_PTPTSLUR_TSUPNS ((uint32_t)0x80000000) /* Time stamp update Positive or negative time */ +#define ETH_PTPTSLUR_TSUSS ((uint32_t)0x7FFFFFFF) /* Time stamp update sub-seconds */ + +/* Bit definition for Ethernet PTP Time Stamp Addend Register */ +#define ETH_PTPTSAR_TSA ((uint32_t)0xFFFFFFFF) /* Time stamp addend */ + +/* Bit definition for Ethernet PTP Target Time High Register */ +#define ETH_PTPTTHR_TTSH ((uint32_t)0xFFFFFFFF) /* Target time stamp high */ + +/* Bit definition for Ethernet PTP Target Time Low Register */ +#define ETH_PTPTTLR_TTSL ((uint32_t)0xFFFFFFFF) /* Target time stamp low */ + +/******************************************************************************/ +/* Ethernet DMA Registers bits definition */ +/******************************************************************************/ + +/* Bit definition for Ethernet DMA Bus Mode Register */ +#define ETH_DMABMR_AAB ((uint32_t)0x02000000) /* Address-Aligned beats */ +#define ETH_DMABMR_FPM ((uint32_t)0x01000000) /* 4xPBL mode */ +#define ETH_DMABMR_USP ((uint32_t)0x00800000) /* Use separate PBL */ +#define ETH_DMABMR_RDP ((uint32_t)0x007E0000) /* RxDMA PBL */ + #define ETH_DMABMR_RDP_1Beat ((uint32_t)0x00020000) /* maximum number of beats to be transferred in one RxDMA transaction is 1 */ + #define ETH_DMABMR_RDP_2Beat ((uint32_t)0x00040000) /* maximum number of beats to be transferred in one RxDMA transaction is 2 */ + #define ETH_DMABMR_RDP_4Beat ((uint32_t)0x00080000) /* maximum number of beats to be transferred in one RxDMA transaction is 4 */ + #define ETH_DMABMR_RDP_8Beat ((uint32_t)0x00100000) /* maximum number of beats to be transferred in one RxDMA transaction is 8 */ + #define ETH_DMABMR_RDP_16Beat ((uint32_t)0x00200000) /* maximum number of beats to be transferred in one RxDMA transaction is 16 */ + #define ETH_DMABMR_RDP_32Beat ((uint32_t)0x00400000) /* maximum number of beats to be transferred in one RxDMA transaction is 32 */ + #define ETH_DMABMR_RDP_4xPBL_4Beat ((uint32_t)0x01020000) /* maximum number of beats to be transferred in one RxDMA transaction is 4 */ + #define ETH_DMABMR_RDP_4xPBL_8Beat ((uint32_t)0x01040000) /* maximum number of beats to be transferred in one RxDMA transaction is 8 */ + #define ETH_DMABMR_RDP_4xPBL_16Beat ((uint32_t)0x01080000) /* maximum number of beats to be transferred in one RxDMA transaction is 16 */ + #define ETH_DMABMR_RDP_4xPBL_32Beat ((uint32_t)0x01100000) /* maximum number of beats to be transferred in one RxDMA transaction is 32 */ + #define ETH_DMABMR_RDP_4xPBL_64Beat ((uint32_t)0x01200000) /* maximum number of beats to be transferred in one RxDMA transaction is 64 */ + #define ETH_DMABMR_RDP_4xPBL_128Beat ((uint32_t)0x01400000) /* maximum number of beats to be transferred in one RxDMA transaction is 128 */ +#define ETH_DMABMR_FB ((uint32_t)0x00010000) /* Fixed Burst */ +#define ETH_DMABMR_RTPR ((uint32_t)0x0000C000) /* Rx Tx priority ratio */ + #define ETH_DMABMR_RTPR_1_1 ((uint32_t)0x00000000) /* Rx Tx priority ratio */ + #define ETH_DMABMR_RTPR_2_1 ((uint32_t)0x00004000) /* Rx Tx priority ratio */ + #define ETH_DMABMR_RTPR_3_1 ((uint32_t)0x00008000) /* Rx Tx priority ratio */ + #define ETH_DMABMR_RTPR_4_1 ((uint32_t)0x0000C000) /* Rx Tx priority ratio */ +#define ETH_DMABMR_PBL ((uint32_t)0x00003F00) /* Programmable burst length */ + #define ETH_DMABMR_PBL_1Beat ((uint32_t)0x00000100) /* maximum number of beats to be transferred in one TxDMA (or both) transaction is 1 */ + #define ETH_DMABMR_PBL_2Beat ((uint32_t)0x00000200) /* maximum number of beats to be transferred in one TxDMA (or both) transaction is 2 */ + #define ETH_DMABMR_PBL_4Beat ((uint32_t)0x00000400) /* maximum number of beats to be transferred in one TxDMA (or both) transaction is 4 */ + #define ETH_DMABMR_PBL_8Beat ((uint32_t)0x00000800) /* maximum number of beats to be transferred in one TxDMA (or both) transaction is 8 */ + #define ETH_DMABMR_PBL_16Beat ((uint32_t)0x00001000) /* maximum number of beats to be transferred in one TxDMA (or both) transaction is 16 */ + #define ETH_DMABMR_PBL_32Beat ((uint32_t)0x00002000) /* maximum number of beats to be transferred in one TxDMA (or both) transaction is 32 */ + #define ETH_DMABMR_PBL_4xPBL_4Beat ((uint32_t)0x01000100) /* maximum number of beats to be transferred in one TxDMA (or both) transaction is 4 */ + #define ETH_DMABMR_PBL_4xPBL_8Beat ((uint32_t)0x01000200) /* maximum number of beats to be transferred in one TxDMA (or both) transaction is 8 */ + #define ETH_DMABMR_PBL_4xPBL_16Beat ((uint32_t)0x01000400) /* maximum number of beats to be transferred in one TxDMA (or both) transaction is 16 */ + #define ETH_DMABMR_PBL_4xPBL_32Beat ((uint32_t)0x01000800) /* maximum number of beats to be transferred in one TxDMA (or both) transaction is 32 */ + #define ETH_DMABMR_PBL_4xPBL_64Beat ((uint32_t)0x01001000) /* maximum number of beats to be transferred in one TxDMA (or both) transaction is 64 */ + #define ETH_DMABMR_PBL_4xPBL_128Beat ((uint32_t)0x01002000) /* maximum number of beats to be transferred in one TxDMA (or both) transaction is 128 */ +#define ETH_DMABMR_DSL ((uint32_t)0x0000007C) /* Descriptor Skip Length */ +#define ETH_DMABMR_DA ((uint32_t)0x00000002) /* DMA arbitration scheme */ +#define ETH_DMABMR_SR ((uint32_t)0x00000001) /* Software reset */ + +/* Bit definition for Ethernet DMA Transmit Poll Demand Register */ +#define ETH_DMATPDR_TPD ((uint32_t)0xFFFFFFFF) /* Transmit poll demand */ + +/* Bit definition for Ethernet DMA Receive Poll Demand Register */ +#define ETH_DMARPDR_RPD ((uint32_t)0xFFFFFFFF) /* Receive poll demand */ + +/* Bit definition for Ethernet DMA Receive Descriptor List Address Register */ +#define ETH_DMARDLAR_SRL ((uint32_t)0xFFFFFFFF) /* Start of receive list */ + +/* Bit definition for Ethernet DMA Transmit Descriptor List Address Register */ +#define ETH_DMATDLAR_STL ((uint32_t)0xFFFFFFFF) /* Start of transmit list */ + +/* Bit definition for Ethernet DMA Status Register */ +#define ETH_DMASR_TSTS ((uint32_t)0x20000000) /* Time-stamp trigger status */ +#define ETH_DMASR_PMTS ((uint32_t)0x10000000) /* PMT status */ +#define ETH_DMASR_MMCS ((uint32_t)0x08000000) /* MMC status */ +#define ETH_DMASR_EBS ((uint32_t)0x03800000) /* Error bits status */ + /* combination with EBS[2:0] for GetFlagStatus function */ + #define ETH_DMASR_EBS_DescAccess ((uint32_t)0x02000000) /* Error bits 0-data buffer, 1-desc. access */ + #define ETH_DMASR_EBS_ReadTransf ((uint32_t)0x01000000) /* Error bits 0-write trnsf, 1-read transfr */ + #define ETH_DMASR_EBS_DataTransfTx ((uint32_t)0x00800000) /* Error bits 0-Rx DMA, 1-Tx DMA */ +#define ETH_DMASR_TPS ((uint32_t)0x00700000) /* Transmit process state */ + #define ETH_DMASR_TPS_Stopped ((uint32_t)0x00000000) /* Stopped - Reset or Stop Tx Command issued */ + #define ETH_DMASR_TPS_Fetching ((uint32_t)0x00100000) /* Running - fetching the Tx descriptor */ + #define ETH_DMASR_TPS_Waiting ((uint32_t)0x00200000) /* Running - waiting for status */ + #define ETH_DMASR_TPS_Reading ((uint32_t)0x00300000) /* Running - reading the data from host memory */ + #define ETH_DMASR_TPS_Suspended ((uint32_t)0x00600000) /* Suspended - Tx Descriptor unavailabe */ + #define ETH_DMASR_TPS_Closing ((uint32_t)0x00700000) /* Running - closing Rx descriptor */ +#define ETH_DMASR_RPS ((uint32_t)0x000E0000) /* Receive process state */ + #define ETH_DMASR_RPS_Stopped ((uint32_t)0x00000000) /* Stopped - Reset or Stop Rx Command issued */ + #define ETH_DMASR_RPS_Fetching ((uint32_t)0x00020000) /* Running - fetching the Rx descriptor */ + #define ETH_DMASR_RPS_Waiting ((uint32_t)0x00060000) /* Running - waiting for packet */ + #define ETH_DMASR_RPS_Suspended ((uint32_t)0x00080000) /* Suspended - Rx Descriptor unavailable */ + #define ETH_DMASR_RPS_Closing ((uint32_t)0x000A0000) /* Running - closing descriptor */ + #define ETH_DMASR_RPS_Queuing ((uint32_t)0x000E0000) /* Running - queuing the recieve frame into host memory */ +#define ETH_DMASR_NIS ((uint32_t)0x00010000) /* Normal interrupt summary */ +#define ETH_DMASR_AIS ((uint32_t)0x00008000) /* Abnormal interrupt summary */ +#define ETH_DMASR_ERS ((uint32_t)0x00004000) /* Early receive status */ +#define ETH_DMASR_FBES ((uint32_t)0x00002000) /* Fatal bus error status */ +#define ETH_DMASR_ETS ((uint32_t)0x00000400) /* Early transmit status */ +#define ETH_DMASR_RWTS ((uint32_t)0x00000200) /* Receive watchdog timeout status */ +#define ETH_DMASR_RPSS ((uint32_t)0x00000100) /* Receive process stopped status */ +#define ETH_DMASR_RBUS ((uint32_t)0x00000080) /* Receive buffer unavailable status */ +#define ETH_DMASR_RS ((uint32_t)0x00000040) /* Receive status */ +#define ETH_DMASR_TUS ((uint32_t)0x00000020) /* Transmit underflow status */ +#define ETH_DMASR_ROS ((uint32_t)0x00000010) /* Receive overflow status */ +#define ETH_DMASR_TJTS ((uint32_t)0x00000008) /* Transmit jabber timeout status */ +#define ETH_DMASR_TBUS ((uint32_t)0x00000004) /* Transmit buffer unavailable status */ +#define ETH_DMASR_TPSS ((uint32_t)0x00000002) /* Transmit process stopped status */ +#define ETH_DMASR_TS ((uint32_t)0x00000001) /* Transmit status */ + +/* Bit definition for Ethernet DMA Operation Mode Register */ +#define ETH_DMAOMR_DTCEFD ((uint32_t)0x04000000) /* Disable Dropping of TCP/IP checksum error frames */ +#define ETH_DMAOMR_RSF ((uint32_t)0x02000000) /* Receive store and forward */ +#define ETH_DMAOMR_DFRF ((uint32_t)0x01000000) /* Disable flushing of received frames */ +#define ETH_DMAOMR_TSF ((uint32_t)0x00200000) /* Transmit store and forward */ +#define ETH_DMAOMR_FTF ((uint32_t)0x00100000) /* Flush transmit FIFO */ +#define ETH_DMAOMR_TTC ((uint32_t)0x0001C000) /* Transmit threshold control */ + #define ETH_DMAOMR_TTC_64Bytes ((uint32_t)0x00000000) /* threshold level of the MTL Transmit FIFO is 64 Bytes */ + #define ETH_DMAOMR_TTC_128Bytes ((uint32_t)0x00004000) /* threshold level of the MTL Transmit FIFO is 128 Bytes */ + #define ETH_DMAOMR_TTC_192Bytes ((uint32_t)0x00008000) /* threshold level of the MTL Transmit FIFO is 192 Bytes */ + #define ETH_DMAOMR_TTC_256Bytes ((uint32_t)0x0000C000) /* threshold level of the MTL Transmit FIFO is 256 Bytes */ + #define ETH_DMAOMR_TTC_40Bytes ((uint32_t)0x00010000) /* threshold level of the MTL Transmit FIFO is 40 Bytes */ + #define ETH_DMAOMR_TTC_32Bytes ((uint32_t)0x00014000) /* threshold level of the MTL Transmit FIFO is 32 Bytes */ + #define ETH_DMAOMR_TTC_24Bytes ((uint32_t)0x00018000) /* threshold level of the MTL Transmit FIFO is 24 Bytes */ + #define ETH_DMAOMR_TTC_16Bytes ((uint32_t)0x0001C000) /* threshold level of the MTL Transmit FIFO is 16 Bytes */ +#define ETH_DMAOMR_ST ((uint32_t)0x00002000) /* Start/stop transmission command */ +#define ETH_DMAOMR_FEF ((uint32_t)0x00000080) /* Forward error frames */ +#define ETH_DMAOMR_FUGF ((uint32_t)0x00000040) /* Forward undersized good frames */ +#define ETH_DMAOMR_RTC ((uint32_t)0x00000018) /* receive threshold control */ + #define ETH_DMAOMR_RTC_64Bytes ((uint32_t)0x00000000) /* threshold level of the MTL Receive FIFO is 64 Bytes */ + #define ETH_DMAOMR_RTC_32Bytes ((uint32_t)0x00000008) /* threshold level of the MTL Receive FIFO is 32 Bytes */ + #define ETH_DMAOMR_RTC_96Bytes ((uint32_t)0x00000010) /* threshold level of the MTL Receive FIFO is 96 Bytes */ + #define ETH_DMAOMR_RTC_128Bytes ((uint32_t)0x00000018) /* threshold level of the MTL Receive FIFO is 128 Bytes */ +#define ETH_DMAOMR_OSF ((uint32_t)0x00000004) /* operate on second frame */ +#define ETH_DMAOMR_SR ((uint32_t)0x00000002) /* Start/stop receive */ + +/* Bit definition for Ethernet DMA Interrupt Enable Register */ +#define ETH_DMAIER_NISE ((uint32_t)0x00010000) /* Normal interrupt summary enable */ +#define ETH_DMAIER_AISE ((uint32_t)0x00008000) /* Abnormal interrupt summary enable */ +#define ETH_DMAIER_ERIE ((uint32_t)0x00004000) /* Early receive interrupt enable */ +#define ETH_DMAIER_FBEIE ((uint32_t)0x00002000) /* Fatal bus error interrupt enable */ +#define ETH_DMAIER_ETIE ((uint32_t)0x00000400) /* Early transmit interrupt enable */ +#define ETH_DMAIER_RWTIE ((uint32_t)0x00000200) /* Receive watchdog timeout interrupt enable */ +#define ETH_DMAIER_RPSIE ((uint32_t)0x00000100) /* Receive process stopped interrupt enable */ +#define ETH_DMAIER_RBUIE ((uint32_t)0x00000080) /* Receive buffer unavailable interrupt enable */ +#define ETH_DMAIER_RIE ((uint32_t)0x00000040) /* Receive interrupt enable */ +#define ETH_DMAIER_TUIE ((uint32_t)0x00000020) /* Transmit Underflow interrupt enable */ +#define ETH_DMAIER_ROIE ((uint32_t)0x00000010) /* Receive Overflow interrupt enable */ +#define ETH_DMAIER_TJTIE ((uint32_t)0x00000008) /* Transmit jabber timeout interrupt enable */ +#define ETH_DMAIER_TBUIE ((uint32_t)0x00000004) /* Transmit buffer unavailable interrupt enable */ +#define ETH_DMAIER_TPSIE ((uint32_t)0x00000002) /* Transmit process stopped interrupt enable */ +#define ETH_DMAIER_TIE ((uint32_t)0x00000001) /* Transmit interrupt enable */ + +/* Bit definition for Ethernet DMA Missed Frame and Buffer Overflow Counter Register */ +#define ETH_DMAMFBOCR_OFOC ((uint32_t)0x10000000) /* Overflow bit for FIFO overflow counter */ +#define ETH_DMAMFBOCR_MFA ((uint32_t)0x0FFE0000) /* Number of frames missed by the application */ +#define ETH_DMAMFBOCR_OMFC ((uint32_t)0x00010000) /* Overflow bit for missed frame counter */ +#define ETH_DMAMFBOCR_MFC ((uint32_t)0x0000FFFF) /* Number of frames missed by the controller */ + +/* Bit definition for Ethernet DMA Current Host Transmit Descriptor Register */ +#define ETH_DMACHTDR_HTDAP ((uint32_t)0xFFFFFFFF) /* Host transmit descriptor address pointer */ + +/* Bit definition for Ethernet DMA Current Host Receive Descriptor Register */ +#define ETH_DMACHRDR_HRDAP ((uint32_t)0xFFFFFFFF) /* Host receive descriptor address pointer */ + +/* Bit definition for Ethernet DMA Current Host Transmit Buffer Address Register */ +#define ETH_DMACHTBAR_HTBAP ((uint32_t)0xFFFFFFFF) /* Host transmit buffer address pointer */ + +/* Bit definition for Ethernet DMA Current Host Receive Buffer Address Register */ +#define ETH_DMACHRBAR_HRBAP ((uint32_t)0xFFFFFFFF) /* Host receive buffer address pointer */ +#endif /* STM32F10X_CL */ + +/** + * @} + */ + + /** + * @} + */ + +#ifdef USE_STDPERIPH_DRIVER + #include "stm32f10x_conf.h" +#endif + +/** @addtogroup Exported_macro + * @{ + */ + +#define SET_BIT(REG, BIT) ((REG) |= (BIT)) + +#define CLEAR_BIT(REG, BIT) ((REG) &= ~(BIT)) + +#define READ_BIT(REG, BIT) ((REG) & (BIT)) + +#define CLEAR_REG(REG) ((REG) = (0x0)) + +#define WRITE_REG(REG, VAL) ((REG) = (VAL)) + +#define READ_REG(REG) ((REG)) + +#define MODIFY_REG(REG, CLEARMASK, SETMASK) WRITE_REG((REG), (((READ_REG(REG)) & (~(CLEARMASK))) | (SETMASK))) + +/** + * @} + */ + +#ifdef __cplusplus +} +#endif /* __cplusplus */ + +#endif /* __STM32F10x_H */ + +/** + * @} + */ + + /** + * @} + */ + +/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ diff --git a/Libraries/CMSIS/Device/ST/STM32F10x/Include/system_stm32f10x.h b/Libraries/CMSIS/Device/ST/STM32F10x/Include/system_stm32f10x.h new file mode 100644 index 0000000..01daf13 --- /dev/null +++ b/Libraries/CMSIS/Device/ST/STM32F10x/Include/system_stm32f10x.h @@ -0,0 +1,104 @@ +/** + ****************************************************************************** + * @file system_stm32f10x.h + * @author MCD Application Team + * @version V3.6.1 + * @date 09-March-2012 + * @brief CMSIS Cortex-M3 Device Peripheral Access Layer System Header File. + ****************************************************************************** + * @attention + * + *

© COPYRIGHT 2012 STMicroelectronics

+ * + * Licensed under MCD-ST Liberty SW License Agreement V2, (the "License"); + * You may not use this file except in compliance with the License. + * You may obtain a copy of the License at: + * + * http://www.st.com/software_license_agreement_liberty_v2 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, + * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + * + ****************************************************************************** + */ + +/** @addtogroup CMSIS + * @{ + */ + +/** @addtogroup stm32f10x_system + * @{ + */ + +/** + * @brief Define to prevent recursive inclusion + */ +#ifndef __SYSTEM_STM32F10X_H +#define __SYSTEM_STM32F10X_H + +#ifdef __cplusplus + extern "C" { +#endif + +/** @addtogroup STM32F10x_System_Includes + * @{ + */ + +/** + * @} + */ + + +/** @addtogroup STM32F10x_System_Exported_types + * @{ + */ + +extern uint32_t SystemCoreClock; /*!< System Clock Frequency (Core Clock) */ + +/** + * @} + */ + +/** @addtogroup STM32F10x_System_Exported_Constants + * @{ + */ + +/** + * @} + */ + +/** @addtogroup STM32F10x_System_Exported_Macros + * @{ + */ + +/** + * @} + */ + +/** @addtogroup STM32F10x_System_Exported_Functions + * @{ + */ + +extern void SystemInit(void); +extern void SystemCoreClockUpdate(void); +/** + * @} + */ + +#ifdef __cplusplus +} +#endif + +#endif /*__SYSTEM_STM32F10X_H */ + +/** + * @} + */ + +/** + * @} + */ +/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ diff --git a/Libraries/CMSIS/Device/ST/STM32F10x/Release_Notes.html b/Libraries/CMSIS/Device/ST/STM32F10x/Release_Notes.html new file mode 100644 index 0000000..47339ff --- /dev/null +++ b/Libraries/CMSIS/Device/ST/STM32F10x/Release_Notes.html @@ -0,0 +1,289 @@ + + + + + + + + + + + + +Release Notes for STM32F10x CMSIS + + + + + +
+


+

+
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Back to Release page
+

Release +Notes for STM32F10x CMSIS

+

Copyright 2012 STMicroelectronics

+

+
+

 

+ + + + + + +
+

Contents

+
    +
  1. STM32F10x CMSIS +update History
    2. +
  2. License
    3. +
+ +

STM32F10x CMSIS +update History

V3.6.1 / 09-March-2012

+

Main +Changes

+ +
  • All source files: license disclaimer text update and add link to the License file on ST Internet.

V3.6.0 / 27-January-2012

+

Main +Changes

+ +
  • Update directory structure to be compliant with CMSIS V2.1
  • All source files: update disclaimer to add reference to the new license agreement
  • stm32f10x.h
    • Add define for Cortex-M3 revision __CM3_REV
    • Allow +modification of some constants by the application code, definition of +these constants is now bracketed by              #if !defined. The concerned constant are HSE_VALUE, HSI_VALUE and HSE_STARTUP_TIMEOUT
    • Add missing bits definition for DAC CR register
    • Add missing bits definition for FSMC BTR1, BTR2, BTR3, BWTR1, BWTR2, BWTR3 and BWTR4 registers
    • Definition for Flash keys moved from stm32f10x_flash.c to stm32f10x.h
  • Add startup file for TASKING toolchain
  • V3.5.0 (based CMSIS V1.3) vs. V3.6.0 (based on CMSIS V2.1) compatibility update
    • Due to the directory structure difference between CMSIS V1.3 and V2.1, when migrating a project based on STM32F10x drivers V3.5.0 to V3.6.0 you need to perform the following update:
      • In +the compiler preprocessor, remove CortexM3 CMSIS include path. CortexM3 +CMSIS files are included by default in your development toolchain
      • Remove core_cm3.c file (if it is used). Almost of CortexM3 CMSIS function are provided as intrinsic by the compiler
      • In the compiler preprocessor, update path of STM32F10x CMSIS include files from  Libraries\CMSIS\CM3\DeviceSupport\ST\STM32F10x to Libraries\CMSIS\Device\ST\STM32F10x\Include
      • In the project settings, update path of startup_stm32f10x_xx.s file from Libraries\CMSIS\CM3\DeviceSupport\ST\STM32F10x\startup\”Compiler” to Libraries\CMSIS\Device\ST\STM32F10x\Source\Templates\”Compiler”
where, "Compiler" refer to arm, gcc_ride7, iar, TASKING or TrueSTUDIO
+

V3.5.0 / 11-March-2011

+

Main +Changes

+ +
    +
  • stm32f10x.h +and startup_stm32f10x_hd_vl.s files: remove the FSMC interrupt +definition for STM32F10x High-density Value line devices.
    +
    • +
  • system_stm32f10x.c file provided within the CMSIS folder.
    +
    • + +
+ +

3.4.0 +- 10/15/2010

+ +
    +
  1. General
    2. +
+ +
    +
  • Add support +for STM32F10x High-density Value line devices.
    • +
+
    +
  1. STM32F10x CMSIS Device Peripheral Access Layer
    2. +
+ + + +
    +
  • STM32F10x CMSIS Cortex-M3 Device Peripheral Access Layer Header File: stm32f10x.h
    +
    • Update to support High-density Value line devices
      • Add new define STM32F10X_HD_VL
        • +
      • RCC, AFIO, FSMC bits definition updated
        • +
      +
    • + + All +STM32 devices definitions are commented by default. User has to select the +appropriate device before starting else an error will be signaled on compile +time.
      • +
    • Add new IRQs definitions inside the IRQn_Type enumeration for STM23 High-density Value line devices.
      • +
    • "bool" type removed.
      +
      • +
  • STM32F10x CMSIS Cortex-M3 Device Peripheral Access Layer System Files: system_stm32f10x.h and system_stm32f10x.c
    +
    • +
      +
    • "system_stm32f10x.c" moved to to "STM32F10x_StdPeriph_Template" directory. This file is also moved to each example directory under "STM32F10x_StdPeriph_Examples".
      +
      • +
    • SystemInit_ExtMemCtl() function: update to support High-density Value line devices.
      • +
    • Add "VECT_TAB_SRAM" inside "system_stm32f10x.c" +to select if the user want to place the Vector Table in internal SRAM. +An additional define is also to specify the Vector Table offset "VECT_TAB_OFFSET".
      +
      • + +
    +
  • STM32F10x CMSIS startup files:startup_stm32f10x_xx.s
    • Add three +startup files for STM32 High-density Value line devices: + startup_stm32f10x_hd_vl.s
    +
+

3.3.0 +- 04/16/2010

+ +
  1. General
+
  • Add support +for STM32F10x XL-density devices.
  • Add startup files for TrueSTUDIO toolchain
  1. STM32F10x CMSIS Device Peripheral Access Layer
+ +
  • STM32F10x CMSIS Cortex-M3 Device Peripheral Access Layer Header File: stm32f10x.h
    +
    • Update to support XL-density devices
      • Add new define STM32F10X_XL
      • Add new IRQs for TIM9..14
      • Update FLASH_TypeDef structure
      • Add new IP instances TIM9..14
      • RCC, AFIO, DBGMCU bits definition updated
    • Correct IRQs definition for MD-, LD-, MD_VL- and LD_VL-density devices (remove comma "," at the end of enum list)
  • STM32F10x CMSIS Cortex-M3 Device Peripheral Access Layer System Files: system_stm32f10x.h and system_stm32f10x.c
    +
    • SystemInit_ExtMemCtl() function: update to support XL-density devices
    • SystemInit() function: swap the order of SetSysClock() and SystemInit_ExtMemCtl() functions. 
      +
  • STM32F10x CMSIS startup files:
    • add three +startup files for STM32 XL-density devices: + startup_stm32f10x_xl.s
    • startup_stm32f10x_md_vl.s for RIDE7: add USART3 IRQ Handler (was missing in previous version)
    • Add startup files for TrueSTUDIO toolchain
+

3.2.0 +- 03/01/2010

+
    +
  1. General
    2. +
+
    + +
  • STM32F10x CMSIS files updated to CMSIS V1.30 release
    • +
  • Directory structure updated to be aligned with CMSIS V1.30
    +
    • +
  • Add support +for STM32 Low-density Value line (STM32F100x4/6) and +Medium-density Value line (STM32F100x8/B) devices. 
    • + +
+
    +
  1. CMSIS Core Peripheral Access Layer
+ +
    +
  1. STM32F10x CMSIS Device Peripheral Access Layer
    2. + +
+ +
    + +
  • STM32F10x CMSIS Cortex-M3 Device Peripheral Access Layer Header File: stm32f10x.h
    +
    • +
      +
    • Update +the stm32f10x.h file to support new Value line devices features: CEC +peripheral, new General purpose timers TIM15, TIM16 and TIM17.
      • +
    • Peripherals Bits definitions updated to be in line with Value line devices available features.
      +
      • +
    • HSE_Value, +HSI_Value and HSEStartup_TimeOut changed to upper case: HSE_VALUE, +HSI_VALUE and HSE_STARTUP_TIMEOUT. Old names are kept for legacy +purposes.
      +
      • +
    +
  • STM32F10x CMSIS Cortex-M3 Device Peripheral Access Layer System Files: system_stm32f10x.h and system_stm32f10x.c
    +
    • +
      +
    • SystemFrequency variable name changed to SystemCoreClock
      +
      • +
    • Default + SystemCoreClock is changed to 24MHz when Value line devices are selected and to 72MHz on other devices.
      +
      • +
    • All while(1) loop were removed from all clock setting functions. User has to handle the HSE startup failure.
      +
      • +
    • Additional function void SystemCoreClockUpdate (void) is provided.
      +
      • +
    +
  • STM32F10x CMSIS Startup files: startup_stm32f10x_xx.s
    • +
      +
    • Add new +startup files for STM32 Low-density Value line devices: + startup_stm32f10x_ld_vl.s
      • +
    • Add new startup +files for STM32 Medium-density Value line devices: + startup_stm32f10x_md_vl.s
      • +
    • SystemInit() function is called from startup file (startup_stm32f10x_xx.s) before to branch to application main.
      +To reconfigure the default setting of SystemInit() function, refer to system_stm32f10x.c file
      +
      • +
    • GNU startup file for Low density devices (startup_stm32f10x_ld.s) is updated to fix compilation errors.
      +
      • +
    + +
+ +
    +
+

License

+

Licensed under MCD-ST Liberty SW License Agreement V2, (the "License"); You may not use this package except in compliance with the License. You may obtain a copy of the License at:


Unless +required by applicable law or agreed to in writing, software +distributed under the License is distributed on an "AS IS" BASIS,
WITHOUT +WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See +the License for the specific language governing permissions and +limitations under the License. +
+
+

For +complete documentation on STM32 Microcontrollers +visit www.st.com/STM32

+
+

+
+
+

 

+
+ \ No newline at end of file diff --git a/Libraries/CMSIS/Device/ST/STM32F10x/Source/Templates/TASKING/cstart_thumb2.asm b/Libraries/CMSIS/Device/ST/STM32F10x/Source/Templates/TASKING/cstart_thumb2.asm new file mode 100644 index 0000000..f363bdd --- /dev/null +++ b/Libraries/CMSIS/Device/ST/STM32F10x/Source/Templates/TASKING/cstart_thumb2.asm @@ -0,0 +1,140 @@ + + +;; NOTE: To allow the use of this file for both ARMv6M and ARMv7M, +;; we will only use 16-bit Thumb intructions. + + .extern _lc_ub_stack ; usr/sys mode stack pointer + .extern _lc_ue_stack ; symbol required by debugger + .extern _lc_ub_table ; ROM to RAM copy table + .extern main + .extern _Exit + .extern exit + .weak exit + .global __get_argcv + .weak __get_argcv + .extern __argcvbuf + .weak __argcvbuf + ;;.extern __init_hardware + .extern SystemInit + + .if @defined('__PROF_ENABLE__') + .extern __prof_init + .endif + .if @defined('__POSIX__') + .extern posix_main + .extern _posix_boot_stack_top + .endif + + .global _START + + .section .text.cstart + + .thumb +_START: + ;; anticipate possible ROM/RAM remapping + ;; by loading the 'real' program address + ldr r1,=_Next + bx r1 +_Next: + ;; initialize the stack pointer + ldr r1,=_lc_ub_stack ; TODO: make this part of the vector table + mov sp,r1 + + ;; call a user function which initializes function. + bl SystemInit + + ;; copy initialized sections from ROM to RAM + ;; and clear uninitialized data sections in RAM + + ldr r3,=_lc_ub_table + movs r0,#0 +cploop: + ldr r4,[r3,#0] ; load type + ldr r5,[r3,#4] ; dst address + ldr r6,[r3,#8] ; src address + ldr r7,[r3,#12] ; size + + cmp r4,#1 + beq copy + cmp r4,#2 + beq clear + b done + +copy: + subs r7,r7,#1 + ldrb r1,[r6,r7] + strb r1,[r5,r7] + bne copy + + adds r3,r3,#16 + b cploop + +clear: + subs r7,r7,#1 + strb r0,[r5,r7] + bne clear + + adds r3,r3,#16 + b cploop + +done: + + .if @defined('__POSIX__') + + ;; posix stack buffer for system upbringing + ldr r0,=_posix_boot_stack_top + ldr r0, [r0] + mov sp,r0 + + .else + + ;; load r10 with end of USR/SYS stack, which is + ;; needed in case stack overflow checking is on + ;; NOTE: use 16-bit instructions only, for ARMv6M + ldr r0,=_lc_ue_stack + mov r10,r0 + + .endif + + .if @defined('__PROF_ENABLE__') + bl __prof_init + .endif + + .if @defined('__POSIX__') + ;; call posix_main with no arguments + bl posix_main + .else + ;; retrieve argc and argv (default argv[0]==NULL & argc==0) + bl __get_argcv + ldr r1,=__argcvbuf + ;; call main + bl main + .endif + + ;; call exit using the return value from main() + ;; Note. Calling exit will also run all functions + ;; that were supplied through atexit(). + bl exit + +__get_argcv: ; weak definition + movs r0,#0 + bx lr + + .ltorg + .endsec + + .calls '_START', ' ' + .calls '_START','__init_vector_table' + .if @defined('__PROF_ENABLE__') + .calls '_START','__prof_init' + .endif + .if @defined('__POSIX__') + .calls '_START','posix_main' + .else + .calls '_START','__get_argcv' + .calls '_START','main' + .endif + .calls '_START','exit' + .calls '_START','',0 + + .end diff --git a/Libraries/CMSIS/Device/ST/STM32F10x/Source/Templates/TrueSTUDIO/startup_stm32f10x_cl.s b/Libraries/CMSIS/Device/ST/STM32F10x/Source/Templates/TrueSTUDIO/startup_stm32f10x_cl.s new file mode 100644 index 0000000..fea24d8 --- /dev/null +++ b/Libraries/CMSIS/Device/ST/STM32F10x/Source/Templates/TrueSTUDIO/startup_stm32f10x_cl.s @@ -0,0 +1,479 @@ +/** + ****************************************************************************** + * @file startup_stm32f10x_cl.s + * @author MCD Application Team + * @version V3.6.1 + * @date 09-March-2012 + * @brief STM32F10x Connectivity line Devices vector table for Atollic + * toolchain. + * This module performs: + * - Set the initial SP + * - Set the initial PC == Reset_Handler, + * - Set the vector table entries with the exceptions ISR + * address. + * - Configure the clock system + * - Branches to main in the C library (which eventually + * calls main()). + * After Reset the Cortex-M3 processor is in Thread mode, + * priority is Privileged, and the Stack is set to Main. + ****************************************************************************** + * @attention + * + *

© COPYRIGHT 2012 STMicroelectronics

+ * + * Licensed under MCD-ST Liberty SW License Agreement V2, (the "License"); + * You may not use this file except in compliance with the License. + * You may obtain a copy of the License at: + * + * http://www.st.com/software_license_agreement_liberty_v2 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, + * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + * + ****************************************************************************** + */ + + .syntax unified + .cpu cortex-m3 + .fpu softvfp + .thumb + +.global g_pfnVectors +.global Default_Handler + +/* start address for the initialization values of the .data section. +defined in linker script */ +.word _sidata +/* start address for the .data section. defined in linker script */ +.word _sdata +/* end address for the .data section. defined in linker script */ +.word _edata +/* start address for the .bss section. defined in linker script */ +.word _sbss +/* end address for the .bss section. defined in linker script */ +.word _ebss + +.equ BootRAM, 0xF1E0F85F +/** + * @brief This is the code that gets called when the processor first + * starts execution following a reset event. Only the absolutely + * necessary set is performed, after which the application + * supplied main() routine is called. + * @param None + * @retval : None +*/ + + .section .text.Reset_Handler + .weak Reset_Handler + .type Reset_Handler, %function +Reset_Handler: + +/* Copy the data segment initializers from flash to SRAM */ + movs r1, #0 + b LoopCopyDataInit + +CopyDataInit: + ldr r3, =_sidata + ldr r3, [r3, r1] + str r3, [r0, r1] + adds r1, r1, #4 + +LoopCopyDataInit: + ldr r0, =_sdata + ldr r3, =_edata + adds r2, r0, r1 + cmp r2, r3 + bcc CopyDataInit + ldr r2, =_sbss + b LoopFillZerobss + +/* Zero fill the bss segment. */ +FillZerobss: + movs r3, #0 + str r3, [r2], #4 + +LoopFillZerobss: + ldr r3, = _ebss + cmp r2, r3 + bcc FillZerobss + +/* Call the clock system intitialization function.*/ + bl SystemInit +/* Call static constructors */ + bl __libc_init_array +/* Call the application's entry point.*/ + bl main + bx lr +.size Reset_Handler, .-Reset_Handler + +/** + * @brief This is the code that gets called when the processor receives an + * unexpected interrupt. This simply enters an infinite loop, preserving + * the system state for examination by a debugger. + * + * @param None + * @retval : None +*/ + .section .text.Default_Handler,"ax",%progbits +Default_Handler: +Infinite_Loop: + b Infinite_Loop + .size Default_Handler, .-Default_Handler + +/****************************************************************************** +* +* The minimal vector table for a Cortex M3. Note that the proper constructs +* must be placed on this to ensure that it ends up at physical address +* 0x0000.0000. +* +******************************************************************************/ + .section .isr_vector,"a",%progbits + .type g_pfnVectors, %object + .size g_pfnVectors, .-g_pfnVectors + + +g_pfnVectors: + .word _estack + .word Reset_Handler + .word NMI_Handler + .word HardFault_Handler + .word MemManage_Handler + .word BusFault_Handler + .word UsageFault_Handler + .word 0 + .word 0 + .word 0 + .word 0 + .word SVC_Handler + .word DebugMon_Handler + .word 0 + .word PendSV_Handler + .word SysTick_Handler + .word WWDG_IRQHandler + .word PVD_IRQHandler + .word TAMPER_IRQHandler + .word RTC_IRQHandler + .word FLASH_IRQHandler + .word RCC_IRQHandler + .word EXTI0_IRQHandler + .word EXTI1_IRQHandler + .word EXTI2_IRQHandler + .word EXTI3_IRQHandler + .word EXTI4_IRQHandler + .word DMA1_Channel1_IRQHandler + .word DMA1_Channel2_IRQHandler + .word DMA1_Channel3_IRQHandler + .word DMA1_Channel4_IRQHandler + .word DMA1_Channel5_IRQHandler + .word DMA1_Channel6_IRQHandler + .word DMA1_Channel7_IRQHandler + .word ADC1_2_IRQHandler + .word CAN1_TX_IRQHandler + .word CAN1_RX0_IRQHandler + .word CAN1_RX1_IRQHandler + .word CAN1_SCE_IRQHandler + .word EXTI9_5_IRQHandler + .word TIM1_BRK_IRQHandler + .word TIM1_UP_IRQHandler + .word TIM1_TRG_COM_IRQHandler + .word TIM1_CC_IRQHandler + .word TIM2_IRQHandler + .word TIM3_IRQHandler + .word TIM4_IRQHandler + .word I2C1_EV_IRQHandler + .word I2C1_ER_IRQHandler + .word I2C2_EV_IRQHandler + .word I2C2_ER_IRQHandler + .word SPI1_IRQHandler + .word SPI2_IRQHandler + .word USART1_IRQHandler + .word USART2_IRQHandler + .word USART3_IRQHandler + .word EXTI15_10_IRQHandler + .word RTCAlarm_IRQHandler + .word OTG_FS_WKUP_IRQHandler + .word 0 + .word 0 + .word 0 + .word 0 + .word 0 + .word 0 + .word 0 + .word TIM5_IRQHandler + .word SPI3_IRQHandler + .word UART4_IRQHandler + .word UART5_IRQHandler + .word TIM6_IRQHandler + .word TIM7_IRQHandler + .word DMA2_Channel1_IRQHandler + .word DMA2_Channel2_IRQHandler + .word DMA2_Channel3_IRQHandler + .word DMA2_Channel4_IRQHandler + .word DMA2_Channel5_IRQHandler + .word ETH_IRQHandler + .word ETH_WKUP_IRQHandler + .word CAN2_TX_IRQHandler + .word CAN2_RX0_IRQHandler + .word CAN2_RX1_IRQHandler + .word CAN2_SCE_IRQHandler + .word OTG_FS_IRQHandler + .word 0 + .word 0 + .word 0 + .word 0 + .word 0 + .word 0 + .word 0 + .word 0 + .word 0 + .word 0 + .word 0 + .word 0 + .word 0 + .word 0 + .word 0 + .word 0 + .word 0 + .word 0 + .word 0 + .word 0 + .word 0 + .word 0 + .word 0 + .word 0 + .word 0 + .word 0 + .word 0 + .word 0 + .word 0 + .word 0 + .word 0 + .word 0 + .word 0 + .word 0 + .word 0 + .word 0 + .word BootRAM /* @0x1E0. This is for boot in RAM mode for + STM32F10x Connectivity line Devices. */ + +/******************************************************************************* +* +* Provide weak aliases for each Exception handler to the Default_Handler. +* As they are weak aliases, any function with the same name will override +* this definition. +* +*******************************************************************************/ + .weak NMI_Handler + .thumb_set NMI_Handler,Default_Handler + + .weak HardFault_Handler + .thumb_set HardFault_Handler,Default_Handler + + .weak MemManage_Handler + .thumb_set MemManage_Handler,Default_Handler + + .weak BusFault_Handler + .thumb_set BusFault_Handler,Default_Handler + + .weak UsageFault_Handler + .thumb_set UsageFault_Handler,Default_Handler + + .weak SVC_Handler + .thumb_set SVC_Handler,Default_Handler + + .weak DebugMon_Handler + .thumb_set DebugMon_Handler,Default_Handler + + .weak PendSV_Handler + .thumb_set PendSV_Handler,Default_Handler + + .weak SysTick_Handler + .thumb_set SysTick_Handler,Default_Handler + + .weak WWDG_IRQHandler + .thumb_set WWDG_IRQHandler,Default_Handler + + .weak PVD_IRQHandler + .thumb_set PVD_IRQHandler,Default_Handler + + .weak TAMPER_IRQHandler + .thumb_set TAMPER_IRQHandler,Default_Handler + + .weak RTC_IRQHandler + .thumb_set RTC_IRQHandler,Default_Handler + + .weak FLASH_IRQHandler + .thumb_set FLASH_IRQHandler,Default_Handler + + .weak RCC_IRQHandler + .thumb_set RCC_IRQHandler,Default_Handler + + .weak EXTI0_IRQHandler + .thumb_set EXTI0_IRQHandler,Default_Handler + + .weak EXTI1_IRQHandler + .thumb_set EXTI1_IRQHandler,Default_Handler + + .weak EXTI2_IRQHandler + .thumb_set EXTI2_IRQHandler,Default_Handler + + .weak EXTI3_IRQHandler + .thumb_set EXTI3_IRQHandler,Default_Handler + + .weak EXTI4_IRQHandler + .thumb_set EXTI4_IRQHandler,Default_Handler + + .weak DMA1_Channel1_IRQHandler + .thumb_set DMA1_Channel1_IRQHandler,Default_Handler + + .weak DMA1_Channel2_IRQHandler + .thumb_set DMA1_Channel2_IRQHandler,Default_Handler + + .weak DMA1_Channel3_IRQHandler + .thumb_set DMA1_Channel3_IRQHandler,Default_Handler + + .weak DMA1_Channel4_IRQHandler + .thumb_set DMA1_Channel4_IRQHandler,Default_Handler + + .weak DMA1_Channel5_IRQHandler + .thumb_set DMA1_Channel5_IRQHandler,Default_Handler + + .weak DMA1_Channel6_IRQHandler + .thumb_set DMA1_Channel6_IRQHandler,Default_Handler + + .weak DMA1_Channel7_IRQHandler + .thumb_set DMA1_Channel7_IRQHandler,Default_Handler + + .weak ADC1_2_IRQHandler + .thumb_set ADC1_2_IRQHandler,Default_Handler + + .weak CAN1_TX_IRQHandler + .thumb_set CAN1_TX_IRQHandler,Default_Handler + + .weak CAN1_RX0_IRQHandler + .thumb_set CAN1_RX0_IRQHandler,Default_Handler + + .weak CAN1_RX1_IRQHandler + .thumb_set CAN1_RX1_IRQHandler,Default_Handler + + .weak CAN1_SCE_IRQHandler + .thumb_set CAN1_SCE_IRQHandler,Default_Handler + + .weak EXTI9_5_IRQHandler + .thumb_set EXTI9_5_IRQHandler,Default_Handler + + .weak TIM1_BRK_IRQHandler + .thumb_set TIM1_BRK_IRQHandler,Default_Handler + + .weak TIM1_UP_IRQHandler + .thumb_set TIM1_UP_IRQHandler,Default_Handler + + .weak TIM1_TRG_COM_IRQHandler + .thumb_set TIM1_TRG_COM_IRQHandler,Default_Handler + + .weak TIM1_CC_IRQHandler + .thumb_set TIM1_CC_IRQHandler,Default_Handler + + .weak TIM2_IRQHandler + .thumb_set TIM2_IRQHandler,Default_Handler + + .weak TIM3_IRQHandler + .thumb_set TIM3_IRQHandler,Default_Handler + + .weak TIM4_IRQHandler + .thumb_set TIM4_IRQHandler,Default_Handler + + .weak I2C1_EV_IRQHandler + .thumb_set I2C1_EV_IRQHandler,Default_Handler + + .weak I2C1_ER_IRQHandler + .thumb_set I2C1_ER_IRQHandler,Default_Handler + + .weak I2C2_EV_IRQHandler + .thumb_set I2C2_EV_IRQHandler,Default_Handler + + .weak I2C2_ER_IRQHandler + .thumb_set I2C2_ER_IRQHandler,Default_Handler + + .weak SPI1_IRQHandler + .thumb_set SPI1_IRQHandler,Default_Handler + + .weak SPI2_IRQHandler + .thumb_set SPI2_IRQHandler,Default_Handler + + .weak USART1_IRQHandler + .thumb_set USART1_IRQHandler,Default_Handler + + .weak USART2_IRQHandler + .thumb_set USART2_IRQHandler,Default_Handler + + .weak USART3_IRQHandler + .thumb_set USART3_IRQHandler,Default_Handler + + .weak EXTI15_10_IRQHandler + .thumb_set EXTI15_10_IRQHandler,Default_Handler + + .weak RTCAlarm_IRQHandler + .thumb_set RTCAlarm_IRQHandler,Default_Handler + + .weak OTG_FS_WKUP_IRQHandler + .thumb_set OTG_FS_WKUP_IRQHandler,Default_Handler + + .weak TIM5_IRQHandler + .thumb_set TIM5_IRQHandler,Default_Handler + + .weak SPI3_IRQHandler + .thumb_set SPI3_IRQHandler,Default_Handler + + .weak UART4_IRQHandler + .thumb_set UART4_IRQHandler,Default_Handler + + .weak UART5_IRQHandler + .thumb_set UART5_IRQHandler,Default_Handler + + .weak TIM6_IRQHandler + .thumb_set TIM6_IRQHandler,Default_Handler + + .weak TIM7_IRQHandler + .thumb_set TIM7_IRQHandler,Default_Handler + + .weak DMA2_Channel1_IRQHandler + .thumb_set DMA2_Channel1_IRQHandler,Default_Handler + + .weak DMA2_Channel2_IRQHandler + .thumb_set DMA2_Channel2_IRQHandler,Default_Handler + + .weak DMA2_Channel3_IRQHandler + .thumb_set DMA2_Channel3_IRQHandler,Default_Handler + + .weak DMA2_Channel4_IRQHandler + .thumb_set DMA2_Channel4_IRQHandler,Default_Handler + + .weak DMA2_Channel5_IRQHandler + .thumb_set DMA2_Channel5_IRQHandler,Default_Handler + + .weak ETH_IRQHandler + .thumb_set ETH_IRQHandler,Default_Handler + + .weak ETH_WKUP_IRQHandler + .thumb_set ETH_WKUP_IRQHandler,Default_Handler + + .weak CAN2_TX_IRQHandler + .thumb_set CAN2_TX_IRQHandler,Default_Handler + + .weak CAN2_RX0_IRQHandler + .thumb_set CAN2_RX0_IRQHandler,Default_Handler + + .weak CAN2_RX1_IRQHandler + .thumb_set CAN2_RX1_IRQHandler,Default_Handler + + .weak CAN2_SCE_IRQHandler + .thumb_set CAN2_SCE_IRQHandler,Default_Handler + + .weak OTG_FS_IRQHandler + .thumb_set OTG_FS_IRQHandler ,Default_Handler + +/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ diff --git a/Libraries/CMSIS/Device/ST/STM32F10x/Source/Templates/TrueSTUDIO/startup_stm32f10x_hd.s b/Libraries/CMSIS/Device/ST/STM32F10x/Source/Templates/TrueSTUDIO/startup_stm32f10x_hd.s new file mode 100644 index 0000000..7994bd6 --- /dev/null +++ b/Libraries/CMSIS/Device/ST/STM32F10x/Source/Templates/TrueSTUDIO/startup_stm32f10x_hd.s @@ -0,0 +1,475 @@ +/** + ****************************************************************************** + * @file startup_stm32f10x_hd.s + * @author MCD Application Team + * @version V3.6.1 + * @date 09-March-2012 + * @brief STM32F10x High Density Devices vector table for Atollic toolchain. + * This module performs: + * - Set the initial SP + * - Set the initial PC == Reset_Handler, + * - Set the vector table entries with the exceptions ISR address, + * - Configure the clock system + * - Configure external SRAM mounted on STM3210E-EVAL board + * to be used as data memory (optional, to be enabled by user) + * - Branches to main in the C library (which eventually + * calls main()). + * After Reset the Cortex-M3 processor is in Thread mode, + * priority is Privileged, and the Stack is set to Main. + ****************************************************************************** + * @attention + * + *

© COPYRIGHT 2012 STMicroelectronics

+ * + * Licensed under MCD-ST Liberty SW License Agreement V2, (the "License"); + * You may not use this file except in compliance with the License. + * You may obtain a copy of the License at: + * + * http://www.st.com/software_license_agreement_liberty_v2 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, + * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + * + ****************************************************************************** + */ + + .syntax unified + .cpu cortex-m3 + .fpu softvfp + .thumb + +.global g_pfnVectors +.global Default_Handler + +/* start address for the initialization values of the .data section. +defined in linker script */ +.word _sidata +/* start address for the .data section. defined in linker script */ +.word _sdata +/* end address for the .data section. defined in linker script */ +.word _edata +/* start address for the .bss section. defined in linker script */ +.word _sbss +/* end address for the .bss section. defined in linker script */ +.word _ebss + +.equ BootRAM, 0xF1E0F85F +/** + * @brief This is the code that gets called when the processor first + * starts execution following a reset event. Only the absolutely + * necessary set is performed, after which the application + * supplied main() routine is called. + * @param None + * @retval : None +*/ + + .section .text.Reset_Handler + .weak Reset_Handler + .type Reset_Handler, %function +Reset_Handler: + +/* Copy the data segment initializers from flash to SRAM */ + movs r1, #0 + b LoopCopyDataInit + +CopyDataInit: + ldr r3, =_sidata + ldr r3, [r3, r1] + str r3, [r0, r1] + adds r1, r1, #4 + +LoopCopyDataInit: + ldr r0, =_sdata + ldr r3, =_edata + adds r2, r0, r1 + cmp r2, r3 + bcc CopyDataInit + ldr r2, =_sbss + b LoopFillZerobss +/* Zero fill the bss segment. */ +FillZerobss: + movs r3, #0 + str r3, [r2], #4 + +LoopFillZerobss: + ldr r3, = _ebss + cmp r2, r3 + bcc FillZerobss + +/* Call the clock system intitialization function.*/ + bl SystemInit +/* Call static constructors */ + bl __libc_init_array +/* Call the application's entry point.*/ + bl main + bx lr +.size Reset_Handler, .-Reset_Handler + +/** + * @brief This is the code that gets called when the processor receives an + * unexpected interrupt. This simply enters an infinite loop, preserving + * the system state for examination by a debugger. + * + * @param None + * @retval : None +*/ + .section .text.Default_Handler,"ax",%progbits +Default_Handler: +Infinite_Loop: + b Infinite_Loop + .size Default_Handler, .-Default_Handler +/****************************************************************************** +* +* The minimal vector table for a Cortex M3. Note that the proper constructs +* must be placed on this to ensure that it ends up at physical address +* 0x0000.0000. +* +******************************************************************************/ + .section .isr_vector,"a",%progbits + .type g_pfnVectors, %object + .size g_pfnVectors, .-g_pfnVectors + + +g_pfnVectors: + .word _estack + .word Reset_Handler + .word NMI_Handler + .word HardFault_Handler + .word MemManage_Handler + .word BusFault_Handler + .word UsageFault_Handler + .word 0 + .word 0 + .word 0 + .word 0 + .word SVC_Handler + .word DebugMon_Handler + .word 0 + .word PendSV_Handler + .word SysTick_Handler + .word WWDG_IRQHandler + .word PVD_IRQHandler + .word TAMPER_IRQHandler + .word RTC_IRQHandler + .word FLASH_IRQHandler + .word RCC_IRQHandler + .word EXTI0_IRQHandler + .word EXTI1_IRQHandler + .word EXTI2_IRQHandler + .word EXTI3_IRQHandler + .word EXTI4_IRQHandler + .word DMA1_Channel1_IRQHandler + .word DMA1_Channel2_IRQHandler + .word DMA1_Channel3_IRQHandler + .word DMA1_Channel4_IRQHandler + .word DMA1_Channel5_IRQHandler + .word DMA1_Channel6_IRQHandler + .word DMA1_Channel7_IRQHandler + .word ADC1_2_IRQHandler + .word USB_HP_CAN1_TX_IRQHandler + .word USB_LP_CAN1_RX0_IRQHandler + .word CAN1_RX1_IRQHandler + .word CAN1_SCE_IRQHandler + .word EXTI9_5_IRQHandler + .word TIM1_BRK_IRQHandler + .word TIM1_UP_IRQHandler + .word TIM1_TRG_COM_IRQHandler + .word TIM1_CC_IRQHandler + .word TIM2_IRQHandler + .word TIM3_IRQHandler + .word TIM4_IRQHandler + .word I2C1_EV_IRQHandler + .word I2C1_ER_IRQHandler + .word I2C2_EV_IRQHandler + .word I2C2_ER_IRQHandler + .word SPI1_IRQHandler + .word SPI2_IRQHandler + .word USART1_IRQHandler + .word USART2_IRQHandler + .word USART3_IRQHandler + .word EXTI15_10_IRQHandler + .word RTCAlarm_IRQHandler + .word USBWakeUp_IRQHandler + .word TIM8_BRK_IRQHandler + .word TIM8_UP_IRQHandler + .word TIM8_TRG_COM_IRQHandler + .word TIM8_CC_IRQHandler + .word ADC3_IRQHandler + .word FSMC_IRQHandler + .word SDIO_IRQHandler + .word TIM5_IRQHandler + .word SPI3_IRQHandler + .word UART4_IRQHandler + .word UART5_IRQHandler + .word TIM6_IRQHandler + .word TIM7_IRQHandler + .word DMA2_Channel1_IRQHandler + .word DMA2_Channel2_IRQHandler + .word DMA2_Channel3_IRQHandler + .word DMA2_Channel4_5_IRQHandler + .word 0 + .word 0 + .word 0 + .word 0 + .word 0 + .word 0 + .word 0 + .word 0 + .word 0 + .word 0 + .word 0 + .word 0 + .word 0 + .word 0 + .word 0 + .word 0 + .word 0 + .word 0 + .word 0 + .word 0 + .word 0 + .word 0 + .word 0 + .word 0 + .word 0 + .word 0 + .word 0 + .word 0 + .word 0 + .word 0 + .word 0 + .word 0 + .word 0 + .word 0 + .word 0 + .word 0 + .word 0 + .word 0 + .word 0 + .word 0 + .word 0 + .word 0 + .word 0 + .word 0 + .word BootRAM /* @0x1E0. This is for boot in RAM mode for + STM32F10x High Density devices. */ + +/******************************************************************************* +* +* Provide weak aliases for each Exception handler to the Default_Handler. +* As they are weak aliases, any function with the same name will override +* this definition. +* +*******************************************************************************/ + + .weak NMI_Handler + .thumb_set NMI_Handler,Default_Handler + + .weak HardFault_Handler + .thumb_set HardFault_Handler,Default_Handler + + .weak MemManage_Handler + .thumb_set MemManage_Handler,Default_Handler + + .weak BusFault_Handler + .thumb_set BusFault_Handler,Default_Handler + + .weak UsageFault_Handler + .thumb_set UsageFault_Handler,Default_Handler + + .weak SVC_Handler + .thumb_set SVC_Handler,Default_Handler + + .weak DebugMon_Handler + .thumb_set DebugMon_Handler,Default_Handler + + .weak PendSV_Handler + .thumb_set PendSV_Handler,Default_Handler + + .weak SysTick_Handler + .thumb_set SysTick_Handler,Default_Handler + + .weak WWDG_IRQHandler + .thumb_set WWDG_IRQHandler,Default_Handler + + .weak PVD_IRQHandler + .thumb_set PVD_IRQHandler,Default_Handler + + .weak TAMPER_IRQHandler + .thumb_set TAMPER_IRQHandler,Default_Handler + + .weak RTC_IRQHandler + .thumb_set RTC_IRQHandler,Default_Handler + + .weak FLASH_IRQHandler + .thumb_set FLASH_IRQHandler,Default_Handler + + .weak RCC_IRQHandler + .thumb_set RCC_IRQHandler,Default_Handler + + .weak EXTI0_IRQHandler + .thumb_set EXTI0_IRQHandler,Default_Handler + + .weak EXTI1_IRQHandler + .thumb_set EXTI1_IRQHandler,Default_Handler + + .weak EXTI2_IRQHandler + .thumb_set EXTI2_IRQHandler,Default_Handler + + .weak EXTI3_IRQHandler + .thumb_set EXTI3_IRQHandler,Default_Handler + + .weak EXTI4_IRQHandler + .thumb_set EXTI4_IRQHandler,Default_Handler + + .weak DMA1_Channel1_IRQHandler + .thumb_set DMA1_Channel1_IRQHandler,Default_Handler + + .weak DMA1_Channel2_IRQHandler + .thumb_set DMA1_Channel2_IRQHandler,Default_Handler + + .weak DMA1_Channel3_IRQHandler + .thumb_set DMA1_Channel3_IRQHandler,Default_Handler + + .weak DMA1_Channel4_IRQHandler + .thumb_set DMA1_Channel4_IRQHandler,Default_Handler + + .weak DMA1_Channel5_IRQHandler + .thumb_set DMA1_Channel5_IRQHandler,Default_Handler + + .weak DMA1_Channel6_IRQHandler + .thumb_set DMA1_Channel6_IRQHandler,Default_Handler + + .weak DMA1_Channel7_IRQHandler + .thumb_set DMA1_Channel7_IRQHandler,Default_Handler + + .weak ADC1_2_IRQHandler + .thumb_set ADC1_2_IRQHandler,Default_Handler + + .weak USB_HP_CAN1_TX_IRQHandler + .thumb_set USB_HP_CAN1_TX_IRQHandler,Default_Handler + + .weak USB_LP_CAN1_RX0_IRQHandler + .thumb_set USB_LP_CAN1_RX0_IRQHandler,Default_Handler + + .weak CAN1_RX1_IRQHandler + .thumb_set CAN1_RX1_IRQHandler,Default_Handler + + .weak CAN1_SCE_IRQHandler + .thumb_set CAN1_SCE_IRQHandler,Default_Handler + + .weak EXTI9_5_IRQHandler + .thumb_set EXTI9_5_IRQHandler,Default_Handler + + .weak TIM1_BRK_IRQHandler + .thumb_set TIM1_BRK_IRQHandler,Default_Handler + + .weak TIM1_UP_IRQHandler + .thumb_set TIM1_UP_IRQHandler,Default_Handler + + .weak TIM1_TRG_COM_IRQHandler + .thumb_set TIM1_TRG_COM_IRQHandler,Default_Handler + + .weak TIM1_CC_IRQHandler + .thumb_set TIM1_CC_IRQHandler,Default_Handler + + .weak TIM2_IRQHandler + .thumb_set TIM2_IRQHandler,Default_Handler + + .weak TIM3_IRQHandler + .thumb_set TIM3_IRQHandler,Default_Handler + + .weak TIM4_IRQHandler + .thumb_set TIM4_IRQHandler,Default_Handler + + .weak I2C1_EV_IRQHandler + .thumb_set I2C1_EV_IRQHandler,Default_Handler + + .weak I2C1_ER_IRQHandler + .thumb_set I2C1_ER_IRQHandler,Default_Handler + + .weak I2C2_EV_IRQHandler + .thumb_set I2C2_EV_IRQHandler,Default_Handler + + .weak I2C2_ER_IRQHandler + .thumb_set I2C2_ER_IRQHandler,Default_Handler + + .weak SPI1_IRQHandler + .thumb_set SPI1_IRQHandler,Default_Handler + + .weak SPI2_IRQHandler + .thumb_set SPI2_IRQHandler,Default_Handler + + .weak USART1_IRQHandler + .thumb_set USART1_IRQHandler,Default_Handler + + .weak USART2_IRQHandler + .thumb_set USART2_IRQHandler,Default_Handler + + .weak USART3_IRQHandler + .thumb_set USART3_IRQHandler,Default_Handler + + .weak EXTI15_10_IRQHandler + .thumb_set EXTI15_10_IRQHandler,Default_Handler + + .weak RTCAlarm_IRQHandler + .thumb_set RTCAlarm_IRQHandler,Default_Handler + + .weak USBWakeUp_IRQHandler + .thumb_set USBWakeUp_IRQHandler,Default_Handler + + .weak TIM8_BRK_IRQHandler + .thumb_set TIM8_BRK_IRQHandler,Default_Handler + + .weak TIM8_UP_IRQHandler + .thumb_set TIM8_UP_IRQHandler,Default_Handler + + .weak TIM8_TRG_COM_IRQHandler + .thumb_set TIM8_TRG_COM_IRQHandler,Default_Handler + + .weak TIM8_CC_IRQHandler + .thumb_set TIM8_CC_IRQHandler,Default_Handler + + .weak ADC3_IRQHandler + .thumb_set ADC3_IRQHandler,Default_Handler + + .weak FSMC_IRQHandler + .thumb_set FSMC_IRQHandler,Default_Handler + + .weak SDIO_IRQHandler + .thumb_set SDIO_IRQHandler,Default_Handler + + .weak TIM5_IRQHandler + .thumb_set TIM5_IRQHandler,Default_Handler + + .weak SPI3_IRQHandler + .thumb_set SPI3_IRQHandler,Default_Handler + + .weak UART4_IRQHandler + .thumb_set UART4_IRQHandler,Default_Handler + + .weak UART5_IRQHandler + .thumb_set UART5_IRQHandler,Default_Handler + + .weak TIM6_IRQHandler + .thumb_set TIM6_IRQHandler,Default_Handler + + .weak TIM7_IRQHandler + .thumb_set TIM7_IRQHandler,Default_Handler + + .weak DMA2_Channel1_IRQHandler + .thumb_set DMA2_Channel1_IRQHandler,Default_Handler + + .weak DMA2_Channel2_IRQHandler + .thumb_set DMA2_Channel2_IRQHandler,Default_Handler + + .weak DMA2_Channel3_IRQHandler + .thumb_set DMA2_Channel3_IRQHandler,Default_Handler + + .weak DMA2_Channel4_5_IRQHandler + .thumb_set DMA2_Channel4_5_IRQHandler,Default_Handler + +/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ diff --git a/Libraries/CMSIS/Device/ST/STM32F10x/Source/Templates/TrueSTUDIO/startup_stm32f10x_hd_vl.s b/Libraries/CMSIS/Device/ST/STM32F10x/Source/Templates/TrueSTUDIO/startup_stm32f10x_hd_vl.s new file mode 100644 index 0000000..8deb6a2 --- /dev/null +++ b/Libraries/CMSIS/Device/ST/STM32F10x/Source/Templates/TrueSTUDIO/startup_stm32f10x_hd_vl.s @@ -0,0 +1,457 @@ +/** + ****************************************************************************** + * @file startup_stm32f10x_hd_vl.s + * @author MCD Application Team + * @version V3.6.1 + * @date 09-March-2012 + * @brief STM32F10x High Density Value Line Devices vector table for Atollic + * toolchain. + * This module performs: + * - Set the initial SP + * - Set the initial PC == Reset_Handler, + * - Set the vector table entries with the exceptions ISR address + * - Configure the clock system + * - Configure external SRAM mounted on STM32100E-EVAL board + * to be used as data memory (optional, to be enabled by user) + * - Branches to main in the C library (which eventually + * calls main()). + * After Reset the Cortex-M3 processor is in Thread mode, + * priority is Privileged, and the Stack is set to Main. + ****************************************************************************** + * @attention + * + *

© COPYRIGHT 2012 STMicroelectronics

+ * + * Licensed under MCD-ST Liberty SW License Agreement V2, (the "License"); + * You may not use this file except in compliance with the License. + * You may obtain a copy of the License at: + * + * http://www.st.com/software_license_agreement_liberty_v2 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, + * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + * + ****************************************************************************** + */ + + .syntax unified + .cpu cortex-m3 + .fpu softvfp + .thumb + +.global g_pfnVectors +.global Default_Handler + +/* start address for the initialization values of the .data section. +defined in linker script */ +.word _sidata +/* start address for the .data section. defined in linker script */ +.word _sdata +/* end address for the .data section. defined in linker script */ +.word _edata +/* start address for the .bss section. defined in linker script */ +.word _sbss +/* end address for the .bss section. defined in linker script */ +.word _ebss + +.equ BootRAM, 0xF108F85F +/** + * @brief This is the code that gets called when the processor first + * starts execution following a reset event. Only the absolutely + * necessary set is performed, after which the application + * supplied main() routine is called. + * @param None + * @retval : None +*/ + + .section .text.Reset_Handler + .weak Reset_Handler + .type Reset_Handler, %function +Reset_Handler: + +/* Copy the data segment initializers from flash to SRAM */ + movs r1, #0 + b LoopCopyDataInit + +CopyDataInit: + ldr r3, =_sidata + ldr r3, [r3, r1] + str r3, [r0, r1] + adds r1, r1, #4 + +LoopCopyDataInit: + ldr r0, =_sdata + ldr r3, =_edata + adds r2, r0, r1 + cmp r2, r3 + bcc CopyDataInit + ldr r2, =_sbss + b LoopFillZerobss +/* Zero fill the bss segment. */ +FillZerobss: + movs r3, #0 + str r3, [r2], #4 + +LoopFillZerobss: + ldr r3, = _ebss + cmp r2, r3 + bcc FillZerobss + +/* Call the clock system intitialization function.*/ + bl SystemInit +/* Call static constructors */ + bl __libc_init_array +/* Call the application's entry point.*/ + bl main + bx lr +.size Reset_Handler, .-Reset_Handler + +/** + * @brief This is the code that gets called when the processor receives an + * unexpected interrupt. This simply enters an infinite loop, preserving + * the system state for examination by a debugger. + * + * @param None + * @retval : None +*/ + .section .text.Default_Handler,"ax",%progbits +Default_Handler: +Infinite_Loop: + b Infinite_Loop + .size Default_Handler, .-Default_Handler +/****************************************************************************** +* +* The minimal vector table for a Cortex M3. Note that the proper constructs +* must be placed on this to ensure that it ends up at physical address +* 0x0000.0000. +* +******************************************************************************/ + .section .isr_vector,"a",%progbits + .type g_pfnVectors, %object + .size g_pfnVectors, .-g_pfnVectors + + +g_pfnVectors: + .word _estack + .word Reset_Handler + .word NMI_Handler + .word HardFault_Handler + .word MemManage_Handler + .word BusFault_Handler + .word UsageFault_Handler + .word 0 + .word 0 + .word 0 + .word 0 + .word SVC_Handler + .word DebugMon_Handler + .word 0 + .word PendSV_Handler + .word SysTick_Handler + .word WWDG_IRQHandler + .word PVD_IRQHandler + .word TAMPER_IRQHandler + .word RTC_IRQHandler + .word FLASH_IRQHandler + .word RCC_IRQHandler + .word EXTI0_IRQHandler + .word EXTI1_IRQHandler + .word EXTI2_IRQHandler + .word EXTI3_IRQHandler + .word EXTI4_IRQHandler + .word DMA1_Channel1_IRQHandler + .word DMA1_Channel2_IRQHandler + .word DMA1_Channel3_IRQHandler + .word DMA1_Channel4_IRQHandler + .word DMA1_Channel5_IRQHandler + .word DMA1_Channel6_IRQHandler + .word DMA1_Channel7_IRQHandler + .word ADC1_IRQHandler + .word 0 + .word 0 + .word 0 + .word 0 + .word EXTI9_5_IRQHandler + .word TIM1_BRK_TIM15_IRQHandler + .word TIM1_UP_TIM16_IRQHandler + .word TIM1_TRG_COM_TIM17_IRQHandler + .word TIM1_CC_IRQHandler + .word TIM2_IRQHandler + .word TIM3_IRQHandler + .word TIM4_IRQHandler + .word I2C1_EV_IRQHandler + .word I2C1_ER_IRQHandler + .word I2C2_EV_IRQHandler + .word I2C2_ER_IRQHandler + .word SPI1_IRQHandler + .word SPI2_IRQHandler + .word USART1_IRQHandler + .word USART2_IRQHandler + .word USART3_IRQHandler + .word EXTI15_10_IRQHandler + .word RTCAlarm_IRQHandler + .word CEC_IRQHandler + .word TIM12_IRQHandler + .word TIM13_IRQHandler + .word TIM14_IRQHandler + .word 0 + .word 0 + .word 0 + .word 0 + .word TIM5_IRQHandler + .word SPI3_IRQHandler + .word UART4_IRQHandler + .word UART5_IRQHandler + .word TIM6_DAC_IRQHandler + .word TIM7_IRQHandler + .word DMA2_Channel1_IRQHandler + .word DMA2_Channel2_IRQHandler + .word DMA2_Channel3_IRQHandler + .word DMA2_Channel4_5_IRQHandler + .word DMA2_Channel5_IRQHandler + .word 0 + .word 0 + .word 0 + .word 0 + .word 0 + .word 0 + .word 0 + .word 0 + .word 0 + .word 0 + .word 0 + .word 0 + .word 0 + .word 0 + .word 0 + .word 0 + .word 0 + .word 0 + .word 0 + .word 0 + .word 0 + .word 0 + .word 0 + .word 0 + .word 0 + .word 0 + .word 0 + .word 0 + .word 0 + .word 0 + .word 0 + .word 0 + .word 0 + .word 0 + .word 0 + .word 0 + .word 0 + .word 0 + .word 0 + .word 0 + .word 0 + .word 0 + .word 0 + .word BootRAM /* @0x1E0. This is for boot in RAM mode for + STM32F10x High Density Value line devices. */ + +/******************************************************************************* +* +* Provide weak aliases for each Exception handler to the Default_Handler. +* As they are weak aliases, any function with the same name will override +* this definition. +* +*******************************************************************************/ + + + .weak NMI_Handler + .thumb_set NMI_Handler,Default_Handler + + .weak HardFault_Handler + .thumb_set HardFault_Handler,Default_Handler + + .weak MemManage_Handler + .thumb_set MemManage_Handler,Default_Handler + + .weak BusFault_Handler + .thumb_set BusFault_Handler,Default_Handler + + .weak UsageFault_Handler + .thumb_set UsageFault_Handler,Default_Handler + + .weak SVC_Handler + .thumb_set SVC_Handler,Default_Handler + + .weak DebugMon_Handler + .thumb_set DebugMon_Handler,Default_Handler + + .weak PendSV_Handler + .thumb_set PendSV_Handler,Default_Handler + + .weak SysTick_Handler + .thumb_set SysTick_Handler,Default_Handler + + .weak WWDG_IRQHandler + .thumb_set WWDG_IRQHandler,Default_Handler + + .weak PVD_IRQHandler + .thumb_set PVD_IRQHandler,Default_Handler + + .weak TAMPER_IRQHandler + .thumb_set TAMPER_IRQHandler,Default_Handler + + .weak RTC_IRQHandler + .thumb_set RTC_IRQHandler,Default_Handler + + .weak FLASH_IRQHandler + .thumb_set FLASH_IRQHandler,Default_Handler + + .weak RCC_IRQHandler + .thumb_set RCC_IRQHandler,Default_Handler + + .weak EXTI0_IRQHandler + .thumb_set EXTI0_IRQHandler,Default_Handler + + .weak EXTI1_IRQHandler + .thumb_set EXTI1_IRQHandler,Default_Handler + + .weak EXTI2_IRQHandler + .thumb_set EXTI2_IRQHandler,Default_Handler + + .weak EXTI3_IRQHandler + .thumb_set EXTI3_IRQHandler,Default_Handler + + .weak EXTI4_IRQHandler + .thumb_set EXTI4_IRQHandler,Default_Handler + + .weak DMA1_Channel1_IRQHandler + .thumb_set DMA1_Channel1_IRQHandler,Default_Handler + + .weak DMA1_Channel2_IRQHandler + .thumb_set DMA1_Channel2_IRQHandler,Default_Handler + + .weak DMA1_Channel3_IRQHandler + .thumb_set DMA1_Channel3_IRQHandler,Default_Handler + + .weak DMA1_Channel4_IRQHandler + .thumb_set DMA1_Channel4_IRQHandler,Default_Handler + + .weak DMA1_Channel5_IRQHandler + .thumb_set DMA1_Channel5_IRQHandler,Default_Handler + + .weak DMA1_Channel6_IRQHandler + .thumb_set DMA1_Channel6_IRQHandler,Default_Handler + + .weak DMA1_Channel7_IRQHandler + .thumb_set DMA1_Channel7_IRQHandler,Default_Handler + + .weak ADC1_IRQHandler + .thumb_set ADC1_IRQHandler,Default_Handler + + .weak EXTI9_5_IRQHandler + .thumb_set EXTI9_5_IRQHandler,Default_Handler + + .weak TIM1_BRK_TIM15_IRQHandler + .thumb_set TIM1_BRK_TIM15_IRQHandler,Default_Handler + + .weak TIM1_UP_TIM16_IRQHandler + .thumb_set TIM1_UP_TIM16_IRQHandler,Default_Handler + + .weak TIM1_TRG_COM_TIM17_IRQHandler + .thumb_set TIM1_TRG_COM_TIM17_IRQHandler,Default_Handler + + .weak TIM1_CC_IRQHandler + .thumb_set TIM1_CC_IRQHandler,Default_Handler + + .weak TIM2_IRQHandler + .thumb_set TIM2_IRQHandler,Default_Handler + + .weak TIM3_IRQHandler + .thumb_set TIM3_IRQHandler,Default_Handler + + .weak TIM4_IRQHandler + .thumb_set TIM4_IRQHandler,Default_Handler + + .weak I2C1_EV_IRQHandler + .thumb_set I2C1_EV_IRQHandler,Default_Handler + + .weak I2C1_ER_IRQHandler + .thumb_set I2C1_ER_IRQHandler,Default_Handler + + .weak I2C2_EV_IRQHandler + .thumb_set I2C2_EV_IRQHandler,Default_Handler + + .weak I2C2_ER_IRQHandler + .thumb_set I2C2_ER_IRQHandler,Default_Handler + + .weak SPI1_IRQHandler + .thumb_set SPI1_IRQHandler,Default_Handler + + .weak SPI2_IRQHandler + .thumb_set SPI2_IRQHandler,Default_Handler + + .weak USART1_IRQHandler + .thumb_set USART1_IRQHandler,Default_Handler + + .weak USART2_IRQHandler + .thumb_set USART2_IRQHandler,Default_Handler + + .weak USART3_IRQHandler + .thumb_set USART3_IRQHandler,Default_Handler + + .weak EXTI15_10_IRQHandler + .thumb_set EXTI15_10_IRQHandler,Default_Handler + + .weak RTCAlarm_IRQHandler + .thumb_set RTCAlarm_IRQHandler,Default_Handler + + .weak CEC_IRQHandler + .thumb_set CEC_IRQHandler,Default_Handler + + .weak TIM12_IRQHandler + .thumb_set TIM12_IRQHandler,Default_Handler + + .weak TIM13_IRQHandler + .thumb_set TIM13_IRQHandler,Default_Handler + + .weak TIM14_IRQHandler + .thumb_set TIM14_IRQHandler,Default_Handler + + .weak TIM5_IRQHandler + .thumb_set TIM5_IRQHandler,Default_Handler + + .weak SPI3_IRQHandler + .thumb_set SPI3_IRQHandler,Default_Handler + + .weak UART4_IRQHandler + .thumb_set UART4_IRQHandler,Default_Handler + + .weak UART5_IRQHandler + .thumb_set UART5_IRQHandler,Default_Handler + + .weak TIM6_DAC_IRQHandler + .thumb_set TIM6_DAC_IRQHandler,Default_Handler + + .weak TIM7_IRQHandler + .thumb_set TIM7_IRQHandler,Default_Handler + + .weak DMA2_Channel1_IRQHandler + .thumb_set DMA2_Channel1_IRQHandler,Default_Handler + + .weak DMA2_Channel2_IRQHandler + .thumb_set DMA2_Channel2_IRQHandler,Default_Handler + + .weak DMA2_Channel3_IRQHandler + .thumb_set DMA2_Channel3_IRQHandler,Default_Handler + + .weak DMA2_Channel4_5_IRQHandler + .thumb_set DMA2_Channel4_5_IRQHandler,Default_Handler + + .weak DMA2_Channel5_IRQHandler + .thumb_set DMA2_Channel5_IRQHandler,Default_Handler + +/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ + diff --git a/Libraries/CMSIS/Device/ST/STM32F10x/Source/Templates/TrueSTUDIO/startup_stm32f10x_ld.s b/Libraries/CMSIS/Device/ST/STM32F10x/Source/Templates/TrueSTUDIO/startup_stm32f10x_ld.s new file mode 100644 index 0000000..19a6724 --- /dev/null +++ b/Libraries/CMSIS/Device/ST/STM32F10x/Source/Templates/TrueSTUDIO/startup_stm32f10x_ld.s @@ -0,0 +1,353 @@ +/** + ****************************************************************************** + * @file startup_stm32f10x_ld.s + * @author MCD Application Team + * @version V3.6.1 + * @date 09-March-2012 + * @brief STM32F10x Low Density Devices vector table for Atollic toolchain. + * This module performs: + * - Set the initial SP + * - Set the initial PC == Reset_Handler, + * - Set the vector table entries with the exceptions ISR address. + * - Configure the clock system + * - Branches to main in the C library (which eventually + * calls main()). + * After Reset the Cortex-M3 processor is in Thread mode, + * priority is Privileged, and the Stack is set to Main. + ****************************************************************************** + * @attention + * + *

© COPYRIGHT 2012 STMicroelectronics

+ * + * Licensed under MCD-ST Liberty SW License Agreement V2, (the "License"); + * You may not use this file except in compliance with the License. + * You may obtain a copy of the License at: + * + * http://www.st.com/software_license_agreement_liberty_v2 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, + * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + * + ****************************************************************************** + */ + + .syntax unified + .cpu cortex-m3 + .fpu softvfp + .thumb + +.global g_pfnVectors +.global Default_Handler + +/* start address for the initialization values of the .data section. +defined in linker script */ +.word _sidata +/* start address for the .data section. defined in linker script */ +.word _sdata +/* end address for the .data section. defined in linker script */ +.word _edata +/* start address for the .bss section. defined in linker script */ +.word _sbss +/* end address for the .bss section. defined in linker script */ +.word _ebss + +.equ BootRAM, 0xF108F85F +/** + * @brief This is the code that gets called when the processor first + * starts execution following a reset event. Only the absolutely + * necessary set is performed, after which the application + * supplied main() routine is called. + * @param None + * @retval : None +*/ + + .section .text.Reset_Handler + .weak Reset_Handler + .type Reset_Handler, %function +Reset_Handler: + +/* Copy the data segment initializers from flash to SRAM */ + movs r1, #0 + b LoopCopyDataInit + +CopyDataInit: + ldr r3, =_sidata + ldr r3, [r3, r1] + str r3, [r0, r1] + adds r1, r1, #4 + +LoopCopyDataInit: + ldr r0, =_sdata + ldr r3, =_edata + adds r2, r0, r1 + cmp r2, r3 + bcc CopyDataInit + ldr r2, =_sbss + b LoopFillZerobss +/* Zero fill the bss segment. */ +FillZerobss: + movs r3, #0 + str r3, [r2], #4 + +LoopFillZerobss: + ldr r3, = _ebss + cmp r2, r3 + bcc FillZerobss + +/* Call the clock system intitialization function.*/ + bl SystemInit +/* Call static constructors */ + bl __libc_init_array +/* Call the application's entry point.*/ + bl main + bx lr +.size Reset_Handler, .-Reset_Handler + +/** + * @brief This is the code that gets called when the processor receives an + * unexpected interrupt. This simply enters an infinite loop, preserving + * the system state for examination by a debugger. + * + * @param None + * @retval : None +*/ + .section .text.Default_Handler,"ax",%progbits +Default_Handler: +Infinite_Loop: + b Infinite_Loop + .size Default_Handler, .-Default_Handler +/****************************************************************************** +* +* The minimal vector table for a Cortex M3. Note that the proper constructs +* must be placed on this to ensure that it ends up at physical address +* 0x0000.0000. +* +******************************************************************************/ + .section .isr_vector,"a",%progbits + .type g_pfnVectors, %object + .size g_pfnVectors, .-g_pfnVectors + + +g_pfnVectors: + .word _estack + .word Reset_Handler + .word NMI_Handler + .word HardFault_Handler + .word MemManage_Handler + .word BusFault_Handler + .word UsageFault_Handler + .word 0 + .word 0 + .word 0 + .word 0 + .word SVC_Handler + .word DebugMon_Handler + .word 0 + .word PendSV_Handler + .word SysTick_Handler + .word WWDG_IRQHandler + .word PVD_IRQHandler + .word TAMPER_IRQHandler + .word RTC_IRQHandler + .word FLASH_IRQHandler + .word RCC_IRQHandler + .word EXTI0_IRQHandler + .word EXTI1_IRQHandler + .word EXTI2_IRQHandler + .word EXTI3_IRQHandler + .word EXTI4_IRQHandler + .word DMA1_Channel1_IRQHandler + .word DMA1_Channel2_IRQHandler + .word DMA1_Channel3_IRQHandler + .word DMA1_Channel4_IRQHandler + .word DMA1_Channel5_IRQHandler + .word DMA1_Channel6_IRQHandler + .word DMA1_Channel7_IRQHandler + .word ADC1_2_IRQHandler + .word USB_HP_CAN1_TX_IRQHandler + .word USB_LP_CAN1_RX0_IRQHandler + .word CAN1_RX1_IRQHandler + .word CAN1_SCE_IRQHandler + .word EXTI9_5_IRQHandler + .word TIM1_BRK_IRQHandler + .word TIM1_UP_IRQHandler + .word TIM1_TRG_COM_IRQHandler + .word TIM1_CC_IRQHandler + .word TIM2_IRQHandler + .word TIM3_IRQHandler + .word 0 + .word I2C1_EV_IRQHandler + .word I2C1_ER_IRQHandler + .word 0 + .word 0 + .word SPI1_IRQHandler + .word 0 + .word USART1_IRQHandler + .word USART2_IRQHandler + .word 0 + .word EXTI15_10_IRQHandler + .word RTCAlarm_IRQHandler + .word USBWakeUp_IRQHandler + .word 0 + .word 0 + .word 0 + .word 0 + .word 0 + .word 0 + .word 0 + .word BootRAM /* @0x108. This is for boot in RAM mode for + STM32F10x Low Density devices.*/ + +/******************************************************************************* +* +* Provide weak aliases for each Exception handler to the Default_Handler. +* As they are weak aliases, any function with the same name will override +* this definition. +* +*******************************************************************************/ + + .weak NMI_Handler + .thumb_set NMI_Handler,Default_Handler + + .weak HardFault_Handler + .thumb_set HardFault_Handler,Default_Handler + + .weak MemManage_Handler + .thumb_set MemManage_Handler,Default_Handler + + .weak BusFault_Handler + .thumb_set BusFault_Handler,Default_Handler + + .weak UsageFault_Handler + .thumb_set UsageFault_Handler,Default_Handler + + .weak SVC_Handler + .thumb_set SVC_Handler,Default_Handler + + .weak DebugMon_Handler + .thumb_set DebugMon_Handler,Default_Handler + + .weak PendSV_Handler + .thumb_set PendSV_Handler,Default_Handler + + .weak SysTick_Handler + .thumb_set SysTick_Handler,Default_Handler + + .weak WWDG_IRQHandler + .thumb_set WWDG_IRQHandler,Default_Handler + + .weak PVD_IRQHandler + .thumb_set PVD_IRQHandler,Default_Handler + + .weak TAMPER_IRQHandler + .thumb_set TAMPER_IRQHandler,Default_Handler + + .weak RTC_IRQHandler + .thumb_set RTC_IRQHandler,Default_Handler + + .weak FLASH_IRQHandler + .thumb_set FLASH_IRQHandler,Default_Handler + + .weak RCC_IRQHandler + .thumb_set RCC_IRQHandler,Default_Handler + + .weak EXTI0_IRQHandler + .thumb_set EXTI0_IRQHandler,Default_Handler + + .weak EXTI1_IRQHandler + .thumb_set EXTI1_IRQHandler,Default_Handler + + .weak EXTI2_IRQHandler + .thumb_set EXTI2_IRQHandler,Default_Handler + + .weak EXTI3_IRQHandler + .thumb_set EXTI3_IRQHandler,Default_Handler + + .weak EXTI4_IRQHandler + .thumb_set EXTI4_IRQHandler,Default_Handler + + .weak DMA1_Channel1_IRQHandler + .thumb_set DMA1_Channel1_IRQHandler,Default_Handler + + .weak DMA1_Channel2_IRQHandler + .thumb_set DMA1_Channel2_IRQHandler,Default_Handler + + .weak DMA1_Channel3_IRQHandler + .thumb_set DMA1_Channel3_IRQHandler,Default_Handler + + .weak DMA1_Channel4_IRQHandler + .thumb_set DMA1_Channel4_IRQHandler,Default_Handler + + .weak DMA1_Channel5_IRQHandler + .thumb_set DMA1_Channel5_IRQHandler,Default_Handler + + .weak DMA1_Channel6_IRQHandler + .thumb_set DMA1_Channel6_IRQHandler,Default_Handler + + .weak DMA1_Channel7_IRQHandler + .thumb_set DMA1_Channel7_IRQHandler,Default_Handler + + .weak ADC1_2_IRQHandler + .thumb_set ADC1_2_IRQHandler,Default_Handler + + .weak USB_HP_CAN1_TX_IRQHandler + .thumb_set USB_HP_CAN1_TX_IRQHandler,Default_Handler + + .weak USB_LP_CAN1_RX0_IRQHandler + .thumb_set USB_LP_CAN1_RX0_IRQHandler,Default_Handler + + .weak CAN1_RX1_IRQHandler + .thumb_set CAN1_RX1_IRQHandler,Default_Handler + + .weak CAN1_SCE_IRQHandler + .thumb_set CAN1_SCE_IRQHandler,Default_Handler + + .weak EXTI9_5_IRQHandler + .thumb_set EXTI9_5_IRQHandler,Default_Handler + + .weak TIM1_BRK_IRQHandler + .thumb_set TIM1_BRK_IRQHandler,Default_Handler + + .weak TIM1_UP_IRQHandler + .thumb_set TIM1_UP_IRQHandler,Default_Handler + + .weak TIM1_TRG_COM_IRQHandler + .thumb_set TIM1_TRG_COM_IRQHandler,Default_Handler + + .weak TIM1_CC_IRQHandler + .thumb_set TIM1_CC_IRQHandler,Default_Handler + + .weak TIM2_IRQHandler + .thumb_set TIM2_IRQHandler,Default_Handler + + .weak TIM3_IRQHandler + .thumb_set TIM3_IRQHandler,Default_Handler + + .weak I2C1_EV_IRQHandler + .thumb_set I2C1_EV_IRQHandler,Default_Handler + + .weak I2C1_ER_IRQHandler + .thumb_set I2C1_ER_IRQHandler,Default_Handler + + .weak SPI1_IRQHandler + .thumb_set SPI1_IRQHandler,Default_Handler + + .weak USART1_IRQHandler + .thumb_set USART1_IRQHandler,Default_Handler + + .weak USART2_IRQHandler + .thumb_set USART2_IRQHandler,Default_Handler + + .weak EXTI15_10_IRQHandler + .thumb_set EXTI15_10_IRQHandler,Default_Handler + + .weak RTCAlarm_IRQHandler + .thumb_set RTCAlarm_IRQHandler,Default_Handler + + .weak USBWakeUp_IRQHandler + .thumb_set USBWakeUp_IRQHandler,Default_Handler + +/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ diff --git a/Libraries/CMSIS/Device/ST/STM32F10x/Source/Templates/TrueSTUDIO/startup_stm32f10x_ld_vl.s b/Libraries/CMSIS/Device/ST/STM32F10x/Source/Templates/TrueSTUDIO/startup_stm32f10x_ld_vl.s new file mode 100644 index 0000000..a5f6850 --- /dev/null +++ b/Libraries/CMSIS/Device/ST/STM32F10x/Source/Templates/TrueSTUDIO/startup_stm32f10x_ld_vl.s @@ -0,0 +1,398 @@ +/** + ****************************************************************************** + * @file startup_stm32f10x_ld_vl.s + * @author MCD Application Team + * @version V3.6.1 + * @date 09-March-2012 + * @brief STM32F10x Low Density Value Line Devices vector table for Atollic toolchain. + * This module performs: + * - Set the initial SP + * - Set the initial PC == Reset_Handler, + * - Set the vector table entries with the exceptions ISR address + * - Configure the clock system + * - Branches to main in the C library (which eventually + * calls main()). + * After Reset the Cortex-M3 processor is in Thread mode, + * priority is Privileged, and the Stack is set to Main. + ****************************************************************************** + * @attention + * + *

© COPYRIGHT 2012 STMicroelectronics

+ * + * Licensed under MCD-ST Liberty SW License Agreement V2, (the "License"); + * You may not use this file except in compliance with the License. + * You may obtain a copy of the License at: + * + * http://www.st.com/software_license_agreement_liberty_v2 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, + * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + * + ****************************************************************************** + */ + + .syntax unified + .cpu cortex-m3 + .fpu softvfp + .thumb + +.global g_pfnVectors +.global Default_Handler + +/* start address for the initialization values of the .data section. +defined in linker script */ +.word _sidata +/* start address for the .data section. defined in linker script */ +.word _sdata +/* end address for the .data section. defined in linker script */ +.word _edata +/* start address for the .bss section. defined in linker script */ +.word _sbss +/* end address for the .bss section. defined in linker script */ +.word _ebss + +.equ BootRAM, 0xF108F85F +/** + * @brief This is the code that gets called when the processor first + * starts execution following a reset event. Only the absolutely + * necessary set is performed, after which the application + * supplied main() routine is called. + * @param None + * @retval : None +*/ + + .section .text.Reset_Handler + .weak Reset_Handler + .type Reset_Handler, %function +Reset_Handler: + +/* Copy the data segment initializers from flash to SRAM */ + movs r1, #0 + b LoopCopyDataInit + +CopyDataInit: + ldr r3, =_sidata + ldr r3, [r3, r1] + str r3, [r0, r1] + adds r1, r1, #4 + +LoopCopyDataInit: + ldr r0, =_sdata + ldr r3, =_edata + adds r2, r0, r1 + cmp r2, r3 + bcc CopyDataInit + ldr r2, =_sbss + b LoopFillZerobss +/* Zero fill the bss segment. */ +FillZerobss: + movs r3, #0 + str r3, [r2], #4 + +LoopFillZerobss: + ldr r3, = _ebss + cmp r2, r3 + bcc FillZerobss + +/* Call the clock system intitialization function.*/ + bl SystemInit +/* Call static constructors */ + bl __libc_init_array +/* Call the application's entry point.*/ + bl main + bx lr +.size Reset_Handler, .-Reset_Handler + +/** + * @brief This is the code that gets called when the processor receives an + * unexpected interrupt. This simply enters an infinite loop, preserving + * the system state for examination by a debugger. + * + * @param None + * @retval : None +*/ + .section .text.Default_Handler,"ax",%progbits +Default_Handler: +Infinite_Loop: + b Infinite_Loop + .size Default_Handler, .-Default_Handler +/****************************************************************************** +* +* The minimal vector table for a Cortex M3. Note that the proper constructs +* must be placed on this to ensure that it ends up at physical address +* 0x0000.0000. +* +******************************************************************************/ + .section .isr_vector,"a",%progbits + .type g_pfnVectors, %object + .size g_pfnVectors, .-g_pfnVectors + + +g_pfnVectors: + .word _estack + .word Reset_Handler + .word NMI_Handler + .word HardFault_Handler + .word MemManage_Handler + .word BusFault_Handler + .word UsageFault_Handler + .word 0 + .word 0 + .word 0 + .word 0 + .word SVC_Handler + .word DebugMon_Handler + .word 0 + .word PendSV_Handler + .word SysTick_Handler + .word WWDG_IRQHandler + .word PVD_IRQHandler + .word TAMPER_IRQHandler + .word RTC_IRQHandler + .word FLASH_IRQHandler + .word RCC_IRQHandler + .word EXTI0_IRQHandler + .word EXTI1_IRQHandler + .word EXTI2_IRQHandler + .word EXTI3_IRQHandler + .word EXTI4_IRQHandler + .word DMA1_Channel1_IRQHandler + .word DMA1_Channel2_IRQHandler + .word DMA1_Channel3_IRQHandler + .word DMA1_Channel4_IRQHandler + .word DMA1_Channel5_IRQHandler + .word DMA1_Channel6_IRQHandler + .word DMA1_Channel7_IRQHandler + .word ADC1_IRQHandler + .word 0 + .word 0 + .word 0 + .word 0 + .word EXTI9_5_IRQHandler + .word TIM1_BRK_TIM15_IRQHandler + .word TIM1_UP_TIM16_IRQHandler + .word TIM1_TRG_COM_TIM17_IRQHandler + .word TIM1_CC_IRQHandler + .word TIM2_IRQHandler + .word TIM3_IRQHandler + .word 0 + .word I2C1_EV_IRQHandler + .word I2C1_ER_IRQHandler + .word 0 + .word 0 + .word SPI1_IRQHandler + .word 0 + .word USART1_IRQHandler + .word USART2_IRQHandler + .word 0 + .word EXTI15_10_IRQHandler + .word RTCAlarm_IRQHandler + .word CEC_IRQHandler + .word 0 + .word 0 + .word 0 + .word 0 + .word 0 + .word 0 + .word 0 + .word 0 + .word 0 + .word 0 + .word 0 + .word TIM6_DAC_IRQHandler + .word TIM7_IRQHandler + .word 0 + .word 0 + .word 0 + .word 0 + .word 0 + .word 0 + .word 0 + .word 0 + .word 0 + .word 0 + .word 0 + .word 0 + .word 0 + .word 0 + .word 0 + .word 0 + .word 0 + .word 0 + .word 0 + .word 0 + .word 0 + .word 0 + .word 0 + .word 0 + .word 0 + .word 0 + .word 0 + .word 0 + .word 0 + .word 0 + .word 0 + .word 0 + .word 0 + .word 0 + .word 0 + .word 0 + .word 0 + .word 0 + .word 0 + .word 0 + .word 0 + .word 0 + .word 0 + .word BootRAM /* @0x01CC. This is for boot in RAM mode for + STM32F10x Medium Value Line Density devices. */ + +/******************************************************************************* +* +* Provide weak aliases for each Exception handler to the Default_Handler. +* As they are weak aliases, any function with the same name will override +* this definition. +* +*******************************************************************************/ + + + .weak NMI_Handler + .thumb_set NMI_Handler,Default_Handler + + .weak HardFault_Handler + .thumb_set HardFault_Handler,Default_Handler + + .weak MemManage_Handler + .thumb_set MemManage_Handler,Default_Handler + + .weak BusFault_Handler + .thumb_set BusFault_Handler,Default_Handler + + .weak UsageFault_Handler + .thumb_set UsageFault_Handler,Default_Handler + + .weak SVC_Handler + .thumb_set SVC_Handler,Default_Handler + + .weak DebugMon_Handler + .thumb_set DebugMon_Handler,Default_Handler + + .weak PendSV_Handler + .thumb_set PendSV_Handler,Default_Handler + + .weak SysTick_Handler + .thumb_set SysTick_Handler,Default_Handler + + .weak WWDG_IRQHandler + .thumb_set WWDG_IRQHandler,Default_Handler + + .weak PVD_IRQHandler + .thumb_set PVD_IRQHandler,Default_Handler + + .weak TAMPER_IRQHandler + .thumb_set TAMPER_IRQHandler,Default_Handler + + .weak RTC_IRQHandler + .thumb_set RTC_IRQHandler,Default_Handler + + .weak FLASH_IRQHandler + .thumb_set FLASH_IRQHandler,Default_Handler + + .weak RCC_IRQHandler + .thumb_set RCC_IRQHandler,Default_Handler + + .weak EXTI0_IRQHandler + .thumb_set EXTI0_IRQHandler,Default_Handler + + .weak EXTI1_IRQHandler + .thumb_set EXTI1_IRQHandler,Default_Handler + + .weak EXTI2_IRQHandler + .thumb_set EXTI2_IRQHandler,Default_Handler + + .weak EXTI3_IRQHandler + .thumb_set EXTI3_IRQHandler,Default_Handler + + .weak EXTI4_IRQHandler + .thumb_set EXTI4_IRQHandler,Default_Handler + + .weak DMA1_Channel1_IRQHandler + .thumb_set DMA1_Channel1_IRQHandler,Default_Handler + + .weak DMA1_Channel2_IRQHandler + .thumb_set DMA1_Channel2_IRQHandler,Default_Handler + + .weak DMA1_Channel3_IRQHandler + .thumb_set DMA1_Channel3_IRQHandler,Default_Handler + + .weak DMA1_Channel4_IRQHandler + .thumb_set DMA1_Channel4_IRQHandler,Default_Handler + + .weak DMA1_Channel5_IRQHandler + .thumb_set DMA1_Channel5_IRQHandler,Default_Handler + + .weak DMA1_Channel6_IRQHandler + .thumb_set DMA1_Channel6_IRQHandler,Default_Handler + + .weak DMA1_Channel7_IRQHandler + .thumb_set DMA1_Channel7_IRQHandler,Default_Handler + + .weak ADC1_IRQHandler + .thumb_set ADC1_IRQHandler,Default_Handler + + .weak EXTI9_5_IRQHandler + .thumb_set EXTI9_5_IRQHandler,Default_Handler + + .weak TIM1_BRK_TIM15_IRQHandler + .thumb_set TIM1_BRK_TIM15_IRQHandler,Default_Handler + + .weak TIM1_UP_TIM16_IRQHandler + .thumb_set TIM1_UP_TIM16_IRQHandler,Default_Handler + + .weak TIM1_TRG_COM_TIM17_IRQHandler + .thumb_set TIM1_TRG_COM_TIM17_IRQHandler,Default_Handler + + .weak TIM1_CC_IRQHandler + .thumb_set TIM1_CC_IRQHandler,Default_Handler + + .weak TIM2_IRQHandler + .thumb_set TIM2_IRQHandler,Default_Handler + + .weak TIM3_IRQHandler + .thumb_set TIM3_IRQHandler,Default_Handler + + .weak I2C1_EV_IRQHandler + .thumb_set I2C1_EV_IRQHandler,Default_Handler + + .weak I2C1_ER_IRQHandler + .thumb_set I2C1_ER_IRQHandler,Default_Handler + + .weak SPI1_IRQHandler + .thumb_set SPI1_IRQHandler,Default_Handler + + .weak USART1_IRQHandler + .thumb_set USART1_IRQHandler,Default_Handler + + .weak USART2_IRQHandler + .thumb_set USART2_IRQHandler,Default_Handler + + .weak EXTI15_10_IRQHandler + .thumb_set EXTI15_10_IRQHandler,Default_Handler + + .weak RTCAlarm_IRQHandler + .thumb_set RTCAlarm_IRQHandler,Default_Handler + + .weak CEC_IRQHandler + .thumb_set CEC_IRQHandler,Default_Handler + + .weak TIM6_DAC_IRQHandler + .thumb_set TIM6_DAC_IRQHandler,Default_Handler + + .weak TIM7_IRQHandler + .thumb_set TIM7_IRQHandler,Default_Handler + +/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ + diff --git a/Libraries/CMSIS/Device/ST/STM32F10x/Source/Templates/TrueSTUDIO/startup_stm32f10x_md.s b/Libraries/CMSIS/Device/ST/STM32F10x/Source/Templates/TrueSTUDIO/startup_stm32f10x_md.s new file mode 100644 index 0000000..7e2f3f6 --- /dev/null +++ b/Libraries/CMSIS/Device/ST/STM32F10x/Source/Templates/TrueSTUDIO/startup_stm32f10x_md.s @@ -0,0 +1,369 @@ +/** + ****************************************************************************** + * @file startup_stm32f10x_md.s + * @author MCD Application Team + * @version V3.6.1 + * @date 09-March-2012 + * @brief STM32F10x Medium Density Devices vector table for Atollic toolchain. + * This module performs: + * - Set the initial SP + * - Set the initial PC == Reset_Handler, + * - Set the vector table entries with the exceptions ISR address + * - Configure the clock system + * - Branches to main in the C library (which eventually + * calls main()). + * After Reset the Cortex-M3 processor is in Thread mode, + * priority is Privileged, and the Stack is set to Main. + ****************************************************************************** + * @attention + * + *

© COPYRIGHT 2012 STMicroelectronics

+ * + * Licensed under MCD-ST Liberty SW License Agreement V2, (the "License"); + * You may not use this file except in compliance with the License. + * You may obtain a copy of the License at: + * + * http://www.st.com/software_license_agreement_liberty_v2 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, + * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + * + ****************************************************************************** + */ + + .syntax unified + .cpu cortex-m3 + .fpu softvfp + .thumb + +.global g_pfnVectors +.global Default_Handler + +/* start address for the initialization values of the .data section. +defined in linker script */ +.word _sidata +/* start address for the .data section. defined in linker script */ +.word _sdata +/* end address for the .data section. defined in linker script */ +.word _edata +/* start address for the .bss section. defined in linker script */ +.word _sbss +/* end address for the .bss section. defined in linker script */ +.word _ebss + +.equ BootRAM, 0xF108F85F +/** + * @brief This is the code that gets called when the processor first + * starts execution following a reset event. Only the absolutely + * necessary set is performed, after which the application + * supplied main() routine is called. + * @param None + * @retval : None +*/ + + .section .text.Reset_Handler + .weak Reset_Handler + .type Reset_Handler, %function +Reset_Handler: + +/* Copy the data segment initializers from flash to SRAM */ + movs r1, #0 + b LoopCopyDataInit + +CopyDataInit: + ldr r3, =_sidata + ldr r3, [r3, r1] + str r3, [r0, r1] + adds r1, r1, #4 + +LoopCopyDataInit: + ldr r0, =_sdata + ldr r3, =_edata + adds r2, r0, r1 + cmp r2, r3 + bcc CopyDataInit + ldr r2, =_sbss + b LoopFillZerobss +/* Zero fill the bss segment. */ +FillZerobss: + movs r3, #0 + str r3, [r2], #4 + +LoopFillZerobss: + ldr r3, = _ebss + cmp r2, r3 + bcc FillZerobss + +/* Call the clock system intitialization function.*/ + bl SystemInit +/* Call static constructors */ + bl __libc_init_array +/* Call the application's entry point.*/ + bl main + bx lr +.size Reset_Handler, .-Reset_Handler + +/** + * @brief This is the code that gets called when the processor receives an + * unexpected interrupt. This simply enters an infinite loop, preserving + * the system state for examination by a debugger. + * + * @param None + * @retval : None +*/ + .section .text.Default_Handler,"ax",%progbits +Default_Handler: +Infinite_Loop: + b Infinite_Loop + .size Default_Handler, .-Default_Handler +/****************************************************************************** +* +* The minimal vector table for a Cortex M3. Note that the proper constructs +* must be placed on this to ensure that it ends up at physical address +* 0x0000.0000. +* +******************************************************************************/ + .section .isr_vector,"a",%progbits + .type g_pfnVectors, %object + .size g_pfnVectors, .-g_pfnVectors + + +g_pfnVectors: + .word _estack + .word Reset_Handler + .word NMI_Handler + .word HardFault_Handler + .word MemManage_Handler + .word BusFault_Handler + .word UsageFault_Handler + .word 0 + .word 0 + .word 0 + .word 0 + .word SVC_Handler + .word DebugMon_Handler + .word 0 + .word PendSV_Handler + .word SysTick_Handler + .word WWDG_IRQHandler + .word PVD_IRQHandler + .word TAMPER_IRQHandler + .word RTC_IRQHandler + .word FLASH_IRQHandler + .word RCC_IRQHandler + .word EXTI0_IRQHandler + .word EXTI1_IRQHandler + .word EXTI2_IRQHandler + .word EXTI3_IRQHandler + .word EXTI4_IRQHandler + .word DMA1_Channel1_IRQHandler + .word DMA1_Channel2_IRQHandler + .word DMA1_Channel3_IRQHandler + .word DMA1_Channel4_IRQHandler + .word DMA1_Channel5_IRQHandler + .word DMA1_Channel6_IRQHandler + .word DMA1_Channel7_IRQHandler + .word ADC1_2_IRQHandler + .word USB_HP_CAN1_TX_IRQHandler + .word USB_LP_CAN1_RX0_IRQHandler + .word CAN1_RX1_IRQHandler + .word CAN1_SCE_IRQHandler + .word EXTI9_5_IRQHandler + .word TIM1_BRK_IRQHandler + .word TIM1_UP_IRQHandler + .word TIM1_TRG_COM_IRQHandler + .word TIM1_CC_IRQHandler + .word TIM2_IRQHandler + .word TIM3_IRQHandler + .word TIM4_IRQHandler + .word I2C1_EV_IRQHandler + .word I2C1_ER_IRQHandler + .word I2C2_EV_IRQHandler + .word I2C2_ER_IRQHandler + .word SPI1_IRQHandler + .word SPI2_IRQHandler + .word USART1_IRQHandler + .word USART2_IRQHandler + .word USART3_IRQHandler + .word EXTI15_10_IRQHandler + .word RTCAlarm_IRQHandler + .word USBWakeUp_IRQHandler + .word 0 + .word 0 + .word 0 + .word 0 + .word 0 + .word 0 + .word 0 + .word BootRAM /* @0x108. This is for boot in RAM mode for + STM32F10x Medium Density devices. */ + +/******************************************************************************* +* +* Provide weak aliases for each Exception handler to the Default_Handler. +* As they are weak aliases, any function with the same name will override +* this definition. +* +*******************************************************************************/ + + .weak NMI_Handler + .thumb_set NMI_Handler,Default_Handler + + .weak HardFault_Handler + .thumb_set HardFault_Handler,Default_Handler + + .weak MemManage_Handler + .thumb_set MemManage_Handler,Default_Handler + + .weak BusFault_Handler + .thumb_set BusFault_Handler,Default_Handler + + .weak UsageFault_Handler + .thumb_set UsageFault_Handler,Default_Handler + + .weak SVC_Handler + .thumb_set SVC_Handler,Default_Handler + + .weak DebugMon_Handler + .thumb_set DebugMon_Handler,Default_Handler + + .weak PendSV_Handler + .thumb_set PendSV_Handler,Default_Handler + + .weak SysTick_Handler + .thumb_set SysTick_Handler,Default_Handler + + .weak WWDG_IRQHandler + .thumb_set WWDG_IRQHandler,Default_Handler + + .weak PVD_IRQHandler + .thumb_set PVD_IRQHandler,Default_Handler + + .weak TAMPER_IRQHandler + .thumb_set TAMPER_IRQHandler,Default_Handler + + .weak RTC_IRQHandler + .thumb_set RTC_IRQHandler,Default_Handler + + .weak FLASH_IRQHandler + .thumb_set FLASH_IRQHandler,Default_Handler + + .weak RCC_IRQHandler + .thumb_set RCC_IRQHandler,Default_Handler + + .weak EXTI0_IRQHandler + .thumb_set EXTI0_IRQHandler,Default_Handler + + .weak EXTI1_IRQHandler + .thumb_set EXTI1_IRQHandler,Default_Handler + + .weak EXTI2_IRQHandler + .thumb_set EXTI2_IRQHandler,Default_Handler + + .weak EXTI3_IRQHandler + .thumb_set EXTI3_IRQHandler,Default_Handler + + .weak EXTI4_IRQHandler + .thumb_set EXTI4_IRQHandler,Default_Handler + + .weak DMA1_Channel1_IRQHandler + .thumb_set DMA1_Channel1_IRQHandler,Default_Handler + + .weak DMA1_Channel2_IRQHandler + .thumb_set DMA1_Channel2_IRQHandler,Default_Handler + + .weak DMA1_Channel3_IRQHandler + .thumb_set DMA1_Channel3_IRQHandler,Default_Handler + + .weak DMA1_Channel4_IRQHandler + .thumb_set DMA1_Channel4_IRQHandler,Default_Handler + + .weak DMA1_Channel5_IRQHandler + .thumb_set DMA1_Channel5_IRQHandler,Default_Handler + + .weak DMA1_Channel6_IRQHandler + .thumb_set DMA1_Channel6_IRQHandler,Default_Handler + + .weak DMA1_Channel7_IRQHandler + .thumb_set DMA1_Channel7_IRQHandler,Default_Handler + + .weak ADC1_2_IRQHandler + .thumb_set ADC1_2_IRQHandler,Default_Handler + + .weak USB_HP_CAN1_TX_IRQHandler + .thumb_set USB_HP_CAN1_TX_IRQHandler,Default_Handler + + .weak USB_LP_CAN1_RX0_IRQHandler + .thumb_set USB_LP_CAN1_RX0_IRQHandler,Default_Handler + + .weak CAN1_RX1_IRQHandler + .thumb_set CAN1_RX1_IRQHandler,Default_Handler + + .weak CAN1_SCE_IRQHandler + .thumb_set CAN1_SCE_IRQHandler,Default_Handler + + .weak EXTI9_5_IRQHandler + .thumb_set EXTI9_5_IRQHandler,Default_Handler + + .weak TIM1_BRK_IRQHandler + .thumb_set TIM1_BRK_IRQHandler,Default_Handler + + .weak TIM1_UP_IRQHandler + .thumb_set TIM1_UP_IRQHandler,Default_Handler + + .weak TIM1_TRG_COM_IRQHandler + .thumb_set TIM1_TRG_COM_IRQHandler,Default_Handler + + .weak TIM1_CC_IRQHandler + .thumb_set TIM1_CC_IRQHandler,Default_Handler + + .weak TIM2_IRQHandler + .thumb_set TIM2_IRQHandler,Default_Handler + + .weak TIM3_IRQHandler + .thumb_set TIM3_IRQHandler,Default_Handler + + .weak TIM4_IRQHandler + .thumb_set TIM4_IRQHandler,Default_Handler + + .weak I2C1_EV_IRQHandler + .thumb_set I2C1_EV_IRQHandler,Default_Handler + + .weak I2C1_ER_IRQHandler + .thumb_set I2C1_ER_IRQHandler,Default_Handler + + .weak I2C2_EV_IRQHandler + .thumb_set I2C2_EV_IRQHandler,Default_Handler + + .weak I2C2_ER_IRQHandler + .thumb_set I2C2_ER_IRQHandler,Default_Handler + + .weak SPI1_IRQHandler + .thumb_set SPI1_IRQHandler,Default_Handler + + .weak SPI2_IRQHandler + .thumb_set SPI2_IRQHandler,Default_Handler + + .weak USART1_IRQHandler + .thumb_set USART1_IRQHandler,Default_Handler + + .weak USART2_IRQHandler + .thumb_set USART2_IRQHandler,Default_Handler + + .weak USART3_IRQHandler + .thumb_set USART3_IRQHandler,Default_Handler + + .weak EXTI15_10_IRQHandler + .thumb_set EXTI15_10_IRQHandler,Default_Handler + + .weak RTCAlarm_IRQHandler + .thumb_set RTCAlarm_IRQHandler,Default_Handler + + .weak USBWakeUp_IRQHandler + .thumb_set USBWakeUp_IRQHandler,Default_Handler + +/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ + diff --git a/Libraries/CMSIS/Device/ST/STM32F10x/Source/Templates/TrueSTUDIO/startup_stm32f10x_md_vl.s b/Libraries/CMSIS/Device/ST/STM32F10x/Source/Templates/TrueSTUDIO/startup_stm32f10x_md_vl.s new file mode 100644 index 0000000..2427331 --- /dev/null +++ b/Libraries/CMSIS/Device/ST/STM32F10x/Source/Templates/TrueSTUDIO/startup_stm32f10x_md_vl.s @@ -0,0 +1,414 @@ +/** + ****************************************************************************** + * @file startup_stm32f10x_md_vl.s + * @author MCD Application Team + * @version V3.6.1 + * @date 09-March-2012 + * @brief STM32F10x Medium Density Value Line Devices vector table for Atollic + * toolchain. + * This module performs: + * - Set the initial SP + * - Set the initial PC == Reset_Handler, + * - Set the vector table entries with the exceptions ISR address + * - Configure the clock system + * - Branches to main in the C library (which eventually + * calls main()). + * After Reset the Cortex-M3 processor is in Thread mode, + * priority is Privileged, and the Stack is set to Main. + ****************************************************************************** + * @attention + * + *

© COPYRIGHT 2012 STMicroelectronics

+ * + * Licensed under MCD-ST Liberty SW License Agreement V2, (the "License"); + * You may not use this file except in compliance with the License. + * You may obtain a copy of the License at: + * + * http://www.st.com/software_license_agreement_liberty_v2 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, + * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + * + ****************************************************************************** + */ + + .syntax unified + .cpu cortex-m3 + .fpu softvfp + .thumb + +.global g_pfnVectors +.global Default_Handler + +/* start address for the initialization values of the .data section. +defined in linker script */ +.word _sidata +/* start address for the .data section. defined in linker script */ +.word _sdata +/* end address for the .data section. defined in linker script */ +.word _edata +/* start address for the .bss section. defined in linker script */ +.word _sbss +/* end address for the .bss section. defined in linker script */ +.word _ebss + +.equ BootRAM, 0xF108F85F +/** + * @brief This is the code that gets called when the processor first + * starts execution following a reset event. Only the absolutely + * necessary set is performed, after which the application + * supplied main() routine is called. + * @param None + * @retval : None +*/ + + .section .text.Reset_Handler + .weak Reset_Handler + .type Reset_Handler, %function +Reset_Handler: + +/* Copy the data segment initializers from flash to SRAM */ + movs r1, #0 + b LoopCopyDataInit + +CopyDataInit: + ldr r3, =_sidata + ldr r3, [r3, r1] + str r3, [r0, r1] + adds r1, r1, #4 + +LoopCopyDataInit: + ldr r0, =_sdata + ldr r3, =_edata + adds r2, r0, r1 + cmp r2, r3 + bcc CopyDataInit + ldr r2, =_sbss + b LoopFillZerobss +/* Zero fill the bss segment. */ +FillZerobss: + movs r3, #0 + str r3, [r2], #4 + +LoopFillZerobss: + ldr r3, = _ebss + cmp r2, r3 + bcc FillZerobss + +/* Call the clock system intitialization function.*/ + bl SystemInit +/* Call static constructors */ + bl __libc_init_array +/* Call the application's entry point.*/ + bl main + bx lr +.size Reset_Handler, .-Reset_Handler + +/** + * @brief This is the code that gets called when the processor receives an + * unexpected interrupt. This simply enters an infinite loop, preserving + * the system state for examination by a debugger. + * + * @param None + * @retval : None +*/ + .section .text.Default_Handler,"ax",%progbits +Default_Handler: +Infinite_Loop: + b Infinite_Loop + .size Default_Handler, .-Default_Handler +/****************************************************************************** +* +* The minimal vector table for a Cortex M3. Note that the proper constructs +* must be placed on this to ensure that it ends up at physical address +* 0x0000.0000. +* +******************************************************************************/ + .section .isr_vector,"a",%progbits + .type g_pfnVectors, %object + .size g_pfnVectors, .-g_pfnVectors + + +g_pfnVectors: + .word _estack + .word Reset_Handler + .word NMI_Handler + .word HardFault_Handler + .word MemManage_Handler + .word BusFault_Handler + .word UsageFault_Handler + .word 0 + .word 0 + .word 0 + .word 0 + .word SVC_Handler + .word DebugMon_Handler + .word 0 + .word PendSV_Handler + .word SysTick_Handler + .word WWDG_IRQHandler + .word PVD_IRQHandler + .word TAMPER_IRQHandler + .word RTC_IRQHandler + .word FLASH_IRQHandler + .word RCC_IRQHandler + .word EXTI0_IRQHandler + .word EXTI1_IRQHandler + .word EXTI2_IRQHandler + .word EXTI3_IRQHandler + .word EXTI4_IRQHandler + .word DMA1_Channel1_IRQHandler + .word DMA1_Channel2_IRQHandler + .word DMA1_Channel3_IRQHandler + .word DMA1_Channel4_IRQHandler + .word DMA1_Channel5_IRQHandler + .word DMA1_Channel6_IRQHandler + .word DMA1_Channel7_IRQHandler + .word ADC1_IRQHandler + .word 0 + .word 0 + .word 0 + .word 0 + .word EXTI9_5_IRQHandler + .word TIM1_BRK_TIM15_IRQHandler + .word TIM1_UP_TIM16_IRQHandler + .word TIM1_TRG_COM_TIM17_IRQHandler + .word TIM1_CC_IRQHandler + .word TIM2_IRQHandler + .word TIM3_IRQHandler + .word TIM4_IRQHandler + .word I2C1_EV_IRQHandler + .word I2C1_ER_IRQHandler + .word I2C2_EV_IRQHandler + .word I2C2_ER_IRQHandler + .word SPI1_IRQHandler + .word SPI2_IRQHandler + .word USART1_IRQHandler + .word USART2_IRQHandler + .word USART3_IRQHandler + .word EXTI15_10_IRQHandler + .word RTCAlarm_IRQHandler + .word CEC_IRQHandler + .word 0 + .word 0 + .word 0 + .word 0 + .word 0 + .word 0 + .word 0 + .word 0 + .word 0 + .word 0 + .word 0 + .word TIM6_DAC_IRQHandler + .word TIM7_IRQHandler + .word 0 + .word 0 + .word 0 + .word 0 + .word 0 + .word 0 + .word 0 + .word 0 + .word 0 + .word 0 + .word 0 + .word 0 + .word 0 + .word 0 + .word 0 + .word 0 + .word 0 + .word 0 + .word 0 + .word 0 + .word 0 + .word 0 + .word 0 + .word 0 + .word 0 + .word 0 + .word 0 + .word 0 + .word 0 + .word 0 + .word 0 + .word 0 + .word 0 + .word 0 + .word 0 + .word 0 + .word 0 + .word 0 + .word 0 + .word 0 + .word 0 + .word 0 + .word 0 + .word BootRAM /* @0x01CC. This is for boot in RAM mode for + STM32F10x Medium Value Line Density devices. */ + +/******************************************************************************* +* +* Provide weak aliases for each Exception handler to the Default_Handler. +* As they are weak aliases, any function with the same name will override +* this definition. +* +*******************************************************************************/ + + + .weak NMI_Handler + .thumb_set NMI_Handler,Default_Handler + + .weak HardFault_Handler + .thumb_set HardFault_Handler,Default_Handler + + .weak MemManage_Handler + .thumb_set MemManage_Handler,Default_Handler + + .weak BusFault_Handler + .thumb_set BusFault_Handler,Default_Handler + + .weak UsageFault_Handler + .thumb_set UsageFault_Handler,Default_Handler + + .weak SVC_Handler + .thumb_set SVC_Handler,Default_Handler + + .weak DebugMon_Handler + .thumb_set DebugMon_Handler,Default_Handler + + .weak PendSV_Handler + .thumb_set PendSV_Handler,Default_Handler + + .weak SysTick_Handler + .thumb_set SysTick_Handler,Default_Handler + + .weak WWDG_IRQHandler + .thumb_set WWDG_IRQHandler,Default_Handler + + .weak PVD_IRQHandler + .thumb_set PVD_IRQHandler,Default_Handler + + .weak TAMPER_IRQHandler + .thumb_set TAMPER_IRQHandler,Default_Handler + + .weak RTC_IRQHandler + .thumb_set RTC_IRQHandler,Default_Handler + + .weak FLASH_IRQHandler + .thumb_set FLASH_IRQHandler,Default_Handler + + .weak RCC_IRQHandler + .thumb_set RCC_IRQHandler,Default_Handler + + .weak EXTI0_IRQHandler + .thumb_set EXTI0_IRQHandler,Default_Handler + + .weak EXTI1_IRQHandler + .thumb_set EXTI1_IRQHandler,Default_Handler + + .weak EXTI2_IRQHandler + .thumb_set EXTI2_IRQHandler,Default_Handler + + .weak EXTI3_IRQHandler + .thumb_set EXTI3_IRQHandler,Default_Handler + + .weak EXTI4_IRQHandler + .thumb_set EXTI4_IRQHandler,Default_Handler + + .weak DMA1_Channel1_IRQHandler + .thumb_set DMA1_Channel1_IRQHandler,Default_Handler + + .weak DMA1_Channel2_IRQHandler + .thumb_set DMA1_Channel2_IRQHandler,Default_Handler + + .weak DMA1_Channel3_IRQHandler + .thumb_set DMA1_Channel3_IRQHandler,Default_Handler + + .weak DMA1_Channel4_IRQHandler + .thumb_set DMA1_Channel4_IRQHandler,Default_Handler + + .weak DMA1_Channel5_IRQHandler + .thumb_set DMA1_Channel5_IRQHandler,Default_Handler + + .weak DMA1_Channel6_IRQHandler + .thumb_set DMA1_Channel6_IRQHandler,Default_Handler + + .weak DMA1_Channel7_IRQHandler + .thumb_set DMA1_Channel7_IRQHandler,Default_Handler + + .weak ADC1_IRQHandler + .thumb_set ADC1_IRQHandler,Default_Handler + + .weak EXTI9_5_IRQHandler + .thumb_set EXTI9_5_IRQHandler,Default_Handler + + .weak TIM1_BRK_TIM15_IRQHandler + .thumb_set TIM1_BRK_TIM15_IRQHandler,Default_Handler + + .weak TIM1_UP_TIM16_IRQHandler + .thumb_set TIM1_UP_TIM16_IRQHandler,Default_Handler + + .weak TIM1_TRG_COM_TIM17_IRQHandler + .thumb_set TIM1_TRG_COM_TIM17_IRQHandler,Default_Handler + + .weak TIM1_CC_IRQHandler + .thumb_set TIM1_CC_IRQHandler,Default_Handler + + .weak TIM2_IRQHandler + .thumb_set TIM2_IRQHandler,Default_Handler + + .weak TIM3_IRQHandler + .thumb_set TIM3_IRQHandler,Default_Handler + + .weak TIM4_IRQHandler + .thumb_set TIM4_IRQHandler,Default_Handler + + .weak I2C1_EV_IRQHandler + .thumb_set I2C1_EV_IRQHandler,Default_Handler + + .weak I2C1_ER_IRQHandler + .thumb_set I2C1_ER_IRQHandler,Default_Handler + + .weak I2C2_EV_IRQHandler + .thumb_set I2C2_EV_IRQHandler,Default_Handler + + .weak I2C2_ER_IRQHandler + .thumb_set I2C2_ER_IRQHandler,Default_Handler + + .weak SPI1_IRQHandler + .thumb_set SPI1_IRQHandler,Default_Handler + + .weak SPI2_IRQHandler + .thumb_set SPI2_IRQHandler,Default_Handler + + .weak USART1_IRQHandler + .thumb_set USART1_IRQHandler,Default_Handler + + .weak USART2_IRQHandler + .thumb_set USART2_IRQHandler,Default_Handler + + .weak USART3_IRQHandler + .thumb_set USART3_IRQHandler,Default_Handler + + .weak EXTI15_10_IRQHandler + .thumb_set EXTI15_10_IRQHandler,Default_Handler + + .weak RTCAlarm_IRQHandler + .thumb_set RTCAlarm_IRQHandler,Default_Handler + + .weak CEC_IRQHandler + .thumb_set CEC_IRQHandler,Default_Handler + + .weak TIM6_DAC_IRQHandler + .thumb_set TIM6_DAC_IRQHandler,Default_Handler + + .weak TIM7_IRQHandler + .thumb_set TIM7_IRQHandler,Default_Handler + +/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ + diff --git a/Libraries/CMSIS/Device/ST/STM32F10x/Source/Templates/TrueSTUDIO/startup_stm32f10x_xl.s b/Libraries/CMSIS/Device/ST/STM32F10x/Source/Templates/TrueSTUDIO/startup_stm32f10x_xl.s new file mode 100644 index 0000000..366a965 --- /dev/null +++ b/Libraries/CMSIS/Device/ST/STM32F10x/Source/Templates/TrueSTUDIO/startup_stm32f10x_xl.s @@ -0,0 +1,473 @@ +/** + ****************************************************************************** + * @file startup_stm32f10x_xl.s + * @author MCD Application Team + * @version V3.6.1 + * @date 09-March-2012 + * @brief STM32F10x XL-Density Devices vector table for TrueSTUDIO toolchain. + * This module performs: + * - Set the initial SP + * - Set the initial PC == Reset_Handler, + * - Set the vector table entries with the exceptions ISR address + * - Configure the clock system and the external SRAM mounted on + * STM3210E-EVAL board to be used as data memory (optional, + * to be enabled by user) + * - Branches to main in the C library (which eventually + * calls main()). + * After Reset the Cortex-M3 processor is in Thread mode, + * priority is Privileged, and the Stack is set to Main. + ****************************************************************************** + * @attention + * + *

© COPYRIGHT 2012 STMicroelectronics

+ * + * Licensed under MCD-ST Liberty SW License Agreement V2, (the "License"); + * You may not use this file except in compliance with the License. + * You may obtain a copy of the License at: + * + * http://www.st.com/software_license_agreement_liberty_v2 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, + * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + * + ****************************************************************************** + */ + + .syntax unified + .cpu cortex-m3 + .fpu softvfp + .thumb + +.global g_pfnVectors +.global Default_Handler + +/* start address for the initialization values of the .data section. +defined in linker script */ +.word _sidata +/* start address for the .data section. defined in linker script */ +.word _sdata +/* end address for the .data section. defined in linker script */ +.word _edata +/* start address for the .bss section. defined in linker script */ +.word _sbss +/* end address for the .bss section. defined in linker script */ +.word _ebss + +.equ BootRAM, 0xF1E0F85F +/** + * @brief This is the code that gets called when the processor first + * starts execution following a reset event. Only the absolutely + * necessary set is performed, after which the application + * supplied main() routine is called. + * @param None + * @retval : None +*/ + + .section .text.Reset_Handler + .weak Reset_Handler + .type Reset_Handler, %function +Reset_Handler: + +/* Copy the data segment initializers from flash to SRAM */ + movs r1, #0 + b LoopCopyDataInit + +CopyDataInit: + ldr r3, =_sidata + ldr r3, [r3, r1] + str r3, [r0, r1] + adds r1, r1, #4 + +LoopCopyDataInit: + ldr r0, =_sdata + ldr r3, =_edata + adds r2, r0, r1 + cmp r2, r3 + bcc CopyDataInit + ldr r2, =_sbss + b LoopFillZerobss +/* Zero fill the bss segment. */ +FillZerobss: + movs r3, #0 + str r3, [r2], #4 + +LoopFillZerobss: + ldr r3, = _ebss + cmp r2, r3 + bcc FillZerobss + +/* Call the clock system intitialization function.*/ + bl SystemInit +/* Call static constructors */ + bl __libc_init_array +/* Call the application's entry point.*/ + bl main + bx lr +.size Reset_Handler, .-Reset_Handler + +/** + * @brief This is the code that gets called when the processor receives an + * unexpected interrupt. This simply enters an infinite loop, preserving + * the system state for examination by a debugger. + * @param None + * @retval None +*/ + .section .text.Default_Handler,"ax",%progbits +Default_Handler: +Infinite_Loop: + b Infinite_Loop + .size Default_Handler, .-Default_Handler +/****************************************************************************** +* +* The minimal vector table for a Cortex M3. Note that the proper constructs +* must be placed on this to ensure that it ends up at physical address +* 0x0000.0000. +* +*******************************************************************************/ + .section .isr_vector,"a",%progbits + .type g_pfnVectors, %object + .size g_pfnVectors, .-g_pfnVectors + + +g_pfnVectors: + .word _estack + .word Reset_Handler + .word NMI_Handler + .word HardFault_Handler + .word MemManage_Handler + .word BusFault_Handler + .word UsageFault_Handler + .word 0 + .word 0 + .word 0 + .word 0 + .word SVC_Handler + .word DebugMon_Handler + .word 0 + .word PendSV_Handler + .word SysTick_Handler + .word WWDG_IRQHandler + .word PVD_IRQHandler + .word TAMPER_IRQHandler + .word RTC_IRQHandler + .word FLASH_IRQHandler + .word RCC_IRQHandler + .word EXTI0_IRQHandler + .word EXTI1_IRQHandler + .word EXTI2_IRQHandler + .word EXTI3_IRQHandler + .word EXTI4_IRQHandler + .word DMA1_Channel1_IRQHandler + .word DMA1_Channel2_IRQHandler + .word DMA1_Channel3_IRQHandler + .word DMA1_Channel4_IRQHandler + .word DMA1_Channel5_IRQHandler + .word DMA1_Channel6_IRQHandler + .word DMA1_Channel7_IRQHandler + .word ADC1_2_IRQHandler + .word USB_HP_CAN1_TX_IRQHandler + .word USB_LP_CAN1_RX0_IRQHandler + .word CAN1_RX1_IRQHandler + .word CAN1_SCE_IRQHandler + .word EXTI9_5_IRQHandler + .word TIM1_BRK_TIM9_IRQHandler + .word TIM1_UP_TIM10_IRQHandler + .word TIM1_TRG_COM_TIM11_IRQHandler + .word TIM1_CC_IRQHandler + .word TIM2_IRQHandler + .word TIM3_IRQHandler + .word TIM4_IRQHandler + .word I2C1_EV_IRQHandler + .word I2C1_ER_IRQHandler + .word I2C2_EV_IRQHandler + .word I2C2_ER_IRQHandler + .word SPI1_IRQHandler + .word SPI2_IRQHandler + .word USART1_IRQHandler + .word USART2_IRQHandler + .word USART3_IRQHandler + .word EXTI15_10_IRQHandler + .word RTCAlarm_IRQHandler + .word USBWakeUp_IRQHandler + .word TIM8_BRK_TIM12_IRQHandler + .word TIM8_UP_TIM13_IRQHandler + .word TIM8_TRG_COM_TIM14_IRQHandler + .word TIM8_CC_IRQHandler + .word ADC3_IRQHandler + .word FSMC_IRQHandler + .word SDIO_IRQHandler + .word TIM5_IRQHandler + .word SPI3_IRQHandler + .word UART4_IRQHandler + .word UART5_IRQHandler + .word TIM6_IRQHandler + .word TIM7_IRQHandler + .word DMA2_Channel1_IRQHandler + .word DMA2_Channel2_IRQHandler + .word DMA2_Channel3_IRQHandler + .word DMA2_Channel4_5_IRQHandler + .word 0 + .word 0 + .word 0 + .word 0 + .word 0 + .word 0 + .word 0 + .word 0 + .word 0 + .word 0 + .word 0 + .word 0 + .word 0 + .word 0 + .word 0 + .word 0 + .word 0 + .word 0 + .word 0 + .word 0 + .word 0 + .word 0 + .word 0 + .word 0 + .word 0 + .word 0 + .word 0 + .word 0 + .word 0 + .word 0 + .word 0 + .word 0 + .word 0 + .word 0 + .word 0 + .word 0 + .word 0 + .word 0 + .word 0 + .word 0 + .word 0 + .word 0 + .word 0 + .word 0 + .word BootRAM /* @0x1E0. This is for boot in RAM mode for + STM32F10x XL-Density devices. */ +/******************************************************************************* +* +* Provide weak aliases for each Exception handler to the Default_Handler. +* As they are weak aliases, any function with the same name will override +* this definition. +* +*******************************************************************************/ + + .weak NMI_Handler + .thumb_set NMI_Handler,Default_Handler + + .weak HardFault_Handler + .thumb_set HardFault_Handler,Default_Handler + + .weak MemManage_Handler + .thumb_set MemManage_Handler,Default_Handler + + .weak BusFault_Handler + .thumb_set BusFault_Handler,Default_Handler + + .weak UsageFault_Handler + .thumb_set UsageFault_Handler,Default_Handler + + .weak SVC_Handler + .thumb_set SVC_Handler,Default_Handler + + .weak DebugMon_Handler + .thumb_set DebugMon_Handler,Default_Handler + + .weak PendSV_Handler + .thumb_set PendSV_Handler,Default_Handler + + .weak SysTick_Handler + .thumb_set SysTick_Handler,Default_Handler + + .weak WWDG_IRQHandler + .thumb_set WWDG_IRQHandler,Default_Handler + + .weak PVD_IRQHandler + .thumb_set PVD_IRQHandler,Default_Handler + + .weak TAMPER_IRQHandler + .thumb_set TAMPER_IRQHandler,Default_Handler + + .weak RTC_IRQHandler + .thumb_set RTC_IRQHandler,Default_Handler + + .weak FLASH_IRQHandler + .thumb_set FLASH_IRQHandler,Default_Handler + + .weak RCC_IRQHandler + .thumb_set RCC_IRQHandler,Default_Handler + + .weak EXTI0_IRQHandler + .thumb_set EXTI0_IRQHandler,Default_Handler + + .weak EXTI1_IRQHandler + .thumb_set EXTI1_IRQHandler,Default_Handler + + .weak EXTI2_IRQHandler + .thumb_set EXTI2_IRQHandler,Default_Handler + + .weak EXTI3_IRQHandler + .thumb_set EXTI3_IRQHandler,Default_Handler + + .weak EXTI4_IRQHandler + .thumb_set EXTI4_IRQHandler,Default_Handler + + .weak DMA1_Channel1_IRQHandler + .thumb_set DMA1_Channel1_IRQHandler,Default_Handler + + .weak DMA1_Channel2_IRQHandler + .thumb_set DMA1_Channel2_IRQHandler,Default_Handler + + .weak DMA1_Channel3_IRQHandler + .thumb_set DMA1_Channel3_IRQHandler,Default_Handler + + .weak DMA1_Channel4_IRQHandler + .thumb_set DMA1_Channel4_IRQHandler,Default_Handler + + .weak DMA1_Channel5_IRQHandler + .thumb_set DMA1_Channel5_IRQHandler,Default_Handler + + .weak DMA1_Channel6_IRQHandler + .thumb_set DMA1_Channel6_IRQHandler,Default_Handler + + .weak DMA1_Channel7_IRQHandler + .thumb_set DMA1_Channel7_IRQHandler,Default_Handler + + .weak ADC1_2_IRQHandler + .thumb_set ADC1_2_IRQHandler,Default_Handler + + .weak USB_HP_CAN1_TX_IRQHandler + .thumb_set USB_HP_CAN1_TX_IRQHandler,Default_Handler + + .weak USB_LP_CAN1_RX0_IRQHandler + .thumb_set USB_LP_CAN1_RX0_IRQHandler,Default_Handler + + .weak CAN1_RX1_IRQHandler + .thumb_set CAN1_RX1_IRQHandler,Default_Handler + + .weak CAN1_SCE_IRQHandler + .thumb_set CAN1_SCE_IRQHandler,Default_Handler + + .weak EXTI9_5_IRQHandler + .thumb_set EXTI9_5_IRQHandler,Default_Handler + + .weak TIM1_BRK_TIM9_IRQHandler + .thumb_set TIM1_BRK_TIM9_IRQHandler,Default_Handler + + .weak TIM1_UP_TIM10_IRQHandler + .thumb_set TIM1_UP_TIM10_IRQHandler,Default_Handler + + .weak TIM1_TRG_COM_TIM11_IRQHandler + .thumb_set TIM1_TRG_COM_TIM11_IRQHandler,Default_Handler + + .weak TIM1_CC_IRQHandler + .thumb_set TIM1_CC_IRQHandler,Default_Handler + + .weak TIM2_IRQHandler + .thumb_set TIM2_IRQHandler,Default_Handler + + .weak TIM3_IRQHandler + .thumb_set TIM3_IRQHandler,Default_Handler + + .weak TIM4_IRQHandler + .thumb_set TIM4_IRQHandler,Default_Handler + + .weak I2C1_EV_IRQHandler + .thumb_set I2C1_EV_IRQHandler,Default_Handler + + .weak I2C1_ER_IRQHandler + .thumb_set I2C1_ER_IRQHandler,Default_Handler + + .weak I2C2_EV_IRQHandler + .thumb_set I2C2_EV_IRQHandler,Default_Handler + + .weak I2C2_ER_IRQHandler + .thumb_set I2C2_ER_IRQHandler,Default_Handler + + .weak SPI1_IRQHandler + .thumb_set SPI1_IRQHandler,Default_Handler + + .weak SPI2_IRQHandler + .thumb_set SPI2_IRQHandler,Default_Handler + + .weak USART1_IRQHandler + .thumb_set USART1_IRQHandler,Default_Handler + + .weak USART2_IRQHandler + .thumb_set USART2_IRQHandler,Default_Handler + + .weak USART3_IRQHandler + .thumb_set USART3_IRQHandler,Default_Handler + + .weak EXTI15_10_IRQHandler + .thumb_set EXTI15_10_IRQHandler,Default_Handler + + .weak RTCAlarm_IRQHandler + .thumb_set RTCAlarm_IRQHandler,Default_Handler + + .weak USBWakeUp_IRQHandler + .thumb_set USBWakeUp_IRQHandler,Default_Handler + + .weak TIM8_BRK_TIM12_IRQHandler + .thumb_set TIM8_BRK_TIM12_IRQHandler,Default_Handler + + .weak TIM8_UP_TIM13_IRQHandler + .thumb_set TIM8_UP_TIM13_IRQHandler,Default_Handler + + .weak TIM8_TRG_COM_TIM14_IRQHandler + .thumb_set TIM8_TRG_COM_TIM14_IRQHandler,Default_Handler + + .weak TIM8_CC_IRQHandler + .thumb_set TIM8_CC_IRQHandler,Default_Handler + + .weak ADC3_IRQHandler + .thumb_set ADC3_IRQHandler,Default_Handler + + .weak FSMC_IRQHandler + .thumb_set FSMC_IRQHandler,Default_Handler + + .weak SDIO_IRQHandler + .thumb_set SDIO_IRQHandler,Default_Handler + + .weak TIM5_IRQHandler + .thumb_set TIM5_IRQHandler,Default_Handler + + .weak SPI3_IRQHandler + .thumb_set SPI3_IRQHandler,Default_Handler + + .weak UART4_IRQHandler + .thumb_set UART4_IRQHandler,Default_Handler + + .weak UART5_IRQHandler + .thumb_set UART5_IRQHandler,Default_Handler + + .weak TIM6_IRQHandler + .thumb_set TIM6_IRQHandler,Default_Handler + + .weak TIM7_IRQHandler + .thumb_set TIM7_IRQHandler,Default_Handler + + .weak DMA2_Channel1_IRQHandler + .thumb_set DMA2_Channel1_IRQHandler,Default_Handler + + .weak DMA2_Channel2_IRQHandler + .thumb_set DMA2_Channel2_IRQHandler,Default_Handler + + .weak DMA2_Channel3_IRQHandler + .thumb_set DMA2_Channel3_IRQHandler,Default_Handler + + .weak DMA2_Channel4_5_IRQHandler + .thumb_set DMA2_Channel4_5_IRQHandler,Default_Handler + +/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ diff --git a/Libraries/CMSIS/Device/ST/STM32F10x/Source/Templates/arm/startup_stm32f10x_cl.s b/Libraries/CMSIS/Device/ST/STM32F10x/Source/Templates/arm/startup_stm32f10x_cl.s new file mode 100644 index 0000000..15a7768 --- /dev/null +++ b/Libraries/CMSIS/Device/ST/STM32F10x/Source/Templates/arm/startup_stm32f10x_cl.s @@ -0,0 +1,375 @@ +;******************** (C) COPYRIGHT 2012 STMicroelectronics ******************** +;* File Name : startup_stm32f10x_cl.s +;* Author : MCD Application Team +;* Version : V3.6.1 +;* Date : 09-March-2012 +;* Description : STM32F10x Connectivity line devices vector table for MDK-ARM +;* toolchain. +;* This module performs: +;* - Set the initial SP +;* - Set the initial PC == Reset_Handler +;* - Set the vector table entries with the exceptions ISR address +;* - Configure the clock system +;* - Branches to __main in the C library (which eventually +;* calls main()). +;* After Reset the CortexM3 processor is in Thread mode, +;* priority is Privileged, and the Stack is set to Main. +;* <<< Use Configuration Wizard in Context Menu >>> +;******************************************************************************* +; +; Licensed under MCD-ST Liberty SW License Agreement V2, (the "License"); +; You may not use this file except in compliance with the License. +; You may obtain a copy of the License at: +; +; http://www.st.com/software_license_agreement_liberty_v2 +; +; Unless required by applicable law or agreed to in writing, software +; distributed under the License is distributed on an "AS IS" BASIS, +; WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +; See the License for the specific language governing permissions and +; limitations under the License. +; +;******************************************************************************* + +; Amount of memory (in bytes) allocated for Stack +; Tailor this value to your application needs +; Stack Configuration +; Stack Size (in Bytes) <0x0-0xFFFFFFFF:8> +; + +Stack_Size EQU 0x00000400 + + AREA STACK, NOINIT, READWRITE, ALIGN=3 +Stack_Mem SPACE Stack_Size +__initial_sp + + +; Heap Configuration +; Heap Size (in Bytes) <0x0-0xFFFFFFFF:8> +; + +Heap_Size EQU 0x00000200 + + AREA HEAP, NOINIT, READWRITE, ALIGN=3 +__heap_base +Heap_Mem SPACE Heap_Size +__heap_limit + + PRESERVE8 + THUMB + + +; Vector Table Mapped to Address 0 at Reset + AREA RESET, DATA, READONLY + EXPORT __Vectors + EXPORT __Vectors_End + EXPORT __Vectors_Size + +__Vectors DCD __initial_sp ; Top of Stack + DCD Reset_Handler ; Reset Handler + DCD NMI_Handler ; NMI Handler + DCD HardFault_Handler ; Hard Fault Handler + DCD MemManage_Handler ; MPU Fault Handler + DCD BusFault_Handler ; Bus Fault Handler + DCD UsageFault_Handler ; Usage Fault Handler + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD SVC_Handler ; SVCall Handler + DCD DebugMon_Handler ; Debug Monitor Handler + DCD 0 ; Reserved + DCD PendSV_Handler ; PendSV Handler + DCD SysTick_Handler ; SysTick Handler + + ; External Interrupts + DCD WWDG_IRQHandler ; Window Watchdog + DCD PVD_IRQHandler ; PVD through EXTI Line detect + DCD TAMPER_IRQHandler ; Tamper + DCD RTC_IRQHandler ; RTC + DCD FLASH_IRQHandler ; Flash + DCD RCC_IRQHandler ; RCC + DCD EXTI0_IRQHandler ; EXTI Line 0 + DCD EXTI1_IRQHandler ; EXTI Line 1 + DCD EXTI2_IRQHandler ; EXTI Line 2 + DCD EXTI3_IRQHandler ; EXTI Line 3 + DCD EXTI4_IRQHandler ; EXTI Line 4 + DCD DMA1_Channel1_IRQHandler ; DMA1 Channel 1 + DCD DMA1_Channel2_IRQHandler ; DMA1 Channel 2 + DCD DMA1_Channel3_IRQHandler ; DMA1 Channel 3 + DCD DMA1_Channel4_IRQHandler ; DMA1 Channel 4 + DCD DMA1_Channel5_IRQHandler ; DMA1 Channel 5 + DCD DMA1_Channel6_IRQHandler ; DMA1 Channel 6 + DCD DMA1_Channel7_IRQHandler ; DMA1 Channel 7 + DCD ADC1_2_IRQHandler ; ADC1 and ADC2 + DCD CAN1_TX_IRQHandler ; CAN1 TX + DCD CAN1_RX0_IRQHandler ; CAN1 RX0 + DCD CAN1_RX1_IRQHandler ; CAN1 RX1 + DCD CAN1_SCE_IRQHandler ; CAN1 SCE + DCD EXTI9_5_IRQHandler ; EXTI Line 9..5 + DCD TIM1_BRK_IRQHandler ; TIM1 Break + DCD TIM1_UP_IRQHandler ; TIM1 Update + DCD TIM1_TRG_COM_IRQHandler ; TIM1 Trigger and Commutation + DCD TIM1_CC_IRQHandler ; TIM1 Capture Compare + DCD TIM2_IRQHandler ; TIM2 + DCD TIM3_IRQHandler ; TIM3 + DCD TIM4_IRQHandler ; TIM4 + DCD I2C1_EV_IRQHandler ; I2C1 Event + DCD I2C1_ER_IRQHandler ; I2C1 Error + DCD I2C2_EV_IRQHandler ; I2C2 Event + DCD I2C2_ER_IRQHandler ; I2C1 Error + DCD SPI1_IRQHandler ; SPI1 + DCD SPI2_IRQHandler ; SPI2 + DCD USART1_IRQHandler ; USART1 + DCD USART2_IRQHandler ; USART2 + DCD USART3_IRQHandler ; USART3 + DCD EXTI15_10_IRQHandler ; EXTI Line 15..10 + DCD RTCAlarm_IRQHandler ; RTC alarm through EXTI line + DCD OTG_FS_WKUP_IRQHandler ; USB OTG FS Wakeup through EXTI line + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD TIM5_IRQHandler ; TIM5 + DCD SPI3_IRQHandler ; SPI3 + DCD UART4_IRQHandler ; UART4 + DCD UART5_IRQHandler ; UART5 + DCD TIM6_IRQHandler ; TIM6 + DCD TIM7_IRQHandler ; TIM7 + DCD DMA2_Channel1_IRQHandler ; DMA2 Channel1 + DCD DMA2_Channel2_IRQHandler ; DMA2 Channel2 + DCD DMA2_Channel3_IRQHandler ; DMA2 Channel3 + DCD DMA2_Channel4_IRQHandler ; DMA2 Channel4 + DCD DMA2_Channel5_IRQHandler ; DMA2 Channel5 + DCD ETH_IRQHandler ; Ethernet + DCD ETH_WKUP_IRQHandler ; Ethernet Wakeup through EXTI line + DCD CAN2_TX_IRQHandler ; CAN2 TX + DCD CAN2_RX0_IRQHandler ; CAN2 RX0 + DCD CAN2_RX1_IRQHandler ; CAN2 RX1 + DCD CAN2_SCE_IRQHandler ; CAN2 SCE + DCD OTG_FS_IRQHandler ; USB OTG FS +__Vectors_End + +__Vectors_Size EQU __Vectors_End - __Vectors + + AREA |.text|, CODE, READONLY + +; Reset handler +Reset_Handler PROC + EXPORT Reset_Handler [WEAK] + IMPORT SystemInit + IMPORT __main + LDR R0, =SystemInit + BLX R0 + LDR R0, =__main + BX R0 + ENDP + +; Dummy Exception Handlers (infinite loops which can be modified) + +NMI_Handler PROC + EXPORT NMI_Handler [WEAK] + B . + ENDP +HardFault_Handler\ + PROC + EXPORT HardFault_Handler [WEAK] + B . + ENDP +MemManage_Handler\ + PROC + EXPORT MemManage_Handler [WEAK] + B . + ENDP +BusFault_Handler\ + PROC + EXPORT BusFault_Handler [WEAK] + B . + ENDP +UsageFault_Handler\ + PROC + EXPORT UsageFault_Handler [WEAK] + B . + ENDP +SVC_Handler PROC + EXPORT SVC_Handler [WEAK] + B . + ENDP +DebugMon_Handler\ + PROC + EXPORT DebugMon_Handler [WEAK] + B . + ENDP +PendSV_Handler PROC + EXPORT PendSV_Handler [WEAK] + B . + ENDP +SysTick_Handler PROC + EXPORT SysTick_Handler [WEAK] + B . + ENDP + +Default_Handler PROC + + EXPORT WWDG_IRQHandler [WEAK] + EXPORT PVD_IRQHandler [WEAK] + EXPORT TAMPER_IRQHandler [WEAK] + EXPORT RTC_IRQHandler [WEAK] + EXPORT FLASH_IRQHandler [WEAK] + EXPORT RCC_IRQHandler [WEAK] + EXPORT EXTI0_IRQHandler [WEAK] + EXPORT EXTI1_IRQHandler [WEAK] + EXPORT EXTI2_IRQHandler [WEAK] + EXPORT EXTI3_IRQHandler [WEAK] + EXPORT EXTI4_IRQHandler [WEAK] + EXPORT DMA1_Channel1_IRQHandler [WEAK] + EXPORT DMA1_Channel2_IRQHandler [WEAK] + EXPORT DMA1_Channel3_IRQHandler [WEAK] + EXPORT DMA1_Channel4_IRQHandler [WEAK] + EXPORT DMA1_Channel5_IRQHandler [WEAK] + EXPORT DMA1_Channel6_IRQHandler [WEAK] + EXPORT DMA1_Channel7_IRQHandler [WEAK] + EXPORT ADC1_2_IRQHandler [WEAK] + EXPORT CAN1_TX_IRQHandler [WEAK] + EXPORT CAN1_RX0_IRQHandler [WEAK] + EXPORT CAN1_RX1_IRQHandler [WEAK] + EXPORT CAN1_SCE_IRQHandler [WEAK] + EXPORT EXTI9_5_IRQHandler [WEAK] + EXPORT TIM1_BRK_IRQHandler [WEAK] + EXPORT TIM1_UP_IRQHandler [WEAK] + EXPORT TIM1_TRG_COM_IRQHandler [WEAK] + EXPORT TIM1_CC_IRQHandler [WEAK] + EXPORT TIM2_IRQHandler [WEAK] + EXPORT TIM3_IRQHandler [WEAK] + EXPORT TIM4_IRQHandler [WEAK] + EXPORT I2C1_EV_IRQHandler [WEAK] + EXPORT I2C1_ER_IRQHandler [WEAK] + EXPORT I2C2_EV_IRQHandler [WEAK] + EXPORT I2C2_ER_IRQHandler [WEAK] + EXPORT SPI1_IRQHandler [WEAK] + EXPORT SPI2_IRQHandler [WEAK] + EXPORT USART1_IRQHandler [WEAK] + EXPORT USART2_IRQHandler [WEAK] + EXPORT USART3_IRQHandler [WEAK] + EXPORT EXTI15_10_IRQHandler [WEAK] + EXPORT RTCAlarm_IRQHandler [WEAK] + EXPORT OTG_FS_WKUP_IRQHandler [WEAK] + EXPORT TIM5_IRQHandler [WEAK] + EXPORT SPI3_IRQHandler [WEAK] + EXPORT UART4_IRQHandler [WEAK] + EXPORT UART5_IRQHandler [WEAK] + EXPORT TIM6_IRQHandler [WEAK] + EXPORT TIM7_IRQHandler [WEAK] + EXPORT DMA2_Channel1_IRQHandler [WEAK] + EXPORT DMA2_Channel2_IRQHandler [WEAK] + EXPORT DMA2_Channel3_IRQHandler [WEAK] + EXPORT DMA2_Channel4_IRQHandler [WEAK] + EXPORT DMA2_Channel5_IRQHandler [WEAK] + EXPORT ETH_IRQHandler [WEAK] + EXPORT ETH_WKUP_IRQHandler [WEAK] + EXPORT CAN2_TX_IRQHandler [WEAK] + EXPORT CAN2_RX0_IRQHandler [WEAK] + EXPORT CAN2_RX1_IRQHandler [WEAK] + EXPORT CAN2_SCE_IRQHandler [WEAK] + EXPORT OTG_FS_IRQHandler [WEAK] + +WWDG_IRQHandler +PVD_IRQHandler +TAMPER_IRQHandler +RTC_IRQHandler +FLASH_IRQHandler +RCC_IRQHandler +EXTI0_IRQHandler +EXTI1_IRQHandler +EXTI2_IRQHandler +EXTI3_IRQHandler +EXTI4_IRQHandler +DMA1_Channel1_IRQHandler +DMA1_Channel2_IRQHandler +DMA1_Channel3_IRQHandler +DMA1_Channel4_IRQHandler +DMA1_Channel5_IRQHandler +DMA1_Channel6_IRQHandler +DMA1_Channel7_IRQHandler +ADC1_2_IRQHandler +CAN1_TX_IRQHandler +CAN1_RX0_IRQHandler +CAN1_RX1_IRQHandler +CAN1_SCE_IRQHandler +EXTI9_5_IRQHandler +TIM1_BRK_IRQHandler +TIM1_UP_IRQHandler +TIM1_TRG_COM_IRQHandler +TIM1_CC_IRQHandler +TIM2_IRQHandler +TIM3_IRQHandler +TIM4_IRQHandler +I2C1_EV_IRQHandler +I2C1_ER_IRQHandler +I2C2_EV_IRQHandler +I2C2_ER_IRQHandler +SPI1_IRQHandler +SPI2_IRQHandler +USART1_IRQHandler +USART2_IRQHandler +USART3_IRQHandler +EXTI15_10_IRQHandler +RTCAlarm_IRQHandler +OTG_FS_WKUP_IRQHandler +TIM5_IRQHandler +SPI3_IRQHandler +UART4_IRQHandler +UART5_IRQHandler +TIM6_IRQHandler +TIM7_IRQHandler +DMA2_Channel1_IRQHandler +DMA2_Channel2_IRQHandler +DMA2_Channel3_IRQHandler +DMA2_Channel4_IRQHandler +DMA2_Channel5_IRQHandler +ETH_IRQHandler +ETH_WKUP_IRQHandler +CAN2_TX_IRQHandler +CAN2_RX0_IRQHandler +CAN2_RX1_IRQHandler +CAN2_SCE_IRQHandler +OTG_FS_IRQHandler + + B . + + ENDP + + ALIGN + +;******************************************************************************* +; User Stack and Heap initialization +;******************************************************************************* + IF :DEF:__MICROLIB + + EXPORT __initial_sp + EXPORT __heap_base + EXPORT __heap_limit + + ELSE + + IMPORT __use_two_region_memory + EXPORT __user_initial_stackheap + +__user_initial_stackheap + + LDR R0, = Heap_Mem + LDR R1, =(Stack_Mem + Stack_Size) + LDR R2, = (Heap_Mem + Heap_Size) + LDR R3, = Stack_Mem + BX LR + + ALIGN + + ENDIF + + END + +;************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE***** diff --git a/Libraries/CMSIS/Device/ST/STM32F10x/Source/Templates/arm/startup_stm32f10x_hd.s b/Libraries/CMSIS/Device/ST/STM32F10x/Source/Templates/arm/startup_stm32f10x_hd.s new file mode 100644 index 0000000..3d25c03 --- /dev/null +++ b/Libraries/CMSIS/Device/ST/STM32F10x/Source/Templates/arm/startup_stm32f10x_hd.s @@ -0,0 +1,366 @@ +;******************** (C) COPYRIGHT 2012 STMicroelectronics ******************** +;* File Name : startup_stm32f10x_hd.s +;* Author : MCD Application Team +;* Version : V3.6.1 +;* Date : 09-March-2012 +;* Description : STM32F10x High Density Devices vector table for MDK-ARM +;* toolchain. +;* This module performs: +;* - Set the initial SP +;* - Set the initial PC == Reset_Handler +;* - Set the vector table entries with the exceptions ISR address +;* - Configure the clock system and also configure the external +;* SRAM mounted on STM3210E-EVAL board to be used as data +;* memory (optional, to be enabled by user) +;* - Branches to __main in the C library (which eventually +;* calls main()). +;* After Reset the CortexM3 processor is in Thread mode, +;* priority is Privileged, and the Stack is set to Main. +;* <<< Use Configuration Wizard in Context Menu >>> +;******************************************************************************* +; +; Licensed under MCD-ST Liberty SW License Agreement V2, (the "License"); +; You may not use this file except in compliance with the License. +; You may obtain a copy of the License at: +; +; http://www.st.com/software_license_agreement_liberty_v2 +; +; Unless required by applicable law or agreed to in writing, software +; distributed under the License is distributed on an "AS IS" BASIS, +; WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +; See the License for the specific language governing permissions and +; limitations under the License. +; +;******************************************************************************* + +; Amount of memory (in bytes) allocated for Stack +; Tailor this value to your application needs +; Stack Configuration +; Stack Size (in Bytes) <0x0-0xFFFFFFFF:8> +; + +; 2015-08-02 armfly ջռ32K +Stack_Size EQU 0x00008000 + + AREA STACK, NOINIT, READWRITE, ALIGN=3 +Stack_Mem SPACE Stack_Size +__initial_sp + +; Heap Configuration +; Heap Size (in Bytes) <0x0-0xFFFFFFFF:8> +; + +Heap_Size EQU 0x00000200 + + AREA HEAP, NOINIT, READWRITE, ALIGN=3 +__heap_base +Heap_Mem SPACE Heap_Size +__heap_limit + + PRESERVE8 + THUMB + + +; Vector Table Mapped to Address 0 at Reset + AREA RESET, DATA, READONLY + EXPORT __Vectors + EXPORT __Vectors_End + EXPORT __Vectors_Size + +__Vectors DCD __initial_sp ; Top of Stack + DCD Reset_Handler ; Reset Handler + DCD NMI_Handler ; NMI Handler + DCD HardFault_Handler ; Hard Fault Handler + DCD MemManage_Handler ; MPU Fault Handler + DCD BusFault_Handler ; Bus Fault Handler + DCD UsageFault_Handler ; Usage Fault Handler + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD SVC_Handler ; SVCall Handler + DCD DebugMon_Handler ; Debug Monitor Handler + DCD 0 ; Reserved + DCD PendSV_Handler ; PendSV Handler + DCD SysTick_Handler ; SysTick Handler + + ; External Interrupts + DCD WWDG_IRQHandler ; Window Watchdog + DCD PVD_IRQHandler ; PVD through EXTI Line detect + DCD TAMPER_IRQHandler ; Tamper + DCD RTC_IRQHandler ; RTC + DCD FLASH_IRQHandler ; Flash + DCD RCC_IRQHandler ; RCC + DCD EXTI0_IRQHandler ; EXTI Line 0 + DCD EXTI1_IRQHandler ; EXTI Line 1 + DCD EXTI2_IRQHandler ; EXTI Line 2 + DCD EXTI3_IRQHandler ; EXTI Line 3 + DCD EXTI4_IRQHandler ; EXTI Line 4 + DCD DMA1_Channel1_IRQHandler ; DMA1 Channel 1 + DCD DMA1_Channel2_IRQHandler ; DMA1 Channel 2 + DCD DMA1_Channel3_IRQHandler ; DMA1 Channel 3 + DCD DMA1_Channel4_IRQHandler ; DMA1 Channel 4 + DCD DMA1_Channel5_IRQHandler ; DMA1 Channel 5 + DCD DMA1_Channel6_IRQHandler ; DMA1 Channel 6 + DCD DMA1_Channel7_IRQHandler ; DMA1 Channel 7 + DCD ADC1_2_IRQHandler ; ADC1 & ADC2 + DCD USB_HP_CAN1_TX_IRQHandler ; USB High Priority or CAN1 TX + DCD USB_LP_CAN1_RX0_IRQHandler ; USB Low Priority or CAN1 RX0 + DCD CAN1_RX1_IRQHandler ; CAN1 RX1 + DCD CAN1_SCE_IRQHandler ; CAN1 SCE + DCD EXTI9_5_IRQHandler ; EXTI Line 9..5 + DCD TIM1_BRK_IRQHandler ; TIM1 Break + DCD TIM1_UP_IRQHandler ; TIM1 Update + DCD TIM1_TRG_COM_IRQHandler ; TIM1 Trigger and Commutation + DCD TIM1_CC_IRQHandler ; TIM1 Capture Compare + DCD TIM2_IRQHandler ; TIM2 + DCD TIM3_IRQHandler ; TIM3 + DCD TIM4_IRQHandler ; TIM4 + DCD I2C1_EV_IRQHandler ; I2C1 Event + DCD I2C1_ER_IRQHandler ; I2C1 Error + DCD I2C2_EV_IRQHandler ; I2C2 Event + DCD I2C2_ER_IRQHandler ; I2C2 Error + DCD SPI1_IRQHandler ; SPI1 + DCD SPI2_IRQHandler ; SPI2 + DCD USART1_IRQHandler ; USART1 + DCD USART2_IRQHandler ; USART2 + DCD USART3_IRQHandler ; USART3 + DCD EXTI15_10_IRQHandler ; EXTI Line 15..10 + DCD RTCAlarm_IRQHandler ; RTC Alarm through EXTI Line + DCD USBWakeUp_IRQHandler ; USB Wakeup from suspend + DCD TIM8_BRK_IRQHandler ; TIM8 Break + DCD TIM8_UP_IRQHandler ; TIM8 Update + DCD TIM8_TRG_COM_IRQHandler ; TIM8 Trigger and Commutation + DCD TIM8_CC_IRQHandler ; TIM8 Capture Compare + DCD ADC3_IRQHandler ; ADC3 + DCD FSMC_IRQHandler ; FSMC + DCD SDIO_IRQHandler ; SDIO + DCD TIM5_IRQHandler ; TIM5 + DCD SPI3_IRQHandler ; SPI3 + DCD UART4_IRQHandler ; UART4 + DCD UART5_IRQHandler ; UART5 + DCD TIM6_IRQHandler ; TIM6 + DCD TIM7_IRQHandler ; TIM7 + DCD DMA2_Channel1_IRQHandler ; DMA2 Channel1 + DCD DMA2_Channel2_IRQHandler ; DMA2 Channel2 + DCD DMA2_Channel3_IRQHandler ; DMA2 Channel3 + DCD DMA2_Channel4_5_IRQHandler ; DMA2 Channel4 & Channel5 +__Vectors_End + +__Vectors_Size EQU __Vectors_End - __Vectors + + AREA |.text|, CODE, READONLY + +; Reset handler +Reset_Handler PROC + EXPORT Reset_Handler [WEAK] + IMPORT __main + IMPORT SystemInit + LDR R0, =SystemInit + BLX R0 + LDR R0, =__main + BX R0 + ENDP + +; Dummy Exception Handlers (infinite loops which can be modified) + +NMI_Handler PROC + EXPORT NMI_Handler [WEAK] + B . + ENDP +HardFault_Handler\ + PROC + EXPORT HardFault_Handler [WEAK] + B . + ENDP +MemManage_Handler\ + PROC + EXPORT MemManage_Handler [WEAK] + B . + ENDP +BusFault_Handler\ + PROC + EXPORT BusFault_Handler [WEAK] + B . + ENDP +UsageFault_Handler\ + PROC + EXPORT UsageFault_Handler [WEAK] + B . + ENDP +SVC_Handler PROC + EXPORT SVC_Handler [WEAK] + B . + ENDP +DebugMon_Handler\ + PROC + EXPORT DebugMon_Handler [WEAK] + B . + ENDP +PendSV_Handler PROC + EXPORT PendSV_Handler [WEAK] + B . + ENDP +SysTick_Handler PROC + EXPORT SysTick_Handler [WEAK] + B . + ENDP + +Default_Handler PROC + + EXPORT WWDG_IRQHandler [WEAK] + EXPORT PVD_IRQHandler [WEAK] + EXPORT TAMPER_IRQHandler [WEAK] + EXPORT RTC_IRQHandler [WEAK] + EXPORT FLASH_IRQHandler [WEAK] + EXPORT RCC_IRQHandler [WEAK] + EXPORT EXTI0_IRQHandler [WEAK] + EXPORT EXTI1_IRQHandler [WEAK] + EXPORT EXTI2_IRQHandler [WEAK] + EXPORT EXTI3_IRQHandler [WEAK] + EXPORT EXTI4_IRQHandler [WEAK] + EXPORT DMA1_Channel1_IRQHandler [WEAK] + EXPORT DMA1_Channel2_IRQHandler [WEAK] + EXPORT DMA1_Channel3_IRQHandler [WEAK] + EXPORT DMA1_Channel4_IRQHandler [WEAK] + EXPORT DMA1_Channel5_IRQHandler [WEAK] + EXPORT DMA1_Channel6_IRQHandler [WEAK] + EXPORT DMA1_Channel7_IRQHandler [WEAK] + EXPORT ADC1_2_IRQHandler [WEAK] + EXPORT USB_HP_CAN1_TX_IRQHandler [WEAK] + EXPORT USB_LP_CAN1_RX0_IRQHandler [WEAK] + EXPORT CAN1_RX1_IRQHandler [WEAK] + EXPORT CAN1_SCE_IRQHandler [WEAK] + EXPORT EXTI9_5_IRQHandler [WEAK] + EXPORT TIM1_BRK_IRQHandler [WEAK] + EXPORT TIM1_UP_IRQHandler [WEAK] + EXPORT TIM1_TRG_COM_IRQHandler [WEAK] + EXPORT TIM1_CC_IRQHandler [WEAK] + EXPORT TIM2_IRQHandler [WEAK] + EXPORT TIM3_IRQHandler [WEAK] + EXPORT TIM4_IRQHandler [WEAK] + EXPORT I2C1_EV_IRQHandler [WEAK] + EXPORT I2C1_ER_IRQHandler [WEAK] + EXPORT I2C2_EV_IRQHandler [WEAK] + EXPORT I2C2_ER_IRQHandler [WEAK] + EXPORT SPI1_IRQHandler [WEAK] + EXPORT SPI2_IRQHandler [WEAK] + EXPORT USART1_IRQHandler [WEAK] + EXPORT USART2_IRQHandler [WEAK] + EXPORT USART3_IRQHandler [WEAK] + EXPORT EXTI15_10_IRQHandler [WEAK] + EXPORT RTCAlarm_IRQHandler [WEAK] + EXPORT USBWakeUp_IRQHandler [WEAK] + EXPORT TIM8_BRK_IRQHandler [WEAK] + EXPORT TIM8_UP_IRQHandler [WEAK] + EXPORT TIM8_TRG_COM_IRQHandler [WEAK] + EXPORT TIM8_CC_IRQHandler [WEAK] + EXPORT ADC3_IRQHandler [WEAK] + EXPORT FSMC_IRQHandler [WEAK] + EXPORT SDIO_IRQHandler [WEAK] + EXPORT TIM5_IRQHandler [WEAK] + EXPORT SPI3_IRQHandler [WEAK] + EXPORT UART4_IRQHandler [WEAK] + EXPORT UART5_IRQHandler [WEAK] + EXPORT TIM6_IRQHandler [WEAK] + EXPORT TIM7_IRQHandler [WEAK] + EXPORT DMA2_Channel1_IRQHandler [WEAK] + EXPORT DMA2_Channel2_IRQHandler [WEAK] + EXPORT DMA2_Channel3_IRQHandler [WEAK] + EXPORT DMA2_Channel4_5_IRQHandler [WEAK] + +WWDG_IRQHandler +PVD_IRQHandler +TAMPER_IRQHandler +RTC_IRQHandler +FLASH_IRQHandler +RCC_IRQHandler +EXTI0_IRQHandler +EXTI1_IRQHandler +EXTI2_IRQHandler +EXTI3_IRQHandler +EXTI4_IRQHandler +DMA1_Channel1_IRQHandler +DMA1_Channel2_IRQHandler +DMA1_Channel3_IRQHandler +DMA1_Channel4_IRQHandler +DMA1_Channel5_IRQHandler +DMA1_Channel6_IRQHandler +DMA1_Channel7_IRQHandler +ADC1_2_IRQHandler +USB_HP_CAN1_TX_IRQHandler +USB_LP_CAN1_RX0_IRQHandler +CAN1_RX1_IRQHandler +CAN1_SCE_IRQHandler +EXTI9_5_IRQHandler +TIM1_BRK_IRQHandler +TIM1_UP_IRQHandler +TIM1_TRG_COM_IRQHandler +TIM1_CC_IRQHandler +TIM2_IRQHandler +TIM3_IRQHandler +TIM4_IRQHandler +I2C1_EV_IRQHandler +I2C1_ER_IRQHandler +I2C2_EV_IRQHandler +I2C2_ER_IRQHandler +SPI1_IRQHandler +SPI2_IRQHandler +USART1_IRQHandler +USART2_IRQHandler +USART3_IRQHandler +EXTI15_10_IRQHandler +RTCAlarm_IRQHandler +USBWakeUp_IRQHandler +TIM8_BRK_IRQHandler +TIM8_UP_IRQHandler +TIM8_TRG_COM_IRQHandler +TIM8_CC_IRQHandler +ADC3_IRQHandler +FSMC_IRQHandler +SDIO_IRQHandler +TIM5_IRQHandler +SPI3_IRQHandler +UART4_IRQHandler +UART5_IRQHandler +TIM6_IRQHandler +TIM7_IRQHandler +DMA2_Channel1_IRQHandler +DMA2_Channel2_IRQHandler +DMA2_Channel3_IRQHandler +DMA2_Channel4_5_IRQHandler + B . + + ENDP + + ALIGN + +;******************************************************************************* +; User Stack and Heap initialization +;******************************************************************************* + IF :DEF:__MICROLIB + + EXPORT __initial_sp + EXPORT __heap_base + EXPORT __heap_limit + + ELSE + + IMPORT __use_two_region_memory + EXPORT __user_initial_stackheap + +__user_initial_stackheap + + LDR R0, = Heap_Mem + LDR R1, =(Stack_Mem + Stack_Size) + LDR R2, = (Heap_Mem + Heap_Size) + LDR R3, = Stack_Mem + BX LR + + ALIGN + + ENDIF + + END + +;************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE***** diff --git a/Libraries/CMSIS/Device/ST/STM32F10x/Source/Templates/arm/startup_stm32f10x_hd_vl.s b/Libraries/CMSIS/Device/ST/STM32F10x/Source/Templates/arm/startup_stm32f10x_hd_vl.s new file mode 100644 index 0000000..d6ac20c --- /dev/null +++ b/Libraries/CMSIS/Device/ST/STM32F10x/Source/Templates/arm/startup_stm32f10x_hd_vl.s @@ -0,0 +1,353 @@ +;******************** (C) COPYRIGHT 2012 STMicroelectronics ******************** +;* File Name : startup_stm32f10x_hd_vl.s +;* Author : MCD Application Team +;* Version : V3.6.1 +;* Date : 09-March-2012 +;* Description : STM32F10x High Density Value Line Devices vector table +;* for MDK-ARM toolchain. +;* This module performs: +;* - Set the initial SP +;* - Set the initial PC == Reset_Handler +;* - Set the vector table entries with the exceptions ISR address +;* - Configure the clock system and also configure the external +;* SRAM mounted on STM32100E-EVAL board to be used as data +;* memory (optional, to be enabled by user) +;* - Branches to __main in the C library (which eventually +;* calls main()). +;* After Reset the CortexM3 processor is in Thread mode, +;* priority is Privileged, and the Stack is set to Main. +;* <<< Use Configuration Wizard in Context Menu >>> +;******************************************************************************* +; +; Licensed under MCD-ST Liberty SW License Agreement V2, (the "License"); +; You may not use this file except in compliance with the License. +; You may obtain a copy of the License at: +; +; http://www.st.com/software_license_agreement_liberty_v2 +; +; Unless required by applicable law or agreed to in writing, software +; distributed under the License is distributed on an "AS IS" BASIS, +; WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +; See the License for the specific language governing permissions and +; limitations under the License. +; +;******************************************************************************* + +; Amount of memory (in bytes) allocated for Stack +; Tailor this value to your application needs +; Stack Configuration +; Stack Size (in Bytes) <0x0-0xFFFFFFFF:8> +; + +Stack_Size EQU 0x00000400 + + AREA STACK, NOINIT, READWRITE, ALIGN=3 +Stack_Mem SPACE Stack_Size +__initial_sp + + +; Heap Configuration +; Heap Size (in Bytes) <0x0-0xFFFFFFFF:8> +; + +Heap_Size EQU 0x00000200 + + AREA HEAP, NOINIT, READWRITE, ALIGN=3 +__heap_base +Heap_Mem SPACE Heap_Size +__heap_limit + + PRESERVE8 + THUMB + + +; Vector Table Mapped to Address 0 at Reset + AREA RESET, DATA, READONLY + EXPORT __Vectors + EXPORT __Vectors_End + EXPORT __Vectors_Size + +__Vectors DCD __initial_sp ; Top of Stack + DCD Reset_Handler ; Reset Handler + DCD NMI_Handler ; NMI Handler + DCD HardFault_Handler ; Hard Fault Handler + DCD MemManage_Handler ; MPU Fault Handler + DCD BusFault_Handler ; Bus Fault Handler + DCD UsageFault_Handler ; Usage Fault Handler + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD SVC_Handler ; SVCall Handler + DCD DebugMon_Handler ; Debug Monitor Handler + DCD 0 ; Reserved + DCD PendSV_Handler ; PendSV Handler + DCD SysTick_Handler ; SysTick Handler + + ; External Interrupts + DCD WWDG_IRQHandler ; Window Watchdog + DCD PVD_IRQHandler ; PVD through EXTI Line detect + DCD TAMPER_IRQHandler ; Tamper + DCD RTC_IRQHandler ; RTC + DCD FLASH_IRQHandler ; Flash + DCD RCC_IRQHandler ; RCC + DCD EXTI0_IRQHandler ; EXTI Line 0 + DCD EXTI1_IRQHandler ; EXTI Line 1 + DCD EXTI2_IRQHandler ; EXTI Line 2 + DCD EXTI3_IRQHandler ; EXTI Line 3 + DCD EXTI4_IRQHandler ; EXTI Line 4 + DCD DMA1_Channel1_IRQHandler ; DMA1 Channel 1 + DCD DMA1_Channel2_IRQHandler ; DMA1 Channel 2 + DCD DMA1_Channel3_IRQHandler ; DMA1 Channel 3 + DCD DMA1_Channel4_IRQHandler ; DMA1 Channel 4 + DCD DMA1_Channel5_IRQHandler ; DMA1 Channel 5 + DCD DMA1_Channel6_IRQHandler ; DMA1 Channel 6 + DCD DMA1_Channel7_IRQHandler ; DMA1 Channel 7 + DCD ADC1_IRQHandler ; ADC1 + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD EXTI9_5_IRQHandler ; EXTI Line 9..5 + DCD TIM1_BRK_TIM15_IRQHandler ; TIM1 Break and TIM15 + DCD TIM1_UP_TIM16_IRQHandler ; TIM1 Update and TIM16 + DCD TIM1_TRG_COM_TIM17_IRQHandler ; TIM1 Trigger and Commutation and TIM17 + DCD TIM1_CC_IRQHandler ; TIM1 Capture Compare + DCD TIM2_IRQHandler ; TIM2 + DCD TIM3_IRQHandler ; TIM3 + DCD TIM4_IRQHandler ; TIM4 + DCD I2C1_EV_IRQHandler ; I2C1 Event + DCD I2C1_ER_IRQHandler ; I2C1 Error + DCD I2C2_EV_IRQHandler ; I2C2 Event + DCD I2C2_ER_IRQHandler ; I2C2 Error + DCD SPI1_IRQHandler ; SPI1 + DCD SPI2_IRQHandler ; SPI2 + DCD USART1_IRQHandler ; USART1 + DCD USART2_IRQHandler ; USART2 + DCD USART3_IRQHandler ; USART3 + DCD EXTI15_10_IRQHandler ; EXTI Line 15..10 + DCD RTCAlarm_IRQHandler ; RTC Alarm through EXTI Line + DCD CEC_IRQHandler ; HDMI-CEC + DCD TIM12_IRQHandler ; TIM12 + DCD TIM13_IRQHandler ; TIM13 + DCD TIM14_IRQHandler ; TIM14 + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD TIM5_IRQHandler ; TIM5 + DCD SPI3_IRQHandler ; SPI3 + DCD UART4_IRQHandler ; UART4 + DCD UART5_IRQHandler ; UART5 + DCD TIM6_DAC_IRQHandler ; TIM6 and DAC underrun + DCD TIM7_IRQHandler ; TIM7 + DCD DMA2_Channel1_IRQHandler ; DMA2 Channel1 + DCD DMA2_Channel2_IRQHandler ; DMA2 Channel2 + DCD DMA2_Channel3_IRQHandler ; DMA2 Channel3 + DCD DMA2_Channel4_5_IRQHandler ; DMA2 Channel4 & Channel5 + DCD DMA2_Channel5_IRQHandler ; DMA2 Channel5 +__Vectors_End + +__Vectors_Size EQU __Vectors_End - __Vectors + + AREA |.text|, CODE, READONLY + +; Reset handler +Reset_Handler PROC + EXPORT Reset_Handler [WEAK] + IMPORT __main + IMPORT SystemInit + LDR R0, =SystemInit + BLX R0 + LDR R0, =__main + BX R0 + ENDP + +; Dummy Exception Handlers (infinite loops which can be modified) + +NMI_Handler PROC + EXPORT NMI_Handler [WEAK] + B . + ENDP +HardFault_Handler\ + PROC + EXPORT HardFault_Handler [WEAK] + B . + ENDP +MemManage_Handler\ + PROC + EXPORT MemManage_Handler [WEAK] + B . + ENDP +BusFault_Handler\ + PROC + EXPORT BusFault_Handler [WEAK] + B . + ENDP +UsageFault_Handler\ + PROC + EXPORT UsageFault_Handler [WEAK] + B . + ENDP +SVC_Handler PROC + EXPORT SVC_Handler [WEAK] + B . + ENDP +DebugMon_Handler\ + PROC + EXPORT DebugMon_Handler [WEAK] + B . + ENDP +PendSV_Handler PROC + EXPORT PendSV_Handler [WEAK] + B . + ENDP +SysTick_Handler PROC + EXPORT SysTick_Handler [WEAK] + B . + ENDP + +Default_Handler PROC + + EXPORT WWDG_IRQHandler [WEAK] + EXPORT PVD_IRQHandler [WEAK] + EXPORT TAMPER_IRQHandler [WEAK] + EXPORT RTC_IRQHandler [WEAK] + EXPORT FLASH_IRQHandler [WEAK] + EXPORT RCC_IRQHandler [WEAK] + EXPORT EXTI0_IRQHandler [WEAK] + EXPORT EXTI1_IRQHandler [WEAK] + EXPORT EXTI2_IRQHandler [WEAK] + EXPORT EXTI3_IRQHandler [WEAK] + EXPORT EXTI4_IRQHandler [WEAK] + EXPORT DMA1_Channel1_IRQHandler [WEAK] + EXPORT DMA1_Channel2_IRQHandler [WEAK] + EXPORT DMA1_Channel3_IRQHandler [WEAK] + EXPORT DMA1_Channel4_IRQHandler [WEAK] + EXPORT DMA1_Channel5_IRQHandler [WEAK] + EXPORT DMA1_Channel6_IRQHandler [WEAK] + EXPORT DMA1_Channel7_IRQHandler [WEAK] + EXPORT ADC1_IRQHandler [WEAK] + EXPORT EXTI9_5_IRQHandler [WEAK] + EXPORT TIM1_BRK_TIM15_IRQHandler [WEAK] + EXPORT TIM1_UP_TIM16_IRQHandler [WEAK] + EXPORT TIM1_TRG_COM_TIM17_IRQHandler [WEAK] + EXPORT TIM1_CC_IRQHandler [WEAK] + EXPORT TIM2_IRQHandler [WEAK] + EXPORT TIM3_IRQHandler [WEAK] + EXPORT TIM4_IRQHandler [WEAK] + EXPORT I2C1_EV_IRQHandler [WEAK] + EXPORT I2C1_ER_IRQHandler [WEAK] + EXPORT I2C2_EV_IRQHandler [WEAK] + EXPORT I2C2_ER_IRQHandler [WEAK] + EXPORT SPI1_IRQHandler [WEAK] + EXPORT SPI2_IRQHandler [WEAK] + EXPORT USART1_IRQHandler [WEAK] + EXPORT USART2_IRQHandler [WEAK] + EXPORT USART3_IRQHandler [WEAK] + EXPORT EXTI15_10_IRQHandler [WEAK] + EXPORT RTCAlarm_IRQHandler [WEAK] + EXPORT CEC_IRQHandler [WEAK] + EXPORT TIM12_IRQHandler [WEAK] + EXPORT TIM13_IRQHandler [WEAK] + EXPORT TIM14_IRQHandler [WEAK] + EXPORT TIM5_IRQHandler [WEAK] + EXPORT SPI3_IRQHandler [WEAK] + EXPORT UART4_IRQHandler [WEAK] + EXPORT UART5_IRQHandler [WEAK] + EXPORT TIM6_DAC_IRQHandler [WEAK] + EXPORT TIM7_IRQHandler [WEAK] + EXPORT DMA2_Channel1_IRQHandler [WEAK] + EXPORT DMA2_Channel2_IRQHandler [WEAK] + EXPORT DMA2_Channel3_IRQHandler [WEAK] + EXPORT DMA2_Channel4_5_IRQHandler [WEAK] + EXPORT DMA2_Channel5_IRQHandler [WEAK] + +WWDG_IRQHandler +PVD_IRQHandler +TAMPER_IRQHandler +RTC_IRQHandler +FLASH_IRQHandler +RCC_IRQHandler +EXTI0_IRQHandler +EXTI1_IRQHandler +EXTI2_IRQHandler +EXTI3_IRQHandler +EXTI4_IRQHandler +DMA1_Channel1_IRQHandler +DMA1_Channel2_IRQHandler +DMA1_Channel3_IRQHandler +DMA1_Channel4_IRQHandler +DMA1_Channel5_IRQHandler +DMA1_Channel6_IRQHandler +DMA1_Channel7_IRQHandler +ADC1_IRQHandler +EXTI9_5_IRQHandler +TIM1_BRK_TIM15_IRQHandler +TIM1_UP_TIM16_IRQHandler +TIM1_TRG_COM_TIM17_IRQHandler +TIM1_CC_IRQHandler +TIM2_IRQHandler +TIM3_IRQHandler +TIM4_IRQHandler +I2C1_EV_IRQHandler +I2C1_ER_IRQHandler +I2C2_EV_IRQHandler +I2C2_ER_IRQHandler +SPI1_IRQHandler +SPI2_IRQHandler +USART1_IRQHandler +USART2_IRQHandler +USART3_IRQHandler +EXTI15_10_IRQHandler +RTCAlarm_IRQHandler +CEC_IRQHandler +TIM12_IRQHandler +TIM13_IRQHandler +TIM14_IRQHandler +TIM5_IRQHandler +SPI3_IRQHandler +UART4_IRQHandler +UART5_IRQHandler +TIM6_DAC_IRQHandler +TIM7_IRQHandler +DMA2_Channel1_IRQHandler +DMA2_Channel2_IRQHandler +DMA2_Channel3_IRQHandler +DMA2_Channel4_5_IRQHandler +DMA2_Channel5_IRQHandler + B . + + ENDP + + ALIGN + +;******************************************************************************* +; User Stack and Heap initialization +;******************************************************************************* + IF :DEF:__MICROLIB + + EXPORT __initial_sp + EXPORT __heap_base + EXPORT __heap_limit + + ELSE + + IMPORT __use_two_region_memory + EXPORT __user_initial_stackheap + +__user_initial_stackheap + + LDR R0, = Heap_Mem + LDR R1, =(Stack_Mem + Stack_Size) + LDR R2, = (Heap_Mem + Heap_Size) + LDR R3, = Stack_Mem + BX LR + + ALIGN + + ENDIF + + END + +;************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE***** diff --git a/Libraries/CMSIS/Device/ST/STM32F10x/Source/Templates/arm/startup_stm32f10x_ld.s b/Libraries/CMSIS/Device/ST/STM32F10x/Source/Templates/arm/startup_stm32f10x_ld.s new file mode 100644 index 0000000..4d9b5ce --- /dev/null +++ b/Libraries/CMSIS/Device/ST/STM32F10x/Source/Templates/arm/startup_stm32f10x_ld.s @@ -0,0 +1,304 @@ +;******************** (C) COPYRIGHT 2012 STMicroelectronics ******************** +;* File Name : startup_stm32f10x_ld.s +;* Author : MCD Application Team +;* Version : V3.6.1 +;* Date : 09-March-2012 +;* Description : STM32F10x Low Density Devices vector table for MDK-ARM +;* toolchain. +;* This module performs: +;* - Set the initial SP +;* - Set the initial PC == Reset_Handler +;* - Set the vector table entries with the exceptions ISR address +;* - Configure the clock system +;* - Branches to __main in the C library (which eventually +;* calls main()). +;* After Reset the CortexM3 processor is in Thread mode, +;* priority is Privileged, and the Stack is set to Main. +;* <<< Use Configuration Wizard in Context Menu >>> +;******************************************************************************* +; +; Licensed under MCD-ST Liberty SW License Agreement V2, (the "License"); +; You may not use this file except in compliance with the License. +; You may obtain a copy of the License at: +; +; http://www.st.com/software_license_agreement_liberty_v2 +; +; Unless required by applicable law or agreed to in writing, software +; distributed under the License is distributed on an "AS IS" BASIS, +; WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +; See the License for the specific language governing permissions and +; limitations under the License. +; +;******************************************************************************* + +; Amount of memory (in bytes) allocated for Stack +; Tailor this value to your application needs +; Stack Configuration +; Stack Size (in Bytes) <0x0-0xFFFFFFFF:8> +; + +Stack_Size EQU 0x00000400 + + AREA STACK, NOINIT, READWRITE, ALIGN=3 +Stack_Mem SPACE Stack_Size +__initial_sp + + +; Heap Configuration +; Heap Size (in Bytes) <0x0-0xFFFFFFFF:8> +; + +Heap_Size EQU 0x00000200 + + AREA HEAP, NOINIT, READWRITE, ALIGN=3 +__heap_base +Heap_Mem SPACE Heap_Size +__heap_limit + + PRESERVE8 + THUMB + + +; Vector Table Mapped to Address 0 at Reset + AREA RESET, DATA, READONLY + EXPORT __Vectors + EXPORT __Vectors_End + EXPORT __Vectors_Size + +__Vectors DCD __initial_sp ; Top of Stack + DCD Reset_Handler ; Reset Handler + DCD NMI_Handler ; NMI Handler + DCD HardFault_Handler ; Hard Fault Handler + DCD MemManage_Handler ; MPU Fault Handler + DCD BusFault_Handler ; Bus Fault Handler + DCD UsageFault_Handler ; Usage Fault Handler + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD SVC_Handler ; SVCall Handler + DCD DebugMon_Handler ; Debug Monitor Handler + DCD 0 ; Reserved + DCD PendSV_Handler ; PendSV Handler + DCD SysTick_Handler ; SysTick Handler + + ; External Interrupts + DCD WWDG_IRQHandler ; Window Watchdog + DCD PVD_IRQHandler ; PVD through EXTI Line detect + DCD TAMPER_IRQHandler ; Tamper + DCD RTC_IRQHandler ; RTC + DCD FLASH_IRQHandler ; Flash + DCD RCC_IRQHandler ; RCC + DCD EXTI0_IRQHandler ; EXTI Line 0 + DCD EXTI1_IRQHandler ; EXTI Line 1 + DCD EXTI2_IRQHandler ; EXTI Line 2 + DCD EXTI3_IRQHandler ; EXTI Line 3 + DCD EXTI4_IRQHandler ; EXTI Line 4 + DCD DMA1_Channel1_IRQHandler ; DMA1 Channel 1 + DCD DMA1_Channel2_IRQHandler ; DMA1 Channel 2 + DCD DMA1_Channel3_IRQHandler ; DMA1 Channel 3 + DCD DMA1_Channel4_IRQHandler ; DMA1 Channel 4 + DCD DMA1_Channel5_IRQHandler ; DMA1 Channel 5 + DCD DMA1_Channel6_IRQHandler ; DMA1 Channel 6 + DCD DMA1_Channel7_IRQHandler ; DMA1 Channel 7 + DCD ADC1_2_IRQHandler ; ADC1_2 + DCD USB_HP_CAN1_TX_IRQHandler ; USB High Priority or CAN1 TX + DCD USB_LP_CAN1_RX0_IRQHandler ; USB Low Priority or CAN1 RX0 + DCD CAN1_RX1_IRQHandler ; CAN1 RX1 + DCD CAN1_SCE_IRQHandler ; CAN1 SCE + DCD EXTI9_5_IRQHandler ; EXTI Line 9..5 + DCD TIM1_BRK_IRQHandler ; TIM1 Break + DCD TIM1_UP_IRQHandler ; TIM1 Update + DCD TIM1_TRG_COM_IRQHandler ; TIM1 Trigger and Commutation + DCD TIM1_CC_IRQHandler ; TIM1 Capture Compare + DCD TIM2_IRQHandler ; TIM2 + DCD TIM3_IRQHandler ; TIM3 + DCD 0 ; Reserved + DCD I2C1_EV_IRQHandler ; I2C1 Event + DCD I2C1_ER_IRQHandler ; I2C1 Error + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD SPI1_IRQHandler ; SPI1 + DCD 0 ; Reserved + DCD USART1_IRQHandler ; USART1 + DCD USART2_IRQHandler ; USART2 + DCD 0 ; Reserved + DCD EXTI15_10_IRQHandler ; EXTI Line 15..10 + DCD RTCAlarm_IRQHandler ; RTC Alarm through EXTI Line + DCD USBWakeUp_IRQHandler ; USB Wakeup from suspend +__Vectors_End + +__Vectors_Size EQU __Vectors_End - __Vectors + + AREA |.text|, CODE, READONLY + +; Reset handler routine +Reset_Handler PROC + EXPORT Reset_Handler [WEAK] + IMPORT __main + IMPORT SystemInit + LDR R0, =SystemInit + BLX R0 + LDR R0, =__main + BX R0 + ENDP + +; Dummy Exception Handlers (infinite loops which can be modified) + +NMI_Handler PROC + EXPORT NMI_Handler [WEAK] + B . + ENDP +HardFault_Handler\ + PROC + EXPORT HardFault_Handler [WEAK] + B . + ENDP +MemManage_Handler\ + PROC + EXPORT MemManage_Handler [WEAK] + B . + ENDP +BusFault_Handler\ + PROC + EXPORT BusFault_Handler [WEAK] + B . + ENDP +UsageFault_Handler\ + PROC + EXPORT UsageFault_Handler [WEAK] + B . + ENDP +SVC_Handler PROC + EXPORT SVC_Handler [WEAK] + B . + ENDP +DebugMon_Handler\ + PROC + EXPORT DebugMon_Handler [WEAK] + B . + ENDP +PendSV_Handler PROC + EXPORT PendSV_Handler [WEAK] + B . + ENDP +SysTick_Handler PROC + EXPORT SysTick_Handler [WEAK] + B . + ENDP + +Default_Handler PROC + + EXPORT WWDG_IRQHandler [WEAK] + EXPORT PVD_IRQHandler [WEAK] + EXPORT TAMPER_IRQHandler [WEAK] + EXPORT RTC_IRQHandler [WEAK] + EXPORT FLASH_IRQHandler [WEAK] + EXPORT RCC_IRQHandler [WEAK] + EXPORT EXTI0_IRQHandler [WEAK] + EXPORT EXTI1_IRQHandler [WEAK] + EXPORT EXTI2_IRQHandler [WEAK] + EXPORT EXTI3_IRQHandler [WEAK] + EXPORT EXTI4_IRQHandler [WEAK] + EXPORT DMA1_Channel1_IRQHandler [WEAK] + EXPORT DMA1_Channel2_IRQHandler [WEAK] + EXPORT DMA1_Channel3_IRQHandler [WEAK] + EXPORT DMA1_Channel4_IRQHandler [WEAK] + EXPORT DMA1_Channel5_IRQHandler [WEAK] + EXPORT DMA1_Channel6_IRQHandler [WEAK] + EXPORT DMA1_Channel7_IRQHandler [WEAK] + EXPORT ADC1_2_IRQHandler [WEAK] + EXPORT USB_HP_CAN1_TX_IRQHandler [WEAK] + EXPORT USB_LP_CAN1_RX0_IRQHandler [WEAK] + EXPORT CAN1_RX1_IRQHandler [WEAK] + EXPORT CAN1_SCE_IRQHandler [WEAK] + EXPORT EXTI9_5_IRQHandler [WEAK] + EXPORT TIM1_BRK_IRQHandler [WEAK] + EXPORT TIM1_UP_IRQHandler [WEAK] + EXPORT TIM1_TRG_COM_IRQHandler [WEAK] + EXPORT TIM1_CC_IRQHandler [WEAK] + EXPORT TIM2_IRQHandler [WEAK] + EXPORT TIM3_IRQHandler [WEAK] + EXPORT I2C1_EV_IRQHandler [WEAK] + EXPORT I2C1_ER_IRQHandler [WEAK] + EXPORT SPI1_IRQHandler [WEAK] + EXPORT USART1_IRQHandler [WEAK] + EXPORT USART2_IRQHandler [WEAK] + EXPORT EXTI15_10_IRQHandler [WEAK] + EXPORT RTCAlarm_IRQHandler [WEAK] + EXPORT USBWakeUp_IRQHandler [WEAK] + +WWDG_IRQHandler +PVD_IRQHandler +TAMPER_IRQHandler +RTC_IRQHandler +FLASH_IRQHandler +RCC_IRQHandler +EXTI0_IRQHandler +EXTI1_IRQHandler +EXTI2_IRQHandler +EXTI3_IRQHandler +EXTI4_IRQHandler +DMA1_Channel1_IRQHandler +DMA1_Channel2_IRQHandler +DMA1_Channel3_IRQHandler +DMA1_Channel4_IRQHandler +DMA1_Channel5_IRQHandler +DMA1_Channel6_IRQHandler +DMA1_Channel7_IRQHandler +ADC1_2_IRQHandler +USB_HP_CAN1_TX_IRQHandler +USB_LP_CAN1_RX0_IRQHandler +CAN1_RX1_IRQHandler +CAN1_SCE_IRQHandler +EXTI9_5_IRQHandler +TIM1_BRK_IRQHandler +TIM1_UP_IRQHandler +TIM1_TRG_COM_IRQHandler +TIM1_CC_IRQHandler +TIM2_IRQHandler +TIM3_IRQHandler +I2C1_EV_IRQHandler +I2C1_ER_IRQHandler +SPI1_IRQHandler +USART1_IRQHandler +USART2_IRQHandler +EXTI15_10_IRQHandler +RTCAlarm_IRQHandler +USBWakeUp_IRQHandler + + B . + + ENDP + + ALIGN + +;******************************************************************************* +; User Stack and Heap initialization +;******************************************************************************* + IF :DEF:__MICROLIB + + EXPORT __initial_sp + EXPORT __heap_base + EXPORT __heap_limit + + ELSE + + IMPORT __use_two_region_memory + EXPORT __user_initial_stackheap + +__user_initial_stackheap + + LDR R0, = Heap_Mem + LDR R1, =(Stack_Mem + Stack_Size) + LDR R2, = (Heap_Mem + Heap_Size) + LDR R3, = Stack_Mem + BX LR + + ALIGN + + ENDIF + + END + +;************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE***** diff --git a/Libraries/CMSIS/Device/ST/STM32F10x/Source/Templates/arm/startup_stm32f10x_ld_vl.s b/Libraries/CMSIS/Device/ST/STM32F10x/Source/Templates/arm/startup_stm32f10x_ld_vl.s new file mode 100644 index 0000000..0eb5010 --- /dev/null +++ b/Libraries/CMSIS/Device/ST/STM32F10x/Source/Templates/arm/startup_stm32f10x_ld_vl.s @@ -0,0 +1,311 @@ +;******************** (C) COPYRIGHT 2012 STMicroelectronics ******************** +;* File Name : startup_stm32f10x_ld_vl.s +;* Author : MCD Application Team +;* Version : V3.6.1 +;* Date : 09-March-2012 +;* Description : STM32F10x Low Density Value Line Devices vector table +;* for MDK-ARM toolchain. +;* This module performs: +;* - Set the initial SP +;* - Set the initial PC == Reset_Handler +;* - Set the vector table entries with the exceptions ISR address +;* - Configure the clock system +;* - Branches to __main in the C library (which eventually +;* calls main()). +;* After Reset the CortexM3 processor is in Thread mode, +;* priority is Privileged, and the Stack is set to Main. +;* <<< Use Configuration Wizard in Context Menu >>> +;******************************************************************************* +; +; Licensed under MCD-ST Liberty SW License Agreement V2, (the "License"); +; You may not use this file except in compliance with the License. +; You may obtain a copy of the License at: +; +; http://www.st.com/software_license_agreement_liberty_v2 +; +; Unless required by applicable law or agreed to in writing, software +; distributed under the License is distributed on an "AS IS" BASIS, +; WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +; See the License for the specific language governing permissions and +; limitations under the License. +; +;******************************************************************************* + +; Amount of memory (in bytes) allocated for Stack +; Tailor this value to your application needs +; Stack Configuration +; Stack Size (in Bytes) <0x0-0xFFFFFFFF:8> +; + +Stack_Size EQU 0x00000400 + + AREA STACK, NOINIT, READWRITE, ALIGN=3 +Stack_Mem SPACE Stack_Size +__initial_sp + + +; Heap Configuration +; Heap Size (in Bytes) <0x0-0xFFFFFFFF:8> +; + +Heap_Size EQU 0x00000200 + + AREA HEAP, NOINIT, READWRITE, ALIGN=3 +__heap_base +Heap_Mem SPACE Heap_Size +__heap_limit + + PRESERVE8 + THUMB + + +; Vector Table Mapped to Address 0 at Reset + AREA RESET, DATA, READONLY + EXPORT __Vectors + EXPORT __Vectors_End + EXPORT __Vectors_Size + +__Vectors DCD __initial_sp ; Top of Stack + DCD Reset_Handler ; Reset Handler + DCD NMI_Handler ; NMI Handler + DCD HardFault_Handler ; Hard Fault Handler + DCD MemManage_Handler ; MPU Fault Handler + DCD BusFault_Handler ; Bus Fault Handler + DCD UsageFault_Handler ; Usage Fault Handler + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD SVC_Handler ; SVCall Handler + DCD DebugMon_Handler ; Debug Monitor Handler + DCD 0 ; Reserved + DCD PendSV_Handler ; PendSV Handler + DCD SysTick_Handler ; SysTick Handler + + ; External Interrupts + DCD WWDG_IRQHandler ; Window Watchdog + DCD PVD_IRQHandler ; PVD through EXTI Line detect + DCD TAMPER_IRQHandler ; Tamper + DCD RTC_IRQHandler ; RTC + DCD FLASH_IRQHandler ; Flash + DCD RCC_IRQHandler ; RCC + DCD EXTI0_IRQHandler ; EXTI Line 0 + DCD EXTI1_IRQHandler ; EXTI Line 1 + DCD EXTI2_IRQHandler ; EXTI Line 2 + DCD EXTI3_IRQHandler ; EXTI Line 3 + DCD EXTI4_IRQHandler ; EXTI Line 4 + DCD DMA1_Channel1_IRQHandler ; DMA1 Channel 1 + DCD DMA1_Channel2_IRQHandler ; DMA1 Channel 2 + DCD DMA1_Channel3_IRQHandler ; DMA1 Channel 3 + DCD DMA1_Channel4_IRQHandler ; DMA1 Channel 4 + DCD DMA1_Channel5_IRQHandler ; DMA1 Channel 5 + DCD DMA1_Channel6_IRQHandler ; DMA1 Channel 6 + DCD DMA1_Channel7_IRQHandler ; DMA1 Channel 7 + DCD ADC1_IRQHandler ; ADC1 + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD EXTI9_5_IRQHandler ; EXTI Line 9..5 + DCD TIM1_BRK_TIM15_IRQHandler ; TIM1 Break and TIM15 + DCD TIM1_UP_TIM16_IRQHandler ; TIM1 Update and TIM16 + DCD TIM1_TRG_COM_TIM17_IRQHandler ; TIM1 Trigger and Commutation and TIM17 + DCD TIM1_CC_IRQHandler ; TIM1 Capture Compare + DCD TIM2_IRQHandler ; TIM2 + DCD TIM3_IRQHandler ; TIM3 + DCD 0 ; Reserved + DCD I2C1_EV_IRQHandler ; I2C1 Event + DCD I2C1_ER_IRQHandler ; I2C1 Error + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD SPI1_IRQHandler ; SPI1 + DCD 0 ; Reserved + DCD USART1_IRQHandler ; USART1 + DCD USART2_IRQHandler ; USART2 + DCD 0 ; Reserved + DCD EXTI15_10_IRQHandler ; EXTI Line 15..10 + DCD RTCAlarm_IRQHandler ; RTC Alarm through EXTI Line + DCD CEC_IRQHandler ; HDMI-CEC + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD TIM6_DAC_IRQHandler ; TIM6 and DAC underrun + DCD TIM7_IRQHandler ; TIM7 +__Vectors_End + +__Vectors_Size EQU __Vectors_End - __Vectors + + AREA |.text|, CODE, READONLY + +; Reset handler +Reset_Handler PROC + EXPORT Reset_Handler [WEAK] + IMPORT __main + IMPORT SystemInit + LDR R0, =SystemInit + BLX R0 + LDR R0, =__main + BX R0 + ENDP + +; Dummy Exception Handlers (infinite loops which can be modified) + +NMI_Handler PROC + EXPORT NMI_Handler [WEAK] + B . + ENDP +HardFault_Handler\ + PROC + EXPORT HardFault_Handler [WEAK] + B . + ENDP +MemManage_Handler\ + PROC + EXPORT MemManage_Handler [WEAK] + B . + ENDP +BusFault_Handler\ + PROC + EXPORT BusFault_Handler [WEAK] + B . + ENDP +UsageFault_Handler\ + PROC + EXPORT UsageFault_Handler [WEAK] + B . + ENDP +SVC_Handler PROC + EXPORT SVC_Handler [WEAK] + B . + ENDP +DebugMon_Handler\ + PROC + EXPORT DebugMon_Handler [WEAK] + B . + ENDP +PendSV_Handler PROC + EXPORT PendSV_Handler [WEAK] + B . + ENDP +SysTick_Handler PROC + EXPORT SysTick_Handler [WEAK] + B . + ENDP + +Default_Handler PROC + + EXPORT WWDG_IRQHandler [WEAK] + EXPORT PVD_IRQHandler [WEAK] + EXPORT TAMPER_IRQHandler [WEAK] + EXPORT RTC_IRQHandler [WEAK] + EXPORT FLASH_IRQHandler [WEAK] + EXPORT RCC_IRQHandler [WEAK] + EXPORT EXTI0_IRQHandler [WEAK] + EXPORT EXTI1_IRQHandler [WEAK] + EXPORT EXTI2_IRQHandler [WEAK] + EXPORT EXTI3_IRQHandler [WEAK] + EXPORT EXTI4_IRQHandler [WEAK] + EXPORT DMA1_Channel1_IRQHandler [WEAK] + EXPORT DMA1_Channel2_IRQHandler [WEAK] + EXPORT DMA1_Channel3_IRQHandler [WEAK] + EXPORT DMA1_Channel4_IRQHandler [WEAK] + EXPORT DMA1_Channel5_IRQHandler [WEAK] + EXPORT DMA1_Channel6_IRQHandler [WEAK] + EXPORT DMA1_Channel7_IRQHandler [WEAK] + EXPORT ADC1_IRQHandler [WEAK] + EXPORT EXTI9_5_IRQHandler [WEAK] + EXPORT TIM1_BRK_TIM15_IRQHandler [WEAK] + EXPORT TIM1_UP_TIM16_IRQHandler [WEAK] + EXPORT TIM1_TRG_COM_TIM17_IRQHandler [WEAK] + EXPORT TIM1_CC_IRQHandler [WEAK] + EXPORT TIM2_IRQHandler [WEAK] + EXPORT TIM3_IRQHandler [WEAK] + EXPORT I2C1_EV_IRQHandler [WEAK] + EXPORT I2C1_ER_IRQHandler [WEAK] + EXPORT SPI1_IRQHandler [WEAK] + EXPORT USART1_IRQHandler [WEAK] + EXPORT USART2_IRQHandler [WEAK] + EXPORT EXTI15_10_IRQHandler [WEAK] + EXPORT RTCAlarm_IRQHandler [WEAK] + EXPORT CEC_IRQHandler [WEAK] + EXPORT TIM6_DAC_IRQHandler [WEAK] + EXPORT TIM7_IRQHandler [WEAK] +WWDG_IRQHandler +PVD_IRQHandler +TAMPER_IRQHandler +RTC_IRQHandler +FLASH_IRQHandler +RCC_IRQHandler +EXTI0_IRQHandler +EXTI1_IRQHandler +EXTI2_IRQHandler +EXTI3_IRQHandler +EXTI4_IRQHandler +DMA1_Channel1_IRQHandler +DMA1_Channel2_IRQHandler +DMA1_Channel3_IRQHandler +DMA1_Channel4_IRQHandler +DMA1_Channel5_IRQHandler +DMA1_Channel6_IRQHandler +DMA1_Channel7_IRQHandler +ADC1_IRQHandler +EXTI9_5_IRQHandler +TIM1_BRK_TIM15_IRQHandler +TIM1_UP_TIM16_IRQHandler +TIM1_TRG_COM_TIM17_IRQHandler +TIM1_CC_IRQHandler +TIM2_IRQHandler +TIM3_IRQHandler +I2C1_EV_IRQHandler +I2C1_ER_IRQHandler +SPI1_IRQHandler +USART1_IRQHandler +USART2_IRQHandler +EXTI15_10_IRQHandler +RTCAlarm_IRQHandler +CEC_IRQHandler +TIM6_DAC_IRQHandler +TIM7_IRQHandler + B . + + ENDP + + ALIGN + +;******************************************************************************* +; User Stack and Heap initialization +;******************************************************************************* + IF :DEF:__MICROLIB + + EXPORT __initial_sp + EXPORT __heap_base + EXPORT __heap_limit + + ELSE + + IMPORT __use_two_region_memory + EXPORT __user_initial_stackheap + +__user_initial_stackheap + + LDR R0, = Heap_Mem + LDR R1, =(Stack_Mem + Stack_Size) + LDR R2, = (Heap_Mem + Heap_Size) + LDR R3, = Stack_Mem + BX LR + + ALIGN + + ENDIF + + END + +;************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE***** diff --git a/Libraries/CMSIS/Device/ST/STM32F10x/Source/Templates/arm/startup_stm32f10x_md.s b/Libraries/CMSIS/Device/ST/STM32F10x/Source/Templates/arm/startup_stm32f10x_md.s new file mode 100644 index 0000000..84ae671 --- /dev/null +++ b/Libraries/CMSIS/Device/ST/STM32F10x/Source/Templates/arm/startup_stm32f10x_md.s @@ -0,0 +1,314 @@ +;******************** (C) COPYRIGHT 2012 STMicroelectronics ******************** +;* File Name : startup_stm32f10x_md.s +;* Author : MCD Application Team +;* Version : V3.6.1 +;* Date : 09-March-2012 +;* Description : STM32F10x Medium Density Devices vector table for MDK-ARM +;* toolchain. +;* This module performs: +;* - Set the initial SP +;* - Set the initial PC == Reset_Handler +;* - Set the vector table entries with the exceptions ISR address +;* - Configure the clock system +;* - Branches to __main in the C library (which eventually +;* calls main()). +;* After Reset the CortexM3 processor is in Thread mode, +;* priority is Privileged, and the Stack is set to Main. +;* <<< Use Configuration Wizard in Context Menu >>> +;******************************************************************************* +; +; Licensed under MCD-ST Liberty SW License Agreement V2, (the "License"); +; You may not use this file except in compliance with the License. +; You may obtain a copy of the License at: +; +; http://www.st.com/software_license_agreement_liberty_v2 +; +; Unless required by applicable law or agreed to in writing, software +; distributed under the License is distributed on an "AS IS" BASIS, +; WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +; See the License for the specific language governing permissions and +; limitations under the License. +; +;******************************************************************************* + +; Amount of memory (in bytes) allocated for Stack +; Tailor this value to your application needs +; Stack Configuration +; Stack Size (in Bytes) <0x0-0xFFFFFFFF:8> +; + +Stack_Size EQU 0x00000400 + + AREA STACK, NOINIT, READWRITE, ALIGN=3 +Stack_Mem SPACE Stack_Size +__initial_sp + + +; Heap Configuration +; Heap Size (in Bytes) <0x0-0xFFFFFFFF:8> +; + +Heap_Size EQU 0x00000200 + + AREA HEAP, NOINIT, READWRITE, ALIGN=3 +__heap_base +Heap_Mem SPACE Heap_Size +__heap_limit + + PRESERVE8 + THUMB + + +; Vector Table Mapped to Address 0 at Reset + AREA RESET, DATA, READONLY + EXPORT __Vectors + EXPORT __Vectors_End + EXPORT __Vectors_Size + +__Vectors DCD __initial_sp ; Top of Stack + DCD Reset_Handler ; Reset Handler + DCD NMI_Handler ; NMI Handler + DCD HardFault_Handler ; Hard Fault Handler + DCD MemManage_Handler ; MPU Fault Handler + DCD BusFault_Handler ; Bus Fault Handler + DCD UsageFault_Handler ; Usage Fault Handler + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD SVC_Handler ; SVCall Handler + DCD DebugMon_Handler ; Debug Monitor Handler + DCD 0 ; Reserved + DCD PendSV_Handler ; PendSV Handler + DCD SysTick_Handler ; SysTick Handler + + ; External Interrupts + DCD WWDG_IRQHandler ; Window Watchdog + DCD PVD_IRQHandler ; PVD through EXTI Line detect + DCD TAMPER_IRQHandler ; Tamper + DCD RTC_IRQHandler ; RTC + DCD FLASH_IRQHandler ; Flash + DCD RCC_IRQHandler ; RCC + DCD EXTI0_IRQHandler ; EXTI Line 0 + DCD EXTI1_IRQHandler ; EXTI Line 1 + DCD EXTI2_IRQHandler ; EXTI Line 2 + DCD EXTI3_IRQHandler ; EXTI Line 3 + DCD EXTI4_IRQHandler ; EXTI Line 4 + DCD DMA1_Channel1_IRQHandler ; DMA1 Channel 1 + DCD DMA1_Channel2_IRQHandler ; DMA1 Channel 2 + DCD DMA1_Channel3_IRQHandler ; DMA1 Channel 3 + DCD DMA1_Channel4_IRQHandler ; DMA1 Channel 4 + DCD DMA1_Channel5_IRQHandler ; DMA1 Channel 5 + DCD DMA1_Channel6_IRQHandler ; DMA1 Channel 6 + DCD DMA1_Channel7_IRQHandler ; DMA1 Channel 7 + DCD ADC1_2_IRQHandler ; ADC1_2 + DCD USB_HP_CAN1_TX_IRQHandler ; USB High Priority or CAN1 TX + DCD USB_LP_CAN1_RX0_IRQHandler ; USB Low Priority or CAN1 RX0 + DCD CAN1_RX1_IRQHandler ; CAN1 RX1 + DCD CAN1_SCE_IRQHandler ; CAN1 SCE + DCD EXTI9_5_IRQHandler ; EXTI Line 9..5 + DCD TIM1_BRK_IRQHandler ; TIM1 Break + DCD TIM1_UP_IRQHandler ; TIM1 Update + DCD TIM1_TRG_COM_IRQHandler ; TIM1 Trigger and Commutation + DCD TIM1_CC_IRQHandler ; TIM1 Capture Compare + DCD TIM2_IRQHandler ; TIM2 + DCD TIM3_IRQHandler ; TIM3 + DCD TIM4_IRQHandler ; TIM4 + DCD I2C1_EV_IRQHandler ; I2C1 Event + DCD I2C1_ER_IRQHandler ; I2C1 Error + DCD I2C2_EV_IRQHandler ; I2C2 Event + DCD I2C2_ER_IRQHandler ; I2C2 Error + DCD SPI1_IRQHandler ; SPI1 + DCD SPI2_IRQHandler ; SPI2 + DCD USART1_IRQHandler ; USART1 + DCD USART2_IRQHandler ; USART2 + DCD USART3_IRQHandler ; USART3 + DCD EXTI15_10_IRQHandler ; EXTI Line 15..10 + DCD RTCAlarm_IRQHandler ; RTC Alarm through EXTI Line + DCD USBWakeUp_IRQHandler ; USB Wakeup from suspend +__Vectors_End + +__Vectors_Size EQU __Vectors_End - __Vectors + + AREA |.text|, CODE, READONLY + +; Reset handler +Reset_Handler PROC + EXPORT Reset_Handler [WEAK] + IMPORT __main + IMPORT SystemInit + LDR R0, =SystemInit + BLX R0 + LDR R0, =__main + BX R0 + ENDP + +; Dummy Exception Handlers (infinite loops which can be modified) + +NMI_Handler PROC + EXPORT NMI_Handler [WEAK] + B . + ENDP +HardFault_Handler\ + PROC + EXPORT HardFault_Handler [WEAK] + B . + ENDP +MemManage_Handler\ + PROC + EXPORT MemManage_Handler [WEAK] + B . + ENDP +BusFault_Handler\ + PROC + EXPORT BusFault_Handler [WEAK] + B . + ENDP +UsageFault_Handler\ + PROC + EXPORT UsageFault_Handler [WEAK] + B . + ENDP +SVC_Handler PROC + EXPORT SVC_Handler [WEAK] + B . + ENDP +DebugMon_Handler\ + PROC + EXPORT DebugMon_Handler [WEAK] + B . + ENDP +PendSV_Handler PROC + EXPORT PendSV_Handler [WEAK] + B . + ENDP +SysTick_Handler PROC + EXPORT SysTick_Handler [WEAK] + B . + ENDP + +Default_Handler PROC + + EXPORT WWDG_IRQHandler [WEAK] + EXPORT PVD_IRQHandler [WEAK] + EXPORT TAMPER_IRQHandler [WEAK] + EXPORT RTC_IRQHandler [WEAK] + EXPORT FLASH_IRQHandler [WEAK] + EXPORT RCC_IRQHandler [WEAK] + EXPORT EXTI0_IRQHandler [WEAK] + EXPORT EXTI1_IRQHandler [WEAK] + EXPORT EXTI2_IRQHandler [WEAK] + EXPORT EXTI3_IRQHandler [WEAK] + EXPORT EXTI4_IRQHandler [WEAK] + EXPORT DMA1_Channel1_IRQHandler [WEAK] + EXPORT DMA1_Channel2_IRQHandler [WEAK] + EXPORT DMA1_Channel3_IRQHandler [WEAK] + EXPORT DMA1_Channel4_IRQHandler [WEAK] + EXPORT DMA1_Channel5_IRQHandler [WEAK] + EXPORT DMA1_Channel6_IRQHandler [WEAK] + EXPORT DMA1_Channel7_IRQHandler [WEAK] + EXPORT ADC1_2_IRQHandler [WEAK] + EXPORT USB_HP_CAN1_TX_IRQHandler [WEAK] + EXPORT USB_LP_CAN1_RX0_IRQHandler [WEAK] + EXPORT CAN1_RX1_IRQHandler [WEAK] + EXPORT CAN1_SCE_IRQHandler [WEAK] + EXPORT EXTI9_5_IRQHandler [WEAK] + EXPORT TIM1_BRK_IRQHandler [WEAK] + EXPORT TIM1_UP_IRQHandler [WEAK] + EXPORT TIM1_TRG_COM_IRQHandler [WEAK] + EXPORT TIM1_CC_IRQHandler [WEAK] + EXPORT TIM2_IRQHandler [WEAK] + EXPORT TIM3_IRQHandler [WEAK] + EXPORT TIM4_IRQHandler [WEAK] + EXPORT I2C1_EV_IRQHandler [WEAK] + EXPORT I2C1_ER_IRQHandler [WEAK] + EXPORT I2C2_EV_IRQHandler [WEAK] + EXPORT I2C2_ER_IRQHandler [WEAK] + EXPORT SPI1_IRQHandler [WEAK] + EXPORT SPI2_IRQHandler [WEAK] + EXPORT USART1_IRQHandler [WEAK] + EXPORT USART2_IRQHandler [WEAK] + EXPORT USART3_IRQHandler [WEAK] + EXPORT EXTI15_10_IRQHandler [WEAK] + EXPORT RTCAlarm_IRQHandler [WEAK] + EXPORT USBWakeUp_IRQHandler [WEAK] + +WWDG_IRQHandler +PVD_IRQHandler +TAMPER_IRQHandler +RTC_IRQHandler +FLASH_IRQHandler +RCC_IRQHandler +EXTI0_IRQHandler +EXTI1_IRQHandler +EXTI2_IRQHandler +EXTI3_IRQHandler +EXTI4_IRQHandler +DMA1_Channel1_IRQHandler +DMA1_Channel2_IRQHandler +DMA1_Channel3_IRQHandler +DMA1_Channel4_IRQHandler +DMA1_Channel5_IRQHandler +DMA1_Channel6_IRQHandler +DMA1_Channel7_IRQHandler +ADC1_2_IRQHandler +USB_HP_CAN1_TX_IRQHandler +USB_LP_CAN1_RX0_IRQHandler +CAN1_RX1_IRQHandler +CAN1_SCE_IRQHandler +EXTI9_5_IRQHandler +TIM1_BRK_IRQHandler +TIM1_UP_IRQHandler +TIM1_TRG_COM_IRQHandler +TIM1_CC_IRQHandler +TIM2_IRQHandler +TIM3_IRQHandler +TIM4_IRQHandler +I2C1_EV_IRQHandler +I2C1_ER_IRQHandler +I2C2_EV_IRQHandler +I2C2_ER_IRQHandler +SPI1_IRQHandler +SPI2_IRQHandler +USART1_IRQHandler +USART2_IRQHandler +USART3_IRQHandler +EXTI15_10_IRQHandler +RTCAlarm_IRQHandler +USBWakeUp_IRQHandler + + B . + + ENDP + + ALIGN + +;******************************************************************************* +; User Stack and Heap initialization +;******************************************************************************* + IF :DEF:__MICROLIB + + EXPORT __initial_sp + EXPORT __heap_base + EXPORT __heap_limit + + ELSE + + IMPORT __use_two_region_memory + EXPORT __user_initial_stackheap + +__user_initial_stackheap + + LDR R0, = Heap_Mem + LDR R1, =(Stack_Mem + Stack_Size) + LDR R2, = (Heap_Mem + Heap_Size) + LDR R3, = Stack_Mem + BX LR + + ALIGN + + ENDIF + + END + +;************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE***** diff --git a/Libraries/CMSIS/Device/ST/STM32F10x/Source/Templates/arm/startup_stm32f10x_md_vl.s b/Libraries/CMSIS/Device/ST/STM32F10x/Source/Templates/arm/startup_stm32f10x_md_vl.s new file mode 100644 index 0000000..0d1f84f --- /dev/null +++ b/Libraries/CMSIS/Device/ST/STM32F10x/Source/Templates/arm/startup_stm32f10x_md_vl.s @@ -0,0 +1,322 @@ +;******************** (C) COPYRIGHT 2012 STMicroelectronics ******************** +;* File Name : startup_stm32f10x_md_vl.s +;* Author : MCD Application Team +;* Version : V3.6.1 +;* Date : 09-March-2012 +;* Description : STM32F10x Medium Density Value Line Devices vector table +;* for MDK-ARM toolchain. +;* This module performs: +;* - Set the initial SP +;* - Set the initial PC == Reset_Handler +;* - Set the vector table entries with the exceptions ISR address +;* - Configure the clock system +;* - Branches to __main in the C library (which eventually +;* calls main()). +;* After Reset the CortexM3 processor is in Thread mode, +;* priority is Privileged, and the Stack is set to Main. +;* <<< Use Configuration Wizard in Context Menu >>> +;******************************************************************************* +; +; Licensed under MCD-ST Liberty SW License Agreement V2, (the "License"); +; You may not use this file except in compliance with the License. +; You may obtain a copy of the License at: +; +; http://www.st.com/software_license_agreement_liberty_v2 +; +; Unless required by applicable law or agreed to in writing, software +; distributed under the License is distributed on an "AS IS" BASIS, +; WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +; See the License for the specific language governing permissions and +; limitations under the License. +; +;******************************************************************************* + +; Amount of memory (in bytes) allocated for Stack +; Tailor this value to your application needs +; Stack Configuration +; Stack Size (in Bytes) <0x0-0xFFFFFFFF:8> +; + +Stack_Size EQU 0x00000400 + + AREA STACK, NOINIT, READWRITE, ALIGN=3 +Stack_Mem SPACE Stack_Size +__initial_sp + + +; Heap Configuration +; Heap Size (in Bytes) <0x0-0xFFFFFFFF:8> +; + +Heap_Size EQU 0x00000200 + + AREA HEAP, NOINIT, READWRITE, ALIGN=3 +__heap_base +Heap_Mem SPACE Heap_Size +__heap_limit + + PRESERVE8 + THUMB + + +; Vector Table Mapped to Address 0 at Reset + AREA RESET, DATA, READONLY + EXPORT __Vectors + EXPORT __Vectors_End + EXPORT __Vectors_Size + +__Vectors DCD __initial_sp ; Top of Stack + DCD Reset_Handler ; Reset Handler + DCD NMI_Handler ; NMI Handler + DCD HardFault_Handler ; Hard Fault Handler + DCD MemManage_Handler ; MPU Fault Handler + DCD BusFault_Handler ; Bus Fault Handler + DCD UsageFault_Handler ; Usage Fault Handler + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD SVC_Handler ; SVCall Handler + DCD DebugMon_Handler ; Debug Monitor Handler + DCD 0 ; Reserved + DCD PendSV_Handler ; PendSV Handler + DCD SysTick_Handler ; SysTick Handler + + ; External Interrupts + DCD WWDG_IRQHandler ; Window Watchdog + DCD PVD_IRQHandler ; PVD through EXTI Line detect + DCD TAMPER_IRQHandler ; Tamper + DCD RTC_IRQHandler ; RTC + DCD FLASH_IRQHandler ; Flash + DCD RCC_IRQHandler ; RCC + DCD EXTI0_IRQHandler ; EXTI Line 0 + DCD EXTI1_IRQHandler ; EXTI Line 1 + DCD EXTI2_IRQHandler ; EXTI Line 2 + DCD EXTI3_IRQHandler ; EXTI Line 3 + DCD EXTI4_IRQHandler ; EXTI Line 4 + DCD DMA1_Channel1_IRQHandler ; DMA1 Channel 1 + DCD DMA1_Channel2_IRQHandler ; DMA1 Channel 2 + DCD DMA1_Channel3_IRQHandler ; DMA1 Channel 3 + DCD DMA1_Channel4_IRQHandler ; DMA1 Channel 4 + DCD DMA1_Channel5_IRQHandler ; DMA1 Channel 5 + DCD DMA1_Channel6_IRQHandler ; DMA1 Channel 6 + DCD DMA1_Channel7_IRQHandler ; DMA1 Channel 7 + DCD ADC1_IRQHandler ; ADC1 + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD EXTI9_5_IRQHandler ; EXTI Line 9..5 + DCD TIM1_BRK_TIM15_IRQHandler ; TIM1 Break and TIM15 + DCD TIM1_UP_TIM16_IRQHandler ; TIM1 Update and TIM16 + DCD TIM1_TRG_COM_TIM17_IRQHandler ; TIM1 Trigger and Commutation and TIM17 + DCD TIM1_CC_IRQHandler ; TIM1 Capture Compare + DCD TIM2_IRQHandler ; TIM2 + DCD TIM3_IRQHandler ; TIM3 + DCD TIM4_IRQHandler ; TIM4 + DCD I2C1_EV_IRQHandler ; I2C1 Event + DCD I2C1_ER_IRQHandler ; I2C1 Error + DCD I2C2_EV_IRQHandler ; I2C2 Event + DCD I2C2_ER_IRQHandler ; I2C2 Error + DCD SPI1_IRQHandler ; SPI1 + DCD SPI2_IRQHandler ; SPI2 + DCD USART1_IRQHandler ; USART1 + DCD USART2_IRQHandler ; USART2 + DCD USART3_IRQHandler ; USART3 + DCD EXTI15_10_IRQHandler ; EXTI Line 15..10 + DCD RTCAlarm_IRQHandler ; RTC Alarm through EXTI Line + DCD CEC_IRQHandler ; HDMI-CEC + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD TIM6_DAC_IRQHandler ; TIM6 and DAC underrun + DCD TIM7_IRQHandler ; TIM7 +__Vectors_End + +__Vectors_Size EQU __Vectors_End - __Vectors + + AREA |.text|, CODE, READONLY + +; Reset handler +Reset_Handler PROC + EXPORT Reset_Handler [WEAK] + IMPORT __main + IMPORT SystemInit + LDR R0, =SystemInit + BLX R0 + LDR R0, =__main + BX R0 + ENDP + +; Dummy Exception Handlers (infinite loops which can be modified) + +NMI_Handler PROC + EXPORT NMI_Handler [WEAK] + B . + ENDP +HardFault_Handler\ + PROC + EXPORT HardFault_Handler [WEAK] + B . + ENDP +MemManage_Handler\ + PROC + EXPORT MemManage_Handler [WEAK] + B . + ENDP +BusFault_Handler\ + PROC + EXPORT BusFault_Handler [WEAK] + B . + ENDP +UsageFault_Handler\ + PROC + EXPORT UsageFault_Handler [WEAK] + B . + ENDP +SVC_Handler PROC + EXPORT SVC_Handler [WEAK] + B . + ENDP +DebugMon_Handler\ + PROC + EXPORT DebugMon_Handler [WEAK] + B . + ENDP +PendSV_Handler PROC + EXPORT PendSV_Handler [WEAK] + B . + ENDP +SysTick_Handler PROC + EXPORT SysTick_Handler [WEAK] + B . + ENDP + +Default_Handler PROC + + EXPORT WWDG_IRQHandler [WEAK] + EXPORT PVD_IRQHandler [WEAK] + EXPORT TAMPER_IRQHandler [WEAK] + EXPORT RTC_IRQHandler [WEAK] + EXPORT FLASH_IRQHandler [WEAK] + EXPORT RCC_IRQHandler [WEAK] + EXPORT EXTI0_IRQHandler [WEAK] + EXPORT EXTI1_IRQHandler [WEAK] + EXPORT EXTI2_IRQHandler [WEAK] + EXPORT EXTI3_IRQHandler [WEAK] + EXPORT EXTI4_IRQHandler [WEAK] + EXPORT DMA1_Channel1_IRQHandler [WEAK] + EXPORT DMA1_Channel2_IRQHandler [WEAK] + EXPORT DMA1_Channel3_IRQHandler [WEAK] + EXPORT DMA1_Channel4_IRQHandler [WEAK] + EXPORT DMA1_Channel5_IRQHandler [WEAK] + EXPORT DMA1_Channel6_IRQHandler [WEAK] + EXPORT DMA1_Channel7_IRQHandler [WEAK] + EXPORT ADC1_IRQHandler [WEAK] + EXPORT EXTI9_5_IRQHandler [WEAK] + EXPORT TIM1_BRK_TIM15_IRQHandler [WEAK] + EXPORT TIM1_UP_TIM16_IRQHandler [WEAK] + EXPORT TIM1_TRG_COM_TIM17_IRQHandler [WEAK] + EXPORT TIM1_CC_IRQHandler [WEAK] + EXPORT TIM2_IRQHandler [WEAK] + EXPORT TIM3_IRQHandler [WEAK] + EXPORT TIM4_IRQHandler [WEAK] + EXPORT I2C1_EV_IRQHandler [WEAK] + EXPORT I2C1_ER_IRQHandler [WEAK] + EXPORT I2C2_EV_IRQHandler [WEAK] + EXPORT I2C2_ER_IRQHandler [WEAK] + EXPORT SPI1_IRQHandler [WEAK] + EXPORT SPI2_IRQHandler [WEAK] + EXPORT USART1_IRQHandler [WEAK] + EXPORT USART2_IRQHandler [WEAK] + EXPORT USART3_IRQHandler [WEAK] + EXPORT EXTI15_10_IRQHandler [WEAK] + EXPORT RTCAlarm_IRQHandler [WEAK] + EXPORT CEC_IRQHandler [WEAK] + EXPORT TIM6_DAC_IRQHandler [WEAK] + EXPORT TIM7_IRQHandler [WEAK] + +WWDG_IRQHandler +PVD_IRQHandler +TAMPER_IRQHandler +RTC_IRQHandler +FLASH_IRQHandler +RCC_IRQHandler +EXTI0_IRQHandler +EXTI1_IRQHandler +EXTI2_IRQHandler +EXTI3_IRQHandler +EXTI4_IRQHandler +DMA1_Channel1_IRQHandler +DMA1_Channel2_IRQHandler +DMA1_Channel3_IRQHandler +DMA1_Channel4_IRQHandler +DMA1_Channel5_IRQHandler +DMA1_Channel6_IRQHandler +DMA1_Channel7_IRQHandler +ADC1_IRQHandler +EXTI9_5_IRQHandler +TIM1_BRK_TIM15_IRQHandler +TIM1_UP_TIM16_IRQHandler +TIM1_TRG_COM_TIM17_IRQHandler +TIM1_CC_IRQHandler +TIM2_IRQHandler +TIM3_IRQHandler +TIM4_IRQHandler +I2C1_EV_IRQHandler +I2C1_ER_IRQHandler +I2C2_EV_IRQHandler +I2C2_ER_IRQHandler +SPI1_IRQHandler +SPI2_IRQHandler +USART1_IRQHandler +USART2_IRQHandler +USART3_IRQHandler +EXTI15_10_IRQHandler +RTCAlarm_IRQHandler +CEC_IRQHandler +TIM6_DAC_IRQHandler +TIM7_IRQHandler + B . + + ENDP + + ALIGN + +;******************************************************************************* +; User Stack and Heap initialization +;******************************************************************************* + IF :DEF:__MICROLIB + + EXPORT __initial_sp + EXPORT __heap_base + EXPORT __heap_limit + + ELSE + + IMPORT __use_two_region_memory + EXPORT __user_initial_stackheap + +__user_initial_stackheap + + LDR R0, = Heap_Mem + LDR R1, =(Stack_Mem + Stack_Size) + LDR R2, = (Heap_Mem + Heap_Size) + LDR R3, = Stack_Mem + BX LR + + ALIGN + + ENDIF + + END + +;************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE***** diff --git a/Libraries/CMSIS/Device/ST/STM32F10x/Source/Templates/arm/startup_stm32f10x_xl.s b/Libraries/CMSIS/Device/ST/STM32F10x/Source/Templates/arm/startup_stm32f10x_xl.s new file mode 100644 index 0000000..85dab64 --- /dev/null +++ b/Libraries/CMSIS/Device/ST/STM32F10x/Source/Templates/arm/startup_stm32f10x_xl.s @@ -0,0 +1,365 @@ +;******************** (C) COPYRIGHT 2012 STMicroelectronics ******************** +;* File Name : startup_stm32f10x_xl.s +;* Author : MCD Application Team +;* Version : V3.6.1 +;* Date : 09-March-2012 +;* Description : STM32F10x XL-Density Devices vector table for MDK-ARM +;* toolchain. +;* This module performs: +;* - Set the initial SP +;* - Set the initial PC == Reset_Handler +;* - Set the vector table entries with the exceptions ISR address +;* - Configure the clock system and also configure the external +;* SRAM mounted on STM3210E-EVAL board to be used as data +;* memory (optional, to be enabled by user) +;* - Branches to __main in the C library (which eventually +;* calls main()). +;* After Reset the CortexM3 processor is in Thread mode, +;* priority is Privileged, and the Stack is set to Main. +;* <<< Use Configuration Wizard in Context Menu >>> +;******************************************************************************* +; +; Licensed under MCD-ST Liberty SW License Agreement V2, (the "License"); +; You may not use this file except in compliance with the License. +; You may obtain a copy of the License at: +; +; http://www.st.com/software_license_agreement_liberty_v2 +; +; Unless required by applicable law or agreed to in writing, software +; distributed under the License is distributed on an "AS IS" BASIS, +; WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +; See the License for the specific language governing permissions and +; limitations under the License. +; +;******************************************************************************* + +; Amount of memory (in bytes) allocated for Stack +; Tailor this value to your application needs +; Stack Configuration +; Stack Size (in Bytes) <0x0-0xFFFFFFFF:8> +; + +Stack_Size EQU 0x00000400 + + AREA STACK, NOINIT, READWRITE, ALIGN=3 +Stack_Mem SPACE Stack_Size +__initial_sp + +; Heap Configuration +; Heap Size (in Bytes) <0x0-0xFFFFFFFF:8> +; + +Heap_Size EQU 0x00000200 + + AREA HEAP, NOINIT, READWRITE, ALIGN=3 +__heap_base +Heap_Mem SPACE Heap_Size +__heap_limit + + PRESERVE8 + THUMB + + +; Vector Table Mapped to Address 0 at Reset + AREA RESET, DATA, READONLY + EXPORT __Vectors + EXPORT __Vectors_End + EXPORT __Vectors_Size + +__Vectors DCD __initial_sp ; Top of Stack + DCD Reset_Handler ; Reset Handler + DCD NMI_Handler ; NMI Handler + DCD HardFault_Handler ; Hard Fault Handler + DCD MemManage_Handler ; MPU Fault Handler + DCD BusFault_Handler ; Bus Fault Handler + DCD UsageFault_Handler ; Usage Fault Handler + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD SVC_Handler ; SVCall Handler + DCD DebugMon_Handler ; Debug Monitor Handler + DCD 0 ; Reserved + DCD PendSV_Handler ; PendSV Handler + DCD SysTick_Handler ; SysTick Handler + + ; External Interrupts + DCD WWDG_IRQHandler ; Window Watchdog + DCD PVD_IRQHandler ; PVD through EXTI Line detect + DCD TAMPER_IRQHandler ; Tamper + DCD RTC_IRQHandler ; RTC + DCD FLASH_IRQHandler ; Flash + DCD RCC_IRQHandler ; RCC + DCD EXTI0_IRQHandler ; EXTI Line 0 + DCD EXTI1_IRQHandler ; EXTI Line 1 + DCD EXTI2_IRQHandler ; EXTI Line 2 + DCD EXTI3_IRQHandler ; EXTI Line 3 + DCD EXTI4_IRQHandler ; EXTI Line 4 + DCD DMA1_Channel1_IRQHandler ; DMA1 Channel 1 + DCD DMA1_Channel2_IRQHandler ; DMA1 Channel 2 + DCD DMA1_Channel3_IRQHandler ; DMA1 Channel 3 + DCD DMA1_Channel4_IRQHandler ; DMA1 Channel 4 + DCD DMA1_Channel5_IRQHandler ; DMA1 Channel 5 + DCD DMA1_Channel6_IRQHandler ; DMA1 Channel 6 + DCD DMA1_Channel7_IRQHandler ; DMA1 Channel 7 + DCD ADC1_2_IRQHandler ; ADC1 & ADC2 + DCD USB_HP_CAN1_TX_IRQHandler ; USB High Priority or CAN1 TX + DCD USB_LP_CAN1_RX0_IRQHandler ; USB Low Priority or CAN1 RX0 + DCD CAN1_RX1_IRQHandler ; CAN1 RX1 + DCD CAN1_SCE_IRQHandler ; CAN1 SCE + DCD EXTI9_5_IRQHandler ; EXTI Line 9..5 + DCD TIM1_BRK_TIM9_IRQHandler ; TIM1 Break and TIM9 + DCD TIM1_UP_TIM10_IRQHandler ; TIM1 Update and TIM10 + DCD TIM1_TRG_COM_TIM11_IRQHandler ; TIM1 Trigger and Commutation and TIM11 + DCD TIM1_CC_IRQHandler ; TIM1 Capture Compare + DCD TIM2_IRQHandler ; TIM2 + DCD TIM3_IRQHandler ; TIM3 + DCD TIM4_IRQHandler ; TIM4 + DCD I2C1_EV_IRQHandler ; I2C1 Event + DCD I2C1_ER_IRQHandler ; I2C1 Error + DCD I2C2_EV_IRQHandler ; I2C2 Event + DCD I2C2_ER_IRQHandler ; I2C2 Error + DCD SPI1_IRQHandler ; SPI1 + DCD SPI2_IRQHandler ; SPI2 + DCD USART1_IRQHandler ; USART1 + DCD USART2_IRQHandler ; USART2 + DCD USART3_IRQHandler ; USART3 + DCD EXTI15_10_IRQHandler ; EXTI Line 15..10 + DCD RTCAlarm_IRQHandler ; RTC Alarm through EXTI Line + DCD USBWakeUp_IRQHandler ; USB Wakeup from suspend + DCD TIM8_BRK_TIM12_IRQHandler ; TIM8 Break and TIM12 + DCD TIM8_UP_TIM13_IRQHandler ; TIM8 Update and TIM13 + DCD TIM8_TRG_COM_TIM14_IRQHandler ; TIM8 Trigger and Commutation and TIM14 + DCD TIM8_CC_IRQHandler ; TIM8 Capture Compare + DCD ADC3_IRQHandler ; ADC3 + DCD FSMC_IRQHandler ; FSMC + DCD SDIO_IRQHandler ; SDIO + DCD TIM5_IRQHandler ; TIM5 + DCD SPI3_IRQHandler ; SPI3 + DCD UART4_IRQHandler ; UART4 + DCD UART5_IRQHandler ; UART5 + DCD TIM6_IRQHandler ; TIM6 + DCD TIM7_IRQHandler ; TIM7 + DCD DMA2_Channel1_IRQHandler ; DMA2 Channel1 + DCD DMA2_Channel2_IRQHandler ; DMA2 Channel2 + DCD DMA2_Channel3_IRQHandler ; DMA2 Channel3 + DCD DMA2_Channel4_5_IRQHandler ; DMA2 Channel4 & Channel5 +__Vectors_End + +__Vectors_Size EQU __Vectors_End - __Vectors + + AREA |.text|, CODE, READONLY + +; Reset handler +Reset_Handler PROC + EXPORT Reset_Handler [WEAK] + IMPORT __main + IMPORT SystemInit + LDR R0, =SystemInit + BLX R0 + LDR R0, =__main + BX R0 + ENDP + +; Dummy Exception Handlers (infinite loops which can be modified) + +NMI_Handler PROC + EXPORT NMI_Handler [WEAK] + B . + ENDP +HardFault_Handler\ + PROC + EXPORT HardFault_Handler [WEAK] + B . + ENDP +MemManage_Handler\ + PROC + EXPORT MemManage_Handler [WEAK] + B . + ENDP +BusFault_Handler\ + PROC + EXPORT BusFault_Handler [WEAK] + B . + ENDP +UsageFault_Handler\ + PROC + EXPORT UsageFault_Handler [WEAK] + B . + ENDP +SVC_Handler PROC + EXPORT SVC_Handler [WEAK] + B . + ENDP +DebugMon_Handler\ + PROC + EXPORT DebugMon_Handler [WEAK] + B . + ENDP +PendSV_Handler PROC + EXPORT PendSV_Handler [WEAK] + B . + ENDP +SysTick_Handler PROC + EXPORT SysTick_Handler [WEAK] + B . + ENDP + +Default_Handler PROC + + EXPORT WWDG_IRQHandler [WEAK] + EXPORT PVD_IRQHandler [WEAK] + EXPORT TAMPER_IRQHandler [WEAK] + EXPORT RTC_IRQHandler [WEAK] + EXPORT FLASH_IRQHandler [WEAK] + EXPORT RCC_IRQHandler [WEAK] + EXPORT EXTI0_IRQHandler [WEAK] + EXPORT EXTI1_IRQHandler [WEAK] + EXPORT EXTI2_IRQHandler [WEAK] + EXPORT EXTI3_IRQHandler [WEAK] + EXPORT EXTI4_IRQHandler [WEAK] + EXPORT DMA1_Channel1_IRQHandler [WEAK] + EXPORT DMA1_Channel2_IRQHandler [WEAK] + EXPORT DMA1_Channel3_IRQHandler [WEAK] + EXPORT DMA1_Channel4_IRQHandler [WEAK] + EXPORT DMA1_Channel5_IRQHandler [WEAK] + EXPORT DMA1_Channel6_IRQHandler [WEAK] + EXPORT DMA1_Channel7_IRQHandler [WEAK] + EXPORT ADC1_2_IRQHandler [WEAK] + EXPORT USB_HP_CAN1_TX_IRQHandler [WEAK] + EXPORT USB_LP_CAN1_RX0_IRQHandler [WEAK] + EXPORT CAN1_RX1_IRQHandler [WEAK] + EXPORT CAN1_SCE_IRQHandler [WEAK] + EXPORT EXTI9_5_IRQHandler [WEAK] + EXPORT TIM1_BRK_TIM9_IRQHandler [WEAK] + EXPORT TIM1_UP_TIM10_IRQHandler [WEAK] + EXPORT TIM1_TRG_COM_TIM11_IRQHandler [WEAK] + EXPORT TIM1_CC_IRQHandler [WEAK] + EXPORT TIM2_IRQHandler [WEAK] + EXPORT TIM3_IRQHandler [WEAK] + EXPORT TIM4_IRQHandler [WEAK] + EXPORT I2C1_EV_IRQHandler [WEAK] + EXPORT I2C1_ER_IRQHandler [WEAK] + EXPORT I2C2_EV_IRQHandler [WEAK] + EXPORT I2C2_ER_IRQHandler [WEAK] + EXPORT SPI1_IRQHandler [WEAK] + EXPORT SPI2_IRQHandler [WEAK] + EXPORT USART1_IRQHandler [WEAK] + EXPORT USART2_IRQHandler [WEAK] + EXPORT USART3_IRQHandler [WEAK] + EXPORT EXTI15_10_IRQHandler [WEAK] + EXPORT RTCAlarm_IRQHandler [WEAK] + EXPORT USBWakeUp_IRQHandler [WEAK] + EXPORT TIM8_BRK_TIM12_IRQHandler [WEAK] + EXPORT TIM8_UP_TIM13_IRQHandler [WEAK] + EXPORT TIM8_TRG_COM_TIM14_IRQHandler [WEAK] + EXPORT TIM8_CC_IRQHandler [WEAK] + EXPORT ADC3_IRQHandler [WEAK] + EXPORT FSMC_IRQHandler [WEAK] + EXPORT SDIO_IRQHandler [WEAK] + EXPORT TIM5_IRQHandler [WEAK] + EXPORT SPI3_IRQHandler [WEAK] + EXPORT UART4_IRQHandler [WEAK] + EXPORT UART5_IRQHandler [WEAK] + EXPORT TIM6_IRQHandler [WEAK] + EXPORT TIM7_IRQHandler [WEAK] + EXPORT DMA2_Channel1_IRQHandler [WEAK] + EXPORT DMA2_Channel2_IRQHandler [WEAK] + EXPORT DMA2_Channel3_IRQHandler [WEAK] + EXPORT DMA2_Channel4_5_IRQHandler [WEAK] + +WWDG_IRQHandler +PVD_IRQHandler +TAMPER_IRQHandler +RTC_IRQHandler +FLASH_IRQHandler +RCC_IRQHandler +EXTI0_IRQHandler +EXTI1_IRQHandler +EXTI2_IRQHandler +EXTI3_IRQHandler +EXTI4_IRQHandler +DMA1_Channel1_IRQHandler +DMA1_Channel2_IRQHandler +DMA1_Channel3_IRQHandler +DMA1_Channel4_IRQHandler +DMA1_Channel5_IRQHandler +DMA1_Channel6_IRQHandler +DMA1_Channel7_IRQHandler +ADC1_2_IRQHandler +USB_HP_CAN1_TX_IRQHandler +USB_LP_CAN1_RX0_IRQHandler +CAN1_RX1_IRQHandler +CAN1_SCE_IRQHandler +EXTI9_5_IRQHandler +TIM1_BRK_TIM9_IRQHandler +TIM1_UP_TIM10_IRQHandler +TIM1_TRG_COM_TIM11_IRQHandler +TIM1_CC_IRQHandler +TIM2_IRQHandler +TIM3_IRQHandler +TIM4_IRQHandler +I2C1_EV_IRQHandler +I2C1_ER_IRQHandler +I2C2_EV_IRQHandler +I2C2_ER_IRQHandler +SPI1_IRQHandler +SPI2_IRQHandler +USART1_IRQHandler +USART2_IRQHandler +USART3_IRQHandler +EXTI15_10_IRQHandler +RTCAlarm_IRQHandler +USBWakeUp_IRQHandler +TIM8_BRK_TIM12_IRQHandler +TIM8_UP_TIM13_IRQHandler +TIM8_TRG_COM_TIM14_IRQHandler +TIM8_CC_IRQHandler +ADC3_IRQHandler +FSMC_IRQHandler +SDIO_IRQHandler +TIM5_IRQHandler +SPI3_IRQHandler +UART4_IRQHandler +UART5_IRQHandler +TIM6_IRQHandler +TIM7_IRQHandler +DMA2_Channel1_IRQHandler +DMA2_Channel2_IRQHandler +DMA2_Channel3_IRQHandler +DMA2_Channel4_5_IRQHandler + B . + + ENDP + + ALIGN + +;******************************************************************************* +; User Stack and Heap initialization +;******************************************************************************* + IF :DEF:__MICROLIB + + EXPORT __initial_sp + EXPORT __heap_base + EXPORT __heap_limit + + ELSE + + IMPORT __use_two_region_memory + EXPORT __user_initial_stackheap + +__user_initial_stackheap + + LDR R0, = Heap_Mem + LDR R1, =(Stack_Mem + Stack_Size) + LDR R2, = (Heap_Mem + Heap_Size) + LDR R3, = Stack_Mem + BX LR + + ALIGN + + ENDIF + + END + +;************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE***** diff --git a/Libraries/CMSIS/Device/ST/STM32F10x/Source/Templates/gcc_ride7/startup_stm32f10x_cl.s b/Libraries/CMSIS/Device/ST/STM32F10x/Source/Templates/gcc_ride7/startup_stm32f10x_cl.s new file mode 100644 index 0000000..5a5cd49 --- /dev/null +++ b/Libraries/CMSIS/Device/ST/STM32F10x/Source/Templates/gcc_ride7/startup_stm32f10x_cl.s @@ -0,0 +1,474 @@ +/** + ****************************************************************************** + * @file startup_stm32f10x_cl.s + * @author MCD Application Team + * @version V3.6.1 + * @date 09-March-2012 + * @brief STM32F10x Connectivity line Devices vector table for RIDE7 toolchain. + * This module performs: + * - Set the initial SP + * - Set the initial PC == Reset_Handler, + * - Set the vector table entries with the exceptions ISR + * address. + * - Configure the clock system + * - Branches to main in the C library (which eventually + * calls main()). + * After Reset the Cortex-M3 processor is in Thread mode, + * priority is Privileged, and the Stack is set to Main. + ****************************************************************************** + * @attention + * + *

© COPYRIGHT 2012 STMicroelectronics

+ * + * Licensed under MCD-ST Liberty SW License Agreement V2, (the "License"); + * You may not use this file except in compliance with the License. + * You may obtain a copy of the License at: + * + * http://www.st.com/software_license_agreement_liberty_v2 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, + * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + * + ****************************************************************************** + */ + + .syntax unified + .cpu cortex-m3 + .fpu softvfp + .thumb + +.global g_pfnVectors +.global Default_Handler + +/* start address for the initialization values of the .data section. +defined in linker script */ +.word _sidata +/* start address for the .data section. defined in linker script */ +.word _sdata +/* end address for the .data section. defined in linker script */ +.word _edata +/* start address for the .bss section. defined in linker script */ +.word _sbss +/* end address for the .bss section. defined in linker script */ +.word _ebss + +.equ BootRAM, 0xF1E0F85F +/** + * @brief This is the code that gets called when the processor first + * starts execution following a reset event. Only the absolutely + * necessary set is performed, after which the application + * supplied main() routine is called. + * @param None + * @retval : None +*/ + + .section .text.Reset_Handler + .weak Reset_Handler + .type Reset_Handler, %function +Reset_Handler: + +/* Copy the data segment initializers from flash to SRAM */ + movs r1, #0 + b LoopCopyDataInit + +CopyDataInit: + ldr r3, =_sidata + ldr r3, [r3, r1] + str r3, [r0, r1] + adds r1, r1, #4 + +LoopCopyDataInit: + ldr r0, =_sdata + ldr r3, =_edata + adds r2, r0, r1 + cmp r2, r3 + bcc CopyDataInit + ldr r2, =_sbss + b LoopFillZerobss + +/* Zero fill the bss segment. */ +FillZerobss: + movs r3, #0 + str r3, [r2], #4 + +LoopFillZerobss: + ldr r3, = _ebss + cmp r2, r3 + bcc FillZerobss +/* Call the clock system intitialization function.*/ + bl SystemInit +/* Call the application's entry point.*/ + bl main + bx lr +.size Reset_Handler, .-Reset_Handler + +/** + * @brief This is the code that gets called when the processor receives an + * unexpected interrupt. This simply enters an infinite loop, preserving + * the system state for examination by a debugger. + * @param None + * @retval None +*/ + .section .text.Default_Handler,"ax",%progbits +Default_Handler: +Infinite_Loop: + b Infinite_Loop + .size Default_Handler, .-Default_Handler + +/****************************************************************************** +* +* The minimal vector table for a Cortex M3. Note that the proper constructs +* must be placed on this to ensure that it ends up at physical address +* 0x0000.0000. +* +*******************************************************************************/ + .section .isr_vector,"a",%progbits + .type g_pfnVectors, %object + .size g_pfnVectors, .-g_pfnVectors + + +g_pfnVectors: + .word _estack + .word Reset_Handler + .word NMI_Handler + .word HardFault_Handler + .word MemManage_Handler + .word BusFault_Handler + .word UsageFault_Handler + .word 0 + .word 0 + .word 0 + .word 0 + .word SVC_Handler + .word DebugMon_Handler + .word 0 + .word PendSV_Handler + .word SysTick_Handler + .word WWDG_IRQHandler + .word PVD_IRQHandler + .word TAMPER_IRQHandler + .word RTC_IRQHandler + .word FLASH_IRQHandler + .word RCC_IRQHandler + .word EXTI0_IRQHandler + .word EXTI1_IRQHandler + .word EXTI2_IRQHandler + .word EXTI3_IRQHandler + .word EXTI4_IRQHandler + .word DMA1_Channel1_IRQHandler + .word DMA1_Channel2_IRQHandler + .word DMA1_Channel3_IRQHandler + .word DMA1_Channel4_IRQHandler + .word DMA1_Channel5_IRQHandler + .word DMA1_Channel6_IRQHandler + .word DMA1_Channel7_IRQHandler + .word ADC1_2_IRQHandler + .word CAN1_TX_IRQHandler + .word CAN1_RX0_IRQHandler + .word CAN1_RX1_IRQHandler + .word CAN1_SCE_IRQHandler + .word EXTI9_5_IRQHandler + .word TIM1_BRK_IRQHandler + .word TIM1_UP_IRQHandler + .word TIM1_TRG_COM_IRQHandler + .word TIM1_CC_IRQHandler + .word TIM2_IRQHandler + .word TIM3_IRQHandler + .word TIM4_IRQHandler + .word I2C1_EV_IRQHandler + .word I2C1_ER_IRQHandler + .word I2C2_EV_IRQHandler + .word I2C2_ER_IRQHandler + .word SPI1_IRQHandler + .word SPI2_IRQHandler + .word USART1_IRQHandler + .word USART2_IRQHandler + .word USART3_IRQHandler + .word EXTI15_10_IRQHandler + .word RTCAlarm_IRQHandler + .word OTG_FS_WKUP_IRQHandler + .word 0 + .word 0 + .word 0 + .word 0 + .word 0 + .word 0 + .word 0 + .word TIM5_IRQHandler + .word SPI3_IRQHandler + .word UART4_IRQHandler + .word UART5_IRQHandler + .word TIM6_IRQHandler + .word TIM7_IRQHandler + .word DMA2_Channel1_IRQHandler + .word DMA2_Channel2_IRQHandler + .word DMA2_Channel3_IRQHandler + .word DMA2_Channel4_IRQHandler + .word DMA2_Channel5_IRQHandler + .word ETH_IRQHandler + .word ETH_WKUP_IRQHandler + .word CAN2_TX_IRQHandler + .word CAN2_RX0_IRQHandler + .word CAN2_RX1_IRQHandler + .word CAN2_SCE_IRQHandler + .word OTG_FS_IRQHandler + .word 0 + .word 0 + .word 0 + .word 0 + .word 0 + .word 0 + .word 0 + .word 0 + .word 0 + .word 0 + .word 0 + .word 0 + .word 0 + .word 0 + .word 0 + .word 0 + .word 0 + .word 0 + .word 0 + .word 0 + .word 0 + .word 0 + .word 0 + .word 0 + .word 0 + .word 0 + .word 0 + .word 0 + .word 0 + .word 0 + .word 0 + .word 0 + .word 0 + .word 0 + .word 0 + .word 0 + .word BootRAM /* @0x1E0. This is for boot in RAM mode for + STM32F10x Connectivity line Devices. */ + +/******************************************************************************* +* +* Provide weak aliases for each Exception handler to the Default_Handler. +* As they are weak aliases, any function with the same name will override +* this definition. +* +*******************************************************************************/ + .weak NMI_Handler + .thumb_set NMI_Handler,Default_Handler + + .weak HardFault_Handler + .thumb_set HardFault_Handler,Default_Handler + + .weak MemManage_Handler + .thumb_set MemManage_Handler,Default_Handler + + .weak BusFault_Handler + .thumb_set BusFault_Handler,Default_Handler + + .weak UsageFault_Handler + .thumb_set UsageFault_Handler,Default_Handler + + .weak SVC_Handler + .thumb_set SVC_Handler,Default_Handler + + .weak DebugMon_Handler + .thumb_set DebugMon_Handler,Default_Handler + + .weak PendSV_Handler + .thumb_set PendSV_Handler,Default_Handler + + .weak SysTick_Handler + .thumb_set SysTick_Handler,Default_Handler + + .weak WWDG_IRQHandler + .thumb_set WWDG_IRQHandler,Default_Handler + + .weak PVD_IRQHandler + .thumb_set PVD_IRQHandler,Default_Handler + + .weak TAMPER_IRQHandler + .thumb_set TAMPER_IRQHandler,Default_Handler + + .weak RTC_IRQHandler + .thumb_set RTC_IRQHandler,Default_Handler + + .weak FLASH_IRQHandler + .thumb_set FLASH_IRQHandler,Default_Handler + + .weak RCC_IRQHandler + .thumb_set RCC_IRQHandler,Default_Handler + + .weak EXTI0_IRQHandler + .thumb_set EXTI0_IRQHandler,Default_Handler + + .weak EXTI1_IRQHandler + .thumb_set EXTI1_IRQHandler,Default_Handler + + .weak EXTI2_IRQHandler + .thumb_set EXTI2_IRQHandler,Default_Handler + + .weak EXTI3_IRQHandler + .thumb_set EXTI3_IRQHandler,Default_Handler + + .weak EXTI4_IRQHandler + .thumb_set EXTI4_IRQHandler,Default_Handler + + .weak DMA1_Channel1_IRQHandler + .thumb_set DMA1_Channel1_IRQHandler,Default_Handler + + .weak DMA1_Channel2_IRQHandler + .thumb_set DMA1_Channel2_IRQHandler,Default_Handler + + .weak DMA1_Channel3_IRQHandler + .thumb_set DMA1_Channel3_IRQHandler,Default_Handler + + .weak DMA1_Channel4_IRQHandler + .thumb_set DMA1_Channel4_IRQHandler,Default_Handler + + .weak DMA1_Channel5_IRQHandler + .thumb_set DMA1_Channel5_IRQHandler,Default_Handler + + .weak DMA1_Channel6_IRQHandler + .thumb_set DMA1_Channel6_IRQHandler,Default_Handler + + .weak DMA1_Channel7_IRQHandler + .thumb_set DMA1_Channel7_IRQHandler,Default_Handler + + .weak ADC1_2_IRQHandler + .thumb_set ADC1_2_IRQHandler,Default_Handler + + .weak CAN1_TX_IRQHandler + .thumb_set CAN1_TX_IRQHandler,Default_Handler + + .weak CAN1_RX0_IRQHandler + .thumb_set CAN1_RX0_IRQHandler,Default_Handler + + .weak CAN1_RX1_IRQHandler + .thumb_set CAN1_RX1_IRQHandler,Default_Handler + + .weak CAN1_SCE_IRQHandler + .thumb_set CAN1_SCE_IRQHandler,Default_Handler + + .weak EXTI9_5_IRQHandler + .thumb_set EXTI9_5_IRQHandler,Default_Handler + + .weak TIM1_BRK_IRQHandler + .thumb_set TIM1_BRK_IRQHandler,Default_Handler + + .weak TIM1_UP_IRQHandler + .thumb_set TIM1_UP_IRQHandler,Default_Handler + + .weak TIM1_TRG_COM_IRQHandler + .thumb_set TIM1_TRG_COM_IRQHandler,Default_Handler + + .weak TIM1_CC_IRQHandler + .thumb_set TIM1_CC_IRQHandler,Default_Handler + + .weak TIM2_IRQHandler + .thumb_set TIM2_IRQHandler,Default_Handler + + .weak TIM3_IRQHandler + .thumb_set TIM3_IRQHandler,Default_Handler + + .weak TIM4_IRQHandler + .thumb_set TIM4_IRQHandler,Default_Handler + + .weak I2C1_EV_IRQHandler + .thumb_set I2C1_EV_IRQHandler,Default_Handler + + .weak I2C1_ER_IRQHandler + .thumb_set I2C1_ER_IRQHandler,Default_Handler + + .weak I2C2_EV_IRQHandler + .thumb_set I2C2_EV_IRQHandler,Default_Handler + + .weak I2C2_ER_IRQHandler + .thumb_set I2C2_ER_IRQHandler,Default_Handler + + .weak SPI1_IRQHandler + .thumb_set SPI1_IRQHandler,Default_Handler + + .weak SPI2_IRQHandler + .thumb_set SPI2_IRQHandler,Default_Handler + + .weak USART1_IRQHandler + .thumb_set USART1_IRQHandler,Default_Handler + + .weak USART2_IRQHandler + .thumb_set USART2_IRQHandler,Default_Handler + + .weak USART3_IRQHandler + .thumb_set USART3_IRQHandler,Default_Handler + + .weak EXTI15_10_IRQHandler + .thumb_set EXTI15_10_IRQHandler,Default_Handler + + .weak RTCAlarm_IRQHandler + .thumb_set RTCAlarm_IRQHandler,Default_Handler + + .weak OTG_FS_WKUP_IRQHandler + .thumb_set OTG_FS_WKUP_IRQHandler,Default_Handler + + .weak TIM5_IRQHandler + .thumb_set TIM5_IRQHandler,Default_Handler + + .weak SPI3_IRQHandler + .thumb_set SPI3_IRQHandler,Default_Handler + + .weak UART4_IRQHandler + .thumb_set UART4_IRQHandler,Default_Handler + + .weak UART5_IRQHandler + .thumb_set UART5_IRQHandler,Default_Handler + + .weak TIM6_IRQHandler + .thumb_set TIM6_IRQHandler,Default_Handler + + .weak TIM7_IRQHandler + .thumb_set TIM7_IRQHandler,Default_Handler + + .weak DMA2_Channel1_IRQHandler + .thumb_set DMA2_Channel1_IRQHandler,Default_Handler + + .weak DMA2_Channel2_IRQHandler + .thumb_set DMA2_Channel2_IRQHandler,Default_Handler + + .weak DMA2_Channel3_IRQHandler + .thumb_set DMA2_Channel3_IRQHandler,Default_Handler + + .weak DMA2_Channel4_IRQHandler + .thumb_set DMA2_Channel4_IRQHandler,Default_Handler + + .weak DMA2_Channel5_IRQHandler + .thumb_set DMA2_Channel5_IRQHandler,Default_Handler + + .weak ETH_IRQHandler + .thumb_set ETH_IRQHandler,Default_Handler + + .weak ETH_WKUP_IRQHandler + .thumb_set ETH_WKUP_IRQHandler,Default_Handler + + .weak CAN2_TX_IRQHandler + .thumb_set CAN2_TX_IRQHandler,Default_Handler + + .weak CAN2_RX0_IRQHandler + .thumb_set CAN2_RX0_IRQHandler,Default_Handler + + .weak CAN2_RX1_IRQHandler + .thumb_set CAN2_RX1_IRQHandler,Default_Handler + + .weak CAN2_SCE_IRQHandler + .thumb_set CAN2_SCE_IRQHandler,Default_Handler + + .weak OTG_FS_IRQHandler + .thumb_set OTG_FS_IRQHandler ,Default_Handler + +/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ diff --git a/Libraries/CMSIS/Device/ST/STM32F10x/Source/Templates/gcc_ride7/startup_stm32f10x_hd.s b/Libraries/CMSIS/Device/ST/STM32F10x/Source/Templates/gcc_ride7/startup_stm32f10x_hd.s new file mode 100644 index 0000000..f312d2f --- /dev/null +++ b/Libraries/CMSIS/Device/ST/STM32F10x/Source/Templates/gcc_ride7/startup_stm32f10x_hd.s @@ -0,0 +1,471 @@ +/** + ****************************************************************************** + * @file startup_stm32f10x_hd.s + * @author MCD Application Team + * @version V3.6.1 + * @date 09-March-2012 + * @brief STM32F10x High Density Devices vector table for RIDE7 toolchain. + * This module performs: + * - Set the initial SP + * - Set the initial PC == Reset_Handler, + * - Set the vector table entries with the exceptions ISR address + * - Configure the clock system and the external SRAM mounted on + * STM3210E-EVAL board to be used as data memory (optional, + * to be enabled by user) + * - Branches to main in the C library (which eventually + * calls main()). + * After Reset the Cortex-M3 processor is in Thread mode, + * priority is Privileged, and the Stack is set to Main. + ****************************************************************************** + * @attention + * + *

© COPYRIGHT 2012 STMicroelectronics

+ * + * Licensed under MCD-ST Liberty SW License Agreement V2, (the "License"); + * You may not use this file except in compliance with the License. + * You may obtain a copy of the License at: + * + * http://www.st.com/software_license_agreement_liberty_v2 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, + * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + * + ****************************************************************************** + */ + + .syntax unified + .cpu cortex-m3 + .fpu softvfp + .thumb + +.global g_pfnVectors +.global Default_Handler + +/* start address for the initialization values of the .data section. +defined in linker script */ +.word _sidata +/* start address for the .data section. defined in linker script */ +.word _sdata +/* end address for the .data section. defined in linker script */ +.word _edata +/* start address for the .bss section. defined in linker script */ +.word _sbss +/* end address for the .bss section. defined in linker script */ +.word _ebss +/* stack used for SystemInit_ExtMemCtl; always internal RAM used */ + +.equ BootRAM, 0xF1E0F85F +/** + * @brief This is the code that gets called when the processor first + * starts execution following a reset event. Only the absolutely + * necessary set is performed, after which the application + * supplied main() routine is called. + * @param None + * @retval : None +*/ + + .section .text.Reset_Handler + .weak Reset_Handler + .type Reset_Handler, %function +Reset_Handler: + +/* Copy the data segment initializers from flash to SRAM */ + movs r1, #0 + b LoopCopyDataInit + +CopyDataInit: + ldr r3, =_sidata + ldr r3, [r3, r1] + str r3, [r0, r1] + adds r1, r1, #4 + +LoopCopyDataInit: + ldr r0, =_sdata + ldr r3, =_edata + adds r2, r0, r1 + cmp r2, r3 + bcc CopyDataInit + ldr r2, =_sbss + b LoopFillZerobss +/* Zero fill the bss segment. */ +FillZerobss: + movs r3, #0 + str r3, [r2], #4 + +LoopFillZerobss: + ldr r3, = _ebss + cmp r2, r3 + bcc FillZerobss +/* Call the clock system intitialization function.*/ + bl SystemInit +/* Call the application's entry point.*/ + bl main + bx lr +.size Reset_Handler, .-Reset_Handler + +/** + * @brief This is the code that gets called when the processor receives an + * unexpected interrupt. This simply enters an infinite loop, preserving + * the system state for examination by a debugger. + * @param None + * @retval None +*/ + .section .text.Default_Handler,"ax",%progbits +Default_Handler: +Infinite_Loop: + b Infinite_Loop + .size Default_Handler, .-Default_Handler +/****************************************************************************** +* +* The minimal vector table for a Cortex M3. Note that the proper constructs +* must be placed on this to ensure that it ends up at physical address +* 0x0000.0000. +* +*******************************************************************************/ + .section .isr_vector,"a",%progbits + .type g_pfnVectors, %object + .size g_pfnVectors, .-g_pfnVectors + + +g_pfnVectors: + .word _estack + .word Reset_Handler + .word NMI_Handler + .word HardFault_Handler + .word MemManage_Handler + .word BusFault_Handler + .word UsageFault_Handler + .word 0 + .word 0 + .word 0 + .word 0 + .word SVC_Handler + .word DebugMon_Handler + .word 0 + .word PendSV_Handler + .word SysTick_Handler + .word WWDG_IRQHandler + .word PVD_IRQHandler + .word TAMPER_IRQHandler + .word RTC_IRQHandler + .word FLASH_IRQHandler + .word RCC_IRQHandler + .word EXTI0_IRQHandler + .word EXTI1_IRQHandler + .word EXTI2_IRQHandler + .word EXTI3_IRQHandler + .word EXTI4_IRQHandler + .word DMA1_Channel1_IRQHandler + .word DMA1_Channel2_IRQHandler + .word DMA1_Channel3_IRQHandler + .word DMA1_Channel4_IRQHandler + .word DMA1_Channel5_IRQHandler + .word DMA1_Channel6_IRQHandler + .word DMA1_Channel7_IRQHandler + .word ADC1_2_IRQHandler + .word USB_HP_CAN1_TX_IRQHandler + .word USB_LP_CAN1_RX0_IRQHandler + .word CAN1_RX1_IRQHandler + .word CAN1_SCE_IRQHandler + .word EXTI9_5_IRQHandler + .word TIM1_BRK_IRQHandler + .word TIM1_UP_IRQHandler + .word TIM1_TRG_COM_IRQHandler + .word TIM1_CC_IRQHandler + .word TIM2_IRQHandler + .word TIM3_IRQHandler + .word TIM4_IRQHandler + .word I2C1_EV_IRQHandler + .word I2C1_ER_IRQHandler + .word I2C2_EV_IRQHandler + .word I2C2_ER_IRQHandler + .word SPI1_IRQHandler + .word SPI2_IRQHandler + .word USART1_IRQHandler + .word USART2_IRQHandler + .word USART3_IRQHandler + .word EXTI15_10_IRQHandler + .word RTCAlarm_IRQHandler + .word USBWakeUp_IRQHandler + .word TIM8_BRK_IRQHandler + .word TIM8_UP_IRQHandler + .word TIM8_TRG_COM_IRQHandler + .word TIM8_CC_IRQHandler + .word ADC3_IRQHandler + .word FSMC_IRQHandler + .word SDIO_IRQHandler + .word TIM5_IRQHandler + .word SPI3_IRQHandler + .word UART4_IRQHandler + .word UART5_IRQHandler + .word TIM6_IRQHandler + .word TIM7_IRQHandler + .word DMA2_Channel1_IRQHandler + .word DMA2_Channel2_IRQHandler + .word DMA2_Channel3_IRQHandler + .word DMA2_Channel4_5_IRQHandler + .word 0 + .word 0 + .word 0 + .word 0 + .word 0 + .word 0 + .word 0 + .word 0 + .word 0 + .word 0 + .word 0 + .word 0 + .word 0 + .word 0 + .word 0 + .word 0 + .word 0 + .word 0 + .word 0 + .word 0 + .word 0 + .word 0 + .word 0 + .word 0 + .word 0 + .word 0 + .word 0 + .word 0 + .word 0 + .word 0 + .word 0 + .word 0 + .word 0 + .word 0 + .word 0 + .word 0 + .word 0 + .word 0 + .word 0 + .word 0 + .word 0 + .word 0 + .word 0 + .word 0 + .word BootRAM /* @0x1E0. This is for boot in RAM mode for + STM32F10x High Density devices. */ +/******************************************************************************* +* +* Provide weak aliases for each Exception handler to the Default_Handler. +* As they are weak aliases, any function with the same name will override +* this definition. +* +*******************************************************************************/ + + .weak NMI_Handler + .thumb_set NMI_Handler,Default_Handler + + .weak HardFault_Handler + .thumb_set HardFault_Handler,Default_Handler + + .weak MemManage_Handler + .thumb_set MemManage_Handler,Default_Handler + + .weak BusFault_Handler + .thumb_set BusFault_Handler,Default_Handler + + .weak UsageFault_Handler + .thumb_set UsageFault_Handler,Default_Handler + + .weak SVC_Handler + .thumb_set SVC_Handler,Default_Handler + + .weak DebugMon_Handler + .thumb_set DebugMon_Handler,Default_Handler + + .weak PendSV_Handler + .thumb_set PendSV_Handler,Default_Handler + + .weak SysTick_Handler + .thumb_set SysTick_Handler,Default_Handler + + .weak WWDG_IRQHandler + .thumb_set WWDG_IRQHandler,Default_Handler + + .weak PVD_IRQHandler + .thumb_set PVD_IRQHandler,Default_Handler + + .weak TAMPER_IRQHandler + .thumb_set TAMPER_IRQHandler,Default_Handler + + .weak RTC_IRQHandler + .thumb_set RTC_IRQHandler,Default_Handler + + .weak FLASH_IRQHandler + .thumb_set FLASH_IRQHandler,Default_Handler + + .weak RCC_IRQHandler + .thumb_set RCC_IRQHandler,Default_Handler + + .weak EXTI0_IRQHandler + .thumb_set EXTI0_IRQHandler,Default_Handler + + .weak EXTI1_IRQHandler + .thumb_set EXTI1_IRQHandler,Default_Handler + + .weak EXTI2_IRQHandler + .thumb_set EXTI2_IRQHandler,Default_Handler + + .weak EXTI3_IRQHandler + .thumb_set EXTI3_IRQHandler,Default_Handler + + .weak EXTI4_IRQHandler + .thumb_set EXTI4_IRQHandler,Default_Handler + + .weak DMA1_Channel1_IRQHandler + .thumb_set DMA1_Channel1_IRQHandler,Default_Handler + + .weak DMA1_Channel2_IRQHandler + .thumb_set DMA1_Channel2_IRQHandler,Default_Handler + + .weak DMA1_Channel3_IRQHandler + .thumb_set DMA1_Channel3_IRQHandler,Default_Handler + + .weak DMA1_Channel4_IRQHandler + .thumb_set DMA1_Channel4_IRQHandler,Default_Handler + + .weak DMA1_Channel5_IRQHandler + .thumb_set DMA1_Channel5_IRQHandler,Default_Handler + + .weak DMA1_Channel6_IRQHandler + .thumb_set DMA1_Channel6_IRQHandler,Default_Handler + + .weak DMA1_Channel7_IRQHandler + .thumb_set DMA1_Channel7_IRQHandler,Default_Handler + + .weak ADC1_2_IRQHandler + .thumb_set ADC1_2_IRQHandler,Default_Handler + + .weak USB_HP_CAN1_TX_IRQHandler + .thumb_set USB_HP_CAN1_TX_IRQHandler,Default_Handler + + .weak USB_LP_CAN1_RX0_IRQHandler + .thumb_set USB_LP_CAN1_RX0_IRQHandler,Default_Handler + + .weak CAN1_RX1_IRQHandler + .thumb_set CAN1_RX1_IRQHandler,Default_Handler + + .weak CAN1_SCE_IRQHandler + .thumb_set CAN1_SCE_IRQHandler,Default_Handler + + .weak EXTI9_5_IRQHandler + .thumb_set EXTI9_5_IRQHandler,Default_Handler + + .weak TIM1_BRK_IRQHandler + .thumb_set TIM1_BRK_IRQHandler,Default_Handler + + .weak TIM1_UP_IRQHandler + .thumb_set TIM1_UP_IRQHandler,Default_Handler + + .weak TIM1_TRG_COM_IRQHandler + .thumb_set TIM1_TRG_COM_IRQHandler,Default_Handler + + .weak TIM1_CC_IRQHandler + .thumb_set TIM1_CC_IRQHandler,Default_Handler + + .weak TIM2_IRQHandler + .thumb_set TIM2_IRQHandler,Default_Handler + + .weak TIM3_IRQHandler + .thumb_set TIM3_IRQHandler,Default_Handler + + .weak TIM4_IRQHandler + .thumb_set TIM4_IRQHandler,Default_Handler + + .weak I2C1_EV_IRQHandler + .thumb_set I2C1_EV_IRQHandler,Default_Handler + + .weak I2C1_ER_IRQHandler + .thumb_set I2C1_ER_IRQHandler,Default_Handler + + .weak I2C2_EV_IRQHandler + .thumb_set I2C2_EV_IRQHandler,Default_Handler + + .weak I2C2_ER_IRQHandler + .thumb_set I2C2_ER_IRQHandler,Default_Handler + + .weak SPI1_IRQHandler + .thumb_set SPI1_IRQHandler,Default_Handler + + .weak SPI2_IRQHandler + .thumb_set SPI2_IRQHandler,Default_Handler + + .weak USART1_IRQHandler + .thumb_set USART1_IRQHandler,Default_Handler + + .weak USART2_IRQHandler + .thumb_set USART2_IRQHandler,Default_Handler + + .weak USART3_IRQHandler + .thumb_set USART3_IRQHandler,Default_Handler + + .weak EXTI15_10_IRQHandler + .thumb_set EXTI15_10_IRQHandler,Default_Handler + + .weak RTCAlarm_IRQHandler + .thumb_set RTCAlarm_IRQHandler,Default_Handler + + .weak USBWakeUp_IRQHandler + .thumb_set USBWakeUp_IRQHandler,Default_Handler + + .weak TIM8_BRK_IRQHandler + .thumb_set TIM8_BRK_IRQHandler,Default_Handler + + .weak TIM8_UP_IRQHandler + .thumb_set TIM8_UP_IRQHandler,Default_Handler + + .weak TIM8_TRG_COM_IRQHandler + .thumb_set TIM8_TRG_COM_IRQHandler,Default_Handler + + .weak TIM8_CC_IRQHandler + .thumb_set TIM8_CC_IRQHandler,Default_Handler + + .weak ADC3_IRQHandler + .thumb_set ADC3_IRQHandler,Default_Handler + + .weak FSMC_IRQHandler + .thumb_set FSMC_IRQHandler,Default_Handler + + .weak SDIO_IRQHandler + .thumb_set SDIO_IRQHandler,Default_Handler + + .weak TIM5_IRQHandler + .thumb_set TIM5_IRQHandler,Default_Handler + + .weak SPI3_IRQHandler + .thumb_set SPI3_IRQHandler,Default_Handler + + .weak UART4_IRQHandler + .thumb_set UART4_IRQHandler,Default_Handler + + .weak UART5_IRQHandler + .thumb_set UART5_IRQHandler,Default_Handler + + .weak TIM6_IRQHandler + .thumb_set TIM6_IRQHandler,Default_Handler + + .weak TIM7_IRQHandler + .thumb_set TIM7_IRQHandler,Default_Handler + + .weak DMA2_Channel1_IRQHandler + .thumb_set DMA2_Channel1_IRQHandler,Default_Handler + + .weak DMA2_Channel2_IRQHandler + .thumb_set DMA2_Channel2_IRQHandler,Default_Handler + + .weak DMA2_Channel3_IRQHandler + .thumb_set DMA2_Channel3_IRQHandler,Default_Handler + + .weak DMA2_Channel4_5_IRQHandler + .thumb_set DMA2_Channel4_5_IRQHandler,Default_Handler + +/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ diff --git a/Libraries/CMSIS/Device/ST/STM32F10x/Source/Templates/gcc_ride7/startup_stm32f10x_hd_vl.s b/Libraries/CMSIS/Device/ST/STM32F10x/Source/Templates/gcc_ride7/startup_stm32f10x_hd_vl.s new file mode 100644 index 0000000..d226209 --- /dev/null +++ b/Libraries/CMSIS/Device/ST/STM32F10x/Source/Templates/gcc_ride7/startup_stm32f10x_hd_vl.s @@ -0,0 +1,448 @@ +/** + ****************************************************************************** + * @file startup_stm32f10x_hd_vl.s + * @author MCD Application Team + * @version V3.6.1 + * @date 09-March-2012 + * @brief STM32F10x High Density Value Line Devices vector table for RIDE7 + * toolchain. + * This module performs: + * - Set the initial SP + * - Set the initial PC == Reset_Handler, + * - Set the vector table entries with the exceptions ISR address + * - Configure the clock system and the external SRAM mounted on + * STM32100E-EVAL board to be used as data memory (optional, + * to be enabled by user) + * - Branches to main in the C library (which eventually + * calls main()). + * After Reset the Cortex-M3 processor is in Thread mode, + * priority is Privileged, and the Stack is set to Main. + ****************************************************************************** + * @attention + * + *

© COPYRIGHT 2012 STMicroelectronics

+ * + * Licensed under MCD-ST Liberty SW License Agreement V2, (the "License"); + * You may not use this file except in compliance with the License. + * You may obtain a copy of the License at: + * + * http://www.st.com/software_license_agreement_liberty_v2 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, + * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + * + ****************************************************************************** + */ + + .syntax unified + .cpu cortex-m3 + .fpu softvfp + .thumb + +.global g_pfnVectors +.global Default_Handler + +/* start address for the initialization values of the .data section. +defined in linker script */ +.word _sidata +/* start address for the .data section. defined in linker script */ +.word _sdata +/* end address for the .data section. defined in linker script */ +.word _edata +/* start address for the .bss section. defined in linker script */ +.word _sbss +/* end address for the .bss section. defined in linker script */ +.word _ebss + +.equ BootRAM, 0xF108F85F +/** + * @brief This is the code that gets called when the processor first + * starts execution following a reset event. Only the absolutely + * necessary set is performed, after which the application + * supplied main() routine is called. + * @param None + * @retval None +*/ + + .section .text.Reset_Handler + .weak Reset_Handler + .type Reset_Handler, %function +Reset_Handler: + +/* Copy the data segment initializers from flash to SRAM */ + movs r1, #0 + b LoopCopyDataInit + +CopyDataInit: + ldr r3, =_sidata + ldr r3, [r3, r1] + str r3, [r0, r1] + adds r1, r1, #4 + +LoopCopyDataInit: + ldr r0, =_sdata + ldr r3, =_edata + adds r2, r0, r1 + cmp r2, r3 + bcc CopyDataInit + ldr r2, =_sbss + b LoopFillZerobss +/* Zero fill the bss segment. */ +FillZerobss: + movs r3, #0 + str r3, [r2], #4 + +LoopFillZerobss: + ldr r3, = _ebss + cmp r2, r3 + bcc FillZerobss +/* Call the clock system intitialization function.*/ + bl SystemInit +/* Call the application's entry point.*/ + bl main + bx lr +.size Reset_Handler, .-Reset_Handler + +/** + * @brief This is the code that gets called when the processor receives an + * unexpected interrupt. This simply enters an infinite loop, preserving + * the system state for examination by a debugger. + * @param None + * @retval None +*/ + .section .text.Default_Handler,"ax",%progbits +Default_Handler: +Infinite_Loop: + b Infinite_Loop + .size Default_Handler, .-Default_Handler +/****************************************************************************** +* +* The minimal vector table for a Cortex M3. Note that the proper constructs +* must be placed on this to ensure that it ends up at physical address +* 0x0000.0000. +* +******************************************************************************/ + .section .isr_vector,"a",%progbits + .type g_pfnVectors, %object + .size g_pfnVectors, .-g_pfnVectors + +g_pfnVectors: + .word _estack + .word Reset_Handler + .word NMI_Handler + .word HardFault_Handler + .word MemManage_Handler + .word BusFault_Handler + .word UsageFault_Handler + .word 0 + .word 0 + .word 0 + .word 0 + .word SVC_Handler + .word DebugMon_Handler + .word 0 + .word PendSV_Handler + .word SysTick_Handler + .word WWDG_IRQHandler + .word PVD_IRQHandler + .word TAMPER_IRQHandler + .word RTC_IRQHandler + .word FLASH_IRQHandler + .word RCC_IRQHandler + .word EXTI0_IRQHandler + .word EXTI1_IRQHandler + .word EXTI2_IRQHandler + .word EXTI3_IRQHandler + .word EXTI4_IRQHandler + .word DMA1_Channel1_IRQHandler + .word DMA1_Channel2_IRQHandler + .word DMA1_Channel3_IRQHandler + .word DMA1_Channel4_IRQHandler + .word DMA1_Channel5_IRQHandler + .word DMA1_Channel6_IRQHandler + .word DMA1_Channel7_IRQHandler + .word ADC1_IRQHandler + .word 0 + .word 0 + .word 0 + .word 0 + .word EXTI9_5_IRQHandler + .word TIM1_BRK_TIM15_IRQHandler + .word TIM1_UP_TIM16_IRQHandler + .word TIM1_TRG_COM_TIM17_IRQHandler + .word TIM1_CC_IRQHandler + .word TIM2_IRQHandler + .word TIM3_IRQHandler + .word TIM4_IRQHandler + .word I2C1_EV_IRQHandler + .word I2C1_ER_IRQHandler + .word I2C2_EV_IRQHandler + .word I2C2_ER_IRQHandler + .word SPI1_IRQHandler + .word SPI2_IRQHandler + .word USART1_IRQHandler + .word USART2_IRQHandler + .word USART3_IRQHandler + .word EXTI15_10_IRQHandler + .word RTCAlarm_IRQHandler + .word CEC_IRQHandler + .word TIM12_IRQHandler + .word TIM13_IRQHandler + .word TIM14_IRQHandler + .word 0 + .word 0 + .word 0 + .word 0 + .word TIM5_IRQHandler + .word SPI3_IRQHandler + .word UART4_IRQHandler + .word UART5_IRQHandler + .word TIM6_DAC_IRQHandler + .word TIM7_IRQHandler + .word DMA2_Channel1_IRQHandler + .word DMA2_Channel2_IRQHandler + .word DMA2_Channel3_IRQHandler + .word DMA2_Channel4_5_IRQHandler + .word DMA2_Channel5_IRQHandler + .word 0 + .word 0 + .word 0 + .word 0 + .word 0 + .word 0 + .word 0 + .word 0 + .word 0 + .word 0 + .word 0 + .word 0 + .word 0 + .word 0 + .word 0 + .word 0 + .word 0 + .word 0 + .word 0 + .word 0 + .word 0 + .word 0 + .word 0 + .word 0 + .word 0 + .word 0 + .word 0 + .word 0 + .word 0 + .word 0 + .word 0 + .word 0 + .word 0 + .word 0 + .word 0 + .word 0 + .word 0 + .word 0 + .word 0 + .word 0 + .word 0 + .word 0 + .word 0 + .word BootRAM /* @0x1E0. This is for boot in RAM mode for + STM32F10x High Density Value line devices. */ + +/******************************************************************************* +* Provide weak aliases for each Exception handler to the Default_Handler. +* As they are weak aliases, any function with the same name will override +* this definition. +*******************************************************************************/ + + .weak NMI_Handler + .thumb_set NMI_Handler,Default_Handler + + .weak HardFault_Handler + .thumb_set HardFault_Handler,Default_Handler + + .weak MemManage_Handler + .thumb_set MemManage_Handler,Default_Handler + + .weak BusFault_Handler + .thumb_set BusFault_Handler,Default_Handler + + .weak UsageFault_Handler + .thumb_set UsageFault_Handler,Default_Handler + + .weak SVC_Handler + .thumb_set SVC_Handler,Default_Handler + + .weak DebugMon_Handler + .thumb_set DebugMon_Handler,Default_Handler + + .weak PendSV_Handler + .thumb_set PendSV_Handler,Default_Handler + + .weak SysTick_Handler + .thumb_set SysTick_Handler,Default_Handler + + .weak WWDG_IRQHandler + .thumb_set WWDG_IRQHandler,Default_Handler + + .weak PVD_IRQHandler + .thumb_set PVD_IRQHandler,Default_Handler + + .weak TAMPER_IRQHandler + .thumb_set TAMPER_IRQHandler,Default_Handler + + .weak RTC_IRQHandler + .thumb_set RTC_IRQHandler,Default_Handler + + .weak FLASH_IRQHandler + .thumb_set FLASH_IRQHandler,Default_Handler + + .weak RCC_IRQHandler + .thumb_set RCC_IRQHandler,Default_Handler + + .weak EXTI0_IRQHandler + .thumb_set EXTI0_IRQHandler,Default_Handler + + .weak EXTI1_IRQHandler + .thumb_set EXTI1_IRQHandler,Default_Handler + + .weak EXTI2_IRQHandler + .thumb_set EXTI2_IRQHandler,Default_Handler + + .weak EXTI3_IRQHandler + .thumb_set EXTI3_IRQHandler,Default_Handler + + .weak EXTI4_IRQHandler + .thumb_set EXTI4_IRQHandler,Default_Handler + + .weak DMA1_Channel1_IRQHandler + .thumb_set DMA1_Channel1_IRQHandler,Default_Handler + + .weak DMA1_Channel2_IRQHandler + .thumb_set DMA1_Channel2_IRQHandler,Default_Handler + + .weak DMA1_Channel3_IRQHandler + .thumb_set DMA1_Channel3_IRQHandler,Default_Handler + + .weak DMA1_Channel4_IRQHandler + .thumb_set DMA1_Channel4_IRQHandler,Default_Handler + + .weak DMA1_Channel5_IRQHandler + .thumb_set DMA1_Channel5_IRQHandler,Default_Handler + + .weak DMA1_Channel6_IRQHandler + .thumb_set DMA1_Channel6_IRQHandler,Default_Handler + + .weak DMA1_Channel7_IRQHandler + .thumb_set DMA1_Channel7_IRQHandler,Default_Handler + + .weak ADC1_IRQHandler + .thumb_set ADC1_IRQHandler,Default_Handler + + .weak EXTI9_5_IRQHandler + .thumb_set EXTI9_5_IRQHandler,Default_Handler + + .weak TIM1_BRK_TIM15_IRQHandler + .thumb_set TIM1_BRK_TIM15_IRQHandler,Default_Handler + + .weak TIM1_UP_TIM16_IRQHandler + .thumb_set TIM1_UP_TIM16_IRQHandler,Default_Handler + + .weak TIM1_TRG_COM_TIM17_IRQHandler + .thumb_set TIM1_TRG_COM_TIM17_IRQHandler,Default_Handler + + .weak TIM1_CC_IRQHandler + .thumb_set TIM1_CC_IRQHandler,Default_Handler + + .weak TIM2_IRQHandler + .thumb_set TIM2_IRQHandler,Default_Handler + + .weak TIM3_IRQHandler + .thumb_set TIM3_IRQHandler,Default_Handler + + .weak TIM4_IRQHandler + .thumb_set TIM4_IRQHandler,Default_Handler + + .weak I2C1_EV_IRQHandler + .thumb_set I2C1_EV_IRQHandler,Default_Handler + + .weak I2C1_ER_IRQHandler + .thumb_set I2C1_ER_IRQHandler,Default_Handler + + .weak I2C2_EV_IRQHandler + .thumb_set I2C2_EV_IRQHandler,Default_Handler + + .weak I2C2_ER_IRQHandler + .thumb_set I2C2_ER_IRQHandler,Default_Handler + + .weak SPI1_IRQHandler + .thumb_set SPI1_IRQHandler,Default_Handler + + .weak SPI2_IRQHandler + .thumb_set SPI2_IRQHandler,Default_Handler + + .weak USART1_IRQHandler + .thumb_set USART1_IRQHandler,Default_Handler + + .weak USART2_IRQHandler + .thumb_set USART2_IRQHandler,Default_Handler + + .weak USART3_IRQHandler + .thumb_set USART3_IRQHandler,Default_Handler + + .weak EXTI15_10_IRQHandler + .thumb_set EXTI15_10_IRQHandler,Default_Handler + + .weak RTCAlarm_IRQHandler + .thumb_set RTCAlarm_IRQHandler,Default_Handler + + .weak CEC_IRQHandler + .thumb_set CEC_IRQHandler,Default_Handler + + .weak TIM12_IRQHandler + .thumb_set TIM12_IRQHandler,Default_Handler + + .weak TIM13_IRQHandler + .thumb_set TIM13_IRQHandler,Default_Handler + + .weak TIM14_IRQHandler + .thumb_set TIM14_IRQHandler,Default_Handler + + .weak TIM5_IRQHandler + .thumb_set TIM5_IRQHandler,Default_Handler + + .weak SPI3_IRQHandler + .thumb_set SPI3_IRQHandler,Default_Handler + + .weak UART4_IRQHandler + .thumb_set UART4_IRQHandler,Default_Handler + + .weak UART5_IRQHandler + .thumb_set UART5_IRQHandler,Default_Handler + + .weak TIM6_DAC_IRQHandler + .thumb_set TIM6_DAC_IRQHandler,Default_Handler + + .weak TIM7_IRQHandler + .thumb_set TIM7_IRQHandler,Default_Handler + + .weak DMA2_Channel1_IRQHandler + .thumb_set DMA2_Channel1_IRQHandler,Default_Handler + + .weak DMA2_Channel2_IRQHandler + .thumb_set DMA2_Channel2_IRQHandler,Default_Handler + + .weak DMA2_Channel3_IRQHandler + .thumb_set DMA2_Channel3_IRQHandler,Default_Handler + + .weak DMA2_Channel4_5_IRQHandler + .thumb_set DMA2_Channel4_5_IRQHandler,Default_Handler + + .weak DMA2_Channel5_IRQHandler + .thumb_set DMA2_Channel5_IRQHandler,Default_Handler + +/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ diff --git a/Libraries/CMSIS/Device/ST/STM32F10x/Source/Templates/gcc_ride7/startup_stm32f10x_ld.s b/Libraries/CMSIS/Device/ST/STM32F10x/Source/Templates/gcc_ride7/startup_stm32f10x_ld.s new file mode 100644 index 0000000..e370a4c --- /dev/null +++ b/Libraries/CMSIS/Device/ST/STM32F10x/Source/Templates/gcc_ride7/startup_stm32f10x_ld.s @@ -0,0 +1,349 @@ +/** + ****************************************************************************** + * @file startup_stm32f10x_ld.s + * @author MCD Application Team + * @version V3.6.1 + * @date 09-March-2012 + * @brief STM32F10x Low Density Devices vector table for RIDE7 toolchain. + * This module performs: + * - Set the initial SP + * - Set the initial PC == Reset_Handler, + * - Set the vector table entries with the exceptions ISR address + * - Configure the clock system + * - Branches to main in the C library (which eventually + * calls main()). + * After Reset the Cortex-M3 processor is in Thread mode, + * priority is Privileged, and the Stack is set to Main. + ****************************************************************************** + * @attention + * + *

© COPYRIGHT 2012 STMicroelectronics

+ * + * Licensed under MCD-ST Liberty SW License Agreement V2, (the "License"); + * You may not use this file except in compliance with the License. + * You may obtain a copy of the License at: + * + * http://www.st.com/software_license_agreement_liberty_v2 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, + * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + * + ****************************************************************************** + */ + + .syntax unified + .cpu cortex-m3 + .fpu softvfp + .thumb + +.global g_pfnVectors +.global Default_Handler + +/* start address for the initialization values of the .data section. +defined in linker script */ +.word _sidata +/* start address for the .data section. defined in linker script */ +.word _sdata +/* end address for the .data section. defined in linker script */ +.word _edata +/* start address for the .bss section. defined in linker script */ +.word _sbss +/* end address for the .bss section. defined in linker script */ +.word _ebss + +.equ BootRAM, 0xF108F85F +/** + * @brief This is the code that gets called when the processor first + * starts execution following a reset event. Only the absolutely + * necessary set is performed, after which the application + * supplied main() routine is called. + * @param None + * @retval : None +*/ + + .section .text.Reset_Handler + .weak Reset_Handler + .type Reset_Handler, %function +Reset_Handler: + +/* Copy the data segment initializers from flash to SRAM */ + movs r1, #0 + b LoopCopyDataInit + +CopyDataInit: + ldr r3, =_sidata + ldr r3, [r3, r1] + str r3, [r0, r1] + adds r1, r1, #4 + +LoopCopyDataInit: + ldr r0, =_sdata + ldr r3, =_edata + adds r2, r0, r1 + cmp r2, r3 + bcc CopyDataInit + ldr r2, =_sbss + b LoopFillZerobss +/* Zero fill the bss segment. */ +FillZerobss: + movs r3, #0 + str r3, [r2], #4 + +LoopFillZerobss: + ldr r3, = _ebss + cmp r2, r3 + bcc FillZerobss +/* Call the clock system intitialization function.*/ + bl SystemInit +/* Call the application's entry point.*/ + bl main + bx lr +.size Reset_Handler, .-Reset_Handler + +/** + * @brief This is the code that gets called when the processor receives an + * unexpected interrupt. This simply enters an infinite loop, preserving + * the system state for examination by a debugger. + * @param None + * @retval None +*/ + .section .text.Default_Handler,"ax",%progbits +Default_Handler: +Infinite_Loop: + b Infinite_Loop + .size Default_Handler, .-Default_Handler +/****************************************************************************** +* +* The minimal vector table for a Cortex M3. Note that the proper constructs +* must be placed on this to ensure that it ends up at physical address +* 0x0000.0000. +* +******************************************************************************/ + .section .isr_vector,"a",%progbits + .type g_pfnVectors, %object + .size g_pfnVectors, .-g_pfnVectors + + +g_pfnVectors: + .word _estack + .word Reset_Handler + .word NMI_Handler + .word HardFault_Handler + .word MemManage_Handler + .word BusFault_Handler + .word UsageFault_Handler + .word 0 + .word 0 + .word 0 + .word 0 + .word SVC_Handler + .word DebugMon_Handler + .word 0 + .word PendSV_Handler + .word SysTick_Handler + .word WWDG_IRQHandler + .word PVD_IRQHandler + .word TAMPER_IRQHandler + .word RTC_IRQHandler + .word FLASH_IRQHandler + .word RCC_IRQHandler + .word EXTI0_IRQHandler + .word EXTI1_IRQHandler + .word EXTI2_IRQHandler + .word EXTI3_IRQHandler + .word EXTI4_IRQHandler + .word DMA1_Channel1_IRQHandler + .word DMA1_Channel2_IRQHandler + .word DMA1_Channel3_IRQHandler + .word DMA1_Channel4_IRQHandler + .word DMA1_Channel5_IRQHandler + .word DMA1_Channel6_IRQHandler + .word DMA1_Channel7_IRQHandler + .word ADC1_2_IRQHandler + .word USB_HP_CAN1_TX_IRQHandler + .word USB_LP_CAN1_RX0_IRQHandler + .word CAN1_RX1_IRQHandler + .word CAN1_SCE_IRQHandler + .word EXTI9_5_IRQHandler + .word TIM1_BRK_IRQHandler + .word TIM1_UP_IRQHandler + .word TIM1_TRG_COM_IRQHandler + .word TIM1_CC_IRQHandler + .word TIM2_IRQHandler + .word TIM3_IRQHandler + .word 0 + .word I2C1_EV_IRQHandler + .word I2C1_ER_IRQHandler + .word 0 + .word 0 + .word SPI1_IRQHandler + .word 0 + .word USART1_IRQHandler + .word USART2_IRQHandler + .word 0 + .word EXTI15_10_IRQHandler + .word RTCAlarm_IRQHandler + .word USBWakeUp_IRQHandler + .word 0 + .word 0 + .word 0 + .word 0 + .word 0 + .word 0 + .word 0 + .word BootRAM /* @0x108. This is for boot in RAM mode for + STM32F10x Low Density devices.*/ + +/******************************************************************************* +* +* Provide weak aliases for each Exception handler to the Default_Handler. +* As they are weak aliases, any function with the same name will override +* this definition. +* +*******************************************************************************/ + + .weak NMI_Handler + .thumb_set NMI_Handler,Default_Handler + + .weak HardFault_Handler + .thumb_set HardFault_Handler,Default_Handler + + .weak MemManage_Handler + .thumb_set MemManage_Handler,Default_Handler + + .weak BusFault_Handler + .thumb_set BusFault_Handler,Default_Handler + + .weak UsageFault_Handler + .thumb_set UsageFault_Handler,Default_Handler + + .weak SVC_Handler + .thumb_set SVC_Handler,Default_Handler + + .weak DebugMon_Handler + .thumb_set DebugMon_Handler,Default_Handler + + .weak PendSV_Handler + .thumb_set PendSV_Handler,Default_Handler + + .weak SysTick_Handler + .thumb_set SysTick_Handler,Default_Handler + + .weak WWDG_IRQHandler + .thumb_set WWDG_IRQHandler,Default_Handler + + .weak PVD_IRQHandler + .thumb_set PVD_IRQHandler,Default_Handler + + .weak TAMPER_IRQHandler + .thumb_set TAMPER_IRQHandler,Default_Handler + + .weak RTC_IRQHandler + .thumb_set RTC_IRQHandler,Default_Handler + + .weak FLASH_IRQHandler + .thumb_set FLASH_IRQHandler,Default_Handler + + .weak RCC_IRQHandler + .thumb_set RCC_IRQHandler,Default_Handler + + .weak EXTI0_IRQHandler + .thumb_set EXTI0_IRQHandler,Default_Handler + + .weak EXTI1_IRQHandler + .thumb_set EXTI1_IRQHandler,Default_Handler + + .weak EXTI2_IRQHandler + .thumb_set EXTI2_IRQHandler,Default_Handler + + .weak EXTI3_IRQHandler + .thumb_set EXTI3_IRQHandler,Default_Handler + + .weak EXTI4_IRQHandler + .thumb_set EXTI4_IRQHandler,Default_Handler + + .weak DMA1_Channel1_IRQHandler + .thumb_set DMA1_Channel1_IRQHandler,Default_Handler + + .weak DMA1_Channel2_IRQHandler + .thumb_set DMA1_Channel2_IRQHandler,Default_Handler + + .weak DMA1_Channel3_IRQHandler + .thumb_set DMA1_Channel3_IRQHandler,Default_Handler + + .weak DMA1_Channel4_IRQHandler + .thumb_set DMA1_Channel4_IRQHandler,Default_Handler + + .weak DMA1_Channel5_IRQHandler + .thumb_set DMA1_Channel5_IRQHandler,Default_Handler + + .weak DMA1_Channel6_IRQHandler + .thumb_set DMA1_Channel6_IRQHandler,Default_Handler + + .weak DMA1_Channel7_IRQHandler + .thumb_set DMA1_Channel7_IRQHandler,Default_Handler + + .weak ADC1_2_IRQHandler + .thumb_set ADC1_2_IRQHandler,Default_Handler + + .weak USB_HP_CAN1_TX_IRQHandler + .thumb_set USB_HP_CAN1_TX_IRQHandler,Default_Handler + + .weak USB_LP_CAN1_RX0_IRQHandler + .thumb_set USB_LP_CAN1_RX0_IRQHandler,Default_Handler + + .weak CAN1_RX1_IRQHandler + .thumb_set CAN1_RX1_IRQHandler,Default_Handler + + .weak CAN1_SCE_IRQHandler + .thumb_set CAN1_SCE_IRQHandler,Default_Handler + + .weak EXTI9_5_IRQHandler + .thumb_set EXTI9_5_IRQHandler,Default_Handler + + .weak TIM1_BRK_IRQHandler + .thumb_set TIM1_BRK_IRQHandler,Default_Handler + + .weak TIM1_UP_IRQHandler + .thumb_set TIM1_UP_IRQHandler,Default_Handler + + .weak TIM1_TRG_COM_IRQHandler + .thumb_set TIM1_TRG_COM_IRQHandler,Default_Handler + + .weak TIM1_CC_IRQHandler + .thumb_set TIM1_CC_IRQHandler,Default_Handler + + .weak TIM2_IRQHandler + .thumb_set TIM2_IRQHandler,Default_Handler + + .weak TIM3_IRQHandler + .thumb_set TIM3_IRQHandler,Default_Handler + + .weak I2C1_EV_IRQHandler + .thumb_set I2C1_EV_IRQHandler,Default_Handler + + .weak I2C1_ER_IRQHandler + .thumb_set I2C1_ER_IRQHandler,Default_Handler + + .weak SPI1_IRQHandler + .thumb_set SPI1_IRQHandler,Default_Handler + + .weak USART1_IRQHandler + .thumb_set USART1_IRQHandler,Default_Handler + + .weak USART2_IRQHandler + .thumb_set USART2_IRQHandler,Default_Handler + + .weak EXTI15_10_IRQHandler + .thumb_set EXTI15_10_IRQHandler,Default_Handler + + .weak RTCAlarm_IRQHandler + .thumb_set RTCAlarm_IRQHandler,Default_Handler + + .weak USBWakeUp_IRQHandler + .thumb_set USBWakeUp_IRQHandler,Default_Handler + +/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ diff --git a/Libraries/CMSIS/Device/ST/STM32F10x/Source/Templates/gcc_ride7/startup_stm32f10x_ld_vl.s b/Libraries/CMSIS/Device/ST/STM32F10x/Source/Templates/gcc_ride7/startup_stm32f10x_ld_vl.s new file mode 100644 index 0000000..cba97a4 --- /dev/null +++ b/Libraries/CMSIS/Device/ST/STM32F10x/Source/Templates/gcc_ride7/startup_stm32f10x_ld_vl.s @@ -0,0 +1,389 @@ +/** + ****************************************************************************** + * @file startup_stm32f10x_ld_vl.s + * @author MCD Application Team + * @version V3.6.1 + * @date 09-March-2012 + * @brief STM32F10x Low Density Value Line Devices vector table for RIDE7 + * toolchain. + * This module performs: + * - Set the initial SP + * - Set the initial PC == Reset_Handler, + * - Set the vector table entries with the exceptions ISR address + * - Configure the clock system + * - Branches to main in the C library (which eventually + * calls main()). + * After Reset the Cortex-M3 processor is in Thread mode, + * priority is Privileged, and the Stack is set to Main. + ****************************************************************************** + * @attention + * + *

© COPYRIGHT 2012 STMicroelectronics

+ * + * Licensed under MCD-ST Liberty SW License Agreement V2, (the "License"); + * You may not use this file except in compliance with the License. + * You may obtain a copy of the License at: + * + * http://www.st.com/software_license_agreement_liberty_v2 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, + * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + * + ****************************************************************************** + */ + + .syntax unified + .cpu cortex-m3 + .fpu softvfp + .thumb + +.global g_pfnVectors +.global Default_Handler + +/* start address for the initialization values of the .data section. +defined in linker script */ +.word _sidata +/* start address for the .data section. defined in linker script */ +.word _sdata +/* end address for the .data section. defined in linker script */ +.word _edata +/* start address for the .bss section. defined in linker script */ +.word _sbss +/* end address for the .bss section. defined in linker script */ +.word _ebss + +.equ BootRAM, 0xF108F85F +/** + * @brief This is the code that gets called when the processor first + * starts execution following a reset event. Only the absolutely + * necessary set is performed, after which the application + * supplied main() routine is called. + * @param None + * @retval None +*/ + + .section .text.Reset_Handler + .weak Reset_Handler + .type Reset_Handler, %function +Reset_Handler: + +/* Copy the data segment initializers from flash to SRAM */ + movs r1, #0 + b LoopCopyDataInit + +CopyDataInit: + ldr r3, =_sidata + ldr r3, [r3, r1] + str r3, [r0, r1] + adds r1, r1, #4 + +LoopCopyDataInit: + ldr r0, =_sdata + ldr r3, =_edata + adds r2, r0, r1 + cmp r2, r3 + bcc CopyDataInit + ldr r2, =_sbss + b LoopFillZerobss +/* Zero fill the bss segment. */ +FillZerobss: + movs r3, #0 + str r3, [r2], #4 + +LoopFillZerobss: + ldr r3, = _ebss + cmp r2, r3 + bcc FillZerobss +/* Call the clock system intitialization function.*/ + bl SystemInit +/* Call the application's entry point.*/ + bl main + bx lr +.size Reset_Handler, .-Reset_Handler + +/** + * @brief This is the code that gets called when the processor receives an + * unexpected interrupt. This simply enters an infinite loop, preserving + * the system state for examination by a debugger. + * @param None + * @retval None +*/ + .section .text.Default_Handler,"ax",%progbits +Default_Handler: +Infinite_Loop: + b Infinite_Loop + .size Default_Handler, .-Default_Handler +/****************************************************************************** +* The minimal vector table for a Cortex M3. Note that the proper constructs +* must be placed on this to ensure that it ends up at physical address +* 0x0000.0000. +* +******************************************************************************/ + .section .isr_vector,"a",%progbits + .type g_pfnVectors, %object + .size g_pfnVectors, .-g_pfnVectors + +g_pfnVectors: + .word _estack + .word Reset_Handler + .word NMI_Handler + .word HardFault_Handler + .word MemManage_Handler + .word BusFault_Handler + .word UsageFault_Handler + .word 0 + .word 0 + .word 0 + .word 0 + .word SVC_Handler + .word DebugMon_Handler + .word 0 + .word PendSV_Handler + .word SysTick_Handler + .word WWDG_IRQHandler + .word PVD_IRQHandler + .word TAMPER_IRQHandler + .word RTC_IRQHandler + .word FLASH_IRQHandler + .word RCC_IRQHandler + .word EXTI0_IRQHandler + .word EXTI1_IRQHandler + .word EXTI2_IRQHandler + .word EXTI3_IRQHandler + .word EXTI4_IRQHandler + .word DMA1_Channel1_IRQHandler + .word DMA1_Channel2_IRQHandler + .word DMA1_Channel3_IRQHandler + .word DMA1_Channel4_IRQHandler + .word DMA1_Channel5_IRQHandler + .word DMA1_Channel6_IRQHandler + .word DMA1_Channel7_IRQHandler + .word ADC1_IRQHandler + .word 0 + .word 0 + .word 0 + .word 0 + .word EXTI9_5_IRQHandler + .word TIM1_BRK_TIM15_IRQHandler + .word TIM1_UP_TIM16_IRQHandler + .word TIM1_TRG_COM_TIM17_IRQHandler + .word TIM1_CC_IRQHandler + .word TIM2_IRQHandler + .word TIM3_IRQHandler + .word 0 + .word I2C1_EV_IRQHandler + .word I2C1_ER_IRQHandler + .word 0 + .word 0 + .word SPI1_IRQHandler + .word 0 + .word USART1_IRQHandler + .word USART2_IRQHandler + .word 0 + .word EXTI15_10_IRQHandler + .word RTCAlarm_IRQHandler + .word CEC_IRQHandler + .word 0 + .word 0 + .word 0 + .word 0 + .word 0 + .word 0 + .word 0 + .word 0 + .word 0 + .word 0 + .word 0 + .word TIM6_DAC_IRQHandler + .word TIM7_IRQHandler + .word 0 + .word 0 + .word 0 + .word 0 + .word 0 + .word 0 + .word 0 + .word 0 + .word 0 + .word 0 + .word 0 + .word 0 + .word 0 + .word 0 + .word 0 + .word 0 + .word 0 + .word 0 + .word 0 + .word 0 + .word 0 + .word 0 + .word 0 + .word 0 + .word 0 + .word 0 + .word 0 + .word 0 + .word 0 + .word 0 + .word 0 + .word 0 + .word 0 + .word 0 + .word 0 + .word 0 + .word 0 + .word 0 + .word 0 + .word 0 + .word 0 + .word 0 + .word 0 + .word BootRAM /* @0x01CC. This is for boot in RAM mode for + STM32F10x Low Density Value Line devices. */ + +/******************************************************************************* +* Provide weak aliases for each Exception handler to the Default_Handler. +* As they are weak aliases, any function with the same name will override +* this definition. +*******************************************************************************/ + + .weak NMI_Handler + .thumb_set NMI_Handler,Default_Handler + + .weak HardFault_Handler + .thumb_set HardFault_Handler,Default_Handler + + .weak MemManage_Handler + .thumb_set MemManage_Handler,Default_Handler + + .weak BusFault_Handler + .thumb_set BusFault_Handler,Default_Handler + + .weak UsageFault_Handler + .thumb_set UsageFault_Handler,Default_Handler + + .weak SVC_Handler + .thumb_set SVC_Handler,Default_Handler + + .weak DebugMon_Handler + .thumb_set DebugMon_Handler,Default_Handler + + .weak PendSV_Handler + .thumb_set PendSV_Handler,Default_Handler + + .weak SysTick_Handler + .thumb_set SysTick_Handler,Default_Handler + + .weak WWDG_IRQHandler + .thumb_set WWDG_IRQHandler,Default_Handler + + .weak PVD_IRQHandler + .thumb_set PVD_IRQHandler,Default_Handler + + .weak TAMPER_IRQHandler + .thumb_set TAMPER_IRQHandler,Default_Handler + + .weak RTC_IRQHandler + .thumb_set RTC_IRQHandler,Default_Handler + + .weak FLASH_IRQHandler + .thumb_set FLASH_IRQHandler,Default_Handler + + .weak RCC_IRQHandler + .thumb_set RCC_IRQHandler,Default_Handler + + .weak EXTI0_IRQHandler + .thumb_set EXTI0_IRQHandler,Default_Handler + + .weak EXTI1_IRQHandler + .thumb_set EXTI1_IRQHandler,Default_Handler + + .weak EXTI2_IRQHandler + .thumb_set EXTI2_IRQHandler,Default_Handler + + .weak EXTI3_IRQHandler + .thumb_set EXTI3_IRQHandler,Default_Handler + + .weak EXTI4_IRQHandler + .thumb_set EXTI4_IRQHandler,Default_Handler + + .weak DMA1_Channel1_IRQHandler + .thumb_set DMA1_Channel1_IRQHandler,Default_Handler + + .weak DMA1_Channel2_IRQHandler + .thumb_set DMA1_Channel2_IRQHandler,Default_Handler + + .weak DMA1_Channel3_IRQHandler + .thumb_set DMA1_Channel3_IRQHandler,Default_Handler + + .weak DMA1_Channel4_IRQHandler + .thumb_set DMA1_Channel4_IRQHandler,Default_Handler + + .weak DMA1_Channel5_IRQHandler + .thumb_set DMA1_Channel5_IRQHandler,Default_Handler + + .weak DMA1_Channel6_IRQHandler + .thumb_set DMA1_Channel6_IRQHandler,Default_Handler + + .weak DMA1_Channel7_IRQHandler + .thumb_set DMA1_Channel7_IRQHandler,Default_Handler + + .weak ADC1_IRQHandler + .thumb_set ADC1_IRQHandler,Default_Handler + + .weak EXTI9_5_IRQHandler + .thumb_set EXTI9_5_IRQHandler,Default_Handler + + .weak TIM1_BRK_TIM15_IRQHandler + .thumb_set TIM1_BRK_TIM15_IRQHandler,Default_Handler + + .weak TIM1_UP_TIM16_IRQHandler + .thumb_set TIM1_UP_TIM16_IRQHandler,Default_Handler + + .weak TIM1_TRG_COM_TIM17_IRQHandler + .thumb_set TIM1_TRG_COM_TIM17_IRQHandler,Default_Handler + + .weak TIM1_CC_IRQHandler + .thumb_set TIM1_CC_IRQHandler,Default_Handler + + .weak TIM2_IRQHandler + .thumb_set TIM2_IRQHandler,Default_Handler + + .weak TIM3_IRQHandler + .thumb_set TIM3_IRQHandler,Default_Handler + + .weak I2C1_EV_IRQHandler + .thumb_set I2C1_EV_IRQHandler,Default_Handler + + .weak I2C1_ER_IRQHandler + .thumb_set I2C1_ER_IRQHandler,Default_Handler + + .weak SPI1_IRQHandler + .thumb_set SPI1_IRQHandler,Default_Handler + + .weak USART1_IRQHandler + .thumb_set USART1_IRQHandler,Default_Handler + + .weak USART2_IRQHandler + .thumb_set USART2_IRQHandler,Default_Handler + + .weak EXTI15_10_IRQHandler + .thumb_set EXTI15_10_IRQHandler,Default_Handler + + .weak RTCAlarm_IRQHandler + .thumb_set RTCAlarm_IRQHandler,Default_Handler + + .weak CEC_IRQHandler + .thumb_set CEC_IRQHandler,Default_Handler + + .weak TIM6_DAC_IRQHandler + .thumb_set TIM6_DAC_IRQHandler,Default_Handler + + .weak TIM7_IRQHandler + .thumb_set TIM7_IRQHandler,Default_Handler + +/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ diff --git a/Libraries/CMSIS/Device/ST/STM32F10x/Source/Templates/gcc_ride7/startup_stm32f10x_md.s b/Libraries/CMSIS/Device/ST/STM32F10x/Source/Templates/gcc_ride7/startup_stm32f10x_md.s new file mode 100644 index 0000000..34c987d --- /dev/null +++ b/Libraries/CMSIS/Device/ST/STM32F10x/Source/Templates/gcc_ride7/startup_stm32f10x_md.s @@ -0,0 +1,364 @@ +/** + ****************************************************************************** + * @file startup_stm32f10x_md.s + * @author MCD Application Team + * @version V3.6.1 + * @date 09-March-2012 + * @brief STM32F10x Medium Density Devices vector table for RIDE7 toolchain. + * This module performs: + * - Set the initial SP + * - Set the initial PC == Reset_Handler, + * - Set the vector table entries with the exceptions ISR address + * - Configure the clock system + * - Branches to main in the C library (which eventually + * calls main()). + * After Reset the Cortex-M3 processor is in Thread mode, + * priority is Privileged, and the Stack is set to Main. + ****************************************************************************** + * @attention + * + *

© COPYRIGHT 2012 STMicroelectronics

+ * + * Licensed under MCD-ST Liberty SW License Agreement V2, (the "License"); + * You may not use this file except in compliance with the License. + * You may obtain a copy of the License at: + * + * http://www.st.com/software_license_agreement_liberty_v2 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, + * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + * + ****************************************************************************** + */ + + .syntax unified + .cpu cortex-m3 + .fpu softvfp + .thumb + +.global g_pfnVectors +.global Default_Handler + +/* start address for the initialization values of the .data section. +defined in linker script */ +.word _sidata +/* start address for the .data section. defined in linker script */ +.word _sdata +/* end address for the .data section. defined in linker script */ +.word _edata +/* start address for the .bss section. defined in linker script */ +.word _sbss +/* end address for the .bss section. defined in linker script */ +.word _ebss + +.equ BootRAM, 0xF108F85F +/** + * @brief This is the code that gets called when the processor first + * starts execution following a reset event. Only the absolutely + * necessary set is performed, after which the application + * supplied main() routine is called. + * @param None + * @retval : None +*/ + + .section .text.Reset_Handler + .weak Reset_Handler + .type Reset_Handler, %function +Reset_Handler: + +/* Copy the data segment initializers from flash to SRAM */ + movs r1, #0 + b LoopCopyDataInit + +CopyDataInit: + ldr r3, =_sidata + ldr r3, [r3, r1] + str r3, [r0, r1] + adds r1, r1, #4 + +LoopCopyDataInit: + ldr r0, =_sdata + ldr r3, =_edata + adds r2, r0, r1 + cmp r2, r3 + bcc CopyDataInit + ldr r2, =_sbss + b LoopFillZerobss +/* Zero fill the bss segment. */ +FillZerobss: + movs r3, #0 + str r3, [r2], #4 + +LoopFillZerobss: + ldr r3, = _ebss + cmp r2, r3 + bcc FillZerobss +/* Call the clock system intitialization function.*/ + bl SystemInit +/* Call the application's entry point.*/ + bl main + bx lr +.size Reset_Handler, .-Reset_Handler + +/** + * @brief This is the code that gets called when the processor receives an + * unexpected interrupt. This simply enters an infinite loop, preserving + * the system state for examination by a debugger. + * @param None + * @retval None +*/ + .section .text.Default_Handler,"ax",%progbits +Default_Handler: +Infinite_Loop: + b Infinite_Loop + .size Default_Handler, .-Default_Handler +/****************************************************************************** +* +* The minimal vector table for a Cortex M3. Note that the proper constructs +* must be placed on this to ensure that it ends up at physical address +* 0x0000.0000. +* +******************************************************************************/ + .section .isr_vector,"a",%progbits + .type g_pfnVectors, %object + .size g_pfnVectors, .-g_pfnVectors + + +g_pfnVectors: + .word _estack + .word Reset_Handler + .word NMI_Handler + .word HardFault_Handler + .word MemManage_Handler + .word BusFault_Handler + .word UsageFault_Handler + .word 0 + .word 0 + .word 0 + .word 0 + .word SVC_Handler + .word DebugMon_Handler + .word 0 + .word PendSV_Handler + .word SysTick_Handler + .word WWDG_IRQHandler + .word PVD_IRQHandler + .word TAMPER_IRQHandler + .word RTC_IRQHandler + .word FLASH_IRQHandler + .word RCC_IRQHandler + .word EXTI0_IRQHandler + .word EXTI1_IRQHandler + .word EXTI2_IRQHandler + .word EXTI3_IRQHandler + .word EXTI4_IRQHandler + .word DMA1_Channel1_IRQHandler + .word DMA1_Channel2_IRQHandler + .word DMA1_Channel3_IRQHandler + .word DMA1_Channel4_IRQHandler + .word DMA1_Channel5_IRQHandler + .word DMA1_Channel6_IRQHandler + .word DMA1_Channel7_IRQHandler + .word ADC1_2_IRQHandler + .word USB_HP_CAN1_TX_IRQHandler + .word USB_LP_CAN1_RX0_IRQHandler + .word CAN1_RX1_IRQHandler + .word CAN1_SCE_IRQHandler + .word EXTI9_5_IRQHandler + .word TIM1_BRK_IRQHandler + .word TIM1_UP_IRQHandler + .word TIM1_TRG_COM_IRQHandler + .word TIM1_CC_IRQHandler + .word TIM2_IRQHandler + .word TIM3_IRQHandler + .word TIM4_IRQHandler + .word I2C1_EV_IRQHandler + .word I2C1_ER_IRQHandler + .word I2C2_EV_IRQHandler + .word I2C2_ER_IRQHandler + .word SPI1_IRQHandler + .word SPI2_IRQHandler + .word USART1_IRQHandler + .word USART2_IRQHandler + .word USART3_IRQHandler + .word EXTI15_10_IRQHandler + .word RTCAlarm_IRQHandler + .word USBWakeUp_IRQHandler + .word 0 + .word 0 + .word 0 + .word 0 + .word 0 + .word 0 + .word 0 + .word BootRAM /* @0x108. This is for boot in RAM mode for + STM32F10x Medium Density devices. */ + +/******************************************************************************* +* +* Provide weak aliases for each Exception handler to the Default_Handler. +* As they are weak aliases, any function with the same name will override +* this definition. +* +*******************************************************************************/ + + .weak NMI_Handler + .thumb_set NMI_Handler,Default_Handler + + .weak HardFault_Handler + .thumb_set HardFault_Handler,Default_Handler + + .weak MemManage_Handler + .thumb_set MemManage_Handler,Default_Handler + + .weak BusFault_Handler + .thumb_set BusFault_Handler,Default_Handler + + .weak UsageFault_Handler + .thumb_set UsageFault_Handler,Default_Handler + + .weak SVC_Handler + .thumb_set SVC_Handler,Default_Handler + + .weak DebugMon_Handler + .thumb_set DebugMon_Handler,Default_Handler + + .weak PendSV_Handler + .thumb_set PendSV_Handler,Default_Handler + + .weak SysTick_Handler + .thumb_set SysTick_Handler,Default_Handler + + .weak WWDG_IRQHandler + .thumb_set WWDG_IRQHandler,Default_Handler + + .weak PVD_IRQHandler + .thumb_set PVD_IRQHandler,Default_Handler + + .weak TAMPER_IRQHandler + .thumb_set TAMPER_IRQHandler,Default_Handler + + .weak RTC_IRQHandler + .thumb_set RTC_IRQHandler,Default_Handler + + .weak FLASH_IRQHandler + .thumb_set FLASH_IRQHandler,Default_Handler + + .weak RCC_IRQHandler + .thumb_set RCC_IRQHandler,Default_Handler + + .weak EXTI0_IRQHandler + .thumb_set EXTI0_IRQHandler,Default_Handler + + .weak EXTI1_IRQHandler + .thumb_set EXTI1_IRQHandler,Default_Handler + + .weak EXTI2_IRQHandler + .thumb_set EXTI2_IRQHandler,Default_Handler + + .weak EXTI3_IRQHandler + .thumb_set EXTI3_IRQHandler,Default_Handler + + .weak EXTI4_IRQHandler + .thumb_set EXTI4_IRQHandler,Default_Handler + + .weak DMA1_Channel1_IRQHandler + .thumb_set DMA1_Channel1_IRQHandler,Default_Handler + + .weak DMA1_Channel2_IRQHandler + .thumb_set DMA1_Channel2_IRQHandler,Default_Handler + + .weak DMA1_Channel3_IRQHandler + .thumb_set DMA1_Channel3_IRQHandler,Default_Handler + + .weak DMA1_Channel4_IRQHandler + .thumb_set DMA1_Channel4_IRQHandler,Default_Handler + + .weak DMA1_Channel5_IRQHandler + .thumb_set DMA1_Channel5_IRQHandler,Default_Handler + + .weak DMA1_Channel6_IRQHandler + .thumb_set DMA1_Channel6_IRQHandler,Default_Handler + + .weak DMA1_Channel7_IRQHandler + .thumb_set DMA1_Channel7_IRQHandler,Default_Handler + + .weak ADC1_2_IRQHandler + .thumb_set ADC1_2_IRQHandler,Default_Handler + + .weak USB_HP_CAN1_TX_IRQHandler + .thumb_set USB_HP_CAN1_TX_IRQHandler,Default_Handler + + .weak USB_LP_CAN1_RX0_IRQHandler + .thumb_set USB_LP_CAN1_RX0_IRQHandler,Default_Handler + + .weak CAN1_RX1_IRQHandler + .thumb_set CAN1_RX1_IRQHandler,Default_Handler + + .weak CAN1_SCE_IRQHandler + .thumb_set CAN1_SCE_IRQHandler,Default_Handler + + .weak EXTI9_5_IRQHandler + .thumb_set EXTI9_5_IRQHandler,Default_Handler + + .weak TIM1_BRK_IRQHandler + .thumb_set TIM1_BRK_IRQHandler,Default_Handler + + .weak TIM1_UP_IRQHandler + .thumb_set TIM1_UP_IRQHandler,Default_Handler + + .weak TIM1_TRG_COM_IRQHandler + .thumb_set TIM1_TRG_COM_IRQHandler,Default_Handler + + .weak TIM1_CC_IRQHandler + .thumb_set TIM1_CC_IRQHandler,Default_Handler + + .weak TIM2_IRQHandler + .thumb_set TIM2_IRQHandler,Default_Handler + + .weak TIM3_IRQHandler + .thumb_set TIM3_IRQHandler,Default_Handler + + .weak TIM4_IRQHandler + .thumb_set TIM4_IRQHandler,Default_Handler + + .weak I2C1_EV_IRQHandler + .thumb_set I2C1_EV_IRQHandler,Default_Handler + + .weak I2C1_ER_IRQHandler + .thumb_set I2C1_ER_IRQHandler,Default_Handler + + .weak I2C2_EV_IRQHandler + .thumb_set I2C2_EV_IRQHandler,Default_Handler + + .weak I2C2_ER_IRQHandler + .thumb_set I2C2_ER_IRQHandler,Default_Handler + + .weak SPI1_IRQHandler + .thumb_set SPI1_IRQHandler,Default_Handler + + .weak SPI2_IRQHandler + .thumb_set SPI2_IRQHandler,Default_Handler + + .weak USART1_IRQHandler + .thumb_set USART1_IRQHandler,Default_Handler + + .weak USART2_IRQHandler + .thumb_set USART2_IRQHandler,Default_Handler + + .weak USART3_IRQHandler + .thumb_set USART3_IRQHandler,Default_Handler + + .weak EXTI15_10_IRQHandler + .thumb_set EXTI15_10_IRQHandler,Default_Handler + + .weak RTCAlarm_IRQHandler + .thumb_set RTCAlarm_IRQHandler,Default_Handler + + .weak USBWakeUp_IRQHandler + .thumb_set USBWakeUp_IRQHandler,Default_Handler + +/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ diff --git a/Libraries/CMSIS/Device/ST/STM32F10x/Source/Templates/gcc_ride7/startup_stm32f10x_md_vl.s b/Libraries/CMSIS/Device/ST/STM32F10x/Source/Templates/gcc_ride7/startup_stm32f10x_md_vl.s new file mode 100644 index 0000000..896bb79 --- /dev/null +++ b/Libraries/CMSIS/Device/ST/STM32F10x/Source/Templates/gcc_ride7/startup_stm32f10x_md_vl.s @@ -0,0 +1,405 @@ +/** + ****************************************************************************** + * @file startup_stm32f10x_md_vl.s + * @author MCD Application Team + * @version V3.6.1 + * @date 09-March-2012 + * @brief STM32F10x Medium Density Value Line Devices vector table for RIDE7 + * toolchain. + * This module performs: + * - Set the initial SP + * - Set the initial PC == Reset_Handler, + * - Set the vector table entries with the exceptions ISR address + * - Configure the clock system + * - Branches to main in the C library (which eventually + * calls main()). + * After Reset the Cortex-M3 processor is in Thread mode, + * priority is Privileged, and the Stack is set to Main. + ****************************************************************************** + * @attention + * + *

© COPYRIGHT 2012 STMicroelectronics

+ * + * Licensed under MCD-ST Liberty SW License Agreement V2, (the "License"); + * You may not use this file except in compliance with the License. + * You may obtain a copy of the License at: + * + * http://www.st.com/software_license_agreement_liberty_v2 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, + * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + * + ****************************************************************************** + */ + + .syntax unified + .cpu cortex-m3 + .fpu softvfp + .thumb + +.global g_pfnVectors +.global Default_Handler + +/* start address for the initialization values of the .data section. +defined in linker script */ +.word _sidata +/* start address for the .data section. defined in linker script */ +.word _sdata +/* end address for the .data section. defined in linker script */ +.word _edata +/* start address for the .bss section. defined in linker script */ +.word _sbss +/* end address for the .bss section. defined in linker script */ +.word _ebss + +.equ BootRAM, 0xF108F85F +/** + * @brief This is the code that gets called when the processor first + * starts execution following a reset event. Only the absolutely + * necessary set is performed, after which the application + * supplied main() routine is called. + * @param None + * @retval None +*/ + + .section .text.Reset_Handler + .weak Reset_Handler + .type Reset_Handler, %function +Reset_Handler: + +/* Copy the data segment initializers from flash to SRAM */ + movs r1, #0 + b LoopCopyDataInit + +CopyDataInit: + ldr r3, =_sidata + ldr r3, [r3, r1] + str r3, [r0, r1] + adds r1, r1, #4 + +LoopCopyDataInit: + ldr r0, =_sdata + ldr r3, =_edata + adds r2, r0, r1 + cmp r2, r3 + bcc CopyDataInit + ldr r2, =_sbss + b LoopFillZerobss +/* Zero fill the bss segment. */ +FillZerobss: + movs r3, #0 + str r3, [r2], #4 + +LoopFillZerobss: + ldr r3, = _ebss + cmp r2, r3 + bcc FillZerobss +/* Call the clock system intitialization function.*/ + bl SystemInit +/* Call the application's entry point.*/ + bl main + bx lr +.size Reset_Handler, .-Reset_Handler + +/** + * @brief This is the code that gets called when the processor receives an + * unexpected interrupt. This simply enters an infinite loop, preserving + * the system state for examination by a debugger. + * @param None + * @retval None +*/ + .section .text.Default_Handler,"ax",%progbits +Default_Handler: +Infinite_Loop: + b Infinite_Loop + .size Default_Handler, .-Default_Handler +/****************************************************************************** +* +* The minimal vector table for a Cortex M3. Note that the proper constructs +* must be placed on this to ensure that it ends up at physical address +* 0x0000.0000. +* +******************************************************************************/ + .section .isr_vector,"a",%progbits + .type g_pfnVectors, %object + .size g_pfnVectors, .-g_pfnVectors + +g_pfnVectors: + .word _estack + .word Reset_Handler + .word NMI_Handler + .word HardFault_Handler + .word MemManage_Handler + .word BusFault_Handler + .word UsageFault_Handler + .word 0 + .word 0 + .word 0 + .word 0 + .word SVC_Handler + .word DebugMon_Handler + .word 0 + .word PendSV_Handler + .word SysTick_Handler + .word WWDG_IRQHandler + .word PVD_IRQHandler + .word TAMPER_IRQHandler + .word RTC_IRQHandler + .word FLASH_IRQHandler + .word RCC_IRQHandler + .word EXTI0_IRQHandler + .word EXTI1_IRQHandler + .word EXTI2_IRQHandler + .word EXTI3_IRQHandler + .word EXTI4_IRQHandler + .word DMA1_Channel1_IRQHandler + .word DMA1_Channel2_IRQHandler + .word DMA1_Channel3_IRQHandler + .word DMA1_Channel4_IRQHandler + .word DMA1_Channel5_IRQHandler + .word DMA1_Channel6_IRQHandler + .word DMA1_Channel7_IRQHandler + .word ADC1_IRQHandler + .word 0 + .word 0 + .word 0 + .word 0 + .word EXTI9_5_IRQHandler + .word TIM1_BRK_TIM15_IRQHandler + .word TIM1_UP_TIM16_IRQHandler + .word TIM1_TRG_COM_TIM17_IRQHandler + .word TIM1_CC_IRQHandler + .word TIM2_IRQHandler + .word TIM3_IRQHandler + .word TIM4_IRQHandler + .word I2C1_EV_IRQHandler + .word I2C1_ER_IRQHandler + .word I2C2_EV_IRQHandler + .word I2C2_ER_IRQHandler + .word SPI1_IRQHandler + .word SPI2_IRQHandler + .word USART1_IRQHandler + .word USART2_IRQHandler + .word USART3_IRQHandler + .word EXTI15_10_IRQHandler + .word RTCAlarm_IRQHandler + .word CEC_IRQHandler + .word 0 + .word 0 + .word 0 + .word 0 + .word 0 + .word 0 + .word 0 + .word 0 + .word 0 + .word 0 + .word 0 + .word TIM6_DAC_IRQHandler + .word TIM7_IRQHandler + .word 0 + .word 0 + .word 0 + .word 0 + .word 0 + .word 0 + .word 0 + .word 0 + .word 0 + .word 0 + .word 0 + .word 0 + .word 0 + .word 0 + .word 0 + .word 0 + .word 0 + .word 0 + .word 0 + .word 0 + .word 0 + .word 0 + .word 0 + .word 0 + .word 0 + .word 0 + .word 0 + .word 0 + .word 0 + .word 0 + .word 0 + .word 0 + .word 0 + .word 0 + .word 0 + .word 0 + .word 0 + .word 0 + .word 0 + .word 0 + .word 0 + .word 0 + .word 0 + .word BootRAM /* @0x01CC. This is for boot in RAM mode for + STM32F10x Medium Value Line Density devices. */ + +/******************************************************************************* +* Provide weak aliases for each Exception handler to the Default_Handler. +* As they are weak aliases, any function with the same name will override +* this definition. +*******************************************************************************/ + + .weak NMI_Handler + .thumb_set NMI_Handler,Default_Handler + + .weak HardFault_Handler + .thumb_set HardFault_Handler,Default_Handler + + .weak MemManage_Handler + .thumb_set MemManage_Handler,Default_Handler + + .weak BusFault_Handler + .thumb_set BusFault_Handler,Default_Handler + + .weak UsageFault_Handler + .thumb_set UsageFault_Handler,Default_Handler + + .weak SVC_Handler + .thumb_set SVC_Handler,Default_Handler + + .weak DebugMon_Handler + .thumb_set DebugMon_Handler,Default_Handler + + .weak PendSV_Handler + .thumb_set PendSV_Handler,Default_Handler + + .weak SysTick_Handler + .thumb_set SysTick_Handler,Default_Handler + + .weak WWDG_IRQHandler + .thumb_set WWDG_IRQHandler,Default_Handler + + .weak PVD_IRQHandler + .thumb_set PVD_IRQHandler,Default_Handler + + .weak TAMPER_IRQHandler + .thumb_set TAMPER_IRQHandler,Default_Handler + + .weak RTC_IRQHandler + .thumb_set RTC_IRQHandler,Default_Handler + + .weak FLASH_IRQHandler + .thumb_set FLASH_IRQHandler,Default_Handler + + .weak RCC_IRQHandler + .thumb_set RCC_IRQHandler,Default_Handler + + .weak EXTI0_IRQHandler + .thumb_set EXTI0_IRQHandler,Default_Handler + + .weak EXTI1_IRQHandler + .thumb_set EXTI1_IRQHandler,Default_Handler + + .weak EXTI2_IRQHandler + .thumb_set EXTI2_IRQHandler,Default_Handler + + .weak EXTI3_IRQHandler + .thumb_set EXTI3_IRQHandler,Default_Handler + + .weak EXTI4_IRQHandler + .thumb_set EXTI4_IRQHandler,Default_Handler + + .weak DMA1_Channel1_IRQHandler + .thumb_set DMA1_Channel1_IRQHandler,Default_Handler + + .weak DMA1_Channel2_IRQHandler + .thumb_set DMA1_Channel2_IRQHandler,Default_Handler + + .weak DMA1_Channel3_IRQHandler + .thumb_set DMA1_Channel3_IRQHandler,Default_Handler + + .weak DMA1_Channel4_IRQHandler + .thumb_set DMA1_Channel4_IRQHandler,Default_Handler + + .weak DMA1_Channel5_IRQHandler + .thumb_set DMA1_Channel5_IRQHandler,Default_Handler + + .weak DMA1_Channel6_IRQHandler + .thumb_set DMA1_Channel6_IRQHandler,Default_Handler + + .weak DMA1_Channel7_IRQHandler + .thumb_set DMA1_Channel7_IRQHandler,Default_Handler + + .weak ADC1_IRQHandler + .thumb_set ADC1_IRQHandler,Default_Handler + + .weak EXTI9_5_IRQHandler + .thumb_set EXTI9_5_IRQHandler,Default_Handler + + .weak TIM1_BRK_TIM15_IRQHandler + .thumb_set TIM1_BRK_TIM15_IRQHandler,Default_Handler + + .weak TIM1_UP_TIM16_IRQHandler + .thumb_set TIM1_UP_TIM16_IRQHandler,Default_Handler + + .weak TIM1_TRG_COM_TIM17_IRQHandler + .thumb_set TIM1_TRG_COM_TIM17_IRQHandler,Default_Handler + + .weak TIM1_CC_IRQHandler + .thumb_set TIM1_CC_IRQHandler,Default_Handler + + .weak TIM2_IRQHandler + .thumb_set TIM2_IRQHandler,Default_Handler + + .weak TIM3_IRQHandler + .thumb_set TIM3_IRQHandler,Default_Handler + + .weak TIM4_IRQHandler + .thumb_set TIM4_IRQHandler,Default_Handler + + .weak I2C1_EV_IRQHandler + .thumb_set I2C1_EV_IRQHandler,Default_Handler + + .weak I2C1_ER_IRQHandler + .thumb_set I2C1_ER_IRQHandler,Default_Handler + + .weak I2C2_EV_IRQHandler + .thumb_set I2C2_EV_IRQHandler,Default_Handler + + .weak I2C2_ER_IRQHandler + .thumb_set I2C2_ER_IRQHandler,Default_Handler + + .weak SPI1_IRQHandler + .thumb_set SPI1_IRQHandler,Default_Handler + + .weak SPI2_IRQHandler + .thumb_set SPI2_IRQHandler,Default_Handler + + .weak USART1_IRQHandler + .thumb_set USART1_IRQHandler,Default_Handler + + .weak USART2_IRQHandler + .thumb_set USART2_IRQHandler,Default_Handler + + .weak USART3_IRQHandler + .thumb_set USART3_IRQHandler,Default_Handler + + .weak EXTI15_10_IRQHandler + .thumb_set EXTI15_10_IRQHandler,Default_Handler + + .weak RTCAlarm_IRQHandler + .thumb_set RTCAlarm_IRQHandler,Default_Handler + + .weak CEC_IRQHandler + .thumb_set CEC_IRQHandler,Default_Handler + + .weak TIM6_DAC_IRQHandler + .thumb_set TIM6_DAC_IRQHandler,Default_Handler + + .weak TIM7_IRQHandler + .thumb_set TIM7_IRQHandler,Default_Handler + +/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ diff --git a/Libraries/CMSIS/Device/ST/STM32F10x/Source/Templates/gcc_ride7/startup_stm32f10x_xl.s b/Libraries/CMSIS/Device/ST/STM32F10x/Source/Templates/gcc_ride7/startup_stm32f10x_xl.s new file mode 100644 index 0000000..a0fa498 --- /dev/null +++ b/Libraries/CMSIS/Device/ST/STM32F10x/Source/Templates/gcc_ride7/startup_stm32f10x_xl.s @@ -0,0 +1,471 @@ +/** + ****************************************************************************** + * @file startup_stm32f10x_xl.s + * @author MCD Application Team + * @version V3.6.1 + * @date 09-March-2012 + * @brief STM32F10x XL-Density Devices vector table for RIDE7 toolchain. + * This module performs: + * - Set the initial SP + * - Set the initial PC == Reset_Handler, + * - Set the vector table entries with the exceptions ISR address + * - Configure the clock system and the external SRAM mounted on + * STM3210E-EVAL board to be used as data memory (optional, + * to be enabled by user) + * - Branches to main in the C library (which eventually + * calls main()). + * After Reset the Cortex-M3 processor is in Thread mode, + * priority is Privileged, and the Stack is set to Main. + ****************************************************************************** + * @attention + * + *

© COPYRIGHT 2012 STMicroelectronics

+ * + * Licensed under MCD-ST Liberty SW License Agreement V2, (the "License"); + * You may not use this file except in compliance with the License. + * You may obtain a copy of the License at: + * + * http://www.st.com/software_license_agreement_liberty_v2 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, + * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + * + ****************************************************************************** + */ + + .syntax unified + .cpu cortex-m3 + .fpu softvfp + .thumb + +.global g_pfnVectors +.global Default_Handler + +/* start address for the initialization values of the .data section. +defined in linker script */ +.word _sidata +/* start address for the .data section. defined in linker script */ +.word _sdata +/* end address for the .data section. defined in linker script */ +.word _edata +/* start address for the .bss section. defined in linker script */ +.word _sbss +/* end address for the .bss section. defined in linker script */ +.word _ebss +/* stack used for SystemInit_ExtMemCtl; always internal RAM used */ + +.equ BootRAM, 0xF1E0F85F +/** + * @brief This is the code that gets called when the processor first + * starts execution following a reset event. Only the absolutely + * necessary set is performed, after which the application + * supplied main() routine is called. + * @param None + * @retval : None +*/ + + .section .text.Reset_Handler + .weak Reset_Handler + .type Reset_Handler, %function +Reset_Handler: + +/* Copy the data segment initializers from flash to SRAM */ + movs r1, #0 + b LoopCopyDataInit + +CopyDataInit: + ldr r3, =_sidata + ldr r3, [r3, r1] + str r3, [r0, r1] + adds r1, r1, #4 + +LoopCopyDataInit: + ldr r0, =_sdata + ldr r3, =_edata + adds r2, r0, r1 + cmp r2, r3 + bcc CopyDataInit + ldr r2, =_sbss + b LoopFillZerobss +/* Zero fill the bss segment. */ +FillZerobss: + movs r3, #0 + str r3, [r2], #4 + +LoopFillZerobss: + ldr r3, = _ebss + cmp r2, r3 + bcc FillZerobss +/* Call the clock system intitialization function.*/ + bl SystemInit +/* Call the application's entry point.*/ + bl main + bx lr +.size Reset_Handler, .-Reset_Handler + +/** + * @brief This is the code that gets called when the processor receives an + * unexpected interrupt. This simply enters an infinite loop, preserving + * the system state for examination by a debugger. + * @param None + * @retval None +*/ + .section .text.Default_Handler,"ax",%progbits +Default_Handler: +Infinite_Loop: + b Infinite_Loop + .size Default_Handler, .-Default_Handler +/****************************************************************************** +* +* The minimal vector table for a Cortex M3. Note that the proper constructs +* must be placed on this to ensure that it ends up at physical address +* 0x0000.0000. +* +*******************************************************************************/ + .section .isr_vector,"a",%progbits + .type g_pfnVectors, %object + .size g_pfnVectors, .-g_pfnVectors + + +g_pfnVectors: + .word _estack + .word Reset_Handler + .word NMI_Handler + .word HardFault_Handler + .word MemManage_Handler + .word BusFault_Handler + .word UsageFault_Handler + .word 0 + .word 0 + .word 0 + .word 0 + .word SVC_Handler + .word DebugMon_Handler + .word 0 + .word PendSV_Handler + .word SysTick_Handler + .word WWDG_IRQHandler + .word PVD_IRQHandler + .word TAMPER_IRQHandler + .word RTC_IRQHandler + .word FLASH_IRQHandler + .word RCC_IRQHandler + .word EXTI0_IRQHandler + .word EXTI1_IRQHandler + .word EXTI2_IRQHandler + .word EXTI3_IRQHandler + .word EXTI4_IRQHandler + .word DMA1_Channel1_IRQHandler + .word DMA1_Channel2_IRQHandler + .word DMA1_Channel3_IRQHandler + .word DMA1_Channel4_IRQHandler + .word DMA1_Channel5_IRQHandler + .word DMA1_Channel6_IRQHandler + .word DMA1_Channel7_IRQHandler + .word ADC1_2_IRQHandler + .word USB_HP_CAN1_TX_IRQHandler + .word USB_LP_CAN1_RX0_IRQHandler + .word CAN1_RX1_IRQHandler + .word CAN1_SCE_IRQHandler + .word EXTI9_5_IRQHandler + .word TIM1_BRK_TIM9_IRQHandler + .word TIM1_UP_TIM10_IRQHandler + .word TIM1_TRG_COM_TIM11_IRQHandler + .word TIM1_CC_IRQHandler + .word TIM2_IRQHandler + .word TIM3_IRQHandler + .word TIM4_IRQHandler + .word I2C1_EV_IRQHandler + .word I2C1_ER_IRQHandler + .word I2C2_EV_IRQHandler + .word I2C2_ER_IRQHandler + .word SPI1_IRQHandler + .word SPI2_IRQHandler + .word USART1_IRQHandler + .word USART2_IRQHandler + .word USART3_IRQHandler + .word EXTI15_10_IRQHandler + .word RTCAlarm_IRQHandler + .word USBWakeUp_IRQHandler + .word TIM8_BRK_TIM12_IRQHandler + .word TIM8_UP_TIM13_IRQHandler + .word TIM8_TRG_COM_TIM14_IRQHandler + .word TIM8_CC_IRQHandler + .word ADC3_IRQHandler + .word FSMC_IRQHandler + .word SDIO_IRQHandler + .word TIM5_IRQHandler + .word SPI3_IRQHandler + .word UART4_IRQHandler + .word UART5_IRQHandler + .word TIM6_IRQHandler + .word TIM7_IRQHandler + .word DMA2_Channel1_IRQHandler + .word DMA2_Channel2_IRQHandler + .word DMA2_Channel3_IRQHandler + .word DMA2_Channel4_5_IRQHandler + .word 0 + .word 0 + .word 0 + .word 0 + .word 0 + .word 0 + .word 0 + .word 0 + .word 0 + .word 0 + .word 0 + .word 0 + .word 0 + .word 0 + .word 0 + .word 0 + .word 0 + .word 0 + .word 0 + .word 0 + .word 0 + .word 0 + .word 0 + .word 0 + .word 0 + .word 0 + .word 0 + .word 0 + .word 0 + .word 0 + .word 0 + .word 0 + .word 0 + .word 0 + .word 0 + .word 0 + .word 0 + .word 0 + .word 0 + .word 0 + .word 0 + .word 0 + .word 0 + .word 0 + .word BootRAM /* @0x1E0. This is for boot in RAM mode for + STM32F10x XL Density devices. */ +/******************************************************************************* +* +* Provide weak aliases for each Exception handler to the Default_Handler. +* As they are weak aliases, any function with the same name will override +* this definition. +* +*******************************************************************************/ + + .weak NMI_Handler + .thumb_set NMI_Handler,Default_Handler + + .weak HardFault_Handler + .thumb_set HardFault_Handler,Default_Handler + + .weak MemManage_Handler + .thumb_set MemManage_Handler,Default_Handler + + .weak BusFault_Handler + .thumb_set BusFault_Handler,Default_Handler + + .weak UsageFault_Handler + .thumb_set UsageFault_Handler,Default_Handler + + .weak SVC_Handler + .thumb_set SVC_Handler,Default_Handler + + .weak DebugMon_Handler + .thumb_set DebugMon_Handler,Default_Handler + + .weak PendSV_Handler + .thumb_set PendSV_Handler,Default_Handler + + .weak SysTick_Handler + .thumb_set SysTick_Handler,Default_Handler + + .weak WWDG_IRQHandler + .thumb_set WWDG_IRQHandler,Default_Handler + + .weak PVD_IRQHandler + .thumb_set PVD_IRQHandler,Default_Handler + + .weak TAMPER_IRQHandler + .thumb_set TAMPER_IRQHandler,Default_Handler + + .weak RTC_IRQHandler + .thumb_set RTC_IRQHandler,Default_Handler + + .weak FLASH_IRQHandler + .thumb_set FLASH_IRQHandler,Default_Handler + + .weak RCC_IRQHandler + .thumb_set RCC_IRQHandler,Default_Handler + + .weak EXTI0_IRQHandler + .thumb_set EXTI0_IRQHandler,Default_Handler + + .weak EXTI1_IRQHandler + .thumb_set EXTI1_IRQHandler,Default_Handler + + .weak EXTI2_IRQHandler + .thumb_set EXTI2_IRQHandler,Default_Handler + + .weak EXTI3_IRQHandler + .thumb_set EXTI3_IRQHandler,Default_Handler + + .weak EXTI4_IRQHandler + .thumb_set EXTI4_IRQHandler,Default_Handler + + .weak DMA1_Channel1_IRQHandler + .thumb_set DMA1_Channel1_IRQHandler,Default_Handler + + .weak DMA1_Channel2_IRQHandler + .thumb_set DMA1_Channel2_IRQHandler,Default_Handler + + .weak DMA1_Channel3_IRQHandler + .thumb_set DMA1_Channel3_IRQHandler,Default_Handler + + .weak DMA1_Channel4_IRQHandler + .thumb_set DMA1_Channel4_IRQHandler,Default_Handler + + .weak DMA1_Channel5_IRQHandler + .thumb_set DMA1_Channel5_IRQHandler,Default_Handler + + .weak DMA1_Channel6_IRQHandler + .thumb_set DMA1_Channel6_IRQHandler,Default_Handler + + .weak DMA1_Channel7_IRQHandler + .thumb_set DMA1_Channel7_IRQHandler,Default_Handler + + .weak ADC1_2_IRQHandler + .thumb_set ADC1_2_IRQHandler,Default_Handler + + .weak USB_HP_CAN1_TX_IRQHandler + .thumb_set USB_HP_CAN1_TX_IRQHandler,Default_Handler + + .weak USB_LP_CAN1_RX0_IRQHandler + .thumb_set USB_LP_CAN1_RX0_IRQHandler,Default_Handler + + .weak CAN1_RX1_IRQHandler + .thumb_set CAN1_RX1_IRQHandler,Default_Handler + + .weak CAN1_SCE_IRQHandler + .thumb_set CAN1_SCE_IRQHandler,Default_Handler + + .weak EXTI9_5_IRQHandler + .thumb_set EXTI9_5_IRQHandler,Default_Handler + + .weak TIM1_BRK_TIM9_IRQHandler + .thumb_set TIM1_BRK_TIM9_IRQHandler,Default_Handler + + .weak TIM1_UP_TIM10_IRQHandler + .thumb_set TIM1_UP_TIM10_IRQHandler,Default_Handler + + .weak TIM1_TRG_COM_TIM11_IRQHandler + .thumb_set TIM1_TRG_COM_TIM11_IRQHandler,Default_Handler + + .weak TIM1_CC_IRQHandler + .thumb_set TIM1_CC_IRQHandler,Default_Handler + + .weak TIM2_IRQHandler + .thumb_set TIM2_IRQHandler,Default_Handler + + .weak TIM3_IRQHandler + .thumb_set TIM3_IRQHandler,Default_Handler + + .weak TIM4_IRQHandler + .thumb_set TIM4_IRQHandler,Default_Handler + + .weak I2C1_EV_IRQHandler + .thumb_set I2C1_EV_IRQHandler,Default_Handler + + .weak I2C1_ER_IRQHandler + .thumb_set I2C1_ER_IRQHandler,Default_Handler + + .weak I2C2_EV_IRQHandler + .thumb_set I2C2_EV_IRQHandler,Default_Handler + + .weak I2C2_ER_IRQHandler + .thumb_set I2C2_ER_IRQHandler,Default_Handler + + .weak SPI1_IRQHandler + .thumb_set SPI1_IRQHandler,Default_Handler + + .weak SPI2_IRQHandler + .thumb_set SPI2_IRQHandler,Default_Handler + + .weak USART1_IRQHandler + .thumb_set USART1_IRQHandler,Default_Handler + + .weak USART2_IRQHandler + .thumb_set USART2_IRQHandler,Default_Handler + + .weak USART3_IRQHandler + .thumb_set USART3_IRQHandler,Default_Handler + + .weak EXTI15_10_IRQHandler + .thumb_set EXTI15_10_IRQHandler,Default_Handler + + .weak RTCAlarm_IRQHandler + .thumb_set RTCAlarm_IRQHandler,Default_Handler + + .weak USBWakeUp_IRQHandler + .thumb_set USBWakeUp_IRQHandler,Default_Handler + + .weak TIM8_BRK_TIM12_IRQHandler + .thumb_set TIM8_BRK_TIM12_IRQHandler,Default_Handler + + .weak TIM8_UP_TIM13_IRQHandler + .thumb_set TIM8_UP_TIM13_IRQHandler,Default_Handler + + .weak TIM8_TRG_COM_TIM14_IRQHandler + .thumb_set TIM8_TRG_COM_TIM14_IRQHandler,Default_Handler + + .weak TIM8_CC_IRQHandler + .thumb_set TIM8_CC_IRQHandler,Default_Handler + + .weak ADC3_IRQHandler + .thumb_set ADC3_IRQHandler,Default_Handler + + .weak FSMC_IRQHandler + .thumb_set FSMC_IRQHandler,Default_Handler + + .weak SDIO_IRQHandler + .thumb_set SDIO_IRQHandler,Default_Handler + + .weak TIM5_IRQHandler + .thumb_set TIM5_IRQHandler,Default_Handler + + .weak SPI3_IRQHandler + .thumb_set SPI3_IRQHandler,Default_Handler + + .weak UART4_IRQHandler + .thumb_set UART4_IRQHandler,Default_Handler + + .weak UART5_IRQHandler + .thumb_set UART5_IRQHandler,Default_Handler + + .weak TIM6_IRQHandler + .thumb_set TIM6_IRQHandler,Default_Handler + + .weak TIM7_IRQHandler + .thumb_set TIM7_IRQHandler,Default_Handler + + .weak DMA2_Channel1_IRQHandler + .thumb_set DMA2_Channel1_IRQHandler,Default_Handler + + .weak DMA2_Channel2_IRQHandler + .thumb_set DMA2_Channel2_IRQHandler,Default_Handler + + .weak DMA2_Channel3_IRQHandler + .thumb_set DMA2_Channel3_IRQHandler,Default_Handler + + .weak DMA2_Channel4_5_IRQHandler + .thumb_set DMA2_Channel4_5_IRQHandler,Default_Handler + +/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ diff --git a/Libraries/CMSIS/Device/ST/STM32F10x/Source/Templates/iar/startup_stm32f10x_cl.s b/Libraries/CMSIS/Device/ST/STM32F10x/Source/Templates/iar/startup_stm32f10x_cl.s new file mode 100644 index 0000000..9c29765 --- /dev/null +++ b/Libraries/CMSIS/Device/ST/STM32F10x/Source/Templates/iar/startup_stm32f10x_cl.s @@ -0,0 +1,514 @@ +;******************** (C) COPYRIGHT 2012 STMicroelectronics ******************* +;* File Name : startup_stm32f10x_cl.s +;* Author : MCD Application Team +;* Version : V3.6.1 +;* Date : 09-March-2012 +;* Description : STM32F10x Connectivity line devices vector table for +;* EWARM toolchain. +;* This module performs: +;* - Set the initial SP +;* - Configure the clock system +;* - Set the initial PC == __iar_program_start, +;* - Set the vector table entries with the exceptions ISR +;* address. +;* After Reset the Cortex-M3 processor is in Thread mode, +;* priority is Privileged, and the Stack is set to Main. +;******************************************************************************** +;* +;* Licensed under MCD-ST Liberty SW License Agreement V2, (the "License"); +;* You may not use this file except in compliance with the License. +;* You may obtain a copy of the License at: +;* +;* http://www.st.com/software_license_agreement_liberty_v2 +;* +;* Unless required by applicable law or agreed to in writing, software +;* distributed under the License is distributed on an "AS IS" BASIS, +;* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +;* See the License for the specific language governing permissions and +;* limitations under the License. +;* +;******************************************************************************* +; +; +; The modules in this file are included in the libraries, and may be replaced +; by any user-defined modules that define the PUBLIC symbol _program_start or +; a user defined start symbol. +; To override the cstartup defined in the library, simply add your modified +; version to the workbench project. +; +; The vector table is normally located at address 0. +; When debugging in RAM, it can be located in RAM, aligned to at least 2^6. +; The name "__vector_table" has special meaning for C-SPY: +; it is where the SP start value is found, and the NVIC vector +; table register (VTOR) is initialized to this address if != 0. +; +; Cortex-M version +; + + MODULE ?cstartup + + ;; Forward declaration of sections. + SECTION CSTACK:DATA:NOROOT(3) + + SECTION .intvec:CODE:NOROOT(2) + + EXTERN __iar_program_start + EXTERN SystemInit + PUBLIC __vector_table + + DATA +__vector_table + DCD sfe(CSTACK) + DCD Reset_Handler ; Reset Handler + DCD NMI_Handler ; NMI Handler + DCD HardFault_Handler ; Hard Fault Handler + DCD MemManage_Handler ; MPU Fault Handler + DCD BusFault_Handler ; Bus Fault Handler + DCD UsageFault_Handler ; Usage Fault Handler + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD SVC_Handler ; SVCall Handler + DCD DebugMon_Handler ; Debug Monitor Handler + DCD 0 ; Reserved + DCD PendSV_Handler ; PendSV Handler + DCD SysTick_Handler ; SysTick Handler + + ; External Interrupts + DCD WWDG_IRQHandler ; Window Watchdog + DCD PVD_IRQHandler ; PVD through EXTI Line detect + DCD TAMPER_IRQHandler ; Tamper + DCD RTC_IRQHandler ; RTC + DCD FLASH_IRQHandler ; Flash + DCD RCC_IRQHandler ; RCC + DCD EXTI0_IRQHandler ; EXTI Line 0 + DCD EXTI1_IRQHandler ; EXTI Line 1 + DCD EXTI2_IRQHandler ; EXTI Line 2 + DCD EXTI3_IRQHandler ; EXTI Line 3 + DCD EXTI4_IRQHandler ; EXTI Line 4 + DCD DMA1_Channel1_IRQHandler ; DMA1 Channel 1 + DCD DMA1_Channel2_IRQHandler ; DMA1 Channel 2 + DCD DMA1_Channel3_IRQHandler ; DMA1 Channel 3 + DCD DMA1_Channel4_IRQHandler ; DMA1 Channel 4 + DCD DMA1_Channel5_IRQHandler ; DMA1 Channel 5 + DCD DMA1_Channel6_IRQHandler ; DMA1 Channel 6 + DCD DMA1_Channel7_IRQHandler ; DMA1 Channel 7 + DCD ADC1_2_IRQHandler ; ADC1 and ADC2 + DCD CAN1_TX_IRQHandler ; CAN1 TX + DCD CAN1_RX0_IRQHandler ; CAN1 RX0 + DCD CAN1_RX1_IRQHandler ; CAN1 RX1 + DCD CAN1_SCE_IRQHandler ; CAN1 SCE + DCD EXTI9_5_IRQHandler ; EXTI Line 9..5 + DCD TIM1_BRK_IRQHandler ; TIM1 Break + DCD TIM1_UP_IRQHandler ; TIM1 Update + DCD TIM1_TRG_COM_IRQHandler ; TIM1 Trigger and Commutation + DCD TIM1_CC_IRQHandler ; TIM1 Capture Compare + DCD TIM2_IRQHandler ; TIM2 + DCD TIM3_IRQHandler ; TIM3 + DCD TIM4_IRQHandler ; TIM4 + DCD I2C1_EV_IRQHandler ; I2C1 Event + DCD I2C1_ER_IRQHandler ; I2C1 Error + DCD I2C2_EV_IRQHandler ; I2C2 Event + DCD I2C2_ER_IRQHandler ; I2C1 Error + DCD SPI1_IRQHandler ; SPI1 + DCD SPI2_IRQHandler ; SPI2 + DCD USART1_IRQHandler ; USART1 + DCD USART2_IRQHandler ; USART2 + DCD USART3_IRQHandler ; USART3 + DCD EXTI15_10_IRQHandler ; EXTI Line 15..10 + DCD RTCAlarm_IRQHandler ; RTC alarm through EXTI line + DCD OTG_FS_WKUP_IRQHandler ; USB OTG FS Wakeup through EXTI line + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD TIM5_IRQHandler ; TIM5 + DCD SPI3_IRQHandler ; SPI3 + DCD UART4_IRQHandler ; UART4 + DCD UART5_IRQHandler ; UART5 + DCD TIM6_IRQHandler ; TIM6 + DCD TIM7_IRQHandler ; TIM7 + DCD DMA2_Channel1_IRQHandler ; DMA2 Channel1 + DCD DMA2_Channel2_IRQHandler ; DMA2 Channel2 + DCD DMA2_Channel3_IRQHandler ; DMA2 Channel3 + DCD DMA2_Channel4_IRQHandler ; DMA2 Channel4 + DCD DMA2_Channel5_IRQHandler ; DMA2 Channel5 + DCD ETH_IRQHandler ; Ethernet + DCD ETH_WKUP_IRQHandler ; Ethernet Wakeup through EXTI line + DCD CAN2_TX_IRQHandler ; CAN2 TX + DCD CAN2_RX0_IRQHandler ; CAN2 RX0 + DCD CAN2_RX1_IRQHandler ; CAN2 RX1 + DCD CAN2_SCE_IRQHandler ; CAN2 SCE + DCD OTG_FS_IRQHandler ; USB OTG FS + +;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;; +;; +;; Default interrupt handlers. +;; + THUMB + + PUBWEAK Reset_Handler + SECTION .text:CODE:REORDER(2) +Reset_Handler + LDR R0, =SystemInit + BLX R0 + LDR R0, =__iar_program_start + BX R0 + + PUBWEAK NMI_Handler + SECTION .text:CODE:REORDER(1) +NMI_Handler + B NMI_Handler + + PUBWEAK HardFault_Handler + SECTION .text:CODE:REORDER(1) +HardFault_Handler + B HardFault_Handler + + PUBWEAK MemManage_Handler + SECTION .text:CODE:REORDER(1) +MemManage_Handler + B MemManage_Handler + + PUBWEAK BusFault_Handler + SECTION .text:CODE:REORDER(1) +BusFault_Handler + B BusFault_Handler + + PUBWEAK UsageFault_Handler + SECTION .text:CODE:REORDER(1) +UsageFault_Handler + B UsageFault_Handler + + PUBWEAK SVC_Handler + SECTION .text:CODE:REORDER(1) +SVC_Handler + B SVC_Handler + + PUBWEAK DebugMon_Handler + SECTION .text:CODE:REORDER(1) +DebugMon_Handler + B DebugMon_Handler + + PUBWEAK PendSV_Handler + SECTION .text:CODE:REORDER(1) +PendSV_Handler + B PendSV_Handler + + PUBWEAK SysTick_Handler + SECTION .text:CODE:REORDER(1) +SysTick_Handler + B SysTick_Handler + + PUBWEAK WWDG_IRQHandler + SECTION .text:CODE:REORDER(1) +WWDG_IRQHandler + B WWDG_IRQHandler + + PUBWEAK PVD_IRQHandler + SECTION .text:CODE:REORDER(1) +PVD_IRQHandler + B PVD_IRQHandler + + PUBWEAK TAMPER_IRQHandler + SECTION .text:CODE:REORDER(1) +TAMPER_IRQHandler + B TAMPER_IRQHandler + + PUBWEAK RTC_IRQHandler + SECTION .text:CODE:REORDER(1) +RTC_IRQHandler + B RTC_IRQHandler + + PUBWEAK FLASH_IRQHandler + SECTION .text:CODE:REORDER(1) +FLASH_IRQHandler + B FLASH_IRQHandler + + PUBWEAK RCC_IRQHandler + SECTION .text:CODE:REORDER(1) +RCC_IRQHandler + B RCC_IRQHandler + + PUBWEAK EXTI0_IRQHandler + SECTION .text:CODE:REORDER(1) +EXTI0_IRQHandler + B EXTI0_IRQHandler + + PUBWEAK EXTI1_IRQHandler + SECTION .text:CODE:REORDER(1) +EXTI1_IRQHandler + B EXTI1_IRQHandler + + PUBWEAK EXTI2_IRQHandler + SECTION .text:CODE:REORDER(1) +EXTI2_IRQHandler + B EXTI2_IRQHandler + + PUBWEAK EXTI3_IRQHandler + SECTION .text:CODE:REORDER(1) +EXTI3_IRQHandler + B EXTI3_IRQHandler + + + PUBWEAK EXTI4_IRQHandler + SECTION .text:CODE:REORDER(1) +EXTI4_IRQHandler + B EXTI4_IRQHandler + + PUBWEAK DMA1_Channel1_IRQHandler + SECTION .text:CODE:REORDER(1) +DMA1_Channel1_IRQHandler + B DMA1_Channel1_IRQHandler + + PUBWEAK DMA1_Channel2_IRQHandler + SECTION .text:CODE:REORDER(1) +DMA1_Channel2_IRQHandler + B DMA1_Channel2_IRQHandler + + PUBWEAK DMA1_Channel3_IRQHandler + SECTION .text:CODE:REORDER(1) +DMA1_Channel3_IRQHandler + B DMA1_Channel3_IRQHandler + + PUBWEAK DMA1_Channel4_IRQHandler + SECTION .text:CODE:REORDER(1) +DMA1_Channel4_IRQHandler + B DMA1_Channel4_IRQHandler + + PUBWEAK DMA1_Channel5_IRQHandler + SECTION .text:CODE:REORDER(1) +DMA1_Channel5_IRQHandler + B DMA1_Channel5_IRQHandler + + PUBWEAK DMA1_Channel6_IRQHandler + SECTION .text:CODE:REORDER(1) +DMA1_Channel6_IRQHandler + B DMA1_Channel6_IRQHandler + + PUBWEAK DMA1_Channel7_IRQHandler + SECTION .text:CODE:REORDER(1) +DMA1_Channel7_IRQHandler + B DMA1_Channel7_IRQHandler + + PUBWEAK ADC1_2_IRQHandler + SECTION .text:CODE:REORDER(1) +ADC1_2_IRQHandler + B ADC1_2_IRQHandler + + PUBWEAK CAN1_TX_IRQHandler + SECTION .text:CODE:REORDER(1) +CAN1_TX_IRQHandler + B CAN1_TX_IRQHandler + + PUBWEAK CAN1_RX0_IRQHandler + SECTION .text:CODE:REORDER(1) +CAN1_RX0_IRQHandler + B CAN1_RX0_IRQHandler + + PUBWEAK CAN1_RX1_IRQHandler + SECTION .text:CODE:REORDER(1) +CAN1_RX1_IRQHandler + B CAN1_RX1_IRQHandler + + PUBWEAK CAN1_SCE_IRQHandler + SECTION .text:CODE:REORDER(1) +CAN1_SCE_IRQHandler + B CAN1_SCE_IRQHandler + + PUBWEAK EXTI9_5_IRQHandler + SECTION .text:CODE:REORDER(1) +EXTI9_5_IRQHandler + B EXTI9_5_IRQHandler + + PUBWEAK TIM1_BRK_IRQHandler + SECTION .text:CODE:REORDER(1) +TIM1_BRK_IRQHandler + B TIM1_BRK_IRQHandler + + PUBWEAK TIM1_UP_IRQHandler + SECTION .text:CODE:REORDER(1) +TIM1_UP_IRQHandler + B TIM1_UP_IRQHandler + + PUBWEAK TIM1_TRG_COM_IRQHandler + SECTION .text:CODE:REORDER(1) +TIM1_TRG_COM_IRQHandler + B TIM1_TRG_COM_IRQHandler + + PUBWEAK TIM1_CC_IRQHandler + SECTION .text:CODE:REORDER(1) +TIM1_CC_IRQHandler + B TIM1_CC_IRQHandler + + PUBWEAK TIM2_IRQHandler + SECTION .text:CODE:REORDER(1) +TIM2_IRQHandler + B TIM2_IRQHandler + + PUBWEAK TIM3_IRQHandler + SECTION .text:CODE:REORDER(1) +TIM3_IRQHandler + B TIM3_IRQHandler + + PUBWEAK TIM4_IRQHandler + SECTION .text:CODE:REORDER(1) +TIM4_IRQHandler + B TIM4_IRQHandler + + PUBWEAK I2C1_EV_IRQHandler + SECTION .text:CODE:REORDER(1) +I2C1_EV_IRQHandler + B I2C1_EV_IRQHandler + + PUBWEAK I2C1_ER_IRQHandler + SECTION .text:CODE:REORDER(1) +I2C1_ER_IRQHandler + B I2C1_ER_IRQHandler + + PUBWEAK I2C2_EV_IRQHandler + SECTION .text:CODE:REORDER(1) +I2C2_EV_IRQHandler + B I2C2_EV_IRQHandler + + PUBWEAK I2C2_ER_IRQHandler + SECTION .text:CODE:REORDER(1) +I2C2_ER_IRQHandler + B I2C2_ER_IRQHandler + + PUBWEAK SPI1_IRQHandler + SECTION .text:CODE:REORDER(1) +SPI1_IRQHandler + B SPI1_IRQHandler + + PUBWEAK SPI2_IRQHandler + SECTION .text:CODE:REORDER(1) +SPI2_IRQHandler + B SPI2_IRQHandler + + PUBWEAK USART1_IRQHandler + SECTION .text:CODE:REORDER(1) +USART1_IRQHandler + B USART1_IRQHandler + + PUBWEAK USART2_IRQHandler + SECTION .text:CODE:REORDER(1) +USART2_IRQHandler + B USART2_IRQHandler + + PUBWEAK USART3_IRQHandler + SECTION .text:CODE:REORDER(1) +USART3_IRQHandler + B USART3_IRQHandler + + PUBWEAK EXTI15_10_IRQHandler + SECTION .text:CODE:REORDER(1) +EXTI15_10_IRQHandler + B EXTI15_10_IRQHandler + + PUBWEAK RTCAlarm_IRQHandler + SECTION .text:CODE:REORDER(1) +RTCAlarm_IRQHandler + B RTCAlarm_IRQHandler + + PUBWEAK OTG_FS_WKUP_IRQHandler + SECTION .text:CODE:REORDER(1) +OTG_FS_WKUP_IRQHandler + B OTG_FS_WKUP_IRQHandler + + PUBWEAK TIM5_IRQHandler + SECTION .text:CODE:REORDER(1) +TIM5_IRQHandler + B TIM5_IRQHandler + + PUBWEAK SPI3_IRQHandler + SECTION .text:CODE:REORDER(1) +SPI3_IRQHandler + B SPI3_IRQHandler + + PUBWEAK UART4_IRQHandler + SECTION .text:CODE:REORDER(1) +UART4_IRQHandler + B UART4_IRQHandler + + PUBWEAK UART5_IRQHandler + SECTION .text:CODE:REORDER(1) +UART5_IRQHandler + B UART5_IRQHandler + + PUBWEAK TIM6_IRQHandler + SECTION .text:CODE:REORDER(1) +TIM6_IRQHandler + B TIM6_IRQHandler + + PUBWEAK TIM7_IRQHandler + SECTION .text:CODE:REORDER(1) +TIM7_IRQHandler + B TIM7_IRQHandler + + PUBWEAK DMA2_Channel1_IRQHandler + SECTION .text:CODE:REORDER(1) +DMA2_Channel1_IRQHandler + B DMA2_Channel1_IRQHandler + + PUBWEAK DMA2_Channel2_IRQHandler + SECTION .text:CODE:REORDER(1) +DMA2_Channel2_IRQHandler + B DMA2_Channel2_IRQHandler + + PUBWEAK DMA2_Channel3_IRQHandler + SECTION .text:CODE:REORDER(1) +DMA2_Channel3_IRQHandler + B DMA2_Channel3_IRQHandler + + PUBWEAK DMA2_Channel4_IRQHandler + SECTION .text:CODE:REORDER(1) +DMA2_Channel4_IRQHandler + B DMA2_Channel4_IRQHandler + + PUBWEAK DMA2_Channel5_IRQHandler + SECTION .text:CODE:REORDER(1) +DMA2_Channel5_IRQHandler + B DMA2_Channel5_IRQHandler + + PUBWEAK ETH_IRQHandler + SECTION .text:CODE:REORDER(1) +ETH_IRQHandler + B ETH_IRQHandler + + PUBWEAK ETH_WKUP_IRQHandler + SECTION .text:CODE:REORDER(1) +ETH_WKUP_IRQHandler + B ETH_WKUP_IRQHandler + + PUBWEAK CAN2_TX_IRQHandler + SECTION .text:CODE:REORDER(1) +CAN2_TX_IRQHandler + B CAN2_TX_IRQHandler + + PUBWEAK CAN2_RX0_IRQHandler + SECTION .text:CODE:REORDER(1) +CAN2_RX0_IRQHandler + B CAN2_RX0_IRQHandler + + PUBWEAK CAN2_RX1_IRQHandler + SECTION .text:CODE:REORDER(1) +CAN2_RX1_IRQHandler + B CAN2_RX1_IRQHandler + + PUBWEAK CAN2_SCE_IRQHandler + SECTION .text:CODE:REORDER(1) +CAN2_SCE_IRQHandler + B CAN2_SCE_IRQHandler + + PUBWEAK OTG_FS_IRQHandler + SECTION .text:CODE:REORDER(1) +OTG_FS_IRQHandler + B OTG_FS_IRQHandler + + END +/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ diff --git a/Libraries/CMSIS/Device/ST/STM32F10x/Source/Templates/iar/startup_stm32f10x_hd.s b/Libraries/CMSIS/Device/ST/STM32F10x/Source/Templates/iar/startup_stm32f10x_hd.s new file mode 100644 index 0000000..4af1336 --- /dev/null +++ b/Libraries/CMSIS/Device/ST/STM32F10x/Source/Templates/iar/startup_stm32f10x_hd.s @@ -0,0 +1,503 @@ +;******************** (C) COPYRIGHT 2012 STMicroelectronics ******************** +;* File Name : startup_stm32f10x_hd.s +;* Author : MCD Application Team +;* Version : V3.6.1 +;* Date : 09-March-2012 +;* Description : STM32F10x High Density Devices vector table for EWARM +;* toolchain. +;* This module performs: +;* - Set the initial SP +;* - Configure the clock system and the external SRAM +;* mounted on STM3210E-EVAL board to be used as data +;* memory (optional, to be enabled by user) +;* - Set the initial PC == __iar_program_start, +;* - Set the vector table entries with the exceptions ISR address, +;* After Reset the Cortex-M3 processor is in Thread mode, +;* priority is Privileged, and the Stack is set to Main. +;******************************************************************************** +;* +;* Licensed under MCD-ST Liberty SW License Agreement V2, (the "License"); +;* You may not use this file except in compliance with the License. +;* You may obtain a copy of the License at: +;* +;* http://www.st.com/software_license_agreement_liberty_v2 +;* +;* Unless required by applicable law or agreed to in writing, software +;* distributed under the License is distributed on an "AS IS" BASIS, +;* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +;* See the License for the specific language governing permissions and +;* limitations under the License. +;* +;******************************************************************************* +; +; +; The modules in this file are included in the libraries, and may be replaced +; by any user-defined modules that define the PUBLIC symbol _program_start or +; a user defined start symbol. +; To override the cstartup defined in the library, simply add your modified +; version to the workbench project. +; +; The vector table is normally located at address 0. +; When debugging in RAM, it can be located in RAM, aligned to at least 2^6. +; The name "__vector_table" has special meaning for C-SPY: +; it is where the SP start value is found, and the NVIC vector +; table register (VTOR) is initialized to this address if != 0. +; +; Cortex-M version +; + + MODULE ?cstartup + + ;; Forward declaration of sections. + SECTION CSTACK:DATA:NOROOT(3) + + SECTION .intvec:CODE:NOROOT(2) + + EXTERN __iar_program_start + EXTERN SystemInit + PUBLIC __vector_table + + DATA + +__vector_table + DCD sfe(CSTACK) + DCD Reset_Handler ; Reset Handler + DCD NMI_Handler ; NMI Handler + DCD HardFault_Handler ; Hard Fault Handler + DCD MemManage_Handler ; MPU Fault Handler + DCD BusFault_Handler ; Bus Fault Handler + DCD UsageFault_Handler ; Usage Fault Handler + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD SVC_Handler ; SVCall Handler + DCD DebugMon_Handler ; Debug Monitor Handler + DCD 0 ; Reserved + DCD PendSV_Handler ; PendSV Handler + DCD SysTick_Handler ; SysTick Handler + + ; External Interrupts + DCD WWDG_IRQHandler ; Window Watchdog + DCD PVD_IRQHandler ; PVD through EXTI Line detect + DCD TAMPER_IRQHandler ; Tamper + DCD RTC_IRQHandler ; RTC + DCD FLASH_IRQHandler ; Flash + DCD RCC_IRQHandler ; RCC + DCD EXTI0_IRQHandler ; EXTI Line 0 + DCD EXTI1_IRQHandler ; EXTI Line 1 + DCD EXTI2_IRQHandler ; EXTI Line 2 + DCD EXTI3_IRQHandler ; EXTI Line 3 + DCD EXTI4_IRQHandler ; EXTI Line 4 + DCD DMA1_Channel1_IRQHandler ; DMA1 Channel 1 + DCD DMA1_Channel2_IRQHandler ; DMA1 Channel 2 + DCD DMA1_Channel3_IRQHandler ; DMA1 Channel 3 + DCD DMA1_Channel4_IRQHandler ; DMA1 Channel 4 + DCD DMA1_Channel5_IRQHandler ; DMA1 Channel 5 + DCD DMA1_Channel6_IRQHandler ; DMA1 Channel 6 + DCD DMA1_Channel7_IRQHandler ; DMA1 Channel 7 + DCD ADC1_2_IRQHandler ; ADC1 & ADC2 + DCD USB_HP_CAN1_TX_IRQHandler ; USB High Priority or CAN1 TX + DCD USB_LP_CAN1_RX0_IRQHandler ; USB Low Priority or CAN1 RX0 + DCD CAN1_RX1_IRQHandler ; CAN1 RX1 + DCD CAN1_SCE_IRQHandler ; CAN1 SCE + DCD EXTI9_5_IRQHandler ; EXTI Line 9..5 + DCD TIM1_BRK_IRQHandler ; TIM1 Break + DCD TIM1_UP_IRQHandler ; TIM1 Update + DCD TIM1_TRG_COM_IRQHandler ; TIM1 Trigger and Commutation + DCD TIM1_CC_IRQHandler ; TIM1 Capture Compare + DCD TIM2_IRQHandler ; TIM2 + DCD TIM3_IRQHandler ; TIM3 + DCD TIM4_IRQHandler ; TIM4 + DCD I2C1_EV_IRQHandler ; I2C1 Event + DCD I2C1_ER_IRQHandler ; I2C1 Error + DCD I2C2_EV_IRQHandler ; I2C2 Event + DCD I2C2_ER_IRQHandler ; I2C2 Error + DCD SPI1_IRQHandler ; SPI1 + DCD SPI2_IRQHandler ; SPI2 + DCD USART1_IRQHandler ; USART1 + DCD USART2_IRQHandler ; USART2 + DCD USART3_IRQHandler ; USART3 + DCD EXTI15_10_IRQHandler ; EXTI Line 15..10 + DCD RTCAlarm_IRQHandler ; RTC Alarm through EXTI Line + DCD USBWakeUp_IRQHandler ; USB Wakeup from suspend + DCD TIM8_BRK_IRQHandler ; TIM8 Break + DCD TIM8_UP_IRQHandler ; TIM8 Update + DCD TIM8_TRG_COM_IRQHandler ; TIM8 Trigger and Commutation + DCD TIM8_CC_IRQHandler ; TIM8 Capture Compare + DCD ADC3_IRQHandler ; ADC3 + DCD FSMC_IRQHandler ; FSMC + DCD SDIO_IRQHandler ; SDIO + DCD TIM5_IRQHandler ; TIM5 + DCD SPI3_IRQHandler ; SPI3 + DCD UART4_IRQHandler ; UART4 + DCD UART5_IRQHandler ; UART5 + DCD TIM6_IRQHandler ; TIM6 + DCD TIM7_IRQHandler ; TIM7 + DCD DMA2_Channel1_IRQHandler ; DMA2 Channel1 + DCD DMA2_Channel2_IRQHandler ; DMA2 Channel2 + DCD DMA2_Channel3_IRQHandler ; DMA2 Channel3 + DCD DMA2_Channel4_5_IRQHandler ; DMA2 Channel4 & Channel5 +;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;; +;; +;; Default interrupt handlers. +;; + THUMB + + PUBWEAK Reset_Handler + SECTION .text:CODE:REORDER(2) +Reset_Handler + LDR R0, =SystemInit + BLX R0 + LDR R0, =__iar_program_start + BX R0 + + PUBWEAK NMI_Handler + SECTION .text:CODE:REORDER(1) +NMI_Handler + B NMI_Handler + + PUBWEAK HardFault_Handler + SECTION .text:CODE:REORDER(1) +HardFault_Handler + B HardFault_Handler + + PUBWEAK MemManage_Handler + SECTION .text:CODE:REORDER(1) +MemManage_Handler + B MemManage_Handler + + PUBWEAK BusFault_Handler + SECTION .text:CODE:REORDER(1) +BusFault_Handler + B BusFault_Handler + + PUBWEAK UsageFault_Handler + SECTION .text:CODE:REORDER(1) +UsageFault_Handler + B UsageFault_Handler + + PUBWEAK SVC_Handler + SECTION .text:CODE:REORDER(1) +SVC_Handler + B SVC_Handler + + PUBWEAK DebugMon_Handler + SECTION .text:CODE:REORDER(1) +DebugMon_Handler + B DebugMon_Handler + + PUBWEAK PendSV_Handler + SECTION .text:CODE:REORDER(1) +PendSV_Handler + B PendSV_Handler + + PUBWEAK SysTick_Handler + SECTION .text:CODE:REORDER(1) +SysTick_Handler + B SysTick_Handler + + PUBWEAK WWDG_IRQHandler + SECTION .text:CODE:REORDER(1) +WWDG_IRQHandler + B WWDG_IRQHandler + + PUBWEAK PVD_IRQHandler + SECTION .text:CODE:REORDER(1) +PVD_IRQHandler + B PVD_IRQHandler + + PUBWEAK TAMPER_IRQHandler + SECTION .text:CODE:REORDER(1) +TAMPER_IRQHandler + B TAMPER_IRQHandler + + PUBWEAK RTC_IRQHandler + SECTION .text:CODE:REORDER(1) +RTC_IRQHandler + B RTC_IRQHandler + + PUBWEAK FLASH_IRQHandler + SECTION .text:CODE:REORDER(1) +FLASH_IRQHandler + B FLASH_IRQHandler + + PUBWEAK RCC_IRQHandler + SECTION .text:CODE:REORDER(1) +RCC_IRQHandler + B RCC_IRQHandler + + PUBWEAK EXTI0_IRQHandler + SECTION .text:CODE:REORDER(1) +EXTI0_IRQHandler + B EXTI0_IRQHandler + + PUBWEAK EXTI1_IRQHandler + SECTION .text:CODE:REORDER(1) +EXTI1_IRQHandler + B EXTI1_IRQHandler + + PUBWEAK EXTI2_IRQHandler + SECTION .text:CODE:REORDER(1) +EXTI2_IRQHandler + B EXTI2_IRQHandler + + PUBWEAK EXTI3_IRQHandler + SECTION .text:CODE:REORDER(1) +EXTI3_IRQHandler + B EXTI3_IRQHandler + + PUBWEAK EXTI4_IRQHandler + SECTION .text:CODE:REORDER(1) +EXTI4_IRQHandler + B EXTI4_IRQHandler + + PUBWEAK DMA1_Channel1_IRQHandler + SECTION .text:CODE:REORDER(1) +DMA1_Channel1_IRQHandler + B DMA1_Channel1_IRQHandler + + PUBWEAK DMA1_Channel2_IRQHandler + SECTION .text:CODE:REORDER(1) +DMA1_Channel2_IRQHandler + B DMA1_Channel2_IRQHandler + + PUBWEAK DMA1_Channel3_IRQHandler + SECTION .text:CODE:REORDER(1) +DMA1_Channel3_IRQHandler + B DMA1_Channel3_IRQHandler + + PUBWEAK DMA1_Channel4_IRQHandler + SECTION .text:CODE:REORDER(1) +DMA1_Channel4_IRQHandler + B DMA1_Channel4_IRQHandler + + PUBWEAK DMA1_Channel5_IRQHandler + SECTION .text:CODE:REORDER(1) +DMA1_Channel5_IRQHandler + B DMA1_Channel5_IRQHandler + + PUBWEAK DMA1_Channel6_IRQHandler + SECTION .text:CODE:REORDER(1) +DMA1_Channel6_IRQHandler + B DMA1_Channel6_IRQHandler + + PUBWEAK DMA1_Channel7_IRQHandler + SECTION .text:CODE:REORDER(1) +DMA1_Channel7_IRQHandler + B DMA1_Channel7_IRQHandler + + PUBWEAK ADC1_2_IRQHandler + SECTION .text:CODE:REORDER(1) +ADC1_2_IRQHandler + B ADC1_2_IRQHandler + + PUBWEAK USB_HP_CAN1_TX_IRQHandler + SECTION .text:CODE:REORDER(1) +USB_HP_CAN1_TX_IRQHandler + B USB_HP_CAN1_TX_IRQHandler + + PUBWEAK USB_LP_CAN1_RX0_IRQHandler + SECTION .text:CODE:REORDER(1) +USB_LP_CAN1_RX0_IRQHandler + B USB_LP_CAN1_RX0_IRQHandler + + PUBWEAK CAN1_RX1_IRQHandler + SECTION .text:CODE:REORDER(1) +CAN1_RX1_IRQHandler + B CAN1_RX1_IRQHandler + + PUBWEAK CAN1_SCE_IRQHandler + SECTION .text:CODE:REORDER(1) +CAN1_SCE_IRQHandler + B CAN1_SCE_IRQHandler + + PUBWEAK EXTI9_5_IRQHandler + SECTION .text:CODE:REORDER(1) +EXTI9_5_IRQHandler + B EXTI9_5_IRQHandler + + PUBWEAK TIM1_BRK_IRQHandler + SECTION .text:CODE:REORDER(1) +TIM1_BRK_IRQHandler + B TIM1_BRK_IRQHandler + + PUBWEAK TIM1_UP_IRQHandler + SECTION .text:CODE:REORDER(1) +TIM1_UP_IRQHandler + B TIM1_UP_IRQHandler + + PUBWEAK TIM1_TRG_COM_IRQHandler + SECTION .text:CODE:REORDER(1) +TIM1_TRG_COM_IRQHandler + B TIM1_TRG_COM_IRQHandler + + PUBWEAK TIM1_CC_IRQHandler + SECTION .text:CODE:REORDER(1) +TIM1_CC_IRQHandler + B TIM1_CC_IRQHandler + + PUBWEAK TIM2_IRQHandler + SECTION .text:CODE:REORDER(1) +TIM2_IRQHandler + B TIM2_IRQHandler + + PUBWEAK TIM3_IRQHandler + SECTION .text:CODE:REORDER(1) +TIM3_IRQHandler + B TIM3_IRQHandler + + PUBWEAK TIM4_IRQHandler + SECTION .text:CODE:REORDER(1) +TIM4_IRQHandler + B TIM4_IRQHandler + + PUBWEAK I2C1_EV_IRQHandler + SECTION .text:CODE:REORDER(1) +I2C1_EV_IRQHandler + B I2C1_EV_IRQHandler + + PUBWEAK I2C1_ER_IRQHandler + SECTION .text:CODE:REORDER(1) +I2C1_ER_IRQHandler + B I2C1_ER_IRQHandler + + PUBWEAK I2C2_EV_IRQHandler + SECTION .text:CODE:REORDER(1) +I2C2_EV_IRQHandler + B I2C2_EV_IRQHandler + + PUBWEAK I2C2_ER_IRQHandler + SECTION .text:CODE:REORDER(1) +I2C2_ER_IRQHandler + B I2C2_ER_IRQHandler + + PUBWEAK SPI1_IRQHandler + SECTION .text:CODE:REORDER(1) +SPI1_IRQHandler + B SPI1_IRQHandler + + PUBWEAK SPI2_IRQHandler + SECTION .text:CODE:REORDER(1) +SPI2_IRQHandler + B SPI2_IRQHandler + + PUBWEAK USART1_IRQHandler + SECTION .text:CODE:REORDER(1) +USART1_IRQHandler + B USART1_IRQHandler + + PUBWEAK USART2_IRQHandler + SECTION .text:CODE:REORDER(1) +USART2_IRQHandler + B USART2_IRQHandler + + PUBWEAK USART3_IRQHandler + SECTION .text:CODE:REORDER(1) +USART3_IRQHandler + B USART3_IRQHandler + + PUBWEAK EXTI15_10_IRQHandler + SECTION .text:CODE:REORDER(1) +EXTI15_10_IRQHandler + B EXTI15_10_IRQHandler + + PUBWEAK RTCAlarm_IRQHandler + SECTION .text:CODE:REORDER(1) +RTCAlarm_IRQHandler + B RTCAlarm_IRQHandler + + PUBWEAK USBWakeUp_IRQHandler + SECTION .text:CODE:REORDER(1) +USBWakeUp_IRQHandler + B USBWakeUp_IRQHandler + + PUBWEAK TIM8_BRK_IRQHandler + SECTION .text:CODE:REORDER(1) +TIM8_BRK_IRQHandler + B TIM8_BRK_IRQHandler + + PUBWEAK TIM8_UP_IRQHandler + SECTION .text:CODE:REORDER(1) +TIM8_UP_IRQHandler + B TIM8_UP_IRQHandler + + PUBWEAK TIM8_TRG_COM_IRQHandler + SECTION .text:CODE:REORDER(1) +TIM8_TRG_COM_IRQHandler + B TIM8_TRG_COM_IRQHandler + + PUBWEAK TIM8_CC_IRQHandler + SECTION .text:CODE:REORDER(1) +TIM8_CC_IRQHandler + B TIM8_CC_IRQHandler + + PUBWEAK ADC3_IRQHandler + SECTION .text:CODE:REORDER(1) +ADC3_IRQHandler + B ADC3_IRQHandler + + PUBWEAK FSMC_IRQHandler + SECTION .text:CODE:REORDER(1) +FSMC_IRQHandler + B FSMC_IRQHandler + + PUBWEAK SDIO_IRQHandler + SECTION .text:CODE:REORDER(1) +SDIO_IRQHandler + B SDIO_IRQHandler + + PUBWEAK TIM5_IRQHandler + SECTION .text:CODE:REORDER(1) +TIM5_IRQHandler + B TIM5_IRQHandler + + PUBWEAK SPI3_IRQHandler + SECTION .text:CODE:REORDER(1) +SPI3_IRQHandler + B SPI3_IRQHandler + + PUBWEAK UART4_IRQHandler + SECTION .text:CODE:REORDER(1) +UART4_IRQHandler + B UART4_IRQHandler + + PUBWEAK UART5_IRQHandler + SECTION .text:CODE:REORDER(1) +UART5_IRQHandler + B UART5_IRQHandler + + PUBWEAK TIM6_IRQHandler + SECTION .text:CODE:REORDER(1) +TIM6_IRQHandler + B TIM6_IRQHandler + + PUBWEAK TIM7_IRQHandler + SECTION .text:CODE:REORDER(1) +TIM7_IRQHandler + B TIM7_IRQHandler + + PUBWEAK DMA2_Channel1_IRQHandler + SECTION .text:CODE:REORDER(1) +DMA2_Channel1_IRQHandler + B DMA2_Channel1_IRQHandler + + PUBWEAK DMA2_Channel2_IRQHandler + SECTION .text:CODE:REORDER(1) +DMA2_Channel2_IRQHandler + B DMA2_Channel2_IRQHandler + + PUBWEAK DMA2_Channel3_IRQHandler + SECTION .text:CODE:REORDER(1) +DMA2_Channel3_IRQHandler + B DMA2_Channel3_IRQHandler + + PUBWEAK DMA2_Channel4_5_IRQHandler + SECTION .text:CODE:REORDER(1) +DMA2_Channel4_5_IRQHandler + B DMA2_Channel4_5_IRQHandler + + + END + +/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ diff --git a/Libraries/CMSIS/Device/ST/STM32F10x/Source/Templates/iar/startup_stm32f10x_hd_vl.s b/Libraries/CMSIS/Device/ST/STM32F10x/Source/Templates/iar/startup_stm32f10x_hd_vl.s new file mode 100644 index 0000000..7390a93 --- /dev/null +++ b/Libraries/CMSIS/Device/ST/STM32F10x/Source/Templates/iar/startup_stm32f10x_hd_vl.s @@ -0,0 +1,468 @@ +;******************** (C) COPYRIGHT 2012 STMicroelectronics ******************** +;* File Name : startup_stm32f10x_hd_vl.s +;* Author : MCD Application Team +;* Version : V3.6.1 +;* Date : 09-March-2012 +;* Description : STM32F10x High Density Value Line Devices vector table +;* for EWARM toolchain. +;* This module performs: +;* - Set the initial SP +;* - Configure the clock system and the external SRAM +;* mounted on STM32100E-EVAL board to be used as data +;* memory (optional, to be enabled by user) +;* - Set the initial PC == __iar_program_start, +;* - Set the vector table entries with the exceptions ISR +;* address. +;* After Reset the Cortex-M3 processor is in Thread mode, +;* priority is Privileged, and the Stack is set to Main. +;******************************************************************************** +;* +;* Licensed under MCD-ST Liberty SW License Agreement V2, (the "License"); +;* You may not use this file except in compliance with the License. +;* You may obtain a copy of the License at: +;* +;* http://www.st.com/software_license_agreement_liberty_v2 +;* +;* Unless required by applicable law or agreed to in writing, software +;* distributed under the License is distributed on an "AS IS" BASIS, +;* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +;* See the License for the specific language governing permissions and +;* limitations under the License. +;* +;******************************************************************************* +; +; +; The modules in this file are included in the libraries, and may be replaced +; by any user-defined modules that define the PUBLIC symbol _program_start or +; a user defined start symbol. +; To override the cstartup defined in the library, simply add your modified +; version to the workbench project. +; +; The vector table is normally located at address 0. +; When debugging in RAM, it can be located in RAM, aligned to at least 2^6. +; The name "__vector_table" has special meaning for C-SPY: +; it is where the SP start value is found, and the NVIC vector +; table register (VTOR) is initialized to this address if != 0. +; +; Cortex-M version +; + + MODULE ?cstartup + + ;; Forward declaration of sections. + SECTION CSTACK:DATA:NOROOT(3) + + SECTION .intvec:CODE:NOROOT(2) + + EXTERN __iar_program_start + EXTERN SystemInit + PUBLIC __vector_table + + DATA +__vector_table + DCD sfe(CSTACK) + DCD Reset_Handler ; Reset Handler + DCD NMI_Handler ; NMI Handler + DCD HardFault_Handler ; Hard Fault Handler + DCD MemManage_Handler ; MPU Fault Handler + DCD BusFault_Handler ; Bus Fault Handler + DCD UsageFault_Handler ; Usage Fault Handler + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD SVC_Handler ; SVCall Handler + DCD DebugMon_Handler ; Debug Monitor Handler + DCD 0 ; Reserved + DCD PendSV_Handler ; PendSV Handler + DCD SysTick_Handler ; SysTick Handler + + ; External Interrupts + DCD WWDG_IRQHandler ; Window Watchdog + DCD PVD_IRQHandler ; PVD through EXTI Line detect + DCD TAMPER_IRQHandler ; Tamper + DCD RTC_IRQHandler ; RTC + DCD FLASH_IRQHandler ; Flash + DCD RCC_IRQHandler ; RCC + DCD EXTI0_IRQHandler ; EXTI Line 0 + DCD EXTI1_IRQHandler ; EXTI Line 1 + DCD EXTI2_IRQHandler ; EXTI Line 2 + DCD EXTI3_IRQHandler ; EXTI Line 3 + DCD EXTI4_IRQHandler ; EXTI Line 4 + DCD DMA1_Channel1_IRQHandler ; DMA1 Channel 1 + DCD DMA1_Channel2_IRQHandler ; DMA1 Channel 2 + DCD DMA1_Channel3_IRQHandler ; DMA1 Channel 3 + DCD DMA1_Channel4_IRQHandler ; DMA1 Channel 4 + DCD DMA1_Channel5_IRQHandler ; DMA1 Channel 5 + DCD DMA1_Channel6_IRQHandler ; DMA1 Channel 6 + DCD DMA1_Channel7_IRQHandler ; DMA1 Channel 7 + DCD ADC1_IRQHandler ; ADC1 + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD EXTI9_5_IRQHandler ; EXTI Line 9..5 + DCD TIM1_BRK_TIM15_IRQHandler ; TIM1 Break and TIM15 + DCD TIM1_UP_TIM16_IRQHandler ; TIM1 Update and TIM16 + DCD TIM1_TRG_COM_TIM17_IRQHandler ; TIM1 Trigger and Commutation and TIM17 + DCD TIM1_CC_IRQHandler ; TIM1 Capture Compare + DCD TIM2_IRQHandler ; TIM2 + DCD TIM3_IRQHandler ; TIM3 + DCD TIM4_IRQHandler ; TIM4 + DCD I2C1_EV_IRQHandler ; I2C1 Event + DCD I2C1_ER_IRQHandler ; I2C1 Error + DCD I2C2_EV_IRQHandler ; I2C2 Event + DCD I2C2_ER_IRQHandler ; I2C2 Error + DCD SPI1_IRQHandler ; SPI1 + DCD SPI2_IRQHandler ; SPI2 + DCD USART1_IRQHandler ; USART1 + DCD USART2_IRQHandler ; USART2 + DCD USART3_IRQHandler ; USART3 + DCD EXTI15_10_IRQHandler ; EXTI Line 15..10 + DCD RTCAlarm_IRQHandler ; RTC Alarm through EXTI Line + DCD CEC_IRQHandler ; HDMI-CEC + DCD TIM12_IRQHandler ; TIM12 + DCD TIM13_IRQHandler ; TIM13 + DCD TIM14_IRQHandler ; TIM14 + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD TIM5_IRQHandler ; TIM5 + DCD SPI3_IRQHandler ; SPI3 + DCD UART4_IRQHandler ; UART4 + DCD UART5_IRQHandler ; UART5 + DCD TIM6_DAC_IRQHandler ; TIM6 and DAC underrun + DCD TIM7_IRQHandler ; TIM7 + DCD DMA2_Channel1_IRQHandler ; DMA2 Channel1 + DCD DMA2_Channel2_IRQHandler ; DMA2 Channel2 + DCD DMA2_Channel3_IRQHandler ; DMA2 Channel3 + DCD DMA2_Channel4_5_IRQHandler ; DMA2 Channel4 & Channel5 + DCD DMA2_Channel5_IRQHandler ; DMA2 Channel5 + +;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;; +;; +;; Default interrupt handlers. +;; + THUMB + + PUBWEAK Reset_Handler + SECTION .text:CODE:REORDER(2) +Reset_Handler + LDR R0, =SystemInit + BLX R0 + LDR R0, =__iar_program_start + BX R0 + + PUBWEAK NMI_Handler + SECTION .text:CODE:REORDER(1) +NMI_Handler + B NMI_Handler + + PUBWEAK HardFault_Handler + SECTION .text:CODE:REORDER(1) +HardFault_Handler + B HardFault_Handler + + PUBWEAK MemManage_Handler + SECTION .text:CODE:REORDER(1) +MemManage_Handler + B MemManage_Handler + + PUBWEAK BusFault_Handler + SECTION .text:CODE:REORDER(1) +BusFault_Handler + B BusFault_Handler + + PUBWEAK UsageFault_Handler + SECTION .text:CODE:REORDER(1) +UsageFault_Handler + B UsageFault_Handler + + PUBWEAK SVC_Handler + SECTION .text:CODE:REORDER(1) +SVC_Handler + B SVC_Handler + + PUBWEAK DebugMon_Handler + SECTION .text:CODE:REORDER(1) +DebugMon_Handler + B DebugMon_Handler + + PUBWEAK PendSV_Handler + SECTION .text:CODE:REORDER(1) +PendSV_Handler + B PendSV_Handler + + PUBWEAK SysTick_Handler + SECTION .text:CODE:REORDER(1) +SysTick_Handler + B SysTick_Handler + + PUBWEAK WWDG_IRQHandler + SECTION .text:CODE:REORDER(1) +WWDG_IRQHandler + B WWDG_IRQHandler + + PUBWEAK PVD_IRQHandler + SECTION .text:CODE:REORDER(1) +PVD_IRQHandler + B PVD_IRQHandler + + PUBWEAK TAMPER_IRQHandler + SECTION .text:CODE:REORDER(1) +TAMPER_IRQHandler + B TAMPER_IRQHandler + + PUBWEAK RTC_IRQHandler + SECTION .text:CODE:REORDER(1) +RTC_IRQHandler + B RTC_IRQHandler + + PUBWEAK FLASH_IRQHandler + SECTION .text:CODE:REORDER(1) +FLASH_IRQHandler + B FLASH_IRQHandler + + PUBWEAK RCC_IRQHandler + SECTION .text:CODE:REORDER(1) +RCC_IRQHandler + B RCC_IRQHandler + + PUBWEAK EXTI0_IRQHandler + SECTION .text:CODE:REORDER(1) +EXTI0_IRQHandler + B EXTI0_IRQHandler + + PUBWEAK EXTI1_IRQHandler + SECTION .text:CODE:REORDER(1) +EXTI1_IRQHandler + B EXTI1_IRQHandler + + PUBWEAK EXTI2_IRQHandler + SECTION .text:CODE:REORDER(1) +EXTI2_IRQHandler + B EXTI2_IRQHandler + + PUBWEAK EXTI3_IRQHandler + SECTION .text:CODE:REORDER(1) +EXTI3_IRQHandler + B EXTI3_IRQHandler + + PUBWEAK EXTI4_IRQHandler + SECTION .text:CODE:REORDER(1) +EXTI4_IRQHandler + B EXTI4_IRQHandler + + PUBWEAK DMA1_Channel1_IRQHandler + SECTION .text:CODE:REORDER(1) +DMA1_Channel1_IRQHandler + B DMA1_Channel1_IRQHandler + + PUBWEAK DMA1_Channel2_IRQHandler + SECTION .text:CODE:REORDER(1) +DMA1_Channel2_IRQHandler + B DMA1_Channel2_IRQHandler + + PUBWEAK DMA1_Channel3_IRQHandler + SECTION .text:CODE:REORDER(1) +DMA1_Channel3_IRQHandler + B DMA1_Channel3_IRQHandler + + PUBWEAK DMA1_Channel4_IRQHandler + SECTION .text:CODE:REORDER(1) +DMA1_Channel4_IRQHandler + B DMA1_Channel4_IRQHandler + + PUBWEAK DMA1_Channel5_IRQHandler + SECTION .text:CODE:REORDER(1) +DMA1_Channel5_IRQHandler + B DMA1_Channel5_IRQHandler + + PUBWEAK DMA1_Channel6_IRQHandler + SECTION .text:CODE:REORDER(1) +DMA1_Channel6_IRQHandler + B DMA1_Channel6_IRQHandler + + PUBWEAK DMA1_Channel7_IRQHandler + SECTION .text:CODE:REORDER(1) +DMA1_Channel7_IRQHandler + B DMA1_Channel7_IRQHandler + + PUBWEAK ADC1_IRQHandler + SECTION .text:CODE:REORDER(1) +ADC1_IRQHandler + B ADC1_IRQHandler + + PUBWEAK EXTI9_5_IRQHandler + SECTION .text:CODE:REORDER(1) +EXTI9_5_IRQHandler + B EXTI9_5_IRQHandler + + PUBWEAK TIM1_BRK_TIM15_IRQHandler + SECTION .text:CODE:REORDER(1) +TIM1_BRK_TIM15_IRQHandler + B TIM1_BRK_TIM15_IRQHandler + + PUBWEAK TIM1_UP_TIM16_IRQHandler + SECTION .text:CODE:REORDER(1) +TIM1_UP_TIM16_IRQHandler + B TIM1_UP_TIM16_IRQHandler + + PUBWEAK TIM1_TRG_COM_TIM17_IRQHandler + SECTION .text:CODE:REORDER(1) +TIM1_TRG_COM_TIM17_IRQHandler + B TIM1_TRG_COM_TIM17_IRQHandler + + PUBWEAK TIM1_CC_IRQHandler + SECTION .text:CODE:REORDER(1) +TIM1_CC_IRQHandler + B TIM1_CC_IRQHandler + + PUBWEAK TIM2_IRQHandler + SECTION .text:CODE:REORDER(1) +TIM2_IRQHandler + B TIM2_IRQHandler + + PUBWEAK TIM3_IRQHandler + SECTION .text:CODE:REORDER(1) +TIM3_IRQHandler + B TIM3_IRQHandler + + PUBWEAK TIM4_IRQHandler + SECTION .text:CODE:REORDER(1) +TIM4_IRQHandler + B TIM4_IRQHandler + + PUBWEAK I2C1_EV_IRQHandler + SECTION .text:CODE:REORDER(1) +I2C1_EV_IRQHandler + B I2C1_EV_IRQHandler + + PUBWEAK I2C1_ER_IRQHandler + SECTION .text:CODE:REORDER(1) +I2C1_ER_IRQHandler + B I2C1_ER_IRQHandler + + PUBWEAK I2C2_EV_IRQHandler + SECTION .text:CODE:REORDER(1) +I2C2_EV_IRQHandler + B I2C2_EV_IRQHandler + + PUBWEAK I2C2_ER_IRQHandler + SECTION .text:CODE:REORDER(1) +I2C2_ER_IRQHandler + B I2C2_ER_IRQHandler + + PUBWEAK SPI1_IRQHandler + SECTION .text:CODE:REORDER(1) +SPI1_IRQHandler + B SPI1_IRQHandler + + PUBWEAK SPI2_IRQHandler + SECTION .text:CODE:REORDER(1) +SPI2_IRQHandler + B SPI2_IRQHandler + + PUBWEAK USART1_IRQHandler + SECTION .text:CODE:REORDER(1) +USART1_IRQHandler + B USART1_IRQHandler + + PUBWEAK USART2_IRQHandler + SECTION .text:CODE:REORDER(1) +USART2_IRQHandler + B USART2_IRQHandler + + PUBWEAK USART3_IRQHandler + SECTION .text:CODE:REORDER(1) +USART3_IRQHandler + B USART3_IRQHandler + + PUBWEAK EXTI15_10_IRQHandler + SECTION .text:CODE:REORDER(1) +EXTI15_10_IRQHandler + B EXTI15_10_IRQHandler + + PUBWEAK RTCAlarm_IRQHandler + SECTION .text:CODE:REORDER(1) +RTCAlarm_IRQHandler + B RTCAlarm_IRQHandler + + PUBWEAK CEC_IRQHandler + SECTION .text:CODE:REORDER(1) +CEC_IRQHandler + B CEC_IRQHandler + + PUBWEAK TIM12_IRQHandler + SECTION .text:CODE:REORDER(1) +TIM12_IRQHandler + B TIM12_IRQHandler + + PUBWEAK TIM13_IRQHandler + SECTION .text:CODE:REORDER(1) +TIM13_IRQHandler + B TIM13_IRQHandler + + PUBWEAK TIM14_IRQHandler + SECTION .text:CODE:REORDER(1) +TIM14_IRQHandler + B TIM14_IRQHandler + + PUBWEAK TIM5_IRQHandler + SECTION .text:CODE:REORDER(1) +TIM5_IRQHandler + B TIM5_IRQHandler + + PUBWEAK SPI3_IRQHandler + SECTION .text:CODE:REORDER(1) +SPI3_IRQHandler + B SPI3_IRQHandler + + PUBWEAK UART4_IRQHandler + SECTION .text:CODE:REORDER(1) +UART4_IRQHandler + B UART4_IRQHandler + + PUBWEAK UART5_IRQHandler + SECTION .text:CODE:REORDER(1) +UART5_IRQHandler + B UART5_IRQHandler + + PUBWEAK TIM6_DAC_IRQHandler + SECTION .text:CODE:REORDER(1) +TIM6_DAC_IRQHandler + B TIM6_DAC_IRQHandler + + PUBWEAK TIM7_IRQHandler + SECTION .text:CODE:REORDER(1) +TIM7_IRQHandler + B TIM7_IRQHandler + + PUBWEAK DMA2_Channel1_IRQHandler + SECTION .text:CODE:REORDER(1) +DMA2_Channel1_IRQHandler + B DMA2_Channel1_IRQHandler + + PUBWEAK DMA2_Channel2_IRQHandler + SECTION .text:CODE:REORDER(1) +DMA2_Channel2_IRQHandler + B DMA2_Channel2_IRQHandler + + PUBWEAK DMA2_Channel3_IRQHandler + SECTION .text:CODE:REORDER(1) +DMA2_Channel3_IRQHandler + B DMA2_Channel3_IRQHandler + + PUBWEAK DMA2_Channel4_5_IRQHandler + SECTION .text:CODE:REORDER(1) +DMA2_Channel4_5_IRQHandler + B DMA2_Channel4_5_IRQHandler + + PUBWEAK DMA2_Channel5_IRQHandler + SECTION .text:CODE:REORDER(1) +DMA2_Channel5_IRQHandler + B DMA2_Channel5_IRQHandler + + END +/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ diff --git a/Libraries/CMSIS/Device/ST/STM32F10x/Source/Templates/iar/startup_stm32f10x_ld.s b/Libraries/CMSIS/Device/ST/STM32F10x/Source/Templates/iar/startup_stm32f10x_ld.s new file mode 100644 index 0000000..cfbaa95 --- /dev/null +++ b/Libraries/CMSIS/Device/ST/STM32F10x/Source/Templates/iar/startup_stm32f10x_ld.s @@ -0,0 +1,373 @@ +;******************** (C) COPYRIGHT 2012 STMicroelectronics ******************** +;* File Name : startup_stm32f10x_ld.s +;* Author : MCD Application Team +;* Version : V3.6.1 +;* Date : 09-March-2012 +;* Description : STM32F10x Low Density Devices vector table for EWARM +;* toolchain. +;* This module performs: +;* - Set the initial SP +;* - Configure the clock system +;* - Set the initial PC == __iar_program_start, +;* - Set the vector table entries with the exceptions ISR +;* address. +;* After Reset the Cortex-M3 processor is in Thread mode, +;* priority is Privileged, and the Stack is set to Main. +;******************************************************************************** +;* +;* Licensed under MCD-ST Liberty SW License Agreement V2, (the "License"); +;* You may not use this file except in compliance with the License. +;* You may obtain a copy of the License at: +;* +;* http://www.st.com/software_license_agreement_liberty_v2 +;* +;* Unless required by applicable law or agreed to in writing, software +;* distributed under the License is distributed on an "AS IS" BASIS, +;* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +;* See the License for the specific language governing permissions and +;* limitations under the License. +;* +;******************************************************************************* +; +; +; The modules in this file are included in the libraries, and may be replaced +; by any user-defined modules that define the PUBLIC symbol _program_start or +; a user defined start symbol. +; To override the cstartup defined in the library, simply add your modified +; version to the workbench project. +; +; The vector table is normally located at address 0. +; When debugging in RAM, it can be located in RAM, aligned to at least 2^6. +; The name "__vector_table" has special meaning for C-SPY: +; it is where the SP start value is found, and the NVIC vector +; table register (VTOR) is initialized to this address if != 0. +; +; Cortex-M version +; + + MODULE ?cstartup + + ;; Forward declaration of sections. + SECTION CSTACK:DATA:NOROOT(3) + + SECTION .intvec:CODE:NOROOT(2) + + EXTERN __iar_program_start + EXTERN SystemInit + PUBLIC __vector_table + + DATA +__vector_table + DCD sfe(CSTACK) + DCD Reset_Handler ; Reset Handler + DCD NMI_Handler ; NMI Handler + DCD HardFault_Handler ; Hard Fault Handler + DCD MemManage_Handler ; MPU Fault Handler + DCD BusFault_Handler ; Bus Fault Handler + DCD UsageFault_Handler ; Usage Fault Handler + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD SVC_Handler ; SVCall Handler + DCD DebugMon_Handler ; Debug Monitor Handler + DCD 0 ; Reserved + DCD PendSV_Handler ; PendSV Handler + DCD SysTick_Handler ; SysTick Handler + + ; External Interrupts + DCD WWDG_IRQHandler ; Window Watchdog + DCD PVD_IRQHandler ; PVD through EXTI Line detect + DCD TAMPER_IRQHandler ; Tamper + DCD RTC_IRQHandler ; RTC + DCD FLASH_IRQHandler ; Flash + DCD RCC_IRQHandler ; RCC + DCD EXTI0_IRQHandler ; EXTI Line 0 + DCD EXTI1_IRQHandler ; EXTI Line 1 + DCD EXTI2_IRQHandler ; EXTI Line 2 + DCD EXTI3_IRQHandler ; EXTI Line 3 + DCD EXTI4_IRQHandler ; EXTI Line 4 + DCD DMA1_Channel1_IRQHandler ; DMA1 Channel 1 + DCD DMA1_Channel2_IRQHandler ; DMA1 Channel 2 + DCD DMA1_Channel3_IRQHandler ; DMA1 Channel 3 + DCD DMA1_Channel4_IRQHandler ; DMA1 Channel 4 + DCD DMA1_Channel5_IRQHandler ; DMA1 Channel 5 + DCD DMA1_Channel6_IRQHandler ; DMA1 Channel 6 + DCD DMA1_Channel7_IRQHandler ; DMA1 Channel 7 + DCD ADC1_2_IRQHandler ; ADC1 & ADC2 + DCD USB_HP_CAN1_TX_IRQHandler ; USB High Priority or CAN1 TX + DCD USB_LP_CAN1_RX0_IRQHandler ; USB Low Priority or CAN1 RX0 + DCD CAN1_RX1_IRQHandler ; CAN1 RX1 + DCD CAN1_SCE_IRQHandler ; CAN1 SCE + DCD EXTI9_5_IRQHandler ; EXTI Line 9..5 + DCD TIM1_BRK_IRQHandler ; TIM1 Break + DCD TIM1_UP_IRQHandler ; TIM1 Update + DCD TIM1_TRG_COM_IRQHandler ; TIM1 Trigger and Commutation + DCD TIM1_CC_IRQHandler ; TIM1 Capture Compare + DCD TIM2_IRQHandler ; TIM2 + DCD TIM3_IRQHandler ; TIM3 + DCD 0 ; Reserved + DCD I2C1_EV_IRQHandler ; I2C1 Event + DCD I2C1_ER_IRQHandler ; I2C1 Error + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD SPI1_IRQHandler ; SPI1 + DCD 0 ; Reserved + DCD USART1_IRQHandler ; USART1 + DCD USART2_IRQHandler ; USART2 + DCD 0 ; Reserved + DCD EXTI15_10_IRQHandler ; EXTI Line 15..10 + DCD RTCAlarm_IRQHandler ; RTC Alarm through EXTI Line + DCD USBWakeUp_IRQHandler ; USB Wakeup from suspend + +;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;; +;; +;; Default interrupt handlers. +;; + THUMB + + PUBWEAK Reset_Handler + SECTION .text:CODE:REORDER(2) +Reset_Handler + LDR R0, =SystemInit + BLX R0 + LDR R0, =__iar_program_start + BX R0 + + PUBWEAK NMI_Handler + SECTION .text:CODE:REORDER(1) +NMI_Handler + B NMI_Handler + + PUBWEAK HardFault_Handler + SECTION .text:CODE:REORDER(1) +HardFault_Handler + B HardFault_Handler + + PUBWEAK MemManage_Handler + SECTION .text:CODE:REORDER(1) +MemManage_Handler + B MemManage_Handler + + PUBWEAK BusFault_Handler + SECTION .text:CODE:REORDER(1) +BusFault_Handler + B BusFault_Handler + + PUBWEAK UsageFault_Handler + SECTION .text:CODE:REORDER(1) +UsageFault_Handler + B UsageFault_Handler + + PUBWEAK SVC_Handler + SECTION .text:CODE:REORDER(1) +SVC_Handler + B SVC_Handler + + PUBWEAK DebugMon_Handler + SECTION .text:CODE:REORDER(1) +DebugMon_Handler + B DebugMon_Handler + + PUBWEAK PendSV_Handler + SECTION .text:CODE:REORDER(1) +PendSV_Handler + B PendSV_Handler + + PUBWEAK SysTick_Handler + SECTION .text:CODE:REORDER(1) +SysTick_Handler + B SysTick_Handler + + PUBWEAK WWDG_IRQHandler + SECTION .text:CODE:REORDER(1) +WWDG_IRQHandler + B WWDG_IRQHandler + + PUBWEAK PVD_IRQHandler + SECTION .text:CODE:REORDER(1) +PVD_IRQHandler + B PVD_IRQHandler + + PUBWEAK TAMPER_IRQHandler + SECTION .text:CODE:REORDER(1) +TAMPER_IRQHandler + B TAMPER_IRQHandler + + PUBWEAK RTC_IRQHandler + SECTION .text:CODE:REORDER(1) +RTC_IRQHandler + B RTC_IRQHandler + + PUBWEAK FLASH_IRQHandler + SECTION .text:CODE:REORDER(1) +FLASH_IRQHandler + B FLASH_IRQHandler + + PUBWEAK RCC_IRQHandler + SECTION .text:CODE:REORDER(1) +RCC_IRQHandler + B RCC_IRQHandler + + PUBWEAK EXTI0_IRQHandler + SECTION .text:CODE:REORDER(1) +EXTI0_IRQHandler + B EXTI0_IRQHandler + + PUBWEAK EXTI1_IRQHandler + SECTION .text:CODE:REORDER(1) +EXTI1_IRQHandler + B EXTI1_IRQHandler + + PUBWEAK EXTI2_IRQHandler + SECTION .text:CODE:REORDER(1) +EXTI2_IRQHandler + B EXTI2_IRQHandler + + PUBWEAK EXTI3_IRQHandler + SECTION .text:CODE:REORDER(1) +EXTI3_IRQHandler + B EXTI3_IRQHandler + + PUBWEAK EXTI4_IRQHandler + SECTION .text:CODE:REORDER(1) +EXTI4_IRQHandler + B EXTI4_IRQHandler + + PUBWEAK DMA1_Channel1_IRQHandler + SECTION .text:CODE:REORDER(1) +DMA1_Channel1_IRQHandler + B DMA1_Channel1_IRQHandler + + PUBWEAK DMA1_Channel2_IRQHandler + SECTION .text:CODE:REORDER(1) +DMA1_Channel2_IRQHandler + B DMA1_Channel2_IRQHandler + + PUBWEAK DMA1_Channel3_IRQHandler + SECTION .text:CODE:REORDER(1) +DMA1_Channel3_IRQHandler + B DMA1_Channel3_IRQHandler + + PUBWEAK DMA1_Channel4_IRQHandler + SECTION .text:CODE:REORDER(1) +DMA1_Channel4_IRQHandler + B DMA1_Channel4_IRQHandler + + PUBWEAK DMA1_Channel5_IRQHandler + SECTION .text:CODE:REORDER(1) +DMA1_Channel5_IRQHandler + B DMA1_Channel5_IRQHandler + + PUBWEAK DMA1_Channel6_IRQHandler + SECTION .text:CODE:REORDER(1) +DMA1_Channel6_IRQHandler + B DMA1_Channel6_IRQHandler + + PUBWEAK DMA1_Channel7_IRQHandler + SECTION .text:CODE:REORDER(1) +DMA1_Channel7_IRQHandler + B DMA1_Channel7_IRQHandler + + PUBWEAK ADC1_2_IRQHandler + SECTION .text:CODE:REORDER(1) +ADC1_2_IRQHandler + B ADC1_2_IRQHandler + + PUBWEAK USB_HP_CAN1_TX_IRQHandler + SECTION .text:CODE:REORDER(1) +USB_HP_CAN1_TX_IRQHandler + B USB_HP_CAN1_TX_IRQHandler + + PUBWEAK USB_LP_CAN1_RX0_IRQHandler + SECTION .text:CODE:REORDER(1) +USB_LP_CAN1_RX0_IRQHandler + B USB_LP_CAN1_RX0_IRQHandler + + PUBWEAK CAN1_RX1_IRQHandler + SECTION .text:CODE:REORDER(1) +CAN1_RX1_IRQHandler + B CAN1_RX1_IRQHandler + + PUBWEAK CAN1_SCE_IRQHandler + SECTION .text:CODE:REORDER(1) +CAN1_SCE_IRQHandler + B CAN1_SCE_IRQHandler + + PUBWEAK EXTI9_5_IRQHandler + SECTION .text:CODE:REORDER(1) +EXTI9_5_IRQHandler + B EXTI9_5_IRQHandler + + PUBWEAK TIM1_BRK_IRQHandler + SECTION .text:CODE:REORDER(1) +TIM1_BRK_IRQHandler + B TIM1_BRK_IRQHandler + + PUBWEAK TIM1_UP_IRQHandler + SECTION .text:CODE:REORDER(1) +TIM1_UP_IRQHandler + B TIM1_UP_IRQHandler + + PUBWEAK TIM1_TRG_COM_IRQHandler + SECTION .text:CODE:REORDER(1) +TIM1_TRG_COM_IRQHandler + B TIM1_TRG_COM_IRQHandler + + PUBWEAK TIM1_CC_IRQHandler + SECTION .text:CODE:REORDER(1) +TIM1_CC_IRQHandler + B TIM1_CC_IRQHandler + + PUBWEAK TIM2_IRQHandler + SECTION .text:CODE:REORDER(1) +TIM2_IRQHandler + B TIM2_IRQHandler + + PUBWEAK TIM3_IRQHandler + SECTION .text:CODE:REORDER(1) +TIM3_IRQHandler + B TIM3_IRQHandler + + PUBWEAK I2C1_EV_IRQHandler + SECTION .text:CODE:REORDER(1) +I2C1_EV_IRQHandler + B I2C1_EV_IRQHandler + + PUBWEAK I2C1_ER_IRQHandler + SECTION .text:CODE:REORDER(1) +I2C1_ER_IRQHandler + B I2C1_ER_IRQHandler + + PUBWEAK SPI1_IRQHandler + SECTION .text:CODE:REORDER(1) +SPI1_IRQHandler + B SPI1_IRQHandler + + PUBWEAK USART1_IRQHandler + SECTION .text:CODE:REORDER(1) +USART1_IRQHandler + B USART1_IRQHandler + + PUBWEAK USART2_IRQHandler + SECTION .text:CODE:REORDER(1) +USART2_IRQHandler + B USART2_IRQHandler + + PUBWEAK EXTI15_10_IRQHandler + SECTION .text:CODE:REORDER(1) +EXTI15_10_IRQHandler + B EXTI15_10_IRQHandler + + PUBWEAK RTCAlarm_IRQHandler + SECTION .text:CODE:REORDER(1) +RTCAlarm_IRQHandler + B RTCAlarm_IRQHandler + + PUBWEAK USBWakeUp_IRQHandler + SECTION .text:CODE:REORDER(1) +USBWakeUp_IRQHandler + B USBWakeUp_IRQHandler + + END +/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ diff --git a/Libraries/CMSIS/Device/ST/STM32F10x/Source/Templates/iar/startup_stm32f10x_ld_vl.s b/Libraries/CMSIS/Device/ST/STM32F10x/Source/Templates/iar/startup_stm32f10x_ld_vl.s new file mode 100644 index 0000000..7cde5bb --- /dev/null +++ b/Libraries/CMSIS/Device/ST/STM32F10x/Source/Templates/iar/startup_stm32f10x_ld_vl.s @@ -0,0 +1,376 @@ +;******************** (C) COPYRIGHT 2012 STMicroelectronics ******************** +;* File Name : startup_stm32f10x_ld_vl.s +;* Author : MCD Application Team +;* Version : V3.6.1 +;* Date : 09-March-2012 +;* Description : STM32F10x Low Density Value Line Devices vector table +;* for EWARM toolchain. +;* This module performs: +;* - Set the initial SP +;* - Configure the clock system +;* - Set the initial PC == __iar_program_start, +;* - Set the vector table entries with the exceptions ISR +;* address. +;* After Reset the Cortex-M3 processor is in Thread mode, +;* priority is Privileged, and the Stack is set to Main. +;******************************************************************************** +;* +;* Licensed under MCD-ST Liberty SW License Agreement V2, (the "License"); +;* You may not use this file except in compliance with the License. +;* You may obtain a copy of the License at: +;* +;* http://www.st.com/software_license_agreement_liberty_v2 +;* +;* Unless required by applicable law or agreed to in writing, software +;* distributed under the License is distributed on an "AS IS" BASIS, +;* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +;* See the License for the specific language governing permissions and +;* limitations under the License. +;* +;******************************************************************************* +; +; +; The modules in this file are included in the libraries, and may be replaced +; by any user-defined modules that define the PUBLIC symbol _program_start or +; a user defined start symbol. +; To override the cstartup defined in the library, simply add your modified +; version to the workbench project. +; +; The vector table is normally located at address 0. +; When debugging in RAM, it can be located in RAM, aligned to at least 2^6. +; The name "__vector_table" has special meaning for C-SPY: +; it is where the SP start value is found, and the NVIC vector +; table register (VTOR) is initialized to this address if != 0. +; +; Cortex-M version +; + + MODULE ?cstartup + + ;; Forward declaration of sections. + SECTION CSTACK:DATA:NOROOT(3) + + SECTION .intvec:CODE:NOROOT(2) + + EXTERN __iar_program_start + EXTERN SystemInit + PUBLIC __vector_table + + DATA +__vector_table + DCD sfe(CSTACK) + DCD Reset_Handler ; Reset Handler + DCD NMI_Handler ; NMI Handler + DCD HardFault_Handler ; Hard Fault Handler + DCD MemManage_Handler ; MPU Fault Handler + DCD BusFault_Handler ; Bus Fault Handler + DCD UsageFault_Handler ; Usage Fault Handler + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD SVC_Handler ; SVCall Handler + DCD DebugMon_Handler ; Debug Monitor Handler + DCD 0 ; Reserved + DCD PendSV_Handler ; PendSV Handler + DCD SysTick_Handler ; SysTick Handler + + ; External Interrupts + DCD WWDG_IRQHandler ; Window Watchdog + DCD PVD_IRQHandler ; PVD through EXTI Line detect + DCD TAMPER_IRQHandler ; Tamper + DCD RTC_IRQHandler ; RTC + DCD FLASH_IRQHandler ; Flash + DCD RCC_IRQHandler ; RCC + DCD EXTI0_IRQHandler ; EXTI Line 0 + DCD EXTI1_IRQHandler ; EXTI Line 1 + DCD EXTI2_IRQHandler ; EXTI Line 2 + DCD EXTI3_IRQHandler ; EXTI Line 3 + DCD EXTI4_IRQHandler ; EXTI Line 4 + DCD DMA1_Channel1_IRQHandler ; DMA1 Channel 1 + DCD DMA1_Channel2_IRQHandler ; DMA1 Channel 2 + DCD DMA1_Channel3_IRQHandler ; DMA1 Channel 3 + DCD DMA1_Channel4_IRQHandler ; DMA1 Channel 4 + DCD DMA1_Channel5_IRQHandler ; DMA1 Channel 5 + DCD DMA1_Channel6_IRQHandler ; DMA1 Channel 6 + DCD DMA1_Channel7_IRQHandler ; DMA1 Channel 7 + DCD ADC1_IRQHandler ; ADC1 + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD EXTI9_5_IRQHandler ; EXTI Line 9..5 + DCD TIM1_BRK_TIM15_IRQHandler ; TIM1 Break and TIM15 + DCD TIM1_UP_TIM16_IRQHandler ; TIM1 Update and TIM16 + DCD TIM1_TRG_COM_TIM17_IRQHandler ; TIM1 Trigger and Commutation and TIM17 + DCD TIM1_CC_IRQHandler ; TIM1 Capture Compare + DCD TIM2_IRQHandler ; TIM2 + DCD TIM3_IRQHandler ; TIM3 + DCD 0 ; Reserved + DCD I2C1_EV_IRQHandler ; I2C1 Event + DCD I2C1_ER_IRQHandler ; I2C1 Error + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD SPI1_IRQHandler ; SPI1 + DCD 0 ; Reserved + DCD USART1_IRQHandler ; USART1 + DCD USART2_IRQHandler ; USART2 + DCD 0 ; Reserved + DCD EXTI15_10_IRQHandler ; EXTI Line 15..10 + DCD RTCAlarm_IRQHandler ; RTC Alarm through EXTI Line + DCD CEC_IRQHandler ; HDMI-CEC + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD TIM6_DAC_IRQHandler ; TIM6 and DAC underrun + DCD TIM7_IRQHandler ; TIM7 + +;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;; +;; +;; Default interrupt handlers. +;; + THUMB + + PUBWEAK Reset_Handler + SECTION .text:CODE:REORDER(2) +Reset_Handler + LDR R0, =SystemInit + BLX R0 + LDR R0, =__iar_program_start + BX R0 + + PUBWEAK NMI_Handler + SECTION .text:CODE:REORDER(1) +NMI_Handler + B NMI_Handler + + PUBWEAK HardFault_Handler + SECTION .text:CODE:REORDER(1) +HardFault_Handler + B HardFault_Handler + + PUBWEAK MemManage_Handler + SECTION .text:CODE:REORDER(1) +MemManage_Handler + B MemManage_Handler + + PUBWEAK BusFault_Handler + SECTION .text:CODE:REORDER(1) +BusFault_Handler + B BusFault_Handler + + PUBWEAK UsageFault_Handler + SECTION .text:CODE:REORDER(1) +UsageFault_Handler + B UsageFault_Handler + + PUBWEAK SVC_Handler + SECTION .text:CODE:REORDER(1) +SVC_Handler + B SVC_Handler + + PUBWEAK DebugMon_Handler + SECTION .text:CODE:REORDER(1) +DebugMon_Handler + B DebugMon_Handler + + PUBWEAK PendSV_Handler + SECTION .text:CODE:REORDER(1) +PendSV_Handler + B PendSV_Handler + + PUBWEAK SysTick_Handler + SECTION .text:CODE:REORDER(1) +SysTick_Handler + B SysTick_Handler + + PUBWEAK WWDG_IRQHandler + SECTION .text:CODE:REORDER(1) +WWDG_IRQHandler + B WWDG_IRQHandler + + PUBWEAK PVD_IRQHandler + SECTION .text:CODE:REORDER(1) +PVD_IRQHandler + B PVD_IRQHandler + + PUBWEAK TAMPER_IRQHandler + SECTION .text:CODE:REORDER(1) +TAMPER_IRQHandler + B TAMPER_IRQHandler + + PUBWEAK RTC_IRQHandler + SECTION .text:CODE:REORDER(1) +RTC_IRQHandler + B RTC_IRQHandler + + PUBWEAK FLASH_IRQHandler + SECTION .text:CODE:REORDER(1) +FLASH_IRQHandler + B FLASH_IRQHandler + + PUBWEAK RCC_IRQHandler + SECTION .text:CODE:REORDER(1) +RCC_IRQHandler + B RCC_IRQHandler + + PUBWEAK EXTI0_IRQHandler + SECTION .text:CODE:REORDER(1) +EXTI0_IRQHandler + B EXTI0_IRQHandler + + PUBWEAK EXTI1_IRQHandler + SECTION .text:CODE:REORDER(1) +EXTI1_IRQHandler + B EXTI1_IRQHandler + + PUBWEAK EXTI2_IRQHandler + SECTION .text:CODE:REORDER(1) +EXTI2_IRQHandler + B EXTI2_IRQHandler + + PUBWEAK EXTI3_IRQHandler + SECTION .text:CODE:REORDER(1) +EXTI3_IRQHandler + B EXTI3_IRQHandler + + PUBWEAK EXTI4_IRQHandler + SECTION .text:CODE:REORDER(1) +EXTI4_IRQHandler + B EXTI4_IRQHandler + + PUBWEAK DMA1_Channel1_IRQHandler + SECTION .text:CODE:REORDER(1) +DMA1_Channel1_IRQHandler + B DMA1_Channel1_IRQHandler + + PUBWEAK DMA1_Channel2_IRQHandler + SECTION .text:CODE:REORDER(1) +DMA1_Channel2_IRQHandler + B DMA1_Channel2_IRQHandler + + PUBWEAK DMA1_Channel3_IRQHandler + SECTION .text:CODE:REORDER(1) +DMA1_Channel3_IRQHandler + B DMA1_Channel3_IRQHandler + + PUBWEAK DMA1_Channel4_IRQHandler + SECTION .text:CODE:REORDER(1) +DMA1_Channel4_IRQHandler + B DMA1_Channel4_IRQHandler + + PUBWEAK DMA1_Channel5_IRQHandler + SECTION .text:CODE:REORDER(1) +DMA1_Channel5_IRQHandler + B DMA1_Channel5_IRQHandler + + PUBWEAK DMA1_Channel6_IRQHandler + SECTION .text:CODE:REORDER(1) +DMA1_Channel6_IRQHandler + B DMA1_Channel6_IRQHandler + + PUBWEAK DMA1_Channel7_IRQHandler + SECTION .text:CODE:REORDER(1) +DMA1_Channel7_IRQHandler + B DMA1_Channel7_IRQHandler + + PUBWEAK ADC1_IRQHandler + SECTION .text:CODE:REORDER(1) +ADC1_IRQHandler + B ADC1_IRQHandler + + PUBWEAK EXTI9_5_IRQHandler + SECTION .text:CODE:REORDER(1) +EXTI9_5_IRQHandler + B EXTI9_5_IRQHandler + + PUBWEAK TIM1_BRK_TIM15_IRQHandler + SECTION .text:CODE:REORDER(1) +TIM1_BRK_TIM15_IRQHandler + B TIM1_BRK_TIM15_IRQHandler + + PUBWEAK TIM1_UP_TIM16_IRQHandler + SECTION .text:CODE:REORDER(1) +TIM1_UP_TIM16_IRQHandler + B TIM1_UP_TIM16_IRQHandler + + PUBWEAK TIM1_TRG_COM_TIM17_IRQHandler + SECTION .text:CODE:REORDER(1) +TIM1_TRG_COM_TIM17_IRQHandler + B TIM1_TRG_COM_TIM17_IRQHandler + + PUBWEAK TIM1_CC_IRQHandler + SECTION .text:CODE:REORDER(1) +TIM1_CC_IRQHandler + B TIM1_CC_IRQHandler + + PUBWEAK TIM2_IRQHandler + SECTION .text:CODE:REORDER(1) +TIM2_IRQHandler + B TIM2_IRQHandler + + PUBWEAK TIM3_IRQHandler + SECTION .text:CODE:REORDER(1) +TIM3_IRQHandler + B TIM3_IRQHandler + + PUBWEAK I2C1_EV_IRQHandler + SECTION .text:CODE:REORDER(1) +I2C1_EV_IRQHandler + B I2C1_EV_IRQHandler + + PUBWEAK I2C1_ER_IRQHandler + SECTION .text:CODE:REORDER(1) +I2C1_ER_IRQHandler + B I2C1_ER_IRQHandler + + PUBWEAK SPI1_IRQHandler + SECTION .text:CODE:REORDER(1) +SPI1_IRQHandler + B SPI1_IRQHandler + + PUBWEAK USART1_IRQHandler + SECTION .text:CODE:REORDER(1) +USART1_IRQHandler + B USART1_IRQHandler + + PUBWEAK USART2_IRQHandler + SECTION .text:CODE:REORDER(1) +USART2_IRQHandler + B USART2_IRQHandler + + PUBWEAK EXTI15_10_IRQHandler + SECTION .text:CODE:REORDER(1) +EXTI15_10_IRQHandler + B EXTI15_10_IRQHandler + + PUBWEAK RTCAlarm_IRQHandler + SECTION .text:CODE:REORDER(1) +RTCAlarm_IRQHandler + B RTCAlarm_IRQHandler + + PUBWEAK CEC_IRQHandler + SECTION .text:CODE:REORDER(1) +CEC_IRQHandler + B CEC_IRQHandler + + PUBWEAK TIM6_DAC_IRQHandler + SECTION .text:CODE:REORDER(1) +TIM6_DAC_IRQHandler + B TIM6_DAC_IRQHandler + + PUBWEAK TIM7_IRQHandler + SECTION .text:CODE:REORDER(1) +TIM7_IRQHandler + B TIM7_IRQHandler + + END +/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ diff --git a/Libraries/CMSIS/Device/ST/STM32F10x/Source/Templates/iar/startup_stm32f10x_md.s b/Libraries/CMSIS/Device/ST/STM32F10x/Source/Templates/iar/startup_stm32f10x_md.s new file mode 100644 index 0000000..db28cda --- /dev/null +++ b/Libraries/CMSIS/Device/ST/STM32F10x/Source/Templates/iar/startup_stm32f10x_md.s @@ -0,0 +1,398 @@ +;******************** (C) COPYRIGHT 2012 STMicroelectronics ******************** +;* File Name : startup_stm32f10x_md.s +;* Author : MCD Application Team +;* Version : V3.6.1 +;* Date : 09-March-2012 +;* Description : STM32F10x Medium Density Devices vector table for +;* EWARM toolchain. +;* This module performs: +;* - Set the initial SP +;* - Configure the clock system +;* - Set the initial PC == __iar_program_start, +;* - Set the vector table entries with the exceptions ISR +;* address. +;* After Reset the Cortex-M3 processor is in Thread mode, +;* priority is Privileged, and the Stack is set to Main. +;******************************************************************************** +;* +;* Licensed under MCD-ST Liberty SW License Agreement V2, (the "License"); +;* You may not use this file except in compliance with the License. +;* You may obtain a copy of the License at: +;* +;* http://www.st.com/software_license_agreement_liberty_v2 +;* +;* Unless required by applicable law or agreed to in writing, software +;* distributed under the License is distributed on an "AS IS" BASIS, +;* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +;* See the License for the specific language governing permissions and +;* limitations under the License. +;* +;******************************************************************************* +; +; +; The modules in this file are included in the libraries, and may be replaced +; by any user-defined modules that define the PUBLIC symbol _program_start or +; a user defined start symbol. +; To override the cstartup defined in the library, simply add your modified +; version to the workbench project. +; +; The vector table is normally located at address 0. +; When debugging in RAM, it can be located in RAM, aligned to at least 2^6. +; The name "__vector_table" has special meaning for C-SPY: +; it is where the SP start value is found, and the NVIC vector +; table register (VTOR) is initialized to this address if != 0. +; +; Cortex-M version +; + + MODULE ?cstartup + + ;; Forward declaration of sections. + SECTION CSTACK:DATA:NOROOT(3) + + SECTION .intvec:CODE:NOROOT(2) + + EXTERN __iar_program_start + EXTERN SystemInit + PUBLIC __vector_table + + DATA +__vector_table + DCD sfe(CSTACK) + DCD Reset_Handler ; Reset Handler + DCD NMI_Handler ; NMI Handler + DCD HardFault_Handler ; Hard Fault Handler + DCD MemManage_Handler ; MPU Fault Handler + DCD BusFault_Handler ; Bus Fault Handler + DCD UsageFault_Handler ; Usage Fault Handler + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD SVC_Handler ; SVCall Handler + DCD DebugMon_Handler ; Debug Monitor Handler + DCD 0 ; Reserved + DCD PendSV_Handler ; PendSV Handler + DCD SysTick_Handler ; SysTick Handler + + ; External Interrupts + DCD WWDG_IRQHandler ; Window Watchdog + DCD PVD_IRQHandler ; PVD through EXTI Line detect + DCD TAMPER_IRQHandler ; Tamper + DCD RTC_IRQHandler ; RTC + DCD FLASH_IRQHandler ; Flash + DCD RCC_IRQHandler ; RCC + DCD EXTI0_IRQHandler ; EXTI Line 0 + DCD EXTI1_IRQHandler ; EXTI Line 1 + DCD EXTI2_IRQHandler ; EXTI Line 2 + DCD EXTI3_IRQHandler ; EXTI Line 3 + DCD EXTI4_IRQHandler ; EXTI Line 4 + DCD DMA1_Channel1_IRQHandler ; DMA1 Channel 1 + DCD DMA1_Channel2_IRQHandler ; DMA1 Channel 2 + DCD DMA1_Channel3_IRQHandler ; DMA1 Channel 3 + DCD DMA1_Channel4_IRQHandler ; DMA1 Channel 4 + DCD DMA1_Channel5_IRQHandler ; DMA1 Channel 5 + DCD DMA1_Channel6_IRQHandler ; DMA1 Channel 6 + DCD DMA1_Channel7_IRQHandler ; DMA1 Channel 7 + DCD ADC1_2_IRQHandler ; ADC1 & ADC2 + DCD USB_HP_CAN1_TX_IRQHandler ; USB High Priority or CAN1 TX + DCD USB_LP_CAN1_RX0_IRQHandler ; USB Low Priority or CAN1 RX0 + DCD CAN1_RX1_IRQHandler ; CAN1 RX1 + DCD CAN1_SCE_IRQHandler ; CAN1 SCE + DCD EXTI9_5_IRQHandler ; EXTI Line 9..5 + DCD TIM1_BRK_IRQHandler ; TIM1 Break + DCD TIM1_UP_IRQHandler ; TIM1 Update + DCD TIM1_TRG_COM_IRQHandler ; TIM1 Trigger and Commutation + DCD TIM1_CC_IRQHandler ; TIM1 Capture Compare + DCD TIM2_IRQHandler ; TIM2 + DCD TIM3_IRQHandler ; TIM3 + DCD TIM4_IRQHandler ; TIM4 + DCD I2C1_EV_IRQHandler ; I2C1 Event + DCD I2C1_ER_IRQHandler ; I2C1 Error + DCD I2C2_EV_IRQHandler ; I2C2 Event + DCD I2C2_ER_IRQHandler ; I2C2 Error + DCD SPI1_IRQHandler ; SPI1 + DCD SPI2_IRQHandler ; SPI2 + DCD USART1_IRQHandler ; USART1 + DCD USART2_IRQHandler ; USART2 + DCD USART3_IRQHandler ; USART3 + DCD EXTI15_10_IRQHandler ; EXTI Line 15..10 + DCD RTCAlarm_IRQHandler ; RTC Alarm through EXTI Line + DCD USBWakeUp_IRQHandler ; USB Wakeup from suspend + +;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;; +;; +;; Default interrupt handlers. +;; + THUMB + + PUBWEAK Reset_Handler + SECTION .text:CODE:REORDER(2) +Reset_Handler + LDR R0, =SystemInit + BLX R0 + LDR R0, =__iar_program_start + BX R0 + + PUBWEAK NMI_Handler + SECTION .text:CODE:REORDER(1) +NMI_Handler + B NMI_Handler + + PUBWEAK HardFault_Handler + SECTION .text:CODE:REORDER(1) +HardFault_Handler + B HardFault_Handler + + PUBWEAK MemManage_Handler + SECTION .text:CODE:REORDER(1) +MemManage_Handler + B MemManage_Handler + + PUBWEAK BusFault_Handler + SECTION .text:CODE:REORDER(1) +BusFault_Handler + B BusFault_Handler + + PUBWEAK UsageFault_Handler + SECTION .text:CODE:REORDER(1) +UsageFault_Handler + B UsageFault_Handler + + PUBWEAK SVC_Handler + SECTION .text:CODE:REORDER(1) +SVC_Handler + B SVC_Handler + + PUBWEAK DebugMon_Handler + SECTION .text:CODE:REORDER(1) +DebugMon_Handler + B DebugMon_Handler + + PUBWEAK PendSV_Handler + SECTION .text:CODE:REORDER(1) +PendSV_Handler + B PendSV_Handler + + PUBWEAK SysTick_Handler + SECTION .text:CODE:REORDER(1) +SysTick_Handler + B SysTick_Handler + + PUBWEAK WWDG_IRQHandler + SECTION .text:CODE:REORDER(1) +WWDG_IRQHandler + B WWDG_IRQHandler + + PUBWEAK PVD_IRQHandler + SECTION .text:CODE:REORDER(1) +PVD_IRQHandler + B PVD_IRQHandler + + PUBWEAK TAMPER_IRQHandler + SECTION .text:CODE:REORDER(1) +TAMPER_IRQHandler + B TAMPER_IRQHandler + + PUBWEAK RTC_IRQHandler + SECTION .text:CODE:REORDER(1) +RTC_IRQHandler + B RTC_IRQHandler + + PUBWEAK FLASH_IRQHandler + SECTION .text:CODE:REORDER(1) +FLASH_IRQHandler + B FLASH_IRQHandler + + PUBWEAK RCC_IRQHandler + SECTION .text:CODE:REORDER(1) +RCC_IRQHandler + B RCC_IRQHandler + + PUBWEAK EXTI0_IRQHandler + SECTION .text:CODE:REORDER(1) +EXTI0_IRQHandler + B EXTI0_IRQHandler + + PUBWEAK EXTI1_IRQHandler + SECTION .text:CODE:REORDER(1) +EXTI1_IRQHandler + B EXTI1_IRQHandler + + PUBWEAK EXTI2_IRQHandler + SECTION .text:CODE:REORDER(1) +EXTI2_IRQHandler + B EXTI2_IRQHandler + + PUBWEAK EXTI3_IRQHandler + SECTION .text:CODE:REORDER(1) +EXTI3_IRQHandler + B EXTI3_IRQHandler + + PUBWEAK EXTI4_IRQHandler + SECTION .text:CODE:REORDER(1) +EXTI4_IRQHandler + B EXTI4_IRQHandler + + PUBWEAK DMA1_Channel1_IRQHandler + SECTION .text:CODE:REORDER(1) +DMA1_Channel1_IRQHandler + B DMA1_Channel1_IRQHandler + + PUBWEAK DMA1_Channel2_IRQHandler + SECTION .text:CODE:REORDER(1) +DMA1_Channel2_IRQHandler + B DMA1_Channel2_IRQHandler + + PUBWEAK DMA1_Channel3_IRQHandler + SECTION .text:CODE:REORDER(1) +DMA1_Channel3_IRQHandler + B DMA1_Channel3_IRQHandler + + PUBWEAK DMA1_Channel4_IRQHandler + SECTION .text:CODE:REORDER(1) +DMA1_Channel4_IRQHandler + B DMA1_Channel4_IRQHandler + + PUBWEAK DMA1_Channel5_IRQHandler + SECTION .text:CODE:REORDER(1) +DMA1_Channel5_IRQHandler + B DMA1_Channel5_IRQHandler + + PUBWEAK DMA1_Channel6_IRQHandler + SECTION .text:CODE:REORDER(1) +DMA1_Channel6_IRQHandler + B DMA1_Channel6_IRQHandler + + PUBWEAK DMA1_Channel7_IRQHandler + SECTION .text:CODE:REORDER(1) +DMA1_Channel7_IRQHandler + B DMA1_Channel7_IRQHandler + + PUBWEAK ADC1_2_IRQHandler + SECTION .text:CODE:REORDER(1) +ADC1_2_IRQHandler + B ADC1_2_IRQHandler + + PUBWEAK USB_HP_CAN1_TX_IRQHandler + SECTION .text:CODE:REORDER(1) +USB_HP_CAN1_TX_IRQHandler + B USB_HP_CAN1_TX_IRQHandler + + PUBWEAK USB_LP_CAN1_RX0_IRQHandler + SECTION .text:CODE:REORDER(1) +USB_LP_CAN1_RX0_IRQHandler + B USB_LP_CAN1_RX0_IRQHandler + + PUBWEAK CAN1_RX1_IRQHandler + SECTION .text:CODE:REORDER(1) +CAN1_RX1_IRQHandler + B CAN1_RX1_IRQHandler + + PUBWEAK CAN1_SCE_IRQHandler + SECTION .text:CODE:REORDER(1) +CAN1_SCE_IRQHandler + B CAN1_SCE_IRQHandler + + PUBWEAK EXTI9_5_IRQHandler + SECTION .text:CODE:REORDER(1) +EXTI9_5_IRQHandler + B EXTI9_5_IRQHandler + + PUBWEAK TIM1_BRK_IRQHandler + SECTION .text:CODE:REORDER(1) +TIM1_BRK_IRQHandler + B TIM1_BRK_IRQHandler + + PUBWEAK TIM1_UP_IRQHandler + SECTION .text:CODE:REORDER(1) +TIM1_UP_IRQHandler + B TIM1_UP_IRQHandler + + PUBWEAK TIM1_TRG_COM_IRQHandler + SECTION .text:CODE:REORDER(1) +TIM1_TRG_COM_IRQHandler + B TIM1_TRG_COM_IRQHandler + + PUBWEAK TIM1_CC_IRQHandler + SECTION .text:CODE:REORDER(1) +TIM1_CC_IRQHandler + B TIM1_CC_IRQHandler + + PUBWEAK TIM2_IRQHandler + SECTION .text:CODE:REORDER(1) +TIM2_IRQHandler + B TIM2_IRQHandler + + PUBWEAK TIM3_IRQHandler + SECTION .text:CODE:REORDER(1) +TIM3_IRQHandler + B TIM3_IRQHandler + + PUBWEAK TIM4_IRQHandler + SECTION .text:CODE:REORDER(1) +TIM4_IRQHandler + B TIM4_IRQHandler + + PUBWEAK I2C1_EV_IRQHandler + SECTION .text:CODE:REORDER(1) +I2C1_EV_IRQHandler + B I2C1_EV_IRQHandler + + PUBWEAK I2C1_ER_IRQHandler + SECTION .text:CODE:REORDER(1) +I2C1_ER_IRQHandler + B I2C1_ER_IRQHandler + + PUBWEAK I2C2_EV_IRQHandler + SECTION .text:CODE:REORDER(1) +I2C2_EV_IRQHandler + B I2C2_EV_IRQHandler + + PUBWEAK I2C2_ER_IRQHandler + SECTION .text:CODE:REORDER(1) +I2C2_ER_IRQHandler + B I2C2_ER_IRQHandler + + PUBWEAK SPI1_IRQHandler + SECTION .text:CODE:REORDER(1) +SPI1_IRQHandler + B SPI1_IRQHandler + + PUBWEAK SPI2_IRQHandler + SECTION .text:CODE:REORDER(1) +SPI2_IRQHandler + B SPI2_IRQHandler + + PUBWEAK USART1_IRQHandler + SECTION .text:CODE:REORDER(1) +USART1_IRQHandler + B USART1_IRQHandler + + PUBWEAK USART2_IRQHandler + SECTION .text:CODE:REORDER(1) +USART2_IRQHandler + B USART2_IRQHandler + + PUBWEAK USART3_IRQHandler + SECTION .text:CODE:REORDER(1) +USART3_IRQHandler + B USART3_IRQHandler + + PUBWEAK EXTI15_10_IRQHandler + SECTION .text:CODE:REORDER(1) +EXTI15_10_IRQHandler + B EXTI15_10_IRQHandler + + PUBWEAK RTCAlarm_IRQHandler + SECTION .text:CODE:REORDER(1) +RTCAlarm_IRQHandler + B RTCAlarm_IRQHandler + + PUBWEAK USBWakeUp_IRQHandler + SECTION .text:CODE:REORDER(1) +USBWakeUp_IRQHandler + B USBWakeUp_IRQHandler + + END +/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ diff --git a/Libraries/CMSIS/Device/ST/STM32F10x/Source/Templates/iar/startup_stm32f10x_md_vl.s b/Libraries/CMSIS/Device/ST/STM32F10x/Source/Templates/iar/startup_stm32f10x_md_vl.s new file mode 100644 index 0000000..b4af984 --- /dev/null +++ b/Libraries/CMSIS/Device/ST/STM32F10x/Source/Templates/iar/startup_stm32f10x_md_vl.s @@ -0,0 +1,401 @@ +;******************** (C) COPYRIGHT 2012 STMicroelectronics ******************** +;* File Name : startup_stm32f10x_md_vl.s +;* Author : MCD Application Team +;* Version : V3.6.1 +;* Date : 09-March-2012 +;* Description : STM32F10x Medium Density Value Line Devices vector table +;* for EWARM toolchain. +;* This module performs: +;* - Set the initial SP +;* - Configure the clock system +;* - Set the initial PC == __iar_program_start, +;* - Set the vector table entries with the exceptions ISR +;* address. +;* After Reset the Cortex-M3 processor is in Thread mode, +;* priority is Privileged, and the Stack is set to Main. +;******************************************************************************** +;* +;* Licensed under MCD-ST Liberty SW License Agreement V2, (the "License"); +;* You may not use this file except in compliance with the License. +;* You may obtain a copy of the License at: +;* +;* http://www.st.com/software_license_agreement_liberty_v2 +;* +;* Unless required by applicable law or agreed to in writing, software +;* distributed under the License is distributed on an "AS IS" BASIS, +;* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +;* See the License for the specific language governing permissions and +;* limitations under the License. +;* +;******************************************************************************* +; +; +; The modules in this file are included in the libraries, and may be replaced +; by any user-defined modules that define the PUBLIC symbol _program_start or +; a user defined start symbol. +; To override the cstartup defined in the library, simply add your modified +; version to the workbench project. +; +; The vector table is normally located at address 0. +; When debugging in RAM, it can be located in RAM, aligned to at least 2^6. +; The name "__vector_table" has special meaning for C-SPY: +; it is where the SP start value is found, and the NVIC vector +; table register (VTOR) is initialized to this address if != 0. +; +; Cortex-M version +; + + MODULE ?cstartup + + ;; Forward declaration of sections. + SECTION CSTACK:DATA:NOROOT(3) + + SECTION .intvec:CODE:NOROOT(2) + + EXTERN __iar_program_start + EXTERN SystemInit + PUBLIC __vector_table + + DATA +__vector_table + DCD sfe(CSTACK) + DCD Reset_Handler ; Reset Handler + DCD NMI_Handler ; NMI Handler + DCD HardFault_Handler ; Hard Fault Handler + DCD MemManage_Handler ; MPU Fault Handler + DCD BusFault_Handler ; Bus Fault Handler + DCD UsageFault_Handler ; Usage Fault Handler + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD SVC_Handler ; SVCall Handler + DCD DebugMon_Handler ; Debug Monitor Handler + DCD 0 ; Reserved + DCD PendSV_Handler ; PendSV Handler + DCD SysTick_Handler ; SysTick Handler + + ; External Interrupts + DCD WWDG_IRQHandler ; Window Watchdog + DCD PVD_IRQHandler ; PVD through EXTI Line detect + DCD TAMPER_IRQHandler ; Tamper + DCD RTC_IRQHandler ; RTC + DCD FLASH_IRQHandler ; Flash + DCD RCC_IRQHandler ; RCC + DCD EXTI0_IRQHandler ; EXTI Line 0 + DCD EXTI1_IRQHandler ; EXTI Line 1 + DCD EXTI2_IRQHandler ; EXTI Line 2 + DCD EXTI3_IRQHandler ; EXTI Line 3 + DCD EXTI4_IRQHandler ; EXTI Line 4 + DCD DMA1_Channel1_IRQHandler ; DMA1 Channel 1 + DCD DMA1_Channel2_IRQHandler ; DMA1 Channel 2 + DCD DMA1_Channel3_IRQHandler ; DMA1 Channel 3 + DCD DMA1_Channel4_IRQHandler ; DMA1 Channel 4 + DCD DMA1_Channel5_IRQHandler ; DMA1 Channel 5 + DCD DMA1_Channel6_IRQHandler ; DMA1 Channel 6 + DCD DMA1_Channel7_IRQHandler ; DMA1 Channel 7 + DCD ADC1_IRQHandler ; ADC1 + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD EXTI9_5_IRQHandler ; EXTI Line 9..5 + DCD TIM1_BRK_TIM15_IRQHandler ; TIM1 Break and TIM15 + DCD TIM1_UP_TIM16_IRQHandler ; TIM1 Update and TIM16 + DCD TIM1_TRG_COM_TIM17_IRQHandler ; TIM1 Trigger and Commutation and TIM17 + DCD TIM1_CC_IRQHandler ; TIM1 Capture Compare + DCD TIM2_IRQHandler ; TIM2 + DCD TIM3_IRQHandler ; TIM3 + DCD TIM4_IRQHandler ; TIM4 + DCD I2C1_EV_IRQHandler ; I2C1 Event + DCD I2C1_ER_IRQHandler ; I2C1 Error + DCD I2C2_EV_IRQHandler ; I2C2 Event + DCD I2C2_ER_IRQHandler ; I2C2 Error + DCD SPI1_IRQHandler ; SPI1 + DCD SPI2_IRQHandler ; SPI2 + DCD USART1_IRQHandler ; USART1 + DCD USART2_IRQHandler ; USART2 + DCD USART3_IRQHandler ; USART3 + DCD EXTI15_10_IRQHandler ; EXTI Line 15..10 + DCD RTCAlarm_IRQHandler ; RTC Alarm through EXTI Line + DCD CEC_IRQHandler ; HDMI-CEC + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD TIM6_DAC_IRQHandler ; TIM6 and DAC underrun + DCD TIM7_IRQHandler ; TIM7 + +;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;; +;; +;; Default interrupt handlers. +;; + THUMB + + PUBWEAK Reset_Handler + SECTION .text:CODE:REORDER(2) +Reset_Handler + LDR R0, =SystemInit + BLX R0 + LDR R0, =__iar_program_start + BX R0 + + PUBWEAK NMI_Handler + SECTION .text:CODE:REORDER(1) +NMI_Handler + B NMI_Handler + + PUBWEAK HardFault_Handler + SECTION .text:CODE:REORDER(1) +HardFault_Handler + B HardFault_Handler + + PUBWEAK MemManage_Handler + SECTION .text:CODE:REORDER(1) +MemManage_Handler + B MemManage_Handler + + PUBWEAK BusFault_Handler + SECTION .text:CODE:REORDER(1) +BusFault_Handler + B BusFault_Handler + + PUBWEAK UsageFault_Handler + SECTION .text:CODE:REORDER(1) +UsageFault_Handler + B UsageFault_Handler + + PUBWEAK SVC_Handler + SECTION .text:CODE:REORDER(1) +SVC_Handler + B SVC_Handler + + PUBWEAK DebugMon_Handler + SECTION .text:CODE:REORDER(1) +DebugMon_Handler + B DebugMon_Handler + + PUBWEAK PendSV_Handler + SECTION .text:CODE:REORDER(1) +PendSV_Handler + B PendSV_Handler + + PUBWEAK SysTick_Handler + SECTION .text:CODE:REORDER(1) +SysTick_Handler + B SysTick_Handler + + PUBWEAK WWDG_IRQHandler + SECTION .text:CODE:REORDER(1) +WWDG_IRQHandler + B WWDG_IRQHandler + + PUBWEAK PVD_IRQHandler + SECTION .text:CODE:REORDER(1) +PVD_IRQHandler + B PVD_IRQHandler + + PUBWEAK TAMPER_IRQHandler + SECTION .text:CODE:REORDER(1) +TAMPER_IRQHandler + B TAMPER_IRQHandler + + PUBWEAK RTC_IRQHandler + SECTION .text:CODE:REORDER(1) +RTC_IRQHandler + B RTC_IRQHandler + + PUBWEAK FLASH_IRQHandler + SECTION .text:CODE:REORDER(1) +FLASH_IRQHandler + B FLASH_IRQHandler + + PUBWEAK RCC_IRQHandler + SECTION .text:CODE:REORDER(1) +RCC_IRQHandler + B RCC_IRQHandler + + PUBWEAK EXTI0_IRQHandler + SECTION .text:CODE:REORDER(1) +EXTI0_IRQHandler + B EXTI0_IRQHandler + + PUBWEAK EXTI1_IRQHandler + SECTION .text:CODE:REORDER(1) +EXTI1_IRQHandler + B EXTI1_IRQHandler + + PUBWEAK EXTI2_IRQHandler + SECTION .text:CODE:REORDER(1) +EXTI2_IRQHandler + B EXTI2_IRQHandler + + PUBWEAK EXTI3_IRQHandler + SECTION .text:CODE:REORDER(1) +EXTI3_IRQHandler + B EXTI3_IRQHandler + + PUBWEAK EXTI4_IRQHandler + SECTION .text:CODE:REORDER(1) +EXTI4_IRQHandler + B EXTI4_IRQHandler + + PUBWEAK DMA1_Channel1_IRQHandler + SECTION .text:CODE:REORDER(1) +DMA1_Channel1_IRQHandler + B DMA1_Channel1_IRQHandler + + PUBWEAK DMA1_Channel2_IRQHandler + SECTION .text:CODE:REORDER(1) +DMA1_Channel2_IRQHandler + B DMA1_Channel2_IRQHandler + + PUBWEAK DMA1_Channel3_IRQHandler + SECTION .text:CODE:REORDER(1) +DMA1_Channel3_IRQHandler + B DMA1_Channel3_IRQHandler + + PUBWEAK DMA1_Channel4_IRQHandler + SECTION .text:CODE:REORDER(1) +DMA1_Channel4_IRQHandler + B DMA1_Channel4_IRQHandler + + PUBWEAK DMA1_Channel5_IRQHandler + SECTION .text:CODE:REORDER(1) +DMA1_Channel5_IRQHandler + B DMA1_Channel5_IRQHandler + + PUBWEAK DMA1_Channel6_IRQHandler + SECTION .text:CODE:REORDER(1) +DMA1_Channel6_IRQHandler + B DMA1_Channel6_IRQHandler + + PUBWEAK DMA1_Channel7_IRQHandler + SECTION .text:CODE:REORDER(1) +DMA1_Channel7_IRQHandler + B DMA1_Channel7_IRQHandler + + PUBWEAK ADC1_IRQHandler + SECTION .text:CODE:REORDER(1) +ADC1_IRQHandler + B ADC1_IRQHandler + + PUBWEAK EXTI9_5_IRQHandler + SECTION .text:CODE:REORDER(1) +EXTI9_5_IRQHandler + B EXTI9_5_IRQHandler + + PUBWEAK TIM1_BRK_TIM15_IRQHandler + SECTION .text:CODE:REORDER(1) +TIM1_BRK_TIM15_IRQHandler + B TIM1_BRK_TIM15_IRQHandler + + PUBWEAK TIM1_UP_TIM16_IRQHandler + SECTION .text:CODE:REORDER(1) +TIM1_UP_TIM16_IRQHandler + B TIM1_UP_TIM16_IRQHandler + + PUBWEAK TIM1_TRG_COM_TIM17_IRQHandler + SECTION .text:CODE:REORDER(1) +TIM1_TRG_COM_TIM17_IRQHandler + B TIM1_TRG_COM_TIM17_IRQHandler + + PUBWEAK TIM1_CC_IRQHandler + SECTION .text:CODE:REORDER(1) +TIM1_CC_IRQHandler + B TIM1_CC_IRQHandler + + PUBWEAK TIM2_IRQHandler + SECTION .text:CODE:REORDER(1) +TIM2_IRQHandler + B TIM2_IRQHandler + + PUBWEAK TIM3_IRQHandler + SECTION .text:CODE:REORDER(1) +TIM3_IRQHandler + B TIM3_IRQHandler + + PUBWEAK TIM4_IRQHandler + SECTION .text:CODE:REORDER(1) +TIM4_IRQHandler + B TIM4_IRQHandler + + PUBWEAK I2C1_EV_IRQHandler + SECTION .text:CODE:REORDER(1) +I2C1_EV_IRQHandler + B I2C1_EV_IRQHandler + + PUBWEAK I2C1_ER_IRQHandler + SECTION .text:CODE:REORDER(1) +I2C1_ER_IRQHandler + B I2C1_ER_IRQHandler + + PUBWEAK I2C2_EV_IRQHandler + SECTION .text:CODE:REORDER(1) +I2C2_EV_IRQHandler + B I2C2_EV_IRQHandler + + PUBWEAK I2C2_ER_IRQHandler + SECTION .text:CODE:REORDER(1) +I2C2_ER_IRQHandler + B I2C2_ER_IRQHandler + + PUBWEAK SPI1_IRQHandler + SECTION .text:CODE:REORDER(1) +SPI1_IRQHandler + B SPI1_IRQHandler + + PUBWEAK SPI2_IRQHandler + SECTION .text:CODE:REORDER(1) +SPI2_IRQHandler + B SPI2_IRQHandler + + PUBWEAK USART1_IRQHandler + SECTION .text:CODE:REORDER(1) +USART1_IRQHandler + B USART1_IRQHandler + + PUBWEAK USART2_IRQHandler + SECTION .text:CODE:REORDER(1) +USART2_IRQHandler + B USART2_IRQHandler + + PUBWEAK USART3_IRQHandler + SECTION .text:CODE:REORDER(1) +USART3_IRQHandler + B USART3_IRQHandler + + PUBWEAK EXTI15_10_IRQHandler + SECTION .text:CODE:REORDER(1) +EXTI15_10_IRQHandler + B EXTI15_10_IRQHandler + + PUBWEAK RTCAlarm_IRQHandler + SECTION .text:CODE:REORDER(1) +RTCAlarm_IRQHandler + B RTCAlarm_IRQHandler + + PUBWEAK CEC_IRQHandler + SECTION .text:CODE:REORDER(1) +CEC_IRQHandler + B CEC_IRQHandler + + PUBWEAK TIM6_DAC_IRQHandler + SECTION .text:CODE:REORDER(1) +TIM6_DAC_IRQHandler + B TIM6_DAC_IRQHandler + + PUBWEAK TIM7_IRQHandler + SECTION .text:CODE:REORDER(1) +TIM7_IRQHandler + B TIM7_IRQHandler + + END +/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ diff --git a/Libraries/CMSIS/Device/ST/STM32F10x/Source/Templates/iar/startup_stm32f10x_xl.s b/Libraries/CMSIS/Device/ST/STM32F10x/Source/Templates/iar/startup_stm32f10x_xl.s new file mode 100644 index 0000000..c85fb39 --- /dev/null +++ b/Libraries/CMSIS/Device/ST/STM32F10x/Source/Templates/iar/startup_stm32f10x_xl.s @@ -0,0 +1,503 @@ +;******************** (C) COPYRIGHT 2012 STMicroelectronics ******************** +;* File Name : startup_stm32f10x_xl.s +;* Author : MCD Application Team +;* Version : V3.6.1 +;* Date : 09-March-2012 +;* Description : STM32F10x XL-Density Devices vector table for EWARM +;* toolchain. +;* This module performs: +;* - Set the initial SP +;* - Configure the clock system and the external SRAM +;* mounted on STM3210E-EVAL board to be used as data +;* memory (optional, to be enabled by user) +;* - Set the initial PC == __iar_program_start, +;* - Set the vector table entries with the exceptions ISR address, +;* After Reset the Cortex-M3 processor is in Thread mode, +;* priority is Privileged, and the Stack is set to Main. +;******************************************************************************** +;* +;* Licensed under MCD-ST Liberty SW License Agreement V2, (the "License"); +;* You may not use this file except in compliance with the License. +;* You may obtain a copy of the License at: +;* +;* http://www.st.com/software_license_agreement_liberty_v2 +;* +;* Unless required by applicable law or agreed to in writing, software +;* distributed under the License is distributed on an "AS IS" BASIS, +;* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +;* See the License for the specific language governing permissions and +;* limitations under the License. +;* +;******************************************************************************* +; +; +; The modules in this file are included in the libraries, and may be replaced +; by any user-defined modules that define the PUBLIC symbol _program_start or +; a user defined start symbol. +; To override the cstartup defined in the library, simply add your modified +; version to the workbench project. +; +; The vector table is normally located at address 0. +; When debugging in RAM, it can be located in RAM, aligned to at least 2^6. +; The name "__vector_table" has special meaning for C-SPY: +; it is where the SP start value is found, and the NVIC vector +; table register (VTOR) is initialized to this address if != 0. +; +; Cortex-M version +; + + MODULE ?cstartup + + ;; Forward declaration of sections. + SECTION CSTACK:DATA:NOROOT(3) + + SECTION .intvec:CODE:NOROOT(2) + + EXTERN __iar_program_start + EXTERN SystemInit + PUBLIC __vector_table + + DATA + +__vector_table + DCD sfe(CSTACK) + DCD Reset_Handler ; Reset Handler + DCD NMI_Handler ; NMI Handler + DCD HardFault_Handler ; Hard Fault Handler + DCD MemManage_Handler ; MPU Fault Handler + DCD BusFault_Handler ; Bus Fault Handler + DCD UsageFault_Handler ; Usage Fault Handler + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD SVC_Handler ; SVCall Handler + DCD DebugMon_Handler ; Debug Monitor Handler + DCD 0 ; Reserved + DCD PendSV_Handler ; PendSV Handler + DCD SysTick_Handler ; SysTick Handler + + ; External Interrupts + DCD WWDG_IRQHandler ; Window Watchdog + DCD PVD_IRQHandler ; PVD through EXTI Line detect + DCD TAMPER_IRQHandler ; Tamper + DCD RTC_IRQHandler ; RTC + DCD FLASH_IRQHandler ; Flash + DCD RCC_IRQHandler ; RCC + DCD EXTI0_IRQHandler ; EXTI Line 0 + DCD EXTI1_IRQHandler ; EXTI Line 1 + DCD EXTI2_IRQHandler ; EXTI Line 2 + DCD EXTI3_IRQHandler ; EXTI Line 3 + DCD EXTI4_IRQHandler ; EXTI Line 4 + DCD DMA1_Channel1_IRQHandler ; DMA1 Channel 1 + DCD DMA1_Channel2_IRQHandler ; DMA1 Channel 2 + DCD DMA1_Channel3_IRQHandler ; DMA1 Channel 3 + DCD DMA1_Channel4_IRQHandler ; DMA1 Channel 4 + DCD DMA1_Channel5_IRQHandler ; DMA1 Channel 5 + DCD DMA1_Channel6_IRQHandler ; DMA1 Channel 6 + DCD DMA1_Channel7_IRQHandler ; DMA1 Channel 7 + DCD ADC1_2_IRQHandler ; ADC1 & ADC2 + DCD USB_HP_CAN1_TX_IRQHandler ; USB High Priority or CAN1 TX + DCD USB_LP_CAN1_RX0_IRQHandler ; USB Low Priority or CAN1 RX0 + DCD CAN1_RX1_IRQHandler ; CAN1 RX1 + DCD CAN1_SCE_IRQHandler ; CAN1 SCE + DCD EXTI9_5_IRQHandler ; EXTI Line 9..5 + DCD TIM1_BRK_TIM9_IRQHandler ; TIM1 Break and TIM9 + DCD TIM1_UP_TIM10_IRQHandler ; TIM1 Update and TIM10 + DCD TIM1_TRG_COM_TIM11_IRQHandler ; TIM1 Trigger and Commutation and TIM11 + DCD TIM1_CC_IRQHandler ; TIM1 Capture Compare + DCD TIM2_IRQHandler ; TIM2 + DCD TIM3_IRQHandler ; TIM3 + DCD TIM4_IRQHandler ; TIM4 + DCD I2C1_EV_IRQHandler ; I2C1 Event + DCD I2C1_ER_IRQHandler ; I2C1 Error + DCD I2C2_EV_IRQHandler ; I2C2 Event + DCD I2C2_ER_IRQHandler ; I2C2 Error + DCD SPI1_IRQHandler ; SPI1 + DCD SPI2_IRQHandler ; SPI2 + DCD USART1_IRQHandler ; USART1 + DCD USART2_IRQHandler ; USART2 + DCD USART3_IRQHandler ; USART3 + DCD EXTI15_10_IRQHandler ; EXTI Line 15..10 + DCD RTCAlarm_IRQHandler ; RTC Alarm through EXTI Line + DCD USBWakeUp_IRQHandler ; USB Wakeup from suspend + DCD TIM8_BRK_TIM12_IRQHandler ; TIM8 Break and TIM12 + DCD TIM8_UP_TIM13_IRQHandler ; TIM8 Update and TIM13 + DCD TIM8_TRG_COM_TIM14_IRQHandler ; TIM8 Trigger and Commutation and TIM14 + DCD TIM8_CC_IRQHandler ; TIM8 Capture Compare + DCD ADC3_IRQHandler ; ADC3 + DCD FSMC_IRQHandler ; FSMC + DCD SDIO_IRQHandler ; SDIO + DCD TIM5_IRQHandler ; TIM5 + DCD SPI3_IRQHandler ; SPI3 + DCD UART4_IRQHandler ; UART4 + DCD UART5_IRQHandler ; UART5 + DCD TIM6_IRQHandler ; TIM6 + DCD TIM7_IRQHandler ; TIM7 + DCD DMA2_Channel1_IRQHandler ; DMA2 Channel1 + DCD DMA2_Channel2_IRQHandler ; DMA2 Channel2 + DCD DMA2_Channel3_IRQHandler ; DMA2 Channel3 + DCD DMA2_Channel4_5_IRQHandler ; DMA2 Channel4 & Channel5 +;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;; +;; +;; Default interrupt handlers. +;; + THUMB + + PUBWEAK Reset_Handler + SECTION .text:CODE:REORDER(2) +Reset_Handler + LDR R0, =SystemInit + BLX R0 + LDR R0, =__iar_program_start + BX R0 + + PUBWEAK NMI_Handler + SECTION .text:CODE:REORDER(1) +NMI_Handler + B NMI_Handler + + PUBWEAK HardFault_Handler + SECTION .text:CODE:REORDER(1) +HardFault_Handler + B HardFault_Handler + + PUBWEAK MemManage_Handler + SECTION .text:CODE:REORDER(1) +MemManage_Handler + B MemManage_Handler + + PUBWEAK BusFault_Handler + SECTION .text:CODE:REORDER(1) +BusFault_Handler + B BusFault_Handler + + PUBWEAK UsageFault_Handler + SECTION .text:CODE:REORDER(1) +UsageFault_Handler + B UsageFault_Handler + + PUBWEAK SVC_Handler + SECTION .text:CODE:REORDER(1) +SVC_Handler + B SVC_Handler + + PUBWEAK DebugMon_Handler + SECTION .text:CODE:REORDER(1) +DebugMon_Handler + B DebugMon_Handler + + PUBWEAK PendSV_Handler + SECTION .text:CODE:REORDER(1) +PendSV_Handler + B PendSV_Handler + + PUBWEAK SysTick_Handler + SECTION .text:CODE:REORDER(1) +SysTick_Handler + B SysTick_Handler + + PUBWEAK WWDG_IRQHandler + SECTION .text:CODE:REORDER(1) +WWDG_IRQHandler + B WWDG_IRQHandler + + PUBWEAK PVD_IRQHandler + SECTION .text:CODE:REORDER(1) +PVD_IRQHandler + B PVD_IRQHandler + + PUBWEAK TAMPER_IRQHandler + SECTION .text:CODE:REORDER(1) +TAMPER_IRQHandler + B TAMPER_IRQHandler + + PUBWEAK RTC_IRQHandler + SECTION .text:CODE:REORDER(1) +RTC_IRQHandler + B RTC_IRQHandler + + PUBWEAK FLASH_IRQHandler + SECTION .text:CODE:REORDER(1) +FLASH_IRQHandler + B FLASH_IRQHandler + + PUBWEAK RCC_IRQHandler + SECTION .text:CODE:REORDER(1) +RCC_IRQHandler + B RCC_IRQHandler + + PUBWEAK EXTI0_IRQHandler + SECTION .text:CODE:REORDER(1) +EXTI0_IRQHandler + B EXTI0_IRQHandler + + PUBWEAK EXTI1_IRQHandler + SECTION .text:CODE:REORDER(1) +EXTI1_IRQHandler + B EXTI1_IRQHandler + + PUBWEAK EXTI2_IRQHandler + SECTION .text:CODE:REORDER(1) +EXTI2_IRQHandler + B EXTI2_IRQHandler + + PUBWEAK EXTI3_IRQHandler + SECTION .text:CODE:REORDER(1) +EXTI3_IRQHandler + B EXTI3_IRQHandler + + PUBWEAK EXTI4_IRQHandler + SECTION .text:CODE:REORDER(1) +EXTI4_IRQHandler + B EXTI4_IRQHandler + + PUBWEAK DMA1_Channel1_IRQHandler + SECTION .text:CODE:REORDER(1) +DMA1_Channel1_IRQHandler + B DMA1_Channel1_IRQHandler + + PUBWEAK DMA1_Channel2_IRQHandler + SECTION .text:CODE:REORDER(1) +DMA1_Channel2_IRQHandler + B DMA1_Channel2_IRQHandler + + PUBWEAK DMA1_Channel3_IRQHandler + SECTION .text:CODE:REORDER(1) +DMA1_Channel3_IRQHandler + B DMA1_Channel3_IRQHandler + + PUBWEAK DMA1_Channel4_IRQHandler + SECTION .text:CODE:REORDER(1) +DMA1_Channel4_IRQHandler + B DMA1_Channel4_IRQHandler + + PUBWEAK DMA1_Channel5_IRQHandler + SECTION .text:CODE:REORDER(1) +DMA1_Channel5_IRQHandler + B DMA1_Channel5_IRQHandler + + PUBWEAK DMA1_Channel6_IRQHandler + SECTION .text:CODE:REORDER(1) +DMA1_Channel6_IRQHandler + B DMA1_Channel6_IRQHandler + + PUBWEAK DMA1_Channel7_IRQHandler + SECTION .text:CODE:REORDER(1) +DMA1_Channel7_IRQHandler + B DMA1_Channel7_IRQHandler + + PUBWEAK ADC1_2_IRQHandler + SECTION .text:CODE:REORDER(1) +ADC1_2_IRQHandler + B ADC1_2_IRQHandler + + PUBWEAK USB_HP_CAN1_TX_IRQHandler + SECTION .text:CODE:REORDER(1) +USB_HP_CAN1_TX_IRQHandler + B USB_HP_CAN1_TX_IRQHandler + + PUBWEAK USB_LP_CAN1_RX0_IRQHandler + SECTION .text:CODE:REORDER(1) +USB_LP_CAN1_RX0_IRQHandler + B USB_LP_CAN1_RX0_IRQHandler + + PUBWEAK CAN1_RX1_IRQHandler + SECTION .text:CODE:REORDER(1) +CAN1_RX1_IRQHandler + B CAN1_RX1_IRQHandler + + PUBWEAK CAN1_SCE_IRQHandler + SECTION .text:CODE:REORDER(1) +CAN1_SCE_IRQHandler + B CAN1_SCE_IRQHandler + + PUBWEAK EXTI9_5_IRQHandler + SECTION .text:CODE:REORDER(1) +EXTI9_5_IRQHandler + B EXTI9_5_IRQHandler + + PUBWEAK TIM1_BRK_TIM9_IRQHandler + SECTION .text:CODE:REORDER(1) +TIM1_BRK_TIM9_IRQHandler + B TIM1_BRK_TIM9_IRQHandler + + PUBWEAK TIM1_UP_TIM10_IRQHandler + SECTION .text:CODE:REORDER(1) +TIM1_UP_TIM10_IRQHandler + B TIM1_UP_TIM10_IRQHandler + + PUBWEAK TIM1_TRG_COM_TIM11_IRQHandler + SECTION .text:CODE:REORDER(1) +TIM1_TRG_COM_TIM11_IRQHandler + B TIM1_TRG_COM_TIM11_IRQHandler + + PUBWEAK TIM1_CC_IRQHandler + SECTION .text:CODE:REORDER(1) +TIM1_CC_IRQHandler + B TIM1_CC_IRQHandler + + PUBWEAK TIM2_IRQHandler + SECTION .text:CODE:REORDER(1) +TIM2_IRQHandler + B TIM2_IRQHandler + + PUBWEAK TIM3_IRQHandler + SECTION .text:CODE:REORDER(1) +TIM3_IRQHandler + B TIM3_IRQHandler + + PUBWEAK TIM4_IRQHandler + SECTION .text:CODE:REORDER(1) +TIM4_IRQHandler + B TIM4_IRQHandler + + PUBWEAK I2C1_EV_IRQHandler + SECTION .text:CODE:REORDER(1) +I2C1_EV_IRQHandler + B I2C1_EV_IRQHandler + + PUBWEAK I2C1_ER_IRQHandler + SECTION .text:CODE:REORDER(1) +I2C1_ER_IRQHandler + B I2C1_ER_IRQHandler + + PUBWEAK I2C2_EV_IRQHandler + SECTION .text:CODE:REORDER(1) +I2C2_EV_IRQHandler + B I2C2_EV_IRQHandler + + PUBWEAK I2C2_ER_IRQHandler + SECTION .text:CODE:REORDER(1) +I2C2_ER_IRQHandler + B I2C2_ER_IRQHandler + + PUBWEAK SPI1_IRQHandler + SECTION .text:CODE:REORDER(1) +SPI1_IRQHandler + B SPI1_IRQHandler + + PUBWEAK SPI2_IRQHandler + SECTION .text:CODE:REORDER(1) +SPI2_IRQHandler + B SPI2_IRQHandler + + PUBWEAK USART1_IRQHandler + SECTION .text:CODE:REORDER(1) +USART1_IRQHandler + B USART1_IRQHandler + + PUBWEAK USART2_IRQHandler + SECTION .text:CODE:REORDER(1) +USART2_IRQHandler + B USART2_IRQHandler + + PUBWEAK USART3_IRQHandler + SECTION .text:CODE:REORDER(1) +USART3_IRQHandler + B USART3_IRQHandler + + PUBWEAK EXTI15_10_IRQHandler + SECTION .text:CODE:REORDER(1) +EXTI15_10_IRQHandler + B EXTI15_10_IRQHandler + + PUBWEAK RTCAlarm_IRQHandler + SECTION .text:CODE:REORDER(1) +RTCAlarm_IRQHandler + B RTCAlarm_IRQHandler + + PUBWEAK USBWakeUp_IRQHandler + SECTION .text:CODE:REORDER(1) +USBWakeUp_IRQHandler + B USBWakeUp_IRQHandler + + PUBWEAK TIM8_BRK_TIM12_IRQHandler + SECTION .text:CODE:REORDER(1) +TIM8_BRK_TIM12_IRQHandler + B TIM8_BRK_TIM12_IRQHandler + + PUBWEAK TIM8_UP_TIM13_IRQHandler + SECTION .text:CODE:REORDER(1) +TIM8_UP_TIM13_IRQHandler + B TIM8_UP_TIM13_IRQHandler + + PUBWEAK TIM8_TRG_COM_TIM14_IRQHandler + SECTION .text:CODE:REORDER(1) +TIM8_TRG_COM_TIM14_IRQHandler + B TIM8_TRG_COM_TIM14_IRQHandler + + PUBWEAK TIM8_CC_IRQHandler + SECTION .text:CODE:REORDER(1) +TIM8_CC_IRQHandler + B TIM8_CC_IRQHandler + + PUBWEAK ADC3_IRQHandler + SECTION .text:CODE:REORDER(1) +ADC3_IRQHandler + B ADC3_IRQHandler + + PUBWEAK FSMC_IRQHandler + SECTION .text:CODE:REORDER(1) +FSMC_IRQHandler + B FSMC_IRQHandler + + PUBWEAK SDIO_IRQHandler + SECTION .text:CODE:REORDER(1) +SDIO_IRQHandler + B SDIO_IRQHandler + + PUBWEAK TIM5_IRQHandler + SECTION .text:CODE:REORDER(1) +TIM5_IRQHandler + B TIM5_IRQHandler + + PUBWEAK SPI3_IRQHandler + SECTION .text:CODE:REORDER(1) +SPI3_IRQHandler + B SPI3_IRQHandler + + PUBWEAK UART4_IRQHandler + SECTION .text:CODE:REORDER(1) +UART4_IRQHandler + B UART4_IRQHandler + + PUBWEAK UART5_IRQHandler + SECTION .text:CODE:REORDER(1) +UART5_IRQHandler + B UART5_IRQHandler + + PUBWEAK TIM6_IRQHandler + SECTION .text:CODE:REORDER(1) +TIM6_IRQHandler + B TIM6_IRQHandler + + PUBWEAK TIM7_IRQHandler + SECTION .text:CODE:REORDER(1) +TIM7_IRQHandler + B TIM7_IRQHandler + + PUBWEAK DMA2_Channel1_IRQHandler + SECTION .text:CODE:REORDER(1) +DMA2_Channel1_IRQHandler + B DMA2_Channel1_IRQHandler + + PUBWEAK DMA2_Channel2_IRQHandler + SECTION .text:CODE:REORDER(1) +DMA2_Channel2_IRQHandler + B DMA2_Channel2_IRQHandler + + PUBWEAK DMA2_Channel3_IRQHandler + SECTION .text:CODE:REORDER(1) +DMA2_Channel3_IRQHandler + B DMA2_Channel3_IRQHandler + + PUBWEAK DMA2_Channel4_5_IRQHandler + SECTION .text:CODE:REORDER(1) +DMA2_Channel4_5_IRQHandler + B DMA2_Channel4_5_IRQHandler + + + END + +/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ diff --git a/Libraries/CMSIS/Device/ST/STM32F10x/Source/Templates/system_stm32f10x.c b/Libraries/CMSIS/Device/ST/STM32F10x/Source/Templates/system_stm32f10x.c new file mode 100644 index 0000000..c0489e7 --- /dev/null +++ b/Libraries/CMSIS/Device/ST/STM32F10x/Source/Templates/system_stm32f10x.c @@ -0,0 +1,1100 @@ +/** + ****************************************************************************** + * @file system_stm32f10x.c + * @author MCD Application Team + * @version V3.6.1 + * @date 09-March-2012 + * @brief CMSIS Cortex-M3 Device Peripheral Access Layer System Source File. + * + * 1. This file provides two functions and one global variable to be called from + * user application: + * - SystemInit(): Setups the system clock (System clock source, PLL Multiplier + * factors, AHB/APBx prescalers and Flash settings). + * This function is called at startup just after reset and + * before branch to main program. This call is made inside + * the "startup_stm32f10x_xx.s" file. + * + * - SystemCoreClock variable: Contains the core clock (HCLK), it can be used + * by the user application to setup the SysTick + * timer or configure other parameters. + * + * - SystemCoreClockUpdate(): Updates the variable SystemCoreClock and must + * be called whenever the core clock is changed + * during program execution. + * + * 2. After each device reset the HSI (8 MHz) is used as system clock source. + * Then SystemInit() function is called, in "startup_stm32f10x_xx.s" file, to + * configure the system clock before to branch to main program. + * + * 3. If the system clock source selected by user fails to startup, the SystemInit() + * function will do nothing and HSI still used as system clock source. User can + * add some code to deal with this issue inside the SetSysClock() function. + * + * 4. The default value of HSE crystal is set to 8 MHz (or 25 MHz, depedning on + * the product used), refer to "HSE_VALUE" define in "stm32f10x.h" file. + * When HSE is used as system clock source, directly or through PLL, and you + * are using different crystal you have to adapt the HSE value to your own + * configuration. + * + ****************************************************************************** + * @attention + * + *

© COPYRIGHT 2012 STMicroelectronics

+ * + * Licensed under MCD-ST Liberty SW License Agreement V2, (the "License"); + * You may not use this file except in compliance with the License. + * You may obtain a copy of the License at: + * + * http://www.st.com/software_license_agreement_liberty_v2 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, + * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + * + ****************************************************************************** + */ + +/** @addtogroup CMSIS + * @{ + */ + +/** @addtogroup stm32f10x_system + * @{ + */ + +/** @addtogroup STM32F10x_System_Private_Includes + * @{ + */ + +#include "stm32f10x.h" + +/** + * @} + */ + +/** @addtogroup STM32F10x_System_Private_TypesDefinitions + * @{ + */ + +/** + * @} + */ + +/** @addtogroup STM32F10x_System_Private_Defines + * @{ + */ + +/*!< Uncomment the line corresponding to the desired System clock (SYSCLK) + frequency (after reset the HSI is used as SYSCLK source) + + IMPORTANT NOTE: + ============== + 1. After each device reset the HSI is used as System clock source. + + 2. Please make sure that the selected System clock doesn't exceed your device's + maximum frequency. + + 3. If none of the define below is enabled, the HSI is used as System clock + source. + + 4. The System clock configuration functions provided within this file assume that: + - For Low, Medium and High density Value line devices an external 8MHz + crystal is used to drive the System clock. + - For Low, Medium and High density devices an external 8MHz crystal is + used to drive the System clock. + - For Connectivity line devices an external 25MHz crystal is used to drive + the System clock. + If you are using different crystal you have to adapt those functions accordingly. + */ + +#if defined (STM32F10X_LD_VL) || (defined STM32F10X_MD_VL) || (defined STM32F10X_HD_VL) +/* #define SYSCLK_FREQ_HSE HSE_VALUE */ + #define SYSCLK_FREQ_24MHz 24000000 +#else +/* #define SYSCLK_FREQ_HSE HSE_VALUE */ +/* #define SYSCLK_FREQ_24MHz 24000000 */ +/* #define SYSCLK_FREQ_36MHz 36000000 */ +/* #define SYSCLK_FREQ_48MHz 48000000 */ +/* #define SYSCLK_FREQ_56MHz 56000000 */ +#define SYSCLK_FREQ_72MHz 72000000 +#endif + +/*!< Uncomment the following line if you need to use external SRAM mounted + on STM3210E-EVAL board (STM32 High density and XL-density devices) or on + STM32100E-EVAL board (STM32 High-density value line devices) as data memory */ +#if defined (STM32F10X_HD) || (defined STM32F10X_XL) || (defined STM32F10X_HD_VL) +/* #define DATA_IN_ExtSRAM */ +#endif + +/*!< Uncomment the following line if you need to relocate your vector Table in + Internal SRAM. */ +/* #define VECT_TAB_SRAM */ +#define VECT_TAB_OFFSET 0x0 /*!< Vector Table base offset field. + This value must be a multiple of 0x200. */ + + +/** + * @} + */ + +/** @addtogroup STM32F10x_System_Private_Macros + * @{ + */ + +/** + * @} + */ + +/** @addtogroup STM32F10x_System_Private_Variables + * @{ + */ + +/******************************************************************************* +* Clock Definitions +*******************************************************************************/ +#ifdef SYSCLK_FREQ_HSE + uint32_t SystemCoreClock = SYSCLK_FREQ_HSE; /*!< System Clock Frequency (Core Clock) */ +#elif defined SYSCLK_FREQ_24MHz + uint32_t SystemCoreClock = SYSCLK_FREQ_24MHz; /*!< System Clock Frequency (Core Clock) */ +#elif defined SYSCLK_FREQ_36MHz + uint32_t SystemCoreClock = SYSCLK_FREQ_36MHz; /*!< System Clock Frequency (Core Clock) */ +#elif defined SYSCLK_FREQ_48MHz + uint32_t SystemCoreClock = SYSCLK_FREQ_48MHz; /*!< System Clock Frequency (Core Clock) */ +#elif defined SYSCLK_FREQ_56MHz + uint32_t SystemCoreClock = SYSCLK_FREQ_56MHz; /*!< System Clock Frequency (Core Clock) */ +#elif defined SYSCLK_FREQ_72MHz + uint32_t SystemCoreClock = SYSCLK_FREQ_72MHz; /*!< System Clock Frequency (Core Clock) */ +#else /*!< HSI Selected as System Clock source */ + uint32_t SystemCoreClock = HSI_VALUE; /*!< System Clock Frequency (Core Clock) */ +#endif + +__I uint8_t AHBPrescTable[16] = {0, 0, 0, 0, 0, 0, 0, 0, 1, 2, 3, 4, 6, 7, 8, 9}; +/** + * @} + */ + +/** @addtogroup STM32F10x_System_Private_FunctionPrototypes + * @{ + */ + +static void SetSysClock(void); + +#ifdef SYSCLK_FREQ_HSE + static void SetSysClockToHSE(void); +#elif defined SYSCLK_FREQ_24MHz + static void SetSysClockTo24(void); +#elif defined SYSCLK_FREQ_36MHz + static void SetSysClockTo36(void); +#elif defined SYSCLK_FREQ_48MHz + static void SetSysClockTo48(void); +#elif defined SYSCLK_FREQ_56MHz + static void SetSysClockTo56(void); +#elif defined SYSCLK_FREQ_72MHz + static void SetSysClockTo72(void); +#endif + +#ifdef DATA_IN_ExtSRAM + static void SystemInit_ExtMemCtl(void); +#endif /* DATA_IN_ExtSRAM */ + +/** + * @} + */ + +/** @addtogroup STM32F10x_System_Private_Functions + * @{ + */ + +/** + * @brief Setup the microcontroller system + * Initialize the Embedded Flash Interface, the PLL and update the + * SystemCoreClock variable. + * @note This function should be used only after reset. + * @param None + * @retval None + */ +void SystemInit (void) +{ + /* Reset the RCC clock configuration to the default reset state(for debug purpose) */ + /* Set HSION bit */ + RCC->CR |= (uint32_t)0x00000001; + + /* Reset SW, HPRE, PPRE1, PPRE2, ADCPRE and MCO bits */ +#ifndef STM32F10X_CL + RCC->CFGR &= (uint32_t)0xF8FF0000; +#else + RCC->CFGR &= (uint32_t)0xF0FF0000; +#endif /* STM32F10X_CL */ + + /* Reset HSEON, CSSON and PLLON bits */ + RCC->CR &= (uint32_t)0xFEF6FFFF; + + /* Reset HSEBYP bit */ + RCC->CR &= (uint32_t)0xFFFBFFFF; + + /* Reset PLLSRC, PLLXTPRE, PLLMUL and USBPRE/OTGFSPRE bits */ + RCC->CFGR &= (uint32_t)0xFF80FFFF; + +#ifdef STM32F10X_CL + /* Reset PLL2ON and PLL3ON bits */ + RCC->CR &= (uint32_t)0xEBFFFFFF; + + /* Disable all interrupts and clear pending bits */ + RCC->CIR = 0x00FF0000; + + /* Reset CFGR2 register */ + RCC->CFGR2 = 0x00000000; +#elif defined (STM32F10X_LD_VL) || defined (STM32F10X_MD_VL) || (defined STM32F10X_HD_VL) + /* Disable all interrupts and clear pending bits */ + RCC->CIR = 0x009F0000; + + /* Reset CFGR2 register */ + RCC->CFGR2 = 0x00000000; +#else + /* Disable all interrupts and clear pending bits */ + RCC->CIR = 0x009F0000; +#endif /* STM32F10X_CL */ + +#if defined (STM32F10X_HD) || (defined STM32F10X_XL) || (defined STM32F10X_HD_VL) + #ifdef DATA_IN_ExtSRAM + SystemInit_ExtMemCtl(); + #endif /* DATA_IN_ExtSRAM */ +#endif + + /* Configure the System clock frequency, HCLK, PCLK2 and PCLK1 prescalers */ + /* Configure the Flash Latency cycles and enable prefetch buffer */ + SetSysClock(); + +#ifdef VECT_TAB_SRAM + SCB->VTOR = SRAM_BASE | VECT_TAB_OFFSET; /* Vector Table Relocation in Internal SRAM. */ +#else + SCB->VTOR = FLASH_BASE | VECT_TAB_OFFSET; /* Vector Table Relocation in Internal FLASH. */ +#endif +} + +/** + * @brief Update SystemCoreClock variable according to Clock Register Values. + * The SystemCoreClock variable contains the core clock (HCLK), it can + * be used by the user application to setup the SysTick timer or configure + * other parameters. + * + * @note Each time the core clock (HCLK) changes, this function must be called + * to update SystemCoreClock variable value. Otherwise, any configuration + * based on this variable will be incorrect. + * + * @note - The system frequency computed by this function is not the real + * frequency in the chip. It is calculated based on the predefined + * constant and the selected clock source: + * + * - If SYSCLK source is HSI, SystemCoreClock will contain the HSI_VALUE(*) + * + * - If SYSCLK source is HSE, SystemCoreClock will contain the HSE_VALUE(**) + * + * - If SYSCLK source is PLL, SystemCoreClock will contain the HSE_VALUE(**) + * or HSI_VALUE(*) multiplied by the PLL factors. + * + * (*) HSI_VALUE is a constant defined in stm32f1xx.h file (default value + * 8 MHz) but the real value may vary depending on the variations + * in voltage and temperature. + * + * (**) HSE_VALUE is a constant defined in stm32f1xx.h file (default value + * 8 MHz or 25 MHz, depending on the product used), user has to ensure + * that HSE_VALUE is same as the real frequency of the crystal used. + * Otherwise, this function may have wrong result. + * + * - The result of this function could be not correct when using fractional + * value for HSE crystal. + * @param None + * @retval None + */ +void SystemCoreClockUpdate (void) +{ + uint32_t tmp = 0, pllmull = 0, pllsource = 0; + +#ifdef STM32F10X_CL + uint32_t prediv1source = 0, prediv1factor = 0, prediv2factor = 0, pll2mull = 0; +#endif /* STM32F10X_CL */ + +#if defined (STM32F10X_LD_VL) || defined (STM32F10X_MD_VL) || (defined STM32F10X_HD_VL) + uint32_t prediv1factor = 0; +#endif /* STM32F10X_LD_VL or STM32F10X_MD_VL or STM32F10X_HD_VL */ + + /* Get SYSCLK source -------------------------------------------------------*/ + tmp = RCC->CFGR & RCC_CFGR_SWS; + + switch (tmp) + { + case 0x00: /* HSI used as system clock */ + SystemCoreClock = HSI_VALUE; + break; + case 0x04: /* HSE used as system clock */ + SystemCoreClock = HSE_VALUE; + break; + case 0x08: /* PLL used as system clock */ + + /* Get PLL clock source and multiplication factor ----------------------*/ + pllmull = RCC->CFGR & RCC_CFGR_PLLMULL; + pllsource = RCC->CFGR & RCC_CFGR_PLLSRC; + +#ifndef STM32F10X_CL + pllmull = ( pllmull >> 18) + 2; + + if (pllsource == 0x00) + { + /* HSI oscillator clock divided by 2 selected as PLL clock entry */ + SystemCoreClock = (HSI_VALUE >> 1) * pllmull; + } + else + { + #if defined (STM32F10X_LD_VL) || defined (STM32F10X_MD_VL) || (defined STM32F10X_HD_VL) + prediv1factor = (RCC->CFGR2 & RCC_CFGR2_PREDIV1) + 1; + /* HSE oscillator clock selected as PREDIV1 clock entry */ + SystemCoreClock = (HSE_VALUE / prediv1factor) * pllmull; + #else + /* HSE selected as PLL clock entry */ + if ((RCC->CFGR & RCC_CFGR_PLLXTPRE) != (uint32_t)RESET) + {/* HSE oscillator clock divided by 2 */ + SystemCoreClock = (HSE_VALUE >> 1) * pllmull; + } + else + { + SystemCoreClock = HSE_VALUE * pllmull; + } + #endif + } +#else + pllmull = pllmull >> 18; + + if (pllmull != 0x0D) + { + pllmull += 2; + } + else + { /* PLL multiplication factor = PLL input clock * 6.5 */ + pllmull = 13 / 2; + } + + if (pllsource == 0x00) + { + /* HSI oscillator clock divided by 2 selected as PLL clock entry */ + SystemCoreClock = (HSI_VALUE >> 1) * pllmull; + } + else + {/* PREDIV1 selected as PLL clock entry */ + + /* Get PREDIV1 clock source and division factor */ + prediv1source = RCC->CFGR2 & RCC_CFGR2_PREDIV1SRC; + prediv1factor = (RCC->CFGR2 & RCC_CFGR2_PREDIV1) + 1; + + if (prediv1source == 0) + { + /* HSE oscillator clock selected as PREDIV1 clock entry */ + SystemCoreClock = (HSE_VALUE / prediv1factor) * pllmull; + } + else + {/* PLL2 clock selected as PREDIV1 clock entry */ + + /* Get PREDIV2 division factor and PLL2 multiplication factor */ + prediv2factor = ((RCC->CFGR2 & RCC_CFGR2_PREDIV2) >> 4) + 1; + pll2mull = ((RCC->CFGR2 & RCC_CFGR2_PLL2MUL) >> 8 ) + 2; + SystemCoreClock = (((HSE_VALUE / prediv2factor) * pll2mull) / prediv1factor) * pllmull; + } + } +#endif /* STM32F10X_CL */ + break; + + default: + SystemCoreClock = HSI_VALUE; + break; + } + + /* Compute HCLK clock frequency ----------------*/ + /* Get HCLK prescaler */ + tmp = AHBPrescTable[((RCC->CFGR & RCC_CFGR_HPRE) >> 4)]; + /* HCLK clock frequency */ + SystemCoreClock >>= tmp; +} + +/** + * @brief Configures the System clock frequency, HCLK, PCLK2 and PCLK1 prescalers. + * @param None + * @retval None + */ +static void SetSysClock(void) +{ +#ifdef SYSCLK_FREQ_HSE + SetSysClockToHSE(); +#elif defined SYSCLK_FREQ_24MHz + SetSysClockTo24(); +#elif defined SYSCLK_FREQ_36MHz + SetSysClockTo36(); +#elif defined SYSCLK_FREQ_48MHz + SetSysClockTo48(); +#elif defined SYSCLK_FREQ_56MHz + SetSysClockTo56(); +#elif defined SYSCLK_FREQ_72MHz + SetSysClockTo72(); +#endif + + /* If none of the define above is enabled, the HSI is used as System clock + source (default after reset) */ +} + +/** + * @brief Setup the external memory controller. Called in startup_stm32f10x.s + * before jump to __main + * @param None + * @retval None + */ +#ifdef DATA_IN_ExtSRAM +/** + * @brief Setup the external memory controller. + * Called in startup_stm32f10x_xx.s/.c before jump to main. + * This function configures the external SRAM mounted on STM3210E-EVAL + * board (STM32 High density devices). This SRAM will be used as program + * data memory (including heap and stack). + * @param None + * @retval None + */ +void SystemInit_ExtMemCtl(void) +{ +/*!< FSMC Bank1 NOR/SRAM3 is used for the STM3210E-EVAL, if another Bank is + required, then adjust the Register Addresses */ + + /* Enable FSMC clock */ + RCC->AHBENR = 0x00000114; + + /* Enable GPIOD, GPIOE, GPIOF and GPIOG clocks */ + RCC->APB2ENR = 0x000001E0; + +/* --------------- SRAM Data lines, NOE and NWE configuration ---------------*/ +/*---------------- SRAM Address lines configuration -------------------------*/ +/*---------------- NOE and NWE configuration --------------------------------*/ +/*---------------- NE3 configuration ----------------------------------------*/ +/*---------------- NBL0, NBL1 configuration ---------------------------------*/ + + GPIOD->CRL = 0x44BB44BB; + GPIOD->CRH = 0xBBBBBBBB; + + GPIOE->CRL = 0xB44444BB; + GPIOE->CRH = 0xBBBBBBBB; + + GPIOF->CRL = 0x44BBBBBB; + GPIOF->CRH = 0xBBBB4444; + + GPIOG->CRL = 0x44BBBBBB; + GPIOG->CRH = 0x44444B44; + +/*---------------- FSMC Configuration ---------------------------------------*/ +/*---------------- Enable FSMC Bank1_SRAM Bank ------------------------------*/ + + FSMC_Bank1->BTCR[4] = 0x00001011; + FSMC_Bank1->BTCR[5] = 0x00000200; +} +#endif /* DATA_IN_ExtSRAM */ + +#ifdef SYSCLK_FREQ_HSE +/** + * @brief Selects HSE as System clock source and configure HCLK, PCLK2 + * and PCLK1 prescalers. + * @note This function should be used only after reset. + * @param None + * @retval None + */ +static void SetSysClockToHSE(void) +{ + __IO uint32_t StartUpCounter = 0, HSEStatus = 0; + + /* SYSCLK, HCLK, PCLK2 and PCLK1 configuration ---------------------------*/ + /* Enable HSE */ + RCC->CR |= ((uint32_t)RCC_CR_HSEON); + + /* Wait till HSE is ready and if Time out is reached exit */ + do + { + HSEStatus = RCC->CR & RCC_CR_HSERDY; + StartUpCounter++; + } while((HSEStatus == 0) && (StartUpCounter != HSE_STARTUP_TIMEOUT)); + + if ((RCC->CR & RCC_CR_HSERDY) != RESET) + { + HSEStatus = (uint32_t)0x01; + } + else + { + HSEStatus = (uint32_t)0x00; + } + + if (HSEStatus == (uint32_t)0x01) + { + +#if !defined STM32F10X_LD_VL && !defined STM32F10X_MD_VL && !defined STM32F10X_HD_VL + /* Enable Prefetch Buffer */ + FLASH->ACR |= FLASH_ACR_PRFTBE; + + /* Flash 0 wait state */ + FLASH->ACR &= (uint32_t)((uint32_t)~FLASH_ACR_LATENCY); + +#ifndef STM32F10X_CL + FLASH->ACR |= (uint32_t)FLASH_ACR_LATENCY_0; +#else + if (HSE_VALUE <= 24000000) + { + FLASH->ACR |= (uint32_t)FLASH_ACR_LATENCY_0; + } + else + { + FLASH->ACR |= (uint32_t)FLASH_ACR_LATENCY_1; + } +#endif /* STM32F10X_CL */ +#endif + + /* HCLK = SYSCLK */ + RCC->CFGR |= (uint32_t)RCC_CFGR_HPRE_DIV1; + + /* PCLK2 = HCLK */ + RCC->CFGR |= (uint32_t)RCC_CFGR_PPRE2_DIV1; + + /* PCLK1 = HCLK */ + RCC->CFGR |= (uint32_t)RCC_CFGR_PPRE1_DIV1; + + /* Select HSE as system clock source */ + RCC->CFGR &= (uint32_t)((uint32_t)~(RCC_CFGR_SW)); + RCC->CFGR |= (uint32_t)RCC_CFGR_SW_HSE; + + /* Wait till HSE is used as system clock source */ + while ((RCC->CFGR & (uint32_t)RCC_CFGR_SWS) != (uint32_t)0x04) + { + } + } + else + { /* If HSE fails to start-up, the application will have wrong clock + configuration. User can add here some code to deal with this error */ + } +} +#elif defined SYSCLK_FREQ_24MHz +/** + * @brief Sets System clock frequency to 24MHz and configure HCLK, PCLK2 + * and PCLK1 prescalers. + * @note This function should be used only after reset. + * @param None + * @retval None + */ +static void SetSysClockTo24(void) +{ + __IO uint32_t StartUpCounter = 0, HSEStatus = 0; + + /* SYSCLK, HCLK, PCLK2 and PCLK1 configuration ---------------------------*/ + /* Enable HSE */ + RCC->CR |= ((uint32_t)RCC_CR_HSEON); + + /* Wait till HSE is ready and if Time out is reached exit */ + do + { + HSEStatus = RCC->CR & RCC_CR_HSERDY; + StartUpCounter++; + } while((HSEStatus == 0) && (StartUpCounter != HSE_STARTUP_TIMEOUT)); + + if ((RCC->CR & RCC_CR_HSERDY) != RESET) + { + HSEStatus = (uint32_t)0x01; + } + else + { + HSEStatus = (uint32_t)0x00; + } + + if (HSEStatus == (uint32_t)0x01) + { +#if !defined STM32F10X_LD_VL && !defined STM32F10X_MD_VL && !defined STM32F10X_HD_VL + /* Enable Prefetch Buffer */ + FLASH->ACR |= FLASH_ACR_PRFTBE; + + /* Flash 0 wait state */ + FLASH->ACR &= (uint32_t)((uint32_t)~FLASH_ACR_LATENCY); + FLASH->ACR |= (uint32_t)FLASH_ACR_LATENCY_0; +#endif + + /* HCLK = SYSCLK */ + RCC->CFGR |= (uint32_t)RCC_CFGR_HPRE_DIV1; + + /* PCLK2 = HCLK */ + RCC->CFGR |= (uint32_t)RCC_CFGR_PPRE2_DIV1; + + /* PCLK1 = HCLK */ + RCC->CFGR |= (uint32_t)RCC_CFGR_PPRE1_DIV1; + +#ifdef STM32F10X_CL + /* Configure PLLs ------------------------------------------------------*/ + /* PLL configuration: PLLCLK = PREDIV1 * 6 = 24 MHz */ + RCC->CFGR &= (uint32_t)~(RCC_CFGR_PLLXTPRE | RCC_CFGR_PLLSRC | RCC_CFGR_PLLMULL); + RCC->CFGR |= (uint32_t)(RCC_CFGR_PLLXTPRE_PREDIV1 | RCC_CFGR_PLLSRC_PREDIV1 | + RCC_CFGR_PLLMULL6); + + /* PLL2 configuration: PLL2CLK = (HSE / 5) * 8 = 40 MHz */ + /* PREDIV1 configuration: PREDIV1CLK = PLL2 / 10 = 4 MHz */ + RCC->CFGR2 &= (uint32_t)~(RCC_CFGR2_PREDIV2 | RCC_CFGR2_PLL2MUL | + RCC_CFGR2_PREDIV1 | RCC_CFGR2_PREDIV1SRC); + RCC->CFGR2 |= (uint32_t)(RCC_CFGR2_PREDIV2_DIV5 | RCC_CFGR2_PLL2MUL8 | + RCC_CFGR2_PREDIV1SRC_PLL2 | RCC_CFGR2_PREDIV1_DIV10); + + /* Enable PLL2 */ + RCC->CR |= RCC_CR_PLL2ON; + /* Wait till PLL2 is ready */ + while((RCC->CR & RCC_CR_PLL2RDY) == 0) + { + } +#elif defined (STM32F10X_LD_VL) || defined (STM32F10X_MD_VL) || defined (STM32F10X_HD_VL) + /* PLL configuration: = (HSE / 2) * 6 = 24 MHz */ + RCC->CFGR &= (uint32_t)((uint32_t)~(RCC_CFGR_PLLSRC | RCC_CFGR_PLLXTPRE | RCC_CFGR_PLLMULL)); + RCC->CFGR |= (uint32_t)(RCC_CFGR_PLLSRC_PREDIV1 | RCC_CFGR_PLLXTPRE_PREDIV1_Div2 | RCC_CFGR_PLLMULL6); +#else + /* PLL configuration: = (HSE / 2) * 6 = 24 MHz */ + RCC->CFGR &= (uint32_t)((uint32_t)~(RCC_CFGR_PLLSRC | RCC_CFGR_PLLXTPRE | RCC_CFGR_PLLMULL)); + RCC->CFGR |= (uint32_t)(RCC_CFGR_PLLSRC_HSE | RCC_CFGR_PLLXTPRE_HSE_Div2 | RCC_CFGR_PLLMULL6); +#endif /* STM32F10X_CL */ + + /* Enable PLL */ + RCC->CR |= RCC_CR_PLLON; + + /* Wait till PLL is ready */ + while((RCC->CR & RCC_CR_PLLRDY) == 0) + { + } + + /* Select PLL as system clock source */ + RCC->CFGR &= (uint32_t)((uint32_t)~(RCC_CFGR_SW)); + RCC->CFGR |= (uint32_t)RCC_CFGR_SW_PLL; + + /* Wait till PLL is used as system clock source */ + while ((RCC->CFGR & (uint32_t)RCC_CFGR_SWS) != (uint32_t)0x08) + { + } + } + else + { /* If HSE fails to start-up, the application will have wrong clock + configuration. User can add here some code to deal with this error */ + } +} +#elif defined SYSCLK_FREQ_36MHz +/** + * @brief Sets System clock frequency to 36MHz and configure HCLK, PCLK2 + * and PCLK1 prescalers. + * @note This function should be used only after reset. + * @param None + * @retval None + */ +static void SetSysClockTo36(void) +{ + __IO uint32_t StartUpCounter = 0, HSEStatus = 0; + + /* SYSCLK, HCLK, PCLK2 and PCLK1 configuration ---------------------------*/ + /* Enable HSE */ + RCC->CR |= ((uint32_t)RCC_CR_HSEON); + + /* Wait till HSE is ready and if Time out is reached exit */ + do + { + HSEStatus = RCC->CR & RCC_CR_HSERDY; + StartUpCounter++; + } while((HSEStatus == 0) && (StartUpCounter != HSE_STARTUP_TIMEOUT)); + + if ((RCC->CR & RCC_CR_HSERDY) != RESET) + { + HSEStatus = (uint32_t)0x01; + } + else + { + HSEStatus = (uint32_t)0x00; + } + + if (HSEStatus == (uint32_t)0x01) + { + /* Enable Prefetch Buffer */ + FLASH->ACR |= FLASH_ACR_PRFTBE; + + /* Flash 1 wait state */ + FLASH->ACR &= (uint32_t)((uint32_t)~FLASH_ACR_LATENCY); + FLASH->ACR |= (uint32_t)FLASH_ACR_LATENCY_1; + + /* HCLK = SYSCLK */ + RCC->CFGR |= (uint32_t)RCC_CFGR_HPRE_DIV1; + + /* PCLK2 = HCLK */ + RCC->CFGR |= (uint32_t)RCC_CFGR_PPRE2_DIV1; + + /* PCLK1 = HCLK */ + RCC->CFGR |= (uint32_t)RCC_CFGR_PPRE1_DIV1; + +#ifdef STM32F10X_CL + /* Configure PLLs ------------------------------------------------------*/ + + /* PLL configuration: PLLCLK = PREDIV1 * 9 = 36 MHz */ + RCC->CFGR &= (uint32_t)~(RCC_CFGR_PLLXTPRE | RCC_CFGR_PLLSRC | RCC_CFGR_PLLMULL); + RCC->CFGR |= (uint32_t)(RCC_CFGR_PLLXTPRE_PREDIV1 | RCC_CFGR_PLLSRC_PREDIV1 | + RCC_CFGR_PLLMULL9); + + /*!< PLL2 configuration: PLL2CLK = (HSE / 5) * 8 = 40 MHz */ + /* PREDIV1 configuration: PREDIV1CLK = PLL2 / 10 = 4 MHz */ + + RCC->CFGR2 &= (uint32_t)~(RCC_CFGR2_PREDIV2 | RCC_CFGR2_PLL2MUL | + RCC_CFGR2_PREDIV1 | RCC_CFGR2_PREDIV1SRC); + RCC->CFGR2 |= (uint32_t)(RCC_CFGR2_PREDIV2_DIV5 | RCC_CFGR2_PLL2MUL8 | + RCC_CFGR2_PREDIV1SRC_PLL2 | RCC_CFGR2_PREDIV1_DIV10); + + /* Enable PLL2 */ + RCC->CR |= RCC_CR_PLL2ON; + /* Wait till PLL2 is ready */ + while((RCC->CR & RCC_CR_PLL2RDY) == 0) + { + } + +#else + /* PLL configuration: PLLCLK = (HSE / 2) * 9 = 36 MHz */ + RCC->CFGR &= (uint32_t)((uint32_t)~(RCC_CFGR_PLLSRC | RCC_CFGR_PLLXTPRE | RCC_CFGR_PLLMULL)); + RCC->CFGR |= (uint32_t)(RCC_CFGR_PLLSRC_HSE | RCC_CFGR_PLLXTPRE_HSE_Div2 | RCC_CFGR_PLLMULL9); +#endif /* STM32F10X_CL */ + + /* Enable PLL */ + RCC->CR |= RCC_CR_PLLON; + + /* Wait till PLL is ready */ + while((RCC->CR & RCC_CR_PLLRDY) == 0) + { + } + + /* Select PLL as system clock source */ + RCC->CFGR &= (uint32_t)((uint32_t)~(RCC_CFGR_SW)); + RCC->CFGR |= (uint32_t)RCC_CFGR_SW_PLL; + + /* Wait till PLL is used as system clock source */ + while ((RCC->CFGR & (uint32_t)RCC_CFGR_SWS) != (uint32_t)0x08) + { + } + } + else + { /* If HSE fails to start-up, the application will have wrong clock + configuration. User can add here some code to deal with this error */ + } +} +#elif defined SYSCLK_FREQ_48MHz +/** + * @brief Sets System clock frequency to 48MHz and configure HCLK, PCLK2 + * and PCLK1 prescalers. + * @note This function should be used only after reset. + * @param None + * @retval None + */ +static void SetSysClockTo48(void) +{ + __IO uint32_t StartUpCounter = 0, HSEStatus = 0; + + /* SYSCLK, HCLK, PCLK2 and PCLK1 configuration ---------------------------*/ + /* Enable HSE */ + RCC->CR |= ((uint32_t)RCC_CR_HSEON); + + /* Wait till HSE is ready and if Time out is reached exit */ + do + { + HSEStatus = RCC->CR & RCC_CR_HSERDY; + StartUpCounter++; + } while((HSEStatus == 0) && (StartUpCounter != HSE_STARTUP_TIMEOUT)); + + if ((RCC->CR & RCC_CR_HSERDY) != RESET) + { + HSEStatus = (uint32_t)0x01; + } + else + { + HSEStatus = (uint32_t)0x00; + } + + if (HSEStatus == (uint32_t)0x01) + { + /* Enable Prefetch Buffer */ + FLASH->ACR |= FLASH_ACR_PRFTBE; + + /* Flash 1 wait state */ + FLASH->ACR &= (uint32_t)((uint32_t)~FLASH_ACR_LATENCY); + FLASH->ACR |= (uint32_t)FLASH_ACR_LATENCY_1; + + /* HCLK = SYSCLK */ + RCC->CFGR |= (uint32_t)RCC_CFGR_HPRE_DIV1; + + /* PCLK2 = HCLK */ + RCC->CFGR |= (uint32_t)RCC_CFGR_PPRE2_DIV1; + + /* PCLK1 = HCLK */ + RCC->CFGR |= (uint32_t)RCC_CFGR_PPRE1_DIV2; + +#ifdef STM32F10X_CL + /* Configure PLLs ------------------------------------------------------*/ + /* PLL2 configuration: PLL2CLK = (HSE / 5) * 8 = 40 MHz */ + /* PREDIV1 configuration: PREDIV1CLK = PLL2 / 5 = 8 MHz */ + + RCC->CFGR2 &= (uint32_t)~(RCC_CFGR2_PREDIV2 | RCC_CFGR2_PLL2MUL | + RCC_CFGR2_PREDIV1 | RCC_CFGR2_PREDIV1SRC); + RCC->CFGR2 |= (uint32_t)(RCC_CFGR2_PREDIV2_DIV5 | RCC_CFGR2_PLL2MUL8 | + RCC_CFGR2_PREDIV1SRC_PLL2 | RCC_CFGR2_PREDIV1_DIV5); + + /* Enable PLL2 */ + RCC->CR |= RCC_CR_PLL2ON; + /* Wait till PLL2 is ready */ + while((RCC->CR & RCC_CR_PLL2RDY) == 0) + { + } + + + /* PLL configuration: PLLCLK = PREDIV1 * 6 = 48 MHz */ + RCC->CFGR &= (uint32_t)~(RCC_CFGR_PLLXTPRE | RCC_CFGR_PLLSRC | RCC_CFGR_PLLMULL); + RCC->CFGR |= (uint32_t)(RCC_CFGR_PLLXTPRE_PREDIV1 | RCC_CFGR_PLLSRC_PREDIV1 | + RCC_CFGR_PLLMULL6); +#else + /* PLL configuration: PLLCLK = HSE * 6 = 48 MHz */ + RCC->CFGR &= (uint32_t)((uint32_t)~(RCC_CFGR_PLLSRC | RCC_CFGR_PLLXTPRE | RCC_CFGR_PLLMULL)); + RCC->CFGR |= (uint32_t)(RCC_CFGR_PLLSRC_HSE | RCC_CFGR_PLLMULL6); +#endif /* STM32F10X_CL */ + + /* Enable PLL */ + RCC->CR |= RCC_CR_PLLON; + + /* Wait till PLL is ready */ + while((RCC->CR & RCC_CR_PLLRDY) == 0) + { + } + + /* Select PLL as system clock source */ + RCC->CFGR &= (uint32_t)((uint32_t)~(RCC_CFGR_SW)); + RCC->CFGR |= (uint32_t)RCC_CFGR_SW_PLL; + + /* Wait till PLL is used as system clock source */ + while ((RCC->CFGR & (uint32_t)RCC_CFGR_SWS) != (uint32_t)0x08) + { + } + } + else + { /* If HSE fails to start-up, the application will have wrong clock + configuration. User can add here some code to deal with this error */ + } +} + +#elif defined SYSCLK_FREQ_56MHz +/** + * @brief Sets System clock frequency to 56MHz and configure HCLK, PCLK2 + * and PCLK1 prescalers. + * @note This function should be used only after reset. + * @param None + * @retval None + */ +static void SetSysClockTo56(void) +{ + __IO uint32_t StartUpCounter = 0, HSEStatus = 0; + + /* SYSCLK, HCLK, PCLK2 and PCLK1 configuration ---------------------------*/ + /* Enable HSE */ + RCC->CR |= ((uint32_t)RCC_CR_HSEON); + + /* Wait till HSE is ready and if Time out is reached exit */ + do + { + HSEStatus = RCC->CR & RCC_CR_HSERDY; + StartUpCounter++; + } while((HSEStatus == 0) && (StartUpCounter != HSE_STARTUP_TIMEOUT)); + + if ((RCC->CR & RCC_CR_HSERDY) != RESET) + { + HSEStatus = (uint32_t)0x01; + } + else + { + HSEStatus = (uint32_t)0x00; + } + + if (HSEStatus == (uint32_t)0x01) + { + /* Enable Prefetch Buffer */ + FLASH->ACR |= FLASH_ACR_PRFTBE; + + /* Flash 2 wait state */ + FLASH->ACR &= (uint32_t)((uint32_t)~FLASH_ACR_LATENCY); + FLASH->ACR |= (uint32_t)FLASH_ACR_LATENCY_2; + + /* HCLK = SYSCLK */ + RCC->CFGR |= (uint32_t)RCC_CFGR_HPRE_DIV1; + + /* PCLK2 = HCLK */ + RCC->CFGR |= (uint32_t)RCC_CFGR_PPRE2_DIV1; + + /* PCLK1 = HCLK */ + RCC->CFGR |= (uint32_t)RCC_CFGR_PPRE1_DIV2; + +#ifdef STM32F10X_CL + /* Configure PLLs ------------------------------------------------------*/ + /* PLL2 configuration: PLL2CLK = (HSE / 5) * 8 = 40 MHz */ + /* PREDIV1 configuration: PREDIV1CLK = PLL2 / 5 = 8 MHz */ + + RCC->CFGR2 &= (uint32_t)~(RCC_CFGR2_PREDIV2 | RCC_CFGR2_PLL2MUL | + RCC_CFGR2_PREDIV1 | RCC_CFGR2_PREDIV1SRC); + RCC->CFGR2 |= (uint32_t)(RCC_CFGR2_PREDIV2_DIV5 | RCC_CFGR2_PLL2MUL8 | + RCC_CFGR2_PREDIV1SRC_PLL2 | RCC_CFGR2_PREDIV1_DIV5); + + /* Enable PLL2 */ + RCC->CR |= RCC_CR_PLL2ON; + /* Wait till PLL2 is ready */ + while((RCC->CR & RCC_CR_PLL2RDY) == 0) + { + } + + + /* PLL configuration: PLLCLK = PREDIV1 * 7 = 56 MHz */ + RCC->CFGR &= (uint32_t)~(RCC_CFGR_PLLXTPRE | RCC_CFGR_PLLSRC | RCC_CFGR_PLLMULL); + RCC->CFGR |= (uint32_t)(RCC_CFGR_PLLXTPRE_PREDIV1 | RCC_CFGR_PLLSRC_PREDIV1 | + RCC_CFGR_PLLMULL7); +#else + /* PLL configuration: PLLCLK = HSE * 7 = 56 MHz */ + RCC->CFGR &= (uint32_t)((uint32_t)~(RCC_CFGR_PLLSRC | RCC_CFGR_PLLXTPRE | RCC_CFGR_PLLMULL)); + RCC->CFGR |= (uint32_t)(RCC_CFGR_PLLSRC_HSE | RCC_CFGR_PLLMULL7); + +#endif /* STM32F10X_CL */ + + /* Enable PLL */ + RCC->CR |= RCC_CR_PLLON; + + /* Wait till PLL is ready */ + while((RCC->CR & RCC_CR_PLLRDY) == 0) + { + } + + /* Select PLL as system clock source */ + RCC->CFGR &= (uint32_t)((uint32_t)~(RCC_CFGR_SW)); + RCC->CFGR |= (uint32_t)RCC_CFGR_SW_PLL; + + /* Wait till PLL is used as system clock source */ + while ((RCC->CFGR & (uint32_t)RCC_CFGR_SWS) != (uint32_t)0x08) + { + } + } + else + { /* If HSE fails to start-up, the application will have wrong clock + configuration. User can add here some code to deal with this error */ + } +} + +#elif defined SYSCLK_FREQ_72MHz +/** + * @brief Sets System clock frequency to 72MHz and configure HCLK, PCLK2 + * and PCLK1 prescalers. + * @note This function should be used only after reset. + * @param None + * @retval None + */ +static void SetSysClockTo72(void) +{ + __IO uint32_t StartUpCounter = 0, HSEStatus = 0; + + /* SYSCLK, HCLK, PCLK2 and PCLK1 configuration ---------------------------*/ + /* Enable HSE */ + RCC->CR |= ((uint32_t)RCC_CR_HSEON); + + /* Wait till HSE is ready and if Time out is reached exit */ + do + { + HSEStatus = RCC->CR & RCC_CR_HSERDY; + StartUpCounter++; + } while((HSEStatus == 0) && (StartUpCounter != HSE_STARTUP_TIMEOUT)); + + if ((RCC->CR & RCC_CR_HSERDY) != RESET) + { + HSEStatus = (uint32_t)0x01; + } + else + { + HSEStatus = (uint32_t)0x00; + } + + if (HSEStatus == (uint32_t)0x01) + { + /* Enable Prefetch Buffer */ + FLASH->ACR |= FLASH_ACR_PRFTBE; + + /* Flash 2 wait state */ + FLASH->ACR &= (uint32_t)((uint32_t)~FLASH_ACR_LATENCY); + FLASH->ACR |= (uint32_t)FLASH_ACR_LATENCY_2; + + + /* HCLK = SYSCLK */ + RCC->CFGR |= (uint32_t)RCC_CFGR_HPRE_DIV1; + + /* PCLK2 = HCLK */ + RCC->CFGR |= (uint32_t)RCC_CFGR_PPRE2_DIV1; + + /* PCLK1 = HCLK */ + RCC->CFGR |= (uint32_t)RCC_CFGR_PPRE1_DIV2; + +#ifdef STM32F10X_CL + /* Configure PLLs ------------------------------------------------------*/ + /* PLL2 configuration: PLL2CLK = (HSE / 5) * 8 = 40 MHz */ + /* PREDIV1 configuration: PREDIV1CLK = PLL2 / 5 = 8 MHz */ + + RCC->CFGR2 &= (uint32_t)~(RCC_CFGR2_PREDIV2 | RCC_CFGR2_PLL2MUL | + RCC_CFGR2_PREDIV1 | RCC_CFGR2_PREDIV1SRC); + RCC->CFGR2 |= (uint32_t)(RCC_CFGR2_PREDIV2_DIV5 | RCC_CFGR2_PLL2MUL8 | + RCC_CFGR2_PREDIV1SRC_PLL2 | RCC_CFGR2_PREDIV1_DIV5); + + /* Enable PLL2 */ + RCC->CR |= RCC_CR_PLL2ON; + /* Wait till PLL2 is ready */ + while((RCC->CR & RCC_CR_PLL2RDY) == 0) + { + } + + + /* PLL configuration: PLLCLK = PREDIV1 * 9 = 72 MHz */ + RCC->CFGR &= (uint32_t)~(RCC_CFGR_PLLXTPRE | RCC_CFGR_PLLSRC | RCC_CFGR_PLLMULL); + RCC->CFGR |= (uint32_t)(RCC_CFGR_PLLXTPRE_PREDIV1 | RCC_CFGR_PLLSRC_PREDIV1 | + RCC_CFGR_PLLMULL9); +#else + /* PLL configuration: PLLCLK = HSE * 9 = 72 MHz */ + RCC->CFGR &= (uint32_t)((uint32_t)~(RCC_CFGR_PLLSRC | RCC_CFGR_PLLXTPRE | + RCC_CFGR_PLLMULL)); + RCC->CFGR |= (uint32_t)(RCC_CFGR_PLLSRC_HSE | RCC_CFGR_PLLMULL9); +#endif /* STM32F10X_CL */ + + /* Enable PLL */ + RCC->CR |= RCC_CR_PLLON; + + /* Wait till PLL is ready */ + while((RCC->CR & RCC_CR_PLLRDY) == 0) + { + } + + /* Select PLL as system clock source */ + RCC->CFGR &= (uint32_t)((uint32_t)~(RCC_CFGR_SW)); + RCC->CFGR |= (uint32_t)RCC_CFGR_SW_PLL; + + /* Wait till PLL is used as system clock source */ + while ((RCC->CFGR & (uint32_t)RCC_CFGR_SWS) != (uint32_t)0x08) + { + } + } + else + { /* If HSE fails to start-up, the application will have wrong clock + configuration. User can add here some code to deal with this error */ + } +} +#endif + +/** + * @} + */ + +/** + * @} + */ + +/** + * @} + */ +/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ diff --git a/Libraries/CMSIS/Device/ST/STM32F30x/Include/stm32f30x.h b/Libraries/CMSIS/Device/ST/STM32F30x/Include/stm32f30x.h new file mode 100644 index 0000000..c18f853 --- /dev/null +++ b/Libraries/CMSIS/Device/ST/STM32F30x/Include/stm32f30x.h @@ -0,0 +1,6205 @@ +/** + ****************************************************************************** + * @file stm32f30x.h + * @author MCD Application Team + * @version V1.0.0 + * @date 04-September-2012 + * @brief CMSIS Cortex-M4 Device Peripheral Access Layer Header File. + * This file contains all the peripheral registers definitions, bits + * definitions and memory mapping for STM32F30x devices. + * + * The file is the unique include file that the application programmer + * is using in the C source code, usually in main.c. This file contains: + * - Configuration section that allows to select: + * - The device used in the target application + * - To use or not the peripherals drivers in application code(i.e. + * code will be based on direct access to peripherals registers + * rather than drivers API), this option is controlled by + * "#define USE_STDPERIPH_DRIVER" + * - To change few application-specific parameters such as the HSE + * crystal frequency + * - Data structures and the address mapping for all peripherals + * - Peripheral registers declarations and bits definition + * - Macros to access peripheral registers hardware + * + ****************************************************************************** + * @attention + * + *

© COPYRIGHT 2012 STMicroelectronics

+ * + * Licensed under MCD-ST Liberty SW License Agreement V2, (the "License"); + * You may not use this file except in compliance with the License. + * You may obtain a copy of the License at: + * + * http://www.st.com/software_license_agreement_liberty_v2 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, + * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + * + ****************************************************************************** + */ + +/** @addtogroup CMSIS + * @{ + */ + +/** @addtogroup stm32f30x + * @{ + */ + +#ifndef __STM32F30x_H +#define __STM32F30x_H + +#ifdef __cplusplus + extern "C" { +#endif /* __cplusplus */ + +/** @addtogroup Library_configuration_section + * @{ + */ + +/* Uncomment the line below according to the target STM32 device used in your + application + */ + +#if !defined (STM32F30X) + #define STM32F30X +#endif + +/* Tip: To avoid modifying this file each time you need to switch between these + devices, you can define the device in your toolchain compiler preprocessor. + */ + +#if !defined (STM32F30X) + #error "Please select first the target STM32F30X device used in your application (in stm32f30x.h file)" +#endif + +#if !defined (USE_STDPERIPH_DRIVER) +/** + * @brief Comment the line below if you will not use the peripherals drivers. + In this case, these drivers will not be included and the application code will + be based on direct access to peripherals registers + */ + /*#define USE_STDPERIPH_DRIVER*/ +#endif /* USE_STDPERIPH_DRIVER */ + +/** + * @brief In the following line adjust the value of External High Speed oscillator (HSE) + used in your application + + Tip: To avoid modifying this file each time you need to use different HSE, you + can define the HSE value in your toolchain compiler preprocessor. + */ +#if !defined (HSE_VALUE) + #define HSE_VALUE ((uint32_t)8000000) /*!< Value of the External oscillator in Hz */ +#endif /* HSE_VALUE */ + +/** + * @brief In the following line adjust the External High Speed oscillator (HSE) Startup + Timeout value + */ +#if !defined (HSE_STARTUP_TIMEOUT) + #define HSE_STARTUP_TIMEOUT ((uint16_t)0x0500) /*!< Time out for HSE start up */ +#endif /* HSE_STARTUP_TIMEOUT */ + +/** + * @brief In the following line adjust the Internal High Speed oscillator (HSI) Startup + Timeout value + */ +#if !defined (HSI_STARTUP_TIMEOUT) + #define HSI_STARTUP_TIMEOUT ((uint16_t)0x0500) /*!< Time out for HSI start up */ +#endif /* HSI_STARTUP_TIMEOUT */ + +#if !defined (HSI_VALUE) + #define HSI_VALUE ((uint32_t)8000000) +#endif /* HSI_VALUE */ /*!< Value of the Internal High Speed oscillator in Hz. + The real value may vary depending on the variations + in voltage and temperature. */ +#if !defined (LSI_VALUE) + #define LSI_VALUE ((uint32_t)40000) +#endif /* LSI_VALUE */ /*!< Value of the Internal Low Speed oscillator in Hz + The real value may vary depending on the variations + in voltage and temperature. */ +#if !defined (LSE_VALUE) + #define LSE_VALUE ((uint32_t)32768) /*!< Value of the External Low Speed oscillator in Hz */ +#endif /* LSE_VALUE */ + + +/** + * @brief STM32F30x Standard Peripherals Library version number V1.0.0 + */ +#define __STM32F30X_STDPERIPH_VERSION_MAIN (0x01) /*!< [31:24] main version */ +#define __STM32F30X_STDPERIPH_VERSION_SUB1 (0x00) /*!< [23:16] sub1 version */ +#define __STM32F30X_STDPERIPH_VERSION_SUB2 (0x00) /*!< [15:8] sub2 version */ +#define __STM32F30X_STDPERIPH_VERSION_RC (0x00) /*!< [7:0] release candidate */ +#define __STM32F30X_STDPERIPH_VERSION ( (__STM32F30X_STDPERIPH_VERSION_MAIN << 24)\ + |(__STM32F30X_STDPERIPH_VERSION_SUB1 << 16)\ + |(__STM32F30X_STDPERIPH_VERSION_SUB2 << 8)\ + |(__STM32F30X_STDPERIPH_VERSION_RC)) + +/** + * @} + */ + +/** @addtogroup Configuration_section_for_CMSIS + * @{ + */ + +/** + * @brief Configuration of the Cortex-M4 Processor and Core Peripherals + */ +#define __CM4_REV 0x0001 /*!< Core revision r0p1 */ +#define __MPU_PRESENT 1 /*!< STM32F30X provide an MPU */ +#define __NVIC_PRIO_BITS 4 /*!< STM32F30X uses 4 Bits for the Priority Levels */ +#define __Vendor_SysTickConfig 0 /*!< Set to 1 if different SysTick Config is used */ +#define __FPU_PRESENT 1 /*!< STM32F30X provide an FPU */ + + +/** + * @brief STM32F30X Interrupt Number Definition, according to the selected device + * in @ref Library_configuration_section + */ +typedef enum IRQn +{ +/****** Cortex-M4 Processor Exceptions Numbers ****************************************************************/ + NonMaskableInt_IRQn = -14, /*!< 2 Non Maskable Interrupt */ + MemoryManagement_IRQn = -12, /*!< 4 Cortex-M4 Memory Management Interrupt */ + BusFault_IRQn = -11, /*!< 5 Cortex-M4 Bus Fault Interrupt */ + UsageFault_IRQn = -10, /*!< 6 Cortex-M4 Usage Fault Interrupt */ + SVCall_IRQn = -5, /*!< 11 Cortex-M4 SV Call Interrupt */ + DebugMonitor_IRQn = -4, /*!< 12 Cortex-M4 Debug Monitor Interrupt */ + PendSV_IRQn = -2, /*!< 14 Cortex-M4 Pend SV Interrupt */ + SysTick_IRQn = -1, /*!< 15 Cortex-M4 System Tick Interrupt */ +/****** STM32 specific Interrupt Numbers **********************************************************************/ + WWDG_IRQn = 0, /*!< Window WatchDog Interrupt */ + PVD_IRQn = 1, /*!< PVD through EXTI Line detection Interrupt */ + TAMPER_STAMP_IRQn = 2, /*!< Tamper and TimeStamp interrupts */ + RTC_WKUP_IRQn = 3, /*!< RTC Wakeup interrupt through the EXTI lines 17, 19 & 20 */ + FLASH_IRQn = 4, /*!< FLASH global Interrupt */ + RCC_IRQn = 5, /*!< RCC global Interrupt */ + EXTI0_IRQn = 6, /*!< EXTI Line0 Interrupt */ + EXTI1_IRQn = 7, /*!< EXTI Line1 Interrupt */ + EXTI2_TS_IRQn = 8, /*!< EXTI Line2 Interrupt and Touch Sense Interrupt */ + EXTI3_IRQn = 9, /*!< EXTI Line3 Interrupt */ + EXTI4_IRQn = 10, /*!< EXTI Line4 Interrupt */ + DMA1_Channel1_IRQn = 11, /*!< DMA1 Channel 1 Interrupt */ + DMA1_Channel2_IRQn = 12, /*!< DMA1 Channel 2 Interrupt */ + DMA1_Channel3_IRQn = 13, /*!< DMA1 Channel 3 Interrupt */ + DMA1_Channel4_IRQn = 14, /*!< DMA1 Channel 4 Interrupt */ + DMA1_Channel5_IRQn = 15, /*!< DMA1 Channel 5 Interrupt */ + DMA1_Channel6_IRQn = 16, /*!< DMA1 Channel 6 Interrupt */ + DMA1_Channel7_IRQn = 17, /*!< DMA1 Channel 7 Interrupt */ + ADC1_2_IRQn = 18, /*!< ADC1 & ADC2 Interrupts */ + USB_HP_CAN1_TX_IRQn = 19, /*!< USB Device High Priority or CAN1 TX Interrupts */ + USB_LP_CAN1_RX0_IRQn = 20, /*!< USB Device Low Priority or CAN1 RX0 Interrupts */ + CAN1_RX1_IRQn = 21, /*!< CAN1 RX1 Interrupt */ + CAN1_SCE_IRQn = 22, /*!< CAN1 SCE Interrupt */ + EXTI9_5_IRQn = 23, /*!< External Line[9:5] Interrupts */ + TIM1_BRK_TIM15_IRQn = 24, /*!< TIM1 Break and TIM15 Interrupts */ + TIM1_UP_TIM16_IRQn = 25, /*!< TIM1 Update and TIM16 Interrupts */ + TIM1_TRG_COM_TIM17_IRQn = 26, /*!< TIM1 Trigger and Commutation and TIM17 Interrupt */ + TIM1_CC_IRQn = 27, /*!< TIM1 Capture Compare Interrupt */ + TIM2_IRQn = 28, /*!< TIM2 global Interrupt */ + TIM3_IRQn = 29, /*!< TIM3 global Interrupt */ + TIM4_IRQn = 30, /*!< TIM4 global Interrupt */ + I2C1_EV_IRQn = 31, /*!< I2C1 Event Interrupt */ + I2C1_ER_IRQn = 32, /*!< I2C1 Error Interrupt */ + I2C2_EV_IRQn = 33, /*!< I2C2 Event Interrupt */ + I2C2_ER_IRQn = 34, /*!< I2C2 Error Interrupt */ + SPI1_IRQn = 35, /*!< SPI1 global Interrupt */ + SPI2_IRQn = 36, /*!< SPI2 global Interrupt */ + USART1_IRQn = 37, /*!< USART1 global Interrupt */ + USART2_IRQn = 38, /*!< USART2 global Interrupt */ + USART3_IRQn = 39, /*!< USART3 global Interrupt */ + EXTI15_10_IRQn = 40, /*!< External Line[15:10] Interrupts */ + RTC_Alarm_IRQn = 41, /*!< RTC Alarm (A and B) through EXTI Line Interrupt */ + USBWakeUp_IRQn = 42, /*!< USB Wakeup Interrupt */ + TIM8_BRK_IRQn = 43, /*!< TIM8 Break Interrupt */ + TIM8_UP_IRQn = 44, /*!< TIM8 Update Interrupt */ + TIM8_TRG_COM_IRQn = 45, /*!< TIM8 Trigger and Commutation Interrupt */ + TIM8_CC_IRQn = 46, /*!< TIM8 Capture Compare Interrupt */ + ADC3_IRQn = 47, /*!< ADC3 global Interrupt */ + SPI3_IRQn = 51, /*!< SPI3 global Interrupt */ + UART4_IRQn = 52, /*!< UART4 global Interrupt */ + UART5_IRQn = 53, /*!< UART5 global Interrupt */ + TIM6_DAC_IRQn = 54, /*!< TIM6 global and DAC1&2 underrun error interrupts */ + TIM7_IRQn = 55, /*!< TIM7 global Interrupt */ + DMA2_Channel1_IRQn = 56, /*!< DMA2 Channel 1 global Interrupt */ + DMA2_Channel2_IRQn = 57, /*!< DMA2 Channel 2 global Interrupt */ + DMA2_Channel3_IRQn = 58, /*!< DMA2 Channel 3 global Interrupt */ + DMA2_Channel4_IRQn = 59, /*!< DMA2 Channel 4 global Interrupt */ + DMA2_Channel5_IRQn = 60, /*!< DMA2 Channel 5 global Interrupt */ + ADC4_IRQn = 61, /*!< ADC4 global Interrupt */ + COMP1_2_3_IRQn = 64, /*!< COMP1, COMP2 and COMP3 global Interrupt */ + COMP4_5_6_IRQn = 65, /*!< COMP5, COMP6 and COMP4 global Interrupt */ + COMP7_IRQn = 66, /*!< COMP7 global Interrupt */ + USB_HP_IRQn = 74, /*!< USB High Priority global Interrupt remap */ + USB_LP_IRQn = 75, /*!< USB Low Priority global Interrupt remap */ + USBWakeUp_RMP_IRQn = 76, /*!< USB Wakeup Interrupt remap */ + FPU_IRQn = 81 /*!< Floating point Interrupt */ +} IRQn_Type; + +/** + * @} + */ + +#include "core_cm4.h" /* Cortex-M4 processor and core peripherals */ +#include "system_stm32f30x.h" /* STM32F30x System Header */ +#include + +/** @addtogroup Exported_types + * @{ + */ +/*!< STM32F10x Standard Peripheral Library old types (maintained for legacy purpose) */ +typedef int32_t s32; +typedef int16_t s16; +typedef int8_t s8; + +typedef const int32_t sc32; /*!< Read Only */ +typedef const int16_t sc16; /*!< Read Only */ +typedef const int8_t sc8; /*!< Read Only */ + +typedef __IO int32_t vs32; +typedef __IO int16_t vs16; +typedef __IO int8_t vs8; + +typedef __I int32_t vsc32; /*!< Read Only */ +typedef __I int16_t vsc16; /*!< Read Only */ +typedef __I int8_t vsc8; /*!< Read Only */ + +typedef uint32_t u32; +typedef uint16_t u16; +typedef uint8_t u8; + +typedef const uint32_t uc32; /*!< Read Only */ +typedef const uint16_t uc16; /*!< Read Only */ +typedef const uint8_t uc8; /*!< Read Only */ + +typedef __IO uint32_t vu32; +typedef __IO uint16_t vu16; +typedef __IO uint8_t vu8; + +typedef __I uint32_t vuc32; /*!< Read Only */ +typedef __I uint16_t vuc16; /*!< Read Only */ +typedef __I uint8_t vuc8; /*!< Read Only */ + +typedef enum {RESET = 0, SET = !RESET} FlagStatus, ITStatus; + +typedef enum {DISABLE = 0, ENABLE = !DISABLE} FunctionalState; +#define IS_FUNCTIONAL_STATE(STATE) (((STATE) == DISABLE) || ((STATE) == ENABLE)) + +typedef enum {ERROR = 0, SUCCESS = !ERROR} ErrorStatus; + +/** + * @} + */ + +/** @addtogroup Peripheral_registers_structures + * @{ + */ + +/** + * @brief Analog to Digital Converter + */ + +typedef struct +{ + __IO uint32_t ISR; /*!< ADC Interrupt and Status Register, Address offset: 0x00 */ + __IO uint32_t IER; /*!< ADC Interrupt Enable Register, Address offset: 0x04 */ + __IO uint32_t CR; /*!< ADC control register, Address offset: 0x08 */ + __IO uint32_t CFGR; /*!< ADC Configuration register, Address offset: 0x0C */ + uint32_t RESERVED0; /*!< Reserved, 0x010 */ + __IO uint32_t SMPR1; /*!< ADC sample time register 1, Address offset: 0x14 */ + __IO uint32_t SMPR2; /*!< ADC sample time register 2, Address offset: 0x18 */ + uint32_t RESERVED1; /*!< Reserved, 0x01C */ + __IO uint32_t TR1; /*!< ADC watchdog threshold register 1, Address offset: 0x20 */ + __IO uint32_t TR2; /*!< ADC watchdog threshold register 2, Address offset: 0x24 */ + __IO uint32_t TR3; /*!< ADC watchdog threshold register 3, Address offset: 0x28 */ + uint32_t RESERVED2; /*!< Reserved, 0x02C */ + __IO uint32_t SQR1; /*!< ADC regular sequence register 1, Address offset: 0x30 */ + __IO uint32_t SQR2; /*!< ADC regular sequence register 2, Address offset: 0x34 */ + __IO uint32_t SQR3; /*!< ADC regular sequence register 3, Address offset: 0x38 */ + __IO uint32_t SQR4; /*!< ADC regular sequence register 4, Address offset: 0x3C */ + __IO uint32_t DR; /*!< ADC regular data register, Address offset: 0x40 */ + uint32_t RESERVED3; /*!< Reserved, 0x044 */ + uint32_t RESERVED4; /*!< Reserved, 0x048 */ + __IO uint32_t JSQR; /*!< ADC injected sequence register, Address offset: 0x4C */ + uint32_t RESERVED5[4]; /*!< Reserved, 0x050 - 0x05C */ + __IO uint32_t OFR1; /*!< ADC offset register 1, Address offset: 0x60 */ + __IO uint32_t OFR2; /*!< ADC offset register 2, Address offset: 0x64 */ + __IO uint32_t OFR3; /*!< ADC offset register 3, Address offset: 0x68 */ + __IO uint32_t OFR4; /*!< ADC offset register 4, Address offset: 0x6C */ + uint32_t RESERVED6[4]; /*!< Reserved, 0x070 - 0x07C */ + __IO uint32_t JDR1; /*!< ADC injected data register 1, Address offset: 0x80 */ + __IO uint32_t JDR2; /*!< ADC injected data register 2, Address offset: 0x84 */ + __IO uint32_t JDR3; /*!< ADC injected data register 3, Address offset: 0x88 */ + __IO uint32_t JDR4; /*!< ADC injected data register 4, Address offset: 0x8C */ + uint32_t RESERVED7[4]; /*!< Reserved, 0x090 - 0x09C */ + __IO uint32_t AWD2CR; /*!< ADC Analog Watchdog 2 Configuration Register, Address offset: 0xA0 */ + __IO uint32_t AWD3CR; /*!< ADC Analog Watchdog 3 Configuration Register, Address offset: 0xA4 */ + uint32_t RESERVED8; /*!< Reserved, 0x0A8 */ + uint32_t RESERVED9; /*!< Reserved, 0x0AC */ + __IO uint32_t DIFSEL; /*!< ADC Differential Mode Selection Register, Address offset: 0xB0 */ + __IO uint32_t CALFACT; /*!< ADC Calibration Factors, Address offset: 0xB4 */ + +} ADC_TypeDef; + +typedef struct +{ + __IO uint32_t CSR; /*!< ADC Common status register, Address offset: ADC1/3 base address + 0x300 */ + uint32_t RESERVED; /*!< Reserved, ADC1/3 base address + 0x304 */ + __IO uint32_t CCR; /*!< ADC common control register, Address offset: ADC1/3 base address + 0x308 */ + __IO uint32_t CDR; /*!< ADC common regular data register for dual + AND triple modes, Address offset: ADC1/3 base address + 0x30C */ +} ADC_Common_TypeDef; + + +/** + * @brief Controller Area Network TxMailBox + */ +typedef struct +{ + __IO uint32_t TIR; /*!< CAN TX mailbox identifier register */ + __IO uint32_t TDTR; /*!< CAN mailbox data length control and time stamp register */ + __IO uint32_t TDLR; /*!< CAN mailbox data low register */ + __IO uint32_t TDHR; /*!< CAN mailbox data high register */ +} CAN_TxMailBox_TypeDef; + +/** + * @brief Controller Area Network FIFOMailBox + */ +typedef struct +{ + __IO uint32_t RIR; /*!< CAN receive FIFO mailbox identifier register */ + __IO uint32_t RDTR; /*!< CAN receive FIFO mailbox data length control and time stamp register */ + __IO uint32_t RDLR; /*!< CAN receive FIFO mailbox data low register */ + __IO uint32_t RDHR; /*!< CAN receive FIFO mailbox data high register */ +} CAN_FIFOMailBox_TypeDef; + +/** + * @brief Controller Area Network FilterRegister + */ +typedef struct +{ + __IO uint32_t FR1; /*!< CAN Filter bank register 1 */ + __IO uint32_t FR2; /*!< CAN Filter bank register 1 */ +} CAN_FilterRegister_TypeDef; + +/** + * @brief Controller Area Network + */ +typedef struct +{ + __IO uint32_t MCR; /*!< CAN master control register, Address offset: 0x00 */ + __IO uint32_t MSR; /*!< CAN master status register, Address offset: 0x04 */ + __IO uint32_t TSR; /*!< CAN transmit status register, Address offset: 0x08 */ + __IO uint32_t RF0R; /*!< CAN receive FIFO 0 register, Address offset: 0x0C */ + __IO uint32_t RF1R; /*!< CAN receive FIFO 1 register, Address offset: 0x10 */ + __IO uint32_t IER; /*!< CAN interrupt enable register, Address offset: 0x14 */ + __IO uint32_t ESR; /*!< CAN error status register, Address offset: 0x18 */ + __IO uint32_t BTR; /*!< CAN bit timing register, Address offset: 0x1C */ + uint32_t RESERVED0[88]; /*!< Reserved, 0x020 - 0x17F */ + CAN_TxMailBox_TypeDef sTxMailBox[3]; /*!< CAN Tx MailBox, Address offset: 0x180 - 0x1AC */ + CAN_FIFOMailBox_TypeDef sFIFOMailBox[2]; /*!< CAN FIFO MailBox, Address offset: 0x1B0 - 0x1CC */ + uint32_t RESERVED1[12]; /*!< Reserved, 0x1D0 - 0x1FF */ + __IO uint32_t FMR; /*!< CAN filter master register, Address offset: 0x200 */ + __IO uint32_t FM1R; /*!< CAN filter mode register, Address offset: 0x204 */ + uint32_t RESERVED2; /*!< Reserved, 0x208 */ + __IO uint32_t FS1R; /*!< CAN filter scale register, Address offset: 0x20C */ + uint32_t RESERVED3; /*!< Reserved, 0x210 */ + __IO uint32_t FFA1R; /*!< CAN filter FIFO assignment register, Address offset: 0x214 */ + uint32_t RESERVED4; /*!< Reserved, 0x218 */ + __IO uint32_t FA1R; /*!< CAN filter activation register, Address offset: 0x21C */ + uint32_t RESERVED5[8]; /*!< Reserved, 0x220-0x23F */ + CAN_FilterRegister_TypeDef sFilterRegister[28]; /*!< CAN Filter Register, Address offset: 0x240-0x31C */ +} CAN_TypeDef; + + +/** + * @brief Analog Comparators + */ + +typedef struct +{ + __IO uint32_t CSR; /*!< Comparator control Status register, Address offset: 0x00 */ +} COMP_TypeDef; + +/** + * @brief CRC calculation unit + */ + +typedef struct +{ + __IO uint32_t DR; /*!< CRC Data register, Address offset: 0x00 */ + __IO uint8_t IDR; /*!< CRC Independent data register, Address offset: 0x04 */ + uint8_t RESERVED0; /*!< Reserved, 0x05 */ + uint16_t RESERVED1; /*!< Reserved, 0x06 */ + __IO uint32_t CR; /*!< CRC Control register, Address offset: 0x08 */ + uint32_t RESERVED2; /*!< Reserved, 0x0C */ + __IO uint32_t INIT; /*!< Initial CRC value register, Address offset: 0x10 */ + __IO uint32_t POL; /*!< CRC polynomial register, Address offset: 0x14 */ +} CRC_TypeDef; + +/** + * @brief Digital to Analog Converter + */ + +typedef struct +{ + __IO uint32_t CR; /*!< DAC control register, Address offset: 0x00 */ + __IO uint32_t SWTRIGR; /*!< DAC software trigger register, Address offset: 0x04 */ + __IO uint32_t DHR12R1; /*!< DAC channel1 12-bit right-aligned data holding register, Address offset: 0x08 */ + __IO uint32_t DHR12L1; /*!< DAC channel1 12-bit left aligned data holding register, Address offset: 0x0C */ + __IO uint32_t DHR8R1; /*!< DAC channel1 8-bit right aligned data holding register, Address offset: 0x10 */ + __IO uint32_t DHR12R2; /*!< DAC channel2 12-bit right aligned data holding register, Address offset: 0x14 */ + __IO uint32_t DHR12L2; /*!< DAC channel2 12-bit left aligned data holding register, Address offset: 0x18 */ + __IO uint32_t DHR8R2; /*!< DAC channel2 8-bit right-aligned data holding register, Address offset: 0x1C */ + __IO uint32_t DHR12RD; /*!< Dual DAC 12-bit right-aligned data holding register, Address offset: 0x20 */ + __IO uint32_t DHR12LD; /*!< DUAL DAC 12-bit left aligned data holding register, Address offset: 0x24 */ + __IO uint32_t DHR8RD; /*!< DUAL DAC 8-bit right aligned data holding register, Address offset: 0x28 */ + __IO uint32_t DOR1; /*!< DAC channel1 data output register, Address offset: 0x2C */ + __IO uint32_t DOR2; /*!< DAC channel2 data output register, Address offset: 0x30 */ + __IO uint32_t SR; /*!< DAC status register, Address offset: 0x34 */ +} DAC_TypeDef; + +/** + * @brief Debug MCU + */ + +typedef struct +{ + __IO uint32_t IDCODE; /*!< MCU device ID code, Address offset: 0x00 */ + __IO uint32_t CR; /*!< Debug MCU configuration register, Address offset: 0x04 */ + __IO uint32_t APB1FZ; /*!< Debug MCU APB1 freeze register, Address offset: 0x08 */ + __IO uint32_t APB2FZ; /*!< Debug MCU APB2 freeze register, Address offset: 0x0C */ +}DBGMCU_TypeDef; + +/** + * @brief DMA Controller + */ + +typedef struct +{ + __IO uint32_t CCR; /*!< DMA channel x configuration register */ + __IO uint32_t CNDTR; /*!< DMA channel x number of data register */ + __IO uint32_t CPAR; /*!< DMA channel x peripheral address register */ + __IO uint32_t CMAR; /*!< DMA channel x memory address register */ +} DMA_Channel_TypeDef; + +typedef struct +{ + __IO uint32_t ISR; /*!< DMA interrupt status register, Address offset: 0x00 */ + __IO uint32_t IFCR; /*!< DMA interrupt clear flag register, Address offset: 0x04 */ +} DMA_TypeDef; + +/** + * @brief External Interrupt/Event Controller + */ + +typedef struct +{ + __IO uint32_t IMR; /*!< EXTI Interrupt mask register, Address offset: 0x00 */ + __IO uint32_t EMR; /*!< EXTI Event mask register, Address offset: 0x04 */ + __IO uint32_t RTSR; /*!< EXTI Rising trigger selection register, Address offset: 0x08 */ + __IO uint32_t FTSR; /*!< EXTI Falling trigger selection register, Address offset: 0x0C */ + __IO uint32_t SWIER; /*!< EXTI Software interrupt event register, Address offset: 0x10 */ + __IO uint32_t PR; /*!< EXTI Pending register, Address offset: 0x14 */ + uint32_t RESERVED1; /*!< Reserved, 0x18 */ + uint32_t RESERVED2; /*!< Reserved, 0x1C */ + __IO uint32_t IMR2; /*!< EXTI Interrupt mask register, Address offset: 0x20 */ + __IO uint32_t EMR2; /*!< EXTI Event mask register, Address offset: 0x24 */ + __IO uint32_t RTSR2; /*!< EXTI Rising trigger selection register, Address offset: 0x28 */ + __IO uint32_t FTSR2; /*!< EXTI Falling trigger selection register, Address offset: 0x2C */ + __IO uint32_t SWIER2; /*!< EXTI Software interrupt event register, Address offset: 0x30 */ + __IO uint32_t PR2; /*!< EXTI Pending register, Address offset: 0x34 */ +}EXTI_TypeDef; + +/** + * @brief FLASH Registers + */ + +typedef struct +{ + __IO uint32_t ACR; /*!< FLASH access control register, Address offset: 0x00 */ + __IO uint32_t KEYR; /*!< FLASH key register, Address offset: 0x04 */ + __IO uint32_t OPTKEYR; /*!< FLASH option key register, Address offset: 0x08 */ + __IO uint32_t SR; /*!< FLASH status register, Address offset: 0x0C */ + __IO uint32_t CR; /*!< FLASH control register, Address offset: 0x10 */ + __IO uint32_t AR; /*!< FLASH address register, Address offset: 0x14 */ + uint32_t RESERVED; /*!< Reserved, 0x18 */ + __IO uint32_t OBR; /*!< FLASH Option byte register, Address offset: 0x1C */ + __IO uint32_t WRPR; /*!< FLASH Write register, Address offset: 0x20 */ + +} FLASH_TypeDef; + +/** + * @brief Option Bytes Registers + */ +typedef struct +{ + __IO uint16_t RDP; /*!
© COPYRIGHT 2012 STMicroelectronics
+ * + * Licensed under MCD-ST Liberty SW License Agreement V2, (the "License"); + * You may not use this file except in compliance with the License. + * You may obtain a copy of the License at: + * + * http://www.st.com/software_license_agreement_liberty_v2 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, + * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + * + ****************************************************************************** + */ + +/** @addtogroup CMSIS + * @{ + */ + +/** @addtogroup stm32f30x_system + * @{ + */ + +/** + * @brief Define to prevent recursive inclusion + */ +#ifndef __SYSTEM_STM32F30X_H +#define __SYSTEM_STM32F30X_H + +#ifdef __cplusplus + extern "C" { +#endif + +/** @addtogroup STM32F30x_System_Includes + * @{ + */ + +/** + * @} + */ + + +/** @addtogroup STM32F30x_System_Exported_types + * @{ + */ + +extern uint32_t SystemCoreClock; /*!< System Clock Frequency (Core Clock) */ + + +/** + * @} + */ + +/** @addtogroup STM32F30x_System_Exported_Constants + * @{ + */ + +/** + * @} + */ + +/** @addtogroup STM32F30x_System_Exported_Macros + * @{ + */ + +/** + * @} + */ + +/** @addtogroup STM32F30x_System_Exported_Functions + * @{ + */ + +extern void SystemInit(void); +extern void SystemCoreClockUpdate(void); +/** + * @} + */ + +#ifdef __cplusplus +} +#endif + +#endif /*__SYSTEM_STM32F30X_H */ + +/** + * @} + */ + +/** + * @} + */ +/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ diff --git a/Libraries/CMSIS/Device/ST/STM32F30x/Release_Notes.html b/Libraries/CMSIS/Device/ST/STM32F30x/Release_Notes.html new file mode 100644 index 0000000..26085fd --- /dev/null +++ b/Libraries/CMSIS/Device/ST/STM32F30x/Release_Notes.html @@ -0,0 +1,136 @@ + + + + + + + + +Release Notes for STM32F30x CMSIS + + + + + +
+


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Release +Notes for STM32F30x CMSIS

+

Copyright 2012 STMicroelectronics

+

+
+

 

+ + + + + + +
+

Contents

+
    +
  1. STM32F30x CMSIS +update History
    2. +
  2. License
    3. +
+ +

STM32F30x CMSIS +update History

V1.0.0 / 04-September-2012

Main +Changes

+
  • First official release for STM32F30x devices
+ +
    +
+

License

Licensed +under MCD-ST Liberty SW License Agreement V2, (the "License"); You may not use +this package +except in compliance with the License. You may obtain a copy of the License +at:

+
Unless +required by applicable law or agreed to in writing, software distributed under +the License is distributed on an "AS IS" BASIS,
WITHOUT WARRANTIES OR +CONDITIONS OF ANY KIND, either express or implied. See the License for the +specific language governing permissions and limitations under the +License. + +
+
+

For +complete documentation on STM32 Microcontrollers visit www.st.com/STM32

+
+

+
+
+

 

+
+ \ No newline at end of file diff --git a/Libraries/CMSIS/Device/ST/STM32F30x/Source/Templates/TrueSTUDIO/startup_stm32f30x.s b/Libraries/CMSIS/Device/ST/STM32F30x/Source/Templates/TrueSTUDIO/startup_stm32f30x.s new file mode 100644 index 0000000..4acbed8 --- /dev/null +++ b/Libraries/CMSIS/Device/ST/STM32F30x/Source/Templates/TrueSTUDIO/startup_stm32f30x.s @@ -0,0 +1,469 @@ +/** + ****************************************************************************** + * @file startup_stm32f30x.s + * @author MCD Application Team + * @version V1.0.0 + * @date 04-September-2012 + * @brief stm32f30x vector table for Atollic TrueSTUDIO toolchain. + * This module performs: + * - Set the initial SP + * - Set the initial PC == Reset_Handler, + * - Set the vector table entries with the exceptions ISR address, + * - Configure the clock system + * - Branches to main in the C library (which eventually + * calls main()). + * After Reset the Cortex-M4 processor is in Thread mode, + * priority is Privileged, and the Stack is set to Main. + ****************************************************************************** + * @attention + * + *

© COPYRIGHT 2012 STMicroelectronics

+ * + * Licensed under MCD-ST Liberty SW License Agreement V2, (the "License"); + * You may not use this file except in compliance with the License. + * You may obtain a copy of the License at: + * + * http://www.st.com/software_license_agreement_liberty_v2 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, + * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + * + ****************************************************************************** + */ + + .syntax unified + .cpu cortex-m4 + .fpu softvfp + .thumb + +.global g_pfnVectors +.global Default_Handler + +/* start address for the initialization values of the .data section. +defined in linker script */ +.word _sidata +/* start address for the .data section. defined in linker script */ +.word _sdata +/* end address for the .data section. defined in linker script */ +.word _edata +/* start address for the .bss section. defined in linker script */ +.word _sbss +/* end address for the .bss section. defined in linker script */ +.word _ebss + +.equ BootRAM, 0xF1E0F85F +/** + * @brief This is the code that gets called when the processor first + * starts execution following a reset event. Only the absolutely + * necessary set is performed, after which the application + * supplied main() routine is called. + * @param None + * @retval : None +*/ + + .section .text.Reset_Handler + .weak Reset_Handler + .type Reset_Handler, %function +Reset_Handler: + +/* Copy the data segment initializers from flash to SRAM */ + movs r1, #0 + b LoopCopyDataInit + +CopyDataInit: + ldr r3, =_sidata + ldr r3, [r3, r1] + str r3, [r0, r1] + adds r1, r1, #4 + +LoopCopyDataInit: + ldr r0, =_sdata + ldr r3, =_edata + adds r2, r0, r1 + cmp r2, r3 + bcc CopyDataInit + ldr r2, =_sbss + b LoopFillZerobss +/* Zero fill the bss segment. */ +FillZerobss: + movs r3, #0 + str r3, [r2], #4 + +LoopFillZerobss: + ldr r3, = _ebss + cmp r2, r3 + bcc FillZerobss + +/* Call the clock system intitialization function.*/ + bl SystemInit +/* Call static constructors */ + bl __libc_init_array +/* Call the application's entry point.*/ + bl main + +LoopForever: + b LoopForever + +.size Reset_Handler, .-Reset_Handler + +/** + * @brief This is the code that gets called when the processor receives an + * unexpected interrupt. This simply enters an infinite loop, preserving + * the system state for examination by a debugger. + * + * @param None + * @retval : None +*/ + .section .text.Default_Handler,"ax",%progbits +Default_Handler: +Infinite_Loop: + b Infinite_Loop + .size Default_Handler, .-Default_Handler +/****************************************************************************** +* +* The minimal vector table for a Cortex-M4. Note that the proper constructs +* must be placed on this to ensure that it ends up at physical address +* 0x0000.0000. +* +******************************************************************************/ + .section .isr_vector,"a",%progbits + .type g_pfnVectors, %object + .size g_pfnVectors, .-g_pfnVectors + + +g_pfnVectors: + .word _estack + .word Reset_Handler + .word NMI_Handler + .word HardFault_Handler + .word MemManage_Handler + .word BusFault_Handler + .word UsageFault_Handler + .word 0 + .word 0 + .word 0 + .word 0 + .word SVC_Handler + .word DebugMon_Handler + .word 0 + .word PendSV_Handler + .word SysTick_Handler + .word WWDG_IRQHandler + .word PVD_IRQHandler + .word TAMPER_STAMP_IRQHandler + .word RTC_WKUP_IRQHandler + .word FLASH_IRQHandler + .word RCC_IRQHandler + .word EXTI0_IRQHandler + .word EXTI1_IRQHandler + .word EXTI2_TS_IRQHandler + .word EXTI3_IRQHandler + .word EXTI4_IRQHandler + .word DMA1_Channel1_IRQHandler + .word DMA1_Channel2_IRQHandler + .word DMA1_Channel3_IRQHandler + .word DMA1_Channel4_IRQHandler + .word DMA1_Channel5_IRQHandler + .word DMA1_Channel6_IRQHandler + .word DMA1_Channel7_IRQHandler + .word ADC1_2_IRQHandler + .word USB_HP_CAN1_TX_IRQHandler + .word USB_LP_CAN1_RX0_IRQHandler + .word CAN1_RX1_IRQHandler + .word CAN1_SCE_IRQHandler + .word EXTI9_5_IRQHandler + .word TIM1_BRK_TIM15_IRQHandler + .word TIM1_UP_TIM16_IRQHandler + .word TIM1_TRG_COM_TIM17_IRQHandler + .word TIM1_CC_IRQHandler + .word TIM2_IRQHandler + .word TIM3_IRQHandler + .word TIM4_IRQHandler + .word I2C1_EV_IRQHandler + .word I2C1_ER_IRQHandler + .word I2C2_EV_IRQHandler + .word I2C2_ER_IRQHandler + .word SPI1_IRQHandler + .word SPI2_IRQHandler + .word USART1_IRQHandler + .word USART2_IRQHandler + .word USART3_IRQHandler + .word EXTI15_10_IRQHandler + .word RTC_Alarm_IRQHandler + .word USBWakeUp_IRQHandler + .word TIM8_BRK_IRQHandler + .word TIM8_UP_IRQHandler + .word TIM8_TRG_COM_IRQHandler + .word TIM8_CC_IRQHandler + .word ADC3_IRQHandler + .word 0 + .word 0 + .word 0 + .word SPI3_IRQHandler + .word UART4_IRQHandler + .word UART5_IRQHandler + .word TIM6_DAC_IRQHandler + .word TIM7_IRQHandler + .word DMA2_Channel1_IRQHandler + .word DMA2_Channel2_IRQHandler + .word DMA2_Channel3_IRQHandler + .word DMA2_Channel4_IRQHandler + .word DMA2_Channel5_IRQHandler + .word ADC4_IRQHandler + .word 0 + .word 0 + .word COMP1_2_3_IRQHandler + .word COMP4_5_6_IRQHandler + .word COMP7_IRQHandler + .word 0 + .word 0 + .word 0 + .word 0 + .word 0 + .word 0 + .word 0 + .word USB_HP_IRQHandler + .word USB_LP_IRQHandler + .word USBWakeUp_RMP_IRQHandler + .word 0 + .word 0 + .word 0 + .word 0 + .word FPU_IRQHandler + +/******************************************************************************* +* +* Provide weak aliases for each Exception handler to the Default_Handler. +* As they are weak aliases, any function with the same name will override +* this definition. +* +*******************************************************************************/ + + .weak NMI_Handler + .thumb_set NMI_Handler,Default_Handler + + .weak HardFault_Handler + .thumb_set HardFault_Handler,Default_Handler + + .weak MemManage_Handler + .thumb_set MemManage_Handler,Default_Handler + + .weak BusFault_Handler + .thumb_set BusFault_Handler,Default_Handler + + .weak UsageFault_Handler + .thumb_set UsageFault_Handler,Default_Handler + + .weak SVC_Handler + .thumb_set SVC_Handler,Default_Handler + + .weak DebugMon_Handler + .thumb_set DebugMon_Handler,Default_Handler + + .weak PendSV_Handler + .thumb_set PendSV_Handler,Default_Handler + + .weak SysTick_Handler + .thumb_set SysTick_Handler,Default_Handler + + .weak WWDG_IRQHandler + .thumb_set WWDG_IRQHandler,Default_Handler + + .weak PVD_IRQHandler + .thumb_set PVD_IRQHandler,Default_Handler + + .weak TAMPER_STAMP_IRQHandler + .thumb_set TAMPER_STAMP_IRQHandler,Default_Handler + + .weak RTC_WKUP_IRQHandler + .thumb_set RTC_WKUP_IRQHandler,Default_Handler + + .weak FLASH_IRQHandler + .thumb_set FLASH_IRQHandler,Default_Handler + + .weak RCC_IRQHandler + .thumb_set RCC_IRQHandler,Default_Handler + + .weak EXTI0_IRQHandler + .thumb_set EXTI0_IRQHandler,Default_Handler + + .weak EXTI1_IRQHandler + .thumb_set EXTI1_IRQHandler,Default_Handler + + .weak EXTI2_TS_IRQHandler + .thumb_set EXTI2_TS_IRQHandler,Default_Handler + + .weak EXTI3_IRQHandler + .thumb_set EXTI3_IRQHandler,Default_Handler + + .weak EXTI4_IRQHandler + .thumb_set EXTI4_IRQHandler,Default_Handler + + .weak DMA1_Channel1_IRQHandler + .thumb_set DMA1_Channel1_IRQHandler,Default_Handler + + .weak DMA1_Channel2_IRQHandler + .thumb_set DMA1_Channel2_IRQHandler,Default_Handler + + .weak DMA1_Channel3_IRQHandler + .thumb_set DMA1_Channel3_IRQHandler,Default_Handler + + .weak DMA1_Channel4_IRQHandler + .thumb_set DMA1_Channel4_IRQHandler,Default_Handler + + .weak DMA1_Channel5_IRQHandler + .thumb_set DMA1_Channel5_IRQHandler,Default_Handler + + .weak DMA1_Channel6_IRQHandler + .thumb_set DMA1_Channel6_IRQHandler,Default_Handler + + .weak DMA1_Channel7_IRQHandler + .thumb_set DMA1_Channel7_IRQHandler,Default_Handler + + .weak ADC1_2_IRQHandler + .thumb_set ADC1_2_IRQHandler,Default_Handler + + .weak USB_HP_CAN1_TX_IRQHandler + .thumb_set USB_HP_CAN1_TX_IRQHandler,Default_Handler + + .weak USB_LP_CAN1_RX0_IRQHandler + .thumb_set USB_LP_CAN1_RX0_IRQHandler,Default_Handler + + .weak CAN1_RX1_IRQHandler + .thumb_set CAN1_RX1_IRQHandler,Default_Handler + + .weak CAN1_SCE_IRQHandler + .thumb_set CAN1_SCE_IRQHandler,Default_Handler + + .weak EXTI9_5_IRQHandler + .thumb_set EXTI9_5_IRQHandler,Default_Handler + + .weak TIM1_BRK_TIM15_IRQHandler + .thumb_set TIM1_BRK_TIM15_IRQHandler,Default_Handler + + .weak TIM1_UP_TIM16_IRQHandler + .thumb_set TIM1_UP_TIM16_IRQHandler,Default_Handler + + .weak TIM1_TRG_COM_TIM17_IRQHandler + .thumb_set TIM1_TRG_COM_TIM17_IRQHandler,Default_Handler + + .weak TIM1_CC_IRQHandler + .thumb_set TIM1_CC_IRQHandler,Default_Handler + + .weak TIM2_IRQHandler + .thumb_set TIM2_IRQHandler,Default_Handler + + .weak TIM3_IRQHandler + .thumb_set TIM3_IRQHandler,Default_Handler + + .weak TIM4_IRQHandler + .thumb_set TIM4_IRQHandler,Default_Handler + + .weak I2C1_EV_IRQHandler + .thumb_set I2C1_EV_IRQHandler,Default_Handler + + .weak I2C1_ER_IRQHandler + .thumb_set I2C1_ER_IRQHandler,Default_Handler + + .weak I2C2_EV_IRQHandler + .thumb_set I2C2_EV_IRQHandler,Default_Handler + + .weak I2C2_ER_IRQHandler + .thumb_set I2C2_ER_IRQHandler,Default_Handler + + .weak SPI1_IRQHandler + .thumb_set SPI1_IRQHandler,Default_Handler + + .weak SPI2_IRQHandler + .thumb_set SPI2_IRQHandler,Default_Handler + + .weak USART1_IRQHandler + .thumb_set USART1_IRQHandler,Default_Handler + + .weak USART2_IRQHandler + .thumb_set USART2_IRQHandler,Default_Handler + + .weak USART3_IRQHandler + .thumb_set USART3_IRQHandler,Default_Handler + + .weak EXTI15_10_IRQHandler + .thumb_set EXTI15_10_IRQHandler,Default_Handler + + .weak RTC_Alarm_IRQHandler + .thumb_set RTC_Alarm_IRQHandler,Default_Handler + + .weak USBWakeUp_IRQHandler + .thumb_set USBWakeUp_IRQHandler,Default_Handler + + .weak TIM8_BRK_IRQHandler + .thumb_set TIM8_BRK_IRQHandler,Default_Handler + + .weak TIM8_UP_IRQHandler + .thumb_set TIM8_UP_IRQHandler,Default_Handler + + .weak TIM8_TRG_COM_IRQHandler + .thumb_set TIM8_TRG_COM_IRQHandler,Default_Handler + + .weak TIM8_CC_IRQHandler + .thumb_set TIM8_CC_IRQHandler,Default_Handler + + .weak ADC3_IRQHandler + .thumb_set ADC3_IRQHandler,Default_Handler + + .weak SPI3_IRQHandler + .thumb_set SPI3_IRQHandler,Default_Handler + + .weak UART4_IRQHandler + .thumb_set UART4_IRQHandler,Default_Handler + + .weak UART5_IRQHandler + .thumb_set UART5_IRQHandler,Default_Handler + + .weak TIM6_DAC_IRQHandler + .thumb_set TIM6_DAC_IRQHandler,Default_Handler + + .weak TIM7_IRQHandler + .thumb_set TIM7_IRQHandler,Default_Handler + + .weak DMA2_Channel1_IRQHandler + .thumb_set DMA2_Channel1_IRQHandler,Default_Handler + + .weak DMA2_Channel2_IRQHandler + .thumb_set DMA2_Channel2_IRQHandler,Default_Handler + + .weak DMA2_Channel3_IRQHandler + .thumb_set DMA2_Channel3_IRQHandler,Default_Handler + + .weak DMA2_Channel4_IRQHandler + .thumb_set DMA2_Channel4_IRQHandler,Default_Handler + + .weak DMA2_Channel5_IRQHandler + .thumb_set DMA2_Channel5_IRQHandler,Default_Handler + + .weak ADC4_IRQHandler + .thumb_set ADC4_IRQHandler,Default_Handler + + .weak COMP1_2_3_IRQHandler + .thumb_set COMP1_2_3_IRQHandler,Default_Handler + + .weak COMP4_5_6_IRQHandler + .thumb_set COMP4_5_6_IRQHandler,Default_Handler + + .weak COMP7_IRQHandler + .thumb_set COMP7_IRQHandler,Default_Handler + + .weak USB_HP_IRQHandler + .thumb_set USB_HP_IRQHandler,Default_Handler + + .weak USB_LP_IRQHandler + .thumb_set USB_LP_IRQHandler,Default_Handler + + .weak USBWakeUp_RMP_IRQHandler + .thumb_set USBWakeUp_RMP_IRQHandler,Default_Handler + + .weak FPU_IRQHandler + .thumb_set FPU_IRQHandler,Default_Handler +/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ diff --git a/Libraries/CMSIS/Device/ST/STM32F30x/Source/Templates/arm/startup_stm32f30x.s b/Libraries/CMSIS/Device/ST/STM32F30x/Source/Templates/arm/startup_stm32f30x.s new file mode 100644 index 0000000..897368a --- /dev/null +++ b/Libraries/CMSIS/Device/ST/STM32F30x/Source/Templates/arm/startup_stm32f30x.s @@ -0,0 +1,399 @@ +;******************** (C) COPYRIGHT 2012 STMicroelectronics ******************** +;* File Name : startup_stm32f30x.s +;* Author : MCD Application Team +;* Version : V1.0.0 +;* Date : 04-September-2012 +;* Description : STM32F30x devices vector table for MDK-ARM toolchain. +;* This module performs: +;* - Set the initial SP +;* - Set the initial PC == Reset_Handler +;* - Set the vector table entries with the exceptions ISR address +;* - Branches to __main in the C library (which eventually +;* calls main()). +;* After Reset the CortexM4 processor is in Thread mode, +;* priority is Privileged, and the Stack is set to Main. +;* <<< Use Configuration Wizard in Context Menu >>> +;******************************************************************************* +; +; Licensed under MCD-ST Liberty SW License Agreement V2, (the "License"); +; You may not use this file except in compliance with the License. +; You may obtain a copy of the License at: +; +; http://www.st.com/software_license_agreement_liberty_v2 +; +; Unless required by applicable law or agreed to in writing, software +; distributed under the License is distributed on an "AS IS" BASIS, +; WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +; See the License for the specific language governing permissions and +; limitations under the License. +; +;******************************************************************************* + +; Amount of memory (in bytes) allocated for Stack +; Tailor this value to your application needs +; Stack Configuration +; Stack Size (in Bytes) <0x0-0xFFFFFFFF:8> +; + +Stack_Size EQU 0x00000400 + + AREA STACK, NOINIT, READWRITE, ALIGN=3 +Stack_Mem SPACE Stack_Size +__initial_sp + + +; Heap Configuration +; Heap Size (in Bytes) <0x0-0xFFFFFFFF:8> +; + +Heap_Size EQU 0x00000200 + + AREA HEAP, NOINIT, READWRITE, ALIGN=3 +__heap_base +Heap_Mem SPACE Heap_Size +__heap_limit + + PRESERVE8 + THUMB + + +; Vector Table Mapped to Address 0 at Reset + AREA RESET, DATA, READONLY + EXPORT __Vectors + EXPORT __Vectors_End + EXPORT __Vectors_Size + +__Vectors DCD __initial_sp ; Top of Stack + DCD Reset_Handler ; Reset Handler + DCD NMI_Handler ; NMI Handler + DCD HardFault_Handler ; Hard Fault Handler + DCD MemManage_Handler ; MPU Fault Handler + DCD BusFault_Handler ; Bus Fault Handler + DCD UsageFault_Handler ; Usage Fault Handler + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD SVC_Handler ; SVCall Handler + DCD DebugMon_Handler ; Debug Monitor Handler + DCD 0 ; Reserved + DCD PendSV_Handler ; PendSV Handler + DCD SysTick_Handler ; SysTick Handler + + ; External Interrupts + DCD WWDG_IRQHandler ; Window WatchDog + DCD PVD_IRQHandler ; PVD through EXTI Line detection + DCD TAMPER_STAMP_IRQHandler ; Tamper and TimeStamps through the EXTI line + DCD RTC_WKUP_IRQHandler ; RTC Wakeup through the EXTI line + DCD FLASH_IRQHandler ; FLASH + DCD RCC_IRQHandler ; RCC + DCD EXTI0_IRQHandler ; EXTI Line0 + DCD EXTI1_IRQHandler ; EXTI Line1 + DCD EXTI2_TS_IRQHandler ; EXTI Line2 and Touch + DCD EXTI3_IRQHandler ; EXTI Line3 + DCD EXTI4_IRQHandler ; EXTI Line4 + DCD DMA1_Channel1_IRQHandler ; DMA1 Channel 1 + DCD DMA1_Channel2_IRQHandler ; DMA1 Channel 2 + DCD DMA1_Channel3_IRQHandler ; DMA1 Channel 3 + DCD DMA1_Channel4_IRQHandler ; DMA1 Channel 4 + DCD DMA1_Channel5_IRQHandler ; DMA1 Channel 5 + DCD DMA1_Channel6_IRQHandler ; DMA1 Channel 6 + DCD DMA1_Channel7_IRQHandler ; DMA1 Channel 7 + DCD ADC1_2_IRQHandler ; ADC1 and ADC2 + DCD USB_HP_CAN1_TX_IRQHandler ; USB Device High Priority or CAN1 TX + DCD USB_LP_CAN1_RX0_IRQHandler ; USB Device Low Priority or CAN1 RX0 + DCD CAN1_RX1_IRQHandler ; CAN1 RX1 + DCD CAN1_SCE_IRQHandler ; CAN1 SCE + DCD EXTI9_5_IRQHandler ; External Line[9:5]s + DCD TIM1_BRK_TIM15_IRQHandler ; TIM1 Break and TIM15 + DCD TIM1_UP_TIM16_IRQHandler ; TIM1 Update and TIM16 + DCD TIM1_TRG_COM_TIM17_IRQHandler ; TIM1 Trigger and Commutation and TIM17 + DCD TIM1_CC_IRQHandler ; TIM1 Capture Compare + DCD TIM2_IRQHandler ; TIM2 + DCD TIM3_IRQHandler ; TIM3 + DCD TIM4_IRQHandler ; TIM4 + DCD I2C1_EV_IRQHandler ; I2C1 Event + DCD I2C1_ER_IRQHandler ; I2C1 Error + DCD I2C2_EV_IRQHandler ; I2C2 Event + DCD I2C2_ER_IRQHandler ; I2C2 Error + DCD SPI1_IRQHandler ; SPI1 + DCD SPI2_IRQHandler ; SPI2 + DCD USART1_IRQHandler ; USART1 + DCD USART2_IRQHandler ; USART2 + DCD USART3_IRQHandler ; USART3 + DCD EXTI15_10_IRQHandler ; External Line[15:10]s + DCD RTC_Alarm_IRQHandler ; RTC Alarm (A and B) through EXTI Line + DCD USBWakeUp_IRQHandler ; USB Wakeup through EXTI line + DCD TIM8_BRK_IRQHandler ; TIM8 Break + DCD TIM8_UP_IRQHandler ; TIM8 Update + DCD TIM8_TRG_COM_IRQHandler ; TIM8 Trigger and Commutation + DCD TIM8_CC_IRQHandler ; TIM8 Capture Compare + DCD ADC3_IRQHandler ; ADC3 + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD SPI3_IRQHandler ; SPI3 + DCD UART4_IRQHandler ; UART4 + DCD UART5_IRQHandler ; UART5 + DCD TIM6_DAC_IRQHandler ; TIM6 and DAC1&2 underrun errors + DCD TIM7_IRQHandler ; TIM7 + DCD DMA2_Channel1_IRQHandler ; DMA2 Channel 1 + DCD DMA2_Channel2_IRQHandler ; DMA2 Channel 2 + DCD DMA2_Channel3_IRQHandler ; DMA2 Channel 3 + DCD DMA2_Channel4_IRQHandler ; DMA2 Channel 4 + DCD DMA2_Channel5_IRQHandler ; DMA2 Channel 5 + DCD ADC4_IRQHandler ; ADC4 + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD COMP1_2_3_IRQHandler ; COMP1, COMP2 and COMP3 + DCD COMP4_5_6_IRQHandler ; COMP4, COMP5 and COMP6 + DCD COMP7_IRQHandler ; COMP7 + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD USB_HP_IRQHandler ; USB High Priority remap + DCD USB_LP_IRQHandler ; USB Low Priority remap + DCD USBWakeUp_RMP_IRQHandler ; USB Wakeup remap through EXTI + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD FPU_IRQHandler ; FPU + +__Vectors_End + +__Vectors_Size EQU __Vectors_End - __Vectors + + AREA |.text|, CODE, READONLY + +; Reset handler +Reset_Handler PROC + EXPORT Reset_Handler [WEAK] + IMPORT SystemInit + IMPORT __main + + LDR R0, =SystemInit + BLX R0 + LDR R0, =__main + BX R0 + ENDP + +; Dummy Exception Handlers (infinite loops which can be modified) + +NMI_Handler PROC + EXPORT NMI_Handler [WEAK] + B . + ENDP +HardFault_Handler\ + PROC + EXPORT HardFault_Handler [WEAK] + B . + ENDP +MemManage_Handler\ + PROC + EXPORT MemManage_Handler [WEAK] + B . + ENDP +BusFault_Handler\ + PROC + EXPORT BusFault_Handler [WEAK] + B . + ENDP +UsageFault_Handler\ + PROC + EXPORT UsageFault_Handler [WEAK] + B . + ENDP +SVC_Handler PROC + EXPORT SVC_Handler [WEAK] + B . + ENDP +DebugMon_Handler\ + PROC + EXPORT DebugMon_Handler [WEAK] + B . + ENDP +PendSV_Handler PROC + EXPORT PendSV_Handler [WEAK] + B . + ENDP +SysTick_Handler PROC + EXPORT SysTick_Handler [WEAK] + B . + ENDP + +Default_Handler PROC + + EXPORT WWDG_IRQHandler [WEAK] + EXPORT PVD_IRQHandler [WEAK] + EXPORT TAMPER_STAMP_IRQHandler [WEAK] + EXPORT RTC_WKUP_IRQHandler [WEAK] + EXPORT FLASH_IRQHandler [WEAK] + EXPORT RCC_IRQHandler [WEAK] + EXPORT EXTI0_IRQHandler [WEAK] + EXPORT EXTI1_IRQHandler [WEAK] + EXPORT EXTI2_TS_IRQHandler [WEAK] + EXPORT EXTI3_IRQHandler [WEAK] + EXPORT EXTI4_IRQHandler [WEAK] + EXPORT DMA1_Channel1_IRQHandler [WEAK] + EXPORT DMA1_Channel2_IRQHandler [WEAK] + EXPORT DMA1_Channel3_IRQHandler [WEAK] + EXPORT DMA1_Channel4_IRQHandler [WEAK] + EXPORT DMA1_Channel5_IRQHandler [WEAK] + EXPORT DMA1_Channel6_IRQHandler [WEAK] + EXPORT DMA1_Channel7_IRQHandler [WEAK] + EXPORT ADC1_2_IRQHandler [WEAK] + EXPORT USB_HP_CAN1_TX_IRQHandler [WEAK] + EXPORT USB_LP_CAN1_RX0_IRQHandler [WEAK] + EXPORT CAN1_RX1_IRQHandler [WEAK] + EXPORT CAN1_SCE_IRQHandler [WEAK] + EXPORT EXTI9_5_IRQHandler [WEAK] + EXPORT TIM1_BRK_TIM15_IRQHandler [WEAK] + EXPORT TIM1_UP_TIM16_IRQHandler [WEAK] + EXPORT TIM1_TRG_COM_TIM17_IRQHandler [WEAK] + EXPORT TIM1_CC_IRQHandler [WEAK] + EXPORT TIM2_IRQHandler [WEAK] + EXPORT TIM3_IRQHandler [WEAK] + EXPORT TIM4_IRQHandler [WEAK] + EXPORT I2C1_EV_IRQHandler [WEAK] + EXPORT I2C1_ER_IRQHandler [WEAK] + EXPORT I2C2_EV_IRQHandler [WEAK] + EXPORT I2C2_ER_IRQHandler [WEAK] + EXPORT SPI1_IRQHandler [WEAK] + EXPORT SPI2_IRQHandler [WEAK] + EXPORT USART1_IRQHandler [WEAK] + EXPORT USART2_IRQHandler [WEAK] + EXPORT USART3_IRQHandler [WEAK] + EXPORT EXTI15_10_IRQHandler [WEAK] + EXPORT RTC_Alarm_IRQHandler [WEAK] + EXPORT USBWakeUp_IRQHandler [WEAK] + EXPORT TIM8_BRK_IRQHandler [WEAK] + EXPORT TIM8_UP_IRQHandler [WEAK] + EXPORT TIM8_TRG_COM_IRQHandler [WEAK] + EXPORT TIM8_CC_IRQHandler [WEAK] + EXPORT ADC3_IRQHandler [WEAK] + EXPORT SPI3_IRQHandler [WEAK] + EXPORT UART4_IRQHandler [WEAK] + EXPORT UART5_IRQHandler [WEAK] + EXPORT TIM6_DAC_IRQHandler [WEAK] + EXPORT TIM7_IRQHandler [WEAK] + EXPORT DMA2_Channel1_IRQHandler [WEAK] + EXPORT DMA2_Channel2_IRQHandler [WEAK] + EXPORT DMA2_Channel3_IRQHandler [WEAK] + EXPORT DMA2_Channel4_IRQHandler [WEAK] + EXPORT DMA2_Channel5_IRQHandler [WEAK] + EXPORT ADC4_IRQHandler [WEAK] + EXPORT COMP1_2_3_IRQHandler [WEAK] + EXPORT COMP4_5_6_IRQHandler [WEAK] + EXPORT COMP7_IRQHandler [WEAK] + EXPORT USB_HP_IRQHandler [WEAK] + EXPORT USB_LP_IRQHandler [WEAK] + EXPORT USBWakeUp_RMP_IRQHandler [WEAK] + EXPORT FPU_IRQHandler [WEAK] + +WWDG_IRQHandler +PVD_IRQHandler +TAMPER_STAMP_IRQHandler +RTC_WKUP_IRQHandler +FLASH_IRQHandler +RCC_IRQHandler +EXTI0_IRQHandler +EXTI1_IRQHandler +EXTI2_TS_IRQHandler +EXTI3_IRQHandler +EXTI4_IRQHandler +DMA1_Channel1_IRQHandler +DMA1_Channel2_IRQHandler +DMA1_Channel3_IRQHandler +DMA1_Channel4_IRQHandler +DMA1_Channel5_IRQHandler +DMA1_Channel6_IRQHandler +DMA1_Channel7_IRQHandler +ADC1_2_IRQHandler +USB_HP_CAN1_TX_IRQHandler +USB_LP_CAN1_RX0_IRQHandler +CAN1_RX1_IRQHandler +CAN1_SCE_IRQHandler +EXTI9_5_IRQHandler +TIM1_BRK_TIM15_IRQHandler +TIM1_UP_TIM16_IRQHandler +TIM1_TRG_COM_TIM17_IRQHandler +TIM1_CC_IRQHandler +TIM2_IRQHandler +TIM3_IRQHandler +TIM4_IRQHandler +I2C1_EV_IRQHandler +I2C1_ER_IRQHandler +I2C2_EV_IRQHandler +I2C2_ER_IRQHandler +SPI1_IRQHandler +SPI2_IRQHandler +USART1_IRQHandler +USART2_IRQHandler +USART3_IRQHandler +EXTI15_10_IRQHandler +RTC_Alarm_IRQHandler +USBWakeUp_IRQHandler +TIM8_BRK_IRQHandler +TIM8_UP_IRQHandler +TIM8_TRG_COM_IRQHandler +TIM8_CC_IRQHandler +ADC3_IRQHandler +SPI3_IRQHandler +UART4_IRQHandler +UART5_IRQHandler +TIM6_DAC_IRQHandler +TIM7_IRQHandler +DMA2_Channel1_IRQHandler +DMA2_Channel2_IRQHandler +DMA2_Channel3_IRQHandler +DMA2_Channel4_IRQHandler +DMA2_Channel5_IRQHandler +ADC4_IRQHandler +COMP1_2_3_IRQHandler +COMP4_5_6_IRQHandler +COMP7_IRQHandler +USB_HP_IRQHandler +USB_LP_IRQHandler +USBWakeUp_RMP_IRQHandler +FPU_IRQHandler + + B . + + ENDP + + ALIGN + +;******************************************************************************* +; User Stack and Heap initialization +;******************************************************************************* + IF :DEF:__MICROLIB + + EXPORT __initial_sp + EXPORT __heap_base + EXPORT __heap_limit + + ELSE + + IMPORT __use_two_region_memory + EXPORT __user_initial_stackheap + +__user_initial_stackheap + + LDR R0, = Heap_Mem + LDR R1, =(Stack_Mem + Stack_Size) + LDR R2, = (Heap_Mem + Heap_Size) + LDR R3, = Stack_Mem + BX LR + + ALIGN + + ENDIF + + END + +;************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE***** diff --git a/Libraries/CMSIS/Device/ST/STM32F30x/Source/Templates/gcc_ride7/startup_stm32f30x.s b/Libraries/CMSIS/Device/ST/STM32F30x/Source/Templates/gcc_ride7/startup_stm32f30x.s new file mode 100644 index 0000000..77efbdf --- /dev/null +++ b/Libraries/CMSIS/Device/ST/STM32F30x/Source/Templates/gcc_ride7/startup_stm32f30x.s @@ -0,0 +1,465 @@ +/** + ****************************************************************************** + * @file startup_stm32f30x.s + * @author MCD Application Team + * @version V1.0.0 + * @date 04-Spetember-2012 + * @brief STM32F30x Devices vector table for RIDE7 toolchain. + * This module performs: + * - Set the initial SP + * - Set the initial PC == Reset_Handler, + * - Set the vector table entries with the exceptions ISR address + * - Configure the clock system and the external SRAM mounted on + * STM3230C-EVAL board to be used as data memory (optional, + * to be enabled by user) + * - Branches to main in the C library (which eventually + * calls main()). + * After Reset the Cortex-M4 processor is in Thread mode, + * priority is Privileged, and the Stack is set to Main. + ****************************************************************************** + * @attention + * + *

© COPYRIGHT 2012 STMicroelectronics

+ * + * Licensed under MCD-ST Liberty SW License Agreement V2, (the "License"); + * You may not use this file except in compliance with the License. + * You may obtain a copy of the License at: + * + * http://www.st.com/software_license_agreement_liberty_v2 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, + * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + * + ****************************************************************************** + */ + + .syntax unified + .cpu cortex-m4 + .fpu softvfp + .thumb + +.global g_pfnVectors +.global Default_Handler + +/* start address for the initialization values of the .data section. +defined in linker script */ +.word _sidata +/* start address for the .data section. defined in linker script */ +.word _sdata +/* end address for the .data section. defined in linker script */ +.word _edata +/* start address for the .bss section. defined in linker script */ +.word _sbss +/* end address for the .bss section. defined in linker script */ +.word _ebss +/* stack used for SystemInit_ExtMemCtl; always internal RAM used */ + +/** + * @brief This is the code that gets called when the processor first + * starts execution following a reset event. Only the absolutely + * necessary set is performed, after which the application + * supplied main() routine is called. + * @param None + * @retval : None +*/ + + .section .text.Reset_Handler + .weak Reset_Handler + .type Reset_Handler, %function +Reset_Handler: + +/* Copy the data segment initializers from flash to SRAM */ + movs r1, #0 + b LoopCopyDataInit + +CopyDataInit: + ldr r3, =_sidata + ldr r3, [r3, r1] + str r3, [r0, r1] + adds r1, r1, #4 + +LoopCopyDataInit: + ldr r0, =_sdata + ldr r3, =_edata + adds r2, r0, r1 + cmp r2, r3 + bcc CopyDataInit + ldr r2, =_sbss + b LoopFillZerobss +/* Zero fill the bss segment. */ +FillZerobss: + movs r3, #0 + str r3, [r2], #4 + +LoopFillZerobss: + ldr r3, = _ebss + cmp r2, r3 + bcc FillZerobss + +/* Call the clock system intitialization function.*/ + bl SystemInit +/* Call the application's entry point.*/ + bl main + bx lr +.size Reset_Handler, .-Reset_Handler + +/** + * @brief This is the code that gets called when the processor receives an + * unexpected interrupt. This simply enters an infinite loop, preserving + * the system state for examination by a debugger. + * @param None + * @retval None +*/ + .section .text.Default_Handler,"ax",%progbits +Default_Handler: +Infinite_Loop: + b Infinite_Loop + .size Default_Handler, .-Default_Handler +/****************************************************************************** +* +* The minimal vector table for a Cortex M4. Note that the proper constructs +* must be placed on this to ensure that it ends up at physical address +* 0x0000.0000. +* +*******************************************************************************/ + .section .isr_vector,"a",%progbits + .type g_pfnVectors, %object + .size g_pfnVectors, .-g_pfnVectors + + +g_pfnVectors: + .word _estack + .word Reset_Handler + .word NMI_Handler + .word HardFault_Handler + .word MemManage_Handler + .word BusFault_Handler + .word UsageFault_Handler + .word 0 + .word 0 + .word 0 + .word 0 + .word SVC_Handler + .word DebugMon_Handler + .word 0 + .word PendSV_Handler + .word SysTick_Handler + .word WWDG_IRQHandler + .word PVD_IRQHandler + .word TAMPER_STAMP_IRQHandler + .word RTC_WKUP_IRQHandler + .word FLASH_IRQHandler + .word RCC_IRQHandler + .word EXTI0_IRQHandler + .word EXTI1_IRQHandler + .word EXTI2_TS_IRQHandler + .word EXTI3_IRQHandler + .word EXTI4_IRQHandler + .word DMA1_Channel1_IRQHandler + .word DMA1_Channel2_IRQHandler + .word DMA1_Channel3_IRQHandler + .word DMA1_Channel4_IRQHandler + .word DMA1_Channel5_IRQHandler + .word DMA1_Channel6_IRQHandler + .word DMA1_Channel7_IRQHandler + .word ADC1_2_IRQHandler + .word USB_HP_CAN1_TX_IRQHandler + .word USB_LP_CAN1_RX0_IRQHandler + .word CAN1_RX1_IRQHandler + .word CAN1_SCE_IRQHandler + .word EXTI9_5_IRQHandler + .word TIM1_BRK_TIM15_IRQHandler + .word TIM1_UP_TIM16_IRQHandler + .word TIM1_TRG_COM_TIM17_IRQHandler + .word TIM1_CC_IRQHandler + .word TIM2_IRQHandler + .word TIM3_IRQHandler + .word TIM4_IRQHandler + .word I2C1_EV_IRQHandler + .word I2C1_ER_IRQHandler + .word I2C2_EV_IRQHandler + .word I2C2_ER_IRQHandler + .word SPI1_IRQHandler + .word SPI2_IRQHandler + .word USART1_IRQHandler + .word USART2_IRQHandler + .word USART3_IRQHandler + .word EXTI15_10_IRQHandler + .word RTC_Alarm_IRQHandler + .word USBWakeUp_IRQHandler + .word TIM8_BRK_IRQHandler + .word TIM8_UP_IRQHandler + .word TIM8_TRG_COM_IRQHandler + .word TIM8_CC_IRQHandler + .word ADC3_IRQHandler + .word 0 + .word 0 + .word 0 + .word SPI3_IRQHandler + .word UART4_IRQHandler + .word UART5_IRQHandler + .word TIM6_DAC_IRQHandler + .word TIM7_IRQHandler + .word DMA2_Channel1_IRQHandler + .word DMA2_Channel2_IRQHandler + .word DMA2_Channel3_IRQHandler + .word DMA2_Channel4_IRQHandler + .word DMA2_Channel5_IRQHandler + .word ADC4_IRQHandler + .word 0 + .word 0 + .word COMP1_2_3_IRQHandler + .word COMP4_5_6_IRQHandler + .word COMP7_IRQHandler + .word 0 + .word 0 + .word 0 + .word 0 + .word 0 + .word 0 + .word 0 + .word USB_HP_IRQHandler + .word USB_LP_IRQHandler + .word USBWakeUp_RMP_IRQHandler + .word 0 + .word 0 + .word 0 + .word 0 + .word FPU_IRQHandler + +/******************************************************************************* +* +* Provide weak aliases for each Exception handler to the Default_Handler. +* As they are weak aliases, any function with the same name will override +* this definition. +* +*******************************************************************************/ + + .weak NMI_Handler + .thumb_set NMI_Handler,Default_Handler + + .weak HardFault_Handler + .thumb_set HardFault_Handler,Default_Handler + + .weak MemManage_Handler + .thumb_set MemManage_Handler,Default_Handler + + .weak BusFault_Handler + .thumb_set BusFault_Handler,Default_Handler + + .weak UsageFault_Handler + .thumb_set UsageFault_Handler,Default_Handler + + .weak SVC_Handler + .thumb_set SVC_Handler,Default_Handler + + .weak DebugMon_Handler + .thumb_set DebugMon_Handler,Default_Handler + + .weak PendSV_Handler + .thumb_set PendSV_Handler,Default_Handler + + .weak SysTick_Handler + .thumb_set SysTick_Handler,Default_Handler + + .weak WWDG_IRQHandler + .thumb_set WWDG_IRQHandler,Default_Handler + + .weak PVD_IRQHandler + .thumb_set PVD_IRQHandler,Default_Handler + + .weak TAMPER_STAMP_IRQHandler + .thumb_set TAMPER_STAMP_IRQHandler,Default_Handler + + .weak RTC_WKUP_IRQHandler + .thumb_set RTC_WKUP_IRQHandler,Default_Handler + + .weak FLASH_IRQHandler + .thumb_set FLASH_IRQHandler,Default_Handler + + .weak RCC_IRQHandler + .thumb_set RCC_IRQHandler,Default_Handler + + .weak EXTI0_IRQHandler + .thumb_set EXTI0_IRQHandler,Default_Handler + + .weak EXTI1_IRQHandler + .thumb_set EXTI1_IRQHandler,Default_Handler + + .weak EXTI2_TS_IRQHandler + .thumb_set EXTI2_TS_IRQHandler,Default_Handler + + .weak EXTI3_IRQHandler + .thumb_set EXTI3_IRQHandler,Default_Handler + + .weak EXTI4_IRQHandler + .thumb_set EXTI4_IRQHandler,Default_Handler + + .weak DMA1_Channel1_IRQHandler + .thumb_set DMA1_Channel1_IRQHandler,Default_Handler + + .weak DMA1_Channel2_IRQHandler + .thumb_set DMA1_Channel2_IRQHandler,Default_Handler + + .weak DMA1_Channel3_IRQHandler + .thumb_set DMA1_Channel3_IRQHandler,Default_Handler + + .weak DMA1_Channel4_IRQHandler + .thumb_set DMA1_Channel4_IRQHandler,Default_Handler + + .weak DMA1_Channel5_IRQHandler + .thumb_set DMA1_Channel5_IRQHandler,Default_Handler + + .weak DMA1_Channel6_IRQHandler + .thumb_set DMA1_Channel6_IRQHandler,Default_Handler + + .weak DMA1_Channel7_IRQHandler + .thumb_set DMA1_Channel7_IRQHandler,Default_Handler + + .weak ADC1_2_IRQHandler + .thumb_set ADC1_2_IRQHandler,Default_Handler + + .weak USB_HP_CAN1_TX_IRQHandler + .thumb_set USB_HP_CAN1_TX_IRQHandler,Default_Handler + + .weak USB_LP_CAN1_RX0_IRQHandler + .thumb_set USB_LP_CAN1_RX0_IRQHandler,Default_Handler + + .weak CAN1_RX1_IRQHandler + .thumb_set CAN1_RX1_IRQHandler,Default_Handler + + .weak CAN1_SCE_IRQHandler + .thumb_set CAN1_SCE_IRQHandler,Default_Handler + + .weak EXTI9_5_IRQHandler + .thumb_set EXTI9_5_IRQHandler,Default_Handler + + .weak TIM1_BRK_TIM15_IRQHandler + .thumb_set TIM1_BRK_TIM15_IRQHandler,Default_Handler + + .weak TIM1_UP_TIM16_IRQHandler + .thumb_set TIM1_UP_TIM16_IRQHandler,Default_Handler + + .weak TIM1_TRG_COM_TIM17_IRQHandler + .thumb_set TIM1_TRG_COM_TIM17_IRQHandler,Default_Handler + + .weak TIM1_CC_IRQHandler + .thumb_set TIM1_CC_IRQHandler,Default_Handler + + .weak TIM2_IRQHandler + .thumb_set TIM2_IRQHandler,Default_Handler + + .weak TIM3_IRQHandler + .thumb_set TIM3_IRQHandler,Default_Handler + + .weak TIM4_IRQHandler + .thumb_set TIM4_IRQHandler,Default_Handler + + .weak I2C1_EV_IRQHandler + .thumb_set I2C1_EV_IRQHandler,Default_Handler + + .weak I2C1_ER_IRQHandler + .thumb_set I2C1_ER_IRQHandler,Default_Handler + + .weak I2C2_EV_IRQHandler + .thumb_set I2C2_EV_IRQHandler,Default_Handler + + .weak I2C2_ER_IRQHandler + .thumb_set I2C2_ER_IRQHandler,Default_Handler + + .weak SPI1_IRQHandler + .thumb_set SPI1_IRQHandler,Default_Handler + + .weak SPI2_IRQHandler + .thumb_set SPI2_IRQHandler,Default_Handler + + .weak USART1_IRQHandler + .thumb_set USART1_IRQHandler,Default_Handler + + .weak USART2_IRQHandler + .thumb_set USART2_IRQHandler,Default_Handler + + .weak USART3_IRQHandler + .thumb_set USART3_IRQHandler,Default_Handler + + .weak EXTI15_10_IRQHandler + .thumb_set EXTI15_10_IRQHandler,Default_Handler + + .weak RTC_Alarm_IRQHandler + .thumb_set RTC_Alarm_IRQHandler,Default_Handler + + .weak USBWakeUp_IRQHandler + .thumb_set USBWakeUp_IRQHandler,Default_Handler + + .weak TIM8_BRK_IRQHandler + .thumb_set TIM8_BRK_IRQHandler,Default_Handler + + .weak TIM8_UP_IRQHandler + .thumb_set TIM8_UP_IRQHandler,Default_Handler + + .weak TIM8_TRG_COM_IRQHandler + .thumb_set TIM8_TRG_COM_IRQHandler,Default_Handler + + .weak TIM8_CC_IRQHandler + .thumb_set TIM8_CC_IRQHandler,Default_Handler + + .weak ADC3_IRQHandler + .thumb_set ADC3_IRQHandler,Default_Handler + + .weak SPI3_IRQHandler + .thumb_set SPI3_IRQHandler,Default_Handler + + .weak UART4_IRQHandler + .thumb_set UART4_IRQHandler,Default_Handler + + .weak UART5_IRQHandler + .thumb_set UART5_IRQHandler,Default_Handler + + .weak TIM6_DAC_IRQHandler + .thumb_set TIM6_DAC_IRQHandler,Default_Handler + + .weak TIM7_IRQHandler + .thumb_set TIM7_IRQHandler,Default_Handler + + .weak DMA2_Channel1_IRQHandler + .thumb_set DMA2_Channel1_IRQHandler,Default_Handler + + .weak DMA2_Channel2_IRQHandler + .thumb_set DMA2_Channel2_IRQHandler,Default_Handler + + .weak DMA2_Channel3_IRQHandler + .thumb_set DMA2_Channel3_IRQHandler,Default_Handler + + .weak DMA2_Channel4_IRQHandler + .thumb_set DMA2_Channel4_IRQHandler,Default_Handler + + .weak DMA2_Channel5_IRQHandler + .thumb_set DMA2_Channel5_IRQHandler,Default_Handler + + .weak ADC4_IRQHandler + .thumb_set ADC4_IRQHandler,Default_Handler + + .weak COMP1_2_3_IRQHandler + .thumb_set COMP1_2_3_IRQHandler,Default_Handler + + .weak COMP4_5_6_IRQHandler + .thumb_set COMP4_5_6_IRQHandler,Default_Handler + + .weak COMP7_IRQHandler + .thumb_set COMP7_IRQHandler,Default_Handler + + .weak USB_HP_IRQHandler + .thumb_set USB_HP_IRQHandler,Default_Handler + + .weak USB_LP_IRQHandler + .thumb_set USB_LP_IRQHandler,Default_Handler + + .weak USBWakeUp_RMP_IRQHandler + .thumb_set USBWakeUp_RMP_IRQHandler,Default_Handler + + .weak FPU_IRQHandler + .thumb_set FPU_IRQHandler,Default_Handler +/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ diff --git a/Libraries/CMSIS/Device/ST/STM32F30x/Source/Templates/iar/startup_stm32f30x.s b/Libraries/CMSIS/Device/ST/STM32F30x/Source/Templates/iar/startup_stm32f30x.s new file mode 100644 index 0000000..d8db7d0 --- /dev/null +++ b/Libraries/CMSIS/Device/ST/STM32F30x/Source/Templates/iar/startup_stm32f30x.s @@ -0,0 +1,554 @@ +;/******************** (C) COPYRIGHT 2012 STMicroelectronics ******************** +;* File Name : startup_stm32f30x.s +;* Author : MCD Application Team +;* Version : V1.0.0 +;* Date : 04-Sptember-2012 +;* Description : STM32F30x devices vector table for EWARM toolchain. +;* This module performs: +;* - Set the initial SP +;* - Set the initial PC == _iar_program_start, +;* - Set the vector table entries with the exceptions ISR +;* address. +;* - Branches to main in the C library (which eventually +;* calls main()). +;* After Reset the Cortex-M4 processor is in Thread mode, +;* priority is Privileged, and the Stack is set to Main. +;******************************************************************************** +;* +;* Licensed under MCD-ST Liberty SW License Agreement V2, (the "License"); +;* You may not use this file except in compliance with the License. +;* You may obtain a copy of the License at: +;* +;* http://www.st.com/software_license_agreement_liberty_v2 +;* +;* Unless required by applicable law or agreed to in writing, software +;* distributed under the License is distributed on an "AS IS" BASIS, +;* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +;* See the License for the specific language governing permissions and +;* limitations under the License. +;* +;******************************************************************************* +; +; +; The modules in this file are included in the libraries, and may be replaced +; by any user-defined modules that define the PUBLIC symbol _program_start or +; a user defined start symbol. +; To override the cstartup defined in the library, simply add your modified +; version to the workbench project. +; +; The vector table is normally located at address 0. +; When debugging in RAM, it can be located in RAM, aligned to at least 2^6. +; The name "__vector_table" has special meaning for C-SPY: +; it is where the SP start value is found, and the NVIC vector +; table register (VTOR) is initialized to this address if != 0. +; +; Cortex-M version +; + + MODULE ?cstartup + + ;; Forward declaration of sections. + SECTION CSTACK:DATA:NOROOT(3) + + SECTION .intvec:CODE:NOROOT(2) + + EXTERN __iar_program_start + EXTERN SystemInit + PUBLIC __vector_table + + DATA +__vector_table + DCD sfe(CSTACK) + DCD Reset_Handler ; Reset Handler + + DCD NMI_Handler ; NMI Handler + DCD HardFault_Handler ; Hard Fault Handler + DCD MemManage_Handler ; MPU Fault Handler + DCD BusFault_Handler ; Bus Fault Handler + DCD UsageFault_Handler ; Usage Fault Handler + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD SVC_Handler ; SVCall Handler + DCD DebugMon_Handler ; Debug Monitor Handler + DCD 0 ; Reserved + DCD PendSV_Handler ; PendSV Handler + DCD SysTick_Handler ; SysTick Handler + + ; External Interrupts + DCD WWDG_IRQHandler ; Window WatchDog + DCD PVD_IRQHandler ; PVD through EXTI Line detection + DCD TAMPER_STAMP_IRQHandler ; Tamper and TimeStamps through the EXTI line + DCD RTC_WKUP_IRQHandler ; RTC Wakeup through the EXTI line + DCD FLASH_IRQHandler ; FLASH + DCD RCC_IRQHandler ; RCC + DCD EXTI0_IRQHandler ; EXTI Line0 + DCD EXTI1_IRQHandler ; EXTI Line1 + DCD EXTI2_TS_IRQHandler ; EXTI Line2 and Touch Sense + DCD EXTI3_IRQHandler ; EXTI Line3 + DCD EXTI4_IRQHandler ; EXTI Line4 + DCD DMA1_Channel1_IRQHandler ; DMA1 Channel 1 + DCD DMA1_Channel2_IRQHandler ; DMA1 Channel 2 + DCD DMA1_Channel3_IRQHandler ; DMA1 Channel 3 + DCD DMA1_Channel4_IRQHandler ; DMA1 Channel 4 + DCD DMA1_Channel5_IRQHandler ; DMA1 Channel 5 + DCD DMA1_Channel6_IRQHandler ; DMA1 Channel 6 + DCD DMA1_Channel7_IRQHandler ; DMA1 Channel 7 + DCD ADC1_2_IRQHandler ; ADC1 and ADC2 + DCD USB_HP_CAN1_TX_IRQHandler ; USB Device High Priority or CAN1 TX + DCD USB_LP_CAN1_RX0_IRQHandler ; USB Device Low Priority or CAN1 RX0 + DCD CAN1_RX1_IRQHandler ; CAN1 RX1 + DCD CAN1_SCE_IRQHandler ; CAN1 SCE + DCD EXTI9_5_IRQHandler ; External Line[9:5]s + DCD TIM1_BRK_TIM15_IRQHandler ; TIM1 Break and TIM15 + DCD TIM1_UP_TIM16_IRQHandler ; TIM1 Update and TIM16 + DCD TIM1_TRG_COM_TIM17_IRQHandler ; TIM1 Trigger and Commutation and TIM17 + DCD TIM1_CC_IRQHandler ; TIM1 Capture Compare + DCD TIM2_IRQHandler ; TIM2 + DCD TIM3_IRQHandler ; TIM3 + DCD TIM4_IRQHandler ; TIM4 + DCD I2C1_EV_IRQHandler ; I2C1 Event + DCD I2C1_ER_IRQHandler ; I2C1 Error + DCD I2C2_EV_IRQHandler ; I2C2 Event + DCD I2C2_ER_IRQHandler ; I2C2 Error + DCD SPI1_IRQHandler ; SPI1 + DCD SPI2_IRQHandler ; SPI2 + DCD USART1_IRQHandler ; USART1 + DCD USART2_IRQHandler ; USART2 + DCD USART3_IRQHandler ; USART3 + DCD EXTI15_10_IRQHandler ; External Line[15:10]s + DCD RTC_Alarm_IRQHandler ; RTC Alarm (A and B) through EXTI Line + DCD USBWakeUp_IRQHandler ; USB Wakeup through EXTI line + DCD TIM8_BRK_IRQHandler ; TIM8 Break + DCD TIM8_UP_IRQHandler ; TIM8 Update + DCD TIM8_TRG_COM_IRQHandler ; TIM8 Trigger and Commutation + DCD TIM8_CC_IRQHandler ; TIM8 Capture Compare + DCD ADC3_IRQHandler ; ADC3 + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD SPI3_IRQHandler ; SPI3 + DCD UART4_IRQHandler ; UART4 + DCD UART5_IRQHandler ; UART5 + DCD TIM6_DAC_IRQHandler ; TIM6 and DAC1&2 underrun errors + DCD TIM7_IRQHandler ; TIM7 + DCD DMA2_Channel1_IRQHandler ; DMA2 Channel 1 + DCD DMA2_Channel2_IRQHandler ; DMA2 Channel 2 + DCD DMA2_Channel3_IRQHandler ; DMA2 Channel 3 + DCD DMA2_Channel4_IRQHandler ; DMA2 Channel 4 + DCD DMA2_Channel5_IRQHandler ; DMA2 Channel 5 + DCD ADC4_IRQHandler ; ADC4 + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD COMP1_2_3_IRQHandler ; COMP1, COMP2 and COMP3 + DCD COMP4_5_6_IRQHandler ; COMP4, COMP5 and COMP6 + DCD COMP7_IRQHandler ; COMP7 + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD USB_HP_IRQHandler ; USB High Priority remap + DCD USB_LP_IRQHandler ; USB Low Priority remap + DCD USBWakeUp_RMP_IRQHandler ; USB Wakeup remap through EXTI + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD FPU_IRQHandler ; FPU + +;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;; +;; +;; Default interrupt handlers. +;; + THUMB + PUBWEAK Reset_Handler + SECTION .text:CODE:REORDER(2) +Reset_Handler + + LDR R0, =SystemInit + BLX R0 + LDR R0, =__iar_program_start + BX R0 + + PUBWEAK NMI_Handler + SECTION .text:CODE:REORDER(1) +NMI_Handler + B NMI_Handler + + PUBWEAK HardFault_Handler + SECTION .text:CODE:REORDER(1) +HardFault_Handler + B HardFault_Handler + + PUBWEAK MemManage_Handler + SECTION .text:CODE:REORDER(1) +MemManage_Handler + B MemManage_Handler + + PUBWEAK BusFault_Handler + SECTION .text:CODE:REORDER(1) +BusFault_Handler + B BusFault_Handler + + PUBWEAK UsageFault_Handler + SECTION .text:CODE:REORDER(1) +UsageFault_Handler + B UsageFault_Handler + + PUBWEAK SVC_Handler + SECTION .text:CODE:REORDER(1) +SVC_Handler + B SVC_Handler + + PUBWEAK DebugMon_Handler + SECTION .text:CODE:REORDER(1) +DebugMon_Handler + B DebugMon_Handler + + PUBWEAK PendSV_Handler + SECTION .text:CODE:REORDER(1) +PendSV_Handler + B PendSV_Handler + + PUBWEAK SysTick_Handler + SECTION .text:CODE:REORDER(1) +SysTick_Handler + B SysTick_Handler + + PUBWEAK WWDG_IRQHandler + SECTION .text:CODE:REORDER(1) +WWDG_IRQHandler + B WWDG_IRQHandler + + PUBWEAK PVD_IRQHandler + SECTION .text:CODE:REORDER(1) +PVD_IRQHandler + B PVD_IRQHandler + + PUBWEAK TAMPER_STAMP_IRQHandler + SECTION .text:CODE:REORDER(1) +TAMPER_STAMP_IRQHandler + B TAMPER_STAMP_IRQHandler + + PUBWEAK RTC_WKUP_IRQHandler + SECTION .text:CODE:REORDER(1) +RTC_WKUP_IRQHandler + B RTC_WKUP_IRQHandler + + PUBWEAK FLASH_IRQHandler + SECTION .text:CODE:REORDER(1) +FLASH_IRQHandler + B FLASH_IRQHandler + + PUBWEAK RCC_IRQHandler + SECTION .text:CODE:REORDER(1) +RCC_IRQHandler + B RCC_IRQHandler + + PUBWEAK EXTI0_IRQHandler + SECTION .text:CODE:REORDER(1) +EXTI0_IRQHandler + B EXTI0_IRQHandler + + PUBWEAK EXTI1_IRQHandler + SECTION .text:CODE:REORDER(1) +EXTI1_IRQHandler + B EXTI1_IRQHandler + + PUBWEAK EXTI2_TS_IRQHandler + SECTION .text:CODE:REORDER(1) +EXTI2_TS_IRQHandler + B EXTI2_TS_IRQHandler + + PUBWEAK EXTI3_IRQHandler + SECTION .text:CODE:REORDER(1) +EXTI3_IRQHandler + B EXTI3_IRQHandler + + PUBWEAK EXTI4_IRQHandler + SECTION .text:CODE:REORDER(1) +EXTI4_IRQHandler + B EXTI4_IRQHandler + + PUBWEAK DMA1_Channel1_IRQHandler + SECTION .text:CODE:REORDER(1) +DMA1_Channel1_IRQHandler + B DMA1_Channel1_IRQHandler + + PUBWEAK DMA1_Channel2_IRQHandler + SECTION .text:CODE:REORDER(1) +DMA1_Channel2_IRQHandler + B DMA1_Channel2_IRQHandler + + PUBWEAK DMA1_Channel3_IRQHandler + SECTION .text:CODE:REORDER(1) +DMA1_Channel3_IRQHandler + B DMA1_Channel3_IRQHandler + + PUBWEAK DMA1_Channel4_IRQHandler + SECTION .text:CODE:REORDER(1) +DMA1_Channel4_IRQHandler + B DMA1_Channel4_IRQHandler + + PUBWEAK DMA1_Channel5_IRQHandler + SECTION .text:CODE:REORDER(1) +DMA1_Channel5_IRQHandler + B DMA1_Channel5_IRQHandler + + PUBWEAK DMA1_Channel6_IRQHandler + SECTION .text:CODE:REORDER(1) +DMA1_Channel6_IRQHandler + B DMA1_Channel6_IRQHandler + + PUBWEAK DMA1_Channel7_IRQHandler + SECTION .text:CODE:REORDER(1) +DMA1_Channel7_IRQHandler + B DMA1_Channel7_IRQHandler + + PUBWEAK ADC1_2_IRQHandler + SECTION .text:CODE:REORDER(1) +ADC1_2_IRQHandler + B ADC1_2_IRQHandler + + PUBWEAK USB_HP_CAN1_TX_IRQHandler + SECTION .text:CODE:REORDER(1) +USB_HP_CAN1_TX_IRQHandler + B USB_HP_CAN1_TX_IRQHandler + + PUBWEAK USB_LP_CAN1_RX0_IRQHandler + SECTION .text:CODE:REORDER(1) +USB_LP_CAN1_RX0_IRQHandler + B USB_LP_CAN1_RX0_IRQHandler + + PUBWEAK CAN1_RX1_IRQHandler + SECTION .text:CODE:REORDER(1) +CAN1_RX1_IRQHandler + B CAN1_RX1_IRQHandler + + PUBWEAK CAN1_SCE_IRQHandler + SECTION .text:CODE:REORDER(1) +CAN1_SCE_IRQHandler + B CAN1_SCE_IRQHandler + + PUBWEAK EXTI9_5_IRQHandler + SECTION .text:CODE:REORDER(1) +EXTI9_5_IRQHandler + B EXTI9_5_IRQHandler + + PUBWEAK TIM1_BRK_TIM15_IRQHandler + SECTION .text:CODE:REORDER(1) +TIM1_BRK_TIM15_IRQHandler + B TIM1_BRK_TIM15_IRQHandler + + PUBWEAK TIM1_UP_TIM16_IRQHandler + SECTION .text:CODE:REORDER(1) +TIM1_UP_TIM16_IRQHandler + B TIM1_UP_TIM16_IRQHandler + + PUBWEAK TIM1_TRG_COM_TIM17_IRQHandler + SECTION .text:CODE:REORDER(1) +TIM1_TRG_COM_TIM17_IRQHandler + B TIM1_TRG_COM_TIM17_IRQHandler + + PUBWEAK TIM1_CC_IRQHandler + SECTION .text:CODE:REORDER(1) +TIM1_CC_IRQHandler + B TIM1_CC_IRQHandler + + PUBWEAK TIM2_IRQHandler + SECTION .text:CODE:REORDER(1) +TIM2_IRQHandler + B TIM2_IRQHandler + + PUBWEAK TIM3_IRQHandler + SECTION .text:CODE:REORDER(1) +TIM3_IRQHandler + B TIM3_IRQHandler + + PUBWEAK TIM4_IRQHandler + SECTION .text:CODE:REORDER(1) +TIM4_IRQHandler + B TIM4_IRQHandler + + PUBWEAK I2C1_EV_IRQHandler + SECTION .text:CODE:REORDER(1) +I2C1_EV_IRQHandler + B I2C1_EV_IRQHandler + + PUBWEAK I2C1_ER_IRQHandler + SECTION .text:CODE:REORDER(1) +I2C1_ER_IRQHandler + B I2C1_ER_IRQHandler + + PUBWEAK I2C2_EV_IRQHandler + SECTION .text:CODE:REORDER(1) +I2C2_EV_IRQHandler + B I2C2_EV_IRQHandler + + PUBWEAK I2C2_ER_IRQHandler + SECTION .text:CODE:REORDER(1) +I2C2_ER_IRQHandler + B I2C2_ER_IRQHandler + + PUBWEAK SPI1_IRQHandler + SECTION .text:CODE:REORDER(1) +SPI1_IRQHandler + B SPI1_IRQHandler + + PUBWEAK SPI2_IRQHandler + SECTION .text:CODE:REORDER(1) +SPI2_IRQHandler + B SPI2_IRQHandler + + PUBWEAK USART1_IRQHandler + SECTION .text:CODE:REORDER(1) +USART1_IRQHandler + B USART1_IRQHandler + + PUBWEAK USART2_IRQHandler + SECTION .text:CODE:REORDER(1) +USART2_IRQHandler + B USART2_IRQHandler + + PUBWEAK USART3_IRQHandler + SECTION .text:CODE:REORDER(1) +USART3_IRQHandler + B USART3_IRQHandler + + PUBWEAK EXTI15_10_IRQHandler + SECTION .text:CODE:REORDER(1) +EXTI15_10_IRQHandler + B EXTI15_10_IRQHandler + + PUBWEAK RTC_Alarm_IRQHandler + SECTION .text:CODE:REORDER(1) +RTC_Alarm_IRQHandler + B RTC_Alarm_IRQHandler + + PUBWEAK USBWakeUp_IRQHandler + SECTION .text:CODE:REORDER(1) +USBWakeUp_IRQHandler + B USBWakeUp_IRQHandler + + PUBWEAK TIM8_BRK_IRQHandler + SECTION .text:CODE:REORDER(1) +TIM8_BRK_IRQHandler + B TIM8_BRK_IRQHandler + + PUBWEAK TIM8_UP_IRQHandler + SECTION .text:CODE:REORDER(1) +TIM8_UP_IRQHandler + B TIM8_UP_IRQHandler + + PUBWEAK TIM8_TRG_COM_IRQHandler + SECTION .text:CODE:REORDER(1) +TIM8_TRG_COM_IRQHandler + B TIM8_TRG_COM_IRQHandler + + PUBWEAK TIM8_CC_IRQHandler + SECTION .text:CODE:REORDER(1) +TIM8_CC_IRQHandler + B TIM8_CC_IRQHandler + + PUBWEAK ADC3_IRQHandler + SECTION .text:CODE:REORDER(1) +ADC3_IRQHandler + B ADC3_IRQHandler + + PUBWEAK SPI3_IRQHandler + SECTION .text:CODE:REORDER(1) +SPI3_IRQHandler + B SPI3_IRQHandler + + PUBWEAK UART4_IRQHandler + SECTION .text:CODE:REORDER(1) +UART4_IRQHandler + B UART4_IRQHandler + + PUBWEAK UART5_IRQHandler + SECTION .text:CODE:REORDER(1) +UART5_IRQHandler + B UART5_IRQHandler + + PUBWEAK TIM6_DAC_IRQHandler + SECTION .text:CODE:REORDER(1) +TIM6_DAC_IRQHandler + B TIM6_DAC_IRQHandler + + PUBWEAK TIM7_IRQHandler + SECTION .text:CODE:REORDER(1) +TIM7_IRQHandler + B TIM7_IRQHandler + + PUBWEAK DMA2_Channel1_IRQHandler + SECTION .text:CODE:REORDER(1) +DMA2_Channel1_IRQHandler + B DMA2_Channel1_IRQHandler + + PUBWEAK DMA2_Channel2_IRQHandler + SECTION .text:CODE:REORDER(1) +DMA2_Channel2_IRQHandler + B DMA2_Channel2_IRQHandler + + PUBWEAK DMA2_Channel3_IRQHandler + SECTION .text:CODE:REORDER(1) +DMA2_Channel3_IRQHandler + B DMA2_Channel3_IRQHandler + + PUBWEAK DMA2_Channel4_IRQHandler + SECTION .text:CODE:REORDER(1) +DMA2_Channel4_IRQHandler + B DMA2_Channel4_IRQHandler + + PUBWEAK DMA2_Channel5_IRQHandler + SECTION .text:CODE:REORDER(1) +DMA2_Channel5_IRQHandler + B DMA2_Channel5_IRQHandler + + + PUBWEAK ADC4_IRQHandler + SECTION .text:CODE:REORDER(1) +ADC4_IRQHandler + B ADC4_IRQHandler + + PUBWEAK COMP1_2_3_IRQHandler + SECTION .text:CODE:REORDER(1) +COMP1_2_3_IRQHandler + B COMP1_2_3_IRQHandler + + PUBWEAK COMP4_5_6_IRQHandler + SECTION .text:CODE:REORDER(1) +COMP4_5_6_IRQHandler + B COMP4_5_6_IRQHandler + + PUBWEAK COMP7_IRQHandler + SECTION .text:CODE:REORDER(1) +COMP7_IRQHandler + B COMP7_IRQHandler + + PUBWEAK USB_HP_IRQHandler + SECTION .text:CODE:REORDER(1) +USB_HP_IRQHandler + B USB_HP_IRQHandler + + PUBWEAK USB_LP_IRQHandler + SECTION .text:CODE:REORDER(1) +USB_LP_IRQHandler + B USB_LP_IRQHandler + + PUBWEAK USBWakeUp_RMP_IRQHandler + SECTION .text:CODE:REORDER(1) +USBWakeUp_RMP_IRQHandler + B USBWakeUp_RMP_IRQHandler + + PUBWEAK FPU_IRQHandler + SECTION .text:CODE:REORDER(1) +FPU_IRQHandler + B FPU_IRQHandler + + END +/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ diff --git a/Libraries/CMSIS/Device/ST/STM32F30x/Source/Templates/system_stm32f30x.c b/Libraries/CMSIS/Device/ST/STM32F30x/Source/Templates/system_stm32f30x.c new file mode 100644 index 0000000..831bd65 --- /dev/null +++ b/Libraries/CMSIS/Device/ST/STM32F30x/Source/Templates/system_stm32f30x.c @@ -0,0 +1,382 @@ +/** + ****************************************************************************** + * @file system_stm32f30x.c + * @author MCD Application Team + * @version V1.0.0 + * @date 04-September-2012 + * @brief CMSIS Cortex-M4 Device Peripheral Access Layer System Source File. + * This file contains the system clock configuration for STM32F30x devices, + * and is generated by the clock configuration tool + * stm32f30x_Clock_Configuration_V1.0.0.xls + * + * 1. This file provides two functions and one global variable to be called from + * user application: + * - SystemInit(): Setups the system clock (System clock source, PLL Multiplier + * and Divider factors, AHB/APBx prescalers and Flash settings), + * depending on the configuration made in the clock xls tool. + * This function is called at startup just after reset and + * before branch to main program. This call is made inside + * the "startup_stm32f30x.s" file. + * + * - SystemCoreClock variable: Contains the core clock (HCLK), it can be used + * by the user application to setup the SysTick + * timer or configure other parameters. + * + * - SystemCoreClockUpdate(): Updates the variable SystemCoreClock and must + * be called whenever the core clock is changed + * during program execution. + * + * 2. After each device reset the HSI (8 MHz) is used as system clock source. + * Then SystemInit() function is called, in "startup_stm32f30x.s" file, to + * configure the system clock before to branch to main program. + * + * 3. If the system clock source selected by user fails to startup, the SystemInit() + * function will do nothing and HSI still used as system clock source. User can + * add some code to deal with this issue inside the SetSysClock() function. + * + * 4. The default value of HSE crystal is set to 8MHz, refer to "HSE_VALUE" define + * in "stm32f30x.h" file. When HSE is used as system clock source, directly or + * through PLL, and you are using different crystal you have to adapt the HSE + * value to your own configuration. + * + * 5. This file configures the system clock as follows: + *============================================================================= + * Supported STM32F30x device + *----------------------------------------------------------------------------- + * System Clock source | PLL (HSE) + *----------------------------------------------------------------------------- + * SYSCLK(Hz) | 72000000 + *----------------------------------------------------------------------------- + * HCLK(Hz) | 72000000 + *----------------------------------------------------------------------------- + * AHB Prescaler | 1 + *----------------------------------------------------------------------------- + * APB2 Prescaler | 1 + *----------------------------------------------------------------------------- + * APB1 Prescaler | 2 + *----------------------------------------------------------------------------- + * HSE Frequency(Hz) | 8000000 + *---------------------------------------------------------------------------- + * PLLMUL | 9 + *----------------------------------------------------------------------------- + * PREDIV | 1 + *----------------------------------------------------------------------------- + * USB Clock | DISABLE + *----------------------------------------------------------------------------- + * Flash Latency(WS) | 2 + *----------------------------------------------------------------------------- + * Prefetch Buffer | ON + *----------------------------------------------------------------------------- + *============================================================================= + ****************************************************************************** + * @attention + * + *

© COPYRIGHT 2012 STMicroelectronics

+ * + * Licensed under MCD-ST Liberty SW License Agreement V2, (the "License"); + * You may not use this file except in compliance with the License. + * You may obtain a copy of the License at: + * + * http://www.st.com/software_license_agreement_liberty_v2 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, + * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + * + ****************************************************************************** + */ +/** @addtogroup CMSIS + * @{ + */ + +/** @addtogroup stm32f30x_system + * @{ + */ + +/** @addtogroup STM32F30x_System_Private_Includes + * @{ + */ + +#include "stm32f30x.h" + +/** + * @} + */ + +/** @addtogroup STM32F30x_System_Private_TypesDefinitions + * @{ + */ + +/** + * @} + */ + +/** @addtogroup STM32F30x_System_Private_Defines + * @{ + */ +/*!< Uncomment the following line if you need to relocate your vector Table in + Internal SRAM. */ +/* #define VECT_TAB_SRAM */ +#define VECT_TAB_OFFSET 0x0 /*!< Vector Table base offset field. + This value must be a multiple of 0x200. */ +/** + * @} + */ + +/** @addtogroup STM32F30x_System_Private_Macros + * @{ + */ + +/** + * @} + */ + +/** @addtogroup STM32F30x_System_Private_Variables + * @{ + */ + + uint32_t SystemCoreClock = 72000000; + + __I uint8_t AHBPrescTable[16] = {0, 0, 0, 0, 0, 0, 0, 0, 1, 2, 3, 4, 6, 7, 8, 9}; + +/** + * @} + */ + +/** @addtogroup STM32F30x_System_Private_FunctionPrototypes + * @{ + */ + +static void SetSysClock(void); + +/** + * @} + */ + +/** @addtogroup STM32F30x_System_Private_Functions + * @{ + */ + +/** + * @brief Setup the microcontroller system + * Initialize the Embedded Flash Interface, the PLL and update the + * SystemFrequency variable. + * @param None + * @retval None + */ +void SystemInit(void) +{ + /* FPU settings ------------------------------------------------------------*/ + #if (__FPU_PRESENT == 1) && (__FPU_USED == 1) + SCB->CPACR |= ((3UL << 10*2)|(3UL << 11*2)); /* set CP10 and CP11 Full Access */ + #endif + + /* Reset the RCC clock configuration to the default reset state ------------*/ + /* Set HSION bit */ + RCC->CR |= (uint32_t)0x00000001; + + /* Reset CFGR register */ + RCC->CFGR &= 0xF87FC00C; + + /* Reset HSEON, CSSON and PLLON bits */ + RCC->CR &= (uint32_t)0xFEF6FFFF; + + /* Reset HSEBYP bit */ + RCC->CR &= (uint32_t)0xFFFBFFFF; + + /* Reset PLLSRC, PLLXTPRE, PLLMUL and USBPRE bits */ + RCC->CFGR &= (uint32_t)0xFF80FFFF; + + /* Reset PREDIV1[3:0] bits */ + RCC->CFGR2 &= (uint32_t)0xFFFFFFF0; + + /* Reset USARTSW[1:0], I2CSW and TIMs bits */ + RCC->CFGR3 &= (uint32_t)0xFF00FCCC; + + /* Disable all interrupts */ + RCC->CIR = 0x00000000; + + /* Configure the System clock source, PLL Multiplier and Divider factors, + AHB/APBx prescalers and Flash settings ----------------------------------*/ + SetSysClock(); + +#ifdef VECT_TAB_SRAM + SCB->VTOR = SRAM_BASE | VECT_TAB_OFFSET; /* Vector Table Relocation in Internal SRAM. */ +#else + SCB->VTOR = FLASH_BASE | VECT_TAB_OFFSET; /* Vector Table Relocation in Internal FLASH. */ +#endif +} + +/** + * @brief Update SystemCoreClock variable according to Clock Register Values. + * The SystemCoreClock variable contains the core clock (HCLK), it can + * be used by the user application to setup the SysTick timer or configure + * other parameters. + * + * @note Each time the core clock (HCLK) changes, this function must be called + * to update SystemCoreClock variable value. Otherwise, any configuration + * based on this variable will be incorrect. + * + * @note - The system frequency computed by this function is not the real + * frequency in the chip. It is calculated based on the predefined + * constant and the selected clock source: + * + * - If SYSCLK source is HSI, SystemCoreClock will contain the HSI_VALUE(*) + * + * - If SYSCLK source is HSE, SystemCoreClock will contain the HSE_VALUE(**) + * + * - If SYSCLK source is PLL, SystemCoreClock will contain the HSE_VALUE(**) + * or HSI_VALUE(*) multiplied/divided by the PLL factors. + * + * (*) HSI_VALUE is a constant defined in stm32f30x.h file (default value + * 8 MHz) but the real value may vary depending on the variations + * in voltage and temperature. + * + * (**) HSE_VALUE is a constant defined in stm32f30x.h file (default value + * 8 MHz), user has to ensure that HSE_VALUE is same as the real + * frequency of the crystal used. Otherwise, this function may + * have wrong result. + * + * - The result of this function could be not correct when using fractional + * value for HSE crystal. + * + * @param None + * @retval None + */ +void SystemCoreClockUpdate (void) +{ + uint32_t tmp = 0, pllmull = 0, pllsource = 0, prediv1factor = 0; + + /* Get SYSCLK source -------------------------------------------------------*/ + tmp = RCC->CFGR & RCC_CFGR_SWS; + + switch (tmp) + { + case 0x00: /* HSI used as system clock */ + SystemCoreClock = HSI_VALUE; + break; + case 0x04: /* HSE used as system clock */ + SystemCoreClock = HSE_VALUE; + break; + case 0x08: /* PLL used as system clock */ + /* Get PLL clock source and multiplication factor ----------------------*/ + pllmull = RCC->CFGR & RCC_CFGR_PLLMULL; + pllsource = RCC->CFGR & RCC_CFGR_PLLSRC; + pllmull = ( pllmull >> 18) + 2; + + if (pllsource == 0x00) + { + /* HSI oscillator clock divided by 2 selected as PLL clock entry */ + SystemCoreClock = (HSI_VALUE >> 1) * pllmull; + } + else + { + prediv1factor = (RCC->CFGR2 & RCC_CFGR2_PREDIV1) + 1; + /* HSE oscillator clock selected as PREDIV1 clock entry */ + SystemCoreClock = (HSE_VALUE / prediv1factor) * pllmull; + } + break; + default: /* HSI used as system clock */ + SystemCoreClock = HSI_VALUE; + break; + } + /* Compute HCLK clock frequency ----------------*/ + /* Get HCLK prescaler */ + tmp = AHBPrescTable[((RCC->CFGR & RCC_CFGR_HPRE) >> 4)]; + /* HCLK clock frequency */ + SystemCoreClock >>= tmp; +} + +/** + * @brief Configures the System clock source, PLL Multiplier and Divider factors, + * AHB/APBx prescalers and Flash settings + * @note This function should be called only once the RCC clock configuration + * is reset to the default reset state (done in SystemInit() function). + * @param None + * @retval None + */ +static void SetSysClock(void) +{ + __IO uint32_t StartUpCounter = 0, HSEStatus = 0; + +/******************************************************************************/ +/* PLL (clocked by HSE) used as System clock source */ +/******************************************************************************/ + + /* SYSCLK, HCLK, PCLK2 and PCLK1 configuration -----------*/ + /* Enable HSE */ + RCC->CR |= ((uint32_t)RCC_CR_HSEON); + + /* Wait till HSE is ready and if Time out is reached exit */ + do + { + HSEStatus = RCC->CR & RCC_CR_HSERDY; + StartUpCounter++; + } while((HSEStatus == 0) && (StartUpCounter != HSE_STARTUP_TIMEOUT)); + + if ((RCC->CR & RCC_CR_HSERDY) != RESET) + { + HSEStatus = (uint32_t)0x01; + } + else + { + HSEStatus = (uint32_t)0x00; + } + + if (HSEStatus == (uint32_t)0x01) + { + /* Enable Prefetch Buffer and set Flash Latency */ + FLASH->ACR = FLASH_ACR_PRFTBE | (uint32_t)FLASH_ACR_LATENCY_1; + + /* HCLK = SYSCLK / 1 */ + RCC->CFGR |= (uint32_t)RCC_CFGR_HPRE_DIV1; + + /* PCLK2 = HCLK / 1 */ + RCC->CFGR |= (uint32_t)RCC_CFGR_PPRE2_DIV1; + + /* PCLK1 = HCLK / 2 */ + RCC->CFGR |= (uint32_t)RCC_CFGR_PPRE1_DIV2; + + /* PLL configuration */ + RCC->CFGR &= (uint32_t)((uint32_t)~(RCC_CFGR_PLLSRC | RCC_CFGR_PLLXTPRE | RCC_CFGR_PLLMULL)); + RCC->CFGR |= (uint32_t)(RCC_CFGR_PLLSRC_PREDIV1 | RCC_CFGR_PLLXTPRE_PREDIV1 | RCC_CFGR_PLLMULL9); + + /* Enable PLL */ + RCC->CR |= RCC_CR_PLLON; + + /* Wait till PLL is ready */ + while((RCC->CR & RCC_CR_PLLRDY) == 0) + { + } + + /* Select PLL as system clock source */ + RCC->CFGR &= (uint32_t)((uint32_t)~(RCC_CFGR_SW)); + RCC->CFGR |= (uint32_t)RCC_CFGR_SW_PLL; + + /* Wait till PLL is used as system clock source */ + while ((RCC->CFGR & (uint32_t)RCC_CFGR_SWS) != (uint32_t)RCC_CFGR_SWS_PLL) + { + } + } + else + { /* If HSE fails to start-up, the application will have wrong clock + configuration. User can add here some code to deal with this error */ + } +} + +/** + * @} + */ + +/** + * @} + */ + +/** + * @} + */ + +/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ + diff --git a/Libraries/CMSIS/Device/ST/STM32F37x/Include/stm32f37x.h b/Libraries/CMSIS/Device/ST/STM32F37x/Include/stm32f37x.h new file mode 100644 index 0000000..9cbd5ae --- /dev/null +++ b/Libraries/CMSIS/Device/ST/STM32F37x/Include/stm32f37x.h @@ -0,0 +1,5438 @@ +/** + ****************************************************************************** + * @file stm32f37x.h + * @author MCD Application Team + * @version V1.0.0 + * @date 20-September-2012 + * @brief CMSIS Cortex-M4 Device Peripheral Access Layer Header File. + * This file contains all the peripheral registers definitions, bits + * definitions and memory mapping for STM32F37x devices. + * + * The file is the unique include file that the application programmer + * is using in the C source code, usually in main.c. This file contains: + * - Configuration section that allows to select: + * - The device used in the target application + * - To use or not the peripherals drivers in application code(i.e. + * code will be based on direct access to peripherals registers + * rather than drivers API), this option is controlled by + * "#define USE_STDPERIPH_DRIVER" + * - To change few application-specific parameters such as the HSE + * crystal frequency + * - Data structures and the address mapping for all peripherals + * - Peripheral registers declarations and bits definition + * - Macros to access peripheral registers hardware + * + ****************************************************************************** + * @attention + * + * THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS + * WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE + * TIME. AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY + * DIRECT, INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING + * FROM THE CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE + * CODING INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS. + * + * FOR MORE INFORMATION PLEASE READ CAREFULLY THE LICENSE AGREEMENT FILE + * LOCATED IN THE ROOT DIRECTORY OF THIS FIRMWARE PACKAGE. + * + *

© COPYRIGHT 2012 STMicroelectronics

+ ****************************************************************************** + */ + +/** @addtogroup CMSIS + * @{ + */ + +/** @addtogroup stm32f37x + * @{ + */ + +#ifndef __STM32F37x_H +#define __STM32F37x_H + +#ifdef __cplusplus + extern "C" { +#endif /* __cplusplus */ + +/** @addtogroup Library_configuration_section + * @{ + */ + +/* Uncomment the line below according to the target STM32 device used in your + application + */ + +#if !defined (STM32F37X) + #define STM32F37X +#endif + +/* Tip: To avoid modifying this file each time you need to switch between these + devices, you can define the device in your toolchain compiler preprocessor. + */ + +#if !defined (STM32F37X) + #error "Please select first the target STM32F37X device used in your application (in stm32f37x.h file)" +#endif + +#if !defined (USE_STDPERIPH_DRIVER) +/** + * @brief Comment the line below if you will not use the peripherals drivers. + In this case, these drivers will not be included and the application code will + be based on direct access to peripherals registers + */ + /*#define USE_STDPERIPH_DRIVER*/ +#endif /* USE_STDPERIPH_DRIVER */ + +/** + * @brief In the following line adjust the value of External High Speed oscillator (HSE) + used in your application + + Tip: To avoid modifying this file each time you need to use different HSE, you + can define the HSE value in your toolchain compiler preprocessor. + */ +#if !defined (HSE_VALUE) + #define HSE_VALUE ((uint32_t)8000000) /*!< Value of the External oscillator in Hz */ +#endif /* HSE_VALUE */ +/** + * @brief In the following line adjust the External High Speed oscillator (HSE) Startup + Timeout value + */ +#if !defined (HSE_STARTUP_TIMEOUT) + #define HSE_STARTUP_TIMEOUT ((uint16_t)0x0500) /*!< Time out for HSE start up */ +#endif /* HSE_STARTUP_TIMEOUT */ +/** + * @brief In the following line adjust the Internal High Speed oscillator (HSI) Startup + Timeout value + */ +#define HSI_STARTUP_TIMEOUT ((uint16_t)0x0500) /*!< Time out for HSI start up */ + +#if !defined (HSI_VALUE) + #define HSI_VALUE ((uint32_t)8000000) +#endif /* HSI_VALUE */ /*!< Value of the Internal High Speed oscillator in Hz. + The real value may vary depending on the variations + in voltage and temperature. */ +#if !defined (LSI_VALUE) + #define LSI_VALUE ((uint32_t)40000) +#endif /* LSI_VALUE */ /*!< Value of the Internal Low Speed oscillator in Hz + The real value may vary depending on the variations + in voltage and temperature. */ +#if !defined (LSE_VALUE) + #define LSE_VALUE ((uint32_t)32768) /*!< Value of the External Low Speed oscillator in Hz */ +#endif /* LSE_VALUE */ + +/** + * @brief STM32F37x Standard Peripherals Library version number V1.0.0 + */ +#define __STM32F37X_STDPERIPH_VERSION_MAIN (0x01) /*!< [31:24] main version */ +#define __STM32F37X_STDPERIPH_VERSION_SUB1 (0x00) /*!< [23:16] sub1 version */ +#define __STM32F37X_STDPERIPH_VERSION_SUB2 (0x00) /*!< [15:8] sub2 version */ +#define __STM32F37X_STDPERIPH_VERSION_RC (0x00) /*!< [7:0] release candidate */ +#define __STM32F37X_STDPERIPH_VERSION ( (__STM32F37X_STDPERIPH_VERSION_MAIN << 24)\ + |(__STM32F37X_STDPERIPH_VERSION_SUB1 << 16)\ + |(__STM32F37X_STDPERIPH_VERSION_SUB2 << 8)\ + |(__STM32F37X_STDPERIPH_VERSION_RC)) + +/** + * @} + */ + +/** @addtogroup Configuration_section_for_CMSIS + * @{ + */ + +/** + * @brief Configuration of the Cortex-M4 Processor and Core Peripherals + */ +#define __CM4_REV 0x0001 /*!< Core revision r0p1 */ +#define __MPU_PRESENT 1 /*!< STM32F37X provide an MPU */ +#define __NVIC_PRIO_BITS 4 /*!< STM32F37X uses 4 Bits for the Priority Levels */ +#define __Vendor_SysTickConfig 0 /*!< Set to 1 if different SysTick Config is used */ +#define __FPU_PRESENT 1 /*!< STM32F37X provide an FPU */ + + +/** + * @brief STM32F37X Interrupt Number Definition, according to the selected device + * in @ref Library_configuration_section + */ +typedef enum IRQn +{ +/****** Cortex-M4 Processor Exceptions Numbers ****************************************************************/ + NonMaskableInt_IRQn = -14, /*!< 2 Non Maskable Interrupt */ + MemoryManagement_IRQn = -12, /*!< 4 Cortex-M4 Memory Management Interrupt */ + BusFault_IRQn = -11, /*!< 5 Cortex-M4 Bus Fault Interrupt */ + UsageFault_IRQn = -10, /*!< 6 Cortex-M4 Usage Fault Interrupt */ + SVCall_IRQn = -5, /*!< 11 Cortex-M4 SV Call Interrupt */ + DebugMonitor_IRQn = -4, /*!< 12 Cortex-M4 Debug Monitor Interrupt */ + PendSV_IRQn = -2, /*!< 14 Cortex-M4 Pend SV Interrupt */ + SysTick_IRQn = -1, /*!< 15 Cortex-M4 System Tick Interrupt */ +/****** STM32 specific Interrupt Numbers **********************************************************************/ + WWDG_IRQn = 0, /*!< Window WatchDog Interrupt */ + PVD_IRQn = 1, /*!< PVD through EXTI Line detection Interrupt */ + TAMPER_STAMP_IRQn = 2, /*!< Tamper and TimeStamp interrupts through the EXTI line 19 */ + RTC_WKUP_IRQn = 3, /*!< RTC Wakeup interrupt through the EXTI line 20 */ + FLASH_IRQn = 4, /*!< FLASH global Interrupt */ + RCC_IRQn = 5, /*!< RCC global Interrupt */ + EXTI0_IRQn = 6, /*!< EXTI Line0 Interrupt */ + EXTI1_IRQn = 7, /*!< EXTI Line1 Interrupt */ + EXTI2_TS_IRQn = 8, /*!< EXTI Line2 Interrupt and Touch Sense Interrupt */ + EXTI3_IRQn = 9, /*!< EXTI Line3 Interrupt */ + EXTI4_IRQn = 10, /*!< EXTI Line4 Interrupt */ + DMA1_Channel1_IRQn = 11, /*!< DMA1 Channel 1 Interrupt */ + DMA1_Channel2_IRQn = 12, /*!< DMA1 Channel 2 Interrupt */ + DMA1_Channel3_IRQn = 13, /*!< DMA1 Channel 3 Interrupt */ + DMA1_Channel4_IRQn = 14, /*!< DMA1 Channel 4 Interrupt */ + DMA1_Channel5_IRQn = 15, /*!< DMA1 Channel 5 Interrupt */ + DMA1_Channel6_IRQn = 16, /*!< DMA1 Channel 6 Interrupt */ + DMA1_Channel7_IRQn = 17, /*!< DMA1 Channel 7 Interrupt */ + ADC1_IRQn = 18, /*!< ADC1 Interrupts */ + CAN1_TX_IRQn = 19, /*!< CAN1 TX Interrupt */ + CAN1_RX0_IRQn = 20, /*!< CAN1 RX0 Interrupt */ + CAN1_RX1_IRQn = 21, /*!< CAN1 RX1 Interrupt */ + CAN1_SCE_IRQn = 22, /*!< CAN1 SCE Interrupt */ + EXTI9_5_IRQn = 23, /*!< External Line[9:5] Interrupts */ + TIM15_IRQn = 24, /*!< TIM15 global Interrupt */ + TIM16_IRQn = 25, /*!< TIM16 global Interrupt */ + TIM17_IRQn = 26, /*!< TIM17 global Interrupt */ + TIM18_DAC2_IRQn = 27, /*!< TIM18 global Interrupt and DAC2 underrun Interrupt */ + TIM2_IRQn = 28, /*!< TIM2 global Interrupt */ + TIM3_IRQn = 29, /*!< TIM3 global Interrupt */ + TIM4_IRQn = 30, /*!< TIM4 global Interrupt */ + I2C1_EV_IRQn = 31, /*!< I2C1 Event Interrupt */ + I2C1_ER_IRQn = 32, /*!< I2C1 Error Interrupt */ + I2C2_EV_IRQn = 33, /*!< I2C2 Event Interrupt */ + I2C2_ER_IRQn = 34, /*!< I2C2 Error Interrupt */ + SPI1_IRQn = 35, /*!< SPI1 global Interrupt */ + SPI2_IRQn = 36, /*!< SPI2 global Interrupt */ + USART1_IRQn = 37, /*!< USART1 global Interrupt */ + USART2_IRQn = 38, /*!< USART2 global Interrupt */ + USART3_IRQn = 39, /*!< USART3 global Interrupt */ + EXTI15_10_IRQn = 40, /*!< External Line[15:10] Interrupts */ + RTC_Alarm_IRQn = 41, /*!< RTC Alarm (A and B) through EXTI Line Interrupt */ + CEC_IRQn = 42, /*!< CEC Interrupt */ + TIM12_IRQn = 43, /*!< TIM12 global interrupt */ + TIM13_IRQn = 44, /*!< TIM13 global interrupt */ + TIM14_IRQn = 45, /*!< TIM14 global interrupt */ + TIM5_IRQn = 50, /*!< TIM5 global Interrupt */ + SPI3_IRQn = 51, /*!< SPI3 global Interrupt */ + TIM6_DAC1_IRQn = 54, /*!< TIM6 global and DAC1 Cahnnel1 & Cahnnel2 underrun error Interrupts*/ + TIM7_IRQn = 55, /*!< TIM7 global Interrupt */ + DMA2_Channel1_IRQn = 56, /*!< DMA2 Channel 1 global Interrupt */ + DMA2_Channel2_IRQn = 57, /*!< DMA2 Channel 2 global Interrupt */ + DMA2_Channel3_IRQn = 58, /*!< DMA2 Channel 3 global Interrupt */ + DMA2_Channel4_IRQn = 59, /*!< DMA2 Channel 4 global Interrupt */ + DMA2_Channel5_IRQn = 60, /*!< DMA2 Channel 5 global Interrupt */ + SDADC1_IRQn = 61, /*!< ADC Sigma Delta 1 global Interrupt */ + SDADC2_IRQn = 62, /*!< ADC Sigma Delta 2 global Interrupt */ + SDADC3_IRQn = 63, /*!< ADC Sigma Delta 1 global Interrupt */ + COMP_IRQn = 64, /*!< COMP1 and COMP2 global Interrupt */ + USB_HP_IRQn = 74, /*!< USB High Priority global Interrupt */ + USB_LP_IRQn = 75, /*!< USB Low Priority global Interrupt */ + USBWakeUp_IRQn = 76, /*!< USB Wakeup Interrupt */ + TIM19_IRQn = 78, /*!< TIM19 global Interrupt */ + FPU_IRQn = 81 /*!< Floating point Interrupt */ +} IRQn_Type; + +/** + * @} + */ + +#include "core_cm4.h" /* Cortex-M4 processor and core peripherals */ +#include "system_stm32f37x.h" /* STM32F37x System Header */ +#include + +/** @addtogroup Exported_types + * @{ + */ +/*!< STM32F10x Standard Peripheral Library old types (maintained for legacy purpose) */ +typedef int32_t s32; +typedef int16_t s16; +typedef int8_t s8; + +typedef const int32_t sc32; /*!< Read Only */ +typedef const int16_t sc16; /*!< Read Only */ +typedef const int8_t sc8; /*!< Read Only */ + +typedef __IO int32_t vs32; +typedef __IO int16_t vs16; +typedef __IO int8_t vs8; + +typedef __I int32_t vsc32; /*!< Read Only */ +typedef __I int16_t vsc16; /*!< Read Only */ +typedef __I int8_t vsc8; /*!< Read Only */ + +typedef uint32_t u32; +typedef uint16_t u16; +typedef uint8_t u8; + +typedef const uint32_t uc32; /*!< Read Only */ +typedef const uint16_t uc16; /*!< Read Only */ +typedef const uint8_t uc8; /*!< Read Only */ + +typedef __IO uint32_t vu32; +typedef __IO uint16_t vu16; +typedef __IO uint8_t vu8; + +typedef __I uint32_t vuc32; /*!< Read Only */ +typedef __I uint16_t vuc16; /*!< Read Only */ +typedef __I uint8_t vuc8; /*!< Read Only */ + +typedef enum {RESET = 0, SET = !RESET} FlagStatus, ITStatus; + +typedef enum {DISABLE = 0, ENABLE = !DISABLE} FunctionalState; +#define IS_FUNCTIONAL_STATE(STATE) (((STATE) == DISABLE) || ((STATE) == ENABLE)) + +typedef enum {ERROR = 0, SUCCESS = !ERROR} ErrorStatus; + +/** + * @} + */ + +/** @addtogroup Peripheral_registers_structures + * @{ + */ + +/** + * @brief Analog to Digital Converter + */ + +typedef struct +{ + __IO uint32_t SR; /*!< ADC status register, Address offset: 0x00 */ + __IO uint32_t CR1; /*!< ADC control register 1, Address offset: 0x04 */ + __IO uint32_t CR2; /*!< ADC control register 2, Address offset: 0x08 */ + __IO uint32_t SMPR1; /*!< ADC sample time register 1, Address offset: 0x0C */ + __IO uint32_t SMPR2; /*!< ADC sample time register 2, Address offset: 0x10 */ + __IO uint32_t JOFR1; /*!< ADC injected channel data offset register 1, Address offset: 0x14 */ + __IO uint32_t JOFR2; /*!< ADC injected channel data offset register 2, Address offset: 0x18 */ + __IO uint32_t JOFR3; /*!< ADC injected channel data offset register 3, Address offset: 0x1C */ + __IO uint32_t JOFR4; /*!< ADC injected channel data offset register 4, Address offset: 0x20 */ + __IO uint32_t HTR; /*!< ADC watchdog higher threshold register, Address offset: 0x24 */ + __IO uint32_t LTR; /*!< ADC watchdog lower threshold register, Address offset: 0x28 */ + __IO uint32_t SQR1; /*!< ADC regular sequence register 1, Address offset: 0x2C */ + __IO uint32_t SQR2; /*!< ADC regular sequence register 2, Address offset: 0x30 */ + __IO uint32_t SQR3; /*!< ADC regular sequence register 3, Address offset: 0x34 */ + __IO uint32_t JSQR; /*!< ADC injected sequence register, Address offset: 0x38 */ + __IO uint32_t JDR1; /*!< ADC injected data register 1, Address offset: 0x3C */ + __IO uint32_t JDR2; /*!< ADC injected data register 2, Address offset: 0x40 */ + __IO uint32_t JDR3; /*!< ADC injected data register 3, Address offset: 0x44 */ + __IO uint32_t JDR4; /*!< ADC injected data register 4, Address offset: 0x48 */ + __IO uint32_t DR; /*!< ADC regular data register, Address offset: 0x4C */ +} ADC_TypeDef; + + +/** + * @brief Controller Area Network TxMailBox + */ +typedef struct +{ + __IO uint32_t TIR; /*!< CAN TX mailbox identifier register */ + __IO uint32_t TDTR; /*!< CAN mailbox data length control and time stamp register */ + __IO uint32_t TDLR; /*!< CAN mailbox data low register */ + __IO uint32_t TDHR; /*!< CAN mailbox data high register */ +} CAN_TxMailBox_TypeDef; + +/** + * @brief Controller Area Network FIFOMailBox + */ +typedef struct +{ + __IO uint32_t RIR; /*!< CAN receive FIFO mailbox identifier register */ + __IO uint32_t RDTR; /*!< CAN receive FIFO mailbox data length control and time stamp register */ + __IO uint32_t RDLR; /*!< CAN receive FIFO mailbox data low register */ + __IO uint32_t RDHR; /*!< CAN receive FIFO mailbox data high register */ +} CAN_FIFOMailBox_TypeDef; + +/** + * @brief Controller Area Network FilterRegister + */ +typedef struct +{ + __IO uint32_t FR1; /*!< CAN Filter bank register 1 */ + __IO uint32_t FR2; /*!< CAN Filter bank register 1 */ +} CAN_FilterRegister_TypeDef; + +/** + * @brief Controller Area Network + */ +typedef struct +{ + __IO uint32_t MCR; /*!< CAN master control register, Address offset: 0x00 */ + __IO uint32_t MSR; /*!< CAN master status register, Address offset: 0x04 */ + __IO uint32_t TSR; /*!< CAN transmit status register, Address offset: 0x08 */ + __IO uint32_t RF0R; /*!< CAN receive FIFO 0 register, Address offset: 0x0C */ + __IO uint32_t RF1R; /*!< CAN receive FIFO 1 register, Address offset: 0x10 */ + __IO uint32_t IER; /*!< CAN interrupt enable register, Address offset: 0x14 */ + __IO uint32_t ESR; /*!< CAN error status register, Address offset: 0x18 */ + __IO uint32_t BTR; /*!< CAN bit timing register, Address offset: 0x1C */ + uint32_t RESERVED0[88]; /*!< Reserved, 0x020 - 0x17F */ + CAN_TxMailBox_TypeDef sTxMailBox[3]; /*!< CAN Tx MailBox, Address offset: 0x180 - 0x1AC */ + CAN_FIFOMailBox_TypeDef sFIFOMailBox[2]; /*!< CAN FIFO MailBox, Address offset: 0x1B0 - 0x1CC */ + uint32_t RESERVED1[12]; /*!< Reserved, 0x1D0 - 0x1FF */ + __IO uint32_t FMR; /*!< CAN filter master register, Address offset: 0x200 */ + __IO uint32_t FM1R; /*!< CAN filter mode register, Address offset: 0x204 */ + uint32_t RESERVED2; /*!< Reserved, 0x208 */ + __IO uint32_t FS1R; /*!< CAN filter scale register, Address offset: 0x20C */ + uint32_t RESERVED3; /*!< Reserved, 0x210 */ + __IO uint32_t FFA1R; /*!< CAN filter FIFO assignment register, Address offset: 0x214 */ + uint32_t RESERVED4; /*!< Reserved, 0x218 */ + __IO uint32_t FA1R; /*!< CAN filter activation register, Address offset: 0x21C */ + uint32_t RESERVED5[8]; /*!< Reserved, 0x220-0x23F */ + CAN_FilterRegister_TypeDef sFilterRegister[28]; /*!< CAN Filter Register, Address offset: 0x240-0x31C */ +} CAN_TypeDef; + +/** + * @brief Consumer Electronics Control + */ + +typedef struct +{ + __IO uint32_t CR; /*!< CEC control register, Address offset:0x00 */ + __IO uint32_t CFGR; /*!< CEC configuration register, Address offset:0x04 */ + __IO uint32_t TXDR; /*!< CEC Tx data register , Address offset:0x08 */ + __IO uint32_t RXDR; /*!< CEC Rx Data Register, Address offset:0x0C */ + __IO uint32_t ISR; /*!< CEC Interrupt and Status Register, Address offset:0x10 */ + __IO uint32_t IER; /*!< CEC interrupt enable register, Address offset:0x14 */ +}CEC_TypeDef; + +/** + * @brief Analog Comparators + */ + +typedef struct +{ + __IO uint32_t CSR; /*!< Comparator control Status register, Address offset: 0x00 */ +} COMP_TypeDef; + +/** + * @brief CRC calculation unit + */ + +typedef struct +{ + __IO uint32_t DR; /*!< CRC Data register, Address offset: 0x00 */ + __IO uint8_t IDR; /*!< CRC Independent data register, Address offset: 0x04 */ + uint8_t RESERVED0; /*!< Reserved, 0x05 */ + uint16_t RESERVED1; /*!< Reserved, 0x06 */ + __IO uint32_t CR; /*!< CRC Control register, Address offset: 0x08 */ + uint32_t RESERVED2; /*!< Reserved, 0x0C */ + __IO uint32_t INIT; /*!< Initial CRC value register, Address offset: 0x10 */ + __IO uint32_t POL; /*!< CRC polynomial register, Address offset: 0x14 */ +} CRC_TypeDef; + +/** + * @brief Digital to Analog Converter + */ + +typedef struct +{ + __IO uint32_t CR; /*!< DAC control register, Address offset: 0x00 */ + __IO uint32_t SWTRIGR; /*!< DAC software trigger register, Address offset: 0x04 */ + __IO uint32_t DHR12R1; /*!< DAC channel1 12-bit right-aligned data holding register, Address offset: 0x08 */ + __IO uint32_t DHR12L1; /*!< DAC channel1 12-bit left aligned data holding register, Address offset: 0x0C */ + __IO uint32_t DHR8R1; /*!< DAC channel1 8-bit right aligned data holding register, Address offset: 0x10 */ + __IO uint32_t DHR12R2; /*!< DAC channel2 12-bit right aligned data holding register, Address offset: 0x14 */ + __IO uint32_t DHR12L2; /*!< DAC channel2 12-bit left aligned data holding register, Address offset: 0x18 */ + __IO uint32_t DHR8R2; /*!< DAC channel2 8-bit right-aligned data holding register, Address offset: 0x1C */ + __IO uint32_t DHR12RD; /*!< Dual DAC 12-bit right-aligned data holding register, Address offset: 0x20 */ + __IO uint32_t DHR12LD; /*!< DUAL DAC 12-bit left aligned data holding register, Address offset: 0x24 */ + __IO uint32_t DHR8RD; /*!< DUAL DAC 8-bit right aligned data holding register, Address offset: 0x28 */ + __IO uint32_t DOR1; /*!< DAC channel1 data output register, Address offset: 0x2C */ + __IO uint32_t DOR2; /*!< DAC channel2 data output register, Address offset: 0x30 */ + __IO uint32_t SR; /*!< DAC status register, Address offset: 0x34 */ +} DAC_TypeDef; + +/** + * @brief Debug MCU + */ + +typedef struct +{ + __IO uint32_t IDCODE; /*!< MCU device ID code, Address offset: 0x00 */ + __IO uint32_t CR; /*!< Debug MCU configuration register, Address offset: 0x04 */ + __IO uint32_t APB1FZ; /*!< Debug MCU APB1 freeze register, Address offset: 0x08 */ + __IO uint32_t APB2FZ; /*!< Debug MCU APB2 freeze register, Address offset: 0x0C */ +}DBGMCU_TypeDef; + +/** + * @brief DMA Controller + */ + +typedef struct +{ + __IO uint32_t CCR; /*!< DMA channel x configuration register */ + __IO uint32_t CNDTR; /*!< DMA channel x number of data register */ + __IO uint32_t CPAR; /*!< DMA channel x peripheral address register */ + __IO uint32_t CMAR; /*!< DMA channel x memory address register */ +} DMA_Channel_TypeDef; + +typedef struct +{ + __IO uint32_t ISR; /*!< DMA interrupt status register, Address offset: 0x00 */ + __IO uint32_t IFCR; /*!< DMA interrupt flag clear register, Address offset: 0x04 */ +} DMA_TypeDef; + +/** + * @brief External Interrupt/Event Controller + */ + +typedef struct +{ + __IO uint32_t IMR; /*!
© COPYRIGHT 2012 STMicroelectronics
+ * + * Licensed under MCD-ST Liberty SW License Agreement V2, (the "License"); + * You may not use this file except in compliance with the License. + * You may obtain a copy of the License at: + * + * http://www.st.com/software_license_agreement_liberty_v2 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, + * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + * + ****************************************************************************** + */ + +/** @addtogroup CMSIS + * @{ + */ + +/** @addtogroup stm32f37x_system + * @{ + */ + +/** + * @brief Define to prevent recursive inclusion + */ +#ifndef __SYSTEM_STM32F37X_H +#define __SYSTEM_STM32F37X_H + +#ifdef __cplusplus + extern "C" { +#endif + +/** @addtogroup STM32F37x_System_Includes + * @{ + */ + +/** + * @} + */ + + +/** @addtogroup STM32F37x_System_Exported_types + * @{ + */ + +extern uint32_t SystemCoreClock; /*!< System Clock Frequency (Core Clock) */ + +/** + * @} + */ + +/** @addtogroup STM32F37x_System_Exported_Constants + * @{ + */ + +/** + * @} + */ + +/** @addtogroup STM32F37x_System_Exported_Macros + * @{ + */ + +/** + * @} + */ + +/** @addtogroup STM32F37x_System_Exported_Functions + * @{ + */ + +extern void SystemInit(void); +extern void SystemCoreClockUpdate(void); +/** + * @} + */ + +#ifdef __cplusplus +} +#endif + +#endif /*__SYSTEM_STM32F37X_H */ + +/** + * @} + */ + +/** + * @} + */ +/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ diff --git a/Libraries/CMSIS/Device/ST/STM32F37x/Release_Notes.html b/Libraries/CMSIS/Device/ST/STM32F37x/Release_Notes.html new file mode 100644 index 0000000..b07de37 --- /dev/null +++ b/Libraries/CMSIS/Device/ST/STM32F37x/Release_Notes.html @@ -0,0 +1,133 @@ + + + + + + + + + +Release Notes for STM32F37x CMSIS + + + + + +
+


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+

Release +Notes for STM32F37x CMSIS

+

Copyright 2012 STMicroelectronics

+

+
+

 

+ + + + + + +
+

Contents

+
    +
  1. STM32F37x CMSIS +update History
    2. +
  2. License
    3. +
+ +

STM32F37x CMSIS +update History

V1.0.0 /20-September-2012

Main +Changes

+
  • First official release for +STM32F37x devices
+ +
    +
+

License

Licensed under MCD-ST Liberty SW License Agreement V2, (the "License"); You may not use this package except in compliance with the License. You may obtain a copy of the License at:


Unless +required by applicable law or agreed to in writing, software +distributed under the License is distributed on an "AS IS" BASIS,
WITHOUT +WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See +the License for the specific language governing permissions and +limitations under the License. + +
+
+ For + complete documentation on STM32 + Microcontrollers visit www.st.com/stm32f3

+
+

+
+
+

 

+
+ \ No newline at end of file diff --git a/Libraries/CMSIS/Device/ST/STM32F37x/Source/Templates/TrueSTUDIO/startup_stm32f37x.s b/Libraries/CMSIS/Device/ST/STM32F37x/Source/Templates/TrueSTUDIO/startup_stm32f37x.s new file mode 100644 index 0000000..30da828 --- /dev/null +++ b/Libraries/CMSIS/Device/ST/STM32F37x/Source/Templates/TrueSTUDIO/startup_stm32f37x.s @@ -0,0 +1,463 @@ +/** + ****************************************************************************** + * @file startup_stm32f37x.s + * @author MCD Application Team + * @version V1.0.0 + * @date 20-September-2012 + * @brief stm32f37x vector table for Atollic TrueSTUDIO toolchain. + * This module performs: + * - Set the initial SP + * - Set the initial PC == Reset_Handler, + * - Set the vector table entries with the exceptions ISR address, + * - Configure the clock system + * - Branches to main in the C library (which eventually + * calls main()). + * After Reset the Cortex-M4 processor is in Thread mode, + * priority is Privileged, and the Stack is set to Main. + ****************************************************************************** + * @attention + * + *

© COPYRIGHT 2012 STMicroelectronics

+ * + * Licensed under MCD-ST Liberty SW License Agreement V2, (the "License"); + * You may not use this file except in compliance with the License. + * You may obtain a copy of the License at: + * + * http://www.st.com/software_license_agreement_liberty_v2 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, + * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + * + ****************************************************************************** + */ + + .syntax unified + .cpu cortex-m4 + .fpu softvfp + .thumb + +.global g_pfnVectors +.global Default_Handler + +/* start address for the initialization values of the .data section. +defined in linker script */ +.word _sidata +/* start address for the .data section. defined in linker script */ +.word _sdata +/* end address for the .data section. defined in linker script */ +.word _edata +/* start address for the .bss section. defined in linker script */ +.word _sbss +/* end address for the .bss section. defined in linker script */ +.word _ebss + +.equ BootRAM, 0xF1E0F85F +/** + * @brief This is the code that gets called when the processor first + * starts execution following a reset event. Only the absolutely + * necessary set is performed, after which the application + * supplied main() routine is called. + * @param None + * @retval : None +*/ + + .section .text.Reset_Handler + .weak Reset_Handler + .type Reset_Handler, %function +Reset_Handler: + +/* Copy the data segment initializers from flash to SRAM */ + movs r1, #0 + b LoopCopyDataInit + +CopyDataInit: + ldr r3, =_sidata + ldr r3, [r3, r1] + str r3, [r0, r1] + adds r1, r1, #4 + +LoopCopyDataInit: + ldr r0, =_sdata + ldr r3, =_edata + adds r2, r0, r1 + cmp r2, r3 + bcc CopyDataInit + ldr r2, =_sbss + b LoopFillZerobss +/* Zero fill the bss segment. */ +FillZerobss: + movs r3, #0 + str r3, [r2], #4 + +LoopFillZerobss: + ldr r3, = _ebss + cmp r2, r3 + bcc FillZerobss + +/* Call the clock system intitialization function.*/ + bl SystemInit +/* Call static constructors */ + bl __libc_init_array +/* Call the application's entry point.*/ + bl main + +LoopForever: + b LoopForever + +.size Reset_Handler, .-Reset_Handler + +/** + * @brief This is the code that gets called when the processor receives an + * unexpected interrupt. This simply enters an infinite loop, preserving + * the system state for examination by a debugger. + * + * @param None + * @retval : None +*/ + .section .text.Default_Handler,"ax",%progbits +Default_Handler: +Infinite_Loop: + b Infinite_Loop + .size Default_Handler, .-Default_Handler +/****************************************************************************** +* +* The minimal vector table for a Cortex-M4. Note that the proper constructs +* must be placed on this to ensure that it ends up at physical address +* 0x0000.0000. +* +******************************************************************************/ + .section .isr_vector,"a",%progbits + .type g_pfnVectors, %object + .size g_pfnVectors, .-g_pfnVectors + + +g_pfnVectors: + .word _estack + .word Reset_Handler + .word NMI_Handler + .word HardFault_Handler + .word MemManage_Handler + .word BusFault_Handler + .word UsageFault_Handler + .word 0 + .word 0 + .word 0 + .word 0 + .word SVC_Handler + .word DebugMon_Handler + .word 0 + .word PendSV_Handler + .word SysTick_Handler + .word WWDG_IRQHandler + .word PVD_IRQHandler + .word TAMPER_STAMP_IRQHandler + .word RTC_WKUP_IRQHandler + .word FLASH_IRQHandler + .word RCC_IRQHandler + .word EXTI0_IRQHandler + .word EXTI1_IRQHandler + .word EXTI2_TS_IRQHandler + .word EXTI3_IRQHandler + .word EXTI4_IRQHandler + .word DMA1_Channel1_IRQHandler + .word DMA1_Channel2_IRQHandler + .word DMA1_Channel3_IRQHandler + .word DMA1_Channel4_IRQHandler + .word DMA1_Channel5_IRQHandler + .word DMA1_Channel6_IRQHandler + .word DMA1_Channel7_IRQHandler + .word ADC1_IRQHandler + .word CAN1_TX_IRQHandler + .word CAN1_RX0_IRQHandler + .word CAN1_RX1_IRQHandler + .word CAN1_SCE_IRQHandler + .word EXTI9_5_IRQHandler + .word TIM15_IRQHandler + .word TIM16_IRQHandler + .word TIM17_IRQHandler + .word TIM18_DAC2_IRQHandler + .word TIM2_IRQHandler + .word TIM3_IRQHandler + .word TIM4_IRQHandler + .word I2C1_EV_IRQHandler + .word I2C1_ER_IRQHandler + .word I2C2_EV_IRQHandler + .word I2C2_ER_IRQHandler + .word SPI1_IRQHandler + .word SPI2_IRQHandler + .word USART1_IRQHandler + .word USART2_IRQHandler + .word USART3_IRQHandler + .word EXTI15_10_IRQHandler + .word RTC_Alarm_IRQHandler + .word CEC_IRQHandler + .word TIM12_IRQHandler + .word TIM13_IRQHandler + .word TIM14_IRQHandler + .word 0 + .word 0 + .word 0 + .word 0 + .word TIM5_IRQHandler + .word SPI3_IRQHandler + .word 0 + .word 0 + .word TIM6_DAC1_IRQHandler + .word TIM7_IRQHandler + .word DMA2_Channel1_IRQHandler + .word DMA2_Channel2_IRQHandler + .word DMA2_Channel3_IRQHandler + .word DMA2_Channel4_IRQHandler + .word DMA2_Channel5_IRQHandler + .word SDADC1_IRQHandler + .word SDADC2_IRQHandler + .word SDADC3_IRQHandler + .word COMP_IRQHandler + .word 0 + .word 0 + .word 0 + .word 0 + .word 0 + .word 0 + .word 0 + .word 0 + .word 0 + .word USB_HP_IRQHandler + .word USB_LP_IRQHandler + .word USBWakeUp_IRQHandler + .word 0 + .word TIM19_IRQHandler + .word 0 + .word 0 + .word FPU_IRQHandler + +/******************************************************************************* +* +* Provide weak aliases for each Exception handler to the Default_Handler. +* As they are weak aliases, any function with the same name will override +* this definition. +* +*******************************************************************************/ + + .weak NMI_Handler + .thumb_set NMI_Handler,Default_Handler + + .weak HardFault_Handler + .thumb_set HardFault_Handler,Default_Handler + + .weak MemManage_Handler + .thumb_set MemManage_Handler,Default_Handler + + .weak BusFault_Handler + .thumb_set BusFault_Handler,Default_Handler + + .weak UsageFault_Handler + .thumb_set UsageFault_Handler,Default_Handler + + .weak SVC_Handler + .thumb_set SVC_Handler,Default_Handler + + .weak DebugMon_Handler + .thumb_set DebugMon_Handler,Default_Handler + + .weak PendSV_Handler + .thumb_set PendSV_Handler,Default_Handler + + .weak SysTick_Handler + .thumb_set SysTick_Handler,Default_Handler + + .weak WWDG_IRQHandler + .thumb_set WWDG_IRQHandler,Default_Handler + + .weak PVD_IRQHandler + .thumb_set PVD_IRQHandler,Default_Handler + + .weak TAMPER_STAMP_IRQHandler + .thumb_set TAMPER_STAMP_IRQHandler,Default_Handler + + .weak RTC_WKUP_IRQHandler + .thumb_set RTC_WKUP_IRQHandler,Default_Handler + + .weak FLASH_IRQHandler + .thumb_set FLASH_IRQHandler,Default_Handler + + .weak RCC_IRQHandler + .thumb_set RCC_IRQHandler,Default_Handler + + .weak EXTI0_IRQHandler + .thumb_set EXTI0_IRQHandler,Default_Handler + + .weak EXTI1_IRQHandler + .thumb_set EXTI1_IRQHandler,Default_Handler + + .weak EXTI2_TS_IRQHandler + .thumb_set EXTI2_TS_IRQHandler,Default_Handler + + .weak EXTI3_IRQHandler + .thumb_set EXTI3_IRQHandler,Default_Handler + + .weak EXTI4_IRQHandler + .thumb_set EXTI4_IRQHandler,Default_Handler + + .weak DMA1_Channel1_IRQHandler + .thumb_set DMA1_Channel1_IRQHandler,Default_Handler + + .weak DMA1_Channel2_IRQHandler + .thumb_set DMA1_Channel2_IRQHandler,Default_Handler + + .weak DMA1_Channel3_IRQHandler + .thumb_set DMA1_Channel3_IRQHandler,Default_Handler + + .weak DMA1_Channel4_IRQHandler + .thumb_set DMA1_Channel4_IRQHandler,Default_Handler + + .weak DMA1_Channel5_IRQHandler + .thumb_set DMA1_Channel5_IRQHandler,Default_Handler + + .weak DMA1_Channel6_IRQHandler + .thumb_set DMA1_Channel6_IRQHandler,Default_Handler + + .weak DMA1_Channel7_IRQHandler + .thumb_set DMA1_Channel7_IRQHandler,Default_Handler + + .weak ADC1_IRQHandler + .thumb_set ADC1_IRQHandler,Default_Handler + + .weak CAN1_TX_IRQHandler + .thumb_set CAN1_TX_IRQHandler,Default_Handler + + .weak CAN1_RX0_IRQHandler + .thumb_set CAN1_RX0_IRQHandler,Default_Handler + + .weak CAN1_RX1_IRQHandler + .thumb_set CAN1_RX1_IRQHandler,Default_Handler + + .weak CAN1_SCE_IRQHandler + .thumb_set CAN1_SCE_IRQHandler,Default_Handler + + .weak EXTI9_5_IRQHandler + .thumb_set EXTI9_5_IRQHandler,Default_Handler + + .weak TIM15_IRQHandler + .thumb_set TIM15_IRQHandler,Default_Handler + + .weak TIM16_IRQHandler + .thumb_set TIM16_IRQHandler,Default_Handler + + .weak TIM17_IRQHandler + .thumb_set TIM17_IRQHandler,Default_Handler + + .weak TIM18_DAC2_IRQHandler + .thumb_set TIM18_DAC2_IRQHandler,Default_Handler + + .weak TIM2_IRQHandler + .thumb_set TIM2_IRQHandler,Default_Handler + + .weak TIM3_IRQHandler + .thumb_set TIM3_IRQHandler,Default_Handler + + .weak TIM4_IRQHandler + .thumb_set TIM4_IRQHandler,Default_Handler + + .weak I2C1_EV_IRQHandler + .thumb_set I2C1_EV_IRQHandler,Default_Handler + + .weak I2C1_ER_IRQHandler + .thumb_set I2C1_ER_IRQHandler,Default_Handler + + .weak I2C2_EV_IRQHandler + .thumb_set I2C2_EV_IRQHandler,Default_Handler + + .weak I2C2_ER_IRQHandler + .thumb_set I2C2_ER_IRQHandler,Default_Handler + + .weak SPI1_IRQHandler + .thumb_set SPI1_IRQHandler,Default_Handler + + .weak SPI2_IRQHandler + .thumb_set SPI2_IRQHandler,Default_Handler + + .weak USART1_IRQHandler + .thumb_set USART1_IRQHandler,Default_Handler + + .weak USART2_IRQHandler + .thumb_set USART2_IRQHandler,Default_Handler + + .weak USART3_IRQHandler + .thumb_set USART3_IRQHandler,Default_Handler + + .weak EXTI15_10_IRQHandler + .thumb_set EXTI15_10_IRQHandler,Default_Handler + + .weak RTC_Alarm_IRQHandler + .thumb_set RTC_Alarm_IRQHandler,Default_Handler + + .weak CEC_IRQHandler + .thumb_set CEC_IRQHandler,Default_Handler + + .weak TIM12_IRQHandler + .thumb_set TIM12_IRQHandler,Default_Handler + + .weak TIM13_IRQHandler + .thumb_set TIM13_IRQHandler,Default_Handler + + .weak TIM14_IRQHandler + .thumb_set TIM14_IRQHandler,Default_Handler + + .weak TIM5_IRQHandler + .thumb_set TIM5_IRQHandler,Default_Handler + + .weak SPI3_IRQHandler + .thumb_set SPI3_IRQHandler,Default_Handler + + .weak TIM6_DAC1_IRQHandler + .thumb_set TIM6_DAC1_IRQHandler,Default_Handler + + .weak TIM7_IRQHandler + .thumb_set TIM7_IRQHandler,Default_Handler + + .weak DMA2_Channel1_IRQHandler + .thumb_set DMA2_Channel1_IRQHandler,Default_Handler + + .weak DMA2_Channel2_IRQHandler + .thumb_set DMA2_Channel2_IRQHandler,Default_Handler + + .weak DMA2_Channel3_IRQHandler + .thumb_set DMA2_Channel3_IRQHandler,Default_Handler + + .weak DMA2_Channel4_IRQHandler + .thumb_set DMA2_Channel4_IRQHandler,Default_Handler + + .weak DMA2_Channel5_IRQHandler + .thumb_set DMA2_Channel5_IRQHandler,Default_Handler + + .weak SDADC1_IRQHandler + .thumb_set SDADC1_IRQHandler,Default_Handler + + .weak SDADC2_IRQHandler + .thumb_set SDADC2_IRQHandler,Default_Handler + + .weak SDADC3_IRQHandler + .thumb_set SDADC3_IRQHandler,Default_Handler + + .weak COMP_IRQHandler + .thumb_set COMP_IRQHandler,Default_Handler + + .weak USB_HP_IRQHandler + .thumb_set USB_HP_IRQHandler,Default_Handler + + .weak USB_LP_IRQHandler + .thumb_set USB_LP_IRQHandler,Default_Handler + + .weak USBWakeUp_IRQHandler + .thumb_set USBWakeUp_IRQHandler,Default_Handler + + .weak TIM19_IRQHandler + .thumb_set TIM19_IRQHandler,Default_Handler + + .weak FPU_IRQHandler + .thumb_set FPU_IRQHandler,Default_Handler +/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ diff --git a/Libraries/CMSIS/Device/ST/STM32F37x/Source/Templates/arm/startup_stm32f37x.s b/Libraries/CMSIS/Device/ST/STM32F37x/Source/Templates/arm/startup_stm32f37x.s new file mode 100644 index 0000000..6ca14f8 --- /dev/null +++ b/Libraries/CMSIS/Device/ST/STM32F37x/Source/Templates/arm/startup_stm32f37x.s @@ -0,0 +1,396 @@ +;******************** (C) COPYRIGHT 2012 STMicroelectronics ******************** +;* File Name : startup_stm32f37x.s +;* Author : MCD Application Team +;* Version : V1.0.0 +;* Date : 20-September-2012 +;* Description : STM32F37x devices vector table for MDK-ARM toolchain. +;* This module performs: +;* - Set the initial SP +;* - Set the initial PC == Reset_Handler +;* - Set the vector table entries with the exceptions ISR address +;* - Branches to __main in the C library (which eventually +;* calls main()). +;* After Reset the CortexM4 processor is in Thread mode, +;* priority is Privileged, and the Stack is set to Main. +;* <<< Use Configuration Wizard in Context Menu >>> +;******************************************************************************* +; @attention +; +; Licensed under MCD-ST Liberty SW License Agreement V2, (the "License"); +; You may not use this file except in compliance with the License. +; You may obtain a copy of the License at: +; +; http://www.st.com/software_license_agreement_liberty_v2 +; +; Unless required by applicable law or agreed to in writing, software +; distributed under the License is distributed on an "AS IS" BASIS, +; WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +; See the License for the specific language governing permissions and +; limitations under the License. +; +;******************************************************************************* +; +; Amount of memory (in bytes) allocated for Stack +; Tailor this value to your application needs +; Stack Configuration +; Stack Size (in Bytes) <0x0-0xFFFFFFFF:8> +; + +Stack_Size EQU 0x00000400 + + AREA STACK, NOINIT, READWRITE, ALIGN=3 +Stack_Mem SPACE Stack_Size +__initial_sp + + +; Heap Configuration +; Heap Size (in Bytes) <0x0-0xFFFFFFFF:8> +; + +Heap_Size EQU 0x00000200 + + AREA HEAP, NOINIT, READWRITE, ALIGN=3 +__heap_base +Heap_Mem SPACE Heap_Size +__heap_limit + + PRESERVE8 + THUMB + + +; Vector Table Mapped to Address 0 at Reset + AREA RESET, DATA, READONLY + EXPORT __Vectors + EXPORT __Vectors_End + EXPORT __Vectors_Size + +__Vectors DCD __initial_sp ; Top of Stack + DCD Reset_Handler ; Reset Handler + DCD NMI_Handler ; NMI Handler + DCD HardFault_Handler ; Hard Fault Handler + DCD MemManage_Handler ; MPU Fault Handler + DCD BusFault_Handler ; Bus Fault Handler + DCD UsageFault_Handler ; Usage Fault Handler + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD SVC_Handler ; SVCall Handler + DCD DebugMon_Handler ; Debug Monitor Handler + DCD 0 ; Reserved + DCD PendSV_Handler ; PendSV Handler + DCD SysTick_Handler ; SysTick Handler + + ; External Interrupts + DCD WWDG_IRQHandler ; Window WatchDog + DCD PVD_IRQHandler ; PVD through EXTI Line detection + DCD TAMPER_STAMP_IRQHandler ; Tamper and TimeStamps through the EXTI line + DCD RTC_WKUP_IRQHandler ; RTC Wakeup through the EXTI line + DCD FLASH_IRQHandler ; FLASH + DCD RCC_IRQHandler ; RCC + DCD EXTI0_IRQHandler ; EXTI Line0 + DCD EXTI1_IRQHandler ; EXTI Line1 + DCD EXTI2_TS_IRQHandler ; EXTI Line2 and Touch Sense + DCD EXTI3_IRQHandler ; EXTI Line3 + DCD EXTI4_IRQHandler ; EXTI Line4 + DCD DMA1_Channel1_IRQHandler ; DMA1 Channel 1 + DCD DMA1_Channel2_IRQHandler ; DMA1 Channel 2 + DCD DMA1_Channel3_IRQHandler ; DMA1 Channel 3 + DCD DMA1_Channel4_IRQHandler ; DMA1 Channel 4 + DCD DMA1_Channel5_IRQHandler ; DMA1 Channel 5 + DCD DMA1_Channel6_IRQHandler ; DMA1 Channel 6 + DCD DMA1_Channel7_IRQHandler ; DMA1 Channel 7 + DCD ADC1_IRQHandler ; ADC1 + DCD CAN1_TX_IRQHandler ; CAN1 TX + DCD CAN1_RX0_IRQHandler ; CAN1 RX0 + DCD CAN1_RX1_IRQHandler ; CAN1 RX1 + DCD CAN1_SCE_IRQHandler ; CAN1 SCE + DCD EXTI9_5_IRQHandler ; External Line[9:5]s + DCD TIM15_IRQHandler ; TIM15 + DCD TIM16_IRQHandler ; TIM16 + DCD TIM17_IRQHandler ; TIM17 + DCD TIM18_DAC2_IRQHandler ; TIM18 and DAC2 + DCD TIM2_IRQHandler ; TIM2 + DCD TIM3_IRQHandler ; TIM3 + DCD TIM4_IRQHandler ; TIM4 + DCD I2C1_EV_IRQHandler ; I2C1 Event + DCD I2C1_ER_IRQHandler ; I2C1 Error + DCD I2C2_EV_IRQHandler ; I2C2 Event + DCD I2C2_ER_IRQHandler ; I2C2 Error + DCD SPI1_IRQHandler ; SPI1 + DCD SPI2_IRQHandler ; SPI2 + DCD USART1_IRQHandler ; USART1 + DCD USART2_IRQHandler ; USART2 + DCD USART3_IRQHandler ; USART3 + DCD EXTI15_10_IRQHandler ; External Line[15:10]s + DCD RTC_Alarm_IRQHandler ; RTC Alarm (A and B) through EXTI Line + DCD CEC_IRQHandler ; CEC + DCD TIM12_IRQHandler ; TIM12 + DCD TIM13_IRQHandler ; TIM13 + DCD TIM14_IRQHandler ; TIM14 + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD TIM5_IRQHandler ; TIM5 + DCD SPI3_IRQHandler ; SPI3 + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD TIM6_DAC1_IRQHandler ; TIM6 and DAC1 Channel1 & channel2 + DCD TIM7_IRQHandler ; TIM7 + DCD DMA2_Channel1_IRQHandler ; DMA2 Channel 1 + DCD DMA2_Channel2_IRQHandler ; DMA2 Channel 2 + DCD DMA2_Channel3_IRQHandler ; DMA2 Channel 3 + DCD DMA2_Channel4_IRQHandler ; DMA2 Channel 4 + DCD DMA2_Channel5_IRQHandler ; DMA2 Channel 5 + DCD SDADC1_IRQHandler ; SDADC1 + DCD SDADC2_IRQHandler ; SDADC2 + DCD SDADC3_IRQHandler ; SDADC3 + DCD COMP_IRQHandler ; COMP + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD USB_HP_IRQHandler ; USB High Priority + DCD USB_LP_IRQHandler ; USB Low Priority + DCD USBWakeUp_IRQHandler ; USB Wakeup + DCD 0 ; Reserved + DCD TIM19_IRQHandler ; TIM19 + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD FPU_IRQHandler ; FPU +__Vectors_End + +__Vectors_Size EQU __Vectors_End - __Vectors + + AREA |.text|, CODE, READONLY + +; Reset handler +Reset_Handler PROC + EXPORT Reset_Handler [WEAK] + IMPORT SystemInit + IMPORT __main + + LDR R0, =SystemInit + BLX R0 + LDR R0, =__main + BX R0 + ENDP + +; Dummy Exception Handlers (infinite loops which can be modified) + +NMI_Handler PROC + EXPORT NMI_Handler [WEAK] + B . + ENDP +HardFault_Handler\ + PROC + EXPORT HardFault_Handler [WEAK] + B . + ENDP +MemManage_Handler\ + PROC + EXPORT MemManage_Handler [WEAK] + B . + ENDP +BusFault_Handler\ + PROC + EXPORT BusFault_Handler [WEAK] + B . + ENDP +UsageFault_Handler\ + PROC + EXPORT UsageFault_Handler [WEAK] + B . + ENDP +SVC_Handler PROC + EXPORT SVC_Handler [WEAK] + B . + ENDP +DebugMon_Handler\ + PROC + EXPORT DebugMon_Handler [WEAK] + B . + ENDP +PendSV_Handler PROC + EXPORT PendSV_Handler [WEAK] + B . + ENDP +SysTick_Handler PROC + EXPORT SysTick_Handler [WEAK] + B . + ENDP + +Default_Handler PROC + + EXPORT WWDG_IRQHandler [WEAK] + EXPORT PVD_IRQHandler [WEAK] + EXPORT TAMPER_STAMP_IRQHandler [WEAK] + EXPORT RTC_WKUP_IRQHandler [WEAK] + EXPORT FLASH_IRQHandler [WEAK] + EXPORT RCC_IRQHandler [WEAK] + EXPORT EXTI0_IRQHandler [WEAK] + EXPORT EXTI1_IRQHandler [WEAK] + EXPORT EXTI2_TS_IRQHandler [WEAK] + EXPORT EXTI3_IRQHandler [WEAK] + EXPORT EXTI4_IRQHandler [WEAK] + EXPORT DMA1_Channel1_IRQHandler [WEAK] + EXPORT DMA1_Channel2_IRQHandler [WEAK] + EXPORT DMA1_Channel3_IRQHandler [WEAK] + EXPORT DMA1_Channel4_IRQHandler [WEAK] + EXPORT DMA1_Channel5_IRQHandler [WEAK] + EXPORT DMA1_Channel6_IRQHandler [WEAK] + EXPORT DMA1_Channel7_IRQHandler [WEAK] + EXPORT ADC1_IRQHandler [WEAK] + EXPORT CAN1_TX_IRQHandler [WEAK] + EXPORT CAN1_RX0_IRQHandler [WEAK] + EXPORT CAN1_RX1_IRQHandler [WEAK] + EXPORT CAN1_SCE_IRQHandler [WEAK] + EXPORT EXTI9_5_IRQHandler [WEAK] + EXPORT TIM15_IRQHandler [WEAK] + EXPORT TIM16_IRQHandler [WEAK] + EXPORT TIM17_IRQHandler [WEAK] + EXPORT TIM18_DAC2_IRQHandler [WEAK] + EXPORT TIM2_IRQHandler [WEAK] + EXPORT TIM3_IRQHandler [WEAK] + EXPORT TIM4_IRQHandler [WEAK] + EXPORT I2C1_EV_IRQHandler [WEAK] + EXPORT I2C1_ER_IRQHandler [WEAK] + EXPORT I2C2_EV_IRQHandler [WEAK] + EXPORT I2C2_ER_IRQHandler [WEAK] + EXPORT SPI1_IRQHandler [WEAK] + EXPORT SPI2_IRQHandler [WEAK] + EXPORT USART1_IRQHandler [WEAK] + EXPORT USART2_IRQHandler [WEAK] + EXPORT USART3_IRQHandler [WEAK] + EXPORT EXTI15_10_IRQHandler [WEAK] + EXPORT RTC_Alarm_IRQHandler [WEAK] + EXPORT CEC_IRQHandler [WEAK] + EXPORT TIM12_IRQHandler [WEAK] + EXPORT TIM13_IRQHandler [WEAK] + EXPORT TIM14_IRQHandler [WEAK] + EXPORT TIM5_IRQHandler [WEAK] + EXPORT SPI3_IRQHandler [WEAK] + EXPORT TIM6_DAC1_IRQHandler [WEAK] + EXPORT TIM7_IRQHandler [WEAK] + EXPORT DMA2_Channel1_IRQHandler [WEAK] + EXPORT DMA2_Channel2_IRQHandler [WEAK] + EXPORT DMA2_Channel3_IRQHandler [WEAK] + EXPORT DMA2_Channel4_IRQHandler [WEAK] + EXPORT DMA2_Channel5_IRQHandler [WEAK] + EXPORT SDADC1_IRQHandler [WEAK] + EXPORT SDADC2_IRQHandler [WEAK] + EXPORT SDADC3_IRQHandler [WEAK] + EXPORT COMP_IRQHandler [WEAK] + EXPORT USB_HP_IRQHandler [WEAK] + EXPORT USB_LP_IRQHandler [WEAK] + EXPORT USBWakeUp_IRQHandler [WEAK] + EXPORT TIM19_IRQHandler [WEAK] + EXPORT FPU_IRQHandler [WEAK] + + +WWDG_IRQHandler +PVD_IRQHandler +TAMPER_STAMP_IRQHandler +RTC_WKUP_IRQHandler +FLASH_IRQHandler +RCC_IRQHandler +EXTI0_IRQHandler +EXTI1_IRQHandler +EXTI2_TS_IRQHandler +EXTI3_IRQHandler +EXTI4_IRQHandler +DMA1_Channel1_IRQHandler +DMA1_Channel2_IRQHandler +DMA1_Channel3_IRQHandler +DMA1_Channel4_IRQHandler +DMA1_Channel5_IRQHandler +DMA1_Channel6_IRQHandler +DMA1_Channel7_IRQHandler +ADC1_IRQHandler +CAN1_TX_IRQHandler +CAN1_RX0_IRQHandler +CAN1_RX1_IRQHandler +CAN1_SCE_IRQHandler +EXTI9_5_IRQHandler +TIM15_IRQHandler +TIM16_IRQHandler +TIM17_IRQHandler +TIM18_DAC2_IRQHandler +TIM2_IRQHandler +TIM3_IRQHandler +TIM4_IRQHandler +I2C1_EV_IRQHandler +I2C1_ER_IRQHandler +I2C2_EV_IRQHandler +I2C2_ER_IRQHandler +SPI1_IRQHandler +SPI2_IRQHandler +USART1_IRQHandler +USART2_IRQHandler +USART3_IRQHandler +EXTI15_10_IRQHandler +RTC_Alarm_IRQHandler +CEC_IRQHandler +TIM12_IRQHandler +TIM13_IRQHandler +TIM14_IRQHandler +TIM5_IRQHandler +SPI3_IRQHandler +TIM6_DAC1_IRQHandler +TIM7_IRQHandler +DMA2_Channel1_IRQHandler +DMA2_Channel2_IRQHandler +DMA2_Channel3_IRQHandler +DMA2_Channel4_IRQHandler +DMA2_Channel5_IRQHandler +SDADC1_IRQHandler +SDADC2_IRQHandler +SDADC3_IRQHandler +COMP_IRQHandler +USB_HP_IRQHandler +USB_LP_IRQHandler +USBWakeUp_IRQHandler +TIM19_IRQHandler +FPU_IRQHandler + + B . + + ENDP + + ALIGN + +;******************************************************************************* +; User Stack and Heap initialization +;******************************************************************************* + IF :DEF:__MICROLIB + + EXPORT __initial_sp + EXPORT __heap_base + EXPORT __heap_limit + + ELSE + + IMPORT __use_two_region_memory + EXPORT __user_initial_stackheap + +__user_initial_stackheap + + LDR R0, = Heap_Mem + LDR R1, =(Stack_Mem + Stack_Size) + LDR R2, = (Heap_Mem + Heap_Size) + LDR R3, = Stack_Mem + BX LR + + ALIGN + + ENDIF + + END + +;************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE***** diff --git a/Libraries/CMSIS/Device/ST/STM32F37x/Source/Templates/gcc_ride7/startup_stm32f37x.s b/Libraries/CMSIS/Device/ST/STM32F37x/Source/Templates/gcc_ride7/startup_stm32f37x.s new file mode 100644 index 0000000..f3951af --- /dev/null +++ b/Libraries/CMSIS/Device/ST/STM32F37x/Source/Templates/gcc_ride7/startup_stm32f37x.s @@ -0,0 +1,460 @@ +/** + ****************************************************************************** + * @file startup_stm32f37x.s + * @author MCD Application Team + * @version V1.0.0 + * @date 20-September-2012 + * @brief STM32F37x Devices vector table for RIDE7 toolchain. + * This module performs: + * - Set the initial SP + * - Set the initial PC == Reset_Handler, + * - Set the vector table entries with the exceptions ISR address + * - Configure the clock system + * - Branches to main in the C library (which eventually + * calls main()). + * After Reset the Cortex-M4 processor is in Thread mode, + * priority is Privileged, and the Stack is set to Main. + ****************************************************************************** + * @attention + * + *

© COPYRIGHT 2012 STMicroelectronics

+ * + * Licensed under MCD-ST Liberty SW License Agreement V2, (the "License"); + * You may not use this file except in compliance with the License. + * You may obtain a copy of the License at: + * + * http://www.st.com/software_license_agreement_liberty_v2 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, + * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + * + ****************************************************************************** + */ + + .syntax unified + .cpu cortex-m4 + .fpu softvfp + .thumb + +.global g_pfnVectors +.global Default_Handler + +/* start address for the initialization values of the .data section. +defined in linker script */ +.word _sidata +/* start address for the .data section. defined in linker script */ +.word _sdata +/* end address for the .data section. defined in linker script */ +.word _edata +/* start address for the .bss section. defined in linker script */ +.word _sbss +/* end address for the .bss section. defined in linker script */ +.word _ebss +/* stack used for SystemInit_ExtMemCtl; always internal RAM used */ + +/** + * @brief This is the code that gets called when the processor first + * starts execution following a reset event. Only the absolutely + * necessary set is performed, after which the application + * supplied main() routine is called. + * @param None + * @retval : None +*/ + + .section .text.Reset_Handler + .weak Reset_Handler + .type Reset_Handler, %function +Reset_Handler: + +/* Copy the data segment initializers from flash to SRAM */ + movs r1, #0 + b LoopCopyDataInit + +CopyDataInit: + ldr r3, =_sidata + ldr r3, [r3, r1] + str r3, [r0, r1] + adds r1, r1, #4 + +LoopCopyDataInit: + ldr r0, =_sdata + ldr r3, =_edata + adds r2, r0, r1 + cmp r2, r3 + bcc CopyDataInit + ldr r2, =_sbss + b LoopFillZerobss +/* Zero fill the bss segment. */ +FillZerobss: + movs r3, #0 + str r3, [r2], #4 + +LoopFillZerobss: + ldr r3, = _ebss + cmp r2, r3 + bcc FillZerobss + +/* Call the clock system intitialization function.*/ + bl SystemInit +/* Call the application's entry point.*/ + bl main + bx lr +.size Reset_Handler, .-Reset_Handler + +/** + * @brief This is the code that gets called when the processor receives an + * unexpected interrupt. This simply enters an infinite loop, preserving + * the system state for examination by a debugger. + * @param None + * @retval None +*/ + .section .text.Default_Handler,"ax",%progbits +Default_Handler: +Infinite_Loop: + b Infinite_Loop + .size Default_Handler, .-Default_Handler +/****************************************************************************** +* +* The minimal vector table for a Cortex-M4. Note that the proper constructs +* must be placed on this to ensure that it ends up at physical address +* 0x0000.0000. +* +*******************************************************************************/ + .section .isr_vector,"a",%progbits + .type g_pfnVectors, %object + .size g_pfnVectors, .-g_pfnVectors + + +g_pfnVectors: + .word _estack + .word Reset_Handler + .word NMI_Handler + .word HardFault_Handler + .word MemManage_Handler + .word BusFault_Handler + .word UsageFault_Handler + .word 0 + .word 0 + .word 0 + .word 0 + .word SVC_Handler + .word DebugMon_Handler + .word 0 + .word PendSV_Handler + .word SysTick_Handler + + /* External Interrupts */ + .word WWDG_IRQHandler /* Window WatchDog */ + .word PVD_IRQHandler /* PVD through EXTI Line detection */ + .word TAMPER_STAMP_IRQHandler /* Tamper and TimeStamps through the EXTI line */ + .word RTC_WKUP_IRQHandler /* RTC Wakeup through the EXTI line */ + .word FLASH_IRQHandler /* FLASH */ + .word RCC_IRQHandler /* RCC */ + .word EXTI0_IRQHandler /* EXTI Line0 */ + .word EXTI1_IRQHandler /* EXTI Line1 */ + .word EXTI2_TS_IRQHandler /* EXTI Line2 */ + .word EXTI3_IRQHandler /* EXTI Line3 */ + .word EXTI4_IRQHandler /* EXTI Line4 */ + .word DMA1_Channel1_IRQHandler /* DMA1 Channel 1 */ + .word DMA1_Channel2_IRQHandler /* DMA1 Channel 2 */ + .word DMA1_Channel3_IRQHandler /* DMA1 Channel 3 */ + .word DMA1_Channel4_IRQHandler /* DMA1 Channel 4 */ + .word DMA1_Channel5_IRQHandler /* DMA1 Channel 5 */ + .word DMA1_Channel6_IRQHandler /* DMA1 Channel 6 */ + .word DMA1_Channel7_IRQHandler /* DMA1 Channel 7 */ + .word ADC1_IRQHandler /* ADC1 */ + .word CAN1_TX_IRQHandler /* CAN1 TX */ + .word CAN1_RX0_IRQHandler /* CAN1 RX0 */ + .word CAN1_RX1_IRQHandler /* CAN1 RX1 */ + .word CAN1_SCE_IRQHandler /* CAN1 SCE */ + .word EXTI9_5_IRQHandler /* External Line[9:5]s */ + .word TIM15_IRQHandler /* TIM15 */ + .word TIM16_IRQHandler /* TIM16 */ + .word TIM17_IRQHandler /* TIM17 */ + .word TIM18_DAC2_IRQHandler /* TIM18 and DAC2 */ + .word TIM2_IRQHandler /* TIM2 */ + .word TIM3_IRQHandler /* TIM3 */ + .word TIM4_IRQHandler /* TIM4 */ + .word I2C1_EV_IRQHandler /* I2C1 Event */ + .word I2C1_ER_IRQHandler /* I2C1 Error */ + .word I2C2_EV_IRQHandler /* I2C2 Event */ + .word I2C2_ER_IRQHandler /* I2C2 Error */ + .word SPI1_IRQHandler /* SPI1 */ + .word SPI2_IRQHandler /* SPI2 */ + .word USART1_IRQHandler /* USART1 */ + .word USART2_IRQHandler /* USART2 */ + .word USART3_IRQHandler /* USART3 */ + .word EXTI15_10_IRQHandler /* External Line[15:10]s */ + .word RTC_Alarm_IRQHandler /* RTC_Alarm_IRQHandler */ + .word CEC_IRQHandler /* CEC */ + .word TIM12_IRQHandler /* TIM12 */ + .word TIM13_IRQHandler /* TIM13 */ + .word TIM14_IRQHandler /* TIM14 */ + .word 0 /* Reserved */ + .word 0 /* Reserved */ + .word 0 /* Reserved */ + .word 0 /* Reserved */ + .word TIM5_IRQHandler /* TIM5 */ + .word SPI3_IRQHandler /* SPI3 */ + .word 0 /* Reserved */ + .word 0 /* Reserved */ + .word TIM6_DAC1_IRQHandler /* TIM6 and DAC1 Channel1 & channel2 */ + .word TIM7_IRQHandler /* TIM7 */ + .word DMA2_Channel1_IRQHandler /* DMA2 Channel 1 */ + .word DMA2_Channel2_IRQHandler /* DMA2 Channel 2 */ + .word DMA2_Channel3_IRQHandler /* DMA2 Channel 3 */ + .word DMA2_Channel4_IRQHandler /* DMA2 Channel 4 */ + .word DMA2_Channel5_IRQHandler /* DMA2 Channel 5 */ + .word SDADC1_IRQHandler /* SDADC1 */ + .word SDADC2_IRQHandler /* SDADC2 */ + .word SDADC3_IRQHandler /* SDADC3 */ + .word COMP_IRQHandler /* COMP */ + .word 0 /* Reserved */ + .word 0 /* Reserved */ + .word 0 /* Reserved */ + .word 0 /* Reserved */ + .word 0 /* Reserved */ + .word 0 /* Reserved */ + .word 0 /* Reserved */ + .word 0 /* Reserved */ + .word 0 /* Reserved */ + .word USB_HP_IRQHandler /* USB High Priority */ + .word USB_LP_IRQHandler /* USB Low Priority */ + .word USBWakeUp_IRQHandler /* USB Wakeup */ + .word 0 /* Resrved */ + .word TIM19_IRQHandler /*TIM19 */ + .word 0 /* Resrved */ + .word FPU_IRQHandler /* FPU */ + + +/******************************************************************************* +* +* Provide weak aliases for each Exception handler to the Default_Handler. +* As they are weak aliases, any function with the same name will override +* this definition. +* +*******************************************************************************/ + .weak NMI_Handler + .thumb_set NMI_Handler,Default_Handler + + .weak HardFault_Handler + .thumb_set HardFault_Handler,Default_Handler + + .weak MemManage_Handler + .thumb_set MemManage_Handler,Default_Handler + + .weak BusFault_Handler + .thumb_set BusFault_Handler,Default_Handler + + .weak UsageFault_Handler + .thumb_set UsageFault_Handler,Default_Handler + + .weak SVC_Handler + .thumb_set SVC_Handler,Default_Handler + + .weak DebugMon_Handler + .thumb_set DebugMon_Handler,Default_Handler + + .weak PendSV_Handler + .thumb_set PendSV_Handler,Default_Handler + + .weak SysTick_Handler + .thumb_set SysTick_Handler,Default_Handler + + .weak WWDG_IRQHandler + .thumb_set WWDG_IRQHandler,Default_Handler + + .weak PVD_IRQHandler + .thumb_set PVD_IRQHandler,Default_Handler + + .weak TAMPER_STAMP_IRQHandler + .thumb_set TAMPER_STAMP_IRQHandler,Default_Handler + + .weak RTC_WKUP_IRQHandler + .thumb_set RTC_WKUP_IRQHandler,Default_Handler + + .weak FLASH_IRQHandler + .thumb_set FLASH_IRQHandler,Default_Handler + + .weak RCC_IRQHandler + .thumb_set RCC_IRQHandler,Default_Handler + + .weak EXTI0_IRQHandler + .thumb_set EXTI0_IRQHandler,Default_Handler + + .weak EXTI1_IRQHandler + .thumb_set EXTI1_IRQHandler,Default_Handler + + .weak EXTI2_TS_IRQHandler + .thumb_set EXTI2_TS_IRQHandler,Default_Handler + + .weak EXTI3_IRQHandler + .thumb_set EXTI3_IRQHandler,Default_Handler + + .weak EXTI4_IRQHandler + .thumb_set EXTI4_IRQHandler,Default_Handler + + .weak DMA1_Channel1_IRQHandler + .thumb_set DMA1_Channel1_IRQHandler,Default_Handler + + .weak DMA1_Channel2_IRQHandler + .thumb_set DMA1_Channel2_IRQHandler,Default_Handler + + .weak DMA1_Channel3_IRQHandler + .thumb_set DMA1_Channel3_IRQHandler,Default_Handler + + .weak DMA1_Channel4_IRQHandler + .thumb_set DMA1_Channel4_IRQHandler,Default_Handler + + .weak DMA1_Channel5_IRQHandler + .thumb_set DMA1_Channel5_IRQHandler,Default_Handler + + .weak DMA1_Channel6_IRQHandler + .thumb_set DMA1_Channel6_IRQHandler,Default_Handler + + .weak DMA1_Channel7_IRQHandler + .thumb_set DMA1_Channel7_IRQHandler,Default_Handler + + .weak ADC1_IRQHandler + .thumb_set ADC1_IRQHandler,Default_Handler + + .weak CAN1_TX_IRQHandler + .thumb_set CAN1_TX_IRQHandler,Default_Handler + + .weak CAN1_RX0_IRQHandler + .thumb_set CAN1_RX0_IRQHandler,Default_Handler + + .weak CAN1_RX1_IRQHandler + .thumb_set CAN1_RX1_IRQHandler,Default_Handler + + .weak CAN1_SCE_IRQHandler + .thumb_set CAN1_SCE_IRQHandler,Default_Handler + + .weak EXTI9_5_IRQHandler + .thumb_set EXTI9_5_IRQHandler,Default_Handler + + .weak TIM15_IRQHandler + .thumb_set TIM15_IRQHandler,Default_Handler + + .weak TIM16_IRQHandler + .thumb_set TIM16_IRQHandler,Default_Handler + + .weak TIM17_IRQHandler + .thumb_set TIM17_IRQHandler,Default_Handler + + .weak TIM18_DAC2_IRQHandler + .thumb_set TIM18_DAC2_IRQHandler,Default_Handler + + .weak TIM2_IRQHandler + .thumb_set TIM2_IRQHandler,Default_Handler + + .weak TIM3_IRQHandler + .thumb_set TIM3_IRQHandler,Default_Handler + + .weak TIM4_IRQHandler + .thumb_set TIM4_IRQHandler,Default_Handler + + .weak I2C1_EV_IRQHandler + .thumb_set I2C1_EV_IRQHandler,Default_Handler + + .weak I2C1_ER_IRQHandler + .thumb_set I2C1_ER_IRQHandler,Default_Handler + + .weak I2C2_EV_IRQHandler + .thumb_set I2C2_EV_IRQHandler,Default_Handler + + .weak I2C2_ER_IRQHandler + .thumb_set I2C2_ER_IRQHandler,Default_Handler + + .weak SPI1_IRQHandler + .thumb_set SPI1_IRQHandler,Default_Handler + + .weak SPI2_IRQHandler + .thumb_set SPI2_IRQHandler,Default_Handler + + .weak USART1_IRQHandler + .thumb_set USART1_IRQHandler,Default_Handler + + .weak USART2_IRQHandler + .thumb_set USART2_IRQHandler,Default_Handler + + .weak USART3_IRQHandler + .thumb_set USART3_IRQHandler,Default_Handler + + .weak EXTI15_10_IRQHandler + .thumb_set EXTI15_10_IRQHandler,Default_Handler + + .weak RTC_Alarm_IRQHandler + .thumb_set RTC_Alarm_IRQHandler,Default_Handler + + .weak CEC_IRQHandler + .thumb_set CEC_IRQHandler,Default_Handler + + .weak TIM12_IRQHandler + .thumb_set TIM12_IRQHandler,Default_Handler + + .weak TIM13_IRQHandler + .thumb_set TIM13_IRQHandler,Default_Handler + + .weak TIM14_IRQHandler + .thumb_set TIM14_IRQHandler,Default_Handler + + .weak TIM5_IRQHandler + .thumb_set TIM5_IRQHandler,Default_Handler + + .weak SPI3_IRQHandler + .thumb_set SPI3_IRQHandler,Default_Handler + + .weak TIM6_DAC1_IRQHandler + .thumb_set TIM6_DAC1_IRQHandler,Default_Handler + + .weak TIM7_IRQHandler + .thumb_set TIM7_IRQHandler,Default_Handler + + .weak DMA2_Channel1_IRQHandler + .thumb_set DMA2_Channel1_IRQHandler,Default_Handler + + .weak DMA2_Channel2_IRQHandler + .thumb_set DMA2_Channel2_IRQHandler,Default_Handler + + .weak DMA2_Channel3_IRQHandler + .thumb_set DMA2_Channel3_IRQHandler,Default_Handler + + .weak DMA2_Channel4_IRQHandler + .thumb_set DMA2_Channel4_IRQHandler,Default_Handler + + .weak DMA2_Channel5_IRQHandler + .thumb_set DMA2_Channel5_IRQHandler,Default_Handler + + .weak SDADC1_IRQHandler + .thumb_set SDADC1_IRQHandler,Default_Handler + + .weak SDADC2_IRQHandler + .thumb_set SDADC2_IRQHandler,Default_Handler + + .weak SDADC3_IRQHandler + .thumb_set SDADC3_IRQHandler,Default_Handler + + .weak COMP_IRQHandler + .thumb_set COMP_IRQHandler,Default_Handler + + .weak USB_HP_IRQHandler + .thumb_set USB_HP_IRQHandler,Default_Handler + + .weak USB_LP_IRQHandler + .thumb_set USB_LP_IRQHandler,Default_Handler + + .weak USBWakeUp_IRQHandler + .thumb_set USBWakeUp_IRQHandler,Default_Handler + + .weak TIM19_IRQHandler + .thumb_set TIM19_IRQHandler,Default_Handler + + .weak FPU_IRQHandler + .thumb_set FPU_IRQHandler,Default_Handler + + +/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ diff --git a/Libraries/CMSIS/Device/ST/STM32F37x/Source/Templates/iar/startup_stm32f37x.s b/Libraries/CMSIS/Device/ST/STM32F37x/Source/Templates/iar/startup_stm32f37x.s new file mode 100644 index 0000000..211862e --- /dev/null +++ b/Libraries/CMSIS/Device/ST/STM32F37x/Source/Templates/iar/startup_stm32f37x.s @@ -0,0 +1,542 @@ +;/******************** (C) COPYRIGHT 2012 STMicroelectronics ******************** +;* File Name : startup_stm32f37x.s +;* Author : MCD Application Team +;* Version : V1.0.0 +;* Date : 20-September-2012 +;* Description : STM32F37x Devices vector table for EWARM toolchain. +;* This module performs: +;* - Set the initial SP +;* - Set the initial PC == iar_program_start, +;* - Set the vector table entries with the exceptions ISR +;* address. +;* After Reset the Cortex-M4 processor is in Thread mode, +;* priority is Privileged, and the Stack is set to Main. +;******************************************************************************* +; @attention +; +; Licensed under MCD-ST Liberty SW License Agreement V2, (the "License"); +; You may not use this file except in compliance with the License. +; You may obtain a copy of the License at: +; +; http://www.st.com/software_license_agreement_liberty_v2 +; +; Unless required by applicable law or agreed to in writing, software +; distributed under the License is distributed on an "AS IS" BASIS, +; WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +; See the License for the specific language governing permissions and +; limitations under the License. +; +;******************************************************************************* +; +; +; The modules in this file are included in the libraries, and may be replaced +; by any user-defined modules that define the PUBLIC symbol _program_start or +; a user defined start symbol. +; To override the cstartup defined in the library, simply add your modified +; version to the workbench project. +; +; The vector table is normally located at address 0. +; When debugging in RAM, it can be located in RAM, aligned to at least 2^6. +; The name "__vector_table" has special meaning for C-SPY: +; it is where the SP start value is found, and the NVIC vector +; table register (VTOR) is initialized to this address if != 0. +; +; Cortex-M version +; + + MODULE ?cstartup + + ;; Forward declaration of sections. + SECTION CSTACK:DATA:NOROOT(3) + + SECTION .intvec:CODE:NOROOT(2) + + EXTERN __iar_program_start + EXTERN SystemInit + PUBLIC __vector_table + + DATA +__vector_table + DCD sfe(CSTACK) + DCD Reset_Handler ; Reset Handler + + DCD NMI_Handler ; NMI Handler + DCD HardFault_Handler ; Hard Fault Handler + DCD MemManage_Handler ; MPU Fault Handler + DCD BusFault_Handler ; Bus Fault Handler + DCD UsageFault_Handler ; Usage Fault Handler + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD SVC_Handler ; SVCall Handler + DCD DebugMon_Handler ; Debug Monitor Handler + DCD 0 ; Reserved + DCD PendSV_Handler ; PendSV Handler + DCD SysTick_Handler ; SysTick Handler + + ; External Interrupts + DCD WWDG_IRQHandler ; Window WatchDog + DCD PVD_IRQHandler ; PVD through EXTI Line detection + DCD TAMPER_STAMP_IRQHandler ; Tamper and TimeStamps through the EXTI line + DCD RTC_WKUP_IRQHandler ; RTC Wakeup through the EXTI line + DCD FLASH_IRQHandler ; FLASH + DCD RCC_IRQHandler ; RCC + DCD EXTI0_IRQHandler ; EXTI Line0 + DCD EXTI1_IRQHandler ; EXTI Line1 + DCD EXTI2_TS_IRQHandler ; EXTI Line2 and Touch Sense controller + DCD EXTI3_IRQHandler ; EXTI Line3 + DCD EXTI4_IRQHandler ; EXTI Line4 + DCD DMA1_Channel1_IRQHandler ; DMA1 Channel 1 + DCD DMA1_Channel2_IRQHandler ; DMA1 Channel 2 + DCD DMA1_Channel3_IRQHandler ; DMA1 Channel 3 + DCD DMA1_Channel4_IRQHandler ; DMA1 Channel 4 + DCD DMA1_Channel5_IRQHandler ; DMA1 Channel 5 + DCD DMA1_Channel6_IRQHandler ; DMA1 Channel 6 + DCD DMA1_Channel7_IRQHandler ; DMA1 Channel 7 + DCD ADC1_IRQHandler ; ADC1 + DCD CAN1_TX_IRQHandler ; CAN1 TX + DCD CAN1_RX0_IRQHandler ; CAN1 RX0 + DCD CAN1_RX1_IRQHandler ; CAN1 RX1 + DCD CAN1_SCE_IRQHandler ; CAN1 SCE + DCD EXTI9_5_IRQHandler ; External Line[9:5]s + DCD TIM15_IRQHandler ; TIM15 + DCD TIM16_IRQHandler ; TIM16 + DCD TIM17_IRQHandler ; TIM17 + DCD TIM18_DAC2_IRQHandler ; TIM18 and DAC2 + DCD TIM2_IRQHandler ; TIM2 + DCD TIM3_IRQHandler ; TIM3 + DCD TIM4_IRQHandler ; TIM4 + DCD I2C1_EV_IRQHandler ; I2C1 Event + DCD I2C1_ER_IRQHandler ; I2C1 Error + DCD I2C2_EV_IRQHandler ; I2C2 Event + DCD I2C2_ER_IRQHandler ; I2C2 Error + DCD SPI1_IRQHandler ; SPI1 + DCD SPI2_IRQHandler ; SPI2 + DCD USART1_IRQHandler ; USART1 + DCD USART2_IRQHandler ; USART2 + DCD USART3_IRQHandler ; USART3 + DCD EXTI15_10_IRQHandler ; External Line[15:10]s + DCD RTC_Alarm_IRQHandler ; RTC Alarm (A and B) through EXTI Line + DCD CEC_IRQHandler ; CEC + DCD TIM12_IRQHandler ; TIM12 + DCD TIM13_IRQHandler ; TIM13 + DCD TIM14_IRQHandler ; TIM14 + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD TIM5_IRQHandler ; TIM5 + DCD SPI3_IRQHandler ; SPI3 + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD TIM6_DAC1_IRQHandler ; TIM6 and DAC1 Channel1 & channel2 + DCD TIM7_IRQHandler ; TIM7 + DCD DMA2_Channel1_IRQHandler ; DMA2 Channel 1 + DCD DMA2_Channel2_IRQHandler ; DMA2 Channel 2 + DCD DMA2_Channel3_IRQHandler ; DMA2 Channel 3 + DCD DMA2_Channel4_IRQHandler ; DMA2 Channel 4 + DCD DMA2_Channel5_IRQHandler ; DMA2 Channel 5 + DCD SDADC1_IRQHandler ; SDADC1 + DCD SDADC2_IRQHandler ; SDADC2 + DCD SDADC3_IRQHandler ; SDADC3 + DCD COMP_IRQHandler ; COMP + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD USB_HP_IRQHandler ; USB High Priority + DCD USB_LP_IRQHandler ; USB Low Priority + DCD USBWakeUp_IRQHandler ; USB Wakeup + DCD 0 ; Reserved + DCD TIM19_IRQHandler ; TIM19 + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD FPU_IRQHandler ; FPU + +;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;; +;; +;; Default interrupt handlers. +;; + THUMB + PUBWEAK Reset_Handler + SECTION .text:CODE:REORDER(2) +Reset_Handler + + LDR R0, =SystemInit + BLX R0 + LDR R0, =__iar_program_start + BX R0 + + PUBWEAK NMI_Handler + SECTION .text:CODE:REORDER(1) +NMI_Handler + B NMI_Handler + + PUBWEAK HardFault_Handler + SECTION .text:CODE:REORDER(1) +HardFault_Handler + B HardFault_Handler + + PUBWEAK MemManage_Handler + SECTION .text:CODE:REORDER(1) +MemManage_Handler + B MemManage_Handler + + PUBWEAK BusFault_Handler + SECTION .text:CODE:REORDER(1) +BusFault_Handler + B BusFault_Handler + + PUBWEAK UsageFault_Handler + SECTION .text:CODE:REORDER(1) +UsageFault_Handler + B UsageFault_Handler + + PUBWEAK SVC_Handler + SECTION .text:CODE:REORDER(1) +SVC_Handler + B SVC_Handler + + PUBWEAK DebugMon_Handler + SECTION .text:CODE:REORDER(1) +DebugMon_Handler + B DebugMon_Handler + + PUBWEAK PendSV_Handler + SECTION .text:CODE:REORDER(1) +PendSV_Handler + B PendSV_Handler + + PUBWEAK SysTick_Handler + SECTION .text:CODE:REORDER(1) +SysTick_Handler + B SysTick_Handler + + PUBWEAK WWDG_IRQHandler + SECTION .text:CODE:REORDER(1) +WWDG_IRQHandler + B WWDG_IRQHandler + + PUBWEAK PVD_IRQHandler + SECTION .text:CODE:REORDER(1) +PVD_IRQHandler + B PVD_IRQHandler + + PUBWEAK TAMPER_STAMP_IRQHandler + SECTION .text:CODE:REORDER(1) +TAMPER_STAMP_IRQHandler + B TAMPER_STAMP_IRQHandler + + PUBWEAK RTC_WKUP_IRQHandler + SECTION .text:CODE:REORDER(1) +RTC_WKUP_IRQHandler + B RTC_WKUP_IRQHandler + + PUBWEAK FLASH_IRQHandler + SECTION .text:CODE:REORDER(1) +FLASH_IRQHandler + B FLASH_IRQHandler + + PUBWEAK RCC_IRQHandler + SECTION .text:CODE:REORDER(1) +RCC_IRQHandler + B RCC_IRQHandler + + PUBWEAK EXTI0_IRQHandler + SECTION .text:CODE:REORDER(1) +EXTI0_IRQHandler + B EXTI0_IRQHandler + + PUBWEAK EXTI1_IRQHandler + SECTION .text:CODE:REORDER(1) +EXTI1_IRQHandler + B EXTI1_IRQHandler + + PUBWEAK EXTI2_TS_IRQHandler + SECTION .text:CODE:REORDER(1) +EXTI2_TS_IRQHandler + B EXTI2_TS_IRQHandler + + PUBWEAK EXTI3_IRQHandler + SECTION .text:CODE:REORDER(1) +EXTI3_IRQHandler + B EXTI3_IRQHandler + + PUBWEAK EXTI4_IRQHandler + SECTION .text:CODE:REORDER(1) +EXTI4_IRQHandler + B EXTI4_IRQHandler + + PUBWEAK DMA1_Channel1_IRQHandler + SECTION .text:CODE:REORDER(1) +DMA1_Channel1_IRQHandler + B DMA1_Channel1_IRQHandler + + PUBWEAK DMA1_Channel2_IRQHandler + SECTION .text:CODE:REORDER(1) +DMA1_Channel2_IRQHandler + B DMA1_Channel2_IRQHandler + + PUBWEAK DMA1_Channel3_IRQHandler + SECTION .text:CODE:REORDER(1) +DMA1_Channel3_IRQHandler + B DMA1_Channel3_IRQHandler + + PUBWEAK DMA1_Channel4_IRQHandler + SECTION .text:CODE:REORDER(1) +DMA1_Channel4_IRQHandler + B DMA1_Channel4_IRQHandler + + PUBWEAK DMA1_Channel5_IRQHandler + SECTION .text:CODE:REORDER(1) +DMA1_Channel5_IRQHandler + B DMA1_Channel5_IRQHandler + + PUBWEAK DMA1_Channel6_IRQHandler + SECTION .text:CODE:REORDER(1) +DMA1_Channel6_IRQHandler + B DMA1_Channel6_IRQHandler + + PUBWEAK DMA1_Channel7_IRQHandler + SECTION .text:CODE:REORDER(1) +DMA1_Channel7_IRQHandler + B DMA1_Channel7_IRQHandler + + PUBWEAK ADC1_IRQHandler + SECTION .text:CODE:REORDER(1) +ADC1_IRQHandler + B ADC1_IRQHandler + + PUBWEAK CAN1_TX_IRQHandler + SECTION .text:CODE:REORDER(1) +CAN1_TX_IRQHandler + B CAN1_TX_IRQHandler + + PUBWEAK CAN1_RX0_IRQHandler + SECTION .text:CODE:REORDER(1) +CAN1_RX0_IRQHandler + B CAN1_RX0_IRQHandler + + PUBWEAK CAN1_RX1_IRQHandler + SECTION .text:CODE:REORDER(1) +CAN1_RX1_IRQHandler + B CAN1_RX1_IRQHandler + + PUBWEAK CAN1_SCE_IRQHandler + SECTION .text:CODE:REORDER(1) +CAN1_SCE_IRQHandler + B CAN1_SCE_IRQHandler + + PUBWEAK EXTI9_5_IRQHandler + SECTION .text:CODE:REORDER(1) +EXTI9_5_IRQHandler + B EXTI9_5_IRQHandler + + PUBWEAK TIM15_IRQHandler + SECTION .text:CODE:REORDER(1) +TIM15_IRQHandler + B TIM15_IRQHandler + + PUBWEAK TIM16_IRQHandler + SECTION .text:CODE:REORDER(1) +TIM16_IRQHandler + B TIM16_IRQHandler + + PUBWEAK TIM17_IRQHandler + SECTION .text:CODE:REORDER(1) +TIM17_IRQHandler + B TIM17_IRQHandler + + PUBWEAK TIM18_DAC2_IRQHandler + SECTION .text:CODE:REORDER(1) +TIM18_DAC2_IRQHandler + B TIM18_DAC2_IRQHandler + + PUBWEAK TIM2_IRQHandler + SECTION .text:CODE:REORDER(1) +TIM2_IRQHandler + B TIM2_IRQHandler + + PUBWEAK TIM3_IRQHandler + SECTION .text:CODE:REORDER(1) +TIM3_IRQHandler + B TIM3_IRQHandler + + PUBWEAK TIM4_IRQHandler + SECTION .text:CODE:REORDER(1) +TIM4_IRQHandler + B TIM4_IRQHandler + + PUBWEAK I2C1_EV_IRQHandler + SECTION .text:CODE:REORDER(1) +I2C1_EV_IRQHandler + B I2C1_EV_IRQHandler + + PUBWEAK I2C1_ER_IRQHandler + SECTION .text:CODE:REORDER(1) +I2C1_ER_IRQHandler + B I2C1_ER_IRQHandler + + PUBWEAK I2C2_EV_IRQHandler + SECTION .text:CODE:REORDER(1) +I2C2_EV_IRQHandler + B I2C2_EV_IRQHandler + + PUBWEAK I2C2_ER_IRQHandler + SECTION .text:CODE:REORDER(1) +I2C2_ER_IRQHandler + B I2C2_ER_IRQHandler + + PUBWEAK SPI1_IRQHandler + SECTION .text:CODE:REORDER(1) +SPI1_IRQHandler + B SPI1_IRQHandler + + PUBWEAK SPI2_IRQHandler + SECTION .text:CODE:REORDER(1) +SPI2_IRQHandler + B SPI2_IRQHandler + + PUBWEAK USART1_IRQHandler + SECTION .text:CODE:REORDER(1) +USART1_IRQHandler + B USART1_IRQHandler + + PUBWEAK USART2_IRQHandler + SECTION .text:CODE:REORDER(1) +USART2_IRQHandler + B USART2_IRQHandler + + PUBWEAK USART3_IRQHandler + SECTION .text:CODE:REORDER(1) +USART3_IRQHandler + B USART3_IRQHandler + + PUBWEAK EXTI15_10_IRQHandler + SECTION .text:CODE:REORDER(1) +EXTI15_10_IRQHandler + B EXTI15_10_IRQHandler + + PUBWEAK RTC_Alarm_IRQHandler + SECTION .text:CODE:REORDER(1) +RTC_Alarm_IRQHandler + B RTC_Alarm_IRQHandler + + PUBWEAK CEC_IRQHandler + SECTION .text:CODE:REORDER(1) +CEC_IRQHandler + B CEC_IRQHandler + + PUBWEAK TIM12_IRQHandler + SECTION .text:CODE:REORDER(1) +TIM12_IRQHandler + B TIM12_IRQHandler + + PUBWEAK TIM13_IRQHandler + SECTION .text:CODE:REORDER(1) +TIM13_IRQHandler + B TIM13_IRQHandler + + PUBWEAK TIM14_IRQHandler + SECTION .text:CODE:REORDER(1) +TIM14_IRQHandler + B TIM14_IRQHandler + + PUBWEAK TIM5_IRQHandler + SECTION .text:CODE:REORDER(1) +TIM5_IRQHandler + B TIM5_IRQHandler + + PUBWEAK SPI3_IRQHandler + SECTION .text:CODE:REORDER(1) +SPI3_IRQHandler + B SPI3_IRQHandler + + PUBWEAK TIM6_DAC1_IRQHandler + SECTION .text:CODE:REORDER(1) +TIM6_DAC1_IRQHandler + B TIM6_DAC1_IRQHandler + + PUBWEAK TIM7_IRQHandler + SECTION .text:CODE:REORDER(1) +TIM7_IRQHandler + B TIM7_IRQHandler + + PUBWEAK DMA2_Channel1_IRQHandler + SECTION .text:CODE:REORDER(1) +DMA2_Channel1_IRQHandler + B DMA2_Channel1_IRQHandler + + PUBWEAK DMA2_Channel2_IRQHandler + SECTION .text:CODE:REORDER(1) +DMA2_Channel2_IRQHandler + B DMA2_Channel2_IRQHandler + + PUBWEAK DMA2_Channel3_IRQHandler + SECTION .text:CODE:REORDER(1) +DMA2_Channel3_IRQHandler + B DMA2_Channel3_IRQHandler + + PUBWEAK DMA2_Channel4_IRQHandler + SECTION .text:CODE:REORDER(1) +DMA2_Channel4_IRQHandler + B DMA2_Channel4_IRQHandler + + PUBWEAK DMA2_Channel5_IRQHandler + SECTION .text:CODE:REORDER(1) +DMA2_Channel5_IRQHandler + B DMA2_Channel5_IRQHandler + + PUBWEAK SDADC1_IRQHandler + SECTION .text:CODE:REORDER(1) +SDADC1_IRQHandler + B SDADC1_IRQHandler + + PUBWEAK SDADC2_IRQHandler + SECTION .text:CODE:REORDER(1) +SDADC2_IRQHandler + B SDADC2_IRQHandler + + PUBWEAK SDADC3_IRQHandler + SECTION .text:CODE:REORDER(1) +SDADC3_IRQHandler + B SDADC3_IRQHandler + + PUBWEAK COMP_IRQHandler + SECTION .text:CODE:REORDER(1) +COMP_IRQHandler + B COMP_IRQHandler + + PUBWEAK USB_HP_IRQHandler + SECTION .text:CODE:REORDER(1) +USB_HP_IRQHandler + B USB_HP_IRQHandler + + PUBWEAK USB_LP_IRQHandler + SECTION .text:CODE:REORDER(1) +USB_LP_IRQHandler + B USB_LP_IRQHandler + + PUBWEAK USBWakeUp_IRQHandler + SECTION .text:CODE:REORDER(1) +USBWakeUp_IRQHandler + B USBWakeUp_IRQHandler + + PUBWEAK TIM19_IRQHandler + SECTION .text:CODE:REORDER(1) +TIM19_IRQHandler + B TIM19_IRQHandler + + PUBWEAK FPU_IRQHandler + SECTION .text:CODE:REORDER(1) +FPU_IRQHandler + B FPU_IRQHandler + + END +;************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE***** diff --git a/Libraries/CMSIS/Device/ST/STM32F37x/Source/Templates/system_stm32f37x.c b/Libraries/CMSIS/Device/ST/STM32F37x/Source/Templates/system_stm32f37x.c new file mode 100644 index 0000000..f7add14 --- /dev/null +++ b/Libraries/CMSIS/Device/ST/STM32F37x/Source/Templates/system_stm32f37x.c @@ -0,0 +1,380 @@ +/** + ****************************************************************************** + * @file system_stm32f37x.c + * @author MCD Application Team + * @version V1.0.0 + * @date 20-September-2012 + * @brief CMSIS Cortex-M4 Device Peripheral Access Layer System Source File. + * This file contains the system clock configuration for STM32F37x devices, + * and is generated by the clock configuration tool + * STM32f37x_Clock_Configuration_V1.0.0.xls + * + * 1. This file provides two functions and one global variable to be called from + * user application: + * - SystemInit(): Setups the system clock (System clock source, PLL Multiplier + * and Divider factors, AHB/APBx prescalers and Flash settings), + * depending on the configuration made in the clock xls tool. + * This function is called at startup just after reset and + * before branch to main program. This call is made inside + * the "startup_stm32f37x.s" file. + * + * - SystemCoreClock variable: Contains the core clock (HCLK), it can be used + * by the user application to setup the SysTick + * timer or configure other parameters. + * + * - SystemCoreClockUpdate(): Updates the variable SystemCoreClock and must + * be called whenever the core clock is changed + * during program execution. + * + * 2. After each device reset the HSI (8 MHz Range) is used as system clock source. + * Then SystemInit() function is called, in "startup_stm32f37x.s" file, to + * configure the system clock before to branch to main program. + * + * 3. If the system clock source selected by user fails to startup, the SystemInit() + * function will do nothing and HSI still used as system clock source. User can + * add some code to deal with this issue inside the SetSysClock() function. + * + * 4. The default value of HSE crystal is set to 8MHz, refer to "HSE_VALUE" defined + * in "stm32f37x.h" file. When HSE is used as system clock source, directly or + * through PLL, and you are using different crystal you have to adapt the HSE + * value to your own configuration. + * + * 5. This file configures the system clock as follows: + *============================================================================= + * Supported STM32F37x device + *============================================================================= + * System Clock source | PLL (HSE) + *----------------------------------------------------------------------------- + * SYSCLK(Hz) | 72000000 + *----------------------------------------------------------------------------- + * HCLK(Hz) | 72000000 + *----------------------------------------------------------------------------- + * AHB Prescaler | 1 + *----------------------------------------------------------------------------- + * APB2 Prescaler | 1 + *----------------------------------------------------------------------------- + * APB1 Prescaler | 2 + *----------------------------------------------------------------------------- + * HSE Frequency(Hz) | 8000000 + *---------------------------------------------------------------------------- + * PLLMUL | 9 + *----------------------------------------------------------------------------- + * PREDIV | 1 + *----------------------------------------------------------------------------- + * USB Clock | DISABLE + *----------------------------------------------------------------------------- + * Flash Latency(WS) | 2 + *----------------------------------------------------------------------------- + * Prefetch Buffer | ON + *----------------------------------------------------------------------------- + *============================================================================= + ****************************************************************************** + * @attention + * + *

© COPYRIGHT 2012 STMicroelectronics

+ * + * Licensed under MCD-ST Liberty SW License Agreement V2, (the "License"); + * You may not use this file except in compliance with the License. + * You may obtain a copy of the License at: + * + * http://www.st.com/software_license_agreement_liberty_v2 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, + * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + * + ****************************************************************************** + */ + +/** @addtogroup CMSIS + * @{ + */ + +/** @addtogroup STM32F37x_System + * @{ + */ + +/** @addtogroup STM32F37x_System_Private_Includes + * @{ + */ + +#include "stm32f37x.h" + +/** + * @} + */ + +/** @addtogroup STM32F37x_System_Private_TypesDefinitions + * @{ + */ + +/** + * @} + */ + +/** @addtogroup STM32F37x_System_Private_Defines + * @{ + */ + +/*!< Uncomment the following line if you need to relocate your vector Table in + Internal SRAM. */ +/* #define VECT_TAB_SRAM */ +#define VECT_TAB_OFFSET 0x0 /*!< Vector Table base offset field. + This value must be a multiple of 0x200. */ +/** + * @} + */ + +/** @addtogroup STM32F37x_System_Private_Macros + * @{ + */ + +/** + * @} + */ + +/** @addtogroup STM32F37x_System_Private_Variables + * @{ + */ +uint32_t SystemCoreClock = 72000000; +__I uint8_t AHBPrescTable[16] = {0, 0, 0, 0, 0, 0, 0, 0, 1, 2, 3, 4, 6, 7, 8, 9}; + +/** + * @} + */ + +/** @addtogroup STM32F37x_System_Private_FunctionPrototypes + * @{ + */ + +static void SetSysClock(void); + +/** + * @} + */ + +/** @addtogroup STM32F37x_System_Private_Functions + * @{ + */ + +/** + * @brief Setup the microcontrollers system. + * Initialize the Embedded Flash Interface, the PLL and update the + * SystemCoreClock variable. + * @param None + * @retval None + */ +void SystemInit (void) +{ + /* FPU settings ------------------------------------------------------------*/ + #if (__FPU_PRESENT == 1) && (__FPU_USED == 1) + SCB->CPACR |= ((3UL << 10*2)|(3UL << 11*2)); /* set CP10 and CP11 Full Access */ + #endif + + /* Set HSION bit */ + RCC->CR |= (uint32_t)0x00000001; + + /* Reset SW[1:0], HPRE[3:0], PPRE[2:0], ADCPRE, SDADCPRE and MCOSEL[2:0] bits */ + RCC->CFGR &= (uint32_t)0x00FF0000; + + /* Reset HSEON, CSSON and PLLON bits */ + RCC->CR &= (uint32_t)0xFEF6FFFF; + + /* Reset HSEBYP bit */ + RCC->CR &= (uint32_t)0xFFFBFFFF; + + /* Reset PLLSRC, PLLXTPRE, PLLMUL and USBPRE bits */ + RCC->CFGR &= (uint32_t)0xFF80FFFF; + + /* Reset PREDIV1[3:0] bits */ + RCC->CFGR2 &= (uint32_t)0xFFFFFFF0; + + /* Reset USARTSW[1:0], I2CSW and CECSW bits */ + RCC->CFGR3 &= (uint32_t)0xFFF0F8C; + + /* Disable all interrupts */ + RCC->CIR = 0x00000000; + +/* Configure the System clock frequency, AHB/APBx prescalers and Flash settings */ + SetSysClock(); + + +#ifdef VECT_TAB_SRAM + SCB->VTOR = SRAM_BASE | VECT_TAB_OFFSET; /* Vector Table Relocation in Internal SRAM. */ +#else + SCB->VTOR = FLASH_BASE | VECT_TAB_OFFSET; /* Vector Table Relocation in Internal FLASH. */ +#endif +} + +/** + * @brief Update SystemCoreClock according to Clock Register Values + * The SystemCoreClock variable contains the core clock (HCLK), it can + * be used by the user application to setup the SysTick timer or configure + * other parameters. + * + * @note Each time the core clock (HCLK) changes, this function must be called + * to update SystemCoreClock variable value. Otherwise, any configuration + * based on this variable will be incorrect. + * + * @note - The system frequency computed by this function is not the real + * frequency in the chip. It is calculated based on the predefined + * constant and the selected clock source: + * + * - If SYSCLK source is HSI, SystemCoreClock will contain the HSI_VALUE(*) + * + * - If SYSCLK source is HSE, SystemCoreClock will contain the HSE_VALUE(**) + * + * - If SYSCLK source is PLL, SystemCoreClock will contain the HSE_VALUE(**) + * or HSI_VALUE(*) multiplied/divided by the PLL factors. + * + * (*) HSI_VALUE is a constant defined in stm32f37x.h file (default value + * 8 MHz) but the real value may vary depending on the variations + * in voltage and temperature. + * + * (**) HSE_VALUE is a constant defined in stm32f37x.h file (default value + * 8 MHz), user has to ensure that HSE_VALUE is same as the real + * frequency of the crystal used. Otherwise, this function may + * have wrong result. + * + * - The result of this function could be not correct when using fractional + * value for HSE crystal. + * @param None + * @retval None + */ +void SystemCoreClockUpdate (void) +{ + uint32_t tmp = 0, pllmull = 0, pllsource = 0, prediv1factor = 0; + + /* Get SYSCLK source -------------------------------------------------------*/ + tmp = RCC->CFGR & RCC_CFGR_SWS; + + switch (tmp) + { + case 0x00: /* HSI used as system clock */ + SystemCoreClock = HSI_VALUE; + break; + case 0x04: /* HSE used as system clock */ + SystemCoreClock = HSE_VALUE; + break; + case 0x08: /* PLL used as system clock */ + /* Get PLL clock source and multiplication factor ----------------------*/ + pllmull = RCC->CFGR & RCC_CFGR_PLLMULL; + pllsource = RCC->CFGR & RCC_CFGR_PLLSRC; + pllmull = ( pllmull >> 18) + 2; + + if (pllsource == 0x00) + { + /* HSI oscillator clock divided by 2 selected as PLL clock entry */ + SystemCoreClock = (HSI_VALUE >> 1) * pllmull; + } + else + { + prediv1factor = (RCC->CFGR2 & RCC_CFGR2_PREDIV1) + 1; + /* HSE oscillator clock selected as PREDIV1 clock entry */ + SystemCoreClock = (HSE_VALUE / prediv1factor) * pllmull; + } + break; + default: /* HSI used as system clock */ + SystemCoreClock = HSI_VALUE; + break; + } + /* Compute HCLK clock frequency ----------------*/ + /* Get HCLK prescaler */ + tmp = AHBPrescTable[((RCC->CFGR & RCC_CFGR_HPRE) >> 4)]; + /* HCLK clock frequency */ + SystemCoreClock >>= tmp; +} + +/** + * @brief Configures the System clock frequency, AHB/APBx prescalers and Flash + * settings. + * @note This function should be called only once the RCC clock configuration + * is reset to the default reset state (done in SystemInit() function). + * @param None + * @retval None + */ +static void SetSysClock(void) +{ + __IO uint32_t StartUpCounter = 0, HSEStatus = 0; + +/******************************************************************************/ +/* PLL (clocked by HSE) used as System clock source */ +/******************************************************************************/ + + /* SYSCLK, HCLK, PCLK2 and PCLK1 configuration -----------*/ + /* Enable HSE */ + RCC->CR |= ((uint32_t)RCC_CR_HSEON); + + /* Wait till HSE is ready and if Time out is reached exit */ + do + { + HSEStatus = RCC->CR & RCC_CR_HSERDY; + StartUpCounter++; + } while((HSEStatus == 0) && (StartUpCounter != HSE_STARTUP_TIMEOUT)); + + if ((RCC->CR & RCC_CR_HSERDY) != RESET) + { + HSEStatus = (uint32_t)0x01; + } + else + { + HSEStatus = (uint32_t)0x00; + } + + if (HSEStatus == (uint32_t)0x01) + { + /* Enable Prefetch Buffer and set Flash Latency */ + FLASH->ACR = FLASH_ACR_PRFTBE | (uint32_t)FLASH_ACR_LATENCY_1; + + /* HCLK = SYSCLK / 1 */ + RCC->CFGR |= (uint32_t)RCC_CFGR_HPRE_DIV1; + + /* PCLK2 = HCLK / 1 */ + RCC->CFGR |= (uint32_t)RCC_CFGR_PPRE2_DIV1; + + /* PCLK1 = HCLK / 2 */ + RCC->CFGR |= (uint32_t)RCC_CFGR_PPRE1_DIV2; + + /* PLL configuration */ + RCC->CFGR &= (uint32_t)((uint32_t)~(RCC_CFGR_PLLSRC | RCC_CFGR_PLLXTPRE | RCC_CFGR_PLLMULL)); + RCC->CFGR |= (uint32_t)(RCC_CFGR_PLLSRC_PREDIV1 | RCC_CFGR_PLLXTPRE_PREDIV1 | RCC_CFGR_PLLMULL9); + + /* Enable PLL */ + RCC->CR |= RCC_CR_PLLON; + + /* Wait till PLL is ready */ + while((RCC->CR & RCC_CR_PLLRDY) == 0) + { + } + + /* Select PLL as system clock source */ + RCC->CFGR &= (uint32_t)((uint32_t)~(RCC_CFGR_SW)); + RCC->CFGR |= (uint32_t)RCC_CFGR_SW_PLL; + + /* Wait till PLL is used as system clock source */ + while ((RCC->CFGR & (uint32_t)RCC_CFGR_SWS) != (uint32_t)RCC_CFGR_SWS_PLL) + { + } + } + else + { /* If HSE fails to start-up, the application will have wrong clock + configuration. User can add here some code to deal with this error */ + } +} + +/** + * @} + */ + +/** + * @} + */ + +/** + * @} + */ + +/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ + diff --git a/Libraries/CMSIS/Device/ST/STM32L1xx/Include/stm32l1xx.h b/Libraries/CMSIS/Device/ST/STM32L1xx/Include/stm32l1xx.h new file mode 100644 index 0000000..df5adaa --- /dev/null +++ b/Libraries/CMSIS/Device/ST/STM32L1xx/Include/stm32l1xx.h @@ -0,0 +1,6351 @@ +/** + ****************************************************************************** + * @file stm32l1xx.h + * @author MCD Application Team + * @version V1.1.1 + * @date 09-March-2012 + * @brief CMSIS Cortex-M3 Device Peripheral Access Layer Header File. + * This file contains all the peripheral register's definitions, bits + * definitions and memory mapping for STM32L1xx High-, Medium-density + * and Medium-density Plus devices. + * + * The file is the unique include file that the application programmer + * is using in the C source code, usually in main.c. This file contains: + * - Configuration section that allows to select: + * - The device used in the target application + * - To use or not the peripherals drivers in application code(i.e. + * code will be based on direct access to peripherals registers + * rather than drivers API), this option is controlled by + * "#define USE_STDPERIPH_DRIVER" + * - To change few application-specific parameters such as the HSE + * crystal frequency + * - Data structures and the address mapping for all peripherals + * - Peripheral's registers declarations and bits definition + * - Macros to access peripherals registers hardware + * + ****************************************************************************** + * @attention + * + *

© COPYRIGHT 2012 STMicroelectronics

+ * + * Licensed under MCD-ST Liberty SW License Agreement V2, (the "License"); + * You may not use this file except in compliance with the License. + * You may obtain a copy of the License at: + * + * http://www.st.com/software_license_agreement_liberty_v2 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, + * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + * + ****************************************************************************** + */ + +/** @addtogroup CMSIS + * @{ + */ + +/** @addtogroup stm32l1xx + * @{ + */ + +#ifndef __STM32L1XX_H +#define __STM32L1XX_H + +#ifdef __cplusplus + extern "C" { +#endif + +/** @addtogroup Library_configuration_section + * @{ + */ + +/* Uncomment the line below according to the target STM32L device used in your + application + */ + +#if !defined (STM32L1XX_MD) && !defined (STM32L1XX_MDP) && !defined (STM32L1XX_HD) + /* #define STM32L1XX_MD */ /*!< STM32L1XX_MD: STM32L Ultra Low Power Medium-density devices */ + /* #define STM32L1XX_MDP */ /*!< STM32L1XX_MDP: STM32L Ultra Low Power Medium-density Plus devices */ + #define STM32L1XX_HD /*!< STM32L1XX_HD: STM32L Ultra Low Power High-density devices */ +#endif +/* Tip: To avoid modifying this file each time you need to switch between these + devices, you can define the device in your toolchain compiler preprocessor. + + - Ultra Low Power Medium-density devices are STM32L151xx and STM32L152xx + microcontrollers where the Flash memory density ranges between 64 and 128 Kbytes. + - Ultra Low Power Medium-density Plus devices are STM32L151xx, STM32L152xx and + STM32L162xx microcontrollers where the Flash memory density is 256 Kbytes. + - Ultra Low Power High-density devices are STM32L151xx, STM32L152xx and STM32L162xx + microcontrollers where the Flash memory density is 384 Kbytes. + */ + +#if !defined (STM32L1XX_MD) && !defined (STM32L1XX_MDP) && !defined (STM32L1XX_HD) + #error "Please select first the target STM32L1xx device used in your application (in stm32l1xx.h file)" +#endif + +#if !defined USE_STDPERIPH_DRIVER +/** + * @brief Comment the line below if you will not use the peripherals drivers. + In this case, these drivers will not be included and the application code will + be based on direct access to peripherals registers + */ + /*#define USE_STDPERIPH_DRIVER*/ +#endif + +/** + * @brief In the following line adjust the value of External High Speed oscillator (HSE) + used in your application + + Tip: To avoid modifying this file each time you need to use different HSE, you + can define the HSE value in your toolchain compiler preprocessor. + */ +#if !defined (HSE_VALUE) +#define HSE_VALUE ((uint32_t)8000000) /*!< Value of the External oscillator in Hz */ +#endif + +/** + * @brief In the following line adjust the External High Speed oscillator (HSE) Startup + Timeout value + */ +#if !defined (HSE_STARTUP_TIMEOUT) +#define HSE_STARTUP_TIMEOUT ((uint16_t)0x0500) /*!< Time out for HSE start up */ +#endif + +/** + * @brief In the following line adjust the Internal High Speed oscillator (HSI) Startup + Timeout value + */ +#if !defined (HSI_STARTUP_TIMEOUT) +#define HSI_STARTUP_TIMEOUT ((uint16_t)0x0500) /*!< Time out for HSI start up */ +#endif + +#if !defined (HSI_VALUE) +#define HSI_VALUE ((uint32_t)16000000) /*!< Value of the Internal High Speed oscillator in Hz. + The real value may vary depending on the variations + in voltage and temperature. */ +#endif + +#if !defined (LSI_VALUE) +#define LSI_VALUE ((uint32_t)37000) /*!< Value of the Internal Low Speed oscillator in Hz + The real value may vary depending on the variations + in voltage and temperature. */ +#endif + +#if !defined (LSE_VALUE) +#define LSE_VALUE ((uint32_t)32768) /*!< Value of the External Low Speed oscillator in Hz */ +#endif + +/** + * @brief STM32L1xx Standard Peripheral Library version number V1.1.1 + */ +#define __STM32L1XX_STDPERIPH_VERSION_MAIN (0x01) /*!< [31:24] main version */ +#define __STM32L1XX_STDPERIPH_VERSION_SUB1 (0x01) /*!< [23:16] sub1 version */ +#define __STM32L1XX_STDPERIPH_VERSION_SUB2 (0x01) /*!< [15:8] sub2 version */ +#define __STM32L1XX_STDPERIPH_VERSION_RC (0x00) /*!< [7:0] release candidate */ +#define __STM32L1XX_STDPERIPH_VERSION ( (__STM32L1XX_STDPERIPH_VERSION_MAIN << 24)\ + |(__STM32L1XX_STDPERIPH_VERSION_SUB1 << 16)\ + |(__STM32L1XX_STDPERIPH_VERSION_SUB2 << 8)\ + |(__STM32L1XX_STDPERIPH_VERSION_RC)) + +/** + * @} + */ + +/** @addtogroup Configuration_section_for_CMSIS + * @{ + */ + +/** + * @brief STM32L1xx Interrupt Number Definition, according to the selected device + * in @ref Library_configuration_section + */ +#define __CM3_REV 0x200 /*!< Cortex-M3 Revision r2p0 */ +#define __MPU_PRESENT 1 /*!< STM32L provides MPU */ +#define __NVIC_PRIO_BITS 4 /*!< STM32 uses 4 Bits for the Priority Levels */ +#define __Vendor_SysTickConfig 0 /*!< Set to 1 if different SysTick Config is used */ + +/*!< Interrupt Number Definition */ +typedef enum IRQn +{ +/****** Cortex-M3 Processor Exceptions Numbers ******************************************************/ + NonMaskableInt_IRQn = -14, /*!< 2 Non Maskable Interrupt */ + MemoryManagement_IRQn = -12, /*!< 4 Cortex-M3 Memory Management Interrupt */ + BusFault_IRQn = -11, /*!< 5 Cortex-M3 Bus Fault Interrupt */ + UsageFault_IRQn = -10, /*!< 6 Cortex-M3 Usage Fault Interrupt */ + SVC_IRQn = -5, /*!< 11 Cortex-M3 SV Call Interrupt */ + DebugMonitor_IRQn = -4, /*!< 12 Cortex-M3 Debug Monitor Interrupt */ + PendSV_IRQn = -2, /*!< 14 Cortex-M3 Pend SV Interrupt */ + SysTick_IRQn = -1, /*!< 15 Cortex-M3 System Tick Interrupt */ + +/****** STM32L specific Interrupt Numbers ***********************************************************/ + WWDG_IRQn = 0, /*!< Window WatchDog Interrupt */ + PVD_IRQn = 1, /*!< PVD through EXTI Line detection Interrupt */ + TAMPER_STAMP_IRQn = 2, /*!< Tamper and Time Stamp through EXTI Line Interrupts */ + RTC_WKUP_IRQn = 3, /*!< RTC Wakeup Timer through EXTI Line Interrupt */ + FLASH_IRQn = 4, /*!< FLASH global Interrupt */ + RCC_IRQn = 5, /*!< RCC global Interrupt */ + EXTI0_IRQn = 6, /*!< EXTI Line0 Interrupt */ + EXTI1_IRQn = 7, /*!< EXTI Line1 Interrupt */ + EXTI2_IRQn = 8, /*!< EXTI Line2 Interrupt */ + EXTI3_IRQn = 9, /*!< EXTI Line3 Interrupt */ + EXTI4_IRQn = 10, /*!< EXTI Line4 Interrupt */ + DMA1_Channel1_IRQn = 11, /*!< DMA1 Channel 1 global Interrupt */ + DMA1_Channel2_IRQn = 12, /*!< DMA1 Channel 2 global Interrupt */ + DMA1_Channel3_IRQn = 13, /*!< DMA1 Channel 3 global Interrupt */ + DMA1_Channel4_IRQn = 14, /*!< DMA1 Channel 4 global Interrupt */ + DMA1_Channel5_IRQn = 15, /*!< DMA1 Channel 5 global Interrupt */ + DMA1_Channel6_IRQn = 16, /*!< DMA1 Channel 6 global Interrupt */ + DMA1_Channel7_IRQn = 17, /*!< DMA1 Channel 7 global Interrupt */ + ADC1_IRQn = 18, /*!< ADC1 global Interrupt */ + USB_HP_IRQn = 19, /*!< USB High Priority Interrupt */ + USB_LP_IRQn = 20, /*!< USB Low Priority Interrupt */ + DAC_IRQn = 21, /*!< DAC Interrupt */ + COMP_IRQn = 22, /*!< Comparator through EXTI Line Interrupt */ + EXTI9_5_IRQn = 23, /*!< External Line[9:5] Interrupts */ + LCD_IRQn = 24, /*!< LCD Interrupt */ + TIM9_IRQn = 25, /*!< TIM9 global Interrupt */ + TIM10_IRQn = 26, /*!< TIM10 global Interrupt */ + TIM11_IRQn = 27, /*!< TIM11 global Interrupt */ + TIM2_IRQn = 28, /*!< TIM2 global Interrupt */ + TIM3_IRQn = 29, /*!< TIM3 global Interrupt */ + TIM4_IRQn = 30, /*!< TIM4 global Interrupt */ + I2C1_EV_IRQn = 31, /*!< I2C1 Event Interrupt */ + I2C1_ER_IRQn = 32, /*!< I2C1 Error Interrupt */ + I2C2_EV_IRQn = 33, /*!< I2C2 Event Interrupt */ + I2C2_ER_IRQn = 34, /*!< I2C2 Error Interrupt */ + SPI1_IRQn = 35, /*!< SPI1 global Interrupt */ + SPI2_IRQn = 36, /*!< SPI2 global Interrupt */ + USART1_IRQn = 37, /*!< USART1 global Interrupt */ + USART2_IRQn = 38, /*!< USART2 global Interrupt */ + USART3_IRQn = 39, /*!< USART3 global Interrupt */ + EXTI15_10_IRQn = 40, /*!< External Line[15:10] Interrupts */ + RTC_Alarm_IRQn = 41, /*!< RTC Alarm through EXTI Line Interrupt */ + USB_FS_WKUP_IRQn = 42, /*!< USB FS WakeUp from suspend through EXTI Line Interrupt */ + TIM6_IRQn = 43, /*!< TIM6 global Interrupt */ +#ifdef STM32L1XX_MD + TIM7_IRQn = 44 /*!< TIM7 global Interrupt */ +#endif + +#ifdef STM32L1XX_MDP + TIM7_IRQn = 44, /*!< TIM7 global Interrupt */ + TIM5_IRQn = 46, /*!< TIM5 global Interrupt */ + SPI3_IRQn = 47, /*!< SPI3 global Interrupt */ + DMA2_Channel1_IRQn = 50, /*!< DMA2 Channel 1 global Interrupt */ + DMA2_Channel2_IRQn = 51, /*!< DMA2 Channel 2 global Interrupt */ + DMA2_Channel3_IRQn = 52, /*!< DMA2 Channel 3 global Interrupt */ + DMA2_Channel4_IRQn = 53, /*!< DMA2 Channel 4 global Interrupt */ + DMA2_Channel5_IRQn = 54, /*!< DMA2 Channel 5 global Interrupt */ + AES_IRQn = 55, /*!< AES global Interrupt */ + COMP_ACQ_IRQn = 56 /*!< Comparator Channel Acquisition global Interrupt */ +#endif + +#ifdef STM32L1XX_HD + TIM7_IRQn = 44, /*!< TIM7 global Interrupt */ + SDIO_IRQn = 45, /*!< SDIO global Interrupt */ + TIM5_IRQn = 46, /*!< TIM5 global Interrupt */ + SPI3_IRQn = 47, /*!< SPI3 global Interrupt */ + UART4_IRQn = 48, /*!< UART4 global Interrupt */ + UART5_IRQn = 49, /*!< UART5 global Interrupt */ + DMA2_Channel1_IRQn = 50, /*!< DMA2 Channel 1 global Interrupt */ + DMA2_Channel2_IRQn = 51, /*!< DMA2 Channel 2 global Interrupt */ + DMA2_Channel3_IRQn = 52, /*!< DMA2 Channel 3 global Interrupt */ + DMA2_Channel4_IRQn = 53, /*!< DMA2 Channel 4 global Interrupt */ + DMA2_Channel5_IRQn = 54, /*!< DMA2 Channel 5 global Interrupt */ + AES_IRQn = 55, /*!< AES global Interrupt */ + COMP_ACQ_IRQn = 56 /*!< Comparator Channel Acquisition global Interrupt */ +#endif +} IRQn_Type; + +/** + * @} + */ + +#include "core_cm3.h" +#include "system_stm32l1xx.h" +#include + +/** @addtogroup Exported_types + * @{ + */ + +typedef enum {RESET = 0, SET = !RESET} FlagStatus, ITStatus; + +typedef enum {DISABLE = 0, ENABLE = !DISABLE} FunctionalState; +#define IS_FUNCTIONAL_STATE(STATE) (((STATE) == DISABLE) || ((STATE) == ENABLE)) + +typedef enum {ERROR = 0, SUCCESS = !ERROR} ErrorStatus; + +/** + * @brief __RAM_FUNC definition + */ +#if defined ( __CC_ARM ) +/* ARM Compiler + ------------ + RAM functions are defined using the toolchain options. + Functions that are executed in RAM should reside in a separate source + module. Using the 'Options for File' dialog you can simply change the + 'Code / Const' area of a module to a memory space in physical RAM. + Available memory areas are declared in the 'Target' tab of the + 'Options for Target' dialog. +*/ + #define __RAM_FUNC FLASH_Status + +#elif defined ( __ICCARM__ ) +/* ICCARM Compiler + --------------- + RAM functions are defined using a specific toolchain keyword "__ramfunc". +*/ + #define __RAM_FUNC __ramfunc FLASH_Status + +#elif defined ( __GNUC__ ) +/* GNU Compiler + ------------ + RAM functions are defined using a specific toolchain attribute + "__attribute__((section(".data")))". +*/ + #define __RAM_FUNC FLASH_Status __attribute__((section(".data"))) + +#elif defined ( __TASKING__ ) +/* TASKING Compiler + ---------------- + RAM functions are defined using a specific toolchain pragma. This pragma is + defined in the stm32l1xx_flash_ramfunc.c +*/ + #define __RAM_FUNC FLASH_Status + +#endif + +/** + * @} + */ + +/** @addtogroup Peripheral_registers_structures + * @{ + */ + +/** + * @brief Analog to Digital Converter + */ + +typedef struct +{ + __IO uint32_t SR; /*!< ADC status register, Address offset: 0x00 */ + __IO uint32_t CR1; /*!< ADC control register 1, Address offset: 0x04 */ + __IO uint32_t CR2; /*!< ADC control register 2, Address offset: 0x08 */ + __IO uint32_t SMPR1; /*!< ADC sample time register 1, Address offset: 0x0C */ + __IO uint32_t SMPR2; /*!< ADC sample time register 2, Address offset: 0x10 */ + __IO uint32_t SMPR3; /*!< ADC sample time register 3, Address offset: 0x14 */ + __IO uint32_t JOFR1; /*!< ADC injected channel data offset register 1, Address offset: 0x18 */ + __IO uint32_t JOFR2; /*!< ADC injected channel data offset register 2, Address offset: 0x1C */ + __IO uint32_t JOFR3; /*!< ADC injected channel data offset register 3, Address offset: 0x20 */ + __IO uint32_t JOFR4; /*!< ADC injected channel data offset register 4, Address offset: 0x24 */ + __IO uint32_t HTR; /*!< ADC watchdog higher threshold register, Address offset: 0x28 */ + __IO uint32_t LTR; /*!< ADC watchdog lower threshold register, Address offset: 0x2C */ + __IO uint32_t SQR1; /*!< ADC regular sequence register 1, Address offset: 0x30 */ + __IO uint32_t SQR2; /*!< ADC regular sequence register 2, Address offset: 0x34 */ + __IO uint32_t SQR3; /*!< ADC regular sequence register 3, Address offset: 0x38 */ + __IO uint32_t SQR4; /*!< ADC regular sequence register 4, Address offset: 0x3C */ + __IO uint32_t SQR5; /*!< ADC regular sequence register 5, Address offset: 0x40 */ + __IO uint32_t JSQR; /*!< ADC injected sequence register, Address offset: 0x44 */ + __IO uint32_t JDR1; /*!< ADC injected data register 1, Address offset: 0x48 */ + __IO uint32_t JDR2; /*!< ADC injected data register 2, Address offset: 0x4C */ + __IO uint32_t JDR3; /*!< ADC injected data register 3, Address offset: 0x50 */ + __IO uint32_t JDR4; /*!< ADC injected data register 4, Address offset: 0x54 */ + __IO uint32_t DR; /*!< ADC regular data register, Address offset: 0x58 */ + __IO uint32_t SMPR0; /*!< ADC sample time register 0, Address offset: 0x5C */ +} ADC_TypeDef; + +typedef struct +{ + __IO uint32_t CSR; /*!< ADC common status register, Address offset: ADC1 base address + 0x300 */ + __IO uint32_t CCR; /*!< ADC common control register, Address offset: ADC1 base address + 0x304 */ +} ADC_Common_TypeDef; + + +/** + * @brief AES hardware accelerator + */ + +typedef struct +{ + __IO uint32_t CR; /*!< AES control register, Address offset: 0x00 */ + __IO uint32_t SR; /*!< AES status register, Address offset: 0x04 */ + __IO uint32_t DINR; /*!< AES data input register, Address offset: 0x08 */ + __IO uint32_t DOUTR; /*!< AES data output register, Address offset: 0x0C */ + __IO uint32_t KEYR0; /*!< AES key register 0, Address offset: 0x10 */ + __IO uint32_t KEYR1; /*!< AES key register 1, Address offset: 0x14 */ + __IO uint32_t KEYR2; /*!< AES key register 2, Address offset: 0x18 */ + __IO uint32_t KEYR3; /*!< AES key register 3, Address offset: 0x1C */ + __IO uint32_t IVR0; /*!< AES initialization vector register 0, Address offset: 0x20 */ + __IO uint32_t IVR1; /*!< AES initialization vector register 1, Address offset: 0x24 */ + __IO uint32_t IVR2; /*!< AES initialization vector register 2, Address offset: 0x28 */ + __IO uint32_t IVR3; /*!< AES initialization vector register 3, Address offset: 0x2C */ +} AES_TypeDef; + +/** + * @brief Comparator + */ + +typedef struct +{ + __IO uint32_t CSR; /*!< COMP comparator control and status register, Address offset: 0x00 */ +} COMP_TypeDef; + +/** + * @brief CRC calculation unit + */ + +typedef struct +{ + __IO uint32_t DR; /*!< CRC Data register, Address offset: 0x00 */ + __IO uint8_t IDR; /*!< CRC Independent data register, Address offset: 0x04 */ + uint8_t RESERVED0; /*!< Reserved, 0x05 */ + uint16_t RESERVED1; /*!< Reserved, 0x06 */ + __IO uint32_t CR; /*!< CRC Control register, Address offset: 0x08 */ +} CRC_TypeDef; + +/** + * @brief Digital to Analog Converter + */ + +typedef struct +{ + __IO uint32_t CR; /*!< DAC control register, Address offset: 0x00 */ + __IO uint32_t SWTRIGR; /*!< DAC software trigger register, Address offset: 0x04 */ + __IO uint32_t DHR12R1; /*!< DAC channel1 12-bit right-aligned data holding register, Address offset: 0x08 */ + __IO uint32_t DHR12L1; /*!< DAC channel1 12-bit left aligned data holding register, Address offset: 0x0C */ + __IO uint32_t DHR8R1; /*!< DAC channel1 8-bit right aligned data holding register, Address offset: 0x10 */ + __IO uint32_t DHR12R2; /*!< DAC channel2 12-bit right aligned data holding register, Address offset: 0x14 */ + __IO uint32_t DHR12L2; /*!< DAC channel2 12-bit left aligned data holding register, Address offset: 0x18 */ + __IO uint32_t DHR8R2; /*!< DAC channel2 8-bit right-aligned data holding register, Address offset: 0x1C */ + __IO uint32_t DHR12RD; /*!< Dual DAC 12-bit right-aligned data holding register, Address offset: 0x20 */ + __IO uint32_t DHR12LD; /*!< DUAL DAC 12-bit left aligned data holding register, Address offset: 0x24 */ + __IO uint32_t DHR8RD; /*!< DUAL DAC 8-bit right aligned data holding register, Address offset: 0x28 */ + __IO uint32_t DOR1; /*!< DAC channel1 data output register, Address offset: 0x2C */ + __IO uint32_t DOR2; /*!< DAC channel2 data output register, Address offset: 0x30 */ + __IO uint32_t SR; /*!< DAC status register, Address offset: 0x34 */ +} DAC_TypeDef; + +/** + * @brief Debug MCU + */ + +typedef struct +{ + __IO uint32_t IDCODE; /*!< MCU device ID code, Address offset: 0x00 */ + __IO uint32_t CR; /*!< Debug MCU configuration register, Address offset: 0x04 */ + __IO uint32_t APB1FZ; /*!< Debug MCU APB1 freeze register, Address offset: 0x08 */ + __IO uint32_t APB2FZ; /*!< Debug MCU APB2 freeze register, Address offset: 0x0C */ +}DBGMCU_TypeDef; + +/** + * @brief DMA Controller + */ + +typedef struct +{ + __IO uint32_t CCR; /*!< DMA channel x configuration register */ + __IO uint32_t CNDTR; /*!< DMA channel x number of data register */ + __IO uint32_t CPAR; /*!< DMA channel x peripheral address register */ + __IO uint32_t CMAR; /*!< DMA channel x memory address register */ +} DMA_Channel_TypeDef; + +typedef struct +{ + __IO uint32_t ISR; /*!< DMA interrupt status register, Address offset: 0x00 */ + __IO uint32_t IFCR; /*!< DMA interrupt flag clear register, Address offset: 0x04 */ +} DMA_TypeDef; + +/** + * @brief External Interrupt/Event Controller + */ + +typedef struct +{ + __IO uint32_t IMR; /*!< EXTI interrupt mask register, Address offset: 0x00 */ + __IO uint32_t EMR; /*!< EXTI event mask register, Address offset: 0x04 */ + __IO uint32_t RTSR; /*!< EXTI rising edge trigger selection register, Address offset: 0x08 */ + __IO uint32_t FTSR; /*!< EXTI Falling edge trigger selection register, Address offset: 0x0C */ + __IO uint32_t SWIER; /*!< EXTI software interrupt event register, Address offset: 0x10 */ + __IO uint32_t PR; /*!< EXTI pending register, Address offset: 0x14 */ +} EXTI_TypeDef; + +/** + * @brief FLASH Registers + */ + +typedef struct +{ + __IO uint32_t ACR; /*!< Access control register, Address offset: 0x00 */ + __IO uint32_t PECR; /*!< Program/erase control register, Address offset: 0x04 */ + __IO uint32_t PDKEYR; /*!< Power down key register, Address offset: 0x08 */ + __IO uint32_t PEKEYR; /*!< Program/erase key register, Address offset: 0x0c */ + __IO uint32_t PRGKEYR; /*!< Program memory key register, Address offset: 0x10 */ + __IO uint32_t OPTKEYR; /*!< Option byte key register, Address offset: 0x14 */ + __IO uint32_t SR; /*!< Status register, Address offset: 0x18 */ + __IO uint32_t OBR; /*!< Option byte register, Address offset: 0x1c */ + __IO uint32_t WRPR; /*!< Write protection register, Address offset: 0x20 */ + uint32_t RESERVED[23]; /*!< Reserved, 0x24 */ + __IO uint32_t WRPR1; /*!< Write protection register 1, Address offset: 0x28 */ + __IO uint32_t WRPR2; /*!< Write protection register 2, Address offset: 0x2C */ +} FLASH_TypeDef; + +/** + * @brief Option Bytes Registers + */ + +typedef struct +{ + __IO uint32_t RDP; /*!< Read protection register, Address offset: 0x00 */ + __IO uint32_t USER; /*!< user register, Address offset: 0x04 */ + __IO uint32_t WRP01; /*!< write protection register 0 1, Address offset: 0x08 */ + __IO uint32_t WRP23; /*!< write protection register 2 3, Address offset: 0x0C */ + __IO uint32_t WRP45; /*!< write protection register 4 5, Address offset: 0x10 */ + __IO uint32_t WRP67; /*!< write protection register 6 7, Address offset: 0x14 */ + __IO uint32_t WRP89; /*!< write protection register 8 9, Address offset: 0x18 */ + __IO uint32_t WRP1011; /*!< write protection register 10 11, Address offset: 0x1C */ +} OB_TypeDef; + +/** + * @brief Operational Amplifier (OPAMP) + */ + +typedef struct +{ + __IO uint32_t CSR; /*!< OPAMP control/status register, Address offset: 0x00 */ + __IO uint32_t OTR; /*!< OPAMP offset trimming register for normal mode, Address offset: 0x04 */ + __IO uint32_t LPOTR; /*!< OPAMP offset trimming register for low power mode, Address offset: 0x08 */ +} OPAMP_TypeDef; + +/** + * @brief Flexible Static Memory Controller + */ + +typedef struct +{ + __IO uint32_t BTCR[8]; /*!< NOR/PSRAM chip-select control register(BCR) and chip-select timing register(BTR), Address offset: 0x00-1C */ +} FSMC_Bank1_TypeDef; + +/** + * @brief Flexible Static Memory Controller Bank1E + */ + +typedef struct +{ + __IO uint32_t BWTR[7]; /*!< NOR/PSRAM write timing registers, Address offset: 0x104-0x11C */ +} FSMC_Bank1E_TypeDef; + +/** + * @brief General Purpose IO + */ + +typedef struct +{ + __IO uint32_t MODER; /*!< GPIO port mode register, Address offset: 0x00 */ + __IO uint16_t OTYPER; /*!< GPIO port output type register, Address offset: 0x04 */ + uint16_t RESERVED0; /*!< Reserved, 0x06 */ + __IO uint32_t OSPEEDR; /*!< GPIO port output speed register, Address offset: 0x08 */ + __IO uint32_t PUPDR; /*!< GPIO port pull-up/pull-down register, Address offset: 0x0C */ + __IO uint16_t IDR; /*!< GPIO port input data register, Address offset: 0x10 */ + uint16_t RESERVED1; /*!< Reserved, 0x12 */ + __IO uint16_t ODR; /*!< GPIO port output data register, Address offset: 0x14 */ + uint16_t RESERVED2; /*!< Reserved, 0x16 */ + __IO uint16_t BSRRL; /*!< GPIO port bit set/reset low registerBSRR, Address offset: 0x18 */ + __IO uint16_t BSRRH; /*!< GPIO port bit set/reset high registerBSRR, Address offset: 0x1A */ + __IO uint32_t LCKR; /*!< GPIO port configuration lock register, Address offset: 0x1C */ + __IO uint32_t AFR[2]; /*!< GPIO alternate function low register, Address offset: 0x20-0x24 */ + __IO uint16_t BRR; /*!< GPIO bit reset register, Address offset: 0x28 */ + uint16_t RESERVED3; /*!< Reserved, 0x2A */ +} GPIO_TypeDef; + +/** + * @brief SysTem Configuration + */ + +typedef struct +{ + __IO uint32_t MEMRMP; /*!< SYSCFG memory remap register, Address offset: 0x00 */ + __IO uint32_t PMC; /*!< SYSCFG peripheral mode configuration register, Address offset: 0x04 */ + __IO uint32_t EXTICR[4]; /*!< SYSCFG external interrupt configuration registers, Address offset: 0x08-0x14 */ +} SYSCFG_TypeDef; + +/** + * @brief Inter-integrated Circuit Interface + */ + +typedef struct +{ + __IO uint16_t CR1; /*!< I2C Control register 1, Address offset: 0x00 */ + uint16_t RESERVED0; /*!< Reserved, 0x02 */ + __IO uint16_t CR2; /*!< I2C Control register 2, Address offset: 0x04 */ + uint16_t RESERVED1; /*!< Reserved, 0x06 */ + __IO uint16_t OAR1; /*!< I2C Own address register 1, Address offset: 0x08 */ + uint16_t RESERVED2; /*!< Reserved, 0x0A */ + __IO uint16_t OAR2; /*!< I2C Own address register 2, Address offset: 0x0C */ + uint16_t RESERVED3; /*!< Reserved, 0x0E */ + __IO uint16_t DR; /*!< I2C Data register, Address offset: 0x10 */ + uint16_t RESERVED4; /*!< Reserved, 0x12 */ + __IO uint16_t SR1; /*!< I2C Status register 1, Address offset: 0x14 */ + uint16_t RESERVED5; /*!< Reserved, 0x16 */ + __IO uint16_t SR2; /*!< I2C Status register 2, Address offset: 0x18 */ + uint16_t RESERVED6; /*!< Reserved, 0x1A */ + __IO uint16_t CCR; /*!< I2C Clock control register, Address offset: 0x1C */ + uint16_t RESERVED7; /*!< Reserved, 0x1E */ + __IO uint16_t TRISE; /*!< I2C TRISE register, Address offset: 0x20 */ + uint16_t RESERVED8; /*!< Reserved, 0x22 */ +} I2C_TypeDef; + +/** + * @brief Independent WATCHDOG + */ + +typedef struct +{ + __IO uint32_t KR; /*!< Key register, Address offset: 0x00 */ + __IO uint32_t PR; /*!< Prescaler register, Address offset: 0x04 */ + __IO uint32_t RLR; /*!< Reload register, Address offset: 0x08 */ + __IO uint32_t SR; /*!< Status register, Address offset: 0x0C */ +} IWDG_TypeDef; + + +/** + * @brief LCD + */ + +typedef struct +{ + __IO uint32_t CR; /*!< LCD control register, Address offset: 0x00 */ + __IO uint32_t FCR; /*!< LCD frame control register, Address offset: 0x04 */ + __IO uint32_t SR; /*!< LCD status register, Address offset: 0x08 */ + __IO uint32_t CLR; /*!< LCD clear register, Address offset: 0x0C */ + uint32_t RESERVED; /*!< Reserved, Address offset: 0x10 */ + __IO uint32_t RAM[16]; /*!< LCD display memory, Address offset: 0x14-0x50 */ +} LCD_TypeDef; + +/** + * @brief Power Control + */ + +typedef struct +{ + __IO uint32_t CR; /*!< PWR power control register, Address offset: 0x00 */ + __IO uint32_t CSR; /*!< PWR power control/status register, Address offset: 0x04 */ +} PWR_TypeDef; + +/** + * @brief Reset and Clock Control + */ + +typedef struct +{ + __IO uint32_t CR; /*!< RCC clock control register, Address offset: 0x00 */ + __IO uint32_t ICSCR; /*!< RCC Internal clock sources calibration register, Address offset: 0x04 */ + __IO uint32_t CFGR; /*!< RCC Clock configuration register, Address offset: 0x08 */ + __IO uint32_t CIR; /*!< RCC Clock interrupt register, Address offset: 0x0C */ + __IO uint32_t AHBRSTR; /*!< RCC AHB peripheral reset register, Address offset: 0x10 */ + __IO uint32_t APB2RSTR; /*!< RCC APB2 peripheral reset register, Address offset: 0x14 */ + __IO uint32_t APB1RSTR; /*!< RCC APB1 peripheral reset register, Address offset: 0x18 */ + __IO uint32_t AHBENR; /*!< RCC AHB peripheral clock enable register, Address offset: 0x1C */ + __IO uint32_t APB2ENR; /*!< RCC APB2 peripheral clock enable register, Address offset: 0x20 */ + __IO uint32_t APB1ENR; /*!< RCC APB1 peripheral clock enable register, Address offset: 0x24 */ + __IO uint32_t AHBLPENR; /*!< RCC AHB peripheral clock enable in low power mode register, Address offset: 0x28 */ + __IO uint32_t APB2LPENR; /*!< RCC APB2 peripheral clock enable in low power mode register, Address offset: 0x2C */ + __IO uint32_t APB1LPENR; /*!< RCC APB1 peripheral clock enable in low power mode register, Address offset: 0x30 */ + __IO uint32_t CSR; /*!< RCC Control/status register, Address offset: 0x34 */ +} RCC_TypeDef; + +/** + * @brief Routing Interface + */ + +typedef struct +{ + __IO uint32_t ICR; /*!< RI input capture register, Address offset: 0x00 */ + __IO uint32_t ASCR1; /*!< RI analog switches control register, Address offset: 0x04 */ + __IO uint32_t ASCR2; /*!< RI analog switch control register 2, Address offset: 0x08 */ + __IO uint32_t HYSCR1; /*!< RI hysteresis control register, Address offset: 0x0C */ + __IO uint32_t HYSCR2; /*!< RI Hysteresis control register, Address offset: 0x10 */ + __IO uint32_t HYSCR3; /*!< RI Hysteresis control register, Address offset: 0x14 */ + __IO uint32_t HYSCR4; /*!< RI Hysteresis control register, Address offset: 0x18 */ +} RI_TypeDef; + +/** + * @brief Real-Time Clock + */ + +typedef struct +{ + __IO uint32_t TR; /*!< RTC time register, Address offset: 0x00 */ + __IO uint32_t DR; /*!< RTC date register, Address offset: 0x04 */ + __IO uint32_t CR; /*!< RTC control register, Address offset: 0x08 */ + __IO uint32_t ISR; /*!< RTC initialization and status register, Address offset: 0x0C */ + __IO uint32_t PRER; /*!< RTC prescaler register, Address offset: 0x10 */ + __IO uint32_t WUTR; /*!< RTC wakeup timer register, Address offset: 0x14 */ + __IO uint32_t CALIBR; /*!< RTC calibration register, Address offset: 0x18 */ + __IO uint32_t ALRMAR; /*!< RTC alarm A register, Address offset: 0x1C */ + __IO uint32_t ALRMBR; /*!< RTC alarm B register, Address offset: 0x20 */ + __IO uint32_t WPR; /*!< RTC write protection register, Address offset: 0x24 */ + __IO uint32_t SSR; /*!< RTC sub second register, Address offset: 0x28 */ + __IO uint32_t SHIFTR; /*!< RTC shift control register, Address offset: 0x2C */ + __IO uint32_t TSTR; /*!< RTC time stamp time register, Address offset: 0x30 */ + __IO uint32_t TSDR; /*!< RTC time stamp date register, Address offset: 0x34 */ + __IO uint32_t TSSSR; /*!< RTC time-stamp sub second register, Address offset: 0x38 */ + __IO uint32_t CALR; /*!< RRTC calibration register, Address offset: 0x3C */ + __IO uint32_t TAFCR; /*!< RTC tamper and alternate function configuration register, Address offset: 0x40 */ + __IO uint32_t ALRMASSR; /*!< RTC alarm A sub second register, Address offset: 0x44 */ + __IO uint32_t ALRMBSSR; /*!< RTC alarm B sub second register, Address offset: 0x48 */ + uint32_t RESERVED7; /*!< Reserved, 0x4C */ + __IO uint32_t BKP0R; /*!< RTC backup register 0, Address offset: 0x50 */ + __IO uint32_t BKP1R; /*!< RTC backup register 1, Address offset: 0x54 */ + __IO uint32_t BKP2R; /*!< RTC backup register 2, Address offset: 0x58 */ + __IO uint32_t BKP3R; /*!< RTC backup register 3, Address offset: 0x5C */ + __IO uint32_t BKP4R; /*!< RTC backup register 4, Address offset: 0x60 */ + __IO uint32_t BKP5R; /*!< RTC backup register 5, Address offset: 0x64 */ + __IO uint32_t BKP6R; /*!< RTC backup register 6, Address offset: 0x68 */ + __IO uint32_t BKP7R; /*!< RTC backup register 7, Address offset: 0x6C */ + __IO uint32_t BKP8R; /*!< RTC backup register 8, Address offset: 0x70 */ + __IO uint32_t BKP9R; /*!< RTC backup register 9, Address offset: 0x74 */ + __IO uint32_t BKP10R; /*!< RTC backup register 10, Address offset: 0x78 */ + __IO uint32_t BKP11R; /*!< RTC backup register 11, Address offset: 0x7C */ + __IO uint32_t BKP12R; /*!< RTC backup register 12, Address offset: 0x80 */ + __IO uint32_t BKP13R; /*!< RTC backup register 13, Address offset: 0x84 */ + __IO uint32_t BKP14R; /*!< RTC backup register 14, Address offset: 0x88 */ + __IO uint32_t BKP15R; /*!< RTC backup register 15, Address offset: 0x8C */ + __IO uint32_t BKP16R; /*!< RTC backup register 16, Address offset: 0x90 */ + __IO uint32_t BKP17R; /*!< RTC backup register 17, Address offset: 0x94 */ + __IO uint32_t BKP18R; /*!< RTC backup register 18, Address offset: 0x98 */ + __IO uint32_t BKP19R; /*!< RTC backup register 19, Address offset: 0x9C */ + __IO uint32_t BKP20R; /*!< RTC backup register 20, Address offset: 0xA0 */ + __IO uint32_t BKP21R; /*!< RTC backup register 21, Address offset: 0xA4 */ + __IO uint32_t BKP22R; /*!< RTC backup register 22, Address offset: 0xA8 */ + __IO uint32_t BKP23R; /*!< RTC backup register 23, Address offset: 0xAC */ + __IO uint32_t BKP24R; /*!< RTC backup register 24, Address offset: 0xB0 */ + __IO uint32_t BKP25R; /*!< RTC backup register 25, Address offset: 0xB4 */ + __IO uint32_t BKP26R; /*!< RTC backup register 26, Address offset: 0xB8 */ + __IO uint32_t BKP27R; /*!< RTC backup register 27, Address offset: 0xBC */ + __IO uint32_t BKP28R; /*!< RTC backup register 28, Address offset: 0xC0 */ + __IO uint32_t BKP29R; /*!< RTC backup register 29, Address offset: 0xC4 */ + __IO uint32_t BKP30R; /*!< RTC backup register 30, Address offset: 0xC8 */ + __IO uint32_t BKP31R; /*!< RTC backup register 31, Address offset: 0xCC */ +} RTC_TypeDef; + +/** + * @brief SD host Interface + */ + +typedef struct +{ + __IO uint32_t POWER; /*!< SDIO power control register, Address offset: 0x00 */ + __IO uint32_t CLKCR; /*!< SDI clock control register, Address offset: 0x04 */ + __IO uint32_t ARG; /*!< SDIO argument register, Address offset: 0x08 */ + __IO uint32_t CMD; /*!< SDIO command register, Address offset: 0x0C */ + __I uint32_t RESPCMD; /*!< SDIO command response register, Address offset: 0x10 */ + __I uint32_t RESP1; /*!< SDIO response 1 register, Address offset: 0x14 */ + __I uint32_t RESP2; /*!< SDIO response 2 register, Address offset: 0x18 */ + __I uint32_t RESP3; /*!< SDIO response 3 register, Address offset: 0x1C */ + __I uint32_t RESP4; /*!< SDIO response 4 register, Address offset: 0x20 */ + __IO uint32_t DTIMER; /*!< SDIO data timer register, Address offset: 0x24 */ + __IO uint32_t DLEN; /*!< SDIO data length register, Address offset: 0x28 */ + __IO uint32_t DCTRL; /*!< SDIO data control register, Address offset: 0x2C */ + __I uint32_t DCOUNT; /*!< SDIO data counter register, Address offset: 0x30 */ + __I uint32_t STA; /*!< SDIO status register, Address offset: 0x34 */ + __IO uint32_t ICR; /*!< SDIO interrupt clear register, Address offset: 0x38 */ + __IO uint32_t MASK; /*!< SDIO mask register, Address offset: 0x3C */ + uint32_t RESERVED0[2]; /*!< Reserved, 0x40-0x44 */ + __I uint32_t FIFOCNT; /*!< SDIO FIFO counter register, Address offset: 0x48 */ + uint32_t RESERVED1[13]; /*!< Reserved, 0x4C-0x7C */ + __IO uint32_t FIFO; /*!< SDIO data FIFO register, Address offset: 0x80 */ +} SDIO_TypeDef; + +/** + * @brief Serial Peripheral Interface + */ + +typedef struct +{ + __IO uint16_t CR1; /*!< SPI control register 1 (not used in I2S mode), Address offset: 0x00 */ + uint16_t RESERVED0; /*!< Reserved, 0x02 */ + __IO uint16_t CR2; /*!< SPI control register 2, Address offset: 0x04 */ + uint16_t RESERVED1; /*!< Reserved, 0x06 */ + __IO uint16_t SR; /*!< SPI status register, Address offset: 0x08 */ + uint16_t RESERVED2; /*!< Reserved, 0x0A */ + __IO uint16_t DR; /*!< SPI data register, Address offset: 0x0C */ + uint16_t RESERVED3; /*!< Reserved, 0x0E */ + __IO uint16_t CRCPR; /*!< SPI CRC polynomial register (not used in I2S mode), Address offset: 0x10 */ + uint16_t RESERVED4; /*!< Reserved, 0x12 */ + __IO uint16_t RXCRCR; /*!< SPI RX CRC register (not used in I2S mode), Address offset: 0x14 */ + uint16_t RESERVED5; /*!< Reserved, 0x16 */ + __IO uint16_t TXCRCR; /*!< SPI TX CRC register (not used in I2S mode), Address offset: 0x18 */ + uint16_t RESERVED6; /*!< Reserved, 0x1A */ + __IO uint16_t I2SCFGR; /*!< SPI_I2S configuration register, Address offset: 0x1C */ + uint16_t RESERVED7; /*!< Reserved, 0x1E */ + __IO uint16_t I2SPR; /*!< SPI_I2S prescaler register, Address offset: 0x20 */ + uint16_t RESERVED8; /*!< Reserved, 0x22 */ +} SPI_TypeDef; + +/** + * @brief TIM + */ + +typedef struct +{ + __IO uint16_t CR1; /*!< TIM control register 1, Address offset: 0x00 */ + uint16_t RESERVED0; /*!< Reserved, 0x02 */ + __IO uint16_t CR2; /*!< TIM control register 2, Address offset: 0x04 */ + uint16_t RESERVED1; /*!< Reserved, 0x06 */ + __IO uint16_t SMCR; /*!< TIM slave mode control register, Address offset: 0x08 */ + uint16_t RESERVED2; /*!< Reserved, 0x0A */ + __IO uint16_t DIER; /*!< TIM DMA/interrupt enable register, Address offset: 0x0C */ + uint16_t RESERVED3; /*!< Reserved, 0x0E */ + __IO uint16_t SR; /*!< TIM status register, Address offset: 0x10 */ + uint16_t RESERVED4; /*!< Reserved, 0x12 */ + __IO uint16_t EGR; /*!< TIM event generation register, Address offset: 0x14 */ + uint16_t RESERVED5; /*!< Reserved, 0x16 */ + __IO uint16_t CCMR1; /*!< TIM capture/compare mode register 1, Address offset: 0x18 */ + uint16_t RESERVED6; /*!< Reserved, 0x1A */ + __IO uint16_t CCMR2; /*!< TIM capture/compare mode register 2, Address offset: 0x1C */ + uint16_t RESERVED7; /*!< Reserved, 0x1E */ + __IO uint16_t CCER; /*!< TIM capture/compare enable register, Address offset: 0x20 */ + uint16_t RESERVED8; /*!< Reserved, 0x22 */ + __IO uint32_t CNT; /*!< TIM counter register, Address offset: 0x24 */ + __IO uint16_t PSC; /*!< TIM prescaler, Address offset: 0x28 */ + uint16_t RESERVED10; /*!< Reserved, 0x2A */ + __IO uint32_t ARR; /*!< TIM auto-reload register, Address offset: 0x2C */ + uint32_t RESERVED12; /*!< Reserved, 0x30 */ + __IO uint32_t CCR1; /*!< TIM capture/compare register 1, Address offset: 0x34 */ + __IO uint32_t CCR2; /*!< TIM capture/compare register 2, Address offset: 0x38 */ + __IO uint32_t CCR3; /*!< TIM capture/compare register 3, Address offset: 0x3C */ + __IO uint32_t CCR4; /*!< TIM capture/compare register 4, Address offset: 0x40 */ + uint32_t RESERVED17; /*!< Reserved, 0x44 */ + __IO uint16_t DCR; /*!< TIM DMA control register, Address offset: 0x48 */ + uint16_t RESERVED18; /*!< Reserved, 0x4A */ + __IO uint16_t DMAR; /*!< TIM DMA address for full transfer, Address offset: 0x4C */ + uint16_t RESERVED19; /*!< Reserved, 0x4E */ + __IO uint16_t OR; /*!< TIM option register, Address offset: 0x50 */ + uint16_t RESERVED20; /*!< Reserved, 0x52 */ +} TIM_TypeDef; + +/** + * @brief Universal Synchronous Asynchronous Receiver Transmitter + */ + +typedef struct +{ + __IO uint16_t SR; /*!< USART Status register, Address offset: 0x00 */ + uint16_t RESERVED0; /*!< Reserved, 0x02 */ + __IO uint16_t DR; /*!< USART Data register, Address offset: 0x04 */ + uint16_t RESERVED1; /*!< Reserved, 0x06 */ + __IO uint16_t BRR; /*!< USART Baud rate register, Address offset: 0x08 */ + uint16_t RESERVED2; /*!< Reserved, 0x0A */ + __IO uint16_t CR1; /*!< USART Control register 1, Address offset: 0x0C */ + uint16_t RESERVED3; /*!< Reserved, 0x0E */ + __IO uint16_t CR2; /*!< USART Control register 2, Address offset: 0x10 */ + uint16_t RESERVED4; /*!< Reserved, 0x12 */ + __IO uint16_t CR3; /*!< USART Control register 3, Address offset: 0x14 */ + uint16_t RESERVED5; /*!< Reserved, 0x16 */ + __IO uint16_t GTPR; /*!< USART Guard time and prescaler register, Address offset: 0x18 */ + uint16_t RESERVED6; /*!< Reserved, 0x1A */ +} USART_TypeDef; + +/** + * @brief Window WATCHDOG + */ + +typedef struct +{ + __IO uint32_t CR; /*!< WWDG Control register, Address offset: 0x00 */ + __IO uint32_t CFR; /*!< WWDG Configuration register, Address offset: 0x04 */ + __IO uint32_t SR; /*!< WWDG Status register, Address offset: 0x08 */ +} WWDG_TypeDef; + +/** + * @} + */ + +/** @addtogroup Peripheral_memory_map + * @{ + */ + +#define FLASH_BASE ((uint32_t)0x08000000) /*!< FLASH base address in the alias region */ +#define SRAM_BASE ((uint32_t)0x20000000) /*!< SRAM base address in the alias region */ +#define PERIPH_BASE ((uint32_t)0x40000000) /*!< Peripheral base address in the alias region */ + +#define SRAM_BB_BASE ((uint32_t)0x22000000) /*!< SRAM base address in the bit-band region */ +#define PERIPH_BB_BASE ((uint32_t)0x42000000) /*!< Peripheral base address in the bit-band region */ + +#define FSMC_R_BASE ((uint32_t)0xA0000000) /*!< FSMC registers base address */ + +/*!< Peripheral memory map */ +#define APB1PERIPH_BASE PERIPH_BASE +#define APB2PERIPH_BASE (PERIPH_BASE + 0x10000) +#define AHBPERIPH_BASE (PERIPH_BASE + 0x20000) + +#define TIM2_BASE (APB1PERIPH_BASE + 0x0000) +#define TIM3_BASE (APB1PERIPH_BASE + 0x0400) +#define TIM4_BASE (APB1PERIPH_BASE + 0x0800) +#define TIM5_BASE (APB1PERIPH_BASE + 0x0C00) +#define TIM6_BASE (APB1PERIPH_BASE + 0x1000) +#define TIM7_BASE (APB1PERIPH_BASE + 0x1400) +#define LCD_BASE (APB1PERIPH_BASE + 0x2400) +#define RTC_BASE (APB1PERIPH_BASE + 0x2800) +#define WWDG_BASE (APB1PERIPH_BASE + 0x2C00) +#define IWDG_BASE (APB1PERIPH_BASE + 0x3000) +#define SPI2_BASE (APB1PERIPH_BASE + 0x3800) +#define SPI3_BASE (APB1PERIPH_BASE + 0x3C00) +#define USART2_BASE (APB1PERIPH_BASE + 0x4400) +#define USART3_BASE (APB1PERIPH_BASE + 0x4800) +#define UART4_BASE (APB1PERIPH_BASE + 0x4C00) +#define UART5_BASE (APB1PERIPH_BASE + 0x5000) +#define I2C1_BASE (APB1PERIPH_BASE + 0x5400) +#define I2C2_BASE (APB1PERIPH_BASE + 0x5800) +#define PWR_BASE (APB1PERIPH_BASE + 0x7000) +#define DAC_BASE (APB1PERIPH_BASE + 0x7400) +#define COMP_BASE (APB1PERIPH_BASE + 0x7C00) +#define RI_BASE (APB1PERIPH_BASE + 0x7C04) +#define OPAMP_BASE (APB1PERIPH_BASE + 0x7C5C) + +#define SYSCFG_BASE (APB2PERIPH_BASE + 0x0000) +#define EXTI_BASE (APB2PERIPH_BASE + 0x0400) +#define TIM9_BASE (APB2PERIPH_BASE + 0x0800) +#define TIM10_BASE (APB2PERIPH_BASE + 0x0C00) +#define TIM11_BASE (APB2PERIPH_BASE + 0x1000) +#define ADC1_BASE (APB2PERIPH_BASE + 0x2400) +#define ADC_BASE (APB2PERIPH_BASE + 0x2700) +#define SDIO_BASE (APB2PERIPH_BASE + 0x2C00) +#define SPI1_BASE (APB2PERIPH_BASE + 0x3000) +#define USART1_BASE (APB2PERIPH_BASE + 0x3800) + +#define GPIOA_BASE (AHBPERIPH_BASE + 0x0000) +#define GPIOB_BASE (AHBPERIPH_BASE + 0x0400) +#define GPIOC_BASE (AHBPERIPH_BASE + 0x0800) +#define GPIOD_BASE (AHBPERIPH_BASE + 0x0C00) +#define GPIOE_BASE (AHBPERIPH_BASE + 0x1000) +#define GPIOH_BASE (AHBPERIPH_BASE + 0x1400) +#define GPIOF_BASE (AHBPERIPH_BASE + 0x1800) +#define GPIOG_BASE (AHBPERIPH_BASE + 0x1C00) +#define CRC_BASE (AHBPERIPH_BASE + 0x3000) +#define RCC_BASE (AHBPERIPH_BASE + 0x3800) + + +#define FLASH_R_BASE (AHBPERIPH_BASE + 0x3C00) /*!< FLASH registers base address */ +#define OB_BASE ((uint32_t)0x1FF80000) /*!< FLASH Option Bytes base address */ + +#define DMA1_BASE (AHBPERIPH_BASE + 0x6000) +#define DMA1_Channel1_BASE (DMA1_BASE + 0x0008) +#define DMA1_Channel2_BASE (DMA1_BASE + 0x001C) +#define DMA1_Channel3_BASE (DMA1_BASE + 0x0030) +#define DMA1_Channel4_BASE (DMA1_BASE + 0x0044) +#define DMA1_Channel5_BASE (DMA1_BASE + 0x0058) +#define DMA1_Channel6_BASE (DMA1_BASE + 0x006C) +#define DMA1_Channel7_BASE (DMA1_BASE + 0x0080) + +#define DMA2_BASE (AHBPERIPH_BASE + 0x6400) +#define DMA2_Channel1_BASE (DMA2_BASE + 0x0008) +#define DMA2_Channel2_BASE (DMA2_BASE + 0x001C) +#define DMA2_Channel3_BASE (DMA2_BASE + 0x0030) +#define DMA2_Channel4_BASE (DMA2_BASE + 0x0044) +#define DMA2_Channel5_BASE (DMA2_BASE + 0x0058) + +#define AES_BASE ((uint32_t)0x50060000) + +#define FSMC_Bank1_R_BASE (FSMC_R_BASE + 0x0000) /*!< FSMC Bank1 registers base address */ +#define FSMC_Bank1E_R_BASE (FSMC_R_BASE + 0x0104) /*!< FSMC Bank1E registers base address */ + +#define DBGMCU_BASE ((uint32_t)0xE0042000) /*!< Debug MCU registers base address */ + +/** + * @} + */ + +/** @addtogroup Peripheral_declaration + * @{ + */ + +#define TIM2 ((TIM_TypeDef *) TIM2_BASE) +#define TIM3 ((TIM_TypeDef *) TIM3_BASE) +#define TIM4 ((TIM_TypeDef *) TIM4_BASE) +#define TIM5 ((TIM_TypeDef *) TIM5_BASE) +#define TIM6 ((TIM_TypeDef *) TIM6_BASE) +#define TIM7 ((TIM_TypeDef *) TIM7_BASE) +#define LCD ((LCD_TypeDef *) LCD_BASE) +#define RTC ((RTC_TypeDef *) RTC_BASE) +#define WWDG ((WWDG_TypeDef *) WWDG_BASE) +#define IWDG ((IWDG_TypeDef *) IWDG_BASE) +#define SPI2 ((SPI_TypeDef *) SPI2_BASE) +#define SPI3 ((SPI_TypeDef *) SPI3_BASE) +#define USART2 ((USART_TypeDef *) USART2_BASE) +#define USART3 ((USART_TypeDef *) USART3_BASE) +#define UART4 ((USART_TypeDef *) UART4_BASE) +#define UART5 ((USART_TypeDef *) UART5_BASE) +#define I2C1 ((I2C_TypeDef *) I2C1_BASE) +#define I2C2 ((I2C_TypeDef *) I2C2_BASE) +#define PWR ((PWR_TypeDef *) PWR_BASE) +#define DAC ((DAC_TypeDef *) DAC_BASE) +#define COMP ((COMP_TypeDef *) COMP_BASE) +#define RI ((RI_TypeDef *) RI_BASE) +#define OPAMP ((OPAMP_TypeDef *) OPAMP_BASE) +#define SYSCFG ((SYSCFG_TypeDef *) SYSCFG_BASE) +#define EXTI ((EXTI_TypeDef *) EXTI_BASE) + +#define ADC1 ((ADC_TypeDef *) ADC1_BASE) +#define ADC ((ADC_Common_TypeDef *) ADC_BASE) +#define SDIO ((SDIO_TypeDef *) SDIO_BASE) +#define TIM9 ((TIM_TypeDef *) TIM9_BASE) +#define TIM10 ((TIM_TypeDef *) TIM10_BASE) +#define TIM11 ((TIM_TypeDef *) TIM11_BASE) +#define SPI1 ((SPI_TypeDef *) SPI1_BASE) +#define USART1 ((USART_TypeDef *) USART1_BASE) +#define DMA1 ((DMA_TypeDef *) DMA1_BASE) +#define DMA1_Channel1 ((DMA_Channel_TypeDef *) DMA1_Channel1_BASE) +#define DMA1_Channel2 ((DMA_Channel_TypeDef *) DMA1_Channel2_BASE) +#define DMA1_Channel3 ((DMA_Channel_TypeDef *) DMA1_Channel3_BASE) +#define DMA1_Channel4 ((DMA_Channel_TypeDef *) DMA1_Channel4_BASE) +#define DMA1_Channel5 ((DMA_Channel_TypeDef *) DMA1_Channel5_BASE) +#define DMA1_Channel6 ((DMA_Channel_TypeDef *) DMA1_Channel6_BASE) +#define DMA1_Channel7 ((DMA_Channel_TypeDef *) DMA1_Channel7_BASE) + +#define DMA2 ((DMA_TypeDef *) DMA2_BASE) +#define DMA2_Channel1 ((DMA_Channel_TypeDef *) DMA2_Channel1_BASE) +#define DMA2_Channel2 ((DMA_Channel_TypeDef *) DMA2_Channel2_BASE) +#define DMA2_Channel3 ((DMA_Channel_TypeDef *) DMA2_Channel3_BASE) +#define DMA2_Channel4 ((DMA_Channel_TypeDef *) DMA2_Channel4_BASE) +#define DMA2_Channel5 ((DMA_Channel_TypeDef *) DMA2_Channel5_BASE) + +#define RCC ((RCC_TypeDef *) RCC_BASE) +#define CRC ((CRC_TypeDef *) CRC_BASE) + +#define GPIOA ((GPIO_TypeDef *) GPIOA_BASE) +#define GPIOB ((GPIO_TypeDef *) GPIOB_BASE) +#define GPIOC ((GPIO_TypeDef *) GPIOC_BASE) +#define GPIOD ((GPIO_TypeDef *) GPIOD_BASE) +#define GPIOE ((GPIO_TypeDef *) GPIOE_BASE) +#define GPIOH ((GPIO_TypeDef *) GPIOH_BASE) +#define GPIOF ((GPIO_TypeDef *) GPIOF_BASE) +#define GPIOG ((GPIO_TypeDef *) GPIOG_BASE) + +#define FLASH ((FLASH_TypeDef *) FLASH_R_BASE) +#define OB ((OB_TypeDef *) OB_BASE) + +#define AES ((AES_TypeDef *) AES_BASE) + +#define FSMC_Bank1 ((FSMC_Bank1_TypeDef *) FSMC_Bank1_R_BASE) +#define FSMC_Bank1E ((FSMC_Bank1E_TypeDef *) FSMC_Bank1E_R_BASE) + +#define DBGMCU ((DBGMCU_TypeDef *) DBGMCU_BASE) + +/** + * @} + */ + +/** @addtogroup Exported_constants + * @{ + */ + +/** @addtogroup Peripheral_Registers_Bits_Definition + * @{ + */ + +/******************************************************************************/ +/* Peripheral Registers Bits Definition */ +/******************************************************************************/ +/******************************************************************************/ +/* */ +/* Analog to Digital Converter (ADC) */ +/* */ +/******************************************************************************/ + +/******************** Bit definition for ADC_SR register ********************/ +#define ADC_SR_AWD ((uint32_t)0x00000001) /*!< Analog watchdog flag */ +#define ADC_SR_EOC ((uint32_t)0x00000002) /*!< End of conversion */ +#define ADC_SR_JEOC ((uint32_t)0x00000004) /*!< Injected channel end of conversion */ +#define ADC_SR_JSTRT ((uint32_t)0x00000008) /*!< Injected channel Start flag */ +#define ADC_SR_STRT ((uint32_t)0x00000010) /*!< Regular channel Start flag */ +#define ADC_SR_OVR ((uint32_t)0x00000020) /*!< Overrun flag */ +#define ADC_SR_ADONS ((uint32_t)0x00000040) /*!< ADC ON status */ +#define ADC_SR_RCNR ((uint32_t)0x00000100) /*!< Regular channel not ready flag */ +#define ADC_SR_JCNR ((uint32_t)0x00000200) /*!< Injected channel not ready flag */ + +/******************* Bit definition for ADC_CR1 register ********************/ +#define ADC_CR1_AWDCH ((uint32_t)0x0000001F) /*!< AWDCH[4:0] bits (Analog watchdog channel select bits) */ +#define ADC_CR1_AWDCH_0 ((uint32_t)0x00000001) /*!< Bit 0 */ +#define ADC_CR1_AWDCH_1 ((uint32_t)0x00000002) /*!< Bit 1 */ +#define ADC_CR1_AWDCH_2 ((uint32_t)0x00000004) /*!< Bit 2 */ +#define ADC_CR1_AWDCH_3 ((uint32_t)0x00000008) /*!< Bit 3 */ +#define ADC_CR1_AWDCH_4 ((uint32_t)0x00000010) /*!< Bit 4 */ + +#define ADC_CR1_EOCIE ((uint32_t)0x00000020) /*!< Interrupt enable for EOC */ +#define ADC_CR1_AWDIE ((uint32_t)0x00000040) /*!< Analog Watchdog interrupt enable */ +#define ADC_CR1_JEOCIE ((uint32_t)0x00000080) /*!< Interrupt enable for injected channels */ +#define ADC_CR1_SCAN ((uint32_t)0x00000100) /*!< Scan mode */ +#define ADC_CR1_AWDSGL ((uint32_t)0x00000200) /*!< Enable the watchdog on a single channel in scan mode */ +#define ADC_CR1_JAUTO ((uint32_t)0x00000400) /*!< Automatic injected group conversion */ +#define ADC_CR1_DISCEN ((uint32_t)0x00000800) /*!< Discontinuous mode on regular channels */ +#define ADC_CR1_JDISCEN ((uint32_t)0x00001000) /*!< Discontinuous mode on injected channels */ + +#define ADC_CR1_DISCNUM ((uint32_t)0x0000E000) /*!< DISCNUM[2:0] bits (Discontinuous mode channel count) */ +#define ADC_CR1_DISCNUM_0 ((uint32_t)0x00002000) /*!< Bit 0 */ +#define ADC_CR1_DISCNUM_1 ((uint32_t)0x00004000) /*!< Bit 1 */ +#define ADC_CR1_DISCNUM_2 ((uint32_t)0x00008000) /*!< Bit 2 */ + +#define ADC_CR1_PDD ((uint32_t)0x00010000) /*!< Power Down during Delay phase */ +#define ADC_CR1_PDI ((uint32_t)0x00020000) /*!< Power Down during Idle phase */ + +#define ADC_CR1_JAWDEN ((uint32_t)0x00400000) /*!< Analog watchdog enable on injected channels */ +#define ADC_CR1_AWDEN ((uint32_t)0x00800000) /*!< Analog watchdog enable on regular channels */ + +#define ADC_CR1_RES ((uint32_t)0x03000000) /*!< RES[1:0] bits (Resolution) */ +#define ADC_CR1_RES_0 ((uint32_t)0x01000000) /*!< Bit 0 */ +#define ADC_CR1_RES_1 ((uint32_t)0x02000000) /*!< Bit 1 */ + +#define ADC_CR1_OVRIE ((uint32_t)0x04000000) /*!< Overrun interrupt enable */ + +/******************* Bit definition for ADC_CR2 register ********************/ +#define ADC_CR2_ADON ((uint32_t)0x00000001) /*!< A/D Converter ON / OFF */ +#define ADC_CR2_CONT ((uint32_t)0x00000002) /*!< Continuous Conversion */ +#define ADC_CR2_CFG ((uint32_t)0x00000004) /*!< ADC Configuration */ + +#define ADC_CR2_DELS ((uint32_t)0x00000070) /*!< DELS[2:0] bits (Delay selection) */ +#define ADC_CR2_DELS_0 ((uint32_t)0x00000010) /*!< Bit 0 */ +#define ADC_CR2_DELS_1 ((uint32_t)0x00000020) /*!< Bit 1 */ +#define ADC_CR2_DELS_2 ((uint32_t)0x00000040) /*!< Bit 2 */ + +#define ADC_CR2_DMA ((uint32_t)0x00000100) /*!< Direct Memory access mode */ +#define ADC_CR2_DDS ((uint32_t)0x00000200) /*!< DMA disable selection (Single ADC) */ +#define ADC_CR2_EOCS ((uint32_t)0x00000400) /*!< End of conversion selection */ +#define ADC_CR2_ALIGN ((uint32_t)0x00000800) /*!< Data Alignment */ + +#define ADC_CR2_JEXTSEL ((uint32_t)0x000F0000) /*!< JEXTSEL[3:0] bits (External event select for injected group) */ +#define ADC_CR2_JEXTSEL_0 ((uint32_t)0x00010000) /*!< Bit 0 */ +#define ADC_CR2_JEXTSEL_1 ((uint32_t)0x00020000) /*!< Bit 1 */ +#define ADC_CR2_JEXTSEL_2 ((uint32_t)0x00040000) /*!< Bit 2 */ +#define ADC_CR2_JEXTSEL_3 ((uint32_t)0x00080000) /*!< Bit 3 */ + +#define ADC_CR2_JEXTEN ((uint32_t)0x00300000) /*!< JEXTEN[1:0] bits (External Trigger Conversion mode for injected channels) */ +#define ADC_CR2_JEXTEN_0 ((uint32_t)0x00100000) /*!< Bit 0 */ +#define ADC_CR2_JEXTEN_1 ((uint32_t)0x00200000) /*!< Bit 1 */ + +#define ADC_CR2_JSWSTART ((uint32_t)0x00400000) /*!< Start Conversion of injected channels */ + +#define ADC_CR2_EXTSEL ((uint32_t)0x0F000000) /*!< EXTSEL[3:0] bits (External Event Select for regular group) */ +#define ADC_CR2_EXTSEL_0 ((uint32_t)0x01000000) /*!< Bit 0 */ +#define ADC_CR2_EXTSEL_1 ((uint32_t)0x02000000) /*!< Bit 1 */ +#define ADC_CR2_EXTSEL_2 ((uint32_t)0x04000000) /*!< Bit 2 */ +#define ADC_CR2_EXTSEL_3 ((uint32_t)0x08000000) /*!< Bit 3 */ + +#define ADC_CR2_EXTEN ((uint32_t)0x30000000) /*!< EXTEN[1:0] bits (External Trigger Conversion mode for regular channels) */ +#define ADC_CR2_EXTEN_0 ((uint32_t)0x10000000) /*!< Bit 0 */ +#define ADC_CR2_EXTEN_1 ((uint32_t)0x20000000) /*!< Bit 1 */ + +#define ADC_CR2_SWSTART ((uint32_t)0x40000000) /*!< Start Conversion of regular channels */ + +/****************** Bit definition for ADC_SMPR1 register *******************/ +#define ADC_SMPR1_SMP20 ((uint32_t)0x00000007) /*!< SMP20[2:0] bits (Channel 20 Sample time selection) */ +#define ADC_SMPR1_SMP20_0 ((uint32_t)0x00000001) /*!< Bit 0 */ +#define ADC_SMPR1_SMP20_1 ((uint32_t)0x00000002) /*!< Bit 1 */ +#define ADC_SMPR1_SMP20_2 ((uint32_t)0x00000004) /*!< Bit 2 */ + +#define ADC_SMPR1_SMP21 ((uint32_t)0x00000038) /*!< SMP21[2:0] bits (Channel 21 Sample time selection) */ +#define ADC_SMPR1_SMP21_0 ((uint32_t)0x00000008) /*!< Bit 0 */ +#define ADC_SMPR1_SMP21_1 ((uint32_t)0x00000010) /*!< Bit 1 */ +#define ADC_SMPR1_SMP21_2 ((uint32_t)0x00000020) /*!< Bit 2 */ + +#define ADC_SMPR1_SMP22 ((uint32_t)0x000001C0) /*!< SMP22[2:0] bits (Channel 22 Sample time selection) */ +#define ADC_SMPR1_SMP22_0 ((uint32_t)0x00000040) /*!< Bit 0 */ +#define ADC_SMPR1_SMP22_1 ((uint32_t)0x00000080) /*!< Bit 1 */ +#define ADC_SMPR1_SMP22_2 ((uint32_t)0x00000100) /*!< Bit 2 */ + +#define ADC_SMPR1_SMP23 ((uint32_t)0x00000E00) /*!< SMP23[2:0] bits (Channel 23 Sample time selection) */ +#define ADC_SMPR1_SMP23_0 ((uint32_t)0x00000200) /*!< Bit 0 */ +#define ADC_SMPR1_SMP23_1 ((uint32_t)0x00000400) /*!< Bit 1 */ +#define ADC_SMPR1_SMP23_2 ((uint32_t)0x00000800) /*!< Bit 2 */ + +#define ADC_SMPR1_SMP24 ((uint32_t)0x00007000) /*!< SMP24[2:0] bits (Channel 24 Sample time selection) */ +#define ADC_SMPR1_SMP24_0 ((uint32_t)0x00001000) /*!< Bit 0 */ +#define ADC_SMPR1_SMP24_1 ((uint32_t)0x00002000) /*!< Bit 1 */ +#define ADC_SMPR1_SMP24_2 ((uint32_t)0x00004000) /*!< Bit 2 */ + +#define ADC_SMPR1_SMP25 ((uint32_t)0x00038000) /*!< SMP25[2:0] bits (Channel 25 Sample time selection) */ +#define ADC_SMPR1_SMP25_0 ((uint32_t)0x00008000) /*!< Bit 0 */ +#define ADC_SMPR1_SMP25_1 ((uint32_t)0x00010000) /*!< Bit 1 */ +#define ADC_SMPR1_SMP25_2 ((uint32_t)0x00020000) /*!< Bit 2 */ + +#define ADC_SMPR1_SMP26 ((uint32_t)0x001C0000) /*!< SMP26[2:0] bits (Channel 26 Sample time selection) */ +#define ADC_SMPR1_SMP26_0 ((uint32_t)0x00040000) /*!< Bit 0 */ +#define ADC_SMPR1_SMP26_1 ((uint32_t)0x00080000) /*!< Bit 1 */ +#define ADC_SMPR1_SMP26_2 ((uint32_t)0x00100000) /*!< Bit 2 */ + +#define ADC_SMPR1_SMP27 ((uint32_t)0x00E00000) /*!< SMP27[2:0] bits (Channel 27 Sample time selection) */ +#define ADC_SMPR1_SMP27_0 ((uint32_t)0x00200000) /*!< Bit 0 */ +#define ADC_SMPR1_SMP27_1 ((uint32_t)0x00400000) /*!< Bit 1 */ +#define ADC_SMPR1_SMP27_2 ((uint32_t)0x00800000) /*!< Bit 2 */ + +#define ADC_SMPR1_SMP28 ((uint32_t)0x07000000) /*!< SMP28[2:0] bits (Channel 28 Sample time selection) */ +#define ADC_SMPR1_SMP28_0 ((uint32_t)0x01000000) /*!< Bit 0 */ +#define ADC_SMPR1_SMP28_1 ((uint32_t)0x02000000) /*!< Bit 1 */ +#define ADC_SMPR1_SMP28_2 ((uint32_t)0x04000000) /*!< Bit 2 */ + +#define ADC_SMPR1_SMP29 ((uint32_t)0x38000000) /*!< SMP29[2:0] bits (Channel 29 Sample time selection) */ +#define ADC_SMPR1_SMP29_0 ((uint32_t)0x08000000) /*!< Bit 0 */ +#define ADC_SMPR1_SMP29_1 ((uint32_t)0x10000000) /*!< Bit 1 */ +#define ADC_SMPR1_SMP29_2 ((uint32_t)0x20000000) /*!< Bit 2 */ + +/****************** Bit definition for ADC_SMPR2 register *******************/ +#define ADC_SMPR2_SMP10 ((uint32_t)0x00000007) /*!< SMP10[2:0] bits (Channel 10 Sample time selection) */ +#define ADC_SMPR2_SMP10_0 ((uint32_t)0x00000001) /*!< Bit 0 */ +#define ADC_SMPR2_SMP10_1 ((uint32_t)0x00000002) /*!< Bit 1 */ +#define ADC_SMPR2_SMP10_2 ((uint32_t)0x00000004) /*!< Bit 2 */ + +#define ADC_SMPR2_SMP11 ((uint32_t)0x00000038) /*!< SMP11[2:0] bits (Channel 11 Sample time selection) */ +#define ADC_SMPR2_SMP11_0 ((uint32_t)0x00000008) /*!< Bit 0 */ +#define ADC_SMPR2_SMP11_1 ((uint32_t)0x00000010) /*!< Bit 1 */ +#define ADC_SMPR2_SMP11_2 ((uint32_t)0x00000020) /*!< Bit 2 */ + +#define ADC_SMPR2_SMP12 ((uint32_t)0x000001C0) /*!< SMP12[2:0] bits (Channel 12 Sample time selection) */ +#define ADC_SMPR2_SMP12_0 ((uint32_t)0x00000040) /*!< Bit 0 */ +#define ADC_SMPR2_SMP12_1 ((uint32_t)0x00000080) /*!< Bit 1 */ +#define ADC_SMPR2_SMP12_2 ((uint32_t)0x00000100) /*!< Bit 2 */ + +#define ADC_SMPR2_SMP13 ((uint32_t)0x00000E00) /*!< SMP13[2:0] bits (Channel 13 Sample time selection) */ +#define ADC_SMPR2_SMP13_0 ((uint32_t)0x00000200) /*!< Bit 0 */ +#define ADC_SMPR2_SMP13_1 ((uint32_t)0x00000400) /*!< Bit 1 */ +#define ADC_SMPR2_SMP13_2 ((uint32_t)0x00000800) /*!< Bit 2 */ + +#define ADC_SMPR2_SMP14 ((uint32_t)0x00007000) /*!< SMP14[2:0] bits (Channel 14 Sample time selection) */ +#define ADC_SMPR2_SMP14_0 ((uint32_t)0x00001000) /*!< Bit 0 */ +#define ADC_SMPR2_SMP14_1 ((uint32_t)0x00002000) /*!< Bit 1 */ +#define ADC_SMPR2_SMP14_2 ((uint32_t)0x00004000) /*!< Bit 2 */ + +#define ADC_SMPR2_SMP15 ((uint32_t)0x00038000) /*!< SMP15[2:0] bits (Channel 5 Sample time selection) */ +#define ADC_SMPR2_SMP15_0 ((uint32_t)0x00008000) /*!< Bit 0 */ +#define ADC_SMPR2_SMP15_1 ((uint32_t)0x00010000) /*!< Bit 1 */ +#define ADC_SMPR2_SMP15_2 ((uint32_t)0x00020000) /*!< Bit 2 */ + +#define ADC_SMPR2_SMP16 ((uint32_t)0x001C0000) /*!< SMP16[2:0] bits (Channel 16 Sample time selection) */ +#define ADC_SMPR2_SMP16_0 ((uint32_t)0x00040000) /*!< Bit 0 */ +#define ADC_SMPR2_SMP16_1 ((uint32_t)0x00080000) /*!< Bit 1 */ +#define ADC_SMPR2_SMP16_2 ((uint32_t)0x00100000) /*!< Bit 2 */ + +#define ADC_SMPR2_SMP17 ((uint32_t)0x00E00000) /*!< SMP17[2:0] bits (Channel 17 Sample time selection) */ +#define ADC_SMPR2_SMP17_0 ((uint32_t)0x00200000) /*!< Bit 0 */ +#define ADC_SMPR2_SMP17_1 ((uint32_t)0x00400000) /*!< Bit 1 */ +#define ADC_SMPR2_SMP17_2 ((uint32_t)0x00800000) /*!< Bit 2 */ + +#define ADC_SMPR2_SMP18 ((uint32_t)0x07000000) /*!< SMP18[2:0] bits (Channel 18 Sample time selection) */ +#define ADC_SMPR2_SMP18_0 ((uint32_t)0x01000000) /*!< Bit 0 */ +#define ADC_SMPR2_SMP18_1 ((uint32_t)0x02000000) /*!< Bit 1 */ +#define ADC_SMPR2_SMP18_2 ((uint32_t)0x04000000) /*!< Bit 2 */ + +#define ADC_SMPR2_SMP19 ((uint32_t)0x38000000) /*!< SMP19[2:0] bits (Channel 19 Sample time selection) */ +#define ADC_SMPR2_SMP19_0 ((uint32_t)0x08000000) /*!< Bit 0 */ +#define ADC_SMPR2_SMP19_1 ((uint32_t)0x10000000) /*!< Bit 1 */ +#define ADC_SMPR2_SMP19_2 ((uint32_t)0x20000000) /*!< Bit 2 */ + +/****************** Bit definition for ADC_SMPR3 register *******************/ +#define ADC_SMPR3_SMP0 ((uint32_t)0x00000007) /*!< SMP0[2:0] bits (Channel 0 Sample time selection) */ +#define ADC_SMPR3_SMP0_0 ((uint32_t)0x00000001) /*!< Bit 0 */ +#define ADC_SMPR3_SMP0_1 ((uint32_t)0x00000002) /*!< Bit 1 */ +#define ADC_SMPR3_SMP0_2 ((uint32_t)0x00000004) /*!< Bit 2 */ + +#define ADC_SMPR3_SMP1 ((uint32_t)0x00000038) /*!< SMP1[2:0] bits (Channel 1 Sample time selection) */ +#define ADC_SMPR3_SMP1_0 ((uint32_t)0x00000008) /*!< Bit 0 */ +#define ADC_SMPR3_SMP1_1 ((uint32_t)0x00000010) /*!< Bit 1 */ +#define ADC_SMPR3_SMP1_2 ((uint32_t)0x00000020) /*!< Bit 2 */ + +#define ADC_SMPR3_SMP2 ((uint32_t)0x000001C0) /*!< SMP2[2:0] bits (Channel 2 Sample time selection) */ +#define ADC_SMPR3_SMP2_0 ((uint32_t)0x00000040) /*!< Bit 0 */ +#define ADC_SMPR3_SMP2_1 ((uint32_t)0x00000080) /*!< Bit 1 */ +#define ADC_SMPR3_SMP2_2 ((uint32_t)0x00000100) /*!< Bit 2 */ + +#define ADC_SMPR3_SMP3 ((uint32_t)0x00000E00) /*!< SMP3[2:0] bits (Channel 3 Sample time selection) */ +#define ADC_SMPR3_SMP3_0 ((uint32_t)0x00000200) /*!< Bit 0 */ +#define ADC_SMPR3_SMP3_1 ((uint32_t)0x00000400) /*!< Bit 1 */ +#define ADC_SMPR3_SMP3_2 ((uint32_t)0x00000800) /*!< Bit 2 */ + +#define ADC_SMPR3_SMP4 ((uint32_t)0x00007000) /*!< SMP4[2:0] bits (Channel 4 Sample time selection) */ +#define ADC_SMPR3_SMP4_0 ((uint32_t)0x00001000) /*!< Bit 0 */ +#define ADC_SMPR3_SMP4_1 ((uint32_t)0x00002000) /*!< Bit 1 */ +#define ADC_SMPR3_SMP4_2 ((uint32_t)0x00004000) /*!< Bit 2 */ + +#define ADC_SMPR3_SMP5 ((uint32_t)0x00038000) /*!< SMP5[2:0] bits (Channel 5 Sample time selection) */ +#define ADC_SMPR3_SMP5_0 ((uint32_t)0x00008000) /*!< Bit 0 */ +#define ADC_SMPR3_SMP5_1 ((uint32_t)0x00010000) /*!< Bit 1 */ +#define ADC_SMPR3_SMP5_2 ((uint32_t)0x00020000) /*!< Bit 2 */ + +#define ADC_SMPR3_SMP6 ((uint32_t)0x001C0000) /*!< SMP6[2:0] bits (Channel 6 Sample time selection) */ +#define ADC_SMPR3_SMP6_0 ((uint32_t)0x00040000) /*!< Bit 0 */ +#define ADC_SMPR3_SMP6_1 ((uint32_t)0x00080000) /*!< Bit 1 */ +#define ADC_SMPR3_SMP6_2 ((uint32_t)0x00100000) /*!< Bit 2 */ + +#define ADC_SMPR3_SMP7 ((uint32_t)0x00E00000) /*!< SMP7[2:0] bits (Channel 7 Sample time selection) */ +#define ADC_SMPR3_SMP7_0 ((uint32_t)0x00200000) /*!< Bit 0 */ +#define ADC_SMPR3_SMP7_1 ((uint32_t)0x00400000) /*!< Bit 1 */ +#define ADC_SMPR3_SMP7_2 ((uint32_t)0x00800000) /*!< Bit 2 */ + +#define ADC_SMPR3_SMP8 ((uint32_t)0x07000000) /*!< SMP8[2:0] bits (Channel 8 Sample time selection) */ +#define ADC_SMPR3_SMP8_0 ((uint32_t)0x01000000) /*!< Bit 0 */ +#define ADC_SMPR3_SMP8_1 ((uint32_t)0x02000000) /*!< Bit 1 */ +#define ADC_SMPR3_SMP8_2 ((uint32_t)0x04000000) /*!< Bit 2 */ + +#define ADC_SMPR3_SMP9 ((uint32_t)0x38000000) /*!< SMP9[2:0] bits (Channel 9 Sample time selection) */ +#define ADC_SMPR3_SMP9_0 ((uint32_t)0x08000000) /*!< Bit 0 */ +#define ADC_SMPR3_SMP9_1 ((uint32_t)0x10000000) /*!< Bit 1 */ +#define ADC_SMPR3_SMP9_2 ((uint32_t)0x20000000) /*!< Bit 2 */ + +/****************** Bit definition for ADC_JOFR1 register *******************/ +#define ADC_JOFR1_JOFFSET1 ((uint32_t)0x00000FFF) /*!< Data offset for injected channel 1 */ + +/****************** Bit definition for ADC_JOFR2 register *******************/ +#define ADC_JOFR2_JOFFSET2 ((uint32_t)0x00000FFF) /*!< Data offset for injected channel 2 */ + +/****************** Bit definition for ADC_JOFR3 register *******************/ +#define ADC_JOFR3_JOFFSET3 ((uint32_t)0x00000FFF) /*!< Data offset for injected channel 3 */ + +/****************** Bit definition for ADC_JOFR4 register *******************/ +#define ADC_JOFR4_JOFFSET4 ((uint32_t)0x00000FFF) /*!< Data offset for injected channel 4 */ + +/******************* Bit definition for ADC_HTR register ********************/ +#define ADC_HTR_HT ((uint32_t)0x00000FFF) /*!< Analog watchdog high threshold */ + +/******************* Bit definition for ADC_LTR register ********************/ +#define ADC_LTR_LT ((uint32_t)0x00000FFF) /*!< Analog watchdog low threshold */ + +/******************* Bit definition for ADC_SQR1 register *******************/ +#define ADC_SQR1_L ((uint32_t)0x00F00000) /*!< L[3:0] bits (Regular channel sequence length) */ +#define ADC_SQR1_L_0 ((uint32_t)0x00100000) /*!< Bit 0 */ +#define ADC_SQR1_L_1 ((uint32_t)0x00200000) /*!< Bit 1 */ +#define ADC_SQR1_L_2 ((uint32_t)0x00400000) /*!< Bit 2 */ +#define ADC_SQR1_L_3 ((uint32_t)0x00800000) /*!< Bit 3 */ + +#define ADC_SQR1_SQ28 ((uint32_t)0x000F8000) /*!< SQ28[4:0] bits (25th conversion in regular sequence) */ +#define ADC_SQR1_SQ28_0 ((uint32_t)0x00008000) /*!< Bit 0 */ +#define ADC_SQR1_SQ28_1 ((uint32_t)0x00010000) /*!< Bit 1 */ +#define ADC_SQR1_SQ28_2 ((uint32_t)0x00020000) /*!< Bit 2 */ +#define ADC_SQR1_SQ28_3 ((uint32_t)0x00040000) /*!< Bit 3 */ +#define ADC_SQR1_SQ28_4 ((uint32_t)0x00080000) /*!< Bit 4 */ + +#define ADC_SQR1_SQ27 ((uint32_t)0x00007C00) /*!< SQ27[4:0] bits (27th conversion in regular sequence) */ +#define ADC_SQR1_SQ27_0 ((uint32_t)0x00000400) /*!< Bit 0 */ +#define ADC_SQR1_SQ27_1 ((uint32_t)0x00000800) /*!< Bit 1 */ +#define ADC_SQR1_SQ27_2 ((uint32_t)0x00001000) /*!< Bit 2 */ +#define ADC_SQR1_SQ27_3 ((uint32_t)0x00002000) /*!< Bit 3 */ +#define ADC_SQR1_SQ27_4 ((uint32_t)0x00004000) /*!< Bit 4 */ + +#define ADC_SQR1_SQ26 ((uint32_t)0x000003E0) /*!< SQ26[4:0] bits (26th conversion in regular sequence) */ +#define ADC_SQR1_SQ26_0 ((uint32_t)0x00000020) /*!< Bit 0 */ +#define ADC_SQR1_SQ26_1 ((uint32_t)0x00000040) /*!< Bit 1 */ +#define ADC_SQR1_SQ26_2 ((uint32_t)0x00000080) /*!< Bit 2 */ +#define ADC_SQR1_SQ26_3 ((uint32_t)0x00000100) /*!< Bit 3 */ +#define ADC_SQR1_SQ26_4 ((uint32_t)0x00000200) /*!< Bit 4 */ + +#define ADC_SQR1_SQ25 ((uint32_t)0x0000001F) /*!< SQ25[4:0] bits (25th conversion in regular sequence) */ +#define ADC_SQR1_SQ25_0 ((uint32_t)0x00000001) /*!< Bit 0 */ +#define ADC_SQR1_SQ25_1 ((uint32_t)0x00000002) /*!< Bit 1 */ +#define ADC_SQR1_SQ25_2 ((uint32_t)0x00000004) /*!< Bit 2 */ +#define ADC_SQR1_SQ25_3 ((uint32_t)0x00000008) /*!< Bit 3 */ +#define ADC_SQR1_SQ25_4 ((uint32_t)0x00000010) /*!< Bit 4 */ + +/******************* Bit definition for ADC_SQR2 register *******************/ +#define ADC_SQR2_SQ19 ((uint32_t)0x0000001F) /*!< SQ19[4:0] bits (19th conversion in regular sequence) */ +#define ADC_SQR2_SQ19_0 ((uint32_t)0x00000001) /*!< Bit 0 */ +#define ADC_SQR2_SQ19_1 ((uint32_t)0x00000002) /*!< Bit 1 */ +#define ADC_SQR2_SQ19_2 ((uint32_t)0x00000004) /*!< Bit 2 */ +#define ADC_SQR2_SQ19_3 ((uint32_t)0x00000008) /*!< Bit 3 */ +#define ADC_SQR2_SQ19_4 ((uint32_t)0x00000010) /*!< Bit 4 */ + +#define ADC_SQR2_SQ20 ((uint32_t)0x000003E0) /*!< SQ20[4:0] bits (20th conversion in regular sequence) */ +#define ADC_SQR2_SQ20_0 ((uint32_t)0x00000020) /*!< Bit 0 */ +#define ADC_SQR2_SQ20_1 ((uint32_t)0x00000040) /*!< Bit 1 */ +#define ADC_SQR2_SQ20_2 ((uint32_t)0x00000080) /*!< Bit 2 */ +#define ADC_SQR2_SQ20_3 ((uint32_t)0x00000100) /*!< Bit 3 */ +#define ADC_SQR2_SQ20_4 ((uint32_t)0x00000200) /*!< Bit 4 */ + +#define ADC_SQR2_SQ21 ((uint32_t)0x00007C00) /*!< SQ21[4:0] bits (21th conversion in regular sequence) */ +#define ADC_SQR2_SQ21_0 ((uint32_t)0x00000400) /*!< Bit 0 */ +#define ADC_SQR2_SQ21_1 ((uint32_t)0x00000800) /*!< Bit 1 */ +#define ADC_SQR2_SQ21_2 ((uint32_t)0x00001000) /*!< Bit 2 */ +#define ADC_SQR2_SQ21_3 ((uint32_t)0x00002000) /*!< Bit 3 */ +#define ADC_SQR2_SQ21_4 ((uint32_t)0x00004000) /*!< Bit 4 */ + +#define ADC_SQR2_SQ22 ((uint32_t)0x000F8000) /*!< SQ22[4:0] bits (22th conversion in regular sequence) */ +#define ADC_SQR2_SQ22_0 ((uint32_t)0x00008000) /*!< Bit 0 */ +#define ADC_SQR2_SQ22_1 ((uint32_t)0x00010000) /*!< Bit 1 */ +#define ADC_SQR2_SQ22_2 ((uint32_t)0x00020000) /*!< Bit 2 */ +#define ADC_SQR2_SQ22_3 ((uint32_t)0x00040000) /*!< Bit 3 */ +#define ADC_SQR2_SQ22_4 ((uint32_t)0x00080000) /*!< Bit 4 */ + +#define ADC_SQR2_SQ23 ((uint32_t)0x01F00000) /*!< SQ23[4:0] bits (23th conversion in regular sequence) */ +#define ADC_SQR2_SQ23_0 ((uint32_t)0x00100000) /*!< Bit 0 */ +#define ADC_SQR2_SQ23_1 ((uint32_t)0x00200000) /*!< Bit 1 */ +#define ADC_SQR2_SQ23_2 ((uint32_t)0x00400000) /*!< Bit 2 */ +#define ADC_SQR2_SQ23_3 ((uint32_t)0x00800000) /*!< Bit 3 */ +#define ADC_SQR2_SQ23_4 ((uint32_t)0x01000000) /*!< Bit 4 */ + +#define ADC_SQR2_SQ24 ((uint32_t)0x3E000000) /*!< SQ24[4:0] bits (24th conversion in regular sequence) */ +#define ADC_SQR2_SQ24_0 ((uint32_t)0x02000000) /*!< Bit 0 */ +#define ADC_SQR2_SQ24_1 ((uint32_t)0x04000000) /*!< Bit 1 */ +#define ADC_SQR2_SQ24_2 ((uint32_t)0x08000000) /*!< Bit 2 */ +#define ADC_SQR2_SQ24_3 ((uint32_t)0x10000000) /*!< Bit 3 */ +#define ADC_SQR2_SQ24_4 ((uint32_t)0x20000000) /*!< Bit 4 */ + +/******************* Bit definition for ADC_SQR3 register *******************/ +#define ADC_SQR3_SQ13 ((uint32_t)0x0000001F) /*!< SQ13[4:0] bits (13th conversion in regular sequence) */ +#define ADC_SQR3_SQ13_0 ((uint32_t)0x00000001) /*!< Bit 0 */ +#define ADC_SQR3_SQ13_1 ((uint32_t)0x00000002) /*!< Bit 1 */ +#define ADC_SQR3_SQ13_2 ((uint32_t)0x00000004) /*!< Bit 2 */ +#define ADC_SQR3_SQ13_3 ((uint32_t)0x00000008) /*!< Bit 3 */ +#define ADC_SQR3_SQ13_4 ((uint32_t)0x00000010) /*!< Bit 4 */ + +#define ADC_SQR3_SQ14 ((uint32_t)0x000003E0) /*!< SQ14[4:0] bits (14th conversion in regular sequence) */ +#define ADC_SQR3_SQ14_0 ((uint32_t)0x00000020) /*!< Bit 0 */ +#define ADC_SQR3_SQ14_1 ((uint32_t)0x00000040) /*!< Bit 1 */ +#define ADC_SQR3_SQ14_2 ((uint32_t)0x00000080) /*!< Bit 2 */ +#define ADC_SQR3_SQ14_3 ((uint32_t)0x00000100) /*!< Bit 3 */ +#define ADC_SQR3_SQ14_4 ((uint32_t)0x00000200) /*!< Bit 4 */ + +#define ADC_SQR3_SQ15 ((uint32_t)0x00007C00) /*!< SQ15[4:0] bits (15th conversion in regular sequence) */ +#define ADC_SQR3_SQ15_0 ((uint32_t)0x00000400) /*!< Bit 0 */ +#define ADC_SQR3_SQ15_1 ((uint32_t)0x00000800) /*!< Bit 1 */ +#define ADC_SQR3_SQ15_2 ((uint32_t)0x00001000) /*!< Bit 2 */ +#define ADC_SQR3_SQ15_3 ((uint32_t)0x00002000) /*!< Bit 3 */ +#define ADC_SQR3_SQ15_4 ((uint32_t)0x00004000) /*!< Bit 4 */ + +#define ADC_SQR3_SQ16 ((uint32_t)0x000F8000) /*!< SQ16[4:0] bits (16th conversion in regular sequence) */ +#define ADC_SQR3_SQ16_0 ((uint32_t)0x00008000) /*!< Bit 0 */ +#define ADC_SQR3_SQ16_1 ((uint32_t)0x00010000) /*!< Bit 1 */ +#define ADC_SQR3_SQ16_2 ((uint32_t)0x00020000) /*!< Bit 2 */ +#define ADC_SQR3_SQ16_3 ((uint32_t)0x00040000) /*!< Bit 3 */ +#define ADC_SQR3_SQ16_4 ((uint32_t)0x00080000) /*!< Bit 4 */ + +#define ADC_SQR3_SQ17 ((uint32_t)0x01F00000) /*!< SQ17[4:0] bits (17th conversion in regular sequence) */ +#define ADC_SQR3_SQ17_0 ((uint32_t)0x00100000) /*!< Bit 0 */ +#define ADC_SQR3_SQ17_1 ((uint32_t)0x00200000) /*!< Bit 1 */ +#define ADC_SQR3_SQ17_2 ((uint32_t)0x00400000) /*!< Bit 2 */ +#define ADC_SQR3_SQ17_3 ((uint32_t)0x00800000) /*!< Bit 3 */ +#define ADC_SQR3_SQ17_4 ((uint32_t)0x01000000) /*!< Bit 4 */ + +#define ADC_SQR3_SQ18 ((uint32_t)0x3E000000) /*!< SQ18[4:0] bits (18th conversion in regular sequence) */ +#define ADC_SQR3_SQ18_0 ((uint32_t)0x02000000) /*!< Bit 0 */ +#define ADC_SQR3_SQ18_1 ((uint32_t)0x04000000) /*!< Bit 1 */ +#define ADC_SQR3_SQ18_2 ((uint32_t)0x08000000) /*!< Bit 2 */ +#define ADC_SQR3_SQ18_3 ((uint32_t)0x10000000) /*!< Bit 3 */ +#define ADC_SQR3_SQ18_4 ((uint32_t)0x20000000) /*!< Bit 4 */ + +/******************* Bit definition for ADC_SQR4 register *******************/ +#define ADC_SQR4_SQ7 ((uint32_t)0x0000001F) /*!< SQ7[4:0] bits (7th conversion in regular sequence) */ +#define ADC_SQR4_SQ7_0 ((uint32_t)0x00000001) /*!< Bit 0 */ +#define ADC_SQR4_SQ7_1 ((uint32_t)0x00000002) /*!< Bit 1 */ +#define ADC_SQR4_SQ7_2 ((uint32_t)0x00000004) /*!< Bit 2 */ +#define ADC_SQR4_SQ7_3 ((uint32_t)0x00000008) /*!< Bit 3 */ +#define ADC_SQR4_SQ7_4 ((uint32_t)0x00000010) /*!< Bit 4 */ + +#define ADC_SQR4_SQ8 ((uint32_t)0x000003E0) /*!< SQ8[4:0] bits (8th conversion in regular sequence) */ +#define ADC_SQR4_SQ8_0 ((uint32_t)0x00000020) /*!< Bit 0 */ +#define ADC_SQR4_SQ8_1 ((uint32_t)0x00000040) /*!< Bit 1 */ +#define ADC_SQR4_SQ8_2 ((uint32_t)0x00000080) /*!< Bit 2 */ +#define ADC_SQR4_SQ8_3 ((uint32_t)0x00000100) /*!< Bit 3 */ +#define ADC_SQR4_SQ8_4 ((uint32_t)0x00000200) /*!< Bit 4 */ + +#define ADC_SQR4_SQ9 ((uint32_t)0x00007C00) /*!< SQ9[4:0] bits (9th conversion in regular sequence) */ +#define ADC_SQR4_SQ9_0 ((uint32_t)0x00000400) /*!< Bit 0 */ +#define ADC_SQR4_SQ9_1 ((uint32_t)0x00000800) /*!< Bit 1 */ +#define ADC_SQR4_SQ9_2 ((uint32_t)0x00001000) /*!< Bit 2 */ +#define ADC_SQR4_SQ9_3 ((uint32_t)0x00002000) /*!< Bit 3 */ +#define ADC_SQR4_SQ9_4 ((uint32_t)0x00004000) /*!< Bit 4 */ + +#define ADC_SQR4_SQ10 ((uint32_t)0x000F8000) /*!< SQ10[4:0] bits (10th conversion in regular sequence) */ +#define ADC_SQR4_SQ10_0 ((uint32_t)0x00008000) /*!< Bit 0 */ +#define ADC_SQR4_SQ10_1 ((uint32_t)0x00010000) /*!< Bit 1 */ +#define ADC_SQR4_SQ10_2 ((uint32_t)0x00020000) /*!< Bit 2 */ +#define ADC_SQR4_SQ10_3 ((uint32_t)0x00040000) /*!< Bit 3 */ +#define ADC_SQR4_SQ10_4 ((uint32_t)0x00080000) /*!< Bit 4 */ + +#define ADC_SQR4_SQ11 ((uint32_t)0x01F00000) /*!< SQ11[4:0] bits (11th conversion in regular sequence) */ +#define ADC_SQR4_SQ11_0 ((uint32_t)0x00100000) /*!< Bit 0 */ +#define ADC_SQR4_SQ11_1 ((uint32_t)0x00200000) /*!< Bit 1 */ +#define ADC_SQR4_SQ11_2 ((uint32_t)0x00400000) /*!< Bit 2 */ +#define ADC_SQR4_SQ11_3 ((uint32_t)0x00800000) /*!< Bit 3 */ +#define ADC_SQR4_SQ11_4 ((uint32_t)0x01000000) /*!< Bit 4 */ + +#define ADC_SQR4_SQ12 ((uint32_t)0x3E000000) /*!< SQ12[4:0] bits (12th conversion in regular sequence) */ +#define ADC_SQR4_SQ12_0 ((uint32_t)0x02000000) /*!< Bit 0 */ +#define ADC_SQR4_SQ12_1 ((uint32_t)0x04000000) /*!< Bit 1 */ +#define ADC_SQR4_SQ12_2 ((uint32_t)0x08000000) /*!< Bit 2 */ +#define ADC_SQR4_SQ12_3 ((uint32_t)0x10000000) /*!< Bit 3 */ +#define ADC_SQR4_SQ12_4 ((uint32_t)0x20000000) /*!< Bit 4 */ + +/******************* Bit definition for ADC_SQR5 register *******************/ +#define ADC_SQR5_SQ1 ((uint32_t)0x0000001F) /*!< SQ1[4:0] bits (1st conversion in regular sequence) */ +#define ADC_SQR5_SQ1_0 ((uint32_t)0x00000001) /*!< Bit 0 */ +#define ADC_SQR5_SQ1_1 ((uint32_t)0x00000002) /*!< Bit 1 */ +#define ADC_SQR5_SQ1_2 ((uint32_t)0x00000004) /*!< Bit 2 */ +#define ADC_SQR5_SQ1_3 ((uint32_t)0x00000008) /*!< Bit 3 */ +#define ADC_SQR5_SQ1_4 ((uint32_t)0x00000010) /*!< Bit 4 */ + +#define ADC_SQR5_SQ2 ((uint32_t)0x000003E0) /*!< SQ2[4:0] bits (2nd conversion in regular sequence) */ +#define ADC_SQR5_SQ2_0 ((uint32_t)0x00000020) /*!< Bit 0 */ +#define ADC_SQR5_SQ2_1 ((uint32_t)0x00000040) /*!< Bit 1 */ +#define ADC_SQR5_SQ2_2 ((uint32_t)0x00000080) /*!< Bit 2 */ +#define ADC_SQR5_SQ2_3 ((uint32_t)0x00000100) /*!< Bit 3 */ +#define ADC_SQR5_SQ2_4 ((uint32_t)0x00000200) /*!< Bit 4 */ + +#define ADC_SQR5_SQ3 ((uint32_t)0x00007C00) /*!< SQ3[4:0] bits (3rd conversion in regular sequence) */ +#define ADC_SQR5_SQ3_0 ((uint32_t)0x00000400) /*!< Bit 0 */ +#define ADC_SQR5_SQ3_1 ((uint32_t)0x00000800) /*!< Bit 1 */ +#define ADC_SQR5_SQ3_2 ((uint32_t)0x00001000) /*!< Bit 2 */ +#define ADC_SQR5_SQ3_3 ((uint32_t)0x00002000) /*!< Bit 3 */ +#define ADC_SQR5_SQ3_4 ((uint32_t)0x00004000) /*!< Bit 4 */ + +#define ADC_SQR5_SQ4 ((uint32_t)0x000F8000) /*!< SQ4[4:0] bits (4th conversion in regular sequence) */ +#define ADC_SQR5_SQ4_0 ((uint32_t)0x00008000) /*!< Bit 0 */ +#define ADC_SQR5_SQ4_1 ((uint32_t)0x00010000) /*!< Bit 1 */ +#define ADC_SQR5_SQ4_2 ((uint32_t)0x00020000) /*!< Bit 2 */ +#define ADC_SQR5_SQ4_3 ((uint32_t)0x00040000) /*!< Bit 3 */ +#define ADC_SQR5_SQ4_4 ((uint32_t)0x00080000) /*!< Bit 4 */ + +#define ADC_SQR5_SQ5 ((uint32_t)0x01F00000) /*!< SQ5[4:0] bits (5th conversion in regular sequence) */ +#define ADC_SQR5_SQ5_0 ((uint32_t)0x00100000) /*!< Bit 0 */ +#define ADC_SQR5_SQ5_1 ((uint32_t)0x00200000) /*!< Bit 1 */ +#define ADC_SQR5_SQ5_2 ((uint32_t)0x00400000) /*!< Bit 2 */ +#define ADC_SQR5_SQ5_3 ((uint32_t)0x00800000) /*!< Bit 3 */ +#define ADC_SQR5_SQ5_4 ((uint32_t)0x01000000) /*!< Bit 4 */ + +#define ADC_SQR5_SQ6 ((uint32_t)0x3E000000) /*!< SQ6[4:0] bits (6th conversion in regular sequence) */ +#define ADC_SQR5_SQ6_0 ((uint32_t)0x02000000) /*!< Bit 0 */ +#define ADC_SQR5_SQ6_1 ((uint32_t)0x04000000) /*!< Bit 1 */ +#define ADC_SQR5_SQ6_2 ((uint32_t)0x08000000) /*!< Bit 2 */ +#define ADC_SQR5_SQ6_3 ((uint32_t)0x10000000) /*!< Bit 3 */ +#define ADC_SQR5_SQ6_4 ((uint32_t)0x20000000) /*!< Bit 4 */ + + +/******************* Bit definition for ADC_JSQR register *******************/ +#define ADC_JSQR_JSQ1 ((uint32_t)0x0000001F) /*!< JSQ1[4:0] bits (1st conversion in injected sequence) */ +#define ADC_JSQR_JSQ1_0 ((uint32_t)0x00000001) /*!< Bit 0 */ +#define ADC_JSQR_JSQ1_1 ((uint32_t)0x00000002) /*!< Bit 1 */ +#define ADC_JSQR_JSQ1_2 ((uint32_t)0x00000004) /*!< Bit 2 */ +#define ADC_JSQR_JSQ1_3 ((uint32_t)0x00000008) /*!< Bit 3 */ +#define ADC_JSQR_JSQ1_4 ((uint32_t)0x00000010) /*!< Bit 4 */ + +#define ADC_JSQR_JSQ2 ((uint32_t)0x000003E0) /*!< JSQ2[4:0] bits (2nd conversion in injected sequence) */ +#define ADC_JSQR_JSQ2_0 ((uint32_t)0x00000020) /*!< Bit 0 */ +#define ADC_JSQR_JSQ2_1 ((uint32_t)0x00000040) /*!< Bit 1 */ +#define ADC_JSQR_JSQ2_2 ((uint32_t)0x00000080) /*!< Bit 2 */ +#define ADC_JSQR_JSQ2_3 ((uint32_t)0x00000100) /*!< Bit 3 */ +#define ADC_JSQR_JSQ2_4 ((uint32_t)0x00000200) /*!< Bit 4 */ + +#define ADC_JSQR_JSQ3 ((uint32_t)0x00007C00) /*!< JSQ3[4:0] bits (3rd conversion in injected sequence) */ +#define ADC_JSQR_JSQ3_0 ((uint32_t)0x00000400) /*!< Bit 0 */ +#define ADC_JSQR_JSQ3_1 ((uint32_t)0x00000800) /*!< Bit 1 */ +#define ADC_JSQR_JSQ3_2 ((uint32_t)0x00001000) /*!< Bit 2 */ +#define ADC_JSQR_JSQ3_3 ((uint32_t)0x00002000) /*!< Bit 3 */ +#define ADC_JSQR_JSQ3_4 ((uint32_t)0x00004000) /*!< Bit 4 */ + +#define ADC_JSQR_JSQ4 ((uint32_t)0x000F8000) /*!< JSQ4[4:0] bits (4th conversion in injected sequence) */ +#define ADC_JSQR_JSQ4_0 ((uint32_t)0x00008000) /*!< Bit 0 */ +#define ADC_JSQR_JSQ4_1 ((uint32_t)0x00010000) /*!< Bit 1 */ +#define ADC_JSQR_JSQ4_2 ((uint32_t)0x00020000) /*!< Bit 2 */ +#define ADC_JSQR_JSQ4_3 ((uint32_t)0x00040000) /*!< Bit 3 */ +#define ADC_JSQR_JSQ4_4 ((uint32_t)0x00080000) /*!< Bit 4 */ + +#define ADC_JSQR_JL ((uint32_t)0x00300000) /*!< JL[1:0] bits (Injected Sequence length) */ +#define ADC_JSQR_JL_0 ((uint32_t)0x00100000) /*!< Bit 0 */ +#define ADC_JSQR_JL_1 ((uint32_t)0x00200000) /*!< Bit 1 */ + +/******************* Bit definition for ADC_JDR1 register *******************/ +#define ADC_JDR1_JDATA ((uint32_t)0x0000FFFF) /*!< Injected data */ + +/******************* Bit definition for ADC_JDR2 register *******************/ +#define ADC_JDR2_JDATA ((uint32_t)0x0000FFFF) /*!< Injected data */ + +/******************* Bit definition for ADC_JDR3 register *******************/ +#define ADC_JDR3_JDATA ((uint32_t)0x0000FFFF) /*!< Injected data */ + +/******************* Bit definition for ADC_JDR4 register *******************/ +#define ADC_JDR4_JDATA ((uint32_t)0x0000FFFF) /*!< Injected data */ + +/******************** Bit definition for ADC_DR register ********************/ +#define ADC_DR_DATA ((uint32_t)0x0000FFFF) /*!< Regular data */ + +/****************** Bit definition for ADC_SMPR0 register *******************/ +#define ADC_SMPR3_SMP30 ((uint32_t)0x00000007) /*!< SMP30[2:0] bits (Channel 30 Sample time selection) */ +#define ADC_SMPR3_SMP30_0 ((uint32_t)0x00000001) /*!< Bit 0 */ +#define ADC_SMPR3_SMP30_1 ((uint32_t)0x00000002) /*!< Bit 1 */ +#define ADC_SMPR3_SMP30_2 ((uint32_t)0x00000004) /*!< Bit 2 */ + +#define ADC_SMPR3_SMP31 ((uint32_t)0x00000038) /*!< SMP31[2:0] bits (Channel 31 Sample time selection) */ +#define ADC_SMPR3_SMP31_0 ((uint32_t)0x00000008) /*!< Bit 0 */ +#define ADC_SMPR3_SMP31_1 ((uint32_t)0x00000010) /*!< Bit 1 */ +#define ADC_SMPR3_SMP31_2 ((uint32_t)0x00000020) /*!< Bit 2 */ + +/******************* Bit definition for ADC_CSR register ********************/ +#define ADC_CSR_AWD1 ((uint32_t)0x00000001) /*!< ADC1 Analog watchdog flag */ +#define ADC_CSR_EOC1 ((uint32_t)0x00000002) /*!< ADC1 End of conversion */ +#define ADC_CSR_JEOC1 ((uint32_t)0x00000004) /*!< ADC1 Injected channel end of conversion */ +#define ADC_CSR_JSTRT1 ((uint32_t)0x00000008) /*!< ADC1 Injected channel Start flag */ +#define ADC_CSR_STRT1 ((uint32_t)0x00000010) /*!< ADC1 Regular channel Start flag */ +#define ADC_CSR_OVR1 ((uint32_t)0x00000020) /*!< ADC1 overrun flag */ +#define ADC_CSR_ADONS1 ((uint32_t)0x00000040) /*!< ADON status of ADC1 */ + +/******************* Bit definition for ADC_CCR register ********************/ +#define ADC_CCR_ADCPRE ((uint32_t)0x00030000) /*!< ADC prescaler*/ +#define ADC_CCR_ADCPRE_0 ((uint32_t)0x00010000) /*!< Bit 0 */ +#define ADC_CCR_ADCPRE_1 ((uint32_t)0x00020000) /*!< Bit 1 */ +#define ADC_CCR_TSVREFE ((uint32_t)0x00800000) /*!< Temperature Sensor and VREFINT Enable */ + +/******************************************************************************/ +/* */ +/* Advanced Encryption Standard (AES) */ +/* */ +/******************************************************************************/ +/******************* Bit definition for AES_CR register *********************/ +#define AES_CR_EN ((uint32_t)0x00000001) /*!< AES Enable */ +#define AES_CR_DATATYPE ((uint32_t)0x00000006) /*!< Data type selection */ +#define AES_CR_DATATYPE_0 ((uint32_t)0x00000002) /*!< Bit 0 */ +#define AES_CR_DATATYPE_1 ((uint32_t)0x00000004) /*!< Bit 1 */ + +#define AES_CR_MODE ((uint32_t)0x00000018) /*!< AES Mode Of Operation */ +#define AES_CR_MODE_0 ((uint32_t)0x00000008) /*!< Bit 0 */ +#define AES_CR_MODE_1 ((uint32_t)0x00000010) /*!< Bit 1 */ + +#define AES_CR_CHMOD ((uint32_t)0x00000060) /*!< AES Chaining Mode */ +#define AES_CR_CHMOD_0 ((uint32_t)0x00000020) /*!< Bit 0 */ +#define AES_CR_CHMOD_1 ((uint32_t)0x00000040) /*!< Bit 1 */ + +#define AES_CR_CCFC ((uint32_t)0x00000080) /*!< Computation Complete Flag Clear */ +#define AES_CR_ERRC ((uint32_t)0x00000100) /*!< Error Clear */ +#define AES_CR_CCIE ((uint32_t)0x00000200) /*!< Computation Complete Interrupt Enable */ +#define AES_CR_ERRIE ((uint32_t)0x00000400) /*!< Error Interrupt Enable */ +#define AES_CR_DMAINEN ((uint32_t)0x00000800) /*!< DMA ENable managing the data input phase */ +#define AES_CR_DMAOUTEN ((uint32_t)0x00001000) /*!< DMA Enable managing the data output phase */ + +/******************* Bit definition for AES_SR register *********************/ +#define AES_SR_CCF ((uint32_t)0x00000001) /*!< Computation Complete Flag */ +#define AES_SR_RDERR ((uint32_t)0x00000002) /*!< Read Error Flag */ +#define AES_SR_WRERR ((uint32_t)0x00000004) /*!< Write Error Flag */ + +/******************* Bit definition for AES_DINR register *******************/ +#define AES_DINR ((uint32_t)0x0000FFFF) /*!< AES Data Input Register */ + +/******************* Bit definition for AES_DOUTR register ******************/ +#define AES_DOUTR ((uint32_t)0x0000FFFF) /*!< AES Data Output Register */ + +/******************* Bit definition for AES_KEYR0 register ******************/ +#define AES_KEYR0 ((uint32_t)0x0000FFFF) /*!< AES Key Register 0 */ + +/******************* Bit definition for AES_KEYR1 register ******************/ +#define AES_KEYR1 ((uint32_t)0x0000FFFF) /*!< AES Key Register 1 */ + +/******************* Bit definition for AES_KEYR2 register ******************/ +#define AES_KEYR2 ((uint32_t)0x0000FFFF) /*!< AES Key Register 2 */ + +/******************* Bit definition for AES_KEYR3 register ******************/ +#define AES_KEYR3 ((uint32_t)0x0000FFFF) /*!< AES Key Register 3 */ + +/******************* Bit definition for AES_IVR0 register *******************/ +#define AES_IVR0 ((uint32_t)0x0000FFFF) /*!< AES Initialization Vector Register 0 */ + +/******************* Bit definition for AES_IVR1 register *******************/ +#define AES_IVR1 ((uint32_t)0x0000FFFF) /*!< AES Initialization Vector Register 1 */ + +/******************* Bit definition for AES_IVR2 register *******************/ +#define AES_IVR2 ((uint32_t)0x0000FFFF) /*!< AES Initialization Vector Register 2 */ + +/******************* Bit definition for AES_IVR3 register *******************/ +#define AES_IVR3 ((uint32_t)0x0000FFFF) /*!< AES Initialization Vector Register 3 */ + +/******************************************************************************/ +/* */ +/* Analog Comparators (COMP) */ +/* */ +/******************************************************************************/ + +/****************** Bit definition for COMP_CSR register ********************/ +#define COMP_CSR_10KPU ((uint32_t)0x00000001) /*!< 10K pull-up resistor */ +#define COMP_CSR_400KPU ((uint32_t)0x00000002) /*!< 400K pull-up resistor */ +#define COMP_CSR_10KPD ((uint32_t)0x00000004) /*!< 10K pull-down resistor */ +#define COMP_CSR_400KPD ((uint32_t)0x00000008) /*!< 400K pull-down resistor */ + +#define COMP_CSR_CMP1EN ((uint32_t)0x00000010) /*!< Comparator 1 enable */ +#define COMP_CSR_SW1 ((uint32_t)0x00000020) /*!< SW1 analog switch enable */ +#define COMP_CSR_CMP1OUT ((uint32_t)0x00000080) /*!< Comparator 1 output */ + +#define COMP_CSR_SPEED ((uint32_t)0x00001000) /*!< Comparator 2 speed */ +#define COMP_CSR_CMP2OUT ((uint32_t)0x00002000) /*!< Comparator 2 ouput */ + +#define COMP_CSR_VREFOUTEN ((uint32_t)0x00010000) /*!< Comparator Vref Enable */ +#define COMP_CSR_WNDWE ((uint32_t)0x00020000) /*!< Window mode enable */ + +#define COMP_CSR_INSEL ((uint32_t)0x001C0000) /*!< INSEL[2:0] Inversion input Selection */ +#define COMP_CSR_INSEL_0 ((uint32_t)0x00040000) /*!< Bit 0 */ +#define COMP_CSR_INSEL_1 ((uint32_t)0x00080000) /*!< Bit 1 */ +#define COMP_CSR_INSEL_2 ((uint32_t)0x00100000) /*!< Bit 2 */ + +#define COMP_CSR_OUTSEL ((uint32_t)0x00E00000) /*!< OUTSEL[2:0] comparator 2 output redirection */ +#define COMP_CSR_OUTSEL_0 ((uint32_t)0x00200000) /*!< Bit 0 */ +#define COMP_CSR_OUTSEL_1 ((uint32_t)0x00400000) /*!< Bit 1 */ +#define COMP_CSR_OUTSEL_2 ((uint32_t)0x00800000) /*!< Bit 2 */ + +#define COMP_CSR_FCH3 ((uint32_t)0x04000000) /*!< Bit 26 */ +#define COMP_CSR_FCH8 ((uint32_t)0x08000000) /*!< Bit 27 */ +#define COMP_CSR_RCH13 ((uint32_t)0x10000000) /*!< Bit 28 */ + +#define COMP_CSR_CAIE ((uint32_t)0x20000000) /*!< Bit 29 */ +#define COMP_CSR_CAIF ((uint32_t)0x40000000) /*!< Bit 30 */ +#define COMP_CSR_TSUSP ((uint32_t)0x80000000) /*!< Bit 31 */ + +/******************************************************************************/ +/* */ +/* Operational Amplifier (OPAMP) */ +/* */ +/******************************************************************************/ +/******************* Bit definition for OPAMP_CSR register ******************/ +#define OPAMP_CSR_OPA1PD ((uint32_t)0x00000001) /*!< OPAMP1 disable */ +#define OPAMP_CSR_S3SEL1 ((uint32_t)0x00000002) /*!< Switch 3 for OPAMP1 Enable */ +#define OPAMP_CSR_S4SEL1 ((uint32_t)0x00000004) /*!< Switch 4 for OPAMP1 Enable */ +#define OPAMP_CSR_S5SEL1 ((uint32_t)0x00000008) /*!< Switch 5 for OPAMP1 Enable */ +#define OPAMP_CSR_S6SEL1 ((uint32_t)0x00000010) /*!< Switch 6 for OPAMP1 Enable */ +#define OPAMP_CSR_OPA1CAL_L ((uint32_t)0x00000020) /*!< OPAMP1 Offset calibration for P differential pair */ +#define OPAMP_CSR_OPA1CAL_H ((uint32_t)0x00000040) /*!< OPAMP1 Offset calibration for N differential pair */ +#define OPAMP_CSR_OPA1LPM ((uint32_t)0x00000080) /*!< OPAMP1 Low power enable */ +#define OPAMP_CSR_OPA2PD ((uint32_t)0x00000100) /*!< OPAMP2 disable */ +#define OPAMP_CSR_S3SEL2 ((uint32_t)0x00000200) /*!< Switch 3 for OPAMP2 Enable */ +#define OPAMP_CSR_S4SEL2 ((uint32_t)0x00000400) /*!< Switch 4 for OPAMP2 Enable */ +#define OPAMP_CSR_S5SEL2 ((uint32_t)0x00000800) /*!< Switch 5 for OPAMP2 Enable */ +#define OPAMP_CSR_S6SEL2 ((uint32_t)0x00001000) /*!< Switch 6 for OPAMP2 Enable */ +#define OPAMP_CSR_OPA2CAL_L ((uint32_t)0x00002000) /*!< OPAMP2 Offset calibration for P differential pair */ +#define OPAMP_CSR_OPA2CAL_H ((uint32_t)0x00004000) /*!< OPAMP2 Offset calibration for N differential pair */ +#define OPAMP_CSR_OPA2LPM ((uint32_t)0x00008000) /*!< OPAMP2 Low power enable */ +#define OPAMP_CSR_OPA3PD ((uint32_t)0x00010000) /*!< OPAMP3 disable */ +#define OPAMP_CSR_S3SEL3 ((uint32_t)0x00020000) /*!< Switch 3 for OPAMP3 Enable */ +#define OPAMP_CSR_S4SEL3 ((uint32_t)0x00040000) /*!< Switch 4 for OPAMP3 Enable */ +#define OPAMP_CSR_S5SEL3 ((uint32_t)0x00080000) /*!< Switch 5 for OPAMP3 Enable */ +#define OPAMP_CSR_S6SEL3 ((uint32_t)0x00100000) /*!< Switch 6 for OPAMP3 Enable */ +#define OPAMP_CSR_OPA3CAL_L ((uint32_t)0x00200000) /*!< OPAMP3 Offset calibration for P differential pair */ +#define OPAMP_CSR_OPA3CAL_H ((uint32_t)0x00400000) /*!< OPAMP3 Offset calibration for N differential pair */ +#define OPAMP_CSR_OPA3LPM ((uint32_t)0x00800000) /*!< OPAMP3 Low power enable */ +#define OPAMP_CSR_ANAWSEL1 ((uint32_t)0x01000000) /*!< Switch ANA Enable for OPAMP1 */ +#define OPAMP_CSR_ANAWSEL2 ((uint32_t)0x02000000) /*!< Switch ANA Enable for OPAMP2 */ +#define OPAMP_CSR_ANAWSEL3 ((uint32_t)0x04000000) /*!< Switch ANA Enable for OPAMP3 */ +#define OPAMP_CSR_S7SEL2 ((uint32_t)0x08000000) /*!< Switch 7 for OPAMP2 Enable */ +#define OPAMP_CSR_AOP_RANGE ((uint32_t)0x10000000) /*!< Power range selection */ +#define OPAMP_CSR_OPA1CALOUT ((uint32_t)0x20000000) /*!< OPAMP1 calibration output */ +#define OPAMP_CSR_OPA2CALOUT ((uint32_t)0x40000000) /*!< OPAMP2 calibration output */ +#define OPAMP_CSR_OPA3CALOUT ((uint32_t)0x80000000) /*!< OPAMP3 calibration output */ + +/******************* Bit definition for OPAMP_OTR register ******************/ +#define OPAMP_OTR_AO1_OPT_OFFSET_TRIM ((uint32_t)0x000003FF) /*!< Offset trim for OPAMP1 */ +#define OPAMP_OTR_AO2_OPT_OFFSET_TRIM ((uint32_t)0x000FFC00) /*!< Offset trim for OPAMP2 */ +#define OPAMP_OTR_AO3_OPT_OFFSET_TRIM ((uint32_t)0x3FF00000) /*!< Offset trim for OPAMP2 */ +#define OPAMP_OTR_OT_USER ((uint32_t)0x80000000) /*!< Switch to OPAMP offset user trimmed values */ + +/******************* Bit definition for OPAMP_LPOTR register ****************/ +#define OPAMP_LP_OTR_AO1_OPT_OFFSET_TRIM_LP ((uint32_t)0x000003FF) /*!< Offset trim in low power for OPAMP1 */ +#define OPAMP_LP_OTR_AO2_OPT_OFFSET_TRIM_LP ((uint32_t)0x000FFC00) /*!< Offset trim in low power for OPAMP2 */ +#define OPAMP_LP_OTR_AO3_OPT_OFFSET_TRIM_LP ((uint32_t)0x3FF00000) /*!< Offset trim in low power for OPAMP3 */ + +/******************************************************************************/ +/* */ +/* CRC calculation unit (CRC) */ +/* */ +/******************************************************************************/ + +/******************* Bit definition for CRC_DR register *********************/ +#define CRC_DR_DR ((uint32_t)0xFFFFFFFF) /*!< Data register bits */ + +/******************* Bit definition for CRC_IDR register ********************/ +#define CRC_IDR_IDR ((uint8_t)0xFF) /*!< General-purpose 8-bit data register bits */ + +/******************** Bit definition for CRC_CR register ********************/ +#define CRC_CR_RESET ((uint32_t)0x00000001) /*!< RESET bit */ + +/******************************************************************************/ +/* */ +/* Digital to Analog Converter (DAC) */ +/* */ +/******************************************************************************/ + +/******************** Bit definition for DAC_CR register ********************/ +#define DAC_CR_EN1 ((uint32_t)0x00000001) /*!
© COPYRIGHT 2012 STMicroelectronics
+ * + * Licensed under MCD-ST Liberty SW License Agreement V2, (the "License"); + * You may not use this file except in compliance with the License. + * You may obtain a copy of the License at: + * + * http://www.st.com/software_license_agreement_liberty_v2 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, + * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + * + ****************************************************************************** + */ + +/** @addtogroup CMSIS + * @{ + */ + +/** @addtogroup stm32l1xx_system + * @{ + */ + +/** + * @brief Define to prevent recursive inclusion + */ +#ifndef __SYSTEM_STM32L1XX_H +#define __SYSTEM_STM32L1XX_H + +#ifdef __cplusplus + extern "C" { +#endif + +/** @addtogroup STM32L1xx_System_Includes + * @{ + */ + +/** + * @} + */ + + +/** @addtogroup STM32L1xx_System_Exported_types + * @{ + */ + +extern uint32_t SystemCoreClock; /*!< System Clock Frequency (Core Clock) */ + +/** + * @} + */ + +/** @addtogroup STM32L1xx_System_Exported_Constants + * @{ + */ + +/** + * @} + */ + +/** @addtogroup STM32L1xx_System_Exported_Macros + * @{ + */ + +/** + * @} + */ + +/** @addtogroup STM32L1xx_System_Exported_Functions + * @{ + */ + +extern void SystemInit(void); +extern void SystemCoreClockUpdate(void); +/** + * @} + */ + +#ifdef __cplusplus +} +#endif + +#endif /*__SYSTEM_STM32L1XX_H */ + +/** + * @} + */ + +/** + * @} + */ +/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ diff --git a/Libraries/CMSIS/Device/ST/STM32L1xx/Release_Notes.html b/Libraries/CMSIS/Device/ST/STM32L1xx/Release_Notes.html new file mode 100644 index 0000000..7164799 --- /dev/null +++ b/Libraries/CMSIS/Device/ST/STM32L1xx/Release_Notes.html @@ -0,0 +1,365 @@ + + + + + + + + + + + +Release Notes for STM32L1xx CMSIS + + + + + + +
+


+

+
+ + + + + + +
+ + + + + + +
+ +

Release +Notes for STM32L1xx CMSIS
+

+

Copyright + 2012 STMicroelectronics

+

+
+

 

+ + + + + + +
+

Contents

+
    +
  1. STM32L1xx CMSIS update history
    2. +
  2. License
    3. +
+

STM32L1xx CMSIS update history

+

V1.1.1 / 05-March-2012

+

Main +Changes

+ +
  • All source files: license disclaimer text update and add link to the License file on ST Internet.

V1.1.0 / 24-January-2012

+

Main +Changes

+ +
    +
  • Alpha version for STM32L1xx High-density and Medium-density Plus devices.
    • +
  • Add support for STM32L1xx High-density and Medium-density Plus devices:
    • +
      +
    • Add new product define: "#define STM32L1XX_MDP"
      • +
    • Add new product define: "#define STM32L1XX_HD"
      • + +
    + +
      +
    • Change the library version to V1.1.0
      +
      • +
    +
      +
    • Add new IRQ to support STM32L1XX_HD and STM32L1XX_MDP vector table
      • +
    +
      +
    • Add new and update some Typedef to support new peripherals (AES, SDIO, OPAMP, FSMC, I2S)
      • +
    +
      +
    • Add new peripherals address mapping
      • +
    +
      +
    • Update bits definition
      • +
    +
  • Add new startup file "startup_stm32l1xx_mdp.s" for all toolchains
    • +
  • Add new startup file "startup_stm32l1xx_hd.s" for all toolchains
    • +
  • Change the RTC "CAL" register name to "CALR"
    • +
  • Update registers bits definitions.
    + +
    • +
+ + +

V1.0.0 / 31-December-2010

Main +Changes

+
  • Created

    + +

    License

    Licensed under MCD-ST Liberty SW License Agreement V2, (the "License"); You may not use this package except in compliance with the License. You may obtain a copy of the License at:


    Unless +required by applicable law or agreed to in writing, software +distributed under the License is distributed on an "AS IS" BASIS,
    WITHOUT +WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See +the License for the specific language governing permissions and +limitations under the License.     +
    +
    +

    For +complete documentation on STM32 Microcontrollers +visit www.st.com/STM32

    +
    +

    +
    +
    +

     

    +
    + \ No newline at end of file diff --git a/Libraries/CMSIS/Device/ST/STM32L1xx/Source/Templates/TASKING/cstart_thumb2.asm b/Libraries/CMSIS/Device/ST/STM32L1xx/Source/Templates/TASKING/cstart_thumb2.asm new file mode 100644 index 0000000..85626cd --- /dev/null +++ b/Libraries/CMSIS/Device/ST/STM32L1xx/Source/Templates/TASKING/cstart_thumb2.asm @@ -0,0 +1,140 @@ + + +;; NOTE: To allow the use of this file for both ARMv6M and ARMv7M, +;; we will only use 16-bit Thumb intructions. + + .extern _lc_ub_stack ; usr/sys mode stack pointer + .extern _lc_ue_stack ; symbol required by debugger + .extern _lc_ub_table ; ROM to RAM copy table + .extern main + .extern _Exit + .extern exit + .weak exit + .global __get_argcv + .weak __get_argcv + .extern __argcvbuf + .weak __argcvbuf + ;;.extern __init_hardware + .extern SystemInit + + .if @defined('__PROF_ENABLE__') + .extern __prof_init + .endif + .if @defined('__POSIX__') + .extern posix_main + .extern _posix_boot_stack_top + .endif + + .global _START + + .section .text.cstart + + .thumb +_START: + ;; anticipate possible ROM/RAM remapping + ;; by loading the 'real' program address + ldr r1,=_Next + bx r1 +_Next: + ;; initialize the stack pointer + ldr r1,=_lc_ub_stack ; TODO: make this part of the vector table + mov sp,r1 + + ;; call a user function which initializes function. + bl SystemInit + + ;; copy initialized sections from ROM to RAM + ;; and clear uninitialized data sections in RAM + + ldr r3,=_lc_ub_table + movs r0,#0 +cploop: + ldr r4,[r3,#0] ; load type + ldr r5,[r3,#4] ; dst address + ldr r6,[r3,#8] ; src address + ldr r7,[r3,#12] ; size + + cmp r4,#1 + beq copy + cmp r4,#2 + beq clear + b done + +copy: + subs r7,r7,#1 + ldrb r1,[r6,r7] + strb r1,[r5,r7] + bne copy + + adds r3,r3,#16 + b cploop + +clear: + subs r7,r7,#1 + strb r0,[r5,r7] + bne clear + + adds r3,r3,#16 + b cploop + +done: + + .if @defined('__POSIX__') + + ;; posix stack buffer for system upbringing + ldr r0,=_posix_boot_stack_top + ldr r0, [r0] + mov sp,r0 + + .else + + ;; load r10 with end of USR/SYS stack, which is + ;; needed in case stack overflow checking is on + ;; NOTE: use 16-bit instructions only, for ARMv6M + ldr r0,=_lc_ue_stack + mov r10,r0 + + .endif + + .if @defined('__PROF_ENABLE__') + bl __prof_init + .endif + + .if @defined('__POSIX__') + ;; call posix_main with no arguments + bl posix_main + .else + ;; retrieve argc and argv (default argv[0]==NULL & argc==0) + bl __get_argcv + ldr r1,=__argcvbuf + ;; call main + bl main + .endif + + ;; call exit using the return value from main() + ;; Note. Calling exit will also run all functions + ;; that were supplied through atexit(). + bl exit + +__get_argcv: ; weak definition + movs r0,#0 + bx lr + + .ltorg + .endsec + + .calls '_START', ' ' + .calls '_START','__init_vector_table' + .if @defined('__PROF_ENABLE__') + .calls '_START','__prof_init' + .endif + .if @defined('__POSIX__') + .calls '_START','posix_main' + .else + .calls '_START','__get_argcv' + .calls '_START','main' + .endif + .calls '_START','exit' + .calls '_START','',0 + + .end diff --git a/Libraries/CMSIS/Device/ST/STM32L1xx/Source/Templates/TrueSTUDIO/startup_stm32l1xx_hd.s b/Libraries/CMSIS/Device/ST/STM32L1xx/Source/Templates/TrueSTUDIO/startup_stm32l1xx_hd.s new file mode 100644 index 0000000..45aefde --- /dev/null +++ b/Libraries/CMSIS/Device/ST/STM32L1xx/Source/Templates/TrueSTUDIO/startup_stm32l1xx_hd.s @@ -0,0 +1,424 @@ +/** + ****************************************************************************** + * @file startup_stm32l1xx_hd.s + * @author MCD Application Team + * @version V1.1.1 + * @date 09-March-2012 + * @brief STM32L1xx Ultra Low Power High-density Devices vector table for + * Atollic toolchain. + * This module performs: + * - Set the initial SP + * - Set the initial PC == Reset_Handler, + * - Set the vector table entries with the exceptions ISR address + * - Configure the clock system + * - Branches to main in the C library (which eventually + * calls main()). + * After Reset the Cortex-M3 processor is in Thread mode, + * priority is Privileged, and the Stack is set to Main. + ****************************************************************************** + * @attention + * + *

    © COPYRIGHT 2012 STMicroelectronics

    + * + * Licensed under MCD-ST Liberty SW License Agreement V2, (the "License"); + * You may not use this file except in compliance with the License. + * You may obtain a copy of the License at: + * + * http://www.st.com/software_license_agreement_liberty_v2 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, + * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + * + ****************************************************************************** + */ + + .syntax unified + .cpu cortex-m3 + .fpu softvfp + .thumb + +.global g_pfnVectors +.global Default_Handler + +/* start address for the initialization values of the .data section. +defined in linker script */ +.word _sidata +/* start address for the .data section. defined in linker script */ +.word _sdata +/* end address for the .data section. defined in linker script */ +.word _edata +/* start address for the .bss section. defined in linker script */ +.word _sbss +/* end address for the .bss section. defined in linker script */ +.word _ebss + +.equ BootRAM, 0xF108F85F +/** + * @brief This is the code that gets called when the processor first + * starts execution following a reset event. Only the absolutely + * necessary set is performed, after which the application + * supplied main() routine is called. + * @param None + * @retval : None +*/ + + .section .text.Reset_Handler + .weak Reset_Handler + .type Reset_Handler, %function +Reset_Handler: + +/* Copy the data segment initializers from flash to SRAM */ + movs r1, #0 + b LoopCopyDataInit + +CopyDataInit: + ldr r3, =_sidata + ldr r3, [r3, r1] + str r3, [r0, r1] + adds r1, r1, #4 + +LoopCopyDataInit: + ldr r0, =_sdata + ldr r3, =_edata + adds r2, r0, r1 + cmp r2, r3 + bcc CopyDataInit + ldr r2, =_sbss + b LoopFillZerobss +/* Zero fill the bss segment. */ +FillZerobss: + movs r3, #0 + str r3, [r2], #4 + +LoopFillZerobss: + ldr r3, = _ebss + cmp r2, r3 + bcc FillZerobss + +/* Call the clock system intitialization function.*/ + bl SystemInit +/* Call static constructors */ + bl __libc_init_array +/* Call the application's entry point.*/ + bl main + bx lr +.size Reset_Handler, .-Reset_Handler + +/** + * @brief This is the code that gets called when the processor receives an + * unexpected interrupt. This simply enters an infinite loop, preserving + * the system state for examination by a debugger. + * + * @param None + * @retval : None +*/ + .section .text.Default_Handler,"ax",%progbits +Default_Handler: +Infinite_Loop: + b Infinite_Loop + .size Default_Handler, .-Default_Handler +/****************************************************************************** +* +* The minimal vector table for a Cortex M3. Note that the proper constructs +* must be placed on this to ensure that it ends up at physical address +* 0x0000.0000. +* +******************************************************************************/ + .section .isr_vector,"a",%progbits + .type g_pfnVectors, %object + .size g_pfnVectors, .-g_pfnVectors + + +g_pfnVectors: + .word _estack + .word Reset_Handler + .word NMI_Handler + .word HardFault_Handler + .word MemManage_Handler + .word BusFault_Handler + .word UsageFault_Handler + .word 0 + .word 0 + .word 0 + .word 0 + .word SVC_Handler + .word DebugMon_Handler + .word 0 + .word PendSV_Handler + .word SysTick_Handler + .word WWDG_IRQHandler + .word PVD_IRQHandler + .word TAMPER_STAMP_IRQHandler + .word RTC_WKUP_IRQHandler + .word FLASH_IRQHandler + .word RCC_IRQHandler + .word EXTI0_IRQHandler + .word EXTI1_IRQHandler + .word EXTI2_IRQHandler + .word EXTI3_IRQHandler + .word EXTI4_IRQHandler + .word DMA1_Channel1_IRQHandler + .word DMA1_Channel2_IRQHandler + .word DMA1_Channel3_IRQHandler + .word DMA1_Channel4_IRQHandler + .word DMA1_Channel5_IRQHandler + .word DMA1_Channel6_IRQHandler + .word DMA1_Channel7_IRQHandler + .word ADC1_IRQHandler + .word USB_HP_IRQHandler + .word USB_LP_IRQHandler + .word DAC_IRQHandler + .word COMP_IRQHandler + .word EXTI9_5_IRQHandler + .word LCD_IRQHandler + .word TIM9_IRQHandler + .word TIM10_IRQHandler + .word TIM11_IRQHandler + .word TIM2_IRQHandler + .word TIM3_IRQHandler + .word TIM4_IRQHandler + .word I2C1_EV_IRQHandler + .word I2C1_ER_IRQHandler + .word I2C2_EV_IRQHandler + .word I2C2_ER_IRQHandler + .word SPI1_IRQHandler + .word SPI2_IRQHandler + .word USART1_IRQHandler + .word USART2_IRQHandler + .word USART3_IRQHandler + .word EXTI15_10_IRQHandler + .word RTC_Alarm_IRQHandler + .word USB_FS_WKUP_IRQHandler + .word TIM6_IRQHandler + .word TIM7_IRQHandler + .word SDIO_IRQHandler + .word TIM5_IRQHandler + .word SPI3_IRQHandler + .word UART4_IRQHandler + .word UART5_IRQHandler + .word DMA2_Channel1_IRQHandler + .word DMA2_Channel2_IRQHandler + .word DMA2_Channel3_IRQHandler + .word DMA2_Channel4_IRQHandler + .word DMA2_Channel5_IRQHandler + .word AES_IRQHandler + .word COMP_ACQ_IRQHandler + .word 0 + .word 0 + .word 0 + .word 0 + .word 0 + .word BootRAM /* @0x108. This is for boot in RAM mode for + STM32L15x ULtra Low Power High-density devices. */ + +/******************************************************************************* +* +* Provide weak aliases for each Exception handler to the Default_Handler. +* As they are weak aliases, any function with the same name will override +* this definition. +* +*******************************************************************************/ + + .weak NMI_Handler + .thumb_set NMI_Handler,Default_Handler + + .weak HardFault_Handler + .thumb_set HardFault_Handler,Default_Handler + + .weak MemManage_Handler + .thumb_set MemManage_Handler,Default_Handler + + .weak BusFault_Handler + .thumb_set BusFault_Handler,Default_Handler + + .weak UsageFault_Handler + .thumb_set UsageFault_Handler,Default_Handler + + .weak SVC_Handler + .thumb_set SVC_Handler,Default_Handler + + .weak DebugMon_Handler + .thumb_set DebugMon_Handler,Default_Handler + + .weak PendSV_Handler + .thumb_set PendSV_Handler,Default_Handler + + .weak SysTick_Handler + .thumb_set SysTick_Handler,Default_Handler + + .weak WWDG_IRQHandler + .thumb_set WWDG_IRQHandler,Default_Handler + + .weak PVD_IRQHandler + .thumb_set PVD_IRQHandler,Default_Handler + + .weak TAMPER_STAMP_IRQHandler + .thumb_set TAMPER_STAMP_IRQHandler,Default_Handler + + .weak RTC_WKUP_IRQHandler + .thumb_set RTC_WKUP_IRQHandler,Default_Handler + + .weak FLASH_IRQHandler + .thumb_set FLASH_IRQHandler,Default_Handler + + .weak RCC_IRQHandler + .thumb_set RCC_IRQHandler,Default_Handler + + .weak EXTI0_IRQHandler + .thumb_set EXTI0_IRQHandler,Default_Handler + + .weak EXTI1_IRQHandler + .thumb_set EXTI1_IRQHandler,Default_Handler + + .weak EXTI2_IRQHandler + .thumb_set EXTI2_IRQHandler,Default_Handler + + .weak EXTI3_IRQHandler + .thumb_set EXTI3_IRQHandler,Default_Handler + + .weak EXTI4_IRQHandler + .thumb_set EXTI4_IRQHandler,Default_Handler + + .weak DMA1_Channel1_IRQHandler + .thumb_set DMA1_Channel1_IRQHandler,Default_Handler + + .weak DMA1_Channel2_IRQHandler + .thumb_set DMA1_Channel2_IRQHandler,Default_Handler + + .weak DMA1_Channel3_IRQHandler + .thumb_set DMA1_Channel3_IRQHandler,Default_Handler + + .weak DMA1_Channel4_IRQHandler + .thumb_set DMA1_Channel4_IRQHandler,Default_Handler + + .weak DMA1_Channel5_IRQHandler + .thumb_set DMA1_Channel5_IRQHandler,Default_Handler + + .weak DMA1_Channel6_IRQHandler + .thumb_set DMA1_Channel6_IRQHandler,Default_Handler + + .weak DMA1_Channel7_IRQHandler + .thumb_set DMA1_Channel7_IRQHandler,Default_Handler + + .weak ADC1_IRQHandler + .thumb_set ADC1_IRQHandler,Default_Handler + + .weak USB_HP_IRQHandler + .thumb_set USB_HP_IRQHandler,Default_Handler + + .weak USB_LP_IRQHandler + .thumb_set USB_LP_IRQHandler,Default_Handler + + .weak DAC_IRQHandler + .thumb_set DAC_IRQHandler,Default_Handler + + .weak COMP_IRQHandler + .thumb_set COMP_IRQHandler,Default_Handler + + .weak EXTI9_5_IRQHandler + .thumb_set EXTI9_5_IRQHandler,Default_Handler + + .weak LCD_IRQHandler + .thumb_set LCD_IRQHandler,Default_Handler + + .weak TIM9_IRQHandler + .thumb_set TIM9_IRQHandler,Default_Handler + + .weak TIM10_IRQHandler + .thumb_set TIM10_IRQHandler,Default_Handler + + .weak TIM11_IRQHandler + .thumb_set TIM11_IRQHandler,Default_Handler + + .weak TIM2_IRQHandler + .thumb_set TIM2_IRQHandler,Default_Handler + + .weak TIM3_IRQHandler + .thumb_set TIM3_IRQHandler,Default_Handler + + .weak TIM4_IRQHandler + .thumb_set TIM4_IRQHandler,Default_Handler + + .weak I2C1_EV_IRQHandler + .thumb_set I2C1_EV_IRQHandler,Default_Handler + + .weak I2C1_ER_IRQHandler + .thumb_set I2C1_ER_IRQHandler,Default_Handler + + .weak I2C2_EV_IRQHandler + .thumb_set I2C2_EV_IRQHandler,Default_Handler + + .weak I2C2_ER_IRQHandler + .thumb_set I2C2_ER_IRQHandler,Default_Handler + + .weak SPI1_IRQHandler + .thumb_set SPI1_IRQHandler,Default_Handler + + .weak SPI2_IRQHandler + .thumb_set SPI2_IRQHandler,Default_Handler + + .weak USART1_IRQHandler + .thumb_set USART1_IRQHandler,Default_Handler + + .weak USART2_IRQHandler + .thumb_set USART2_IRQHandler,Default_Handler + + .weak USART3_IRQHandler + .thumb_set USART3_IRQHandler,Default_Handler + + .weak EXTI15_10_IRQHandler + .thumb_set EXTI15_10_IRQHandler,Default_Handler + + .weak RTC_Alarm_IRQHandler + .thumb_set RTC_Alarm_IRQHandler,Default_Handler + + .weak USB_FS_WKUP_IRQHandler + .thumb_set USB_FS_WKUP_IRQHandler,Default_Handler + + .weak TIM6_IRQHandler + .thumb_set TIM6_IRQHandler,Default_Handler + + .weak TIM7_IRQHandler + .thumb_set TIM7_IRQHandler,Default_Handler + + .weak SDIO_IRQHandler + .thumb_set SDIO_IRQHandler,Default_Handler + + .weak TIM5_IRQHandler + .thumb_set TIM5_IRQHandler,Default_Handler + + .weak SPI3_IRQHandler + .thumb_set SPI3_IRQHandler,Default_Handler + + .weak UART4_IRQHandler + .thumb_set UART4_IRQHandler,Default_Handler + + .weak UART5_IRQHandler + .thumb_set UART5_IRQHandler,Default_Handler + + .weak DMA2_Channel1_IRQHandler + .thumb_set DMA2_Channel1_IRQHandler,Default_Handler + + .weak DMA2_Channel2_IRQHandler + .thumb_set DMA2_Channel2_IRQHandler,Default_Handler + + .weak DMA2_Channel3_IRQHandler + .thumb_set DMA2_Channel3_IRQHandler,Default_Handler + + .weak DMA2_Channel4_IRQHandler + .thumb_set DMA2_Channel4_IRQHandler,Default_Handler + + .weak DMA2_Channel5_IRQHandler + .thumb_set DMA2_Channel5_IRQHandler,Default_Handler + + .weak AES_IRQHandler + .thumb_set AES_IRQHandler,Default_Handler + + .weak COMP_ACQ_IRQHandler + .thumb_set COMP_ACQ_IRQHandler,Default_Handler + +/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ + diff --git a/Libraries/CMSIS/Device/ST/STM32L1xx/Source/Templates/TrueSTUDIO/startup_stm32l1xx_md.s b/Libraries/CMSIS/Device/ST/STM32L1xx/Source/Templates/TrueSTUDIO/startup_stm32l1xx_md.s new file mode 100644 index 0000000..91a0c7d --- /dev/null +++ b/Libraries/CMSIS/Device/ST/STM32L1xx/Source/Templates/TrueSTUDIO/startup_stm32l1xx_md.s @@ -0,0 +1,376 @@ +/** + ****************************************************************************** + * @file startup_stm32l1xx_md.s + * @author MCD Application Team + * @version V1.1.1 + * @date 09-March-2012 + * @brief STM32L1xx Ultra Low Power Medium-density Devices vector table for + * Atollic toolchain. + * This module performs: + * - Set the initial SP + * - Set the initial PC == Reset_Handler, + * - Set the vector table entries with the exceptions ISR address + * - Configure the clock system + * - Branches to main in the C library (which eventually + * calls main()). + * After Reset the Cortex-M3 processor is in Thread mode, + * priority is Privileged, and the Stack is set to Main. + ****************************************************************************** + * @attention + * + *

    © COPYRIGHT 2012 STMicroelectronics

    + * + * Licensed under MCD-ST Liberty SW License Agreement V2, (the "License"); + * You may not use this file except in compliance with the License. + * You may obtain a copy of the License at: + * + * http://www.st.com/software_license_agreement_liberty_v2 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, + * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + * + ****************************************************************************** + */ + + .syntax unified + .cpu cortex-m3 + .fpu softvfp + .thumb + +.global g_pfnVectors +.global Default_Handler + +/* start address for the initialization values of the .data section. +defined in linker script */ +.word _sidata +/* start address for the .data section. defined in linker script */ +.word _sdata +/* end address for the .data section. defined in linker script */ +.word _edata +/* start address for the .bss section. defined in linker script */ +.word _sbss +/* end address for the .bss section. defined in linker script */ +.word _ebss + +.equ BootRAM, 0xF108F85F +/** + * @brief This is the code that gets called when the processor first + * starts execution following a reset event. Only the absolutely + * necessary set is performed, after which the application + * supplied main() routine is called. + * @param None + * @retval : None +*/ + + .section .text.Reset_Handler + .weak Reset_Handler + .type Reset_Handler, %function +Reset_Handler: + +/* Copy the data segment initializers from flash to SRAM */ + movs r1, #0 + b LoopCopyDataInit + +CopyDataInit: + ldr r3, =_sidata + ldr r3, [r3, r1] + str r3, [r0, r1] + adds r1, r1, #4 + +LoopCopyDataInit: + ldr r0, =_sdata + ldr r3, =_edata + adds r2, r0, r1 + cmp r2, r3 + bcc CopyDataInit + ldr r2, =_sbss + b LoopFillZerobss +/* Zero fill the bss segment. */ +FillZerobss: + movs r3, #0 + str r3, [r2], #4 + +LoopFillZerobss: + ldr r3, = _ebss + cmp r2, r3 + bcc FillZerobss + +/* Call the clock system intitialization function.*/ + bl SystemInit +/* Call static constructors */ + bl __libc_init_array +/* Call the application's entry point.*/ + bl main + bx lr +.size Reset_Handler, .-Reset_Handler + +/** + * @brief This is the code that gets called when the processor receives an + * unexpected interrupt. This simply enters an infinite loop, preserving + * the system state for examination by a debugger. + * + * @param None + * @retval : None +*/ + .section .text.Default_Handler,"ax",%progbits +Default_Handler: +Infinite_Loop: + b Infinite_Loop + .size Default_Handler, .-Default_Handler +/****************************************************************************** +* +* The minimal vector table for a Cortex M3. Note that the proper constructs +* must be placed on this to ensure that it ends up at physical address +* 0x0000.0000. +* +******************************************************************************/ + .section .isr_vector,"a",%progbits + .type g_pfnVectors, %object + .size g_pfnVectors, .-g_pfnVectors + + +g_pfnVectors: + .word _estack + .word Reset_Handler + .word NMI_Handler + .word HardFault_Handler + .word MemManage_Handler + .word BusFault_Handler + .word UsageFault_Handler + .word 0 + .word 0 + .word 0 + .word 0 + .word SVC_Handler + .word DebugMon_Handler + .word 0 + .word PendSV_Handler + .word SysTick_Handler + .word WWDG_IRQHandler + .word PVD_IRQHandler + .word TAMPER_STAMP_IRQHandler + .word RTC_WKUP_IRQHandler + .word FLASH_IRQHandler + .word RCC_IRQHandler + .word EXTI0_IRQHandler + .word EXTI1_IRQHandler + .word EXTI2_IRQHandler + .word EXTI3_IRQHandler + .word EXTI4_IRQHandler + .word DMA1_Channel1_IRQHandler + .word DMA1_Channel2_IRQHandler + .word DMA1_Channel3_IRQHandler + .word DMA1_Channel4_IRQHandler + .word DMA1_Channel5_IRQHandler + .word DMA1_Channel6_IRQHandler + .word DMA1_Channel7_IRQHandler + .word ADC1_IRQHandler + .word USB_HP_IRQHandler + .word USB_LP_IRQHandler + .word DAC_IRQHandler + .word COMP_IRQHandler + .word EXTI9_5_IRQHandler + .word LCD_IRQHandler + .word TIM9_IRQHandler + .word TIM10_IRQHandler + .word TIM11_IRQHandler + .word TIM2_IRQHandler + .word TIM3_IRQHandler + .word TIM4_IRQHandler + .word I2C1_EV_IRQHandler + .word I2C1_ER_IRQHandler + .word I2C2_EV_IRQHandler + .word I2C2_ER_IRQHandler + .word SPI1_IRQHandler + .word SPI2_IRQHandler + .word USART1_IRQHandler + .word USART2_IRQHandler + .word USART3_IRQHandler + .word EXTI15_10_IRQHandler + .word RTC_Alarm_IRQHandler + .word USB_FS_WKUP_IRQHandler + .word TIM6_IRQHandler + .word TIM7_IRQHandler + .word 0 + .word 0 + .word 0 + .word 0 + .word 0 + .word BootRAM /* @0x108. This is for boot in RAM mode for + STM32L15x ULtra Low Power Medium-density devices. */ + +/******************************************************************************* +* +* Provide weak aliases for each Exception handler to the Default_Handler. +* As they are weak aliases, any function with the same name will override +* this definition. +* +*******************************************************************************/ + + .weak NMI_Handler + .thumb_set NMI_Handler,Default_Handler + + .weak HardFault_Handler + .thumb_set HardFault_Handler,Default_Handler + + .weak MemManage_Handler + .thumb_set MemManage_Handler,Default_Handler + + .weak BusFault_Handler + .thumb_set BusFault_Handler,Default_Handler + + .weak UsageFault_Handler + .thumb_set UsageFault_Handler,Default_Handler + + .weak SVC_Handler + .thumb_set SVC_Handler,Default_Handler + + .weak DebugMon_Handler + .thumb_set DebugMon_Handler,Default_Handler + + .weak PendSV_Handler + .thumb_set PendSV_Handler,Default_Handler + + .weak SysTick_Handler + .thumb_set SysTick_Handler,Default_Handler + + .weak WWDG_IRQHandler + .thumb_set WWDG_IRQHandler,Default_Handler + + .weak PVD_IRQHandler + .thumb_set PVD_IRQHandler,Default_Handler + + .weak TAMPER_STAMP_IRQHandler + .thumb_set TAMPER_STAMP_IRQHandler,Default_Handler + + .weak RTC_WKUP_IRQHandler + .thumb_set RTC_WKUP_IRQHandler,Default_Handler + + .weak FLASH_IRQHandler + .thumb_set FLASH_IRQHandler,Default_Handler + + .weak RCC_IRQHandler + .thumb_set RCC_IRQHandler,Default_Handler + + .weak EXTI0_IRQHandler + .thumb_set EXTI0_IRQHandler,Default_Handler + + .weak EXTI1_IRQHandler + .thumb_set EXTI1_IRQHandler,Default_Handler + + .weak EXTI2_IRQHandler + .thumb_set EXTI2_IRQHandler,Default_Handler + + .weak EXTI3_IRQHandler + .thumb_set EXTI3_IRQHandler,Default_Handler + + .weak EXTI4_IRQHandler + .thumb_set EXTI4_IRQHandler,Default_Handler + + .weak DMA1_Channel1_IRQHandler + .thumb_set DMA1_Channel1_IRQHandler,Default_Handler + + .weak DMA1_Channel2_IRQHandler + .thumb_set DMA1_Channel2_IRQHandler,Default_Handler + + .weak DMA1_Channel3_IRQHandler + .thumb_set DMA1_Channel3_IRQHandler,Default_Handler + + .weak DMA1_Channel4_IRQHandler + .thumb_set DMA1_Channel4_IRQHandler,Default_Handler + + .weak DMA1_Channel5_IRQHandler + .thumb_set DMA1_Channel5_IRQHandler,Default_Handler + + .weak DMA1_Channel6_IRQHandler + .thumb_set DMA1_Channel6_IRQHandler,Default_Handler + + .weak DMA1_Channel7_IRQHandler + .thumb_set DMA1_Channel7_IRQHandler,Default_Handler + + .weak ADC1_IRQHandler + .thumb_set ADC1_IRQHandler,Default_Handler + + .weak USB_HP_IRQHandler + .thumb_set USB_HP_IRQHandler,Default_Handler + + .weak USB_LP_IRQHandler + .thumb_set USB_LP_IRQHandler,Default_Handler + + .weak DAC_IRQHandler + .thumb_set DAC_IRQHandler,Default_Handler + + .weak COMP_IRQHandler + .thumb_set COMP_IRQHandler,Default_Handler + + .weak EXTI9_5_IRQHandler + .thumb_set EXTI9_5_IRQHandler,Default_Handler + + .weak LCD_IRQHandler + .thumb_set LCD_IRQHandler,Default_Handler + + .weak TIM9_IRQHandler + .thumb_set TIM9_IRQHandler,Default_Handler + + .weak TIM10_IRQHandler + .thumb_set TIM10_IRQHandler,Default_Handler + + .weak TIM11_IRQHandler + .thumb_set TIM11_IRQHandler,Default_Handler + + .weak TIM2_IRQHandler + .thumb_set TIM2_IRQHandler,Default_Handler + + .weak TIM3_IRQHandler + .thumb_set TIM3_IRQHandler,Default_Handler + + .weak TIM4_IRQHandler + .thumb_set TIM4_IRQHandler,Default_Handler + + .weak I2C1_EV_IRQHandler + .thumb_set I2C1_EV_IRQHandler,Default_Handler + + .weak I2C1_ER_IRQHandler + .thumb_set I2C1_ER_IRQHandler,Default_Handler + + .weak I2C2_EV_IRQHandler + .thumb_set I2C2_EV_IRQHandler,Default_Handler + + .weak I2C2_ER_IRQHandler + .thumb_set I2C2_ER_IRQHandler,Default_Handler + + .weak SPI1_IRQHandler + .thumb_set SPI1_IRQHandler,Default_Handler + + .weak SPI2_IRQHandler + .thumb_set SPI2_IRQHandler,Default_Handler + + .weak USART1_IRQHandler + .thumb_set USART1_IRQHandler,Default_Handler + + .weak USART2_IRQHandler + .thumb_set USART2_IRQHandler,Default_Handler + + .weak USART3_IRQHandler + .thumb_set USART3_IRQHandler,Default_Handler + + .weak EXTI15_10_IRQHandler + .thumb_set EXTI15_10_IRQHandler,Default_Handler + + .weak RTC_Alarm_IRQHandler + .thumb_set RTC_Alarm_IRQHandler,Default_Handler + + .weak USB_FS_WKUP_IRQHandler + .thumb_set USB_FS_WKUP_IRQHandler,Default_Handler + + .weak TIM6_IRQHandler + .thumb_set TIM6_IRQHandler,Default_Handler + + .weak TIM7_IRQHandler + .thumb_set TIM7_IRQHandler,Default_Handler + +/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ + diff --git a/Libraries/CMSIS/Device/ST/STM32L1xx/Source/Templates/TrueSTUDIO/startup_stm32l1xx_mdp.s b/Libraries/CMSIS/Device/ST/STM32L1xx/Source/Templates/TrueSTUDIO/startup_stm32l1xx_mdp.s new file mode 100644 index 0000000..cc8d06c --- /dev/null +++ b/Libraries/CMSIS/Device/ST/STM32L1xx/Source/Templates/TrueSTUDIO/startup_stm32l1xx_mdp.s @@ -0,0 +1,415 @@ +/** + ****************************************************************************** + * @file startup_stm32l1xx_mdp.s + * @author MCD Application Team + * @version V1.1.1 + * @date 09-March-2012 + * @brief STM32L1xx Ultra Low Power Medium-density Plus Devices vector table + * for Atollic toolchain. + * This module performs: + * - Set the initial SP + * - Set the initial PC == Reset_Handler, + * - Set the vector table entries with the exceptions ISR address + * - Configure the clock system + * - Branches to main in the C library (which eventually + * calls main()). + * After Reset the Cortex-M3 processor is in Thread mode, + * priority is Privileged, and the Stack is set to Main. + ****************************************************************************** + * @attention + * + *

    © COPYRIGHT 2012 STMicroelectronics

    + * + * Licensed under MCD-ST Liberty SW License Agreement V2, (the "License"); + * You may not use this file except in compliance with the License. + * You may obtain a copy of the License at: + * + * http://www.st.com/software_license_agreement_liberty_v2 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, + * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + * + ****************************************************************************** + */ + + .syntax unified + .cpu cortex-m3 + .fpu softvfp + .thumb + +.global g_pfnVectors +.global Default_Handler + +/* start address for the initialization values of the .data section. +defined in linker script */ +.word _sidata +/* start address for the .data section. defined in linker script */ +.word _sdata +/* end address for the .data section. defined in linker script */ +.word _edata +/* start address for the .bss section. defined in linker script */ +.word _sbss +/* end address for the .bss section. defined in linker script */ +.word _ebss + +.equ BootRAM, 0xF108F85F +/** + * @brief This is the code that gets called when the processor first + * starts execution following a reset event. Only the absolutely + * necessary set is performed, after which the application + * supplied main() routine is called. + * @param None + * @retval : None +*/ + + .section .text.Reset_Handler + .weak Reset_Handler + .type Reset_Handler, %function +Reset_Handler: + +/* Copy the data segment initializers from flash to SRAM */ + movs r1, #0 + b LoopCopyDataInit + +CopyDataInit: + ldr r3, =_sidata + ldr r3, [r3, r1] + str r3, [r0, r1] + adds r1, r1, #4 + +LoopCopyDataInit: + ldr r0, =_sdata + ldr r3, =_edata + adds r2, r0, r1 + cmp r2, r3 + bcc CopyDataInit + ldr r2, =_sbss + b LoopFillZerobss +/* Zero fill the bss segment. */ +FillZerobss: + movs r3, #0 + str r3, [r2], #4 + +LoopFillZerobss: + ldr r3, = _ebss + cmp r2, r3 + bcc FillZerobss + +/* Call the clock system intitialization function.*/ + bl SystemInit +/* Call static constructors */ + bl __libc_init_array +/* Call the application's entry point.*/ + bl main + bx lr +.size Reset_Handler, .-Reset_Handler + +/** + * @brief This is the code that gets called when the processor receives an + * unexpected interrupt. This simply enters an infinite loop, preserving + * the system state for examination by a debugger. + * + * @param None + * @retval : None +*/ + .section .text.Default_Handler,"ax",%progbits +Default_Handler: +Infinite_Loop: + b Infinite_Loop + .size Default_Handler, .-Default_Handler +/****************************************************************************** +* +* The minimal vector table for a Cortex M3. Note that the proper constructs +* must be placed on this to ensure that it ends up at physical address +* 0x0000.0000. +* +******************************************************************************/ + .section .isr_vector,"a",%progbits + .type g_pfnVectors, %object + .size g_pfnVectors, .-g_pfnVectors + + +g_pfnVectors: + .word _estack + .word Reset_Handler + .word NMI_Handler + .word HardFault_Handler + .word MemManage_Handler + .word BusFault_Handler + .word UsageFault_Handler + .word 0 + .word 0 + .word 0 + .word 0 + .word SVC_Handler + .word DebugMon_Handler + .word 0 + .word PendSV_Handler + .word SysTick_Handler + .word WWDG_IRQHandler + .word PVD_IRQHandler + .word TAMPER_STAMP_IRQHandler + .word RTC_WKUP_IRQHandler + .word FLASH_IRQHandler + .word RCC_IRQHandler + .word EXTI0_IRQHandler + .word EXTI1_IRQHandler + .word EXTI2_IRQHandler + .word EXTI3_IRQHandler + .word EXTI4_IRQHandler + .word DMA1_Channel1_IRQHandler + .word DMA1_Channel2_IRQHandler + .word DMA1_Channel3_IRQHandler + .word DMA1_Channel4_IRQHandler + .word DMA1_Channel5_IRQHandler + .word DMA1_Channel6_IRQHandler + .word DMA1_Channel7_IRQHandler + .word ADC1_IRQHandler + .word USB_HP_IRQHandler + .word USB_LP_IRQHandler + .word DAC_IRQHandler + .word COMP_IRQHandler + .word EXTI9_5_IRQHandler + .word LCD_IRQHandler + .word TIM9_IRQHandler + .word TIM10_IRQHandler + .word TIM11_IRQHandler + .word TIM2_IRQHandler + .word TIM3_IRQHandler + .word TIM4_IRQHandler + .word I2C1_EV_IRQHandler + .word I2C1_ER_IRQHandler + .word I2C2_EV_IRQHandler + .word I2C2_ER_IRQHandler + .word SPI1_IRQHandler + .word SPI2_IRQHandler + .word USART1_IRQHandler + .word USART2_IRQHandler + .word USART3_IRQHandler + .word EXTI15_10_IRQHandler + .word RTC_Alarm_IRQHandler + .word USB_FS_WKUP_IRQHandler + .word TIM6_IRQHandler + .word TIM7_IRQHandler + .word 0 + .word TIM5_IRQHandler + .word SPI3_IRQHandler + .word 0 + .word 0 + .word DMA2_Channel1_IRQHandler + .word DMA2_Channel2_IRQHandler + .word DMA2_Channel3_IRQHandler + .word DMA2_Channel4_IRQHandler + .word DMA2_Channel5_IRQHandler + .word AES_IRQHandler + .word COMP_ACQ_IRQHandler + .word 0 + .word 0 + .word 0 + .word 0 + .word 0 + .word BootRAM /* @0x108. This is for boot in RAM mode for + STM32L15x ULtra Low Power Medium-density devices. */ + +/******************************************************************************* +* +* Provide weak aliases for each Exception handler to the Default_Handler. +* As they are weak aliases, any function with the same name will override +* this definition. +* +*******************************************************************************/ + + .weak NMI_Handler + .thumb_set NMI_Handler,Default_Handler + + .weak HardFault_Handler + .thumb_set HardFault_Handler,Default_Handler + + .weak MemManage_Handler + .thumb_set MemManage_Handler,Default_Handler + + .weak BusFault_Handler + .thumb_set BusFault_Handler,Default_Handler + + .weak UsageFault_Handler + .thumb_set UsageFault_Handler,Default_Handler + + .weak SVC_Handler + .thumb_set SVC_Handler,Default_Handler + + .weak DebugMon_Handler + .thumb_set DebugMon_Handler,Default_Handler + + .weak PendSV_Handler + .thumb_set PendSV_Handler,Default_Handler + + .weak SysTick_Handler + .thumb_set SysTick_Handler,Default_Handler + + .weak WWDG_IRQHandler + .thumb_set WWDG_IRQHandler,Default_Handler + + .weak PVD_IRQHandler + .thumb_set PVD_IRQHandler,Default_Handler + + .weak TAMPER_STAMP_IRQHandler + .thumb_set TAMPER_STAMP_IRQHandler,Default_Handler + + .weak RTC_WKUP_IRQHandler + .thumb_set RTC_WKUP_IRQHandler,Default_Handler + + .weak FLASH_IRQHandler + .thumb_set FLASH_IRQHandler,Default_Handler + + .weak RCC_IRQHandler + .thumb_set RCC_IRQHandler,Default_Handler + + .weak EXTI0_IRQHandler + .thumb_set EXTI0_IRQHandler,Default_Handler + + .weak EXTI1_IRQHandler + .thumb_set EXTI1_IRQHandler,Default_Handler + + .weak EXTI2_IRQHandler + .thumb_set EXTI2_IRQHandler,Default_Handler + + .weak EXTI3_IRQHandler + .thumb_set EXTI3_IRQHandler,Default_Handler + + .weak EXTI4_IRQHandler + .thumb_set EXTI4_IRQHandler,Default_Handler + + .weak DMA1_Channel1_IRQHandler + .thumb_set DMA1_Channel1_IRQHandler,Default_Handler + + .weak DMA1_Channel2_IRQHandler + .thumb_set DMA1_Channel2_IRQHandler,Default_Handler + + .weak DMA1_Channel3_IRQHandler + .thumb_set DMA1_Channel3_IRQHandler,Default_Handler + + .weak DMA1_Channel4_IRQHandler + .thumb_set DMA1_Channel4_IRQHandler,Default_Handler + + .weak DMA1_Channel5_IRQHandler + .thumb_set DMA1_Channel5_IRQHandler,Default_Handler + + .weak DMA1_Channel6_IRQHandler + .thumb_set DMA1_Channel6_IRQHandler,Default_Handler + + .weak DMA1_Channel7_IRQHandler + .thumb_set DMA1_Channel7_IRQHandler,Default_Handler + + .weak ADC1_IRQHandler + .thumb_set ADC1_IRQHandler,Default_Handler + + .weak USB_HP_IRQHandler + .thumb_set USB_HP_IRQHandler,Default_Handler + + .weak USB_LP_IRQHandler + .thumb_set USB_LP_IRQHandler,Default_Handler + + .weak DAC_IRQHandler + .thumb_set DAC_IRQHandler,Default_Handler + + .weak COMP_IRQHandler + .thumb_set COMP_IRQHandler,Default_Handler + + .weak EXTI9_5_IRQHandler + .thumb_set EXTI9_5_IRQHandler,Default_Handler + + .weak LCD_IRQHandler + .thumb_set LCD_IRQHandler,Default_Handler + + .weak TIM9_IRQHandler + .thumb_set TIM9_IRQHandler,Default_Handler + + .weak TIM10_IRQHandler + .thumb_set TIM10_IRQHandler,Default_Handler + + .weak TIM11_IRQHandler + .thumb_set TIM11_IRQHandler,Default_Handler + + .weak TIM2_IRQHandler + .thumb_set TIM2_IRQHandler,Default_Handler + + .weak TIM3_IRQHandler + .thumb_set TIM3_IRQHandler,Default_Handler + + .weak TIM4_IRQHandler + .thumb_set TIM4_IRQHandler,Default_Handler + + .weak I2C1_EV_IRQHandler + .thumb_set I2C1_EV_IRQHandler,Default_Handler + + .weak I2C1_ER_IRQHandler + .thumb_set I2C1_ER_IRQHandler,Default_Handler + + .weak I2C2_EV_IRQHandler + .thumb_set I2C2_EV_IRQHandler,Default_Handler + + .weak I2C2_ER_IRQHandler + .thumb_set I2C2_ER_IRQHandler,Default_Handler + + .weak SPI1_IRQHandler + .thumb_set SPI1_IRQHandler,Default_Handler + + .weak SPI2_IRQHandler + .thumb_set SPI2_IRQHandler,Default_Handler + + .weak USART1_IRQHandler + .thumb_set USART1_IRQHandler,Default_Handler + + .weak USART2_IRQHandler + .thumb_set USART2_IRQHandler,Default_Handler + + .weak USART3_IRQHandler + .thumb_set USART3_IRQHandler,Default_Handler + + .weak EXTI15_10_IRQHandler + .thumb_set EXTI15_10_IRQHandler,Default_Handler + + .weak RTC_Alarm_IRQHandler + .thumb_set RTC_Alarm_IRQHandler,Default_Handler + + .weak USB_FS_WKUP_IRQHandler + .thumb_set USB_FS_WKUP_IRQHandler,Default_Handler + + .weak TIM6_IRQHandler + .thumb_set TIM6_IRQHandler,Default_Handler + + .weak TIM7_IRQHandler + .thumb_set TIM7_IRQHandler,Default_Handler + + .weak TIM5_IRQHandler + .thumb_set TIM5_IRQHandler,Default_Handler + + .weak SPI3_IRQHandler + .thumb_set SPI3_IRQHandler,Default_Handler + + .weak DMA2_Channel1_IRQHandler + .thumb_set DMA2_Channel1_IRQHandler,Default_Handler + + .weak DMA2_Channel2_IRQHandler + .thumb_set DMA2_Channel2_IRQHandler,Default_Handler + + .weak DMA2_Channel3_IRQHandler + .thumb_set DMA2_Channel3_IRQHandler,Default_Handler + + .weak DMA2_Channel4_IRQHandler + .thumb_set DMA2_Channel4_IRQHandler,Default_Handler + + .weak DMA2_Channel5_IRQHandler + .thumb_set DMA2_Channel5_IRQHandler,Default_Handler + + .weak AES_IRQHandler + .thumb_set AES_IRQHandler,Default_Handler + + .weak COMP_ACQ_IRQHandler + .thumb_set COMP_ACQ_IRQHandler,Default_Handler + +/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ + diff --git a/Libraries/CMSIS/Device/ST/STM32L1xx/Source/Templates/arm/startup_stm32l1xx_hd.s b/Libraries/CMSIS/Device/ST/STM32L1xx/Source/Templates/arm/startup_stm32l1xx_hd.s new file mode 100644 index 0000000..c7d1e5e --- /dev/null +++ b/Libraries/CMSIS/Device/ST/STM32L1xx/Source/Templates/arm/startup_stm32l1xx_hd.s @@ -0,0 +1,356 @@ +;******************** (C) COPYRIGHT 2012 STMicroelectronics ******************** +;* File Name : startup_stm32l1xx_hd.s +;* Author : MCD Application Team +;* Version : V1.1.1 +;* Date : 09-March-2012 +;* Description : STM32L1xx Ultra Low Power High-density Devices vector +;* table for MDK-ARM toolchain. +;* This module performs: +;* - Set the initial SP +;* - Set the initial PC == Reset_Handler +;* - Set the vector table entries with the exceptions ISR address +;* - Branches to __main in the C library (which eventually +;* calls main()). +;* After Reset the CortexM3 processor is in Thread mode, +;* priority is Privileged, and the Stack is set to Main. +;* <<< Use Configuration Wizard in Context Menu >>> +;******************************************************************************* +; +; Licensed under MCD-ST Liberty SW License Agreement V2, (the "License"); +; You may not use this file except in compliance with the License. +; You may obtain a copy of the License at: +; +; http://www.st.com/software_license_agreement_liberty_v2 +; +; Unless required by applicable law or agreed to in writing, software +; distributed under the License is distributed on an "AS IS" BASIS, +; WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +; See the License for the specific language governing permissions and +; limitations under the License. +; +;******************************************************************************* + +; Amount of memory (in bytes) allocated for Stack +; Tailor this value to your application needs +; Stack Configuration +; Stack Size (in Bytes) <0x0-0xFFFFFFFF:8> +; + +Stack_Size EQU 0x00000400 + + AREA STACK, NOINIT, READWRITE, ALIGN=3 +Stack_Mem SPACE Stack_Size +__initial_sp + + +; Heap Configuration +; Heap Size (in Bytes) <0x0-0xFFFFFFFF:8> +; + +Heap_Size EQU 0x00000200 + + AREA HEAP, NOINIT, READWRITE, ALIGN=3 +__heap_base +Heap_Mem SPACE Heap_Size +__heap_limit + + PRESERVE8 + THUMB + + +; Vector Table Mapped to Address 0 at Reset + AREA RESET, DATA, READONLY + EXPORT __Vectors + EXPORT __Vectors_End + EXPORT __Vectors_Size + +__Vectors DCD __initial_sp ; Top of Stack + DCD Reset_Handler ; Reset Handler + DCD NMI_Handler ; NMI Handler + DCD HardFault_Handler ; Hard Fault Handler + DCD MemManage_Handler ; MPU Fault Handler + DCD BusFault_Handler ; Bus Fault Handler + DCD UsageFault_Handler ; Usage Fault Handler + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD SVC_Handler ; SVCall Handler + DCD DebugMon_Handler ; Debug Monitor Handler + DCD 0 ; Reserved + DCD PendSV_Handler ; PendSV Handler + DCD SysTick_Handler ; SysTick Handler + + ; External Interrupts + DCD WWDG_IRQHandler ; Window Watchdog + DCD PVD_IRQHandler ; PVD through EXTI Line detect + DCD TAMPER_STAMP_IRQHandler ; Tamper and Time Stamp + DCD RTC_WKUP_IRQHandler ; RTC Wakeup + DCD FLASH_IRQHandler ; FLASH + DCD RCC_IRQHandler ; RCC + DCD EXTI0_IRQHandler ; EXTI Line 0 + DCD EXTI1_IRQHandler ; EXTI Line 1 + DCD EXTI2_IRQHandler ; EXTI Line 2 + DCD EXTI3_IRQHandler ; EXTI Line 3 + DCD EXTI4_IRQHandler ; EXTI Line 4 + DCD DMA1_Channel1_IRQHandler ; DMA1 Channel 1 + DCD DMA1_Channel2_IRQHandler ; DMA1 Channel 2 + DCD DMA1_Channel3_IRQHandler ; DMA1 Channel 3 + DCD DMA1_Channel4_IRQHandler ; DMA1 Channel 4 + DCD DMA1_Channel5_IRQHandler ; DMA1 Channel 5 + DCD DMA1_Channel6_IRQHandler ; DMA1 Channel 6 + DCD DMA1_Channel7_IRQHandler ; DMA1 Channel 7 + DCD ADC1_IRQHandler ; ADC1 + DCD USB_HP_IRQHandler ; USB High Priority + DCD USB_LP_IRQHandler ; USB Low Priority + DCD DAC_IRQHandler ; DAC + DCD COMP_IRQHandler ; COMP through EXTI Line + DCD EXTI9_5_IRQHandler ; EXTI Line 9..5 + DCD LCD_IRQHandler ; LCD + DCD TIM9_IRQHandler ; TIM9 + DCD TIM10_IRQHandler ; TIM10 + DCD TIM11_IRQHandler ; TIM11 + DCD TIM2_IRQHandler ; TIM2 + DCD TIM3_IRQHandler ; TIM3 + DCD TIM4_IRQHandler ; TIM4 + DCD I2C1_EV_IRQHandler ; I2C1 Event + DCD I2C1_ER_IRQHandler ; I2C1 Error + DCD I2C2_EV_IRQHandler ; I2C2 Event + DCD I2C2_ER_IRQHandler ; I2C2 Error + DCD SPI1_IRQHandler ; SPI1 + DCD SPI2_IRQHandler ; SPI2 + DCD USART1_IRQHandler ; USART1 + DCD USART2_IRQHandler ; USART2 + DCD USART3_IRQHandler ; USART3 + DCD EXTI15_10_IRQHandler ; EXTI Line 15..10 + DCD RTC_Alarm_IRQHandler ; RTC Alarm through EXTI Line + DCD USB_FS_WKUP_IRQHandler ; USB FS Wakeup from suspend + DCD TIM6_IRQHandler ; TIM6 + DCD TIM7_IRQHandler ; TIM7 + DCD SDIO_IRQHandler ; SDIO + DCD TIM5_IRQHandler ; TIM5 + DCD SPI3_IRQHandler ; SPI3 + DCD UART4_IRQHandler ; UART4 + DCD UART5_IRQHandler ; UART5 + DCD DMA2_Channel1_IRQHandler ; DMA2 Channel 1 + DCD DMA2_Channel2_IRQHandler ; DMA2 Channel 2 + DCD DMA2_Channel3_IRQHandler ; DMA2 Channel 3 + DCD DMA2_Channel4_IRQHandler ; DMA2 Channel 4 + DCD DMA2_Channel5_IRQHandler ; DMA2 Channel 5 + DCD AES_IRQHandler ; AES + DCD COMP_ACQ_IRQHandler ; Comparator Channel Acquisition + +__Vectors_End + +__Vectors_Size EQU __Vectors_End - __Vectors + + AREA |.text|, CODE, READONLY + +; Reset handler routine +Reset_Handler PROC + EXPORT Reset_Handler [WEAK] + IMPORT __main + IMPORT SystemInit + LDR R0, =SystemInit + BLX R0 + LDR R0, =__main + BX R0 + ENDP + +; Dummy Exception Handlers (infinite loops which can be modified) + +NMI_Handler PROC + EXPORT NMI_Handler [WEAK] + B . + ENDP +HardFault_Handler\ + PROC + EXPORT HardFault_Handler [WEAK] + B . + ENDP +MemManage_Handler\ + PROC + EXPORT MemManage_Handler [WEAK] + B . + ENDP +BusFault_Handler\ + PROC + EXPORT BusFault_Handler [WEAK] + B . + ENDP +UsageFault_Handler\ + PROC + EXPORT UsageFault_Handler [WEAK] + B . + ENDP +SVC_Handler PROC + EXPORT SVC_Handler [WEAK] + B . + ENDP +DebugMon_Handler\ + PROC + EXPORT DebugMon_Handler [WEAK] + B . + ENDP +PendSV_Handler PROC + EXPORT PendSV_Handler [WEAK] + B . + ENDP +SysTick_Handler PROC + EXPORT SysTick_Handler [WEAK] + B . + ENDP + +Default_Handler PROC + + EXPORT WWDG_IRQHandler [WEAK] + EXPORT PVD_IRQHandler [WEAK] + EXPORT TAMPER_STAMP_IRQHandler [WEAK] + EXPORT RTC_WKUP_IRQHandler [WEAK] + EXPORT FLASH_IRQHandler [WEAK] + EXPORT RCC_IRQHandler [WEAK] + EXPORT EXTI0_IRQHandler [WEAK] + EXPORT EXTI1_IRQHandler [WEAK] + EXPORT EXTI2_IRQHandler [WEAK] + EXPORT EXTI3_IRQHandler [WEAK] + EXPORT EXTI4_IRQHandler [WEAK] + EXPORT DMA1_Channel1_IRQHandler [WEAK] + EXPORT DMA1_Channel2_IRQHandler [WEAK] + EXPORT DMA1_Channel3_IRQHandler [WEAK] + EXPORT DMA1_Channel4_IRQHandler [WEAK] + EXPORT DMA1_Channel5_IRQHandler [WEAK] + EXPORT DMA1_Channel6_IRQHandler [WEAK] + EXPORT DMA1_Channel7_IRQHandler [WEAK] + EXPORT ADC1_IRQHandler [WEAK] + EXPORT USB_HP_IRQHandler [WEAK] + EXPORT USB_LP_IRQHandler [WEAK] + EXPORT DAC_IRQHandler [WEAK] + EXPORT COMP_IRQHandler [WEAK] + EXPORT EXTI9_5_IRQHandler [WEAK] + EXPORT LCD_IRQHandler [WEAK] + EXPORT TIM9_IRQHandler [WEAK] + EXPORT TIM10_IRQHandler [WEAK] + EXPORT TIM11_IRQHandler [WEAK] + EXPORT TIM2_IRQHandler [WEAK] + EXPORT TIM3_IRQHandler [WEAK] + EXPORT TIM4_IRQHandler [WEAK] + EXPORT I2C1_EV_IRQHandler [WEAK] + EXPORT I2C1_ER_IRQHandler [WEAK] + EXPORT I2C2_EV_IRQHandler [WEAK] + EXPORT I2C2_ER_IRQHandler [WEAK] + EXPORT SPI1_IRQHandler [WEAK] + EXPORT SPI2_IRQHandler [WEAK] + EXPORT USART1_IRQHandler [WEAK] + EXPORT USART2_IRQHandler [WEAK] + EXPORT USART3_IRQHandler [WEAK] + EXPORT EXTI15_10_IRQHandler [WEAK] + EXPORT RTC_Alarm_IRQHandler [WEAK] + EXPORT USB_FS_WKUP_IRQHandler [WEAK] + EXPORT TIM6_IRQHandler [WEAK] + EXPORT TIM7_IRQHandler [WEAK] + EXPORT SDIO_IRQHandler [WEAK] + EXPORT TIM5_IRQHandler [WEAK] + EXPORT SPI3_IRQHandler [WEAK] + EXPORT UART4_IRQHandler [WEAK] + EXPORT UART5_IRQHandler [WEAK] + EXPORT DMA2_Channel1_IRQHandler [WEAK] + EXPORT DMA2_Channel2_IRQHandler [WEAK] + EXPORT DMA2_Channel3_IRQHandler [WEAK] + EXPORT DMA2_Channel4_IRQHandler [WEAK] + EXPORT DMA2_Channel5_IRQHandler [WEAK] + EXPORT AES_IRQHandler [WEAK] + EXPORT COMP_ACQ_IRQHandler [WEAK] + +WWDG_IRQHandler +PVD_IRQHandler +TAMPER_STAMP_IRQHandler +RTC_WKUP_IRQHandler +FLASH_IRQHandler +RCC_IRQHandler +EXTI0_IRQHandler +EXTI1_IRQHandler +EXTI2_IRQHandler +EXTI3_IRQHandler +EXTI4_IRQHandler +DMA1_Channel1_IRQHandler +DMA1_Channel2_IRQHandler +DMA1_Channel3_IRQHandler +DMA1_Channel4_IRQHandler +DMA1_Channel5_IRQHandler +DMA1_Channel6_IRQHandler +DMA1_Channel7_IRQHandler +ADC1_IRQHandler +USB_HP_IRQHandler +USB_LP_IRQHandler +DAC_IRQHandler +COMP_IRQHandler +EXTI9_5_IRQHandler +LCD_IRQHandler +TIM9_IRQHandler +TIM10_IRQHandler +TIM11_IRQHandler +TIM2_IRQHandler +TIM3_IRQHandler +TIM4_IRQHandler +I2C1_EV_IRQHandler +I2C1_ER_IRQHandler +I2C2_EV_IRQHandler +I2C2_ER_IRQHandler +SPI1_IRQHandler +SPI2_IRQHandler +USART1_IRQHandler +USART2_IRQHandler +USART3_IRQHandler +EXTI15_10_IRQHandler +RTC_Alarm_IRQHandler +USB_FS_WKUP_IRQHandler +TIM6_IRQHandler +TIM7_IRQHandler +SDIO_IRQHandler +TIM5_IRQHandler +SPI3_IRQHandler +UART4_IRQHandler +UART5_IRQHandler +DMA2_Channel1_IRQHandler +DMA2_Channel2_IRQHandler +DMA2_Channel3_IRQHandler +DMA2_Channel4_IRQHandler +DMA2_Channel5_IRQHandler +AES_IRQHandler +COMP_ACQ_IRQHandler + + B . + + ENDP + + ALIGN + +;******************************************************************************* +; User Stack and Heap initialization +;******************************************************************************* + IF :DEF:__MICROLIB + + EXPORT __initial_sp + EXPORT __heap_base + EXPORT __heap_limit + + ELSE + + IMPORT __use_two_region_memory + EXPORT __user_initial_stackheap + +__user_initial_stackheap + + LDR R0, = Heap_Mem + LDR R1, =(Stack_Mem + Stack_Size) + LDR R2, = (Heap_Mem + Heap_Size) + LDR R3, = Stack_Mem + BX LR + + ALIGN + + ENDIF + + END + +;************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE***** diff --git a/Libraries/CMSIS/Device/ST/STM32L1xx/Source/Templates/arm/startup_stm32l1xx_md.s b/Libraries/CMSIS/Device/ST/STM32L1xx/Source/Templates/arm/startup_stm32l1xx_md.s new file mode 100644 index 0000000..4fc8d5f --- /dev/null +++ b/Libraries/CMSIS/Device/ST/STM32L1xx/Source/Templates/arm/startup_stm32l1xx_md.s @@ -0,0 +1,319 @@ +;******************** (C) COPYRIGHT 2012 STMicroelectronics ******************** +;* File Name : startup_stm32l1xx_md.s +;* Author : MCD Application Team +;* Version : V1.1.1 +;* Date : 09-March-2012 +;* Description : STM32L1xx Ultra Low Power Medium-density Devices vector +;* table for MDK-ARM toolchain. +;* This module performs: +;* - Set the initial SP +;* - Set the initial PC == Reset_Handler +;* - Set the vector table entries with the exceptions ISR address +;* - Branches to __main in the C library (which eventually +;* calls main()). +;* After Reset the CortexM3 processor is in Thread mode, +;* priority is Privileged, and the Stack is set to Main. +;* <<< Use Configuration Wizard in Context Menu >>> +;******************************************************************************* +; +; Licensed under MCD-ST Liberty SW License Agreement V2, (the "License"); +; You may not use this file except in compliance with the License. +; You may obtain a copy of the License at: +; +; http://www.st.com/software_license_agreement_liberty_v2 +; +; Unless required by applicable law or agreed to in writing, software +; distributed under the License is distributed on an "AS IS" BASIS, +; WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +; See the License for the specific language governing permissions and +; limitations under the License. +; +;******************************************************************************* + +; Amount of memory (in bytes) allocated for Stack +; Tailor this value to your application needs +; Stack Configuration +; Stack Size (in Bytes) <0x0-0xFFFFFFFF:8> +; + +Stack_Size EQU 0x00000400 + + AREA STACK, NOINIT, READWRITE, ALIGN=3 +Stack_Mem SPACE Stack_Size +__initial_sp + + +; Heap Configuration +; Heap Size (in Bytes) <0x0-0xFFFFFFFF:8> +; + +Heap_Size EQU 0x00000200 + + AREA HEAP, NOINIT, READWRITE, ALIGN=3 +__heap_base +Heap_Mem SPACE Heap_Size +__heap_limit + + PRESERVE8 + THUMB + + +; Vector Table Mapped to Address 0 at Reset + AREA RESET, DATA, READONLY + EXPORT __Vectors + EXPORT __Vectors_End + EXPORT __Vectors_Size + +__Vectors DCD __initial_sp ; Top of Stack + DCD Reset_Handler ; Reset Handler + DCD NMI_Handler ; NMI Handler + DCD HardFault_Handler ; Hard Fault Handler + DCD MemManage_Handler ; MPU Fault Handler + DCD BusFault_Handler ; Bus Fault Handler + DCD UsageFault_Handler ; Usage Fault Handler + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD SVC_Handler ; SVCall Handler + DCD DebugMon_Handler ; Debug Monitor Handler + DCD 0 ; Reserved + DCD PendSV_Handler ; PendSV Handler + DCD SysTick_Handler ; SysTick Handler + + ; External Interrupts + DCD WWDG_IRQHandler ; Window Watchdog + DCD PVD_IRQHandler ; PVD through EXTI Line detect + DCD TAMPER_STAMP_IRQHandler ; Tamper and Time Stamp + DCD RTC_WKUP_IRQHandler ; RTC Wakeup + DCD FLASH_IRQHandler ; FLASH + DCD RCC_IRQHandler ; RCC + DCD EXTI0_IRQHandler ; EXTI Line 0 + DCD EXTI1_IRQHandler ; EXTI Line 1 + DCD EXTI2_IRQHandler ; EXTI Line 2 + DCD EXTI3_IRQHandler ; EXTI Line 3 + DCD EXTI4_IRQHandler ; EXTI Line 4 + DCD DMA1_Channel1_IRQHandler ; DMA1 Channel 1 + DCD DMA1_Channel2_IRQHandler ; DMA1 Channel 2 + DCD DMA1_Channel3_IRQHandler ; DMA1 Channel 3 + DCD DMA1_Channel4_IRQHandler ; DMA1 Channel 4 + DCD DMA1_Channel5_IRQHandler ; DMA1 Channel 5 + DCD DMA1_Channel6_IRQHandler ; DMA1 Channel 6 + DCD DMA1_Channel7_IRQHandler ; DMA1 Channel 7 + DCD ADC1_IRQHandler ; ADC1 + DCD USB_HP_IRQHandler ; USB High Priority + DCD USB_LP_IRQHandler ; USB Low Priority + DCD DAC_IRQHandler ; DAC + DCD COMP_IRQHandler ; COMP through EXTI Line + DCD EXTI9_5_IRQHandler ; EXTI Line 9..5 + DCD LCD_IRQHandler ; LCD + DCD TIM9_IRQHandler ; TIM9 + DCD TIM10_IRQHandler ; TIM10 + DCD TIM11_IRQHandler ; TIM11 + DCD TIM2_IRQHandler ; TIM2 + DCD TIM3_IRQHandler ; TIM3 + DCD TIM4_IRQHandler ; TIM4 + DCD I2C1_EV_IRQHandler ; I2C1 Event + DCD I2C1_ER_IRQHandler ; I2C1 Error + DCD I2C2_EV_IRQHandler ; I2C2 Event + DCD I2C2_ER_IRQHandler ; I2C2 Error + DCD SPI1_IRQHandler ; SPI1 + DCD SPI2_IRQHandler ; SPI2 + DCD USART1_IRQHandler ; USART1 + DCD USART2_IRQHandler ; USART2 + DCD USART3_IRQHandler ; USART3 + DCD EXTI15_10_IRQHandler ; EXTI Line 15..10 + DCD RTC_Alarm_IRQHandler ; RTC Alarm through EXTI Line + DCD USB_FS_WKUP_IRQHandler ; USB FS Wakeup from suspend + DCD TIM6_IRQHandler ; TIM6 + DCD TIM7_IRQHandler ; TIM7 +__Vectors_End + +__Vectors_Size EQU __Vectors_End - __Vectors + + AREA |.text|, CODE, READONLY + +; Reset handler routine +Reset_Handler PROC + EXPORT Reset_Handler [WEAK] + IMPORT __main + IMPORT SystemInit + LDR R0, =SystemInit + BLX R0 + LDR R0, =__main + BX R0 + ENDP + +; Dummy Exception Handlers (infinite loops which can be modified) + +NMI_Handler PROC + EXPORT NMI_Handler [WEAK] + B . + ENDP +HardFault_Handler\ + PROC + EXPORT HardFault_Handler [WEAK] + B . + ENDP +MemManage_Handler\ + PROC + EXPORT MemManage_Handler [WEAK] + B . + ENDP +BusFault_Handler\ + PROC + EXPORT BusFault_Handler [WEAK] + B . + ENDP +UsageFault_Handler\ + PROC + EXPORT UsageFault_Handler [WEAK] + B . + ENDP +SVC_Handler PROC + EXPORT SVC_Handler [WEAK] + B . + ENDP +DebugMon_Handler\ + PROC + EXPORT DebugMon_Handler [WEAK] + B . + ENDP +PendSV_Handler PROC + EXPORT PendSV_Handler [WEAK] + B . + ENDP +SysTick_Handler PROC + EXPORT SysTick_Handler [WEAK] + B . + ENDP + +Default_Handler PROC + + EXPORT WWDG_IRQHandler [WEAK] + EXPORT PVD_IRQHandler [WEAK] + EXPORT TAMPER_STAMP_IRQHandler [WEAK] + EXPORT RTC_WKUP_IRQHandler [WEAK] + EXPORT FLASH_IRQHandler [WEAK] + EXPORT RCC_IRQHandler [WEAK] + EXPORT EXTI0_IRQHandler [WEAK] + EXPORT EXTI1_IRQHandler [WEAK] + EXPORT EXTI2_IRQHandler [WEAK] + EXPORT EXTI3_IRQHandler [WEAK] + EXPORT EXTI4_IRQHandler [WEAK] + EXPORT DMA1_Channel1_IRQHandler [WEAK] + EXPORT DMA1_Channel2_IRQHandler [WEAK] + EXPORT DMA1_Channel3_IRQHandler [WEAK] + EXPORT DMA1_Channel4_IRQHandler [WEAK] + EXPORT DMA1_Channel5_IRQHandler [WEAK] + EXPORT DMA1_Channel6_IRQHandler [WEAK] + EXPORT DMA1_Channel7_IRQHandler [WEAK] + EXPORT ADC1_IRQHandler [WEAK] + EXPORT USB_HP_IRQHandler [WEAK] + EXPORT USB_LP_IRQHandler [WEAK] + EXPORT DAC_IRQHandler [WEAK] + EXPORT COMP_IRQHandler [WEAK] + EXPORT EXTI9_5_IRQHandler [WEAK] + EXPORT LCD_IRQHandler [WEAK] + EXPORT TIM9_IRQHandler [WEAK] + EXPORT TIM10_IRQHandler [WEAK] + EXPORT TIM11_IRQHandler [WEAK] + EXPORT TIM2_IRQHandler [WEAK] + EXPORT TIM3_IRQHandler [WEAK] + EXPORT TIM4_IRQHandler [WEAK] + EXPORT I2C1_EV_IRQHandler [WEAK] + EXPORT I2C1_ER_IRQHandler [WEAK] + EXPORT I2C2_EV_IRQHandler [WEAK] + EXPORT I2C2_ER_IRQHandler [WEAK] + EXPORT SPI1_IRQHandler [WEAK] + EXPORT SPI2_IRQHandler [WEAK] + EXPORT USART1_IRQHandler [WEAK] + EXPORT USART2_IRQHandler [WEAK] + EXPORT USART3_IRQHandler [WEAK] + EXPORT EXTI15_10_IRQHandler [WEAK] + EXPORT RTC_Alarm_IRQHandler [WEAK] + EXPORT USB_FS_WKUP_IRQHandler [WEAK] + EXPORT TIM6_IRQHandler [WEAK] + EXPORT TIM7_IRQHandler [WEAK] + +WWDG_IRQHandler +PVD_IRQHandler +TAMPER_STAMP_IRQHandler +RTC_WKUP_IRQHandler +FLASH_IRQHandler +RCC_IRQHandler +EXTI0_IRQHandler +EXTI1_IRQHandler +EXTI2_IRQHandler +EXTI3_IRQHandler +EXTI4_IRQHandler +DMA1_Channel1_IRQHandler +DMA1_Channel2_IRQHandler +DMA1_Channel3_IRQHandler +DMA1_Channel4_IRQHandler +DMA1_Channel5_IRQHandler +DMA1_Channel6_IRQHandler +DMA1_Channel7_IRQHandler +ADC1_IRQHandler +USB_HP_IRQHandler +USB_LP_IRQHandler +DAC_IRQHandler +COMP_IRQHandler +EXTI9_5_IRQHandler +LCD_IRQHandler +TIM9_IRQHandler +TIM10_IRQHandler +TIM11_IRQHandler +TIM2_IRQHandler +TIM3_IRQHandler +TIM4_IRQHandler +I2C1_EV_IRQHandler +I2C1_ER_IRQHandler +I2C2_EV_IRQHandler +I2C2_ER_IRQHandler +SPI1_IRQHandler +SPI2_IRQHandler +USART1_IRQHandler +USART2_IRQHandler +USART3_IRQHandler +EXTI15_10_IRQHandler +RTC_Alarm_IRQHandler +USB_FS_WKUP_IRQHandler +TIM6_IRQHandler +TIM7_IRQHandler + + B . + + ENDP + + ALIGN + +;******************************************************************************* +; User Stack and Heap initialization +;******************************************************************************* + IF :DEF:__MICROLIB + + EXPORT __initial_sp + EXPORT __heap_base + EXPORT __heap_limit + + ELSE + + IMPORT __use_two_region_memory + EXPORT __user_initial_stackheap + +__user_initial_stackheap + + LDR R0, = Heap_Mem + LDR R1, =(Stack_Mem + Stack_Size) + LDR R2, = (Heap_Mem + Heap_Size) + LDR R3, = Stack_Mem + BX LR + + ALIGN + + ENDIF + + END + +;************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE***** diff --git a/Libraries/CMSIS/Device/ST/STM32L1xx/Source/Templates/arm/startup_stm32l1xx_mdp.s b/Libraries/CMSIS/Device/ST/STM32L1xx/Source/Templates/arm/startup_stm32l1xx_mdp.s new file mode 100644 index 0000000..8ea1e39 --- /dev/null +++ b/Libraries/CMSIS/Device/ST/STM32L1xx/Source/Templates/arm/startup_stm32l1xx_mdp.s @@ -0,0 +1,350 @@ +;******************** (C) COPYRIGHT 2012 STMicroelectronics ******************** +;* File Name : startup_stm32l1xx_mdp.s +;* Author : MCD Application Team +;* Version : V1.1.1 +;* Date : 09-March-2012 +;* Description : STM32L1xx Ultra Low Power Medium-density Plus Devices vector +;* table for MDK-ARM toolchain. +;* This module performs: +;* - Set the initial SP +;* - Set the initial PC == Reset_Handler +;* - Set the vector table entries with the exceptions ISR address +;* - Branches to __main in the C library (which eventually +;* calls main()). +;* After Reset the CortexM3 processor is in Thread mode, +;* priority is Privileged, and the Stack is set to Main. +;* <<< Use Configuration Wizard in Context Menu >>> +;******************************************************************************* +; +; Licensed under MCD-ST Liberty SW License Agreement V2, (the "License"); +; You may not use this file except in compliance with the License. +; You may obtain a copy of the License at: +; +; http://www.st.com/software_license_agreement_liberty_v2 +; +; Unless required by applicable law or agreed to in writing, software +; distributed under the License is distributed on an "AS IS" BASIS, +; WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +; See the License for the specific language governing permissions and +; limitations under the License. +; +;******************************************************************************* + +; Amount of memory (in bytes) allocated for Stack +; Tailor this value to your application needs +; Stack Configuration +; Stack Size (in Bytes) <0x0-0xFFFFFFFF:8> +; + +Stack_Size EQU 0x00000400 + + AREA STACK, NOINIT, READWRITE, ALIGN=3 +Stack_Mem SPACE Stack_Size +__initial_sp + + +; Heap Configuration +; Heap Size (in Bytes) <0x0-0xFFFFFFFF:8> +; + +Heap_Size EQU 0x00000200 + + AREA HEAP, NOINIT, READWRITE, ALIGN=3 +__heap_base +Heap_Mem SPACE Heap_Size +__heap_limit + + PRESERVE8 + THUMB + + +; Vector Table Mapped to Address 0 at Reset + AREA RESET, DATA, READONLY + EXPORT __Vectors + EXPORT __Vectors_End + EXPORT __Vectors_Size + +__Vectors DCD __initial_sp ; Top of Stack + DCD Reset_Handler ; Reset Handler + DCD NMI_Handler ; NMI Handler + DCD HardFault_Handler ; Hard Fault Handler + DCD MemManage_Handler ; MPU Fault Handler + DCD BusFault_Handler ; Bus Fault Handler + DCD UsageFault_Handler ; Usage Fault Handler + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD SVC_Handler ; SVCall Handler + DCD DebugMon_Handler ; Debug Monitor Handler + DCD 0 ; Reserved + DCD PendSV_Handler ; PendSV Handler + DCD SysTick_Handler ; SysTick Handler + + ; External Interrupts + DCD WWDG_IRQHandler ; Window Watchdog + DCD PVD_IRQHandler ; PVD through EXTI Line detect + DCD TAMPER_STAMP_IRQHandler ; Tamper and Time Stamp + DCD RTC_WKUP_IRQHandler ; RTC Wakeup + DCD FLASH_IRQHandler ; FLASH + DCD RCC_IRQHandler ; RCC + DCD EXTI0_IRQHandler ; EXTI Line 0 + DCD EXTI1_IRQHandler ; EXTI Line 1 + DCD EXTI2_IRQHandler ; EXTI Line 2 + DCD EXTI3_IRQHandler ; EXTI Line 3 + DCD EXTI4_IRQHandler ; EXTI Line 4 + DCD DMA1_Channel1_IRQHandler ; DMA1 Channel 1 + DCD DMA1_Channel2_IRQHandler ; DMA1 Channel 2 + DCD DMA1_Channel3_IRQHandler ; DMA1 Channel 3 + DCD DMA1_Channel4_IRQHandler ; DMA1 Channel 4 + DCD DMA1_Channel5_IRQHandler ; DMA1 Channel 5 + DCD DMA1_Channel6_IRQHandler ; DMA1 Channel 6 + DCD DMA1_Channel7_IRQHandler ; DMA1 Channel 7 + DCD ADC1_IRQHandler ; ADC1 + DCD USB_HP_IRQHandler ; USB High Priority + DCD USB_LP_IRQHandler ; USB Low Priority + DCD DAC_IRQHandler ; DAC + DCD COMP_IRQHandler ; COMP through EXTI Line + DCD EXTI9_5_IRQHandler ; EXTI Line 9..5 + DCD LCD_IRQHandler ; LCD + DCD TIM9_IRQHandler ; TIM9 + DCD TIM10_IRQHandler ; TIM10 + DCD TIM11_IRQHandler ; TIM11 + DCD TIM2_IRQHandler ; TIM2 + DCD TIM3_IRQHandler ; TIM3 + DCD TIM4_IRQHandler ; TIM4 + DCD I2C1_EV_IRQHandler ; I2C1 Event + DCD I2C1_ER_IRQHandler ; I2C1 Error + DCD I2C2_EV_IRQHandler ; I2C2 Event + DCD I2C2_ER_IRQHandler ; I2C2 Error + DCD SPI1_IRQHandler ; SPI1 + DCD SPI2_IRQHandler ; SPI2 + DCD USART1_IRQHandler ; USART1 + DCD USART2_IRQHandler ; USART2 + DCD USART3_IRQHandler ; USART3 + DCD EXTI15_10_IRQHandler ; EXTI Line 15..10 + DCD RTC_Alarm_IRQHandler ; RTC Alarm through EXTI Line + DCD USB_FS_WKUP_IRQHandler ; USB FS Wakeup from suspend + DCD TIM6_IRQHandler ; TIM6 + DCD TIM7_IRQHandler ; TIM7 + DCD 0 ; Reserved + DCD TIM5_IRQHandler ; TIM5 + DCD SPI3_IRQHandler ; SPI3 + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD DMA2_Channel1_IRQHandler ; DMA2 Channel 1 + DCD DMA2_Channel2_IRQHandler ; DMA2 Channel 2 + DCD DMA2_Channel3_IRQHandler ; DMA2 Channel 3 + DCD DMA2_Channel4_IRQHandler ; DMA2 Channel 4 + DCD DMA2_Channel5_IRQHandler ; DMA2 Channel 5 + DCD AES_IRQHandler ; AES + DCD COMP_ACQ_IRQHandler ; Comparator Channel Acquisition + +__Vectors_End + +__Vectors_Size EQU __Vectors_End - __Vectors + + AREA |.text|, CODE, READONLY + +; Reset handler routine +Reset_Handler PROC + EXPORT Reset_Handler [WEAK] + IMPORT __main + IMPORT SystemInit + LDR R0, =SystemInit + BLX R0 + LDR R0, =__main + BX R0 + ENDP + +; Dummy Exception Handlers (infinite loops which can be modified) + +NMI_Handler PROC + EXPORT NMI_Handler [WEAK] + B . + ENDP +HardFault_Handler\ + PROC + EXPORT HardFault_Handler [WEAK] + B . + ENDP +MemManage_Handler\ + PROC + EXPORT MemManage_Handler [WEAK] + B . + ENDP +BusFault_Handler\ + PROC + EXPORT BusFault_Handler [WEAK] + B . + ENDP +UsageFault_Handler\ + PROC + EXPORT UsageFault_Handler [WEAK] + B . + ENDP +SVC_Handler PROC + EXPORT SVC_Handler [WEAK] + B . + ENDP +DebugMon_Handler\ + PROC + EXPORT DebugMon_Handler [WEAK] + B . + ENDP +PendSV_Handler PROC + EXPORT PendSV_Handler [WEAK] + B . + ENDP +SysTick_Handler PROC + EXPORT SysTick_Handler [WEAK] + B . + ENDP + +Default_Handler PROC + + EXPORT WWDG_IRQHandler [WEAK] + EXPORT PVD_IRQHandler [WEAK] + EXPORT TAMPER_STAMP_IRQHandler [WEAK] + EXPORT RTC_WKUP_IRQHandler [WEAK] + EXPORT FLASH_IRQHandler [WEAK] + EXPORT RCC_IRQHandler [WEAK] + EXPORT EXTI0_IRQHandler [WEAK] + EXPORT EXTI1_IRQHandler [WEAK] + EXPORT EXTI2_IRQHandler [WEAK] + EXPORT EXTI3_IRQHandler [WEAK] + EXPORT EXTI4_IRQHandler [WEAK] + EXPORT DMA1_Channel1_IRQHandler [WEAK] + EXPORT DMA1_Channel2_IRQHandler [WEAK] + EXPORT DMA1_Channel3_IRQHandler [WEAK] + EXPORT DMA1_Channel4_IRQHandler [WEAK] + EXPORT DMA1_Channel5_IRQHandler [WEAK] + EXPORT DMA1_Channel6_IRQHandler [WEAK] + EXPORT DMA1_Channel7_IRQHandler [WEAK] + EXPORT ADC1_IRQHandler [WEAK] + EXPORT USB_HP_IRQHandler [WEAK] + EXPORT USB_LP_IRQHandler [WEAK] + EXPORT DAC_IRQHandler [WEAK] + EXPORT COMP_IRQHandler [WEAK] + EXPORT EXTI9_5_IRQHandler [WEAK] + EXPORT LCD_IRQHandler [WEAK] + EXPORT TIM9_IRQHandler [WEAK] + EXPORT TIM10_IRQHandler [WEAK] + EXPORT TIM11_IRQHandler [WEAK] + EXPORT TIM2_IRQHandler [WEAK] + EXPORT TIM3_IRQHandler [WEAK] + EXPORT TIM4_IRQHandler [WEAK] + EXPORT I2C1_EV_IRQHandler [WEAK] + EXPORT I2C1_ER_IRQHandler [WEAK] + EXPORT I2C2_EV_IRQHandler [WEAK] + EXPORT I2C2_ER_IRQHandler [WEAK] + EXPORT SPI1_IRQHandler [WEAK] + EXPORT SPI2_IRQHandler [WEAK] + EXPORT USART1_IRQHandler [WEAK] + EXPORT USART2_IRQHandler [WEAK] + EXPORT USART3_IRQHandler [WEAK] + EXPORT EXTI15_10_IRQHandler [WEAK] + EXPORT RTC_Alarm_IRQHandler [WEAK] + EXPORT USB_FS_WKUP_IRQHandler [WEAK] + EXPORT TIM6_IRQHandler [WEAK] + EXPORT TIM7_IRQHandler [WEAK] + EXPORT TIM5_IRQHandler [WEAK] + EXPORT SPI3_IRQHandler [WEAK] + EXPORT DMA2_Channel1_IRQHandler [WEAK] + EXPORT DMA2_Channel2_IRQHandler [WEAK] + EXPORT DMA2_Channel3_IRQHandler [WEAK] + EXPORT DMA2_Channel4_IRQHandler [WEAK] + EXPORT DMA2_Channel5_IRQHandler [WEAK] + EXPORT AES_IRQHandler [WEAK] + EXPORT COMP_ACQ_IRQHandler [WEAK] + +WWDG_IRQHandler +PVD_IRQHandler +TAMPER_STAMP_IRQHandler +RTC_WKUP_IRQHandler +FLASH_IRQHandler +RCC_IRQHandler +EXTI0_IRQHandler +EXTI1_IRQHandler +EXTI2_IRQHandler +EXTI3_IRQHandler +EXTI4_IRQHandler +DMA1_Channel1_IRQHandler +DMA1_Channel2_IRQHandler +DMA1_Channel3_IRQHandler +DMA1_Channel4_IRQHandler +DMA1_Channel5_IRQHandler +DMA1_Channel6_IRQHandler +DMA1_Channel7_IRQHandler +ADC1_IRQHandler +USB_HP_IRQHandler +USB_LP_IRQHandler +DAC_IRQHandler +COMP_IRQHandler +EXTI9_5_IRQHandler +LCD_IRQHandler +TIM9_IRQHandler +TIM10_IRQHandler +TIM11_IRQHandler +TIM2_IRQHandler +TIM3_IRQHandler +TIM4_IRQHandler +I2C1_EV_IRQHandler +I2C1_ER_IRQHandler +I2C2_EV_IRQHandler +I2C2_ER_IRQHandler +SPI1_IRQHandler +SPI2_IRQHandler +USART1_IRQHandler +USART2_IRQHandler +USART3_IRQHandler +EXTI15_10_IRQHandler +RTC_Alarm_IRQHandler +USB_FS_WKUP_IRQHandler +TIM6_IRQHandler +TIM7_IRQHandler +TIM5_IRQHandler +SPI3_IRQHandler +DMA2_Channel1_IRQHandler +DMA2_Channel2_IRQHandler +DMA2_Channel3_IRQHandler +DMA2_Channel4_IRQHandler +DMA2_Channel5_IRQHandler +AES_IRQHandler +COMP_ACQ_IRQHandler + + B . + + ENDP + + ALIGN + +;******************************************************************************* +; User Stack and Heap initialization +;******************************************************************************* + IF :DEF:__MICROLIB + + EXPORT __initial_sp + EXPORT __heap_base + EXPORT __heap_limit + + ELSE + + IMPORT __use_two_region_memory + EXPORT __user_initial_stackheap + +__user_initial_stackheap + + LDR R0, = Heap_Mem + LDR R1, =(Stack_Mem + Stack_Size) + LDR R2, = (Heap_Mem + Heap_Size) + LDR R3, = Stack_Mem + BX LR + + ALIGN + + ENDIF + + END + +;************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE***** diff --git a/Libraries/CMSIS/Device/ST/STM32L1xx/Source/Templates/gcc_ride7/startup_stm32l1xx_hd.s b/Libraries/CMSIS/Device/ST/STM32L1xx/Source/Templates/gcc_ride7/startup_stm32l1xx_hd.s new file mode 100644 index 0000000..d1e0458 --- /dev/null +++ b/Libraries/CMSIS/Device/ST/STM32L1xx/Source/Templates/gcc_ride7/startup_stm32l1xx_hd.s @@ -0,0 +1,419 @@ +/** + ****************************************************************************** + * @file startup_stm32l1xx_hd.s + * @author MCD Application Team + * @version V1.1.1 + * @date 09-March-2012 + * @brief STM32L1xx Ultra Low Power High-density Devices vector table for + * RIDE7 toolchain. + * This module performs: + * - Set the initial SP + * - Set the initial PC == Reset_Handler, + * - Set the vector table entries with the exceptions ISR address + * - Branches to main in the C library (which eventually + * calls main()). + * After Reset the Cortex-M3 processor is in Thread mode, + * priority is Privileged, and the Stack is set to Main. + ****************************************************************************** + * @attention + * + *

    © COPYRIGHT 2012 STMicroelectronics

    + * + * Licensed under MCD-ST Liberty SW License Agreement V2, (the "License"); + * You may not use this file except in compliance with the License. + * You may obtain a copy of the License at: + * + * http://www.st.com/software_license_agreement_liberty_v2 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, + * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + * + ****************************************************************************** + */ + + .syntax unified + .cpu cortex-m3 + .fpu softvfp + .thumb + +.global g_pfnVectors +.global Default_Handler + +/* start address for the initialization values of the .data section. +defined in linker script */ +.word _sidata +/* start address for the .data section. defined in linker script */ +.word _sdata +/* end address for the .data section. defined in linker script */ +.word _edata +/* start address for the .bss section. defined in linker script */ +.word _sbss +/* end address for the .bss section. defined in linker script */ +.word _ebss + +.equ BootRAM, 0xF108F85F +/** + * @brief This is the code that gets called when the processor first + * starts execution following a reset event. Only the absolutely + * necessary set is performed, after which the application + * supplied main() routine is called. + * @param None + * @retval : None +*/ + + .section .text.Reset_Handler + .weak Reset_Handler + .type Reset_Handler, %function +Reset_Handler: + +/* Copy the data segment initializers from flash to SRAM */ + movs r1, #0 + b LoopCopyDataInit + +CopyDataInit: + ldr r3, =_sidata + ldr r3, [r3, r1] + str r3, [r0, r1] + adds r1, r1, #4 + +LoopCopyDataInit: + ldr r0, =_sdata + ldr r3, =_edata + adds r2, r0, r1 + cmp r2, r3 + bcc CopyDataInit + ldr r2, =_sbss + b LoopFillZerobss +/* Zero fill the bss segment. */ +FillZerobss: + movs r3, #0 + str r3, [r2], #4 + +LoopFillZerobss: + ldr r3, = _ebss + cmp r2, r3 + bcc FillZerobss +/* Call the clock system intitialization function.*/ + bl SystemInit +/* Call the application's entry point.*/ + bl main + bx lr +.size Reset_Handler, .-Reset_Handler + +/** + * @brief This is the code that gets called when the processor receives an + * unexpected interrupt. This simply enters an infinite loop, preserving + * the system state for examination by a debugger. + * + * @param None + * @retval None +*/ + .section .text.Default_Handler,"ax",%progbits +Default_Handler: +Infinite_Loop: + b Infinite_Loop + .size Default_Handler, .-Default_Handler +/******************************************************************************* +* +* The minimal vector table for a Cortex M3. Note that the proper constructs +* must be placed on this to ensure that it ends up at physical address +* 0x0000.0000. +*******************************************************************************/ + .section .isr_vector,"a",%progbits + .type g_pfnVectors, %object + .size g_pfnVectors, .-g_pfnVectors + + +g_pfnVectors: + .word _estack + .word Reset_Handler + .word NMI_Handler + .word HardFault_Handler + .word MemManage_Handler + .word BusFault_Handler + .word UsageFault_Handler + .word 0 + .word 0 + .word 0 + .word 0 + .word SVC_Handler + .word DebugMon_Handler + .word 0 + .word PendSV_Handler + .word SysTick_Handler + .word WWDG_IRQHandler + .word PVD_IRQHandler + .word TAMPER_STAMP_IRQHandler + .word RTC_WKUP_IRQHandler + .word FLASH_IRQHandler + .word RCC_IRQHandler + .word EXTI0_IRQHandler + .word EXTI1_IRQHandler + .word EXTI2_IRQHandler + .word EXTI3_IRQHandler + .word EXTI4_IRQHandler + .word DMA1_Channel1_IRQHandler + .word DMA1_Channel2_IRQHandler + .word DMA1_Channel3_IRQHandler + .word DMA1_Channel4_IRQHandler + .word DMA1_Channel5_IRQHandler + .word DMA1_Channel6_IRQHandler + .word DMA1_Channel7_IRQHandler + .word ADC1_IRQHandler + .word USB_HP_IRQHandler + .word USB_LP_IRQHandler + .word DAC_IRQHandler + .word COMP_IRQHandler + .word EXTI9_5_IRQHandler + .word LCD_IRQHandler + .word TIM9_IRQHandler + .word TIM10_IRQHandler + .word TIM11_IRQHandler + .word TIM2_IRQHandler + .word TIM3_IRQHandler + .word TIM4_IRQHandler + .word I2C1_EV_IRQHandler + .word I2C1_ER_IRQHandler + .word I2C2_EV_IRQHandler + .word I2C2_ER_IRQHandler + .word SPI1_IRQHandler + .word SPI2_IRQHandler + .word USART1_IRQHandler + .word USART2_IRQHandler + .word USART3_IRQHandler + .word EXTI15_10_IRQHandler + .word RTC_Alarm_IRQHandler + .word USB_FS_WKUP_IRQHandler + .word TIM6_IRQHandler + .word TIM7_IRQHandler + .word SDIO_IRQHandler + .word TIM5_IRQHandler + .word SPI3_IRQHandler + .word UART4_IRQHandler + .word UART5_IRQHandler + .word DMA2_Channel1_IRQHandler + .word DMA2_Channel2_IRQHandler + .word DMA2_Channel3_IRQHandler + .word DMA2_Channel4_IRQHandler + .word DMA2_Channel5_IRQHandler + .word AES_IRQHandler + .word COMP_ACQ_IRQHandler + .word 0 + .word 0 + .word 0 + .word 0 + .word 0 + .word BootRAM /* @0x108. This is for boot in RAM mode for + STM32L15x ULtra Low Power High-density devices. */ + +/******************************************************************************* +* +* Provide weak aliases for each Exception handler to the Default_Handler. +* As they are weak aliases, any function with the same name will override +* this definition. +* +*******************************************************************************/ + + .weak NMI_Handler + .thumb_set NMI_Handler,Default_Handler + + .weak HardFault_Handler + .thumb_set HardFault_Handler,Default_Handler + + .weak MemManage_Handler + .thumb_set MemManage_Handler,Default_Handler + + .weak BusFault_Handler + .thumb_set BusFault_Handler,Default_Handler + + .weak UsageFault_Handler + .thumb_set UsageFault_Handler,Default_Handler + + .weak SVC_Handler + .thumb_set SVC_Handler,Default_Handler + + .weak DebugMon_Handler + .thumb_set DebugMon_Handler,Default_Handler + + .weak PendSV_Handler + .thumb_set PendSV_Handler,Default_Handler + + .weak SysTick_Handler + .thumb_set SysTick_Handler,Default_Handler + + .weak WWDG_IRQHandler + .thumb_set WWDG_IRQHandler,Default_Handler + + .weak PVD_IRQHandler + .thumb_set PVD_IRQHandler,Default_Handler + + .weak TAMPER_STAMP_IRQHandler + .thumb_set TAMPER_STAMP_IRQHandler,Default_Handler + + .weak RTC_WKUP_IRQHandler + .thumb_set RTC_WKUP_IRQHandler,Default_Handler + + .weak FLASH_IRQHandler + .thumb_set FLASH_IRQHandler,Default_Handler + + .weak RCC_IRQHandler + .thumb_set RCC_IRQHandler,Default_Handler + + .weak EXTI0_IRQHandler + .thumb_set EXTI0_IRQHandler,Default_Handler + + .weak EXTI1_IRQHandler + .thumb_set EXTI1_IRQHandler,Default_Handler + + .weak EXTI2_IRQHandler + .thumb_set EXTI2_IRQHandler,Default_Handler + + .weak EXTI3_IRQHandler + .thumb_set EXTI3_IRQHandler,Default_Handler + + .weak EXTI4_IRQHandler + .thumb_set EXTI4_IRQHandler,Default_Handler + + .weak DMA1_Channel1_IRQHandler + .thumb_set DMA1_Channel1_IRQHandler,Default_Handler + + .weak DMA1_Channel2_IRQHandler + .thumb_set DMA1_Channel2_IRQHandler,Default_Handler + + .weak DMA1_Channel3_IRQHandler + .thumb_set DMA1_Channel3_IRQHandler,Default_Handler + + .weak DMA1_Channel4_IRQHandler + .thumb_set DMA1_Channel4_IRQHandler,Default_Handler + + .weak DMA1_Channel5_IRQHandler + .thumb_set DMA1_Channel5_IRQHandler,Default_Handler + + .weak DMA1_Channel6_IRQHandler + .thumb_set DMA1_Channel6_IRQHandler,Default_Handler + + .weak DMA1_Channel7_IRQHandler + .thumb_set DMA1_Channel7_IRQHandler,Default_Handler + + .weak ADC1_IRQHandler + .thumb_set ADC1_IRQHandler,Default_Handler + + .weak USB_HP_IRQHandler + .thumb_set USB_HP_IRQHandler,Default_Handler + + .weak USB_LP_IRQHandler + .thumb_set USB_LP_IRQHandler,Default_Handler + + .weak DAC_IRQHandler + .thumb_set DAC_IRQHandler,Default_Handler + + .weak COMP_IRQHandler + .thumb_set COMP_IRQHandler,Default_Handler + + .weak EXTI9_5_IRQHandler + .thumb_set EXTI9_5_IRQHandler,Default_Handler + + .weak LCD_IRQHandler + .thumb_set LCD_IRQHandler,Default_Handler + + .weak TIM9_IRQHandler + .thumb_set TIM9_IRQHandler,Default_Handler + + .weak TIM10_IRQHandler + .thumb_set TIM10_IRQHandler,Default_Handler + + .weak TIM11_IRQHandler + .thumb_set TIM11_IRQHandler,Default_Handler + + .weak TIM2_IRQHandler + .thumb_set TIM2_IRQHandler,Default_Handler + + .weak TIM3_IRQHandler + .thumb_set TIM3_IRQHandler,Default_Handler + + .weak TIM4_IRQHandler + .thumb_set TIM4_IRQHandler,Default_Handler + + .weak I2C1_EV_IRQHandler + .thumb_set I2C1_EV_IRQHandler,Default_Handler + + .weak I2C1_ER_IRQHandler + .thumb_set I2C1_ER_IRQHandler,Default_Handler + + .weak I2C2_EV_IRQHandler + .thumb_set I2C2_EV_IRQHandler,Default_Handler + + .weak I2C2_ER_IRQHandler + .thumb_set I2C2_ER_IRQHandler,Default_Handler + + .weak SPI1_IRQHandler + .thumb_set SPI1_IRQHandler,Default_Handler + + .weak SPI2_IRQHandler + .thumb_set SPI2_IRQHandler,Default_Handler + + .weak USART1_IRQHandler + .thumb_set USART1_IRQHandler,Default_Handler + + .weak USART2_IRQHandler + .thumb_set USART2_IRQHandler,Default_Handler + + .weak USART3_IRQHandler + .thumb_set USART3_IRQHandler,Default_Handler + + .weak EXTI15_10_IRQHandler + .thumb_set EXTI15_10_IRQHandler,Default_Handler + + .weak RTC_Alarm_IRQHandler + .thumb_set RTC_Alarm_IRQHandler,Default_Handler + + .weak USB_FS_WKUP_IRQHandler + .thumb_set USB_FS_WKUP_IRQHandler,Default_Handler + + .weak TIM6_IRQHandler + .thumb_set TIM6_IRQHandler,Default_Handler + + .weak TIM7_IRQHandler + .thumb_set TIM7_IRQHandler,Default_Handler + + .weak SDIO_IRQHandler + .thumb_set SDIO_IRQHandler,Default_Handler + + .weak TIM5_IRQHandler + .thumb_set TIM5_IRQHandler,Default_Handler + + .weak SPI3_IRQHandler + .thumb_set SPI3_IRQHandler,Default_Handler + + .weak UART4_IRQHandler + .thumb_set UART4_IRQHandler,Default_Handler + + .weak UART5_IRQHandler + .thumb_set UART5_IRQHandler,Default_Handler + + .weak DMA2_Channel1_IRQHandler + .thumb_set DMA2_Channel1_IRQHandler,Default_Handler + + .weak DMA2_Channel2_IRQHandler + .thumb_set DMA2_Channel2_IRQHandler,Default_Handler + + .weak DMA2_Channel3_IRQHandler + .thumb_set DMA2_Channel3_IRQHandler,Default_Handler + + .weak DMA2_Channel4_IRQHandler + .thumb_set DMA2_Channel4_IRQHandler,Default_Handler + + .weak DMA2_Channel5_IRQHandler + .thumb_set DMA2_Channel5_IRQHandler,Default_Handler + + .weak AES_IRQHandler + .thumb_set AES_IRQHandler,Default_Handler + + .weak COMP_ACQ_IRQHandler + .thumb_set COMP_ACQ_IRQHandler,Default_Handler + +/************************* (C) COPYRIGHT STMicroelectronics *****END OF FILE***/ + diff --git a/Libraries/CMSIS/Device/ST/STM32L1xx/Source/Templates/gcc_ride7/startup_stm32l1xx_md.s b/Libraries/CMSIS/Device/ST/STM32L1xx/Source/Templates/gcc_ride7/startup_stm32l1xx_md.s new file mode 100644 index 0000000..bd72ed0 --- /dev/null +++ b/Libraries/CMSIS/Device/ST/STM32L1xx/Source/Templates/gcc_ride7/startup_stm32l1xx_md.s @@ -0,0 +1,371 @@ +/** + ****************************************************************************** + * @file startup_stm32l1xx_md.s + * @author MCD Application Team + * @version V1.1.1 + * @date 09-March-2012 + * @brief STM32L1xx Ultra Low Power Medium-density Devices vector table for + * RIDE7 toolchain. + * This module performs: + * - Set the initial SP + * - Set the initial PC == Reset_Handler, + * - Set the vector table entries with the exceptions ISR address + * - Branches to main in the C library (which eventually + * calls main()). + * After Reset the Cortex-M3 processor is in Thread mode, + * priority is Privileged, and the Stack is set to Main. + ****************************************************************************** + * @attention + * + *

    © COPYRIGHT 2012 STMicroelectronics

    + * + * Licensed under MCD-ST Liberty SW License Agreement V2, (the "License"); + * You may not use this file except in compliance with the License. + * You may obtain a copy of the License at: + * + * http://www.st.com/software_license_agreement_liberty_v2 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, + * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + * + ****************************************************************************** + */ + + .syntax unified + .cpu cortex-m3 + .fpu softvfp + .thumb + +.global g_pfnVectors +.global Default_Handler + +/* start address for the initialization values of the .data section. +defined in linker script */ +.word _sidata +/* start address for the .data section. defined in linker script */ +.word _sdata +/* end address for the .data section. defined in linker script */ +.word _edata +/* start address for the .bss section. defined in linker script */ +.word _sbss +/* end address for the .bss section. defined in linker script */ +.word _ebss + +.equ BootRAM, 0xF108F85F +/** + * @brief This is the code that gets called when the processor first + * starts execution following a reset event. Only the absolutely + * necessary set is performed, after which the application + * supplied main() routine is called. + * @param None + * @retval : None +*/ + + .section .text.Reset_Handler + .weak Reset_Handler + .type Reset_Handler, %function +Reset_Handler: + +/* Copy the data segment initializers from flash to SRAM */ + movs r1, #0 + b LoopCopyDataInit + +CopyDataInit: + ldr r3, =_sidata + ldr r3, [r3, r1] + str r3, [r0, r1] + adds r1, r1, #4 + +LoopCopyDataInit: + ldr r0, =_sdata + ldr r3, =_edata + adds r2, r0, r1 + cmp r2, r3 + bcc CopyDataInit + ldr r2, =_sbss + b LoopFillZerobss +/* Zero fill the bss segment. */ +FillZerobss: + movs r3, #0 + str r3, [r2], #4 + +LoopFillZerobss: + ldr r3, = _ebss + cmp r2, r3 + bcc FillZerobss +/* Call the clock system intitialization function.*/ + bl SystemInit +/* Call the application's entry point.*/ + bl main + bx lr +.size Reset_Handler, .-Reset_Handler + +/** + * @brief This is the code that gets called when the processor receives an + * unexpected interrupt. This simply enters an infinite loop, preserving + * the system state for examination by a debugger. + * + * @param None + * @retval None +*/ + .section .text.Default_Handler,"ax",%progbits +Default_Handler: +Infinite_Loop: + b Infinite_Loop + .size Default_Handler, .-Default_Handler +/******************************************************************************* +* +* The minimal vector table for a Cortex M3. Note that the proper constructs +* must be placed on this to ensure that it ends up at physical address +* 0x0000.0000. +*******************************************************************************/ + .section .isr_vector,"a",%progbits + .type g_pfnVectors, %object + .size g_pfnVectors, .-g_pfnVectors + + +g_pfnVectors: + .word _estack + .word Reset_Handler + .word NMI_Handler + .word HardFault_Handler + .word MemManage_Handler + .word BusFault_Handler + .word UsageFault_Handler + .word 0 + .word 0 + .word 0 + .word 0 + .word SVC_Handler + .word DebugMon_Handler + .word 0 + .word PendSV_Handler + .word SysTick_Handler + .word WWDG_IRQHandler + .word PVD_IRQHandler + .word TAMPER_STAMP_IRQHandler + .word RTC_WKUP_IRQHandler + .word FLASH_IRQHandler + .word RCC_IRQHandler + .word EXTI0_IRQHandler + .word EXTI1_IRQHandler + .word EXTI2_IRQHandler + .word EXTI3_IRQHandler + .word EXTI4_IRQHandler + .word DMA1_Channel1_IRQHandler + .word DMA1_Channel2_IRQHandler + .word DMA1_Channel3_IRQHandler + .word DMA1_Channel4_IRQHandler + .word DMA1_Channel5_IRQHandler + .word DMA1_Channel6_IRQHandler + .word DMA1_Channel7_IRQHandler + .word ADC1_IRQHandler + .word USB_HP_IRQHandler + .word USB_LP_IRQHandler + .word DAC_IRQHandler + .word COMP_IRQHandler + .word EXTI9_5_IRQHandler + .word LCD_IRQHandler + .word TIM9_IRQHandler + .word TIM10_IRQHandler + .word TIM11_IRQHandler + .word TIM2_IRQHandler + .word TIM3_IRQHandler + .word TIM4_IRQHandler + .word I2C1_EV_IRQHandler + .word I2C1_ER_IRQHandler + .word I2C2_EV_IRQHandler + .word I2C2_ER_IRQHandler + .word SPI1_IRQHandler + .word SPI2_IRQHandler + .word USART1_IRQHandler + .word USART2_IRQHandler + .word USART3_IRQHandler + .word EXTI15_10_IRQHandler + .word RTC_Alarm_IRQHandler + .word USB_FS_WKUP_IRQHandler + .word TIM6_IRQHandler + .word TIM7_IRQHandler + .word 0 + .word 0 + .word 0 + .word 0 + .word 0 + .word BootRAM /* @0x108. This is for boot in RAM mode for + STM32L15x ULtra Low Power Medium-density devices. */ + +/******************************************************************************* +* +* Provide weak aliases for each Exception handler to the Default_Handler. +* As they are weak aliases, any function with the same name will override +* this definition. +* +*******************************************************************************/ + + .weak NMI_Handler + .thumb_set NMI_Handler,Default_Handler + + .weak HardFault_Handler + .thumb_set HardFault_Handler,Default_Handler + + .weak MemManage_Handler + .thumb_set MemManage_Handler,Default_Handler + + .weak BusFault_Handler + .thumb_set BusFault_Handler,Default_Handler + + .weak UsageFault_Handler + .thumb_set UsageFault_Handler,Default_Handler + + .weak SVC_Handler + .thumb_set SVC_Handler,Default_Handler + + .weak DebugMon_Handler + .thumb_set DebugMon_Handler,Default_Handler + + .weak PendSV_Handler + .thumb_set PendSV_Handler,Default_Handler + + .weak SysTick_Handler + .thumb_set SysTick_Handler,Default_Handler + + .weak WWDG_IRQHandler + .thumb_set WWDG_IRQHandler,Default_Handler + + .weak PVD_IRQHandler + .thumb_set PVD_IRQHandler,Default_Handler + + .weak TAMPER_STAMP_IRQHandler + .thumb_set TAMPER_STAMP_IRQHandler,Default_Handler + + .weak RTC_WKUP_IRQHandler + .thumb_set RTC_WKUP_IRQHandler,Default_Handler + + .weak FLASH_IRQHandler + .thumb_set FLASH_IRQHandler,Default_Handler + + .weak RCC_IRQHandler + .thumb_set RCC_IRQHandler,Default_Handler + + .weak EXTI0_IRQHandler + .thumb_set EXTI0_IRQHandler,Default_Handler + + .weak EXTI1_IRQHandler + .thumb_set EXTI1_IRQHandler,Default_Handler + + .weak EXTI2_IRQHandler + .thumb_set EXTI2_IRQHandler,Default_Handler + + .weak EXTI3_IRQHandler + .thumb_set EXTI3_IRQHandler,Default_Handler + + .weak EXTI4_IRQHandler + .thumb_set EXTI4_IRQHandler,Default_Handler + + .weak DMA1_Channel1_IRQHandler + .thumb_set DMA1_Channel1_IRQHandler,Default_Handler + + .weak DMA1_Channel2_IRQHandler + .thumb_set DMA1_Channel2_IRQHandler,Default_Handler + + .weak DMA1_Channel3_IRQHandler + .thumb_set DMA1_Channel3_IRQHandler,Default_Handler + + .weak DMA1_Channel4_IRQHandler + .thumb_set DMA1_Channel4_IRQHandler,Default_Handler + + .weak DMA1_Channel5_IRQHandler + .thumb_set DMA1_Channel5_IRQHandler,Default_Handler + + .weak DMA1_Channel6_IRQHandler + .thumb_set DMA1_Channel6_IRQHandler,Default_Handler + + .weak DMA1_Channel7_IRQHandler + .thumb_set DMA1_Channel7_IRQHandler,Default_Handler + + .weak ADC1_IRQHandler + .thumb_set ADC1_IRQHandler,Default_Handler + + .weak USB_HP_IRQHandler + .thumb_set USB_HP_IRQHandler,Default_Handler + + .weak USB_LP_IRQHandler + .thumb_set USB_LP_IRQHandler,Default_Handler + + .weak DAC_IRQHandler + .thumb_set DAC_IRQHandler,Default_Handler + + .weak COMP_IRQHandler + .thumb_set COMP_IRQHandler,Default_Handler + + .weak EXTI9_5_IRQHandler + .thumb_set EXTI9_5_IRQHandler,Default_Handler + + .weak LCD_IRQHandler + .thumb_set LCD_IRQHandler,Default_Handler + + .weak TIM9_IRQHandler + .thumb_set TIM9_IRQHandler,Default_Handler + + .weak TIM10_IRQHandler + .thumb_set TIM10_IRQHandler,Default_Handler + + .weak TIM11_IRQHandler + .thumb_set TIM11_IRQHandler,Default_Handler + + .weak TIM2_IRQHandler + .thumb_set TIM2_IRQHandler,Default_Handler + + .weak TIM3_IRQHandler + .thumb_set TIM3_IRQHandler,Default_Handler + + .weak TIM4_IRQHandler + .thumb_set TIM4_IRQHandler,Default_Handler + + .weak I2C1_EV_IRQHandler + .thumb_set I2C1_EV_IRQHandler,Default_Handler + + .weak I2C1_ER_IRQHandler + .thumb_set I2C1_ER_IRQHandler,Default_Handler + + .weak I2C2_EV_IRQHandler + .thumb_set I2C2_EV_IRQHandler,Default_Handler + + .weak I2C2_ER_IRQHandler + .thumb_set I2C2_ER_IRQHandler,Default_Handler + + .weak SPI1_IRQHandler + .thumb_set SPI1_IRQHandler,Default_Handler + + .weak SPI2_IRQHandler + .thumb_set SPI2_IRQHandler,Default_Handler + + .weak USART1_IRQHandler + .thumb_set USART1_IRQHandler,Default_Handler + + .weak USART2_IRQHandler + .thumb_set USART2_IRQHandler,Default_Handler + + .weak USART3_IRQHandler + .thumb_set USART3_IRQHandler,Default_Handler + + .weak EXTI15_10_IRQHandler + .thumb_set EXTI15_10_IRQHandler,Default_Handler + + .weak RTC_Alarm_IRQHandler + .thumb_set RTC_Alarm_IRQHandler,Default_Handler + + .weak USB_FS_WKUP_IRQHandler + .thumb_set USB_FS_WKUP_IRQHandler,Default_Handler + + .weak TIM6_IRQHandler + .thumb_set TIM6_IRQHandler,Default_Handler + + .weak TIM7_IRQHandler + .thumb_set TIM7_IRQHandler,Default_Handler + +/************************* (C) COPYRIGHT STMicroelectronics *****END OF FILE***/ + diff --git a/Libraries/CMSIS/Device/ST/STM32L1xx/Source/Templates/gcc_ride7/startup_stm32l1xx_mdp.s b/Libraries/CMSIS/Device/ST/STM32L1xx/Source/Templates/gcc_ride7/startup_stm32l1xx_mdp.s new file mode 100644 index 0000000..d9f3587 --- /dev/null +++ b/Libraries/CMSIS/Device/ST/STM32L1xx/Source/Templates/gcc_ride7/startup_stm32l1xx_mdp.s @@ -0,0 +1,410 @@ +/** + ****************************************************************************** + * @file startup_stm32l1xx_mdp.s + * @author MCD Application Team + * @version V1.1.1 + * @date 09-March-2012 + * @brief STM32L1xx Ultra Low Power Medium-density Plus Devices vector table + * for RIDE7 toolchain. + * This module performs: + * - Set the initial SP + * - Set the initial PC == Reset_Handler, + * - Set the vector table entries with the exceptions ISR address + * - Branches to main in the C library (which eventually + * calls main()). + * After Reset the Cortex-M3 processor is in Thread mode, + * priority is Privileged, and the Stack is set to Main. + ****************************************************************************** + * @attention + * + *

    © COPYRIGHT 2012 STMicroelectronics

    + * + * Licensed under MCD-ST Liberty SW License Agreement V2, (the "License"); + * You may not use this file except in compliance with the License. + * You may obtain a copy of the License at: + * + * http://www.st.com/software_license_agreement_liberty_v2 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, + * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + * + ****************************************************************************** + */ + + .syntax unified + .cpu cortex-m3 + .fpu softvfp + .thumb + +.global g_pfnVectors +.global Default_Handler + +/* start address for the initialization values of the .data section. +defined in linker script */ +.word _sidata +/* start address for the .data section. defined in linker script */ +.word _sdata +/* end address for the .data section. defined in linker script */ +.word _edata +/* start address for the .bss section. defined in linker script */ +.word _sbss +/* end address for the .bss section. defined in linker script */ +.word _ebss + +.equ BootRAM, 0xF108F85F +/** + * @brief This is the code that gets called when the processor first + * starts execution following a reset event. Only the absolutely + * necessary set is performed, after which the application + * supplied main() routine is called. + * @param None + * @retval : None +*/ + + .section .text.Reset_Handler + .weak Reset_Handler + .type Reset_Handler, %function +Reset_Handler: + +/* Copy the data segment initializers from flash to SRAM */ + movs r1, #0 + b LoopCopyDataInit + +CopyDataInit: + ldr r3, =_sidata + ldr r3, [r3, r1] + str r3, [r0, r1] + adds r1, r1, #4 + +LoopCopyDataInit: + ldr r0, =_sdata + ldr r3, =_edata + adds r2, r0, r1 + cmp r2, r3 + bcc CopyDataInit + ldr r2, =_sbss + b LoopFillZerobss +/* Zero fill the bss segment. */ +FillZerobss: + movs r3, #0 + str r3, [r2], #4 + +LoopFillZerobss: + ldr r3, = _ebss + cmp r2, r3 + bcc FillZerobss +/* Call the clock system intitialization function.*/ + bl SystemInit +/* Call the application's entry point.*/ + bl main + bx lr +.size Reset_Handler, .-Reset_Handler + +/** + * @brief This is the code that gets called when the processor receives an + * unexpected interrupt. This simply enters an infinite loop, preserving + * the system state for examination by a debugger. + * + * @param None + * @retval None +*/ + .section .text.Default_Handler,"ax",%progbits +Default_Handler: +Infinite_Loop: + b Infinite_Loop + .size Default_Handler, .-Default_Handler +/******************************************************************************* +* +* The minimal vector table for a Cortex M3. Note that the proper constructs +* must be placed on this to ensure that it ends up at physical address +* 0x0000.0000. +*******************************************************************************/ + .section .isr_vector,"a",%progbits + .type g_pfnVectors, %object + .size g_pfnVectors, .-g_pfnVectors + + +g_pfnVectors: + .word _estack + .word Reset_Handler + .word NMI_Handler + .word HardFault_Handler + .word MemManage_Handler + .word BusFault_Handler + .word UsageFault_Handler + .word 0 + .word 0 + .word 0 + .word 0 + .word SVC_Handler + .word DebugMon_Handler + .word 0 + .word PendSV_Handler + .word SysTick_Handler + .word WWDG_IRQHandler + .word PVD_IRQHandler + .word TAMPER_STAMP_IRQHandler + .word RTC_WKUP_IRQHandler + .word FLASH_IRQHandler + .word RCC_IRQHandler + .word EXTI0_IRQHandler + .word EXTI1_IRQHandler + .word EXTI2_IRQHandler + .word EXTI3_IRQHandler + .word EXTI4_IRQHandler + .word DMA1_Channel1_IRQHandler + .word DMA1_Channel2_IRQHandler + .word DMA1_Channel3_IRQHandler + .word DMA1_Channel4_IRQHandler + .word DMA1_Channel5_IRQHandler + .word DMA1_Channel6_IRQHandler + .word DMA1_Channel7_IRQHandler + .word ADC1_IRQHandler + .word USB_HP_IRQHandler + .word USB_LP_IRQHandler + .word DAC_IRQHandler + .word COMP_IRQHandler + .word EXTI9_5_IRQHandler + .word LCD_IRQHandler + .word TIM9_IRQHandler + .word TIM10_IRQHandler + .word TIM11_IRQHandler + .word TIM2_IRQHandler + .word TIM3_IRQHandler + .word TIM4_IRQHandler + .word I2C1_EV_IRQHandler + .word I2C1_ER_IRQHandler + .word I2C2_EV_IRQHandler + .word I2C2_ER_IRQHandler + .word SPI1_IRQHandler + .word SPI2_IRQHandler + .word USART1_IRQHandler + .word USART2_IRQHandler + .word USART3_IRQHandler + .word EXTI15_10_IRQHandler + .word RTC_Alarm_IRQHandler + .word USB_FS_WKUP_IRQHandler + .word TIM6_IRQHandler + .word TIM7_IRQHandler + .word 0 + .word TIM5_IRQHandler + .word SPI3_IRQHandler + .word 0 + .word 0 + .word DMA2_Channel1_IRQHandler + .word DMA2_Channel2_IRQHandler + .word DMA2_Channel3_IRQHandler + .word DMA2_Channel4_IRQHandler + .word DMA2_Channel5_IRQHandler + .word AES_IRQHandler + .word COMP_ACQ_IRQHandler + .word 0 + .word 0 + .word 0 + .word 0 + .word 0 + .word BootRAM /* @0x108. This is for boot in RAM mode for + STM32L15x ULtra Low Power Medium-density Plus devices. */ + +/******************************************************************************* +* +* Provide weak aliases for each Exception handler to the Default_Handler. +* As they are weak aliases, any function with the same name will override +* this definition. +* +*******************************************************************************/ + + .weak NMI_Handler + .thumb_set NMI_Handler,Default_Handler + + .weak HardFault_Handler + .thumb_set HardFault_Handler,Default_Handler + + .weak MemManage_Handler + .thumb_set MemManage_Handler,Default_Handler + + .weak BusFault_Handler + .thumb_set BusFault_Handler,Default_Handler + + .weak UsageFault_Handler + .thumb_set UsageFault_Handler,Default_Handler + + .weak SVC_Handler + .thumb_set SVC_Handler,Default_Handler + + .weak DebugMon_Handler + .thumb_set DebugMon_Handler,Default_Handler + + .weak PendSV_Handler + .thumb_set PendSV_Handler,Default_Handler + + .weak SysTick_Handler + .thumb_set SysTick_Handler,Default_Handler + + .weak WWDG_IRQHandler + .thumb_set WWDG_IRQHandler,Default_Handler + + .weak PVD_IRQHandler + .thumb_set PVD_IRQHandler,Default_Handler + + .weak TAMPER_STAMP_IRQHandler + .thumb_set TAMPER_STAMP_IRQHandler,Default_Handler + + .weak RTC_WKUP_IRQHandler + .thumb_set RTC_WKUP_IRQHandler,Default_Handler + + .weak FLASH_IRQHandler + .thumb_set FLASH_IRQHandler,Default_Handler + + .weak RCC_IRQHandler + .thumb_set RCC_IRQHandler,Default_Handler + + .weak EXTI0_IRQHandler + .thumb_set EXTI0_IRQHandler,Default_Handler + + .weak EXTI1_IRQHandler + .thumb_set EXTI1_IRQHandler,Default_Handler + + .weak EXTI2_IRQHandler + .thumb_set EXTI2_IRQHandler,Default_Handler + + .weak EXTI3_IRQHandler + .thumb_set EXTI3_IRQHandler,Default_Handler + + .weak EXTI4_IRQHandler + .thumb_set EXTI4_IRQHandler,Default_Handler + + .weak DMA1_Channel1_IRQHandler + .thumb_set DMA1_Channel1_IRQHandler,Default_Handler + + .weak DMA1_Channel2_IRQHandler + .thumb_set DMA1_Channel2_IRQHandler,Default_Handler + + .weak DMA1_Channel3_IRQHandler + .thumb_set DMA1_Channel3_IRQHandler,Default_Handler + + .weak DMA1_Channel4_IRQHandler + .thumb_set DMA1_Channel4_IRQHandler,Default_Handler + + .weak DMA1_Channel5_IRQHandler + .thumb_set DMA1_Channel5_IRQHandler,Default_Handler + + .weak DMA1_Channel6_IRQHandler + .thumb_set DMA1_Channel6_IRQHandler,Default_Handler + + .weak DMA1_Channel7_IRQHandler + .thumb_set DMA1_Channel7_IRQHandler,Default_Handler + + .weak ADC1_IRQHandler + .thumb_set ADC1_IRQHandler,Default_Handler + + .weak USB_HP_IRQHandler + .thumb_set USB_HP_IRQHandler,Default_Handler + + .weak USB_LP_IRQHandler + .thumb_set USB_LP_IRQHandler,Default_Handler + + .weak DAC_IRQHandler + .thumb_set DAC_IRQHandler,Default_Handler + + .weak COMP_IRQHandler + .thumb_set COMP_IRQHandler,Default_Handler + + .weak EXTI9_5_IRQHandler + .thumb_set EXTI9_5_IRQHandler,Default_Handler + + .weak LCD_IRQHandler + .thumb_set LCD_IRQHandler,Default_Handler + + .weak TIM9_IRQHandler + .thumb_set TIM9_IRQHandler,Default_Handler + + .weak TIM10_IRQHandler + .thumb_set TIM10_IRQHandler,Default_Handler + + .weak TIM11_IRQHandler + .thumb_set TIM11_IRQHandler,Default_Handler + + .weak TIM2_IRQHandler + .thumb_set TIM2_IRQHandler,Default_Handler + + .weak TIM3_IRQHandler + .thumb_set TIM3_IRQHandler,Default_Handler + + .weak TIM4_IRQHandler + .thumb_set TIM4_IRQHandler,Default_Handler + + .weak I2C1_EV_IRQHandler + .thumb_set I2C1_EV_IRQHandler,Default_Handler + + .weak I2C1_ER_IRQHandler + .thumb_set I2C1_ER_IRQHandler,Default_Handler + + .weak I2C2_EV_IRQHandler + .thumb_set I2C2_EV_IRQHandler,Default_Handler + + .weak I2C2_ER_IRQHandler + .thumb_set I2C2_ER_IRQHandler,Default_Handler + + .weak SPI1_IRQHandler + .thumb_set SPI1_IRQHandler,Default_Handler + + .weak SPI2_IRQHandler + .thumb_set SPI2_IRQHandler,Default_Handler + + .weak USART1_IRQHandler + .thumb_set USART1_IRQHandler,Default_Handler + + .weak USART2_IRQHandler + .thumb_set USART2_IRQHandler,Default_Handler + + .weak USART3_IRQHandler + .thumb_set USART3_IRQHandler,Default_Handler + + .weak EXTI15_10_IRQHandler + .thumb_set EXTI15_10_IRQHandler,Default_Handler + + .weak RTC_Alarm_IRQHandler + .thumb_set RTC_Alarm_IRQHandler,Default_Handler + + .weak USB_FS_WKUP_IRQHandler + .thumb_set USB_FS_WKUP_IRQHandler,Default_Handler + + .weak TIM6_IRQHandler + .thumb_set TIM6_IRQHandler,Default_Handler + + .weak TIM7_IRQHandler + .thumb_set TIM7_IRQHandler,Default_Handler + + .weak TIM5_IRQHandler + .thumb_set TIM5_IRQHandler,Default_Handler + + .weak SPI3_IRQHandler + .thumb_set SPI3_IRQHandler,Default_Handler + + .weak DMA2_Channel1_IRQHandler + .thumb_set DMA2_Channel1_IRQHandler,Default_Handler + + .weak DMA2_Channel2_IRQHandler + .thumb_set DMA2_Channel2_IRQHandler,Default_Handler + + .weak DMA2_Channel3_IRQHandler + .thumb_set DMA2_Channel3_IRQHandler,Default_Handler + + .weak DMA2_Channel4_IRQHandler + .thumb_set DMA2_Channel4_IRQHandler,Default_Handler + + .weak DMA2_Channel5_IRQHandler + .thumb_set DMA2_Channel5_IRQHandler,Default_Handler + + .weak AES_IRQHandler + .thumb_set AES_IRQHandler,Default_Handler + + .weak COMP_ACQ_IRQHandler + .thumb_set COMP_ACQ_IRQHandler,Default_Handler + +/************************* (C) COPYRIGHT STMicroelectronics *****END OF FILE***/ + diff --git a/Libraries/CMSIS/Device/ST/STM32L1xx/Source/Templates/iar/startup_stm32l1xx_hd.s b/Libraries/CMSIS/Device/ST/STM32L1xx/Source/Templates/iar/startup_stm32l1xx_hd.s new file mode 100644 index 0000000..a92913e --- /dev/null +++ b/Libraries/CMSIS/Device/ST/STM32L1xx/Source/Templates/iar/startup_stm32l1xx_hd.s @@ -0,0 +1,544 @@ +;/******************** (C) COPYRIGHT 2012 STMicroelectronics ******************** +;* File Name : startup_stm32l1xx_hd.s +;* Author : MCD Application Team +;* Version : V1.1.1 +;* Date : 09-March-2012 +;* Description : STM32L1xx Ultra Low Power High-density Devices vector +;* table for EWARM toolchain. +;* This module performs: +;* - Set the initial SP +;* - Set the initial PC == __iar_program_start, +;* - Set the vector table entries with the exceptions ISR +;* address. +;* After Reset the Cortex-M3 processor is in Thread mode, +;* priority is Privileged, and the Stack is set to Main. +;******************************************************************************** +;* +;* Licensed under MCD-ST Liberty SW License Agreement V2, (the "License"); +;* You may not use this file except in compliance with the License. +;* You may obtain a copy of the License at: +;* +;* http://www.st.com/software_license_agreement_liberty_v2 +;* +;* Unless required by applicable law or agreed to in writing, software +;* distributed under the License is distributed on an "AS IS" BASIS, +;* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +;* See the License for the specific language governing permissions and +;* limitations under the License. +;* +;*******************************************************************************/ +; +; +; The modules in this file are included in the libraries, and may be replaced +; by any user-defined modules that define the PUBLIC symbol _program_start or +; a user defined start symbol. +; To override the cstartup defined in the library, simply add your modified +; version to the workbench project. +; +; The vector table is normally located at address 0. +; When debugging in RAM, it can be located in RAM, aligned to at least 2^6. +; The name "__vector_table" has special meaning for C-SPY: +; it is where the SP start value is found, and the NVIC vector +; table register (VTOR) is initialized to this address if != 0. +; +; Cortex-M version +; + + MODULE ?cstartup + + ;; Forward declaration of sections. + SECTION CSTACK:DATA:NOROOT(3) + + SECTION .intvec:CODE:NOROOT(2) + + EXTERN __iar_program_start + EXTERN SystemInit + PUBLIC __vector_table + + DATA +__vector_table + DCD sfe(CSTACK) + DCD Reset_Handler ; Reset Handler + + DCD NMI_Handler ; NMI Handler + DCD HardFault_Handler ; Hard Fault Handler + DCD MemManage_Handler ; MPU Fault Handler + DCD BusFault_Handler ; Bus Fault Handler + DCD UsageFault_Handler ; Usage Fault Handler + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD SVC_Handler ; SVCall Handler + DCD DebugMon_Handler ; Debug Monitor Handler + DCD 0 ; Reserved + DCD PendSV_Handler ; PendSV Handler + DCD SysTick_Handler ; SysTick Handler + + ; External Interrupts + DCD WWDG_IRQHandler ; Window Watchdog + DCD PVD_IRQHandler ; PVD through EXTI Line detect + DCD TAMPER_STAMP_IRQHandler ; Tamper and Time Stamp + DCD RTC_WKUP_IRQHandler ; RTC Wakeup + DCD FLASH_IRQHandler ; FLASH + DCD RCC_IRQHandler ; RCC + DCD EXTI0_IRQHandler ; EXTI Line 0 + DCD EXTI1_IRQHandler ; EXTI Line 1 + DCD EXTI2_IRQHandler ; EXTI Line 2 + DCD EXTI3_IRQHandler ; EXTI Line 3 + DCD EXTI4_IRQHandler ; EXTI Line 4 + DCD DMA1_Channel1_IRQHandler ; DMA1 Channel 1 + DCD DMA1_Channel2_IRQHandler ; DMA1 Channel 2 + DCD DMA1_Channel3_IRQHandler ; DMA1 Channel 3 + DCD DMA1_Channel4_IRQHandler ; DMA1 Channel 4 + DCD DMA1_Channel5_IRQHandler ; DMA1 Channel 5 + DCD DMA1_Channel6_IRQHandler ; DMA1 Channel 6 + DCD DMA1_Channel7_IRQHandler ; DMA1 Channel 7 + DCD ADC1_IRQHandler ; ADC1 + DCD USB_HP_IRQHandler ; USB High Priority + DCD USB_LP_IRQHandler ; USB Low Priority + DCD DAC_IRQHandler ; DAC + DCD COMP_IRQHandler ; COMP through EXTI Line + DCD EXTI9_5_IRQHandler ; EXTI Line 9..5 + DCD LCD_IRQHandler ; LCD + DCD TIM9_IRQHandler ; TIM9 + DCD TIM10_IRQHandler ; TIM10 + DCD TIM11_IRQHandler ; TIM11 + DCD TIM2_IRQHandler ; TIM2 + DCD TIM3_IRQHandler ; TIM3 + DCD TIM4_IRQHandler ; TIM4 + DCD I2C1_EV_IRQHandler ; I2C1 Event + DCD I2C1_ER_IRQHandler ; I2C1 Error + DCD I2C2_EV_IRQHandler ; I2C2 Event + DCD I2C2_ER_IRQHandler ; I2C2 Error + DCD SPI1_IRQHandler ; SPI1 + DCD SPI2_IRQHandler ; SPI2 + DCD USART1_IRQHandler ; USART1 + DCD USART2_IRQHandler ; USART2 + DCD USART3_IRQHandler ; USART3 + DCD EXTI15_10_IRQHandler ; EXTI Line 15..10 + DCD RTC_Alarm_IRQHandler ; RTC Alarm through EXTI Line + DCD USB_FS_WKUP_IRQHandler ; USB FS Wakeup from suspend + DCD TIM6_IRQHandler ; TIM6 + DCD TIM7_IRQHandler ; TIM7 + DCD SDIO_IRQHandler ; SDIO + DCD TIM5_IRQHandler ; TIM5 + DCD SPI3_IRQHandler ; SPI3 + DCD UART4_IRQHandler ; UART4 + DCD UART5_IRQHandler ; UART5 + DCD DMA2_Channel1_IRQHandler ; DMA2 Channel 1 + DCD DMA2_Channel2_IRQHandler ; DMA2 Channel 2 + DCD DMA2_Channel3_IRQHandler ; DMA2 Channel 3 + DCD DMA2_Channel4_IRQHandler ; DMA2 Channel 4 + DCD DMA2_Channel5_IRQHandler ; DMA2 Channel 5 + DCD AES_IRQHandler ; AES + DCD COMP_ACQ_IRQHandler ; Comparator Channel Acquisition + +;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;; +;; +;; Default interrupt handlers. +;; + THUMB + + PUBWEAK Reset_Handler + SECTION .text:CODE:REORDER(2) +Reset_Handler + LDR R0, =SystemInit + BLX R0 + LDR R0, =__iar_program_start + BX R0 + + PUBWEAK NMI_Handler + SECTION .text:CODE:REORDER(1) +NMI_Handler + B NMI_Handler + + + PUBWEAK HardFault_Handler + SECTION .text:CODE:REORDER(1) +HardFault_Handler + B HardFault_Handler + + + PUBWEAK MemManage_Handler + SECTION .text:CODE:REORDER(1) +MemManage_Handler + B MemManage_Handler + + + PUBWEAK BusFault_Handler + SECTION .text:CODE:REORDER(1) +BusFault_Handler + B BusFault_Handler + + + PUBWEAK UsageFault_Handler + SECTION .text:CODE:REORDER(1) +UsageFault_Handler + B UsageFault_Handler + + + PUBWEAK SVC_Handler + SECTION .text:CODE:REORDER(1) +SVC_Handler + B SVC_Handler + + + PUBWEAK DebugMon_Handler + SECTION .text:CODE:REORDER(1) +DebugMon_Handler + B DebugMon_Handler + + + PUBWEAK PendSV_Handler + SECTION .text:CODE:REORDER(1) +PendSV_Handler + B PendSV_Handler + + + PUBWEAK SysTick_Handler + SECTION .text:CODE:REORDER(1) +SysTick_Handler + B SysTick_Handler + + + PUBWEAK WWDG_IRQHandler + SECTION .text:CODE:REORDER(1) +WWDG_IRQHandler + B WWDG_IRQHandler + + + PUBWEAK PVD_IRQHandler + SECTION .text:CODE:REORDER(1) +PVD_IRQHandler + B PVD_IRQHandler + + + PUBWEAK TAMPER_STAMP_IRQHandler + SECTION .text:CODE:REORDER(1) +TAMPER_STAMP_IRQHandler + B TAMPER_STAMP_IRQHandler + + + PUBWEAK RTC_WKUP_IRQHandler + SECTION .text:CODE:REORDER(1) +RTC_WKUP_IRQHandler + B RTC_WKUP_IRQHandler + + + PUBWEAK FLASH_IRQHandler + SECTION .text:CODE:REORDER(1) +FLASH_IRQHandler + B FLASH_IRQHandler + + + PUBWEAK RCC_IRQHandler + SECTION .text:CODE:REORDER(1) +RCC_IRQHandler + B RCC_IRQHandler + + + PUBWEAK EXTI0_IRQHandler + SECTION .text:CODE:REORDER(1) +EXTI0_IRQHandler + B EXTI0_IRQHandler + + + PUBWEAK EXTI1_IRQHandler + SECTION .text:CODE:REORDER(1) +EXTI1_IRQHandler + B EXTI1_IRQHandler + + + PUBWEAK EXTI2_IRQHandler + SECTION .text:CODE:REORDER(1) +EXTI2_IRQHandler + B EXTI2_IRQHandler + + + PUBWEAK EXTI3_IRQHandler + SECTION .text:CODE:REORDER(1) +EXTI3_IRQHandler + B EXTI3_IRQHandler + + + PUBWEAK EXTI4_IRQHandler + SECTION .text:CODE:REORDER(1) +EXTI4_IRQHandler + B EXTI4_IRQHandler + + + PUBWEAK DMA1_Channel1_IRQHandler + SECTION .text:CODE:REORDER(1) +DMA1_Channel1_IRQHandler + B DMA1_Channel1_IRQHandler + + + PUBWEAK DMA1_Channel2_IRQHandler + SECTION .text:CODE:REORDER(1) +DMA1_Channel2_IRQHandler + B DMA1_Channel2_IRQHandler + + + PUBWEAK DMA1_Channel3_IRQHandler + SECTION .text:CODE:REORDER(1) +DMA1_Channel3_IRQHandler + B DMA1_Channel3_IRQHandler + + + PUBWEAK DMA1_Channel4_IRQHandler + SECTION .text:CODE:REORDER(1) +DMA1_Channel4_IRQHandler + B DMA1_Channel4_IRQHandler + + + PUBWEAK DMA1_Channel5_IRQHandler + SECTION .text:CODE:REORDER(1) +DMA1_Channel5_IRQHandler + B DMA1_Channel5_IRQHandler + + + PUBWEAK DMA1_Channel6_IRQHandler + SECTION .text:CODE:REORDER(1) +DMA1_Channel6_IRQHandler + B DMA1_Channel6_IRQHandler + + + PUBWEAK DMA1_Channel7_IRQHandler + SECTION .text:CODE:REORDER(1) +DMA1_Channel7_IRQHandler + B DMA1_Channel7_IRQHandler + + + PUBWEAK ADC1_IRQHandler + SECTION .text:CODE:REORDER(1) +ADC1_IRQHandler + B ADC1_IRQHandler + + + PUBWEAK USB_HP_IRQHandler + SECTION .text:CODE:REORDER(1) +USB_HP_IRQHandler + B USB_HP_IRQHandler + + + PUBWEAK USB_LP_IRQHandler + SECTION .text:CODE:REORDER(1) +USB_LP_IRQHandler + B USB_LP_IRQHandler + + + PUBWEAK DAC_IRQHandler + SECTION .text:CODE:REORDER(1) +DAC_IRQHandler + B DAC_IRQHandler + + + PUBWEAK COMP_IRQHandler + SECTION .text:CODE:REORDER(1) +COMP_IRQHandler + B COMP_IRQHandler + + + PUBWEAK EXTI9_5_IRQHandler + SECTION .text:CODE:REORDER(1) +EXTI9_5_IRQHandler + B EXTI9_5_IRQHandler + + + PUBWEAK LCD_IRQHandler + SECTION .text:CODE:REORDER(1) +LCD_IRQHandler + B LCD_IRQHandler + + + PUBWEAK TIM9_IRQHandler + SECTION .text:CODE:REORDER(1) +TIM9_IRQHandler + B TIM9_IRQHandler + + + PUBWEAK TIM10_IRQHandler + SECTION .text:CODE:REORDER(1) +TIM10_IRQHandler + B TIM10_IRQHandler + + + PUBWEAK TIM11_IRQHandler + SECTION .text:CODE:REORDER(1) +TIM11_IRQHandler + B TIM11_IRQHandler + + + PUBWEAK TIM2_IRQHandler + SECTION .text:CODE:REORDER(1) +TIM2_IRQHandler + B TIM2_IRQHandler + + + PUBWEAK TIM3_IRQHandler + SECTION .text:CODE:REORDER(1) +TIM3_IRQHandler + B TIM3_IRQHandler + + + PUBWEAK TIM4_IRQHandler + SECTION .text:CODE:REORDER(1) +TIM4_IRQHandler + B TIM4_IRQHandler + + + PUBWEAK I2C1_EV_IRQHandler + SECTION .text:CODE:REORDER(1) +I2C1_EV_IRQHandler + B I2C1_EV_IRQHandler + + + PUBWEAK I2C1_ER_IRQHandler + SECTION .text:CODE:REORDER(1) +I2C1_ER_IRQHandler + B I2C1_ER_IRQHandler + + + PUBWEAK I2C2_EV_IRQHandler + SECTION .text:CODE:REORDER(1) +I2C2_EV_IRQHandler + B I2C2_EV_IRQHandler + + + PUBWEAK I2C2_ER_IRQHandler + SECTION .text:CODE:REORDER(1) +I2C2_ER_IRQHandler + B I2C2_ER_IRQHandler + + + PUBWEAK SPI1_IRQHandler + SECTION .text:CODE:REORDER(1) +SPI1_IRQHandler + B SPI1_IRQHandler + + + PUBWEAK SPI2_IRQHandler + SECTION .text:CODE:REORDER(1) +SPI2_IRQHandler + B SPI2_IRQHandler + + + PUBWEAK USART1_IRQHandler + SECTION .text:CODE:REORDER(1) +USART1_IRQHandler + B USART1_IRQHandler + + + PUBWEAK USART2_IRQHandler + SECTION .text:CODE:REORDER(1) +USART2_IRQHandler + B USART2_IRQHandler + + + PUBWEAK USART3_IRQHandler + SECTION .text:CODE:REORDER(1) +USART3_IRQHandler + B USART3_IRQHandler + + + PUBWEAK EXTI15_10_IRQHandler + SECTION .text:CODE:REORDER(1) +EXTI15_10_IRQHandler + B EXTI15_10_IRQHandler + + + PUBWEAK RTC_Alarm_IRQHandler + SECTION .text:CODE:REORDER(1) +RTC_Alarm_IRQHandler + B RTC_Alarm_IRQHandler + + + PUBWEAK USB_FS_WKUP_IRQHandler + SECTION .text:CODE:REORDER(1) +USB_FS_WKUP_IRQHandler + B USB_FS_WKUP_IRQHandler + + + PUBWEAK TIM6_IRQHandler + SECTION .text:CODE:REORDER(1) +TIM6_IRQHandler + B TIM6_IRQHandler + + + PUBWEAK TIM7_IRQHandler + SECTION .text:CODE:REORDER(1) +TIM7_IRQHandler + B TIM7_IRQHandler + + PUBWEAK SDIO_IRQHandler + SECTION .text:CODE:REORDER(1) +SDIO_IRQHandler + B SDIO_IRQHandler + + + PUBWEAK TIM5_IRQHandler + SECTION .text:CODE:REORDER(1) +TIM5_IRQHandler + B TIM5_IRQHandler + + PUBWEAK SPI3_IRQHandler + SECTION .text:CODE:REORDER(1) +SPI3_IRQHandler + B SPI3_IRQHandler + + + PUBWEAK UART4_IRQHandler + SECTION .text:CODE:REORDER(1) +UART4_IRQHandler + B UART4_IRQHandler + + + PUBWEAK UART5_IRQHandler + SECTION .text:CODE:REORDER(1) +UART5_IRQHandler + B UART5_IRQHandler + + PUBWEAK DMA2_Channel1_IRQHandler + SECTION .text:CODE:REORDER(1) +DMA2_Channel1_IRQHandler + B DMA2_Channel1_IRQHandler + + + PUBWEAK DMA2_Channel2_IRQHandler + SECTION .text:CODE:REORDER(1) +DMA2_Channel2_IRQHandler + B DMA2_Channel2_IRQHandler + + + PUBWEAK DMA2_Channel3_IRQHandler + SECTION .text:CODE:REORDER(1) +DMA2_Channel3_IRQHandler + B DMA2_Channel3_IRQHandler + + + PUBWEAK DMA2_Channel4_IRQHandler + SECTION .text:CODE:REORDER(1) +DMA2_Channel4_IRQHandler + B DMA2_Channel4_IRQHandler + + + PUBWEAK DMA2_Channel5_IRQHandler + SECTION .text:CODE:REORDER(1) +DMA2_Channel5_IRQHandler + B DMA2_Channel5_IRQHandler + + + PUBWEAK AES_IRQHandler + SECTION .text:CODE:REORDER(1) +AES_IRQHandler + B AES_IRQHandler + + + PUBWEAK COMP_ACQ_IRQHandler + SECTION .text:CODE:REORDER(1) +COMP_ACQ_IRQHandler + B COMP_ACQ_IRQHandler + + END +/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ diff --git a/Libraries/CMSIS/Device/ST/STM32L1xx/Source/Templates/iar/startup_stm32l1xx_md.s b/Libraries/CMSIS/Device/ST/STM32L1xx/Source/Templates/iar/startup_stm32l1xx_md.s new file mode 100644 index 0000000..552b42d --- /dev/null +++ b/Libraries/CMSIS/Device/ST/STM32L1xx/Source/Templates/iar/startup_stm32l1xx_md.s @@ -0,0 +1,463 @@ +;/******************** (C) COPYRIGHT 2012 STMicroelectronics ******************** +;* File Name : startup_stm32l1xx_md.s +;* Author : MCD Application Team +;* Version : V1.1.1 +;* Date : 09-March-2012 +;* Description : STM32L1xx Ultra Low Power Medium-density Devices vector +;* table for EWARM toolchain. +;* This module performs: +;* - Set the initial SP +;* - Set the initial PC == __iar_program_start, +;* - Set the vector table entries with the exceptions ISR +;* address. +;* After Reset the Cortex-M3 processor is in Thread mode, +;* priority is Privileged, and the Stack is set to Main. +;******************************************************************************** +;* +;* Licensed under MCD-ST Liberty SW License Agreement V2, (the "License"); +;* You may not use this file except in compliance with the License. +;* You may obtain a copy of the License at: +;* +;* http://www.st.com/software_license_agreement_liberty_v2 +;* +;* Unless required by applicable law or agreed to in writing, software +;* distributed under the License is distributed on an "AS IS" BASIS, +;* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +;* See the License for the specific language governing permissions and +;* limitations under the License. +;* +;*******************************************************************************/ +; +; +; The modules in this file are included in the libraries, and may be replaced +; by any user-defined modules that define the PUBLIC symbol _program_start or +; a user defined start symbol. +; To override the cstartup defined in the library, simply add your modified +; version to the workbench project. +; +; The vector table is normally located at address 0. +; When debugging in RAM, it can be located in RAM, aligned to at least 2^6. +; The name "__vector_table" has special meaning for C-SPY: +; it is where the SP start value is found, and the NVIC vector +; table register (VTOR) is initialized to this address if != 0. +; +; Cortex-M version +; + + MODULE ?cstartup + + ;; Forward declaration of sections. + SECTION CSTACK:DATA:NOROOT(3) + + SECTION .intvec:CODE:NOROOT(2) + + EXTERN __iar_program_start + EXTERN SystemInit + PUBLIC __vector_table + + DATA +__vector_table + DCD sfe(CSTACK) + DCD Reset_Handler ; Reset Handler + + DCD NMI_Handler ; NMI Handler + DCD HardFault_Handler ; Hard Fault Handler + DCD MemManage_Handler ; MPU Fault Handler + DCD BusFault_Handler ; Bus Fault Handler + DCD UsageFault_Handler ; Usage Fault Handler + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD SVC_Handler ; SVCall Handler + DCD DebugMon_Handler ; Debug Monitor Handler + DCD 0 ; Reserved + DCD PendSV_Handler ; PendSV Handler + DCD SysTick_Handler ; SysTick Handler + + ; External Interrupts + DCD WWDG_IRQHandler ; Window Watchdog + DCD PVD_IRQHandler ; PVD through EXTI Line detect + DCD TAMPER_STAMP_IRQHandler ; Tamper and Time Stamp + DCD RTC_WKUP_IRQHandler ; RTC Wakeup + DCD FLASH_IRQHandler ; FLASH + DCD RCC_IRQHandler ; RCC + DCD EXTI0_IRQHandler ; EXTI Line 0 + DCD EXTI1_IRQHandler ; EXTI Line 1 + DCD EXTI2_IRQHandler ; EXTI Line 2 + DCD EXTI3_IRQHandler ; EXTI Line 3 + DCD EXTI4_IRQHandler ; EXTI Line 4 + DCD DMA1_Channel1_IRQHandler ; DMA1 Channel 1 + DCD DMA1_Channel2_IRQHandler ; DMA1 Channel 2 + DCD DMA1_Channel3_IRQHandler ; DMA1 Channel 3 + DCD DMA1_Channel4_IRQHandler ; DMA1 Channel 4 + DCD DMA1_Channel5_IRQHandler ; DMA1 Channel 5 + DCD DMA1_Channel6_IRQHandler ; DMA1 Channel 6 + DCD DMA1_Channel7_IRQHandler ; DMA1 Channel 7 + DCD ADC1_IRQHandler ; ADC1 + DCD USB_HP_IRQHandler ; USB High Priority + DCD USB_LP_IRQHandler ; USB Low Priority + DCD DAC_IRQHandler ; DAC + DCD COMP_IRQHandler ; COMP through EXTI Line + DCD EXTI9_5_IRQHandler ; EXTI Line 9..5 + DCD LCD_IRQHandler ; LCD + DCD TIM9_IRQHandler ; TIM9 + DCD TIM10_IRQHandler ; TIM10 + DCD TIM11_IRQHandler ; TIM11 + DCD TIM2_IRQHandler ; TIM2 + DCD TIM3_IRQHandler ; TIM3 + DCD TIM4_IRQHandler ; TIM4 + DCD I2C1_EV_IRQHandler ; I2C1 Event + DCD I2C1_ER_IRQHandler ; I2C1 Error + DCD I2C2_EV_IRQHandler ; I2C2 Event + DCD I2C2_ER_IRQHandler ; I2C2 Error + DCD SPI1_IRQHandler ; SPI1 + DCD SPI2_IRQHandler ; SPI2 + DCD USART1_IRQHandler ; USART1 + DCD USART2_IRQHandler ; USART2 + DCD USART3_IRQHandler ; USART3 + DCD EXTI15_10_IRQHandler ; EXTI Line 15..10 + DCD RTC_Alarm_IRQHandler ; RTC Alarm through EXTI Line + DCD USB_FS_WKUP_IRQHandler ; USB FS Wakeup from suspend + DCD TIM6_IRQHandler ; TIM6 + DCD TIM7_IRQHandler ; TIM7 + +;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;; +;; +;; Default interrupt handlers. +;; + THUMB + + PUBWEAK Reset_Handler + SECTION .text:CODE:REORDER(2) +Reset_Handler + LDR R0, =SystemInit + BLX R0 + LDR R0, =__iar_program_start + BX R0 + + PUBWEAK NMI_Handler + SECTION .text:CODE:REORDER(1) +NMI_Handler + B NMI_Handler + + + PUBWEAK HardFault_Handler + SECTION .text:CODE:REORDER(1) +HardFault_Handler + B HardFault_Handler + + + PUBWEAK MemManage_Handler + SECTION .text:CODE:REORDER(1) +MemManage_Handler + B MemManage_Handler + + + PUBWEAK BusFault_Handler + SECTION .text:CODE:REORDER(1) +BusFault_Handler + B BusFault_Handler + + + PUBWEAK UsageFault_Handler + SECTION .text:CODE:REORDER(1) +UsageFault_Handler + B UsageFault_Handler + + + PUBWEAK SVC_Handler + SECTION .text:CODE:REORDER(1) +SVC_Handler + B SVC_Handler + + + PUBWEAK DebugMon_Handler + SECTION .text:CODE:REORDER(1) +DebugMon_Handler + B DebugMon_Handler + + + PUBWEAK PendSV_Handler + SECTION .text:CODE:REORDER(1) +PendSV_Handler + B PendSV_Handler + + + PUBWEAK SysTick_Handler + SECTION .text:CODE:REORDER(1) +SysTick_Handler + B SysTick_Handler + + + PUBWEAK WWDG_IRQHandler + SECTION .text:CODE:REORDER(1) +WWDG_IRQHandler + B WWDG_IRQHandler + + + PUBWEAK PVD_IRQHandler + SECTION .text:CODE:REORDER(1) +PVD_IRQHandler + B PVD_IRQHandler + + + PUBWEAK TAMPER_STAMP_IRQHandler + SECTION .text:CODE:REORDER(1) +TAMPER_STAMP_IRQHandler + B TAMPER_STAMP_IRQHandler + + + PUBWEAK RTC_WKUP_IRQHandler + SECTION .text:CODE:REORDER(1) +RTC_WKUP_IRQHandler + B RTC_WKUP_IRQHandler + + + PUBWEAK FLASH_IRQHandler + SECTION .text:CODE:REORDER(1) +FLASH_IRQHandler + B FLASH_IRQHandler + + + PUBWEAK RCC_IRQHandler + SECTION .text:CODE:REORDER(1) +RCC_IRQHandler + B RCC_IRQHandler + + + PUBWEAK EXTI0_IRQHandler + SECTION .text:CODE:REORDER(1) +EXTI0_IRQHandler + B EXTI0_IRQHandler + + + PUBWEAK EXTI1_IRQHandler + SECTION .text:CODE:REORDER(1) +EXTI1_IRQHandler + B EXTI1_IRQHandler + + + PUBWEAK EXTI2_IRQHandler + SECTION .text:CODE:REORDER(1) +EXTI2_IRQHandler + B EXTI2_IRQHandler + + + PUBWEAK EXTI3_IRQHandler + SECTION .text:CODE:REORDER(1) +EXTI3_IRQHandler + B EXTI3_IRQHandler + + + PUBWEAK EXTI4_IRQHandler + SECTION .text:CODE:REORDER(1) +EXTI4_IRQHandler + B EXTI4_IRQHandler + + + PUBWEAK DMA1_Channel1_IRQHandler + SECTION .text:CODE:REORDER(1) +DMA1_Channel1_IRQHandler + B DMA1_Channel1_IRQHandler + + + PUBWEAK DMA1_Channel2_IRQHandler + SECTION .text:CODE:REORDER(1) +DMA1_Channel2_IRQHandler + B DMA1_Channel2_IRQHandler + + + PUBWEAK DMA1_Channel3_IRQHandler + SECTION .text:CODE:REORDER(1) +DMA1_Channel3_IRQHandler + B DMA1_Channel3_IRQHandler + + + PUBWEAK DMA1_Channel4_IRQHandler + SECTION .text:CODE:REORDER(1) +DMA1_Channel4_IRQHandler + B DMA1_Channel4_IRQHandler + + + PUBWEAK DMA1_Channel5_IRQHandler + SECTION .text:CODE:REORDER(1) +DMA1_Channel5_IRQHandler + B DMA1_Channel5_IRQHandler + + + PUBWEAK DMA1_Channel6_IRQHandler + SECTION .text:CODE:REORDER(1) +DMA1_Channel6_IRQHandler + B DMA1_Channel6_IRQHandler + + + PUBWEAK DMA1_Channel7_IRQHandler + SECTION .text:CODE:REORDER(1) +DMA1_Channel7_IRQHandler + B DMA1_Channel7_IRQHandler + + + PUBWEAK ADC1_IRQHandler + SECTION .text:CODE:REORDER(1) +ADC1_IRQHandler + B ADC1_IRQHandler + + + PUBWEAK USB_HP_IRQHandler + SECTION .text:CODE:REORDER(1) +USB_HP_IRQHandler + B USB_HP_IRQHandler + + + PUBWEAK USB_LP_IRQHandler + SECTION .text:CODE:REORDER(1) +USB_LP_IRQHandler + B USB_LP_IRQHandler + + + PUBWEAK DAC_IRQHandler + SECTION .text:CODE:REORDER(1) +DAC_IRQHandler + B DAC_IRQHandler + + + PUBWEAK COMP_IRQHandler + SECTION .text:CODE:REORDER(1) +COMP_IRQHandler + B COMP_IRQHandler + + + PUBWEAK EXTI9_5_IRQHandler + SECTION .text:CODE:REORDER(1) +EXTI9_5_IRQHandler + B EXTI9_5_IRQHandler + + + PUBWEAK LCD_IRQHandler + SECTION .text:CODE:REORDER(1) +LCD_IRQHandler + B LCD_IRQHandler + + + PUBWEAK TIM9_IRQHandler + SECTION .text:CODE:REORDER(1) +TIM9_IRQHandler + B TIM9_IRQHandler + + + PUBWEAK TIM10_IRQHandler + SECTION .text:CODE:REORDER(1) +TIM10_IRQHandler + B TIM10_IRQHandler + + + PUBWEAK TIM11_IRQHandler + SECTION .text:CODE:REORDER(1) +TIM11_IRQHandler + B TIM11_IRQHandler + + + PUBWEAK TIM2_IRQHandler + SECTION .text:CODE:REORDER(1) +TIM2_IRQHandler + B TIM2_IRQHandler + + + PUBWEAK TIM3_IRQHandler + SECTION .text:CODE:REORDER(1) +TIM3_IRQHandler + B TIM3_IRQHandler + + + PUBWEAK TIM4_IRQHandler + SECTION .text:CODE:REORDER(1) +TIM4_IRQHandler + B TIM4_IRQHandler + + + PUBWEAK I2C1_EV_IRQHandler + SECTION .text:CODE:REORDER(1) +I2C1_EV_IRQHandler + B I2C1_EV_IRQHandler + + + PUBWEAK I2C1_ER_IRQHandler + SECTION .text:CODE:REORDER(1) +I2C1_ER_IRQHandler + B I2C1_ER_IRQHandler + + + PUBWEAK I2C2_EV_IRQHandler + SECTION .text:CODE:REORDER(1) +I2C2_EV_IRQHandler + B I2C2_EV_IRQHandler + + + PUBWEAK I2C2_ER_IRQHandler + SECTION .text:CODE:REORDER(1) +I2C2_ER_IRQHandler + B I2C2_ER_IRQHandler + + + PUBWEAK SPI1_IRQHandler + SECTION .text:CODE:REORDER(1) +SPI1_IRQHandler + B SPI1_IRQHandler + + + PUBWEAK SPI2_IRQHandler + SECTION .text:CODE:REORDER(1) +SPI2_IRQHandler + B SPI2_IRQHandler + + + PUBWEAK USART1_IRQHandler + SECTION .text:CODE:REORDER(1) +USART1_IRQHandler + B USART1_IRQHandler + + + PUBWEAK USART2_IRQHandler + SECTION .text:CODE:REORDER(1) +USART2_IRQHandler + B USART2_IRQHandler + + + PUBWEAK USART3_IRQHandler + SECTION .text:CODE:REORDER(1) +USART3_IRQHandler + B USART3_IRQHandler + + + PUBWEAK EXTI15_10_IRQHandler + SECTION .text:CODE:REORDER(1) +EXTI15_10_IRQHandler + B EXTI15_10_IRQHandler + + + PUBWEAK RTC_Alarm_IRQHandler + SECTION .text:CODE:REORDER(1) +RTC_Alarm_IRQHandler + B RTC_Alarm_IRQHandler + + + PUBWEAK USB_FS_WKUP_IRQHandler + SECTION .text:CODE:REORDER(1) +USB_FS_WKUP_IRQHandler + B USB_FS_WKUP_IRQHandler + + + PUBWEAK TIM6_IRQHandler + SECTION .text:CODE:REORDER(1) +TIM6_IRQHandler + B TIM6_IRQHandler + + + PUBWEAK TIM7_IRQHandler + SECTION .text:CODE:REORDER(1) +TIM7_IRQHandler + B TIM7_IRQHandler + + END +/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ diff --git a/Libraries/CMSIS/Device/ST/STM32L1xx/Source/Templates/iar/startup_stm32l1xx_mdp.s b/Libraries/CMSIS/Device/ST/STM32L1xx/Source/Templates/iar/startup_stm32l1xx_mdp.s new file mode 100644 index 0000000..cba4f98 --- /dev/null +++ b/Libraries/CMSIS/Device/ST/STM32L1xx/Source/Templates/iar/startup_stm32l1xx_mdp.s @@ -0,0 +1,520 @@ +;/******************** (C) COPYRIGHT 2012 STMicroelectronics ******************** +;* File Name : startup_stm32l1xx_mdp.s +;* Author : MCD Application Team +;* Version : V1.1.1 +;* Date : 09-March-2012 +;* Description : STM32L1xx Ultra Low Power Medium-density Plus Devices vector +;* table for EWARM toolchain. +;* This module performs: +;* - Set the initial SP +;* - Set the initial PC == __iar_program_start, +;* - Set the vector table entries with the exceptions ISR +;* address. +;* After Reset the Cortex-M3 processor is in Thread mode, +;* priority is Privileged, and the Stack is set to Main. +;******************************************************************************** +;* +;* Licensed under MCD-ST Liberty SW License Agreement V2, (the "License"); +;* You may not use this file except in compliance with the License. +;* You may obtain a copy of the License at: +;* +;* http://www.st.com/software_license_agreement_liberty_v2 +;* +;* Unless required by applicable law or agreed to in writing, software +;* distributed under the License is distributed on an "AS IS" BASIS, +;* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +;* See the License for the specific language governing permissions and +;* limitations under the License. +;* +;*******************************************************************************/ +; +; +; The modules in this file are included in the libraries, and may be replaced +; by any user-defined modules that define the PUBLIC symbol _program_start or +; a user defined start symbol. +; To override the cstartup defined in the library, simply add your modified +; version to the workbench project. +; +; The vector table is normally located at address 0. +; When debugging in RAM, it can be located in RAM, aligned to at least 2^6. +; The name "__vector_table" has special meaning for C-SPY: +; it is where the SP start value is found, and the NVIC vector +; table register (VTOR) is initialized to this address if != 0. +; +; Cortex-M version +; + + MODULE ?cstartup + + ;; Forward declaration of sections. + SECTION CSTACK:DATA:NOROOT(3) + + SECTION .intvec:CODE:NOROOT(2) + + EXTERN __iar_program_start + EXTERN SystemInit + PUBLIC __vector_table + + DATA +__vector_table + DCD sfe(CSTACK) + DCD Reset_Handler ; Reset Handler + + DCD NMI_Handler ; NMI Handler + DCD HardFault_Handler ; Hard Fault Handler + DCD MemManage_Handler ; MPU Fault Handler + DCD BusFault_Handler ; Bus Fault Handler + DCD UsageFault_Handler ; Usage Fault Handler + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD SVC_Handler ; SVCall Handler + DCD DebugMon_Handler ; Debug Monitor Handler + DCD 0 ; Reserved + DCD PendSV_Handler ; PendSV Handler + DCD SysTick_Handler ; SysTick Handler + + ; External Interrupts + DCD WWDG_IRQHandler ; Window Watchdog + DCD PVD_IRQHandler ; PVD through EXTI Line detect + DCD TAMPER_STAMP_IRQHandler ; Tamper and Time Stamp + DCD RTC_WKUP_IRQHandler ; RTC Wakeup + DCD FLASH_IRQHandler ; FLASH + DCD RCC_IRQHandler ; RCC + DCD EXTI0_IRQHandler ; EXTI Line 0 + DCD EXTI1_IRQHandler ; EXTI Line 1 + DCD EXTI2_IRQHandler ; EXTI Line 2 + DCD EXTI3_IRQHandler ; EXTI Line 3 + DCD EXTI4_IRQHandler ; EXTI Line 4 + DCD DMA1_Channel1_IRQHandler ; DMA1 Channel 1 + DCD DMA1_Channel2_IRQHandler ; DMA1 Channel 2 + DCD DMA1_Channel3_IRQHandler ; DMA1 Channel 3 + DCD DMA1_Channel4_IRQHandler ; DMA1 Channel 4 + DCD DMA1_Channel5_IRQHandler ; DMA1 Channel 5 + DCD DMA1_Channel6_IRQHandler ; DMA1 Channel 6 + DCD DMA1_Channel7_IRQHandler ; DMA1 Channel 7 + DCD ADC1_IRQHandler ; ADC1 + DCD USB_HP_IRQHandler ; USB High Priority + DCD USB_LP_IRQHandler ; USB Low Priority + DCD DAC_IRQHandler ; DAC + DCD COMP_IRQHandler ; COMP through EXTI Line + DCD EXTI9_5_IRQHandler ; EXTI Line 9..5 + DCD LCD_IRQHandler ; LCD + DCD TIM9_IRQHandler ; TIM9 + DCD TIM10_IRQHandler ; TIM10 + DCD TIM11_IRQHandler ; TIM11 + DCD TIM2_IRQHandler ; TIM2 + DCD TIM3_IRQHandler ; TIM3 + DCD TIM4_IRQHandler ; TIM4 + DCD I2C1_EV_IRQHandler ; I2C1 Event + DCD I2C1_ER_IRQHandler ; I2C1 Error + DCD I2C2_EV_IRQHandler ; I2C2 Event + DCD I2C2_ER_IRQHandler ; I2C2 Error + DCD SPI1_IRQHandler ; SPI1 + DCD SPI2_IRQHandler ; SPI2 + DCD USART1_IRQHandler ; USART1 + DCD USART2_IRQHandler ; USART2 + DCD USART3_IRQHandler ; USART3 + DCD EXTI15_10_IRQHandler ; EXTI Line 15..10 + DCD RTC_Alarm_IRQHandler ; RTC Alarm through EXTI Line + DCD USB_FS_WKUP_IRQHandler ; USB FS Wakeup from suspend + DCD TIM6_IRQHandler ; TIM6 + DCD TIM7_IRQHandler ; TIM7 + DCD 0 ; Reserved + DCD TIM5_IRQHandler ; TIM5 + DCD SPI3_IRQHandler ; SPI3 + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD DMA2_Channel1_IRQHandler ; DMA2 Channel 1 + DCD DMA2_Channel2_IRQHandler ; DMA2 Channel 2 + DCD DMA2_Channel3_IRQHandler ; DMA2 Channel 3 + DCD DMA2_Channel4_IRQHandler ; DMA2 Channel 4 + DCD DMA2_Channel5_IRQHandler ; DMA2 Channel 5 + DCD AES_IRQHandler ; AES + DCD COMP_ACQ_IRQHandler ; Comparator Channel Acquisition + +;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;; +;; +;; Default interrupt handlers. +;; + THUMB + + PUBWEAK Reset_Handler + SECTION .text:CODE:REORDER(2) +Reset_Handler + LDR R0, =SystemInit + BLX R0 + LDR R0, =__iar_program_start + BX R0 + + PUBWEAK NMI_Handler + SECTION .text:CODE:REORDER(1) +NMI_Handler + B NMI_Handler + + + PUBWEAK HardFault_Handler + SECTION .text:CODE:REORDER(1) +HardFault_Handler + B HardFault_Handler + + + PUBWEAK MemManage_Handler + SECTION .text:CODE:REORDER(1) +MemManage_Handler + B MemManage_Handler + + + PUBWEAK BusFault_Handler + SECTION .text:CODE:REORDER(1) +BusFault_Handler + B BusFault_Handler + + + PUBWEAK UsageFault_Handler + SECTION .text:CODE:REORDER(1) +UsageFault_Handler + B UsageFault_Handler + + + PUBWEAK SVC_Handler + SECTION .text:CODE:REORDER(1) +SVC_Handler + B SVC_Handler + + + PUBWEAK DebugMon_Handler + SECTION .text:CODE:REORDER(1) +DebugMon_Handler + B DebugMon_Handler + + + PUBWEAK PendSV_Handler + SECTION .text:CODE:REORDER(1) +PendSV_Handler + B PendSV_Handler + + + PUBWEAK SysTick_Handler + SECTION .text:CODE:REORDER(1) +SysTick_Handler + B SysTick_Handler + + + PUBWEAK WWDG_IRQHandler + SECTION .text:CODE:REORDER(1) +WWDG_IRQHandler + B WWDG_IRQHandler + + + PUBWEAK PVD_IRQHandler + SECTION .text:CODE:REORDER(1) +PVD_IRQHandler + B PVD_IRQHandler + + + PUBWEAK TAMPER_STAMP_IRQHandler + SECTION .text:CODE:REORDER(1) +TAMPER_STAMP_IRQHandler + B TAMPER_STAMP_IRQHandler + + + PUBWEAK RTC_WKUP_IRQHandler + SECTION .text:CODE:REORDER(1) +RTC_WKUP_IRQHandler + B RTC_WKUP_IRQHandler + + + PUBWEAK FLASH_IRQHandler + SECTION .text:CODE:REORDER(1) +FLASH_IRQHandler + B FLASH_IRQHandler + + + PUBWEAK RCC_IRQHandler + SECTION .text:CODE:REORDER(1) +RCC_IRQHandler + B RCC_IRQHandler + + + PUBWEAK EXTI0_IRQHandler + SECTION .text:CODE:REORDER(1) +EXTI0_IRQHandler + B EXTI0_IRQHandler + + + PUBWEAK EXTI1_IRQHandler + SECTION .text:CODE:REORDER(1) +EXTI1_IRQHandler + B EXTI1_IRQHandler + + + PUBWEAK EXTI2_IRQHandler + SECTION .text:CODE:REORDER(1) +EXTI2_IRQHandler + B EXTI2_IRQHandler + + + PUBWEAK EXTI3_IRQHandler + SECTION .text:CODE:REORDER(1) +EXTI3_IRQHandler + B EXTI3_IRQHandler + + + PUBWEAK EXTI4_IRQHandler + SECTION .text:CODE:REORDER(1) +EXTI4_IRQHandler + B EXTI4_IRQHandler + + + PUBWEAK DMA1_Channel1_IRQHandler + SECTION .text:CODE:REORDER(1) +DMA1_Channel1_IRQHandler + B DMA1_Channel1_IRQHandler + + + PUBWEAK DMA1_Channel2_IRQHandler + SECTION .text:CODE:REORDER(1) +DMA1_Channel2_IRQHandler + B DMA1_Channel2_IRQHandler + + + PUBWEAK DMA1_Channel3_IRQHandler + SECTION .text:CODE:REORDER(1) +DMA1_Channel3_IRQHandler + B DMA1_Channel3_IRQHandler + + + PUBWEAK DMA1_Channel4_IRQHandler + SECTION .text:CODE:REORDER(1) +DMA1_Channel4_IRQHandler + B DMA1_Channel4_IRQHandler + + + PUBWEAK DMA1_Channel5_IRQHandler + SECTION .text:CODE:REORDER(1) +DMA1_Channel5_IRQHandler + B DMA1_Channel5_IRQHandler + + + PUBWEAK DMA1_Channel6_IRQHandler + SECTION .text:CODE:REORDER(1) +DMA1_Channel6_IRQHandler + B DMA1_Channel6_IRQHandler + + + PUBWEAK DMA1_Channel7_IRQHandler + SECTION .text:CODE:REORDER(1) +DMA1_Channel7_IRQHandler + B DMA1_Channel7_IRQHandler + + + PUBWEAK ADC1_IRQHandler + SECTION .text:CODE:REORDER(1) +ADC1_IRQHandler + B ADC1_IRQHandler + + + PUBWEAK USB_HP_IRQHandler + SECTION .text:CODE:REORDER(1) +USB_HP_IRQHandler + B USB_HP_IRQHandler + + + PUBWEAK USB_LP_IRQHandler + SECTION .text:CODE:REORDER(1) +USB_LP_IRQHandler + B USB_LP_IRQHandler + + + PUBWEAK DAC_IRQHandler + SECTION .text:CODE:REORDER(1) +DAC_IRQHandler + B DAC_IRQHandler + + + PUBWEAK COMP_IRQHandler + SECTION .text:CODE:REORDER(1) +COMP_IRQHandler + B COMP_IRQHandler + + + PUBWEAK EXTI9_5_IRQHandler + SECTION .text:CODE:REORDER(1) +EXTI9_5_IRQHandler + B EXTI9_5_IRQHandler + + + PUBWEAK LCD_IRQHandler + SECTION .text:CODE:REORDER(1) +LCD_IRQHandler + B LCD_IRQHandler + + + PUBWEAK TIM9_IRQHandler + SECTION .text:CODE:REORDER(1) +TIM9_IRQHandler + B TIM9_IRQHandler + + + PUBWEAK TIM10_IRQHandler + SECTION .text:CODE:REORDER(1) +TIM10_IRQHandler + B TIM10_IRQHandler + + + PUBWEAK TIM11_IRQHandler + SECTION .text:CODE:REORDER(1) +TIM11_IRQHandler + B TIM11_IRQHandler + + + PUBWEAK TIM2_IRQHandler + SECTION .text:CODE:REORDER(1) +TIM2_IRQHandler + B TIM2_IRQHandler + + + PUBWEAK TIM3_IRQHandler + SECTION .text:CODE:REORDER(1) +TIM3_IRQHandler + B TIM3_IRQHandler + + + PUBWEAK TIM4_IRQHandler + SECTION .text:CODE:REORDER(1) +TIM4_IRQHandler + B TIM4_IRQHandler + + + PUBWEAK I2C1_EV_IRQHandler + SECTION .text:CODE:REORDER(1) +I2C1_EV_IRQHandler + B I2C1_EV_IRQHandler + + + PUBWEAK I2C1_ER_IRQHandler + SECTION .text:CODE:REORDER(1) +I2C1_ER_IRQHandler + B I2C1_ER_IRQHandler + + + PUBWEAK I2C2_EV_IRQHandler + SECTION .text:CODE:REORDER(1) +I2C2_EV_IRQHandler + B I2C2_EV_IRQHandler + + + PUBWEAK I2C2_ER_IRQHandler + SECTION .text:CODE:REORDER(1) +I2C2_ER_IRQHandler + B I2C2_ER_IRQHandler + + + PUBWEAK SPI1_IRQHandler + SECTION .text:CODE:REORDER(1) +SPI1_IRQHandler + B SPI1_IRQHandler + + + PUBWEAK SPI2_IRQHandler + SECTION .text:CODE:REORDER(1) +SPI2_IRQHandler + B SPI2_IRQHandler + + + PUBWEAK USART1_IRQHandler + SECTION .text:CODE:REORDER(1) +USART1_IRQHandler + B USART1_IRQHandler + + + PUBWEAK USART2_IRQHandler + SECTION .text:CODE:REORDER(1) +USART2_IRQHandler + B USART2_IRQHandler + + + PUBWEAK USART3_IRQHandler + SECTION .text:CODE:REORDER(1) +USART3_IRQHandler + B USART3_IRQHandler + + + PUBWEAK EXTI15_10_IRQHandler + SECTION .text:CODE:REORDER(1) +EXTI15_10_IRQHandler + B EXTI15_10_IRQHandler + + + PUBWEAK RTC_Alarm_IRQHandler + SECTION .text:CODE:REORDER(1) +RTC_Alarm_IRQHandler + B RTC_Alarm_IRQHandler + + + PUBWEAK USB_FS_WKUP_IRQHandler + SECTION .text:CODE:REORDER(1) +USB_FS_WKUP_IRQHandler + B USB_FS_WKUP_IRQHandler + + + PUBWEAK TIM6_IRQHandler + SECTION .text:CODE:REORDER(1) +TIM6_IRQHandler + B TIM6_IRQHandler + + + PUBWEAK TIM7_IRQHandler + SECTION .text:CODE:REORDER(1) +TIM7_IRQHandler + B TIM7_IRQHandler + + PUBWEAK TIM5_IRQHandler + SECTION .text:CODE:REORDER(1) +TIM5_IRQHandler + B TIM5_IRQHandler + + PUBWEAK SPI3_IRQHandler + SECTION .text:CODE:REORDER(1) +SPI3_IRQHandler + B SPI3_IRQHandler + + PUBWEAK DMA2_Channel1_IRQHandler + SECTION .text:CODE:REORDER(1) +DMA2_Channel1_IRQHandler + B DMA2_Channel1_IRQHandler + + PUBWEAK DMA2_Channel2_IRQHandler + SECTION .text:CODE:REORDER(1) +DMA2_Channel2_IRQHandler + B DMA2_Channel2_IRQHandler + + PUBWEAK DMA2_Channel3_IRQHandler + SECTION .text:CODE:REORDER(1) +DMA2_Channel3_IRQHandler + B DMA2_Channel3_IRQHandler + + PUBWEAK DMA2_Channel4_IRQHandler + SECTION .text:CODE:REORDER(1) +DMA2_Channel4_IRQHandler + B DMA2_Channel4_IRQHandler + + PUBWEAK DMA2_Channel5_IRQHandler + SECTION .text:CODE:REORDER(1) +DMA2_Channel5_IRQHandler + B DMA2_Channel5_IRQHandler + + PUBWEAK AES_IRQHandler + SECTION .text:CODE:REORDER(1) +AES_IRQHandler + B AES_IRQHandler + + PUBWEAK COMP_ACQ_IRQHandler + SECTION .text:CODE:REORDER(1) +COMP_ACQ_IRQHandler + B COMP_ACQ_IRQHandler + + END +/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ diff --git a/Libraries/CMSIS/Device/ST/STM32L1xx/Source/Templates/system_stm32l1xx.c b/Libraries/CMSIS/Device/ST/STM32L1xx/Source/Templates/system_stm32l1xx.c new file mode 100644 index 0000000..06528af --- /dev/null +++ b/Libraries/CMSIS/Device/ST/STM32L1xx/Source/Templates/system_stm32l1xx.c @@ -0,0 +1,533 @@ +/** + ****************************************************************************** + * @file system_stm32l1xx.c + * @author MCD Application Team + * @version V1.1.1 + * @date 09-March-2012 + * @brief CMSIS Cortex-M3 Device Peripheral Access Layer System Source File. + * This file contains the system clock configuration for STM32L1xx Ultra + * Low Power devices, and is generated by the clock configuration + * tool "STM32L1xx_Clock_Configuration_V1.1.0.xls". + * + * 1. This file provides two functions and one global variable to be called from + * user application: + * - SystemInit(): Setups the system clock (System clock source, PLL Multiplier + * and Divider factors, AHB/APBx prescalers and Flash settings), + * depending on the configuration made in the clock xls tool. + * This function is called at startup just after reset and + * before branch to main program. This call is made inside + * the "startup_stm32l1xx_xx.s" file. + * + * - SystemCoreClock variable: Contains the core clock (HCLK), it can be used + * by the user application to setup the SysTick + * timer or configure other parameters. + * + * - SystemCoreClockUpdate(): Updates the variable SystemCoreClock and must + * be called whenever the core clock is changed + * during program execution. + * + * 2. After each device reset the MSI (2.1 MHz Range) is used as system clock source. + * Then SystemInit() function is called, in "startup_stm32l1xx_xx.s" file, to + * configure the system clock before to branch to main program. + * + * 3. If the system clock source selected by user fails to startup, the SystemInit() + * function will do nothing and MSI still used as system clock source. User can + * add some code to deal with this issue inside the SetSysClock() function. + * + * 4. The default value of HSE crystal is set to 8MHz, refer to "HSE_VALUE" define + * in "stm32l1xx.h" file. When HSE is used as system clock source, directly or + * through PLL, and you are using different crystal you have to adapt the HSE + * value to your own configuration. + * + * 5. This file configures the system clock as follows: + *============================================================================= + * System Clock Configuration + *============================================================================= + * System Clock source | PLL(HSE) + *----------------------------------------------------------------------------- + * SYSCLK | 32000000 Hz + *----------------------------------------------------------------------------- + * HCLK | 32000000 Hz + *----------------------------------------------------------------------------- + * AHB Prescaler | 1 + *----------------------------------------------------------------------------- + * APB1 Prescaler | 1 + *----------------------------------------------------------------------------- + * APB2 Prescaler | 1 + *----------------------------------------------------------------------------- + * HSE Frequency | 8000000 Hz + *----------------------------------------------------------------------------- + * PLL DIV | 3 + *----------------------------------------------------------------------------- + * PLL MUL | 12 + *----------------------------------------------------------------------------- + * VDD | 3.3 V + *----------------------------------------------------------------------------- + * Vcore | 1.8 V (Range 1) + *----------------------------------------------------------------------------- + * Flash Latency | 1 WS + *----------------------------------------------------------------------------- + * SDIO clock (SDIOCLK) | 48000000 Hz + *----------------------------------------------------------------------------- + * Require 48MHz for USB clock | Disabled + *----------------------------------------------------------------------------- + *============================================================================= + ****************************************************************************** + * @attention + * + *

    © COPYRIGHT 2012 STMicroelectronics

    + * + * Licensed under MCD-ST Liberty SW License Agreement V2, (the "License"); + * You may not use this file except in compliance with the License. + * You may obtain a copy of the License at: + * + * http://www.st.com/software_license_agreement_liberty_v2 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, + * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + * + ****************************************************************************** + */ + +/** @addtogroup CMSIS + * @{ + */ + +/** @addtogroup stm32l1xx_system + * @{ + */ + +/** @addtogroup STM32L1xx_System_Private_Includes + * @{ + */ + +#include "stm32l1xx.h" + +/** + * @} + */ + +/** @addtogroup STM32L1xx_System_Private_TypesDefinitions + * @{ + */ + +/** + * @} + */ + +/** @addtogroup STM32L1xx_System_Private_Defines + * @{ + */ + +/*!< Uncomment the following line if you need to use external SRAM mounted + on STM32L152D_EVAL board as data memory */ +/* #define DATA_IN_ExtSRAM */ + +/*!< Uncomment the following line if you need to relocate your vector Table in + Internal SRAM. */ +/* #define VECT_TAB_SRAM */ +#define VECT_TAB_OFFSET 0x0 /*!< Vector Table base offset field. + This value must be a multiple of 0x200. */ +/** + * @} + */ + +/** @addtogroup STM32L1xx_System_Private_Macros + * @{ + */ + +/** + * @} + */ + +/** @addtogroup STM32L1xx_System_Private_Variables + * @{ + */ +uint32_t SystemCoreClock = 32000000; +__I uint8_t PLLMulTable[9] = {3, 4, 6, 8, 12, 16, 24, 32, 48}; +__I uint8_t AHBPrescTable[16] = {0, 0, 0, 0, 0, 0, 0, 0, 1, 2, 3, 4, 6, 7, 8, 9}; + +/** + * @} + */ + +/** @addtogroup STM32L1xx_System_Private_FunctionPrototypes + * @{ + */ + +static void SetSysClock(void); +#ifdef DATA_IN_ExtSRAM + static void SystemInit_ExtMemCtl(void); +#endif /* DATA_IN_ExtSRAM */ + +/** + * @} + */ + +/** @addtogroup STM32L1xx_System_Private_Functions + * @{ + */ + +/** + * @brief Setup the microcontroller system. + * Initialize the Embedded Flash Interface, the PLL and update the + * SystemCoreClock variable. + * @param None + * @retval None + */ +void SystemInit (void) +{ + /*!< Set MSION bit */ + RCC->CR |= (uint32_t)0x00000100; + + /*!< Reset SW[1:0], HPRE[3:0], PPRE1[2:0], PPRE2[2:0], MCOSEL[2:0] and MCOPRE[2:0] bits */ + RCC->CFGR &= (uint32_t)0x88FFC00C; + + /*!< Reset HSION, HSEON, CSSON and PLLON bits */ + RCC->CR &= (uint32_t)0xEEFEFFFE; + + /*!< Reset HSEBYP bit */ + RCC->CR &= (uint32_t)0xFFFBFFFF; + + /*!< Reset PLLSRC, PLLMUL[3:0] and PLLDIV[1:0] bits */ + RCC->CFGR &= (uint32_t)0xFF02FFFF; + + /*!< Disable all interrupts */ + RCC->CIR = 0x00000000; + +#ifdef DATA_IN_ExtSRAM + SystemInit_ExtMemCtl(); +#endif /* DATA_IN_ExtSRAM */ + + /* Configure the System clock frequency, AHB/APBx prescalers and Flash settings */ + SetSysClock(); + +#ifdef VECT_TAB_SRAM + SCB->VTOR = SRAM_BASE | VECT_TAB_OFFSET; /* Vector Table Relocation in Internal SRAM. */ +#else + SCB->VTOR = FLASH_BASE | VECT_TAB_OFFSET; /* Vector Table Relocation in Internal FLASH. */ +#endif +} + +/** + * @brief Update SystemCoreClock according to Clock Register Values + * The SystemCoreClock variable contains the core clock (HCLK), it can + * be used by the user application to setup the SysTick timer or configure + * other parameters. + * + * @note Each time the core clock (HCLK) changes, this function must be called + * to update SystemCoreClock variable value. Otherwise, any configuration + * based on this variable will be incorrect. + * + * @note - The system frequency computed by this function is not the real + * frequency in the chip. It is calculated based on the predefined + * constant and the selected clock source: + * + * - If SYSCLK source is MSI, SystemCoreClock will contain the MSI + * value as defined by the MSI range. + * + * - If SYSCLK source is HSI, SystemCoreClock will contain the HSI_VALUE(*) + * + * - If SYSCLK source is HSE, SystemCoreClock will contain the HSE_VALUE(**) + * + * - If SYSCLK source is PLL, SystemCoreClock will contain the HSE_VALUE(**) + * or HSI_VALUE(*) multiplied/divided by the PLL factors. + * + * (*) HSI_VALUE is a constant defined in stm32l1xx.h file (default value + * 16 MHz) but the real value may vary depending on the variations + * in voltage and temperature. + * + * (**) HSE_VALUE is a constant defined in stm32l1xx.h file (default value + * 8 MHz), user has to ensure that HSE_VALUE is same as the real + * frequency of the crystal used. Otherwise, this function may + * have wrong result. + * + * - The result of this function could be not correct when using fractional + * value for HSE crystal. + * @param None + * @retval None + */ +void SystemCoreClockUpdate (void) +{ + uint32_t tmp = 0, pllmul = 0, plldiv = 0, pllsource = 0, msirange = 0; + + /* Get SYSCLK source -------------------------------------------------------*/ + tmp = RCC->CFGR & RCC_CFGR_SWS; + + switch (tmp) + { + case 0x00: /* MSI used as system clock */ + msirange = (RCC->ICSCR & RCC_ICSCR_MSIRANGE) >> 13; + SystemCoreClock = (32768 * (1 << (msirange + 1))); + break; + case 0x04: /* HSI used as system clock */ + SystemCoreClock = HSI_VALUE; + break; + case 0x08: /* HSE used as system clock */ + SystemCoreClock = HSE_VALUE; + break; + case 0x0C: /* PLL used as system clock */ + /* Get PLL clock source and multiplication factor ----------------------*/ + pllmul = RCC->CFGR & RCC_CFGR_PLLMUL; + plldiv = RCC->CFGR & RCC_CFGR_PLLDIV; + pllmul = PLLMulTable[(pllmul >> 18)]; + plldiv = (plldiv >> 22) + 1; + + pllsource = RCC->CFGR & RCC_CFGR_PLLSRC; + + if (pllsource == 0x00) + { + /* HSI oscillator clock selected as PLL clock entry */ + SystemCoreClock = (((HSI_VALUE) * pllmul) / plldiv); + } + else + { + /* HSE selected as PLL clock entry */ + SystemCoreClock = (((HSE_VALUE) * pllmul) / plldiv); + } + break; + default: /* MSI used as system clock */ + msirange = (RCC->ICSCR & RCC_ICSCR_MSIRANGE) >> 13; + SystemCoreClock = (32768 * (1 << (msirange + 1))); + break; + } + /* Compute HCLK clock frequency --------------------------------------------*/ + /* Get HCLK prescaler */ + tmp = AHBPrescTable[((RCC->CFGR & RCC_CFGR_HPRE) >> 4)]; + /* HCLK clock frequency */ + SystemCoreClock >>= tmp; +} + +/** + * @brief Configures the System clock frequency, AHB/APBx prescalers and Flash + * settings. + * @note This function should be called only once the RCC clock configuration + * is reset to the default reset state (done in SystemInit() function). + * @param None + * @retval None + */ +static void SetSysClock(void) +{ + __IO uint32_t StartUpCounter = 0, HSEStatus = 0; + + /* SYSCLK, HCLK, PCLK2 and PCLK1 configuration ---------------------------*/ + /* Enable HSE */ + RCC->CR |= ((uint32_t)RCC_CR_HSEON); + + /* Wait till HSE is ready and if Time out is reached exit */ + do + { + HSEStatus = RCC->CR & RCC_CR_HSERDY; + StartUpCounter++; + } while((HSEStatus == 0) && (StartUpCounter != HSE_STARTUP_TIMEOUT)); + + if ((RCC->CR & RCC_CR_HSERDY) != RESET) + { + HSEStatus = (uint32_t)0x01; + } + else + { + HSEStatus = (uint32_t)0x00; + } + + if (HSEStatus == (uint32_t)0x01) + { + /* Enable 64-bit access */ + FLASH->ACR |= FLASH_ACR_ACC64; + + /* Enable Prefetch Buffer */ + FLASH->ACR |= FLASH_ACR_PRFTEN; + + /* Flash 1 wait state */ + FLASH->ACR |= FLASH_ACR_LATENCY; + + /* Power enable */ + RCC->APB1ENR |= RCC_APB1ENR_PWREN; + + /* Select the Voltage Range 1 (1.8 V) */ + PWR->CR = PWR_CR_VOS_0; + + /* Wait Until the Voltage Regulator is ready */ + while((PWR->CSR & PWR_CSR_VOSF) != RESET) + { + } + + /* HCLK = SYSCLK /1*/ + RCC->CFGR |= (uint32_t)RCC_CFGR_HPRE_DIV1; + + /* PCLK2 = HCLK /1*/ + RCC->CFGR |= (uint32_t)RCC_CFGR_PPRE2_DIV1; + + /* PCLK1 = HCLK /1*/ + RCC->CFGR |= (uint32_t)RCC_CFGR_PPRE1_DIV1; + + /* PLL configuration */ + RCC->CFGR &= (uint32_t)((uint32_t)~(RCC_CFGR_PLLSRC | RCC_CFGR_PLLMUL | + RCC_CFGR_PLLDIV)); + RCC->CFGR |= (uint32_t)(RCC_CFGR_PLLSRC_HSE | RCC_CFGR_PLLMUL12 | RCC_CFGR_PLLDIV3); + + /* Enable PLL */ + RCC->CR |= RCC_CR_PLLON; + + /* Wait till PLL is ready */ + while((RCC->CR & RCC_CR_PLLRDY) == 0) + { + } + + /* Select PLL as system clock source */ + RCC->CFGR &= (uint32_t)((uint32_t)~(RCC_CFGR_SW)); + RCC->CFGR |= (uint32_t)RCC_CFGR_SW_PLL; + + /* Wait till PLL is used as system clock source */ + while ((RCC->CFGR & (uint32_t)RCC_CFGR_SWS) != (uint32_t)RCC_CFGR_SWS_PLL) + { + } + } + else + { + /* If HSE fails to start-up, the application will have wrong clock + configuration. User can add here some code to deal with this error */ + } +} + +#ifdef DATA_IN_ExtSRAM +/** + * @brief Setup the external memory controller. + * Called in SystemInit() function before jump to main. + * This function configures the external SRAM mounted on STM32L152D_EVAL board + * This SRAM will be used as program data memory (including heap and stack). + * @param None + * @retval None + */ +void SystemInit_ExtMemCtl(void) +{ +/*-- GPIOs Configuration -----------------------------------------------------*/ +/* + +-------------------+--------------------+------------------+------------------+ + + SRAM pins assignment + + +-------------------+--------------------+------------------+------------------+ + | PD0 <-> FSMC_D2 | PE0 <-> FSMC_NBL0 | PF0 <-> FSMC_A0 | PG0 <-> FSMC_A10 | + | PD1 <-> FSMC_D3 | PE1 <-> FSMC_NBL1 | PF1 <-> FSMC_A1 | PG1 <-> FSMC_A11 | + | PD4 <-> FSMC_NOE | PE7 <-> FSMC_D4 | PF2 <-> FSMC_A2 | PG2 <-> FSMC_A12 | + | PD5 <-> FSMC_NWE | PE8 <-> FSMC_D5 | PF3 <-> FSMC_A3 | PG3 <-> FSMC_A13 | + | PD8 <-> FSMC_D13 | PE9 <-> FSMC_D6 | PF4 <-> FSMC_A4 | PG4 <-> FSMC_A14 | + | PD9 <-> FSMC_D14 | PE10 <-> FSMC_D7 | PF5 <-> FSMC_A5 | PG5 <-> FSMC_A15 | + | PD10 <-> FSMC_D15 | PE11 <-> FSMC_D8 | PF12 <-> FSMC_A6 | PG10<-> FSMC_NE2 | + | PD11 <-> FSMC_A16 | PE12 <-> FSMC_D9 | PF13 <-> FSMC_A7 |------------------+ + | PD12 <-> FSMC_A17 | PE13 <-> FSMC_D10 | PF14 <-> FSMC_A8 | + | PD13 <-> FSMC_A18 | PE14 <-> FSMC_D11 | PF15 <-> FSMC_A9 | + | PD14 <-> FSMC_D0 | PE15 <-> FSMC_D12 |------------------+ + | PD15 <-> FSMC_D1 |--------------------+ + +-------------------+ +*/ + + /* Enable GPIOD, GPIOE, GPIOF and GPIOG interface clock */ + RCC->AHBENR = 0x000080D8; + + /* Connect PDx pins to FSMC Alternate function */ + GPIOD->AFR[0] = 0x00CC00CC; + GPIOD->AFR[1] = 0xCCCCCCCC; + /* Configure PDx pins in Alternate function mode */ + GPIOD->MODER = 0xAAAA0A0A; + /* Configure PDx pins speed to 40 MHz */ + GPIOD->OSPEEDR = 0xFFFF0F0F; + /* Configure PDx pins Output type to push-pull */ + GPIOD->OTYPER = 0x00000000; + /* No pull-up, pull-down for PDx pins */ + GPIOD->PUPDR = 0x00000000; + + /* Connect PEx pins to FSMC Alternate function */ + GPIOE->AFR[0] = 0xC00000CC; + GPIOE->AFR[1] = 0xCCCCCCCC; + /* Configure PEx pins in Alternate function mode */ + GPIOE->MODER = 0xAAAA800A; + /* Configure PEx pins speed to 40 MHz */ + GPIOE->OSPEEDR = 0xFFFFC00F; + /* Configure PEx pins Output type to push-pull */ + GPIOE->OTYPER = 0x00000000; + /* No pull-up, pull-down for PEx pins */ + GPIOE->PUPDR = 0x00000000; + + /* Connect PFx pins to FSMC Alternate function */ + GPIOF->AFR[0] = 0x00CCCCCC; + GPIOF->AFR[1] = 0xCCCC0000; + /* Configure PFx pins in Alternate function mode */ + GPIOF->MODER = 0xAA000AAA; + /* Configure PFx pins speed to 40 MHz */ + GPIOF->OSPEEDR = 0xFF000FFF; + /* Configure PFx pins Output type to push-pull */ + GPIOF->OTYPER = 0x00000000; + /* No pull-up, pull-down for PFx pins */ + GPIOF->PUPDR = 0x00000000; + + /* Connect PGx pins to FSMC Alternate function */ + GPIOG->AFR[0] = 0x00CCCCCC; + GPIOG->AFR[1] = 0x00000C00; + /* Configure PGx pins in Alternate function mode */ + GPIOG->MODER = 0x00200AAA; + /* Configure PGx pins speed to 40 MHz */ + GPIOG->OSPEEDR = 0x00300FFF; + /* Configure PGx pins Output type to push-pull */ + GPIOG->OTYPER = 0x00000000; + /* No pull-up, pull-down for PGx pins */ + GPIOG->PUPDR = 0x00000000; + +/*-- FSMC Configuration ------------------------------------------------------*/ + /* Enable the FSMC interface clock */ + RCC->AHBENR = 0x400080D8; + + /* Configure and enable Bank1_SRAM3 */ + FSMC_Bank1->BTCR[4] = 0x00001011; + FSMC_Bank1->BTCR[5] = 0x00000300; + FSMC_Bank1E->BWTR[4] = 0x0FFFFFFF; +/* + Bank1_SRAM3 is configured as follow: + + p.FSMC_AddressSetupTime = 0; + p.FSMC_AddressHoldTime = 0; + p.FSMC_DataSetupTime = 3; + p.FSMC_BusTurnAroundDuration = 0; + p.FSMC_CLKDivision = 0; + p.FSMC_DataLatency = 0; + p.FSMC_AccessMode = FSMC_AccessMode_A; + + FSMC_NORSRAMInitStructure.FSMC_Bank = FSMC_Bank1_NORSRAM3; + FSMC_NORSRAMInitStructure.FSMC_DataAddressMux = FSMC_DataAddressMux_Disable; + FSMC_NORSRAMInitStructure.FSMC_MemoryType = FSMC_MemoryType_SRAM; + FSMC_NORSRAMInitStructure.FSMC_MemoryDataWidth = FSMC_MemoryDataWidth_16b; + FSMC_NORSRAMInitStructure.FSMC_BurstAccessMode = FSMC_BurstAccessMode_Disable; + FSMC_NORSRAMInitStructure.FSMC_AsynchronousWait = FSMC_AsynchronousWait_Disable; + FSMC_NORSRAMInitStructure.FSMC_WaitSignalPolarity = FSMC_WaitSignalPolarity_Low; + FSMC_NORSRAMInitStructure.FSMC_WrapMode = FSMC_WrapMode_Disable; + FSMC_NORSRAMInitStructure.FSMC_WaitSignalActive = FSMC_WaitSignalActive_BeforeWaitState; + FSMC_NORSRAMInitStructure.FSMC_WriteOperation = FSMC_WriteOperation_Enable; + FSMC_NORSRAMInitStructure.FSMC_WaitSignal = FSMC_WaitSignal_Disable; + FSMC_NORSRAMInitStructure.FSMC_ExtendedMode = FSMC_ExtendedMode_Disable; + FSMC_NORSRAMInitStructure.FSMC_WriteBurst = FSMC_WriteBurst_Disable; + FSMC_NORSRAMInitStructure.FSMC_ReadWriteTimingStruct = &p; + FSMC_NORSRAMInitStructure.FSMC_WriteTimingStruct = &p; + + FSMC_NORSRAMInit(&FSMC_NORSRAMInitStructure); + + FSMC_NORSRAMCmd(FSMC_Bank1_NORSRAM3, ENABLE); +*/ + +} +#endif /* DATA_IN_ExtSRAM */ + +/** + * @} + */ + +/** + * @} + */ + +/** + * @} + */ + +/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ diff --git a/Libraries/CMSIS/Documentation/Core/html/CMSIS_CORE_Files.png b/Libraries/CMSIS/Documentation/Core/html/CMSIS_CORE_Files.png new file mode 100644 index 0000000000000000000000000000000000000000..a542159e74046b623789b341ef7f1b144e5385d0 GIT binary patch literal 20924 zcmYJabzGC*|38d`2nZ+&NQ($a_vltaQt3uw)Cd`!0uq7((lA1iZWuKhk!Exa7%8K3 zbpD3#&;7ms;Bh^6uEVM8T<00D*Y!nHU6GiOnh*;Mi&$Cd^?NKV>@QeY_pl#eV@l}Q zXZA4{0v9C%Fcua`$KBt(Zs!6kOyNE7dqp{{vO(Gn%nw`}Sv6TKtjZXos}FdX-_I?T z-m76@`LJMNefo@rb%81Rw2p=4&WnY$X^w>@mV$*v>5|^?P67+-9kcRlS#2-VoeZ@C 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zXOzMJ;tS8CV@wPZ5-uV;D;rNf{WM}a$Kb^A;~4qqqX-EOvC)ut`I7oBlId-RkPaU{ zjK)oyqGzw0aDoy^?u+Ad`BDOU+;}4%ef%*xO`d4ltSM$pn}+_k-l`;*l>OBBrx6?y ztm2m=NryNok|Ig(hRvHWf8IQ-|MO2eA7O}U5ryefr{WgAFR|0CtW3;!>rEwzC5-g1 zF=N$$qZdz_4x!aGt#F=Fv_Ydrc#`#OT)!UUCq9FC=67YP5SvjGC=yctOq!MCcTeOe zzGNf1I{Mc|EfMJ}M}Np^u+ibI9M(ZPGxY{6TDVY2qhZ5`p$Wn9%1bY!VWWn)ZQwv9 z4F!a6OrHUfZUVYSjT_@H=I_$2D~=pKqB>N(UFr1X + + + +MISRA-C:2004 Compliance Exceptions + + + + + + + + + + + + + + +
    + +
    +
    +
    + +
    +
    +
    +
    MISRA-C:2004 Compliance Exceptions
    +
    +
    +

    CMSIS-CORE uses the common coding rules for CMSIS components that are documented under Introduction .

    +

    CMSIS-CORE violates the following MISRA-C:2004 rules:

    +
      +
    • Required Rule 8.5, object/function definition in header file.
      + Violated since function definitions in header files are used to allow 'inlining'.
      • +
    +
      +
    • Required Rule 18.4, declaration of union type or object of union type: '{...}'.
      + Violated since unions are used for effective representation of core registers.
      • +
    +
      +
    • Advisory Rule 19.7, Function-like macro defined.
      + Violated since function-like macros are used to allow more efficient code.
      • +
    +
    +
    + + + + + diff --git a/Libraries/CMSIS/Documentation/Core/html/_reg_map_pg.html b/Libraries/CMSIS/Documentation/Core/html/_reg_map_pg.html new file mode 100644 index 0000000..bdf0347 --- /dev/null +++ b/Libraries/CMSIS/Documentation/Core/html/_reg_map_pg.html @@ -0,0 +1,305 @@ + + + + +Register Mapping + + + + + + + + + + + + + +
    + +
    + + + + + + + + + + + +
    +
    CMSIS-CORE +  Version 3.01 +
    +
    CMSIS-CORE support for Cortex-M processor-based devices
    +
    +
    + +
    + +
    + + + +
    +
    + +
    +
    +
    + +
    +
    +
    +
    Register Mapping
    +
    +
    +

    The table below associates some common register names used in CMSIS to the register names used in Technical Reference Manuals.

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    CMSIS Register Name Cortex-M3 and Cortex-M4 Cortex-M0 and Cortex-M0+ Register Name
    Nested Vectored Interrupt Controller (NVIC) Register Access
    NVIC->ISER[] NVIC_ISER0..7 ISER Interrupt Set-Enable Registers
    NVIC->ICER[] NVIC_ICER0..7 ICER Interrupt Clear-Enable Registers
    NVIC->ISPR[] NVIC_ISPR0..7 ISPR Interrupt Set-Pending Registers
    NVIC->ICPR[] NVIC_ICPR0..7 ICPR Interrupt Clear-Pending Registers
    NVIC->IABR[] NVIC_IABR0..7 - Interrupt Active Bit Register
    NVIC->IP[] NVIC_IPR0..59 IPR0..7 Interrupt Priority Register
    NVIC->STIR STIR - Software Triggered Interrupt Register
    System Control Block (SCB) Register Access
    SCB->CPUID CPUID CPUID CPUID Base Register
    SCB->ICSR ICSR ICSR Interrupt Control and State Register
    SCB->VTOR VTOR - Vector Table Offset Register
    SCB->AIRCR AIRCR AIRCR Application Interrupt and Reset Control Register
    SCB->SCR SCR SCR System Control Register
    SCB->CCR CCR CCR Configuration and Control Register
    SCB->SHP[] SHPR1..3 SHPR2..3 System Handler Priority Registers
    SCB->SHCSR SHCSR SHCSR System Handler Control and State Register
    SCB->CFSR CFSR - Configurable Fault Status Registers
    SCB->HFSR HFSR - HardFault Status Register
    SCB->DFSR DFSR - Debug Fault Status Register
    SCB->MMFAR MMFAR - MemManage Fault Address Register
    SCB->BFAR BFAR - BusFault Address Register
    SCB->AFSR AFSR - Auxiliary Fault Status Register
    SCB->PFR[] ID_PFR0..1 - Processor Feature Registers
    SCB->DFR ID_DFR0 - Debug Feature Register
    SCB->ADR ID_AFR0 - Auxiliary Feature Register
    SCB->MMFR[] ID_MMFR0..3 - Memory Model Feature Registers
    SCB->ISAR[] ID_ISAR0..4 - Instruction Set Attributes Registers
    SCB->CPACR CPACR - Coprocessor Access Control Register
    System Control and ID Registers not in the SCB (SCnSCB) Register Access
    SCnSCB->ICTR ICTR - Interrupt Controller Type Register
    SCnSCB->ACTLR ACTLR - Auxiliary Control Register
    System Timer (SysTick) Control and Status Register Access
    SysTick->CTRL STCSR SYST_CSR SysTick Control and Status Register
    SysTick->LOAD STRVR SYST_RVR SysTick Reload Value Register
    SysTick->VAL STCVR SYST_CVR SysTick Current Value Register
    SysTick->CALIB STCR SYST_CALIB SysTick Calibaration Value Register
    Data Watchpoint and Trace (DWT) Register Access
    DWT->CTRL DWT_CTRL - Control Register
    DWT->CYCCNT DWT_CYCCNT - Cycle Count Register
    DWT->CPICNT DWT_CPICNT - CPI Count Register
    DWT->EXCCNT DWT_EXCCNT - Exception Overhead Count Register
    DWT->SLEEPCNT DWT_SLEEPCNT - Sleep Count Register
    DWT->LSUCNT DWT_LSUCNT - LSU Count Register
    DWT->FOLDCNT DWT_FOLDCNT - Folded-instruction Count Register
    DWT->PCSR DWT_PCSR - Program Counter Sample Register
    DWT->COMP0..3 DWT_COMP0..3 - Comparator Register 0..3
    DWT->MASK0..3 DWT_MASK0..3 - Mask Register 0..3
    DWT->FUNCTION0..3 DWT_FUNCTION0..3 - Function Register 0..3
    Instrumentation Trace Macrocell (ITM) Register Access
    ITM->PORT[] ITM_STIM0..31 - Stimulus Port Registers
    ITM->TER ITM_TER - Trace Enable Register
    ITM->TPR ITM_TPR - ITM Trace Privilege Register
    ITM->TCR ITM_TCR - Trace Control Register
    Trace Port Interface (TPIU) Register Access
    TPI->SSPSR TPIU_SSPR - Supported Parallel Port Size Register
    TPI->CSPSR TPIU_CSPSR - Current Parallel Port Size Register
    TPI->ACPR TPIU_ACPR - Asynchronous Clock Prescaler Register
    TPI->SPPR TPIU_SPPR - Selected Pin Protocol Register
    TPI->FFSR TPIU_FFSR - Formatter and Flush Status Register
    TPI->FFCR TPIU_FFCR - Formatter and Flush Control Register
    TPI->FSCR TPIU_FSCR - Formatter Synchronization Counter Register
    TPI->TRIGGER TRIGGER - TRIGGER
    TPI->FIFO0 FIFO data 0 - Integration ETM Data
    TPI->ITATBCTR2 ITATBCTR2 - ITATBCTR2
    TPI->ITATBCTR0 ITATBCTR0 - ITATBCTR0
    TPI->FIFO1 FIFO data 1 - Integration ITM Data
    TPI->ITCTRL TPIU_ITCTRL - Integration Mode Control
    TPI->CLAIMSET CLAIMSET - Claim tag set
    TPI->CLAIMCLR CLAIMCLR - Claim tag clear
    TPI->DEVID TPIU_DEVID - TPIU_DEVID
    TPI->DEVTYPE TPIU_DEVTYPE - TPIU_DEVTYPE
    Memory Protection Unit (MPU) Register Access
    MPU->TYPE MPU_TYPE - MPU Type Register
    MPU->CTRL MPU_CTRL - MPU Control Register
    MPU->RNR MPU_RNR - MPU Region Number Register
    MPU->RBAR MPU_RBAR - MPU Region Base Address Register
    MPU->RASR MPU_RASR - MPU Region Attribute and Size Register
    MPU->RBAR_A1..3 MPU_RBAR_A1..3 - MPU alias Register
    MPU->RSAR_A1..3 MPU_RSAR_A1..3 - MPU alias Register
    Floating Point Unit (FPU) Register Access [only Cortex-M4 with FPU]
    FPU->FPCCR FPCCR - FP Context Control Register
    FPU->FPCAR FPCAR - FP Context Address Register
    FPU->FPDSCR FPDSCR - FP Default Status Control Register
    FPU->MVFR0..1 MVFR0..1 - Media and VFP Feature Registers
    +
    +
    + + + + + diff --git a/Libraries/CMSIS/Documentation/Core/html/_templates_pg.html b/Libraries/CMSIS/Documentation/Core/html/_templates_pg.html new file mode 100644 index 0000000..fbaf463 --- /dev/null +++ b/Libraries/CMSIS/Documentation/Core/html/_templates_pg.html @@ -0,0 +1,215 @@ + + + + +Template Files + + + + + + + + + + + + + +
    + +
    + + + + + + + + + + + +
    +
    CMSIS-CORE +  Version 3.01 +
    +
    CMSIS-CORE support for Cortex-M processor-based devices
    +
    +
    + +
    + +
    + + + +
    +
    + +
    +
    +
    + +
    +
    +
    +
    Template Files
    +
    +
    +

    ARM supplies CMSIS-CORE template files for the all supported Cortex-M processors and various compiler vendors. Refer to the list of Tested and Verified Toolchains for compliancy. These template files include the following:

    +
      +
    • Register names of the Core Peripherals and names of the Core Exception Vectors.
      • +
    • Functions to access core peripherals, special CPU instructions and SIMD instructions (for Cortex-M4)
      • +
    • Generic startup code and system configuration code.
      • +
    +

    The detailed file structure of the CMSIS-CORE is shown in the following picture.

    +
    +CMSIS_CORE_Files.png +
    +CMSIS-CORE File Structure
    +

    +Template Files

    +

    The CMSIS-CORE template files should be extended by the silicon vendor to reflect the actual device and device peripherals. Silicon vendors add in this context the:

    +
      +
    • Device Peripheral Access Layer that provides definitions for device-specific peripherals.
      • +
    • Access Functions for Peripherals (optional) that provides additional helper functions to access device-specific peripherals.
      • +
    • Interrupt vectors in the startup file that are device specific.
      • +
    + + + + + + + + + + + + + + + + + +
    Template File Description
    ".\Device\_Template_Vendor\Vendor\Device\Source\ARM\startup_Device.s" Startup file template for ARM C/C++ Compiler.
    ".\Device\_Template_Vendor\Vendor\Device\Source\GCC\startup_Device.s" Startup file template for GNU GCC ARM Embedded Compiler.
    ".\Device\_Template_Vendor\Vendor\Device\Source\G++\startup_Device.s" Startup file template for GNU Sourcery G++ Compiler.
    ".\Device\_Template_Vendor\Vendor\Device\Source\IAR\startup_Device.s" Startup file template for IAR C/C++ Compiler.
    ".\Device\_Template_Vendor\Vendor\Device\Source\system_Device.c" Generic system_Device.c file for system configuration (i.e. processor clock and memory bus system).
    ".\Device\_Template_Vendor\Vendor\Device\Include\Device.h" Generic device header file. Needs to be extended with the device-specific peripheral registers. Optionally functions that access the peripherals can be part of that file.
    ".\Device\_Template_Vendor\Vendor\Device\Include\system_Device.h" Generic system device configuration include file.
    +

    In addition ARM provides the following core header files that do not need any modifications.

    + + + + + + + + + + + +
    Core Header Files Description
    core_<cpu>.h Defines the core peripherals and provides helper functions that access the core registers. This file is available for all supported processors:
      +
    • core_cm0.h: for the Cortex-M0 processor
      • +
    • core_cm0plus.h: for the Cortex-M0+ processor
      • +
    • core_cm3.h: for the Cortex-M0 processor
      • +
    • core_cm4.h: for the Cortex-M0 processor
      • +
    • core_sc000.h: for the SecurCore SC000 processor
      • +
    • core_sc300.h: for the SecurCore SC300 processor
      • +
    +
    core_cmInstr.h Defines intrinsic functions to access special Cortex-M instructions.
    core_cmFunc.h Defines functions to access the Cortex-M core peripherals.
    core_cm4_simd.h Defines intrinsic functions to access the Cortex-M4 SIMD instructions.
    +

    +Adaption of Template Files to Devices

    +

    Copy the complete folder including files and replace:

    +
      +
    • folder name 'Vendor' with the abbreviation for the device vendor e.g.: NXP.
      • +
    • folder name 'Device' with the specific device name e.g.: LPC17xx.
      • +
    • in the filenames 'Device' with the specific device name e.g.: LPC17xx.
      • +
    +

    Each template file contains comments that start with ToDo: that describe a required modification. The template files contain placeholders:

    + + + + + + + + + + + +
    Placeholder Replaced with
    <Device> the specific device name or device family name; i.e. LPC17xx.
    <DeviceInterrupt> a specific interrupt name of the device; i.e. TIM1 for Timer 1.
    <DeviceAbbreviation> short name or abbreviation of the device family; i.e. LPC.
    Cortex-M# the specific Cortex-M processor name; i.e. Cortex-M3.
    +

    The adaption of the template files is described in detail on the following pages:

    + +
    +
    + + + + + diff --git a/Libraries/CMSIS/Documentation/Core/html/_using__a_r_m_pg.html b/Libraries/CMSIS/Documentation/Core/html/_using__a_r_m_pg.html new file mode 100644 index 0000000..a69504c --- /dev/null +++ b/Libraries/CMSIS/Documentation/Core/html/_using__a_r_m_pg.html @@ -0,0 +1,167 @@ + + + + +Using CMSIS with generic ARM Processors + + + + + + + + + + + + + +
    + +
    + + + + + + + + + + + +
    +
    CMSIS-CORE +  Version 3.01 +
    +
    CMSIS-CORE support for Cortex-M processor-based devices
    +
    +
    + +
    + +
    + + + +
    +
    + +
    +
    +
    + +
    +
    +
    +
    Using CMSIS with generic ARM Processors
    +
    +
    +

    ARM provides CMSIS-CORE files for the supported ARM Processors and for various compiler vendors. These files can be used when standard ARM processors should be used in a project. The table below lists the folder and device names of the ARM processors.

    + + + + + + + + + + + + + + + +
    Folder Processor Description
    ".\Device\ARM\ARMCM0" Cortex-M0 Contains Include and Source template files configured for the Cortex-M0 processor. The device name is ARMCM0 and the name of the Device Header File <device.h> is <ARMCM0.h>.
    ".\Device\ARM\ARMCM0plus" Cortex-M0+ Contains Include and Source template files configured for the Cortex-M0+ processor. The device name is ARMCM0plus and the name of the Device Header File <device.h> is <ARMCM0plus.h>.
    ".\Device\ARM\ARMCM3" Cortex-M3 Contains Include and Source template files configured for the Cortex-M3 processor. The device name is ARMCM3 and the name of the Device Header File <device.h> is <ARMCM3.h>.
    ".\Device\ARM\ARMCM4" Cortex-M4 Contains Include and Source template files configured for the Cortex-M4 processor. The device name is ARMCM4 and the name of the Device Header File <device.h> is <ARMCM4.h>.
    ".\Device\ARM\ARMSC000" SecurCore SC000 Contains Include and Source template files configured for the SecurCore SC000 processor. The device name is ARMSC000 and the name of the Device Header File <device.h> is <ARMSC000.h>.
    ".\Device\ARM\ARMSC300" SecurCore SC300 Contains Include and Source template files configured for the SecurCore SC300 processor. The device name is ARMSC300 and the name of the Device Header File <device.h> is <ARMSC300.h>.
    +

    +Create generic Libraries with CMSIS

    +

    The CMSIS Processor and Core Peripheral files allow also to create generic libraries. The CMSIS-DSP Libraries are an example for such a generic library.

    +

    To build a generic Library set the define __CMSIS_GENERIC and include the relevant core_<cpu>.h CMSIS CPU & Core Access header file for the processor. The define __CMSIS_GENERIC disables device-dependent features such as the SysTick timer and the Interrupt System. Refer to Configuration of the Processor and Core Peripherals for a list of the available core_<cpu>.h header files.

    +

    Example:

    +

    The following code section shows the usage of the core_<cpu>.h header files to build a generic library for Cortex-M0, Cortex-M3, or Cortex-M4. To select the processor the source code uses the define CORTEX_M4, CORTEX_M3, or CORTEX_M0. By using this header file, the source code can access the functions for Core Register Access, Intrinsic Functions for CPU Instructions, Intrinsic Functions for SIMD Instructions [only Cortex-M4], and Debug Access.

    +
    #define __CMSIS_GENERIC              /* disable NVIC and Systick functions */
+
+#if defined (CORTEX_M4)
+  #include "core_cm4.h"
+#elif defined (CORTEX_M3)
+  #include "core_cm3.h"
+#elif defined (CORTEX_M0)
+  #include "core_cm0.h"
+#elif defined (CORTEX_M0PLUS)
+  #include "core_cm0plus.h"
+#else
+  #error "Processor not specified or unsupported."
+#endif
+
    +
    + + + + + diff --git a/Libraries/CMSIS/Documentation/Core/html/_using_pg.html b/Libraries/CMSIS/Documentation/Core/html/_using_pg.html new file mode 100644 index 0000000..4e6a54b --- /dev/null +++ b/Libraries/CMSIS/Documentation/Core/html/_using_pg.html @@ -0,0 +1,216 @@ + + + + +Using CMSIS in Embedded Applications + + + + + + + + + + + + + +
    + +
    + + + + + + + + + + + +
    +
    CMSIS-CORE +  Version 3.01 +
    +
    CMSIS-CORE support for Cortex-M processor-based devices
    +
    +
    + +
    + +
    + + + +
    +
    + +
    +
    +
    + +
    +
    +
    +
    Using CMSIS in Embedded Applications
    +
    +
    +

    To use the CMSIS-CORE the following files are added to the embedded application:

    + +
    Note:
    The files Startup File startup_<device>.s and System Configuration Files system_<device>.c and system_<device>.h may require application specific adaptations and therefore should be copied into the application project folder prior configuration. The Device Header File <device.h> is included in all source files that need device access and can be stored on a central include folder that is generic for all projects.
    +

    The Startup File startup_<device>.s is executed after reset and calls SystemInit. After the system initialization control is transferred to the C/C++ run-time library which performs initialization and calls the main function in the user code. In addition the Startup File startup_<device>.s contains all exception and interrupt vectors and implements a default function for every interrupt. It may also contain stack and heap configurations for the user application.

    +

    The System Configuration Files system_<device>.c and system_<device>.h performs the setup for the processor clock. The variable SystemCoreClock indicates the CPU clock speed. System and Clock Configuration describes the minimum feature set. In addition the file may contain functions for the memory BUS setup and clock re-configuration.

    +

    The Device Header File <device.h> is the central include file that the application programmer is using in the C source code. It provides the following features:

    + +
    +CMSIS_CORE_Files_user.png +
    +CMSIS-CORE User Files
    +

    The CMSIS-CORE are device specific. In addition, the Startup File startup_<device>.s is also compiler vendor specific. The various compiler vendor tool chains may provide folders that contain the CMSIS files for each supported device. Using CMSIS with generic ARM Processors explains how to use CMSIS-CORE for ARM processors.

    +

    For example, the following files are provided in MDK-ARM to support the STM32F10x Connectivity Line device variants:

    + + + + + + + + + + + +
    File Description
    ".\ARM\Startup\ST\STM32F10x\startup_stm32f10x_cl.s" Startup File startup_<device>.s for the STM32F10x Connectivity Line device variants.
    ".\ARM\Startup\ST\STM32F10x\system_stmf10x.c" System Configuration Files system_<device>.c and system_<device>.h for the STM32F10x device families.
    ".\ARM\INC\ST\STM32F10x\stm32f10x.h" Device Header File <device.h> for the STM32F10x device families.
    ".\ARM\INC\ST\STM32F10x\system_stm32f10x.h" system_Device.h Template File for the STM32F10x device families.
    +
    Note:
    The silicon vendors create these device-specific CMSIS-CORE files based on Template Files provide by ARM.
    +

    Thereafter, the functions described under Reference can be used in the application.

    +

    A typical example for using the CMSIS layer is provided below. The example is based on a STM32F10x Device.

    +
    #include <stm32f10x.h>                           // File name depends on device used
+
+uint32_t volatile msTicks;                       // Counter for millisecond Interval
+
+void SysTick_Handler (void) {                    // SysTick Interrupt Handler
+  msTicks++;                                     // Increment Counter
+}
+
+void WaitForTick (void)  {
+  uint32_t curTicks;
+
+  curTicks = msTicks;                            // Save Current SysTick Value
+  while (msTicks == curTicks)  {                 // Wait for next SysTick Interrupt
+    __WFE ();                                    // Power-Down until next Event/Interrupt
+  }
+}
+
+void TIM1_UP_IRQHandler (void) {                 // Timer Interrupt Handler
+  ;                                              // Add user code here
+}
+
+void timer1_init(int frequency) {                // Set up Timer (device specific)
+  NVIC_SetPriority (TIM1_UP_IRQn, 1);            // Set Timer priority
+  NVIC_EnableIRQ (TIM1_UP_IRQn);                 // Enable Timer Interrupt
+}
+
+
+void Device_Initialization (void)  {             // Configure & Initialize MCU
+  if (SysTick_Config (SystemCoreClock / 1000)) { // SysTick 1mSec
+       : // Handle Error 
+  }
+  timer1_init ();                                // setup device-specific timer
+}
+
+
+// The processor clock is initialized by CMSIS startup + system file
+void main (void) {                                   // user application starts here
+  Device_Initialization ();                      // Configure & Initialize MCU
+  while (1)  {                                   // Endless Loop (the Super-Loop)
+    __disable_irq ();                            // Disable all interrupts
+    Get_InputValues ();                          // Read Values
+    __enable_irq ();                             // Enable all interrupts 
+    Calculation_Response ();                     // Calculate Results
+    Output_Response ();                          // Output Results
+    WaitForTick ();                              // Synchronize to SysTick Timer
+  }
+}
+
    +
    + + + + + diff --git a/Libraries/CMSIS/Documentation/Core/html/annotated.html b/Libraries/CMSIS/Documentation/Core/html/annotated.html new file mode 100644 index 0000000..58ecef1 --- /dev/null +++ b/Libraries/CMSIS/Documentation/Core/html/annotated.html @@ -0,0 +1,152 @@ + + + + +Data Structures + + + + + + + + + + + + + +
    + +
    + + + + + + + + + + + +
    +
    CMSIS-CORE +  Version 3.01 +
    +
    CMSIS-CORE support for Cortex-M processor-based devices
    +
    +
    + +
    + +
    + + + + +
    +
    + +
    +
    +
    + +
    +
    +
    +
    Data Structures
    +
    +
    +
    Here are the data structures with brief descriptions:
    + + + + + + + + + + + + + + +
    APSR_TypeUnion type to access the Application Program Status Register (APSR)
    CONTROL_TypeUnion type to access the Control Registers (CONTROL)
    CoreDebug_TypeStructure type to access the Core Debug Register (CoreDebug)
    DWT_TypeStructure type to access the Data Watchpoint and Trace Register (DWT)
    FPU_TypeStructure type to access the Floating Point Unit (FPU)
    IPSR_TypeUnion type to access the Interrupt Program Status Register (IPSR)
    ITM_TypeStructure type to access the Instrumentation Trace Macrocell Register (ITM)
    MPU_TypeStructure type to access the Memory Protection Unit (MPU)
    NVIC_TypeStructure type to access the Nested Vectored Interrupt Controller (NVIC)
    SCB_TypeStructure type to access the System Control Block (SCB)
    SCnSCB_TypeStructure type to access the System Control and ID Register not in the SCB
    SysTick_TypeStructure type to access the System Timer (SysTick)
    TPI_TypeStructure type to access the Trace Port Interface Register (TPI)
    xPSR_TypeUnion type to access the Special-Purpose Program Status Registers (xPSR)
    +
    +
    + + + + + diff --git a/Libraries/CMSIS/Documentation/Core/html/bc_s.png b/Libraries/CMSIS/Documentation/Core/html/bc_s.png new file mode 100644 index 0000000000000000000000000000000000000000..43f6f23bd0f83d23f1c2e3b9cbd312816eb4c111 GIT binary patch literal 702 zcmV;v0zv(WP)F_N(iil7IPXeigLJ2g&kfPK~D8;BS@!(exVaYG( z#K5FZixP>lEK{R{*39W%(5VE`UOj0N#42cGd*;7zpWHWGAGmM0ukSe-y#H~t+MWXd zr4Dy60L5ap4ega$QN`6N%D)AF%qju7^8bguqQIY&TMa(}*c|TQuQYIJWF7!!D~e@V zP_sUVJNPse@PGTg@8MXlsX*HaAPtcIyK?}bCWNe4l^7YLr0%mP=t_dVJ9CNikhws2 zAV(7B9iC8E67&uyAHIV#x>RYC;{Ys9Z)g($$c5YQQ?GnnVv_7y4Ig!SLn8n{dT!06 zf;yc>HEuKMV@_|#z8wI7Pvurwui~_0!55k&-8bJU!KoZcJX@5fU0d*l8cFB%w@RR4 zlzc6>%9K*FhjjcmtposY!<4V9Gh_?Xwl35jf@gs*-irhl(|+T0RUiC zHLVG7#wZD9jlk!ZRwHA{J{-L`nK&<(nk5Zqq-EJ3P5vOO*x&LeL%l}eO@?fBY}p^} zP3vT1&&1#2jGGH}WmzI0bNi#iY2fhri9AY)&u)WdKHUATc!{PH%P~GB7YQATcmHFgQ9gIUp-AF)%RoqGHAX000McNliru z)&&<0F)fD2eNX@Z010qNS#tmY3h)2`3h)6!tTdPa000DMK}|sb0I`n?{9y$E00Qz! zL_t(|+D%hkNRwd{e!g!%4z@XGYQ#uwZjnhsgQkx1Ux zRp^ZobYl^MBvED(LWXN-{?^oQqMQ43Tl@X~I`8LZZai%7%X!Xw&Uv20;rQnTtT;dq zZ{#~qTJ3IGlDN=8@{bx(rZA6J_=W&Qi3GJs;f~0oXsM8FW8D`!9Q9RaAS49@Qu~PJ zlGq3au)MyvFRq9W@EY$a`Y%CdG+mM0U~*1AYrA8Y_$0j1IrvioLYXk4*#vU*EwS?v%^5%1XxRIiCn8CP-TT%3j6T% z>~q|2=)?GxFG!|!m~8Q&w#=o?c!bFPvqMlMI;2YhMY}E|82NCFbmkNcZa+j^N}$f_ z!jEg)a9Z4l0{I5e|8e2hck+ zNJFJZ*{i`CQvU#0Cmn$JVM;H?R@a1}M2dPM%jovBASQ27*^hC1n#klkg}ojw2V$qF zh0Q3Ikf57wW+>)F18$;Af1V%FpXQBOS%TFFBr^rCG3=9K5eH>jmM{^2gB{ICeWIoR#Dk?^q=ZauSW49^^V9P;>-|!v5|5|vj9$@99Pjm zCUNkWU^7-j + + + +Data Structure Index + + + + + + + + + + + + + +
    + +
    + + + + + + + + + + + +
    +
    CMSIS-CORE +  Version 3.01 +
    +
    CMSIS-CORE support for Cortex-M processor-based devices
    +
    +
    + +
    + +
    + + + + +
    +
    + +
    +
    +
    + +
    +
    +
    +
    Data Structure Index
    +
    +
    +
    A | C | D | F | I | M | N | S | T | X
    + + + + + + + + + + + +
      A  
    +
      D  
    +    		ITM_Type   
      S  
    +
      X  
    +
      M  
    +
    APSR_Type   DWT_Type   SCB_Type   xPSR_Type   
      C  
    +
      F  
    +    		MPU_Type   SCnSCB_Type   
      N  
    +    		SysTick_Type   
    CONTROL_Type   FPU_Type   
      T  
    +
    CoreDebug_Type   
      I  
    +    		NVIC_Type   
    TPI_Type   
    IPSR_Type   
    +
    A | C | D | F | I | M | N | S | T | X
    +
    +
    + + + + + diff --git a/Libraries/CMSIS/Documentation/Core/html/closed.png b/Libraries/CMSIS/Documentation/Core/html/closed.png new file mode 100644 index 0000000000000000000000000000000000000000..09380f7a5a95e200ada81e0347f9b863c7443f3b GIT binary patch literal 126 zcmeAS@N?(olHy`uVBq!ia0vp^oFL4>1|%O$WD@{VuAVNAAr*{o?;hlJP~>0^cpav5 z^y~QpSC`6of96+VTk3Nm`LlxT!lO0G>u!AYwpEZY5M46=5u+=gcZ$}66?dK}xT^oy Z%&6ijBA|Yl;~~&M22WQ%mvv4FO#r)QD0u(? literal 0 HcmV?d00001 diff --git a/Libraries/CMSIS/Documentation/Core/html/cmsis.css b/Libraries/CMSIS/Documentation/Core/html/cmsis.css new file mode 100644 index 0000000..a5c4b8d --- /dev/null +++ b/Libraries/CMSIS/Documentation/Core/html/cmsis.css @@ -0,0 +1,957 @@ +/* The standard CSS for doxygen */ + +body, table, div, p, dl { + font-family: Lucida Grande, Verdana, Geneva, Arial, sans-serif; + font-size: 12px; +} + +/* CMSIS styles */ + +.style1 { + text-align: center; +} +.style2 { + color: #0000FF; + font-weight: normal; +} +.style3 { + text-align: left; +} +.style4 { + color: #008000; +} +.style5 { + color: #0000FF; +} +.style6 { + color: #000000; + font-style:italic; +} +.mand { + color: #0000FF; +} +.opt { + color: #008000; +} +.cond { + color: #990000; +} + +.choice +{ + background-color:#F7F9D0; +} +.seq +{ + background-color:#C9DECB; +} +.group1 +{ + background-color:#F8F1F1; +} +.group2 +{ + background-color:#DCEDEA; +} + + +ul ul { + list-style-type: disc; +} + +ul ul ul { + list-style-type: disc; +} + +ul.hierarchy { + color: green; +} + +em { + color: #000000; + font-style:italic; +} + + + +/* CMSIS Tables */ +table.cmtab1 { + padding: 4px; + border-collapse: collapse; + border: 1px solid #A3B4D7; + text-align: justify; + width:70%; +} + +th.cmtab1 { + background: #EBEFF6; + font-weight: bold; + height: 28px; +} + +td.cmtab1 { + padding:1px; + text-align: left; +} + +table.cmtable { + border-collapse:collapse; + text-align: justify; +} + +table.cmtable td, table.cmtable th { + border: 1px solid #2D4068; + padding: 3px 7px 2px; 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+ text-align: center; +} + +div.qindex, div.navtab{ + background-color: #EBEFF6; + border: 1px solid #A3B4D7; + text-align: center; + margin: 2px; + padding: 2px; +} + +div.qindex, div.navpath { + width: 100%; + line-height: 140%; +} + +div.navtab { + margin-right: 15px; +} + +/* @group Link Styling */ + +a { + color: #3D578C; + font-weight: normal; + text-decoration: none; +} + +.contents a:visited { + color: #4665A2; +} + +a:hover { + text-decoration: underline; +} + +a.qindex { + font-weight: bold; +} + +a.qindexHL { + font-weight: bold; + background-color: #9CAFD4; + color: #ffffff; + border: 1px double #869DCA; +} + +.contents a.qindexHL:visited { + color: #ffffff; +} + +a.el { + font-weight: bold; +} + +a.elRef { +} + +a.code { + color: #4665A2; +} + +a.codeRef { + color: #4665A2; +} + +/* @end */ + +dl.el { + margin-left: -1cm; +} + +.fragment { + font-family: monospace, fixed; + font-size: 105%; +} + +pre.fragment { + border: 1px solid #C4CFE5; + background-color: #FBFCFD; + padding: 4px 6px; + margin: 4px 8px 4px 2px; + overflow: auto; + word-wrap: break-word; + font-size: 9pt; + line-height: 125%; +} + +div.ah { + background-color: black; + font-weight: bold; + color: #ffffff; + margin-bottom: 3px; + margin-top: 3px; + padding: 0.2em; + border: solid thin #333; + border-radius: 0.5em; + -webkit-border-radius: .5em; + -moz-border-radius: .5em; + box-shadow: 2px 2px 3px #999; + -webkit-box-shadow: 2px 2px 3px #999; + -moz-box-shadow: rgba(0, 0, 0, 0.15) 2px 2px 2px; + background-image: -webkit-gradient(linear, left top, left bottom, from(#eee), to(#000),color-stop(0.3, #444)); + background-image: -moz-linear-gradient(center top, #eee 0%, #444 40%, #000); +} + +div.groupHeader { + margin-left: 16px; + margin-top: 12px; + font-weight: bold; +} + +div.groupText { + margin-left: 16px; + font-style: italic; +} + +body { + background: white; + color: black; + margin: 0; +} + +div.contents { + margin-top: 10px; + margin-left: 10px; + margin-right: 5px; +} + +td.indexkey { + background-color: #EBEFF6; + font-weight: bold; + border: 1px solid #C4CFE5; + margin: 2px 0px 2px 0; + padding: 2px 10px; +} + +td.indexvalue { + background-color: #EBEFF6; + border: 1px solid #C4CFE5; + padding: 2px 10px; + margin: 2px 0px; +} + +tr.memlist { + background-color: #EEF1F7; +} + +p.formulaDsp { + text-align: center; +} + +img.formulaDsp { + +} + +img.formulaInl { + vertical-align: middle; +} + +div.center { + text-align: center; + margin-top: 0px; + margin-bottom: 0px; + padding: 0px; +} + +div.center img { + border: 0px; +} + +address.footer { + text-align: right; + padding-right: 12px; +} + +img.footer { + border: 0px; + vertical-align: middle; +} + +/* @group Code Colorization */ + +span.keyword { + color: #008000 +} + +span.keywordtype { + color: #604020 +} + +span.keywordflow { + color: #e08000 +} + +span.comment { + color: #800000 +} + +span.preprocessor { + color: #806020 +} + +span.stringliteral { + color: #002080 +} + +span.charliteral { + color: #008080 +} + +span.vhdldigit { + color: #ff00ff +} + +span.vhdlchar { + color: #000000 +} + +span.vhdlkeyword { + color: #700070 +} + +span.vhdllogic { + color: #ff0000 +} + +/* @end */ + +/* +.search { + color: #003399; + font-weight: bold; +} + +form.search { + margin-bottom: 0px; + margin-top: 0px; +} + +input.search { + font-size: 75%; + color: #000080; + font-weight: normal; + background-color: #e8eef2; +} +*/ + +td.tiny { + font-size: 75%; +} + +.dirtab { + padding: 4px; + border-collapse: collapse; + border: 1px solid #A3B4D7; +} + +th.dirtab { + background: #EBEFF6; + font-weight: bold; +} + +hr { + height: 0px; + border: none; + border-top: 1px solid #4A6AAA; +} + +hr.footer { + height: 1px; +} + +/* @group Member Descriptions */ + +table.memberdecls { + border-spacing: 0px; + padding: 0px; +} + +.mdescLeft, .mdescRight, +.memItemLeft, .memItemRight, +.memTemplItemLeft, .memTemplItemRight, .memTemplParams { + background-color: #F9FAFC; + border: none; + margin: 4px; + padding: 1px 0 0 8px; +} + +.mdescLeft, .mdescRight { + padding: 0px 8px 4px 8px; + color: #555; +} + +.memItemLeft, .memItemRight, .memTemplParams { + border-top: 1px solid #C4CFE5; +} + +.memItemLeft, .memTemplItemLeft { + white-space: nowrap; +} + +.memItemRight { + width: 100%; +} + +.memTemplParams { + color: #4665A2; + white-space: nowrap; +} + +/* @end */ + +/* @group Member Details */ + +/* Styles for detailed member documentation */ + +.memtemplate { + font-size: 80%; + color: #4665A2; + font-weight: normal; + margin-left: 9px; +} + +.memnav { + background-color: #EBEFF6; + border: 1px solid #A3B4D7; + text-align: center; + margin: 2px; + margin-right: 15px; + padding: 2px; +} + +.mempage { + width: 100%; +} + +.memitem { + padding: 0; + margin-bottom: 10px; + margin-right: 5px; +} + +.memname { + white-space: nowrap; + font-weight: bold; + margin-left: 6px; +} + +.memproto { + border-top: 1px solid #A8B8D9; + border-left: 1px solid #A8B8D9; + border-right: 1px solid #A8B8D9; + padding: 6px 0px 6px 0px; + color: #253555; + font-weight: bold; + text-shadow: 0px 1px 1px rgba(255, 255, 255, 0.9); + /* opera specific markup */ + box-shadow: 5px 5px 5px rgba(0, 0, 0, 0.15); + border-top-right-radius: 8px; + border-top-left-radius: 8px; + /* firefox specific markup */ + -moz-box-shadow: rgba(0, 0, 0, 0.15) 5px 5px 5px; + -moz-border-radius-topright: 8px; + -moz-border-radius-topleft: 8px; + /* webkit specific markup */ + -webkit-box-shadow: 5px 5px 5px rgba(0, 0, 0, 0.15); + -webkit-border-top-right-radius: 8px; + -webkit-border-top-left-radius: 8px; + background-image:url('nav_f.png'); + background-repeat:repeat-x; + background-color: #E2E8F2; + +} + +.memdoc { + border-bottom: 1px solid #A8B8D9; + border-left: 1px solid #A8B8D9; + border-right: 1px solid #A8B8D9; + padding: 2px 5px; + background-color: #FBFCFD; + border-top-width: 0; + /* opera specific markup */ + border-bottom-left-radius: 8px; + border-bottom-right-radius: 8px; + box-shadow: 5px 5px 5px rgba(0, 0, 0, 0.15); + /* firefox specific markup */ + -moz-border-radius-bottomleft: 8px; + -moz-border-radius-bottomright: 8px; + -moz-box-shadow: rgba(0, 0, 0, 0.15) 5px 5px 5px; + background-image: -moz-linear-gradient(center top, #FFFFFF 0%, #FFFFFF 60%, #F7F8FB 95%, #EEF1F7); + /* webkit specific markup */ + -webkit-border-bottom-left-radius: 8px; + -webkit-border-bottom-right-radius: 8px; + -webkit-box-shadow: 5px 5px 5px rgba(0, 0, 0, 0.15); + background-image: -webkit-gradient(linear,center top,center bottom,from(#FFFFFF), color-stop(0.6,#FFFFFF), color-stop(0.60,#FFFFFF), color-stop(0.95,#F7F8FB), to(#EEF1F7)); +} + +.paramkey { + text-align: right; +} + +.paramtype { + white-space: nowrap; +} + +.paramname { + color: #602020; + white-space: nowrap; +} +.paramname em { + font-style: normal; +} + +.params, .retval, .exception, .tparams { + border-spacing: 6px 2px; +} + +.params .paramname, .retval .paramname { + font-weight: bold; + vertical-align: top; +} + +.params .paramtype { + font-style: italic; + vertical-align: top; +} + +.params .paramdir { + font-family: "courier new",courier,monospace; + vertical-align: top; +} + + + + +/* @end */ + +/* @group Directory (tree) */ + +/* for the tree view */ + +.ftvtree { + font-family: sans-serif; + margin: 0px; +} + +/* these are for tree view when used as main index */ + +.directory { + font-size: 9pt; + font-weight: bold; + margin: 5px; +} + +.directory h3 { + margin: 0px; + margin-top: 1em; + font-size: 11pt; +} + +/* +The following two styles can be used to replace the root node title +with an image of your choice. Simply uncomment the next two styles, +specify the name of your image and be sure to set 'height' to the +proper pixel height of your image. +*/ + +/* +.directory h3.swap { + height: 61px; + background-repeat: no-repeat; + background-image: url("yourimage.gif"); +} +.directory h3.swap span { + display: none; +} +*/ + +.directory > h3 { + margin-top: 0; +} + +.directory p { + margin: 0px; + white-space: nowrap; +} + +.directory div { + display: none; + margin: 0px; +} + +.directory img { + vertical-align: -30%; +} + +/* these are for tree view when not used as main index */ + +.directory-alt { + font-size: 100%; + font-weight: bold; +} + +.directory-alt h3 { + margin: 0px; + margin-top: 1em; + font-size: 11pt; +} + +.directory-alt > h3 { + margin-top: 0; +} + +.directory-alt p { + margin: 0px; + white-space: nowrap; +} + +.directory-alt div { + display: none; + margin: 0px; +} + +.directory-alt img { + vertical-align: -30%; +} + +/* @end */ + +div.dynheader { + margin-top: 8px; +} + +address { + font-style: normal; + color: #2A3D61; +} + +table.doxtable { + border-collapse:collapse; +} + +table.doxtable td, table.doxtable th { + border: 1px solid #2D4068; + padding: 3px 7px 2px; +} + +table.doxtable th { + background-color: #374F7F; + color: #FFFFFF; + font-size: 110%; + padding-bottom: 4px; + padding-top: 5px; + text-align:left; +} + +.tabsearch { + top: 0px; + left: 10px; + height: 36px; + background-image: url('tab_b.png'); + z-index: 101; + overflow: hidden; + font-size: 13px; +} + +.navpath ul +{ + font-size: 11px; + background-image:url('tab_b.png'); + background-repeat:repeat-x; + height:30px; + line-height:30px; + color:#8AA0CC; + border:solid 1px #C2CDE4; + overflow:hidden; + margin:0px; + padding:0px; +} + +.navpath li +{ + list-style-type:none; + float:left; + padding-left:10px; + padding-right:15px; + background-image:url('bc_s.png'); + background-repeat:no-repeat; + background-position:right; + color:#364D7C; +} + +.navpath li.navelem a +{ + height:32px; + display:block; + text-decoration: none; + outline: none; +} + +.navpath li.navelem a:hover +{ + color:#6884BD; +} + +.navpath li.footer +{ + list-style-type:none; + float:right; + padding-left:10px; + padding-right:15px; + background-image:none; + background-repeat:no-repeat; + background-position:right; + color:#364D7C; + font-size: 8pt; +} + + +div.summary +{ + float: right; + font-size: 8pt; + padding-right: 5px; + width: 50%; + text-align: right; +} + +div.summary a +{ + white-space: nowrap; +} + +div.ingroups +{ + font-size: 8pt; + padding-left: 5px; + width: 50%; + text-align: left; +} + +div.ingroups a +{ + white-space: nowrap; +} + +div.header +{ + background-image:url('nav_h.png'); + background-repeat:repeat-x; + background-color: #F9FAFC; + margin: 0px; + border-bottom: 1px solid #C4CFE5; +} + +div.headertitle +{ + padding: 5px 5px 5px 10px; +} + +dl +{ + padding: 0 0 0 10px; +} + +dl.note, dl.warning, dl.attention, dl.pre, dl.post, dl.invariant, dl.deprecated, dl.todo, dl.test, dl.bug +{ + border-left:4px solid; + padding: 0 0 0 6px; +} + +dl.note +{ + border-color: #D0C000; +} + +dl.warning, dl.attention +{ + border-color: #FF0000; +} + +dl.pre, dl.post, dl.invariant +{ + border-color: #00D000; +} + +dl.deprecated +{ + border-color: #505050; +} + +dl.todo +{ + border-color: #00C0E0; +} + +dl.test +{ + border-color: #3030E0; +} + +dl.bug +{ + border-color: #C08050; +} + +#projectlogo +{ + text-align: center; + vertical-align: bottom; + border-collapse: separate; +} + +#projectlogo img +{ + border: 0px none; +} + +#projectname +{ + font: 200% Tahoma, Arial,sans-serif; + margin: 0px; + padding: 2px 0px; +} + +#projectbrief +{ + font: 120% Tahoma, Arial,sans-serif; + margin: 0px; + padding: 0px; +} + +#projectnumber +{ + font: 50% Tahoma, Arial,sans-serif; + margin: 0px; + padding: 0px; +} + +#titlearea +{ + padding: 0px; + margin: 0px; + width: 100%; + border-bottom: 1px solid #5373B4; +} + +.image +{ + text-align: center; +} + +.dotgraph +{ + text-align: center; +} + +.mscgraph +{ + text-align: center; +} + +.caption +{ + font-weight: bold; +} + diff --git a/Libraries/CMSIS/Documentation/Core/html/device_h_pg.html b/Libraries/CMSIS/Documentation/Core/html/device_h_pg.html new file mode 100644 index 0000000..463bf6b --- /dev/null +++ b/Libraries/CMSIS/Documentation/Core/html/device_h_pg.html @@ -0,0 +1,516 @@ + + + + +Device Header File <device.h> + + + + + + + + + + + + + +
    + +
    + + + + + + + + + + + +
    +
    CMSIS-CORE +  Version 3.01 +
    +
    CMSIS-CORE support for Cortex-M processor-based devices
    +
    +
    + +
    + +
    + + + +
    +
    + +
    +
    +
    + +
    +
    +
    +
    Device Header File <device.h>
    +
    +
    +

    The Device Header File <device.h> contains the following sections that are device specific:

    +
      +
    • Interrupt Number Definition provides interrupt numbers (IRQn) for all exceptions and interrupts of the device.
      • +
    • Configuration of the Processor and Core Peripherals reflect the features of the device.
      • +
    • Device Peripheral Access Layer provides definitions for the Peripheral Access to all device peripherals. It contains all data structures and the address mapping for device-specific peripherals.
      • +
    • Access Functions for Peripherals (optional) provide additional helper functions for peripherals that are useful for programming of these peripherals. Access Functions may be provided as inline functions or can be extern references to a device-specific library provided by the silicon vendor.
      • +
    +

    Reference describes the standard features and functions of the Device Header File <device.h> in detail.

    +

    +Interrupt Number Definition

    +

    Device Header File <device.h> contains the enumeration IRQn_Type that defines all exceptions and interrupts of the device.

    +
      +
    • Negative IRQn values represent processor core exceptions (internal interrupts).
      • +
    • Positive IRQn values represent device-specific exceptions (external interrupts). The first device-specific interrupt has the IRQn value 0. The IRQn values needs extension to reflect the device-specific interrupt vector table in the Startup File startup_<device>.s.
      • +
    +

    Example:

    +

    The following example shows the extension of the interrupt vector table for the LPC1100 device family.

    +
    typedef enum IRQn
+{
+/******  Cortex-M0 Processor Exceptions Numbers ***************************************************/
+  NonMaskableInt_IRQn           = -14,      
+  HardFault_IRQn                = -13,      
+  SVCall_IRQn                   = -5,       
+  PendSV_IRQn                   = -2,       
+  SysTick_IRQn                  = -1,       
+/******  LPC11xx/LPC11Cxx Specific Interrupt Numbers **********************************************/
+  WAKEUP0_IRQn                  = 0,        
+  WAKEUP1_IRQn                  = 1,        
+  WAKEUP2_IRQn                  = 2,
+                 :       :
+                 :       :
+  EINT1_IRQn                    = 30,       
+  EINT0_IRQn                    = 31,       
+} IRQn_Type;
+

    +Configuration of the Processor and Core Peripherals

    +

    The Device Header File <device.h> configures the Cortex-M or SecurCore processor and the core peripherals with #defines that are set prior to including the file core_<cpu>.h.

    +

    The following tables list the #defines along with the possible values for each processor core. If these #defines are missing default values are used.

    +

    core_cm0.h

    + + + + + + + + + +
    #define Value Range Default Description
    __CM0_REV 0x0000 0x0000 Core revision number ([15:8] revision number, [7:0] patch number)
    __NVIC_PRIO_BITS 2 2 Number of priority bits implemented in the NVIC (device specific)
    __Vendor_SysTickConfig 0 .. 1 0 If this define is set to 1, then the default SysTick_Config function is excluded. In this case, the file device.h must contain a vendor specific implementation of this function.
    +

    core_cm0plus.h

    + + + + + + + + + +
    #define Value Range Default Description
    __CM0PLUS_REV 0x0000 0x0000 Core revision number ([15:8] revision number, [7:0] patch number)
    __NVIC_PRIO_BITS 2 2 Number of priority bits implemented in the NVIC (device specific)
    __Vendor_SysTickConfig 0 .. 1 0 If this define is set to 1, then the default SysTick_Config function is excluded. In this case, the file device.h must contain a vendor specific implementation of this function.
    +

    core_cm3.h

    + + + + + + + + + + + +
    #define Value Range Default Description
    __CM3_REV 0x0101 | 0x0200 0x0200 Core revision number ([15:8] revision number, [7:0] patch number)
    __NVIC_PRIO_BITS 2 .. 8 4 Number of priority bits implemented in the NVIC (device specific)
    __MPU_PRESENT 0 .. 1 0 Defines if a MPU is present or not
    __Vendor_SysTickConfig 0 .. 1 0 If this define is set to 1, then the default SysTick_Config function is excluded. In this case, the file device.h must contain a vendor specific implementation of this function.
    +

    core_cm4.h

    + + + + + + + + + + + + + +
    #define Value Range Default Description
    __CM4_REV 0x0000 0x0000 Core revision number ([15:8] revision number, [7:0] patch number)
    __NVIC_PRIO_BITS 2 .. 8 4 Number of priority bits implemented in the NVIC (device specific)
    __MPU_PRESENT 0 .. 1 0 Defines if a MPU is present or not
    __FPU_PRESENT 0 .. 1 0 Defines if a FPU is present or not
    __Vendor_SysTickConfig 0 .. 1 0 If this define is set to 1, then the default SysTick_Config function is excluded. In this case, the file device.h must contain a vendor specific implementation of this function.
    +

    core_sc000.h

    + + + + + + + + + + + +
    #define Value Range Default Description
    __SC000_REV 0x0000 0x0000 Core revision number ([15:8] revision number, [7:0] patch number)
    __NVIC_PRIO_BITS 2 2 Number of priority bits implemented in the NVIC (device specific)
    __MPU_PRESENT 0 .. 1 0 Defines if a MPU is present or not
    __Vendor_SysTickConfig 0 .. 1 0 If this define is set to 1, then the default SysTick_Config function is excluded. In this case, the file device.h must contain a vendor specific implementation of this function.
    +

    core_sc300.h

    + + + + + + + + + + + +
    #define Value Range Default Description
    __SC300_REV 0x0000 0x0000 Core revision number ([15:8] revision number, [7:0] patch number)
    __NVIC_PRIO_BITS 2 .. 8 4 Number of priority bits implemented in the NVIC (device specific)
    __MPU_PRESENT 0 .. 1 0 Defines if a MPU is present or not
    __Vendor_SysTickConfig 0 .. 1 0 If this define is set to 1, then the default SysTick_Config function is excluded. In this case, the file device.h must contain a vendor specific implementation of this function.
    +

    Example

    +

    The following code exemplifies the configuration of the Cortex-M4 Processor and Core Peripherals.

    +
    #define __CM4_REV                 0x0001    /* Core revision r0p1                                 */
+#define __MPU_PRESENT             1         /* MPU present or not                                 */
+#define __NVIC_PRIO_BITS          3         /* Number of Bits used for Priority Levels            */
+#define __Vendor_SysTickConfig    0         /* Set to 1 if different SysTick Config is used       */
+#define __FPU_PRESENT             1         /* FPU present or not                                 */
+.
+.
+#include <core_cm4.h>                       /* Cortex-M4 processor and core peripherals           */
+

    +CMSIS Version and Processor Information

    +

    Defines in the core_cpu.h file identify the version of the CMSIS-CORE and the processor used. The following shows the defines in the various core_cpu.h files that may be used in the Device Header File <device.h> to verify a minimum version or ensure that the right processor core is used.

    +

    core_cm0.h

    +
    #define __CM0_CMSIS_VERSION_MAIN    (0x03)                                   /* [31:16] CMSIS HAL main version   */
+#define __CM0_CMSIS_VERSION_SUB     (0x00)                                   /* [15:0]  CMSIS HAL sub version    */
+#define __CM0_CMSIS_VERSION         ((__CM0_CMSIS_VERSION_MAIN << 16) | \
+                                      __CM0_CMSIS_VERSION_SUB          )     /* CMSIS HAL version number         */
+...    
+#define __CORTEX_M                  (0x00)                                   /* Cortex-M Core                    */
+

    core_cm0plus.h

    +
    #define __CM0PLUS_CMSIS_VERSION_MAIN   (0x03)                                /* [31:16] CMSIS HAL main version   */
+#define __CM0PLUS_CMSIS_VERSION_SUB    (0x00)                                /* [15:0]  CMSIS HAL sub version    */
+#define __CM0PLUS_CMSIS_VERSION        ((__CM0P_CMSIS_VERSION_MAIN << 16) | \
+                                     __CM0P_CMSIS_VERSION_SUB          )  /* CMSIS HAL version number         */
+...    
+#define __CORTEX_M                  (0x00)                                /* Cortex-M Core                    */
+

    core_cm3.h

    +
    #define __CM3_CMSIS_VERSION_MAIN    (0x03)                                   /* [31:16] CMSIS HAL main version   */
+#define __CM3_CMSIS_VERSION_SUB     (0x00)                                   /* [15:0]  CMSIS HAL sub version    */
+#define __CM3_CMSIS_VERSION         ((__CM3_CMSIS_VERSION_MAIN << 16) | \
+                                      __CM3_CMSIS_VERSION_SUB          )     /* CMSIS HAL version number         */
+...    
+#define __CORTEX_M                  (0x03)                                   /* Cortex-M Core                    */
+

    core_cm4.h

    +
    #define __CM4_CMSIS_VERSION_MAIN    (0x03)                                   /* [31:16] CMSIS HAL main version   */
+#define __CM4_CMSIS_VERSION_SUB     (0x00)                                   /* [15:0]  CMSIS HAL sub version    */
+#define __CM4_CMSIS_VERSION         ((__CM4_CMSIS_VERSION_MAIN << 16) | \
+                                      __CM4_CMSIS_VERSION_SUB          )     /* CMSIS HAL version number         */
+...    
+#define __CORTEX_M                  (0x04)                                   /* Cortex-M Core                    */
+

    core_sc000.h

    +
    #define __SC000_CMSIS_VERSION_MAIN  (0x03)                                   /* [31:16] CMSIS HAL main version */
+#define __SC000_CMSIS_VERSION_SUB   (0x00)                                   /* [15:0]  CMSIS HAL sub version  */
+#define __SC000_CMSIS_VERSION       ((__SC000_CMSIS_VERSION_MAIN << 16) | \
+                                      __SC000_CMSIS_VERSION_SUB          )   /* CMSIS HAL version number       */
+...    
+#define __CORTEX_SC                 (0)                                      /* Cortex secure core             */
+

    core_sc300.h

    +
    #define __SC300_CMSIS_VERSION_MAIN  (0x03)                                   /* [31:16] CMSIS HAL main version */
+#define __SC300_CMSIS_VERSION_SUB   (0x00)                                   /* [15:0]  CMSIS HAL sub version  */
+#define __SC300_CMSIS_VERSION       ((__SC300_CMSIS_VERSION_MAIN << 16) | \
+                                      __SC300_CMSIS_VERSION_SUB          )   /* CMSIS HAL version number       */
+...    
+#define __CORTEX_SC                 (300)                                    /* Cortex secure core             */
+

    +Device Peripheral Access Layer

    +

    The Device Header File <device.h> contains for each peripheral:

    +
      +
    • Register Layout Typedef
      • +
    • Base Address
      • +
    • Access Definitions
      • +
    +

    The section Peripheral Access shows examples for peripheral definitions.

    +

    +Device.h Template File

    +

    The silicon vendor needs to extend the Device.h template file with the CMSIS features described above. In addition the Device Header File <device.h> may contain functions to access device-specific peripherals. The system_Device.h Template File which is provided as part of the CMSIS specification is shown below.

    +
    /**************************************************************************//**
+ * @file     <Device>.h
+ * @brief    CMSIS Cortex-M# Core Peripheral Access Layer Header File for
+ *           Device <Device>
+ * @version  V3.01
+ * @date     06. March 2012
+ *
+ * @note
+ * Copyright (C) 2010-2012 ARM Limited. All rights reserved.
+ *
+ * @par
+ * ARM Limited (ARM) is supplying this software for use with Cortex-M 
+ * processor based microcontrollers.  This file can be freely distributed 
+ * within development tools that are supporting such ARM based processors. 
+ *
+ * @par
+ * THIS SOFTWARE IS PROVIDED "AS IS".  NO WARRANTIES, WHETHER EXPRESS, IMPLIED
+ * OR STATUTORY, INCLUDING, BUT NOT LIMITED TO, IMPLIED WARRANTIES OF
+ * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE APPLY TO THIS SOFTWARE.
+ * ARM SHALL NOT, IN ANY CIRCUMSTANCES, BE LIABLE FOR SPECIAL, INCIDENTAL, OR
+ * CONSEQUENTIAL DAMAGES, FOR ANY REASON WHATSOEVER.
+ *
+ ******************************************************************************/
+
+
+#ifndef <Device>_H      /* ToDo: replace '<Device>' with your device name */
+#define <Device>_H
+
+#ifdef __cplusplus
+ extern "C" {
+#endif 
+
+/* ToDo: replace '<Device>' with your device name; add your doxyGen comment   */
+/** @addtogroup <Device>_Definitions <Device> Definitions
+  This file defines all structures and symbols for <Device>:
+    - registers and bitfields
+    - peripheral base address
+    - peripheral ID
+    - Peripheral definitions
+  @{
+*/
+
+
+/******************************************************************************/
+/*                Processor and Core Peripherals                              */
+/******************************************************************************/
+/** @addtogroup <Device>_CMSIS Device CMSIS Definitions
+  Configuration of the Cortex-M# Processor and Core Peripherals
+  @{
+*/
+
+/*
+ * ==========================================================================
+ * ---------- Interrupt Number Definition -----------------------------------
+ * ==========================================================================
+ */
+
+typedef enum IRQn
+{
+/******  Cortex-M# Processor Exceptions Numbers ***************************************************/
+
+/* ToDo: use this Cortex interrupt numbers if your device is a CORTEX-M0 device                   */
+  NonMaskableInt_IRQn           = -14,      /*!<  2 Non Maskable Interrupt                        */
+  HardFault_IRQn                = -13,      /*!<  3 Hard Fault Interrupt                          */
+  SVCall_IRQn                   = -5,       /*!< 11 SV Call Interrupt                             */
+  PendSV_IRQn                   = -2,       /*!< 14 Pend SV Interrupt                             */
+  SysTick_IRQn                  = -1,       /*!< 15 System Tick Interrupt                         */
+
+/* ToDo: use this Cortex interrupt numbers if your device is a CORTEX-M3 / Cortex-M4 device       */
+  NonMaskableInt_IRQn           = -14,      /*!<  2 Non Maskable Interrupt                        */
+  MemoryManagement_IRQn         = -12,      /*!<  4 Memory Management Interrupt                   */
+  BusFault_IRQn                 = -11,      /*!<  5 Bus Fault Interrupt                           */
+  UsageFault_IRQn               = -10,      /*!<  6 Usage Fault Interrupt                         */
+  SVCall_IRQn                   = -5,       /*!< 11 SV Call Interrupt                             */
+  DebugMonitor_IRQn             = -4,       /*!< 12 Debug Monitor Interrupt                       */
+  PendSV_IRQn                   = -2,       /*!< 14 Pend SV Interrupt                             */
+  SysTick_IRQn                  = -1,       /*!< 15 System Tick Interrupt                         */
+
+/******  Device Specific Interrupt Numbers ********************************************************/
+/* ToDo: add here your device specific external interrupt numbers
+         according the interrupt handlers defined in startup_Device.s
+         eg.: Interrupt for Timer#1       TIM1_IRQHandler   ->   TIM1_IRQn                        */
+  <DeviceInterrupt>_IRQn        = 0,        /*!< Device Interrupt                                 */
+} IRQn_Type;
+
+
+/*
+ * ==========================================================================
+ * ----------- Processor and Core Peripheral Section ------------------------
+ * ==========================================================================
+ */
+
+/* Configuration of the Cortex-M# Processor and Core Peripherals */
+/* ToDo: set the defines according your Device                                                    */
+/* ToDo: define the correct core revision
+         __CM0_REV if your device is a CORTEX-M0 device
+         __CM3_REV if your device is a CORTEX-M3 device
+         __CM4_REV if your device is a CORTEX-M4 device                                           */
+#define __CM#_REV                 0x0201    /*!< Core Revision r2p1                               */
+#define __NVIC_PRIO_BITS          2         /*!< Number of Bits used for Priority Levels          */
+#define __Vendor_SysTickConfig    0         /*!< Set to 1 if different SysTick Config is used     */
+#define __MPU_PRESENT             0         /*!< MPU present or not                               */
+/* ToDo: define __FPU_PRESENT if your devise is a CORTEX-M4                                       */
+#define __FPU_PRESENT             0        /*!< FPU present or not                                */
+
+/*@}*/ /* end of group <Device>_CMSIS */
+
+
+/* ToDo: include the correct core_cm#.h file
+         core_cm0.h if your device is a CORTEX-M0 device
+         core_cm3.h if your device is a CORTEX-M3 device
+         core_cm4.h if your device is a CORTEX-M4 device                                          */
+#include <core_cm#.h>                       /* Cortex-M# processor and core peripherals           */
+/* ToDo: include your system_<Device>.h file
+         replace '<Device>' with your device name                                                 */
+#include "system_<Device>.h"                /* <Device> System  include file                      */
+
+
+/******************************************************************************/
+/*                Device Specific Peripheral registers structures             */
+/******************************************************************************/
+/** @addtogroup <Device>_Peripherals <Device> Peripherals
+  <Device> Device Specific Peripheral registers structures
+  @{
+*/
+
+#if defined ( __CC_ARM   )
+#pragma anon_unions
+#endif
+
+/* ToDo: add here your device specific peripheral access structure typedefs
+         following is an example for a timer                                  */
+
+/*------------- 16-bit Timer/Event Counter (TMR) -----------------------------*/
+/** @addtogroup <Device>_TMR <Device> 16-bit Timer/Event Counter (TMR)
+  @{
+*/
+typedef struct
+{
+  __IO uint32_t EN;                         /*!< Offset: 0x0000   Timer Enable Register           */               
+  __IO uint32_t RUN;                        /*!< Offset: 0x0004   Timer RUN Register              */
+  __IO uint32_t CR;                         /*!< Offset: 0x0008   Timer Control Register          */
+  __IO uint32_t MOD;                        /*!< Offset: 0x000C   Timer Mode Register             */
+       uint32_t RESERVED0[1];
+  __IO uint32_t ST;                         /*!< Offset: 0x0014   Timer Status Register           */
+  __IO uint32_t IM;                         /*!< Offset: 0x0018   Interrupt Mask Register         */
+  __IO uint32_t UC;                         /*!< Offset: 0x001C   Timer Up Counter Register       */
+  __IO uint32_t RG0                         /*!< Offset: 0x0020   Timer Register                  */
+       uint32_t RESERVED1[2];
+  __IO uint32_t CP;                         /*!< Offset: 0x002C   Capture register                */
+} <DeviceAbbreviation>_TMR_TypeDef;
+/*@}*/ /* end of group <Device>_TMR */
+
+
+#if defined ( __CC_ARM   )
+#pragma no_anon_unions
+#endif
+
+/*@}*/ /* end of group <Device>_Peripherals */
+
+
+/******************************************************************************/
+/*                         Peripheral memory map                              */
+/******************************************************************************/
+/* ToDo: add here your device peripherals base addresses                
+         following is an example for timer                                    */
+/** @addtogroup <Device>_MemoryMap <Device> Memory Mapping
+  @{
+*/
+
+/* Peripheral and SRAM base address */
+#define <DeviceAbbreviation>_FLASH_BASE       (0x00000000UL)                              /*!< (FLASH     ) Base Address */
+#define <DeviceAbbreviation>_SRAM_BASE        (0x20000000UL)                              /*!< (SRAM      ) Base Address */
+#define <DeviceAbbreviation>_PERIPH_BASE      (0x40000000UL)                              /*!< (Peripheral) Base Address */
+
+/* Peripheral memory map */
+#define <DeviceAbbreviation>TIM0_BASE         (<DeviceAbbreviation>_PERIPH_BASE)          /*!< (Timer0    ) Base Address */
+#define <DeviceAbbreviation>TIM1_BASE         (<DeviceAbbreviation>_PERIPH_BASE + 0x0800) /*!< (Timer1    ) Base Address */
+#define <DeviceAbbreviation>TIM2_BASE         (<DeviceAbbreviation>_PERIPH_BASE + 0x1000) /*!< (Timer2    ) Base Address */
+/*@}*/ /* end of group <Device>_MemoryMap */
+
+
+/******************************************************************************/
+/*                         Peripheral declaration                             */
+/******************************************************************************/
+/* ToDo: add here your device peripherals pointer definitions                
+         following is an example for timer                                    */
+
+/** @addtogroup <Device>_PeripheralDecl <Device> Peripheral Declaration
+  @{
+*/
+
+#define <DeviceAbbreviation>_TIM0        ((<DeviceAbbreviation>_TMR_TypeDef *) <DeviceAbbreviation>TIM0_BASE)
+#define <DeviceAbbreviation>_TIM1        ((<DeviceAbbreviation>_TMR_TypeDef *) <DeviceAbbreviation>TIM0_BASE)
+#define <DeviceAbbreviation>_TIM2        ((<DeviceAbbreviation>_TMR_TypeDef *) <DeviceAbbreviation>TIM0_BASE)
+/*@}*/ /* end of group <Device>_PeripheralDecl */
+
+/*@}*/ /* end of group <Device>_Definitions */
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif  /* <Device>_H */
+
    +
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    Core Register Access
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    +Functions

    uint32_t __get_CONTROL (void)
     Read the CONTROL register.
    void __set_CONTROL (uint32_t control)
     Set the CONTROL Register.
    uint32_t __get_IPSR (void)
     Read the IPSR register.
    uint32_t __get_APSR (void)
     Read the APSR register.
    uint32_t __get_xPSR (void)
     Read the xPSR register.
    uint32_t __get_PSP (void)
     Read the PSP register.
    void __set_PSP (uint32_t topOfProcStack)
     Set the PSP register.
    uint32_t __get_MSP (void)
     Read the MSP register.
    void __set_MSP (uint32_t topOfMainStack)
     Set the MSP register.
    uint32_t __get_PRIMASK (void)
     Read the PRIMASK register bit.
    void __set_PRIMASK (uint32_t priMask)
     Set the Priority Mask bit.
    uint32_t __get_BASEPRI (void)
     Read the BASEPRI register [not for Cortex-M0 variants].
    void __set_BASEPRI (uint32_t basePri)
     Set the BASEPRI register [not for Cortex-M0 variants].
    uint32_t __get_FAULTMASK (void)
     Read the FAULTMASK register [not for Cortex-M0 variants].
    void __set_FAULTMASK (uint32_t faultMask)
     Set the FAULTMASK register [not for Cortex-M0 variants].
    uint32_t __get_FPSCR (void)
     Read the FPSCR register [only for Cortex-M4].
    void __set_FPSCR (uint32_t fpscr)
     Set the FPSC register [only for Cortex-M4].
    void __enable_irq (void)
     Globally enables interrupts and configurable fault handlers.
    void __disable_irq (void)
     Globally disables interrupts and configurable fault handlers.
    void __enable_fault_irq (void)
     Enables interrupts and all fault handlers [not for Cortex-M0 variants].
    void __disable_fault_irq (void)
     Disables interrupts and all fault handlers [not for Cortex-M0 variants].
    +

    Description

    +

    The following functions provide access to Cortex-M core registers.

    +

    Function Documentation

    + +
    +
    + + + + + + + + +
    void __disable_fault_irq (void )
    +
    +
    +

    The function disables interrupts and all fault handlers by setting the F-bit in the CPSR. The function uses the instruction CPSID f.

    +
    Remarks:
      +
    • not for Cortex-M0 variants.
      • +
    • Can be executed in privileged mode only.
      • +
    • An interrupt can enter pending state even if it is disabled. Disabling an interrupt only prevents the processor from taking that interrupt.
      • +
    +
    +
    See also:
    +
    + +
    +
    + +
    +
    + + + + + + + + +
    void __disable_irq (void )
    +
    +
    +

    The function disables interrupts and all configurable fault handlers by setting the I-bit in the CPSR. The function uses the instruction CPSID i.

    +
    Remarks:
      +
    • Can be executed in privileged mode only.
      • +
    • Basically, it sets PRIMASK.
      • +
    • An interrupt can enter pending state even if it is disabled. Disabling an interrupt only prevents the processor from taking that interrupt.
      • +
    +
    +
    See also:
    +
    + +
    +
    + +
    +
    + + + + + + + + +
    void __enable_fault_irq (void )
    +
    +
    +

    The function enables interrupts and all fault handlers by clearing the F-bit in the CPSR. The function uses the instruction CPSIE f.

    +
    Remarks:
      +
    • not for Cortex-M0 variants.
      • +
    • Can be executed in privileged mode only.
      • +
    +
    +
    See also:
    +
    + +
    +
    + +
    +
    + + + + + + + + +
    void __enable_irq (void )
    +
    +
    +

    The function enables interrupts and all configurable fault handlers by clearing the I-bit in the CPSR. The function uses the instruction CPSIE i.

    +
    Remarks:
      +
    • Can be executed in privileged mode only.
      • +
    • Basically, it clears PRIMASK.
      • +
    +
    +
    See also:
    +
    + +
    +
    + +
    +
    + + + + + + + + +
    uint32_t __get_APSR (void )
    +
    +
    +

    The function reads the Application Program Status Register (APSR) using the instruction MRS.
    +
    + The APSR contains the current state of the condition flags from instructions executed previously. The APSR is essential for controlling conditional branches. The following flags are used:

    +
      +
    • N (APSR[31]) (Negative flag)
        +
      • =1 The instruction result has a negative value (when interpreted as signed integer).
        • +
      • =0 The instruction result has a positive value or equal zero.
        +
        +
        • +
      +
      • +
    • Z (APSR[30]) (Zero flag)
        +
      • =1 The instruction result is zero. Or, after a compare instruction, when the two values are the same.
        +
        +
        • +
      +
      • +
    • C (APSR[29]) (Carry or borrow flag)
        +
      • =1 For unsigned additions, if an unsigned overflow occurred.
        • +
      • =inverse of borrow output status For unsigned subtract operations.
        +
        +
        • +
      +
      • +
    • V (APSR[28]) (Overflow flag)
        +
      • =1 A signed overflow occurred (for signed additions or subtractions).
        +
        +
        • +
      +
      • +
    • Q (APSR[27]) (DSP overflow or saturation flag) [not Cortex-M0]
        +
      • This flag is a sticky flag. Saturating and certain mutliplying instructions can set the flag, but cannot clear it.
        • +
      • =1 When saturation or an overflow occurred.
        +
        +
        • +
      +
      • +
    • GE (APSR[19:16]) (Greater than or Equal flags) [not Cortex-M0]
        +
      • Can be set by the parallel add and subtract instructions.
        • +
      • Are used by the SEL instruction to perform byte-based selection from two registers.
        • +
      +
      • +
    +
    Returns:
    APSR register value
    +
    Remarks:
      +
    • Some instructions update all flags; some instructions update a subset of the flags.
      • +
    • If a flag is not updated, the original value is preserved.
      • +
    • Conditional instructions that are not executed have no effect on the flags.
      • +
    • The CMSIS does not provide a function to update this register.
      • +
    +
    +
    See also:
    +
    + +
    +
    + +
    +
    + + + + + + + + +
    uint32_t __get_BASEPRI (void )
    +
    +
    +

    The function returns the Base Priority Mask register (BASEPRI) using the instruction MRS.
    +
    + BASEPRI defines the minimum priority for exception processing. When BASEPRI is set to a non-zero value, it prevents the activation of all exceptions with the same or lower priority level as the BASEPRI value.

    +
    Returns:
    BASEPRI register value
    +
    Remarks:
      +
    • not for Cortex-M0 variants.
      • +
    +
    +
    See also:
    +
    + +
    +
    + +
    +
    + + + + + + + + +
    uint32_t __get_CONTROL (void )
    +
    +
    +

    The function reads the CONTROL register value using the instruction MRS.
    +
    + The CONTROL register controls the stack used and the privilege level for software execution when the processor is in thread mode and, if implemented, indicates whether the FPU state is active. This register uses the following bits:
    +

    +
      +
    • CONTROL[2] [only Cortex-M4]
        +
      • =0 FPU not active
        • +
      • =1 FPU active
        +
        +
        • +
      +
      • +
    • CONTROL[1]
        +
      • =0 In handler mode - MSP is selected. No alternate stack possible for handler mode.
        • +
      • =0 In thread mode - Default stack pointer MSP is used.
        • +
      • =1 In thread mode - Alternate stack pointer PSP is used.
        +
        +
        • +
      +
      • +
    • CONTROL[0] [not Cortex-M0]
        +
      • =0 In thread mode and privileged state.
        • +
      • =1 In thread mode and user state.
        • +
      +
      • +
    +
    Returns:
    CONTROL register value
    +
    Remarks:
      +
    • The processor can be in user state or privileged state when running in thread mode.
      • +
    • Exception handlers always run in privileged state.
      • +
    • On reset, the processor is in thread mode with privileged access rights.
      • +
    +
    +
    See also:
    +
    + +
    +
    + +
    +
    + + + + + + + + +
    uint32_t __get_FAULTMASK (void )
    +
    +
    +

    The function reads the Fault Mask register (FAULTMASK) value using the instruction MRS.
    +
    + FAULTMASK prevents activation of all exceptions except for the Non-Maskable Interrupt (NMI).

    +
    Returns:
    FAULTMASK register value
    +
    Remarks:
      +
    • not for Cortex-M0 variants.
      • +
    • Is cleared automatically upon exiting the exception handler, except when returning from the NMI handler.
      • +
    +
    +
    See also:
    +
    + +
    +
    + +
    +
    + + + + + + + + +
    uint32_t __get_FPSCR (void )
    +
    +
    +

    The function reads the Floating-Point Status Control Register (FPSCR) value.
    +
    + FPSCR provides all necessary User level controls of the floating-point system.

    +
    Returns:
      +
    • FPSCR register value, when __FPU_PRESENT=1
      • +
    • =0, when __FPU_PRESENT=0
      • +
    +
    +
    Remarks:
      +
    • Only for Cortex-M4.
      • +
    +
    +
    See also:
    +
    + +
    +
    + +
    +
    + + + + + + + + +
    uint32_t __get_IPSR (void )
    +
    +
    +

    The function reads the Interrupt Program Status Register (IPSR) using the instruction MRS.
    +
    + The ISPR contains the exception type number of the current Interrupt Service Routine (ISR). Each exception has an assocciated unique IRQn number. The following bits are used:

    +
      +
    • ISR_NUMBER (IPSR[8:0])
        +
      • =0 Thread mode
        • +
      • =1 Reserved
        • +
      • =2 NMI
        • +
      • =3 HardFault
        • +
      • =4 MemManage
        • +
      • =5 BusFault
        • +
      • =6 UsageFault
        • +
      • =7-10 Reserved
        • +
      • =11 SVCall
        • +
      • =12 Reserved for Debug
        • +
      • =13 Reserved
        • +
      • =14 PendSV
        • +
      • =15 SysTick
        • +
      • =16 IRQ0
        • +
      • ...
        • +
      • =n+15 IRQ(n-1)
        • +
      +
      • +
    +
    Returns:
    ISPR register value
    +
    Remarks:
      +
    • This register is read-only.
      • +
    +
    +
    See also:
    +
    + +
    +
    + +
    +
    + + + + + + + + +
    uint32_t __get_MSP (void )
    +
    +
    +

    The function reads the Main Status Pointer (MSP) value using the instruction MRS.
    +
    + Physically two different stack pointers (SP) exist:

    +
      +
    • The Main Stack Pointer (MSP) is the default stack pointer after reset. It is also used when running exception handlers (handler mode).
      • +
    • The Process Stack Pointer (PSP), which can be used only in thread mode.
      • +
    +

    Register R13 banks the SP. The SP selection is determined by the bit[1] of the CONTROL register:

    +
      +
    • =0 MSP is the current stack pointer. This is also the default SP. The initial value is loaded from the first 32-bit word of the vector table from the program memory.
      • +
    • =1 PSP is the current stack pointer. The initial value is undefined.
      • +
    +
    Returns:
    MSP Register value
    +
    Remarks:
      +
    • Only one of the two SPs is visible at a time.
      • +
    • For many applications, the system can completely rely on the MSP.
      • +
    • The PSP is normally used in designs with an OS where the stack memory for OS Kernel must be separated from the application code.
      • +
    +
    +
    See also:
    +
    + +
    +
    + +
    +
    + + + + + + + + +
    uint32_t __get_PRIMASK (void )
    +
    +
    +

    The function reads the Priority Mask register (PRIMASK) value using the instruction MRS.
    +
    + PRIMASK is a 1-bit-wide interrupt mask register. When set, it blocks all interrupts apart from the non-maskable interrupt (NMI) and the hard fault exception. The PRIMASK prevents activation of all exceptions with configurable priority.

    +
    Returns:
    PRIMASK register value
      +
    • =0 no effect
      • +
    • =1 prevents the activation of all exceptions with configurable priority
      • +
    +
    +
    See also:
    +
    + +
    +
    + +
    +
    + + + + + + + + +
    uint32_t __get_PSP (void )
    +
    +
    +

    The function reads the Program Status Pointer (PSP) value using the instruction MRS.
    +
    + Physically two different stack pointers (SP) exist:

    +
      +
    • The Main Stack Pointer (MSP) is the default stack pointer after reset. It is also used when running exception handlers (handler mode).
      • +
    • The Process Stack Pointer (PSP), which can be used only in thread mode.
      • +
    +

    Register R13 banks the SP. The SP selection is determined by the bit[1] of the CONTROL register:

    +
      +
    • =0 MSP is the current stack pointer. This is also the default SP. The initial value is loaded from the first 32-bit word of the vector table from the program memory.
      • +
    • =1 PSP is the current stack pointer. The initial value is undefined.
      • +
    +
    Returns:
    PSP register value
    +
    Remarks:
      +
    • Only one of the two SPs is visible at a time.
      • +
    • For many applications, the system can completely rely on the MSP.
      • +
    • The PSP is normally used in designs with an OS where the stack memory for OS Kernel must be separated from the application code.
      • +
    +
    +
    See also:
    +
    + +
    +
    + +
    +
    + + + + + + + + +
    uint32_t __get_xPSR (void )
    +
    +
    +

    The function reads the combined Program Status Register (xPSR) using the instruction MRS.
    +
    + xPSR provides information about program execution and the APSR flags. It consists of the following PSRs:

    +
      +
    • Application Program Status Register (APSR)
      • +
    • Interrupt Program Status Register (IPSR)
      • +
    • Execution Program Status Register (EPSR)
      • +
    +

    In addition to the flags described in __get_APSR and __get_IPSR, the register provides the following flags:

    +
      +
    • IT (xPSR[26:25]) (If-Then condition instruction)
        +
      • Contains up to four instructions following an IT instruction.
        • +
      • Each instruction in the block is conditional.
        • +
      • The conditions for the instructions are either all the same, or some can be the inverse of others.
        +
        +
        • +
      +
      • +
    • T (xPSR[24]) (Thumb bit)
        +
      • =1 Indicates that that the processor is in Thumb state.
        • +
      • =0 Attempting to execute instructions when the T bit is 0 results in a fault or lockup.
        • +
      • The conditions for the instructions are either all the same, or some can be the inverse of others.
        • +
      +
      • +
    +
    Returns:
    xPSR register value
    +
    Remarks:
      +
    • The CMSIS does not provide functions that access EPSR.
      • +
    +
    +
    See also:
    +
    + +
    +
    + +
    +
    + + + + + + + + +
    void __set_BASEPRI (uint32_t basePri)
    +
    +
    +

    The function sets the Base Priority Mask register (BASEPRI) value using the instruction MSR.
    +
    + BASEPRI defines the minimum priority for exception processing. When BASEPRI is set to a non-zero value, it prevents the activation of all exceptions with the same or lower priority level as the BASEPRI value.

    +
    Parameters:
    + + +
    [in]basePriBASEPRI value to set
    +
    +
    +
    Remarks:
      +
    • not for Cortex-M0 variants.
      • +
    • Cannot be set in user state.
      • +
    • Useful for changing the masking level or disabling the masking.
      • +
    +
    +
    See also:
    +
    + +
    +
    + +
    +
    + + + + + + + + +
    void __set_CONTROL (uint32_t control)
    +
    +
    +

    The function sets the CONTROL register value using the instruction MSR.
    +
    + The CONTROL register controls the stack used and the privilege level for software execution when the processor is in thread mode and, if implemented, indicates whether the FPU state is active. This register uses the following bits:
    +

    +
      +
    • CONTROL[2] [only Cortex-M4]
        +
      • =0 FPU not active
        • +
      • =1 FPU active
        +
        +
        • +
      +
      • +
    • CONTROL[1]
        +
      • Writeable only when the processor is in thread mode and privileged state (CONTROL[0]=0).
        • +
      • =0 In handler mode - MSP is selected. No alternate stack pointer possible for handler mode.
        • +
      • =0 In thread mode - Default stack pointer MSP is used.
        • +
      • =1 In thread mode - Alternate stack pointer PSP is used.
        +
        +
        • +
      +
      • +
    • CONTROL[0] [not writeable for Cortex-M0]
        +
      • Writeable only when the processor is in privileged state.
        • +
      • Can be used to switch the processor to user state (thread mode).
        • +
      • Once in user state, trigger an interrupt and change the state to privileged in the exception handler (the only way).
        • +
      • =0 In thread mode and privileged state.
        • +
      • =1 In thread mode and user state.
        • +
      +
      • +
    +
    Parameters:
    + + +
    [in]controlCONTROL register value to set
    +
    +
    +
    Remarks:
      +
    • The processor can be in user state or privileged state when running in thread mode.
      • +
    • Exception handlers always run in privileged state.
      • +
    • On reset, the processor is in thread mode with privileged access rights.
      • +
    +
    +
    See also:
    +
    + +
    +
    + +
    +
    + + + + + + + + +
    void __set_FAULTMASK (uint32_t faultMask)
    +
    +
    +

    The function sets the Fault Mask register (FAULTMASK) value using the instruction MSR.
    +
    + FAULTMASK prevents activation of all exceptions except for Non-Maskable Interrupt (NMI). FAULTMASK can be used to escalate a configurable fault handler (BusFault, usage fault, or memory management fault) to hard fault level without invoking a hard fault. This allows the fault handler to pretend to be the hard fault handler, whith the ability to:

    +
      +
    1. Mask BusFault by setting the BFHFNMIGN in the Configuration Control register. It can be used to test the bus system without causing a lockup.
      2. +
    2. Bypass the MPU, allowing accessing the MPU protected memory location without reprogramming the MPU to just carry out a few transfers for fixing faults.
      3. +
    +
    Parameters:
    + + +
    [in]faultMaskFAULTMASK register value to set
    +
    +
    +
    Remarks:
      +
    • not for Cortex-M0 variants.
      • +
    • Is cleared automatically upon exiting the exception handler, except when returning from the NMI handler.
      • +
    • When set, it changes the effective current priority level to -1, so that even the hard fault handler is blocked.
      • +
    • Can be used by fault handlers to change their priority to -1 to have access to some features for hard fault exceptions (see above).
      • +
    • When set, lockups can still be caused by incorrect or undefined instructions, or by using SVC in the wrong priority level.
      • +
    +
    +
    See also:
    +
    + +
    +
    + +
    +
    + + + + + + + + +
    void __set_FPSCR (uint32_t fpscr)
    +
    +
    +

    The function sets the Floating-Point Status Control Register (FPSCR) value.
    +
    + FPSCR provides all necessary User level control of the floating-point system.
    +

    +
      +
    • N (FPSC[31]) (Negative flag)
        +
      • =1 The instruction result has a negative value (when interpreted as signed integer).
        • +
      • =0 The instruction result has a positive value or equal zero.
        +
        +
        • +
      +
      • +
    • Z (FPSC[30]) (Zero flag)
        +
      • =1 The instruction result is zero. Or, after a compare instruction, when the two values are the same.
        +
        +
        • +
      +
      • +
    • C (FPSC[29]) (Carry or borrow flag)
        +
      • =1 For unsigned additions, if an unsigned overflow occurred.
        • +
      • =inverse of borrow output status For unsigned subtract operations.
        +
        +
        • +
      +
      • +
    • V (FPSC[28]) (Overflow flag)
        +
      • =1 A signed overflow occurred (for signed additions or subtractions).
        +
        +
        • +
      +
      • +
    • AHP (FPSC[26]) (Alternative half-precision flag)
        +
      • =1 Alternative half-precision format selected.
        • +
      • =0 IEEE half-precision format selected.
        +
        +
        • +
      +
      • +
    • DN (FPSC[25]) (Default NaN mode control flag)
        +
      • =1 Any operation involving one or more NaNs returns the Default NaN.
        • +
      • =0 NaN operands propagate through to the output of a floating-point operation.
        +
        +
        • +
      +
      • +
    • FZ (FPSC[24]) (Flush-to-zero mode control flag)
        +
      • =1 Flush-to-zero mode enabled.
        • +
      • =0 Flush-to-zero mode disabled. Behavior of the floating-point system is fully compliant with the IEEE 754 standard.
        +
        +
        • +
      +
      • +
    • RMode (FPSC[23:22]) (Rounding Mode control flags)
        +
      • =0b00 Round to Nearest (RN) mode.
        • +
      • =0b01 Round towards Plus Infinity (RP) mode.
        • +
      • =0b10 Round towards Minus Infinity (RM) mode.
        • +
      • =0b11 Round towards Zero (RZ) mode.
        • +
      • The specified rounding mode is used by almost all floating-point instructions.
        +
        +
        • +
      +
      • +
    • IDC (FPSC[7]) (Input Denormal cumulative exception flags)
        +
      • See Cumulative exception bits (FPSC[4:0]).
        +
        +
        • +
      +
      • +
    • IXC (FPSC[4]) (Inexact cumulative exception flag)
        +
      • =1 Exception occurred.
        • +
      • =0 Value has to be set explicitly.
        • +
      • Flag is not cleared automatically.
        +
        +
        • +
      +
      • +
    • UFC (FPSC[3]) (Underflow cumulative exception flag)
        +
      • =1 Exception occurred.
        • +
      • =0 Value has to be set explicitly.
        • +
      • Flag is not cleared automatically.
        +
        +
        • +
      +
      • +
    • OFC (FPSC[2]) (Overflow cumulative exception flag)
        +
      • =1 Exception occurred.
        • +
      • =0 Value has to be set explicitly.
        • +
      • Flag is not cleared automatically.
        +
        +
        • +
      +
      • +
    • DZC (FPSC[1]) (Division by Zero cumulative exception flag)
        +
      • =1 Exception occurred.
        • +
      • =0 Value has to be set explicitly.
        • +
      • Flag is not cleared automatically.
        +
        +
        • +
      +
      • +
    • IOC (FPSC[0]) (Invalid Operation cumulative exception flag)
        +
      • =1 Exception occurred.
        • +
      • =0 Value has to be set explicitly.
        • +
      • Flag is not cleared automatically.
        • +
      +
      • +
    +
    Parameters:
    + + +
    [in]fpscrFPSCR value to set
    +
    +
    +
    Remarks:
      +
    • Only for Cortex-M4.
      • +
    • The variable __FPU_PRESENT has to be set to 1.
      • +
    +
    +
    See also:
    +
    + +
    +
    + +
    +
    + + + + + + + + +
    void __set_MSP (uint32_t topOfMainStack)
    +
    +
    +

    The function sets the Main Status Pointer (MSP) value using the instruction MSR.
    +
    + Physically two different stack pointers (SP) exist:

    +
      +
    • The Main Stack Pointer (MSP) is the default stack pointer after reset. It is also used when running exception handlers (handler mode).
      • +
    • The Process Stack Pointer (PSP), which can be used only in thread mode.
      • +
    +

    Register R13 banks the SP. The SP selection is determined by the bit[1] of the CONTROL register:

    +
      +
    • =0 MSP is the current stack pointer. This is also the default SP. The initial value is loaded from the first 32-bit word of the vector table from the program memory.
      • +
    • =1 PSP is the current stack pointer. The initial value is undefined.
      • +
    +
    Parameters:
    + + +
    [in]topOfMainStackMSP value to set
    +
    +
    +
    Remarks:
      +
    • Only one of the two SPs is visible at a time.
      • +
    • For many applications, the system can completely rely on the MSP.
      • +
    • The PSP is normally used in designs with an OS where the stack memory for OS Kernel must be separated from the application code.
      • +
    +
    +
    See also:
    +
    + +
    +
    + +
    +
    + + + + + + + + +
    void __set_PRIMASK (uint32_t priMask)
    +
    +
    +

    The function sets the Priority Mask register (PRIMASK) value using the instruction MSR.
    +
    + PRIMASK is a 1-bit-wide interrupt mask register. When set, it blocks all interrupts apart from the non-maskable interrupt (NMI) and the hard fault exception. The PRIMASK prevents activation of all exceptions with configurable priority.

    +
    Parameters:
    + + +
    [in]priMaskPriority Mask
      +
    • =0 no effect
      • +
    • =1 prevents the activation of all exceptions with configurable priority
      • +
    +
    +
    +
    +
    Remarks:
      +
    • When set, PRIMASK effectively changes the current priority level to 0. This is the highest programmable level.
      • +
    • When set and a fault occurs, the hard fault handler will be executed.
      • +
    • Useful for temprorarily disabling all interrupts for timing critical tasks.
      • +
    • Does not have the ability to mask BusFault or bypass MPU.
      • +
    +
    +
    See also:
    +
    + +
    +
    + +
    +
    + + + + + + + + +
    void __set_PSP (uint32_t topOfProcStack)
    +
    +
    +

    The function sets the Program Status Pointer (PSP) value using the instruction MSR.
    +
    + Physically two different stack pointers (SP) exist:

    +
      +
    • The Main Stack Pointer (MSP) is the default stack pointer after reset. It is also used when running exception handlers (handler mode).
      • +
    • The Process Stack Pointer (PSP), which can be used only in thread mode.
      • +
    +

    Register R13 banks the SP. The SP selection is determined by the bit[1] of the CONTROL register:

    +
      +
    • =0 MSP is the current stack pointer. This is also the default SP. The initial value is loaded from the first 32-bit word of the vector table from the program memory.
      • +
    • =1 PSP is the current stack pointer. The initial value is undefined.
      • +
    +
    Parameters:
    + + +
    [in]topOfProcStackPSP value to set
    +
    +
    +
    Remarks:
      +
    • Only one of the two SPs is visible at a time.
      • +
    • For many applications, the system can completely rely on the MSP.
      • +
    • The PSP is normally used in designs with an OS where the stack memory for OS Kernel must be separated from the application code.
      • +
    +
    +
    See also:
    +
    + +
    +
    +
    +
    + + + + + diff --git a/Libraries/CMSIS/Documentation/Core/html/group___i_t_m___debug__gr.html b/Libraries/CMSIS/Documentation/Core/html/group___i_t_m___debug__gr.html new file mode 100644 index 0000000..08890ab --- /dev/null +++ b/Libraries/CMSIS/Documentation/Core/html/group___i_t_m___debug__gr.html @@ -0,0 +1,278 @@ + + + + +Debug Access + + + + + + + + + + + + + +
    + +
    + + + + + + + + + + + +
    +
    CMSIS-CORE +  Version 3.01 +
    +
    CMSIS-CORE support for Cortex-M processor-based devices
    +
    +
    + +
    + +
    + + + +
    +
    + +
    +
    +
    + +
    +
    +
    +Variables | +Functions
    +
    +
    Debug Access
    +
    +
    + + + + + + + + + + + +

    +Variables

    volatile int32_t ITM_RxBuffer
     external variable to receive characters

    +Functions

    uint32_t ITM_SendChar (uint32_t ch)
     Transmits a character via channel 0.
    int32_t ITM_ReceiveChar (void)
     ITM Receive Character.
    int32_t ITM_CheckChar (void)
     ITM Check Character.
    +

    Description

    +

    CMSIS provides additional debug functions to enlarge the Debug Access. Data can be transmitted via a certain global buffer variable towards the target system.

    +

    The Cortex-M3 / Cortex-M4 incorporates the Instrumented Trace Macrocell (ITM) that provides together with the Serial Viewer Output (SVO) trace capabilities for the microcontroller system. The ITM has 32 communication channels; two ITM communication channels are used by CMSIS to output the following information:

    +
      +
    • ITM Channel 0: implements the ITM_SendChar function which can be used for printf-style output via the debug interface.
      • +
    +
      +
    • ITM Channel 31: is reserved for the RTOS kernel and can be used for kernel awareness debugging.
      • +
    +
    Remarks:
      +
    • ITM channels have 4 groups with 8 channels each, whereby each group can be configured for access rights in the Unprivileged level.
      • +
    • The ITM channel 0 can be enabled for the user task.
      • +
    • ITM channel 31 can be accessed only in Privileged mode from the RTOS kernel itself. The ITM channel 31 has been selected for the RTOS kernel because some kernels may use the Privileged level for program execution.
      • +
    +
    +
    +

    +ITM Debug Support in uVision

    +

    In a debug session, uVision uses the Debug (printf) Viewer window to display data.

    +

    Direction: Microcontroller --> uVision:

    +
      +
    • Characters received via ITM communication channel 0 are written in a printf-style to the Debug (printf) Viewer window.
      • +
    +

    Direction: uVision --> Microcontroller:

    +
      +
    • Check if ITM_RxBuffer variable is available (only performed once).
      • +
    • Read the character from the Debug (printf) Viewer window.
      • +
    • If ITM_RxBuffer is empty, write character to ITM_RxBuffer.
      • +
    +
    Note:
    The current solution does not use a buffer mechanism for transmitting the characters.
    +
    +

    +Example:

    +

    Example for the usage of the ITM Channel 31 for RTOS Kernels:

    +
    // check if debugger connected and ITM channel enabled for tracing
+if ((CoreDebug->DEMCR & CoreDebug_DEMCR_TRCENA) &&
+    (ITM->TCR & ITM_TCR_ITMENA) &&
+    (ITM->TER & (1UL >> 31))) {
+    
+    // transmit trace data
+    while (ITM->PORT31_U32 == 0);
+    ITM->PORT[31].u8 = task_id;      // id of next task
+    while (ITM->PORT[31].u32 == 0);
+    ITM->PORT[31].u32 = task_status; // status information
+}
+

    Variable Documentation

    + +
    +
    + + + + +
    volatile int32_t ITM_RxBuffer
    +
    +
    + +
    +
    +

    Function Documentation

    + +
    +
    + + + + + + + + +
    int32_t ITM_CheckChar (void )
    +
    +
    +

    This function reads the external variable ITM_RxBuffer and checks whether a character is available or not.

    +
    Returns:
      +
    • =0 - No character available
      • +
    • =1 - Character available
      • +
    +
    + +
    +
    + +
    +
    + + + + + + + + +
    int32_t ITM_ReceiveChar (void )
    +
    +
    +

    This function inputs a character via the external variable ITM_RxBuffer. It returns when no debugger is connected that has booked the output. It is blocking when a debugger is connected, but the previously sent character has not been transmitted.

    +
    Returns:
      +
    • Received character
      • +
    • =1 - No character received
      • +
    +
    + +
    +
    + +
    +
    + + + + + + + + +
    uint32_t ITM_SendChar (uint32_t ch)
    +
    +
    +

    This function transmits a character via the ITM channel 0. It returns when no debugger is connected that has booked the output. It is blocking when a debugger is connected, but the previously sent character has not been transmitted.

    +
    Parameters:
    + + +
    [in]chCharacter to transmit
    +
    +
    +
    Returns:
    Character to transmit
    + +
    +
    +
    +
    + + + + + diff --git a/Libraries/CMSIS/Documentation/Core/html/group___n_v_i_c__gr.html b/Libraries/CMSIS/Documentation/Core/html/group___n_v_i_c__gr.html new file mode 100644 index 0000000..6d1c509 --- /dev/null +++ b/Libraries/CMSIS/Documentation/Core/html/group___n_v_i_c__gr.html @@ -0,0 +1,1033 @@ + + + + +Interrupts and Exceptions (NVIC) + + + + + + + + + + + + + +
    + +
    + + + + + + + + + + + +
    +
    CMSIS-CORE +  Version 3.01 +
    +
    CMSIS-CORE support for Cortex-M processor-based devices
    +
    +
    + +
    + +
    + + + +
    +
    + +
    +
    +
    + +
    +
    +
    +Enumerations | +Functions
    +
    +
    Interrupts and Exceptions (NVIC)
    +
    +
    + +

    Describes programming of interrupts and exception functions. +More...

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +

    +Enumerations

    enum  IRQn_Type {
    +  NonMaskableInt_IRQn = -14, +
    +  HardFault_IRQn = -13, +
    +  MemoryManagement_IRQn = -12, +
    +  BusFault_IRQn = -11, +
    +  UsageFault_IRQn = -10, +
    +  SVCall_IRQn = -5, +
    +  DebugMonitor_IRQn = -4, +
    +  PendSV_IRQn = -2, +
    +  SysTick_IRQn = -1, +
    +  WWDG_STM_IRQn = 0, +
    +  PVD_STM_IRQn = 1 +
    + }
     Definition of IRQn numbers. More...

    +Functions

    void NVIC_SetPriorityGrouping (uint32_t PriorityGroup)
     Set priority grouping [not for Cortex-M0 variants].
    uint32_t NVIC_GetPriorityGrouping (void)
     Read the priority grouping [not for Cortex-M0 variants].
    void NVIC_EnableIRQ (IRQn_Type IRQn)
     Enable an external interrupt.
    void NVIC_DisableIRQ (IRQn_Type IRQn)
     Disable an external interrupt.
    uint32_t NVIC_GetPendingIRQ (IRQn_Type IRQn)
     Get the pending interrupt.
    void NVIC_SetPendingIRQ (IRQn_Type IRQn)
     Set an interrupt to pending.
    void NVIC_ClearPendingIRQ (IRQn_Type IRQn)
     Clear an interrupt from pending.
    uint32_t NVIC_GetActive (IRQn_Type IRQn)
     Get the interrupt active status [not for Cortex-M0 variants].
    void NVIC_SetPriority (IRQn_Type IRQn, uint32_t priority)
     Set the priority for an interrupt.
    uint32_t NVIC_GetPriority (IRQn_Type IRQn)
     Get the priority of an interrupt.
    uint32_t NVIC_EncodePriority (uint32_t PriorityGroup, uint32_t PreemptPriority, uint32_t SubPriority)
     Encodes Priority [not for Cortex-M0 variants].
    void NVIC_DecodePriority (uint32_t Priority, uint32_t PriorityGroup, uint32_t *pPreemptPriority, uint32_t *pSubPriority)
     Decode the interrupt priority [not for Cortex-M0 variants].
    void NVIC_SystemReset (void)
     Reset the system.
    +

    Description

    +

    ARM provides a template file startup_device for each supported compiler. The file must be adapted by the silicon vendor to include interrupt vectors for all device-specific interrupt handlers. Each interrupt handler is defined as a weak function to an dummy handler. These interrupt handlers can be used directly in application software without being adapted by the programmer.

    +

    The table below describes the core exception names and their availability in various Cortex-M cores.

    + + + + + + + + + + + + + + + + + + + + + +
    Core Exception Name IRQn Value M0 M0p M3 M4 SC000 SC300 Description
    NonMaskableInt_IRQn -14
    +check.png +
    +
    +check.png +
    +
    +check.png +
    +
    +check.png +
    +
    +check.png +
    +
    +check.png +
    +     		Non Maskable Interrupt
    HardFault_IRQn -13
    +check.png +
    +
    +check.png +
    +
    +check.png +
    +
    +check.png +
    +
    +check.png +
    +
    +check.png +
    +     		Hard Fault Interrupt
    MemoryManagement_IRQn -12    
    +check.png +
    +
    +check.png +
    +     		 
    +check.png +
    +     		Memory Management Interrupt
    BusFault_IRQn -11    
    +check.png +
    +
    +check.png +
    +     		 
    +check.png +
    +     		Bus Fault Interrupt
    UsageFault_IRQn -10    
    +check.png +
    +
    +check.png +
    +     		 
    +check.png +
    +     		Usage Fault Interrupt
    SVCall_IRQn -5
    +check.png +
    +
    +check.png +
    +
    +check.png +
    +
    +check.png +
    +
    +check.png +
    +
    +check.png +
    +     		SV Call Interrupt
    DebugMonitor_IRQn -4    
    +check.png +
    +
    +check.png +
    +     		 
    +check.png +
    +     		Debug Monitor Interrupt
    PendSV_IRQn -2
    +check.png +
    +
    +check.png +
    +
    +check.png +
    +
    +check.png +
    +
    +check.png +
    +
    +check.png +
    +     		Pend SV Interrupt
    SysTick_IRQn -1
    +check.png +
    +
    +check.png +
    +
    +check.png +
    +
    +check.png +
    +
    +check.png +
    +
    +check.png +
    +     		System Tick Interrupt
    +

    +For Cortex-M0 and Cortex-M0+

    +

    The following exception names are fixed and define the start of the vector table for Cortex-M0 variants:

    +
    __Vectors       DCD     __initial_sp              ; Top of Stack
+                DCD     Reset_Handler             ; Reset Handler
+                DCD     NMI_Handler               ; NMI Handler
+                DCD     HardFault_Handler         ; Hard Fault Handler
+                DCD     0                         ; Reserved
+                DCD     0                         ; Reserved
+                DCD     0                         ; Reserved
+                DCD     0                         ; Reserved
+                DCD     0                         ; Reserved
+                DCD     0                         ; Reserved
+                DCD     0                         ; Reserved
+                DCD     SVC_Handler               ; SVCall Handler
+                DCD     0                         ; Reserved
+                DCD     0                         ; Reserved
+                DCD     PendSV_Handler            ; PendSV Handler
+                DCD     SysTick_Handler           ; SysTick Handler
+

    +For Cortex-M3

    +

    The following exception names are fixed and define the start of the vector table for a Cortex-M3:

    +
    __Vectors       DCD     __initial_sp              ; Top of Stack
+                DCD     Reset_Handler             ; Reset Handler
+                DCD     NMI_Handler               ; NMI Handler
+                DCD     HardFault_Handler         ; Hard Fault Handler
+                DCD     MemManage_Handler         ; MPU Fault Handler
+                DCD     BusFault_Handler          ; Bus Fault Handler
+                DCD     UsageFault_Handler        ; Usage Fault Handler
+                DCD     0                         ; Reserved
+                DCD     0                         ; Reserved
+                DCD     0                         ; Reserved
+                DCD     0                         ; Reserved
+                DCD     SVC_Handler               ; SVCall Handler
+                DCD     DebugMon_Handler          ; Debug Monitor Handler
+                DCD     0                         ; Reserved
+                DCD     PendSV_Handler            ; PendSV Handler
+                DCD     SysTick_Handler           ; SysTick Handler
+

    +Example

    +

    The following is an examples for device-specific interrupts:

    +
    ; External Interrupts
+                DCD     WWDG_IRQHandler           ; Window Watchdog
+                DCD     PVD_IRQHandler            ; PVD through EXTI Line detect
+                DCD     TAMPER_IRQHandler         ; Tamper
+

    Device-specific interrupts must have a dummy function that can be overwritten in user code. Below is an example for this dummy function.

    +
    Default_Handler PROC
+                EXPORT WWDG_IRQHandler   [WEAK]
+                EXPORT PVD_IRQHandler    [WEAK]
+                EXPORT TAMPER_IRQHandler [WEAK]
+                :
+                :
+                WWDG_IRQHandler
+                PVD_IRQHandler
+                TAMPER_IRQHandler
+                :
+                :
+                B .
+                ENDP
+

    The user application may simply define an interrupt handler function by using the handler name as shown below.

    +
    void WWDG_IRQHandler(void)
+{
+  ...
+}
+

    +Code Example 1

    +

    The code below shows the usage of the CMSIS NVIC functions NVIC_SetPriorityGrouping(), NVIC_GetPriorityGrouping(), NVIC_SetPriority(), NVIC_GetPriority(), NVIC_EncodePriority(), and NVIC_DecodePriority() with an LPC1700.

    +
    #include "LPC17xx.h"
+
+uint32_t priorityGroup;                                     /* Variables to store priority group and priority */
+uint32_t priority;
+uint32_t preemptPriority;
+uint32_t subPriority;
+
+
+int main (void)  {
+
+  NVIC_SetPriorityGrouping(5);                              /* Set priority group to 5:
+                                                               Bit[7..6] preempt priority Bits, 
+                                                               Bit[5..3] subpriority Bits 
+                                                               (valid for five priority bits) */
+     
+  priorityGroup =  NVIC_GetPriorityGrouping();              /* Get used priority grouping */
+
+  priority = NVIC_EncodePriority(priorityGroup, 1, 6);      /* Encode priority with 6 for subpriority and 1 for preempt priority
+                                                               Note: priority depends on the used priority grouping */
+                                                               
+  NVIC_SetPriority(UART0_IRQn, priority);                   /* Set new priority */
+
+  priority =  NVIC_GetPriority(UART0_IRQn);                 /* Retrieve priority again */    
+
+  NVIC_DecodePriority(priority, priorityGroup, &preemptPriority, &subPriority);
+
+  while(1);
+}
+

    +Code Example 2

    +

    The code below shows the usage of the CMSIS NVIC functions NVIC_EnableIRQ(), NVIC_GetActive() with an LPC1700.

    +
    #include "LPC17xx.h"
+
+uint32_t active;                                            /* Variable to store interrupt active state */
+
+
+void TIMER0_IRQHandler(void)  {                             /* Timer 0 interrupt handler  */
+
+  if (LPC_TIM0->IR & (1 << 0))  {                           /* Check if interrupt for match channel 0 occured */ 
+    LPC_TIM0->IR |= (1 << 0);                               /* Acknowledge interrupt for match channel 0 occured */
+  }
+  active = NVIC_GetActive(TIMER0_IRQn);                     /* Get interrupt active state of timer 0 */
+}
+
+
+int main (void) {
+                                                            /* Set match channel register MR0 to 1 millisecond */
+  LPC_TIM0->MR0 = (((SystemCoreClock / 1000) / 4) - 1);     /* 1 ms? */
+  
+  LPC_TIM0->MCR = (3 << 0);                                 /* Enable interrupt and reset for match channel MR0 */
+
+  NVIC_EnableIRQ(TIMER0_IRQn);                              /* Enable NVIC interrupt for timer 0 */
+  
+  LPC_TIM0->TCR = (1 << 0);                                 /* Enable timer 0 */
+
+  while(1);
+}
+

    Enumeration Type Documentation

    + +
    +
    + + + + +
    enum IRQn_Type
    +
    +
    +

    The core exception enumeration names for IRQn values are defined in the file device.h.

    +

    Negative IRQn values represent processor core exceptions (internal interrupts). Positive IRQn values represent device-specific exceptions (external interrupts). The first device-specific interrupt has the IRQn value 0.

    +

    The table below describes the core exception names and their availability in various Cortex-M cores.

    +
    Enumerator:
    + + + + + + + + + + + +
    NonMaskableInt_IRQn  +

    Exception 2: Non Maskable Interrupt.

    +
    HardFault_IRQn  +

    Exception 3: Hard Fault Interrupt.

    +
    MemoryManagement_IRQn  +

    Exception 4: Memory Management Interrupt [not on Cortex-M0 variants].

    +
    BusFault_IRQn  +

    Exception 5: Bus Fault Interrupt [not on Cortex-M0 variants].

    +
    UsageFault_IRQn  +

    Exception 6: Usage Fault Interrupt [not on Cortex-M0 variants].

    +
    SVCall_IRQn  +

    Exception 11: SV Call Interrupt.

    +
    DebugMonitor_IRQn  +

    Exception 12: Debug Monitor Interrupt [not on Cortex-M0 variants].

    +
    PendSV_IRQn  +

    Exception 14: Pend SV Interrupt [not on Cortex-M0 variants].

    +
    SysTick_IRQn  +

    Exception 15: System Tick Interrupt.

    +
    WWDG_STM_IRQn  +

    Device Interrupt 0: Window WatchDog Interrupt.

    +
    PVD_STM_IRQn  +

    Device Interrupt 1: PVD through EXTI Line detection Interrupt.

    +
    +
    +
    + +
    +
    +

    Function Documentation

    + +
    +
    + + + + + + + + +
    void NVIC_ClearPendingIRQ (IRQn_Type IRQn)
    +
    +
    +

    This function removes the pending state of the specified interrupt IRQn. IRQn cannot be a negative number.

    +
    Parameters:
    + + +
    [in]IRQnInterrupt number
    +
    +
    +
    Remarks:
      +
    • The registers that control the status of interrupts are called SETPEND and CLRPEND.
      • +
    • An interrupt can have the status pending though it is not active.
      • +
    +
    +
    See also:
    +
    + +
    +
    + +
    +
    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    void NVIC_DecodePriority (uint32_t Priority,
    uint32_t PriorityGroup,
    uint32_t * pPreemptPriority,
    uint32_t * pSubPriority 
    )
    +
    +
    +

    This function decodes an interrupt priority value with the priority group PriorityGroup to preemptive priority value pPreemptPriority and subpriority value pSubPriority. In case of a conflict between priority grouping and available priority bits (__NVIC_PRIO_BITS) the smallest possible priority group is set.

    +
    Parameters:
    + + + + + +
    [in]PriorityPriority
    [in]PriorityGroupPriority group
    [out]*pPreemptPriorityPreemptive priority value (starting from 0)
    [out]*pSubPrioritySubpriority value (starting from 0)
    +
    +
    +
    Remarks:
      +
    • not for Cortex-M0 variants.
      • +
    +
    +
    See also:
    +
    + +
    +
    + +
    +
    + + + + + + + + +
    void NVIC_DisableIRQ (IRQn_Type IRQn)
    +
    +
    +

    This function disables the specified device-specific interrupt IRQn. IRQn cannot be a negative value.

    +
    Parameters:
    + + +
    [in]IRQnNumber of the external interrupt to disable
    +
    +
    +
    Remarks:
      +
    • The registers that control the enabling and disabling of interrupts are called SETENA and CLRENA.
      • +
    +
    +
    See also:
    +
    + +
    +
    + +
    +
    + + + + + + + + +
    void NVIC_EnableIRQ (IRQn_Type IRQn)
    +
    +
    +

    This function enables the specified device-specific interrupt IRQn. IRQn cannot be a negative value.

    +
    Parameters:
    + + +
    [in]IRQnInterrupt number
    +
    +
    +
    Remarks:
      +
    • The registers that control the enabling and disabling of interrupts are called SETENA and CLRENA.
      • +
    • The number of supported interrupts depends on the implementation of the chip designer and can be read form the Interrupt Controller Type Register (ICTR) in granularities of 32:
      + ICTR[4:0]
        +
      • =0 - 32 interrupts supported
        • +
      • =1 - 64 interrupts supported
        • +
      • ...
        • +
      +
      • +
    +
    +
    See also:
    +
    + +
    +
    + +
    +
    + + + + + + + + + + + + + + + + + + + + + + + + +
    uint32_t NVIC_EncodePriority (uint32_t PriorityGroup,
    uint32_t PreemptPriority,
    uint32_t SubPriority 
    )
    +
    +
    +

    This function encodes the priority for an interrupt with the priority group PriorityGroup, preemptive priority value PreemptPriority, and subpriority value SubPriority. In case of a conflict between priority grouping and available priority bits (__NVIC_PRIO_BITS) the smallest possible priority group is set.

    +
    Parameters:
    + + + + +
    [in]PriorityGroupPriority group
    [in]PreemptPriorityPreemptive priority value (starting from 0)
    [in]SubPrioritySubpriority value (starting from 0)
    +
    +
    +
    Returns:
    Encoded priority for the interrupt
    +
    Remarks:
      +
    • not for Cortex-M0 variants.
      • +
    +
    +
    See also:
    +
    + +
    +
    + +
    +
    + + + + + + + + +
    uint32_t NVIC_GetActive (IRQn_Type IRQn)
    +
    +
    +

    This function reads the Interrupt Active Register (NVIC_IABR0-NVIC_IABR7) in NVIC and returns the active bit of the interrupt IRQn.

    +
    Parameters:
    + + +
    [in]IRQnInterrupt number
    +
    +
    +
    Returns:
      +
    • =0 Interrupt is not active
      • +
    • =1 Interrupt is active, or active and pending
      • +
    +
    +
    Remarks:
      +
    • not for Cortex-M0 variants.
      • +
    • Each external interrupt has an active status bit. When the processor starts the interrupt handler the bit is set to 1 and cleared when the interrupt return is executed.
      • +
    • When an ISR is preempted and the processor executes anohter interrupt handler, the previous interrupt is still defined as active.
      • +
    +
    +
    See also:
    +
    + +
    +
    + +
    +
    + + + + + + + + +
    uint32_t NVIC_GetPendingIRQ (IRQn_Type IRQn)
    +
    +
    +

    This function returns the pending status of the specified interrupt IRQn.

    +
    Parameters:
    + + +
    [in]IRQnInterrupt number
    +
    +
    +
    Returns:
      +
    • =0 Interrupt is not pending
      • +
    • =1 Interrupt is pending
      • +
    +
    +
    Remarks:
      +
    • The registers that control the status of interrupts are called SETPEND and CLRPEND.
      • +
    +
    +
    See also:
    +
    + +
    +
    + +
    +
    + + + + + + + + +
    uint32_t NVIC_GetPriority (IRQn_Type IRQn)
    +
    +
    +

    This function reads the priority for the specified interrupt IRQn. IRQn can can specify any device-specific (external) interrupt, or core (internal) interrupt.

    +

    The returned priority value is automatically aligned to the implemented priority bits of the microcontroller.

    +
    Parameters:
    + + +
    [in]IRQnInterrupt number
    +
    +
    +
    Returns:
    Interrupt priority
    +
    Remarks:
      +
    • Each external interrupt has an associated priority-level register.
      • +
    • Unimplemented bits are read as zero.
      • +
    +
    +
    See also:
    +
    + +
    +
    + +
    +
    + + + + + + + + +
    uint32_t NVIC_GetPriorityGrouping (void )
    +
    +
    +

    This functuion returns the priority grouping (flag PRIGROUP in AIRCR[10:8]).

    +
    Returns:
    Priority grouping field
    +
    Remarks:
      +
    • not for Cortex-M0 variants.
      • +
    • By default, priority group setting is zero.
      • +
    +
    +
    See also:
    +
    + +
    +
    + +
    +
    + + + + + + + + +
    void NVIC_SetPendingIRQ (IRQn_Type IRQn)
    +
    +
    +

    This function sets the pending bit for the specified interrupt IRQn. IRQn cannot be a negative value.

    +
    Parameters:
    + + +
    [in]IRQnInterrupt number
    +
    +
    +
    Remarks:
      +
    • The registers that control the status of interrupts are called SETPEND and CLRPEND.
      • +
    +
    +
    See also:
    +
    + +
    +
    + +
    +
    + + + + + + + + + + + + + + + + + + +
    void NVIC_SetPriority (IRQn_Type IRQn,
    uint32_t priority 
    )
    +
    +
    +

    Sets the priority for the interrupt specified by IRQn.IRQn can can specify any device-specific (external) interrupt, or core (internal) interrupt. The priority specifies the interrupt priority value, whereby lower values indicate a higher priority. The default priority is 0 for every interrupt. This is the highest possible priority.

    +

    The priority cannot be set for every core interrupt. HardFault and NMI have a fixed (negative) priority that is higher than any configurable exception or interrupt.

    +
    Parameters:
    + + + +
    [in]IRQnInterrupt Number
    [in]priorityPriority to set
    +
    +
    +
    Remarks:
      +
    • The number of priority levels is configurable and depends on the implementation of the chip designer. To determine the number of bits implemented for interrupt priority-level registers, write 0xFF to one of the priority-level register, then read back the value. For example, if the minimum number of 3 bits have been implemented, the read-back value is 0xE0.
      • +
    • Writes to unimplemented bits are ignored.
      • +
    • For Cortex-M0:
        +
      • Dynamic switching of interrupt priority levels is not supported. The priority level of an interrupt should not be changed after it has been enabled.
        • +
      • Supports 0 to 192 priority levels.
        • +
      • Priority-level registers are 2 bit wide, occupying the two MSBs. Each Interrupt Priority Level Register is 1-byte wide.
        • +
      +
      • +
    • For Cortex-M3 and Cortex-M4:
        +
      • Dynamic switching of interrupt priority levels is supported.
        • +
      • Supports 0 to 255 priority levels.
        • +
      • Priority-level registers have a maximum width of 8 bits and a minumum of 3 bits. Each register can be further devided into preempt priority level and subpriority level.
        • +
      +
      • +
    +
    +
    See also:
    +
    + +
    +
    + +
    +
    + + + + + + + + +
    void NVIC_SetPriorityGrouping (uint32_t PriorityGroup)
    +
    +
    +

    The function sets the priority grouping PriorityGroup using the required unlock sequence. PriorityGroup is assigned to the field PRIGROUP (register AIRCR[10:8]). This field determines the split of group priority from subpriority. Only values from 0..7 are used. In case of a conflict between priority grouping and available priority bits (__NVIC_PRIO_BITS), the smallest possible priority group is set.

    +
    Parameters:
    + + +
    [in]PriorityGroupPriority group
    +
    +
    +
    Remarks:
      +
    • not for Cortex-M0 variants.
      • +
    • By default, priority group setting is zero.
      • +
    +
    +
    See also:
    +
    + +
    +
    + +
    +
    + + + + + + + + +
    void NVIC_SystemReset (void )
    +
    +
    +

    This function requests a system reset by setting the SYSRESETREQ flag in the AIRCR register.

    +
    Remarks:
      +
    • In most microcontroller designs, setting the SYSRESETREQ flag resets the processor and most parts of the system, but should not affect the debug system.
      • +
    +
    +
    See also:
    +
    + +
    +
    +
    +
    + + + + + diff --git a/Libraries/CMSIS/Documentation/Core/html/group___sys_tick__gr.html b/Libraries/CMSIS/Documentation/Core/html/group___sys_tick__gr.html new file mode 100644 index 0000000..0c55ae9 --- /dev/null +++ b/Libraries/CMSIS/Documentation/Core/html/group___sys_tick__gr.html @@ -0,0 +1,196 @@ + + + + +Systick Timer (SYSTICK) + + + + + + + + + + + + + +
    + +
    + + + + + + + + + + + +
    +
    CMSIS-CORE +  Version 3.01 +
    +
    CMSIS-CORE support for Cortex-M processor-based devices
    +
    +
    + +
    + +
    + + + +
    +
    + +
    +
    +
    + +
    +
    +
    +Functions
    +
    +
    Systick Timer (SYSTICK)
    +
    +
    + +

    Initialize and start the SysTick timer. +More...

    + + + + +

    +Functions

    uint32_t SysTick_Config (uint32_t ticks)
     System Tick Timer Configuration.
    +

    Description

    +

    The System Tick Time (SysTick) generates interrupt requests on a regular basis. This allows an OS to carry out context switching to support multiple tasking. For applications that do not require an OS, the SysTick can be used for time keeping, time measurement, or as an interrupt source for tasks that need to be executed regularly.

    +

    +Code Example

    +

    The code below shows the usage of the function SysTick_Config() with an LPC1700.

    +
    #include "LPC17xx.h"
+
+uint32_t msTicks = 0;                                       /* Variable to store millisecond ticks */
+
+                                            
+void SysTick_Handler(void)  {                               /* SysTick interrupt Handler.
+  msTicks++;                                                   See startup file startup_LPC17xx.s for SysTick vector */ 
+}
+
+
+int main (void)  {
+  uint32_t returnCode;
+
+  returnCode = SysTick_Config(SystemCoreClock / 1000);      /* Configure SysTick to generate an interrupt every millisecond */
+
+  if (returnCode != 0)  {                                   /* Check return code for errors */
+    // Error Handling 
+  }
+
+  while(1);
+}
+

    Function Documentation

    + +
    +
    + + + + + + + + +
    uint32_t SysTick_Config (uint32_t ticks)
    +
    +
    +

    Initialises and starts the System Tick Timer and its interrupt. After this call, the SysTick timer creates interrupts with the specified time interval. Counter is in free running mode to generate periodical interrupts.

    +
    Parameters:
    + + +
    [in]ticksNumber of ticks between two interrupts
    +
    +
    +
    Returns:
    0 - success
    +
    +1 - failure
    +
    Note:
    When #define __Vendor_SysTickConfig is set to 1, the standard function SysTick_Config is excluded. In this case, the file device.h must contain a vendor specific implementation of this function.
    + +
    +
    +
    +
    + + + + + diff --git a/Libraries/CMSIS/Documentation/Core/html/group__intrinsic___c_p_u__gr.html b/Libraries/CMSIS/Documentation/Core/html/group__intrinsic___c_p_u__gr.html new file mode 100644 index 0000000..9935034 --- /dev/null +++ b/Libraries/CMSIS/Documentation/Core/html/group__intrinsic___c_p_u__gr.html @@ -0,0 +1,766 @@ + + + + +Intrinsic Functions for CPU Instructions + + + + + + + + + + + + + +
    + +
    + + + + + + + + + + + +
    +
    CMSIS-CORE +  Version 3.01 +
    +
    CMSIS-CORE support for Cortex-M processor-based devices
    +
    +
    + +
    + +
    + + + +
    +
    + +
    +
    +
    + +
    +
    +
    +Functions
    +
    +
    Intrinsic Functions for CPU Instructions
    +
    +
    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +

    +Functions

    void __NOP (void)
     No Operation.
    void __WFI (void)
     Wait For Interrupt.
    void __WFE (void)
     Wait For Event.
    void __SEV (void)
     Send Event.
    void __ISB (void)
     Instruction Synchronization Barrier.
    void __DSB (void)
     Data Synchronization Barrier.
    void __DMB (void)
     Data Memory Barrier.
    uint32_t __REV (uint32_t value)
     Reverse byte order (32 bit)
    uint32_t __REV16 (uint32_t value)
     Reverse byte order (16 bit)
    int32_t __REVSH (int32_t value)
     Reverse byte order in signed short value.
    uint32_t __RBIT (uint32_t value)
     Reverse bit order of value [not for Cortex-M0 variants].
    uint32_t __ROR (uint32_t value, uint32_t shift)
     Rotate a value right by a number of bits.
    uint8_t __LDREXB (volatile uint8_t *addr)
     LDR Exclusive (8 bit) [not for Cortex-M0 variants].
    uint16_t __LDREXH (volatile uint16_t *addr)
     LDR Exclusive (16 bit) [not for Cortex-M0 variants].
    uint32_t __LDREXW (volatile uint32_t *addr)
     LDR Exclusive (32 bit) [not for Cortex-M0 variants].
    uint32_t __STREXB (uint8_t value, volatile uint8_t *addr)
     STR Exclusive (8 bit) [not for Cortex-M0 variants].
    uint32_t __STREXH (uint16_t value, volatile uint16_t *addr)
     STR Exclusive (16 bit) [not for Cortex-M0 variants].
    uint32_t __STREXW (uint32_t value, volatile uint32_t *addr)
     STR Exclusive (32 bit) [not for Cortex-M0 variants].
    void __CLREX (void)
     Remove the exclusive lock [not for Cortex-M0 variants].
    uint32_t __SSAT (unint32_t value, uint32_t sat)
     Signed Saturate [not for Cortex-M0 variants].
    uint32_t __USAT (uint32_t value, uint32_t sat)
     Unsigned Saturate [not for Cortex-M0 variants].
    uint8_t __CLZ (uint32_t value)
     Count leading zeros [not for Cortex-M0 variants].
    +

    Description

    +

    The following functions generate specific Cortex-M instructions that cannot be directly accessed by the C/C++ Compiler.

    +

    Function Documentation

    + +
    +
    + + + + + + + + +
    void __CLREX (void )
    +
    +
    +

    This function removes the exclusive lock which is created by LDREX [not for Cortex-M0 variants].

    + +
    +
    + +
    +
    + + + + + + + + +
    uint8_t __CLZ (uint32_t value)
    +
    +
    +

    This function counts the number of leading zeros of a data value [not for Cortex-M0 variants].

    +
    Parameters:
    + + +
    [in]valueValue to count the leading zeros
    +
    +
    +
    Returns:
    number of leading zeros in value
    + +
    +
    + +
    +
    + + + + + + + + +
    void __DMB (void )
    +
    +
    +

    This function ensures the apparent order of the explicit memory operations before and after the instruction, without ensuring their completion.

    + +
    +
    + +
    +
    + + + + + + + + +
    void __DSB (void )
    +
    +
    +

    This function acts as a special kind of Data Memory Barrier. It completes when all explicit memory accesses before this instruction complete.

    + +
    +
    + +
    +
    + + + + + + + + +
    void __ISB (void )
    +
    +
    +

    Instruction Synchronization Barrier flushes the pipeline in the processor, so that all instructions following the ISB are fetched from cache or memory, after the instruction has been completed.

    + +
    +
    + +
    +
    + + + + + + + + +
    uint8_t __LDREXB (volatile uint8_t * addr)
    +
    +
    +

    This function performs a exclusive LDR command for 8 bit value [not for Cortex-M0 variants].

    +
    Parameters:
    + + +
    [in]*addrPointer to data
    +
    +
    +
    Returns:
    value of type uint8_t at (*addr)
    + +
    +
    + +
    +
    + + + + + + + + +
    uint16_t __LDREXH (volatile uint16_t * addr)
    +
    +
    +

    This function performs a exclusive LDR command for 16 bit values [not for Cortex-M0 variants].

    +
    Parameters:
    + + +
    [in]*addrPointer to data
    +
    +
    +
    Returns:
    value of type uint16_t at (*addr)
    + +
    +
    + +
    +
    + + + + + + + + +
    uint32_t __LDREXW (volatile uint32_t * addr)
    +
    +
    +

    This function performs a exclusive LDR command for 32 bit values [not for Cortex-M0 variants].

    +
    Parameters:
    + + +
    [in]*addrPointer to data
    +
    +
    +
    Returns:
    value of type uint32_t at (*addr)
    + +
    +
    + +
    +
    + + + + + + + + +
    void __NOP (void )
    +
    +
    +

    This function does nothing. This instruction can be used for code alignment purposes.

    + +
    +
    + +
    +
    + + + + + + + + +
    uint32_t __RBIT (uint32_t value)
    +
    +
    +

    This function reverses the bit order of the given value [not for Cortex-M0 variants].

    +
    Parameters:
    + + +
    [in]valueValue to reverse
    +
    +
    +
    Returns:
    Reversed value
    + +
    +
    + +
    +
    + + + + + + + + +
    uint32_t __REV (uint32_t value)
    +
    +
    +

    This function reverses the byte order in integer value.

    +
    Parameters:
    + + +
    [in]valueValue to reverse
    +
    +
    +
    Returns:
    Reversed value
    + +
    +
    + +
    +
    + + + + + + + + +
    uint32_t __REV16 (uint32_t value)
    +
    +
    +

    This function reverses the byte order in two unsigned short values.

    +
    Parameters:
    + + +
    [in]valueValue to reverse
    +
    +
    +
    Returns:
    Reversed value
    + +
    +
    + +
    +
    + + + + + + + + +
    int32_t __REVSH (int32_t value)
    +
    +
    +

    This function reverses the byte order in a signed short value with sign extension to integer.

    +
    Parameters:
    + + +
    [in]valueValue to reverse
    +
    +
    +
    Returns:
    Reversed value
    + +
    +
    + +
    +
    + + + + + + + + + + + + + + + + + + +
    uint32_t __ROR (uint32_t value,
    uint32_t shift 
    )
    +
    +
    +

    This function rotates a value right by a specified number of bits.

    +
    Parameters:
    + + + +
    [in]valueValue to be shifted right
    [in]shiftNumber of bits in the range [1..31]
    +
    +
    +
    Returns:
    Rotated value
    + +
    +
    + +
    +
    + + + + + + + + +
    void __SEV (void )
    +
    +
    +

    Send Event is a hint instruction. It causes an event to be signaled to the CPU.

    + +
    +
    + +
    +
    + + + + + + + + + + + + + + + + + + +
    uint32_t __SSAT (unint32_t value,
    uint32_t sat 
    )
    +
    +
    +

    This function saturates a signed value [not for Cortex-M0 variants].

    +
    Parameters:
    + + + +
    [in]valueValue to be saturated
    [in]satBit position to saturate to [1..32]
    +
    +
    +
    Returns:
    Saturated value
    + +
    +
    + +
    +
    + + + + + + + + + + + + + + + + + + +
    uint32_t __STREXB (uint8_t value,
    volatile uint8_t * addr 
    )
    +
    +
    +

    This function performs a exclusive STR command for 8 bit values [not for Cortex-M0 variants].

    +
    Parameters:
    + + + +
    [in]valueValue to store
    [in]*addrPointer to location
    +
    +
    +
    Returns:
    0 Function succeeded
    +
    +1 Function failed
    + +
    +
    + +
    +
    + + + + + + + + + + + + + + + + + + +
    uint32_t __STREXH (uint16_t value,
    volatile uint16_t * addr 
    )
    +
    +
    +

    This function performs a exclusive STR command for 16 bit values [not for Cortex-M0 variants].

    +
    Parameters:
    + + + +
    [in]valueValue to store
    [in]*addrPointer to location
    +
    +
    +
    Returns:
    0 Function succeeded
    +
    +1 Function failed
    + +
    +
    + +
    +
    + + + + + + + + + + + + + + + + + + +
    uint32_t __STREXW (uint32_t value,
    volatile uint32_t * addr 
    )
    +
    +
    +

    This function performs a exclusive STR command for 32 bit values [not for Cortex-M0 variants].

    +
    Parameters:
    + + + +
    [in]valueValue to store
    [in]*addrPointer to location
    +
    +
    +
    Returns:
    0 Function succeeded
    +
    +1 Function failed
    + +
    +
    + +
    +
    + + + + + + + + + + + + + + + + + + +
    uint32_t __USAT (uint32_t value,
    uint32_t sat 
    )
    +
    +
    +

    This function saturates an unsigned value [not for Cortex-M0 variants].

    +
    Parameters:
    + + + +
    [in]valueValue to be saturated
    [in]satBit position to saturate to [0..31]
    +
    +
    +
    Returns:
    Saturated value
    + +
    +
    + +
    +
    + + + + + + + + +
    void __WFE (void )
    +
    +
    +

    Wait For Event is a hint instruction that permits the processor to enter a low-power state until an events occurs:

    +
      +
    • If the event register is 0, then WFE suspends execution until one of the following events occurs:
        +
      • An exception, unless masked by the exception mask registers or the current priority level.
        • +
      • An exception enters the Pending state, if SEVONPEND in the System Control Register is set.
        • +
      • A Debug Entry request, if Debug is enabled.
        • +
      • An event signaled by a peripheral or another processor in a multiprocessor system using the SEV instruction.
        • +
      +
      • +
    +
      +
    • If the event register is 1, then WFE clears it to 0 and returns immediately.
      • +
    + +
    +
    + +
    +
    + + + + + + + + +
    void __WFI (void )
    +
    +
    +

    WFI is a hint instruction that suspends execution until one of the following events occurs:

    +
      +
    • A non-masked interrupt occurs and is taken.
      • +
    • An interrupt masked by PRIMASK becomes pending.
      • +
    • A Debug Entry request.
      • +
    + +
    +
    +
    +
    + + + + + diff --git a/Libraries/CMSIS/Documentation/Core/html/group__intrinsic___s_i_m_d__gr.html b/Libraries/CMSIS/Documentation/Core/html/group__intrinsic___s_i_m_d__gr.html new file mode 100644 index 0000000..dc102cd --- /dev/null +++ b/Libraries/CMSIS/Documentation/Core/html/group__intrinsic___s_i_m_d__gr.html @@ -0,0 +1,3079 @@ + + + + +Intrinsic Functions for SIMD Instructions [only Cortex-M4] + + + + + + + + + + + + + +
    + +
    + + + + + + + + + + + +
    +
    CMSIS-CORE +  Version 3.01 +
    +
    CMSIS-CORE support for Cortex-M processor-based devices
    +
    +
    + +
    + +
    + + + +
    +
    + +
    +
    +
    + +
    +
    +
    +Functions
    +
    +
    Intrinsic Functions for SIMD Instructions [only Cortex-M4]
    +
    +
    + +

    Access to dedicated SIMD instructions. +More...

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +

    +Functions

    uint32_t __SADD8 (uint32_t val1, uint32_t val2)
     GE setting quad 8-bit signed addition.
    uint32_t __QADD8 (uint32_t val1, uint32_t val2)
     Q setting quad 8-bit saturating addition.
    uint32_t __SHADD8 (uint32_t val1, uint32_t val2)
     Quad 8-bit signed addition with halved results.
    uint32_t __UADD8 (uint32_t val1, uint32_t val2)
     GE setting quad 8-bit unsigned addition.
    uint32_t __UQADD8 (uint32_t val1, uint32_t val2)
     Quad 8-bit unsigned saturating addition.
    uint32_t __UHADD8 (uint32_t val1, uint32_t val2)
     Quad 8-bit unsigned addition with halved results.
    uint32_t __SSUB8 (uint32_t val1, uint32_t val2)
     GE setting quad 8-bit signed subtraction.
    uint32_t __QSUB8 (uint32_t val1, uint32_t val2)
     Q setting quad 8-bit saturating subtract.
    uint32_t __SHSUB8 (uint32_t val1, uint32_t val2)
     Quad 8-bit signed subtraction with halved results.
    uint32_t __USUB8 (uint32_t val1, uint32_t val2)
     GE setting quad 8-bit unsigned subtract.
    uint32_t __UQSUB8 (uint32_t val1, uint32_t val2)
     Quad 8-bit unsigned saturating subtraction.
    uint32_t __UHSUB8 (uint32_t val1, uint32_t val2)
     Quad 8-bit unsigned subtraction with halved results.
    uint32_t __SADD16 (uint32_t val1, uint32_t val2)
     GE setting dual 16-bit signed addition.
    uint32_t __QADD16 (uint32_t val1, uint32_t val2)
     Q setting dual 16-bit saturating addition.
    uint32_t __SHADD16 (uint32_t val1, uint32_t val2)
     Dual 16-bit signed addition with halved results.
    uint32_t __UADD16 (uint32_t val1, uint32_t val2)
     GE setting dual 16-bit unsigned addition.
    uint32_t __UQADD16 (uint32_t val1, uint32_t val2)
     Dual 16-bit unsigned saturating addition.
    uint32_t __UHADD16 (uint32_t val1, uint32_t val2)
     Dual 16-bit unsigned addition with halved results.
    uint32_t __SSUB16 (uint32_t val1, uint32_t val2)
     GE setting dual 16-bit signed subtraction.
    uint32_t __QSUB16 (uint32_t val1, uint32_t val2)
     Q setting dual 16-bit saturating subtract.
    uint32_t __SHSUB16 (uint32_t val1, uint32_t val2)
     Dual 16-bit signed subtraction with halved results.
    uint32_t __USUB16 (uint32_t val1, uint32_t val2)
     GE setting dual 16-bit unsigned subtract.
    uint32_t __UQSUB16 (uint32_t val1, uint32_t val2)
     Dual 16-bit unsigned saturating subtraction.
    uint32_t __UHSUB16 (uint32_t val1, uint32_t val2)
     Dual 16-bit unsigned subtraction with halved results.
    uint32_t __SASX (uint32_t val1, uint32_t val2)
     GE setting dual 16-bit addition and subtraction with exchange.
    uint32_t __QASX (uint32_t val1, uint32_t val2)
     Q setting dual 16-bit add and subtract with exchange.
    uint32_t __SHASX (uint32_t val1, uint32_t val2)
     Dual 16-bit signed addition and subtraction with halved results.
    uint32_t __UASX (uint32_t val1, uint32_t val2)
     GE setting dual 16-bit unsigned addition and subtraction with exchange.
    uint32_t __UQASX (uint32_t val1, uint32_t val2)
     Dual 16-bit unsigned saturating addition and subtraction with exchange.
    uint32_t __UHASX (uint32_t val1, uint32_t val2)
     Dual 16-bit unsigned addition and subtraction with halved results and exchange.
    uint32_t __SSAX (uint32_t val1, uint32_t val2)
     GE setting dual 16-bit signed subtraction and addition with exchange.
    uint32_t __QSAX (uint32_t val1, uint32_t val2)
     Q setting dual 16-bit subtract and add with exchange.
    uint32_t __SHSAX (uint32_t val1, uint32_t val2)
     Dual 16-bit signed subtraction and addition with halved results.
    uint32_t __USAX (uint32_t val1, uint32_t val2)
     GE setting dual 16-bit unsigned subtract and add with exchange.
    uint32_t __UQSAX (uint32_t val1, uint32_t val2)
     Dual 16-bit unsigned saturating subtraction and addition with exchange.
    uint32_t __UHSAX (uint32_t val1, uint32_t val2)
     Dual 16-bit unsigned subtraction and addition with halved results and exchange.
    uint32_t __USAD8 (uint32_t val1, uint32_t val2)
     Unsigned sum of quad 8-bit unsigned absolute difference.
    uint32_t __USADA8 (uint32_t val1, uint32_t val2, uint32_t val3)
     Unsigned sum of quad 8-bit unsigned absolute difference with 32-bit accumulate.
    uint32_t __SSAT16 (uint32_t val1, const uint32_t val2)
     Q setting dual 16-bit saturate.
    uint32_t __USAT16 (uint32_t val1, const uint32_t val2)
     Q setting dual 16-bit unsigned saturate.
    uint32_t __UXTB16 (uint32_t val)
     Dual extract 8-bits and zero-extend to 16-bits.
    uint32_t __UXTAB16 (uint32_t val1, uint32_t val2)
     Extracted 16-bit to 32-bit unsigned addition.
    uint32_t __SXTB16 (uint32_t val)
     Dual extract 8-bits and sign extend each to 16-bits.
    uint32_t __SXTAB16 (uint32_t val1, uint32_t val2)
     Dual extracted 8-bit to 16-bit signed addition.
    uint32_t __SMUAD (uint32_t val1, uint32_t val2)
     Q setting sum of dual 16-bit signed multiply.
    uint32_t __SMUADX (uint32_t val1, uint32_t val2)
     Q setting sum of dual 16-bit signed multiply with exchange.
    uint32_t __SMLAD (uint32_t val1, uint32_t val2, uint32_t val3)
     Q setting dual 16-bit signed multiply with single 32-bit accumulator.
    uint32_t __SMLADX (uint32_t val1, uint32_t val2, uint32_t val3)
     Q setting pre-exchanged dual 16-bit signed multiply with single 32-bit accumulator.
    uint64_t __SMLALD (uint32_t val1, uint32_t val2, uint64_t val3)
     Dual 16-bit signed multiply with single 64-bit accumulator.
    unsigned long long __SMLALDX (uint32_t val1, uint32_t val2, unsigned long long val3)
     Dual 16-bit signed multiply with exchange with single 64-bit accumulator.
    uint32_t __SMUSD (uint32_t val1, uint32_t val2)
     Dual 16-bit signed multiply returning difference.
    uint32_t __SMUSDX (uint32_t val1, uint32_t val2)
     Dual 16-bit signed multiply with exchange returning difference.
    uint32_t __SMLSD (uint32_t val1, uint32_t val2, uint32_t val3)
     Q setting dual 16-bit signed multiply subtract with 32-bit accumulate.
    uint32_t __SMLSDX (uint32_t val1, uint32_t val2, uint32_t val3)
     Q setting dual 16-bit signed multiply with exchange subtract with 32-bit accumulate.
    uint64_t __SMLSLD (uint32_t val1, uint32_t val2, uint64_t val3)
     Q setting dual 16-bit signed multiply subtract with 64-bit accumulate.
    unsigned long long __SMLSLDX (uint32_t val1, uint32_t val2, unsigned long long val3)
     Q setting dual 16-bit signed multiply with exchange subtract with 64-bit accumulate.
    uint32_t __SEL (uint32_t val1, uint32_t val2)
     Select bytes based on GE bits.
    uint32_t __QADD (uint32_t val1, uint32_t val2)
     Q setting saturating add.
    uint32_t __QSUB (uint32_t val1, uint32_t val2)
     Q setting saturating subtract.
    uint32_t __PKHBT (uint32_t val1, uint32_t val2, uint32_t val3)
     Halfword packing instruction. Combines bits[15:0] of val1 with bits[31:16] of val2 levitated with the val3.
    uint32_t __PKHTB (uint32_t val1, uint32_t val2, uint32_t val3)
     Halfword packing instruction. Combines bits[31:16] of val1 with bits[15:0] of val2 right-shifted with the val3.
    +

    Description

    +

    Single Instruction Multiple Data (SIMD) extensions are provided only for Cortex-M4 cores to simplify development of application software. SIMD extensions increase the processing capability without materially increasing the power consumption. The SIMD extensions are completely transparent to the operating system (OS), allowing existing OS ports to be used.

    +

    SIMD Features:

    +
      +
    • Simultaneous computation of 2x16-bit or 4x8-bit operands
      • +
    • Fractional arithmetic
      • +
    • User definable saturation modes (arbitrary word-width)
      • +
    • Dual 16x16 multiply-add/subtract 32x32 fractional MAC
      • +
    • Simultaneous 8/16-bit select operations
      • +
    • Performance up to 3.2 GOPS at 800MHz
      • +
    • Performance is achieved with a "near zero" increase in power consumption on a typical implementation
      • +
    +

    Examples:

    +

    Addition: Add two values using SIMD function

    +
    uint32_t add_halfwords(uint32_t val1, uint32_t val2)
+{
+  return __SADD16(val1, val2);
+}
+

    Subtraction: Subtract two values using SIMD function

    +
    uint32_t sub_halfwords(uint32_t val1, uint32_t val2)
+{
+  return __SSUB16(val1, val2);
+}
+

    Multiplication: Performing a multiplication using SIMD function

    +
    uint32_t dual_mul_add_products(uint32_t val1, uint32_t val2)
+{
+  return __SMUAD(val1, val2);
+}
+

    Function Documentation

    + +
    +
    + + + + + + + + + + + + + + + + + + + + + + + + +
    uint32_t __PKHBT (uint32_t val1,
    uint32_t val2,
    uint32_t val3 
    )
    +
    +
    +

    Combine a halfword from one register with a halfword from another register. The second argument can be left-shifted before extraction of the halfword. The registers PC and SP are not allowed as arguments. This instruction does not change the flags.

    +
    Parameters:
    + + + + +
    val1first 16-bit operands
    val2second 16-bit operands
    val3value for left-shifting val2. Value range [0..31].
    +
    +
    +
    Returns:
    the combination of halfwords.
    +
    Operation:
       res[15:0]  = val1[15:0]
+   res[31:16] = val2[31:16]<<val3 
+
    + +
    +
    + +
    +
    + + + + + + + + + + + + + + + + + + + + + + + + +
    uint32_t __PKHTB (uint32_t val1,
    uint32_t val2,
    uint32_t val3 
    )
    +
    +
    +

    Combines a halfword from one register with a halfword from another register. The second argument can be right-shifted before extraction of the halfword. The registers PC and SP are not allowed as arguments. This instruction does not change the flags.

    +
    Parameters:
    + + + + +
    val1second 16-bit operands
    val2first 16-bit operands
    val3value for right-shifting val2. Value range [1..32].
    +
    +
    +
    Returns:
    the combination of halfwords.
    +
    Operation:
       res[15:0]  = val2[15:0]>>val3
+   res[31:16] = val1[31:16] 
+
    + +
    +
    + +
    +
    + + + + + + + + + + + + + + + + + + +
    uint32_t __QADD (uint32_t val1,
    uint32_t val2 
    )
    +
    +
    +

    This function enables you to obtain the saturating add of two integers.
    + The Q bit is set if the operation saturates.

    +
    Parameters:
    + + + +
    val1first summand of the saturating add operation.
    val2second summand of the saturating add operation.
    +
    +
    +
    Returns:
    the saturating addition of val1 and val2.
    +
    Operation:
       res[31:0] = SAT(val1 + SAT(val2 * 2))
+
    + +
    +
    + +
    +
    + + + + + + + + + + + + + + + + + + +
    uint32_t __QADD16 (uint32_t val1,
    uint32_t val2 
    )
    +
    +
    +

    This function enables you to perform two 16-bit integer arithmetic additions in parallel, saturating the results to the 16-bit signed integer range -215 <= x <= 215 - 1.

    +
    Parameters:
    + + + +
    val1first two 16-bit summands.
    val2second two 16-bit summands.
    +
    +
    +
    Returns:
      +
    • the saturated addition of the low halfwords, in the low halfword of the return value.
      • +
    • the saturated addition of the high halfwords, in the high halfword of the return value.
      • +
    +
    +
    The returned results are saturated to the 16-bit signed integer range -215 <= x <= 215 - 1
    +
    Operation:
       res[15:0]  = val1[15:0]  + val2[15:0]
+   res[31:16] = val1[31:16] + val2[31:16]
+
    + +
    +
    + +
    +
    + + + + + + + + + + + + + + + + + + +
    uint32_t __QADD8 (uint32_t val1,
    uint32_t val2 
    )
    +
    +
    +

    This function enables you to perform four 8-bit integer additions, saturating the results to the 8-bit signed integer range -27 <= x <= 27 - 1.

    +
    Parameters:
    + + + +
    val1first four 8-bit summands.
    val2second four 8-bit summands.
    +
    +
    +
    Returns:
      +
    • the saturated addition of the first byte of each operand in the first byte of the return value.
      • +
    • the saturated addition of the second byte of each operand in the second byte of the return value.
      • +
    • the saturated addition of the third byte of each operand in the third byte of the return value.
      • +
    • the saturated addition of the fourth byte of each operand in the fourth byte of the return value.
      • +
    +
    +
    The returned results are saturated to the 16-bit signed integer range -27 <= x <= 27 - 1.
    +
    Operation:
       res[7:0]   = val1[7:0]   + val2[7:0] 
+   res[15:8]  = val1[15:8]  + val2[15:8] 
+   res[23:16] = val1[23:16] + val2[23:16] 
+   res[31:24] = val1[31:24] + val2[31:24]          
+
    + +
    +
    + +
    +
    + + + + + + + + + + + + + + + + + + +
    uint32_t __QASX (uint32_t val1,
    uint32_t val2 
    )
    +
    +
    +

    This function enables you to exchange the halfwords of the one operand, then add the high halfwords and subtract the low halfwords, saturating the results to the 16-bit signed integer range -215 <= x <= 215 - 1.

    +
    Parameters:
    + + + +
    val1first operand for the subtraction in the low halfword, and the first operand for the addition in the high halfword.
    val2second operand for the subtraction in the high halfword, and the second operand for the addition in the low halfword.
    +
    +
    +
    Returns:
      +
    • the saturated subtraction of the high halfword in the second operand from the low halfword in the first operand, in the low halfword of the return value.
      • +
    • the saturated addition of the high halfword in the first operand and the low halfword in the second operand, in the high halfword of the return value.
      • +
    +
    +
    The returned results are saturated to the 16-bit signed integer range -215 <= x <= 215 - 1.
    +
    Operation:
       res[15:0]  = val1[15:0]  - val2[31:16]   
+   res[31:16] = val1[31:16] + val2[15:0]  
+
    + +
    +
    + +
    +
    + + + + + + + + + + + + + + + + + + +
    uint32_t __QSAX (uint32_t val1,
    uint32_t val2 
    )
    +
    +
    +

    This function enables you to exchange the halfwords of one operand, then subtract the high halfwords and add the low halfwords, saturating the results to the 16-bit signed integer range -215 <= x <= 215 - 1.

    +
    Parameters:
    + + + +
    val1first operand for the addition in the low halfword, and the first operand for the subtraction in the high halfword.
    val2second operand for the addition in the high halfword, and the second operand for the subtraction in the low halfword.
    +
    +
    +
    Returns:
      +
    • the saturated addition of the low halfword of the first operand and the high halfword of the second operand, in the low halfword of the return value.
      • +
    • the saturated subtraction of the low halfword of the second operand from the high halfword of the first operand, in the high halfword of the return value.
      • +
    +
    +
    The returned results are saturated to the 16-bit signed integer range -215 <= x <= 215 - 1.
    +
    Operation:
       res[15:0]  = val1[15:0]  + val2[31:16]
+   res[31:16] = val1[31:16] - val2[15:0] 
+
    + +
    +
    + +
    +
    + + + + + + + + + + + + + + + + + + +
    uint32_t __QSUB (uint32_t val1,
    uint32_t val2 
    )
    +
    +
    +

    This function enables you to obtain the saturating subtraction of two integers.
    + The Q bit is set if the operation saturates.

    +
    Parameters:
    + + + +
    val1minuend of the saturating subtraction operation.
    val2subtrahend of the saturating subtraction operation.
    +
    +
    +
    Returns:
    the saturating subtraction of val1 and val2.
    +
    Operation:
       res[31:0] = SAT(val1 - SAT(val2 * 2))
+
    + +
    +
    + +
    +
    + + + + + + + + + + + + + + + + + + +
    uint32_t __QSUB16 (uint32_t val1,
    uint32_t val2 
    )
    +
    +
    +

    This function enables you to perform two 16-bit integer subtractions, saturating the results to the 16-bit signed integer range -215 <= x <= 215 - 1.

    +
    Parameters:
    + + + +
    val1first two 16-bit operands.
    val2second two 16-bit operands.
    +
    +
    +
    Returns:
      +
    • the saturated subtraction of the low halfword in the second operand from the low halfword in the first operand, in the low halfword of the returned result.
      • +
    • the saturated subtraction of the high halfword in the second operand from the high halfword in the first operand, in the high halfword of the returned result.
      • +
    +
    +
    The returned results are saturated to the 16-bit signed integer range -215 <= x <= 215 - 1.
    +
    Operation:
       res[15:0]  = val1[15:0]  - val2[15:0]
+   res[31:16] = val1[31:16] - val2[31:16]
+
    + +
    +
    + +
    +
    + + + + + + + + + + + + + + + + + + +
    uint32_t __QSUB8 (uint32_t val1,
    uint32_t val2 
    )
    +
    +
    +

    This function enables you to perform four 8-bit integer subtractions, saturating the results to the 8-bit signed integer range -27 <= x <= 27 - 1.

    +
    Parameters:
    + + + +
    val1first four 8-bit operands.
    val2second four 8-bit operands.
    +
    +
    +
    Returns:
      +
    • the subtraction of the first byte in the second operand from the first byte in the first operand, in the first bytes of the return value.
      • +
    • the subtraction of the second byte in the second operand from the second byte in the first operand, in the second byte of the return value.
      • +
    • the subtraction of the third byte in the second operand from the third byte in the first operand, in the third byte of the return value.
      • +
    • the subtraction of the fourth byte in the second operand from the fourth byte in the first operand, in the fourth byte of the return value.
      • +
    +
    +
    The returned results are saturated to the 8-bit signed integer range -27 <= x <= 27 - 1.
    +
    Operation:
       res[7:0]   = val1[7:0]   - val2[7:0] 
+   res[15:8]  = val1[15:8]  - val2[15:8]
+   res[23:16] = val1[23:16] - val2[23:16]
+   res[31:24] = val1[31:24] - val2[31:24]
+
    + +
    +
    + +
    +
    + + + + + + + + + + + + + + + + + + +
    uint32_t __SADD16 (uint32_t val1,
    uint32_t val2 
    )
    +
    +
    +

    This function enables you to perform two 16-bit signed integer additions.
    + The GE bits in the APSR are set according to the results of the additions.

    +
    Parameters:
    + + + +
    val1first two 16-bit summands.
    val2second two 16-bit summands.
    +
    +
    +
    Returns:
      +
    • the addition of the low halfwords in the low halfword of the return value.
      • +
    • the addition of the high halfwords in the high halfword of the return value.
      • +
    +
    +
    Each bit in APSR.GE is set or cleared for each byte in the return value, depending on the results of the operation.
    +
    If res is the return value, then:
      +
    • if res[15:0] >= 0 then APSR.GE[1:0] = 11 else 00
      • +
    • if res[31:16] >= 0 then APSR.GE[3:2] = 11 else 00
      • +
    +
    +
    Operation:
       res[15:0]  = val1[15:0]  + val2[15:0]
+   res[31:16] = val1[31:16] + val2[31:16]
+
    + +
    +
    + +
    +
    + + + + + + + + + + + + + + + + + + +
    uint32_t __SADD8 (uint32_t val1,
    uint32_t val2 
    )
    +
    +
    +

    This function performs four 8-bit signed integer additions. The GE bits of the APSR are set according to the results of the additions.

    +
    Parameters:
    + + + +
    val1first four 8-bit summands.
    val2second four 8-bit summands.
    +
    +
    +
    Returns:
      +
    • the addition of the first bytes from each operand, in the first byte of the return value.
      • +
    • the addition of the second bytes of each operand, in the second byte of the return value.
      • +
    • the addition of the third bytes of each operand, in the third byte of the return value.
      • +
    • the addition of the fourth bytes of each operand, in the fourth byte of the return value.
      • +
    +
    +
    Each bit in APSR.GE is set or cleared for each byte in the return value, depending on the results of the operation.
    +
    If res is the return value, then:
      +
    • if res[7:0] >= 0 then APSR.GE[0] = 1 else 0
      • +
    • if res[15:8] >= 0 then APSR.GE[1] = 1 else 0
      • +
    • if res[23:16] >= 0 then APSR.GE[2] = 1 else 0
      • +
    • if res[31:24] >= 0 then APSR.GE[3] = 1 else 0
      • +
    +
    +
    Operation:
       res[7:0]   = val1[7:0]   + val2[7:0] 
+   res[15:8]  = val1[15:8]  + val2[15:8] 
+   res[23:16] = val1[23:16] + val2[23:16] 
+   res[31:24] = val1[31:24] + val2[31:24]          
+
    + +
    +
    + +
    +
    + + + + + + + + + + + + + + + + + + +
    uint32_t __SASX (uint32_t val1,
    uint32_t val2 
    )
    +
    +
    +

    This function inserts an SASX instruction into the instruction stream generated by the compiler. It enables you to exchange the halfwords of the second operand, add the high halfwords and subtract the low halfwords.
    + The GE bits in the APRS are set according to the results.

    +
    Parameters:
    + + + +
    val1first operand for the subtraction in the low halfword, and the first operand for the addition in the high halfword.
    val2second operand for the subtraction in the high halfword, and the second operand for the addition in the low halfword.
    +
    +
    +
    Returns:
      +
    • the subtraction of the high halfword in the second operand from the low halfword in the first operand, in the low halfword of the return value.
      • +
    • the addition of the high halfword in the first operand and the low halfword in the second operand, in the high halfword of the return value.
      • +
    +
    +
    Each bit in APSR.GE is set or cleared for each byte in the return value, depending on the results of the operation.
    +
    If res is the return value, then:
      +
    • if res[15:0] >= 0 then APSR.GE[1:0] = 11 else 00
      • +
    • if res[31:16] >= 0 then APSR.GE[3:2] = 11 else 00
      • +
    +
    +
    Operation:
       res[15:0]  = val1[15:0]  - val2[31:16]   
+   res[31:16] = val1[31:16] + val2[15:0]  
+
    + +
    +
    + +
    +
    + + + + + + + + + + + + + + + + + + +
    uint32_t __SEL (uint32_t val1,
    uint32_t val2 
    )
    +
    +
    +

    This function inserts a SEL instruction into the instruction stream generated by the compiler. It enables you to select bytes from the input parameters, whereby the bytes that are selected depend upon the results of previous SIMD instruction function. The results of previous SIMD instruction function are represented by the Greater than or Equal flags in the Application Program Status Register (APSR). The __SEL function works equally well on both halfword and byte operand function results. This is because halfword operand operations set two (duplicate) GE bits per value.

    +
    Parameters:
    + + + +
    val1four selectable 8-bit values.
    val2four selectable 8-bit values.
    +
    +
    +
    Returns:
    The function selects bytes from the input parameters and returns them in the return value, res, according to the following criteria:
      +
    • if APSR.GE[0] == 1 then res[7:0] = val1[7:0] else res[7:0] = val2[7:0]
      • +
    • if APSR.GE[1] == 1 then res[15:8] = val1[15:8] else res[15:8] = val2[15:8]
      • +
    • if APSR.GE[2] == 1 then res[23:16] = val1[23:16] else res[23:16] = val2[23:16]
      • +
    • if APSR.GE[3] == 1 then res[31;24] = val1[31:24] else res = val2[31:24]
      • +
    +
    + +
    +
    + +
    +
    + + + + + + + + + + + + + + + + + + +
    uint32_t __SHADD16 (uint32_t val1,
    uint32_t val2 
    )
    +
    +
    +

    This function enables you to perform two signed 16-bit integer additions, halving the results.

    +
    Parameters:
    + + + +
    val1first two 16-bit summands.
    val2second two 16-bit summands.
    +
    +
    +
    Returns:
      +
    • the halved addition of the low halfwords, in the low halfword of the return value.
      • +
    • the halved addition of the high halfwords, in the high halfword of the return value.
      • +
    +
    +
    Operation:
       res[15:0]  = val1[15:0]  + val2[15:0]  >> 1
+   res[31:16] = val1[31:16] + val2[31:16] >> 1
+
    + +
    +
    + +
    +
    + + + + + + + + + + + + + + + + + + +
    uint32_t __SHADD8 (uint32_t val1,
    uint32_t val2 
    )
    +
    +
    +

    This function enables you to perform four signed 8-bit integer additions, halving the results.

    +
    Parameters:
    + + + +
    val1first four 8-bit summands.
    val2second four 8-bit summands.
    +
    +
    +
    Returns:
      +
    • the halved addition of the first bytes from each operand, in the first byte of the return value.
      • +
    • the halved addition of the second bytes from each operand, in the second byte of the return value.
      • +
    • the halved addition of the third bytes from each operand, in the third byte of the return value.
      • +
    • the halved addition of the fourth bytes from each operand, in the fourth byte of the return value.
      • +
    +
    +
    Operation:
       res[7:0]   = val1[7:0]   + val2[7:0]  >> 1
+   res[15:8]  = val1[15:8]  + val2[15:8] >> 1
+   res[23:16] = val1[23:16] + val2[23:16] >> 1
+   res[31:24] = val1[31:24] + val2[31:24] >> 1         
+
    + +
    +
    + +
    +
    + + + + + + + + + + + + + + + + + + +
    uint32_t __SHASX (uint32_t val1,
    uint32_t val2 
    )
    +
    +
    +

    This function enables you to exchange the two halfwords of one operand, perform one signed 16-bit integer addition and one signed 16-bit subtraction, and halve the results.

    +
    Parameters:
    + + + +
    val1first 16-bit operands.
    val2second 16-bit operands.
    +
    +
    +
    Returns:
      +
    • the halved subtraction of the high halfword in the second operand from the low halfword in the first operand, in the low halfword of the return value.
      • +
    • the halved subtraction of the low halfword in the second operand from the high halfword in the first operand, in the high halfword of the return value.
      • +
    +
    +
    Operation:
       res[15:0]  = (val1[15:0]  - val2[31:16]) >> 1  
+   res[31:16] = (val1[31:16] - val2[15:0] ) >> 1
+
    + +
    +
    + +
    +
    + + + + + + + + + + + + + + + + + + +
    uint32_t __SHSAX (uint32_t val1,
    uint32_t val2 
    )
    +
    +
    +

    This function enables you to exchange the two halfwords of one operand, perform one signed 16-bit integer subtraction and one signed 16-bit addition, and halve the results.

    +
    Parameters:
    + + + +
    val1first 16-bit operands.
    val2second 16-bit operands.
    +
    +
    +
    Returns:
      +
    • the halved addition of the low halfword in the first operand and the high halfword in the second operand, in the low halfword of the return value.
      • +
    • the halved subtraction of the low halfword in the second operand from the high halfword in the first operand, in the high halfword of the return value.
      • +
    +
    +
    Operation:
       res[15:0]  = (val1[15:0]  + val2[31:16]) >> 1
+   res[31:16] = (val1[31:16] - val2[15:0] ) >> 1
+
    + +
    +
    + +
    +
    + + + + + + + + + + + + + + + + + + +
    uint32_t __SHSUB16 (uint32_t val1,
    uint32_t val2 
    )
    +
    +
    +

    This function enables you to perform two signed 16-bit integer subtractions, halving the results.

    +
    Parameters:
    + + + +
    val1first two 16-bit operands.
    val2second two 16-bit operands.
    +
    +
    +
    Returns:
      +
    • the halved subtraction of the low halfword in the second operand from the low halfword in the first operand, in the low halfword of the returned result.
      • +
    • the halved subtraction of the high halfword in the second operand from the high halfword in the first operand, in the high halfword of the returned result.
      • +
    +
    +
    Operation:
       res[15:0]  = val1[15:0]  - val2[15:0]   >> 1
+   res[31:16] = val1[31:16] - val2[31:16]  >> 1
+
    + +
    +
    + +
    +
    + + + + + + + + + + + + + + + + + + +
    uint32_t __SHSUB8 (uint32_t val1,
    uint32_t val2 
    )
    +
    +
    +

    This function enables you to perform four signed 8-bit integer subtractions, halving the results.

    +
    Parameters:
    + + + +
    val1first four 8-bit operands.
    val2second four 8-bit operands.
    +
    +
    +
    Returns:
      +
    • the halved subtraction of the first byte in the second operand from the first byte in the first operand, in the first bytes of the return value.
      • +
    • the halved subtraction of the second byte in the second operand from the second byte in the first operand, in the second byte of the return value.
      • +
    • the halved subtraction of the third byte in the second operand from the third byte in the first operand, in the third byte of the return value.
      • +
    • the halved subtraction of the fourth byte in the second operand from the fourth byte in the first operand, in the fourth byte of the return value.
      • +
    +
    +
    Operation:
       res[7:0]   = val1[7:0]   - val2[7:0]   >> 1
+   res[15:8]  = val1[15:8]  - val2[15:8]  >> 1
+   res[23:16] = val1[23:16] - val2[23:16] >> 1
+   res[31:24] = val1[31:24] - val2[31:24] >> 1
+
    + +
    +
    + +
    +
    + + + + + + + + + + + + + + + + + + + + + + + + +
    uint32_t __SMLAD (uint32_t val1,
    uint32_t val2,
    uint32_t val3 
    )
    +
    +
    +

    This function enables you to perform two signed 16-bit multiplications, adding both results to a 32-bit accumulate operand.
    + The Q bit is set if the addition overflows. Overflow cannot occur during the multiplications.

    +
    Parameters:
    + + + + +
    val1first 16-bit operands for each multiplication.
    val2second 16-bit operands for each multiplication.
    val3accumulate value.
    +
    +
    +
    Returns:
    the product of each multiplication added to the accumulate value, as a 32-bit integer.
    +
    Operation:
       p1 = val1[15:0]  * val2[15:0]
+   p2 = val1[31:16] * val2[31:16]
+   res[31:0] = p1 + p2 + val3[31:0]
+
    + +
    +
    + +
    +
    + + + + + + + + + + + + + + + + + + + + + + + + +
    uint32_t __SMLADX (uint32_t val1,
    uint32_t val2,
    uint32_t val3 
    )
    +
    +
    +

    This function enables you to perform two signed 16-bit multiplications with exchanged halfwords of the second operand, adding both results to a 32-bit accumulate operand.
    + The Q bit is set if the addition overflows. Overflow cannot occur during the multiplications.

    +
    Parameters:
    + + + + +
    val1first 16-bit operands for each multiplication.
    val2second 16-bit operands for each multiplication.
    val3accumulate value.
    +
    +
    +
    Returns:
    the product of each multiplication with exchanged halfwords of the second operand added to the accumulate value, as a 32-bit integer.
    +
    Operation:
       p1 = val1[15:0]  * val2[31:16]
+   p2 = val1[31:16] * val2[15:0]
+   res[31:0] = p1 + p2 + val3[31:0]
+
    + +
    +
    + +
    +
    + + + + + + + + + + + + + + + + + + + + + + + + +
    uint64_t __SMLALD (uint32_t val1,
    uint32_t val2,
    uint64_t val3 
    )
    +
    +
    +

    This function enables you to perform two signed 16-bit multiplications, adding both results to a 64-bit accumulate operand. Overflow is only possible as a result of the 64-bit addition. This overflow is not detected if it occurs. Instead, the result wraps around modulo264.

    +
    Parameters:
    + + + + +
    val1first 16-bit operands for each multiplication.
    val2second 16-bit operands for each multiplication.
    val3accumulate value.
    +
    +
    +
    Returns:
    the product of each multiplication added to the accumulate value.
    +
    Operation:
       p1 = val1[15:0]  * val2[15:0]
+   p2 = val1[31:16] * val2[31:16]
+   sum = p1 + p2 + val3[63:32][31:0]
+   res[63:32] = sum[63:32]
+   res[31:0]  = sum[31:0]
+
    + +
    +
    + +
    +
    + + + + + + + + + + + + + + + + + + + + + + + + +
    unsigned long long __SMLALDX (uint32_t val1,
    uint32_t val2,
    unsigned long long val3 
    )
    +
    +
    +

    This function enables you to exchange the halfwords of the second operand, and perform two signed 16-bit multiplications, adding both results to a 64-bit accumulate operand. Overflow is only possible as a result of the 64-bit addition. This overflow is not detected if it occurs. Instead, the result wraps around modulo264.

    +
    Parameters:
    + + + + +
    val1first 16-bit operands for each multiplication.
    val2second 16-bit operands for each multiplication.
    val3accumulate value.
    +
    +
    +
    Returns:
    the product of each multiplication added to the accumulate value.
    +
    Operation:
       p1 = val1[15:0]  * val2[31:16]
+   p2 = val1[31:16] * val2[15:0]
+   sum = p1 + p2 + val3[63:32][31:0]
+   res[63:32] = sum[63:32]
+   res[31:0] = sum[31:0]
+
    + +
    +
    + +
    +
    + + + + + + + + + + + + + + + + + + + + + + + + +
    uint32_t __SMLSD (uint32_t val1,
    uint32_t val2,
    uint32_t val3 
    )
    +
    +
    +

    This function enables you to perform two 16-bit signed multiplications, take the difference of the products, subtracting the high halfword product from the low halfword product, and add the difference to a 32-bit accumulate operand.
    + The Q bit is set if the accumulation overflows. Overflow cannot occur during the multiplications or the subtraction.

    +
    Parameters:
    + + + + +
    val1first 16-bit operands for each multiplication.
    val2second 16-bit operands for each multiplication.
    val3accumulate value.
    +
    +
    +
    Returns:
    the difference of the product of each multiplication, added to the accumulate value.
    +
    Operation:
       p1 = val1[15:0]  * val2[15:0]
+   p2 = val1[31:16] * val2[31:16]
+   res[31:0] = p1 - p2 + val3[31:0]
+
    + +
    +
    + +
    +
    + + + + + + + + + + + + + + + + + + + + + + + + +
    uint32_t __SMLSDX (uint32_t val1,
    uint32_t val2,
    uint32_t val3 
    )
    +
    +
    +

    This function enables you to exchange the halfwords in the second operand, then perform two 16-bit signed multiplications. The difference of the products is added to a 32-bit accumulate operand.
    + The Q bit is set if the addition overflows. Overflow cannot occur during the multiplications or the subtraction.

    +
    Parameters:
    + + + + +
    val1first 16-bit operands for each multiplication.
    val2second 16-bit operands for each multiplication.
    val3accumulate value.
    +
    +
    +
    Returns:
    the difference of the product of each multiplication, added to the accumulate value.
    +
    Operation:
       p1 = val1[15:0]  * val2[31:16]
+   p2 = val1[31:16] * val2[15:0]
+   res[31:0] = p1 - p2 + val3[31:0]
+
    + +
    +
    + +
    +
    + + + + + + + + + + + + + + + + + + + + + + + + +
    uint64_t __SMLSLD (uint32_t val1,
    uint32_t val2,
    uint64_t val3 
    )
    +
    +
    +

    This function It enables you to perform two 16-bit signed multiplications, take the difference of the products, subtracting the high halfword product from the low halfword product, and add the difference to a 64-bit accumulate operand. Overflow cannot occur during the multiplications or the subtraction. Overflow can occur as a result of the 64-bit addition, and this overflow is not detected. Instead, the result wraps round to modulo264.

    +
    Parameters:
    + + + + +
    val1first 16-bit operands for each multiplication.
    val2second 16-bit operands for each multiplication.
    val3accumulate value.
    +
    +
    +
    Returns:
    the difference of the product of each multiplication, added to the accumulate value.
    +
    Operation:
       p1 = val1[15:0]  * val2[15:0]
+   p2 = val1[31:16] * val2[31:16]
+   res[63:0] = p1 - p2 + val3[63:0]
+
    + +
    +
    + +
    +
    + + + + + + + + + + + + + + + + + + + + + + + + +
    unsigned long long __SMLSLDX (uint32_t val1,
    uint32_t val2,
    unsigned long long val3 
    )
    +
    +
    +

    This function enables you to exchange the halfwords of the second operand, perform two 16-bit multiplications, adding the difference of the products to a 64-bit accumulate operand. Overflow cannot occur during the multiplications or the subtraction. Overflow can occur as a result of the 64-bit addition, and this overflow is not detected. Instead, the result wraps round to modulo264.

    +
    Parameters:
    + + + + +
    val1first 16-bit operands for each multiplication.
    val2second 16-bit operands for each multiplication.
    val3accumulate value.
    +
    +
    +
    Returns:
    the difference of the product of each multiplication, added to the accumulate value.
    +
    Operation:
       p1 = val1[15:0]  * val2[31:16]
+   p2 = val1[31:16] * val2[15:0]
+   res[63:0] = p1 - p2 + val3[63:0]
+
    + +
    +
    + +
    +
    + + + + + + + + + + + + + + + + + + +
    uint32_t __SMUAD (uint32_t val1,
    uint32_t val2 
    )
    +
    +
    +

    This function enables you to perform two 16-bit signed multiplications, adding the products together.
    + The Q bit is set if the addition overflows.

    +
    Parameters:
    + + + +
    val1first 16-bit operands for each multiplication.
    val2second 16-bit operands for each multiplication.
    +
    +
    +
    Returns:
    the sum of the products of the two 16-bit signed multiplications.
    +
    Operation:
       p1 = val1[15:0]  * val2[15:0]
+   p2 = val1[31:16] * val2[31:16]
+   res[31:0] = p1 + p2
+
    + +
    +
    + +
    +
    + + + + + + + + + + + + + + + + + + +
    uint32_t __SMUADX (uint32_t val1,
    uint32_t val2 
    )
    +
    +
    +

    This function enables you to perform two 16-bit signed multiplications with exchanged halfwords of the second operand, adding the products together.
    + The Q bit is set if the addition overflows.

    +
    Parameters:
    + + + +
    val1first 16-bit operands for each multiplication.
    val2second 16-bit operands for each multiplication.
    +
    +
    +
    Returns:
    the sum of the products of the two 16-bit signed multiplications with exchanged halfwords of the second operand.
    +
    Operation:
       p1 = val1[15:0]  * val2[31:16]
+   p2 = val1[31:16] * val2[15:0]
+   res[31:0] = p1 + p2
+
    + +
    +
    + +
    +
    + + + + + + + + + + + + + + + + + + +
    uint32_t __SMUSD (uint32_t val1,
    uint32_t val2 
    )
    +
    +
    +

    This function enables you to perform two 16-bit signed multiplications, taking the difference of the products by subtracting the high halfword product from the low halfword product.

    +
    Parameters:
    + + + +
    val1first 16-bit operands for each multiplication.
    val2second 16-bit operands for each multiplication.
    +
    +
    +
    Returns:
    the difference of the products of the two 16-bit signed multiplications.
    +
    Operation:
       p1 = val1[15:0]  * val2[15:0]
+   p2 = val1[31:16] * val2[31:16]
+   res[31:0] = p1 - p2
+
    + +
    +
    + +
    +
    + + + + + + + + + + + + + + + + + + +
    uint32_t __SMUSDX (uint32_t val1,
    uint32_t val2 
    )
    +
    +
    +

    This function enables you to perform two 16-bit signed multiplications, subtracting one of the products from the other. The halfwords of the second operand are exchanged before performing the arithmetic. This produces top * bottom and bottom * top multiplication.

    +
    Parameters:
    + + + +
    val1first 16-bit operands for each multiplication.
    val2second 16-bit operands for each multiplication.
    +
    +
    +
    Returns:
    the difference of the products of the two 16-bit signed multiplications.
    +
    Operation:
       p1 = val1[15:0]  * val2[31:16]
+   p2 = val1[31:16] * val2[15:0]
+   res[31:0] = p1 - p2
+
    + +
    +
    + +
    +
    + + + + + + + + + + + + + + + + + + +
    uint32_t __SSAT16 (uint32_t val1,
    const uint32_t val2 
    )
    +
    +
    +

    This function enables you to saturate two signed 16-bit values to a selected signed range.
    + The Q bit is set if either operation saturates.

    +
    Parameters:
    + + + +
    val1two signed 16-bit values to be saturated.
    val2bit position for saturation, an integral constant expression in the range 1 to 16.
    +
    +
    +
    Returns:
    the sum of the absolute differences of the following bytes, added to the accumulation value:
      +
    • the signed saturation of the low halfword in val1, saturated to the bit position specified in val2 and returned in the low halfword of the return value.
      • +
    • the signed saturation of the high halfword in val1, saturated to the bit position specified in val2 and returned in the high halfword of the return value.
      • +
    +
    +
    Operation:
       Saturate halfwords in val1 to the signed range specified by the bit position in val2
+
    + +
    +
    + +
    +
    + + + + + + + + + + + + + + + + + + +
    uint32_t __SSAX (uint32_t val1,
    uint32_t val2 
    )
    +
    +
    +

    This function enables you to exchange the two halfwords of one operand and perform one 16-bit integer subtraction and one 16-bit addition.
    + The GE bits in the APSR are set according to the results.

    +
    Parameters:
    + + + +
    val1first operand for the addition in the low halfword, and the first operand for the subtraction in the high halfword.
    val2second operand for the addition in the high halfword, and the second operand for the subtraction in the low halfword.
    +
    +
    +
    Returns:
      +
    • the addition of the low halfword in the first operand and the high halfword in the second operand, in the low halfword of the return value.
      • +
    • the subtraction of the low halfword in the second operand from the high halfword in the first operand, in the high halfword of the return value.
      • +
    +
    +
    Each bit in APSR.GE is set or cleared for each byte in the return value, depending on the results of the operation.
    +
    If res is the return value, then:
      +
    • if res[15:0] >= 0 then APSR.GE[1:0] = 11 else 00
      • +
    • if res[31:16] >= 0 then APSR.GE[3:2] = 11 else 00
      • +
    +
    +
    Operation:
       res[15:0]  = val1[15:0]  + val2[31:16]
+   res[31:16] = val1[31:16] - val2[15:0] 
+
    + +
    +
    + +
    +
    + + + + + + + + + + + + + + + + + + +
    uint32_t __SSUB16 (uint32_t val1,
    uint32_t val2 
    )
    +
    +
    +

    This function enables you to perform two 16-bit signed integer subtractions.
    + The GE bits in the APSR are set according to the results.

    +
    Parameters:
    + + + +
    val1first two 16-bit operands of each subtraction.
    val2second two 16-bit operands of each subtraction.
    +
    +
    +
    Returns:
      +
    • the subtraction of the low halfword in the second operand from the low halfword in the first operand, in the low halfword of the return value.
      • +
    • the subtraction of the high halfword in the second operand from the high halfword in the first operand, in the high halfword of the return value.
      • +
    +
    +
    Each bit in APSR.GE is set or cleared for each byte in the return value, depending on the results of the operation.
    +
    If
      +
    • res is the return value, then:
      • +
    • if res[15:0] >= 0 then APSR.GE[1:0] = 11 else 00
      • +
    • if res[31:16] >= 0 then APSR.GE[3:2] = 11 else 00
      • +
    +
    +
    Operation:
       res[15:0]  = val1[15:0]  - val2[15:0]
+   res[31:16] = val1[31:16] - val2[31:16]
+
    + +
    +
    + +
    +
    + + + + + + + + + + + + + + + + + + +
    uint32_t __SSUB8 (uint32_t val1,
    uint32_t val2 
    )
    +
    +
    +

    This function enables you to perform four 8-bit signed integer subtractions.
    + The GE bits in the APSR are set according to the results.

    +
    Parameters:
    + + + +
    val1first four 8-bit operands of each subtraction.
    val2second four 8-bit operands of each subtraction.
    +
    +
    +
    Returns:
      +
    • the subtraction of the first byte in the second operand from the first byte in the first operand, in the first bytes of the return value.
      • +
    • the subtraction of the second byte in the second operand from the second byte in the first operand, in the second byte of the return value.
      • +
    • the subtraction of the third byte in the second operand from the third byte in the first operand, in the third byte of the return value.
      • +
    • the subtraction of the fourth byte in the second operand from the fourth byte in the first operand, in the fourth byte of the return value.
      • +
    +
    +
    Each bit in APSR.GE is set or cleared for each byte in the return value, depending on
    the results of the operation.
    +
    If res is the return value, then:
      +
    • if res[8:0] >= 0 then APSR.GE[0] = 1 else 0
      • +
    • if res[15:8] >= 0 then APSR.GE[1] = 1 else 0
      • +
    • if res[23:16] >= 0 then APSR.GE[2] = 1 else 0
      • +
    • if res[31:24] >= 0 then APSR.GE[3] = 1 else 0
      • +
    +
    +
    Operation:
       res[7:0]   = val1[7:0]   - val2[7:0] 
+   res[15:8]  = val1[15:8]  - val2[15:8]
+   res[23:16] = val1[23:16] - val2[23:16]
+   res[31:24] = val1[31:24] - val2[31:24]
+
    + +
    +
    + +
    +
    + + + + + + + + + + + + + + + + + + +
    uint32_t __SXTAB16 (uint32_t val1,
    uint32_t val2 
    )
    +
    +
    +

    This function enables you to extract two 8-bit values from the second operand (at bit positions [7:0] and [23:16]), sign-extend them to 16-bits each, and add the results to the first operand.

    +
    Parameters:
    + + + +
    val1values added to the zero-extended to 16-bit values.
    val2two 8-bit values to be extracted and zero-extended.
    +
    +
    +
    Returns:
    the addition of val1 and val2, where the 8-bit values in val2[7:0] and val2[23:16] have been extracted and sign-extended prior to the addition.
    +
    Operation:
       res[15:0]  = val1[15:0]  + SignExtended(val2[7:0])
+   res[31:16] = val1[31:16] + SignExtended(val2[23:16])
+
    + +
    +
    + +
    +
    + + + + + + + + +
    uint32_t __SXTB16 (uint32_t val)
    +
    +
    +

    This function enables you to extract two 8-bit values from an operand and sign-extend them to 16 bits each.

    +
    Parameters:
    + + +
    valtwo 8-bit values in val[7:0] and val[23:16] to be sign-extended.
    +
    +
    +
    Returns:
    the 8-bit values sign-extended to 16-bit values.
      +
    • sign-extended value of val[7:0] in the low halfword of the return value.
      • +
    • sign-extended value of val[23:16] in the high halfword of the return value.
      • +
    +
    +
    Operation:
       res[15:0]  = SignExtended(val[7:0]
+   res[31:16] = SignExtended(val[23:16]
+
    + +
    +
    + +
    +
    + + + + + + + + + + + + + + + + + + +
    uint32_t __UADD16 (uint32_t val1,
    uint32_t val2 
    )
    +
    +
    +

    This function enables you to perform two 16-bit unsigned integer additions.
    + The GE bits in the APSR are set according to the results.

    +
    Parameters:
    + + + +
    val1first two 16-bit summands for each addition.
    val2second two 16-bit summands for each addition.
    +
    +
    +
    Returns:
      +
    • the addition of the low halfwords in each operand, in the low halfword of the return value.
      • +
    • the addition of the high halfwords in each operand, in the high halfword of the return value.
      • +
    +
    +
    Each bit in APSR.GE is set or cleared for each byte in the return value, depending on the results of the operation.
    +
    If res is the return value, then:
      +
    • if res[15:0] >= 0x10000 then APSR.GE[0] = 11 else 00
      • +
    • if res[31:16] >= 0x10000 then APSR.GE[1] = 11 else 00
      • +
    +
    +
    Operation:
       res[15:0]  = val1[15:0]  + val2[15:0] 
+   res[31:16] = val1[31:16] + val2[31:16]
+
    + +
    +
    + +
    +
    + + + + + + + + + + + + + + + + + + +
    uint32_t __UADD8 (uint32_t val1,
    uint32_t val2 
    )
    +
    +
    +

    This function enables you to perform four unsigned 8-bit integer additions. The GE bits of the APSR are set according to the results.

    +
    Parameters:
    + + + +
    val1first four 8-bit summands for each addition.
    val2second four 8-bit summands for each addition.
    +
    +
    +
    Returns:
      +
    • the halved addition of the first bytes from each operand, in the first byte of the return value.
      • +
    • the halved addition of the second bytes from each operand, in the second byte of the return value.
      • +
    • the halved addition of the third bytes from each operand, in the third byte of the return value.
      • +
    • the halved addition of the fourth bytes from each operand, in the fourth byte of the return value.
      • +
    +
    +
    Each bit in APSR.GE is set or cleared for each byte in the return value, depending on the results of the operation.
    +
    If res is the return value, then:
      +
    • if res[7:0] >= 0x100 then APSR.GE[0] = 1 else 0
      • +
    • if res[15:8] >= 0x100 then APSR.GE[1] = 1 else 0
      • +
    • if res[23:16] >= 0x100 then APSR.GE[2] = 1 else 0
      • +
    • if res[31:24] >= 0x100 then APSR.GE[3] = 1 else 0
      • +
    +
    +
    Operation:
       res[7:0]   = val1[7:0]   + val2[7:0] 
+   res[15:8]  = val1[15:8]  + val2[15:8]
+   res[23:16] = val1[23:16] + val2[23:16]
+   res[31:24] = val1[31:24] + val2[31:24]
+
    + +
    +
    + +
    +
    + + + + + + + + + + + + + + + + + + +
    uint32_t __UASX (uint32_t val1,
    uint32_t val2 
    )
    +
    +
    +

    This function enables you to exchange the two halfwords of the second operand, add the high halfwords and subtract the low halfwords.
    + The GE bits in the APSR are set according to the results.

    +
    Parameters:
    + + + +
    val1first operand for the subtraction in the low halfword, and the first operand for the addition in the high halfword.
    val2second operand for the subtraction in the high halfword and the second operand for the addition in the low halfword.
    +
    +
    +
    Returns:
      +
    • the subtraction of the high halfword in the second operand from the low halfword in the first operand, in the low halfword of the return value.
      • +
    • the addition of the high halfword in the first operand and the low halfword in the second operand, in the high halfword of the return value.
      • +
    +
    +
    Each bit in APSR.GE is set or cleared for each byte in the return value, depending on the results of the operation.
    +
    If res is the return value, then:
      +
    • if res[15:0] >= 0 then APSR.GE[1:0] = 11 else 00
      • +
    • if res[31:16] >= 0x10000 then APSR.GE[3:2] = 11 else 00
      • +
    +
    +
    Operation:
       res[15:0]  = val1[15:0]  - val2[31:16]
+   res[31:16] = val1[31:16] + val2[15:0] 
+
    + +
    +
    + +
    +
    + + + + + + + + + + + + + + + + + + +
    uint32_t __UHADD16 (uint32_t val1,
    uint32_t val2 
    )
    +
    +
    +

    This function enables you to perform two unsigned 16-bit integer additions, halving the results.

    +
    Parameters:
    + + + +
    val1first two 16-bit summands.
    val2second two 16-bit summands.
    +
    +
    +
    Returns:
      +
    • the halved addition of the low halfwords in each operand, in the low halfword of the return value.
      • +
    • the halved addition of the high halfwords in each operand, in the high halfword of the return value.
      • +
    +
    +
    Operation:
       res[15:0]  = val1[15:0]  + val2[15:0]   >> 1
+   res[31:16] = val1[31:16] + val2[31:16]  >> 1
+
    + +
    +
    + +
    +
    + + + + + + + + + + + + + + + + + + +
    uint32_t __UHADD8 (uint32_t val1,
    uint32_t val2 
    )
    +
    +
    +

    This function enables you to perform four unsigned 8-bit integer additions, halving the results.

    +
    Parameters:
    + + + +
    val1first four 8-bit summands.
    val2second four 8-bit summands.
    +
    +
    +
    Returns:
      +
    • the halved addition of the first bytes in each operand, in the first byte of the return value.
      • +
    • the halved addition of the second bytes in each operand, in the second byte of the return value.
      • +
    • the halved addition of the third bytes in each operand, in the third byte of the return value.
      • +
    • the halved addition of the fourth bytes in each operand, in the fourth byte of the return value.
      • +
    +
    +
    Operation:
       res[7:0]   = val1[7:0]   + val2[7:0]   >> 1
+   res[15:8]  = val1[15:8]  + val2[15:8]  >> 1
+   res[23:16] = val1[23:16] + val2[23:16] >> 1
+   res[31:24] = val1[31:24] + val2[31:24] >> 1
+
    + +
    +
    + +
    +
    + + + + + + + + + + + + + + + + + + +
    uint32_t __UHASX (uint32_t val1,
    uint32_t val2 
    )
    +
    +
    +

    This function enables you to exchange the halfwords of the second operand, add the high halfwords and subtract the low halfwords, halving the results.

    +
    Parameters:
    + + + +
    val1first operand for the subtraction in the low halfword, and the first operand for the addition in the high halfword.
    val2second operand for the subtraction in the high halfword, and the second operand for the addition in the low halfword.
    +
    +
    +
    Returns:
      +
    • the halved subtraction of the high halfword in the second operand from the low halfword in the first operand.
      • +
    • the halved addition of the high halfword in the first operand and the low halfword in the second operand.
      • +
    +
    +
    Operation:
       res[15:0]  = (val1[15:0]  - val2[31:16]) >> 1
+   res[31:16] = (val1[31:16] + val2[15:0] ) >> 1
+
    + +
    +
    + +
    +
    + + + + + + + + + + + + + + + + + + +
    uint32_t __UHSAX (uint32_t val1,
    uint32_t val2 
    )
    +
    +
    +

    This function enables you to exchange the halfwords of the second operand, subtract the high halfwords and add the low halfwords, halving the results.

    +
    Parameters:
    + + + +
    val1first operand for the addition in the low halfword, and the first operand for the subtraction in the high halfword.
    val2second operand for the addition in the high halfword, and the second operand for the subtraction in the low halfword.
    +
    +
    +
    Returns:
      +
    • the halved addition of the high halfword in the second operand and the low halfword in the first operand, in the low halfword of the return value.
      • +
    • the halved subtraction of the low halfword in the second operand from the high halfword in the first operand, in the high halfword of the return value.
      • +
    +
    +
    Operation:
       res[15:0]  = (val1[15:0]  + val2[31:16]) >> 1
+   res[31:16] = (val1[31:16] - val2[15:0] ) >> 1
+
    + +
    +
    + +
    +
    + + + + + + + + + + + + + + + + + + +
    uint32_t __UHSUB16 (uint32_t val1,
    uint32_t val2 
    )
    +
    +
    +

    This function enables you to perform two unsigned 16-bit integer subtractions, halving the results.

    +
    Parameters:
    + + + +
    val1first two 16-bit operands.
    val2second two 16-bit operands.
    +
    +
    +
    Returns:
      +
    • the halved subtraction of the low halfword in the second operand from the low halfword in the first operand, in the low halfword of the return value.
      • +
    • the halved subtraction of the high halfword in the second operand from the high halfword in the first operand, in the high halfword of the return value.
      • +
    +
    +
    Operation:
       res[15:0]  = val1[15:0]  - val2[15:0]   >> 1
+   res[31:16] = val1[31:16] - val2[31:16]  >> 1
+
    + +
    +
    + +
    +
    + + + + + + + + + + + + + + + + + + +
    uint32_t __UHSUB8 (uint32_t val1,
    uint32_t val2 
    )
    +
    +
    +

    This function enables you to perform four unsigned 8-bit integer subtractions, halving the results.

    +
    Parameters:
    + + + +
    val1first four 8-bit operands.
    val2second four 8-bit operands.
    +
    +
    +
    Returns:
      +
    • the halved subtraction of the first byte in the second operand from the first byte in the first operand, in the first bytes of the return value.
      • +
    • the halved subtraction of the second byte in the second operand from the second byte in the first operand, in the second byte of the return value.
      • +
    • the halved subtraction of the third byte in the second operand from the third byte in the first operand, in the third byte of the return value.
      • +
    • the halved subtraction of the fourth byte in the second operand from the fourth byte in the first operand, in the fourth byte of the return value.
      • +
    +
    +
    Operation:
       res[7:0]   = val1[7:0]   - val2[7:0]    >> 1
+   res[15:8]  = val1[15:8]  - val2[15:8]   >> 1
+   res[23:16] = val1[23:16] - val2[23:16]  >> 1
+   res[31:24] = val1[31:24] - val2[31:24]  >> 1
+
    + +
    +
    + +
    +
    + + + + + + + + + + + + + + + + + + +
    uint32_t __UQADD16 (uint32_t val1,
    uint32_t val2 
    )
    +
    +
    +

    This function enables you to perform two unsigned 16-bit integer additions, saturating the results to the 16-bit unsigned integer range 0 < x < 216 - 1.

    +
    Parameters:
    + + + +
    val1first two 16-bit summands.
    val2second two 16-bit summands.
    +
    +
    +
    Returns:
      +
    • the addition of the low halfword in the first operand and the low halfword in the second operand, in the low halfword of the return value.
      • +
    • the addition of the high halfword in the first operand and the high halfword in the second operand, in the high halfword of the return value.
      • +
    +
    +
    The results are saturated to the 16-bit unsigned integer range 0 < x < 216 - 1.
    +
    Operation:
       res[15:0]  = val1[15:0]  + val2[15:0] 
+   res[31:16] = val1[31:16] + val2[31:16]
+
    + +
    +
    + +
    +
    + + + + + + + + + + + + + + + + + + +
    uint32_t __UQADD8 (uint32_t val1,
    uint32_t val2 
    )
    +
    +
    +

    This function enables you to perform four unsigned 8-bit integer additions, saturating the results to the 8-bit unsigned integer range 0 < x < 28 - 1.

    +
    Parameters:
    + + + +
    val1first four 8-bit summands.
    val2second four 8-bit summands.
    +
    +
    +
    Returns:
      +
    • the halved addition of the first bytes in each operand, in the first byte of the return value.
      • +
    • the halved addition of the second bytes in each operand, in the second byte of the return value.
      • +
    • the halved addition of the third bytes in each operand, in the third byte of the return value.
      • +
    • the halved addition of the fourth bytes in each operand, in the fourth byte of the return value.
      • +
    +
    +
    The results are saturated to the 8-bit unsigned integer range 0 < x < 28 - 1.
    +
    Operation:
       res[7:0]   = val1[7:0]   + val2[7:0] 
+   res[15:8]  = val1[15:8]  + val2[15:8]
+   res[23:16] = val1[23:16] + val2[23:16]
+   res[31:24] = val1[31:24] + val2[31:24]
+
    + +
    +
    + +
    +
    + + + + + + + + + + + + + + + + + + +
    uint32_t __UQASX (uint32_t val1,
    uint32_t val2 
    )
    +
    +
    +

    This function enables you to exchange the halfwords of the second operand and perform one unsigned 16-bit integer addition and one unsigned 16-bit subtraction, saturating the results to the 16-bit unsigned integer range 0 <= x <= 216 - 1.

    +
    Parameters:
    + + + +
    val1first two 16-bit operands.
    val2second two 16-bit operands.
    +
    +
    +
    Returns:
      +
    • the subtraction of the high halfword in the second operand from the low halfword in the first operand, in the low halfword of the return value.
      • +
    • the subtraction of the low halfword in the second operand from the high halfword in the first operand, in the high halfword of the return value.
      • +
    +
    +
    The results are saturated to the 16-bit unsigned integer range 0 <= x <= 216 - 1.
    +
    Operation:
       res[15:0]  = val1[15:0]  - val2[31:16]
+   res[31:16] = val1[31:16] + val2[15:0] 
+
    + +
    +
    + +
    +
    + + + + + + + + + + + + + + + + + + +
    uint32_t __UQSAX (uint32_t val1,
    uint32_t val2 
    )
    +
    +
    +

    This function enables you to exchange the halfwords of the second operand and perform one unsigned 16-bit integer subtraction and one unsigned 16-bit addition, saturating the results to the 16-bit unsigned integer range 0 <= x <= 216 - 1.

    +
    Parameters:
    + + + +
    val1first 16-bit operand for the addition in the low halfword, and the first 16-bit operand for the subtraction in the high halfword.
    val2second 16-bit halfword for the addition in the high halfword, and the second 16-bit halfword for the subtraction in the low halfword.
    +
    +
    +
    Returns:
      +
    • the addition of the low halfword in the first operand and the high halfword in the second operand, in the low halfword of the return value.
      • +
    • the subtraction of the low halfword in the second operand from the high halfword in the first operand, in the high halfword of the return value.
      • +
    +
    +
    The results are saturated to the 16-bit unsigned integer range 0 <= x <= 216 - 1.
    +
    Operation:
       res[15:0]  = val1[15:0]  + val2[31:16]
+   res[31:16] = val1[31:16] - val2[15:0] 
+
    + +
    +
    + +
    +
    + + + + + + + + + + + + + + + + + + +
    uint32_t __UQSUB16 (uint32_t val1,
    uint32_t val2 
    )
    +
    +
    +

    This function enables you to perform two unsigned 16-bit integer subtractions, saturating the results to the 16-bit unsigned integer range 0 < x < 216 - 1.

    +
    Parameters:
    + + + +
    val1first two 16-bit operands for each subtraction.
    val2second two 16-bit operands for each subtraction.
    +
    +
    +
    Returns:
      +
    • the subtraction of the low halfword in the second operand from the low halfword in the first operand, in the low halfword of the return value.
      • +
    • the subtraction of the high halfword in the second operand from the high halfword in the first operand, in the high halfword of the return value.
      • +
    +
    +
    The results are saturated to the 16-bit unsigned integer range 0 < x < 216 - 1.
    +
    Operation:
       res[15:0]  = val1[15:0]  - val2[15:0]   
+   res[31:16] = val1[31:16] - val2[31:16]  
+
    + +
    +
    + +
    +
    + + + + + + + + + + + + + + + + + + +
    uint32_t __UQSUB8 (uint32_t val1,
    uint32_t val2 
    )
    +
    +
    +

    This function enables you to perform four unsigned 8-bit integer subtractions, saturating the results to the 8-bit unsigned integer range 0 < x < 28 - 1.

    +
    Parameters:
    + + + +
    val1first four 8-bit operands.
    val2second four 8-bit operands.
    +
    +
    +
    Returns:
      +
    • the subtraction of the first byte in the second operand from the first byte in the first operand, in the first bytes of the return value.
      • +
    • the subtraction of the second byte in the second operand from the second byte in the first operand, in the second byte of the return value.
      • +
    • the subtraction of the third byte in the second operand from the third byte in the first operand, in the third byte of the return value.
      • +
    • the subtraction of the fourth byte in the second operand from the fourth byte in the first operand, in the fourth byte of the return value.
      • +
    +
    +
    The results are saturated to the 8-bit unsigned integer range 0 < x < 28 - 1.
    +
    Operation:
       res[7:0]   = val1[7:0]   - val2[7:0]
+   res[15:8]  = val1[15:8]  - val2[15:8]
+   res[23:16] = val1[23:16] - val2[23:16]
+   res[31:24] = val1[31:24] - val2[31:24]
+
    + +
    +
    + +
    +
    + + + + + + + + + + + + + + + + + + +
    uint32_t __USAD8 (uint32_t val1,
    uint32_t val2 
    )
    +
    +
    +

    This function enables you to perform four unsigned 8-bit subtractions, and add the absolute values of the differences together, returning the result as a single unsigned integer.

    +
    Parameters:
    + + + +
    val1first four 8-bit operands for the subtractions.
    val2second four 8-bit operands for the subtractions.
    +
    +
    +
    Returns:
      +
    • the subtraction of the first byte in the second operand from the first byte in the first operand.
      • +
    • the subtraction of the second byte in the second operand from the second byte in the first operand.
      • +
    • the subtraction of the third byte in the second operand from the third byte in the first operand.
      • +
    • the subtraction of the fourth byte in the second operand from the fourth byte in the first operand.
      • +
    +
    +
    The sum is returned as a single unsigned integer.
    +
    Operation:
       absdiff1  = val1[7:0]   - val2[7:0]
+   absdiff2  = val1[15:8]  - val2[15:8]
+   absdiff3  = val1[23:16] - val2[23:16]
+   absdiff4  = val1[31:24] - val2[31:24]
+   res[31:0] = absdiff1 + absdiff2 + absdiff3 + absdiff4
+
    + +
    +
    + +
    +
    + + + + + + + + + + + + + + + + + + + + + + + + +
    uint32_t __USADA8 (uint32_t val1,
    uint32_t val2,
    uint32_t val3 
    )
    +
    +
    +

    This function enables you to perform four unsigned 8-bit subtractions, and add the absolute values of the differences to a 32-bit accumulate operand.

    +
    Parameters:
    + + + + +
    val1first four 8-bit operands for the subtractions.
    val2second four 8-bit operands for the subtractions.
    val3accumulation value.
    +
    +
    +
    Returns:
    the sum of the absolute differences of the following bytes, added to the accumulation value:
      +
    • the subtraction of the first byte in the second operand from the first byte in the first operand.
      • +
    • the subtraction of the second byte in the second operand from the second byte in the first operand.
      • +
    • the subtraction of the third byte in the second operand from the third byte in the first operand.
      • +
    • the subtraction of the fourth byte in the second operand from the fourth byte in the first operand.
      • +
    +
    +
    Operation:
       absdiff1  = val1[7:0]   - val2[7:0]
+   absdiff2  = val1[15:8]  - val2[15:8]
+   absdiff3  = val1[23:16] - val2[23:16]
+   absdiff4  = val1[31:24] - val2[31:24]
+   sum       = absdiff1 + absdiff2 + absdiff3 + absdiff4
+   res[31:0] = sum[31:0] + val3[31:0]
+
    + +
    +
    + +
    +
    + + + + + + + + + + + + + + + + + + +
    uint32_t __USAT16 (uint32_t val1,
    const uint32_t val2 
    )
    +
    +
    +

    This function enables you to saturate two signed 16-bit values to a selected unsigned range.
    + The Q bit is set if either operation saturates.

    +
    Parameters:
    + + + +
    val1two 16-bit values that are to be saturated.
    val2bit position for saturation, and must be an integral constant expression in the range 0 to 15.
    +
    +
    +
    Returns:
    the saturation of the two signed 16-bit values, as non-negative values.
      +
    • the saturation of the low halfword in val1, saturated to the bit position specified in val2 and returned in the low halfword of the return value.
      • +
    • the saturation of the high halfword in val1, saturated to the bit position specified in val2 and returned in the high halfword of the return value.
      • +
    +
    +
    Operation:
       Saturate halfwords in val1 to the unsigned range specified by the bit position in val2
+
    + +
    +
    + +
    +
    + + + + + + + + + + + + + + + + + + +
    uint32_t __USAX (uint32_t val1,
    uint32_t val2 
    )
    +
    +
    +

    This function enables you to exchange the halfwords of the second operand, subtract the high halfwords and add the low halfwords.
    + The GE bits in the APSR are set according to the results.

    +
    Parameters:
    + + + +
    val1first operand for the addition in the low halfword, and the first operand for the subtraction in the high halfword.
    val2second operand for the addition in the high halfword, and the second operand for the subtraction in the low halfword.
    +
    +
    +
    Returns:
      +
    • the addition of the low halfword in the first operand and the high halfword in the second operand, in the low halfword of the return value.
      • +
    • the subtraction of the low halfword in the second operand from the high halfword in the first operand, in the high halfword of the return value.
      • +
    +
    +
    Each bit in APSR.GE is set or cleared for each byte in the return value, depending on the results of the operation.
    +
    If res is the return value, then:
      +
    • if res[15:0] >= 0x10000 then APSR.GE[1:0] = 11 else 00
      • +
    • if res[31:16] >= 0 then APSR.GE[3:2] = 11 else 00
      • +
    +
    +
    Operation:
       res[15:0]  = val1[15:0]  + val2[31:16]
+   res[31:16] = val1[31:16] - val2[15:0] 
+
    + +
    +
    + +
    +
    + + + + + + + + + + + + + + + + + + +
    uint32_t __USUB16 (uint32_t val1,
    uint32_t val2 
    )
    +
    +
    +

    This function enables you to perform two 16-bit unsigned integer subtractions.
    + The GE bits in the APSR are set according to the results.

    +
    Parameters:
    + + + +
    val1first two 16-bit operands.
    val2second two 16-bit operands.
    +
    +
    +
    Returns:
      +
    • the subtraction of the low halfword in the second operand from the low halfword in the first operand, in the low halfword of the return value.
      • +
    • the subtraction of the high halfword in the second operand from the high halfword in the first operand, in the high halfword of the return value.
      • +
    +
    +
    Each bit in APSR.GE is set or cleared for each byte in the return value, depending on the results of the operation.
    +
    If res is the return value, then:
      +
    • if res[15:0] >= 0 then APSR.GE[1:0] = 11 else 00
      • +
    • if res[31:16] >= 0 then APSR.GE[3:2] = 11 else 00
      • +
    +
    +
    Operation:
       res[15:0]  = val1[15:0]  - val2[15:0]   
+   res[31:16] = val1[31:16] - val2[31:16]  
+
    + +
    +
    + +
    +
    + + + + + + + + + + + + + + + + + + +
    uint32_t __USUB8 (uint32_t val1,
    uint32_t val2 
    )
    +
    +
    +

    This function enables you to perform four 8-bit unsigned integer subtractions. The GE bits in the APSR are set according to the results.

    +
    Parameters:
    + + + +
    val1first four 8-bit operands.
    val2second four 8-bit operands.
    +
    +
    +
    Returns:
      +
    • the subtraction of the first byte in the second operand from the first byte in the first operand, in the first bytes of the return value.
      • +
    • the subtraction of the second byte in the second operand from the second byte in the first operand, in the second byte of the return value.
      • +
    • the subtraction of the third byte in the second operand from the third byte in the first operand, in the third byte of the return value.
      • +
    • the subtraction of the fourth byte in the second operand from the fourth byte in the first operand, in the fourth byte of the return value.
      • +
    +
    +
    Each bit in APSR.GE is set or cleared for each byte in the return value, depending on the results of the operation.
    +
    If res is the return value, then:
      +
    • if res[8:0] >= 0 then APSR.GE[0] = 1 else 0
      • +
    • if res[15:8] >= 0 then APSR.GE[1] = 1 else 0
      • +
    • if res[23:16] >= 0 then APSR.GE[2] = 1 else 0
      • +
    • if res[31:24] >= 0 then APSR.GE[3] = 1 else 0
      • +
    +
    +
    Operation:
       res[7:0]   = val1[7:0]   - val2[7:0]
+   res[15:8]  = val1[15:8]  - val2[15:8]
+   res[23:16] = val1[23:16] - val2[23:16]
+   res[31:24] = val1[31:24] - val2[31:24]
+
    + +
    +
    + +
    +
    + + + + + + + + + + + + + + + + + + +
    uint32_t __UXTAB16 (uint32_t val1,
    uint32_t val2 
    )
    +
    +
    +

    This function enables you to extract two 8-bit values from one operand, zero-extend them to 16 bits each, and add the results to two 16-bit values from another operand.

    +
    Parameters:
    + + + +
    val1value added to the zero-extended to 16-bit values.
    val2two 8-bit values to be extracted and zero-extended.
    +
    +
    +
    Returns:
    the 8-bit values in val2, zero-extended to 16-bit values and added to val1.
    +
    Operation:
       res[15:0]  = ZeroExt(val2[7:0]   to 16 bits) + val1[15:0]
+   res[31:16] = ZeroExt(val2[31:16] to 16 bits) + val1[31:16]
+
    + +
    +
    + +
    +
    + + + + + + + + +
    uint32_t __UXTB16 (uint32_t val)
    +
    +
    +

    This function enables you to extract two 8-bit values from an operand and zero-extend them to 16 bits each.

    +
    Parameters:
    + + +
    valtwo 8-bit values in val[7:0] and val[23:16] to be sign-extended.
    +
    +
    +
    Returns:
    the 8-bit values zero-extended to 16-bit values.
      +
    • zero-extended value of val[7:0] in the low halfword of the return value.
      • +
    • zero-extended value of val[23:16] in the high halfword of the return value.
      • +
    +
    +
    Operation:
       res[15:0]  = ZeroExtended(val[7:0]  )
+   res[31:16] = ZeroExtended(val[23:16])
+
    + +
    +
    +
    +
    + + + + + diff --git a/Libraries/CMSIS/Documentation/Core/html/group__peripheral__gr.html b/Libraries/CMSIS/Documentation/Core/html/group__peripheral__gr.html new file mode 100644 index 0000000..ffde56f --- /dev/null +++ b/Libraries/CMSIS/Documentation/Core/html/group__peripheral__gr.html @@ -0,0 +1,231 @@ + + + + +Peripheral Access + + + + + + + + + + + + + +
    + +
    + + + + + + + + + + + +
    +
    CMSIS-CORE +  Version 3.01 +
    +
    CMSIS-CORE support for Cortex-M processor-based devices
    +
    +
    + +
    + +
    + + + +
    +
    + +
    +
    +
    + +
    +
    +
    +
    Peripheral Access
    +
    +
    + +

    Describes naming conventions, requirements, and optional features for accessing peripherals. +More...

    +

    Each peripheral provides a data type definition with a name that is composed of a prefix <device abbreviation>_ and the <peripheral name>_, for example LPC_UART for the device LPC and the peripheral UART. The intention is to avoid name collisions caused by short names. If more peripherals exist of the same type, identifiers have a postfix consisting of a digit or letter, for example LPC_UART0, LPC_UART1.

    +
      +
    • The data type definition uses the standard C data types from the ANSI C header file <stdint.h>. IO Type Qualifiers are used to specify the access to peripheral variables. IO Type Qualifiers are indented to be used for automatic generation of debug information of peripheral registers and are defined as shown below:
      + 
        #define   __I     volatile const       
+  #define   __O     volatile             
+  #define   __IO    volatile             
+
      • +
    +
      +
    • The following typedef is an example for a UART. <device abbreviation>_UART_TypeDef: defines the generic register layout for all UART channels in a device.
      + 
      typedef struct
+{
+  union {
+  __I  uint8_t  RBR;                  /* Offset: 0x000 (R/ )  Receiver Buffer Register            */
+  __O  uint8_t  THR;                  /* Offset: 0x000 ( /W)  Transmit Holding Register           */
+  __IO uint8_t  DLL;                  /* Offset: 0x000 (R/W)  Divisor Latch LSB                   */
+       uint32_t RESERVED0;
+  };
+  union {
+  __IO uint8_t  DLM;                  /* Offset: 0x004 (R/W)  Divisor Latch MSB                   */
+  __IO uint32_t IER;                  /* Offset: 0x004 (R/W)  Interrupt Enable Register           */
+  };
+  union {
+  __I  uint32_t IIR;                  /* Offset: 0x008 (R/ )  Interrupt ID Register               */
+  __O  uint8_t  FCR;                  /* Offset: 0x008 ( /W)  FIFO Control Register               */
+  };
+  __IO uint8_t  LCR;                  /* Offset: 0x00C (R/W)  Line Control Register               */
+       uint8_t  RESERVED1[7];
+  __I  uint8_t  LSR;                  /* Offset: 0x014 (R/ )  Line Status Register                */
+       uint8_t  RESERVED2[7];
+  __IO uint8_t  SCR;                  /* Offset: 0x01C (R/W)  Scratch Pad Register                */
+       uint8_t  RESERVED3[3];
+  __IO uint32_t ACR;                  /* Offset: 0x020 (R/W)  Autobaud Control Register           */
+  __IO uint8_t  ICR;                  /* Offset: 0x024 (R/W)  IrDA Control Register               */
+       uint8_t  RESERVED4[3];
+  __IO uint8_t  FDR;                  /* Offset: 0x028 (R/W)  Fractional Divider Register         */
+       uint8_t  RESERVED5[7];
+  __IO uint8_t  TER;                  /* Offset: 0x030 (R/W)  Transmit Enable Register            */
+       uint8_t  RESERVED6[39];
+  __I  uint8_t  FIFOLVL;              /* Offset: 0x058 (R/ )  FIFO Level Register                 */
+} LPC_UART_TypeDef;
+
      • +
    +
      +
    • To access the registers of the UART defined above, pointers to a register structure are defined. In this example <device abbreviation>_UART# are two pointers to UARTs defined with above register structure.
      + 
      #define LPC_UART2             ((LPC_UART_TypeDef      *) LPC_UART2_BASE    )
+#define LPC_UART3             ((LPC_UART_TypeDef      *) LPC_UART3_BASE    )
+
      • +
    +
      +
    • The registers in the various UARTs can now be referred in the user code as shown below:
      + 
      LPC_UART1->DR   // is the data register of UART1.
+
      • +
    +
    +

    +Minimal Requirements

    +

    To access the peripheral registers and related function in a device, the files device.h and core_cm#.h define as a minimum:
    +
    +

    +
      +
    • The Register Layout Typedef for each peripheral that defines all register names. RESERVED is used to introduce space into the structure for adjusting the addresses of the peripheral registers.
      +
      + Example: 
      typedef struct
+{
+  __IO uint32_t CTRL;                 /* Offset: 0x000 (R/W)  SysTick Control and Status Register */
+  __IO uint32_t LOAD;                 /* Offset: 0x004 (R/W)  SysTick Reload Value Register       */
+  __IO uint32_t VAL;                  /* Offset: 0x008 (R/W)  SysTick Current Value Register      */
+  __I  uint32_t CALIB;                /* Offset: 0x00C (R/ )  SysTick Calibration Register        */
+} SysTick_Type;
+
      • +
    +
      +
    • Base Address for each peripheral (in case of multiple peripherals that use the same register layout typedef multiple base addresses are defined).
      +
      + Example: 
      #define SysTick_BASE (SCS_BASE + 0x0010)            /* SysTick Base Address     */    
+
      • +
    +
      +
    • Access Definitions for each peripheral. In case of multiple peripherals that are using the same register layout typdef, multiple access definitions exist (LPC_UART0, LPC_UART2).
      +
      + Example: 
      #define SysTick ((SysTick_Type *) Systick_BASE)    /* SysTick access definition */
+
      • +
    +

    These definitions allow accessing peripheral registers with simple assignments.

    +

    Example:
    +

    +
    SysTick->CTRL = 0;    
+
    +

    +Optional Features

    +

    Optionally, the file device.h may define:

    +
      +
    • #define constants, which simplify access to peripheral registers. These constants define bit-positions or other specific patterns that are required for programming peripheral registers. The identifiers start with <device abbreviation>_ and <peripheral name>_. It is recommended to use CAPITAL letters for such #define constants.
      • +
    +
      +
    • More complex functions (i.e. status query before a sending register is accessed). Again, these functions start with <device abbreviation>_ and <peripheral name>_.
      • +
    +
    +
    + + + + + diff --git a/Libraries/CMSIS/Documentation/Core/html/group__system__init__gr.html b/Libraries/CMSIS/Documentation/Core/html/group__system__init__gr.html new file mode 100644 index 0000000..c2fa9b3 --- /dev/null +++ b/Libraries/CMSIS/Documentation/Core/html/group__system__init__gr.html @@ -0,0 +1,228 @@ + + + + +System and Clock Configuration + + + + + + + + + + + + + +
    + +
    + + + + + + + + + + + +
    +
    CMSIS-CORE +  Version 3.01 +
    +
    CMSIS-CORE support for Cortex-M processor-based devices
    +
    +
    + +
    + +
    + + + +
    +
    + +
    +
    +
    + +
    +
    +
    +Variables | +Functions
    +
    +
    System and Clock Configuration
    +
    +
    + + + + + + + + + +

    +Variables

    uint32_t SystemCoreClock
     Variable to hold the system core clock value.

    +Functions

    void SystemInit (void)
     Function to Initialize the system.
    void SystemCoreClockUpdate (void)
     Function to update the variable SystemCoreClock.
    +

    Description

    +

    ARM provides a template file system_device.c that must be adapted by the silicon vendor to match their actual device. As a minimum requirement, this file must provide:

    +
      +
    • A device-specific system configuration function, SystemInit().
      • +
    • A global variable that contains the system frequency, SystemCoreClock.
      • +
    +

    The file configures the device and, typically, initializes the oscillator (PLL) that is part of the microcontroller device. This file might export other functions or variables that provide a more flexible configuration of the microcontroller system.

    +

    +Code Example

    +

    The code below shows the usage of the variable SystemCoreClock and the functions SystemInit() and SystemCoreClockUpdate() with an LPC1700.

    +
    #include "LPC17xx.h"
+
+uint32_t coreClock_1 = 0;                       /* Variables to store core clock values */
+uint32_t coreClock_2 = 0;
+
+
+int main (void)  {
+
+  coreClock_1 = SystemCoreClock;                /* Store value of predefined SystemCoreClock */
+
+  SystemCoreClockUpdate();                      /* Update SystemCoreClock according to register settings */
+
+  coreClock_2 = SystemCoreClock;                /* Store value of calculated SystemCoreClock */
+
+  if (coreClock_2 != coreClock_1)  {            /* Without changing the clock setting both core clock values should be the same */ 
+    // Error Handling
+  }
+
+  while(1);
+}
+

    Variable Documentation

    + +
    +
    + + + + +
    uint32_t SystemCoreClock
    +
    +
    +

    Holds the system core clock, which is the system clock frequency supplied to the SysTick timer and the processor core clock. This variable can be used by debuggers to query the frequency of the debug timer or to configure the trace clock speed.

    +
    Attention:
    Compilers must be configured to avoid removing this variable in case the application program is not using it. Debugging systems require the variable to be physically present in memory so that it can be examined to configure the debugger.
    + +
    +
    +

    Function Documentation

    + +
    +
    + + + + + + + + +
    void SystemCoreClockUpdate (void )
    +
    +
    +

    Updates the variable SystemCoreClock and must be called whenever the core clock is changed during program execution. The function evaluates the clock register settings and calculates the current core clock.

    + +
    +
    + +
    +
    + + + + + + + + +
    void SystemInit (void )
    +
    +
    +

    Initializes the microcontroller system. Typically, this function configures the oscillator (PLL) that is part of the microcontroller device. For systems with a variable clock speed, it updates the variable SystemCoreClock. SystemInit is called from the file startup_device.

    + +
    +
    +
    +
    + + + + + diff --git a/Libraries/CMSIS/Documentation/Core/html/index.html b/Libraries/CMSIS/Documentation/Core/html/index.html new file mode 100644 index 0000000..0b4beec --- /dev/null +++ b/Libraries/CMSIS/Documentation/Core/html/index.html @@ -0,0 +1,205 @@ + + + + +Overview + + + + + + + + + + + + + +
    + +
    + + + + + + + + + + + +
    +
    CMSIS-CORE +  Version 3.01 +
    +
    CMSIS-CORE support for Cortex-M processor-based devices
    +
    +
    + +
    + +
    + + + +
    +
    + +
    +
    +
    + +
    +
    +
    +
    Overview
    +
    +
    +

    CMSIS-CORE implements the basic run-time system for a Cortex-M device and gives the user access to the processor core and the device peripherals. In detail it defines:

    +
      +
    • Hardware Abstraction Layer (HAL) for Cortex-M processor registers with standardized definitions for the SysTick, NVIC, System Control Block registers, MPU registers, FPU registers, and core access functions.
      • +
    • System exception names to interface to system exceptions without having compatibility issues.
      • +
    • Methods to organize header files that makes it easy to learn new Cortex-M microcontroller products and improve software portability. This includes naming conventions for device-specific interrupts.
      • +
    • Methods for system initialization to be used by each MCU vendor. For example, the standardized SystemInit() function is essential for configuring the clock system of the device.
      • +
    • Intrinsic functions used to generate CPU instructions that are not supported by standard C functions.
      • +
    • A variable to determine the system clock frequency which simplifies the setup the SysTick timer.
      • +
    +
    +

    This chapter provides details about the CMSIS-CORE and contains the following sections:

    + +
    +

    +Cortex-M Reference Manuals

    +

    The Cortex-M Reference Manuals are generic user guides for devices that implement the various ARM Cortex-M processors. These manuals contain the programmers model and detailed information about the core peripherals.

    + +
    +

    +Tested and Verified Toolchains

    +

    The CMSIS-CORE Template Files supplied by ARM have been tested and verified with the following toolchains:

    +
      +
    • ARM: MDK-ARM Version 4.13a (or greater)
      • +
    • GNU: GCC ARM Embedded 2011-q4-major (or greater)
      • +
    • GNU: Sourcery G++ Lite Edition for ARM 2010.09-51 (or greater)
      • +
    • IAR: IAR Embedded Workbench Kickstart Edition V6.10 (or greater)
      • +
    +
    +

    Revision History of CMSIS-CORE

    + + + + + + + + + + + + + + + + + + + +
    Version Description
    V3.01 Added support for Cortex-M0+ processor.
    + Integration of CMSIS DSP Library version 1.1.0
    +
    V3.00 Added support for GNU GCC ARM Embedded Compiler.
    + Added function __ROR.
    + Added Register Mapping for TPIU, DWT.
    + Added support for SC000 and SC300 processors.
    + Corrected ITM_SendChar function.
    + Corrected the functions __STREXB, __STREXH, __STREXW for the GNU GCC compiler section.
    + Documentation restructured.
    V2.10 Updated documentation.
    + Updated CMSIS core include files.
    + Changed CMSIS/Device folder structure.
    + Added support for Cortex-M0, Cortex-M4 w/o FPU to CMSIS DSP library.
    + Reworked CMSIS DSP library examples.
    V2.00 Added support for Cortex-M4 processor.
    V1.30 Reworked Startup Concept.
    + Added additional Debug Functionality.
    + Changed folder structure.
    + Added doxygen comments.
    + Added definitions for bit.
    V1.01 Added support for Cortex-M0 processor.
    V1.01 Added intrinsic functions for __LDREXB, __LDREXH, __LDREXW, __STREXB, __STREXH, __STREXW, and __CLREX
    V1.00 Initial Release for Cortex-M3 processor.
    +
    +
    + + + + + diff --git a/Libraries/CMSIS/Documentation/Core/html/installdox b/Libraries/CMSIS/Documentation/Core/html/installdox new file mode 100644 index 0000000..edf5bbf --- /dev/null +++ b/Libraries/CMSIS/Documentation/Core/html/installdox @@ -0,0 +1,112 @@ +#!/usr/bin/perl + +%subst = ( ); +$quiet = 0; + +while ( @ARGV ) { + $_ = shift @ARGV; + if ( s/^-// ) { + if ( /^l(.*)/ ) { + $v = ($1 eq "") ? shift @ARGV : $1; + ($v =~ /\/$/) || ($v .= "/"); + $_ = $v; + if ( /(.+)\@(.+)/ ) { + if ( exists $subst{$1} ) { + $subst{$1} = $2; + } else { + print STDERR "Unknown tag file $1 given with option -l\n"; + &usage(); + } + } else { + print STDERR "Argument $_ is invalid for option -l\n"; + &usage(); + } + } + elsif ( /^q/ ) { + $quiet = 1; + } + elsif ( /^\?|^h/ ) { + &usage(); + } + else { + print STDERR "Illegal option -$_\n"; + &usage(); + } + } + else { + push (@files, $_ ); + } +} + +foreach $sub (keys %subst) +{ + if ( $subst{$sub} eq "" ) + { + print STDERR "No substitute given for tag file `$sub'\n"; + &usage(); + } + elsif ( ! $quiet && $sub ne "_doc" && $sub ne "_cgi" ) + { + print "Substituting $subst{$sub} for each occurrence of tag file $sub\n"; + } +} + +if ( ! @files ) { + if (opendir(D,".")) { + foreach $file ( readdir(D) ) { + $match = ".html"; + next if ( $file =~ /^\.\.?$/ ); + ($file =~ /$match/) && (push @files, $file); + ($file =~ /\.svg/) && (push @files, $file); + ($file =~ "navtree.js") && (push @files, $file); + } + closedir(D); + } +} + +if ( ! @files ) { + print STDERR "Warning: No input files given and none found!\n"; +} + +foreach $f (@files) +{ + if ( ! $quiet ) { + print "Editing: $f...\n"; + } + $oldf = $f; + $f .= ".bak"; + unless (rename $oldf,$f) { + print STDERR "Error: cannot rename file $oldf\n"; + exit 1; + } + if (open(F,"<$f")) { + unless (open(G,">$oldf")) { + print STDERR "Error: opening file $oldf for writing\n"; + exit 1; + } + if ($oldf ne "tree.js") { + while () { + s/doxygen\=\"([^ \"\:\t\>\<]*)\:([^ \"\t\>\<]*)\" (xlink:href|href|src)=\"\2/doxygen\=\"$1:$subst{$1}\" \3=\"$subst{$1}/g; + print G "$_"; + } + } + else { + while () { + s/\"([^ \"\:\t\>\<]*)\:([^ \"\t\>\<]*)\", \"\2/\"$1:$subst{$1}\" ,\"$subst{$1}/g; + print G "$_"; + } + } + } + else { + print STDERR "Warning file $f does not exist\n"; + } + unlink $f; +} + +sub usage { + print STDERR "Usage: installdox [options] [html-file [html-file ...]]\n"; + print STDERR "Options:\n"; + print STDERR " -l tagfile\@linkName tag file + URL or directory \n"; + print STDERR " -q Quiet mode\n\n"; + exit 1; +} diff --git a/Libraries/CMSIS/Documentation/Core/html/jquery.js b/Libraries/CMSIS/Documentation/Core/html/jquery.js new file mode 100644 index 0000000..c052173 --- /dev/null +++ b/Libraries/CMSIS/Documentation/Core/html/jquery.js @@ -0,0 +1,54 @@ +/* + * jQuery JavaScript Library v1.3.2 + * http://jquery.com/ + * + * Copyright (c) 2009 John Resig + * Dual licensed under the MIT and GPL licenses. + * http://docs.jquery.com/License + * + * Date: 2009-02-19 17:34:21 -0500 (Thu, 19 Feb 2009) + * Revision: 6246 + */ +(function(){var l=this,g,y=l.jQuery,p=l.$,o=l.jQuery=l.$=function(E,F){return new o.fn.init(E,F)},D=/^[^<]*(<(.|\s)+>)[^>]*$|^#([\w-]+)$/,f=/^.[^:#\[\.,]*$/;o.fn=o.prototype={init:function(E,H){E=E||document;if(E.nodeType){this[0]=E;this.length=1;this.context=E;return this}if(typeof E==="string"){var G=D.exec(E);if(G&&(G[1]||!H)){if(G[1]){E=o.clean([G[1]],H)}else{var I=document.getElementById(G[3]);if(I&&I.id!=G[3]){return o().find(E)}var F=o(I||[]);F.context=document;F.selector=E;return F}}else{return o(H).find(E)}}else{if(o.isFunction(E)){return o(document).ready(E)}}if(E.selector&&E.context){this.selector=E.selector;this.context=E.context}return this.setArray(o.isArray(E)?E:o.makeArray(E))},selector:"",jquery:"1.3.2",size:function(){return this.length},get:function(E){return E===g?Array.prototype.slice.call(this):this[E]},pushStack:function(F,H,E){var G=o(F);G.prevObject=this;G.context=this.context;if(H==="find"){G.selector=this.selector+(this.selector?" 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j;if((c.browser.msie&&(/(static|relative)/).test(this.css("position")))||(/absolute/).test(this.css("position"))){j=this.parents().filter(function(){return(/(relative|absolute|fixed)/).test(c.curCSS(this,"position",1))&&(/(auto|scroll)/).test(c.curCSS(this,"overflow",1)+c.curCSS(this,"overflow-y",1)+c.curCSS(this,"overflow-x",1))}).eq(0)}else{j=this.parents().filter(function(){return(/(auto|scroll)/).test(c.curCSS(this,"overflow",1)+c.curCSS(this,"overflow-y",1)+c.curCSS(this,"overflow-x",1))}).eq(0)}return(/fixed/).test(this.css("position"))||!j.length?c(document):j}});c.extend(c.expr[":"],{data:function(l,k,j){return !!c.data(l,j[3])},focusable:function(k){var l=k.nodeName.toLowerCase(),j=c.attr(k,"tabindex");return(/input|select|textarea|button|object/.test(l)?!k.disabled:"a"==l||"area"==l?k.href||!isNaN(j):!isNaN(j))&&!c(k)["area"==l?"parents":"closest"](":hidden").length},tabbable:function(k){var j=c.attr(k,"tabindex");return(isNaN(j)||j>=0)&&c(k).is(":focusable")}});function g(m,n,o,l){function k(q){var p=c[m][n][q]||[];return(typeof p=="string"?p.split(/,?\s+/):p)}var j=k("getter");if(l.length==1&&typeof l[0]=="string"){j=j.concat(k("getterSetter"))}return(c.inArray(o,j)!=-1)}c.widget=function(k,j){var l=k.split(".")[0];k=k.split(".")[1];c.fn[k]=function(p){var n=(typeof p=="string"),o=Array.prototype.slice.call(arguments,1);if(n&&p.substring(0,1)=="_"){return this}if(n&&g(l,k,p,o)){var m=c.data(this[0],k);return(m?m[p].apply(m,o):undefined)}return this.each(function(){var q=c.data(this,k);(!q&&!n&&c.data(this,k,new c[l][k](this,p))._init());(q&&n&&c.isFunction(q[p])&&q[p].apply(q,o))})};c[l]=c[l]||{};c[l][k]=function(o,n){var m=this;this.namespace=l;this.widgetName=k;this.widgetEventPrefix=c[l][k].eventPrefix||k;this.widgetBaseClass=l+"-"+k;this.options=c.extend({},c.widget.defaults,c[l][k].defaults,c.metadata&&c.metadata.get(o)[k],n);this.element=c(o).bind("setData."+k,function(q,p,r){if(q.target==o){return m._setData(p,r)}}).bind("getData."+k,function(q,p){if(q.target==o){return m._getData(p)}}).bind("remove",function(){return m.destroy()})};c[l][k].prototype=c.extend({},c.widget.prototype,j);c[l][k].getterSetter="option"};c.widget.prototype={_init:function(){},destroy:function(){this.element.removeData(this.widgetName).removeClass(this.widgetBaseClass+"-disabled "+this.namespace+"-state-disabled").removeAttr("aria-disabled")},option:function(l,m){var k=l,j=this;if(typeof l=="string"){if(m===undefined){return this._getData(l)}k={};k[l]=m}c.each(k,function(n,o){j._setData(n,o)})},_getData:function(j){return this.options[j]},_setData:function(j,k){this.options[j]=k;if(j=="disabled"){this.element[k?"addClass":"removeClass"](this.widgetBaseClass+"-disabled "+this.namespace+"-state-disabled").attr("aria-disabled",k)}},enable:function(){this._setData("disabled",false)},disable:function(){this._setData("disabled",true)},_trigger:function(l,m,n){var p=this.options[l],j=(l==this.widgetEventPrefix?l:this.widgetEventPrefix+l);m=c.Event(m);m.type=j;if(m.originalEvent){for(var k=c.event.props.length,o;k;){o=c.event.props[--k];m[o]=m.originalEvent[o]}}this.element.trigger(m,n);return !(c.isFunction(p)&&p.call(this.element[0],m,n)===false||m.isDefaultPrevented())}};c.widget.defaults={disabled:false};c.ui.mouse={_mouseInit:function(){var j=this;this.element.bind("mousedown."+this.widgetName,function(k){return j._mouseDown(k)}).bind("click."+this.widgetName,function(k){if(j._preventClickEvent){j._preventClickEvent=false;k.stopImmediatePropagation();return false}});if(c.browser.msie){this._mouseUnselectable=this.element.attr("unselectable");this.element.attr("unselectable","on")}this.started=false},_mouseDestroy:function(){this.element.unbind("."+this.widgetName);(c.browser.msie&&this.element.attr("unselectable",this._mouseUnselectable))},_mouseDown:function(l){l.originalEvent=l.originalEvent||{};if(l.originalEvent.mouseHandled){return}(this._mouseStarted&&this._mouseUp(l));this._mouseDownEvent=l;var k=this,m=(l.which==1),j=(typeof this.options.cancel=="string"?c(l.target).parents().add(l.target).filter(this.options.cancel).length:false);if(!m||j||!this._mouseCapture(l)){return true}this.mouseDelayMet=!this.options.delay;if(!this.mouseDelayMet){this._mouseDelayTimer=setTimeout(function(){k.mouseDelayMet=true},this.options.delay)}if(this._mouseDistanceMet(l)&&this._mouseDelayMet(l)){this._mouseStarted=(this._mouseStart(l)!==false);if(!this._mouseStarted){l.preventDefault();return true}}this._mouseMoveDelegate=function(n){return k._mouseMove(n)};this._mouseUpDelegate=function(n){return k._mouseUp(n)};c(document).bind("mousemove."+this.widgetName,this._mouseMoveDelegate).bind("mouseup."+this.widgetName,this._mouseUpDelegate);(c.browser.safari||l.preventDefault());l.originalEvent.mouseHandled=true;return true},_mouseMove:function(j){if(c.browser.msie&&!j.button){return this._mouseUp(j)}if(this._mouseStarted){this._mouseDrag(j);return j.preventDefault()}if(this._mouseDistanceMet(j)&&this._mouseDelayMet(j)){this._mouseStarted=(this._mouseStart(this._mouseDownEvent,j)!==false);(this._mouseStarted?this._mouseDrag(j):this._mouseUp(j))}return !this._mouseStarted},_mouseUp:function(j){c(document).unbind("mousemove."+this.widgetName,this._mouseMoveDelegate).unbind("mouseup."+this.widgetName,this._mouseUpDelegate);if(this._mouseStarted){this._mouseStarted=false;this._preventClickEvent=(j.target==this._mouseDownEvent.target);this._mouseStop(j)}return false},_mouseDistanceMet:function(j){return(Math.max(Math.abs(this._mouseDownEvent.pageX-j.pageX),Math.abs(this._mouseDownEvent.pageY-j.pageY))>=this.options.distance)},_mouseDelayMet:function(j){return this.mouseDelayMet},_mouseStart:function(j){},_mouseDrag:function(j){},_mouseStop:function(j){},_mouseCapture:function(j){return true}};c.ui.mouse.defaults={cancel:null,distance:1,delay:0}})(jQuery);;/* * jQuery UI Resizable 1.7.2 + * + * Copyright (c) 2009 AUTHORS.txt (http://jqueryui.com/about) + * Dual licensed under the MIT (MIT-LICENSE.txt) + * and GPL (GPL-LICENSE.txt) licenses. + * + * http://docs.jquery.com/UI/Resizables + * + * Depends: + * ui.core.js + */ +(function(c){c.widget("ui.resizable",c.extend({},c.ui.mouse,{_init:function(){var e=this,j=this.options;this.element.addClass("ui-resizable");c.extend(this,{_aspectRatio:!!(j.aspectRatio),aspectRatio:j.aspectRatio,originalElement:this.element,_proportionallyResizeElements:[],_helper:j.helper||j.ghost||j.animate?j.helper||"ui-resizable-helper":null});if(this.element[0].nodeName.match(/canvas|textarea|input|select|button|img/i)){if(/relative/.test(this.element.css("position"))&&c.browser.opera){this.element.css({position:"relative",top:"auto",left:"auto"})}this.element.wrap(c('
    ').css({position:this.element.css("position"),width:this.element.outerWidth(),height:this.element.outerHeight(),top:this.element.css("top"),left:this.element.css("left")}));this.element=this.element.parent().data("resizable",this.element.data("resizable"));this.elementIsWrapper=true;this.element.css({marginLeft:this.originalElement.css("marginLeft"),marginTop:this.originalElement.css("marginTop"),marginRight:this.originalElement.css("marginRight"),marginBottom:this.originalElement.css("marginBottom")});this.originalElement.css({marginLeft:0,marginTop:0,marginRight:0,marginBottom:0});this.originalResizeStyle=this.originalElement.css("resize");this.originalElement.css("resize","none");this._proportionallyResizeElements.push(this.originalElement.css({position:"static",zoom:1,display:"block"}));this.originalElement.css({margin:this.originalElement.css("margin")});this._proportionallyResize()}this.handles=j.handles||(!c(".ui-resizable-handle",this.element).length?"e,s,se":{n:".ui-resizable-n",e:".ui-resizable-e",s:".ui-resizable-s",w:".ui-resizable-w",se:".ui-resizable-se",sw:".ui-resizable-sw",ne:".ui-resizable-ne",nw:".ui-resizable-nw"});if(this.handles.constructor==String){if(this.handles=="all"){this.handles="n,e,s,w,se,sw,ne,nw"}var k=this.handles.split(",");this.handles={};for(var f=0;f
    ');if(/sw|se|ne|nw/.test(h)){g.css({zIndex:++j.zIndex})}if("se"==h){g.addClass("ui-icon ui-icon-gripsmall-diagonal-se")}this.handles[h]=".ui-resizable-"+h;this.element.append(g)}}this._renderAxis=function(p){p=p||this.element;for(var m in this.handles){if(this.handles[m].constructor==String){this.handles[m]=c(this.handles[m],this.element).show()}if(this.elementIsWrapper&&this.originalElement[0].nodeName.match(/textarea|input|select|button/i)){var n=c(this.handles[m],this.element),o=0;o=/sw|ne|nw|se|n|s/.test(m)?n.outerHeight():n.outerWidth();var l=["padding",/ne|nw|n/.test(m)?"Top":/se|sw|s/.test(m)?"Bottom":/^e$/.test(m)?"Right":"Left"].join("");p.css(l,o);this._proportionallyResize()}if(!c(this.handles[m]).length){continue}}};this._renderAxis(this.element);this._handles=c(".ui-resizable-handle",this.element).disableSelection();this._handles.mouseover(function(){if(!e.resizing){if(this.className){var i=this.className.match(/ui-resizable-(se|sw|ne|nw|n|e|s|w)/i)}e.axis=i&&i[1]?i[1]:"se"}});if(j.autoHide){this._handles.hide();c(this.element).addClass("ui-resizable-autohide").hover(function(){c(this).removeClass("ui-resizable-autohide");e._handles.show()},function(){if(!e.resizing){c(this).addClass("ui-resizable-autohide");e._handles.hide()}})}this._mouseInit()},destroy:function(){this._mouseDestroy();var d=function(f){c(f).removeClass("ui-resizable ui-resizable-disabled ui-resizable-resizing").removeData("resizable").unbind(".resizable").find(".ui-resizable-handle").remove()};if(this.elementIsWrapper){d(this.element);var e=this.element;e.parent().append(this.originalElement.css({position:e.css("position"),width:e.outerWidth(),height:e.outerHeight(),top:e.css("top"),left:e.css("left")})).end().remove()}this.originalElement.css("resize",this.originalResizeStyle);d(this.originalElement)},_mouseCapture:function(e){var f=false;for(var d in this.handles){if(c(this.handles[d])[0]==e.target){f=true}}return this.options.disabled||!!f},_mouseStart:function(f){var i=this.options,e=this.element.position(),d=this.element;this.resizing=true;this.documentScroll={top:c(document).scrollTop(),left:c(document).scrollLeft()};if(d.is(".ui-draggable")||(/absolute/).test(d.css("position"))){d.css({position:"absolute",top:e.top,left:e.left})}if(c.browser.opera&&(/relative/).test(d.css("position"))){d.css({position:"relative",top:"auto",left:"auto"})}this._renderProxy();var j=b(this.helper.css("left")),g=b(this.helper.css("top"));if(i.containment){j+=c(i.containment).scrollLeft()||0;g+=c(i.containment).scrollTop()||0}this.offset=this.helper.offset();this.position={left:j,top:g};this.size=this._helper?{width:d.outerWidth(),height:d.outerHeight()}:{width:d.width(),height:d.height()};this.originalSize=this._helper?{width:d.outerWidth(),height:d.outerHeight()}:{width:d.width(),height:d.height()};this.originalPosition={left:j,top:g};this.sizeDiff={width:d.outerWidth()-d.width(),height:d.outerHeight()-d.height()};this.originalMousePosition={left:f.pageX,top:f.pageY};this.aspectRatio=(typeof i.aspectRatio=="number")?i.aspectRatio:((this.originalSize.width/this.originalSize.height)||1);var h=c(".ui-resizable-"+this.axis).css("cursor");c("body").css("cursor",h=="auto"?this.axis+"-resize":h);d.addClass("ui-resizable-resizing");this._propagate("start",f);return true},_mouseDrag:function(d){var g=this.helper,f=this.options,l={},p=this,i=this.originalMousePosition,m=this.axis;var q=(d.pageX-i.left)||0,n=(d.pageY-i.top)||0;var h=this._change[m];if(!h){return false}var k=h.apply(this,[d,q,n]),j=c.browser.msie&&c.browser.version<7,e=this.sizeDiff;if(this._aspectRatio||d.shiftKey){k=this._updateRatio(k,d)}k=this._respectSize(k,d);this._propagate("resize",d);g.css({top:this.position.top+"px",left:this.position.left+"px",width:this.size.width+"px",height:this.size.height+"px"});if(!this._helper&&this._proportionallyResizeElements.length){this._proportionallyResize()}this._updateCache(k);this._trigger("resize",d,this.ui());return false},_mouseStop:function(g){this.resizing=false;var h=this.options,l=this;if(this._helper){var f=this._proportionallyResizeElements,d=f.length&&(/textarea/i).test(f[0].nodeName),e=d&&c.ui.hasScroll(f[0],"left")?0:l.sizeDiff.height,j=d?0:l.sizeDiff.width;var m={width:(l.size.width-j),height:(l.size.height-e)},i=(parseInt(l.element.css("left"),10)+(l.position.left-l.originalPosition.left))||null,k=(parseInt(l.element.css("top"),10)+(l.position.top-l.originalPosition.top))||null;if(!h.animate){this.element.css(c.extend(m,{top:k,left:i}))}l.helper.height(l.size.height);l.helper.width(l.size.width);if(this._helper&&!h.animate){this._proportionallyResize()}}c("body").css("cursor","auto");this.element.removeClass("ui-resizable-resizing");this._propagate("stop",g);if(this._helper){this.helper.remove()}return false},_updateCache:function(d){var e=this.options;this.offset=this.helper.offset();if(a(d.left)){this.position.left=d.left}if(a(d.top)){this.position.top=d.top}if(a(d.height)){this.size.height=d.height}if(a(d.width)){this.size.width=d.width}},_updateRatio:function(g,f){var h=this.options,i=this.position,e=this.size,d=this.axis;if(g.height){g.width=(e.height*this.aspectRatio)}else{if(g.width){g.height=(e.width/this.aspectRatio)}}if(d=="sw"){g.left=i.left+(e.width-g.width);g.top=null}if(d=="nw"){g.top=i.top+(e.height-g.height);g.left=i.left+(e.width-g.width)}return g},_respectSize:function(k,f){var i=this.helper,h=this.options,q=this._aspectRatio||f.shiftKey,p=this.axis,s=a(k.width)&&h.maxWidth&&(h.maxWidthk.width),r=a(k.height)&&h.minHeight&&(h.minHeight>k.height);if(g){k.width=h.minWidth}if(r){k.height=h.minHeight}if(s){k.width=h.maxWidth}if(l){k.height=h.maxHeight}var e=this.originalPosition.left+this.originalSize.width,n=this.position.top+this.size.height;var j=/sw|nw|w/.test(p),d=/nw|ne|n/.test(p);if(g&&j){k.left=e-h.minWidth}if(s&&j){k.left=e-h.maxWidth}if(r&&d){k.top=n-h.minHeight}if(l&&d){k.top=n-h.maxHeight}var m=!k.width&&!k.height;if(m&&!k.left&&k.top){k.top=null}else{if(m&&!k.top&&k.left){k.left=null}}return k},_proportionallyResize:function(){var j=this.options;if(!this._proportionallyResizeElements.length){return}var f=this.helper||this.element;for(var e=0;e');var d=c.browser.msie&&c.browser.version<7,f=(d?1:0),g=(d?2:-1);this.helper.addClass(this._helper).css({width:this.element.outerWidth()+g,height:this.element.outerHeight()+g,position:"absolute",left:this.elementOffset.left-f+"px",top:this.elementOffset.top-f+"px",zIndex:++h.zIndex});this.helper.appendTo("body").disableSelection()}else{this.helper=this.element}},_change:{e:function(f,e,d){return{width:this.originalSize.width+e}},w:function(g,e,d){var i=this.options,f=this.originalSize,h=this.originalPosition;return{left:h.left+e,width:f.width-e}},n:function(g,e,d){var i=this.options,f=this.originalSize,h=this.originalPosition;return{top:h.top+d,height:f.height-d}},s:function(f,e,d){return{height:this.originalSize.height+d}},se:function(f,e,d){return c.extend(this._change.s.apply(this,arguments),this._change.e.apply(this,[f,e,d]))},sw:function(f,e,d){return c.extend(this._change.s.apply(this,arguments),this._change.w.apply(this,[f,e,d]))},ne:function(f,e,d){return c.extend(this._change.n.apply(this,arguments),this._change.e.apply(this,[f,e,d]))},nw:function(f,e,d){return c.extend(this._change.n.apply(this,arguments),this._change.w.apply(this,[f,e,d]))}},_propagate:function(e,d){c.ui.plugin.call(this,e,[d,this.ui()]);(e!="resize"&&this._trigger(e,d,this.ui()))},plugins:{},ui:function(){return{originalElement:this.originalElement,element:this.element,helper:this.helper,position:this.position,size:this.size,originalSize:this.originalSize,originalPosition:this.originalPosition}}}));c.extend(c.ui.resizable,{version:"1.7.2",eventPrefix:"resize",defaults:{alsoResize:false,animate:false,animateDuration:"slow",animateEasing:"swing",aspectRatio:false,autoHide:false,cancel:":input,option",containment:false,delay:0,distance:1,ghost:false,grid:false,handles:"e,s,se",helper:false,maxHeight:null,maxWidth:null,minHeight:10,minWidth:10,zIndex:1000}});c.ui.plugin.add("resizable","alsoResize",{start:function(e,f){var d=c(this).data("resizable"),g=d.options;_store=function(h){c(h).each(function(){c(this).data("resizable-alsoresize",{width:parseInt(c(this).width(),10),height:parseInt(c(this).height(),10),left:parseInt(c(this).css("left"),10),top:parseInt(c(this).css("top"),10)})})};if(typeof(g.alsoResize)=="object"&&!g.alsoResize.parentNode){if(g.alsoResize.length){g.alsoResize=g.alsoResize[0];_store(g.alsoResize)}else{c.each(g.alsoResize,function(h,i){_store(h)})}}else{_store(g.alsoResize)}},resize:function(f,h){var e=c(this).data("resizable"),i=e.options,g=e.originalSize,k=e.originalPosition;var j={height:(e.size.height-g.height)||0,width:(e.size.width-g.width)||0,top:(e.position.top-k.top)||0,left:(e.position.left-k.left)||0},d=function(l,m){c(l).each(function(){var p=c(this),q=c(this).data("resizable-alsoresize"),o={},n=m&&m.length?m:["width","height","top","left"];c.each(n||["width","height","top","left"],function(r,t){var s=(q[t]||0)+(j[t]||0);if(s&&s>=0){o[t]=s||null}});if(/relative/.test(p.css("position"))&&c.browser.opera){e._revertToRelativePosition=true;p.css({position:"absolute",top:"auto",left:"auto"})}p.css(o)})};if(typeof(i.alsoResize)=="object"&&!i.alsoResize.nodeType){c.each(i.alsoResize,function(l,m){d(l,m)})}else{d(i.alsoResize)}},stop:function(e,f){var d=c(this).data("resizable");if(d._revertToRelativePosition&&c.browser.opera){d._revertToRelativePosition=false;el.css({position:"relative"})}c(this).removeData("resizable-alsoresize-start")}});c.ui.plugin.add("resizable","animate",{stop:function(h,m){var n=c(this).data("resizable"),i=n.options;var g=n._proportionallyResizeElements,d=g.length&&(/textarea/i).test(g[0].nodeName),e=d&&c.ui.hasScroll(g[0],"left")?0:n.sizeDiff.height,k=d?0:n.sizeDiff.width;var f={width:(n.size.width-k),height:(n.size.height-e)},j=(parseInt(n.element.css("left"),10)+(n.position.left-n.originalPosition.left))||null,l=(parseInt(n.element.css("top"),10)+(n.position.top-n.originalPosition.top))||null;n.element.animate(c.extend(f,l&&j?{top:l,left:j}:{}),{duration:i.animateDuration,easing:i.animateEasing,step:function(){var o={width:parseInt(n.element.css("width"),10),height:parseInt(n.element.css("height"),10),top:parseInt(n.element.css("top"),10),left:parseInt(n.element.css("left"),10)};if(g&&g.length){c(g[0]).css({width:o.width,height:o.height})}n._updateCache(o);n._propagate("resize",h)}})}});c.ui.plugin.add("resizable","containment",{start:function(e,q){var s=c(this).data("resizable"),i=s.options,k=s.element;var f=i.containment,j=(f instanceof c)?f.get(0):(/parent/.test(f))?k.parent().get(0):f;if(!j){return}s.containerElement=c(j);if(/document/.test(f)||f==document){s.containerOffset={left:0,top:0};s.containerPosition={left:0,top:0};s.parentData={element:c(document),left:0,top:0,width:c(document).width(),height:c(document).height()||document.body.parentNode.scrollHeight}}else{var m=c(j),h=[];c(["Top","Right","Left","Bottom"]).each(function(p,o){h[p]=b(m.css("padding"+o))});s.containerOffset=m.offset();s.containerPosition=m.position();s.containerSize={height:(m.innerHeight()-h[3]),width:(m.innerWidth()-h[1])};var n=s.containerOffset,d=s.containerSize.height,l=s.containerSize.width,g=(c.ui.hasScroll(j,"left")?j.scrollWidth:l),r=(c.ui.hasScroll(j)?j.scrollHeight:d);s.parentData={element:j,left:n.left,top:n.top,width:g,height:r}}},resize:function(f,p){var s=c(this).data("resizable"),h=s.options,e=s.containerSize,n=s.containerOffset,l=s.size,m=s.position,q=s._aspectRatio||f.shiftKey,d={top:0,left:0},g=s.containerElement;if(g[0]!=document&&(/static/).test(g.css("position"))){d=n}if(m.left<(s._helper?n.left:0)){s.size.width=s.size.width+(s._helper?(s.position.left-n.left):(s.position.left-d.left));if(q){s.size.height=s.size.width/h.aspectRatio}s.position.left=h.helper?n.left:0}if(m.top<(s._helper?n.top:0)) +{s.size.height=s.size.height+(s._helper?(s.position.top-n.top):s.position.top);if(q){s.size.width=s.size.height*h.aspectRatio}s.position.top=s._helper?n.top:0}s.offset.left=s.parentData.left+s.position.left;s.offset.top=s.parentData.top+s.position.top;var k=Math.abs((s._helper?s.offset.left-d.left:(s.offset.left-d.left))+s.sizeDiff.width),r=Math.abs((s._helper?s.offset.top-d.top:(s.offset.top-n.top))+s.sizeDiff.height);var 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o=$.scrollTo=function(a,b,c){o.window().scrollTo(a,b,c)};o.defaults={axis:'y',duration:1};o.window=function(){return $($.browser.safari?'body':'html')};$.fn.scrollTo=function(l,m,n){if(typeof m=='object'){n=m;m=0}n=$.extend({},o.defaults,n);m=m||n.speed||n.duration;n.queue=n.queue&&n.axis.length>1;if(n.queue)m/=2;n.offset=j(n.offset);n.over=j(n.over);return this.each(function(){var a=this,b=$(a),t=l,c,d={},w=b.is('html,body');switch(typeof t){case'number':case'string':if(/^([+-]=)?\d+(px)?$/.test(t)){t=j(t);break}t=$(t,this);case'object':if(t.is||t.style)c=(t=$(t)).offset()}$.each(n.axis.split(''),function(i,f){var P=f=='x'?'Left':'Top',p=P.toLowerCase(),k='scroll'+P,e=a[k],D=f=='x'?'Width':'Height';if(c){d[k]=c[p]+(w?0:e-b.offset()[p]);if(n.margin){d[k]-=parseInt(t.css('margin'+P))||0;d[k]-=parseInt(t.css('border'+P+'Width'))||0}d[k]+=n.offset[p]||0;if(n.over[p])d[k]+=t[D.toLowerCase()]()*n.over[p]}else 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    + +
    + + + + + + + + + + + +
    +
    CMSIS-CORE +  Version 3.01 +
    +
    CMSIS-CORE support for Cortex-M processor-based devices
    +
    +
    + +
    + +
    + + + +
    +
    + +
    +
    +
    + +
    +
    +
    +
    Reference
    +
    +
    +
    Here is a list of all modules:
    +
    +
    + + + + + diff --git a/Libraries/CMSIS/Documentation/Core/html/nav_f.png b/Libraries/CMSIS/Documentation/Core/html/nav_f.png new file mode 100644 index 0000000000000000000000000000000000000000..ed8c4935ef6ca593ade4179c232626adcded738e GIT binary patch literal 156 zcmeAS@N?(olHy`uVBq!ia0vp^j6iI`!2~2XGqLUlQpuh!jv*C{Z|`p8J#4_^5_qcq zwn$@c;1mz9NNdJROUe^dTD0x%@hZMQKmCOGMDG69<0(gyek}QY#4RcLQq`rZMblQW zZdFa^_T%L%?UQ=*>dn.s", "startup_s_pg.html", null ], + [ "System Configuration Files system_.c and system_.h", "system_c_pg.html", null ], + [ "Device Header File ", "device_h_pg.html", null ] + ] ], + [ "MISRA-C:2004 Compliance Exceptions", "_c_o_r_e__m_i_s_r_a__exceptions_pg.html", null ], + [ "Register Mapping", "_reg_map_pg.html", null ] + ] ], + [ "Reference", "modules.html", [ + [ "Peripheral Access", "group__peripheral__gr.html", null ], + [ "System and Clock Configuration", "group__system__init__gr.html", null ], + [ "Interrupts and Exceptions (NVIC)", "group___n_v_i_c__gr.html", null ], + [ "Core Register Access", "group___core___register__gr.html", null ], + [ "Intrinsic Functions for CPU Instructions", "group__intrinsic___c_p_u__gr.html", null ], + [ "Intrinsic Functions for SIMD Instructions [only Cortex-M4]", "group__intrinsic___s_i_m_d__gr.html", null ], + [ "Systick Timer (SYSTICK)", "group___sys_tick__gr.html", null ], + [ "Debug Access", "group___i_t_m___debug__gr.html", null ] + ] ], + [ "Data Structures", "annotated.html", [ + [ "APSR_Type", "union_a_p_s_r___type.html", null ], + [ "CONTROL_Type", "union_c_o_n_t_r_o_l___type.html", null ], + [ "CoreDebug_Type", "struct_core_debug___type.html", null ], + [ "DWT_Type", "struct_d_w_t___type.html", null ], + [ "FPU_Type", "struct_f_p_u___type.html", null ], + [ "IPSR_Type", "union_i_p_s_r___type.html", null ], + [ "ITM_Type", "struct_i_t_m___type.html", null ], + [ "MPU_Type", "struct_m_p_u___type.html", null ], + [ "NVIC_Type", "struct_n_v_i_c___type.html", null ], + [ "SCB_Type", "struct_s_c_b___type.html", null ], + [ "SCnSCB_Type", "struct_s_cn_s_c_b___type.html", null ], + [ "SysTick_Type", "struct_sys_tick___type.html", null ], + [ "TPI_Type", "struct_t_p_i___type.html", null ], + [ "xPSR_Type", "unionx_p_s_r___type.html", null ] + ] ], + [ "Data Structure Index", "classes.html", null ], + [ "Data Fields", "functions.html", null ], + [ "Index", "globals.html", null ] + ] ] +]; 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    + +
    + + + + + + + + + + + +
    +
    CMSIS-CORE +  Version 3.01 +
    +
    CMSIS-CORE support for Cortex-M processor-based devices
    +
    +
    + +
    + +
    + + + +
    +
    + +
    +
    +
    + +
    +
    +
    +
    Usage and Description
    +
    +
    +
    Here is a list of all related documentation pages:
    +
    +
    + + + + + diff --git a/Libraries/CMSIS/Documentation/Core/html/resize.js b/Libraries/CMSIS/Documentation/Core/html/resize.js new file mode 100644 index 0000000..04fa95c --- /dev/null +++ b/Libraries/CMSIS/Documentation/Core/html/resize.js @@ -0,0 +1,81 @@ +var cookie_namespace = 'doxygen'; +var sidenav,navtree,content,header; + +function readCookie(cookie) +{ + var myCookie = cookie_namespace+"_"+cookie+"="; + if (document.cookie) + { + var index = document.cookie.indexOf(myCookie); + if (index != -1) + { + var valStart = index + myCookie.length; + var valEnd = document.cookie.indexOf(";", valStart); + if (valEnd == -1) + { + valEnd = document.cookie.length; + } + var val = document.cookie.substring(valStart, valEnd); + return val; + } + } + return 0; +} + +function writeCookie(cookie, val, expiration) +{ + if (val==undefined) return; + if (expiration == null) + { + var date = new Date(); + date.setTime(date.getTime()+(10*365*24*60*60*1000)); // default expiration is one week + expiration = date.toGMTString(); + } + document.cookie = cookie_namespace + "_" + cookie + "=" + val + "; expires=" + expiration+"; path=/"; +} + +function resizeWidth() +{ + var windowWidth = $(window).width() + "px"; + var sidenavWidth = $(sidenav).width(); + content.css({marginLeft:parseInt(sidenavWidth)+6+"px"}); //account for 6px-wide handle-bar + writeCookie('width',sidenavWidth, null); +} + +function restoreWidth(navWidth) +{ + var windowWidth = $(window).width() + "px"; + content.css({marginLeft:parseInt(navWidth)+6+"px"}); + sidenav.css({width:navWidth + "px"}); +} + +function resizeHeight() +{ + var headerHeight = header.height(); + var footerHeight = footer.height(); + var windowHeight = $(window).height() - headerHeight - footerHeight; + content.css({height:windowHeight + "px"}); + navtree.css({height:windowHeight + "px"}); + sidenav.css({height:windowHeight + "px",top: headerHeight+"px"}); +} + +function initResizable() +{ + header = $("#top"); + sidenav = $("#side-nav"); + content = $("#doc-content"); + navtree = $("#nav-tree"); + footer = $("#nav-path"); + $(".side-nav-resizable").resizable({resize: function(e, ui) { resizeWidth(); } }); + $(window).resize(function() { resizeHeight(); }); + var width = readCookie('width'); + if (width) { restoreWidth(width); } else { resizeWidth(); } + resizeHeight(); + var url = location.href; + var i=url.indexOf("#"); + if (i>=0) window.location.hash=url.substr(i); + var _preventDefault = function(evt) { evt.preventDefault(); }; + $("#splitbar").bind("dragstart", _preventDefault).bind("selectstart", _preventDefault); +} + + diff --git a/Libraries/CMSIS/Documentation/Core/html/search.css b/Libraries/CMSIS/Documentation/Core/html/search.css new file mode 100644 index 0000000..1746d13 --- /dev/null +++ b/Libraries/CMSIS/Documentation/Core/html/search.css @@ -0,0 +1,240 @@ +/*---------------- Search Box */ + +#FSearchBox { + float: left; +} + +#searchli { + float: right; + display: block; + width: 170px; + height: 24px; +} + +#MSearchBox { + white-space : nowrap; + position: absolute; + float: none; + display: inline; + margin-top: 3px; + right: 0px; + width: 170px; + z-index: 102; +} + +#MSearchBox .left +{ + display:block; + position:absolute; + left:10px; + width:20px; + height:19px; + background:url('search_l.png') no-repeat; + background-position:right; +} + +#MSearchSelect { + display:block; + position:absolute; + width:20px; + height:19px; +} + +.left #MSearchSelect { + left:4px; +} + +.right #MSearchSelect { + right:5px; +} + +#MSearchField { + display:block; + position:absolute; + height:19px; + background:url('search_m.png') repeat-x; + border:none; + width:116px; + margin-left:20px; + padding-left:4px; + color: #909090; + outline: none; + font: 9pt Arial, Verdana, sans-serif; +} + +#FSearchBox #MSearchField { + margin-left:15px; +} + +#MSearchBox .right { + display:block; + position:absolute; + right:10px; + top:0px; + width:20px; + height:19px; + background:url('search_r.png') no-repeat; + background-position:left; +} + +#MSearchClose { + display: none; + position: absolute; + top: 4px; + background : none; + border: none; + margin: 0px 4px 0px 0px; + padding: 0px 0px; + outline: none; +} + +.left #MSearchClose { + left: 6px; +} + +.right #MSearchClose { + right: 2px; +} + +.MSearchBoxActive #MSearchField { + color: #000000; +} + +/*---------------- Search filter selection */ + +#MSearchSelectWindow { + display: none; + position: absolute; + left: 0; top: 0; + border: 1px solid #90A5CE; + background-color: #F9FAFC; + z-index: 1; + padding-top: 4px; + padding-bottom: 4px; + -moz-border-radius: 4px; + -webkit-border-top-left-radius: 4px; + -webkit-border-top-right-radius: 4px; + -webkit-border-bottom-left-radius: 4px; + -webkit-border-bottom-right-radius: 4px; + -webkit-box-shadow: 5px 5px 5px rgba(0, 0, 0, 0.15); +} + +.SelectItem { + font: 8pt Arial, Verdana, sans-serif; + padding-left: 2px; + padding-right: 12px; + border: 0px; +} + +span.SelectionMark { + margin-right: 4px; + font-family: monospace; + outline-style: none; + text-decoration: none; +} + +a.SelectItem { + display: block; + outline-style: none; + color: #000000; + text-decoration: none; + padding-left: 6px; + padding-right: 12px; +} + +a.SelectItem:focus, +a.SelectItem:active { + color: #000000; + outline-style: none; + text-decoration: none; +} + +a.SelectItem:hover { + color: #FFFFFF; + background-color: #3D578C; + outline-style: none; + text-decoration: none; + cursor: pointer; + display: block; +} + +/*---------------- Search results window */ + +iframe#MSearchResults { + width: 60ex; + height: 15em; +} + +#MSearchResultsWindow { + display: none; + position: absolute; + left: 0; top: 0; + border: 1px solid #000; + background-color: #EEF1F7; +} + +/* ----------------------------------- */ + + +#SRIndex { + clear:both; + padding-bottom: 15px; +} + +.SREntry { + font-size: 10pt; + padding-left: 1ex; +} + +.SRPage .SREntry { + font-size: 8pt; + padding: 1px 5px; +} + +body.SRPage { + margin: 5px 2px; +} + +.SRChildren { + padding-left: 3ex; padding-bottom: .5em +} + +.SRPage .SRChildren { + display: none; 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    +
    Loading...
    +
    +
    + __CLREX + Ref_cmInstr.txt +
    +
    +
    +
    + __CLZ + Ref_cmInstr.txt +
    +
    +
    +
    + __disable_fault_irq + Ref_CoreReg.txt +
    +
    +
    +
    + __disable_irq + Ref_CoreReg.txt +
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    +
    + __DMB + Ref_cmInstr.txt +
    +
    +
    +
    + __DSB + Ref_cmInstr.txt +
    +
    +
    +
    + __enable_fault_irq + Ref_CoreReg.txt +
    +
    +
    +
    + __enable_irq + Ref_CoreReg.txt +
    +
    +
    +
    + __get_APSR + Ref_CoreReg.txt +
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    +
    +
    + __get_BASEPRI + Ref_CoreReg.txt +
    +
    +
    +
    + __get_CONTROL + Ref_CoreReg.txt +
    +
    +
    +
    + __get_FAULTMASK + Ref_CoreReg.txt +
    +
    +
    +
    + __get_FPSCR + Ref_CoreReg.txt +
    +
    +
    +
    + __get_IPSR + Ref_CoreReg.txt +
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    +
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    +
    + __get_PRIMASK + Ref_CoreReg.txt +
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    +
    +
    + __get_PSP + Ref_CoreReg.txt +
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    +
    +
    + __get_xPSR + Ref_CoreReg.txt +
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    +
    +
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    +
    + __LDREXB + Ref_cmInstr.txt +
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    +
    +
    + __LDREXH + Ref_cmInstr.txt +
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    +
    +
    + __LDREXW + Ref_cmInstr.txt +
    +
    +
    +
    + __NOP + Ref_cmInstr.txt +
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    +
    + __PKHBT + Ref_cm4_simd.txt +
    +
    +
    +
    + __PKHTB + Ref_cm4_simd.txt +
    +
    +
    +
    + __QADD + Ref_cm4_simd.txt +
    +
    +
    +
    + __QADD16 + Ref_cm4_simd.txt +
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    +
    + __QADD8 + Ref_cm4_simd.txt +
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    +
    +
    + __QASX + Ref_cm4_simd.txt +
    +
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    +
    + __QSAX + Ref_cm4_simd.txt +
    +
    +
    +
    + __QSUB + Ref_cm4_simd.txt +
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    +
    + __QSUB16 + Ref_cm4_simd.txt +
    +
    +
    +
    + __QSUB8 + Ref_cm4_simd.txt +
    +
    +
    +
    + __RBIT + Ref_cmInstr.txt +
    +
    +
    +
    + __REV + Ref_cmInstr.txt +
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    +
    +
    + __REV16 + Ref_cmInstr.txt +
    +
    +
    +
    + __REVSH + Ref_cmInstr.txt +
    +
    +
    +
    + __ROR + Ref_cmInstr.txt +
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    +
    +
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    +
    +
    + __SADD8 + Ref_cm4_simd.txt +
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    +
    +
    + __SASX + Ref_cm4_simd.txt +
    +
    +
    +
    + __SEL + Ref_cm4_simd.txt +
    +
    +
    +
    + __set_BASEPRI + Ref_CoreReg.txt +
    +
    +
    +
    + __set_CONTROL + Ref_CoreReg.txt +
    +
    +
    +
    + __set_FAULTMASK + Ref_CoreReg.txt +
    +
    +
    +
    + __set_FPSCR + Ref_CoreReg.txt +
    +
    +
    +
    + __set_MSP + Ref_CoreReg.txt +
    +
    +
    +
    + __set_PRIMASK + Ref_CoreReg.txt +
    +
    +
    +
    + __set_PSP + Ref_CoreReg.txt +
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    +
    + __SEV + Ref_cmInstr.txt +
    +
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    +
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    +
    +
    + __SHADD8 + Ref_cm4_simd.txt +
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    +
    + __SHSAX + Ref_cm4_simd.txt +
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    +
    +
    + __SHSUB16 + Ref_cm4_simd.txt +
    +
    +
    +
    + __SHSUB8 + Ref_cm4_simd.txt +
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    + __SMLAD + Ref_cm4_simd.txt +
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    + __SMLADX + Ref_cm4_simd.txt +
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    +
    + __SMLALDX + Ref_cm4_simd.txt +
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    + __SMLSD + Ref_cm4_simd.txt +
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    + __SMLSDX + Ref_cm4_simd.txt +
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    +
    + __SMLSLD + Ref_cm4_simd.txt +
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    + __SMLSLDX + Ref_cm4_simd.txt +
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    + __SMUAD + Ref_cm4_simd.txt +
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    +
    + __SMUADX + Ref_cm4_simd.txt +
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    +
    + __SMUSDX + Ref_cm4_simd.txt +
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    +
    + __SSUB16 + Ref_cm4_simd.txt +
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    + __SSUB8 + Ref_cm4_simd.txt +
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    +
    +
    + __STREXB + Ref_cmInstr.txt +
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    + __STREXH + Ref_cmInstr.txt +
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    +
    +
    + __STREXW + Ref_cmInstr.txt +
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    +
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    +
    +
    + __SXTB16 + Ref_cm4_simd.txt +
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    +
    + __UADD16 + Ref_cm4_simd.txt +
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    +
    +
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    + __UHADD16 + Ref_cm4_simd.txt +
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    +
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    + __UHASX + Ref_cm4_simd.txt +
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    +
    + __UHSAX + Ref_cm4_simd.txt +
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    + __UHSUB16 + Ref_cm4_simd.txt +
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    + __UHSUB8 + Ref_cm4_simd.txt +
    +
    +
    +
    + __UQADD16 + Ref_cm4_simd.txt +
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    +
    +
    + __UQADD8 + Ref_cm4_simd.txt +
    +
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    +
    + __UQASX + Ref_cm4_simd.txt +
    +
    +
    +
    + __UQSAX + Ref_cm4_simd.txt +
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    +
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    + __UQSUB16 + Ref_cm4_simd.txt +
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    +
    +
    + __UQSUB8 + Ref_cm4_simd.txt +
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    +
    +
    + __USAD8 + Ref_cm4_simd.txt +
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    +
    +
    + __USADA8 + Ref_cm4_simd.txt +
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    +
    +
    + __USAT + Ref_cmInstr.txt +
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    +
    + __USAT16 + Ref_cm4_simd.txt +
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    +
    +
    + __USAX + Ref_cm4_simd.txt +
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    +
    +
    + __USUB16 + Ref_cm4_simd.txt +
    +
    +
    +
    + __USUB8 + Ref_cm4_simd.txt +
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    +
    +
    + __UXTAB16 + Ref_cm4_simd.txt +
    +
    +
    +
    + __UXTB16 + Ref_cm4_simd.txt +
    +
    +
    +
    + __WFE + Ref_cmInstr.txt +
    +
    +
    +
    + __WFI + Ref_cmInstr.txt +
    +
    +
    +
    + _reserved0 +
    + APSR_Type::_reserved0() + IPSR_Type::_reserved0() + xPSR_Type::_reserved0() + CONTROL_Type::_reserved0() +
    +
    +
    +
    Searching...
    +
    No Matches
    + +
    + + diff --git a/Libraries/CMSIS/Documentation/Core/html/search/all_61.html b/Libraries/CMSIS/Documentation/Core/html/search/all_61.html new file mode 100644 index 0000000..e4f1a97 --- /dev/null +++ b/Libraries/CMSIS/Documentation/Core/html/search/all_61.html @@ -0,0 +1,55 @@ + + + + + + + +
    +
    Loading...
    +
    +
    + ACPR + TPI_Type +
    +
    +
    +
    + ACTLR + SCnSCB_Type +
    +
    +
    +
    + ADR + SCB_Type +
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    +
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    +
    +
    + AIRCR + SCB_Type +
    +
    +
    +
    + APSR_Type +
    +
    +
    Searching...
    +
    No Matches
    + +
    + + diff --git a/Libraries/CMSIS/Documentation/Core/html/search/all_62.html b/Libraries/CMSIS/Documentation/Core/html/search/all_62.html new file mode 100644 index 0000000..aa9d4dc --- /dev/null +++ b/Libraries/CMSIS/Documentation/Core/html/search/all_62.html @@ -0,0 +1,43 @@ + + + + + + + +
    +
    Loading...
    + +
    +
    + BFAR + SCB_Type +
    +
    +
    +
    + BusFault_IRQn + Ref_NVIC.txt +
    +
    +
    Searching...
    +
    No Matches
    + +
    + + diff --git a/Libraries/CMSIS/Documentation/Core/html/search/all_63.html b/Libraries/CMSIS/Documentation/Core/html/search/all_63.html new file mode 100644 index 0000000..d49655a --- /dev/null +++ b/Libraries/CMSIS/Documentation/Core/html/search/all_63.html @@ -0,0 +1,133 @@ + + + + + + + +
    +
    Loading...
    + +
    +
    + CALIB + SysTick_Type +
    +
    +
    +
    + CCR + SCB_Type +
    +
    +
    +
    + CFSR + SCB_Type +
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    +
    + CLAIMCLR + TPI_Type +
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    +
    + CLAIMSET + TPI_Type +
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    +
    +
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    +
    +
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    +
    +
    + COMP2 + DWT_Type +
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    +
    +
    + COMP3 + DWT_Type +
    +
    +
    +
    + CONTROL_Type +
    +
    + +
    +
    + CPACR + SCB_Type +
    +
    +
    +
    + CPICNT + DWT_Type +
    +
    +
    +
    + CPUID + SCB_Type +
    +
    +
    +
    + CSPSR + TPI_Type +
    +
    + +
    +
    + CYCCNT + DWT_Type +
    +
    +
    Searching...
    +
    No Matches
    + +
    + + diff --git a/Libraries/CMSIS/Documentation/Core/html/search/all_64.html b/Libraries/CMSIS/Documentation/Core/html/search/all_64.html new file mode 100644 index 0000000..7f145c7 --- /dev/null +++ b/Libraries/CMSIS/Documentation/Core/html/search/all_64.html @@ -0,0 +1,79 @@ + + + + + + + +
    +
    Loading...
    +
    +
    + DCRDR + CoreDebug_Type +
    +
    +
    +
    + DCRSR + CoreDebug_Type +
    +
    +
    +
    + DebugMonitor_IRQn + Ref_NVIC.txt +
    +
    +
    +
    + DEMCR + CoreDebug_Type +
    +
    +
    +
    + DEVID + TPI_Type +
    +
    +
    +
    + DEVTYPE + TPI_Type +
    +
    +
    +
    + DFR + SCB_Type +
    +
    +
    +
    + DFSR + SCB_Type +
    +
    +
    +
    + DHCSR + CoreDebug_Type +
    +
    +
    +
    + DWT_Type +
    +
    +
    Searching...
    +
    No Matches
    + +
    + + diff --git a/Libraries/CMSIS/Documentation/Core/html/search/all_65.html b/Libraries/CMSIS/Documentation/Core/html/search/all_65.html new file mode 100644 index 0000000..b3db09d --- /dev/null +++ b/Libraries/CMSIS/Documentation/Core/html/search/all_65.html @@ -0,0 +1,26 @@ + + + + + + + +
    +
    Loading...
    +
    +
    + EXCCNT + DWT_Type +
    +
    +
    Searching...
    +
    No Matches
    + +
    + + diff --git a/Libraries/CMSIS/Documentation/Core/html/search/all_66.html b/Libraries/CMSIS/Documentation/Core/html/search/all_66.html new file mode 100644 index 0000000..74554be --- /dev/null +++ b/Libraries/CMSIS/Documentation/Core/html/search/all_66.html @@ -0,0 +1,109 @@ + + + + + + + +
    +
    Loading...
    +
    +
    + FFCR + TPI_Type +
    +
    +
    +
    + FFSR + TPI_Type +
    +
    +
    +
    + FIFO0 + TPI_Type +
    +
    +
    +
    + FIFO1 + TPI_Type +
    +
    +
    +
    + FOLDCNT + DWT_Type +
    +
    +
    +
    + FPCA + CONTROL_Type +
    +
    +
    +
    + FPCAR + FPU_Type +
    +
    +
    +
    + FPCCR + FPU_Type +
    +
    +
    +
    + FPDSCR + FPU_Type +
    +
    +
    +
    + FPU_Type +
    +
    +
    +
    + FSCR + TPI_Type +
    +
    +
    +
    + FUNCTION0 + DWT_Type +
    +
    +
    +
    + FUNCTION1 + DWT_Type +
    +
    +
    +
    + FUNCTION2 + DWT_Type +
    +
    +
    +
    + FUNCTION3 + DWT_Type +
    +
    +
    Searching...
    +
    No Matches
    + +
    + + diff --git a/Libraries/CMSIS/Documentation/Core/html/search/all_68.html b/Libraries/CMSIS/Documentation/Core/html/search/all_68.html new file mode 100644 index 0000000..db6d192 --- /dev/null +++ b/Libraries/CMSIS/Documentation/Core/html/search/all_68.html @@ -0,0 +1,32 @@ + + + + + + + +
    +
    Loading...
    +
    +
    + HardFault_IRQn + Ref_NVIC.txt +
    +
    +
    +
    + HFSR + SCB_Type +
    +
    +
    Searching...
    +
    No Matches
    + +
    + + diff --git a/Libraries/CMSIS/Documentation/Core/html/search/all_69.html b/Libraries/CMSIS/Documentation/Core/html/search/all_69.html new file mode 100644 index 0000000..704a08c --- /dev/null +++ b/Libraries/CMSIS/Documentation/Core/html/search/all_69.html @@ -0,0 +1,147 @@ + + + + + + + +
    +
    Loading...
    +
    +
    + IABR + NVIC_Type +
    +
    +
    +
    + ICER + NVIC_Type +
    +
    +
    +
    + ICPR + NVIC_Type +
    +
    +
    +
    + ICSR + SCB_Type +
    +
    +
    +
    + ICTR + SCnSCB_Type +
    +
    +
    +
    + IP + NVIC_Type +
    +
    +
    +
    + IPSR_Type +
    +
    +
    +
    + IRQn_Type + Ref_NVIC.txt +
    +
    +
    +
    + ISAR + SCB_Type +
    +
    +
    +
    + ISER + NVIC_Type +
    +
    +
    +
    + ISPR + NVIC_Type +
    +
    + +
    +
    + IT + xPSR_Type +
    +
    +
    +
    + ITATBCTR0 + TPI_Type +
    +
    +
    +
    + ITATBCTR2 + TPI_Type +
    +
    +
    +
    + ITCTRL + TPI_Type +
    +
    +
    +
    + ITM_CheckChar + Ref_Debug.txt +
    +
    +
    +
    + ITM_ReceiveChar + Ref_Debug.txt +
    +
    +
    +
    + ITM_RxBuffer + Ref_Debug.txt +
    +
    +
    +
    + ITM_SendChar + Ref_Debug.txt +
    +
    +
    +
    + ITM_Type +
    +
    +
    Searching...
    +
    No Matches
    + +
    + + diff --git a/Libraries/CMSIS/Documentation/Core/html/search/all_6c.html b/Libraries/CMSIS/Documentation/Core/html/search/all_6c.html new file mode 100644 index 0000000..337c839 --- /dev/null +++ b/Libraries/CMSIS/Documentation/Core/html/search/all_6c.html @@ -0,0 +1,32 @@ + + + + + + + +
    +
    Loading...
    +
    +
    + LOAD + SysTick_Type +
    +
    +
    +
    + LSUCNT + DWT_Type +
    +
    +
    Searching...
    +
    No Matches
    + +
    + + diff --git a/Libraries/CMSIS/Documentation/Core/html/search/all_6d.html b/Libraries/CMSIS/Documentation/Core/html/search/all_6d.html new file mode 100644 index 0000000..540c1dd --- /dev/null +++ b/Libraries/CMSIS/Documentation/Core/html/search/all_6d.html @@ -0,0 +1,84 @@ + + + + + + + +
    +
    Loading...
    +
    +
    + MASK0 + DWT_Type +
    +
    +
    +
    + MASK1 + DWT_Type +
    +
    +
    +
    + MASK2 + DWT_Type +
    +
    +
    +
    + MASK3 + DWT_Type +
    +
    +
    +
    + MemoryManagement_IRQn + Ref_NVIC.txt +
    +
    +
    +
    + MISRA.txt +
    +
    +
    +
    + MMFAR + SCB_Type +
    +
    +
    +
    + MMFR + SCB_Type +
    +
    +
    +
    + MPU_Type +
    +
    +
    +
    + MVFR0 + FPU_Type +
    +
    +
    +
    + MVFR1 + FPU_Type +
    +
    +
    Searching...
    +
    No Matches
    + +
    + + diff --git a/Libraries/CMSIS/Documentation/Core/html/search/all_6e.html b/Libraries/CMSIS/Documentation/Core/html/search/all_6e.html new file mode 100644 index 0000000..f534a31 --- /dev/null +++ b/Libraries/CMSIS/Documentation/Core/html/search/all_6e.html @@ -0,0 +1,124 @@ + + + + + + + +
    +
    Loading...
    + +
    +
    + NonMaskableInt_IRQn + Ref_NVIC.txt +
    +
    +
    +
    + nPRIV + CONTROL_Type +
    +
    +
    +
    + NVIC_ClearPendingIRQ + Ref_NVIC.txt +
    +
    +
    +
    + NVIC_DecodePriority + Ref_NVIC.txt +
    +
    +
    +
    + NVIC_DisableIRQ + Ref_NVIC.txt +
    +
    +
    +
    + NVIC_EnableIRQ + Ref_NVIC.txt +
    +
    +
    +
    + NVIC_EncodePriority + Ref_NVIC.txt +
    +
    +
    +
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    Searching...
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    + + diff --git a/Libraries/CMSIS/Documentation/Core/html/search/enumvalues_73.html b/Libraries/CMSIS/Documentation/Core/html/search/enumvalues_73.html new file mode 100644 index 0000000..08e3fcc --- /dev/null +++ b/Libraries/CMSIS/Documentation/Core/html/search/enumvalues_73.html @@ -0,0 +1,32 @@ + + + + + + + +
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    Loading...
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    +
    Searching...
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    No Matches
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    + + diff --git a/Libraries/CMSIS/Documentation/Core/html/search/enumvalues_75.html b/Libraries/CMSIS/Documentation/Core/html/search/enumvalues_75.html new file mode 100644 index 0000000..8c4b0e1 --- /dev/null +++ b/Libraries/CMSIS/Documentation/Core/html/search/enumvalues_75.html @@ -0,0 +1,26 @@ + + + + + + + +
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    Searching...
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    + + diff --git a/Libraries/CMSIS/Documentation/Core/html/search/enumvalues_77.html b/Libraries/CMSIS/Documentation/Core/html/search/enumvalues_77.html new file mode 100644 index 0000000..748b4d8 --- /dev/null +++ b/Libraries/CMSIS/Documentation/Core/html/search/enumvalues_77.html @@ -0,0 +1,26 @@ + + + + + + + +
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    Loading...
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    Searching...
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    Loading...
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    + + diff --git a/Libraries/CMSIS/Documentation/Core/html/search/functions_5f.html b/Libraries/CMSIS/Documentation/Core/html/search/functions_5f.html new file mode 100644 index 0000000..b4c96cd --- /dev/null +++ b/Libraries/CMSIS/Documentation/Core/html/search/functions_5f.html @@ -0,0 +1,644 @@ + + + + + + + +
    +
    Loading...
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    + __CLREX + Ref_cmInstr.txt +
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    +
    + __CLZ + Ref_cmInstr.txt +
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    +
    + __disable_fault_irq + Ref_CoreReg.txt +
    +
    +
    +
    + __disable_irq + Ref_CoreReg.txt +
    +
    +
    +
    + __DMB + Ref_cmInstr.txt +
    +
    +
    +
    + __DSB + Ref_cmInstr.txt +
    +
    +
    +
    + __enable_fault_irq + Ref_CoreReg.txt +
    +
    +
    +
    + __enable_irq + Ref_CoreReg.txt +
    +
    +
    +
    + __get_APSR + Ref_CoreReg.txt +
    +
    +
    +
    + __get_BASEPRI + Ref_CoreReg.txt +
    +
    +
    +
    + __get_CONTROL + Ref_CoreReg.txt +
    +
    +
    +
    + __get_FAULTMASK + Ref_CoreReg.txt +
    +
    +
    +
    + __get_FPSCR + Ref_CoreReg.txt +
    +
    +
    +
    + __get_IPSR + Ref_CoreReg.txt +
    +
    +
    +
    + __get_MSP + Ref_CoreReg.txt +
    +
    +
    +
    + __get_PRIMASK + Ref_CoreReg.txt +
    +
    +
    +
    + __get_PSP + Ref_CoreReg.txt +
    +
    +
    +
    + __get_xPSR + Ref_CoreReg.txt +
    +
    +
    +
    + __ISB + Ref_cmInstr.txt +
    +
    +
    +
    + __LDREXB + Ref_cmInstr.txt +
    +
    +
    +
    + __LDREXH + Ref_cmInstr.txt +
    +
    +
    +
    + __LDREXW + Ref_cmInstr.txt +
    +
    +
    +
    + __NOP + Ref_cmInstr.txt +
    +
    +
    +
    + __PKHBT + Ref_cm4_simd.txt +
    +
    +
    +
    + __PKHTB + Ref_cm4_simd.txt +
    +
    +
    +
    + __QADD + Ref_cm4_simd.txt +
    +
    +
    +
    + __QADD16 + Ref_cm4_simd.txt +
    +
    +
    +
    + __QADD8 + Ref_cm4_simd.txt +
    +
    +
    +
    + __QASX + Ref_cm4_simd.txt +
    +
    +
    +
    + __QSAX + Ref_cm4_simd.txt +
    +
    +
    +
    + __QSUB + Ref_cm4_simd.txt +
    +
    +
    +
    + __QSUB16 + Ref_cm4_simd.txt +
    +
    +
    +
    + __QSUB8 + Ref_cm4_simd.txt +
    +
    +
    +
    + __RBIT + Ref_cmInstr.txt +
    +
    +
    +
    + __REV + Ref_cmInstr.txt +
    +
    +
    +
    + __REV16 + Ref_cmInstr.txt +
    +
    +
    +
    + __REVSH + Ref_cmInstr.txt +
    +
    +
    +
    + __ROR + Ref_cmInstr.txt +
    +
    +
    +
    + __SADD16 + Ref_cm4_simd.txt +
    +
    +
    +
    + __SADD8 + Ref_cm4_simd.txt +
    +
    +
    +
    + __SASX + Ref_cm4_simd.txt +
    +
    +
    +
    + __SEL + Ref_cm4_simd.txt +
    +
    +
    +
    + __set_BASEPRI + Ref_CoreReg.txt +
    +
    +
    +
    + __set_CONTROL + Ref_CoreReg.txt +
    +
    +
    +
    + __set_FAULTMASK + Ref_CoreReg.txt +
    +
    +
    +
    + __set_FPSCR + Ref_CoreReg.txt +
    +
    +
    +
    + __set_MSP + Ref_CoreReg.txt +
    +
    +
    +
    + __set_PRIMASK + Ref_CoreReg.txt +
    +
    +
    +
    + __set_PSP + Ref_CoreReg.txt +
    +
    +
    +
    + __SEV + Ref_cmInstr.txt +
    +
    +
    +
    + __SHADD16 + Ref_cm4_simd.txt +
    +
    +
    +
    + __SHADD8 + Ref_cm4_simd.txt +
    +
    +
    +
    + __SHASX + Ref_cm4_simd.txt +
    +
    +
    +
    + __SHSAX + Ref_cm4_simd.txt +
    +
    +
    +
    + __SHSUB16 + Ref_cm4_simd.txt +
    +
    +
    +
    + __SHSUB8 + Ref_cm4_simd.txt +
    +
    +
    +
    + __SMLAD + Ref_cm4_simd.txt +
    +
    +
    +
    + __SMLADX + Ref_cm4_simd.txt +
    +
    +
    +
    + __SMLALD + Ref_cm4_simd.txt +
    +
    +
    +
    + __SMLALDX + Ref_cm4_simd.txt +
    +
    +
    +
    + __SMLSD + Ref_cm4_simd.txt +
    +
    +
    +
    + __SMLSDX + Ref_cm4_simd.txt +
    +
    +
    +
    + __SMLSLD + Ref_cm4_simd.txt +
    +
    +
    +
    + __SMLSLDX + Ref_cm4_simd.txt +
    +
    +
    +
    + __SMUAD + Ref_cm4_simd.txt +
    +
    +
    +
    + __SMUADX + Ref_cm4_simd.txt +
    +
    +
    +
    + __SMUSD + Ref_cm4_simd.txt +
    +
    +
    +
    + __SMUSDX + Ref_cm4_simd.txt +
    +
    +
    +
    + __SSAT + Ref_cmInstr.txt +
    +
    +
    +
    + __SSAT16 + Ref_cm4_simd.txt +
    +
    +
    +
    + __SSAX + Ref_cm4_simd.txt +
    +
    +
    +
    + __SSUB16 + Ref_cm4_simd.txt +
    +
    +
    +
    + __SSUB8 + Ref_cm4_simd.txt +
    +
    +
    +
    + __STREXB + Ref_cmInstr.txt +
    +
    +
    +
    + __STREXH + Ref_cmInstr.txt +
    +
    +
    +
    + __STREXW + Ref_cmInstr.txt +
    +
    +
    +
    + __SXTAB16 + Ref_cm4_simd.txt +
    +
    +
    +
    + __SXTB16 + Ref_cm4_simd.txt +
    +
    +
    +
    + __UADD16 + Ref_cm4_simd.txt +
    +
    +
    +
    + __UADD8 + Ref_cm4_simd.txt +
    +
    +
    +
    + __UASX + Ref_cm4_simd.txt +
    +
    +
    +
    + __UHADD16 + Ref_cm4_simd.txt +
    +
    +
    +
    + __UHADD8 + Ref_cm4_simd.txt +
    +
    +
    +
    + __UHASX + Ref_cm4_simd.txt +
    +
    +
    +
    + __UHSAX + Ref_cm4_simd.txt +
    +
    +
    +
    + __UHSUB16 + Ref_cm4_simd.txt +
    +
    +
    +
    + __UHSUB8 + Ref_cm4_simd.txt +
    +
    +
    +
    + __UQADD16 + Ref_cm4_simd.txt +
    +
    +
    +
    + __UQADD8 + Ref_cm4_simd.txt +
    +
    +
    +
    + __UQASX + Ref_cm4_simd.txt +
    +
    +
    +
    + __UQSAX + Ref_cm4_simd.txt +
    +
    +
    +
    + __UQSUB16 + Ref_cm4_simd.txt +
    +
    +
    +
    + __UQSUB8 + Ref_cm4_simd.txt +
    +
    +
    +
    + __USAD8 + Ref_cm4_simd.txt +
    +
    +
    +
    + __USADA8 + Ref_cm4_simd.txt +
    +
    +
    +
    + __USAT + Ref_cmInstr.txt +
    +
    +
    +
    + __USAT16 + Ref_cm4_simd.txt +
    +
    +
    +
    + __USAX + Ref_cm4_simd.txt +
    +
    +
    +
    + __USUB16 + Ref_cm4_simd.txt +
    +
    +
    +
    + __USUB8 + Ref_cm4_simd.txt +
    +
    +
    +
    + __UXTAB16 + Ref_cm4_simd.txt +
    +
    +
    +
    + __UXTB16 + Ref_cm4_simd.txt +
    +
    +
    +
    + __WFE + Ref_cmInstr.txt +
    +
    +
    +
    + __WFI + Ref_cmInstr.txt +
    +
    +
    Searching...
    +
    No Matches
    + +
    + + diff --git a/Libraries/CMSIS/Documentation/Core/html/search/functions_69.html b/Libraries/CMSIS/Documentation/Core/html/search/functions_69.html new file mode 100644 index 0000000..073a792 --- /dev/null +++ b/Libraries/CMSIS/Documentation/Core/html/search/functions_69.html @@ -0,0 +1,38 @@ + + + + + + + +
    +
    Loading...
    +
    +
    + ITM_CheckChar + Ref_Debug.txt +
    +
    +
    +
    + ITM_ReceiveChar + Ref_Debug.txt +
    +
    +
    +
    + ITM_SendChar + Ref_Debug.txt +
    +
    +
    Searching...
    +
    No Matches
    + +
    + + diff --git a/Libraries/CMSIS/Documentation/Core/html/search/functions_6e.html b/Libraries/CMSIS/Documentation/Core/html/search/functions_6e.html new file mode 100644 index 0000000..f85ddec --- /dev/null +++ b/Libraries/CMSIS/Documentation/Core/html/search/functions_6e.html @@ -0,0 +1,98 @@ + + + + + + + +
    +
    Loading...
    +
    +
    + NVIC_ClearPendingIRQ + Ref_NVIC.txt +
    +
    +
    +
    + NVIC_DecodePriority + Ref_NVIC.txt +
    +
    +
    +
    + NVIC_DisableIRQ + Ref_NVIC.txt +
    +
    +
    +
    + NVIC_EnableIRQ + Ref_NVIC.txt +
    +
    +
    +
    + NVIC_EncodePriority + Ref_NVIC.txt +
    +
    +
    +
    + NVIC_GetActive + Ref_NVIC.txt +
    +
    +
    +
    + NVIC_GetPendingIRQ + Ref_NVIC.txt +
    +
    +
    +
    + NVIC_GetPriority + Ref_NVIC.txt +
    +
    +
    +
    + NVIC_GetPriorityGrouping + Ref_NVIC.txt +
    +
    +
    +
    + NVIC_SetPendingIRQ + Ref_NVIC.txt +
    +
    +
    +
    + NVIC_SetPriority + Ref_NVIC.txt +
    +
    +
    +
    + NVIC_SetPriorityGrouping + Ref_NVIC.txt +
    +
    +
    +
    + NVIC_SystemReset + Ref_NVIC.txt +
    +
    +
    Searching...
    +
    No Matches
    + +
    + + diff --git a/Libraries/CMSIS/Documentation/Core/html/search/functions_73.html b/Libraries/CMSIS/Documentation/Core/html/search/functions_73.html new file mode 100644 index 0000000..add7be0 --- /dev/null +++ b/Libraries/CMSIS/Documentation/Core/html/search/functions_73.html @@ -0,0 +1,38 @@ + + + + + + + +
    +
    Loading...
    +
    +
    + SystemCoreClockUpdate + Ref_SystemAndClock.txt +
    +
    +
    +
    + SystemInit + Ref_SystemAndClock.txt +
    +
    +
    +
    + SysTick_Config + Ref_Systick.txt +
    +
    +
    Searching...
    +
    No Matches
    + +
    + + diff --git a/Libraries/CMSIS/Documentation/Core/html/search/mag_sel.png b/Libraries/CMSIS/Documentation/Core/html/search/mag_sel.png new file mode 100644 index 0000000000000000000000000000000000000000..81f6040a2092402b4d98f9ffa8855d12a0d4ca17 GIT binary patch literal 563 zcmV-30?hr1P)zxx&tqG15pu7)IiiXFflOc2k;dXd>%13GZAy? zRz!q0=|E6a6vV)&ZBS~G9oe0kbqyw1*gvY`{Pop2oKq#FlzgXt@Xh-7fxh>}`Fxg> z$%N%{$!4=5nM{(;=c!aG1Ofr^Do{u%Ih{^&Fc@H2)+a-?TBXrw5DW&z%Nb6mQ!L9O zl}b@6mB?f=tX3;#vl)}ggh(Vpyh(IK z(Mb0D{l{U$FsRjP;!{($+bsaaVi8T#1c0V#qEIOCYa9@UVLV`f__E81L;?WEaRA;Y zUH;rZ;vb;mk7JX|$=i3O~&If0O@oZfLg8gfIjW=dcBsz;gI=!{-r4# z4%6v$&~;q^j7Fo67yJ(NJWuX+I~I!tj^nW3?}^9bq|<3^+vapS5sgM^x7!cs(+mMT z&y%j};&~po+YO)3hoUH4E*E;e9>?R6SS&`X)p`njycAVcg{rEb41T{~Hk(bl-7eSb zmFxA2uIqo#@R?lKm50ND`~6Nfn|-b1|L6O98vt3Tx@gKz#isxO002ovPDHLkV1kyW B_l^Jn literal 0 HcmV?d00001 diff --git a/Libraries/CMSIS/Documentation/Core/html/search/nomatches.html b/Libraries/CMSIS/Documentation/Core/html/search/nomatches.html new file mode 100644 index 0000000..b1ded27 --- /dev/null +++ b/Libraries/CMSIS/Documentation/Core/html/search/nomatches.html @@ -0,0 +1,12 @@ + + + + + + + +
    +
    No Matches
    +
    + + diff --git a/Libraries/CMSIS/Documentation/Core/html/search/search.css b/Libraries/CMSIS/Documentation/Core/html/search/search.css new file mode 100644 index 0000000..1746d13 --- /dev/null +++ b/Libraries/CMSIS/Documentation/Core/html/search/search.css @@ -0,0 +1,240 @@ +/*---------------- Search Box */ + +#FSearchBox { + float: left; +} + +#searchli { + float: right; + display: block; + width: 170px; + height: 24px; +} + +#MSearchBox { + white-space : nowrap; + position: absolute; + float: none; + display: inline; + margin-top: 3px; + right: 0px; + width: 170px; + z-index: 102; +} + +#MSearchBox .left +{ + display:block; + position:absolute; + left:10px; + width:20px; + height:19px; + background:url('search_l.png') no-repeat; + background-position:right; +} + +#MSearchSelect { + display:block; + position:absolute; + width:20px; + height:19px; +} + +.left #MSearchSelect { + left:4px; +} + +.right #MSearchSelect { + right:5px; +} + +#MSearchField { + display:block; + position:absolute; + height:19px; + background:url('search_m.png') repeat-x; + border:none; + width:116px; + margin-left:20px; + padding-left:4px; + color: #909090; + outline: none; + font: 9pt Arial, Verdana, sans-serif; +} + +#FSearchBox #MSearchField { + margin-left:15px; +} + +#MSearchBox .right { + display:block; + position:absolute; + right:10px; + top:0px; + width:20px; + height:19px; + background:url('search_r.png') no-repeat; + background-position:left; +} + +#MSearchClose { + display: none; + position: absolute; + top: 4px; + background : none; + border: none; + margin: 0px 4px 0px 0px; + padding: 0px 0px; + outline: none; +} + +.left #MSearchClose { + left: 6px; +} + +.right #MSearchClose { + right: 2px; +} + +.MSearchBoxActive #MSearchField { + color: #000000; +} + +/*---------------- Search filter selection */ + +#MSearchSelectWindow { + display: none; + position: absolute; + left: 0; top: 0; + border: 1px solid #90A5CE; + background-color: #F9FAFC; + z-index: 1; + padding-top: 4px; + padding-bottom: 4px; + -moz-border-radius: 4px; + -webkit-border-top-left-radius: 4px; + -webkit-border-top-right-radius: 4px; + -webkit-border-bottom-left-radius: 4px; + -webkit-border-bottom-right-radius: 4px; + -webkit-box-shadow: 5px 5px 5px rgba(0, 0, 0, 0.15); +} + +.SelectItem { + font: 8pt Arial, Verdana, sans-serif; + padding-left: 2px; + padding-right: 12px; + border: 0px; +} + +span.SelectionMark { + margin-right: 4px; + font-family: monospace; + outline-style: none; + text-decoration: none; +} + +a.SelectItem { + display: block; + outline-style: none; + color: #000000; + text-decoration: none; + padding-left: 6px; + padding-right: 12px; +} + +a.SelectItem:focus, +a.SelectItem:active { + color: #000000; + outline-style: none; + text-decoration: none; +} + +a.SelectItem:hover { + color: #FFFFFF; + background-color: #3D578C; + outline-style: none; + text-decoration: none; + cursor: pointer; + display: block; +} + +/*---------------- Search results window */ + +iframe#MSearchResults { + width: 60ex; + height: 15em; +} + +#MSearchResultsWindow { + display: none; + position: absolute; + left: 0; top: 0; + border: 1px solid #000; + background-color: #EEF1F7; +} + +/* ----------------------------------- */ + + +#SRIndex { + clear:both; + padding-bottom: 15px; +} + +.SREntry { + font-size: 10pt; + padding-left: 1ex; +} + +.SRPage .SREntry { + font-size: 8pt; + padding: 1px 5px; +} + +body.SRPage { + margin: 5px 2px; +} + +.SRChildren { + padding-left: 3ex; padding-bottom: .5em +} + +.SRPage .SRChildren { + display: none; +} + +.SRSymbol { + font-weight: bold; + color: #425E97; + font-family: Arial, Verdana, sans-serif; + text-decoration: none; + outline: none; +} + +a.SRScope { + display: block; + color: #425E97; + font-family: Arial, Verdana, sans-serif; + text-decoration: none; + outline: none; +} + +a.SRSymbol:focus, a.SRSymbol:active, +a.SRScope:focus, a.SRScope:active { + text-decoration: underline; +} + +.SRPage .SRStatus { + padding: 2px 5px; + font-size: 8pt; + font-style: italic; +} + +.SRResult { + display: none; +} + +DIV.searchresults { + margin-left: 10px; + margin-right: 10px; +} diff --git a/Libraries/CMSIS/Documentation/Core/html/search/search.js b/Libraries/CMSIS/Documentation/Core/html/search/search.js new file mode 100644 index 0000000..6b45bd0 --- /dev/null +++ b/Libraries/CMSIS/Documentation/Core/html/search/search.js @@ -0,0 +1,738 @@ +// Search script generated by doxygen +// Copyright (C) 2009 by Dimitri van Heesch. + +// The code in this file is loosly based on main.js, part of Natural Docs, +// which is Copyright (C) 2003-2008 Greg Valure +// Natural Docs is licensed under the GPL. + +var indexSectionsWithContent = +{ + 0: "0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000010111111011001111111111111010000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000", + 1: "0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000101101001000110000110001000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000", + 2: "0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000101001011000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000", + 3: "0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000010000000001000010000100000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000", + 4: "0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000010111111011001110111111110010000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000", + 5: "0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000001000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000", + 6: "0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000010100010000110100101010000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000" +}; + +var indexSectionNames = +{ + 0: "all", + 1: "classes", + 2: "files", + 3: "functions", + 4: "variables", + 5: "enums", + 6: "enumvalues" +}; + +function convertToId(search) +{ + var result = ''; + for (i=0;i do a search + { + this.Search(); + } + } + + this.OnSearchSelectKey = function(evt) + { + var e = (evt) ? evt : window.event; // for IE + if (e.keyCode==40 && this.searchIndex0) // Up + { + this.searchIndex--; + this.OnSelectItem(this.searchIndex); + } + else if (e.keyCode==13 || e.keyCode==27) + { + this.OnSelectItem(this.searchIndex); + this.CloseSelectionWindow(); + this.DOMSearchField().focus(); + } + return false; + } + + // --------- Actions + + // Closes the results window. + this.CloseResultsWindow = function() + { + this.DOMPopupSearchResultsWindow().style.display = 'none'; + this.DOMSearchClose().style.display = 'none'; + this.Activate(false); + } + + this.CloseSelectionWindow = function() + { + this.DOMSearchSelectWindow().style.display = 'none'; + } + + // Performs a search. + this.Search = function() + { + this.keyTimeout = 0; + + // strip leading whitespace + var searchValue = this.DOMSearchField().value.replace(/^ +/, ""); + + var code = searchValue.toLowerCase().charCodeAt(0); + var hexCode; + if (code<16) + { + hexCode="0"+code.toString(16); + } + else + { + hexCode=code.toString(16); + } + + var resultsPage; + var resultsPageWithSearch; + var hasResultsPage; + + if (indexSectionsWithContent[this.searchIndex].charAt(code) == '1') + { + resultsPage = this.resultsPath + '/' + indexSectionNames[this.searchIndex] + '_' + hexCode + '.html'; + resultsPageWithSearch = resultsPage+'?'+escape(searchValue); + hasResultsPage = true; + } + else // nothing available for this search term + { + resultsPage = this.resultsPath + '/nomatches.html'; + resultsPageWithSearch = resultsPage; + hasResultsPage = false; + } + + window.frames.MSearchResults.location = resultsPageWithSearch; + var domPopupSearchResultsWindow = this.DOMPopupSearchResultsWindow(); + + if (domPopupSearchResultsWindow.style.display!='block') + { + var domSearchBox = this.DOMSearchBox(); + this.DOMSearchClose().style.display = 'inline'; + if (this.insideFrame) + { + var domPopupSearchResults = this.DOMPopupSearchResults(); + domPopupSearchResultsWindow.style.position = 'relative'; + domPopupSearchResultsWindow.style.display = 'block'; + var width = document.body.clientWidth - 8; // the -8 is for IE :-( + domPopupSearchResultsWindow.style.width = width + 'px'; + domPopupSearchResults.style.width = width + 'px'; + } + else + { + var domPopupSearchResults = this.DOMPopupSearchResults(); + var left = getXPos(domSearchBox) + 150; // domSearchBox.offsetWidth; + var top = getYPos(domSearchBox) + 20; // domSearchBox.offsetHeight + 1; + domPopupSearchResultsWindow.style.display = 'block'; + left -= domPopupSearchResults.offsetWidth; + domPopupSearchResultsWindow.style.top = top + 'px'; + domPopupSearchResultsWindow.style.left = left + 'px'; + } + } + + this.lastSearchValue = searchValue; + this.lastResultsPage = resultsPage; + } + + // -------- Activation Functions + + // Activates or deactivates the search panel, resetting things to + // their default values if necessary. + this.Activate = function(isActive) + { + if (isActive || // open it + this.DOMPopupSearchResultsWindow().style.display == 'block' + ) + { + this.DOMSearchBox().className = 'MSearchBoxActive'; + + var searchField = this.DOMSearchField(); + + if (searchField.value == this.searchLabel) // clear "Search" term upon entry + { + searchField.value = ''; + this.searchActive = true; + } + } + else if (!isActive) // directly remove the panel + { + this.DOMSearchBox().className = 'MSearchBoxInactive'; + this.DOMSearchField().value = this.searchLabel; + this.searchActive = false; + this.lastSearchValue = '' + this.lastResultsPage = ''; + } + } +} + +// ----------------------------------------------------------------------- + +// The class that handles everything on the search results page. +function SearchResults(name) +{ + // The number of matches from the last run of . + this.lastMatchCount = 0; + this.lastKey = 0; + this.repeatOn = false; + + // Toggles the visibility of the passed element ID. + this.FindChildElement = function(id) + { + var parentElement = document.getElementById(id); + var element = parentElement.firstChild; + + while (element && element!=parentElement) + { + if (element.nodeName == 'DIV' && element.className == 'SRChildren') + { + return element; + } + + if (element.nodeName == 'DIV' && element.hasChildNodes()) + { + element = element.firstChild; + } + else if (element.nextSibling) + { + element = element.nextSibling; + } + else + { + do + { + element = element.parentNode; + } + while (element && element!=parentElement && !element.nextSibling); + + if (element && element!=parentElement) + { + element = element.nextSibling; + } + } + } + } + + this.Toggle = function(id) + { + var element = this.FindChildElement(id); + if (element) + { + if (element.style.display == 'block') + { + element.style.display = 'none'; + } + else + { + element.style.display = 'block'; + } + } + } + + // Searches for the passed string. If there is no parameter, + // it takes it from the URL query. + // + // Always returns true, since other documents may try to call it + // and that may or may not be possible. + this.Search = function(search) + { + if (!search) // get search word from URL + { + search = window.location.search; + search = search.substring(1); // Remove the leading '?' + search = unescape(search); + } + + search = search.replace(/^ +/, ""); // strip leading spaces + search = search.replace(/ +$/, ""); // strip trailing spaces + search = search.toLowerCase(); + search = convertToId(search); + + var resultRows = document.getElementsByTagName("div"); + var matches = 0; + + var i = 0; + while (i < resultRows.length) + { + var row = resultRows.item(i); + if (row.className == "SRResult") + { + var rowMatchName = row.id.toLowerCase(); + rowMatchName = rowMatchName.replace(/^sr\d*_/, ''); // strip 'sr123_' + + if (search.length<=rowMatchName.length && + rowMatchName.substr(0, search.length)==search) + { + row.style.display = 'block'; + matches++; + } + else + { + row.style.display = 'none'; + } + } + i++; + } + document.getElementById("Searching").style.display='none'; + if (matches == 0) // no results + { + document.getElementById("NoMatches").style.display='block'; + } + else // at least one result + { + document.getElementById("NoMatches").style.display='none'; + } + this.lastMatchCount = matches; + return true; + } + + // return the first item with index index or higher that is visible + this.NavNext = function(index) + { + var focusItem; + while (1) + { + var focusName = 'Item'+index; + focusItem = document.getElementById(focusName); + if (focusItem && focusItem.parentNode.parentNode.style.display=='block') + { + break; + } + else if (!focusItem) // last element + { + break; + } + focusItem=null; + index++; + } + return focusItem; + } + + this.NavPrev = function(index) + { + var focusItem; + while (1) + { + var focusName = 'Item'+index; + focusItem = document.getElementById(focusName); + if (focusItem && focusItem.parentNode.parentNode.style.display=='block') + { + break; + } + else if (!focusItem) // last element + { + break; + } + focusItem=null; + index--; + } + return focusItem; + } + + this.ProcessKeys = function(e) + { + if (e.type == "keydown") + { + this.repeatOn = false; + this.lastKey = e.keyCode; + } + else if (e.type == "keypress") + { + if (!this.repeatOn) + { + if (this.lastKey) this.repeatOn = true; + return false; // ignore first keypress after keydown + } + } + else if (e.type == "keyup") + { + this.lastKey = 0; + this.repeatOn = false; + } + return this.lastKey!=0; + } + + this.Nav = function(evt,itemIndex) + { + var e = (evt) ? evt : window.event; // for IE + if (e.keyCode==13) return true; + if (!this.ProcessKeys(e)) return false; + + if (this.lastKey==38) // Up + { + var newIndex = itemIndex-1; + var focusItem = this.NavPrev(newIndex); + if (focusItem) + { + var child = this.FindChildElement(focusItem.parentNode.parentNode.id); + if (child && child.style.display == 'block') // children visible + { + var n=0; + var tmpElem; + while (1) // search for last child + { + tmpElem = document.getElementById('Item'+newIndex+'_c'+n); + if (tmpElem) + { + focusItem = tmpElem; + } + else // found it! + { + break; + } + n++; + } + } + } + if (focusItem) + { + focusItem.focus(); + } + else // return focus to search field + { + parent.document.getElementById("MSearchField").focus(); + } + } + else if (this.lastKey==40) // Down + { + var newIndex = itemIndex+1; + var focusItem; + var item = document.getElementById('Item'+itemIndex); + var elem = this.FindChildElement(item.parentNode.parentNode.id); + if (elem && elem.style.display == 'block') // children visible + { + focusItem = document.getElementById('Item'+itemIndex+'_c0'); + } + if (!focusItem) focusItem = this.NavNext(newIndex); + if (focusItem) focusItem.focus(); + } + else if (this.lastKey==39) // Right + { + var item = document.getElementById('Item'+itemIndex); + var elem = this.FindChildElement(item.parentNode.parentNode.id); + if (elem) elem.style.display = 'block'; + } + else if (this.lastKey==37) // Left + { + var item = document.getElementById('Item'+itemIndex); + var elem = this.FindChildElement(item.parentNode.parentNode.id); + if (elem) elem.style.display = 'none'; + } + else if (this.lastKey==27) // Escape + { + parent.searchBox.CloseResultsWindow(); + parent.document.getElementById("MSearchField").focus(); + } + else if (this.lastKey==13) // Enter + { + return true; + } + return false; + } + + this.NavChild = function(evt,itemIndex,childIndex) + { + var e = (evt) ? evt : window.event; // for IE + if (e.keyCode==13) return true; + if (!this.ProcessKeys(e)) return false; + + if (this.lastKey==38) // Up + { + if (childIndex>0) + { + var newIndex = childIndex-1; + document.getElementById('Item'+itemIndex+'_c'+newIndex).focus(); + } + else // already at first child, jump to parent + { + document.getElementById('Item'+itemIndex).focus(); + } + } + else if (this.lastKey==40) // Down + { + var newIndex = childIndex+1; + var elem = document.getElementById('Item'+itemIndex+'_c'+newIndex); + if (!elem) // last child, jump to parent next parent + { + elem = this.NavNext(itemIndex+1); + } + if (elem) + { + elem.focus(); + } + } + else if (this.lastKey==27) // Escape + { + parent.searchBox.CloseResultsWindow(); + parent.document.getElementById("MSearchField").focus(); + } + else if (this.lastKey==13) // Enter + { + return true; + } + return false; + } +} diff --git a/Libraries/CMSIS/Documentation/Core/html/search/search_l.png b/Libraries/CMSIS/Documentation/Core/html/search/search_l.png new file mode 100644 index 0000000000000000000000000000000000000000..c872f4da4a01d0754f923e6c94fd8159c0621bd1 GIT binary patch literal 604 zcmV-i0;BzjP)k7RCwB~R6VQOP#AvB$vH7i{6H{96zot$7cZT<7246EF5Np6N}+$IbiG6W zg#87A+NFaX+=_^xM1#gCtshC=E{%9^uQX_%?YwXvo{#q&MnpJ8uh(O?ZRc&~_1%^SsPxG@rfElJg-?U zm!Cz-IOn(qJP3kDp-^~qt+FGbl=5jNli^Wj_xIBG{Rc0en{!oFvyoNC7{V~T8}b>| z=jL2WIReZzX(YN(_9fV;BBD$VXQIxNasAL8ATvEu822WQ%mvv4FO#qs` BFGc_W literal 0 HcmV?d00001 diff --git a/Libraries/CMSIS/Documentation/Core/html/search/search_r.png b/Libraries/CMSIS/Documentation/Core/html/search/search_r.png new file mode 100644 index 0000000000000000000000000000000000000000..97ee8b439687084201b79c6f776a41f495c6392a GIT binary patch literal 612 zcmV-q0-ODbP)PbXFRCwB?)W514K@j&X?z2*SxFI6-@HT2E2K=9X9%Pb zEK*!TBw&g(DMC;|A)uGlRkOS9vd-?zNs%bR4d$w+ox_iFnE8fvIvv7^5<(>Te12Li z7C)9srCzmK{ZcNM{YIl9j{DePFgOWiS%xG@5CnnnJa4nvY<^glbz7^|-ZY!dUkAwd z{gaTC@_>b5h~;ug#R0wRL0>o5!hxm*s0VW?8dr}O#zXTRTnrQm_Z7z1Mrnx>&p zD4qifUjzLvbVVWi?l?rUzwt^sdb~d!f_LEhsRVIXZtQ=qSxuxqm zEX#tf>$?M_Y1-LSDT)HqG?`%-%ZpY!#{N!rcNIiL;G7F0`l?)mNGTD9;f9F5Up3Kg zw}a<-JylhG&;=!>B+fZaCX+?C+kHYrP%c?X2!Zu_olK|GcS4A70HEy;vn)I0>0kLH z`jc(WIaaHc7!HS@f*^R^Znx8W=_jIl2oWJoQ*h1^$FX!>*PqR1J8k|fw}w_y}TpE>7m8DqDO<3z`OzXt$ccSejbEZCg@0000 + + + + + + +
    +
    Loading...
    +
    +
    + _reserved0 +
    + APSR_Type::_reserved0() + IPSR_Type::_reserved0() + xPSR_Type::_reserved0() + CONTROL_Type::_reserved0() +
    +
    +
    +
    Searching...
    +
    No Matches
    + +
    + + diff --git a/Libraries/CMSIS/Documentation/Core/html/search/variables_61.html b/Libraries/CMSIS/Documentation/Core/html/search/variables_61.html new file mode 100644 index 0000000..45a0ac5 --- /dev/null +++ b/Libraries/CMSIS/Documentation/Core/html/search/variables_61.html @@ -0,0 +1,50 @@ + + + + + + + +
    +
    Loading...
    +
    +
    + ACPR + TPI_Type +
    +
    +
    +
    + ACTLR + SCnSCB_Type +
    +
    +
    +
    + ADR + SCB_Type +
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    +
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    + AFSR + SCB_Type +
    +
    +
    +
    + AIRCR + SCB_Type +
    +
    +
    Searching...
    +
    No Matches
    + +
    + + diff --git a/Libraries/CMSIS/Documentation/Core/html/search/variables_62.html b/Libraries/CMSIS/Documentation/Core/html/search/variables_62.html new file mode 100644 index 0000000..5f65963 --- /dev/null +++ b/Libraries/CMSIS/Documentation/Core/html/search/variables_62.html @@ -0,0 +1,37 @@ + + + + + + + +
    +
    Loading...
    + +
    +
    + BFAR + SCB_Type +
    +
    +
    Searching...
    +
    No Matches
    + +
    + + diff --git a/Libraries/CMSIS/Documentation/Core/html/search/variables_63.html b/Libraries/CMSIS/Documentation/Core/html/search/variables_63.html new file mode 100644 index 0000000..7127f12 --- /dev/null +++ b/Libraries/CMSIS/Documentation/Core/html/search/variables_63.html @@ -0,0 +1,123 @@ + + + + + + + +
    +
    Loading...
    + +
    +
    + CALIB + SysTick_Type +
    +
    +
    +
    + CCR + SCB_Type +
    +
    +
    +
    + CFSR + SCB_Type +
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    +
    +
    + CLAIMCLR + TPI_Type +
    +
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    + CLAIMSET + TPI_Type +
    +
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    + COMP0 + DWT_Type +
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    + COMP1 + DWT_Type +
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    +
    +
    + COMP2 + DWT_Type +
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    +
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    + COMP3 + DWT_Type +
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    + CPACR + SCB_Type +
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    + CPICNT + DWT_Type +
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    + CPUID + SCB_Type +
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    + CSPSR + TPI_Type +
    +
    + +
    +
    + CYCCNT + DWT_Type +
    +
    +
    Searching...
    +
    No Matches
    + +
    + + diff --git a/Libraries/CMSIS/Documentation/Core/html/search/variables_64.html b/Libraries/CMSIS/Documentation/Core/html/search/variables_64.html new file mode 100644 index 0000000..2a678b6 --- /dev/null +++ b/Libraries/CMSIS/Documentation/Core/html/search/variables_64.html @@ -0,0 +1,68 @@ + + + + + + + +
    +
    Loading...
    +
    +
    + DCRDR + CoreDebug_Type +
    +
    +
    +
    + DCRSR + CoreDebug_Type +
    +
    +
    +
    + DEMCR + CoreDebug_Type +
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    + DEVID + TPI_Type +
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    + DEVTYPE + TPI_Type +
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    + DFR + SCB_Type +
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    +
    +
    + DFSR + SCB_Type +
    +
    +
    +
    + DHCSR + CoreDebug_Type +
    +
    +
    Searching...
    +
    No Matches
    + +
    + + diff --git a/Libraries/CMSIS/Documentation/Core/html/search/variables_65.html b/Libraries/CMSIS/Documentation/Core/html/search/variables_65.html new file mode 100644 index 0000000..b3db09d --- /dev/null +++ b/Libraries/CMSIS/Documentation/Core/html/search/variables_65.html @@ -0,0 +1,26 @@ + + + + + + + +
    +
    Loading...
    +
    +
    + EXCCNT + DWT_Type +
    +
    +
    Searching...
    +
    No Matches
    + +
    + + diff --git a/Libraries/CMSIS/Documentation/Core/html/search/variables_66.html b/Libraries/CMSIS/Documentation/Core/html/search/variables_66.html new file mode 100644 index 0000000..709a9e9 --- /dev/null +++ b/Libraries/CMSIS/Documentation/Core/html/search/variables_66.html @@ -0,0 +1,104 @@ + + + + + + + +
    +
    Loading...
    +
    +
    + FFCR + TPI_Type +
    +
    +
    +
    + FFSR + TPI_Type +
    +
    +
    +
    + FIFO0 + TPI_Type +
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    +
    +
    + FPCA + CONTROL_Type +
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    + FPCAR + FPU_Type +
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    +
    + FPCCR + FPU_Type +
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    + FPDSCR + FPU_Type +
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    + FSCR + TPI_Type +
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    + FUNCTION0 + DWT_Type +
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    + FUNCTION2 + DWT_Type +
    +
    +
    +
    + FUNCTION3 + DWT_Type +
    +
    +
    Searching...
    +
    No Matches
    + +
    + + diff --git a/Libraries/CMSIS/Documentation/Core/html/search/variables_68.html b/Libraries/CMSIS/Documentation/Core/html/search/variables_68.html new file mode 100644 index 0000000..5b9971c --- /dev/null +++ b/Libraries/CMSIS/Documentation/Core/html/search/variables_68.html @@ -0,0 +1,26 @@ + + + + + + + +
    +
    Loading...
    +
    +
    + HFSR + SCB_Type +
    +
    +
    Searching...
    +
    No Matches
    + +
    + + diff --git a/Libraries/CMSIS/Documentation/Core/html/search/variables_69.html b/Libraries/CMSIS/Documentation/Core/html/search/variables_69.html new file mode 100644 index 0000000..75edc19 --- /dev/null +++ b/Libraries/CMSIS/Documentation/Core/html/search/variables_69.html @@ -0,0 +1,113 @@ + + + + + + + +
    +
    Loading...
    +
    +
    + IABR + NVIC_Type +
    +
    +
    +
    + ICER + NVIC_Type +
    +
    +
    +
    + ICPR + NVIC_Type +
    +
    +
    +
    + ICSR + SCB_Type +
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    +
    +
    + ICTR + SCnSCB_Type +
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    +
    +
    + IP + NVIC_Type +
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    +
    + ISAR + SCB_Type +
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    +
    +
    + ISER + NVIC_Type +
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    +
    +
    + ISPR + NVIC_Type +
    +
    + +
    +
    + IT + xPSR_Type +
    +
    +
    +
    + ITATBCTR0 + TPI_Type +
    +
    +
    +
    + ITATBCTR2 + TPI_Type +
    +
    +
    +
    + ITCTRL + TPI_Type +
    +
    +
    +
    + ITM_RxBuffer + Ref_Debug.txt +
    +
    +
    Searching...
    +
    No Matches
    + +
    + + diff --git a/Libraries/CMSIS/Documentation/Core/html/search/variables_6c.html b/Libraries/CMSIS/Documentation/Core/html/search/variables_6c.html new file mode 100644 index 0000000..337c839 --- /dev/null +++ b/Libraries/CMSIS/Documentation/Core/html/search/variables_6c.html @@ -0,0 +1,32 @@ + + + + + + + +
    +
    Loading...
    +
    +
    + LOAD + SysTick_Type +
    +
    +
    +
    + LSUCNT + DWT_Type +
    +
    +
    Searching...
    +
    No Matches
    + +
    + + diff --git a/Libraries/CMSIS/Documentation/Core/html/search/variables_6d.html b/Libraries/CMSIS/Documentation/Core/html/search/variables_6d.html new file mode 100644 index 0000000..2f3ed3d --- /dev/null +++ b/Libraries/CMSIS/Documentation/Core/html/search/variables_6d.html @@ -0,0 +1,68 @@ + + + + + + + +
    +
    Loading...
    +
    +
    + MASK0 + DWT_Type +
    +
    +
    +
    + MASK1 + DWT_Type +
    +
    +
    +
    + MASK2 + DWT_Type +
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    + MASK3 + DWT_Type +
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    +
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    + MMFAR + SCB_Type +
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    +
    +
    + MMFR + SCB_Type +
    +
    +
    +
    + MVFR0 + FPU_Type +
    +
    +
    +
    + MVFR1 + FPU_Type +
    +
    +
    Searching...
    +
    No Matches
    + +
    + + diff --git a/Libraries/CMSIS/Documentation/Core/html/search/variables_6e.html b/Libraries/CMSIS/Documentation/Core/html/search/variables_6e.html new file mode 100644 index 0000000..a802996 --- /dev/null +++ b/Libraries/CMSIS/Documentation/Core/html/search/variables_6e.html @@ -0,0 +1,35 @@ + + + + + + + +
    +
    Loading...
    + +
    +
    + nPRIV + CONTROL_Type +
    +
    +
    Searching...
    +
    No Matches
    + +
    + + diff --git a/Libraries/CMSIS/Documentation/Core/html/search/variables_70.html b/Libraries/CMSIS/Documentation/Core/html/search/variables_70.html new file mode 100644 index 0000000..a017e22 --- /dev/null +++ b/Libraries/CMSIS/Documentation/Core/html/search/variables_70.html @@ -0,0 +1,38 @@ + + + + + + + +
    +
    Loading...
    +
    +
    + PCSR + DWT_Type +
    +
    +
    +
    + PFR + SCB_Type +
    +
    +
    +
    + PORT + ITM_Type +
    +
    +
    Searching...
    +
    No Matches
    + +
    + + diff --git a/Libraries/CMSIS/Documentation/Core/html/search/variables_71.html b/Libraries/CMSIS/Documentation/Core/html/search/variables_71.html new file mode 100644 index 0000000..0c1e07b --- /dev/null +++ b/Libraries/CMSIS/Documentation/Core/html/search/variables_71.html @@ -0,0 +1,29 @@ + + + + + + + +
    +
    Loading...
    + +
    Searching...
    +
    No Matches
    + +
    + + diff --git a/Libraries/CMSIS/Documentation/Core/html/search/variables_72.html b/Libraries/CMSIS/Documentation/Core/html/search/variables_72.html new file mode 100644 index 0000000..ea9fc46 --- /dev/null +++ b/Libraries/CMSIS/Documentation/Core/html/search/variables_72.html @@ -0,0 +1,148 @@ + + + + + + + +
    +
    Loading...
    +
    +
    + RASR + MPU_Type +
    +
    +
    +
    + RASR_A1 + MPU_Type +
    +
    +
    +
    + RASR_A2 + MPU_Type +
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    +
    +
    + RASR_A3 + MPU_Type +
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    +
    +
    + RBAR + MPU_Type +
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    +
    +
    + RBAR_A1 + MPU_Type +
    +
    +
    +
    + RBAR_A2 + MPU_Type +
    +
    +
    +
    + RBAR_A3 + MPU_Type +
    +
    + + + + + + +
    +
    + RESERVED7 + TPI_Type +
    +
    +
    +
    + RNR + MPU_Type +
    +
    +
    +
    + RSERVED1 + NVIC_Type +
    +
    +
    Searching...
    +
    No Matches
    + +
    + + diff --git a/Libraries/CMSIS/Documentation/Core/html/search/variables_73.html b/Libraries/CMSIS/Documentation/Core/html/search/variables_73.html new file mode 100644 index 0000000..d4b45ae --- /dev/null +++ b/Libraries/CMSIS/Documentation/Core/html/search/variables_73.html @@ -0,0 +1,74 @@ + + + + + + + +
    +
    Loading...
    +
    +
    + SCR + SCB_Type +
    +
    +
    +
    + SHCSR + SCB_Type +
    +
    +
    +
    + SHP + SCB_Type +
    +
    +
    +
    + SLEEPCNT + DWT_Type +
    +
    +
    +
    + SPPR + TPI_Type +
    +
    +
    +
    + SPSEL + CONTROL_Type +
    +
    +
    +
    + SSPSR + TPI_Type +
    +
    +
    +
    + STIR + NVIC_Type +
    +
    +
    +
    + SystemCoreClock + Ref_SystemAndClock.txt +
    +
    +
    Searching...
    +
    No Matches
    + +
    + + diff --git a/Libraries/CMSIS/Documentation/Core/html/search/variables_74.html b/Libraries/CMSIS/Documentation/Core/html/search/variables_74.html new file mode 100644 index 0000000..66d0dbb --- /dev/null +++ b/Libraries/CMSIS/Documentation/Core/html/search/variables_74.html @@ -0,0 +1,56 @@ + + + + + + + +
    +
    Loading...
    +
    +
    + T + xPSR_Type +
    +
    +
    +
    + TCR + ITM_Type +
    +
    +
    +
    + TER + ITM_Type +
    +
    +
    +
    + TPR + ITM_Type +
    +
    +
    +
    + TRIGGER + TPI_Type +
    +
    +
    +
    + TYPE + MPU_Type +
    +
    +
    Searching...
    +
    No Matches
    + +
    + + diff --git a/Libraries/CMSIS/Documentation/Core/html/search/variables_75.html b/Libraries/CMSIS/Documentation/Core/html/search/variables_75.html new file mode 100644 index 0000000..dded075 --- /dev/null +++ b/Libraries/CMSIS/Documentation/Core/html/search/variables_75.html @@ -0,0 +1,38 @@ + + + + + + + +
    +
    Loading...
    +
    +
    + u16 + ITM_Type +
    +
    +
    +
    + u32 + ITM_Type +
    +
    +
    +
    + u8 + ITM_Type +
    +
    +
    Searching...
    +
    No Matches
    + +
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    + VAL + SysTick_Type +
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    + VTOR + SCB_Type +
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    + + diff --git a/Libraries/CMSIS/Documentation/Core/html/search/variables_77.html b/Libraries/CMSIS/Documentation/Core/html/search/variables_77.html new file mode 100644 index 0000000..fdc60a2 --- /dev/null +++ b/Libraries/CMSIS/Documentation/Core/html/search/variables_77.html @@ -0,0 +1,31 @@ + + + + + + + +
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    + + diff --git a/Libraries/CMSIS/Documentation/Core/html/search/variables_7a.html b/Libraries/CMSIS/Documentation/Core/html/search/variables_7a.html new file mode 100644 index 0000000..1c0da89 --- /dev/null +++ b/Libraries/CMSIS/Documentation/Core/html/search/variables_7a.html @@ -0,0 +1,29 @@ + + + + + + + +
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    + + diff --git a/Libraries/CMSIS/Documentation/Core/html/startup_s_pg.html b/Libraries/CMSIS/Documentation/Core/html/startup_s_pg.html new file mode 100644 index 0000000..e16b33c --- /dev/null +++ b/Libraries/CMSIS/Documentation/Core/html/startup_s_pg.html @@ -0,0 +1,359 @@ + + + + +Startup File startup_<device>.s + + + + + + + + + + + + + +
    + +
    + + + + + + + + + + + +
    +
    CMSIS-CORE +  Version 3.01 +
    +
    CMSIS-CORE support for Cortex-M processor-based devices
    +
    +
    + +
    + +
    + + + +
    +
    + +
    +
    +
    + +
    +
    +
    +
    Startup File startup_<device>.s
    +
    +
    +

    The Startup File startup_<device>.s contains:

    +
      +
    • The reset handler which is executed after CPU reset and typically calls the SystemInit function.
      • +
    • The setup values for the Main Stack Pointer (MSP).
      • +
    • Exception vectors of the Cortex-M Processor with weak functions that implement default routines.
      • +
    • Interrupt vectors that are device specific with weak functions that implement default routines.
      • +
    +

    The file exists for each supported toolchain and is the only tool-chain specific CMSIS file.

    +

    To adapt the file to a new device only the interrupt vector table needs to be extended with the device-specific interrupt handlers. The naming convention for the interrupt handler names are <interrupt_name>_IRQHandler. This table needs to be consistent with IRQn_Type that defines all the IRQ numbers for each interrupt.

    +

    Example:

    +

    The following example shows the extension of the interrupt vector table for the LPC1100 device family.

    +
                    ; External Interrupts
+                DCD     WAKEUP0_IRQHandler       ; 16+ 0: Wakeup PIO0.0
+                DCD     WAKEUP1_IRQHandler       ; 16+ 1: Wakeup PIO0.1
+                DCD     WAKEUP2_IRQHandler       ; 16+ 2: Wakeup PIO0.2
+                 :       :
+                 :       :
+                DCD     EINT1_IRQHandler         ; 16+30: PIO INT1
+                DCD     EINT0_IRQHandler         ; 16+31: PIO INT0
+         :  
+         :
+                EXPORT  WAKEUP0_IRQHandler       [WEAK]
+                EXPORT  WAKEUP1_IRQHandler       [WEAK]
+                EXPORT  WAKEUP2_IRQHandler       [WEAK]
+                 :       :
+                 :       :                                               
+                EXPORT  EINT1_IRQHandler         [WEAK]
+                EXPORT  EINT0_IRQHandler         [WEAK]
+
+WAKEUP0_IRQHandler
+WAKEUP1_IRQHandler
+WAKEUP1_IRQHandler
+      :
+      :
+EINT1_IRQHandler
+EINT0_IRQHandler
+                B       .
+

    +startup_Device.s Template File

    +

    The startup_Device.s Template File for the Cortex-M3 and the ARMCC compiler is shown below. The files for other compiler vendors differ slightly in the syntax, but not in the overall structure.

    +
    ;/**************************************************************************//**
+; * @file     startup_<Device>.s
+; * @brief    CMSIS Cortex-M# Core Device Startup File for
+; *           Device <Device>
+; * @version  V3.01
+; * @date     06. March 2012
+; *
+; * @note
+; * Copyright (C) 2012 ARM Limited. All rights reserved.
+; *
+; * @par
+; * ARM Limited (ARM) is supplying this software for use with Cortex-M
+; * processor based microcontrollers.  This file can be freely distributed
+; * within development tools that are supporting such ARM based processors.
+; *
+; * @par
+; * THIS SOFTWARE IS PROVIDED "AS IS".  NO WARRANTIES, WHETHER EXPRESS, IMPLIED
+; * OR STATUTORY, INCLUDING, BUT NOT LIMITED TO, IMPLIED WARRANTIES OF
+; * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE APPLY TO THIS SOFTWARE.
+; * ARM SHALL NOT, IN ANY CIRCUMSTANCES, BE LIABLE FOR SPECIAL, INCIDENTAL, OR
+; * CONSEQUENTIAL DAMAGES, FOR ANY REASON WHATSOEVER.
+; *
+; ******************************************************************************/
+;/*
+;//-------- <<< Use Configuration Wizard in Context Menu >>> ------------------
+;*/
+
+
+; <h> Stack Configuration
+;   <o> Stack Size (in Bytes) <0x0-0xFFFFFFFF:8>
+; </h>
+
+Stack_Size      EQU     0x00000400
+
+                AREA    STACK, NOINIT, READWRITE, ALIGN=3
+Stack_Mem       SPACE   Stack_Size
+__initial_sp
+
+
+; <h> Heap Configuration
+;   <o>  Heap Size (in Bytes) <0x0-0xFFFFFFFF:8>
+; </h>
+
+Heap_Size       EQU     0x00000100
+
+                AREA    HEAP, NOINIT, READWRITE, ALIGN=3
+__heap_base
+Heap_Mem        SPACE   Heap_Size
+__heap_limit
+
+
+                PRESERVE8
+                THUMB
+
+
+; Vector Table Mapped to Address 0 at Reset
+
+                AREA    RESET, DATA, READONLY
+                EXPORT  __Vectors
+                EXPORT  __Vectors_End
+                EXPORT  __Vectors_Size
+
+__Vectors       DCD     __initial_sp              ; Top of Stack
+                DCD     Reset_Handler             ; Reset Handler
+                DCD     NMI_Handler               ; NMI Handler
+                DCD     HardFault_Handler         ; Hard Fault Handler
+                DCD     MemManage_Handler         ; MPU Fault Handler
+                DCD     BusFault_Handler          ; Bus Fault Handler
+                DCD     UsageFault_Handler        ; Usage Fault Handler
+                DCD     0                         ; Reserved
+                DCD     0                         ; Reserved
+                DCD     0                         ; Reserved
+                DCD     0                         ; Reserved
+                DCD     SVC_Handler               ; SVCall Handler
+                DCD     DebugMon_Handler          ; Debug Monitor Handler
+                DCD     0                         ; Reserved
+                DCD     PendSV_Handler            ; PendSV Handler
+                DCD     SysTick_Handler           ; SysTick Handler
+
+                ; External Interrupts
+; ToDo:  Add here the vectors for the device specific external interrupts handler
+                DCD     <DeviceInterrupt>_IRQHandler       ;  0: Default
+__Vectors_End
+
+__Vectors_Size  EQU     __Vectors_End - __Vectors
+
+                AREA    |.text|, CODE, READONLY
+
+
+; Reset Handler
+
+Reset_Handler   PROC
+                EXPORT  Reset_Handler             [WEAK]
+                IMPORT  SystemInit
+                IMPORT  __main
+                LDR     R0, =SystemInit
+                BLX     R0
+                LDR     R0, =__main
+                BX      R0
+                ENDP
+
+
+; Dummy Exception Handlers (infinite loops which can be modified)
+
+NMI_Handler     PROC
+                EXPORT  NMI_Handler               [WEAK]
+                B       .
+                ENDP
+HardFault_Handler\
+                PROC
+                EXPORT  HardFault_Handler         [WEAK]
+                B       .
+                ENDP
+MemManage_Handler\
+                PROC
+                EXPORT  MemManage_Handler         [WEAK]
+                B       .
+                ENDP
+BusFault_Handler\
+                PROC
+                EXPORT  BusFault_Handler          [WEAK]
+                B       .
+                ENDP
+UsageFault_Handler\
+                PROC
+                EXPORT  UsageFault_Handler        [WEAK]
+                B       .
+                ENDP
+SVC_Handler     PROC
+                EXPORT  SVC_Handler               [WEAK]
+                B       .
+                ENDP
+DebugMon_Handler\
+                PROC
+                EXPORT  DebugMon_Handler          [WEAK]
+                B       .
+                ENDP
+PendSV_Handler\
+                PROC
+                EXPORT  PendSV_Handler            [WEAK]
+                B       .
+                ENDP
+SysTick_Handler\
+                PROC
+                EXPORT  SysTick_Handler           [WEAK]
+                B       .
+                ENDP
+
+Default_Handler PROC
+; ToDo:  Add here the export definition for the device specific external interrupts handler
+                EXPORT  <DeviceInterrupt>_IRQHandler         [WEAK]
+
+; ToDo:  Add here the names for the device specific external interrupts handler
+<DeviceInterrupt>_IRQHandler
+                B       .
+                ENDP
+
+
+                ALIGN
+
+
+; User Initial Stack & Heap
+
+                IF      :DEF:__MICROLIB
+
+                EXPORT  __initial_sp
+                EXPORT  __heap_base
+                EXPORT  __heap_limit
+
+                ELSE
+
+                IMPORT  __use_two_region_memory
+                EXPORT  __user_initial_stackheap
+
+__user_initial_stackheap PROC
+                LDR     R0, =  Heap_Mem
+                LDR     R1, =(Stack_Mem + Stack_Size)
+                LDR     R2, = (Heap_Mem +  Heap_Size)
+                LDR     R3, = Stack_Mem
+                BX      LR
+                ENDP
+
+                ALIGN
+
+                ENDIF
+
+
+                END
+
    +
    + + + + + diff --git a/Libraries/CMSIS/Documentation/Core/html/struct_core_debug___type.html b/Libraries/CMSIS/Documentation/Core/html/struct_core_debug___type.html new file mode 100644 index 0000000..2d8c7d6 --- /dev/null +++ b/Libraries/CMSIS/Documentation/Core/html/struct_core_debug___type.html @@ -0,0 +1,207 @@ + + + + +CoreDebug_Type Struct Reference + + + + + + + + + + + + + +
    + +
    + + + + + + + + + + + +
    +
    CMSIS-CORE +  Version 3.01 +
    +
    CMSIS-CORE support for Cortex-M processor-based devices
    +
    +
    + +
    + +
    + + + + +
    +
    + +
    +
    +
    + +
    +
    +
    +Data Fields
    +
    +
    CoreDebug_Type Struct Reference
    +
    +
    + +

    Structure type to access the Core Debug Register (CoreDebug). +

    + + + + + + + + + + +

    +Data Fields

    __IO uint32_t DHCSR
     Offset: 0x000 (R/W) Debug Halting Control and Status Register.
    __O uint32_t DCRSR
     Offset: 0x004 ( /W) Debug Core Register Selector Register.
    __IO uint32_t DCRDR
     Offset: 0x008 (R/W) Debug Core Register Data Register.
    __IO uint32_t DEMCR
     Offset: 0x00C (R/W) Debug Exception and Monitor Control Register.
    +

    Field Documentation

    + +
    +
    + + + + +
    __IO uint32_t CoreDebug_Type::DCRDR
    +
    +
    + +
    +
    + +
    +
    + + + + +
    __O uint32_t CoreDebug_Type::DCRSR
    +
    +
    + +
    +
    + +
    +
    + + + + +
    __IO uint32_t CoreDebug_Type::DEMCR
    +
    +
    + +
    +
    + +
    +
    + + + + +
    __IO uint32_t CoreDebug_Type::DHCSR
    +
    +
    + +
    +
    +
    +
    + + + + + diff --git a/Libraries/CMSIS/Documentation/Core/html/struct_d_w_t___type.html b/Libraries/CMSIS/Documentation/Core/html/struct_d_w_t___type.html new file mode 100644 index 0000000..eb5fb16 --- /dev/null +++ b/Libraries/CMSIS/Documentation/Core/html/struct_d_w_t___type.html @@ -0,0 +1,492 @@ + + + + +DWT_Type Struct Reference + + + + + + + + + + + + + +
    + +
    + + + + + + + + + + + +
    +
    CMSIS-CORE +  Version 3.01 +
    +
    CMSIS-CORE support for Cortex-M processor-based devices
    +
    +
    + +
    + +
    + + + + +
    +
    + +
    +
    +
    + +
    +
    +
    +Data Fields
    +
    +
    DWT_Type Struct Reference
    +
    +
    + +

    Structure type to access the Data Watchpoint and Trace Register (DWT). +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +

    +Data Fields

    __IO uint32_t CTRL
     Offset: 0x000 (R/W) Control Register.
    __IO uint32_t CYCCNT
     Offset: 0x004 (R/W) Cycle Count Register.
    __IO uint32_t CPICNT
     Offset: 0x008 (R/W) CPI Count Register.
    __IO uint32_t EXCCNT
     Offset: 0x00C (R/W) Exception Overhead Count Register.
    __IO uint32_t SLEEPCNT
     Offset: 0x010 (R/W) Sleep Count Register.
    __IO uint32_t LSUCNT
     Offset: 0x014 (R/W) LSU Count Register.
    __IO uint32_t FOLDCNT
     Offset: 0x018 (R/W) Folded-instruction Count Register.
    __I uint32_t PCSR
     Offset: 0x01C (R/ ) Program Counter Sample Register.
    __IO uint32_t COMP0
     Offset: 0x020 (R/W) Comparator Register 0.
    __IO uint32_t MASK0
     Offset: 0x024 (R/W) Mask Register 0.
    __IO uint32_t FUNCTION0
     Offset: 0x028 (R/W) Function Register 0.
    uint32_t RESERVED0 [1]
     Reserved.
    __IO uint32_t COMP1
     Offset: 0x030 (R/W) Comparator Register 1.
    __IO uint32_t MASK1
     Offset: 0x034 (R/W) Mask Register 1.
    __IO uint32_t FUNCTION1
     Offset: 0x038 (R/W) Function Register 1.
    uint32_t RESERVED1 [1]
     Reserved.
    __IO uint32_t COMP2
     Offset: 0x040 (R/W) Comparator Register 2.
    __IO uint32_t MASK2
     Offset: 0x044 (R/W) Mask Register 2.
    __IO uint32_t FUNCTION2
     Offset: 0x048 (R/W) Function Register 2.
    uint32_t RESERVED2 [1]
     Reserved.
    __IO uint32_t COMP3
     Offset: 0x050 (R/W) Comparator Register 3.
    __IO uint32_t MASK3
     Offset: 0x054 (R/W) Mask Register 3.
    __IO uint32_t FUNCTION3
     Offset: 0x058 (R/W) Function Register 3.
    +

    Field Documentation

    + +
    +
    + + + + +
    __IO uint32_t DWT_Type::COMP0
    +
    +
    + +
    +
    + +
    +
    + + + + +
    __IO uint32_t DWT_Type::COMP1
    +
    +
    + +
    +
    + +
    +
    + + + + +
    __IO uint32_t DWT_Type::COMP2
    +
    +
    + +
    +
    + +
    +
    + + + + +
    __IO uint32_t DWT_Type::COMP3
    +
    +
    + +
    +
    + +
    +
    + + + + +
    __IO uint32_t DWT_Type::CPICNT
    +
    +
    + +
    +
    + +
    +
    + + + + +
    __IO uint32_t DWT_Type::CTRL
    +
    +
    + +
    +
    + +
    +
    + + + + +
    __IO uint32_t DWT_Type::CYCCNT
    +
    +
    + +
    +
    + +
    +
    + + + + +
    __IO uint32_t DWT_Type::EXCCNT
    +
    +
    + +
    +
    + +
    +
    + + + + +
    __IO uint32_t DWT_Type::FOLDCNT
    +
    +
    + +
    +
    + +
    +
    + + + + +
    __IO uint32_t DWT_Type::FUNCTION0
    +
    +
    + +
    +
    + +
    +
    + + + + +
    __IO uint32_t DWT_Type::FUNCTION1
    +
    +
    + +
    +
    + +
    +
    + + + + +
    __IO uint32_t DWT_Type::FUNCTION2
    +
    +
    + +
    +
    + +
    +
    + + + + +
    __IO uint32_t DWT_Type::FUNCTION3
    +
    +
    + +
    +
    + +
    +
    + + + + +
    __IO uint32_t DWT_Type::LSUCNT
    +
    +
    + +
    +
    + +
    +
    + + + + +
    __IO uint32_t DWT_Type::MASK0
    +
    +
    + +
    +
    + +
    +
    + + + + +
    __IO uint32_t DWT_Type::MASK1
    +
    +
    + +
    +
    + +
    +
    + + + + +
    __IO uint32_t DWT_Type::MASK2
    +
    +
    + +
    +
    + +
    +
    + + + + +
    __IO uint32_t DWT_Type::MASK3
    +
    +
    + +
    +
    + +
    +
    + + + + +
    __I uint32_t DWT_Type::PCSR
    +
    +
    + +
    +
    + +
    +
    + + + + +
    uint32_t DWT_Type::RESERVED0[1]
    +
    +
    + +
    +
    + +
    +
    + + + + +
    uint32_t DWT_Type::RESERVED1[1]
    +
    +
    + +
    +
    + +
    +
    + + + + +
    uint32_t DWT_Type::RESERVED2[1]
    +
    +
    + +
    +
    + +
    +
    + + + + +
    __IO uint32_t DWT_Type::SLEEPCNT
    +
    +
    + +
    +
    +
    +
    + + + + + diff --git a/Libraries/CMSIS/Documentation/Core/html/struct_f_p_u___type.html b/Libraries/CMSIS/Documentation/Core/html/struct_f_p_u___type.html new file mode 100644 index 0000000..5ac444b --- /dev/null +++ b/Libraries/CMSIS/Documentation/Core/html/struct_f_p_u___type.html @@ -0,0 +1,237 @@ + + + + +FPU_Type Struct Reference + + + + + + + + + + + + + +
    + +
    + + + + + + + + + + + +
    +
    CMSIS-CORE +  Version 3.01 +
    +
    CMSIS-CORE support for Cortex-M processor-based devices
    +
    +
    + +
    + +
    + + + + +
    +
    + +
    +
    +
    + +
    +
    +
    +Data Fields
    +
    +
    FPU_Type Struct Reference
    +
    +
    + +

    Structure type to access the Floating Point Unit (FPU). +

    + + + + + + + + + + + + + + +

    +Data Fields

    uint32_t RESERVED0 [1]
     Reserved.
    __IO uint32_t FPCCR
     Offset: 0x004 (R/W) Floating-Point Context Control Register.
    __IO uint32_t FPCAR
     Offset: 0x008 (R/W) Floating-Point Context Address Register.
    __IO uint32_t FPDSCR
     Offset: 0x00C (R/W) Floating-Point Default Status Control Register.
    __I uint32_t MVFR0
     Offset: 0x010 (R/ ) Media and FP Feature Register 0.
    __I uint32_t MVFR1
     Offset: 0x014 (R/ ) Media and FP Feature Register 1.
    +

    Field Documentation

    + +
    +
    + + + + +
    __IO uint32_t FPU_Type::FPCAR
    +
    +
    + +
    +
    + +
    +
    + + + + +
    __IO uint32_t FPU_Type::FPCCR
    +
    +
    + +
    +
    + +
    +
    + + + + +
    __IO uint32_t FPU_Type::FPDSCR
    +
    +
    + +
    +
    + +
    +
    + + + + +
    __I uint32_t FPU_Type::MVFR0
    +
    +
    + +
    +
    + +
    +
    + + + + +
    __I uint32_t FPU_Type::MVFR1
    +
    +
    + +
    +
    + +
    +
    + + + + +
    uint32_t FPU_Type::RESERVED0[1]
    +
    +
    + +
    +
    +
    +
    + + + + + diff --git a/Libraries/CMSIS/Documentation/Core/html/struct_i_t_m___type.html b/Libraries/CMSIS/Documentation/Core/html/struct_i_t_m___type.html new file mode 100644 index 0000000..807428e --- /dev/null +++ b/Libraries/CMSIS/Documentation/Core/html/struct_i_t_m___type.html @@ -0,0 +1,298 @@ + + + + +ITM_Type Struct Reference + + + + + + + + + + + + + +
    + +
    + + + + + + + + + + + +
    +
    CMSIS-CORE +  Version 3.01 +
    +
    CMSIS-CORE support for Cortex-M processor-based devices
    +
    +
    + +
    + +
    + + + + +
    +
    + +
    +
    +
    + +
    +
    +
    +Data Fields
    +
    +
    ITM_Type Struct Reference
    +
    +
    + +

    Structure type to access the Instrumentation Trace Macrocell Register (ITM). +

    + + + + + + + + + + + + + + + + + + + + + + + +

    +Data Fields

    union {
       __O uint8_t   u8
     Offset: 0x000 ( /W) ITM Stimulus Port 8-bit.
       __O uint16_t   u16
     Offset: 0x000 ( /W) ITM Stimulus Port 16-bit.
       __O uint32_t   u32
     Offset: 0x000 ( /W) ITM Stimulus Port 32-bit.
    } PORT [32]
     Offset: 0x000 ( /W) ITM Stimulus Port Registers.
    uint32_t RESERVED0 [864]
     Reserved.
    __IO uint32_t TER
     Offset: 0xE00 (R/W) ITM Trace Enable Register.
    uint32_t RESERVED1 [15]
     Reserved.
    __IO uint32_t TPR
     Offset: 0xE40 (R/W) ITM Trace Privilege Register.
    uint32_t RESERVED2 [15]
     Reserved.
    __IO uint32_t TCR
     Offset: 0xE80 (R/W) ITM Trace Control Register.
    +

    Field Documentation

    + +
    +
    + + + + +
    __O { ... } ITM_Type::PORT[32]
    +
    +
    + +
    +
    + +
    +
    + + + + +
    uint32_t ITM_Type::RESERVED0[864]
    +
    +
    + +
    +
    + +
    +
    + + + + +
    uint32_t ITM_Type::RESERVED1[15]
    +
    +
    + +
    +
    + +
    +
    + + + + +
    uint32_t ITM_Type::RESERVED2[15]
    +
    +
    + +
    +
    + +
    +
    + + + + +
    __IO uint32_t ITM_Type::TCR
    +
    +
    + +
    +
    + +
    +
    + + + + +
    __IO uint32_t ITM_Type::TER
    +
    +
    + +
    +
    + +
    +
    + + + + +
    __IO uint32_t ITM_Type::TPR
    +
    +
    + +
    +
    + +
    +
    + + + + +
    __O uint16_t ITM_Type::u16
    +
    +
    + +
    +
    + +
    +
    + + + + +
    __O uint32_t ITM_Type::u32
    +
    +
    + +
    +
    + +
    +
    + + + + +
    __O uint8_t ITM_Type::u8
    +
    +
    + +
    +
    +
    +
    + + + + + diff --git a/Libraries/CMSIS/Documentation/Core/html/struct_m_p_u___type.html b/Libraries/CMSIS/Documentation/Core/html/struct_m_p_u___type.html new file mode 100644 index 0000000..6abb25b --- /dev/null +++ b/Libraries/CMSIS/Documentation/Core/html/struct_m_p_u___type.html @@ -0,0 +1,312 @@ + + + + +MPU_Type Struct Reference + + + + + + + + + + + + + +
    + +
    + + + + + + + + + + + +
    +
    CMSIS-CORE +  Version 3.01 +
    +
    CMSIS-CORE support for Cortex-M processor-based devices
    +
    +
    + +
    + +
    + + + + +
    +
    + +
    +
    +
    + +
    +
    +
    +Data Fields
    +
    +
    MPU_Type Struct Reference
    +
    +
    + +

    Structure type to access the Memory Protection Unit (MPU). +

    + + + + + + + + + + + + + + + + + + + + + + + + +

    +Data Fields

    __I uint32_t TYPE
     Offset: 0x000 (R/ ) MPU Type Register.
    __IO uint32_t CTRL
     Offset: 0x004 (R/W) MPU Control Register.
    __IO uint32_t RNR
     Offset: 0x008 (R/W) MPU Region RNRber Register.
    __IO uint32_t RBAR
     Offset: 0x00C (R/W) MPU Region Base Address Register.
    __IO uint32_t RASR
     Offset: 0x010 (R/W) MPU Region Attribute and Size Register.
    __IO uint32_t RBAR_A1
     Offset: 0x014 (R/W) MPU Alias 1 Region Base Address Register.
    __IO uint32_t RASR_A1
     Offset: 0x018 (R/W) MPU Alias 1 Region Attribute and Size Register.
    __IO uint32_t RBAR_A2
     Offset: 0x01C (R/W) MPU Alias 2 Region Base Address Register.
    __IO uint32_t RASR_A2
     Offset: 0x020 (R/W) MPU Alias 2 Region Attribute and Size Register.
    __IO uint32_t RBAR_A3
     Offset: 0x024 (R/W) MPU Alias 3 Region Base Address Register.
    __IO uint32_t RASR_A3
     Offset: 0x028 (R/W) MPU Alias 3 Region Attribute and Size Register.
    +

    Field Documentation

    + +
    +
    + + + + +
    __IO uint32_t MPU_Type::CTRL
    +
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    + +
    +
    + +
    +
    + + + + +
    __IO uint32_t MPU_Type::RASR
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    __IO uint32_t MPU_Type::RASR_A1
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    __IO uint32_t MPU_Type::RASR_A2
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    + + + + +
    __IO uint32_t MPU_Type::RASR_A3
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    + +
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    __IO uint32_t MPU_Type::RBAR
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    __IO uint32_t MPU_Type::RBAR_A1
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    __IO uint32_t MPU_Type::RBAR_A2
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    __IO uint32_t MPU_Type::RBAR_A3
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    +
    + + + + +
    __IO uint32_t MPU_Type::RNR
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    + +
    +
    + +
    +
    + + + + +
    __I uint32_t MPU_Type::TYPE
    +
    +
    + +
    +
    +
    +
    + + + + + diff --git a/Libraries/CMSIS/Documentation/Core/html/struct_n_v_i_c___type.html b/Libraries/CMSIS/Documentation/Core/html/struct_n_v_i_c___type.html new file mode 100644 index 0000000..63b78ca --- /dev/null +++ b/Libraries/CMSIS/Documentation/Core/html/struct_n_v_i_c___type.html @@ -0,0 +1,342 @@ + + + + +NVIC_Type Struct Reference + + + + + + + + + + + + + +
    + +
    + + + + + + + + + + + +
    +
    CMSIS-CORE +  Version 3.01 +
    +
    CMSIS-CORE support for Cortex-M processor-based devices
    +
    +
    + +
    + +
    + + + + +
    +
    + +
    +
    +
    + +
    +
    +
    +Data Fields
    +
    +
    NVIC_Type Struct Reference
    +
    +
    + +

    Structure type to access the Nested Vectored Interrupt Controller (NVIC). +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + +

    +Data Fields

    __IO uint32_t ISER [8]
     Offset: 0x000 (R/W) Interrupt Set Enable Register.
    uint32_t RESERVED0 [24]
     Reserved.
    __IO uint32_t ICER [8]
     Offset: 0x080 (R/W) Interrupt Clear Enable Register.
    uint32_t RSERVED1 [24]
     Reserved.
    __IO uint32_t ISPR [8]
     Offset: 0x100 (R/W) Interrupt Set Pending Register.
    uint32_t RESERVED2 [24]
     Reserved.
    __IO uint32_t ICPR [8]
     Offset: 0x180 (R/W) Interrupt Clear Pending Register.
    uint32_t RESERVED3 [24]
     Reserved.
    __IO uint32_t IABR [8]
     Offset: 0x200 (R/W) Interrupt Active bit Register.
    uint32_t RESERVED4 [56]
     Reserved.
    __IO uint8_t IP [240]
     Offset: 0x300 (R/W) Interrupt Priority Register (8Bit wide)
    uint32_t RESERVED5 [644]
     Reserved.
    __O uint32_t STIR
     Offset: 0xE00 ( /W) Software Trigger Interrupt Register.
    +

    Field Documentation

    + +
    +
    + + + + +
    __IO uint32_t NVIC_Type::IABR[8]
    +
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    __IO uint32_t NVIC_Type::ICER[8]
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    __IO uint32_t NVIC_Type::ICPR[8]
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    __IO uint8_t NVIC_Type::IP[240]
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    __IO uint32_t NVIC_Type::ISER[8]
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    __IO uint32_t NVIC_Type::ISPR[8]
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    uint32_t NVIC_Type::RESERVED0[24]
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    uint32_t NVIC_Type::RESERVED2[24]
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    uint32_t NVIC_Type::RESERVED3[24]
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    uint32_t NVIC_Type::RESERVED4[56]
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    uint32_t NVIC_Type::RESERVED5[644]
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    uint32_t NVIC_Type::RSERVED1[24]
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    + + + + +
    __O uint32_t NVIC_Type::STIR
    +
    +
    + +
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    +
    +
    + + + + + diff --git a/Libraries/CMSIS/Documentation/Core/html/struct_s_c_b___type.html b/Libraries/CMSIS/Documentation/Core/html/struct_s_c_b___type.html new file mode 100644 index 0000000..de2783a --- /dev/null +++ b/Libraries/CMSIS/Documentation/Core/html/struct_s_c_b___type.html @@ -0,0 +1,462 @@ + + + + +SCB_Type Struct Reference + + + + + + + + + + + + + +
    + +
    + + + + + + + + + + + +
    +
    CMSIS-CORE +  Version 3.01 +
    +
    CMSIS-CORE support for Cortex-M processor-based devices
    +
    +
    + +
    + +
    + + + + +
    +
    + +
    +
    +
    + +
    +
    +
    +Data Fields
    +
    +
    SCB_Type Struct Reference
    +
    +
    + +

    Structure type to access the System Control Block (SCB). +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +

    +Data Fields

    __I uint32_t CPUID
     Offset: 0x000 (R/ ) CPUID Base Register.
    __IO uint32_t ICSR
     Offset: 0x004 (R/W) Interrupt Control and State Register.
    __IO uint32_t VTOR
     Offset: 0x008 (R/W) Vector Table Offset Register.
    __IO uint32_t AIRCR
     Offset: 0x00C (R/W) Application Interrupt and Reset Control Register.
    __IO uint32_t SCR
     Offset: 0x010 (R/W) System Control Register.
    __IO uint32_t CCR
     Offset: 0x014 (R/W) Configuration Control Register.
    __IO uint8_t SHP [12]
     Offset: 0x018 (R/W) System Handlers Priority Registers (4-7, 8-11, 12-15)
    __IO uint32_t SHCSR
     Offset: 0x024 (R/W) System Handler Control and State Register.
    __IO uint32_t CFSR
     Offset: 0x028 (R/W) Configurable Fault Status Register.
    __IO uint32_t HFSR
     Offset: 0x02C (R/W) HardFault Status Register.
    __IO uint32_t DFSR
     Offset: 0x030 (R/W) Debug Fault Status Register.
    __IO uint32_t MMFAR
     Offset: 0x034 (R/W) MemManage Fault Address Register.
    __IO uint32_t BFAR
     Offset: 0x038 (R/W) BusFault Address Register.
    __IO uint32_t AFSR
     Offset: 0x03C (R/W) Auxiliary Fault Status Register.
    __I uint32_t PFR [2]
     Offset: 0x040 (R/ ) Processor Feature Register.
    __I uint32_t DFR
     Offset: 0x048 (R/ ) Debug Feature Register.
    __I uint32_t ADR
     Offset: 0x04C (R/ ) Auxiliary Feature Register.
    __I uint32_t MMFR [4]
     Offset: 0x050 (R/ ) Memory Model Feature Register.
    __I uint32_t ISAR [5]
     Offset: 0x060 (R/ ) Instruction Set Attributes Register.
    uint32_t RESERVED0 [5]
     Reserved.
    __IO uint32_t CPACR
     Offset: 0x088 (R/W) Coprocessor Access Control Register.
    +

    Field Documentation

    + +
    +
    + + + + +
    __I uint32_t SCB_Type::ADR
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    __IO uint32_t SCB_Type::AFSR
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    __IO uint32_t SCB_Type::AIRCR
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    __IO uint32_t SCB_Type::BFAR
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    __IO uint32_t SCB_Type::CCR
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    __IO uint32_t SCB_Type::CFSR
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    __IO uint32_t SCB_Type::CPACR
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    __I uint32_t SCB_Type::CPUID
    +
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    +
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    __I uint32_t SCB_Type::DFR
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    __IO uint32_t SCB_Type::DFSR
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    __IO uint32_t SCB_Type::HFSR
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    __IO uint32_t SCB_Type::ICSR
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    __I uint32_t SCB_Type::ISAR[5]
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    __IO uint32_t SCB_Type::MMFAR
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    __I uint32_t SCB_Type::MMFR[4]
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    __I uint32_t SCB_Type::PFR[2]
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    uint32_t SCB_Type::RESERVED0[5]
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    __IO uint32_t SCB_Type::SCR
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    __IO uint32_t SCB_Type::SHCSR
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    __IO uint8_t SCB_Type::SHP[12]
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    __IO uint32_t SCB_Type::VTOR
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    +
    + + + + + diff --git a/Libraries/CMSIS/Documentation/Core/html/struct_s_cn_s_c_b___type.html b/Libraries/CMSIS/Documentation/Core/html/struct_s_cn_s_c_b___type.html new file mode 100644 index 0000000..4c307fe --- /dev/null +++ b/Libraries/CMSIS/Documentation/Core/html/struct_s_cn_s_c_b___type.html @@ -0,0 +1,192 @@ + + + + +SCnSCB_Type Struct Reference + + + + + + + + + + + + + +
    + +
    + + + + + + + + + + + +
    +
    CMSIS-CORE +  Version 3.01 +
    +
    CMSIS-CORE support for Cortex-M processor-based devices
    +
    +
    + +
    + +
    + + + + +
    +
    + +
    +
    +
    + +
    +
    +
    +Data Fields
    +
    +
    SCnSCB_Type Struct Reference
    +
    +
    + +

    Structure type to access the System Control and ID Register not in the SCB. +

    + + + + + + + + +

    +Data Fields

    uint32_t RESERVED0 [1]
     Reserved.
    __I uint32_t ICTR
     Offset: 0x004 (R/ ) Interrupt Controller Type Register.
    __IO uint32_t ACTLR
     Offset: 0x008 (R/W) Auxiliary Control Register.
    +

    Field Documentation

    + +
    +
    + + + + +
    __IO uint32_t SCnSCB_Type::ACTLR
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    __I uint32_t SCnSCB_Type::ICTR
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    uint32_t SCnSCB_Type::RESERVED0[1]
    +
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    +
    +
    + + + + + diff --git a/Libraries/CMSIS/Documentation/Core/html/struct_sys_tick___type.html b/Libraries/CMSIS/Documentation/Core/html/struct_sys_tick___type.html new file mode 100644 index 0000000..81f2d6f --- /dev/null +++ b/Libraries/CMSIS/Documentation/Core/html/struct_sys_tick___type.html @@ -0,0 +1,207 @@ + + + + +SysTick_Type Struct Reference + + + + + + + + + + + + + +
    + +
    + + + + + + + + + + + +
    +
    CMSIS-CORE +  Version 3.01 +
    +
    CMSIS-CORE support for Cortex-M processor-based devices
    +
    +
    + +
    + +
    + + + + +
    +
    + +
    +
    +
    + +
    +
    +
    +Data Fields
    +
    +
    SysTick_Type Struct Reference
    +
    +
    + +

    Structure type to access the System Timer (SysTick). +

    + + + + + + + + + + +

    +Data Fields

    __IO uint32_t CTRL
     Offset: 0x000 (R/W) SysTick Control and Status Register.
    __IO uint32_t LOAD
     Offset: 0x004 (R/W) SysTick Reload Value Register.
    __IO uint32_t VAL
     Offset: 0x008 (R/W) SysTick Current Value Register.
    __I uint32_t CALIB
     Offset: 0x00C (R/ ) SysTick Calibration Register.
    +

    Field Documentation

    + +
    +
    + + + + +
    __I uint32_t SysTick_Type::CALIB
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    __IO uint32_t SysTick_Type::CTRL
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    __IO uint32_t SysTick_Type::LOAD
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    __IO uint32_t SysTick_Type::VAL
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    +
    + + + + + diff --git a/Libraries/CMSIS/Documentation/Core/html/struct_t_p_i___type.html b/Libraries/CMSIS/Documentation/Core/html/struct_t_p_i___type.html new file mode 100644 index 0000000..cadd4e0 --- /dev/null +++ b/Libraries/CMSIS/Documentation/Core/html/struct_t_p_i___type.html @@ -0,0 +1,507 @@ + + + + +TPI_Type Struct Reference + + + + + + + + + + + + + +
    + +
    + + + + + + + + + + + +
    +
    CMSIS-CORE +  Version 3.01 +
    +
    CMSIS-CORE support for Cortex-M processor-based devices
    +
    +
    + +
    + +
    + + + + +
    +
    + +
    +
    +
    + +
    +
    +
    +Data Fields
    +
    +
    TPI_Type Struct Reference
    +
    +
    + +

    Structure type to access the Trace Port Interface Register (TPI). +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +

    +Data Fields

    __IO uint32_t SSPSR
     Offset: 0x000 (R/ ) Supported Parallel Port Size Register.
    __IO uint32_t CSPSR
     Offset: 0x004 (R/W) Current Parallel Port Size Register.
    uint32_t RESERVED0 [2]
     Reserved.
    __IO uint32_t ACPR
     Offset: 0x010 (R/W) Asynchronous Clock Prescaler Register.
    uint32_t RESERVED1 [55]
     Reserved.
    __IO uint32_t SPPR
     Offset: 0x0F0 (R/W) Selected Pin Protocol Register.
    uint32_t RESERVED2 [131]
     Reserved.
    __I uint32_t FFSR
     Offset: 0x300 (R/ ) Formatter and Flush Status Register.
    __IO uint32_t FFCR
     Offset: 0x304 (R/W) Formatter and Flush Control Register.
    __I uint32_t FSCR
     Offset: 0x308 (R/ ) Formatter Synchronization Counter Register.
    uint32_t RESERVED3 [759]
     Reserved.
    __I uint32_t TRIGGER
     Offset: 0xEE8 (R/ ) TRIGGER.
    __I uint32_t FIFO0
     Offset: 0xEEC (R/ ) Integration ETM Data.
    __I uint32_t ITATBCTR2
     Offset: 0xEF0 (R/ ) ITATBCTR2.
    uint32_t RESERVED4 [1]
     Reserved.
    __I uint32_t ITATBCTR0
     Offset: 0xEF8 (R/ ) ITATBCTR0.
    __I uint32_t FIFO1
     Offset: 0xEFC (R/ ) Integration ITM Data.
    __IO uint32_t ITCTRL
     Offset: 0xF00 (R/W) Integration Mode Control.
    uint32_t RESERVED5 [39]
     Reserved.
    __IO uint32_t CLAIMSET
     Offset: 0xFA0 (R/W) Claim tag set.
    __IO uint32_t CLAIMCLR
     Offset: 0xFA4 (R/W) Claim tag clear.
    uint32_t RESERVED7 [8]
     Reserved.
    __I uint32_t DEVID
     Offset: 0xFC8 (R/ ) TPIU_DEVID.
    __I uint32_t DEVTYPE
     Offset: 0xFCC (R/ ) TPIU_DEVTYPE.
    +

    Field Documentation

    + +
    +
    + + + + +
    __IO uint32_t TPI_Type::ACPR
    +
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    __IO uint32_t TPI_Type::CLAIMCLR
    +
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    __IO uint32_t TPI_Type::CLAIMSET
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    __IO uint32_t TPI_Type::CSPSR
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    __I uint32_t TPI_Type::DEVID
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    __I uint32_t TPI_Type::DEVTYPE
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    __IO uint32_t TPI_Type::FFCR
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    __I uint32_t TPI_Type::FFSR
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    __I uint32_t TPI_Type::FIFO0
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    __I uint32_t TPI_Type::FIFO1
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    __I uint32_t TPI_Type::FSCR
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    __I uint32_t TPI_Type::ITATBCTR0
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    __I uint32_t TPI_Type::ITATBCTR2
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    __IO uint32_t TPI_Type::ITCTRL
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    uint32_t TPI_Type::RESERVED0[2]
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    uint32_t TPI_Type::RESERVED1[55]
    +
    +
    + +
    +
    + +
    +
    + + + + +
    uint32_t TPI_Type::RESERVED2[131]
    +
    +
    + +
    +
    + +
    +
    + + + + +
    uint32_t TPI_Type::RESERVED3[759]
    +
    +
    + +
    +
    + +
    +
    + + + + +
    uint32_t TPI_Type::RESERVED4[1]
    +
    +
    + +
    +
    + +
    +
    + + + + +
    uint32_t TPI_Type::RESERVED5[39]
    +
    +
    + +
    +
    + +
    +
    + + + + +
    uint32_t TPI_Type::RESERVED7[8]
    +
    +
    + +
    +
    + +
    +
    + + + + +
    __IO uint32_t TPI_Type::SPPR
    +
    +
    + +
    +
    + +
    +
    + + + + +
    __IO uint32_t TPI_Type::SSPSR
    +
    +
    + +
    +
    + +
    +
    + + + + +
    __I uint32_t TPI_Type::TRIGGER
    +
    +
    + +
    +
    +
    +
    + + + + + diff --git a/Libraries/CMSIS/Documentation/Core/html/system_c_pg.html b/Libraries/CMSIS/Documentation/Core/html/system_c_pg.html new file mode 100644 index 0000000..04920b0 --- /dev/null +++ b/Libraries/CMSIS/Documentation/Core/html/system_c_pg.html @@ -0,0 +1,286 @@ + + + + +System Configuration Files system_<device>.c and system_<device>.h + + + + + + + + + + + + + +
    + +
    + + + + + + + + + + + +
    +
    CMSIS-CORE +  Version 3.01 +
    +
    CMSIS-CORE support for Cortex-M processor-based devices
    +
    +
    + +
    + +
    + + + +
    +
    + +
    +
    +
    + +
    +
    +
    +
    System Configuration Files system_<device>.c and system_<device>.h
    +
    +
    +

    The System Configuration Files system_<device>.c and system_<device>.h provides as a minimum the functions described under System and Clock Configuration. These functions are device specific and need adaptations. In addition, the file might have configuration settings for the device such as XTAL frequency or PLL prescaler settings.

    +

    For devices with external memory BUS the system_<device>.c also configures the BUS system.

    +

    The silicon vendor might expose other functions (i.e. for power configuration) in the system_<device>.c file. In case of additional features the function prototypes need to be added to the system_<device>.h header file.

    +

    +system_Device.c Template File

    +

    The system_Device.c Template File for the Cortex-M3 is shown below.

    +
    /**************************************************************************//**
+ * @file     system_<Device>.c
+ * @brief    CMSIS Cortex-M# Device Peripheral Access Layer Source File for
+ *           Device <Device>
+ * @version  V3.01
+ * @date     06. March 2012
+ *
+ * @note
+ * Copyright (C) 2010-2012 ARM Limited. All rights reserved.
+ *
+ * @par
+ * ARM Limited (ARM) is supplying this software for use with Cortex-M 
+ * processor based microcontrollers.  This file can be freely distributed 
+ * within development tools that are supporting such ARM based processors. 
+ *
+ * @par
+ * THIS SOFTWARE IS PROVIDED "AS IS".  NO WARRANTIES, WHETHER EXPRESS, IMPLIED
+ * OR STATUTORY, INCLUDING, BUT NOT LIMITED TO, IMPLIED WARRANTIES OF
+ * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE APPLY TO THIS SOFTWARE.
+ * ARM SHALL NOT, IN ANY CIRCUMSTANCES, BE LIABLE FOR SPECIAL, INCIDENTAL, OR
+ * CONSEQUENTIAL DAMAGES, FOR ANY REASON WHATSOEVER.
+ *
+ ******************************************************************************/
+
+
+#include <stdint.h>
+#include "<Device>.h"
+
+
+/*----------------------------------------------------------------------------
+  DEFINES
+ *----------------------------------------------------------------------------*/
+    
+/*----------------------------------------------------------------------------
+  Define clocks
+ *----------------------------------------------------------------------------*/
+/* ToDo: add here your necessary defines for device initialization     
+         following is an example for different system frequencies             */
+#define __HSI             ( 6000000UL)
+#define __XTAL            (12000000UL)    /* Oscillator frequency             */
+#define __SYS_OSC_CLK     (    ___HSI)    /* Main oscillator frequency        */
+
+#define __SYSTEM_CLOCK    (4*__XTAL)
+
+
+/*----------------------------------------------------------------------------
+  Clock Variable definitions
+ *----------------------------------------------------------------------------*/
+/* ToDo: initialize SystemCoreClock with the system core clock frequency value
+         achieved after system intitialization.
+         This means system core clock frequency after call to SystemInit()    */
+uint32_t SystemCoreClock = __SYSTEM_CLOCK;  /*!< System Clock Frequency (Core Clock)*/
+
+
+/*----------------------------------------------------------------------------
+  Clock functions
+ *----------------------------------------------------------------------------*/
+void SystemCoreClockUpdate (void)            /* Get Core Clock Frequency      */
+{
+/* ToDo: add code to calculate the system frequency based upon the current
+         register settings.
+         This function can be used to retrieve the system core clock frequeny
+         after user changed register sittings.                                */
+  SystemCoreClock = __SYSTEM_CLOCK;
+}
+
+/**
+ * Initialize the system
+ *
+ * @param  none
+ * @return none
+ *
+ * @brief  Setup the microcontroller system.
+ *         Initialize the System.
+ */
+void SystemInit (void)
+{
+/* ToDo: add code to initialize the system
+         do not use global variables because this function is called before
+         reaching pre-main. RW section maybe overwritten afterwards.          */
+  SystemCoreClock = __SYSTEM_CLOCK;
+}
+

    +system_Device.h Template File

    +

    The system_<device>.h header file contains prototypes to access the public functions in the system_<device>.c file. The system_Device.h Template File is shown below.

    +
    /**************************************************************************//**
+ * @file     system_<Device>.h
+ * @brief    CMSIS Cortex-M# Device Peripheral Access Layer Header File for
+ *           Device <Device>
+ * @version  V3.01
+ * @date     06. March 2012
+ *
+ * @note
+ * Copyright (C) 2010-2012 ARM Limited. All rights reserved.
+ *
+ * @par
+ * ARM Limited (ARM) is supplying this software for use with Cortex-M 
+ * processor based microcontrollers.  This file can be freely distributed 
+ * within development tools that are supporting such ARM based processors. 
+ *
+ * @par
+ * THIS SOFTWARE IS PROVIDED "AS IS".  NO WARRANTIES, WHETHER EXPRESS, IMPLIED
+ * OR STATUTORY, INCLUDING, BUT NOT LIMITED TO, IMPLIED WARRANTIES OF
+ * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE APPLY TO THIS SOFTWARE.
+ * ARM SHALL NOT, IN ANY CIRCUMSTANCES, BE LIABLE FOR SPECIAL, INCIDENTAL, OR
+ * CONSEQUENTIAL DAMAGES, FOR ANY REASON WHATSOEVER.
+ *
+ ******************************************************************************/
+
+
+#ifndef SYSTEM_<Device>_H   /* ToDo: replace '<Device>' with your device name */
+#define SYSTEM_<Device>_H
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+#include <stdint.h>
+
+extern uint32_t SystemCoreClock;     /*!< System Clock Frequency (Core Clock)  */
+
+
+/**
+ * Initialize the system
+ *
+ * @param  none
+ * @return none
+ *
+ * @brief  Setup the microcontroller system.
+ *         Initialize the System and update the SystemCoreClock variable.
+ */
+extern void SystemInit (void);
+
+/**
+ * Update SystemCoreClock variable
+ *
+ * @param  none
+ * @return none
+ *
+ * @brief  Updates the SystemCoreClock with current core Clock 
+ *         retrieved from cpu registers.
+ */
+extern void SystemCoreClockUpdate (void);
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* SYSTEM_<Device>_H */
+
    +
    + + + + + diff --git a/Libraries/CMSIS/Documentation/Core/html/tab_a.png b/Libraries/CMSIS/Documentation/Core/html/tab_a.png new file mode 100644 index 0000000000000000000000000000000000000000..d54650ed50091bfe27c391fe884b3f201c1fc75c GIT binary patch literal 142 zcmeAS@N?(olHy`uVBq!ia0vp^j6kfy!2~3aiye;!QlXwMjv*C{Z|5Fd=@ck(WRgsU zM!w=Bze4>#djC%S(=IB^S7kPyeC5FF&-b6!l-!#ydp-K>M6oDe2M4o8#;a$3zn|^< r%8SRFH@5HW&Ye#a-mgyn-*80!Wh;}Bo$ca&pal$`u6{1-oD!M<8F4nl literal 0 HcmV?d00001 diff --git a/Libraries/CMSIS/Documentation/Core/html/tab_b.png b/Libraries/CMSIS/Documentation/Core/html/tab_b.png new file mode 100644 index 0000000000000000000000000000000000000000..4122a84ec9e24c61bb4da567d055ba7618ecb4e4 GIT binary patch literal 174 zcmeAS@N?(olHy`uVBq!ia0vp^j6kfy!2~3aiye;!Ql*|Qjv*C{Z|@rNH5rIBJe>Zo z-9&&_bfKGzhVFXT52yJ2*6~$LcrW+qUybK!?z7Uf%onY5x!coWa8~>BpCiZb3W!zh zmk?YieJTFgH;)~0h2=}%rp@wOxqjj)*EQTBxeu=R$ms9>^hPt=Khd4*wdIYA9UX!b Z<*mBj&uL9@*22WQ%mvv4FO#o&0L}dT~ literal 0 HcmV?d00001 diff --git a/Libraries/CMSIS/Documentation/Core/html/tab_h.png b/Libraries/CMSIS/Documentation/Core/html/tab_h.png new file mode 100644 index 0000000000000000000000000000000000000000..bf9eb52274d7403dc9279cf6c0ed1d8b8280dec5 GIT binary patch literal 198 zcmV;%06G7OP)z10001uNklGc1iHn){NtS(c4@;tZP+F?+qmW{ zs@Oz#)?vkGSh4gitHU2F-?H$m5)t(=LCt5=H~YFG)0F6*$N&HU07*qoM6N<$f=ij_a^J=A#w=pqJBS3j3^P6m$n4Fmh;vZIjzaOYW($mE;L?bwP&!1v`W*G*{f+Gf}ZW`Y?#K7?7bfqP8fBG+= OA_h-aKbLh*2~7acPeJzp literal 0 HcmV?d00001 diff --git a/Libraries/CMSIS/Documentation/Core/html/tabs.css b/Libraries/CMSIS/Documentation/Core/html/tabs.css new file mode 100644 index 0000000..ffbab50 --- /dev/null +++ b/Libraries/CMSIS/Documentation/Core/html/tabs.css @@ -0,0 +1,71 @@ +.tabs, .tabs1, .tabs2, .tabs3 { + background-image: url('tab_b.png'); + width: 100%; + z-index: 101; + font-size: 10px; +} + +.tabs1 { + background-image: url('tab_topnav.png'); + font-size: 12px; +} + +.tabs2 { + font-size: 10px; +} +.tabs3 { + font-size: 9px; +} + +.tablist { + margin: 0; + padding: 0; + display: table; + line-height: 24px; +} + +.tablist li { + float: left; + display: table-cell; + background-image: url('tab_b.png'); + list-style: none; +} + +.tabs1 .tablist li { + float: left; + display: table-cell; + background-image: url('tab_topnav.png'); + list-style: none; +} + +.tablist a { + display: block; + padding: 0 20px; + font-weight: bold; + background-image:url('tab_s.png'); + background-repeat:no-repeat; + background-position:right; + color: #283A5D; + text-shadow: 0px 1px 1px rgba(255, 255, 255, 0.9); + text-decoration: none; + outline: none; +} + +.tabs3 .tablist a { + padding: 0 10px; +} + +.tablist a:hover { + background-image: url('tab_h.png'); + background-repeat:repeat-x; + color: #fff; + text-shadow: 0px 1px 1px rgba(0, 0, 0, 1.0); + text-decoration: none; +} + +.tablist li.current a { + background-image: url('tab_a.png'); + background-repeat:repeat-x; + color: #fff; + text-shadow: 0px 1px 1px rgba(0, 0, 0, 1.0); +} diff --git a/Libraries/CMSIS/Documentation/Core/html/union_a_p_s_r___type.html b/Libraries/CMSIS/Documentation/Core/html/union_a_p_s_r___type.html new file mode 100644 index 0000000..9bcc52f --- /dev/null +++ b/Libraries/CMSIS/Documentation/Core/html/union_a_p_s_r___type.html @@ -0,0 +1,268 @@ + + + + +APSR_Type Union Reference + + + + + + + + + + + + + +
    + +
    + + + + + + + + + + + +
    +
    CMSIS-CORE +  Version 3.01 +
    +
    CMSIS-CORE support for Cortex-M processor-based devices
    +
    +
    + +
    + +
    + + + + +
    +
    + +
    +
    +
    + +
    +
    +
    +Data Fields
    +
    +
    APSR_Type Union Reference
    +
    +
    + +

    Union type to access the Application Program Status Register (APSR). +

    + + + + + + + + + + + + + + + + + + + +

    +Data Fields

    struct {
       uint32_t   _reserved0:27
     bit: 0..26 Reserved
       uint32_t   Q:1
     bit: 27 Saturation condition flag
       uint32_t   V:1
     bit: 28 Overflow condition code flag
       uint32_t   C:1
     bit: 29 Carry condition code flag
       uint32_t   Z:1
     bit: 30 Zero condition code flag
       uint32_t   N:1
     bit: 31 Negative condition code flag
    } b
     Structure used for bit access.
    uint32_t w
     Type used for word access.
    +

    Field Documentation

    + +
    +
    + + + + +
    uint32_t APSR_Type::_reserved0
    +
    +
    + +
    +
    + +
    +
    + + + + +
    struct { ... } APSR_Type::b
    +
    +
    + +
    +
    + +
    +
    + + + + +
    uint32_t APSR_Type::C
    +
    +
    + +
    +
    + +
    +
    + + + + +
    uint32_t APSR_Type::N
    +
    +
    + +
    +
    + +
    +
    + + + + +
    uint32_t APSR_Type::Q
    +
    +
    + +
    +
    + +
    +
    + + + + +
    uint32_t APSR_Type::V
    +
    +
    + +
    +
    + +
    +
    + + + + +
    uint32_t APSR_Type::w
    +
    +
    + +
    +
    + +
    +
    + + + + +
    uint32_t APSR_Type::Z
    +
    +
    + +
    +
    +
    +
    + + + + + diff --git a/Libraries/CMSIS/Documentation/Core/html/union_c_o_n_t_r_o_l___type.html b/Libraries/CMSIS/Documentation/Core/html/union_c_o_n_t_r_o_l___type.html new file mode 100644 index 0000000..b943e12 --- /dev/null +++ b/Libraries/CMSIS/Documentation/Core/html/union_c_o_n_t_r_o_l___type.html @@ -0,0 +1,238 @@ + + + + +CONTROL_Type Union Reference + + + + + + + + + + + + + +
    + +
    + + + + + + + + + + + +
    +
    CMSIS-CORE +  Version 3.01 +
    +
    CMSIS-CORE support for Cortex-M processor-based devices
    +
    +
    + +
    + +
    + + + + +
    +
    + +
    +
    +
    + +
    +
    +
    +Data Fields
    +
    +
    CONTROL_Type Union Reference
    +
    +
    + +

    Union type to access the Control Registers (CONTROL). +

    + + + + + + + + + + + + + + + +

    +Data Fields

    struct {
       uint32_t   nPRIV:1
     bit: 0 Execution privilege in Thread mode
       uint32_t   SPSEL:1
     bit: 1 Stack to be used
       uint32_t   FPCA:1
     bit: 2 FP extension active flag
       uint32_t   _reserved0:29
     bit: 3..31 Reserved
    } b
     Structure used for bit access.
    uint32_t w
     Type used for word access.
    +

    Field Documentation

    + +
    +
    + + + + +
    uint32_t CONTROL_Type::_reserved0
    +
    +
    + +
    +
    + +
    +
    + + + + +
    struct { ... } CONTROL_Type::b
    +
    +
    + +
    +
    + +
    +
    + + + + +
    uint32_t CONTROL_Type::FPCA
    +
    +
    + +
    +
    + +
    +
    + + + + +
    uint32_t CONTROL_Type::nPRIV
    +
    +
    + +
    +
    + +
    +
    + + + + +
    uint32_t CONTROL_Type::SPSEL
    +
    +
    + +
    +
    + +
    +
    + + + + +
    uint32_t CONTROL_Type::w
    +
    +
    + +
    +
    +
    +
    + + + + + diff --git a/Libraries/CMSIS/Documentation/Core/html/union_i_p_s_r___type.html b/Libraries/CMSIS/Documentation/Core/html/union_i_p_s_r___type.html new file mode 100644 index 0000000..f2cd1c0 --- /dev/null +++ b/Libraries/CMSIS/Documentation/Core/html/union_i_p_s_r___type.html @@ -0,0 +1,208 @@ + + + + +IPSR_Type Union Reference + + + + + + + + + + + + + +
    + +
    + + + + + + + + + + + +
    +
    CMSIS-CORE +  Version 3.01 +
    +
    CMSIS-CORE support for Cortex-M processor-based devices
    +
    +
    + +
    + +
    + + + + +
    +
    + +
    +
    +
    + +
    +
    +
    +Data Fields
    +
    +
    IPSR_Type Union Reference
    +
    +
    + +

    Union type to access the Interrupt Program Status Register (IPSR). +

    + + + + + + + + + + + +

    +Data Fields

    struct {
       uint32_t   ISR:9
     bit: 0.. 8 Exception number
       uint32_t   _reserved0:23
     bit: 9..31 Reserved
    } b
     Structure used for bit access.
    uint32_t w
     Type used for word access.
    +

    Field Documentation

    + +
    +
    + + + + +
    uint32_t IPSR_Type::_reserved0
    +
    +
    + +
    +
    + +
    +
    + + + + +
    struct { ... } IPSR_Type::b
    +
    +
    + +
    +
    + +
    +
    + + + + +
    uint32_t IPSR_Type::ISR
    +
    +
    + +
    +
    + +
    +
    + + + + +
    uint32_t IPSR_Type::w
    +
    +
    + +
    +
    +
    +
    + + + + + diff --git a/Libraries/CMSIS/Documentation/Core/html/unionx_p_s_r___type.html b/Libraries/CMSIS/Documentation/Core/html/unionx_p_s_r___type.html new file mode 100644 index 0000000..1816f20 --- /dev/null +++ b/Libraries/CMSIS/Documentation/Core/html/unionx_p_s_r___type.html @@ -0,0 +1,313 @@ + + + + +xPSR_Type Union Reference + + + + + + + + + + + + + +
    + +
    + + + + + + + + + + + +
    +
    CMSIS-CORE +  Version 3.01 +
    +
    CMSIS-CORE support for Cortex-M processor-based devices
    +
    +
    + +
    + +
    + + + + +
    +
    + +
    +
    +
    + +
    +
    +
    +Data Fields
    +
    +
    xPSR_Type Union Reference
    +
    +
    + +

    Union type to access the Special-Purpose Program Status Registers (xPSR). +

    + + + + + + + + + + + + + + + + + + + + + + + + + +

    +Data Fields

    struct {
       uint32_t   ISR:9
     bit: 0.. 8 Exception number
       uint32_t   _reserved0:15
     bit: 9..23 Reserved
       uint32_t   T:1
     bit: 24 Thumb bit (read 0)
       uint32_t   IT:2
     bit: 25..26 saved IT state (read 0)
       uint32_t   Q:1
     bit: 27 Saturation condition flag
       uint32_t   V:1
     bit: 28 Overflow condition code flag
       uint32_t   C:1
     bit: 29 Carry condition code flag
       uint32_t   Z:1
     bit: 30 Zero condition code flag
       uint32_t   N:1
     bit: 31 Negative condition code flag
    } b
     Structure used for bit access.
    uint32_t w
     Type used for word access.
    +

    Field Documentation

    + +
    +
    + + + + +
    uint32_t xPSR_Type::_reserved0
    +
    +
    + +
    +
    + +
    +
    + + + + +
    struct { ... } xPSR_Type::b
    +
    +
    + +
    +
    + +
    +
    + + + + +
    uint32_t xPSR_Type::C
    +
    +
    + +
    +
    + +
    +
    + + + + +
    uint32_t xPSR_Type::ISR
    +
    +
    + +
    +
    + +
    +
    + + + + +
    uint32_t xPSR_Type::IT
    +
    +
    + +
    +
    + +
    +
    + + + + +
    uint32_t xPSR_Type::N
    +
    +
    + +
    +
    + +
    +
    + + + + +
    uint32_t xPSR_Type::Q
    +
    +
    + +
    +
    + +
    +
    + + + + +
    uint32_t xPSR_Type::T
    +
    +
    + +
    +
    + +
    +
    + + + + +
    uint32_t xPSR_Type::V
    +
    +
    + +
    +
    + +
    +
    + + + + +
    uint32_t xPSR_Type::w
    +
    +
    + +
    +
    + +
    +
    + + + + +
    uint32_t xPSR_Type::Z
    +
    +
    + +
    +
    +
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background-color:#F8F1F1; +} +.group2 +{ + background-color:#DCEDEA; +} + + +ul ul { + list-style-type: disc; +} + +ul ul ul { + list-style-type: disc; +} + +ul.hierarchy { + color: green; +} + +em { + color: #000000; + font-style:italic; +} + + + +/* CMSIS Tables */ +table.cmtab1 { + padding: 4px; + border-collapse: collapse; + border: 1px solid #A3B4D7; + text-align: justify; + width:70%; +} + +th.cmtab1 { + background: #EBEFF6; + font-weight: bold; + height: 28px; +} + +td.cmtab1 { + padding:1px; + text-align: left; +} + +table.cmtable { + border-collapse:collapse; + text-align: justify; +} + +table.cmtable td, table.cmtable th { + border: 1px solid #2D4068; + padding: 3px 7px 2px; +} + +table.cmtable th { + background-color: #EBEFF6; + border: 1px solid #2D4068; + font-size: 110%; + padding-bottom: 4px; + padding-top: 5px; + text-align:left; + height: 28px; +} + +td.MonoTxt { + font-family:"Arial monospaced for SAP"; +} + +span.XML-Token +{ + azimuth: 180; + font-style:italic; + color:Maroon; + z-index:20; + +} + +/* @group Heading Levels */ + +h1 { + font-size: 150%; +} + +.title { + font-size: 150%; + font-weight: bold; + margin: 10px 2px; +} + +h2 { + font-size: 120%; +} + +h3 { + font-size: 100%; +} + +dt { + font-weight: bold; +} + +div.multicol { + -moz-column-gap: 1em; + -webkit-column-gap: 1em; + -moz-column-count: 3; + -webkit-column-count: 3; +} + +p.startli, p.startdd, p.starttd { + margin-top: 2px; +} + +p.endli { + margin-bottom: 0px; +} + +p.enddd { + margin-bottom: 4px; +} + +p.endtd { + margin-bottom: 2px; +} + +/* @end */ + +caption { + font-weight: bold; +} + +span.legend { + font-size: 70%; + text-align: center; +} + +h3.version { + font-size: 90%; + text-align: center; +} + +div.qindex, div.navtab{ + background-color: #EBEFF6; + border: 1px solid #A3B4D7; + text-align: center; + margin: 2px; + padding: 2px; +} + +div.qindex, div.navpath { + width: 100%; + line-height: 140%; +} + +div.navtab { + margin-right: 15px; +} + +/* @group Link Styling */ + +a { + color: #3D578C; + font-weight: normal; + text-decoration: none; +} + +.contents a:visited { + color: #4665A2; +} + +a:hover { + text-decoration: underline; +} + +a.qindex { + font-weight: bold; +} + +a.qindexHL { + font-weight: bold; + background-color: #9CAFD4; + color: #ffffff; + border: 1px double #869DCA; +} + +.contents a.qindexHL:visited { + color: #ffffff; +} + +a.el { + font-weight: bold; +} + +a.elRef { +} + +a.code { + color: #4665A2; +} + +a.codeRef { + color: #4665A2; +} + +/* @end */ + +dl.el { + margin-left: -1cm; +} + +.fragment { + font-family: monospace, fixed; + font-size: 105%; +} + +pre.fragment { + border: 1px solid #C4CFE5; + background-color: #FBFCFD; + padding: 4px 6px; + margin: 4px 8px 4px 2px; + overflow: auto; + word-wrap: break-word; + font-size: 9pt; + line-height: 125%; +} + +div.ah { + background-color: black; + font-weight: bold; + color: #ffffff; + margin-bottom: 3px; + margin-top: 3px; + padding: 0.2em; + border: solid thin #333; + border-radius: 0.5em; + -webkit-border-radius: .5em; + -moz-border-radius: .5em; + box-shadow: 2px 2px 3px #999; + -webkit-box-shadow: 2px 2px 3px #999; + -moz-box-shadow: rgba(0, 0, 0, 0.15) 2px 2px 2px; + background-image: -webkit-gradient(linear, left top, left bottom, from(#eee), to(#000),color-stop(0.3, #444)); + background-image: -moz-linear-gradient(center top, #eee 0%, #444 40%, #000); +} + +div.groupHeader { + margin-left: 16px; + margin-top: 12px; + font-weight: bold; +} + +div.groupText { + margin-left: 16px; + font-style: italic; +} + +body { + background: white; + color: black; + margin: 0; +} + +div.contents { + margin-top: 10px; + margin-left: 10px; + margin-right: 5px; +} + +td.indexkey { + background-color: #EBEFF6; + font-weight: bold; + border: 1px solid #C4CFE5; + margin: 2px 0px 2px 0; + padding: 2px 10px; +} + +td.indexvalue { + background-color: #EBEFF6; + border: 1px solid #C4CFE5; + padding: 2px 10px; + margin: 2px 0px; +} + +tr.memlist { + background-color: #EEF1F7; +} + +p.formulaDsp { + text-align: center; +} + +img.formulaDsp { + +} + +img.formulaInl { + vertical-align: middle; +} + +div.center { + text-align: center; + margin-top: 0px; + margin-bottom: 0px; + padding: 0px; +} + +div.center img { + border: 0px; +} + +address.footer { + text-align: right; + padding-right: 12px; +} + +img.footer { + border: 0px; + vertical-align: middle; +} + +/* @group Code Colorization */ + +span.keyword { + color: #008000 +} + +span.keywordtype { + color: #604020 +} + +span.keywordflow { + color: #e08000 +} + +span.comment { + color: #800000 +} + +span.preprocessor { + color: #806020 +} + +span.stringliteral { + color: #002080 +} + +span.charliteral { + color: #008080 +} + +span.vhdldigit { + color: #ff00ff +} + +span.vhdlchar { + color: #000000 +} + +span.vhdlkeyword { + color: #700070 +} + +span.vhdllogic { + color: #ff0000 +} + +/* @end */ + +/* +.search { + color: #003399; + font-weight: bold; +} + +form.search { + margin-bottom: 0px; + margin-top: 0px; +} + +input.search { + font-size: 75%; + color: #000080; + font-weight: normal; + background-color: #e8eef2; +} +*/ + +td.tiny { + font-size: 75%; +} + +.dirtab { + padding: 4px; + border-collapse: collapse; + border: 1px solid #A3B4D7; +} + +th.dirtab { + background: #EBEFF6; + font-weight: bold; +} + +hr { + height: 0px; + border: none; + border-top: 1px solid #4A6AAA; +} + +hr.footer { + height: 1px; +} + +/* @group Member Descriptions */ + +table.memberdecls { + border-spacing: 0px; + padding: 0px; +} + +.mdescLeft, .mdescRight, +.memItemLeft, .memItemRight, +.memTemplItemLeft, .memTemplItemRight, .memTemplParams { + background-color: #F9FAFC; + border: none; + margin: 4px; + padding: 1px 0 0 8px; +} + +.mdescLeft, .mdescRight { + padding: 0px 8px 4px 8px; + color: #555; +} + +.memItemLeft, .memItemRight, .memTemplParams { + border-top: 1px solid #C4CFE5; +} + +.memItemLeft, .memTemplItemLeft { + white-space: nowrap; +} + +.memItemRight { + width: 100%; +} + +.memTemplParams { + color: #4665A2; + white-space: nowrap; +} + +/* @end */ + +/* @group Member Details */ + +/* Styles for detailed member documentation */ + +.memtemplate { + font-size: 80%; + color: #4665A2; + font-weight: normal; + margin-left: 9px; +} + +.memnav { + background-color: #EBEFF6; + border: 1px solid #A3B4D7; + text-align: center; + margin: 2px; + margin-right: 15px; + padding: 2px; +} + +.mempage { + width: 100%; +} + +.memitem { + padding: 0; + margin-bottom: 10px; + margin-right: 5px; +} + +.memname { + white-space: nowrap; + font-weight: bold; + margin-left: 6px; +} + +.memproto { + border-top: 1px solid #A8B8D9; + border-left: 1px solid #A8B8D9; + border-right: 1px solid #A8B8D9; + padding: 6px 0px 6px 0px; + color: #253555; + font-weight: bold; + text-shadow: 0px 1px 1px rgba(255, 255, 255, 0.9); + /* opera specific markup */ + box-shadow: 5px 5px 5px rgba(0, 0, 0, 0.15); + border-top-right-radius: 8px; + border-top-left-radius: 8px; + /* firefox specific markup */ + -moz-box-shadow: rgba(0, 0, 0, 0.15) 5px 5px 5px; + -moz-border-radius-topright: 8px; + -moz-border-radius-topleft: 8px; + /* webkit specific markup */ + -webkit-box-shadow: 5px 5px 5px rgba(0, 0, 0, 0.15); + -webkit-border-top-right-radius: 8px; + -webkit-border-top-left-radius: 8px; + background-image:url('nav_f.png'); + background-repeat:repeat-x; + background-color: #E2E8F2; + +} + +.memdoc { + border-bottom: 1px solid #A8B8D9; + border-left: 1px solid #A8B8D9; + border-right: 1px solid #A8B8D9; + padding: 2px 5px; + background-color: #FBFCFD; + border-top-width: 0; + /* opera specific markup */ + border-bottom-left-radius: 8px; + border-bottom-right-radius: 8px; + box-shadow: 5px 5px 5px rgba(0, 0, 0, 0.15); + /* firefox specific markup */ + -moz-border-radius-bottomleft: 8px; + -moz-border-radius-bottomright: 8px; + -moz-box-shadow: rgba(0, 0, 0, 0.15) 5px 5px 5px; + background-image: -moz-linear-gradient(center top, #FFFFFF 0%, #FFFFFF 60%, #F7F8FB 95%, #EEF1F7); + /* webkit specific markup */ + -webkit-border-bottom-left-radius: 8px; + -webkit-border-bottom-right-radius: 8px; + -webkit-box-shadow: 5px 5px 5px rgba(0, 0, 0, 0.15); + background-image: -webkit-gradient(linear,center top,center bottom,from(#FFFFFF), color-stop(0.6,#FFFFFF), color-stop(0.60,#FFFFFF), color-stop(0.95,#F7F8FB), to(#EEF1F7)); +} + +.paramkey { + text-align: right; +} + +.paramtype { + white-space: nowrap; +} + +.paramname { + color: #602020; + white-space: nowrap; +} +.paramname em { + font-style: normal; +} + +.params, .retval, .exception, .tparams { + border-spacing: 6px 2px; +} + +.params .paramname, .retval .paramname { + font-weight: bold; + vertical-align: top; +} + +.params .paramtype { + font-style: italic; + vertical-align: top; +} + +.params .paramdir { + font-family: "courier new",courier,monospace; + vertical-align: top; +} + + + + +/* @end */ + +/* @group Directory (tree) */ + +/* for the tree view */ + +.ftvtree { + font-family: sans-serif; + margin: 0px; +} + +/* these are for tree view when used as main index */ + +.directory { + font-size: 9pt; + font-weight: bold; + margin: 5px; +} + +.directory h3 { + margin: 0px; + margin-top: 1em; + font-size: 11pt; +} + +/* +The following two styles can be used to replace the root node title +with an image of your choice. Simply uncomment the next two styles, +specify the name of your image and be sure to set 'height' to the +proper pixel height of your image. +*/ + +/* +.directory h3.swap { + height: 61px; + background-repeat: no-repeat; + background-image: url("yourimage.gif"); +} +.directory h3.swap span { + display: none; +} +*/ + +.directory > h3 { + margin-top: 0; +} + +.directory p { + margin: 0px; + white-space: nowrap; +} + +.directory div { + display: none; + margin: 0px; +} + +.directory img { + vertical-align: -30%; +} + +/* these are for tree view when not used as main index */ + +.directory-alt { + font-size: 100%; + font-weight: bold; +} + +.directory-alt h3 { + margin: 0px; + margin-top: 1em; + font-size: 11pt; +} + +.directory-alt > h3 { + margin-top: 0; +} + +.directory-alt p { + margin: 0px; + white-space: nowrap; +} + +.directory-alt div { + display: none; + margin: 0px; +} + +.directory-alt img { + vertical-align: -30%; +} + +/* @end */ + +div.dynheader { + margin-top: 8px; +} + +address { + font-style: normal; + color: #2A3D61; +} + +table.doxtable { + border-collapse:collapse; +} + +table.doxtable td, table.doxtable th { + border: 1px solid #2D4068; + padding: 3px 7px 2px; +} + +table.doxtable th { + background-color: #374F7F; + color: #FFFFFF; + font-size: 110%; + padding-bottom: 4px; + padding-top: 5px; + text-align:left; +} + +.tabsearch { + top: 0px; + left: 10px; + height: 36px; + background-image: url('tab_b.png'); + z-index: 101; + overflow: hidden; + font-size: 13px; +} + +.navpath ul +{ + font-size: 11px; + background-image:url('tab_b.png'); + background-repeat:repeat-x; + height:30px; + line-height:30px; + color:#8AA0CC; + border:solid 1px #C2CDE4; + overflow:hidden; + margin:0px; + padding:0px; +} + +.navpath li +{ + list-style-type:none; + float:left; + padding-left:10px; + padding-right:15px; + background-image:url('bc_s.png'); + background-repeat:no-repeat; + background-position:right; + color:#364D7C; +} + +.navpath li.navelem a +{ + height:32px; + display:block; + text-decoration: none; + outline: none; +} + +.navpath li.navelem a:hover +{ + color:#6884BD; +} + +.navpath li.footer +{ + list-style-type:none; + float:right; + padding-left:10px; + padding-right:15px; + background-image:none; + background-repeat:no-repeat; + background-position:right; + color:#364D7C; + font-size: 8pt; +} + + +div.summary +{ + float: right; + font-size: 8pt; + padding-right: 5px; + width: 50%; + text-align: right; +} + +div.summary a +{ + white-space: nowrap; +} + +div.ingroups +{ + font-size: 8pt; + padding-left: 5px; + width: 50%; + text-align: left; +} + +div.ingroups a +{ + white-space: nowrap; +} + +div.header +{ + background-image:url('nav_h.png'); + background-repeat:repeat-x; + background-color: #F9FAFC; + margin: 0px; + border-bottom: 1px solid #C4CFE5; +} + +div.headertitle +{ + padding: 5px 5px 5px 10px; +} + +dl +{ + padding: 0 0 0 10px; +} + +dl.note, dl.warning, dl.attention, dl.pre, dl.post, dl.invariant, dl.deprecated, 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    + +
    + + + + + + + + + + + +
    +
    CMSIS +  Version 3.01 +
    +
    Cortex Microcontroller Software Interface Standard
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    + +
    + + +
    +
    + +
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    + +
    +
    +
    +
    Introduction
    +
    +
    +

    The Cortex Microcontroller Software Interface Standard (CMSIS) is a vendor-independent hardware abstraction layer for the Cortex-M processor series. The CMSIS enables consistent and simple software interfaces to the processor and the peripherals, simplifying software re-use, reducing the learning curve for microcontroller developers, and reducing the time to market for new devices.

    +

    The CMSIS is defined in close cooperation with various silicon and software vendors and provides a common approach to interface to peripherals, real-time operating systems, and middleware components. The CMSIS is intended to enable the combination of software components from multiple middleware vendors.

    +

    The CMSIS components are:

    +
      +
    • CMSIS-CORE: API for the Cortex-M processor core and peripherals. It provides at standardized interface for Cortex-M0, Cortex-M3, Cortex-M4, SC000, and SC300. Included are also SIMD intrinsic functions for Cortex-M4 SIMD instructions.
      • +
    +
      +
    • CMSIS-DSP: DSP Library Collection with over 60 Functions for various data types: fix-point (fractional q7, q15, q31) and single precision floating-point (32-bit). The library is available for Cortex-M0, Cortex-M3, and Cortex-M4. The Cortex-M4 implementation is optimized for the SIMD instruction set.
      • +
    +
      +
    • CMSIS-RTOS API: Common API for Real-Time operating systems. It provides a standardized programming interface that is portable to many RTOS and enables therefore software templates, middleware, libraries, and other components that can work acrosss supported the RTOS systems.
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    +
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    • CMSIS-SVD: System View Description for Peripherals. Describes the peripherals of a device in an XML file and can be used to create peripheral awareness in debuggers or header files with peripheral register and interrupt definitions.
      • +
    +
    +CMSIS_V3_small.png +
    +CMSIS Structure
    +

    +Motivation

    +

    CMSIS has been created to help the industry in standardization. It is not a huge software layer that introduces overhead and does not define standard peripherals. The silicon industry can therefore support the wide variations of Cortex-M processor-based devices with this common standard. In detail the benefits of the CMSIS are:

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      +
    • Consistent software interfaces improve the software portability and re-usability. Generic software libraries can interface with device libraries from various silicon vendors.
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    • Reduces the learning curve, development costs, and time-to-market. Developers can write software quicker through an easy to use and standardized software interface.
      • +
    • Provides a compiler independent layer that allows using different compilers. CMSIS is supported by all mainstream compilers (ARMCC, IAR, and GNU).
      • +
    • Enhances program debugging with peripheral information for debuggers and ITM channels for printf-style output and RTOS kernel awareness.
      • +
    +

    +Coding Rules

    +

    The CMSIS uses the following essential coding rules and conventions:

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      +
    • Compliant with ANSI C and C++.
      • +
    • Uses ANSI C standard data types defined in <stdint.h>.
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    • Variables and parameters have a complete data type.
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    • Expressions for #define constants are enclosed in parenthesis.
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    • Conforms to MISRA 2004. MIRSA rule violations are documented.
      • +
    +

    In addition, the CMSIS recommends the following conventions for identifiers:

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      +
    • CAPITAL names to identify Core Registers, Peripheral Registers, and CPU Instructions.
      • +
    • CamelCase names to identify function names and interrupt functions.
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    • Namespace_ prefixes avoid clashes with user identifiers and provide functional groups (i.e. for peripherals, RTOS, or DSP Library).
      • +
    +

    The CMSIS is documented within the source files with:

    +
      +
    • Comments that use the C or C++ style.
      • +
    • Doxygen compliant function comments that provide:
        +
      • brief function overview.
        • +
      • detailed description of the function.
        • +
      • detailed parameter explanation.
        • +
      • detailed information about return values.
        • +
      +
      • +
    +

    Doxygen comment example:

    +
    +/** 
+ * @brief  Enable Interrupt in NVIC Interrupt Controller
+ * @param  IRQn  interrupt number that specifies the interrupt
+ * @return none.
+ * Enable the specified interrupt in the NVIC Interrupt Controller.
+ * Other settings of the interrupt such as priority are not affected.
+ */
+

    +Licence

    +

    The CMSIS is provided free of charge by ARM and can be used for all Cortex-M based devices. View the LICENCE AGREEMENT for CMSIS in detail.

    +
    +
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j;if((c.browser.msie&&(/(static|relative)/).test(this.css("position")))||(/absolute/).test(this.css("position"))){j=this.parents().filter(function(){return(/(relative|absolute|fixed)/).test(c.curCSS(this,"position",1))&&(/(auto|scroll)/).test(c.curCSS(this,"overflow",1)+c.curCSS(this,"overflow-y",1)+c.curCSS(this,"overflow-x",1))}).eq(0)}else{j=this.parents().filter(function(){return(/(auto|scroll)/).test(c.curCSS(this,"overflow",1)+c.curCSS(this,"overflow-y",1)+c.curCSS(this,"overflow-x",1))}).eq(0)}return(/fixed/).test(this.css("position"))||!j.length?c(document):j}});c.extend(c.expr[":"],{data:function(l,k,j){return !!c.data(l,j[3])},focusable:function(k){var l=k.nodeName.toLowerCase(),j=c.attr(k,"tabindex");return(/input|select|textarea|button|object/.test(l)?!k.disabled:"a"==l||"area"==l?k.href||!isNaN(j):!isNaN(j))&&!c(k)["area"==l?"parents":"closest"](":hidden").length},tabbable:function(k){var j=c.attr(k,"tabindex");return(isNaN(j)||j>=0)&&c(k).is(":focusable")}});function g(m,n,o,l){function k(q){var p=c[m][n][q]||[];return(typeof p=="string"?p.split(/,?\s+/):p)}var j=k("getter");if(l.length==1&&typeof l[0]=="string"){j=j.concat(k("getterSetter"))}return(c.inArray(o,j)!=-1)}c.widget=function(k,j){var l=k.split(".")[0];k=k.split(".")[1];c.fn[k]=function(p){var n=(typeof p=="string"),o=Array.prototype.slice.call(arguments,1);if(n&&p.substring(0,1)=="_"){return this}if(n&&g(l,k,p,o)){var m=c.data(this[0],k);return(m?m[p].apply(m,o):undefined)}return this.each(function(){var q=c.data(this,k);(!q&&!n&&c.data(this,k,new c[l][k](this,p))._init());(q&&n&&c.isFunction(q[p])&&q[p].apply(q,o))})};c[l]=c[l]||{};c[l][k]=function(o,n){var m=this;this.namespace=l;this.widgetName=k;this.widgetEventPrefix=c[l][k].eventPrefix||k;this.widgetBaseClass=l+"-"+k;this.options=c.extend({},c.widget.defaults,c[l][k].defaults,c.metadata&&c.metadata.get(o)[k],n);this.element=c(o).bind("setData."+k,function(q,p,r){if(q.target==o){return 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false}});if(c.browser.msie){this._mouseUnselectable=this.element.attr("unselectable");this.element.attr("unselectable","on")}this.started=false},_mouseDestroy:function(){this.element.unbind("."+this.widgetName);(c.browser.msie&&this.element.attr("unselectable",this._mouseUnselectable))},_mouseDown:function(l){l.originalEvent=l.originalEvent||{};if(l.originalEvent.mouseHandled){return}(this._mouseStarted&&this._mouseUp(l));this._mouseDownEvent=l;var k=this,m=(l.which==1),j=(typeof this.options.cancel=="string"?c(l.target).parents().add(l.target).filter(this.options.cancel).length:false);if(!m||j||!this._mouseCapture(l)){return true}this.mouseDelayMet=!this.options.delay;if(!this.mouseDelayMet){this._mouseDelayTimer=setTimeout(function(){k.mouseDelayMet=true},this.options.delay)}if(this._mouseDistanceMet(l)&&this._mouseDelayMet(l)){this._mouseStarted=(this._mouseStart(l)!==false);if(!this._mouseStarted){l.preventDefault();return true}}this._mouseMoveDelegate=function(n){return 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false},_mouseDistanceMet:function(j){return(Math.max(Math.abs(this._mouseDownEvent.pageX-j.pageX),Math.abs(this._mouseDownEvent.pageY-j.pageY))>=this.options.distance)},_mouseDelayMet:function(j){return this.mouseDelayMet},_mouseStart:function(j){},_mouseDrag:function(j){},_mouseStop:function(j){},_mouseCapture:function(j){return true}};c.ui.mouse.defaults={cancel:null,distance:1,delay:0}})(jQuery);;/* * jQuery UI Resizable 1.7.2 + * + * Copyright (c) 2009 AUTHORS.txt (http://jqueryui.com/about) + * Dual licensed under the MIT (MIT-LICENSE.txt) + * and GPL (GPL-LICENSE.txt) licenses. + * + * http://docs.jquery.com/UI/Resizables + * + * Depends: + * ui.core.js + */ +(function(c){c.widget("ui.resizable",c.extend({},c.ui.mouse,{_init:function(){var e=this,j=this.options;this.element.addClass("ui-resizable");c.extend(this,{_aspectRatio:!!(j.aspectRatio),aspectRatio:j.aspectRatio,originalElement:this.element,_proportionallyResizeElements:[],_helper:j.helper||j.ghost||j.animate?j.helper||"ui-resizable-helper":null});if(this.element[0].nodeName.match(/canvas|textarea|input|select|button|img/i)){if(/relative/.test(this.element.css("position"))&&c.browser.opera){this.element.css({position:"relative",top:"auto",left:"auto"})}this.element.wrap(c('
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i=this.className.match(/ui-resizable-(se|sw|ne|nw|n|e|s|w)/i)}e.axis=i&&i[1]?i[1]:"se"}});if(j.autoHide){this._handles.hide();c(this.element).addClass("ui-resizable-autohide").hover(function(){c(this).removeClass("ui-resizable-autohide");e._handles.show()},function(){if(!e.resizing){c(this).addClass("ui-resizable-autohide");e._handles.hide()}})}this._mouseInit()},destroy:function(){this._mouseDestroy();var d=function(f){c(f).removeClass("ui-resizable ui-resizable-disabled ui-resizable-resizing").removeData("resizable").unbind(".resizable").find(".ui-resizable-handle").remove()};if(this.elementIsWrapper){d(this.element);var e=this.element;e.parent().append(this.originalElement.css({position:e.css("position"),width:e.outerWidth(),height:e.outerHeight(),top:e.css("top"),left:e.css("left")})).end().remove()}this.originalElement.css("resize",this.originalResizeStyle);d(this.originalElement)},_mouseCapture:function(e){var f=false;for(var d in this.handles){if(c(this.handles[d])[0]==e.target){f=true}}return this.options.disabled||!!f},_mouseStart:function(f){var i=this.options,e=this.element.position(),d=this.element;this.resizing=true;this.documentScroll={top:c(document).scrollTop(),left:c(document).scrollLeft()};if(d.is(".ui-draggable")||(/absolute/).test(d.css("position"))){d.css({position:"absolute",top:e.top,left:e.left})}if(c.browser.opera&&(/relative/).test(d.css("position"))){d.css({position:"relative",top:"auto",left:"auto"})}this._renderProxy();var j=b(this.helper.css("left")),g=b(this.helper.css("top"));if(i.containment){j+=c(i.containment).scrollLeft()||0;g+=c(i.containment).scrollTop()||0}this.offset=this.helper.offset();this.position={left:j,top:g};this.size=this._helper?{width:d.outerWidth(),height:d.outerHeight()}:{width:d.width(),height:d.height()};this.originalSize=this._helper?{width:d.outerWidth(),height:d.outerHeight()}:{width:d.width(),height:d.height()};this.originalPosition={left:j,top:g};this.sizeDiff={width:d.outerWidth()-d.width(),height:d.outerHeight()-d.height()};this.originalMousePosition={left:f.pageX,top:f.pageY};this.aspectRatio=(typeof i.aspectRatio=="number")?i.aspectRatio:((this.originalSize.width/this.originalSize.height)||1);var h=c(".ui-resizable-"+this.axis).css("cursor");c("body").css("cursor",h=="auto"?this.axis+"-resize":h);d.addClass("ui-resizable-resizing");this._propagate("start",f);return true},_mouseDrag:function(d){var g=this.helper,f=this.options,l={},p=this,i=this.originalMousePosition,m=this.axis;var q=(d.pageX-i.left)||0,n=(d.pageY-i.top)||0;var h=this._change[m];if(!h){return false}var k=h.apply(this,[d,q,n]),j=c.browser.msie&&c.browser.version<7,e=this.sizeDiff;if(this._aspectRatio||d.shiftKey){k=this._updateRatio(k,d)}k=this._respectSize(k,d);this._propagate("resize",d);g.css({top:this.position.top+"px",left:this.position.left+"px",width:this.size.width+"px",height:this.size.height+"px"});if(!this._helper&&this._proportionallyResizeElements.length){this._proportionallyResize()}this._updateCache(k);this._trigger("resize",d,this.ui());return false},_mouseStop:function(g){this.resizing=false;var h=this.options,l=this;if(this._helper){var f=this._proportionallyResizeElements,d=f.length&&(/textarea/i).test(f[0].nodeName),e=d&&c.ui.hasScroll(f[0],"left")?0:l.sizeDiff.height,j=d?0:l.sizeDiff.width;var m={width:(l.size.width-j),height:(l.size.height-e)},i=(parseInt(l.element.css("left"),10)+(l.position.left-l.originalPosition.left))||null,k=(parseInt(l.element.css("top"),10)+(l.position.top-l.originalPosition.top))||null;if(!h.animate){this.element.css(c.extend(m,{top:k,left:i}))}l.helper.height(l.size.height);l.helper.width(l.size.width);if(this._helper&&!h.animate){this._proportionallyResize()}}c("body").css("cursor","auto");this.element.removeClass("ui-resizable-resizing");this._propagate("stop",g);if(this._helper){this.helper.remove()}return false},_updateCache:function(d){var e=this.options;this.offset=this.helper.offset();if(a(d.left)){this.position.left=d.left}if(a(d.top)){this.position.top=d.top}if(a(d.height)){this.size.height=d.height}if(a(d.width)){this.size.width=d.width}},_updateRatio:function(g,f){var h=this.options,i=this.position,e=this.size,d=this.axis;if(g.height){g.width=(e.height*this.aspectRatio)}else{if(g.width){g.height=(e.width/this.aspectRatio)}}if(d=="sw"){g.left=i.left+(e.width-g.width);g.top=null}if(d=="nw"){g.top=i.top+(e.height-g.height);g.left=i.left+(e.width-g.width)}return g},_respectSize:function(k,f){var i=this.helper,h=this.options,q=this._aspectRatio||f.shiftKey,p=this.axis,s=a(k.width)&&h.maxWidth&&(h.maxWidthk.width),r=a(k.height)&&h.minHeight&&(h.minHeight>k.height);if(g){k.width=h.minWidth}if(r){k.height=h.minHeight}if(s){k.width=h.maxWidth}if(l){k.height=h.maxHeight}var e=this.originalPosition.left+this.originalSize.width,n=this.position.top+this.size.height;var j=/sw|nw|w/.test(p),d=/nw|ne|n/.test(p);if(g&&j){k.left=e-h.minWidth}if(s&&j){k.left=e-h.maxWidth}if(r&&d){k.top=n-h.minHeight}if(l&&d){k.top=n-h.maxHeight}var m=!k.width&&!k.height;if(m&&!k.left&&k.top){k.top=null}else{if(m&&!k.top&&k.left){k.left=null}}return k},_proportionallyResize:function(){var j=this.options;if(!this._proportionallyResizeElements.length){return}var f=this.helper||this.element;for(var e=0;e');var d=c.browser.msie&&c.browser.version<7,f=(d?1:0),g=(d?2:-1);this.helper.addClass(this._helper).css({width:this.element.outerWidth()+g,height:this.element.outerHeight()+g,position:"absolute",left:this.elementOffset.left-f+"px",top:this.elementOffset.top-f+"px",zIndex:++h.zIndex});this.helper.appendTo("body").disableSelection()}else{this.helper=this.element}},_change:{e:function(f,e,d){return{width:this.originalSize.width+e}},w:function(g,e,d){var i=this.options,f=this.originalSize,h=this.originalPosition;return{left:h.left+e,width:f.width-e}},n:function(g,e,d){var i=this.options,f=this.originalSize,h=this.originalPosition;return{top:h.top+d,height:f.height-d}},s:function(f,e,d){return{height:this.originalSize.height+d}},se:function(f,e,d){return c.extend(this._change.s.apply(this,arguments),this._change.e.apply(this,[f,e,d]))},sw:function(f,e,d){return c.extend(this._change.s.apply(this,arguments),this._change.w.apply(this,[f,e,d]))},ne:function(f,e,d){return c.extend(this._change.n.apply(this,arguments),this._change.e.apply(this,[f,e,d]))},nw:function(f,e,d){return c.extend(this._change.n.apply(this,arguments),this._change.w.apply(this,[f,e,d]))}},_propagate:function(e,d){c.ui.plugin.call(this,e,[d,this.ui()]);(e!="resize"&&this._trigger(e,d,this.ui()))},plugins:{},ui:function(){return{originalElement:this.originalElement,element:this.element,helper:this.helper,position:this.position,size:this.size,originalSize:this.originalSize,originalPosition:this.originalPosition}}}));c.extend(c.ui.resizable,{version:"1.7.2",eventPrefix:"resize",defaults:{alsoResize:false,animate:false,animateDuration:"slow",animateEasing:"swing",aspectRatio:false,autoHide:false,cancel:":input,option",containment:false,delay:0,distance:1,ghost:false,grid:false,handles:"e,s,se",helper:false,maxHeight:null,maxWidth:null,minHeight:10,minWidth:10,zIndex:1000}});c.ui.plugin.add("resizable","alsoResize",{start:function(e,f){var d=c(this).data("resizable"),g=d.options;_store=function(h){c(h).each(function(){c(this).data("resizable-alsoresize",{width:parseInt(c(this).width(),10),height:parseInt(c(this).height(),10),left:parseInt(c(this).css("left"),10),top:parseInt(c(this).css("top"),10)})})};if(typeof(g.alsoResize)=="object"&&!g.alsoResize.parentNode){if(g.alsoResize.length){g.alsoResize=g.alsoResize[0];_store(g.alsoResize)}else{c.each(g.alsoResize,function(h,i){_store(h)})}}else{_store(g.alsoResize)}},resize:function(f,h){var e=c(this).data("resizable"),i=e.options,g=e.originalSize,k=e.originalPosition;var j={height:(e.size.height-g.height)||0,width:(e.size.width-g.width)||0,top:(e.position.top-k.top)||0,left:(e.position.left-k.left)||0},d=function(l,m){c(l).each(function(){var p=c(this),q=c(this).data("resizable-alsoresize"),o={},n=m&&m.length?m:["width","height","top","left"];c.each(n||["width","height","top","left"],function(r,t){var s=(q[t]||0)+(j[t]||0);if(s&&s>=0){o[t]=s||null}});if(/relative/.test(p.css("position"))&&c.browser.opera){e._revertToRelativePosition=true;p.css({position:"absolute",top:"auto",left:"auto"})}p.css(o)})};if(typeof(i.alsoResize)=="object"&&!i.alsoResize.nodeType){c.each(i.alsoResize,function(l,m){d(l,m)})}else{d(i.alsoResize)}},stop:function(e,f){var d=c(this).data("resizable");if(d._revertToRelativePosition&&c.browser.opera){d._revertToRelativePosition=false;el.css({position:"relative"})}c(this).removeData("resizable-alsoresize-start")}});c.ui.plugin.add("resizable","animate",{stop:function(h,m){var n=c(this).data("resizable"),i=n.options;var g=n._proportionallyResizeElements,d=g.length&&(/textarea/i).test(g[0].nodeName),e=d&&c.ui.hasScroll(g[0],"left")?0:n.sizeDiff.height,k=d?0:n.sizeDiff.width;var f={width:(n.size.width-k),height:(n.size.height-e)},j=(parseInt(n.element.css("left"),10)+(n.position.left-n.originalPosition.left))||null,l=(parseInt(n.element.css("top"),10)+(n.position.top-n.originalPosition.top))||null;n.element.animate(c.extend(f,l&&j?{top:l,left:j}:{}),{duration:i.animateDuration,easing:i.animateEasing,step:function(){var o={width:parseInt(n.element.css("width"),10),height:parseInt(n.element.css("height"),10),top:parseInt(n.element.css("top"),10),left:parseInt(n.element.css("left"),10)};if(g&&g.length){c(g[0]).css({width:o.width,height:o.height})}n._updateCache(o);n._propagate("resize",h)}})}});c.ui.plugin.add("resizable","containment",{start:function(e,q){var s=c(this).data("resizable"),i=s.options,k=s.element;var f=i.containment,j=(f instanceof c)?f.get(0):(/parent/.test(f))?k.parent().get(0):f;if(!j){return}s.containerElement=c(j);if(/document/.test(f)||f==document){s.containerOffset={left:0,top:0};s.containerPosition={left:0,top:0};s.parentData={element:c(document),left:0,top:0,width:c(document).width(),height:c(document).height()||document.body.parentNode.scrollHeight}}else{var m=c(j),h=[];c(["Top","Right","Left","Bottom"]).each(function(p,o){h[p]=b(m.css("padding"+o))});s.containerOffset=m.offset();s.containerPosition=m.position();s.containerSize={height:(m.innerHeight()-h[3]),width:(m.innerWidth()-h[1])};var n=s.containerOffset,d=s.containerSize.height,l=s.containerSize.width,g=(c.ui.hasScroll(j,"left")?j.scrollWidth:l),r=(c.ui.hasScroll(j)?j.scrollHeight:d);s.parentData={element:j,left:n.left,top:n.top,width:g,height:r}}},resize:function(f,p){var s=c(this).data("resizable"),h=s.options,e=s.containerSize,n=s.containerOffset,l=s.size,m=s.position,q=s._aspectRatio||f.shiftKey,d={top:0,left:0},g=s.containerElement;if(g[0]!=document&&(/static/).test(g.css("position"))){d=n}if(m.left<(s._helper?n.left:0)){s.size.width=s.size.width+(s._helper?(s.position.left-n.left):(s.position.left-d.left));if(q){s.size.height=s.size.width/h.aspectRatio}s.position.left=h.helper?n.left:0}if(m.top<(s._helper?n.top:0)) +{s.size.height=s.size.height+(s._helper?(s.position.top-n.top):s.position.top);if(q){s.size.width=s.size.height*h.aspectRatio}s.position.top=s._helper?n.top:0}s.offset.left=s.parentData.left+s.position.left;s.offset.top=s.parentData.top+s.position.top;var k=Math.abs((s._helper?s.offset.left-d.left:(s.offset.left-d.left))+s.sizeDiff.width),r=Math.abs((s._helper?s.offset.top-d.top:(s.offset.top-n.top))+s.sizeDiff.height);var j=s.containerElement.get(0)==s.element.parent().get(0),i=/relative|absolute/.test(s.containerElement.css("position"));if(j&&i){k-=s.parentData.left}if(k+s.size.width>=s.parentData.width){s.size.width=s.parentData.width-k;if(q){s.size.height=s.size.width/s.aspectRatio}}if(r+s.size.height>=s.parentData.height){s.size.height=s.parentData.height-r;if(q){s.size.width=s.size.height*s.aspectRatio}}},stop:function(e,m){var p=c(this).data("resizable"),f=p.options,k=p.position,l=p.containerOffset,d=p.containerPosition,g=p.containerElement;var i=c(p.helper),q=i.offset(),n=i.outerWidth()-p.sizeDiff.width,j=i.outerHeight()-p.sizeDiff.height;if(p._helper&&!f.animate&&(/relative/).test(g.css("position"))){c(this).css({left:q.left-d.left-l.left,width:n,height:j})}if(p._helper&&!f.animate&&(/static/).test(g.css("position"))){c(this).css({left:q.left-d.left-l.left,width:n,height:j})}}});c.ui.plugin.add("resizable","ghost",{start:function(f,g){var d=c(this).data("resizable"),h=d.options,e=d.size;d.ghost=d.originalElement.clone();d.ghost.css({opacity:0.25,display:"block",position:"relative",height:e.height,width:e.width,margin:0,left:0,top:0}).addClass("ui-resizable-ghost").addClass(typeof h.ghost=="string"?h.ghost:"");d.ghost.appendTo(d.helper)},resize:function(e,f){var d=c(this).data("resizable"),g=d.options;if(d.ghost){d.ghost.css({position:"relative",height:d.size.height,width:d.size.width})}},stop:function(e,f){var d=c(this).data("resizable"),g=d.options;if(d.ghost&&d.helper){d.helper.get(0).removeChild(d.ghost.get(0))}}});c.ui.plugin.add("resizable","grid",{resize:function(d,l){var n=c(this).data("resizable"),g=n.options,j=n.size,h=n.originalSize,i=n.originalPosition,m=n.axis,k=g._aspectRatio||d.shiftKey;g.grid=typeof g.grid=="number"?[g.grid,g.grid]:g.grid;var f=Math.round((j.width-h.width)/(g.grid[0]||1))*(g.grid[0]||1),e=Math.round((j.height-h.height)/(g.grid[1]||1))*(g.grid[1]||1);if(/^(se|s|e)$/.test(m)){n.size.width=h.width+f;n.size.height=h.height+e}else{if(/^(ne)$/.test(m)){n.size.width=h.width+f;n.size.height=h.height+e;n.position.top=i.top-e}else{if(/^(sw)$/.test(m)){n.size.width=h.width+f;n.size.height=h.height+e;n.position.left=i.left-f}else{n.size.width=h.width+f;n.size.height=h.height+e;n.position.top=i.top-e;n.position.left=i.left-f}}}}});var b=function(d){return parseInt(d,10)||0};var a=function(d){return !isNaN(parseInt(d,10))}})(jQuery);; +/** + * jQuery.ScrollTo - Easy element scrolling using jQuery. + * Copyright (c) 2008 Ariel Flesler - aflesler(at)gmail(dot)com + * Licensed under GPL license (http://www.opensource.org/licenses/gpl-license.php). + * Date: 2/8/2008 + * @author Ariel Flesler + * @version 1.3.2 + */ +;(function($){var o=$.scrollTo=function(a,b,c){o.window().scrollTo(a,b,c)};o.defaults={axis:'y',duration:1};o.window=function(){return $($.browser.safari?'body':'html')};$.fn.scrollTo=function(l,m,n){if(typeof m=='object'){n=m;m=0}n=$.extend({},o.defaults,n);m=m||n.speed||n.duration;n.queue=n.queue&&n.axis.length>1;if(n.queue)m/=2;n.offset=j(n.offset);n.over=j(n.over);return this.each(function(){var a=this,b=$(a),t=l,c,d={},w=b.is('html,body');switch(typeof t){case'number':case'string':if(/^([+-]=)?\d+(px)?$/.test(t)){t=j(t);break}t=$(t,this);case'object':if(t.is||t.style)c=(t=$(t)).offset()}$.each(n.axis.split(''),function(i,f){var P=f=='x'?'Left':'Top',p=P.toLowerCase(),k='scroll'+P,e=a[k],D=f=='x'?'Width':'Height';if(c){d[k]=c[p]+(w?0:e-b.offset()[p]);if(n.margin){d[k]-=parseInt(t.css('margin'+P))||0;d[k]-=parseInt(t.css('border'+P+'Width'))||0}d[k]+=n.offset[p]||0;if(n.over[p])d[k]+=t[D.toLowerCase()]()*n.over[p]}else d[k]=t[p];if(/^\d+$/.test(d[k]))d[k]=d[k]<=0?0:Math.min(d[k],h(D));if(!i&&n.queue){if(e!=d[k])g(n.onAfterFirst);delete d[k]}});g(n.onAfter);function g(a){b.animate(d,m,n.easing,a&&function(){a.call(this,l)})};function h(D){var b=w?$.browser.opera?document.body:document.documentElement:a;return b['scroll'+D]-b['client'+D]}})};function j(a){return typeof a=='object'?a:{top:a,left:a}}})(jQuery); + diff --git a/Libraries/CMSIS/Documentation/General/html/nav_f.png b/Libraries/CMSIS/Documentation/General/html/nav_f.png new file mode 100644 index 0000000000000000000000000000000000000000..1b07a16207e67c95fe2ee17e7016e6d08ac7ac99 GIT binary patch literal 159 zcmeAS@N?(olHy`uVBq!ia0vp^j6iI`!2~2XGqLUlQfZzpjv*C{Z|{2YIT`Y>1X`Eg z-tTbne1`SITM8Q!Pb(<)UFZ(m>wMzvKZQqKM~~GcZ=A7j<~E6K62>ozFS=cD3)mf8 z9WX0+R&m(l9KUsLdTx4?9~({T__KA%`}olPJ^N;y|F^pHgs_K%!rj~{8>RwnWbkzL Kb6Mw<&;$VTdq1fF literal 0 HcmV?d00001 diff --git a/Libraries/CMSIS/Documentation/General/html/nav_h.png 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0, 1.0); +} + +#nav-tree img { + margin:0px; + padding:0px; + border:0px; + vertical-align: middle; +} + +#nav-tree a { + text-decoration:none; + padding:0px; + margin:0px; + outline:none; +} + +#nav-tree .label { + margin:0px; + padding:0px; +} + +#nav-tree .label a { + padding:2px; +} + +#nav-tree .selected a { + text-decoration:none; + padding:2px; + margin:0px; + color:#fff; +} + +#nav-tree .children_ul { + margin:0px; + padding:0px; +} + +#nav-tree .item { + margin:0px; + padding:0px; +} + +#nav-tree { + padding: 0px 0px; + background-color: #FAFAFF; + font-size:14px; + overflow:auto; +} + +#doc-content { + overflow:auto; + display:block; + padding:0px; + margin:0px; +} + +#side-nav { + padding:0 6px 0 0; + margin: 0px; + display:block; + position: absolute; + left: 0px; + width: 300px; +} + +.ui-resizable .ui-resizable-handle { + display:block; +} + +.ui-resizable-e { + background:url("ftv2splitbar.png") repeat scroll right center transparent; + cursor:e-resize; + height:100%; + right:0; + top:0; + width:6px; +} + +.ui-resizable-handle { + display:none; + font-size:0.1px; + position:absolute; + z-index:1; +} + +#nav-tree-contents { + margin: 6px 0px 0px 0px; +} + +#nav-tree { + background-image:url('nav_h.png'); + background-repeat:repeat-x; + background-color: #F9FAFC; +} + + + diff --git a/Libraries/CMSIS/Documentation/General/html/navtree.js b/Libraries/CMSIS/Documentation/General/html/navtree.js new file mode 100644 index 0000000..5bcb5c7 --- /dev/null +++ b/Libraries/CMSIS/Documentation/General/html/navtree.js @@ -0,0 +1,252 @@ +var NAVTREE = +[ + [ "CMSIS", "index.html", [ + [ "Introduction", "index.html", null ] + ] ] +]; + +function createIndent(o,domNode,node,level) +{ + if (node.parentNode && node.parentNode.parentNode) + { + createIndent(o,domNode,node.parentNode,level+1); + } + var imgNode = document.createElement("img"); + if (level==0 && node.childrenData) + { + node.plus_img = imgNode; + node.expandToggle = document.createElement("a"); + node.expandToggle.href = "javascript:void(0)"; + node.expandToggle.onclick = function() + { + if (node.expanded) + { + $(node.getChildrenUL()).slideUp("fast"); + if (node.isLast) + { + node.plus_img.src = node.relpath+"ftv2plastnode.png"; + } + else + { + node.plus_img.src = node.relpath+"ftv2pnode.png"; + } + node.expanded = false; + } + else + { + expandNode(o, node, false); + } + } + node.expandToggle.appendChild(imgNode); + domNode.appendChild(node.expandToggle); + } + else + { + domNode.appendChild(imgNode); + } + if (level==0) + { + if (node.isLast) + { + if (node.childrenData) + { + imgNode.src = node.relpath+"ftv2plastnode.png"; + } + else + { + imgNode.src = node.relpath+"ftv2lastnode.png"; + domNode.appendChild(imgNode); + } + } + else + { + if (node.childrenData) + { + imgNode.src = node.relpath+"ftv2pnode.png"; + } + else + { + imgNode.src = node.relpath+"ftv2node.png"; + domNode.appendChild(imgNode); + } + } + } + else + { + if (node.isLast) + { + imgNode.src = node.relpath+"ftv2blank.png"; + } + else + { + imgNode.src = node.relpath+"ftv2vertline.png"; + } + } + imgNode.border = "0"; +} + +function newNode(o, po, text, link, childrenData, lastNode) +{ + var node = new Object(); + node.children = Array(); + node.childrenData = childrenData; + node.depth = po.depth + 1; + node.relpath = po.relpath; + node.isLast = lastNode; + + node.li = document.createElement("li"); + po.getChildrenUL().appendChild(node.li); + node.parentNode = po; + + node.itemDiv = document.createElement("div"); + node.itemDiv.className = "item"; + + node.labelSpan = document.createElement("span"); + node.labelSpan.className = "label"; + + createIndent(o,node.itemDiv,node,0); + node.itemDiv.appendChild(node.labelSpan); + node.li.appendChild(node.itemDiv); + + var a = document.createElement("a"); + node.labelSpan.appendChild(a); + node.label = document.createTextNode(text); + a.appendChild(node.label); + if (link) + { + a.href = node.relpath+link; + } + else + { + if (childrenData != null) + { + a.className = "nolink"; + a.href = "javascript:void(0)"; + a.onclick = node.expandToggle.onclick; + node.expanded = false; + } + } + + node.childrenUL = null; + node.getChildrenUL = function() + { + if (!node.childrenUL) + { + node.childrenUL = document.createElement("ul"); + node.childrenUL.className = "children_ul"; + node.childrenUL.style.display = "none"; + node.li.appendChild(node.childrenUL); + } + return node.childrenUL; + }; + + return node; +} + +function showRoot() +{ + var headerHeight = $("#top").height(); + var footerHeight = $("#nav-path").height(); + var windowHeight = $(window).height() - headerHeight - footerHeight; + navtree.scrollTo('#selected',0,{offset:-windowHeight/2}); +} + +function expandNode(o, node, imm) +{ + if (node.childrenData && !node.expanded) + { + if (!node.childrenVisited) + { + getNode(o, node); + } + if (imm) + { + $(node.getChildrenUL()).show(); + } + else + { + $(node.getChildrenUL()).slideDown("fast",showRoot); + } + if (node.isLast) + { + node.plus_img.src = node.relpath+"ftv2mlastnode.png"; + } + else + { + node.plus_img.src = node.relpath+"ftv2mnode.png"; + } + node.expanded = true; + } +} + +function getNode(o, po) +{ + po.childrenVisited = true; + var l = po.childrenData.length-1; + for (var i in po.childrenData) + { + var nodeData = po.childrenData[i]; + po.children[i] = newNode(o, po, nodeData[0], nodeData[1], nodeData[2], + i==l); + } +} + +function findNavTreePage(url, data) +{ + var nodes = data; + var result = null; + for (var i in nodes) + { + var d = nodes[i]; + if (d[1] == url) + { + return new Array(i); + } + else if (d[2] != null) // array of children + { + result = findNavTreePage(url, d[2]); + if (result != null) + { + return (new Array(i).concat(result)); + } + } + } + return null; +} + +function initNavTree(toroot,relpath) +{ + var o = new Object(); + o.toroot = toroot; + o.node = new Object(); + o.node.li = document.getElementById("nav-tree-contents"); + o.node.childrenData = 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    + +
    + + + + + + + + + + + +
    +
    CMSIS-RTOS +  Version 1.00 +
    +
    CMSIS-RTOS API: Generic RTOS interface for Cortex-M processor-based devices.
    +
    +
    + +
    + +
    + + + +
    +
    + +
    +
    +
    + +
    +
    +
    +
    Function Overview
    +
    +
    +

    The following list provides a brief overview of all CMSIS-RTOS functions. Functions marked with $ are optional. A CMSIS RTOS implementation may not provided functions, but this is clearly indicated with osFeatureXXXX defines.

    + + + + + + + + + + +
    +
    + + + + + diff --git a/Libraries/CMSIS/Documentation/RTOS/html/_using_o_s.html b/Libraries/CMSIS/Documentation/RTOS/html/_using_o_s.html new file mode 100644 index 0000000..89bffb7 --- /dev/null +++ b/Libraries/CMSIS/Documentation/RTOS/html/_using_o_s.html @@ -0,0 +1,164 @@ + + + + +Using a CMSIS RTOS Implementation + + + + + + + + + + + + + +
    + +
    + + + + + + + + + + + +
    +
    CMSIS-RTOS +  Version 1.00 +
    +
    CMSIS-RTOS API: Generic RTOS interface for Cortex-M processor-based devices.
    +
    +
    + +
    + +
    + + + +
    +
    + +
    +
    +
    + +
    +
    +
    +
    Using a CMSIS RTOS Implementation
    +
    +
    +

    A CMSIS RTOS implementation is typically provided as a library. To add the RTOS functionality to an existing CMSIS-based application the RTOS library (and typically a configuration file) needs to be added. The available functionality of the RTOS library is defined in the file cmsis_os.h that is specific for each RTOS implementation.

    +
    +CMSIS_RTOS_Files.png +
    +CMSIS-RTOS File Structure
    +

    Depending on the CMSIS-RTOS implementation, execution may start with the main function as the first thread. This has the benefit that an application programmer may use other middleware libraries that create threads internally, but the remaining part of the user application just uses the main thread. Therefore, the usage of the RTOS can be invisible to the application programmer, but libraries can use CMSIS-RTOS features.

    +

    Once the files are added to a project, the user can start using the CMSIS-RTOS functions. A code example is provided below:

    +
    #include "cmsis_os.h"                           // CMSIS RTOS header file
+
+void job1 (void const *argument)  {             // thread function 'job1'
+  while (1)  {
+     :                                          // execute some code
+    osDelay (10);                               // delay execution for 10 milli seconds
+  }
+}
+// define job1 as thread function
+osThreadDef(job1, osPriorityAboveNormal, 1, 0); // define job1 as thread function
+
+
+void job2 (void const *argument)  {             // thread function 'job2'
+  osThreadCreate(osThread(job1),NULL);          // create job1 thread
+  while (1)   {
+    :                                           // execute some code
+  }
+}
+
+osThreadDef(job2, osPriorityNormal, 1, 0);      // define job2 as thread function
+
+
+int main (void) {                               // program execution starts here
+    :                                           // setup and initialize
+  osKernelStart (osThread(job2), NULL);         // start kernel with job2 execution
+  while (1);                                    // program will never reach this point
+}
+
    +
    + + + + + diff --git a/Libraries/CMSIS/Documentation/RTOS/html/annotated.html b/Libraries/CMSIS/Documentation/RTOS/html/annotated.html new file mode 100644 index 0000000..2c03c28 --- /dev/null +++ b/Libraries/CMSIS/Documentation/RTOS/html/annotated.html @@ -0,0 +1,148 @@ + + + + +Data Structures + + + + + + + + + + + + + +
    + +
    + + + + + + + + + + + +
    +
    CMSIS-RTOS +  Version 1.00 +
    +
    CMSIS-RTOS API: Generic RTOS interface for Cortex-M processor-based devices.
    +
    +
    + +
    + +
    + + + + +
    +
    + +
    +
    +
    + +
    +
    +
    +
    Data Structures
    +
    +
    +
    Here are the data structures with brief descriptions:
    + + + + + + + + + +
    os_mailQ
    osEventEvent structure contains detailed information about an event
    osMailQDef_tDefinition structure for mail queue
    osMessageQDef_tDefinition structure for message queue
    osMutexDef_tMutex Definition structure contains setup information for a mutex
    osPoolDef_tDefinition structure for memory block allocation
    osSemaphoreDef_tSemaphore Definition structure contains setup information for a semaphore
    osThreadDef_tThread Definition structure contains startup information of a thread
    osTimerDef_tTimer Definition structure contains timer parameters
    +
    +
    + + + + + diff --git a/Libraries/CMSIS/Documentation/RTOS/html/bc_s.png b/Libraries/CMSIS/Documentation/RTOS/html/bc_s.png new file mode 100644 index 0000000000000000000000000000000000000000..51ba0066debbeac813d4014d805dc95ebd5b532e GIT binary patch literal 705 zcmV;y0zUnTP)rF$rQRw6Q(&UpP1C2j9>6opbR!_oV&F*Ar#jFVPDcrqyulXW;j+8j#k`kzKrw^%mxu{{V1|%gWybaP{#p01Ow~ zB}u2{E{(}bUp!#{_s(CTu-lqpI0GO7kSiTS0H7s=EN*pJI7&&m$E!@mK+B_{Xx(nj zH0-yS_)(8nX^er(4+o=lHsk1YNuDJFz~=EOD_HN~zW*iu%I90GV!oc&bWQk_4geq* z?tP92Q)0;sZ>cqtNr zOitc-rw&Cz$YQa>g0&|*N&WS=YH&7966!J}!88AdX)_x%jMh)j1wW9Z z*IvhmrFxz{vu`%7PR#}L0f5_4b|fCOXQid+8KYfFC_DlHq_*W{G_-J(_zH3*04SWE z4=w=!x2-hRp+Pe7IRei{XXZoQv3aO*zlhc|&K$GAain(EABqhLSF-2uT86!Xj#Z0B zU3k_Xawp7W)%kt^=&@!R3-to)mi?gz3E*IJe>$ba=d_9I2l8b9axei@p6k1qW)^BJ zqHa=NSguR@Srtva-n?v)XN=T%7nVoVfN2cYfePZIbCZQi`9_mavc00000NkvXXu0mjfn{!2m literal 0 HcmV?d00001 diff --git a/Libraries/CMSIS/Documentation/RTOS/html/classes.html b/Libraries/CMSIS/Documentation/RTOS/html/classes.html new file mode 100644 index 0000000..f0636b3 --- /dev/null +++ b/Libraries/CMSIS/Documentation/RTOS/html/classes.html @@ -0,0 +1,146 @@ + + + + +Data Structure Index + + + + + + + + + + + + + +
    + +
    + + + + + + + + + + + +
    +
    CMSIS-RTOS +  Version 1.00 +
    +
    CMSIS-RTOS API: Generic RTOS interface for Cortex-M processor-based devices.
    +
    +
    + +
    + +
    + + + + +
    +
    + +
    +
    +
    + +
    +
    +
    +
    Data Structure Index
    +
    +
    +
    O
    + + + + + +
      O  
    +    		osEvent   osMutexDef_t   osThreadDef_t   
    osMailQDef_t   osPoolDef_t   osTimerDef_t   
    os_mailQ   osMessageQDef_t   osSemaphoreDef_t   
    +
    O
    +
    +
    + + + + + diff --git a/Libraries/CMSIS/Documentation/RTOS/html/closed.png b/Libraries/CMSIS/Documentation/RTOS/html/closed.png new file mode 100644 index 0000000000000000000000000000000000000000..b7d4bd9fef2272c74b94762c9e2496177017775e GIT binary patch literal 126 zcmeAS@N?(olHy`uVBq!ia0vp^oFL4>1|%O$WD@{VuAVNAAr*{o?>h22DDp4|bgj*t z)u^AqcA-V@guRYpb17F<&b?_~8HV>~XqWvB;^$!VVSTy0!eQcJp_yD7TIQA>7dijs YXf6~H5cs^Q6KEiVr>mdKI;Vst0NsWqGynhq literal 0 HcmV?d00001 diff --git a/Libraries/CMSIS/Documentation/RTOS/html/cmsis.css b/Libraries/CMSIS/Documentation/RTOS/html/cmsis.css new file mode 100644 index 0000000..a5c4b8d --- /dev/null +++ b/Libraries/CMSIS/Documentation/RTOS/html/cmsis.css @@ -0,0 +1,957 @@ +/* The standard CSS for doxygen */ + +body, table, div, p, dl { + font-family: Lucida Grande, Verdana, Geneva, Arial, sans-serif; + font-size: 12px; +} + +/* CMSIS styles */ + +.style1 { + text-align: center; +} +.style2 { + color: #0000FF; + font-weight: normal; +} +.style3 { + text-align: left; +} +.style4 { + color: #008000; +} +.style5 { + color: #0000FF; +} +.style6 { + color: #000000; + font-style:italic; +} +.mand { + color: #0000FF; +} +.opt { + color: #008000; +} +.cond { + color: #990000; +} + +.choice +{ + background-color:#F7F9D0; +} +.seq +{ + background-color:#C9DECB; +} +.group1 +{ + background-color:#F8F1F1; +} +.group2 +{ + background-color:#DCEDEA; +} + + +ul ul { + list-style-type: disc; +} + +ul ul ul { + list-style-type: disc; +} + +ul.hierarchy { + color: green; +} + +em { + color: #000000; + font-style:italic; +} + + + +/* CMSIS Tables */ +table.cmtab1 { + padding: 4px; + border-collapse: collapse; + border: 1px solid #A3B4D7; + text-align: justify; + width:70%; +} + +th.cmtab1 { + background: #EBEFF6; + font-weight: bold; + height: 28px; +} + +td.cmtab1 { + padding:1px; + text-align: left; +} + +table.cmtable { + border-collapse:collapse; + text-align: justify; +} + +table.cmtable td, table.cmtable th { + border: 1px solid #2D4068; + padding: 3px 7px 2px; +} + +table.cmtable th { + background-color: #EBEFF6; + border: 1px solid #2D4068; + font-size: 110%; + padding-bottom: 4px; + padding-top: 5px; + text-align:left; + height: 28px; +} + +td.MonoTxt { + font-family:"Arial monospaced for SAP"; +} + +span.XML-Token +{ + azimuth: 180; + font-style:italic; + color:Maroon; + z-index:20; + +} + +/* @group Heading Levels */ + +h1 { + font-size: 150%; +} + +.title { + font-size: 150%; + font-weight: bold; + margin: 10px 2px; +} + +h2 { + font-size: 120%; +} + +h3 { + font-size: 100%; +} + +dt { + font-weight: bold; +} + +div.multicol { + -moz-column-gap: 1em; + -webkit-column-gap: 1em; + -moz-column-count: 3; + -webkit-column-count: 3; +} + +p.startli, p.startdd, p.starttd { + margin-top: 2px; +} + +p.endli { + margin-bottom: 0px; +} + +p.enddd { + margin-bottom: 4px; +} + +p.endtd { + margin-bottom: 2px; +} + +/* @end */ + +caption { + font-weight: bold; +} + +span.legend { + font-size: 70%; + text-align: center; +} + +h3.version { + font-size: 90%; + text-align: center; +} + +div.qindex, div.navtab{ + background-color: #EBEFF6; + border: 1px solid #A3B4D7; + text-align: center; + margin: 2px; + padding: 2px; +} + +div.qindex, div.navpath { + width: 100%; + line-height: 140%; +} + +div.navtab { + margin-right: 15px; +} + +/* @group Link Styling */ + +a { + color: #3D578C; + font-weight: normal; + text-decoration: none; +} + +.contents a:visited { + color: #4665A2; +} + +a:hover { + text-decoration: underline; +} + +a.qindex { + font-weight: bold; +} + +a.qindexHL { + font-weight: bold; + background-color: #9CAFD4; + color: #ffffff; + border: 1px double #869DCA; +} + +.contents a.qindexHL:visited { + color: #ffffff; +} + +a.el { + font-weight: bold; +} + +a.elRef { +} + +a.code { + color: #4665A2; +} + +a.codeRef { + color: #4665A2; +} + +/* @end */ + +dl.el { + margin-left: -1cm; +} + +.fragment { + font-family: monospace, fixed; + font-size: 105%; +} + +pre.fragment { + border: 1px solid #C4CFE5; + background-color: #FBFCFD; + padding: 4px 6px; + margin: 4px 8px 4px 2px; + overflow: auto; + word-wrap: break-word; + font-size: 9pt; + line-height: 125%; +} + +div.ah { + background-color: black; + font-weight: bold; + color: #ffffff; + margin-bottom: 3px; + margin-top: 3px; + padding: 0.2em; + border: solid thin #333; + border-radius: 0.5em; + -webkit-border-radius: .5em; + -moz-border-radius: .5em; + box-shadow: 2px 2px 3px #999; + -webkit-box-shadow: 2px 2px 3px #999; + -moz-box-shadow: rgba(0, 0, 0, 0.15) 2px 2px 2px; + background-image: -webkit-gradient(linear, left top, left bottom, from(#eee), to(#000),color-stop(0.3, #444)); + background-image: -moz-linear-gradient(center top, #eee 0%, #444 40%, #000); +} + +div.groupHeader { + margin-left: 16px; + margin-top: 12px; + font-weight: bold; +} + +div.groupText { + margin-left: 16px; + font-style: italic; +} + +body { + background: white; + color: black; + margin: 0; +} + +div.contents { + margin-top: 10px; + margin-left: 10px; + margin-right: 5px; +} + +td.indexkey { + background-color: #EBEFF6; + font-weight: bold; + border: 1px solid #C4CFE5; + margin: 2px 0px 2px 0; + padding: 2px 10px; +} + +td.indexvalue { + background-color: #EBEFF6; + border: 1px solid #C4CFE5; + padding: 2px 10px; + margin: 2px 0px; +} + +tr.memlist { + background-color: #EEF1F7; +} + +p.formulaDsp { + text-align: center; +} + +img.formulaDsp { + +} + +img.formulaInl { + vertical-align: middle; +} + +div.center { + text-align: center; + margin-top: 0px; + margin-bottom: 0px; + padding: 0px; +} + +div.center img { + border: 0px; +} + +address.footer { + text-align: right; + padding-right: 12px; +} + +img.footer { + border: 0px; + vertical-align: middle; +} + +/* @group Code Colorization */ + +span.keyword { + color: #008000 +} + +span.keywordtype { + color: #604020 +} + +span.keywordflow { + color: #e08000 +} + +span.comment { + color: #800000 +} + +span.preprocessor { + color: #806020 +} + +span.stringliteral { + color: #002080 +} + +span.charliteral { + color: #008080 +} + +span.vhdldigit { + color: #ff00ff +} + +span.vhdlchar { + color: #000000 +} + +span.vhdlkeyword { + color: #700070 +} + +span.vhdllogic { + color: #ff0000 +} + +/* @end */ + +/* +.search { + color: #003399; + font-weight: bold; +} + +form.search { + margin-bottom: 0px; + margin-top: 0px; +} + +input.search { + font-size: 75%; + color: #000080; + font-weight: normal; + background-color: #e8eef2; +} +*/ + +td.tiny { + font-size: 75%; +} + +.dirtab { + padding: 4px; + border-collapse: collapse; + border: 1px solid #A3B4D7; +} + +th.dirtab { + background: #EBEFF6; + font-weight: bold; +} + +hr { + height: 0px; + border: none; + border-top: 1px solid #4A6AAA; +} + +hr.footer { + height: 1px; +} + +/* @group Member Descriptions */ + +table.memberdecls { + border-spacing: 0px; + padding: 0px; +} + +.mdescLeft, .mdescRight, +.memItemLeft, .memItemRight, +.memTemplItemLeft, .memTemplItemRight, .memTemplParams { + background-color: #F9FAFC; + border: none; + margin: 4px; + padding: 1px 0 0 8px; +} + +.mdescLeft, .mdescRight { + padding: 0px 8px 4px 8px; + color: #555; +} + +.memItemLeft, .memItemRight, .memTemplParams { + border-top: 1px solid #C4CFE5; +} + +.memItemLeft, .memTemplItemLeft { + white-space: nowrap; +} + +.memItemRight { + width: 100%; +} + +.memTemplParams { + color: #4665A2; + white-space: nowrap; +} + +/* @end */ + +/* @group Member Details */ + +/* Styles for detailed member documentation */ + +.memtemplate { + font-size: 80%; + color: #4665A2; + font-weight: normal; + margin-left: 9px; +} + +.memnav { + background-color: #EBEFF6; + border: 1px solid #A3B4D7; + text-align: center; + margin: 2px; + margin-right: 15px; + padding: 2px; +} + +.mempage { + width: 100%; +} + +.memitem { + padding: 0; + margin-bottom: 10px; + margin-right: 5px; +} + +.memname { + white-space: nowrap; + font-weight: bold; + margin-left: 6px; +} + +.memproto { + border-top: 1px solid #A8B8D9; + border-left: 1px solid #A8B8D9; + border-right: 1px solid #A8B8D9; + padding: 6px 0px 6px 0px; + color: #253555; + font-weight: bold; + text-shadow: 0px 1px 1px rgba(255, 255, 255, 0.9); + /* opera specific markup */ + box-shadow: 5px 5px 5px rgba(0, 0, 0, 0.15); + border-top-right-radius: 8px; + border-top-left-radius: 8px; + /* firefox specific markup */ + -moz-box-shadow: rgba(0, 0, 0, 0.15) 5px 5px 5px; + -moz-border-radius-topright: 8px; + -moz-border-radius-topleft: 8px; + /* webkit specific markup */ + -webkit-box-shadow: 5px 5px 5px rgba(0, 0, 0, 0.15); + -webkit-border-top-right-radius: 8px; + -webkit-border-top-left-radius: 8px; + background-image:url('nav_f.png'); + background-repeat:repeat-x; + background-color: #E2E8F2; + +} + +.memdoc { + border-bottom: 1px solid #A8B8D9; + border-left: 1px solid #A8B8D9; + border-right: 1px solid #A8B8D9; + padding: 2px 5px; + background-color: #FBFCFD; + border-top-width: 0; + /* opera specific markup */ + border-bottom-left-radius: 8px; + border-bottom-right-radius: 8px; + box-shadow: 5px 5px 5px rgba(0, 0, 0, 0.15); + /* firefox specific markup */ + -moz-border-radius-bottomleft: 8px; + -moz-border-radius-bottomright: 8px; + -moz-box-shadow: rgba(0, 0, 0, 0.15) 5px 5px 5px; + background-image: -moz-linear-gradient(center top, #FFFFFF 0%, #FFFFFF 60%, #F7F8FB 95%, #EEF1F7); + /* webkit specific markup */ + -webkit-border-bottom-left-radius: 8px; + -webkit-border-bottom-right-radius: 8px; + -webkit-box-shadow: 5px 5px 5px rgba(0, 0, 0, 0.15); + background-image: -webkit-gradient(linear,center top,center bottom,from(#FFFFFF), color-stop(0.6,#FFFFFF), color-stop(0.60,#FFFFFF), color-stop(0.95,#F7F8FB), to(#EEF1F7)); +} + +.paramkey { + text-align: right; +} + +.paramtype { + white-space: nowrap; +} + +.paramname { + color: #602020; + white-space: nowrap; +} +.paramname em { + font-style: normal; +} + +.params, .retval, .exception, .tparams { + border-spacing: 6px 2px; +} + +.params .paramname, .retval .paramname { + font-weight: bold; + vertical-align: top; +} + +.params .paramtype { + font-style: italic; + vertical-align: top; +} + +.params .paramdir { + font-family: "courier new",courier,monospace; + vertical-align: top; +} + + + + +/* @end */ + +/* @group Directory (tree) */ + +/* for the tree view */ + +.ftvtree { + font-family: sans-serif; + margin: 0px; +} + +/* these are for tree view when used as main index */ + +.directory { + font-size: 9pt; + font-weight: bold; + margin: 5px; +} + +.directory h3 { + margin: 0px; + margin-top: 1em; + font-size: 11pt; +} + +/* +The following two styles can be used to replace the root node title +with an image of your choice. Simply uncomment the next two styles, +specify the name of your image and be sure to set 'height' to the +proper pixel height of your image. +*/ + +/* +.directory h3.swap { + height: 61px; + background-repeat: no-repeat; + background-image: url("yourimage.gif"); +} +.directory h3.swap span { + display: none; +} +*/ + +.directory > h3 { + margin-top: 0; +} + +.directory p { + margin: 0px; + white-space: nowrap; +} + +.directory div { + display: none; + margin: 0px; +} + +.directory img { + vertical-align: -30%; +} + +/* these are for tree view when not used as main index */ + +.directory-alt { + font-size: 100%; + font-weight: bold; +} + +.directory-alt h3 { + margin: 0px; + margin-top: 1em; + font-size: 11pt; +} + +.directory-alt > h3 { + margin-top: 0; +} + +.directory-alt p { + margin: 0px; + white-space: nowrap; +} + +.directory-alt div { + display: none; + margin: 0px; +} + +.directory-alt img { + vertical-align: -30%; +} + +/* @end */ + +div.dynheader { + margin-top: 8px; +} + +address { + font-style: normal; + color: #2A3D61; +} + +table.doxtable { + border-collapse:collapse; +} + +table.doxtable td, table.doxtable th { + border: 1px solid #2D4068; + padding: 3px 7px 2px; +} + +table.doxtable th { + background-color: #374F7F; + color: #FFFFFF; + font-size: 110%; + padding-bottom: 4px; + padding-top: 5px; + text-align:left; +} + +.tabsearch { + top: 0px; + left: 10px; + height: 36px; + background-image: url('tab_b.png'); + z-index: 101; + overflow: hidden; + font-size: 13px; +} + +.navpath ul +{ + font-size: 11px; + background-image:url('tab_b.png'); + background-repeat:repeat-x; + height:30px; + line-height:30px; + color:#8AA0CC; + border:solid 1px #C2CDE4; + overflow:hidden; + margin:0px; + padding:0px; +} + +.navpath li +{ + list-style-type:none; + float:left; + padding-left:10px; + padding-right:15px; + background-image:url('bc_s.png'); + background-repeat:no-repeat; + background-position:right; + color:#364D7C; +} + +.navpath li.navelem a +{ + height:32px; + display:block; + text-decoration: none; + outline: none; +} + +.navpath li.navelem a:hover +{ + color:#6884BD; +} + +.navpath li.footer +{ + list-style-type:none; + float:right; + padding-left:10px; + padding-right:15px; + background-image:none; + background-repeat:no-repeat; + background-position:right; + color:#364D7C; + font-size: 8pt; +} + + +div.summary +{ + float: right; + font-size: 8pt; + padding-right: 5px; + width: 50%; + text-align: right; +} + +div.summary a +{ + white-space: nowrap; +} + +div.ingroups +{ + font-size: 8pt; + padding-left: 5px; + width: 50%; + text-align: left; +} + +div.ingroups a +{ + white-space: nowrap; +} + +div.header +{ + background-image:url('nav_h.png'); + background-repeat:repeat-x; + background-color: #F9FAFC; + margin: 0px; + border-bottom: 1px solid #C4CFE5; +} + +div.headertitle +{ + padding: 5px 5px 5px 10px; +} + +dl +{ + padding: 0 0 0 10px; +} + +dl.note, dl.warning, dl.attention, dl.pre, dl.post, dl.invariant, dl.deprecated, dl.todo, dl.test, dl.bug +{ + border-left:4px solid; + padding: 0 0 0 6px; +} + +dl.note +{ + border-color: #D0C000; +} + +dl.warning, dl.attention +{ + border-color: #FF0000; +} + +dl.pre, dl.post, dl.invariant +{ + border-color: #00D000; +} + +dl.deprecated +{ + border-color: #505050; +} + +dl.todo +{ + border-color: #00C0E0; +} + +dl.test +{ + border-color: #3030E0; +} + +dl.bug +{ + border-color: #C08050; +} + +#projectlogo +{ + text-align: center; + vertical-align: bottom; + border-collapse: separate; +} + +#projectlogo img +{ + border: 0px none; +} + +#projectname +{ + font: 200% Tahoma, Arial,sans-serif; + margin: 0px; + padding: 2px 0px; +} + +#projectbrief +{ + font: 120% Tahoma, Arial,sans-serif; + margin: 0px; + padding: 0px; +} + +#projectnumber +{ + font: 50% Tahoma, Arial,sans-serif; + margin: 0px; + padding: 0px; +} + +#titlearea +{ + padding: 0px; + margin: 0px; + width: 100%; + border-bottom: 1px solid #5373B4; +} + +.image +{ + text-align: center; +} + +.dotgraph +{ + text-align: center; +} + +.mscgraph +{ + text-align: center; +} + +.caption +{ + font-weight: bold; +} + diff --git a/Libraries/CMSIS/Documentation/RTOS/html/cmsis__os_8h.html b/Libraries/CMSIS/Documentation/RTOS/html/cmsis__os_8h.html new file mode 100644 index 0000000..57998d6 --- /dev/null +++ b/Libraries/CMSIS/Documentation/RTOS/html/cmsis__os_8h.html @@ -0,0 +1,636 @@ + + + + +cmsis_os.h File Reference + + + + + + + + + + + + + +
    + +
    + + + + + + + + + + + +
    +
    CMSIS-RTOS +  Version 1.00 +
    +
    CMSIS-RTOS API: Generic RTOS interface for Cortex-M processor-based devices.
    +
    +
    + +
    + +
    + + + +
    +
    + +
    +
    +
    + +
    +
    +
    +Data Structures | +Defines | +Typedefs | +Enumerations | +Functions
    +
    +
    cmsis_os.h File Reference
    +
    +
    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +

    +Data Structures

    struct  osThreadDef_t
     Thread Definition structure contains startup information of a thread. More...
    struct  osTimerDef_t
     Timer Definition structure contains timer parameters. More...
    struct  osMutexDef_t
     Mutex Definition structure contains setup information for a mutex. More...
    struct  osSemaphoreDef_t
     Semaphore Definition structure contains setup information for a semaphore. More...
    struct  osPoolDef_t
     Definition structure for memory block allocation. More...
    struct  osMessageQDef_t
     Definition structure for message queue. More...
    struct  osMailQDef_t
     Definition structure for mail queue. More...
    struct  osEvent
     Event structure contains detailed information about an event. More...

    +Defines

    #define osCMSIS   0x00003
     API version (main [31:16] .sub [15:0])
    #define osCMSIS_KERNEL   0x10000
     RTOS identification and version (main [31:16] .sub [15:0])
    #define osKernelSystemId   "KERNEL V1.00"
     RTOS identification string.
    #define osFeature_MainThread   1
     main thread 1=main can be thread, 0=not available
    #define osFeature_Pool   1
     Memory Pools: 1=available, 0=not available.
    #define osFeature_MailQ   1
     Mail Queues: 1=available, 0=not available.
    #define osFeature_MessageQ   1
     Message Queues: 1=available, 0=not available.
    #define osFeature_Signals   8
     maximum number of Signal Flags available per thread
    #define osFeature_Semaphore   30
     maximum count for SemaphoreInit function
    #define osFeature_Wait   1
     osWait function: 1=available, 0=not available
    #define osWaitForever   0xFFFFFFFF
     Timeout value.
    #define osThreadDef(name, priority, instances, stacksz)
     Create a Thread Definition with function, priority, and stack requirements.
    #define osThread(name)   &os_thread_def_##name
     Access a Thread defintion.
    #define osTimerDef(name, function)
     Define a Timer object.
    #define osTimer(name)   &os_timer_def_##name
     Access a Timer definition.
    #define osMutexDef(name)   osMutexDef_t os_mutex_def_##name = { 0 }
     Define a Mutex.
    #define osMutex(name)   &os_mutex_def_##name
     Access a Mutex defintion.
    #define osSemaphoreDef(name)   osSemaphoreDef_t os_semaphore_def_##name = { 0 }
     Define a Semaphore object.
    #define osSemaphore(name)   &os_semaphore_def_##name
     Access a Semaphore definition.
    #define osPoolDef(name, no, type)
     Define a Memory Pool.
    #define osPool(name)   &os_pool_def_##name
     Access a Memory Pool definition.
    #define osMessageQDef(name, queue_sz, type)
     Create a Message Queue Definition.
    #define osMessageQ(name)   &os_messageQ_def_##name
     Access a Message Queue Definition.
    #define osMailQDef(name, queue_sz, type)
     Create a Mail Queue Definition.
    #define osMailQ(name)   &os_mailQ_def_##name
     Access a Mail Queue Definition.

    +Typedefs

    typedef void(* os_pthread )(void const *argument)
     Entry point of a thread.
    typedef void(* os_ptimer )(void const *argument)
     Entry point of a timer call back function.
    typedef struct os_thread_cb * osThreadId
     Thread ID identifies the thread (pointer to a thread control block).
    typedef struct os_timer_cb * osTimerId
     Timer ID identifies the timer (pointer to a timer control block).
    typedef struct os_mutex_cb * osMutexId
     Mutex ID identifies the mutex (pointer to a mutex control block).
    typedef struct os_semaphore_cb * osSemaphoreId
     Semaphore ID identifies the semaphore (pointer to a semaphore control block).
    typedef struct os_pool_cb * osPoolId
     Pool ID identifies the memory pool (pointer to a memory pool control block).
    typedef struct os_messageQ_cb * osMessageQId
     Message ID identifies the message queue (pointer to a message queue control block).
    typedef struct os_mailQ_cb * osMailQId
     Mail ID identifies the mail queue (pointer to a mail queue control block).

    +Enumerations

    enum  osPriority {
    +  osPriorityIdle = -3, +
    +  osPriorityLow = -2, +
    +  osPriorityBelowNormal = -1, +
    +  osPriorityNormal = 0, +
    +  osPriorityAboveNormal = +1, +
    +  osPriorityHigh = +2, +
    +  osPriorityRealtime = +3, +
    +  osPriorityError = 0x84 +
    + }
     Priority used for thread control. More...
    enum  osStatus {
    +  osOK = 0, +
    +  osEventSignal = 0x08, +
    +  osEventMessage = 0x10, +
    +  osEventMail = 0x20, +
    +  osEventTimeout = 0x40, +
    +  osErrorParameter = 0x80, +
    +  osErrorResource = 0x81, +
    +  osErrorTimeoutResource = 0xC1, +
    +  osErrorISR = 0x82, +
    +  osErrorISRRecursive = 0x83, +
    +  osErrorPriority = 0x84, +
    +  osErrorNoMemory = 0x85, +
    +  osErrorValue = 0x86, +
    +  osErrorOS = 0xFF, +
    +  os_status_reserved = 0x7FFFFFFF +
    + }
     Status code values returned by CMSIS-RTOS functions. More...
    enum  os_timer_type {
    +  osTimerOnce = 0, +
    +  osTimerPeriodic = 1 +
    + }
     Timer type value for the timer definition. More...

    +Functions

    osStatus osKernelStart (osThreadDef_t *thread_def, void *argument)
     Start the RTOS Kernel with executing the specified thread.
    int32_t osKernelRunning (void)
     Check if the RTOS kernel is already started.
    osThreadId osThreadCreate (osThreadDef_t *thread_def, void *argument)
     Create a thread and add it to Active Threads and set it to state READY.
    osThreadId osThreadGetId (void)
     Return the thread ID of the current running thread.
    osStatus osThreadTerminate (osThreadId thread_id)
     Terminate execution of a thread and remove it from Active Threads.
    osStatus osThreadYield (void)
     Pass control to next thread that is in state READY.
    osStatus osThreadSetPriority (osThreadId thread_id, osPriority priority)
     Change priority of an active thread.
    osPriority osThreadGetPriority (osThreadId thread_id)
     Get current priority of an active thread.
    osStatus osDelay (uint32_t millisec)
     Wait for Timeout (Time Delay)
    osEvent osWait (uint32_t millisec)
     Wait for Signal, Message, Mail, or Timeout.
    osTimerId osTimerCreate (osTimerDef_t *timer_def, os_timer_type type, void *argument)
     Create a timer.
    osStatus osTimerStart (osTimerId timer_id, uint32_t millisec)
     Start or restart a timer.
    osStatus osTimerStop (osTimerId timer_id)
     Stop the timer.
    int32_t osSignalSet (osThreadId thread_id, int32_t signal)
     Set the specified Signal Flags of an active thread.
    int32_t osSignalClear (osThreadId thread_id, int32_t signal)
     Clear the specified Signal Flags of an active thread.
    int32_t osSignalGet (osThreadId thread_id)
     Get Signal Flags status of an active thread.
    osEvent osSignalWait (int32_t signals, uint32_t millisec)
     Wait for one or more Signal Flags to become signaled for the current RUNNING thread.
    osMutexId osMutexCreate (osMutexDef_t *mutex_def)
     Create and Initialize a Mutex object.
    osStatus osMutexWait (osMutexId mutex_id, uint32_t millisec)
     Wait until a Mutex becomes available.
    osStatus osMutexRelease (osMutexId mutex_id)
     Release a Mutex that was obtained by osMutexWait.
    osSemaphoreId osSemaphoreCreate (osSemaphoreDef_t *semaphore_def, int32_t count)
     Create and Initialize a Semaphore object used for managing resources.
    int32_t osSemaphoreWait (osSemaphoreId semaphore_id, uint32_t millisec)
     Wait until a Semaphore token becomes available.
    osStatus osSemaphoreRelease (osSemaphoreId semaphore_id)
     Release a Semaphore token.
    osPoolId osPoolCreate (osPoolDef_t *pool_def)
     Create and Initialize a memory pool.
    void * osPoolAlloc (osPoolId pool_id)
     Allocate a memory block from a memory pool.
    void * osPoolCAlloc (osPoolId pool_id)
     Allocate a memory block from a memory pool and set memory block to zero.
    osStatus osPoolFree (osPoolId pool_id, void *block)
     Return an allocated memory block back to a specific memory pool.
    osMessageQId osMessageCreate (osMessageQDef_t *queue_def, osThreadId thread_id)
     Create and Initialize a Message Queue.
    osStatus osMessagePut (osMessageQId queue_id, uint32_t info, uint32_t millisec)
     Put a Message to a Queue.
    osEvent osMessageGet (osMessageQId queue_id, uint32_t millisec)
     Get a Message or Wait for a Message from a Queue.
    osMailQId osMailCreate (osMailQDef_t *queue_def, osThreadId thread_id)
     Create and Initialize mail queue.
    void * osMailAlloc (osMailQId queue_id, uint32_t millisec)
     Allocate a memory block from a mail.
    void * osMailCAlloc (osMailQId queue_id, uint32_t millisec)
     Allocate a memory block from a mail and set memory block to zero.
    osStatus osMailPut (osMailQId queue_id, void *mail)
     Put a mail to a queue.
    osEvent osMailGet (osMailQId queue_id, uint32_t millisec)
     Get a mail from a queue.
    osStatus osMailFree (osMailQId queue_id, void *mail)
     Free a memory block from a mail.
    +

    Define Documentation

    + +
    +
    + + + + +
    #define osWaitForever   0xFFFFFFFF
    +
    +
    +
    Note:
    MUST REMAIN UNCHANGED: osWaitForever shall be consistent in every CMSIS-RTOS. wait forever timeout value
    + +
    +
    +

    Typedef Documentation

    + +
    +
    + + + + +
    typedef void(* os_pthread)(void const *argument)
    +
    +
    +
    Note:
    MUST REMAIN UNCHANGED: os_pthread shall be consistent in every CMSIS-RTOS.
    + +
    +
    + +
    +
    + + + + +
    typedef void(* os_ptimer)(void const *argument)
    +
    +
    +
    Note:
    MUST REMAIN UNCHANGED: os_ptimer shall be consistent in every CMSIS-RTOS.
    + +
    +
    + +
    +
    + + + + +
    typedef struct os_mailQ_cb* osMailQId
    +
    +
    +
    Note:
    CAN BE CHANGED: os_mailQ_cb is implementation specific in every CMSIS-RTOS.
    + +
    +
    + +
    +
    + + + + +
    typedef struct os_messageQ_cb* osMessageQId
    +
    +
    +
    Note:
    CAN BE CHANGED: os_messageQ_cb is implementation specific in every CMSIS-RTOS.
    + +
    +
    + +
    +
    + + + + +
    typedef struct os_mutex_cb* osMutexId
    +
    +
    +
    Note:
    CAN BE CHANGED: os_mutex_cb is implementation specific in every CMSIS-RTOS.
    + +
    +
    + +
    +
    + + + + +
    typedef struct os_pool_cb* osPoolId
    +
    +
    +
    Note:
    CAN BE CHANGED: os_pool_cb is implementation specific in every CMSIS-RTOS.
    + +
    +
    + +
    +
    + + + + +
    typedef struct os_semaphore_cb* osSemaphoreId
    +
    +
    +
    Note:
    CAN BE CHANGED: os_semaphore_cb is implementation specific in every CMSIS-RTOS.
    + +
    +
    + +
    +
    + + + + +
    typedef struct os_thread_cb* osThreadId
    +
    +
    +
    Note:
    CAN BE CHANGED: os_thread_cb is implementation specific in every CMSIS-RTOS.
    + +
    +
    + +
    +
    + + + + +
    typedef struct os_timer_cb* osTimerId
    +
    +
    +
    Note:
    CAN BE CHANGED: os_timer_cb is implementation specific in every CMSIS-RTOS.
    + +
    +
    +

    Enumeration Type Documentation

    + +
    +
    + + + + +
    enum os_timer_type
    +
    +
    +
    Note:
    MUST REMAIN UNCHANGED: os_timer_type shall be consistent in every CMSIS-RTOS.
    +
    Enumerator:
    + + +
    osTimerOnce  +

    one-shot timer

    +
    osTimerPeriodic  +

    repeating timer

    +
    +
    +
    + +
    +
    + +
    +
    + + + + +
    enum osPriority
    +
    +
    +
    Note:
    MUST REMAIN UNCHANGED: osPriority shall be consistent in every CMSIS-RTOS.
    +
    Enumerator:
    + + + + + + + + +
    osPriorityIdle  +

    priority: idle (lowest)

    +
    osPriorityLow  +

    priority: low

    +
    osPriorityBelowNormal  +

    priority: below normal

    +
    osPriorityNormal  +

    priority: normal (default)

    +
    osPriorityAboveNormal  +

    priority: above normal

    +
    osPriorityHigh  +

    priority: high

    +
    osPriorityRealtime  +

    priority: realtime (highest)

    +
    osPriorityError  +

    system cannot determine priority or thread has illegal priority

    +
    +
    +
    + +
    +
    + +
    +
    + + + + +
    enum osStatus
    +
    +
    +
    Note:
    MUST REMAIN UNCHANGED: osStatus shall be consistent in every CMSIS-RTOS.
    +
    Enumerator:
    + + + + + + + + + + + + + + + +
    osOK  +

    function completed; no event occurred.

    +
    osEventSignal  +

    function completed; signal event occurred.

    +
    osEventMessage  +

    function completed; message event occurred.

    +
    osEventMail  +

    function completed; mail event occurred.

    +
    osEventTimeout  +

    function completed; timeout occurred.

    +
    osErrorParameter  +

    parameter error: a mandatory parameter was missing or specified an incorrect object.

    +
    osErrorResource  +

    resource not available: a specified resource was not available.

    +
    osErrorTimeoutResource  +

    resource not available within given time: a specified resource was not available within the timeout period.

    +
    osErrorISR  +

    not allowed in ISR context: the function cannot be called from interrupt service routines.

    +
    osErrorISRRecursive  +

    function called multiple times from ISR with same object.

    +
    osErrorPriority  +

    system cannot determine priority or thread has illegal priority.

    +
    osErrorNoMemory  +

    system is out of memory: it was impossible to allocate or reserve memory for the operation.

    +
    osErrorValue  +

    value of a parameter is out of range.

    +
    osErrorOS  +

    unspecified RTOS error: run-time error but no other error message fits.

    +
    os_status_reserved  +

    prevent from enum down-size compiler optimization.

    +
    +
    +
    + +
    +
    +
    +
    + + + + + diff --git a/Libraries/CMSIS/Documentation/RTOS/html/cmsis__os_8txt.html b/Libraries/CMSIS/Documentation/RTOS/html/cmsis__os_8txt.html new file mode 100644 index 0000000..7dceb42 --- /dev/null +++ b/Libraries/CMSIS/Documentation/RTOS/html/cmsis__os_8txt.html @@ -0,0 +1,193 @@ + + + + +cmsis_os.txt File Reference + + + + + + + + + + + + + +
    + +
    + + + + + + + + + + + +
    +
    CMSIS-RTOS +  Version 1.00 +
    +
    CMSIS-RTOS API: Generic RTOS interface for Cortex-M processor-based devices.
    +
    +
    + +
    + +
    + + + +
    +
    + +
    +
    +
    + +
    +
    +
    +Enumerations
    +
    +
    cmsis_os.txt File Reference
    +
    +
    + + + + + +

    +Enumerations

    enum  osPriority {
    +  osPriorityIdle = -3, +
    +  osPriorityLow = -2, +
    +  osPriorityBelowNormal = -1, +
    +  osPriorityNormal = 0, +
    +  osPriorityAboveNormal = +1, +
    +  osPriorityHigh = +2, +
    +  osPriorityRealtime = +3, +
    +  osPriorityError = 0x84 +
    + }
    enum  os_timer_type {
    +  osTimerOnce = 0, +
    +  osTimerPeriodic = 1 +
    + }
    enum  osStatus {
    +  osOK = 0, +
    +  osEventSignal = 0x08, +
    +  osEventMessage = 0x10, +
    +  osEventMail = 0x20, +
    +  osEventTimeout = 0x40, +
    +  osErrorParameter = 0x80, +
    +  osErrorResource = 0x81, +
    +  osErrorTimeoutResource = 0xC1, +
    +  osErrorISR = 0x82, +
    +  osErrorISRRecursive = 0x83, +
    +  osErrorPriority = 0x84, +
    +  osErrorNoMemory = 0x85, +
    +  osErrorValue = 0x86, +
    +  osErrorOS = 0xFF, +
    +  os_status_reserved = 0x7FFFFFFF +
    + }
    +
    +
    + + + + + diff --git a/Libraries/CMSIS/Documentation/RTOS/html/cmsis_os_h.html b/Libraries/CMSIS/Documentation/RTOS/html/cmsis_os_h.html new file mode 100644 index 0000000..05bb698 --- /dev/null +++ b/Libraries/CMSIS/Documentation/RTOS/html/cmsis_os_h.html @@ -0,0 +1,169 @@ + + + + +Header File Template: cmsis_os.h + + + + + + + + + + + + + +
    + +
    + + + + + + + + + + + +
    +
    CMSIS-RTOS +  Version 1.00 +
    +
    CMSIS-RTOS API: Generic RTOS interface for Cortex-M processor-based devices.
    +
    +
    + +
    + +
    + + + +
    +
    + +
    +
    +
    + +
    +
    +
    +
    Header File Template: cmsis_os.h
    +
    +
    +

    The file cmsis_os.h is a template header file for a CMSIS-RTOS compliant Real-Time Operating System (RTOS). Each RTOS that is compliant with CMSIS-RTOS shall provide a specific cmsis_os.h header file that represents its implementation.

    +

    The file cmsis_os.h contains:

    +
      +
    • CMSIS-RTOS API function definitions
      • +
    • struct definitions for parameters and return types
      • +
    • status and priority values used by CMSIS-RTOS API functions
      • +
    • macros for defining threads and other kernel objects
      • +
    +

    Name conventions and header file modifications

    +

    All definitions are prefixed with os to give an unique name space for CMSIS-RTOS functions. Definitions that are prefixed os_ are not used in the application code but local to this header file. All definitions and functions that belong to a module are grouped and have a common prefix, i.e. osThread.

    +

    Definitions that are marked with CAN BE CHANGED can be adapted towards the needs of the actual CMSIS-RTOS implementation. These definitions can be specific to the underlying RTOS kernel.

    +

    Definitions that are marked with MUST REMAIN UNCHANGED cannot be altered. Otherwise the CMSIS-RTOS implementation is no longer compliant to the standard. Note that some functions are optional and need not to be provided by every CMSIS-RTOS implementation.

    +

    Function calls from interrupt service routines

    +

    The following CMSIS-RTOS functions can be called from threads and interrupt service routines (ISR):

    + +

    Functions that cannot be called from an ISR are verifying the interrupt status and return in case that they are called from an ISR context the status code osErrorISR. In some implementations this condition might be caught using the HARD FAULT vector.

    +

    Some CMSIS-RTOS implementations support CMSIS-RTOS function calls from multiple ISR at the same time. If this is impossible, the CMSIS-RTOS rejects calls by nested ISR functions with the status code osErrorISRRecursive.

    +

    Define and reference object definitions

    +

    With #define osObjectsExternal objects are defined as external symbols. This allows to create a consistent header file that is used troughtout a project as shown below:

    +

    Header File

    +
    #include <cmsis_os.h>                                         // CMSIS RTOS header file
+
+// Thread definition
+extern void thread_sample (void const *argument);             // function prototype
+osThreadDef (thread_sample, osPriorityBelowNormal, 1, 100);
+
+// Pool definition
+osPoolDef(MyPool, 10, long);                      
+

    This header file defines all objects when included in a C/C++ source file. When #define osObjectsExternal is present before the header file, the objects are defined as external symbols. A single consistent header file can therefore be used throughout the whole project.

    +

    Example

    +
    #include "osObjects.h"     // Definition of the CMSIS-RTOS objects
+
    #define osObjectExternal   // Objects will be defined as external symbols
+#include "osObjects.h"     // Reference to the CMSIS-RTOS objects
+
    +
    + + + + + diff --git a/Libraries/CMSIS/Documentation/RTOS/html/doxygen.png b/Libraries/CMSIS/Documentation/RTOS/html/doxygen.png new file mode 100644 index 0000000000000000000000000000000000000000..635ed52fce7057ac24df92ec7664088a881fa5d0 GIT binary patch literal 3942 zcmV-s51H_ZP)95ENDh(OT9xpYZC{M(=rqI* z+1erNEr&9zRjUI-4rN=4BBz>P@ys*xOjGRjzVE*Fx_qvyt9d@B@BO*&@8Mq!nM{Tc z_WoM84-~xLreSL9@vgZ{m2dF}`u=^ZF3syQ-s2tnBwCI3ZFvSfI20Wbj236~Urq*8Kfw@RKKfRQTgE>}uUHK^ptamY=o)LU(xy55zNQ(`qZ znZ&$O075mrrInIXQgw4%GCbMD8Vn`3n3$EaRwtP1D{A!Gs=e!L%3;ayv@I{rAw{xw z^x^>EIWQM8ob3m}$(BaupDMV;Ed8w5|i(*e`7rU$TOc&1o7`|!LyN5jHI z7uWAR!v4c2xMp?}QmRYyf>i}tYGU(g=>DW&==J@GbhR z5@BNVY3O$`^D%gk4khm9XpFhuwzxUhi9T=Du4rpVuYRSMPHeDqo+4htnZRU@G9`0& z9~p)CsFl1|t*wjfoTo&%davN^3RfJUhQ{ZZIAcD77X^XsF_iR&ZMQ;p>K5*+*48)x z+=<>nh+6Uq85jOkg>{z>a;+V`s(I;I%*5s+R@9a^wNoZ03(g9-EcH%uHvX&yp7`D#`9Kw>DU3s zjD-VuW_A-K)unlS4O3f>_B%pPONUmI#oyL};Lglp3=04>0eBBEw$D1k-$WTsoi#K* z$7h`NcyRZsZ#w~6I<%~u!^xDofYrzF>zVIj2N>Ijs`mVR(Oy&*9f}<{JtQj8jJT!oEc!NQXBq5y|6ET*N?7ox*E6#{i- z@_DLD^IYTtg|Pg?A~!7@OCd8p^)kxK%VBM84docx$Z{MvO)iiqep@or-N}TEU8$%; zJih?#yJ9)V1s_`}c3XbY9V}nEKwNz8ILmR|v)(w|D@oVG;=i`+$*)!(xH{9#$2Za;pyZ1wgU#)mHl|&8%iwu%yncO z`T32Ib0$D}j`c}}5M@M#7oR&G=QwU!!Ja*P7|NJt1@lo=d{_dY-q_lmDcH7{BHncF zR@^PmcLC6EsN?6N{fV3o8}>?h9X_@;=&-p7%tms7$_{3w(anwek_k&<&)~c$Ar?S> zy9gKavndTmxqAbE?SMgcWhXPENdKdz7ntt55Y3Hs3jjc~uR-#$tR(1a_abv9`-QzG z^J0Fsbd&yruq%xAsxf3rc=T}$Zx|AD%x{Fd=? z{qhl3kG5w-PqVK9-Gru%7UIEw)bt$ZMF|Z6HpmO)F%@GNT8yT|#FuWPxv@@Ic={;6 zU7)e!XG|1dx=kU|&|)+m+$&|Yw92Fa;*MnegXcCf8XsHfqg_F5t)3Jt8)EkXKuY21 zqt%4}@R8hK*(_JO0*H+Pa)6Pp&K49rKNeQEYb*x9WY`!`Vh3|80YF%I`lxv9_!$hD zOh$>zWaRIW!);6`vA$Zp;5lnGyX^^N%YEjCeJMHPolKCE1ttIqK<$0w&LcE8)`_c2 z^H^qf6ACV0t7FLLCsu#mL&Mb8gE@rZE#k+1Nrrxw+{N0^#bN*~!qt2>S4e#jC$a$` ze4@{)$aTEYq_!#2|t@Fj3e?w-XVuG$Z}kAR?_kgJAlZIJ)0{eHw#fybNooA zp02jyYVc&w!}m#BVP>ef2|U^J(A-#O1R#A&><*?Y! zOwml{CnE+aU3JfKE@uzge(qMY{^6siuXFt;+mMbapU;Ppejl=L#>s2#SMBbfP9AFT znEVA=TBtZ6d-GfF>kOxylg>Ek%qTp*h2ze!^^hOsmKOEE6b;maQ>~R>3#z`Zawbik z88OTykU3_!Atg^+vnM=1n}?%<$dHzn)?k&T#RWwb+*y;XNQbYNHKo3wr~&}Qa$id; z6^D*K9RTQZUuQVg)g~P%!BIiv+cXllt)KEP9IN)1udQKf>p|~lXj7K<-9}0Q%i9+K zXaF7qXclE>sf)7)J4_M%V{;(sFT7HN$o0#_qU#Ah1D{ zon=JihPcgG5xHuvQwOXBkt3(iUdx{6Gn|aa>@C9Cqg%rPK(+REZ4>6t3z7m@Aj;0l zSHh&%cKSJ*+WOJGwe?Y7d(9RAy)&NVS6uj}1m@U}jXH3oVQT9E0A)$ZDRdK>;_i;+ z7vbEoI7$1XK6vNxT(_sJ(GM4s92e;gB&Q zDO;(Ve^%gPG&lWW1fUf_=9-Q1%&`s%aD^o`Q2u`WI9V>Qm#D5?SW<)Njmt@aR5@6( zL4cdTo+Jg@>Brm1^_gf%0Z?}1AppR3NdFE5uzdpBZz;{Thd6SI-$gb2}pFAww$*j(2=s{mdz2E;lBvVcrN@}i2bC`Q5Y_;BID^f0J+ACVhyQsLg0@`okIk+i=LJ=3yvI*oASj62 za3C{Pu_fQ+atw!zN{$Shr*_UV=|jp4#CqWeGE?Jb`pq!|5bDES&-Ix=-N>DpydHqW z+-{QS+i)d;uGS)M%Suw9khR}3N82j|S{a#&Tctme0s%mTy<1S|;@M-+S4#o@!qr;r z+w(n=;@43Y_n#dI0Gb(T0{G7k-KY8k`MPM_Bss$?)SK){KJMrwv!vz42_U_Za zX7lDqiU8ZvCAfGpAtfVC5bQrYa4C)M9G$S4D&VqpJ8)lm$t5FAAR%ywf>*~VaivC70RVFXISv4Lx&tk^Cf1)qQ|rxp z*8H>)cgoM;(eKxH14u~~@JopNr9@A z#-yXVG?$es;EPqsn-j?45^L52U=nT#0A^T3JY$&B3EH&%2UHdv3P=_3$!n76!34ks zz^2ii@sXAu8LKYMmG=_^*qtiiOFNlG3?QYtG%wrCZh|)vlj8vq3sw~f1b8;_TMB>z zPSyDQy_9bbXD*#sNRGMzfSAwUD}ASX;ZGQcGdE=9q~ORU{v$}=z2Bc8EOe2S&);jS zCZB8P`hPoV1NBk)TQP2z{q$NL-GLUc7%>&fecE^E{I5gs?8!qTK7VgR7Z?}-`YG|z zVN-NvOlQ+B;~J*69_Xd1n-0MLKTY6&*%rTi*0^HXniz8{bCMsVpSXqs(GGO)*_#Kz z9YBCQ_VRhtwhMfppMh@OdxjCN0mH`5hKZr>UoxMx`W~u^kD&bskplglOiRxQvep*2 z0mk+kMP>J)K`8X3`6Zq|X~5IQ-_rrOn+_WvU{1Gs{ow1-Eb;K(Z?p$@ugXpr^?PM( z(5Hv;$*X=QZaqG_4q)N1v9sO(Dsei!;%IcIztt6YUs{yj z^77e`UYa^%<-Ts+d*b=ihKt?0_sj!ePNO@K*PGmGD*v^;rRAkduikx~UNk=@{XKeV zp_ir(dTaGVWBr{_02Kg2Xmlsn|IvIIRYivbo|L{yx}yX5Bte@P6C>1KyqvYnT{boB#j-07*qoM6N<$f^XQQ A+yDRo literal 0 HcmV?d00001 diff --git a/Libraries/CMSIS/Documentation/RTOS/html/files.html b/Libraries/CMSIS/Documentation/RTOS/html/files.html new file mode 100644 index 0000000..87714d4 --- /dev/null +++ b/Libraries/CMSIS/Documentation/RTOS/html/files.html @@ -0,0 +1,133 @@ + + + + +Files + + + + + + + + + + + + + +
    + +
    + + + + + + + + + + + +
    +
    CMSIS-RTOS +  Version 1.00 +
    +
    CMSIS-RTOS API: Generic RTOS interface for Cortex-M processor-based devices.
    +
    +
    + +
    + +
    + + + +
    +
    + +
    +
    +
    + +
    +
    +
    +
    Files
    +
    +
    +
    Here is a list of all files with brief descriptions:
    + +
    cmsis_os.h
    +
    +
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    + +
    + + + + + + + + + + + +
    +
    CMSIS-RTOS +  Version 1.00 +
    +
    CMSIS-RTOS API: Generic RTOS interface for Cortex-M processor-based devices.
    +
    +
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    +
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    +
    + +
    +
    +
    Here is a list of all struct and union fields with links to the structures/unions they belong to:
    +
    +
    + + + + + diff --git a/Libraries/CMSIS/Documentation/RTOS/html/functions_vars.html b/Libraries/CMSIS/Documentation/RTOS/html/functions_vars.html new file mode 100644 index 0000000..fbbec81 --- /dev/null +++ b/Libraries/CMSIS/Documentation/RTOS/html/functions_vars.html @@ -0,0 +1,201 @@ + + + + +Data Fields - Variables + + + + + + + + + + + + + +
    + +
    + + + + + + + + + + + +
    +
    CMSIS-RTOS +  Version 1.00 +
    +
    CMSIS-RTOS API: Generic RTOS interface for Cortex-M processor-based devices.
    +
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    + +
    + +
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    +
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    +
    + +
    +
    +  +
    +
    + + + + + diff --git a/Libraries/CMSIS/Documentation/RTOS/html/globals.html b/Libraries/CMSIS/Documentation/RTOS/html/globals.html new file mode 100644 index 0000000..56b52f9 --- /dev/null +++ b/Libraries/CMSIS/Documentation/RTOS/html/globals.html @@ -0,0 +1,442 @@ + + + + +Index + + + + + + + + + + + + + +
    + +
    + + + + + + + + + + + +
    +
    CMSIS-RTOS +  Version 1.00 +
    +
    CMSIS-RTOS API: Generic RTOS interface for Cortex-M processor-based devices.
    +
    +
    + +
    + +
    + + + + + +
    +
    + +
    +
    +
    + +
    +
    +
    Here is a list of all functions, variables, defines, enums, and typedefs with links to the files they belong to:
    + +

    - o -

    +
    +
    + + + + + diff --git a/Libraries/CMSIS/Documentation/RTOS/html/globals_defs.html b/Libraries/CMSIS/Documentation/RTOS/html/globals_defs.html new file mode 100644 index 0000000..f332c01 --- /dev/null +++ b/Libraries/CMSIS/Documentation/RTOS/html/globals_defs.html @@ -0,0 +1,213 @@ + + + + +Index + + + + + + + + + + + + + +
    + +
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    CMSIS-RTOS +  Version 1.00 +
    +
    CMSIS-RTOS API: Generic RTOS interface for Cortex-M processor-based devices.
    +
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    +
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    +
    + +
    +
    +  +
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    + + + + + diff --git a/Libraries/CMSIS/Documentation/RTOS/html/globals_enum.html b/Libraries/CMSIS/Documentation/RTOS/html/globals_enum.html new file mode 100644 index 0000000..86612ca --- /dev/null +++ b/Libraries/CMSIS/Documentation/RTOS/html/globals_enum.html @@ -0,0 +1,150 @@ + + + + +Index + + + + + + + + + + + + + +
    + +
    + + + + + + + + + + + +
    +
    CMSIS-RTOS +  Version 1.00 +
    +
    CMSIS-RTOS API: Generic RTOS interface for Cortex-M processor-based devices.
    +
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    + +
    + +
    + + + + +
    +
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    +
    + +
    +
    +  +
    +
    + + + + + diff --git a/Libraries/CMSIS/Documentation/RTOS/html/globals_eval.html b/Libraries/CMSIS/Documentation/RTOS/html/globals_eval.html new file mode 100644 index 0000000..6ea2f57 --- /dev/null +++ b/Libraries/CMSIS/Documentation/RTOS/html/globals_eval.html @@ -0,0 +1,213 @@ + + + + +Index + + + + + + + + + + + + + +
    + +
    + + + + + + + + + + + +
    +
    CMSIS-RTOS +  Version 1.00 +
    +
    CMSIS-RTOS API: Generic RTOS interface for Cortex-M processor-based devices.
    +
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    + +
    +
    +  +
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    + + + + + diff --git a/Libraries/CMSIS/Documentation/RTOS/html/globals_func.html b/Libraries/CMSIS/Documentation/RTOS/html/globals_func.html new file mode 100644 index 0000000..4da7758 --- /dev/null +++ b/Libraries/CMSIS/Documentation/RTOS/html/globals_func.html @@ -0,0 +1,253 @@ + + + + +Index + + + + + + + + + + + + + +
    + +
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    +
    CMSIS-RTOS +  Version 1.00 +
    +
    CMSIS-RTOS API: Generic RTOS interface for Cortex-M processor-based devices.
    +
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    +
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    +  + +

    - o -

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    + + + + + diff --git a/Libraries/CMSIS/Documentation/RTOS/html/globals_type.html b/Libraries/CMSIS/Documentation/RTOS/html/globals_type.html new file mode 100644 index 0000000..ad6be33 --- /dev/null +++ b/Libraries/CMSIS/Documentation/RTOS/html/globals_type.html @@ -0,0 +1,165 @@ + + + + +Index + + + + + + + + + + + + + +
    + +
    + + + + + + + + + + + +
    +
    CMSIS-RTOS +  Version 1.00 +
    +
    CMSIS-RTOS API: Generic RTOS interface for Cortex-M processor-based devices.
    +
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    + + + + + diff --git a/Libraries/CMSIS/Documentation/RTOS/html/group___c_m_s_i_s___r_t_o_s.html b/Libraries/CMSIS/Documentation/RTOS/html/group___c_m_s_i_s___r_t_o_s.html new file mode 100644 index 0000000..79f2a64 --- /dev/null +++ b/Libraries/CMSIS/Documentation/RTOS/html/group___c_m_s_i_s___r_t_o_s.html @@ -0,0 +1,177 @@ + + + + +CMSIS-RTOS API + + + + + + + + + + + + + +
    + +
    + + + + + + + + + + + +
    +
    CMSIS-RTOS +  Version 1.00 +
    +
    CMSIS-RTOS API: Generic RTOS interface for Cortex-M processor-based devices.
    +
    +
    + +
    + +
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    + +
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    +
    + +
    +
    +
    +Modules
    +
    +
    CMSIS-RTOS API
    +
    +
    + +

    This section describes the CMSIS-RTOS API. +More...

    + + + + + + + + + + + + + + + + + + + + + + + + + + +

    +Modules

     Kernel Information and Control
     

    Provide version/system information and start the RTOS Kernel.

    +
     Thread Management
     

    Define, create, and control thread functions.

    +
     Generic Wait Functions
     

    Wait for a time period or unspecified events.

    +
     Timer Management
     

    Create and control timer and timer callback functions.

    +
     Signal Management
     

    Control or wait for signal flags.

    +
     Mutex Management
     

    Synchronize thread execution with a Mutex.

    +
     Semaphore Management
     

    Control access to shared resources.

    +
     Memory Pool Management
     

    Define and manage fixed-size memory pools.

    +
     Message Queue Management
     

    Control, send, receive, or wait for messages.

    +
     Mail Queue Management
     

    Control, send, receive, or wait for mail.

    +
     Generic Data Types and Definitions
     

    Data Type Definitions used by the CMSIS-RTOS API functions.

    +
     Status and Error Codes
     

    Status and Error Codes returned by CMSIS-RTOS API functions.

    +
    +

    Description

    +

    The CMSIS-RTOS is a generic API layer that interfaces to an existing RTOS kernel. It provides the following functional modules:

    +
    +
    + + + + + diff --git a/Libraries/CMSIS/Documentation/RTOS/html/group___c_m_s_i_s___r_t_o_s___definitions.html b/Libraries/CMSIS/Documentation/RTOS/html/group___c_m_s_i_s___r_t_o_s___definitions.html new file mode 100644 index 0000000..81dd20d --- /dev/null +++ b/Libraries/CMSIS/Documentation/RTOS/html/group___c_m_s_i_s___r_t_o_s___definitions.html @@ -0,0 +1,300 @@ + + + + +Generic Data Types and Definitions + + + + + + + + + + + + + +
    + +
    + + + + + + + + + + + +
    +
    CMSIS-RTOS +  Version 1.00 +
    +
    CMSIS-RTOS API: Generic RTOS interface for Cortex-M processor-based devices.
    +
    +
    + +
    + +
    + + + +
    +
    + +
    +
    +
    + +
    +
    +
    +Data Structures
    +
    +
    Generic Data Types and Definitions
    +
    CMSIS-RTOS API
    +
    + +

    Data Type Definitions used by the CMSIS-RTOS API functions. +More...

    + + + + + +

    +Data Structures

    struct  osEvent
     Event structure contains detailed information about an event. More...
    struct  os_mailQ
    +

    Description

    +

    The Data Type section lists all data types that are used to exchange information with CMSIS-RTOS functions.

    +

    Data Structure Documentation

    + +
    +
    + + + + +
    struct osEvent
    +
    +
    +
    Note:
    MUST REMAIN UNCHANGED: os_event shall be consistent in every CMSIS-RTOS. However the struct may be extended at the end.
    +

    The osEvent structure describes the events returned by CMSIS-RTOS functions.

    +
    + + + + + + + + + + + + + + + + + + + +

    Data Fields

    osStatus status
     status code: event or error information
    union {
       uint32_t   v
     message as 32-bit value
       void *   p
     message or mail as void pointer
       int32_t   signals
     signal flags
    } value
     event value
    union {
       osMailQId   mail_id
     mail id obtained by osMailCreate
       osMessageQId   message_id
     message id obtained by osMessageCreate
    } def
     event definition
    +

    Field Documentation

    + +
    +
    + + + + +
    union { ... } def
    +
    +
    + +
    +
    + +
    +
    + + + + +
    osMailQId mail_id
    +
    +
    + +
    +
    + +
    +
    + + + + +
    osMessageQId message_id
    +
    +
    + +
    +
    + +
    +
    + + + + +
    void* p
    +
    +
    + +
    +
    + +
    +
    + + + + +
    int32_t signals
    +
    +
    + +
    +
    + +
    +
    + + + + +
    osStatus status
    +
    +
    + +
    +
    + +
    +
    + + + + +
    uint32_t v
    +
    +
    + +
    +
    + +
    +
    + + + + +
    union { ... } value
    +
    +
    + +
    +
    + +
    +
    + +
    +
    + + + + +
    struct os_mailQ
    +
    +
    +

    The osEvent structure describes the events returned by CMSIS-RTOS functions.

    +
    +
    +
    +
    +
    + + + + + diff --git a/Libraries/CMSIS/Documentation/RTOS/html/group___c_m_s_i_s___r_t_o_s___kernel_ctrl.html b/Libraries/CMSIS/Documentation/RTOS/html/group___c_m_s_i_s___r_t_o_s___kernel_ctrl.html new file mode 100644 index 0000000..cd2f1e9 --- /dev/null +++ b/Libraries/CMSIS/Documentation/RTOS/html/group___c_m_s_i_s___r_t_o_s___kernel_ctrl.html @@ -0,0 +1,284 @@ + + + + +Kernel Information and Control + + + + + + + + + + + + + +
    + +
    + + + + + + + + + + + +
    +
    CMSIS-RTOS +  Version 1.00 +
    +
    CMSIS-RTOS API: Generic RTOS interface for Cortex-M processor-based devices.
    +
    +
    + +
    + +
    + + + +
    +
    + +
    +
    +
    + +
    +
    +
    +Defines | +Functions
    +
    +
    Kernel Information and Control
    +
    CMSIS-RTOS API
    +
    + +

    Provide version/system information and start the RTOS Kernel. +More...

    + + + + + + + + + + + + + + + +

    +Defines

    #define osFeature_MainThread   1
     main thread 1=main can be thread, 0=not available
    #define osCMSIS   0x00003
     API version (main [31:16] .sub [15:0])
    #define osCMSIS_KERNEL   0x10000
     RTOS identification and version (main [31:16] .sub [15:0])
    #define osKernelSystemId   "KERNEL V1.00"
     RTOS identification string.

    +Functions

    osStatus osKernelStart (osThreadDef_t *thread_def, void *argument)
     Start the RTOS Kernel with executing the specified thread.
    int32_t osKernelRunning (void)
     Check if the RTOS kernel is already started.
    +

    Description

    +

    The Kernel Information and Control function group allow to:

    +
      +
    • obtain information about the system and the underlaying kernel.
      • +
    • obtain version information about the CMSIS RTOS API.
      • +
    • the start of the RTOS kernel.
      • +
    • checking the execution status of the RTOS kernel.
      • +
    +

    The function main is a special thread function that may be started at system initialization. In this case it has the initial priority osPriorityNormal.

    +

    Define Documentation

    + +
    +
    + + + + +
    #define osCMSIS   0x00003
    +
    +
    +

    Version information of the CMSIS RTOS API whereby major verison is in bits [31:16] and sub version in bits [15:0]. The value 0x10000 represents version 1.00.

    +
    Note:
    MUST REMAIN UNCHANGED: osCMSIS identifies the CMSIS-RTOS API version
    + +
    +
    + +
    +
    + + + + +
    #define osCMSIS_KERNEL   0x10000
    +
    +
    +

    Identifies the underlaying RTOS kernel and version number. The actual name of that define depends on the RTOS Kernel used in the implementation. For example, osCMSIS_FreeRTOS identifies the FreeRTOS kernel and the value indicates the version number of that kernel whereby the major verison is in bits [31:16] and sub version in bits [15:0]. The value 0x10000 represents version 1.00.

    +
    Note:
    CAN BE CHANGED: osCMSIS_KERNEL identifies the underlaying RTOS kernel and version number.
    + +
    +
    + +
    +
    + + + + +
    #define osFeature_MainThread   1
    +
    +
    +

    A CMSIS-RTOS implementation may support to start thread execution with the function 'main'. When the value osFeature_MainThread is 1 the RTOS offers to start with 'main'. The RTOS kernel is in this case already started. When the value osFeature_MainThread is 0 the RTOS requries explicit start with osKernelStart.

    +
    Note:
    MUST REMAIN UNCHANGED: osFeature_xxx shall be consistent in every CMSIS-RTOS.
    + +
    +
    + +
    +
    + + + + +
    #define osKernelSystemId   "KERNEL V1.00"
    +
    +
    +

    Defines a string that identifies the underlaying RTOS Kernel and provides version information. The lenght of that string is limited to 21 bytes. A valid indenification string is for example, "FreeRTOS V1.00".

    +
    Note:
    MUST REMAIN UNCHANGED: osKernelSystemId shall be consistent in every CMSIS-RTOS.
    + +
    +
    +

    Function Documentation

    + +
    +
    + + + + + + + + +
    int32_t osKernelRunning (void )
    +
    +
    +
    Note:
    MUST REMAIN UNCHANGED: osKernelRunning shall be consistent in every CMSIS-RTOS.
    +
    Returns:
    0 RTOS is not started, 1 RTOS is started.
    +

    Identifies if the RTOS kernel is started. For systems with the option to start the 'main' function as a thread this allows to identify that the RTOS kernel is already running.

    + +
    +
    + +
    +
    + + + + + + + + + + + + + + + + + + +
    void osKernelStart (osThreadDef_t * thread_def,
    void * argument 
    )
    +
    +
    +
    Parameters:
    + + + +
    [in]thread_defthread definition referenced with osThread.
    [in]argumentpointer that is passed to the thread function as start argument.
    +
    +
    +
    Returns:
    status code that indicates the execution status of the function.
    +
    Note:
    MUST REMAIN UNCHANGED: osKernelStart shall be consistent in every CMSIS-RTOS.
    +

    Start the RTOS Kernel and begin execution of the thread function specified by thread_def. The argument is passed to the thread function.

    +

    When the CMSIS-RTOS starts thread execution with 'main', the function osKernelStart terminates this 'main; thread and starts execution with the specified thread function. This ensures that the code is portable regardless weather the function 'main' is started as thread or executed without control of the RTOS kernel.

    +
    Note:
    The thread ID of the started thread can be obtained with the function osThreadGetId.
    + +
    +
    +
    +
    + + + + + diff --git a/Libraries/CMSIS/Documentation/RTOS/html/group___c_m_s_i_s___r_t_o_s___mail.html b/Libraries/CMSIS/Documentation/RTOS/html/group___c_m_s_i_s___r_t_o_s___mail.html new file mode 100644 index 0000000..a6390e5 --- /dev/null +++ b/Libraries/CMSIS/Documentation/RTOS/html/group___c_m_s_i_s___r_t_o_s___mail.html @@ -0,0 +1,499 @@ + + + + +Mail Queue Management + + + + + + + + + + + + + +
    + +
    + + + + + + + + + + + +
    +
    CMSIS-RTOS +  Version 1.00 +
    +
    CMSIS-RTOS API: Generic RTOS interface for Cortex-M processor-based devices.
    +
    +
    + +
    + +
    + + + +
    +
    + +
    +
    +
    + +
    +
    +
    +Defines | +Functions
    +
    +
    Mail Queue Management
    +
    CMSIS-RTOS API
    +
    + +

    Control, send, receive, or wait for mail. +More...

    + + + + + + + + + + + + + + + + + + + + + +

    +Defines

    #define osFeature_MailQ   1
     Mail Queues: 1=available, 0=not available.
    #define osMailQDef(name, queue_sz, type)
     Create a Mail Queue Definition.
    #define osMailQ(name)   &os_mailQ_def_##name
     Access a Mail Queue Definition.

    +Functions

    osMailQId osMailCreate (osMailQDef_t *queue_def, osThreadId thread_id)
     Create and Initialize mail queue.
    void * osMailAlloc (osMailQId queue_id, uint32_t millisec)
     Allocate a memory block from a mail.
    void * osMailCAlloc (osMailQId queue_id, uint32_t millisec)
     Allocate a memory block from a mail and set memory block to zero.
    osStatus osMailPut (osMailQId queue_id, void *mail)
     Put a mail to a queue.
    osEvent osMailGet (osMailQId queue_id, uint32_t millisec)
     Get a mail from a queue.
    osStatus osMailFree (osMailQId queue_id, void *mail)
     Free a memory block from a mail.
    +

    Description

    +

    The Mail Queue Management function group allow to control, send, receive, or wait for mail. A mail is a memory block that is send to a thread or interrupt service routine.

    +
    +MailQueue.png +
    +CMSIS-RTOS Mail Queue
    +

    Define Documentation

    + +
    +
    + + + + +
    #define osFeature_MailQ   1
    +
    +
    +

    A CMSIS-RTOS implementation may support mail queues. When the value osFeature_MailQ is 1 mail queues are supported. When the value osFeature_MailQ is 0 no mail queues are supported.

    + +
    +
    + +
    +
    + + + + + + + + +
    #define osMailQ( name)   &os_mailQ_def_##name
    +
    +
    +

    Access to the mail queue definition for the function osMailCreate.

    +
    Parameters:
    + + +
    namename of the queue
    +
    +
    +
    Note:
    CAN BE CHANGED: The parameter to osMailQ shall be consistent but the macro body is implementation specific in every CMSIS-RTOS.
    + +
    +
    + +
    +
    + + + + + + + + + + + + + + + + + + + + + + + + +
    #define osMailQDef( name,
     queue_sz,
     type 
    )
    +
    +
    +

    Define the attributes of a mail queue that can by the function osMailCreate using osMailQ.

    +
    Parameters:
    + + + + +
    namename of the queue
    queue_szmaximum number of messages in queue
    typedata type of a single message element
    +
    +
    +
    Note:
    CAN BE CHANGED: The parameter to osMailQDef shall be consistent but the macro body is implementation specific in every CMSIS-RTOS.
    + +
    +
    +

    Function Documentation

    + +
    +
    + + + + + + + + + + + + + + + + + + +
    void * osMailAlloc (osMailQId queue_id,
    uint32_t millisec 
    )
    +
    +
    +
    Parameters:
    + + + +
    [in]queue_idmail queue ID obtained with osMailCreate.
    [in]millisectimeout value or 0 in case of no time-out
    +
    +
    +
    Returns:
    pointer to memory block that can be filled with mail or NULL in case error.
    +
    Note:
    MUST REMAIN UNCHANGED: osMailAlloc shall be consistent in every CMSIS-RTOS.
    +

    Allocate a memory block from the mail queue that is filled with the mail information. When no memory block slot is available, the tread is put into the state WAITING for the time specified with millisec. When millisec is set to osWaitForever the function will wait for an infinite time until a mail queue slot becomes available.

    +

    A NULL pointer is returned when no memory slot can be obtained or queue specifies an illegal parameter.

    +
    Note:
    The parameter millisec must be 0 for using this function in an ISR.
    + +
    +
    + +
    +
    + + + + + + + + + + + + + + + + + + +
    void * osMailCAlloc (osMailQId queue_id,
    uint32_t millisec 
    )
    +
    +
    +
    Parameters:
    + + + +
    [in]queue_idmail queue ID obtained with osMailCreate.
    [in]millisectimeout value or 0 in case of no time-out
    +
    +
    +
    Returns:
    pointer to memory block that can shall filled with mail or NULL in case error.
    +
    Note:
    MUST REMAIN UNCHANGED: osMailCAlloc shall be consistent in every CMSIS-RTOS.
    +

    Allocate a memory block from the mail queue that is filled with the mail information. The memory block returned is cleared. When no memory block is available, the tread is put into the state WAITING for the time specified with millisec. When millisec is set to osWaitForever the function will wait for an infinite time until a mail queue slot becomes available.

    +

    A NULL pointer is returned when no memory block can be obtained or queue specifies an illegal parameter.

    +
    Note:
    The parameter millisec must be 0 for using this function in an ISR.
    + +
    +
    + +
    +
    + + + + + + + + + + + + + + + + + + +
    osMailQId osMailCreate (osMailQDef_t * queue_def,
    osThreadId thread_id 
    )
    +
    +
    +
    Parameters:
    + + + +
    [in]queue_defreference to the mail queue definition obtain with osMailQ
    [in]thread_idthread ID (obtained by osThreadCreate or osThreadGetId) or NULL.
    +
    +
    +
    Returns:
    mail queue ID for reference by other functions or NULL in case of error.
    +
    Note:
    MUST REMAIN UNCHANGED: osMailCreate shall be consistent in every CMSIS-RTOS.
    +

    Initialize and create a mail queue.

    + +
    +
    + +
    +
    + + + + + + + + + + + + + + + + + + +
    osStatus osMailFree (osMailQId queue_id,
    void * mail 
    )
    +
    +
    +
    Parameters:
    + + + +
    [in]queue_idmail queue ID obtained with osMailCreate.
    [in]mailpointer to the memory block that was obtained with osMailGet.
    +
    +
    +
    Returns:
    status code that indicates the execution status of the function.
    +
    Note:
    MUST REMAIN UNCHANGED: osMailFree shall be consistent in every CMSIS-RTOS.
    +

    Free the memory block specified by mail and return it to the mail queue.

    +

    Status and Error Codes
    +

    +
      +
    • osOK: the mail block is released.
      • +
    • osErrorValue: mail block does not belong to the mail queue pool.
      • +
    • osErrorParameter: the value to the parameter queue is incorrect.
      • +
    + +
    +
    + +
    +
    + + + + + + + + + + + + + + + + + + +
    osEvent osMailGet (osMailQId queue_id,
    uint32_t millisec 
    )
    +
    +
    +
    Parameters:
    + + + +
    [in]queue_idmail queue ID obtained with osMailCreate.
    [in]millisectimeout value or 0 in case of no time-out
    +
    +
    +
    Returns:
    event that contains mail information or error code.
    +
    Note:
    MUST REMAIN UNCHANGED: osMailGet shall be consistent in every CMSIS-RTOS.
    +

    Suspend the execution of the current RUNNING thread until a mail arrives. When a mail is already in the queue, the function returns instantly with the mail information. When millisec is 0, the function returns instantly with status osOK. Otherwise the thread is put into the state WAITING. When millisec is set to osWaitForever the function will wait for an infinite time until a mail arrives.

    +
    Note:
    The parameter millisec must be 0 for using this function in an ISR.
    +

    Status and Error Codes
    +

    +
      +
    • osOK: no mail is available in the queue and no timeout was specified
      • +
    • osEventTimeout: no mail has arrived during the given timeout period.
      • +
    • osEventMail: mail received, value.p contains the pointer to mail content.
      • +
    • osErrorParameter: a parameter is invalid or outside of a permitted range.
      • +
    + +
    +
    + +
    +
    + + + + + + + + + + + + + + + + + + +
    osStatus osMailPut (osMailQId queue_id,
    void * mail 
    )
    +
    +
    +
    Parameters:
    + + + +
    [in]queue_idmail queue ID obtained with osMailCreate.
    [in]mailmemory block previously allocated with osMailAlloc or osMailCAlloc.
    +
    +
    +
    Returns:
    status code that indicates the execution status of the function.
    +
    Note:
    MUST REMAIN UNCHANGED: osMailPut shall be consistent in every CMSIS-RTOS.
    +

    Put the memory block specified with mail into the mail queue specified by queue.

    +

    Status and Error Codes
    +

    +
      +
    • osOK: the message is put into the queue.
      • +
    • osErrorValue: mail was previously not allocated as memory slot.
      • +
    • osErrorParameter: a parameter is invalid or outside of a permitted range.
      • +
    + +
    +
    +
    +
    + + + + + diff --git a/Libraries/CMSIS/Documentation/RTOS/html/group___c_m_s_i_s___r_t_o_s___message.html b/Libraries/CMSIS/Documentation/RTOS/html/group___c_m_s_i_s___r_t_o_s___message.html new file mode 100644 index 0000000..7e383fa --- /dev/null +++ b/Libraries/CMSIS/Documentation/RTOS/html/group___c_m_s_i_s___r_t_o_s___message.html @@ -0,0 +1,380 @@ + + + + +Message Queue Management + + + + + + + + + + + + + +
    + +
    + + + + + + + + + + + +
    +
    CMSIS-RTOS +  Version 1.00 +
    +
    CMSIS-RTOS API: Generic RTOS interface for Cortex-M processor-based devices.
    +
    +
    + +
    + +
    + + + +
    +
    + +
    +
    +
    + +
    +
    +
    +Defines | +Functions
    +
    +
    Message Queue Management
    +
    CMSIS-RTOS API
    +
    + +

    Control, send, receive, or wait for messages. +More...

    + + + + + + + + + + + + + + + +

    +Defines

    #define osFeature_MessageQ   1
     Message Queues: 1=available, 0=not available.
    #define osMessageQDef(name, queue_sz, type)
     Create a Message Queue Definition.
    #define osMessageQ(name)   &os_messageQ_def_##name
     Access a Message Queue Definition.

    +Functions

    osMessageQId osMessageCreate (osMessageQDef_t *queue_def, osThreadId thread_id)
     Create and Initialize a Message Queue.
    osStatus osMessagePut (osMessageQId queue_id, uint32_t info, uint32_t millisec)
     Put a Message to a Queue.
    osEvent osMessageGet (osMessageQId queue_id, uint32_t millisec)
     Get a Message or Wait for a Message from a Queue.
    +

    Description

    +

    Message Queue Management functions allow to control, send, receive, or wait for messages. A message can be an integer or pointer value that is send to a thread or interrupt service routine.

    +
    +MessageQueue.png +
    +CMSIS-RTOS Message Queue
    +

    Define Documentation

    + +
    +
    + + + + +
    #define osFeature_MessageQ   1
    +
    +
    +

    A CMSIS-RTOS implementation may support message queues. When the value osFeature_MailQ is 1 message queues are supported. When the value osFeature_MailQ is 0 no message queues are supported.

    + +
    +
    + +
    +
    + + + + + + + + +
    #define osMessageQ( name)   &os_messageQ_def_##name
    +
    +
    +

    Access to the message queue definition for the function osMessageCreate.

    +
    Parameters:
    + + +
    namename of the queue
    +
    +
    +
    Note:
    CAN BE CHANGED: The parameter to osMessageQ shall be consistent but the macro body is implementation specific in every CMSIS-RTOS.
    + +
    +
    + +
    +
    + + + + + + + + + + + + + + + + + + + + + + + + +
    #define osMessageQDef( name,
     queue_sz,
     type 
    )
    +
    +
    +

    Define the attributes of a message queue created by the function osMessageCreate using osMessageQ.

    +
    Parameters:
    + + + + +
    namename of the queue.
    queue_szmaximum number of messages in the queue.
    typedata type of a single message element (for debugger).
    +
    +
    +
    Note:
    CAN BE CHANGED: The parameter to osMessageQDef shall be consistent but the macro body is implementation specific in every CMSIS-RTOS.
    + +
    +
    +

    Function Documentation

    + +
    +
    + + + + + + + + + + + + + + + + + + +
    osMessageQId osMessageCreate (osMessageQDef_t * queue_def,
    osThreadId thread_id 
    )
    +
    +
    +
    Parameters:
    + + + +
    [in]queue_defqueue definition referenced with osMessageQ.
    [in]thread_idthread ID (obtained by osThreadCreate or osThreadGetId) or NULL.
    +
    +
    +
    Returns:
    message queue ID for reference by other functions or NULL in case of error.
    +
    Note:
    MUST REMAIN UNCHANGED: osMessageCreate shall be consistent in every CMSIS-RTOS.
    +

    Create and initialize a message queue.

    + +
    +
    + +
    +
    + + + + + + + + + + + + + + + + + + +
    osEvent osMessageGet (osMessageQId queue_id,
    uint32_t millisec 
    )
    +
    +
    +
    Parameters:
    + + + +
    [in]queue_idmessage queue ID obtained with osMessageCreate.
    [in]millisectimeout value or 0 in case of no time-out.
    +
    +
    +
    Returns:
    event information that includes status code.
    +
    Note:
    MUST REMAIN UNCHANGED: osMessageGet shall be consistent in every CMSIS-RTOS.
    +

    Suspend the execution of the current RUNNING thread until a message arrives. When a message is already in the queue, the function returns instantly with the message information. When millisec is 0, the function returns instantly with status osOK. Otherwise the thread is put into the state WAITING. When millisec is set to osWaitForever the function will wait for an infinite time until a message arrives.

    +
    Note:
    The parameter millisec must be 0 for using this function in an ISR.
    +

    Status and Error Codes
    +

    +
      +
    • osOK: no message is available in the queue and no timeout was specified.
      • +
    • osEventTimeout: no message has arrived during the given timeout period.
      • +
    • osEventMessage: message received, value.p contains the pointer to message.
      • +
    • osErrorParameter: a parameter is invalid or outside of a permitted range.
      • +
    + +
    +
    + +
    +
    + + + + + + + + + + + + + + + + + + + + + + + + +
    osStatus osMessagePut (osMessageQId queue_id,
    uint32_t info,
    uint32_t millisec 
    )
    +
    +
    +
    Parameters:
    + + + + +
    [in]queue_idmessage queue ID obtained with osMessageCreate.
    [in]infomessage information.
    [in]millisectimeout value or 0 in case of no time-out.
    +
    +
    +
    Returns:
    status code that indicates the execution status of the function.
    +
    Note:
    MUST REMAIN UNCHANGED: osMessagePut shall be consistent in every CMSIS-RTOS.
    +

    Put the message info in a message queue specified by queue_id. When the message queue is full, the system retry for a specified time with millisec. In this case, the tread is put into the state WAITING. When millisec is set to osWaitForever, the function will wait for an infinite time until a message queue slot becomes available.

    +
    Note:
    The parameter millisec must be 0 for using this function in an ISR.
    +

    Status and Error Codes
    +

    +
      +
    • osOK: the message is put into the queue.
      • +
    • osErrorResource: no memory in the queue was available.
      • +
    • osErrorTimeoutResource: no memory in the queue was available during the given time limit.
      • +
    • osErrorParameter: a parameter is invalid or outside of a permitted range.
      • +
    + +
    +
    +
    +
    + + + + + diff --git a/Libraries/CMSIS/Documentation/RTOS/html/group___c_m_s_i_s___r_t_o_s___mutex_mgmt.html b/Libraries/CMSIS/Documentation/RTOS/html/group___c_m_s_i_s___r_t_o_s___mutex_mgmt.html new file mode 100644 index 0000000..5474e13 --- /dev/null +++ b/Libraries/CMSIS/Documentation/RTOS/html/group___c_m_s_i_s___r_t_o_s___mutex_mgmt.html @@ -0,0 +1,317 @@ + + + + +Mutex Management + + + + + + + + + + + + + +
    + +
    + + + + + + + + + + + +
    +
    CMSIS-RTOS +  Version 1.00 +
    +
    CMSIS-RTOS API: Generic RTOS interface for Cortex-M processor-based devices.
    +
    +
    + +
    + +
    + + + +
    +
    + +
    +
    +
    + +
    +
    +
    +Defines | +Functions
    +
    +
    Mutex Management
    +
    CMSIS-RTOS API
    +
    + +

    Synchronize thread execution with a Mutex. +More...

    + + + + + + + + + + + + + +

    +Defines

    #define osMutexDef(name)   osMutexDef_t os_mutex_def_##name = { 0 }
     Define a Mutex.
    #define osMutex(name)   &os_mutex_def_##name
     Access a Mutex defintion.

    +Functions

    osMutexId osMutexCreate (osMutexDef_t *mutex_def)
     Create and Initialize a Mutex object.
    osStatus osMutexWait (osMutexId mutex_id, uint32_t millisec)
     Wait until a Mutex becomes available.
    osStatus osMutexRelease (osMutexId mutex_id)
     Release a Mutex that was obtained by osMutexWait.
    +

    Description

    +

    The Mutex Management function group is used to synchronize the execution of threads. This is for example used to protect access to a shared resource, for example a shared memory image.

    +
    Note:
    Mutex Management functions cannot be called from interrupt service routines (ISR).
    +
    +Mutex.png +
    +CMSIS-RTOS Mutex
    +

    Define Documentation

    + +
    +
    + + + + + + + + +
    #define osMutex( name)   &os_mutex_def_##name
    +
    +
    +

    Access to mutex object for the functions osMutexCreate.

    +
    Parameters:
    + + +
    namename of the mutex object.
    +
    +
    +
    Note:
    CAN BE CHANGED: The parameter to osMutex shall be consistent but the macro body is implementation specific in every CMSIS-RTOS.
    + +
    +
    + +
    +
    + + + + + + + + +
    #define osMutexDef( name)   osMutexDef_t os_mutex_def_##name = { 0 }
    +
    +
    +

    Define a mutex object that is referenced by osMutex.

    +
    Parameters:
    + + +
    namename of the mutex object.
    +
    +
    +
    Note:
    CAN BE CHANGED: The parameter to osMutexDef shall be consistent but the macro body is implementation specific in every CMSIS-RTOS.
    + +
    +
    +

    Function Documentation

    + +
    +
    + + + + + + + + +
    osMutexId osMutexCreate (osMutexDef_t * mutex_def)
    +
    +
    +
    Parameters:
    + + +
    [in]mutex_defmutex definition referenced with osMutex.
    +
    +
    +
    Returns:
    mutex ID for reference by other functions or NULL in case of error.
    +
    Note:
    MUST REMAIN UNCHANGED: osMutexCreate shall be consistent in every CMSIS-RTOS.
    +

    Create and initialize a Mutex object.

    + +
    +
    + +
    +
    + + + + + + + + +
    osStatus osMutexRelease (osMutexId mutex_id)
    +
    +
    +
    Parameters:
    + + +
    [in]mutex_idmutex ID obtained by osMutexCreate.
    +
    +
    +
    Returns:
    status code that indicates the execution status of the function.
    +
    Note:
    MUST REMAIN UNCHANGED: osMutexRelease shall be consistent in every CMSIS-RTOS.
    +

    Release a Mutex that was obtained with osMutexWait. Other threads that currently wait for the same mutex will be now put into the state READY.

    +

    Status and Error Codes
    +

    +
      +
    • osOK: the mutex has been correctly released.
      • +
    • osErrorResource: the mutex was not obtained before.
      • +
    • osErrorParameter: the parameter mutex_id is incorrect.
      • +
    • osErrorISR: osMutexRelease cannot be called from interrupt service routines.
      • +
    + +
    +
    + +
    +
    + + + + + + + + + + + + + + + + + + +
    osStatus osMutexWait (osMutexId mutex_id,
    uint32_t millisec 
    )
    +
    +
    +
    Parameters:
    + + + +
    [in]mutex_idmutex ID obtained by osMutexCreate.
    [in]millisectimeout value or 0 in case of no time-out.
    +
    +
    +
    Returns:
    status code that indicates the execution status of the function.
    +
    Note:
    MUST REMAIN UNCHANGED: osMutexWait shall be consistent in every CMSIS-RTOS.
    +

    Wait until a Mutex becomes available. If no other thread has obtained the Mutex, the function instantly returns and blocks the mutex object.

    +

    Status and Error Codes
    +

    +
      +
    • osOK: the mutex has been obtain.
      • +
    • osErrorTimeoutResource: the mutex could not be obtained in the given time.
      • +
    • osErrorResource: the mutex could not be obtained when no timeout was specified.
      • +
    • osErrorParameter: the parameter mutex_id is incorrect.
      • +
    • osErrorISR: osMutexWait cannot be called from interrupt service routines.
      • +
    + +
    +
    +
    +
    + + + + + diff --git a/Libraries/CMSIS/Documentation/RTOS/html/group___c_m_s_i_s___r_t_o_s___pool_mgmt.html b/Libraries/CMSIS/Documentation/RTOS/html/group___c_m_s_i_s___r_t_o_s___pool_mgmt.html new file mode 100644 index 0000000..b42bd16 --- /dev/null +++ b/Libraries/CMSIS/Documentation/RTOS/html/group___c_m_s_i_s___r_t_o_s___pool_mgmt.html @@ -0,0 +1,364 @@ + + + + +Memory Pool Management + + + + + + + + + + + + + +
    + +
    + + + + + + + + + + + +
    +
    CMSIS-RTOS +  Version 1.00 +
    +
    CMSIS-RTOS API: Generic RTOS interface for Cortex-M processor-based devices.
    +
    +
    + +
    + +
    + + + +
    +
    + +
    +
    +
    + +
    +
    +
    +Defines | +Functions
    +
    +
    Memory Pool Management
    +
    CMSIS-RTOS API
    +
    + +

    Define and manage fixed-size memory pools. +More...

    + + + + + + + + + + + + + + + + + +

    +Defines

    #define osFeature_Pool   1
     Memory Pools: 1=available, 0=not available.
    #define osPoolDef(name, no, type)
     Define a Memory Pool.
    #define osPool(name)   &os_pool_def_##name
     Access a Memory Pool definition.

    +Functions

    osPoolId osPoolCreate (osPoolDef_t *pool_def)
     Create and Initialize a memory pool.
    void * osPoolAlloc (osPoolId pool_id)
     Allocate a memory block from a memory pool.
    void * osPoolCAlloc (osPoolId pool_id)
     Allocate a memory block from a memory pool and set memory block to zero.
    osStatus osPoolFree (osPoolId pool_id, void *block)
     Return an allocated memory block back to a specific memory pool.
    +

    Description

    +

    The Memory Pool Management function group is used to define and manage fixed-sized memory pools.

    +

    Define Documentation

    + +
    +
    + + + + +
    #define osFeature_Pool   1
    +
    +
    +

    A CMSIS-RTOS implementation may support fixed-size memory pools. When the value osFeature_Pool is 1 memory pools are supported. When the value osFeature_Pool is 0 no memory pools are supported.

    + +
    +
    + +
    +
    + + + + + + + + +
    #define osPool( name)   &os_pool_def_##name
    +
    +
    +

    Access a memory pool for the functions osPoolCreate.

    +
    Parameters:
    + + +
    namename of the memory pool
    +
    +
    +
    Note:
    CAN BE CHANGED: The parameter to osPool shall be consistent but the macro body is implementation specific in every CMSIS-RTOS.
    + +
    +
    + +
    +
    + + + + + + + + + + + + + + + + + + + + + + + + +
    #define osPoolDef( name,
     no,
     type 
    )
    +
    +
    +

    Define a memory pool that is referenced by osPool.

    +
    Parameters:
    + + + + +
    namename of the memory pool.
    nomaximum number of objects (elements) in the memory pool.
    typedata type of a single object (element).
    +
    +
    +
    Note:
    CAN BE CHANGED: The parameter to osPoolDef shall be consistent but the macro body is implementation specific in every CMSIS-RTOS.
    + +
    +
    +

    Function Documentation

    + +
    +
    + + + + + + + + +
    void * osPoolAlloc (osPoolId pool_id)
    +
    +
    +
    Parameters:
    + + +
    [in]pool_idmemory pool ID obtain referenced with osPoolCreate.
    +
    +
    +
    Returns:
    address of the allocated memory block or NULL in case of no memory available.
    +
    Note:
    MUST REMAIN UNCHANGED: osPoolAlloc shall be consistent in every CMSIS-RTOS.
    +

    Allocate a memory block from the memory pool.

    + +
    +
    + +
    +
    + + + + + + + + +
    void * osPoolCAlloc (osPoolId pool_id)
    +
    +
    +
    Parameters:
    + + +
    [in]pool_idmemory pool ID obtain referenced with osPoolCreate.
    +
    +
    +
    Returns:
    address of the allocated memory block or NULL in case of no memory available.
    +
    Note:
    MUST REMAIN UNCHANGED: osPoolCAlloc shall be consistent in every CMSIS-RTOS.
    +

    Allocate a memory block from the memory pool. The block is initialized to zero.

    + +
    +
    + +
    +
    + + + + + + + + +
    osPoolId osPoolCreate (osPoolDef_t * pool_def)
    +
    +
    +
    Parameters:
    + + +
    [in]pool_defmemory pool definition referenced with osPool.
    +
    +
    +
    Returns:
    memory pool ID for reference by other functions or NULL in case of error.
    +
    Note:
    MUST REMAIN UNCHANGED: osPoolCreate shall be consistent in every CMSIS-RTOS.
    +

    Create and initialize a memory pool.

    + +
    +
    + +
    +
    + + + + + + + + + + + + + + + + + + +
    osStatus osPoolFree (osPoolId pool_id,
    void * block 
    )
    +
    +
    +
    Parameters:
    + + + +
    [in]pool_idmemory pool ID obtain referenced with osPoolCreate.
    [in]blockaddress of the allocated memory block that is returned to the memory pool.
    +
    +
    +
    Returns:
    status code that indicates the execution status of the function.
    +
    Note:
    MUST REMAIN UNCHANGED: osPoolFree shall be consistent in every CMSIS-RTOS.
    +

    Return a memory block to a memory pool.

    +

    Status and Error Codes
    +

    +
      +
    • osOK: the memory block is released.
      • +
    • osErrorValue: block does not belong to the memory pool.
      • +
    • osErrorParameter: a parameter is invalid or outside of a permitted range.
      • +
    + +
    +
    +
    +
    + + + + + diff --git a/Libraries/CMSIS/Documentation/RTOS/html/group___c_m_s_i_s___r_t_o_s___semaphore_mgmt.html b/Libraries/CMSIS/Documentation/RTOS/html/group___c_m_s_i_s___r_t_o_s___semaphore_mgmt.html new file mode 100644 index 0000000..4a46700 --- /dev/null +++ b/Libraries/CMSIS/Documentation/RTOS/html/group___c_m_s_i_s___r_t_o_s___semaphore_mgmt.html @@ -0,0 +1,335 @@ + + + + +Semaphore Management + + + + + + + + + + + + + +
    + +
    + + + + + + + + + + + +
    +
    CMSIS-RTOS +  Version 1.00 +
    +
    CMSIS-RTOS API: Generic RTOS interface for Cortex-M processor-based devices.
    +
    +
    + +
    + +
    + + + +
    +
    + +
    +
    +
    + +
    +
    +
    +Defines | +Functions
    +
    +
    Semaphore Management
    +
    CMSIS-RTOS API
    +
    + +

    Control access to shared resources. +More...

    + + + + + + + + + + + + + + + +

    +Defines

    #define osFeature_Semaphore   30
     maximum count for SemaphoreInit function
    #define osSemaphoreDef(name)   osSemaphoreDef_t os_semaphore_def_##name = { 0 }
     Define a Semaphore object.
    #define osSemaphore(name)   &os_semaphore_def_##name
     Access a Semaphore definition.

    +Functions

    osSemaphoreId osSemaphoreCreate (osSemaphoreDef_t *semaphore_def, int32_t count)
     Create and Initialize a Semaphore object used for managing resources.
    int32_t osSemaphoreWait (osSemaphoreId semaphore_id, uint32_t millisec)
     Wait until a Semaphore token becomes available.
    osStatus osSemaphoreRelease (osSemaphoreId semaphore_id)
     Release a Semaphore token.
    +

    Description

    +

    The Semaphore Management function group is used to manage and protect access to shared resources. For example, with a Semaphore the access to a group of identical peripherals can be managed. The number of available resources is specified as parameter of the osSemaphoreCreate function.

    +

    Each time a Semaphore token is obtained with osSemaphoreWait the semaphore count is decremented. When the semaphore count is 0, no Semaphore token can be obtained. Semaphores are released with osSemaphoreRelease; this function increments the semaphore count.

    +
    +Semaphore.png +
    +CMSIS-RTOS Semaphore
    +

    Define Documentation

    + +
    +
    + + + + +
    #define osFeature_Semaphore   30
    +
    +
    +

    A CMSIS-RTOS implementation may support semaphores. The value osFeature_Semaphore indicates the maximum index count for a semaphore.

    + +
    +
    + +
    +
    + + + + + + + + +
    #define osSemaphore( name)   &os_semaphore_def_##name
    +
    +
    +

    Access to semaphore object for the functions osSemaphoreCreate.

    +
    Parameters:
    + + +
    namename of the semaphore object.
    +
    +
    +
    Note:
    CAN BE CHANGED: The parameter to osSemaphore shall be consistent but the macro body is implementation specific in every CMSIS-RTOS.
    + +
    +
    + +
    +
    + + + + + + + + +
    #define osSemaphoreDef( name)   osSemaphoreDef_t os_semaphore_def_##name = { 0 }
    +
    +
    +

    Define a semaphore object that is referenced by osSemaphore.

    +
    Parameters:
    + + +
    namename of the semaphore object.
    +
    +
    +
    Note:
    CAN BE CHANGED: The parameter to osSemaphoreDef shall be consistent but the macro body is implementation specific in every CMSIS-RTOS.
    + +
    +
    +

    Function Documentation

    + +
    +
    + + + + + + + + + + + + + + + + + + +
    osSemaphoreId osSemaphoreCreate (osSemaphoreDef_t * semaphore_def,
    int32_t count 
    )
    +
    +
    +
    Parameters:
    + + + +
    [in]semaphore_defsemaphore definition referenced with osSemaphore.
    [in]countnumber of available resources.
    +
    +
    +
    Returns:
    semaphore ID for reference by other functions or NULL in case of error.
    +
    Note:
    MUST REMAIN UNCHANGED: osSemaphoreCreate shall be consistent in every CMSIS-RTOS.
    +

    Create and initialize a Semaphore object that is used to manage access to shared resources. The parameter count specifies the number of available resources. The count value 1 creates a binary semaphore.

    + +
    +
    + +
    +
    + + + + + + + + +
    osStatus osSemaphoreRelease (osSemaphoreId semaphore_id)
    +
    +
    +
    Parameters:
    + + +
    [in]semaphore_idsemaphore object referenced with osSemaphore.
    +
    +
    +
    Returns:
    status code that indicates the execution status of the function.
    +
    Note:
    MUST REMAIN UNCHANGED: osSemaphoreRelease shall be consistent in every CMSIS-RTOS.
    +

    Release a Semaphore token. This increments the count of avaiable semaphore tokens.

    +
    Note:
    osSemaphoreRelease can be called also from interrupt service routines.
    +

    Status and Error Codes
    +

    +
      +
    • osOK: the semaphore has been released.
      • +
    • osErrorResource: all tokens have already been released.
      • +
    • osErrorParameter: the parameter semaphore_id is incorrect.
      • +
    + +
    +
    + +
    +
    + + + + + + + + + + + + + + + + + + +
    int32_t osSemaphoreWait (osSemaphoreId semaphore_id,
    uint32_t millisec 
    )
    +
    +
    +
    Parameters:
    + + + +
    [in]semaphore_idsemaphore object referenced with osSemaphore.
    [in]millisectimeout value or 0 in case of no time-out.
    +
    +
    +
    Returns:
    number of available tokens, or -1 in case of incorrect parameters.
    +
    Note:
    MUST REMAIN UNCHANGED: osSemaphoreWait shall be consistent in every CMSIS-RTOS.
    +

    Wait until a Semaphore token becomes available. When no Semaphore token is available, the function waits for the time specified with the parameter millisec. When millisec is set to osWaitForever, the function will wait for an infinite time until a Semaphore token becomes available. The return value indicates the number of available tokens (the semaphore count value). If 0 is returned, then no semaphore was available.

    + +
    +
    +
    +
    + + + + + diff --git a/Libraries/CMSIS/Documentation/RTOS/html/group___c_m_s_i_s___r_t_o_s___signal_mgmt.html b/Libraries/CMSIS/Documentation/RTOS/html/group___c_m_s_i_s___r_t_o_s___signal_mgmt.html new file mode 100644 index 0000000..7c519ba --- /dev/null +++ b/Libraries/CMSIS/Documentation/RTOS/html/group___c_m_s_i_s___r_t_o_s___signal_mgmt.html @@ -0,0 +1,317 @@ + + + + +Signal Management + + + + + + + + + + + + + +
    + +
    + + + + + + + + + + + +
    +
    CMSIS-RTOS +  Version 1.00 +
    +
    CMSIS-RTOS API: Generic RTOS interface for Cortex-M processor-based devices.
    +
    +
    + +
    + +
    + + + +
    +
    + +
    +
    +
    + +
    +
    +
    +Defines | +Functions
    +
    +
    Signal Management
    +
    CMSIS-RTOS API
    +
    + +

    Control or wait for signal flags. +More...

    + + + + + + + + + + + + + +

    +Defines

    #define osFeature_Signals   8
     maximum number of Signal Flags available per thread

    +Functions

    int32_t osSignalSet (osThreadId thread_id, int32_t signal)
     Set the specified Signal Flags of an active thread.
    int32_t osSignalClear (osThreadId thread_id, int32_t signal)
     Clear the specified Signal Flags of an active thread.
    int32_t osSignalGet (osThreadId thread_id)
     Get Signal Flags status of an active thread.
    osEvent osSignalWait (int32_t signals, uint32_t millisec)
     Wait for one or more Signal Flags to become signaled for the current RUNNING thread.
    +

    Description

    +

    The Signal Management function group allows to control or wait signal flags. Each thread has assigned signal flags.

    +

    Define Documentation

    + +
    +
    + + + + +
    #define osFeature_Signals   8
    +
    +
    +

    The CMSIS-RTOS API may support a variable number of signal flags. This define specifies the number of signal flags available per thread. The maximum value is 31 signal flags per thread.

    + +
    +
    +

    Function Documentation

    + +
    +
    + + + + + + + + + + + + + + + + + + +
    int32_t osSignalClear (osThreadId thread_id,
    int32_t signals 
    )
    +
    +
    +
    Parameters:
    + + + +
    [in]thread_idthread ID obtained by osThreadCreate or osThreadGetId.
    [in]signalsspecifies the signal flags of the thread that shall be cleared.
    +
    +
    +
    Returns:
    previous signal flags of the specified thread or 0x80000000 in case of incorrect parameters.
    +
    Note:
    MUST REMAIN UNCHANGED: osSignalClear shall be consistent in every CMSIS-RTOS.
    +

    Clear the signal flags of an active thread. This function may be used also within interrupt service routines.

    + +
    +
    + +
    +
    + + + + + + + + +
    int32_t osSignalGet (osThreadId thread_id)
    +
    +
    +
    Parameters:
    + + +
    [in]thread_idthread ID obtained by osThreadCreate or osThreadGetId.
    +
    +
    +
    Returns:
    previous signal flags of the specified thread or 0x80000000 in case of incorrect parameters.
    +
    Note:
    MUST REMAIN UNCHANGED: osSignalGet shall be consistent in every CMSIS-RTOS.
    +

    Return the event flags of an active thread. This function may be used also within interrupt service routines. Signal flags that are returned are automatically cleared.

    + +
    +
    + +
    +
    + + + + + + + + + + + + + + + + + + +
    int32_t osSignalSet (osThreadId thread_id,
    int32_t signals 
    )
    +
    +
    +
    Parameters:
    + + + +
    [in]thread_idthread ID obtained by osThreadCreate or osThreadGetId.
    [in]signalsspecifies the signal flags of the thread that should be set.
    +
    +
    +
    Returns:
    previous signal flags of the specified thread or 0x80000000 in case of incorrect parameters.
    +
    Note:
    MUST REMAIN UNCHANGED: osSignalSet shall be consistent in every CMSIS-RTOS.
    +

    Set the signal flags of an active thread. This function may be used also within interrupt service routines.

    + +
    +
    + +
    +
    + + + + + + + + + + + + + + + + + + +
    osEvent osSignalWait (int32_t signals,
    uint32_t millisec 
    )
    +
    +
    +
    Parameters:
    + + + +
    [in]signalswait until all specified signal flags set or 0 for any single signal flag.
    [in]millisectimeout value or 0 in case of no time-out.
    +
    +
    +
    Returns:
    event flag information or error code.
    +
    Note:
    MUST REMAIN UNCHANGED: osSignalWait shall be consistent in every CMSIS-RTOS.
    +

    Suspend the execution of the current RUNNING thread until all specified signal flags with the parameter signals are set. When this signal flags are already set, the function returns instantly. Otherwise the thread is put into the state WAITING. Signal flags that are reported as event are automatically cleared.

    +

    When millisec is set to osWaitForever the function will wait for an inifinite time until a message queue slot becomes available.

    +

    Status and Error Codes
    +

    +
      +
    • osOK: no signal received when the timeout value millisec was zero.
      • +
    • osEventTimeout: signal not occurred within timeout
      • +
    • osEventSignal: signal occurred, value.signals contains the signal flags; these signal flags are cleared.
      • +
    • osErrorValue: the value signals is outside of the permitted range.
      • +
    • osErrorISR: osSignalWait cannot be called from interrupt service routines.
      • +
    + +
    +
    +
    +
    + + + + + diff --git a/Libraries/CMSIS/Documentation/RTOS/html/group___c_m_s_i_s___r_t_o_s___status.html b/Libraries/CMSIS/Documentation/RTOS/html/group___c_m_s_i_s___r_t_o_s___status.html new file mode 100644 index 0000000..5923c83 --- /dev/null +++ b/Libraries/CMSIS/Documentation/RTOS/html/group___c_m_s_i_s___r_t_o_s___status.html @@ -0,0 +1,238 @@ + + + + +Status and Error Codes + + + + + + + + + + + + + +
    + +
    + + + + + + + + + + + +
    +
    CMSIS-RTOS +  Version 1.00 +
    +
    CMSIS-RTOS API: Generic RTOS interface for Cortex-M processor-based devices.
    +
    +
    + +
    + +
    + + + +
    +
    + +
    +
    +
    + +
    +
    +
    +Enumerations
    +
    +
    Status and Error Codes
    +
    CMSIS-RTOS API
    +
    + +

    Status and Error Codes returned by CMSIS-RTOS API functions. +More...

    + + + +

    +Enumerations

    enum  osStatus {
    +  osOK = 0, +
    +  osEventSignal = 0x08, +
    +  osEventMessage = 0x10, +
    +  osEventMail = 0x20, +
    +  osEventTimeout = 0x40, +
    +  osErrorParameter = 0x80, +
    +  osErrorResource = 0x81, +
    +  osErrorTimeoutResource = 0xC1, +
    +  osErrorISR = 0x82, +
    +  osErrorISRRecursive = 0x83, +
    +  osErrorPriority = 0x84, +
    +  osErrorNoMemory = 0x85, +
    +  osErrorValue = 0x86, +
    +  osErrorOS = 0xFF, +
    +  os_status_reserved = 0x7FFFFFFF +
    + }
    +

    Description

    +

    The Status and Error Codes section lists all the return values that the CMSIS-RTOS functions will return.

    +

    Enumeration Type Documentation

    + +
    +
    + + + + +
    enum osStatus
    +
    +
    +
    Note:
    MUST REMAIN UNCHANGED: osStatus shall be consistent in every CMSIS-RTOS.
    +

    The osStatus enumeration defines the event status and error codes that are returned by the CMSIS-RTOS functions.

    +
    Enumerator:
    + + + + + + + + + + + + + + + +
    osOK  +

    function completed; no event occurred.

    +
    osEventSignal  +

    function completed; signal event occurred.

    +
    osEventMessage  +

    function completed; message event occurred.

    +
    osEventMail  +

    function completed; mail event occurred.

    +
    osEventTimeout  +

    function completed; timeout occurred.

    +
    osErrorParameter  +

    parameter error: a mandatory parameter was missing or specified an incorrect object.

    +
    osErrorResource  +

    resource not available: a specified resource was not available.

    +
    osErrorTimeoutResource  +

    resource not available within given time: a specified resource was not available within the timeout period.

    +
    osErrorISR  +

    not allowed in ISR context: the function cannot be called from interrupt service routines.

    +
    osErrorISRRecursive  +

    function called multiple times from ISR with same object.

    +
    osErrorPriority  +

    system cannot determine priority or thread has illegal priority.

    +
    osErrorNoMemory  +

    system is out of memory: it was impossible to allocate or reserve memory for the operation.

    +
    osErrorValue  +

    value of a parameter is out of range.

    +
    osErrorOS  +

    unspecified RTOS error: run-time error but no other error message fits.

    +
    os_status_reserved  +

    prevent from enum down-size compiler optimization.

    +
    +
    +
    + +
    +
    +
    +
    + + + + + diff --git a/Libraries/CMSIS/Documentation/RTOS/html/group___c_m_s_i_s___r_t_o_s___thread_mgmt.html b/Libraries/CMSIS/Documentation/RTOS/html/group___c_m_s_i_s___r_t_o_s___thread_mgmt.html new file mode 100644 index 0000000..205640f --- /dev/null +++ b/Libraries/CMSIS/Documentation/RTOS/html/group___c_m_s_i_s___r_t_o_s___thread_mgmt.html @@ -0,0 +1,511 @@ + + + + +Thread Management + + + + + + + + + + + + + +
    + +
    + + + + + + + + + + + +
    +
    CMSIS-RTOS +  Version 1.00 +
    +
    CMSIS-RTOS API: Generic RTOS interface for Cortex-M processor-based devices.
    +
    +
    + +
    + +
    + + + +
    +
    + +
    +
    +
    + +
    +
    +
    +Defines | +Enumerations | +Functions
    +
    +
    Thread Management
    +
    CMSIS-RTOS API
    +
    + +

    Define, create, and control thread functions. +More...

    + + + + + + + + + + + + + + + + + + + + + +

    +Defines

    #define osThreadDef(name, priority, instances, stacksz)
     Create a Thread Definition with function, priority, and stack requirements.
    #define osThread(name)   &os_thread_def_##name
     Access a Thread defintion.

    +Enumerations

    enum  osPriority {
    +  osPriorityIdle = -3, +
    +  osPriorityLow = -2, +
    +  osPriorityBelowNormal = -1, +
    +  osPriorityNormal = 0, +
    +  osPriorityAboveNormal = +1, +
    +  osPriorityHigh = +2, +
    +  osPriorityRealtime = +3, +
    +  osPriorityError = 0x84 +
    + }

    +Functions

    osThreadId osThreadCreate (osThreadDef_t *thread_def, void *argument)
     Create a thread and add it to Active Threads and set it to state READY.
    osThreadId osThreadGetId (void)
     Return the thread ID of the current running thread.
    osStatus osThreadTerminate (osThreadId thread_id)
     Terminate execution of a thread and remove it from Active Threads.
    osStatus osThreadSetPriority (osThreadId thread_id, osPriority priority)
     Change priority of an active thread.
    osPriority osThreadGetPriority (osThreadId thread_id)
     Get current priority of an active thread.
    osStatus osThreadYield (void)
     Pass control to next thread that is in state READY.
    +

    Description

    +

    The Thread Management function group allow defining, creating, and controlling thread functions in the system. The function main is a special thread function that is started at system initialization and has the initial priority osPriorityNormal.

    +

    Threads can be in the following states:

    +
      +
    • RUNNING: The thread that is currently running is in the RUNNING state. Only one thread at a time can be in this state.
      • +
    • READY: Threads which are ready to run are in the READY state. Once the RUNNING thread has terminated or is WAITING the next READY thread with the highest priority becomes the RUNNING thread.
      • +
    • WAITING: Threads that are waiting for an event to occur are in the WAITING state.
      • +
    • INACTIVE: Threads that are not created or terminated are in the INACTIVE state. These threads typically consume no system resources.
      • +
    +
    +ThreadStatus.png +
    +Thread State and State Transitions
    +

    The CMSIS-RTOS assumes that threads are scheduled as shown in the figure Thread State and State Transitions. The thread states change as described below:

    +
      +
    • A thread is created using the function osThreadCreate. This puts the thread into the READY or RUNNING state (depending on the thread priority).
      • +
    • CMSIS-RTOS is pre-emptive. The active thread with the highest priority becomes the RUNNING thread provided it does not wait for any event. The initial priority of a thread is defined with the osThreadDef but may be changed during execution using the function osThreadSetPriority.
      • +
    • The RUNNING thread transfers into the WAITING state when it is waiting for an event.
      • +
    • Active threads can be terminated any time using the function osThreadTerminate. Threads can terminate also by just returning from the thread function. Threads that are terminated are in the INACTIVE state and typically do not consume any dynamic memory resources.
      • +
    +

    Define Documentation

    + +
    +
    + + + + + + + + +
    #define osThread( name)   &os_thread_def_##name
    +
    +
    +

    Access to the thread definition for the function osThreadCreate.

    +
    Parameters:
    + + +
    namename of the thread definition object.
    +
    +
    +
    Note:
    CAN BE CHANGED: The parameter to osThread shall be consistent but the macro body is implementation specific in every CMSIS-RTOS.
    + +
    +
    + +
    +
    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    #define osThreadDef( name,
     priority,
     instances,
     stacksz 
    )
    +
    +
    +

    Define the attributes of a thread functions that can be created by the function osThreadCreate using osThread.

    +
    Parameters:
    + + + + + +
    namename of the thread function.
    priorityinitial priority of the thread function.
    instancesnumber of possible thread instances.
    stackszstack size (in bytes) requirements for the thread function.
    +
    +
    +
    Note:
    CAN BE CHANGED: The parameters to osThreadDef shall be consistent but the macro body is implementation specific in every CMSIS-RTOS.
    + +
    +
    +

    Enumeration Type Documentation

    + +
    +
    + + + + +
    enum osPriority
    +
    +
    +
    Note:
    MUST REMAIN UNCHANGED: osPriority shall be consistent in every CMSIS-RTOS.
    +

    The osPriority value specifies the priority for a thread. The default thread priority should be osPriorityNormal. If a Thread is active that has a higher priority than the currently executing thread, then a thread switch occurs immediately to execute the new task.

    +

    To prevent from a priority inversion, a CMSIS-RTOS complained OS may optionally implement a priority inheritance method. A priority inversion occurs when a high priority thread is waiting for a resource or event that is controlled by a thread with a lower priority.

    +
    Enumerator:
    + + + + + + + + +
    osPriorityIdle  +

    priority: idle (lowest)

    +
    osPriorityLow  +

    priority: low

    +
    osPriorityBelowNormal  +

    priority: below normal

    +
    osPriorityNormal  +

    priority: normal (default)

    +
    osPriorityAboveNormal  +

    priority: above normal

    +
    osPriorityHigh  +

    priority: high

    +
    osPriorityRealtime  +

    priority: realtime (highest)

    +
    osPriorityError  +

    system cannot determine priority or thread has illegal priority

    +
    +
    +
    + +
    +
    +

    Function Documentation

    + +
    +
    + + + + + + + + + + + + + + + + + + +
    osThreadId osThreadCreate (osThreadDef_t * thread_def,
    void * argument 
    )
    +
    +
    +
    Parameters:
    + + + +
    [in]thread_defthread definition referenced with osThread.
    [in]argumentpointer that is passed to the thread function as start argument.
    +
    +
    +
    Returns:
    thread ID for reference by other functions or NULL in case of error.
    +
    Note:
    MUST REMAIN UNCHANGED: osThreadCreate shall be consistent in every CMSIS-RTOS.
    +

    Start a thread function by adding it to the Active Threads list and set it to state READY. The thread function receives the argument pointer as function argument when the function is started. When the priority of the created thread function is higher than the current RUNNING thread, the created thread function starts instantly and becomes the new RUNNING thread.

    + +
    +
    + +
    +
    + + + + + + + + +
    osThreadId osThreadGetId (void )
    +
    +
    +
    Returns:
    thread ID for reference by other functions or NULL in case of error.
    +
    Note:
    MUST REMAIN UNCHANGED: osThreadGetId shall be consistent in every CMSIS-RTOS.
    +

    Get the thread ID of the current running thread.

    + +
    +
    + +
    +
    + + + + + + + + +
    osPriority osThreadGetPriority (osThreadId thread_id)
    +
    +
    +
    Parameters:
    + + +
    [in]thread_idthread ID obtained by osThreadCreate or osThreadGetId.
    +
    +
    +
    Returns:
    current priority value of the thread function.
    +
    Note:
    MUST REMAIN UNCHANGED: osThreadGetPriority shall be consistent in every CMSIS-RTOS.
    +

    Get the priority of an active thread. In case of a failure the value osPriorityError is returned.

    + +
    +
    + +
    +
    + + + + + + + + + + + + + + + + + + +
    osStatus osThreadSetPriority (osThreadId thread_id,
    osPriority priority 
    )
    +
    +
    +
    Parameters:
    + + + +
    [in]thread_idthread ID obtained by osThreadCreate or osThreadGetId.
    [in]prioritynew priority value for the thread function.
    +
    +
    +
    Returns:
    status code that indicates the execution status of the function.
    +
    Note:
    MUST REMAIN UNCHANGED: osThreadSetPriority shall be consistent in every CMSIS-RTOS.
    +

    Change the priority of an active thread.

    +

    Status and Error Codes
    +

    +
      +
    • osOK: the prioirty of the specified thread has been successfully changed.
      • +
    • osErrorParameter: thread_id is incorrect.
      • +
    • osErrorValue: incorrect priority value.
      • +
    • osErrorResource: thread_id refers to a thread that is not an active thread.
      • +
    • osErrorISR: osThreadSetPriority cannot be called from interrupt service routines.
      • +
    + +
    +
    + +
    +
    + + + + + + + + +
    osStatus osThreadTerminate (osThreadId thread_id)
    +
    +
    +
    Parameters:
    + + +
    [in]thread_idthread ID obtained by osThreadCreate or osThreadGetId.
    +
    +
    +
    Returns:
    status code that indicates the execution status of the function.
    +
    Note:
    MUST REMAIN UNCHANGED: osThreadTerminate shall be consistent in every CMSIS-RTOS.
    +

    Remove the thread function from the active thread list. If the thread is currently RUNNING the execution will stop.

    +
    Note:
    In case that osThreadTerminate terminates the currently running task, the function never returns and other threads that are in the READY state are started.
    +

    Status and Error Codes
    +

    +
      +
    • osOK: the specified thread has been successfully terminated.
      • +
    • osErrorParameter: thread_id is incorrect.
      • +
    • osErrorResource: thread_id refers to a thread that is not an active thread.
      • +
    • osErrorISR: osThreadTerminate cannot be called from interrupt service routines.
      • +
    + +
    +
    + +
    +
    + + + + + + + + +
    osStatus osThreadYield (void )
    +
    +
    +
    Returns:
    status code that indicates the execution status of the function.
    +
    Note:
    MUST REMAIN UNCHANGED: osThreadYield shall be consistent in every CMSIS-RTOS.
    +

    Pass control to next thread that is in state READY. If there is no other thread in the state READY, the current thread continues execution and no thread switching occurs.

    +

    Status and Error Codes
    +

    +
      +
    • osOK: the function has been correctly executed.
      • +
    • osErrorISR: osThreadYield cannot be called from interrupt service routines.
      • +
    + +
    +
    +
    +
    + + + + + diff --git a/Libraries/CMSIS/Documentation/RTOS/html/group___c_m_s_i_s___r_t_o_s___timer_mgmt.html b/Libraries/CMSIS/Documentation/RTOS/html/group___c_m_s_i_s___r_t_o_s___timer_mgmt.html new file mode 100644 index 0000000..f2fee9b --- /dev/null +++ b/Libraries/CMSIS/Documentation/RTOS/html/group___c_m_s_i_s___r_t_o_s___timer_mgmt.html @@ -0,0 +1,377 @@ + + + + +Timer Management + + + + + + + + + + + + + +
    + +
    + + + + + + + + + + + +
    +
    CMSIS-RTOS +  Version 1.00 +
    +
    CMSIS-RTOS API: Generic RTOS interface for Cortex-M processor-based devices.
    +
    +
    + +
    + +
    + + + +
    +
    + +
    +
    +
    + +
    +
    +
    +Defines | +Enumerations | +Functions
    +
    +
    Timer Management
    +
    CMSIS-RTOS API
    +
    + +

    Create and control timer and timer callback functions. +More...

    + + + + + + + + + + + + + + + +

    +Defines

    #define osTimerDef(name, function)
     Define a Timer object.
    #define osTimer(name)   &os_timer_def_##name
     Access a Timer definition.

    +Enumerations

    enum  os_timer_type {
    +  osTimerOnce = 0, +
    +  osTimerPeriodic = 1 +
    + }

    +Functions

    osTimerId osTimerCreate (osTimerDef_t *timer_def, os_timer_type type, void *argument)
     Create a timer.
    osStatus osTimerStart (osTimerId timer_id, uint32_t millisec)
     Start or restart a timer.
    osStatus osTimerStop (osTimerId timer_id)
     Stop the timer.
    +

    Description

    +

    The Timer Management function group allow creating and controlling of timers and callback functions in the system. A callback function is called when a time period expires whereby both one-shot and periodic timers are possible. A timer can be started, restarted, or stopped.

    +

    Timers are handled in the thread osTimerThread. Callback functions run under control of this thread and may use other CMSIS-RTOS API calls.

    +

    The figure below shows the behavior of a periodic timer. For one-shot timers, the timer stops after execution of the callback function.

    +
    +Timer.png +
    +Behavior of a Periodic Timer
    +

    Define Documentation

    + +
    +
    + + + + + + + + +
    #define osTimer( name)   &os_timer_def_##name
    +
    +
    +

    Access to the timer definition for the function osTimerCreate.

    +
    Parameters:
    + + +
    namename of the timer object.
    +
    +
    +
    Note:
    CAN BE CHANGED: The parameter to osTimer shall be consistent but the macro body is implementation specific in every CMSIS-RTOS.
    + +
    +
    + +
    +
    + + + + + + + + + + + + + + + + + + +
    #define osTimerDef( name,
     function 
    )
    +
    +
    +

    Define the attributes of a timer.

    +
    Parameters:
    + + + +
    namename of the timer object.
    functionname of the timer call back function.
    +
    +
    +
    Note:
    CAN BE CHANGED: The parameter to osTimerDef shall be consistent but the macro body is implementation specific in every CMSIS-RTOS.
    + +
    +
    +

    Enumeration Type Documentation

    + +
    +
    + + + + +
    enum os_timer_type
    +
    +
    +
    Note:
    MUST REMAIN UNCHANGED: os_timer_type shall be consistent in every CMSIS-RTOS. The os_timer_type specifies the a repeating (periodic) or one-shot timer for the function osTimerCreate.
    +
    Enumerator:
    + + +
    osTimerOnce  +

    one-shot timer

    +
    osTimerPeriodic  +

    repeating timer

    +
    +
    +
    + +
    +
    +

    Function Documentation

    + +
    +
    + + + + + + + + + + + + + + + + + + + + + + + + +
    osTimerId osTimerCreate (osTimerDef_t * timer_def,
    os_timer_type type,
    void * argument 
    )
    +
    +
    +
    Parameters:
    + + + + +
    [in]timer_deftimer object referenced with osTimer.
    [in]typeosTimerOnce for one-shot or osTimerPeriodic for periodic behavior.
    [in]argumentargument to the timer call back function.
    +
    +
    +
    Returns:
    timer ID for reference by other functions or NULL in case of error.
    +
    Note:
    MUST REMAIN UNCHANGED: osTimerCreate shall be consistent in every CMSIS-RTOS.
    +

    Create a one-shot or periodic timer and associate it with a callback function argument. The timer is in stopped until it is started with osTimerStart.

    + +
    +
    + +
    +
    + + + + + + + + + + + + + + + + + + +
    osStatus osTimerStart (osTimerId timer_id,
    uint32_t millisec 
    )
    +
    +
    +
    Parameters:
    + + + +
    [in]timer_idtimer ID obtained by osTimerCreate.
    [in]millisectime delay value of the timer.
    +
    +
    +
    Returns:
    status code that indicates the execution status of the function.
    +
    Note:
    MUST REMAIN UNCHANGED: osTimerStart shall be consistent in every CMSIS-RTOS.
    +

    Start or restart the timer.

    +

    Status and Error Codes
    +

    +
      +
    • osOK: the specified timer has been started or restarted.
      • +
    • osErrorParameter: timer_id is incorrect.
      • +
    + +
    +
    + +
    +
    + + + + + + + + +
    osStatus osTimerStop (osTimerId timer_id)
    +
    +
    +
    Parameters:
    + + +
    [in]timer_idtimer ID obtained by osTimerCreate.
    +
    +
    +
    Returns:
    status code that indicates the execution status of the function.
    +
    Note:
    MUST REMAIN UNCHANGED: osTimerStop shall be consistent in every CMSIS-RTOS.
    +

    Stop the timer.

    +

    Status and Error Codes
    +

    +
      +
    • osOK: the specified timer has been stopped.
      • +
    • osErrorParameter: timer_id is incorrect.
      • +
    • osErrorResource: the timer is not started.
      • +
    + +
    +
    +
    +
    + + + + + diff --git a/Libraries/CMSIS/Documentation/RTOS/html/group___c_m_s_i_s___r_t_o_s___wait.html b/Libraries/CMSIS/Documentation/RTOS/html/group___c_m_s_i_s___r_t_o_s___wait.html new file mode 100644 index 0000000..100990e --- /dev/null +++ b/Libraries/CMSIS/Documentation/RTOS/html/group___c_m_s_i_s___r_t_o_s___wait.html @@ -0,0 +1,233 @@ + + + + +Generic Wait Functions + + + + + + + + + + + + + +
    + +
    + + + + + + + + + + + +
    +
    CMSIS-RTOS +  Version 1.00 +
    +
    CMSIS-RTOS API: Generic RTOS interface for Cortex-M processor-based devices.
    +
    +
    + +
    + +
    + + + +
    +
    + +
    +
    +
    + +
    +
    +
    +Defines | +Functions
    +
    +
    Generic Wait Functions
    +
    CMSIS-RTOS API
    +
    + +

    Wait for a time period or unspecified events. +More...

    + + + + + + + + + +

    +Defines

    #define osFeature_Wait   1
     osWait function: 1=available, 0=not available

    +Functions

    osStatus osDelay (uint32_t millisec)
     Wait for Timeout (Time Delay)
    osEvent osWait (uint32_t millisec)
     Wait for Signal, Message, Mail, or Timeout.
    +

    Description

    +

    The Generic Wait function group provides means for a time delay and allow to wait for unspecified events.

    +

    Define Documentation

    + +
    +
    + + + + +
    #define osFeature_Wait   1
    +
    +
    +

    A CMSIS-RTOS implementation may support the generic wait function osWait. When the value osFeature_Wait is 1 a generic wait function osWait is available. When the value osFeature_Wait is 0 no generic wait function osWait is available.

    + +
    +
    +

    Function Documentation

    + +
    +
    + + + + + + + + +
    osStatus osDelay (uint32_t millisec)
    +
    +
    +
    Parameters:
    + + +
    [in]millisectime delay value
    +
    +
    +
    Returns:
    status code that indicates the execution status of the function.
    +

    Wait for a specified time period in millisec.

    +

    Status and Error Codes
    +

    +
      +
    • osEventTimeout: the time delay is executed.
      • +
    • osErrorISR: osDelay cannot be called from interrupt service routines.
      • +
    + +
    +
    + +
    +
    + + + + + + + + +
    osStatus osWait (uint32_t millisec)
    +
    +
    +
    Parameters:
    + + +
    [in]millisectimeout value or 0 in case of no time-out
    +
    +
    +
    Returns:
    event that contains signal, message, or mail information or error code.
    +
    Note:
    MUST REMAIN UNCHANGED: osWait shall be consistent in every CMSIS-RTOS.
    +

    Wait for any event of the type Signal, Message, Mail for a specified time period in millisec. When millisec is set to osWaitForever the function will wait for an infinite time until a event occurs.

    +
    Note:
    this function is optionally and may not be provided by all CMSIS-RTOS implementations.
    +

    Status and Error Codes
    +

    +
      +
    • osEventSignal: a signal event occurred and is returned.
      • +
    • osEventMessage: a message event occurred and is returned.
      • +
    • osEventMail: a mail event occurred and is returned.
      • +
    • osEventTimeout: the time delay is executed.
      • +
    • osErrorISR: osDelay cannot be called from interrupt service routines.
      • +
    + +
    +
    +
    +
    + + + + + diff --git a/Libraries/CMSIS/Documentation/RTOS/html/index.html b/Libraries/CMSIS/Documentation/RTOS/html/index.html new file mode 100644 index 0000000..8225cd5 --- /dev/null +++ b/Libraries/CMSIS/Documentation/RTOS/html/index.html @@ -0,0 +1,199 @@ + + + + +Overview + + + + + + + + + + + + + +
    + +
    + + + + + + + + + + + +
    +
    CMSIS-RTOS +  Version 1.00 +
    +
    CMSIS-RTOS API: Generic RTOS interface for Cortex-M processor-based devices.
    +
    +
    + +
    + +
    + + + +
    +
    + +
    +
    +
    + +
    +
    +
    +
    Overview
    +
    +
    +

    The CMSIS-RTOS API is a generic RTOS interface for Cortex-M processor-based devices. CMSIS-RTOS provides a standardized API for software components that require RTOS functionality and gives therefore serious benefits to the users and the software industry.

    +
      +
    • CMSIS-RTOS provides basic features that are required in many applications or technologies such as UML or Java (JVM).
      • +
    • The unified feature set of the CMSIS-RTOS API simplifies sharing of software components and reduces learning efforts.
      • +
    • Middleware components that use the CMSIS-RTOS API are RTOS agnostic. CMSIS-RTOS compliant middleware is easier to adapt.
      • +
    • Standard project templates (such as motor control) of the CMSIS-RTOS API may be shipped with freely available CMSIS-RTOS implementations.
      • +
    +
    Note:
    The CMSIS-RTOS API defines a minimum feature set. Implementations with extended features may be provided by RTOS vendors.
    +
    +API_Structure.png +
    +CMSIS-RTOS API Structure
    +

    A typical CMSIS-RTOS API implementation interfaces to an existing Real-Time Kernel. The CMSIS-RTOS API provides the following attributes and functionalities:

    +
      +
    • Function names, identifiers, and parameters are descriptive and easy to understand. The functions are powerful and flexible which reduces the number of functions exposed to the user.
      • +
    + +
      +
    • Interrupt Service Routines (ISR) can call many CMSIS-RTOS functions. When a CMSIS-RTOS function cannot be called from ISR context, it rejects the invocation.
      • +
    +
      +
    • Three different thread event types support communication between multiple threads and/or ISR:
        +
      • Signals: are flags that may be used to signal specific conditions to a thread. Signals can be modified in an ISR or set from other threads.
        • +
      • Message: is a 32-bit value that can be sent to a thread or an ISR. Messages are buffered in a queue. The message type and queue size is defined in a descriptor.
        • +
      • Mail: is a fixed-size memory block that can be sent to a thread or an ISR. Mails are buffered in a queue and memory allocation is provided. The mail type and queue size is defined in a descriptor.
        • +
      +
      • +
    + +
      +
    • CPU time can be schedule with the following functionalities:
        +
      • A timeout parameter is incorporated in many CMSIS-RTOS functions to avoid system lockup. When a timeout is specified, the system waits until a resource is available or an event occurs. While waiting, other threads are scheduled.
        • +
      • The osDelay function puts a thread into the state WAITING for a specified period of time.
        • +
      • The generic osWait function waits for events that are assigned to a thread.
        • +
      • The osThreadYield provides co-operative thread switching and passes execution to another thread of the same priority.
        • +
      +
      • +
    +

    The CMSIS-RTOS API is designed to optionally incorporate multi-processor systems and/or access protection via the Cortex-M Memory Protection Unit (MPU).

    +

    In some RTOS implementations threads may execute on different processors and Mail and Message queues can therefore reside in shard memory resources.

    +

    The CMSIS-RTOS API encourages the software industry to evolve existing RTOS implementations. Kernel objects are defined and accessed using macros. This allows differentiation. RTOS implementations can be different and optimized in various aspects towards the Cortex-M processors. Optional features may be for example:

    +
      +
    • Generic Wait function; i.e. with support of time intervals.
      • +
    • Support of the Cortex-M Memory Protection Unit (MPU).
      • +
    • Zero-copy mail queue.
      • +
    • Support of multi-processor systems.
      • +
    • Support of a DMA controller.
      • +
    • Deterministic context switching.
      • +
    • Round-robin context switching.
      • +
    • Deadlock avoidance, for example with priority inversion.
      • +
    • Zero interrupt latency by using the Cortex-M3/M4 instructions LDEX and STEX.
      • +
    +
    +

    Revision History of CMSIS-RTOS API

    + + + + + + + +
    Version Description
    V0.02 Preview Release.
    V0.03 Added: osKernelStart; starting 'main' as a thread is now an optional feature.
    + Semaphores have now the standard behavior.
    + osTimerCreate does no longer start the timer. Added: osTimerStart (replaces osTimerRestart).
    + Changed: osThreadPass is renamed to osThreadYield.
    +
    +
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i=this.className.match(/ui-resizable-(se|sw|ne|nw|n|e|s|w)/i)}e.axis=i&&i[1]?i[1]:"se"}});if(j.autoHide){this._handles.hide();c(this.element).addClass("ui-resizable-autohide").hover(function(){c(this).removeClass("ui-resizable-autohide");e._handles.show()},function(){if(!e.resizing){c(this).addClass("ui-resizable-autohide");e._handles.hide()}})}this._mouseInit()},destroy:function(){this._mouseDestroy();var d=function(f){c(f).removeClass("ui-resizable ui-resizable-disabled ui-resizable-resizing").removeData("resizable").unbind(".resizable").find(".ui-resizable-handle").remove()};if(this.elementIsWrapper){d(this.element);var e=this.element;e.parent().append(this.originalElement.css({position:e.css("position"),width:e.outerWidth(),height:e.outerHeight(),top:e.css("top"),left:e.css("left")})).end().remove()}this.originalElement.css("resize",this.originalResizeStyle);d(this.originalElement)},_mouseCapture:function(e){var f=false;for(var d in this.handles){if(c(this.handles[d])[0]==e.target){f=true}}return this.options.disabled||!!f},_mouseStart:function(f){var i=this.options,e=this.element.position(),d=this.element;this.resizing=true;this.documentScroll={top:c(document).scrollTop(),left:c(document).scrollLeft()};if(d.is(".ui-draggable")||(/absolute/).test(d.css("position"))){d.css({position:"absolute",top:e.top,left:e.left})}if(c.browser.opera&&(/relative/).test(d.css("position"))){d.css({position:"relative",top:"auto",left:"auto"})}this._renderProxy();var j=b(this.helper.css("left")),g=b(this.helper.css("top"));if(i.containment){j+=c(i.containment).scrollLeft()||0;g+=c(i.containment).scrollTop()||0}this.offset=this.helper.offset();this.position={left:j,top:g};this.size=this._helper?{width:d.outerWidth(),height:d.outerHeight()}:{width:d.width(),height:d.height()};this.originalSize=this._helper?{width:d.outerWidth(),height:d.outerHeight()}:{width:d.width(),height:d.height()};this.originalPosition={left:j,top:g};this.sizeDiff={width:d.outerWidth()-d.width(),height:d.outerHeight()-d.height()};this.originalMousePosition={left:f.pageX,top:f.pageY};this.aspectRatio=(typeof i.aspectRatio=="number")?i.aspectRatio:((this.originalSize.width/this.originalSize.height)||1);var h=c(".ui-resizable-"+this.axis).css("cursor");c("body").css("cursor",h=="auto"?this.axis+"-resize":h);d.addClass("ui-resizable-resizing");this._propagate("start",f);return true},_mouseDrag:function(d){var g=this.helper,f=this.options,l={},p=this,i=this.originalMousePosition,m=this.axis;var q=(d.pageX-i.left)||0,n=(d.pageY-i.top)||0;var h=this._change[m];if(!h){return false}var k=h.apply(this,[d,q,n]),j=c.browser.msie&&c.browser.version<7,e=this.sizeDiff;if(this._aspectRatio||d.shiftKey){k=this._updateRatio(k,d)}k=this._respectSize(k,d);this._propagate("resize",d);g.css({top:this.position.top+"px",left:this.position.left+"px",width:this.size.width+"px",height:this.size.height+"px"});if(!this._helper&&this._proportionallyResizeElements.length){this._proportionallyResize()}this._updateCache(k);this._trigger("resize",d,this.ui());return false},_mouseStop:function(g){this.resizing=false;var h=this.options,l=this;if(this._helper){var f=this._proportionallyResizeElements,d=f.length&&(/textarea/i).test(f[0].nodeName),e=d&&c.ui.hasScroll(f[0],"left")?0:l.sizeDiff.height,j=d?0:l.sizeDiff.width;var m={width:(l.size.width-j),height:(l.size.height-e)},i=(parseInt(l.element.css("left"),10)+(l.position.left-l.originalPosition.left))||null,k=(parseInt(l.element.css("top"),10)+(l.position.top-l.originalPosition.top))||null;if(!h.animate){this.element.css(c.extend(m,{top:k,left:i}))}l.helper.height(l.size.height);l.helper.width(l.size.width);if(this._helper&&!h.animate){this._proportionallyResize()}}c("body").css("cursor","auto");this.element.removeClass("ui-resizable-resizing");this._propagate("stop",g);if(this._helper){this.helper.remove()}return false},_updateCache:function(d){var e=this.options;this.offset=this.helper.offset();if(a(d.left)){this.position.left=d.left}if(a(d.top)){this.position.top=d.top}if(a(d.height)){this.size.height=d.height}if(a(d.width)){this.size.width=d.width}},_updateRatio:function(g,f){var h=this.options,i=this.position,e=this.size,d=this.axis;if(g.height){g.width=(e.height*this.aspectRatio)}else{if(g.width){g.height=(e.width/this.aspectRatio)}}if(d=="sw"){g.left=i.left+(e.width-g.width);g.top=null}if(d=="nw"){g.top=i.top+(e.height-g.height);g.left=i.left+(e.width-g.width)}return g},_respectSize:function(k,f){var i=this.helper,h=this.options,q=this._aspectRatio||f.shiftKey,p=this.axis,s=a(k.width)&&h.maxWidth&&(h.maxWidthk.width),r=a(k.height)&&h.minHeight&&(h.minHeight>k.height);if(g){k.width=h.minWidth}if(r){k.height=h.minHeight}if(s){k.width=h.maxWidth}if(l){k.height=h.maxHeight}var e=this.originalPosition.left+this.originalSize.width,n=this.position.top+this.size.height;var j=/sw|nw|w/.test(p),d=/nw|ne|n/.test(p);if(g&&j){k.left=e-h.minWidth}if(s&&j){k.left=e-h.maxWidth}if(r&&d){k.top=n-h.minHeight}if(l&&d){k.top=n-h.maxHeight}var m=!k.width&&!k.height;if(m&&!k.left&&k.top){k.top=null}else{if(m&&!k.top&&k.left){k.left=null}}return k},_proportionallyResize:function(){var j=this.options;if(!this._proportionallyResizeElements.length){return}var f=this.helper||this.element;for(var e=0;e');var d=c.browser.msie&&c.browser.version<7,f=(d?1:0),g=(d?2:-1);this.helper.addClass(this._helper).css({width:this.element.outerWidth()+g,height:this.element.outerHeight()+g,position:"absolute",left:this.elementOffset.left-f+"px",top:this.elementOffset.top-f+"px",zIndex:++h.zIndex});this.helper.appendTo("body").disableSelection()}else{this.helper=this.element}},_change:{e:function(f,e,d){return{width:this.originalSize.width+e}},w:function(g,e,d){var i=this.options,f=this.originalSize,h=this.originalPosition;return{left:h.left+e,width:f.width-e}},n:function(g,e,d){var i=this.options,f=this.originalSize,h=this.originalPosition;return{top:h.top+d,height:f.height-d}},s:function(f,e,d){return{height:this.originalSize.height+d}},se:function(f,e,d){return c.extend(this._change.s.apply(this,arguments),this._change.e.apply(this,[f,e,d]))},sw:function(f,e,d){return c.extend(this._change.s.apply(this,arguments),this._change.w.apply(this,[f,e,d]))},ne:function(f,e,d){return c.extend(this._change.n.apply(this,arguments),this._change.e.apply(this,[f,e,d]))},nw:function(f,e,d){return c.extend(this._change.n.apply(this,arguments),this._change.w.apply(this,[f,e,d]))}},_propagate:function(e,d){c.ui.plugin.call(this,e,[d,this.ui()]);(e!="resize"&&this._trigger(e,d,this.ui()))},plugins:{},ui:function(){return{originalElement:this.originalElement,element:this.element,helper:this.helper,position:this.position,size:this.size,originalSize:this.originalSize,originalPosition:this.originalPosition}}}));c.extend(c.ui.resizable,{version:"1.7.2",eventPrefix:"resize",defaults:{alsoResize:false,animate:false,animateDuration:"slow",animateEasing:"swing",aspectRatio:false,autoHide:false,cancel:":input,option",containment:false,delay:0,distance:1,ghost:false,grid:false,handles:"e,s,se",helper:false,maxHeight:null,maxWidth:null,minHeight:10,minWidth:10,zIndex:1000}});c.ui.plugin.add("resizable","alsoResize",{start:function(e,f){var d=c(this).data("resizable"),g=d.options;_store=function(h){c(h).each(function(){c(this).data("resizable-alsoresize",{width:parseInt(c(this).width(),10),height:parseInt(c(this).height(),10),left:parseInt(c(this).css("left"),10),top:parseInt(c(this).css("top"),10)})})};if(typeof(g.alsoResize)=="object"&&!g.alsoResize.parentNode){if(g.alsoResize.length){g.alsoResize=g.alsoResize[0];_store(g.alsoResize)}else{c.each(g.alsoResize,function(h,i){_store(h)})}}else{_store(g.alsoResize)}},resize:function(f,h){var e=c(this).data("resizable"),i=e.options,g=e.originalSize,k=e.originalPosition;var j={height:(e.size.height-g.height)||0,width:(e.size.width-g.width)||0,top:(e.position.top-k.top)||0,left:(e.position.left-k.left)||0},d=function(l,m){c(l).each(function(){var p=c(this),q=c(this).data("resizable-alsoresize"),o={},n=m&&m.length?m:["width","height","top","left"];c.each(n||["width","height","top","left"],function(r,t){var s=(q[t]||0)+(j[t]||0);if(s&&s>=0){o[t]=s||null}});if(/relative/.test(p.css("position"))&&c.browser.opera){e._revertToRelativePosition=true;p.css({position:"absolute",top:"auto",left:"auto"})}p.css(o)})};if(typeof(i.alsoResize)=="object"&&!i.alsoResize.nodeType){c.each(i.alsoResize,function(l,m){d(l,m)})}else{d(i.alsoResize)}},stop:function(e,f){var d=c(this).data("resizable");if(d._revertToRelativePosition&&c.browser.opera){d._revertToRelativePosition=false;el.css({position:"relative"})}c(this).removeData("resizable-alsoresize-start")}});c.ui.plugin.add("resizable","animate",{stop:function(h,m){var n=c(this).data("resizable"),i=n.options;var g=n._proportionallyResizeElements,d=g.length&&(/textarea/i).test(g[0].nodeName),e=d&&c.ui.hasScroll(g[0],"left")?0:n.sizeDiff.height,k=d?0:n.sizeDiff.width;var f={width:(n.size.width-k),height:(n.size.height-e)},j=(parseInt(n.element.css("left"),10)+(n.position.left-n.originalPosition.left))||null,l=(parseInt(n.element.css("top"),10)+(n.position.top-n.originalPosition.top))||null;n.element.animate(c.extend(f,l&&j?{top:l,left:j}:{}),{duration:i.animateDuration,easing:i.animateEasing,step:function(){var o={width:parseInt(n.element.css("width"),10),height:parseInt(n.element.css("height"),10),top:parseInt(n.element.css("top"),10),left:parseInt(n.element.css("left"),10)};if(g&&g.length){c(g[0]).css({width:o.width,height:o.height})}n._updateCache(o);n._propagate("resize",h)}})}});c.ui.plugin.add("resizable","containment",{start:function(e,q){var s=c(this).data("resizable"),i=s.options,k=s.element;var f=i.containment,j=(f instanceof c)?f.get(0):(/parent/.test(f))?k.parent().get(0):f;if(!j){return}s.containerElement=c(j);if(/document/.test(f)||f==document){s.containerOffset={left:0,top:0};s.containerPosition={left:0,top:0};s.parentData={element:c(document),left:0,top:0,width:c(document).width(),height:c(document).height()||document.body.parentNode.scrollHeight}}else{var m=c(j),h=[];c(["Top","Right","Left","Bottom"]).each(function(p,o){h[p]=b(m.css("padding"+o))});s.containerOffset=m.offset();s.containerPosition=m.position();s.containerSize={height:(m.innerHeight()-h[3]),width:(m.innerWidth()-h[1])};var n=s.containerOffset,d=s.containerSize.height,l=s.containerSize.width,g=(c.ui.hasScroll(j,"left")?j.scrollWidth:l),r=(c.ui.hasScroll(j)?j.scrollHeight:d);s.parentData={element:j,left:n.left,top:n.top,width:g,height:r}}},resize:function(f,p){var s=c(this).data("resizable"),h=s.options,e=s.containerSize,n=s.containerOffset,l=s.size,m=s.position,q=s._aspectRatio||f.shiftKey,d={top:0,left:0},g=s.containerElement;if(g[0]!=document&&(/static/).test(g.css("position"))){d=n}if(m.left<(s._helper?n.left:0)){s.size.width=s.size.width+(s._helper?(s.position.left-n.left):(s.position.left-d.left));if(q){s.size.height=s.size.width/h.aspectRatio}s.position.left=h.helper?n.left:0}if(m.top<(s._helper?n.top:0)) +{s.size.height=s.size.height+(s._helper?(s.position.top-n.top):s.position.top);if(q){s.size.width=s.size.height*h.aspectRatio}s.position.top=s._helper?n.top:0}s.offset.left=s.parentData.left+s.position.left;s.offset.top=s.parentData.top+s.position.top;var k=Math.abs((s._helper?s.offset.left-d.left:(s.offset.left-d.left))+s.sizeDiff.width),r=Math.abs((s._helper?s.offset.top-d.top:(s.offset.top-n.top))+s.sizeDiff.height);var j=s.containerElement.get(0)==s.element.parent().get(0),i=/relative|absolute/.test(s.containerElement.css("position"));if(j&&i){k-=s.parentData.left}if(k+s.size.width>=s.parentData.width){s.size.width=s.parentData.width-k;if(q){s.size.height=s.size.width/s.aspectRatio}}if(r+s.size.height>=s.parentData.height){s.size.height=s.parentData.height-r;if(q){s.size.width=s.size.height*s.aspectRatio}}},stop:function(e,m){var p=c(this).data("resizable"),f=p.options,k=p.position,l=p.containerOffset,d=p.containerPosition,g=p.containerElement;var i=c(p.helper),q=i.offset(),n=i.outerWidth()-p.sizeDiff.width,j=i.outerHeight()-p.sizeDiff.height;if(p._helper&&!f.animate&&(/relative/).test(g.css("position"))){c(this).css({left:q.left-d.left-l.left,width:n,height:j})}if(p._helper&&!f.animate&&(/static/).test(g.css("position"))){c(this).css({left:q.left-d.left-l.left,width:n,height:j})}}});c.ui.plugin.add("resizable","ghost",{start:function(f,g){var d=c(this).data("resizable"),h=d.options,e=d.size;d.ghost=d.originalElement.clone();d.ghost.css({opacity:0.25,display:"block",position:"relative",height:e.height,width:e.width,margin:0,left:0,top:0}).addClass("ui-resizable-ghost").addClass(typeof h.ghost=="string"?h.ghost:"");d.ghost.appendTo(d.helper)},resize:function(e,f){var d=c(this).data("resizable"),g=d.options;if(d.ghost){d.ghost.css({position:"relative",height:d.size.height,width:d.size.width})}},stop:function(e,f){var d=c(this).data("resizable"),g=d.options;if(d.ghost&&d.helper){d.helper.get(0).removeChild(d.ghost.get(0))}}});c.ui.plugin.add("resizable","grid",{resize:function(d,l){var n=c(this).data("resizable"),g=n.options,j=n.size,h=n.originalSize,i=n.originalPosition,m=n.axis,k=g._aspectRatio||d.shiftKey;g.grid=typeof g.grid=="number"?[g.grid,g.grid]:g.grid;var f=Math.round((j.width-h.width)/(g.grid[0]||1))*(g.grid[0]||1),e=Math.round((j.height-h.height)/(g.grid[1]||1))*(g.grid[1]||1);if(/^(se|s|e)$/.test(m)){n.size.width=h.width+f;n.size.height=h.height+e}else{if(/^(ne)$/.test(m)){n.size.width=h.width+f;n.size.height=h.height+e;n.position.top=i.top-e}else{if(/^(sw)$/.test(m)){n.size.width=h.width+f;n.size.height=h.height+e;n.position.left=i.left-f}else{n.size.width=h.width+f;n.size.height=h.height+e;n.position.top=i.top-e;n.position.left=i.left-f}}}}});var b=function(d){return parseInt(d,10)||0};var a=function(d){return !isNaN(parseInt(d,10))}})(jQuery);; +/** + * jQuery.ScrollTo - Easy element scrolling using jQuery. + * Copyright (c) 2008 Ariel Flesler - aflesler(at)gmail(dot)com + * Licensed under GPL license (http://www.opensource.org/licenses/gpl-license.php). + * Date: 2/8/2008 + * @author Ariel Flesler + * @version 1.3.2 + */ +;(function($){var o=$.scrollTo=function(a,b,c){o.window().scrollTo(a,b,c)};o.defaults={axis:'y',duration:1};o.window=function(){return $($.browser.safari?'body':'html')};$.fn.scrollTo=function(l,m,n){if(typeof m=='object'){n=m;m=0}n=$.extend({},o.defaults,n);m=m||n.speed||n.duration;n.queue=n.queue&&n.axis.length>1;if(n.queue)m/=2;n.offset=j(n.offset);n.over=j(n.over);return this.each(function(){var a=this,b=$(a),t=l,c,d={},w=b.is('html,body');switch(typeof t){case'number':case'string':if(/^([+-]=)?\d+(px)?$/.test(t)){t=j(t);break}t=$(t,this);case'object':if(t.is||t.style)c=(t=$(t)).offset()}$.each(n.axis.split(''),function(i,f){var P=f=='x'?'Left':'Top',p=P.toLowerCase(),k='scroll'+P,e=a[k],D=f=='x'?'Width':'Height';if(c){d[k]=c[p]+(w?0:e-b.offset()[p]);if(n.margin){d[k]-=parseInt(t.css('margin'+P))||0;d[k]-=parseInt(t.css('border'+P+'Width'))||0}d[k]+=n.offset[p]||0;if(n.over[p])d[k]+=t[D.toLowerCase()]()*n.over[p]}else d[k]=t[p];if(/^\d+$/.test(d[k]))d[k]=d[k]<=0?0:Math.min(d[k],h(D));if(!i&&n.queue){if(e!=d[k])g(n.onAfterFirst);delete d[k]}});g(n.onAfter);function g(a){b.animate(d,m,n.easing,a&&function(){a.call(this,l)})};function h(D){var b=w?$.browser.opera?document.body:document.documentElement:a;return b['scroll'+D]-b['client'+D]}})};function j(a){return typeof a=='object'?a:{top:a,left:a}}})(jQuery); + diff --git a/Libraries/CMSIS/Documentation/RTOS/html/modules.html b/Libraries/CMSIS/Documentation/RTOS/html/modules.html new file mode 100644 index 0000000..d50acf2 --- /dev/null +++ b/Libraries/CMSIS/Documentation/RTOS/html/modules.html @@ -0,0 +1,147 @@ + + + + +Reference + + + + + + + + + + + + + +
    + +
    + + + + + + + + + + + +
    +
    CMSIS-RTOS +  Version 1.00 +
    +
    CMSIS-RTOS API: Generic RTOS interface for Cortex-M processor-based devices.
    +
    +
    + +
    + +
    + + + +
    +
    + +
    +
    +
    + +
    +
    +
    +
    Reference
    +
    +
    +
    Here is a list of all modules:
    +
    +
    + + + + + diff --git a/Libraries/CMSIS/Documentation/RTOS/html/nav_f.png b/Libraries/CMSIS/Documentation/RTOS/html/nav_f.png new file mode 100644 index 0000000000000000000000000000000000000000..1b07a16207e67c95fe2ee17e7016e6d08ac7ac99 GIT binary patch literal 159 zcmeAS@N?(olHy`uVBq!ia0vp^j6iI`!2~2XGqLUlQfZzpjv*C{Z|{2YIT`Y>1X`Eg z-tTbne1`SITM8Q!Pb(<)UFZ(m>wMzvKZQqKM~~GcZ=A7j<~E6K62>ozFS=cD3)mf8 z9WX0+R&m(l9KUsLdTx4?9~({T__KA%`}olPJ^N;y|F^pHgs_K%!rj~{8>RwnWbkzL Kb6Mw<&;$VTdq1fF literal 0 HcmV?d00001 diff --git a/Libraries/CMSIS/Documentation/RTOS/html/nav_h.png b/Libraries/CMSIS/Documentation/RTOS/html/nav_h.png new file mode 100644 index 0000000000000000000000000000000000000000..01f5fa6a596e36bd12c2d6ceff1b0169fda7e699 GIT binary patch literal 97 zcmeAS@N?(olHy`uVBq!ia0vp^j6lr8!2~3AUOE6t1`SUa$B+ufw|6&kG8phMJMJ~w va4>Y+bZ&9QY?(VEUPY_cGd9nQ`um^ZSUyYpAAuKhL7F^W{an^LB{Ts5DmojT literal 0 HcmV?d00001 diff --git a/Libraries/CMSIS/Documentation/RTOS/html/navtree.css b/Libraries/CMSIS/Documentation/RTOS/html/navtree.css new file mode 100644 index 0000000..e46ffcd --- /dev/null +++ b/Libraries/CMSIS/Documentation/RTOS/html/navtree.css @@ -0,0 +1,123 @@ +#nav-tree .children_ul { + margin:0; + padding:4px; +} + +#nav-tree ul { + list-style:none outside none; + margin:0px; + padding:0px; +} + +#nav-tree li { + white-space:nowrap; + margin:0px; + padding:0px; +} + +#nav-tree .plus { + margin:0px; +} + +#nav-tree .selected { + background-image: url('tab_a.png'); + background-repeat:repeat-x; + color: #fff; + text-shadow: 0px 1px 1px rgba(0, 0, 0, 1.0); +} + +#nav-tree img { + margin:0px; + padding:0px; + border:0px; + vertical-align: middle; +} + +#nav-tree a { + text-decoration:none; + padding:0px; + margin:0px; + outline:none; +} + +#nav-tree .label { + margin:0px; + padding:0px; +} + +#nav-tree .label a { + padding:2px; +} + +#nav-tree .selected a { + text-decoration:none; + padding:2px; + margin:0px; + color:#fff; +} + +#nav-tree .children_ul { + margin:0px; + padding:0px; +} + +#nav-tree .item { + margin:0px; + padding:0px; +} + +#nav-tree { + padding: 0px 0px; + background-color: #FAFAFF; + font-size:14px; + overflow:auto; +} + +#doc-content { + overflow:auto; + display:block; + padding:0px; + margin:0px; +} + +#side-nav { + padding:0 6px 0 0; + margin: 0px; + display:block; + position: absolute; + left: 0px; + width: 300px; +} + +.ui-resizable .ui-resizable-handle { + display:block; +} + +.ui-resizable-e { + background:url("ftv2splitbar.png") repeat scroll right center transparent; + cursor:e-resize; + height:100%; + right:0; + top:0; + width:6px; +} + +.ui-resizable-handle { + display:none; + font-size:0.1px; + position:absolute; + z-index:1; +} + +#nav-tree-contents { + margin: 6px 0px 0px 0px; +} + +#nav-tree { + background-image:url('nav_h.png'); + background-repeat:repeat-x; + background-color: #F9FAFC; +} + + + diff --git a/Libraries/CMSIS/Documentation/RTOS/html/navtree.js b/Libraries/CMSIS/Documentation/RTOS/html/navtree.js new file mode 100644 index 0000000..90d2882 --- /dev/null +++ b/Libraries/CMSIS/Documentation/RTOS/html/navtree.js @@ -0,0 +1,290 @@ +var NAVTREE = +[ + [ "CMSIS-RTOS", "index.html", [ + [ "Overview", "index.html", null ], + [ "Usage and Description", "pages.html", [ + [ "Using a CMSIS RTOS Implementation", "_using_o_s.html", null ], + [ "Function Overview", "_function_overview.html", null ], + [ "Header File Template: cmsis_os.h", "cmsis_os_h.html", null ] + ] ], + [ "Reference", "modules.html", [ + [ "CMSIS-RTOS API", "group___c_m_s_i_s___r_t_o_s.html", [ + [ "Kernel Information and Control", "group___c_m_s_i_s___r_t_o_s___kernel_ctrl.html", null ], + [ "Thread Management", "group___c_m_s_i_s___r_t_o_s___thread_mgmt.html", null ], + [ "Generic Wait Functions", "group___c_m_s_i_s___r_t_o_s___wait.html", null ], + [ "Timer Management", "group___c_m_s_i_s___r_t_o_s___timer_mgmt.html", null ], + [ "Signal Management", "group___c_m_s_i_s___r_t_o_s___signal_mgmt.html", null ], + [ "Mutex Management", "group___c_m_s_i_s___r_t_o_s___mutex_mgmt.html", null ], + [ "Semaphore Management", "group___c_m_s_i_s___r_t_o_s___semaphore_mgmt.html", null ], + [ "Memory Pool Management", "group___c_m_s_i_s___r_t_o_s___pool_mgmt.html", null ], + [ "Message Queue Management", "group___c_m_s_i_s___r_t_o_s___message.html", null ], + [ "Mail Queue Management", "group___c_m_s_i_s___r_t_o_s___mail.html", null ], + [ "Generic Data Types and Definitions", "group___c_m_s_i_s___r_t_o_s___definitions.html", null ], + [ "Status and Error Codes", "group___c_m_s_i_s___r_t_o_s___status.html", null ] + ] ] + ] ], + [ "Data Structures", "annotated.html", [ + [ "os_mailQ", "group___c_m_s_i_s___r_t_o_s___definitions.html#structos__mail_q", null ], + [ "osEvent", "group___c_m_s_i_s___r_t_o_s___definitions.html#structos_event", null ], + [ "osMailQDef_t", "structos_mail_q_def__t.html", null ], + [ "osMessageQDef_t", "structos_message_q_def__t.html", null ], + [ "osMutexDef_t", "structos_mutex_def__t.html", null ], + [ "osPoolDef_t", "structos_pool_def__t.html", null ], + [ "osSemaphoreDef_t", "structos_semaphore_def__t.html", null ], + [ "osThreadDef_t", "structos_thread_def__t.html", null ], + [ "osTimerDef_t", "structos_timer_def__t.html", null ] + ] ], + [ "Data Structure Index", "classes.html", null ], + [ "Data Fields", "functions.html", null ], + [ "Files", "files.html", [ + [ "cmsis_os.h", "cmsis__os_8h.html", null ] + ] ], + [ "Index", "globals.html", null ] + ] ] +]; + +function createIndent(o,domNode,node,level) +{ + if (node.parentNode && node.parentNode.parentNode) + { + createIndent(o,domNode,node.parentNode,level+1); + } + var imgNode = document.createElement("img"); + if (level==0 && node.childrenData) + { + node.plus_img = imgNode; + node.expandToggle = document.createElement("a"); + node.expandToggle.href = "javascript:void(0)"; + node.expandToggle.onclick = function() + { + if (node.expanded) + { + $(node.getChildrenUL()).slideUp("fast"); + if (node.isLast) + { + node.plus_img.src = node.relpath+"ftv2plastnode.png"; + } + else + { + node.plus_img.src = node.relpath+"ftv2pnode.png"; + } + node.expanded = false; + } + else + { + expandNode(o, node, false); + } + } + node.expandToggle.appendChild(imgNode); + domNode.appendChild(node.expandToggle); + } + else + { + domNode.appendChild(imgNode); + } + if (level==0) + { + if (node.isLast) + { + if (node.childrenData) + { + imgNode.src = node.relpath+"ftv2plastnode.png"; + } + else + { + imgNode.src = node.relpath+"ftv2lastnode.png"; + domNode.appendChild(imgNode); + } + } + else + { + if (node.childrenData) + { + imgNode.src = node.relpath+"ftv2pnode.png"; + } + else + { + imgNode.src = node.relpath+"ftv2node.png"; + domNode.appendChild(imgNode); + } + } + } + else + { + if (node.isLast) + { + imgNode.src = node.relpath+"ftv2blank.png"; + } + else + { + imgNode.src = node.relpath+"ftv2vertline.png"; + } + } + imgNode.border = "0"; +} + +function newNode(o, po, text, link, childrenData, lastNode) +{ + var node = new Object(); + node.children = Array(); + node.childrenData = childrenData; + node.depth = po.depth + 1; + node.relpath = po.relpath; + node.isLast = lastNode; + + node.li = document.createElement("li"); + po.getChildrenUL().appendChild(node.li); + node.parentNode = po; + + node.itemDiv = document.createElement("div"); + node.itemDiv.className = "item"; + + node.labelSpan = document.createElement("span"); + node.labelSpan.className = "label"; + + createIndent(o,node.itemDiv,node,0); + node.itemDiv.appendChild(node.labelSpan); + node.li.appendChild(node.itemDiv); + + var a = document.createElement("a"); + node.labelSpan.appendChild(a); + node.label = document.createTextNode(text); + a.appendChild(node.label); + if (link) + { + a.href = node.relpath+link; + } + else + { + if (childrenData != null) + { + a.className = "nolink"; + a.href = "javascript:void(0)"; + a.onclick = node.expandToggle.onclick; + node.expanded = false; + } + } + + node.childrenUL = null; + node.getChildrenUL = function() + { + if (!node.childrenUL) + { + node.childrenUL = document.createElement("ul"); + node.childrenUL.className = "children_ul"; + node.childrenUL.style.display = "none"; + node.li.appendChild(node.childrenUL); + } + return node.childrenUL; + }; + + return node; +} + +function showRoot() +{ + var headerHeight = $("#top").height(); + var footerHeight = $("#nav-path").height(); + var windowHeight = $(window).height() - headerHeight - footerHeight; + navtree.scrollTo('#selected',0,{offset:-windowHeight/2}); +} + +function expandNode(o, node, imm) +{ + if (node.childrenData && !node.expanded) + { + if (!node.childrenVisited) + { + getNode(o, node); + } + if (imm) + { + $(node.getChildrenUL()).show(); + } + else + { + $(node.getChildrenUL()).slideDown("fast",showRoot); + } + if (node.isLast) + { + node.plus_img.src = node.relpath+"ftv2mlastnode.png"; + } + else + { + node.plus_img.src = node.relpath+"ftv2mnode.png"; + } + node.expanded = true; + } +} + +function getNode(o, po) +{ + po.childrenVisited = true; + var l = po.childrenData.length-1; + for (var i in po.childrenData) + { + var nodeData = po.childrenData[i]; + po.children[i] = newNode(o, po, nodeData[0], nodeData[1], nodeData[2], + i==l); + } +} + +function findNavTreePage(url, data) +{ + var nodes = data; + var result = null; + for (var i in nodes) + { + var d = nodes[i]; + if (d[1] == url) + { + return new Array(i); + } + else if (d[2] != null) // array of children + { + result = findNavTreePage(url, d[2]); + if (result != null) + { + return (new Array(i).concat(result)); + } + } + } + return null; +} + +function initNavTree(toroot,relpath) +{ + var o = new Object(); + o.toroot = toroot; + o.node = new Object(); + o.node.li = document.getElementById("nav-tree-contents"); + o.node.childrenData = NAVTREE; + o.node.children = new Array(); + o.node.childrenUL = document.createElement("ul"); + o.node.getChildrenUL = function() { return o.node.childrenUL; }; + o.node.li.appendChild(o.node.childrenUL); + o.node.depth = 0; + o.node.relpath = relpath; + + getNode(o, o.node); + + o.breadcrumbs = findNavTreePage(toroot, NAVTREE); + if (o.breadcrumbs == null) + { + o.breadcrumbs = findNavTreePage("index.html",NAVTREE); + } + if (o.breadcrumbs != null && o.breadcrumbs.length>0) + { + var p = o.node; + for (var i in o.breadcrumbs) + { + var j = o.breadcrumbs[i]; + p = p.children[j]; + expandNode(o,p,true); + } + p.itemDiv.className = p.itemDiv.className + " selected"; + p.itemDiv.id = "selected"; + $(window).load(showRoot); + } +} + diff --git a/Libraries/CMSIS/Documentation/RTOS/html/open.png b/Libraries/CMSIS/Documentation/RTOS/html/open.png new file mode 100644 index 0000000000000000000000000000000000000000..7b35d2c2c389743089632fe24c3104f2173d97af GIT binary patch literal 118 zcmeAS@N?(olHy`uVBq!ia0vp^oFL4>1|%O$WD@{Vww^AIAr*{o=Nbw!DDW^(zOibV zl!F8B0?t?i!vld4k#$~0_AX3zElaokn + + + +Usage and Description + + + + + + + + + + + + + +
    + +
    + + + + + + + + + + + +
    +
    CMSIS-RTOS +  Version 1.00 +
    +
    CMSIS-RTOS API: Generic RTOS interface for Cortex-M processor-based devices.
    +
    +
    + +
    + +
    + + + +
    +
    + +
    +
    +
    + +
    +
    +
    +
    Usage and Description
    +
    +
    +
    Here is a list of all related documentation pages:
    +
    +
    + + + + + diff --git a/Libraries/CMSIS/Documentation/RTOS/html/resize.js b/Libraries/CMSIS/Documentation/RTOS/html/resize.js new file mode 100644 index 0000000..04fa95c --- /dev/null +++ b/Libraries/CMSIS/Documentation/RTOS/html/resize.js @@ -0,0 +1,81 @@ +var cookie_namespace = 'doxygen'; +var sidenav,navtree,content,header; + +function readCookie(cookie) +{ + var myCookie = cookie_namespace+"_"+cookie+"="; + if (document.cookie) + { + var index = document.cookie.indexOf(myCookie); + if (index != -1) + { + var valStart = index + myCookie.length; + var valEnd = document.cookie.indexOf(";", valStart); + if (valEnd == -1) + { + valEnd = document.cookie.length; + } + var val = document.cookie.substring(valStart, valEnd); + return val; + } + } + return 0; +} + +function writeCookie(cookie, val, expiration) +{ + if (val==undefined) return; + if (expiration == null) + { + var date = new Date(); + date.setTime(date.getTime()+(10*365*24*60*60*1000)); // default expiration is one week + expiration = date.toGMTString(); + } + document.cookie = cookie_namespace + "_" + cookie + "=" + val + "; expires=" + expiration+"; path=/"; +} + +function resizeWidth() +{ + var windowWidth = $(window).width() + "px"; + var sidenavWidth = $(sidenav).width(); + content.css({marginLeft:parseInt(sidenavWidth)+6+"px"}); //account for 6px-wide handle-bar + writeCookie('width',sidenavWidth, null); +} + +function restoreWidth(navWidth) +{ + var windowWidth = $(window).width() + "px"; + content.css({marginLeft:parseInt(navWidth)+6+"px"}); + sidenav.css({width:navWidth + "px"}); +} + +function resizeHeight() +{ + var headerHeight = header.height(); + var footerHeight = footer.height(); + var windowHeight = $(window).height() - headerHeight - footerHeight; + content.css({height:windowHeight + "px"}); + navtree.css({height:windowHeight + "px"}); + sidenav.css({height:windowHeight + "px",top: headerHeight+"px"}); +} + +function initResizable() +{ + header = $("#top"); + sidenav = $("#side-nav"); + content = $("#doc-content"); + navtree = $("#nav-tree"); + footer = $("#nav-path"); + $(".side-nav-resizable").resizable({resize: function(e, ui) { resizeWidth(); } }); + $(window).resize(function() { resizeHeight(); }); + var width = readCookie('width'); + if (width) { restoreWidth(width); } else { resizeWidth(); } + resizeHeight(); + var url = location.href; + var i=url.indexOf("#"); + if (i>=0) window.location.hash=url.substr(i); + var _preventDefault = function(evt) { evt.preventDefault(); }; + $("#splitbar").bind("dragstart", _preventDefault).bind("selectstart", _preventDefault); +} + + diff --git a/Libraries/CMSIS/Documentation/RTOS/html/search/all_63.html b/Libraries/CMSIS/Documentation/RTOS/html/search/all_63.html new file mode 100644 index 0000000..b71fac6 --- /dev/null +++ b/Libraries/CMSIS/Documentation/RTOS/html/search/all_63.html @@ -0,0 +1,30 @@ + + + + + + + +
    +
    Loading...
    +
    +
    + cmsis_os.h +
    +
    +
    +
    + cmsis_os.txt +
    +
    +
    Searching...
    +
    No Matches
    + +
    + + diff --git a/Libraries/CMSIS/Documentation/RTOS/html/search/all_64.html b/Libraries/CMSIS/Documentation/RTOS/html/search/all_64.html new file mode 100644 index 0000000..17ea606 --- /dev/null +++ b/Libraries/CMSIS/Documentation/RTOS/html/search/all_64.html @@ -0,0 +1,35 @@ + + + + + + + +
    +
    Loading...
    +
    +
    + def + osEvent +
    +
    + +
    Searching...
    +
    No Matches
    + +
    + + diff --git a/Libraries/CMSIS/Documentation/RTOS/html/search/all_69.html b/Libraries/CMSIS/Documentation/RTOS/html/search/all_69.html new file mode 100644 index 0000000..a924b79 --- /dev/null +++ b/Libraries/CMSIS/Documentation/RTOS/html/search/all_69.html @@ -0,0 +1,36 @@ + + + + + + + +
    +
    Loading...
    +
    +
    + instances + osThreadDef_t +
    +
    + +
    Searching...
    +
    No Matches
    + +
    + + diff --git a/Libraries/CMSIS/Documentation/RTOS/html/search/all_6d.html b/Libraries/CMSIS/Documentation/RTOS/html/search/all_6d.html new file mode 100644 index 0000000..68f4268 --- /dev/null +++ b/Libraries/CMSIS/Documentation/RTOS/html/search/all_6d.html @@ -0,0 +1,32 @@ + + + + + + + +
    +
    Loading...
    +
    +
    + mail_id + osEvent +
    +
    +
    +
    + message_id + osEvent +
    +
    +
    Searching...
    +
    No Matches
    + +
    + + diff --git a/Libraries/CMSIS/Documentation/RTOS/html/search/all_6f.html b/Libraries/CMSIS/Documentation/RTOS/html/search/all_6f.html new file mode 100644 index 0000000..6a09242 --- /dev/null +++ b/Libraries/CMSIS/Documentation/RTOS/html/search/all_6f.html @@ -0,0 +1,662 @@ + + + + + + + +
    +
    Loading...
    +
    +
    + os_mailQ +
    +
    +
    +
    + os_pthread + cmsis_os.h +
    +
    +
    +
    + os_ptimer + cmsis_os.h +
    +
    +
    +
    + os_status_reserved + cmsis_os.h +
    +
    + +
    +
    + osCMSIS + cmsis_os.h +
    +
    +
    +
    + osCMSIS_KERNEL + cmsis_os.h +
    +
    +
    +
    + osDelay + cmsis_os.h +
    +
    +
    +
    + osErrorISR + cmsis_os.h +
    +
    +
    +
    + osErrorISRRecursive + cmsis_os.h +
    +
    +
    +
    + osErrorNoMemory + cmsis_os.h +
    +
    +
    +
    + osErrorOS + cmsis_os.h +
    +
    +
    +
    + osErrorParameter + cmsis_os.h +
    +
    +
    +
    + osErrorPriority + cmsis_os.h +
    +
    +
    +
    + osErrorResource + cmsis_os.h +
    +
    +
    +
    + osErrorTimeoutResource + cmsis_os.h +
    +
    +
    +
    + osErrorValue + cmsis_os.h +
    +
    +
    +
    + osEvent +
    +
    +
    +
    + osEventMail + cmsis_os.h +
    +
    +
    +
    + osEventMessage + cmsis_os.h +
    +
    +
    +
    + osEventSignal + cmsis_os.h +
    +
    +
    +
    + osEventTimeout + cmsis_os.h +
    +
    +
    +
    + osFeature_MailQ + cmsis_os.h +
    +
    +
    +
    + osFeature_MainThread + cmsis_os.h +
    +
    +
    +
    + osFeature_MessageQ + cmsis_os.h +
    +
    +
    +
    + osFeature_Pool + cmsis_os.h +
    +
    +
    +
    + osFeature_Semaphore + cmsis_os.h +
    +
    +
    +
    + osFeature_Signals + cmsis_os.h +
    +
    +
    +
    + osFeature_Wait + cmsis_os.h +
    +
    +
    +
    + osKernelRunning + cmsis_os.h +
    +
    +
    +
    + osKernelStart + cmsis_os.h +
    +
    +
    +
    + osKernelSystemId + cmsis_os.h +
    +
    +
    +
    + osMailAlloc + cmsis_os.h +
    +
    +
    +
    + osMailCAlloc + cmsis_os.h +
    +
    +
    +
    + osMailCreate + cmsis_os.h +
    +
    +
    +
    + osMailFree + cmsis_os.h +
    +
    +
    +
    + osMailGet + cmsis_os.h +
    +
    +
    +
    + osMailPut + cmsis_os.h +
    +
    +
    +
    + osMailQ + cmsis_os.h +
    +
    +
    +
    + osMailQDef + cmsis_os.h +
    +
    +
    +
    + osMailQDef_t +
    +
    +
    +
    + osMailQId + cmsis_os.h +
    +
    +
    +
    + osMessageCreate + cmsis_os.h +
    +
    +
    +
    + osMessageGet + cmsis_os.h +
    +
    +
    +
    + osMessagePut + cmsis_os.h +
    +
    +
    +
    + osMessageQ + cmsis_os.h +
    +
    +
    +
    + osMessageQDef + cmsis_os.h +
    +
    + +
    +
    + osMessageQId + cmsis_os.h +
    +
    +
    +
    + osMutex + cmsis_os.h +
    +
    +
    +
    + osMutexCreate + cmsis_os.h +
    +
    +
    +
    + osMutexDef + cmsis_os.h +
    +
    +
    +
    + osMutexDef_t +
    +
    +
    +
    + osMutexId + cmsis_os.h +
    +
    +
    +
    + osMutexRelease + cmsis_os.h +
    +
    +
    +
    + osMutexWait + cmsis_os.h +
    +
    +
    +
    + osOK + cmsis_os.h +
    +
    +
    +
    + osPool + cmsis_os.h +
    +
    +
    +
    + osPoolAlloc + cmsis_os.h +
    +
    +
    +
    + osPoolCAlloc + cmsis_os.h +
    +
    +
    +
    + osPoolCreate + cmsis_os.h +
    +
    +
    +
    + osPoolDef + cmsis_os.h +
    +
    +
    +
    + osPoolDef_t +
    +
    +
    +
    + osPoolFree + cmsis_os.h +
    +
    +
    +
    + osPoolId + cmsis_os.h +
    +
    + +
    +
    + osPriorityAboveNormal + cmsis_os.h +
    +
    +
    +
    + osPriorityBelowNormal + cmsis_os.h +
    +
    +
    +
    + osPriorityError + cmsis_os.h +
    +
    +
    +
    + osPriorityHigh + cmsis_os.h +
    +
    +
    +
    + osPriorityIdle + cmsis_os.h +
    +
    +
    +
    + osPriorityLow + cmsis_os.h +
    +
    +
    +
    + osPriorityNormal + cmsis_os.h +
    +
    +
    +
    + osPriorityRealtime + cmsis_os.h +
    +
    +
    +
    + osSemaphore + cmsis_os.h +
    +
    +
    +
    + osSemaphoreCreate + cmsis_os.h +
    +
    +
    +
    + osSemaphoreDef + cmsis_os.h +
    +
    + +
    +
    + osSemaphoreId + cmsis_os.h +
    +
    +
    +
    + osSemaphoreRelease + cmsis_os.h +
    +
    +
    +
    + osSemaphoreWait + cmsis_os.h +
    +
    +
    +
    + osSignalClear + cmsis_os.h +
    +
    +
    +
    + osSignalGet + cmsis_os.h +
    +
    +
    +
    + osSignalSet + cmsis_os.h +
    +
    +
    +
    + osSignalWait + cmsis_os.h +
    +
    + +
    +
    + osThread + cmsis_os.h +
    +
    +
    +
    + osThreadCreate + cmsis_os.h +
    +
    +
    +
    + osThreadDef + cmsis_os.h +
    +
    +
    +
    + osThreadDef_t +
    +
    +
    +
    + osThreadGetId + cmsis_os.h +
    +
    +
    +
    + osThreadGetPriority + cmsis_os.h +
    +
    +
    +
    + osThreadId + cmsis_os.h +
    +
    +
    +
    + osThreadSetPriority + cmsis_os.h +
    +
    +
    +
    + osThreadTerminate + cmsis_os.h +
    +
    +
    +
    + osThreadYield + cmsis_os.h +
    +
    +
    +
    + osTimer + cmsis_os.h +
    +
    +
    +
    + osTimerCreate + cmsis_os.h +
    +
    +
    +
    + osTimerDef + cmsis_os.h +
    +
    +
    +
    + osTimerDef_t +
    +
    +
    +
    + osTimerId + cmsis_os.h +
    +
    +
    +
    + osTimerOnce + cmsis_os.h +
    +
    +
    +
    + osTimerPeriodic + cmsis_os.h +
    +
    +
    +
    + osTimerStart + cmsis_os.h +
    +
    +
    +
    + osTimerStop + cmsis_os.h +
    +
    +
    +
    + osWait + cmsis_os.h +
    +
    +
    +
    + osWaitForever + cmsis_os.h +
    +
    +
    Searching...
    +
    No Matches
    + +
    + + diff --git a/Libraries/CMSIS/Documentation/RTOS/html/search/all_70.html b/Libraries/CMSIS/Documentation/RTOS/html/search/all_70.html new file mode 100644 index 0000000..760f336 --- /dev/null +++ b/Libraries/CMSIS/Documentation/RTOS/html/search/all_70.html @@ -0,0 +1,54 @@ + + + + + + + +
    +
    Loading...
    +
    +
    + p + osEvent +
    +
    + +
    +
    + pool_sz + osPoolDef_t +
    +
    +
    +
    + pthread + osThreadDef_t +
    +
    +
    +
    + ptimer + osTimerDef_t +
    +
    +
    Searching...
    +
    No Matches
    + +
    + + diff --git a/Libraries/CMSIS/Documentation/RTOS/html/search/all_71.html b/Libraries/CMSIS/Documentation/RTOS/html/search/all_71.html new file mode 100644 index 0000000..9923f9a --- /dev/null +++ b/Libraries/CMSIS/Documentation/RTOS/html/search/all_71.html @@ -0,0 +1,29 @@ + + + + + + + +
    +
    Loading...
    + +
    Searching...
    +
    No Matches
    + +
    + + diff --git a/Libraries/CMSIS/Documentation/RTOS/html/search/all_73.html b/Libraries/CMSIS/Documentation/RTOS/html/search/all_73.html new file mode 100644 index 0000000..bcddb85 --- /dev/null +++ b/Libraries/CMSIS/Documentation/RTOS/html/search/all_73.html @@ -0,0 +1,38 @@ + + + + + + + +
    +
    Loading...
    +
    +
    + signals + osEvent +
    +
    +
    +
    + stacksize + osThreadDef_t +
    +
    +
    +
    + status + osEvent +
    +
    +
    Searching...
    +
    No Matches
    + +
    + + diff --git a/Libraries/CMSIS/Documentation/RTOS/html/search/all_74.html b/Libraries/CMSIS/Documentation/RTOS/html/search/all_74.html new file mode 100644 index 0000000..bd1c905 --- /dev/null +++ b/Libraries/CMSIS/Documentation/RTOS/html/search/all_74.html @@ -0,0 +1,26 @@ + + + + + + + +
    +
    Loading...
    +
    +
    + tpriority + osThreadDef_t +
    +
    +
    Searching...
    +
    No Matches
    + +
    + + diff --git a/Libraries/CMSIS/Documentation/RTOS/html/search/all_76.html b/Libraries/CMSIS/Documentation/RTOS/html/search/all_76.html new file mode 100644 index 0000000..f0a5ee2 --- /dev/null +++ b/Libraries/CMSIS/Documentation/RTOS/html/search/all_76.html @@ -0,0 +1,32 @@ + + + + + + + +
    +
    Loading...
    +
    +
    + v + osEvent +
    +
    +
    +
    + value + osEvent +
    +
    +
    Searching...
    +
    No Matches
    + +
    + + diff --git a/Libraries/CMSIS/Documentation/RTOS/html/search/classes_6f.html b/Libraries/CMSIS/Documentation/RTOS/html/search/classes_6f.html new file mode 100644 index 0000000..e5e385c --- /dev/null +++ b/Libraries/CMSIS/Documentation/RTOS/html/search/classes_6f.html @@ -0,0 +1,65 @@ + + + + + + + +
    +
    Loading...
    +
    +
    + os_mailQ +
    +
    +
    +
    + osEvent +
    +
    +
    +
    + osMailQDef_t +
    +
    + +
    +
    + osMutexDef_t +
    +
    +
    +
    + osPoolDef_t +
    +
    + +
    +
    + osThreadDef_t +
    +
    +
    +
    + osTimerDef_t +
    +
    +
    Searching...
    +
    No Matches
    + +
    + + diff --git a/Libraries/CMSIS/Documentation/RTOS/html/search/close.png b/Libraries/CMSIS/Documentation/RTOS/html/search/close.png new file mode 100644 index 0000000000000000000000000000000000000000..9342d3dfeea7b7c4ee610987e717804b5a42ceb9 GIT binary patch literal 273 zcmV+s0q*{ZP)4(RlMby96)VwnbG{ zbe&}^BDn7x>$<{ck4zAK-=nT;=hHG)kmplIF${xqm8db3oX6wT3bvp`TE@m0cg;b) zBuSL}5?N7O(iZLdAlz@)b)Rd~DnSsSX&P5qC`XwuFwcAYLC+d2>+1(8on;wpt8QIC X2MT$R4iQDd00000NkvXXu0mjfia~GN literal 0 HcmV?d00001 diff --git a/Libraries/CMSIS/Documentation/RTOS/html/search/defines_6f.html b/Libraries/CMSIS/Documentation/RTOS/html/search/defines_6f.html new file mode 100644 index 0000000..72be715 --- /dev/null +++ b/Libraries/CMSIS/Documentation/RTOS/html/search/defines_6f.html @@ -0,0 +1,170 @@ + + + + + + + +
    +
    Loading...
    +
    +
    + osCMSIS + cmsis_os.h +
    +
    +
    +
    + osCMSIS_KERNEL + cmsis_os.h +
    +
    +
    +
    + osFeature_MailQ + cmsis_os.h +
    +
    +
    +
    + osFeature_MainThread + cmsis_os.h +
    +
    +
    +
    + osFeature_MessageQ + cmsis_os.h +
    +
    +
    +
    + osFeature_Pool + cmsis_os.h +
    +
    +
    +
    + osFeature_Semaphore + cmsis_os.h +
    +
    +
    +
    + osFeature_Signals + cmsis_os.h +
    +
    +
    +
    + osFeature_Wait + cmsis_os.h +
    +
    +
    +
    + osKernelSystemId + cmsis_os.h +
    +
    +
    +
    + osMailQ + cmsis_os.h +
    +
    +
    +
    + osMailQDef + cmsis_os.h +
    +
    +
    +
    + osMessageQ + cmsis_os.h +
    +
    +
    +
    + osMessageQDef + cmsis_os.h +
    +
    +
    +
    + osMutex + cmsis_os.h +
    +
    +
    +
    + osMutexDef + cmsis_os.h +
    +
    +
    +
    + osPool + cmsis_os.h +
    +
    +
    +
    + osPoolDef + cmsis_os.h +
    +
    +
    +
    + osSemaphore + cmsis_os.h +
    +
    +
    +
    + osSemaphoreDef + cmsis_os.h +
    +
    +
    +
    + osThread + cmsis_os.h +
    +
    +
    +
    + osThreadDef + cmsis_os.h +
    +
    +
    +
    + osTimer + cmsis_os.h +
    +
    +
    +
    + osTimerDef + cmsis_os.h +
    +
    +
    +
    + osWaitForever + cmsis_os.h +
    +
    +
    Searching...
    +
    No Matches
    + +
    + + diff --git a/Libraries/CMSIS/Documentation/RTOS/html/search/enums_6f.html b/Libraries/CMSIS/Documentation/RTOS/html/search/enums_6f.html new file mode 100644 index 0000000..806ec82 --- /dev/null +++ b/Libraries/CMSIS/Documentation/RTOS/html/search/enums_6f.html @@ -0,0 +1,47 @@ + + + + + + + +
    +
    Loading...
    + + + +
    Searching...
    +
    No Matches
    + +
    + + diff --git a/Libraries/CMSIS/Documentation/RTOS/html/search/enumvalues_6f.html b/Libraries/CMSIS/Documentation/RTOS/html/search/enumvalues_6f.html new file mode 100644 index 0000000..3929b4d --- /dev/null +++ b/Libraries/CMSIS/Documentation/RTOS/html/search/enumvalues_6f.html @@ -0,0 +1,170 @@ + + + + + + + +
    +
    Loading...
    +
    +
    + os_status_reserved + cmsis_os.h +
    +
    +
    +
    + osErrorISR + cmsis_os.h +
    +
    +
    +
    + osErrorISRRecursive + cmsis_os.h +
    +
    +
    +
    + osErrorNoMemory + cmsis_os.h +
    +
    +
    +
    + osErrorOS + cmsis_os.h +
    +
    +
    +
    + osErrorParameter + cmsis_os.h +
    +
    +
    +
    + osErrorPriority + cmsis_os.h +
    +
    +
    +
    + osErrorResource + cmsis_os.h +
    +
    +
    +
    + osErrorTimeoutResource + cmsis_os.h +
    +
    +
    +
    + osErrorValue + cmsis_os.h +
    +
    +
    +
    + osEventMail + cmsis_os.h +
    +
    +
    +
    + osEventMessage + cmsis_os.h +
    +
    +
    +
    + osEventSignal + cmsis_os.h +
    +
    +
    +
    + osEventTimeout + cmsis_os.h +
    +
    +
    +
    + osOK + cmsis_os.h +
    +
    +
    +
    + osPriorityAboveNormal + cmsis_os.h +
    +
    +
    +
    + osPriorityBelowNormal + cmsis_os.h +
    +
    +
    +
    + osPriorityError + cmsis_os.h +
    +
    +
    +
    + osPriorityHigh + cmsis_os.h +
    +
    +
    +
    + osPriorityIdle + cmsis_os.h +
    +
    +
    +
    + osPriorityLow + cmsis_os.h +
    +
    +
    +
    + osPriorityNormal + cmsis_os.h +
    +
    +
    +
    + osPriorityRealtime + cmsis_os.h +
    +
    +
    +
    + osTimerOnce + cmsis_os.h +
    +
    +
    +
    + osTimerPeriodic + cmsis_os.h +
    +
    +
    Searching...
    +
    No Matches
    + +
    + + diff --git a/Libraries/CMSIS/Documentation/RTOS/html/search/files_63.html b/Libraries/CMSIS/Documentation/RTOS/html/search/files_63.html new file mode 100644 index 0000000..b71fac6 --- /dev/null +++ b/Libraries/CMSIS/Documentation/RTOS/html/search/files_63.html @@ -0,0 +1,30 @@ + + + + + + + +
    +
    Loading...
    +
    +
    + cmsis_os.h +
    +
    +
    +
    + cmsis_os.txt +
    +
    +
    Searching...
    +
    No Matches
    + +
    + + diff --git a/Libraries/CMSIS/Documentation/RTOS/html/search/functions_6f.html b/Libraries/CMSIS/Documentation/RTOS/html/search/functions_6f.html new file mode 100644 index 0000000..59c72e0 --- /dev/null +++ b/Libraries/CMSIS/Documentation/RTOS/html/search/functions_6f.html @@ -0,0 +1,236 @@ + + + + + + + +
    +
    Loading...
    +
    +
    + osDelay + cmsis_os.h +
    +
    +
    +
    + osKernelRunning + cmsis_os.h +
    +
    +
    +
    + osKernelStart + cmsis_os.h +
    +
    +
    +
    + osMailAlloc + cmsis_os.h +
    +
    +
    +
    + osMailCAlloc + cmsis_os.h +
    +
    +
    +
    + osMailCreate + cmsis_os.h +
    +
    +
    +
    + osMailFree + cmsis_os.h +
    +
    +
    +
    + osMailGet + cmsis_os.h +
    +
    +
    +
    + osMailPut + cmsis_os.h +
    +
    +
    +
    + osMessageCreate + cmsis_os.h +
    +
    +
    +
    + osMessageGet + cmsis_os.h +
    +
    +
    +
    + osMessagePut + cmsis_os.h +
    +
    +
    +
    + osMutexCreate + cmsis_os.h +
    +
    +
    +
    + osMutexRelease + cmsis_os.h +
    +
    +
    +
    + osMutexWait + cmsis_os.h +
    +
    +
    +
    + osPoolAlloc + cmsis_os.h +
    +
    +
    +
    + osPoolCAlloc + cmsis_os.h +
    +
    +
    +
    + osPoolCreate + cmsis_os.h +
    +
    +
    +
    + osPoolFree + cmsis_os.h +
    +
    +
    +
    + osSemaphoreCreate + cmsis_os.h +
    +
    +
    +
    + osSemaphoreRelease + cmsis_os.h +
    +
    +
    +
    + osSemaphoreWait + cmsis_os.h +
    +
    +
    +
    + osSignalClear + cmsis_os.h +
    +
    +
    +
    + osSignalGet + cmsis_os.h +
    +
    +
    +
    + osSignalSet + cmsis_os.h +
    +
    +
    +
    + osSignalWait + cmsis_os.h +
    +
    +
    +
    + osThreadCreate + cmsis_os.h +
    +
    +
    +
    + osThreadGetId + cmsis_os.h +
    +
    +
    +
    + osThreadGetPriority + cmsis_os.h +
    +
    +
    +
    + osThreadSetPriority + cmsis_os.h +
    +
    +
    +
    + osThreadTerminate + cmsis_os.h +
    +
    +
    +
    + osThreadYield + cmsis_os.h +
    +
    +
    +
    + osTimerCreate + cmsis_os.h +
    +
    +
    +
    + osTimerStart + cmsis_os.h +
    +
    +
    +
    + osTimerStop + cmsis_os.h +
    +
    +
    +
    + osWait + cmsis_os.h +
    +
    +
    Searching...
    +
    No Matches
    + +
    + + diff --git a/Libraries/CMSIS/Documentation/RTOS/html/search/mag_sel.png b/Libraries/CMSIS/Documentation/RTOS/html/search/mag_sel.png new file mode 100644 index 0000000000000000000000000000000000000000..81f6040a2092402b4d98f9ffa8855d12a0d4ca17 GIT binary patch literal 563 zcmV-30?hr1P)zxx&tqG15pu7)IiiXFflOc2k;dXd>%13GZAy? zRz!q0=|E6a6vV)&ZBS~G9oe0kbqyw1*gvY`{Pop2oKq#FlzgXt@Xh-7fxh>}`Fxg> z$%N%{$!4=5nM{(;=c!aG1Ofr^Do{u%Ih{^&Fc@H2)+a-?TBXrw5DW&z%Nb6mQ!L9O zl}b@6mB?f=tX3;#vl)}ggh(Vpyh(IK z(Mb0D{l{U$FsRjP;!{($+bsaaVi8T#1c0V#qEIOCYa9@UVLV`f__E81L;?WEaRA;Y zUH;rZ;vb;mk7JX|$=i3O~&If0O@oZfLg8gfIjW=dcBsz;gI=!{-r4# z4%6v$&~;q^j7Fo67yJ(NJWuX+I~I!tj^nW3?}^9bq|<3^+vapS5sgM^x7!cs(+mMT z&y%j};&~po+YO)3hoUH4E*E;e9>?R6SS&`X)p`njycAVcg{rEb41T{~Hk(bl-7eSb zmFxA2uIqo#@R?lKm50ND`~6Nfn|-b1|L6O98vt3Tx@gKz#isxO002ovPDHLkV1kyW B_l^Jn literal 0 HcmV?d00001 diff --git a/Libraries/CMSIS/Documentation/RTOS/html/search/nomatches.html b/Libraries/CMSIS/Documentation/RTOS/html/search/nomatches.html new file mode 100644 index 0000000..b1ded27 --- /dev/null +++ b/Libraries/CMSIS/Documentation/RTOS/html/search/nomatches.html @@ -0,0 +1,12 @@ + + + + + + + +
    +
    No Matches
    +
    + + diff --git a/Libraries/CMSIS/Documentation/RTOS/html/search/search.css b/Libraries/CMSIS/Documentation/RTOS/html/search/search.css new file mode 100644 index 0000000..1746d13 --- /dev/null +++ b/Libraries/CMSIS/Documentation/RTOS/html/search/search.css @@ -0,0 +1,240 @@ +/*---------------- Search Box */ + +#FSearchBox { + float: left; +} + +#searchli { + float: right; + display: block; + width: 170px; + height: 24px; +} + +#MSearchBox { + white-space : nowrap; + position: absolute; + float: none; + display: inline; + margin-top: 3px; + right: 0px; + width: 170px; + z-index: 102; +} + +#MSearchBox .left +{ + display:block; + position:absolute; + left:10px; + width:20px; + height:19px; + background:url('search_l.png') no-repeat; + background-position:right; +} + +#MSearchSelect { + display:block; + position:absolute; + width:20px; + height:19px; +} + +.left #MSearchSelect { + left:4px; +} + +.right #MSearchSelect { + right:5px; +} + +#MSearchField { + display:block; + position:absolute; + height:19px; + background:url('search_m.png') repeat-x; + border:none; + width:116px; + margin-left:20px; + padding-left:4px; + color: #909090; + outline: none; + font: 9pt Arial, Verdana, sans-serif; +} + +#FSearchBox #MSearchField { + margin-left:15px; +} + +#MSearchBox .right { + display:block; + position:absolute; + right:10px; + top:0px; + width:20px; + height:19px; + background:url('search_r.png') no-repeat; + background-position:left; +} + +#MSearchClose { + display: none; + position: absolute; + top: 4px; + background : none; + border: none; + margin: 0px 4px 0px 0px; + padding: 0px 0px; + outline: none; +} + +.left #MSearchClose { + left: 6px; +} + +.right #MSearchClose { + right: 2px; +} + +.MSearchBoxActive #MSearchField { + color: #000000; +} + +/*---------------- Search filter selection */ + +#MSearchSelectWindow { + display: none; + position: absolute; + left: 0; top: 0; + border: 1px solid #90A5CE; + background-color: #F9FAFC; + z-index: 1; + padding-top: 4px; + padding-bottom: 4px; + -moz-border-radius: 4px; + -webkit-border-top-left-radius: 4px; + -webkit-border-top-right-radius: 4px; + -webkit-border-bottom-left-radius: 4px; + -webkit-border-bottom-right-radius: 4px; + -webkit-box-shadow: 5px 5px 5px rgba(0, 0, 0, 0.15); +} + +.SelectItem { + font: 8pt Arial, Verdana, sans-serif; + padding-left: 2px; + padding-right: 12px; + border: 0px; +} + +span.SelectionMark { + margin-right: 4px; + font-family: monospace; + outline-style: none; + text-decoration: none; +} + +a.SelectItem { + display: block; + outline-style: none; + color: #000000; + text-decoration: none; + padding-left: 6px; + padding-right: 12px; +} + +a.SelectItem:focus, +a.SelectItem:active { + color: #000000; + outline-style: none; + text-decoration: none; +} + +a.SelectItem:hover { + color: #FFFFFF; + background-color: #3D578C; + outline-style: none; + text-decoration: none; + cursor: pointer; + display: block; +} + +/*---------------- Search results window */ + +iframe#MSearchResults { + width: 60ex; + height: 15em; +} + +#MSearchResultsWindow { + display: none; + position: absolute; + left: 0; top: 0; + border: 1px solid #000; + background-color: #EEF1F7; +} + +/* ----------------------------------- */ + + +#SRIndex { + clear:both; + padding-bottom: 15px; +} + +.SREntry { + font-size: 10pt; + padding-left: 1ex; +} + +.SRPage .SREntry { + font-size: 8pt; + padding: 1px 5px; +} + +body.SRPage { + margin: 5px 2px; +} + +.SRChildren { + padding-left: 3ex; padding-bottom: .5em +} + +.SRPage .SRChildren { + display: none; +} + +.SRSymbol { + font-weight: bold; + color: #425E97; + font-family: Arial, Verdana, sans-serif; + text-decoration: none; + outline: none; +} + +a.SRScope { + display: block; + color: #425E97; + font-family: Arial, Verdana, sans-serif; + text-decoration: none; + outline: none; +} + +a.SRSymbol:focus, a.SRSymbol:active, +a.SRScope:focus, a.SRScope:active { + text-decoration: underline; +} + +.SRPage .SRStatus { + padding: 2px 5px; + font-size: 8pt; + font-style: italic; +} + +.SRResult { + display: none; +} + +DIV.searchresults { + margin-left: 10px; + margin-right: 10px; +} diff --git a/Libraries/CMSIS/Documentation/RTOS/html/search/search.js b/Libraries/CMSIS/Documentation/RTOS/html/search/search.js new file mode 100644 index 0000000..32e7118 --- /dev/null +++ b/Libraries/CMSIS/Documentation/RTOS/html/search/search.js @@ -0,0 +1,742 @@ +// Search script generated by doxygen +// Copyright (C) 2009 by Dimitri van Heesch. + +// The code in this file is loosly based on main.js, part of Natural Docs, +// which is Copyright (C) 2003-2008 Greg Valure +// Natural Docs is licensed under the GPL. + +var indexSectionsWithContent = +{ + 0: "0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000001100001000101110110100000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000", + 1: "0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000001000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000", + 2: "0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000001000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000", + 3: "0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000001000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000", + 4: "0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000100001000100110110100000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000", + 5: "0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000001000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000", + 6: "0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000001000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000", + 7: "0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000001000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000", + 8: "0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000001000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000" +}; + +var indexSectionNames = +{ + 0: "all", + 1: "classes", + 2: "files", + 3: "functions", + 4: "variables", + 5: "typedefs", + 6: "enums", + 7: "enumvalues", + 8: "defines" +}; + +function convertToId(search) +{ + var result = ''; + for (i=0;i do a search + { + this.Search(); + } + } + + this.OnSearchSelectKey = function(evt) + { + var e = (evt) ? evt : window.event; // for IE + if (e.keyCode==40 && this.searchIndex0) // Up + { + this.searchIndex--; + this.OnSelectItem(this.searchIndex); + } + else if (e.keyCode==13 || e.keyCode==27) + { + this.OnSelectItem(this.searchIndex); + this.CloseSelectionWindow(); + this.DOMSearchField().focus(); + } + return false; + } + + // --------- Actions + + // Closes the results window. + this.CloseResultsWindow = function() + { + this.DOMPopupSearchResultsWindow().style.display = 'none'; + this.DOMSearchClose().style.display = 'none'; + this.Activate(false); + } + + this.CloseSelectionWindow = function() + { + this.DOMSearchSelectWindow().style.display = 'none'; + } + + // Performs a search. + this.Search = function() + { + this.keyTimeout = 0; + + // strip leading whitespace + var searchValue = this.DOMSearchField().value.replace(/^ +/, ""); + + var code = searchValue.toLowerCase().charCodeAt(0); + var hexCode; + if (code<16) + { + hexCode="0"+code.toString(16); + } + else + { + hexCode=code.toString(16); + } + + var resultsPage; + var resultsPageWithSearch; + var hasResultsPage; + + if (indexSectionsWithContent[this.searchIndex].charAt(code) == '1') + { + resultsPage = this.resultsPath + '/' + indexSectionNames[this.searchIndex] + '_' + hexCode + '.html'; + resultsPageWithSearch = resultsPage+'?'+escape(searchValue); + hasResultsPage = true; + } + else // nothing available for this search term + { + resultsPage = this.resultsPath + '/nomatches.html'; + resultsPageWithSearch = resultsPage; + hasResultsPage = false; + } + + window.frames.MSearchResults.location = resultsPageWithSearch; + var domPopupSearchResultsWindow = this.DOMPopupSearchResultsWindow(); + + if (domPopupSearchResultsWindow.style.display!='block') + { + var domSearchBox = this.DOMSearchBox(); + this.DOMSearchClose().style.display = 'inline'; + if (this.insideFrame) + { + var domPopupSearchResults = this.DOMPopupSearchResults(); + domPopupSearchResultsWindow.style.position = 'relative'; + domPopupSearchResultsWindow.style.display = 'block'; + var width = document.body.clientWidth - 8; // the -8 is for IE :-( + domPopupSearchResultsWindow.style.width = width + 'px'; + domPopupSearchResults.style.width = width + 'px'; + } + else + { + var domPopupSearchResults = this.DOMPopupSearchResults(); + var left = getXPos(domSearchBox) + 150; // domSearchBox.offsetWidth; + var top = getYPos(domSearchBox) + 20; // domSearchBox.offsetHeight + 1; + domPopupSearchResultsWindow.style.display = 'block'; + left -= domPopupSearchResults.offsetWidth; + domPopupSearchResultsWindow.style.top = top + 'px'; + domPopupSearchResultsWindow.style.left = left + 'px'; + } + } + + this.lastSearchValue = searchValue; + this.lastResultsPage = resultsPage; + } + + // -------- Activation Functions + + // Activates or deactivates the search panel, resetting things to + // their default values if necessary. + this.Activate = function(isActive) + { + if (isActive || // open it + this.DOMPopupSearchResultsWindow().style.display == 'block' + ) + { + this.DOMSearchBox().className = 'MSearchBoxActive'; + + var searchField = this.DOMSearchField(); + + if (searchField.value == this.searchLabel) // clear "Search" term upon entry + { + searchField.value = ''; + this.searchActive = true; + } + } + else if (!isActive) // directly remove the panel + { + this.DOMSearchBox().className = 'MSearchBoxInactive'; + this.DOMSearchField().value = this.searchLabel; + this.searchActive = false; + this.lastSearchValue = '' + this.lastResultsPage = ''; + } + } +} + +// ----------------------------------------------------------------------- + +// The class that handles everything on the search results page. +function SearchResults(name) +{ + // The number of matches from the last run of . + this.lastMatchCount = 0; + this.lastKey = 0; + this.repeatOn = false; + + // Toggles the visibility of the passed element ID. + this.FindChildElement = function(id) + { + var parentElement = document.getElementById(id); + var element = parentElement.firstChild; + + while (element && element!=parentElement) + { + if (element.nodeName == 'DIV' && element.className == 'SRChildren') + { + return element; + } + + if (element.nodeName == 'DIV' && element.hasChildNodes()) + { + element = element.firstChild; + } + else if (element.nextSibling) + { + element = element.nextSibling; + } + else + { + do + { + element = element.parentNode; + } + while (element && element!=parentElement && !element.nextSibling); + + if (element && element!=parentElement) + { + element = element.nextSibling; + } + } + } + } + + this.Toggle = function(id) + { + var element = this.FindChildElement(id); + if (element) + { + if (element.style.display == 'block') + { + element.style.display = 'none'; + } + else + { + element.style.display = 'block'; + } + } + } + + // Searches for the passed string. If there is no parameter, + // it takes it from the URL query. + // + // Always returns true, since other documents may try to call it + // and that may or may not be possible. + this.Search = function(search) + { + if (!search) // get search word from URL + { + search = window.location.search; + search = search.substring(1); // Remove the leading '?' + search = unescape(search); + } + + search = search.replace(/^ +/, ""); // strip leading spaces + search = search.replace(/ +$/, ""); // strip trailing spaces + search = search.toLowerCase(); + search = convertToId(search); + + var resultRows = document.getElementsByTagName("div"); + var matches = 0; + + var i = 0; + while (i < resultRows.length) + { + var row = resultRows.item(i); + if (row.className == "SRResult") + { + var rowMatchName = row.id.toLowerCase(); + rowMatchName = rowMatchName.replace(/^sr\d*_/, ''); // strip 'sr123_' + + if (search.length<=rowMatchName.length && + rowMatchName.substr(0, search.length)==search) + { + row.style.display = 'block'; + matches++; + } + else + { + row.style.display = 'none'; + } + } + i++; + } + document.getElementById("Searching").style.display='none'; + if (matches == 0) // no results + { + document.getElementById("NoMatches").style.display='block'; + } + else // at least one result + { + document.getElementById("NoMatches").style.display='none'; + } + this.lastMatchCount = matches; + return true; + } + + // return the first item with index index or higher that is visible + this.NavNext = function(index) + { + var focusItem; + while (1) + { + var focusName = 'Item'+index; + focusItem = document.getElementById(focusName); + if (focusItem && focusItem.parentNode.parentNode.style.display=='block') + { + break; + } + else if (!focusItem) // last element + { + break; + } + focusItem=null; + index++; + } + return focusItem; + } + + this.NavPrev = function(index) + { + var focusItem; + while (1) + { + var focusName = 'Item'+index; + focusItem = document.getElementById(focusName); + if (focusItem && focusItem.parentNode.parentNode.style.display=='block') + { + break; + } + else if (!focusItem) // last element + { + break; + } + focusItem=null; + index--; + } + return focusItem; + } + + this.ProcessKeys = function(e) + { + if (e.type == "keydown") + { + this.repeatOn = false; + this.lastKey = e.keyCode; + } + else if (e.type == "keypress") + { + if (!this.repeatOn) + { + if (this.lastKey) this.repeatOn = true; + return false; // ignore first keypress after keydown + } + } + else if (e.type == "keyup") + { + this.lastKey = 0; + this.repeatOn = false; + } + return this.lastKey!=0; + } + + this.Nav = function(evt,itemIndex) + { + var e = (evt) ? evt : window.event; // for IE + if (e.keyCode==13) return true; + if (!this.ProcessKeys(e)) return false; + + if (this.lastKey==38) // Up + { + var newIndex = itemIndex-1; + var focusItem = this.NavPrev(newIndex); + if (focusItem) + { + var child = this.FindChildElement(focusItem.parentNode.parentNode.id); + if (child && child.style.display == 'block') // children visible + { + var n=0; + var tmpElem; + while (1) // search for last child + { + tmpElem = document.getElementById('Item'+newIndex+'_c'+n); + if (tmpElem) + { + focusItem = tmpElem; + } + else // found it! + { + break; + } + n++; + } + } + } + if (focusItem) + { + focusItem.focus(); + } + else // return focus to search field + { + parent.document.getElementById("MSearchField").focus(); + } + } + else if (this.lastKey==40) // Down + { + var newIndex = itemIndex+1; + var focusItem; + var item = document.getElementById('Item'+itemIndex); + var elem = this.FindChildElement(item.parentNode.parentNode.id); + if (elem && elem.style.display == 'block') // children visible + { + focusItem = document.getElementById('Item'+itemIndex+'_c0'); + } + if (!focusItem) focusItem = this.NavNext(newIndex); + if (focusItem) focusItem.focus(); + } + else if (this.lastKey==39) // Right + { + var item = document.getElementById('Item'+itemIndex); + var elem = this.FindChildElement(item.parentNode.parentNode.id); + if (elem) elem.style.display = 'block'; + } + else if (this.lastKey==37) // Left + { + var item = document.getElementById('Item'+itemIndex); + var elem = this.FindChildElement(item.parentNode.parentNode.id); + if (elem) elem.style.display = 'none'; + } + else if (this.lastKey==27) // Escape + { + parent.searchBox.CloseResultsWindow(); + parent.document.getElementById("MSearchField").focus(); + } + else if (this.lastKey==13) // Enter + { + return true; + } + return false; + } + + this.NavChild = function(evt,itemIndex,childIndex) + { + var e = (evt) ? evt : window.event; // for IE + if (e.keyCode==13) return true; + if (!this.ProcessKeys(e)) return false; + + if (this.lastKey==38) // Up + { + if (childIndex>0) + { + var newIndex = childIndex-1; + document.getElementById('Item'+itemIndex+'_c'+newIndex).focus(); + } + else // already at first child, jump to parent + { + document.getElementById('Item'+itemIndex).focus(); + } + } + else if (this.lastKey==40) // Down + { + var newIndex = childIndex+1; + var elem = document.getElementById('Item'+itemIndex+'_c'+newIndex); + if (!elem) // last child, jump to parent next parent + { + elem = this.NavNext(itemIndex+1); + } + if (elem) + { + elem.focus(); + } + } + else if (this.lastKey==27) // Escape + { + parent.searchBox.CloseResultsWindow(); + parent.document.getElementById("MSearchField").focus(); + } + else if (this.lastKey==13) // Enter + { + return true; + } + return false; + } +} diff --git a/Libraries/CMSIS/Documentation/RTOS/html/search/search_l.png b/Libraries/CMSIS/Documentation/RTOS/html/search/search_l.png new file mode 100644 index 0000000000000000000000000000000000000000..c872f4da4a01d0754f923e6c94fd8159c0621bd1 GIT binary patch literal 604 zcmV-i0;BzjP)k7RCwB~R6VQOP#AvB$vH7i{6H{96zot$7cZT<7246EF5Np6N}+$IbiG6W zg#87A+NFaX+=_^xM1#gCtshC=E{%9^uQX_%?YwXvo{#q&MnpJ8uh(O?ZRc&~_1%^SsPxG@rfElJg-?U zm!Cz-IOn(qJP3kDp-^~qt+FGbl=5jNli^Wj_xIBG{Rc0en{!oFvyoNC7{V~T8}b>| z=jL2WIReZzX(YN(_9fV;BBD$VXQIxNasAL8ATvEu822WQ%mvv4FO#qs` BFGc_W literal 0 HcmV?d00001 diff --git a/Libraries/CMSIS/Documentation/RTOS/html/search/search_r.png b/Libraries/CMSIS/Documentation/RTOS/html/search/search_r.png new file mode 100644 index 0000000000000000000000000000000000000000..97ee8b439687084201b79c6f776a41f495c6392a GIT binary patch literal 612 zcmV-q0-ODbP)PbXFRCwB?)W514K@j&X?z2*SxFI6-@HT2E2K=9X9%Pb zEK*!TBw&g(DMC;|A)uGlRkOS9vd-?zNs%bR4d$w+ox_iFnE8fvIvv7^5<(>Te12Li z7C)9srCzmK{ZcNM{YIl9j{DePFgOWiS%xG@5CnnnJa4nvY<^glbz7^|-ZY!dUkAwd z{gaTC@_>b5h~;ug#R0wRL0>o5!hxm*s0VW?8dr}O#zXTRTnrQm_Z7z1Mrnx>&p zD4qifUjzLvbVVWi?l?rUzwt^sdb~d!f_LEhsRVIXZtQ=qSxuxqm zEX#tf>$?M_Y1-LSDT)HqG?`%-%ZpY!#{N!rcNIiL;G7F0`l?)mNGTD9;f9F5Up3Kg zw}a<-JylhG&;=!>B+fZaCX+?C+kHYrP%c?X2!Zu_olK|GcS4A70HEy;vn)I0>0kLH z`jc(WIaaHc7!HS@f*^R^Znx8W=_jIl2oWJoQ*h1^$FX!>*PqR1J8k|fw}w_y}TpE>7m8DqDO<3z`OzXt$ccSejbEZCg@0000 + + + + + + +
    +
    Loading...
    +
    +
    + os_pthread + cmsis_os.h +
    +
    +
    +
    + os_ptimer + cmsis_os.h +
    +
    +
    +
    + osMailQId + cmsis_os.h +
    +
    +
    +
    + osMessageQId + cmsis_os.h +
    +
    +
    +
    + osMutexId + cmsis_os.h +
    +
    +
    +
    + osPoolId + cmsis_os.h +
    +
    +
    +
    + osSemaphoreId + cmsis_os.h +
    +
    +
    +
    + osThreadId + cmsis_os.h +
    +
    +
    +
    + osTimerId + cmsis_os.h +
    +
    +
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    +
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    + +
    + + diff --git a/Libraries/CMSIS/Documentation/RTOS/html/search/variables_64.html b/Libraries/CMSIS/Documentation/RTOS/html/search/variables_64.html new file mode 100644 index 0000000..17ea606 --- /dev/null +++ b/Libraries/CMSIS/Documentation/RTOS/html/search/variables_64.html @@ -0,0 +1,35 @@ + + + + + + + +
    +
    Loading...
    +
    +
    + def + osEvent +
    +
    + +
    Searching...
    +
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    + +
    + + diff --git a/Libraries/CMSIS/Documentation/RTOS/html/search/variables_69.html b/Libraries/CMSIS/Documentation/RTOS/html/search/variables_69.html new file mode 100644 index 0000000..a924b79 --- /dev/null +++ b/Libraries/CMSIS/Documentation/RTOS/html/search/variables_69.html @@ -0,0 +1,36 @@ + + + + + + + +
    +
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    +
    +
    + instances + osThreadDef_t +
    +
    + +
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    + +
    + + diff --git a/Libraries/CMSIS/Documentation/RTOS/html/search/variables_6d.html b/Libraries/CMSIS/Documentation/RTOS/html/search/variables_6d.html new file mode 100644 index 0000000..68f4268 --- /dev/null +++ b/Libraries/CMSIS/Documentation/RTOS/html/search/variables_6d.html @@ -0,0 +1,32 @@ + + + + + + + +
    +
    Loading...
    +
    +
    + mail_id + osEvent +
    +
    +
    +
    + message_id + osEvent +
    +
    +
    Searching...
    +
    No Matches
    + +
    + + diff --git a/Libraries/CMSIS/Documentation/RTOS/html/search/variables_70.html b/Libraries/CMSIS/Documentation/RTOS/html/search/variables_70.html new file mode 100644 index 0000000..760f336 --- /dev/null +++ b/Libraries/CMSIS/Documentation/RTOS/html/search/variables_70.html @@ -0,0 +1,54 @@ + + + + + + + +
    +
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    +
    +
    + p + osEvent +
    +
    + +
    +
    + pool_sz + osPoolDef_t +
    +
    +
    +
    + pthread + osThreadDef_t +
    +
    +
    +
    + ptimer + osTimerDef_t +
    +
    +
    Searching...
    +
    No Matches
    + +
    + + diff --git a/Libraries/CMSIS/Documentation/RTOS/html/search/variables_71.html b/Libraries/CMSIS/Documentation/RTOS/html/search/variables_71.html new file mode 100644 index 0000000..9923f9a --- /dev/null +++ b/Libraries/CMSIS/Documentation/RTOS/html/search/variables_71.html @@ -0,0 +1,29 @@ + + + + + + + +
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    + +
    + + diff --git a/Libraries/CMSIS/Documentation/RTOS/html/search/variables_73.html b/Libraries/CMSIS/Documentation/RTOS/html/search/variables_73.html new file mode 100644 index 0000000..bcddb85 --- /dev/null +++ b/Libraries/CMSIS/Documentation/RTOS/html/search/variables_73.html @@ -0,0 +1,38 @@ + + + + + + + +
    +
    Loading...
    +
    +
    + signals + osEvent +
    +
    +
    +
    + stacksize + osThreadDef_t +
    +
    +
    +
    + status + osEvent +
    +
    +
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    + +
    + + diff --git a/Libraries/CMSIS/Documentation/RTOS/html/search/variables_74.html b/Libraries/CMSIS/Documentation/RTOS/html/search/variables_74.html new file mode 100644 index 0000000..bd1c905 --- /dev/null +++ b/Libraries/CMSIS/Documentation/RTOS/html/search/variables_74.html @@ -0,0 +1,26 @@ + + + + + + + +
    +
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    +
    +
    + tpriority + osThreadDef_t +
    +
    +
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    + +
    + + diff --git a/Libraries/CMSIS/Documentation/RTOS/html/search/variables_76.html b/Libraries/CMSIS/Documentation/RTOS/html/search/variables_76.html new file mode 100644 index 0000000..f0a5ee2 --- /dev/null +++ b/Libraries/CMSIS/Documentation/RTOS/html/search/variables_76.html @@ -0,0 +1,32 @@ + + + + + + + +
    +
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    +
    +
    + v + osEvent +
    +
    +
    +
    + value + osEvent +
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    +
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    +
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    + +
    + + diff --git a/Libraries/CMSIS/Documentation/RTOS/html/structos_mail_q_def__t.html b/Libraries/CMSIS/Documentation/RTOS/html/structos_mail_q_def__t.html new file mode 100644 index 0000000..9e8b627 --- /dev/null +++ b/Libraries/CMSIS/Documentation/RTOS/html/structos_mail_q_def__t.html @@ -0,0 +1,195 @@ + + + + +osMailQDef_t Struct Reference + + + + + + + + + + + + + +
    + +
    + + + + + + + + + + + +
    +
    CMSIS-RTOS +  Version 1.00 +
    +
    CMSIS-RTOS API: Generic RTOS interface for Cortex-M processor-based devices.
    +
    +
    + +
    + +
    + + + + +
    +
    + +
    +
    +
    + +
    +
    +
    +Data Fields
    +
    +
    osMailQDef_t Struct Reference
    +
    +
    + +

    Definition structure for mail queue. + More...

    + + + + + + + + +

    +Data Fields

    uint32_t queue_sz
     number of elements in the queue
    uint32_t item_sz
     size of an item
    void * pool
     memory array for mail
    +

    Description

    +
    Note:
    CAN BE CHANGED: os_mailQ_def is implementation specific in every CMSIS-RTOS.
    +

    Field Documentation

    + +
    +
    + + + + +
    uint32_t item_sz
    +
    +
    + +
    +
    + +
    +
    + + + + +
    void* pool
    +
    +
    + +
    +
    + +
    +
    + + + + +
    uint32_t queue_sz
    +
    +
    + +
    +
    +
    +
    + + + + + diff --git a/Libraries/CMSIS/Documentation/RTOS/html/structos_message_q_def__t.html b/Libraries/CMSIS/Documentation/RTOS/html/structos_message_q_def__t.html new file mode 100644 index 0000000..eb0a9f7 --- /dev/null +++ b/Libraries/CMSIS/Documentation/RTOS/html/structos_message_q_def__t.html @@ -0,0 +1,195 @@ + + + + +osMessageQDef_t Struct Reference + + + + + + + + + + + + + +
    + +
    + + + + + + + + + + + +
    +
    CMSIS-RTOS +  Version 1.00 +
    +
    CMSIS-RTOS API: Generic RTOS interface for Cortex-M processor-based devices.
    +
    +
    + +
    + +
    + + + + +
    +
    + +
    +
    +
    + +
    +
    +
    +Data Fields
    +
    +
    osMessageQDef_t Struct Reference
    +
    +
    + +

    Definition structure for message queue. + More...

    + + + + + + + + +

    +Data Fields

    uint32_t queue_sz
     number of elements in the queue
    uint32_t item_sz
     size of an item
    void * pool
     memory array for messages
    +

    Description

    +
    Note:
    CAN BE CHANGED: os_messageQ_def is implementation specific in every CMSIS-RTOS.
    +

    Field Documentation

    + +
    +
    + + + + +
    uint32_t item_sz
    +
    +
    + +
    +
    + +
    +
    + + + + +
    void* pool
    +
    +
    + +
    +
    + +
    +
    + + + + +
    uint32_t queue_sz
    +
    +
    + +
    +
    +
    +
    + + + + + diff --git a/Libraries/CMSIS/Documentation/RTOS/html/structos_mutex_def__t.html b/Libraries/CMSIS/Documentation/RTOS/html/structos_mutex_def__t.html new file mode 100644 index 0000000..680b25d --- /dev/null +++ b/Libraries/CMSIS/Documentation/RTOS/html/structos_mutex_def__t.html @@ -0,0 +1,165 @@ + + + + +osMutexDef_t Struct Reference + + + + + + + + + + + + + +
    + +
    + + + + + + + + + + + +
    +
    CMSIS-RTOS +  Version 1.00 +
    +
    CMSIS-RTOS API: Generic RTOS interface for Cortex-M processor-based devices.
    +
    +
    + +
    + +
    + + + + +
    +
    + +
    +
    +
    + +
    +
    +
    +Data Fields
    +
    +
    osMutexDef_t Struct Reference
    +
    +
    + +

    Mutex Definition structure contains setup information for a mutex. + More...

    + + + + +

    +Data Fields

    uint32_t dummy
     dummy value.
    +

    Description

    +
    Note:
    CAN BE CHANGED: os_mutex_def is implementation specific in every CMSIS-RTOS.
    +

    Field Documentation

    + +
    +
    + + + + +
    uint32_t dummy
    +
    +
    + +
    +
    +
    +
    + + + + + diff --git a/Libraries/CMSIS/Documentation/RTOS/html/structos_pool_def__t.html b/Libraries/CMSIS/Documentation/RTOS/html/structos_pool_def__t.html new file mode 100644 index 0000000..da6aade --- /dev/null +++ b/Libraries/CMSIS/Documentation/RTOS/html/structos_pool_def__t.html @@ -0,0 +1,195 @@ + + + + +osPoolDef_t Struct Reference + + + + + + + + + + + + + +
    + +
    + + + + + + + + + + + +
    +
    CMSIS-RTOS +  Version 1.00 +
    +
    CMSIS-RTOS API: Generic RTOS interface for Cortex-M processor-based devices.
    +
    +
    + +
    + +
    + + + + +
    +
    + +
    +
    +
    + +
    +
    +
    +Data Fields
    +
    +
    osPoolDef_t Struct Reference
    +
    +
    + +

    Definition structure for memory block allocation. + More...

    + + + + + + + + +

    +Data Fields

    uint32_t pool_sz
     number of items (elements) in the pool
    uint32_t item_sz
     size of an item
    void * pool
     pointer to memory for pool
    +

    Description

    +
    Note:
    CAN BE CHANGED: os_pool_def is implementation specific in every CMSIS-RTOS.
    +

    Field Documentation

    + +
    +
    + + + + +
    uint32_t item_sz
    +
    +
    + +
    +
    + +
    +
    + + + + +
    void* pool
    +
    +
    + +
    +
    + +
    +
    + + + + +
    uint32_t pool_sz
    +
    +
    + +
    +
    +
    +
    + + + + + diff --git a/Libraries/CMSIS/Documentation/RTOS/html/structos_semaphore_def__t.html b/Libraries/CMSIS/Documentation/RTOS/html/structos_semaphore_def__t.html new file mode 100644 index 0000000..5cbc4e6 --- /dev/null +++ b/Libraries/CMSIS/Documentation/RTOS/html/structos_semaphore_def__t.html @@ -0,0 +1,165 @@ + + + + +osSemaphoreDef_t Struct Reference + + + + + + + + + + + + + +
    + +
    + + + + + + + + + + + +
    +
    CMSIS-RTOS +  Version 1.00 +
    +
    CMSIS-RTOS API: Generic RTOS interface for Cortex-M processor-based devices.
    +
    +
    + +
    + +
    + + + + +
    +
    + +
    +
    +
    + +
    +
    +
    +Data Fields
    +
    +
    osSemaphoreDef_t Struct Reference
    +
    +
    + +

    Semaphore Definition structure contains setup information for a semaphore. + More...

    + + + + +

    +Data Fields

    uint32_t dummy
     dummy value.
    +

    Description

    +
    Note:
    CAN BE CHANGED: os_semaphore_def is implementation specific in every CMSIS-RTOS.
    +

    Field Documentation

    + +
    +
    + + + + +
    uint32_t dummy
    +
    +
    + +
    +
    +
    +
    + + + + + diff --git a/Libraries/CMSIS/Documentation/RTOS/html/structos_thread_def__t.html b/Libraries/CMSIS/Documentation/RTOS/html/structos_thread_def__t.html new file mode 100644 index 0000000..83b9709 --- /dev/null +++ b/Libraries/CMSIS/Documentation/RTOS/html/structos_thread_def__t.html @@ -0,0 +1,210 @@ + + + + +osThreadDef_t Struct Reference + + + + + + + + + + + + + +
    + +
    + + + + + + + + + + + +
    +
    CMSIS-RTOS +  Version 1.00 +
    +
    CMSIS-RTOS API: Generic RTOS interface for Cortex-M processor-based devices.
    +
    +
    + +
    + +
    + + + + +
    +
    + +
    +
    +
    + +
    +
    +
    +Data Fields
    +
    +
    osThreadDef_t Struct Reference
    +
    +
    + +

    Thread Definition structure contains startup information of a thread. + More...

    + + + + + + + + + + +

    +Data Fields

    os_pthread pthread
     start address of thread function
    osPriority tpriority
     initial thread priority
    uint32_t instances
     maximum number of instances of that thread function
    uint32_t stacksize
     stack size requirements in bytes; 0 is default stack size
    +

    Description

    +
    Note:
    CAN BE CHANGED: os_thread_def is implementation specific in every CMSIS-RTOS.
    +

    Field Documentation

    + +
    +
    + + + + +
    uint32_t instances
    +
    +
    + +
    +
    + +
    +
    + + + + +
    os_pthread pthread
    +
    +
    + +
    +
    + +
    +
    + + + + +
    uint32_t stacksize
    +
    +
    + +
    +
    + +
    +
    + + + + +
    osPriority tpriority
    +
    +
    + +
    +
    +
    +
    + + + + + diff --git a/Libraries/CMSIS/Documentation/RTOS/html/structos_timer_def__t.html b/Libraries/CMSIS/Documentation/RTOS/html/structos_timer_def__t.html new file mode 100644 index 0000000..b84eaf1 --- /dev/null +++ b/Libraries/CMSIS/Documentation/RTOS/html/structos_timer_def__t.html @@ -0,0 +1,165 @@ + + + + +osTimerDef_t Struct Reference + + + + + + + + + + + + + +
    + +
    + + + + + + + + + + + +
    +
    CMSIS-RTOS +  Version 1.00 +
    +
    CMSIS-RTOS API: Generic RTOS interface for Cortex-M processor-based devices.
    +
    +
    + +
    + +
    + + + + +
    +
    + +
    +
    +
    + +
    +
    +
    +Data Fields
    +
    +
    osTimerDef_t Struct Reference
    +
    +
    + +

    Timer Definition structure contains timer parameters. + More...

    + + + + +

    +Data Fields

    os_ptimer ptimer
     start address of a timer function
    +

    Description

    +
    Note:
    CAN BE CHANGED: os_timer_def is implementation specific in every CMSIS-RTOS.
    +

    Field Documentation

    + +
    +
    + + + + +
    os_ptimer ptimer
    +
    +
    + +
    +
    +
    +
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zuk3u$kxXnTo70I%+IFi6>2=*7t&%oemp+t17iCKr>lv1jV(En*a8!T+!)url(l7zE zh^!)Yn}%(V`%Fiia%)8fx%SGE^w}E^+Z^Z7lRG9)?T#3-b(C$AQ5;XTe2N_x-AD}< zbU0)M=XE=}hhNJdzFTWH)$_6xT%RFy1^z-41IS{{ryBt*sKf>MrwQUne-_(kl@nf< zDfvUdMP^Ca$1XxhS;g&f#Npz6+dm%W;z82!KlK7zE?vyW#wFYcg82+{&_vg=WN(m| zKOpc$O>Ga4)|0@EH}CJxi*}oO)q)5LJ*r^<9FA|^! zIL=_V5(lFr#JxPg+Rk!U>l5ZW?voUEB_S1l(!nLK)zunPd(sj-$1P?Qc!__J)fES+ zeB{(LGXUGRBN#+)vT0%Zc=UraB-@8y5JeHg={`wkF7@Rr)4^Ru$S%=W6p-1J7R@Vs zCJT03y)EMrE;gPiz$l#D$}7AbY!%+ z0#;xL5yqM2Uy9njcKTYd-frsqp^((~0bL8uuGalEDydA^3c>G{P=E~&k}ZErf4S>W98FyTf@AR_f-^tDm + +
    + + + + + + + + + + + +
    +
    CMSIS-SVD +  Version 1.10 +
    +
    CMSIS System View Description
    +
    +
    + +     + + + + +
    + +
    +
    +
    + +
    +
    +
    +
    Cluster Level (New)
    +
    SVD Extension in Version 1.1
    +
    +

    Cluster adds a new and optional sub-level to the CMSIS SVD registers level. A cluster describes a sequence of registers within a peripheral. A cluster has an base offset relative to the base address of the peripheral. All registers within a cluster specify their address offset relative to the cluster base address. Register and cluster sections can occur in an arbitrary order. This feature, targeted at the generation of device header files, is useful to create a C data structure within the peripheral structure type, rather than describing all registers of a peripheral in a flat structure.

    +
    +
    +<registers> 
        <cluster derivedFrom=identifierType>
+    
+        <!-- dimElementGroup --> 
+        <dim>scaledNonNegativeInteger</dim>
+        <dimIncrement>scaledNonNegativeInteger</dimIncrement>
+        <dimIndex>dimIndexType</dimIndex>
+        <!-- end of dimElementGroup --> 
+    
+        <name>identifierType</name>
+        <description>xs:string</description>
+    
+        <headerStructName>identifierType</headerStructName>
+        <alternateCluster>identifierType</alternateCluster>
+    
+        <addressOffset>scaledNonNegativeInteger</addressOffset>
            <register>
+            ...
+        </register>
+    </cluster>
+    ...
+    <register>
+        ...
+    </register>
+    <cluster>
+        ...
+    </cluster>
+     
+<registers> 
+
    + + + + + + + + + + + + + + + + + + + + + + + + +
    Attribute Name Description Type Occurrence
    derivedFrom Specifies the name of the cluster from which to inherit the data. Elements being specified underneath will override the inherited values.
    +Remarks: When deriving a cluster, it is mandatory to specify at least the name, the description, and the addressOffset.     		registerType 0..1
    Element Name Description Type Occurrence
    See dimElementGroup for details.
    dimIncrement The value defines the number of elements in an array of clusters. scaledNonNegativeInteger 1..1
    dimIncrement If dim is specified, this element becomes mandatory. The element specifies the address increment in between two neighboring clusters of the cluster array in the address map. scaledNonNegativeInteger 1..1
    dimIndex Specifies the substrings that replaces the [%s] placeholder within the cluster name. By default, the index is a decimal value starting with 0 for the first cluster element. dimIndexType 0..1
    name String that identifies the cluster. Register names are required to be unique within the scope of a peripheral. Specify [%s] for generating an array in the device header file. identifierType 1..1
    description String describing the details of the register. xs:string 0..1
    alternateCluster This tag needs to specify the name of the original description of the register sequence if this cluster provides an alternative description. Otherwise the SVDConv will issue errors. identifierType 0..1
    headerStructName This tag specifies the struct type name in the device header file. If not specified, then the name of the cluster will be used. identifierType 0..1
    addressOffset Value defining the cluster address relative to the baseAddress defined by the peripheral of the register. scaledNonNegativeInteger 1..1
    +

    +Example:

    +
    <cluster>
+    <dim>4</dim>
+        <dimIncrement>8</dimIncrement>
+        <dimIndex>0-3</dimIndex>
+    <name>TX[%s]</name>
+    <description>Grouping of Transfer data and address</description>
+    <addressOffset>0x40</addressOffset>
+    <register>
+            <name>TX_DATA</name>
+        ...
+            <addressOffset>0x0</addressOffset>
+        ...
+    </register>
+    <register>
+            <name>TX_ADDR</name>
+        ...
+            <addressOffset>0x4</addressOffset>
+        ...
+    </register>
+</cluster>
+

    The example above describes an array of type TX with 4 elements. TX is a cluster of two consecutive registers with 4 elements. The device header file looks like this:

    +
    typedef struct {
+    ...
+    struct {
+       __IO uint32_t  TX_DATA;
+       __IO uint32_t  TX_ADDR;
+    } TX[4];
+    ...
+} ..._Type;
+
    +
    + + + + + diff --git a/Libraries/CMSIS/Documentation/SVD/html/group__cpu_section__gr.html b/Libraries/CMSIS/Documentation/SVD/html/group__cpu_section__gr.html new file mode 100644 index 0000000..ccc93af --- /dev/null +++ b/Libraries/CMSIS/Documentation/SVD/html/group__cpu_section__gr.html @@ -0,0 +1,152 @@ + + + + +CPU Section (New) + + + + + + + + + + + +
    + +
    + + + + + + + + + + + +
    +
    CMSIS-SVD +  Version 1.10 +
    +
    CMSIS System View Description
    +
    +
    + +
    + +
    + + + +
    +
    + +
    +
    +
    + +
    +
    +
    +
    CPU Section (New)
    +
    SVD Extension in Version 1.1
    +
    +

    The CPU section describes the processor included in the microcontroller device. This section is mandatory if the SVD file shall be used for the device header file generation.

    +
    +<cpu>
+    <name>cpuNameType<name>
+    <revision>revisionType<revision>
+    <endian>endianType<endian>
+    <mpuPresent>xs:boolean<mpuPresent>
+    <fpuPresent>xs:boolean<fpuPresent>
+    <nvicPrioBits>scaledNonNegativeInteger<nvicPrioBits>
+    <vendorSystickConfig>xs:boolean<vendorSystickConfig>
+</cpu>
+
    + + + + + + + + + + + + + + + + +
    Element Name Description Type Occurrence
    name The predefined tokens are:
      +
    • CM0: ARM Cortex-M0
      • +
    • CM0PLUS: ARM Cortex-M0+
      • +
    • CM3: ARM Cortex-M3
      • +
    • CM4: ARM Cortex-M4
      • +
    • SC000: ARM Secure Core SC000
      • +
    • SC300: ARM Secure Core SC300
      • +
    • other: other processor architectures
      • +
    +    		cpuNameType 1..1
    revisionType Defines the HW revision of the processor. The defined version format is rNpM (N,M = [0 - 9]). revisionType 1..1
    endian Defines the endianess of the processor being one of:
      +
    • little: little endian memory (least significant byte gets allocated at the lowest address).
      • +
    • big: byte invariant big endian data organization (most significant byte gets allocated at the lowest address).
      • +
    • selectable: little and big endian are configurable for the device and become active after the next reset.
      • +
    • other: the endianess is neither little nor big endian.
      • +
    +    		endianType 1..1
    mpuPresent Indicates that the processor is equipped with a memory protection unit (MPU). This tag is either set to true or false, 1 or 0. boolean 1..1
    fpuPresent Indicates that the processor is equipped with a hardware floating point unit (FPU). Cortex-M4 is the only available Cortex-M processor with an optional FPU. This tag is either set to true or false, 1 or 0. boolean 1..1
    nvicPrioBits Defines the number of bits that are available in the Nested Vectored Interrupt Controller (NVIC) for configuring the priority. scaledNonNegativeInteger 1..1
    vendorSystickConfig Indicates whether the processor implements a vendor-specific System Tick Timer. If false, then the ARM defined System Tick Timer is available. If true, then a vendor-specific System Tick Timer must be implemented. This tag is either set to true or false, 1 or 0. boolean 1..1
    +

    +Example:

    +
    ...
+<cpu>
+    <name>CM4</name> 
+    <revision>r0p0</revision>
+    <endian>little</endian>
+    <mpuPresent>true</mpuPresent>
+    <fpuPresent>true</fpuPresent>
+    <nvicPrioBits>4</nvicPrioBits>
+    <vendorSystickConfig>false</vendorSystickConfig> 
+</cpu>  
+...
+

    This example describes a Cortex-M4 core of HW revision r0p0, with fixed little endian memory scheme, including Memory Protection Unit and hardware Floating Point Unit. The Nested Vectored Interrupt Controller uses 4 bits for configuring the priority of an interrupt. It is equipped with the standard System Tick Timer as defined by ARM.

    +
    +
    + + + + + diff --git a/Libraries/CMSIS/Documentation/SVD/html/group__device_section_extensions__gr.html b/Libraries/CMSIS/Documentation/SVD/html/group__device_section_extensions__gr.html new file mode 100644 index 0000000..b7d27f4 --- /dev/null +++ b/Libraries/CMSIS/Documentation/SVD/html/group__device_section_extensions__gr.html @@ -0,0 +1,154 @@ + + + + +Extensions to the Device Section + + + + + + + + + + + +
    + +
    + + + + + + + + + + + +
    +
    CMSIS-SVD +  Version 1.10 +
    +
    CMSIS System View Description
    +
    +
    + +
    + +
    + + + +
    +
    + +
    +
    +
    + +
    +
    +
    +
    Extensions to the Device Section
    +
    SVD Extension in Version 1.1
    +
    +

    A number of elements have been added to the device section. These elements are optional but are highly recommended to enable the generation of consistent and CMSIS-compliant device header files from SVD descriptions.

    +
    +<device schemaVersion="xs:decimal" xmlns:xs="http://www.w3.org/2001/XMLSchema-instance" xs:noNamespaceSchemaLocation="CMSIS-SVD_Schema_1_1.xsd">
+    <vendor>stringType</vendor>
+    <vendorID>stringType</vendorID>
+    <name>identifierType</name>
+    <series>stringType</series>
+    <version>xs:string</version>
+    <description>xs:string</description>
+    <licenseText>xs:string</licenseText>
+    <cpu>cpuType</cpu>
+    <headerSystemFilename>identifierType</headerSystemFilename>
+    <headerDefinitionsPrefix>identifierType</headerDefinitionsPrefix>
+
+    ...
+</device>
+
+
    + + + + + + + + + + + + + + +
    Element Name Description Type Occurrence
    vendor This specifies the vendor of the device using the full name. stringType 0..1
    vendorID This specifies the vendor of the device using the vendor abbreviation that does not contain any spaces or special characters. This information shall be used for defining the directory. stringType 0..1
    series This element specifies the name of the device series. stringType 0..1
    licenseText The content of this tag will be copied into the header section of the generated device header file and shall contain the legal disclaimer. New lines can be inserted by using "\n". This section is mandatory if the SVD file shall be used for generating the device header file. stringType 0..1
    headerSystemFilename This tag specifies the file name (without extension) of the device-specific system include file (system_<device>.h; See CMSIS-Core description). This tag is used by the header file generator for customizing the include statement referencing the CMSIS system file within the CMSIS device header file. By default, the filename is "<kbd>system_<i>device:name</i>.h". In cases where a device series shares a single system header file, the name of the series shall be used instead of the individual device name. identifierType 0..1
    headerDefinitionsPrefix The element specifies the string being prepended to all type definition names generated in the CMSIS-Core device header file. This is used if the silicon vendor's software requires vendor-specific types in order to avoid name clashes with other definied types. identifierType 0..1
    +

    +Example:

    +
    ...
+<device schemaVersion="1.1" xmlns:xs="http://www.w3.org/2001/XMLSchema-instance" xs:noNamespaceSchemaLocation="CMSIS-SVD_Schema_1_1.xsd">
+    <vendor>Advanced RISC Machines</vendor>
+    <vendorID>ARM</vendorID>
+    ...
+    <series>ARMCM3</series>
+    ...
+    <licenseText>
+    ARM Limited (ARM) is supplying this software for use with Cortex-M \n
+    processor based microcontrollers.  This file can be freely distributed \n
+    within development tools that are supporting such ARM based processors. \n
+    \n
+    THIS SOFTWARE IS PROVIDED "AS IS".  NO WARRANTIES, WHETHER EXPRESS, IMPLIED \n
+    OR STATUTORY, INCLUDING, BUT NOT LIMITED TO, IMPLIED WARRANTIES OF \n
+    MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE APPLY TO THIS SOFTWARE. \n
+    ARM SHALL NOT, IN ANY CIRCUMSTANCES, BE LIABLE FOR SPECIAL, INCIDENTAL, OR \n
+    CONSEQUENTIAL DAMAGES, FOR ANY REASON WHATSOEVER.
+    </licenseText>
+    ...
+    <headerSystemFilename>system_ARMCM4</headeSystemFilename>
+    <headerDefinitionsPrefix>ARM_</headerDefinitionsPrefix>
+    ...
+</device>       
+...
+

    This example describes a device from the vendor Advanced RISC Machines using ARM as short name. The device belongs to the device family identified by ARMCM4. The legal disclaimer in the header files generated from this description is captured and formatted in accordance to the standard ARM CMSIS disclaimer. The CMSIS system file included by the generated device header file is named system_ARMCM4.h and all type definitions will be prepended with ARM_.

    +
    +
    + + + + + diff --git a/Libraries/CMSIS/Documentation/SVD/html/group__dim_element_group__gr.html b/Libraries/CMSIS/Documentation/SVD/html/group__dim_element_group__gr.html new file mode 100644 index 0000000..db637ac --- /dev/null +++ b/Libraries/CMSIS/Documentation/SVD/html/group__dim_element_group__gr.html @@ -0,0 +1,125 @@ + + + + +dimElementGroup + + + + + + + + + + + +
    + +
    + + + + + + + + + + + +
    +
    CMSIS-SVD +  Version 1.10 +
    +
    CMSIS System View Description
    +
    +
    + +
    + +
    + + + +
    +
    + +
    +
    +
    + +
    +
    +
    +
    dimElementGroup
    +
    Element Groups
    +
    +

    The SVD specification supports the array-of-registers concept. The single register description gets duplicated automatically into an array. The size of the array is specified by the <dim> element. The register names can be composed by the register name and an index-specific substring defined in <dimIndex>. The <dimIncrement> specifies the address offset between two registers. The elements below can be used to generate an array of registers.

    + + + + + + + + + +
    Element Name Description Type Occurrence
    dim The value defines the number of elements in an array of registers. scaledNonNegativeInteger 1..1
    dimIncrement If dim is specified, this element becomes mandatory. The element specifies the address increment in between two neighboring registers of the register array in the address map. scaledNonNegativeInteger 1..1
    dimIndex Specifies the substrings that replaces the s placeholder within the register name. By default, the index is a decimal value starting with 0 for the first register. dimIndexType 0..1
    +

    +Examples:

    +
    ...
+<register>
+    <dim>6</dim> 
+    <dimIncrement>4</dimIncrement> 
+    <dimIndex>A,B,C,D,E,Z</dimIndex> 
+    <name>GPIO_%s_CTRL</name> 
+...
+</register>
+

    The code above generates: => GPIO_A_CTRL, GPIO_B_CTRL, GPIO_C_CTRL, GPIO_D_CTRL, GPIO_E_CTRL, GPIO_Z_CTRL

    +
    ...
+<register>
+    <dim>4</dim> 
+    <dimIncrement>4</dimIncrement> 
+    <dimIndex>3-6</dimIndex> 
+    <name>IRQ%s</name> 
+...
+</register>
+

    The example above generates: => IRQ3, IRQ4, IRQ5, IRQ6

    +
    +
    + + + + + diff --git a/Libraries/CMSIS/Documentation/SVD/html/group__elem__type__gr.html b/Libraries/CMSIS/Documentation/SVD/html/group__elem__type__gr.html new file mode 100644 index 0000000..d66187a --- /dev/null +++ b/Libraries/CMSIS/Documentation/SVD/html/group__elem__type__gr.html @@ -0,0 +1,102 @@ + + + + +Element Groups + + + + + + + + + + + +
    + +
    + + + + + + + + + + + +
    +
    CMSIS-SVD +  Version 1.10 +
    +
    CMSIS System View Description
    +
    +
    + +
    + +
    + + + +
    +
    + +
    +
    +
    + +
    +
    +
    +Modules
    +
    +
    Element Groups
    +
    +
    + + + + +

    +Modules

     dimElementGroup
     registerPropertiesGroup
    +
    +
    + + + + + diff --git a/Libraries/CMSIS/Documentation/SVD/html/group__peripheral_section_extensions__gr.html b/Libraries/CMSIS/Documentation/SVD/html/group__peripheral_section_extensions__gr.html new file mode 100644 index 0000000..94dc75e --- /dev/null +++ b/Libraries/CMSIS/Documentation/SVD/html/group__peripheral_section_extensions__gr.html @@ -0,0 +1,121 @@ + + + + +Extensions to the Peripheral Section + + + + + + + + + + + +
    + +
    + + + + + + + + + + + +
    +
    CMSIS-SVD +  Version 1.10 +
    +
    CMSIS System View Description
    +
    +
    + +
    + +
    + + + +
    +
    + +
    +
    +
    + +
    +
    +
    +
    Extensions to the Peripheral Section
    +
    SVD Extension in Version 1.1
    +
    +

    The following elements have been added to the peripheral section. All new elements are optional but are highly recommended to enable the generation of consistent and CMSIS-compliant device header files from SVD descriptions.

    + + + + + + + +
    Element Name Description Type Occurrence
    alternatePeripheral All address blocks in the memory space of a device are assigned to a unique peripheral by default. If there are multiple peripherals describing the same address blocks, this needs to be specified explicitly. A peripheral redefining an address block needs to specify the name of the peripheral that is listed first in the description. If no alternate peripheral is specified, then the SVDConv utility will generate errors. identifierType 0..1
    headerStructName The header file generator uses the name of a peripheral as the base name for the C structure type. If this element is specfied, then this string is used instead of the peripheral name. This is particularly useful when multiple peripherals get derived from a peripheral description and a generic type name shall be used. identifierType 0..1
    +

    +Example:

    +
    <peripheral>
+  <name>Timer1</name>
+  <version>1.0</version>
+  <description>Timer 1 is a standard timer ... </description>
+  <baseAddress>0x40002000</baseAddress>
+  ...
+</peripheral>
+<peripheral>
+  <name>Timer1_Alt</name>
+  <version>1.0</version>
+  <description>Alternate Timer 1 is a special timer execution mode ... </description>
+  <baseAddress>0x40002000</baseAddress>
+  <alternatePeripheral>Timer1</alternatePeripheral>
+  ...
+</peripheral>
+

    Two timer peripheral descriptions are specified for the same memory block. No redefined addresses will be reported for both peripherals.

    +
    +
    + + + + + diff --git a/Libraries/CMSIS/Documentation/SVD/html/group__register_properties_group__gr.html b/Libraries/CMSIS/Documentation/SVD/html/group__register_properties_group__gr.html new file mode 100644 index 0000000..e1b2272 --- /dev/null +++ b/Libraries/CMSIS/Documentation/SVD/html/group__register_properties_group__gr.html @@ -0,0 +1,116 @@ + + + + +registerPropertiesGroup + + + + + + + + + + + +
    + +
    + + + + + + + + + + + +
    +
    CMSIS-SVD +  Version 1.10 +
    +
    CMSIS System View Description
    +
    +
    + +
    + +
    + + + +
    +
    + +
    +
    +
    + +
    +
    +
    +
    registerPropertiesGroup
    +
    Element Groups
    +
    +

    Register properties can be set on device, peripheral, and register level. Element values defined on a lower level overwrite element values defined on a more general level. For example, the register-level.<size> will overwrite peripheral-level.<size>. Elements that have not been defined on a more general level, must be defined at register level at the latest.

    + + + + + + + + + + + +
    Element Name Description Type Occurrence
    size Defines the default bit-width of any register contained in the device (implicit inheritance). This element can be redefined on any lower level of the description using the size element there. scaledNonNegativeInteger 0..1
    access Defines the default access rights for all registers. Access rights can be redefined on any lower level of the description using the access element there.
    +
    + The predefined tokens are:
      +
    • read-only: read access is permitted. Write operations have an undefined result.
      • +
    • write-only: write access is permitted. Read operations have an undefined result.
      • +
    • read-write: both read and write accesses are permitted. Writes affect the state of the register and reads return a value related to the register.
      • +
    • writeOnce: only the first write after reset has an effect on the register. Read operations deliver undefined results.
      • +
    • read-writeOnce: Read operations deliver a result related to the register content. Only the first write access to this register after a reset will have an effect on the register content.
      • +
    +    		accessType 0..1
    resetValue Defines the default value for all registers at RESET. The default register value can be redefined on any lower level using the resetValue element there. The actual reset value is calculated from the resetValue and the resetMask. The mask is used to specify bits with an undefined reset value. scaledNonNegativeInteger 0..1
    resetMask Identifies which register bits have a defined reset value. These bit positions are set to one. Bit positions with an undefined reset value are set to zero. scaledNonNegativeInteger 0..1
    +
    +
    + + + + + diff --git a/Libraries/CMSIS/Documentation/SVD/html/group__register_section_extensions__gr.html b/Libraries/CMSIS/Documentation/SVD/html/group__register_section_extensions__gr.html new file mode 100644 index 0000000..65a0520 --- /dev/null +++ b/Libraries/CMSIS/Documentation/SVD/html/group__register_section_extensions__gr.html @@ -0,0 +1,151 @@ + + + + +Extensions to the Register Section + + + + + + + + + + + +
    + +
    + + + + + + + + + + + +
    +
    CMSIS-SVD +  Version 1.10 +
    +
    CMSIS System View Description
    +
    +
    + +
    + +
    + + + +
    +
    + +
    +
    +
    + +
    +
    +
    +
    Extensions to the Register Section
    +
    SVD Extension in Version 1.1
    +
    +

    The following elements have been added to the register section. All new elements are optional.

    + + + + + + + +
    Element Name Description Type Occurrence
    alternateRegister This tag can reference a register that has been defined above to current location in the description and that describes the memory location already. This tells the SVDConv's address checker that the redefinition of this particular register is intentional. The register name needs to be unique within the scope of the current peripheral. A register description is defined either for a unique address location or could be a redefinition of an already described address. In the latter case, the register can be either marked alternateRegister and needs to have a unique name, or it can have the same register name but is assigned to a register subgroup through the tag alternateGroup (specified in version 1.0). identifierType 0..1
    dataType It can be useful to assign a specific native C datatype to a register. This helps avoiding type casts. For example, if a 32 bit register shall act as a pointer to a 32 bit unsigned data item, then dataType can be set to "uint32_t *". The following simple data types are predefined:
      +
    • uint8_t: unsigned byte
      • +
    • uint16_t: unsigned half word
      • +
    • uint32_t: unsigned word
      • +
    • uint64_t: unsigned double word
      • +
    • int8_t: signed byte
      • +
    • int16_t: signed half word
      • +
    • int32_t: signed world
      • +
    • int64_t: signed double word
      • +
    • uint8_t *: pointer to unsigned byte
      • +
    • uint16_t *: pointer to unsigned half word
      • +
    • uint32_t *: pointer to unsigned word
      • +
    • uint64_t *: pointer to unsigned double word
      • +
    • int8_t *: pointer to signed byte
      • +
    • int16_t *: pointer to signed half word
      • +
    • int32_t *: pointer to signed world
      • +
    • int64_t *: pointer to signed double word
      • +
    +    		dataTypeType 0..1
    +

    +Example:

    +
    ...
+<register>
+    <name>TIM_MODEA</name>
+    <description>In mode A this register acts as a reload value</description>
+    <addressOffset>0xC</addressOffset>
+</register>
+<register>
+    <name>TIM_MODEB</name>
+    <description>In mode B this register acts as the compare value</description>
+    <alternateRegister>TIM_MODEA</alternateRegister>
+    <addressOffset>0xC</addressOffset>
+</register>     
+<register>
+    <name>DMA_DATA</name>
+    <description>This register contains the address of the data being transferred</description>
+    <dataType>uint32_t *</dataType>
+    <addressOffset>0xf0</addressOffset>
+</register>     
+...
+

    This example describes two registers, TIM_MODEA and TIM_MODEB. Both have the same address offset. Based on the configured operation model being A or B, the register acts as reload or compare value. The register DMA_DATA is specified as a pointer to unsigned word data. The code generated for the device header file is:

    +
    typedef struct {
+  union {
+    __IO   uint32_t TIM_MODEA;
+    __IO   uint32_t TIM_MODEB;
+        };
+  __IO uint32_t * DMA_DATA; 
+  ...
+} <peripheral:name>_Type;
+
    +
    + + + + + diff --git a/Libraries/CMSIS/Documentation/SVD/html/group__schema__1__1__gr.html b/Libraries/CMSIS/Documentation/SVD/html/group__schema__1__1__gr.html new file mode 100644 index 0000000..e47cb52 --- /dev/null +++ b/Libraries/CMSIS/Documentation/SVD/html/group__schema__1__1__gr.html @@ -0,0 +1,603 @@ + + + + +CMSIS-SVD Schema File Ver. 1.1 (draft) + + + + + + + + + + + +
    + +
    + + + + + + + + + + + +
    +
    CMSIS-SVD +  Version 1.10 +
    +
    CMSIS System View Description
    +
    +
    + +
    + +
    + + + +
    +
    + +
    +
    +
    + +
    +
    +
    +
    CMSIS-SVD Schema File Ver. 1.1 (draft)
    +
    +
    +
    <?xml version="1.0" encoding="UTF-8"?>
+<!-- 
+  @note    Copyright (C) 2011-2012 ARM Limited. All rights reserved.
+  @par
+   ARM Limited (ARM) is supplying this software for use with Cortex-M
+   processor based microcontroller, but can be equally used for other
+   suitable  processor architectures. This file can be freely distributed.
+   Modifications to this file shall be clearly marked.
+
+  @date: 12.03.2012
+
+  @par
+   THIS SOFTWARE IS PROVIDED "AS IS".  NO WARRANTIES, WHETHER EXPRESS, IMPLIED
+   OR STATUTORY, INCLUDING, BUT NOT LIMITED TO, IMPLIED WARRANTIES OF
+   MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE APPLY TO THIS SOFTWARE.
+   ARM SHALL NOT, IN ANY CIRCUMSTANCES, BE LIABLE FOR SPECIAL, INCIDENTAL, OR
+   CONSEQUENTIAL DAMAGES, FOR ANY REASON WHATSOEVER.
+
+  This is a draft for CMSIS-SVD version 1.1
+  For backward compatibility all additional tags have been made optional.
+  Extensions may be mandatory for successful device header file generation
+  Other changes are related to some restructuring of the schema.
+  
+  Note that the memory section has been removed since this would limit the
+  reuse of descriptions for a series of devices.
+ -->
+
+<xs:schema xmlns:xs="http://www.w3.org/2001/XMLSchema" elementFormDefault="qualified" attributeFormDefault="qualified" version="1.1">
+  <!-- stringType requires a none empty string of a least one character length -->
+  <xs:simpleType name="stringType">
+    <xs:restriction base="xs:string">
+      <xs:minLength value="1"/>
+    </xs:restriction>
+  </xs:simpleType>
+  <!-- cpuType specifies a selection of Cortex-M and Secure-Cores. This list will get extended as new processors are released -->
+  <xs:simpleType name="cpuNameType">
+    <xs:restriction base="xs:token">
+      <xs:enumeration value="CM0"/>
+      <xs:enumeration value="CM0PLUS"/>
+      <xs:enumeration value="CM0+"/>
+      <xs:enumeration value="SC000"/>
+      <xs:enumeration value="CM3"/>
+      <xs:enumeration value="SC300"/>
+      <xs:enumeration value="CM4"/>
+      <xs:enumeration value="other"/>
+    </xs:restriction>
+  </xs:simpleType>
+  <!-- revisionType specifies the CPU revision format as defined by ARM (rNpM) -->
+  <xs:simpleType name="revisionType">
+    <xs:restriction base="xs:string">
+      <xs:pattern value="r[0-9]p[0-9]"/>
+    </xs:restriction>
+  </xs:simpleType>
+  <!-- EndianType pre-defines the tokens for specifying the endianess of the device -->
+  <xs:simpleType name="endianType">
+    <xs:restriction base="xs:token">
+      <xs:enumeration value="little"/>
+      <xs:enumeration value="big"/>
+      <xs:enumeration value="selectable"/>
+      <xs:enumeration value="other"/>
+    </xs:restriction>
+  </xs:simpleType>
+  <!-- dataType pre-defines the tokens in line with CMSIS data type definitions -->
+  <xs:simpleType name="dataTypeType">
+    <xs:restriction base="xs:token">
+      <xs:enumeration value="uint8_t"/>
+      <xs:enumeration value="uint16_t"/>
+      <xs:enumeration value="uint32_t"/>
+      <xs:enumeration value="uint64_t"/>
+      <xs:enumeration value="int8_t"/>
+      <xs:enumeration value="int16_t"/>
+      <xs:enumeration value="int32_t"/>
+      <xs:enumeration value="int64_t"/>
+      <xs:enumeration value="uint8_t *"/>
+      <xs:enumeration value="uint16_t *"/>
+      <xs:enumeration value="uint32_t *"/>
+      <xs:enumeration value="uint64_t *"/>
+      <xs:enumeration value="int8_t *"/>
+      <xs:enumeration value="int16_t *"/>
+      <xs:enumeration value="int32_t *"/>
+      <xs:enumeration value="int64_t *"/>
+    </xs:restriction>
+  </xs:simpleType>
+  <!-- nvicPrioBitsType specifies the integer value range for the number of bits used in NVIC to encode priority levels -->
+  <xs:simpleType name="nvicPrioBitsType">
+    <xs:restriction base="xs:integer">
+      <xs:minInclusive value="2"/>
+      <xs:maxInclusive value="8"/>
+    </xs:restriction>
+  </xs:simpleType>
+  <!-- identifierType specifies the subset and sequence of characters used for specifying identifiers within the description. -->
+  <!-- this is particularly important as these are used in ANSI C Structures during the device header file generation -->
+  <xs:simpleType name="identifierType">
+    <xs:restriction base="xs:string">
+      <xs:pattern value="((%s)[_A-Za-z]{1}[_A-Za-z0-9]*)|([_A-Za-z]{1}[_A-Za-z0-9]*(\[%s\])?)|([_A-Za-z]{1}[_A-Za-z0-9]*(%s)?[_A-Za-z0-9]*)"/>
+    </xs:restriction>
+  </xs:simpleType>
+  <!-- enumerationNameType specifies the subset and sequence of characters used for specifying names of enumeratedValues. -->
+  <!-- this is particularly important as these are used in ANSI C Structures during the device header file generation -->
+  <xs:simpleType name="enumerationNameType">
+    <xs:restriction base="xs:string">
+      <xs:pattern value="[_A-Za-z0-9]*"/>
+    </xs:restriction>
+  </xs:simpleType>
+
+  <!-- dimIndexType specifies the subset and sequence of characters used for specifying the sequence of indices in register arrays -->
+  <xs:simpleType name="dimIndexType">
+    <xs:restriction base="xs:string">
+      <xs:pattern value="[0-9]+\-[0-9]+|[A-Z]-[A-Z]|[_0-9a-zA-Z]+(,\s*[_0-9a-zA-Z]+)+"/>
+    </xs:restriction>
+  </xs:simpleType>
+  <!-- scaledNonNegativeInteger specifies the format in which numbers are represented in hexadecimal or decimar format -->
+  <xs:simpleType name="scaledNonNegativeInteger">
+    <xs:restriction base="xs:string">
+      <xs:pattern value="[+]?(0x|0X|#)?[0-9a-fA-F]+[kmgtKMGT]?"/>
+    </xs:restriction>
+  </xs:simpleType>
+  <!-- enumeratedValueDataType specifies the number formats for the values in enumeratedValues -->
+  <xs:simpleType name="enumeratedValueDataType">
+    <xs:restriction base="xs:string">
+      <xs:pattern value="[+]?(0x|0X|#)?[0-9a-fxA-FX]+"/>
+    </xs:restriction>
+  </xs:simpleType>
+  <!-- accessType specfies the pre-defined tokens for the available accesses -->
+  <xs:simpleType name="accessType">
+    <xs:restriction base="xs:token">
+      <xs:enumeration value="read-only"/>
+      <xs:enumeration value="write-only"/>
+      <xs:enumeration value="read-write"/>
+      <xs:enumeration value="writeOnce"/>
+      <xs:enumeration value="read-writeOnce"/>
+    </xs:restriction>
+  </xs:simpleType>
+  <!-- modifiedWriteValuesType specifies the pre-defined tokens for the write side effects -->
+  <xs:simpleType name="modifiedWriteValuesType">
+    <xs:restriction base="xs:token">
+      <xs:enumeration value="oneToClear"/>
+      <xs:enumeration value="oneToSet"/>
+      <xs:enumeration value="oneToToggle"/>
+      <xs:enumeration value="zeroToClear"/>
+      <xs:enumeration value="zeroToSet"/>
+      <xs:enumeration value="zeroToToggle"/>
+      <xs:enumeration value="clear"/>
+      <xs:enumeration value="set"/>
+      <xs:enumeration value="modify"/>
+    </xs:restriction>
+  </xs:simpleType>
+  <!-- readAction type specifies the pre-defined tokens for read side effects -->
+  <xs:simpleType name="readActionType">
+    <xs:restriction base="xs:token">
+      <xs:enumeration value="clear"/>
+      <xs:enumeration value="set"/>
+      <xs:enumeration value="modify"/>
+      <xs:enumeration value="modifyExternal"/>
+    </xs:restriction>
+  </xs:simpleType>
+  <!-- enumUsageType specifies the pre-defined tokens for selecting what access types an enumeratedValues set is associated with -->
+  <xs:simpleType name="enumUsageType">
+    <xs:restriction base="xs:token">
+      <xs:enumeration value="read"/>
+      <xs:enumeration value="write"/>
+      <xs:enumeration value="read-write"/>
+    </xs:restriction>
+  </xs:simpleType>
+  <!-- bitRangeType specifies the bit numbers to be restricted values from 0 - 69 -->
+  <xs:simpleType name="bitRangeType">
+    <xs:restriction base="xs:token">
+      <xs:pattern value="\[([0-4])?[0-9]:([0-4])?[0-9]\]"/>
+    </xs:restriction>
+  </xs:simpleType>
+  <!-- writeContraintType specifies how to describe the restriction of the allowed values that can be written to a resource -->
+  <xs:complexType name="writeConstraintType">
+    <xs:choice>
+      <xs:element name="writeAsRead" type="xs:boolean"/>
+      <xs:element name="useEnumeratedValues" type="xs:boolean"/>
+      <xs:element name="range">
+        <xs:complexType>
+          <xs:sequence>
+            <xs:element name="minimum" type="scaledNonNegativeInteger"/>
+            <xs:element name="maximum" type="scaledNonNegativeInteger"/>
+          </xs:sequence>
+        </xs:complexType>
+      </xs:element>
+    </xs:choice>
+  </xs:complexType>
+  <!-- addressBlockType specifies the elements to describe an address block -->
+  <xs:complexType name="addressBlockType">
+    <xs:sequence>
+      <xs:element name="offset" type="scaledNonNegativeInteger"/>
+      <xs:element name="size" type="scaledNonNegativeInteger"/>
+      <xs:element name="usage">
+        <xs:simpleType>
+          <xs:restriction base="xs:token">
+            <xs:enumeration value="registers"/>
+            <xs:enumeration value="buffer"/>
+            <xs:enumeration value="reserved"/>
+          </xs:restriction>
+        </xs:simpleType>
+      </xs:element>
+    </xs:sequence>
+  </xs:complexType>
+  <!-- interruptType specifies how to describe an interrupt associated with a peripheral -->
+  <xs:complexType name="interruptType">
+    <xs:sequence>
+      <xs:element name="name" type="stringType"/>
+      <xs:element name="description" type="xs:string" minOccurs="0"/>
+      <xs:element name="value" type="xs:integer"/>
+    </xs:sequence>
+  </xs:complexType>
+  <!-- register properties group specifies register size, access permission and reset value 
+       this is used in multiple locations. Settings are inherited downstream. -->  
+  <xs:group name="registerPropertiesGroup">
+    <xs:sequence>
+      <xs:element name="size" type="scaledNonNegativeInteger" minOccurs="0"/>
+      <xs:element name="access" type="accessType" minOccurs="0"/>
+      <xs:element name="resetValue" type="scaledNonNegativeInteger" minOccurs="0"/>
+      <xs:element name="resetMask" type="scaledNonNegativeInteger" minOccurs="0"/>
+    </xs:sequence>
+  </xs:group>
+  <!-- bitRangeLsbMsbStyle specifies the bit position of a field within a register 
+       by specifying the least significant and the most significant bit position -->
+  <xs:group name="bitRangeLsbMsbStyle">
+    <xs:sequence>
+      <xs:element name="lsb"  type="scaledNonNegativeInteger"/>
+      <xs:element name="msb"  type="scaledNonNegativeInteger"/>
+    </xs:sequence>
+  </xs:group>
+  <!-- bitRangeOffsetWidthStyle specifies the bit position of a field within a register
+       by specifying the least significant bit position and the bitWidth of the field -->
+  <xs:group name="bitRangeOffsetWidthStyle">
+    <xs:sequence>
+      <xs:element name="bitOffset" type="scaledNonNegativeInteger"/>
+      <xs:element name="bitWidth" type="scaledNonNegativeInteger" minOccurs="0"/>   
+    </xs:sequence> 
+  </xs:group>
+  <!-- dimElementGroup specifies the number of array elements (dim), the address offset
+       between to consecutive array elements and an a comma seperated list of strings 
+       being used for identifying each element in the array -->
+  <xs:group name="dimElementGroup">
+    <xs:sequence>
+      <xs:element name="dim" type="scaledNonNegativeInteger"/>
+      <xs:element name="dimIncrement" type="scaledNonNegativeInteger"/>
+      <xs:element name="dimIndex" type="dimIndexType" minOccurs="0"/>
+    </xs:sequence>
+  </xs:group>
+
+  <xs:complexType name="cpuType">
+    <xs:sequence>
+      <!-- V1.1: ARM processor name: Cortex-Mx / SCxxx -->
+      <xs:element name="name" type="cpuNameType"/>
+      <!-- V1.1: ARM defined revision of the cpu -->
+      <xs:element name="revision" type="revisionType"/>
+      <!-- V1.1: Endian specifies the endianess of the processor/device -->
+      <xs:element name="endian" type="endianType"/>
+      <!-- V1.1: mpuPresent specifies whether or not a memory protection unit is physically present -->
+      <xs:element name="mpuPresent" type="xs:boolean"/>
+      <!-- V1.1: fpuPresent specifies whether or not a floating point hardware unit is physically present -->
+      <xs:element name="fpuPresent" type="xs:boolean"/>
+      <!-- V1.1: nvicPrioBits specifies the number of bits used by the Nested Vectored Interrupt Controller
+                   for defining the priority level = # priority levels -->
+      <xs:element name="nvicPrioBits" type="scaledNonNegativeInteger"/>
+      <!-- V1.1: vendorSystickConfig is set true if a custom system timer is implemented in the device 
+                   instead of the ARM specified SysTickTimer -->
+      <xs:element name="vendorSystickConfig" type="xs:boolean"/>
+    </xs:sequence>
+  </xs:complexType>
+
+  <xs:complexType name="enumeratedValuesType">
+    <xs:sequence>
+      <!-- name specfies a reference to this enumeratedValues section for reuse purposes
+           this name does not appear in the System Viewer nor the Header File. -->
+      <xs:element name="name" type="enumerationNameType" minOccurs="0"/>
+      <!-- usage specifies whether this enumeration is to be used for read or write or 
+                                                       (read and write) accesses -->
+      <xs:element name="usage" type="enumUsageType" minOccurs="0"/>
+      <!-- enumeratedValue derivedFrom=<identifierType> -->
+      <xs:element name="enumeratedValue" minOccurs="1" maxOccurs="unbounded">
+        <xs:complexType>
+          <xs:sequence>
+            <!-- name is a ANSI C indentifier representing the value (C Enumeration) -->
+            <xs:element name="name" type="enumerationNameType"/>
+            <!-- description contains the details about the semantics/behavior specified by this value -->
+            <xs:element name="description" type="stringType" minOccurs="0"/>
+            <xs:choice>
+              <xs:element name="value" type="enumeratedValueDataType"/>
+              <!-- isDefault specifies the name and description for all values that are not
+                   specifically described individually -->
+              <xs:element name="isDefault" type="xs:boolean"/>
+            </xs:choice>
+          </xs:sequence>
+        </xs:complexType>
+      </xs:element>
+    </xs:sequence>
+    <xs:attribute name="derivedFrom" type="identifierType" use="optional"/>
+  </xs:complexType>
+
+  <xs:complexType name="fieldType">
+    <xs:sequence>
+      <!-- name specifies a field's name. The System Viewer and the device header file will
+           use the name of the field as identifier -->
+      <xs:element name="name" type="identifierType"/>
+      <!-- description contains reference manual level information about the function and 
+           options of a field -->
+      <xs:element name="description" type="stringType" minOccurs="0"/>
+      <!-- alternative specifications of the bit position of the field within the register -->
+      <xs:choice minOccurs="1" maxOccurs="1">
+        <!-- bit field described by lsb followed by msb tag -->
+        <xs:group ref="bitRangeLsbMsbStyle"/>
+        <!-- bit field described by bit offset relative to Bit0 + bit width of field -->
+        <xs:group ref="bitRangeOffsetWidthStyle"/>
+        <!-- bit field described by [<msb>:<lsb>] -->
+        <xs:element name="bitRange" type="bitRangeType"/>
+      </xs:choice>
+      <!-- access describes the predefined permissions for the field. -->
+      <xs:element name="access" type="accessType" minOccurs="0"/>
+      <!-- predefined description of write side effects -->
+      <xs:element name="modifiedWriteValues" type="modifiedWriteValuesType" minOccurs="0"/>
+      <!-- writeContstraint specifies the subrange of allowed values -->
+      <xs:element name="writeConstraint" type="writeConstraintType" minOccurs="0"/>
+      <!-- readAction specifies the read side effects. -->
+      <xs:element name="readAction" type="readActionType" minOccurs="0"/>
+      <!-- enumeratedValues derivedFrom=<identifierType> -->
+      <xs:element name="enumeratedValues" type="enumeratedValuesType" minOccurs="0" maxOccurs="2">
+      </xs:element>
+    </xs:sequence>
+    <xs:attribute name="derivedFrom" type="identifierType" use="optional"/>
+  </xs:complexType>
+
+  <xs:complexType name="fieldsType">
+    <xs:sequence>
+      <!-- field derivedFrom=<identifierType> -->
+      <xs:element name="field" type="fieldType" minOccurs="1" maxOccurs="unbounded"/>
+    </xs:sequence>
+  </xs:complexType>
+
+  <xs:complexType name="registerType">
+    <xs:sequence>
+      <xs:group    ref="dimElementGroup" minOccurs="0"/>
+      <!-- name specifies the name of the register. The register name is used by System Viewer and
+                                     device header file generator to represent a register -->
+      <xs:element name="name" type="identifierType"/>
+      <!-- display name specifies a register name without the restritions of an ANSIS C identifier.
+                                     The use of this tag is discouraged because it does not allow consistency between
+                                     the System View and the device header file. -->
+      <xs:element name="displayName" type="stringType" minOccurs="0"/>
+      <!-- description contains a reference manual level description about the register and it's purpose -->
+      <xs:element name="description" type="stringType" minOccurs="0"/>
+      <xs:choice>
+        <!-- alternateGroup specifies the identifier of the subgroup a register belongs to.
+                                       This is useful if a register has a different description per mode but a single name -->
+        <xs:element name="alternateGroup" type="identifierType" minOccurs="0"/>
+        <!-- V1.1: alternateRegister specifies an alternate register description for an address that is
+                                       already fully described. In this case the register name must be unique within the peripheral -->
+        <xs:element name="alternateRegister" type="identifierType" minOccurs="0"/>
+      </xs:choice>
+      <!-- addressOffset describes the address of the register relative to the baseOffset of the peripheral -->
+      <xs:element name="addressOffset" type="scaledNonNegativeInteger"/>
+      <!-- registerPropertiesGroup elements specify the default values for register size, access permission and
+                                     reset value. These default values are inherited to all fields contained in this register -->
+      <xs:group    ref="registerPropertiesGroup" minOccurs="0"/>
+      <!-- V1.1: dataType specifies a CMSIS compliant native dataType for a register (i.e. signed, unsigned, pointer) -->
+      <xs:element name="dataType" type="dataTypeType" minOccurs="0"/>
+      <!-- modifiedWriteValues specifies the write side effects -->
+      <xs:element name="modifiedWriteValues" type="modifiedWriteValuesType" minOccurs="0"/>
+      <!-- writeConstraint specifies the subset of allowed write values -->
+      <xs:element name="writeConstraint" type="writeConstraintType" minOccurs="0"/>
+      <!-- readAcction specifies the read side effects -->
+      <xs:element name="readAction" type="readActionType" minOccurs="0"/>
+      <!-- fields section contains all fields that belong to this register -->
+      <xs:element name="fields" type="fieldsType" minOccurs="0" maxOccurs="1"/>
+    </xs:sequence>
+    <xs:attribute name="derivedFrom" type="identifierType" use="optional"/>
+  </xs:complexType>
+
+  <!-- V1.1: A cluster is a set of registers that are composed into a C data structure in the device header file -->
+  <xs:complexType name="clusterType">
+    <xs:sequence>
+      <xs:group   ref="dimElementGroup" minOccurs="0"/>
+      <xs:element name="name" type="identifierType"/>
+      <xs:element name="description" type="xs:string"/>
+      <!-- V1.1: alternateCluster specifies an alternative description for a cluster address range that is
+                 already fully described. In this case the cluster name must be unique within the peripheral -->
+      <xs:element name="alternateCluster" type="identifierType" minOccurs="0"/>
+      <!-- V1.1: headerStructName specifies the name for the cluster structure typedef
+                 used in the device header generation instead of the cluster name -->
+      <xs:element name="headerStructName" type="identifierType" minOccurs="0"/>
+      <xs:element name="addressOffset" type="scaledNonNegativeInteger"/>
+      <xs:element name="register" type="registerType" minOccurs="1" maxOccurs="unbounded"/>
+    </xs:sequence>
+    <xs:attribute name="derivedFrom" type="identifierType" use="optional"/>
+  </xs:complexType>
+
+  <!-- the registers section can have an arbitrary list of cluster and register sections -->
+  <xs:complexType name="registersType">
+    <xs:choice minOccurs="1" maxOccurs="unbounded">
+      <xs:element name="cluster" type="clusterType"/>
+      <xs:element name="register" type="registerType"/>
+    </xs:choice>
+  </xs:complexType>
+
+  <xs:complexType name="peripheralType">
+    <xs:sequence>
+      <!-- name specifies the name of a peripheral. This name is used for the System View and device header file -->
+      <xs:element name="name" type="xs:Name"/>
+      <!-- version specifies the version of the peripheral descriptions -->
+      <xs:element name="version" type="stringType" minOccurs="0"/>
+      <!-- description provides a high level functional description of the peripheral -->
+      <xs:element name="description" type="stringType" minOccurs="0"/>
+      <!-- V1.1: alternatePeripheral specifies an alternative description for an address range that is
+           already fully by a peripheral described. In this case the peripheral name must be unique within the device description -->
+      <xs:element name="alternatePeripheral" type="identifierType" minOccurs="0"/>
+      <!-- groupName assigns this peripheral to a group of peripherals. This is only used bye the System View -->
+      <xs:element name="groupName" type="xs:Name" minOccurs="0"/>
+      <!-- prependToName specifies a prefix that is placed in front of each register name of this peripheral. 
+                         The device header file will show the registers in a C-Struct of the peripheral without the prefix. -->
+      <xs:element name="prependToName" type="identifierType" minOccurs="0"/>
+      <!-- appendToName is a postfix that is appended to each register name of this peripheral. The device header 
+                         file will sho the registers in a C-Struct of the peripheral without the postfix -->
+      <xs:element name="appendToName" type="identifierType" minOccurs="0"/>
+      <!-- V1.1: headerStructName specifies the name for the peripheral structure typedef
+                         used in the device header generation instead of the peripheral name -->
+      <xs:element name="headerStructName" type="identifierType" minOccurs="0"/>
+      <!-- disableCondition contains a logical expression based on constants and register or bit-field values 
+                         if the condition is evaluated to true, the peripheral display will be disabled -->
+      <xs:element name="disableCondition" type="stringType" minOccurs="0"/>
+      <!-- baseAddress specifies the absolute base address of a peripheral. For derived peripherals it is mandatory
+                         to specify a baseAddress. -->
+      <xs:element name="baseAddress" type="scaledNonNegativeInteger"/>
+      <!-- registerPropertiesGroup elements specify the default values for register size, access permission and
+                         reset value. These default values are inherited to all registers contained in this peripheral -->
+      <xs:group ref="registerPropertiesGroup" minOccurs="0"/>
+      <!-- addressBlock specifies one or more address ranges that are assigned exclusively to this peripheral. 
+                         derived peripherals may have no addressBlock, however none-derived peripherals are required to specify
+                         at least one address block -->
+      <xs:element name="addressBlock" type="addressBlockType" minOccurs="0" maxOccurs="unbounded"/>
+      <!-- interrupt specifies can specify one or more interrtupts by name, description and value -->
+      <xs:element name="interrupt" type="interruptType" minOccurs="0" maxOccurs="unbounded"/>
+      <!-- registers section contains all registers owned by the peripheral. In case a peripheral gets derived it does
+                        not have its own registers section, hence this section is optional. A unique peripheral without a 
+                        registers section is not allowed -->
+      <xs:element name="registers" type="registersType" minOccurs="0" maxOccurs="1">
+      </xs:element>
+    </xs:sequence>
+    <xs:attribute name="derivedFrom" type="identifierType" use="optional"/>
+  </xs:complexType>
+  
+  <!-- ==================================================== -->
+  <!-- The top level element of a description is the device -->
+  <!-- ==================================================== -->
+  <xs:element name="device" nillable="true">
+    <xs:complexType>
+      <xs:sequence>
+        <!-- V1.1: Vendor Name -->
+        <xs:element name="vendor" type="stringType" minOccurs="0"/>
+        <!-- V1.1: Vendor ID - a short name for referring to the vendor (e.g. Texas Instruments = TI) -->
+        <xs:element name="vendorID" type="identifierType" minOccurs="0"/>
+        <!-- name specifies the device name being described -->
+        <xs:element name="name" type="identifierType"/>
+        <!-- V1.1: series specifies the device series or family name -->
+        <xs:element name="series" type="stringType" minOccurs="0"/>
+        <!-- version specifies the version of the device description -->
+        <xs:element name="version" type="stringType"/>
+        <!-- description is a string describing the device features (e.g. memory size, peripherals, etc.) -->
+        <xs:element name="description" type="stringType"/>
+        <!-- V1.1: licenseText specifies the file header section to be included in any derived file -->
+        <xs:element name="licenseText" type="stringType" minOccurs="0"/>
+        <!-- V1.1: cpu specifies the details of the processor included in the device -->
+        <xs:element name="cpu" type="cpuType" minOccurs="0"/>
+        <!-- V1.1: the tag specifies the filename without extension of the CMSIS System Device include file.
+             This tag is used by the header file generator for customizing the include statement referencing the
+             CMSIS system file within the CMSIS device header file. By default the filename is "system_<device.name>"
+             In cases a device series shares a single system header file, the name of the series shall be used 
+             instead of the individual device name. -->
+        <xs:element name="headerSystemFilename" type="identifierType" minOccurs="0"/>
+        <!-- V1.1: headerDefinitionPrefix specifies the string being prepended to all names of types defined in
+             generated device header file -->
+        <xs:element name="headerDefinitionsPrefix" type="identifierType" minOccurs="0"/>
+        <!-- addressUnitBits specifies the size of the minimal addressable unit in bits -->
+        <xs:element name="addressUnitBits" type="scaledNonNegativeInteger"/>
+        <!-- width specifies the number of bits for the maximum single transfer size allowed by the bus interface.
+             This sets the maximum size of a single register that can be defined for an address space -->
+        <xs:element name="width" type="scaledNonNegativeInteger"/>
+        <!-- registerPropertiesGroup elements specify the default values for register size, access permission and
+             reset value -->
+        <xs:group ref="registerPropertiesGroup" minOccurs="0"/>
+
+        <!-- peripherals is containing all peripherals -->
+        <xs:element name="peripherals">
+          <xs:complexType>
+            <xs:sequence>
+              <xs:element name="peripheral" type="peripheralType" minOccurs="1" maxOccurs="unbounded"/>
+            </xs:sequence>
+          </xs:complexType>
+        </xs:element>
+
+        <!-- Vendor Extensions: this section captures custom extensions. This section will be ignored by default -->
+        <xs:element name="vendorExtensions" minOccurs="0" maxOccurs="1">
+          <xs:complexType>
+            <xs:sequence>
+              <xs:any namespace="##any" processContents="lax" minOccurs="0" maxOccurs="unbounded">
+              </xs:any>
+            </xs:sequence>
+          </xs:complexType>
+        </xs:element>
+      </xs:sequence>
+      <xs:attribute name="schemaVersion" type="xs:decimal" use="required" fixed="1.1"/>
+    </xs:complexType>
+  </xs:element>
+</xs:schema>
+
    +
    + + + + + diff --git a/Libraries/CMSIS/Documentation/SVD/html/group__schema__gr.html b/Libraries/CMSIS/Documentation/SVD/html/group__schema__gr.html new file mode 100644 index 0000000..5715fe0 --- /dev/null +++ b/Libraries/CMSIS/Documentation/SVD/html/group__schema__gr.html @@ -0,0 +1,368 @@ + + + + +CMSIS-SVD Schema File Ver. 1.0 + + + + + + + + + + + +
    + +
    + + + + + + + + + + + +
    +
    CMSIS-SVD +  Version 1.10 +
    +
    CMSIS System View Description
    +
    +
    + +
    + +
    + + + +
    +
    + +
    +
    +
    + +
    +
    +
    +
    CMSIS-SVD Schema File Ver. 1.0
    +
    +
    +
    <?xml version="1.0" encoding="UTF-8"?>
+<!-- 
+  @date: 07.12.2011
+  @note    Copyright (C) 2011 ARM Limited. All rights reserved.
+  @par
+   ARM Limited (ARM) is supplying this software for use with Cortex-M
+   processor based microcontroller, but can be equally used for other
+   suitable  processor architectures. This file can be freely distributed.
+   Modifications to this file shall be clearly marked.
+
+  @par
+   THIS SOFTWARE IS PROVIDED "AS IS".  NO WARRANTIES, WHETHER EXPRESS, IMPLIED
+   OR STATUTORY, INCLUDING, BUT NOT LIMITED TO, IMPLIED WARRANTIES OF
+   MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE APPLY TO THIS SOFTWARE.
+   ARM SHALL NOT, IN ANY CIRCUMSTANCES, BE LIABLE FOR SPECIAL, INCIDENTAL, OR
+   CONSEQUENTIAL DAMAGES, FOR ANY REASON WHATSOEVER.
+ -->
+
+<xs:schema xmlns:xs="http://www.w3.org/2001/XMLSchema" elementFormDefault="qualified" attributeFormDefault="qualified" version="1.0">
+  
+  <xs:simpleType name="registerNameType">
+    <xs:restriction base="xs:string">
+      <xs:pattern value="((%s)[_A-Za-z]{1}[_A-Za-z0-9]*)|([_A-Za-z]{1}[_A-Za-z0-9]*(\[%s\])?)|([_A-Za-z]{1}[_A-Za-z0-9]*(%s)?[_A-Za-z0-9]*)"/>
+    </xs:restriction>
+  </xs:simpleType>
+
+  <xs:simpleType name="dimIndexType">
+    <xs:restriction base="xs:string">
+      <xs:pattern value="[0-9]+\-[0-9]+|[A-Z]-[A-Z]|[_0-9a-zA-Z]+(,\s*[_0-9a-zA-Z]+)+"/>
+    </xs:restriction>
+  </xs:simpleType>
+
+  <xs:simpleType name="scaledNonNegativeInteger">
+    <xs:restriction base="xs:string">
+      <xs:pattern value="[+]?(0x|0X|#)?[0-9a-fA-F]+[kmgtKMGT]?"/>
+    </xs:restriction>
+  </xs:simpleType>
+
+  <xs:simpleType name="enumeratedValueDataType">
+    <xs:restriction base="xs:string">
+      <xs:pattern value="[+]?(0x|0X|#)?[0-9a-fxA-FX]+"/>
+    </xs:restriction>
+  </xs:simpleType>
+
+  <xs:simpleType name="accessType">
+    <xs:restriction base="xs:token">
+      <xs:enumeration value="read-only"/>
+      <xs:enumeration value="write-only"/>
+      <xs:enumeration value="read-write"/>
+      <xs:enumeration value="writeOnce"/>
+      <xs:enumeration value="read-writeOnce"/>
+    </xs:restriction>
+  </xs:simpleType>
+
+  <xs:simpleType name="modifiedWriteValuesType">
+    <xs:restriction base="xs:token">
+      <xs:enumeration value="oneToClear"/>
+      <xs:enumeration value="oneToSet"/>
+      <xs:enumeration value="oneToToggle"/>
+      <xs:enumeration value="zeroToClear"/>
+      <xs:enumeration value="zeroToSet"/>
+      <xs:enumeration value="zeroToToggle"/>
+      <xs:enumeration value="clear"/>
+      <xs:enumeration value="set"/>
+      <xs:enumeration value="modify"/>
+    </xs:restriction>
+  </xs:simpleType>
+
+  <xs:simpleType name="readActionType">
+    <xs:restriction base="xs:token">
+      <xs:enumeration value="clear"/>
+      <xs:enumeration value="set"/>
+      <xs:enumeration value="modify"/>
+      <xs:enumeration value="modifyExternal"/>
+    </xs:restriction>
+  </xs:simpleType>
+
+  <xs:simpleType name="enumUsageType">
+    <xs:restriction base="xs:token">
+      <xs:enumeration value="read"/>
+      <xs:enumeration value="write"/>
+      <xs:enumeration value="read-write"/>
+    </xs:restriction>
+  </xs:simpleType>
+
+  <xs:simpleType name="bitRangeType">
+    <xs:restriction base="xs:token">
+      <xs:pattern value="\[([0-3])?[0-9]:([0-3])?[0-9]\]"/>
+    </xs:restriction>
+  </xs:simpleType>
+
+  <xs:complexType name="writeConstraintType">
+    <xs:choice>
+      <xs:element name="writeAsRead" type="xs:boolean"/>
+      <xs:element name="useEnumeratedValues" type="xs:boolean"/>
+      <xs:element name="range">
+        <xs:complexType>
+          <xs:sequence>
+            <xs:element name="minimum" type="scaledNonNegativeInteger"/>
+            <xs:element name="maximum" type="scaledNonNegativeInteger"/>
+          </xs:sequence>
+        </xs:complexType>
+      </xs:element>
+    </xs:choice>
+  </xs:complexType>
+
+  <xs:complexType name="addressBlockType">
+    <xs:sequence>
+      <xs:element name="offset" type="scaledNonNegativeInteger"/>
+      <xs:element name="size" type="scaledNonNegativeInteger"/>
+      <xs:element name="usage">
+        <xs:simpleType>
+          <xs:restriction base="xs:token">
+            <xs:enumeration value="registers"/>
+            <xs:enumeration value="buffer"/>
+            <xs:enumeration value="reserved"/>
+          </xs:restriction>
+        </xs:simpleType>
+      </xs:element>
+    </xs:sequence>
+  </xs:complexType>
+
+  <xs:complexType name="interruptType">
+    <xs:sequence>
+      <xs:element name="name" type="xs:string"/>
+      <xs:element name="value" type="xs:integer"/>
+    </xs:sequence>
+  </xs:complexType>
+
+  <xs:group name="registerPropertiesGroup">
+    <xs:sequence>
+      <xs:element name="size" type="scaledNonNegativeInteger" minOccurs="0"/>
+      <xs:element name="access" type="accessType" minOccurs="0"/>
+      <xs:element name="resetValue" type="scaledNonNegativeInteger" minOccurs="0"/>
+      <xs:element name="resetMask" type="scaledNonNegativeInteger" minOccurs="0"/>
+    </xs:sequence>
+  </xs:group>
+
+  <xs:group name="bitRangeLsbMsbStyle">
+    <xs:sequence>
+      <xs:element name="lsb"  type="scaledNonNegativeInteger"/>
+      <xs:element name="msb"  type="scaledNonNegativeInteger"/>
+    </xs:sequence>
+  </xs:group>
+
+  <xs:group name="bitRangeOffsetWidthStyle">
+    <xs:sequence>
+      <xs:element name="bitOffset" type="scaledNonNegativeInteger"/>
+      <xs:element name="bitWidth" type="scaledNonNegativeInteger" minOccurs="0"/>   
+    </xs:sequence> 
+  </xs:group>
+
+  <xs:group name="dimElementGroup">
+    <xs:sequence>
+      <xs:element name="dim" type="scaledNonNegativeInteger"/>
+      <xs:element name="dimIncrement" type="scaledNonNegativeInteger"/>
+      <xs:element name="dimIndex" type="dimIndexType" minOccurs="0"/>
+    </xs:sequence>
+  </xs:group>
+
+  <xs:element name="device" nillable="true">
+    <xs:complexType>
+      <xs:sequence>
+        <xs:element name="name" type="xs:string"/>
+        <xs:element name="version" type="xs:string"/>
+        <xs:element name="description" type="xs:string"/>
+        <xs:element name="addressUnitBits" type="scaledNonNegativeInteger"/>
+        <xs:element name="width" type="scaledNonNegativeInteger"/>
+        <xs:group ref="registerPropertiesGroup" minOccurs="0"/>
+        <xs:element name="peripherals">
+          <xs:complexType>
+            <xs:sequence>
+              <xs:element name="peripheral" minOccurs="1" maxOccurs="unbounded">
+                <xs:complexType>
+                  <xs:sequence>
+                    <xs:element name="name" type="xs:Name"/>
+                    <xs:element name="version" type="xs:string" minOccurs="0"/>
+                    <xs:element name="description" type="xs:string" minOccurs="0"/>
+                    <xs:element name="groupName" type="xs:string" minOccurs="0"/>
+                    <xs:element name="prependToName" type="xs:string" minOccurs="0"/>
+                    <xs:element name="appendToName" type="xs:string" minOccurs="0"/>
+                    <xs:element name="disableCondition" type="xs:string" minOccurs="0"/>
+                    <xs:element name="baseAddress" type="scaledNonNegativeInteger"/>
+                    <xs:group ref="registerPropertiesGroup" minOccurs="0"/>
+                    <xs:element name="addressBlock" type="addressBlockType" minOccurs="0" maxOccurs="unbounded"/>
+                    <xs:element name="interrupt" type="interruptType" minOccurs="0" maxOccurs="unbounded"/>
+                    <xs:element name="registers" minOccurs="0" maxOccurs="1">
+                      <xs:complexType>
+                        <xs:sequence>
+                          <xs:element name="register" minOccurs="1" maxOccurs="unbounded">
+                            <xs:complexType>
+                              <xs:sequence>
+                                <xs:group ref="dimElementGroup" minOccurs="0"/>
+                                <xs:element name="name" type="registerNameType"/> <!-- was xs:Name -->
+                                <xs:element name="displayName" type="xs:string" minOccurs="0"/>
+                                <xs:element name="description" type="xs:string" minOccurs="0"/>
+                                <xs:element name="alternateGroup" type="xs:Name" minOccurs="0"/>
+                                <xs:element name="addressOffset" type="scaledNonNegativeInteger"/>
+                                <xs:group ref="registerPropertiesGroup" minOccurs="0"/>
+                                <xs:element name="modifiedWriteValues" type="modifiedWriteValuesType" minOccurs="0"/>
+                                <xs:element name="writeConstraint" type="writeConstraintType" minOccurs="0"/>
+                                <xs:element name="readAction" type="readActionType" minOccurs="0"/>
+                                <xs:element name="fields" minOccurs="0" maxOccurs="1">
+                                  <xs:complexType>
+                                    <xs:sequence>
+                                      <xs:element name="field" minOccurs="1" maxOccurs="unbounded">
+                                      <xs:complexType>
+                                        <xs:sequence>
+                                          <xs:element name="name" type="xs:string"/>
+                                          <xs:element name="description" type="xs:string" minOccurs="0"/>
+                                          <xs:choice>
+                                            <xs:group ref="bitRangeLsbMsbStyle" minOccurs="0"/>
+                                            <xs:group ref="bitRangeOffsetWidthStyle" minOccurs="0"/>
+                                            <xs:element name="bitRange" type="bitRangeType" minOccurs="0"/>
+                                          </xs:choice>
+                                          <xs:element name="access" type="accessType" minOccurs="0"/>
+                                          <xs:element name="modifiedWriteValues" type="modifiedWriteValuesType" minOccurs="0"/>
+                                          <xs:element name="writeConstraint" type="writeConstraintType" minOccurs="0"/>
+                                          <xs:element name="readAction" type="readActionType" minOccurs="0"/>
+                                          <xs:element name="enumeratedValues" minOccurs="0" maxOccurs="2">
+                                            <xs:complexType>
+                                              <xs:sequence>
+                                                <xs:element name="name" type="xs:Name" minOccurs="0"/>
+                                                <xs:element name="usage" type="enumUsageType" minOccurs="0"/>
+                                                <xs:element name="enumeratedValue" minOccurs="1" maxOccurs="unbounded">
+                                                  <xs:complexType>
+                                                    <xs:sequence>
+                                                      <xs:element name="name" type="xs:string"/>
+                                                      <xs:element name="description" type="xs:string" minOccurs="0"/>
+                                                      <xs:choice>
+                                                        <xs:element name="value" type="enumeratedValueDataType"/>
+                                                        <xs:element name="isDefault" type="xs:boolean"/>
+                                                      </xs:choice>
+                                                    </xs:sequence>
+                                                  </xs:complexType>
+                                                </xs:element>
+                                              </xs:sequence>
+                                              <xs:attribute name="derivedFrom" type="xs:Name" use="optional"/>
+                                            </xs:complexType>
+                                          </xs:element>
+                                        </xs:sequence>
+                                        <xs:attribute name="derivedFrom" type="xs:Name" use="optional"/>
+                                      </xs:complexType>
+                                    </xs:element>
+                                    </xs:sequence>
+                                  </xs:complexType>
+                                </xs:element>
+                              </xs:sequence>
+                              <xs:attribute name="derivedFrom" type="xs:Name" use="optional"/>
+                            </xs:complexType>
+                          </xs:element>
+                        </xs:sequence>
+                      </xs:complexType>
+                    </xs:element>
+                  </xs:sequence>
+                  <xs:attribute name="derivedFrom" type="xs:Name" use="optional"/>
+                </xs:complexType>
+              </xs:element>
+            </xs:sequence>
+          </xs:complexType>
+        </xs:element>
+        <xs:element name="vendorExtensions" minOccurs="0" maxOccurs="1">
+          <xs:complexType>
+            <xs:sequence>
+              <xs:any namespace="##any" processContents="lax" minOccurs="0" maxOccurs="unbounded">
+              </xs:any>
+            </xs:sequence>
+          </xs:complexType>
+        </xs:element>
+      </xs:sequence>
+      <xs:attribute name="schemaVersion" type="xs:decimal" use="required" fixed="1.0"/>
+    </xs:complexType>
+  </xs:element>
+</xs:schema>
+
    +
    + + + + + diff --git a/Libraries/CMSIS/Documentation/SVD/html/group__svd___format__1__1__gr.html b/Libraries/CMSIS/Documentation/SVD/html/group__svd___format__1__1__gr.html new file mode 100644 index 0000000..0c91e2f --- /dev/null +++ b/Libraries/CMSIS/Documentation/SVD/html/group__svd___format__1__1__gr.html @@ -0,0 +1,107 @@ + + + + +SVD Extension in Version 1.1 + + + + + + + + + + + +
    + +
    + + + + + + + + + + + +
    +
    CMSIS-SVD +  Version 1.10 +
    +
    CMSIS System View Description
    +
    +
    + +
    + +
    + + + +
    +
    + +
    +
    +
    + +
    +
    +
    +Modules
    +
    +
    SVD Extension in Version 1.1
    +
    +
    + + + + + + + +

    +Modules

     Extensions to the Device Section
     CPU Section (New)
     Extensions to the Peripheral Section
     Cluster Level (New)
     Extensions to the Register Section
    +

    Description

    +

    From a schema perspective, CMSIS-SVD Version 1.1 is fully backward compatible to version 1.0. Many of the features added in version 1.1 are required for generating CMSIS-Core device header files from a CMSIS SVD description. It is expected that over time all CMSIS-SVD descriptions will comply with version 1.1. Version 1.1 has not been finalized yet and is therefore currently marked draft.

    +
    +
    + + + + + diff --git a/Libraries/CMSIS/Documentation/SVD/html/group__svd___format__gr.html b/Libraries/CMSIS/Documentation/SVD/html/group__svd___format__gr.html new file mode 100644 index 0000000..f1a0714 --- /dev/null +++ b/Libraries/CMSIS/Documentation/SVD/html/group__svd___format__gr.html @@ -0,0 +1,139 @@ + + + + +SVD File Schema Levels + + + + + + + + + + + +
    + +
    + + + + + + + + + + + +
    +
    CMSIS-SVD +  Version 1.10 +
    +
    CMSIS System View Description
    +
    +
    + +
    + +
    + + + +
    +
    + +
    +
    +
    + +
    +
    +
    +Modules
    +
    +
    SVD File Schema Levels
    +
    +
    + + + + + + + +

    +Modules

     Device Level
     Peripherals Level
     Registers Level
     Fields Level
     Enumerated Values Level
    +

    Description

    +

    This section specifies the SVD file format Version 1.0. Each subsection defines one level of hierarchy and lists all mandatory and optional language elements as well as their type. A brief example description snippet demonstrates the usage of the elements.

    +
    Note:
      +
    • The sequence of elements in CMSIS-SVD is mandatory.
      • +
    • Optional elements are highlighted in green.
      • +
    • Mandatory elements are highlighted in blue. Optional sections can contain mandatory elements, which must be specified when the optional section is used. In this case the mandatory elements are also highlighted in blue.
      • +
    +
    +

    +Names

    +

    All name tags must comply with the ANSI C identifier naming restrictions (identifierType). In particular they must not contain any spaces or special characters. This is necessary to support the generation of device header files thus providing consistency between the names being shown by the debugger and the symbols being used in the CMSIS compliant target software.

    +

    +Constants

    +

    Number constants shall be entered in hexadecimal, decimal, or binary format.

    +
      +
    • The Hexadecimal format is indicated by a leading "0x".
      • +
    • The Binary format is indicated by a leading "#".
      • +
    • All other formats are interpreted as decimal numbers.
      • +
    • The value tag in enumeratedValue accepts do not care bits represented by "x".
      • +
    +

    +Comments

    +

    Comments have the standard XML format.

    +
      +
    • Start a comment with "<!--".
      • +
    • End a comment with "-->".
      • +
    +

    +Empty Tags

    +
      +
    • Single tags are not supported (for example, <name>).
      • +
    • The tag content must not consist of an empty string (instead, omit optional tags).
      • +
    +
    Remarks:
    The CMSIS-SVD Schema File Ver. 1.0 and schema_1_1_gr are provided alongside this document.
    +
    +
    + + + + + diff --git a/Libraries/CMSIS/Documentation/SVD/html/group__svd__xml__device__gr.html b/Libraries/CMSIS/Documentation/SVD/html/group__svd__xml__device__gr.html new file mode 100644 index 0000000..4542279 --- /dev/null +++ b/Libraries/CMSIS/Documentation/SVD/html/group__svd__xml__device__gr.html @@ -0,0 +1,177 @@ + + + + +Device Level + + + + + + + + + + + +
    + +
    + + + + + + + + + + + +
    +
    CMSIS-SVD +  Version 1.10 +
    +
    CMSIS System View Description
    +
    +
    + +
    + +
    + + + +
    +
    + +
    +
    +
    + +
    +
    +
    +
    Device Level
    +
    SVD File Schema Levels
    +
    +

    The element device provides the outermost frame of the description.

    +
      +
    • Only one device section is allowed per file. All other elements like peripherals, registers, fields, enumerated values, and vendor extensions are described within this scope.
      • +
    • A device contains one or more peripherals.
      • +
    • Optional elements like size, access, resetValue, and resetMask defined on this level are used as default values throughout the device description, unless they get redefined at a lower level.
      • +
    +
    +
    +<device schemaVersion="xs:decimal" xmlns:xs="http://www.w3.org/2001/XMLSchema-instance" xs:noNamespaceSchemaLocation="CMSIS-SVD_Schema_1_0.xsd">
        <name>identifierType</name>
+    <version>xs:string</version>
+    <description>xs:string</description>
+    <addressUnitBits>scaledNonNegativeInteger</addressUnitBits>
+    <width>scaledNonNegativeInteger</width>
+
+    <!-- registerPropertiesGroup -->
+    <size>scaledNonNegativeInteger</size>
+    <access>accessType</access>
+    <resetValue>scaledNonNegativeInteger</resetValue>
+    <resetMask>scaledNonNegativeInteger</resetMask>
+    <!-- end of registerPropertiesGroup -->
+
+    <peripherals>
+        ...
+    </peripherals>
+
+    <vendorExtensions>
+        ...
+    </vendorExtensions>
    </device>
+
+
    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    Attribute Name Description Type Occurrence
    xmlns:xs Specifies the underlying XML schema to which the CMSIS-SVD schema is compliant. Has to be set to: "http://www.w3.org/2001/XMLSchema-instance". xs:decimal 1..1
    xmlns:xs Specifies the file path and file name of the CMSIS-SVD Schema. For example, CMSIS-SVD_Schema_1_0.xsd. xs:string 1..1
    schemaVersion Specifies the CMSIS-SVD schema version the description is compliant to (for example, 1.0). xs:decimal 1..1
    Element Name Description Type Occurrence
    name The name string is used to identify the device or device series. Device names are required to be unique. xs:string 1..1
    version The string defines the version of the file. Silicon vendors maintain the description throughout the life-cycle of the device and ensure that all updated and released copies have a unique version string. Higher numbers indicate a more recent version. xs:string 1..1
    description String for describing main features of a device (for example CPU, clock frequency, peripheral overview). xs:string 1..1
    addressUnitBits Defines the number of data bits uniquely selected by each address. The value for Cortex-M based devices is 8 (byte-addressable). scaledNonNegativeInteger 1..1
    width Defines the number of data bit-width of the maximum single data transfer supported by the bus infrastructure. This information is relevant for debuggers when accessing registers, because it might be required to issue multiple accesses for accessing a resource of a bigger size. The expected value for Cortex-M based devices is 32. scaledNonNegativeInteger 1..1
    See registerPropertiesGroup for details.
    size Defines the default bit-width of any register contained in the device (implicit inheritance). scaledNonNegativeInteger 0..1
    access Defines the default access rights for all registers. accessType 0..1
    resetValue Defines the default value for all registers at RESET. scaledNonNegativeInteger 0..1
    resetMask Identifies which register bits have a defined reset value. scaledNonNegativeInteger 0..1
    peripherals Next level of description. see Peripherals Level for details.   1..1
    vendorExtensions The content and format of this section of the description is unspecified. Silicon vendors may choose to provide additional information. By default, this section is ignored for constructing the CMSIS files. It is up to the silicon vendor to specify a schema for this section. xs:anyType (restriction) 0..1
    +

    +Example:

    +
    <device schemaVersion="1.0" xmlns:xs="http://www.w3.org/2001/XMLSchema-instance" xs:noNamespaceSchemaLocation="CMSIS-SVD_Schema_1_0.xsd">
+  <name>ARM_Cortex_M3</name>
+  <version>0.1</version>
+  <description>ARM Cortex-M3 based Microcontroller demonstration device</description>
+  <addressUnitBits>8</addressUnitBits>
+  <width>32</width>
+  <size>32</size>
+  <access>read-write</access>
+  <resetValue>0</resetValue>
+  <resetMask>0xffffffff</resetMask>
+
+  <peripherals>
+    ...
+  </peripherals>
+</device>
+

    The device description above is at version 0.1 and uniquely identifies the device by the name "ARM_Cortex_M3". The peripherals are memory mapped in a byte-addressable address space with a bus width of 32 bits. The default size of the registers contained in the peripherals is set to 32 bits. Unless redefined for specific peripherals, all registers or fields are read-write accessible. A reset value of 0, valid for all 32 bits as specified by the reset mask, is set for all registers unless redefined at a lower level.

    +
    +
    + + + + + diff --git a/Libraries/CMSIS/Documentation/SVD/html/group__svd__xml__enum__gr.html b/Libraries/CMSIS/Documentation/SVD/html/group__svd__xml__enum__gr.html new file mode 100644 index 0000000..0908c1b --- /dev/null +++ b/Libraries/CMSIS/Documentation/SVD/html/group__svd__xml__enum__gr.html @@ -0,0 +1,197 @@ + + + + +Enumerated Values Level + + + + + + + + + + + +
    + +
    + + + + + + + + + + + +
    +
    CMSIS-SVD +  Version 1.10 +
    +
    CMSIS System View Description
    +
    +
    + +
    + +
    + + + +
    +
    + +
    +
    +
    + +
    +
    +
    +
    Enumerated Values Level
    +
    SVD File Schema Levels
    +
    +
    Enumerated Values

    The concept of enumerated values creates a map between unsigned integers and an identifier string. In addition, a description string can be associated with each entry in the map.

    +
    +        0 <-> disabled -> "the clock source clk0 is turned off"
+        1 <-> enabled  -> "the clock source clk1 is running"
+

    This information is used for generating an enum in the device header file. The debugger may use this information to display the identifier string as well as the description. Just like symbolic constants making source code more readable, the system view in the debugger becomes more instructive. The detailed description can provide reference manual level details within the debugger.

    +
    +
    +
+<enumeratedValues derivedFrom="xs:Name">
+
+    <name>identifierType</name>
+    <usage>usageType</usage>
+
+    <enumeratedValue>
+        ...
+    </enumeratedValue>
+
+    ...
+    <enumeratedValue>
+        ...
+    </enumeratedValue>
+
+</enumeratedValues>
+
+
    + + + + + + + + + + + + +
    Attribute Name Description Type Occurrence
    derivedFrom Makes a copy from a previously defined enumeratedValues section. No modifications are allowed. An enumeratedValues entry is referenced by its name. If the name is not unique throughout the description, it needs to be further qualified by specifying the associated field, register, and peripheral as required. For example: 
    +	field:                           clk.dis_en_enum
+	register + field:                ctrl.clk.dis_en_enum
+	peripheral + register + field:   timer0.ctrl.clk.dis_en_enum
+
    		xs:Name 0..1
    Element Name Description Type Occurrence
    name Identifier for the whole enumeration section. xs:Name 0..1
    usage Possible values are read, write, or read-write. This allows specifying two different enumerated values depending whether it is to be used for a read or a write access. If not specified, the default value read-write is used. enumUsageType 0..1
    enumeratedValue Describes a single entry in the enumeration. The number of required items depends on the bit width of the associated field. See section below for details.   1..*
    +
    Enumerated Value

    An enumeratedValue defines a map between an unsigned integer and a human readable string.

    + 
    +
+<enumeratedValue>
        <name>identifierType</name>
+    <description>xs:string</description>
        <choice>
+        <value>scaledNonNegativeInteger</value>
+        <isDefault>xs:boolean</isDefault>
+    </choice>
    </enumeratedValue>
+
+
    + + + + + + + + + + + + +
    Element Name Description Type Occurrence
    name String describing the semantics of the value. Can be displayed instead of the value. identifierType 0..1
    description Extended string describing the value. xs:string 0..1
    choice of 1..1
    value Defines the constant of the bit-field that the name corresponds to. scaledNonNegativeInteger 0..1
    isDefault Defines the name and description for all other values that are not listed explicitly. xs:boolean 0..1
    +

    +Example:

    +
    <enumeratedValues>
+
+    <name>TimerIntSelect</name>
+    <usage>read-write</usage>
+
+    <enumeratedValue>
+        <name>disabled</name>
+        <description>The clock source clk0 is turned off.</description>
+        <value>0</value>
+    </enumeratedValue>
+
+    <enumeratedValue>
+        <name>reserved</name>
+        <description>Reserved values. Do not use.</description>
+        <isDefault>true</isDefault>
+    </enumeratedValue>
+
+</enumeratedValues>
+
    <enumeratedValues>
+
+    <name>TimerIntSelect</name>
+    <usage>read-write</usage>
+
+    <enumeratedValue>
+        <name>disabled</name>
+        <description>Timer does not generate interrupts.</description>
+        <value>0</value>
+    </enumeratedValue>
+
+    <enumeratedValue>
+        <name>enabled</name>
+        <description>Timer generates interrupts.</description>
+        <isDefault>true</isDefault>
+    </enumeratedValue>
+
+</enumeratedValues>
+
    +
    + + + + + diff --git a/Libraries/CMSIS/Documentation/SVD/html/group__svd__xml__fields__gr.html b/Libraries/CMSIS/Documentation/SVD/html/group__svd__xml__fields__gr.html new file mode 100644 index 0000000..342960d --- /dev/null +++ b/Libraries/CMSIS/Documentation/SVD/html/group__svd__xml__fields__gr.html @@ -0,0 +1,215 @@ + + + + +Fields Level + + + + + + + + + + + +
    + +
    + + + + + + + + + + + +
    +
    CMSIS-SVD +  Version 1.10 +
    +
    CMSIS System View Description
    +
    +
    + +
    + +
    + + + +
    +
    + +
    +
    +
    + +
    +
    +
    +
    Fields Level
    +
    SVD File Schema Levels
    +
    +

    All fields of a register are enclosed between the <fields> opening and closing tags

    +

    A bit-field has a name that is unique within the register. The position and size within the register is either described by the combination of the least significant bit's position (lsb) and the most significant bit's position (msb), or the lsb and the bit-width of the field. A field may define an enumeratedValue in order to make the display more intuitive to read.

    + 
    
+<fields>
        <field derivedFrom="xs:Name">
            <name>xs:Name</name>
+        <description>xs:string</description>
            <choice>
+             <!-- bitRangeLsbMsbStyle --> 
+            <bitOffset>scaledNonNegativeInteger<bitOffset>
+            <bitWidth>scaledNonNegativeInteger</bitWidth>
+            or
+             <!-- bitRangeOffsetWidthStyle --> 
+            <lsb>scaledNonNegativeInteger</lsb> 
+            <msb>scaledNonNegativeInteger</msb>
+            or
+             <!-- bitRangePattern --> 
+            <bitRange>pattern</bitRange>
+        </choice>
+        
+        <access>accessType</access>
+        <modifiedWriteValues>writeValueType</modifiedWriteValues>
+        <writeConstraint>writeConstraintType</writeConstraint>
+        <readAction>readActionType</readAction>
            <enumeratedValues>
+            ...
+        </enumeratedValues>
        </field>
+    ...
+    <field>
+       ...
+    </field>
+    
+<fields>
+
+
    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    Attribute Name Description Type Occurrence
    derivedFrom The field is cloned from a previously defined field with a unique name. xs:Name 0..1
    Element Name Description Type Occurrence
    name Name string used to identify the field. Field names must be unique within a register. xs:string 1..1
    description String describing the details of the register. xs:string 0..1
    Choice of Three options exist to describe the field's bit-range. The options are to be used mutually exclusive: 1..1
    1. bitRangeLsbMsbStyle
    bitOffset Value defining the position of the least significant bit of the field within the register it belongs to. scaledNonNegativeInteger 1..1
    bitWidth Value defining the bit-width of the bitfield within the register it belongs to. scaledNonNegativeInteger 0..1
    2. bitRangeOffsetWidthStyle
    lsb Value defining the bit position of the least significant bit within the register it belongs to. scaledNonNegativeInteger 1..1
    msb Value defining the bit position of the most significant bit within the register it belongs to. scaledNonNegativeInteger 1..1
    3. bitRangePattern
    bitRange A string in the format: "[<msb>:<lsb>]" bitRangeType 0..1
    access Predefined strings can be used to define the allowed access types for this field: read-only, write-only, read-write, writeOnce, and read-writeOnce. Can be omitted if it matches the access permission set for the parent register. accessType 0..1
    modifiedWriteValues Describe the manipulation of data written to a field. If not specified, the value written to the field is the value stored in the field. The other options are bitwise operations:
      +
    • oneToClear: write data bit of one shall clear (set to zero) the corresponding bit in the field.
      • +
    • oneToSet: write data bit of one shall set (set to one) the corresponding bit in the field.
      • +
    • oneToToggle: write data bit of one shall toggle (invert) the corresponding bit in the field.
      • +
    • zeroToClear: write data bit of zero shall clear (set to zero) the corresponding bit in the field.
      • +
    • zeroToSet: write data bit of zero shall set (set to one) the corresponding bit in the field.
      • +
    • zeroToToggle: write data bit of zero shall toggle (invert) the corresponding bit in the field.
      • +
    • clear: after a write operation all bits in the field are cleared (set to zero).
      • +
    • set: after a write operation all bits in the field are set (set to one).
      • +
    • modify: after a write operation all bit in the field may be modified (default).
      • +
    +    		modifiedWriteValuesType 0..1
    writeConstraint Three options exist to set write-constraints: 0..1
    1. writeAsRead If TRUE, only the last read value can be written. xs:boolean 0..1
    2. useEnumeratedValues If TRUE, only the values listed in the enumeratedValues list are considered valid write values. xs:boolean 0..1
    3. range Consists of the following two elements:   0..1
    minimum Specifies the smallest number to be written to the field. scaledNonNegativeInteger 1..1
    maximum Specifies the largest number to be written to the field. scaledNonNegativeInteger 1..1
    readAction If set, it specifies the side effect following a read operation. If not set, the field is not modified after a read. The defined side effects are:
      +
    • clear: The field is cleared (set to zero) following a read operation.
      • +
    • set: The field is set (set to ones) following a read operation.
      • +
    • modify: The field is modified in some way after a read operation.
      • +
    • modifyExternal: One or more dependent resources other than the current field are immediately affected by a read operation (it is recommended that the field description specifies these dependencies). Debuggers are not expected to read this field location unless explicitly instructed by the user.
      • +
    +    		readActionType 0..1 register
    enumeratedValues Next lower level of description. See section Enumerated Values Level for details.   0..2
    +

    +Example:

    +
    ...
+<field>
+  <name>TimerCtrl0_IntSel</name>
+  <description>Select interrupt line that is triggered by timer overflow.</description>
+  <bitOffset>1</bitOffset>
+  <bitWidth>3</bitWidth>
+  <access>read-write</access>
+  <resetValue>0x0</resetValue>
+  <modifiedWriteValues>oneToSet</modifiedWriteValues>
+  <writeConstraint>
+    <range>
+      <minimum>0</minimum>
+      <maximum>5</maximum>
+    </range>
+  </writeConstraint>
+  <readAction>clear</readAction>
+ 
+  <enumeratedValues>
+    ...
+  </enumeratedValues>
+</field>
+...
+
    +
    + + + + + diff --git a/Libraries/CMSIS/Documentation/SVD/html/group__svd__xml__peripherals__gr.html b/Libraries/CMSIS/Documentation/SVD/html/group__svd__xml__peripherals__gr.html new file mode 100644 index 0000000..40bf80f --- /dev/null +++ b/Libraries/CMSIS/Documentation/SVD/html/group__svd__xml__peripherals__gr.html @@ -0,0 +1,223 @@ + + + + +Peripherals Level + + + + + + + + + + + +
    + +
    + + + + + + + + + + + +
    +
    CMSIS-SVD +  Version 1.10 +
    +
    CMSIS System View Description
    +
    +
    + +
    + +
    + + + +
    +
    + +
    +
    +
    + +
    +
    +
    +
    Peripherals Level
    +
    SVD File Schema Levels
    +
    +

    All peripherals of a device are enclosed within the tag <peripherals>. At least one peripheral has to be defined. Each peripheral is enclosed in the tag <peripheral>.

    +
      +
    • Each peripheral describes all registers belonging to that peripheral.
      • +
    • The address range allocated by a peripheral is defined through one or more address blocks.
      • +
    • An address block and register addresses are specified relative to the base address of a peripheral. The address block information can be used for constructing a memory map for the device peripherals.
      • +
    +
    Remarks:
    The memory map does not contain any information about RAM, ROM, or FLASH memory.
    +
    +
    + <peripherals> 
        <peripheral derivedFrom="<em>identifierType</em>">
            <name>identifierType</name>
+        <version>xs:string</version>
+        <description>xs:string</description>
+    
+        <groupName>identifierType</groupName>
+        <prependToName>identifierType</prependToName>
+        <appendToName>identifierType</appendToName>
+        <disableCondition>xs:string</disableCondition>
+    
+        <baseAddress>scaledNonNegativeInteger</baseAddress>
+    
+         <!-- registerPropertiesGroup -->
+        <size>scaledNonNegativeInteger</size>
+        <access>accessType</access>
+        <resetValue>scaledNonNegativeInteger</resetValue>
+        <resetMask>scaledNonNegativeInteger</resetMask>
+         <!-- end of registerPropertiesGroup -->
+    
+        <addressBlock>
+            <offset>scaledNonNegativeInteger</offset>
+            <size>scaledNonNegativeInteger</size>
+            <usage>usageType</usage>
+        </addressBlock>
+        ...
+        <addressBlock>
+            <offset>scaledNonNegativeInteger</offset>
+            <size>scaledNonNegativeInteger</size>
+            <usage>usageType</usage>
+        </addressBlock>
+    
+        <interrupt>
+            <name>identifierType</name>
+            <value>scaledNonNegativeInteger</value>
+        </interrupt>
            <registers>
+            ...
+        </registers>
        </peripheral>
+    ...
+    <peripheral>
+       ...
+    </peripheral>
+    
+</peripherals>
+
+
    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    Attribute Name Description Type Occurrence
    derivedFrom Specifies the name of a peripheral from which this peripheral will be derived. Values are inherit. Elements specified underneath will override inherited values. xs:Name 0..1
    Element Name Description Type Occurrence
    name The name string is used to identify the peripheral. Peripheral names are required to be unique for a device. The name needs to be an ANSI C identifier to allow header file generation. xs:Name 1..1
    version The string specifies the version of this peripheral description. xs:string 0..1
    description The string provides an overview of the purpose and functionality of the peripheral. xs:string 0..1
    groupName xs:string 0..1
    prependToName All register names of this peripheral have their names prefixed with this string. xs:string 0..1
    appendToName All register names of this peripheral have their names suffixed with this string. xs:string 0..1
    disableCondition Is a C-language compliant logical expression returning a TRUE or FALSE result. If TRUE, refreshing the display for this peripheral is disabled and related accesses by the debugger are suppressed.
    +
    + Only constants and references to other registers contained in the description are allowed: <peripheral>-><register>-><field>, for example, (System->ClockControl->apbEnable == 0). The following operators are allowed in the expression [&&,||, ==, !=, >>, <<, &, |].
    Attention:
    Use this feature only in cases where accesses from the debugger to registers of un-clocked peripherals result in severe debugging failures. SVD is intended to provide static information and does not include any run-time computation or functions. Such capabilities can be added by the tools, and is beyond the scope of this description language.
    +    		xs:string 0..1
    baseAddress Lowest address reserved or used by the peripheral. scaledNonNegativeInteger 1..1
    See registerPropertiesGroup for details.
    size Defines the default bit-width of any register contained in the device (implicit inheritance). scaledNonNegativeInteger 0..1
    access Defines the default access rights for all registers. accessType 0..1
    resetValue Defines the default value for all registers at RESET. scaledNonNegativeInteger 0..1
    resetMask Identifies which register bits have a defined reset value. scaledNonNegativeInteger 0..1
    addressBlock Specifies an address range uniquely mapped to this peripheral. A peripheral must have at least one address block, but may allocate multiple distinct address ranges. If a peripheral is derived form another peripheral, the addressBlock is not mandatory. addressBlockType 1..*
    offset Specifies the start address of an address block relative to the peripheral baseAddress. scaledNonNegativeInteger 1..1
    size Specifies the number of addressUnitBits being covered by this address block. The end address of an address block results from the sum of baseAddress, offset, and (size - 1). scaledNonNegativeInteger 1..1
    usage The following predefined values can be used: registers, buffer, or reserved. scaledNonNegativeInteger 1..1
    interrupt A peripheral can have multiple associated interrupts. This entry allows the debugger to show interrupt names instead of interrupt numbers. interruptType 0..*
    name The string represents the interrupt name. XS:string 1..1
    value Is the enumeration index value associated to the interrupt. xs:integer 1..1
    registers See Registers Level for details.   0..1
    +

    +Example:

    +
    ...
+<peripheral>
+  <name>Timer0</name>
+  <version>1.0.32</version>
+  <description>Timer 0 is a simple 16 bit timer counting down ... </description>
+  <baseAddress>0x40000000</baseAddress>
+  <addressBlock>
+    <offset>0x0</offset>
+    <size>0x400</size>
+    <usage>registers</usage>
+  </addressBlock>
+  <interrupt><name>TIM0_INT</name><value>34</value></interrupt>
+  <registers>
+    ...
+  </registers>
+</peripheral>
+
+<peripheral derivedFrom="Timer0">
+  <name>Timer1</name>
+  <baseAddress>0x40000400</baseAddress>
+</peripheral>
+...
+
    +
    + + + + + diff --git a/Libraries/CMSIS/Documentation/SVD/html/group__svd__xml__registers__gr.html b/Libraries/CMSIS/Documentation/SVD/html/group__svd__xml__registers__gr.html new file mode 100644 index 0000000..4a26175 --- /dev/null +++ b/Libraries/CMSIS/Documentation/SVD/html/group__svd__xml__registers__gr.html @@ -0,0 +1,234 @@ + + + + +Registers Level + + + + + + + + + + + +
    + +
    + + + + + + + + + + + +
    +
    CMSIS-SVD +  Version 1.10 +
    +
    CMSIS System View Description
    +
    +
    + +
    + +
    + + + +
    +
    + +
    +
    +
    + +
    +
    +
    +
    Registers Level
    +
    SVD File Schema Levels
    +
    +

    All registers of a peripheral are enclosed between the <registers> opening and closing tags.

    +

    The description of registers is the most essential part of the SVD description. The register's name, detailed description, and the address-offset relative to the peripheral base address are the mandatory elements. If the size, access, reset value, and reset mask have not been specified on the device or peripheral level, or if the default values need to be redefined locally, these fields become mandatory.

    +

    A register can represent a single value or can be subdivided into individual bit-fields of specific functionality and semantics. In schema-terms the fields section is optional, however, from a specification perspective, fields are mandatory when they are described in the device documentation.

    +

    The SVD specification supports the array-of-registers concept. The single register description gets duplicated automatically into an array. The size of the array is specified by the <dim> element. The register names can be composed by the register name and an index specific substring define in <dimIndex>. The <dimIncrement> specifies the address offset between two registers.

    +
    +
    +<registers> 
        <register derivedFrom=registerNameType>
+    
+        <!-- dimElementGroup --> 
+        <dim>scaledNonNegativeInteger</dim>
+        <dimIncrement>scaledNonNegativeInteger</dimIncrement>
+        <dimIndex>xs:string</dimIndex>
+        <!-- end of dimElementGroup --> 
+   
+        <name>identifierType</name>
+    
+        <displayName>xs:string</displayName>
+    
+        <description>xs:string</description>
+    
+        <alternateGroup>xs:Name</alternateGroup>
+    
+        <addressOffset>scaledNonNegativeInteger</addressOffset>
+    
+        <!-- registerPropertiesGroup --> 
+        <size>scaledNonNegativeInteger</size>
+        <access>accessType</access>
+        <resetValue>scaledNonNegativeInteger</resetValue>
+        <resetMask>scaledNonNegativeInteger</resetMask>
+        <!-- end of registerPropertiesGroup --> 
+    
+        <modifiedWriteValues>writeValueType</modifiedWriteValues>
+        <writeConstraint>writeConstraintType</writeConstraint>
+        <readAction>readActionType</readAction>
            <fields>
+            ...
+        </fields>
+    
+    </register>
+    ...
+    <register>
+        ...
+    </register>
+    
+<registers> 
+
    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    Attribute Name Description Type Occurrence
    derivedFrom Specifies the name of the register from which to inherit the data. Elements being specified underneath will override the inherited values.
    +Remarks: When deriving a register, it is mandatory to specify at least the name, the description, and the addressOffset.     		xs:Name 0..1
    Element Name Description Type Occurrence
    See dimElementGroup for details.
    dimIncrement The value defines the number of elements in an array of registers. scaledNonNegativeInteger 1..1
    dimIncrement If dim is specified, this element becomes mandatory. The element specifies the address increment in between two neighboring registers of the register array in the address map. scaledNonNegativeInteger 1..1
    dimIndex Specifies the substrings that replaces the s placeholder within the register name. By default, the index is a decimal value starting with 0 for the first register. dimIndexType 0..1
    name Name string used to identify the register. Register names are required to be unique within the scope of a peripheral. registerNameType 1..1
    displayName When specified, the string is being used by a graphical frontend to visualize the register. Otherwise the name element is displayed. The displayName may contain special characters and white spaces. The place holder s can be used and is replaced by the dimIndex substring. xs:string 0..1
    description String describing the details of the register. xs:string 0..1
    alternateGroup Specifies a group name associated with all alternate register that have the same name. At the same time, it indicates that there is a register definition allocating the same absolute address in the address space. xs:Name 0..1
    addressOffset Value defining the address of the register relative to the baseAddress defined by the peripheral of the register. scaledNonNegativeInteger 1..1
    See registerPropertiesGroup for details.
    size Defines the default bit-width of any register contained in the device (implicit inheritance). scaledNonNegativeInteger 0..1
    access Defines the default access rights for all registers. accessType 0..1
    resetValue Defines the default value for all registers at RESET. scaledNonNegativeInteger 0..1
    resetMask Identifies which register bits have a defined reset value. scaledNonNegativeInteger 0..1
    modifiedWriteValues Element to describe the manipulation of data written to a register. If not specified, the value written to the field is the value stored in the field. The other options define bitwise operations:
      +
    • oneToClear: write data bits of one shall clear (set to zero) the corresponding bit in the register.
      • +
    • oneToSet: write data bits of one shall set (set to one) the corresponding bit in the register.
      • +
    • oneToToggle: write data bits of one shall toggle (invert) the corresponding bit in the register.
      • +
    • zeroToClear: write data bits of zero shall clear (set to zero) the corresponding bit in the register.
      • +
    • zeroToSet: write data bits of zero shall set (set to one) the corresponding bit in the register.
      • +
    • zeroToToggle: write data bits of zero shall toggle (invert) the corresponding bit in the register.
      • +
    • clear: after a write operation all bits in the field are cleared (set to zero).
      • +
    • set: after a write operation all bits in the field are set (set to one).
      • +
    • modify: after a write operation all bit in the field may be modified (default).
      • +
    +    		modifiedWriteValuesType 0..1
    writeConstraint Three options exist to set write-constraints: 0..1
    1. writeAsRead If TRUE, only the last read value can be written. xs:boolean 0..1
    2. useEnumeratedValues If TRUE, only the values listed in the enumeratedValues list are considered valid write values. xs:boolean 0..1
    3. range Consists of the following two elements:   0..1
    minimum Specifies the smallest number to be written to the field. scaledNonNegativeInteger 1..1
    maximum Specifies the largest number to be written to the field. scaledNonNegativeInteger 1..1
    readAction If set, it specifies the side effect following a read operation. If not set, the register is not modified. The defined side effects are:
      +
    • clear: The register is cleared (set to zero) following a read operation.
      • +
    • set: The register is set (set to ones) following a read operation.
      • +
    • modify: The register is modified in some way after a read operation.
      • +
    • modifyExternal: One or more dependent resources other than the current register are immediately affected by a read operation (it is recommended that the register description specifies these dependencies). Debuggers are not expected to read this register location unless explicitly instructed by the user.
      • +
    +    		readActionType

    0..1

    +

    +
    fields Next lower level of description (see Fields Level for details). Not all registers are further divided into fields, therefore, this level is optional. In case a register is subdivided into bit fields, it should be reflected in the description. The device header file can only contain bit access macros and bit-field structures if this information is contained in the description.   0..1
    +

    +Example:

    +
    ...
+<register>
+  <name>TimerCtrl0</name>
+  <description>Timer Control Register</description>
+  <addressOffset>0x0</addressOffset>
+  <access>read-write</access>
+  <resetValue>0x00008001</resetValue>
+  <resetMask>0x0000ffff</resetMask>
+  <size>32</size>
+  <fields>
+    ...
+  </fields>
+</register>
+
+<register derivedFrom="TimerCtrl0">
+  <name>TimerCtrl1</name>
+  <description>Derived Timer</description>
+  <addressOffset>0x4</addressOffset>
+</register>
+...
+
    +
    + + + + + diff --git a/Libraries/CMSIS/Documentation/SVD/html/index.html b/Libraries/CMSIS/Documentation/SVD/html/index.html new file mode 100644 index 0000000..813b480 --- /dev/null +++ b/Libraries/CMSIS/Documentation/SVD/html/index.html @@ -0,0 +1,153 @@ + + + + +System View Description + + + + + + + + + + + +
    + +
    + + + + + + + + + + + +
    +
    CMSIS-SVD +  Version 1.10 +
    +
    CMSIS System View Description
    +
    +
    + +
    + +
    + + + +
    +
    + +
    +
    +
    + +
    +
    +
    +
    System View Description
    +
    +
    +

    This chapter contains the introduction and specification of the CMSIS System View Description format (CMSIS-SVD). The introduction section outlines the objectives and benefits CMSIS-SVD.

    +

    Introduction

    +

    CMSIS-SVD formalizes the description of the programmer's view for the system contained in ARM Cortex-M processor-based microcontrollers, in particular the memory mapped registers of the peripherals. The detail contained in system view descriptions is comparable to what is found in device reference manuals published by silicon vendors. The information ranges from a high level functional description of a peripheral all the way down to the definition and purpose of an individual bit field in a memory mapped register. CMSIS-SVD files are developed and maintained by the silicon vendors. Silicon vendors manage their descriptions in a central, web-based Device Database and the CMSIS-SVD files are downloadable via a public web interface once they have been released by the silicon vendor. Tool vendors use these descriptions for providing device-specific debug views of peripherals in their debugger. Last but not least CMSIS compliant device header files are generated from CMSIS-SVD files.

    +

    CMSIS-SVD Benefits

    +
      +
    • The benefits for the Software Developer:
        +
      • Consistency between device header file and what is being displayed by the debugger.
        • +
      • Detailed information about peripherals, registers, fields, and bit values from within the debugger, without the need to reference device documentation.
        • +
      • Public access via a web interface to new and updated descriptions as they become available from silicon vendors.
        • +
      • Improved software development efficiency.
        • +
      +
      • +
    +
      +
    • The benefits for the Silicon Vendor:
        +
      • A tool vendor independent file format enables early device support by a wide range of toolchains with limited effort.
        • +
      • The XML-based format helps ease the integration into in-house design flows.
        • +
      • Automated generation of CMSIS compliant device header files.
        • +
      • Full control throughout the life cycle of the CMSIS-SVD files from creation to maintenance via the web-based Device Database.
        • +
      +
      • +
    +
      +
    • The benefits for the Tool Vendor:
        +
      • Unified file format across silicon vendors helps the efficiency of supporting a wide range of new devices in a timely manner.
        • +
      • Silicon vendors provide early review access to individuals ahead of the publishing date.
        • +
      • Updated descriptions are available over the web simplifying the maintenance of device support.
        • +
      +
      • +
    +

    The Web Infrastructure

    +
    +CMSIS_SVD_WEB_DATABASE.png +
    +CMSIS-SVD Management Processes
    +

    The diagram illustrates the management process steps for uploading, validating, reviewing, publishing, and downloading CMSIS-SVD files.

    +
      +
    • Managing Files: A CMSIS-SVD file is uploaded by a silicon vendor via the web interface (Device Database). The system performs a check against the CMSIS-SVD Schema and runs the SVDConv consistency checker. Only if both checks have been successful the file will be stored in the SVD Storage. Files can be added, replaced and deleted.
      • +
    +
      +
    • Managing Devices: The silicon vendor creates an entry for each of his devices in the database by defining a name and associating it with a CMSIS-SVD file from the SVD Storage. The publishing date set forth for a device is used by the system to determine when this device becomes visible in the public device database. Prior to the publishing date, the silicon vendor can grant review access to individuals for an individual device. Reviewers get notified by e-mail about a device being made available for review.
      • +
    +
      +
    • Public Download: Public access to the silicon vendor specific CMSIS-SVD download pages is provided from cmsis.arm.com or www.arm.com/cmsis. Select the CMSIS-SVD tab and select the Silicon Vendor of interest from the list. For the public download of the CMSIS-SVD files of published devices it is mandatory to:
        +
      • Be logged in on the ARM web site.
        • +
      • Have accepted a silicon vendor specific End Users License Agreement (EULA).
        • +
      +
      • +
    +

    More information about the web infrastructure can be found in the CMSIS-SVD Web Interface User Guide

    +

    Language Outline

    + +

    Language Specification

    + +
    +
    + + + + + diff --git a/Libraries/CMSIS/Documentation/SVD/html/jquery.js b/Libraries/CMSIS/Documentation/SVD/html/jquery.js new file mode 100644 index 0000000..c052173 --- /dev/null +++ b/Libraries/CMSIS/Documentation/SVD/html/jquery.js @@ -0,0 +1,54 @@ +/* + * jQuery JavaScript Library v1.3.2 + * http://jquery.com/ + * + * Copyright (c) 2009 John Resig + * Dual licensed under the MIT and GPL licenses. + * http://docs.jquery.com/License + * + * Date: 2009-02-19 17:34:21 -0500 (Thu, 19 Feb 2009) + * Revision: 6246 + */ +(function(){var l=this,g,y=l.jQuery,p=l.$,o=l.jQuery=l.$=function(E,F){return new o.fn.init(E,F)},D=/^[^<]*(<(.|\s)+>)[^>]*$|^#([\w-]+)$/,f=/^.[^:#\[\.,]*$/;o.fn=o.prototype={init:function(E,H){E=E||document;if(E.nodeType){this[0]=E;this.length=1;this.context=E;return this}if(typeof E==="string"){var G=D.exec(E);if(G&&(G[1]||!H)){if(G[1]){E=o.clean([G[1]],H)}else{var I=document.getElementById(G[3]);if(I&&I.id!=G[3]){return o().find(E)}var F=o(I||[]);F.context=document;F.selector=E;return F}}else{return o(H).find(E)}}else{if(o.isFunction(E)){return o(document).ready(E)}}if(E.selector&&E.context){this.selector=E.selector;this.context=E.context}return this.setArray(o.isArray(E)?E:o.makeArray(E))},selector:"",jquery:"1.3.2",size:function(){return this.length},get:function(E){return E===g?Array.prototype.slice.call(this):this[E]},pushStack:function(F,H,E){var G=o(F);G.prevObject=this;G.context=this.context;if(H==="find"){G.selector=this.selector+(this.selector?" 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g(m,n,o,l){function k(q){var p=c[m][n][q]||[];return(typeof p=="string"?p.split(/,?\s+/):p)}var j=k("getter");if(l.length==1&&typeof l[0]=="string"){j=j.concat(k("getterSetter"))}return(c.inArray(o,j)!=-1)}c.widget=function(k,j){var l=k.split(".")[0];k=k.split(".")[1];c.fn[k]=function(p){var n=(typeof p=="string"),o=Array.prototype.slice.call(arguments,1);if(n&&p.substring(0,1)=="_"){return this}if(n&&g(l,k,p,o)){var m=c.data(this[0],k);return(m?m[p].apply(m,o):undefined)}return this.each(function(){var q=c.data(this,k);(!q&&!n&&c.data(this,k,new c[l][k](this,p))._init());(q&&n&&c.isFunction(q[p])&&q[p].apply(q,o))})};c[l]=c[l]||{};c[l][k]=function(o,n){var m=this;this.namespace=l;this.widgetName=k;this.widgetEventPrefix=c[l][k].eventPrefix||k;this.widgetBaseClass=l+"-"+k;this.options=c.extend({},c.widget.defaults,c[l][k].defaults,c.metadata&&c.metadata.get(o)[k],n);this.element=c(o).bind("setData."+k,function(q,p,r){if(q.target==o){return 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p=this.options[l],j=(l==this.widgetEventPrefix?l:this.widgetEventPrefix+l);m=c.Event(m);m.type=j;if(m.originalEvent){for(var k=c.event.props.length,o;k;){o=c.event.props[--k];m[o]=m.originalEvent[o]}}this.element.trigger(m,n);return !(c.isFunction(p)&&p.call(this.element[0],m,n)===false||m.isDefaultPrevented())}};c.widget.defaults={disabled:false};c.ui.mouse={_mouseInit:function(){var j=this;this.element.bind("mousedown."+this.widgetName,function(k){return j._mouseDown(k)}).bind("click."+this.widgetName,function(k){if(j._preventClickEvent){j._preventClickEvent=false;k.stopImmediatePropagation();return false}});if(c.browser.msie){this._mouseUnselectable=this.element.attr("unselectable");this.element.attr("unselectable","on")}this.started=false},_mouseDestroy:function(){this.element.unbind("."+this.widgetName);(c.browser.msie&&this.element.attr("unselectable",this._mouseUnselectable))},_mouseDown:function(l){l.originalEvent=l.originalEvent||{};if(l.originalEvent.mouseHandled){return}(this._mouseStarted&&this._mouseUp(l));this._mouseDownEvent=l;var k=this,m=(l.which==1),j=(typeof this.options.cancel=="string"?c(l.target).parents().add(l.target).filter(this.options.cancel).length:false);if(!m||j||!this._mouseCapture(l)){return true}this.mouseDelayMet=!this.options.delay;if(!this.mouseDelayMet){this._mouseDelayTimer=setTimeout(function(){k.mouseDelayMet=true},this.options.delay)}if(this._mouseDistanceMet(l)&&this._mouseDelayMet(l)){this._mouseStarted=(this._mouseStart(l)!==false);if(!this._mouseStarted){l.preventDefault();return true}}this._mouseMoveDelegate=function(n){return k._mouseMove(n)};this._mouseUpDelegate=function(n){return k._mouseUp(n)};c(document).bind("mousemove."+this.widgetName,this._mouseMoveDelegate).bind("mouseup."+this.widgetName,this._mouseUpDelegate);(c.browser.safari||l.preventDefault());l.originalEvent.mouseHandled=true;return true},_mouseMove:function(j){if(c.browser.msie&&!j.button){return this._mouseUp(j)}if(this._mouseStarted){this._mouseDrag(j);return j.preventDefault()}if(this._mouseDistanceMet(j)&&this._mouseDelayMet(j)){this._mouseStarted=(this._mouseStart(this._mouseDownEvent,j)!==false);(this._mouseStarted?this._mouseDrag(j):this._mouseUp(j))}return !this._mouseStarted},_mouseUp:function(j){c(document).unbind("mousemove."+this.widgetName,this._mouseMoveDelegate).unbind("mouseup."+this.widgetName,this._mouseUpDelegate);if(this._mouseStarted){this._mouseStarted=false;this._preventClickEvent=(j.target==this._mouseDownEvent.target);this._mouseStop(j)}return false},_mouseDistanceMet:function(j){return(Math.max(Math.abs(this._mouseDownEvent.pageX-j.pageX),Math.abs(this._mouseDownEvent.pageY-j.pageY))>=this.options.distance)},_mouseDelayMet:function(j){return this.mouseDelayMet},_mouseStart:function(j){},_mouseDrag:function(j){},_mouseStop:function(j){},_mouseCapture:function(j){return true}};c.ui.mouse.defaults={cancel:null,distance:1,delay:0}})(jQuery);;/* * jQuery UI Resizable 1.7.2 + * + * Copyright (c) 2009 AUTHORS.txt (http://jqueryui.com/about) + * Dual licensed under the MIT (MIT-LICENSE.txt) + * and GPL (GPL-LICENSE.txt) licenses. + * + * http://docs.jquery.com/UI/Resizables + * + * Depends: + * ui.core.js + */ +(function(c){c.widget("ui.resizable",c.extend({},c.ui.mouse,{_init:function(){var e=this,j=this.options;this.element.addClass("ui-resizable");c.extend(this,{_aspectRatio:!!(j.aspectRatio),aspectRatio:j.aspectRatio,originalElement:this.element,_proportionallyResizeElements:[],_helper:j.helper||j.ghost||j.animate?j.helper||"ui-resizable-helper":null});if(this.element[0].nodeName.match(/canvas|textarea|input|select|button|img/i)){if(/relative/.test(this.element.css("position"))&&c.browser.opera){this.element.css({position:"relative",top:"auto",left:"auto"})}this.element.wrap(c('
    ').css({position:this.element.css("position"),width:this.element.outerWidth(),height:this.element.outerHeight(),top:this.element.css("top"),left:this.element.css("left")}));this.element=this.element.parent().data("resizable",this.element.data("resizable"));this.elementIsWrapper=true;this.element.css({marginLeft:this.originalElement.css("marginLeft"),marginTop:this.originalElement.css("marginTop"),marginRight:this.originalElement.css("marginRight"),marginBottom:this.originalElement.css("marginBottom")});this.originalElement.css({marginLeft:0,marginTop:0,marginRight:0,marginBottom:0});this.originalResizeStyle=this.originalElement.css("resize");this.originalElement.css("resize","none");this._proportionallyResizeElements.push(this.originalElement.css({position:"static",zoom:1,display:"block"}));this.originalElement.css({margin:this.originalElement.css("margin")});this._proportionallyResize()}this.handles=j.handles||(!c(".ui-resizable-handle",this.element).length?"e,s,se":{n:".ui-resizable-n",e:".ui-resizable-e",s:".ui-resizable-s",w:".ui-resizable-w",se:".ui-resizable-se",sw:".ui-resizable-sw",ne:".ui-resizable-ne",nw:".ui-resizable-nw"});if(this.handles.constructor==String){if(this.handles=="all"){this.handles="n,e,s,w,se,sw,ne,nw"}var k=this.handles.split(",");this.handles={};for(var f=0;f
    ');if(/sw|se|ne|nw/.test(h)){g.css({zIndex:++j.zIndex})}if("se"==h){g.addClass("ui-icon ui-icon-gripsmall-diagonal-se")}this.handles[h]=".ui-resizable-"+h;this.element.append(g)}}this._renderAxis=function(p){p=p||this.element;for(var m in this.handles){if(this.handles[m].constructor==String){this.handles[m]=c(this.handles[m],this.element).show()}if(this.elementIsWrapper&&this.originalElement[0].nodeName.match(/textarea|input|select|button/i)){var n=c(this.handles[m],this.element),o=0;o=/sw|ne|nw|se|n|s/.test(m)?n.outerHeight():n.outerWidth();var l=["padding",/ne|nw|n/.test(m)?"Top":/se|sw|s/.test(m)?"Bottom":/^e$/.test(m)?"Right":"Left"].join("");p.css(l,o);this._proportionallyResize()}if(!c(this.handles[m]).length){continue}}};this._renderAxis(this.element);this._handles=c(".ui-resizable-handle",this.element).disableSelection();this._handles.mouseover(function(){if(!e.resizing){if(this.className){var i=this.className.match(/ui-resizable-(se|sw|ne|nw|n|e|s|w)/i)}e.axis=i&&i[1]?i[1]:"se"}});if(j.autoHide){this._handles.hide();c(this.element).addClass("ui-resizable-autohide").hover(function(){c(this).removeClass("ui-resizable-autohide");e._handles.show()},function(){if(!e.resizing){c(this).addClass("ui-resizable-autohide");e._handles.hide()}})}this._mouseInit()},destroy:function(){this._mouseDestroy();var d=function(f){c(f).removeClass("ui-resizable ui-resizable-disabled ui-resizable-resizing").removeData("resizable").unbind(".resizable").find(".ui-resizable-handle").remove()};if(this.elementIsWrapper){d(this.element);var e=this.element;e.parent().append(this.originalElement.css({position:e.css("position"),width:e.outerWidth(),height:e.outerHeight(),top:e.css("top"),left:e.css("left")})).end().remove()}this.originalElement.css("resize",this.originalResizeStyle);d(this.originalElement)},_mouseCapture:function(e){var f=false;for(var d in this.handles){if(c(this.handles[d])[0]==e.target){f=true}}return this.options.disabled||!!f},_mouseStart:function(f){var i=this.options,e=this.element.position(),d=this.element;this.resizing=true;this.documentScroll={top:c(document).scrollTop(),left:c(document).scrollLeft()};if(d.is(".ui-draggable")||(/absolute/).test(d.css("position"))){d.css({position:"absolute",top:e.top,left:e.left})}if(c.browser.opera&&(/relative/).test(d.css("position"))){d.css({position:"relative",top:"auto",left:"auto"})}this._renderProxy();var j=b(this.helper.css("left")),g=b(this.helper.css("top"));if(i.containment){j+=c(i.containment).scrollLeft()||0;g+=c(i.containment).scrollTop()||0}this.offset=this.helper.offset();this.position={left:j,top:g};this.size=this._helper?{width:d.outerWidth(),height:d.outerHeight()}:{width:d.width(),height:d.height()};this.originalSize=this._helper?{width:d.outerWidth(),height:d.outerHeight()}:{width:d.width(),height:d.height()};this.originalPosition={left:j,top:g};this.sizeDiff={width:d.outerWidth()-d.width(),height:d.outerHeight()-d.height()};this.originalMousePosition={left:f.pageX,top:f.pageY};this.aspectRatio=(typeof i.aspectRatio=="number")?i.aspectRatio:((this.originalSize.width/this.originalSize.height)||1);var h=c(".ui-resizable-"+this.axis).css("cursor");c("body").css("cursor",h=="auto"?this.axis+"-resize":h);d.addClass("ui-resizable-resizing");this._propagate("start",f);return true},_mouseDrag:function(d){var g=this.helper,f=this.options,l={},p=this,i=this.originalMousePosition,m=this.axis;var q=(d.pageX-i.left)||0,n=(d.pageY-i.top)||0;var h=this._change[m];if(!h){return false}var k=h.apply(this,[d,q,n]),j=c.browser.msie&&c.browser.version<7,e=this.sizeDiff;if(this._aspectRatio||d.shiftKey){k=this._updateRatio(k,d)}k=this._respectSize(k,d);this._propagate("resize",d);g.css({top:this.position.top+"px",left:this.position.left+"px",width:this.size.width+"px",height:this.size.height+"px"});if(!this._helper&&this._proportionallyResizeElements.length){this._proportionallyResize()}this._updateCache(k);this._trigger("resize",d,this.ui());return false},_mouseStop:function(g){this.resizing=false;var h=this.options,l=this;if(this._helper){var f=this._proportionallyResizeElements,d=f.length&&(/textarea/i).test(f[0].nodeName),e=d&&c.ui.hasScroll(f[0],"left")?0:l.sizeDiff.height,j=d?0:l.sizeDiff.width;var m={width:(l.size.width-j),height:(l.size.height-e)},i=(parseInt(l.element.css("left"),10)+(l.position.left-l.originalPosition.left))||null,k=(parseInt(l.element.css("top"),10)+(l.position.top-l.originalPosition.top))||null;if(!h.animate){this.element.css(c.extend(m,{top:k,left:i}))}l.helper.height(l.size.height);l.helper.width(l.size.width);if(this._helper&&!h.animate){this._proportionallyResize()}}c("body").css("cursor","auto");this.element.removeClass("ui-resizable-resizing");this._propagate("stop",g);if(this._helper){this.helper.remove()}return false},_updateCache:function(d){var e=this.options;this.offset=this.helper.offset();if(a(d.left)){this.position.left=d.left}if(a(d.top)){this.position.top=d.top}if(a(d.height)){this.size.height=d.height}if(a(d.width)){this.size.width=d.width}},_updateRatio:function(g,f){var h=this.options,i=this.position,e=this.size,d=this.axis;if(g.height){g.width=(e.height*this.aspectRatio)}else{if(g.width){g.height=(e.width/this.aspectRatio)}}if(d=="sw"){g.left=i.left+(e.width-g.width);g.top=null}if(d=="nw"){g.top=i.top+(e.height-g.height);g.left=i.left+(e.width-g.width)}return g},_respectSize:function(k,f){var i=this.helper,h=this.options,q=this._aspectRatio||f.shiftKey,p=this.axis,s=a(k.width)&&h.maxWidth&&(h.maxWidthk.width),r=a(k.height)&&h.minHeight&&(h.minHeight>k.height);if(g){k.width=h.minWidth}if(r){k.height=h.minHeight}if(s){k.width=h.maxWidth}if(l){k.height=h.maxHeight}var e=this.originalPosition.left+this.originalSize.width,n=this.position.top+this.size.height;var j=/sw|nw|w/.test(p),d=/nw|ne|n/.test(p);if(g&&j){k.left=e-h.minWidth}if(s&&j){k.left=e-h.maxWidth}if(r&&d){k.top=n-h.minHeight}if(l&&d){k.top=n-h.maxHeight}var m=!k.width&&!k.height;if(m&&!k.left&&k.top){k.top=null}else{if(m&&!k.top&&k.left){k.left=null}}return k},_proportionallyResize:function(){var j=this.options;if(!this._proportionallyResizeElements.length){return}var f=this.helper||this.element;for(var e=0;e');var d=c.browser.msie&&c.browser.version<7,f=(d?1:0),g=(d?2:-1);this.helper.addClass(this._helper).css({width:this.element.outerWidth()+g,height:this.element.outerHeight()+g,position:"absolute",left:this.elementOffset.left-f+"px",top:this.elementOffset.top-f+"px",zIndex:++h.zIndex});this.helper.appendTo("body").disableSelection()}else{this.helper=this.element}},_change:{e:function(f,e,d){return{width:this.originalSize.width+e}},w:function(g,e,d){var i=this.options,f=this.originalSize,h=this.originalPosition;return{left:h.left+e,width:f.width-e}},n:function(g,e,d){var i=this.options,f=this.originalSize,h=this.originalPosition;return{top:h.top+d,height:f.height-d}},s:function(f,e,d){return{height:this.originalSize.height+d}},se:function(f,e,d){return c.extend(this._change.s.apply(this,arguments),this._change.e.apply(this,[f,e,d]))},sw:function(f,e,d){return c.extend(this._change.s.apply(this,arguments),this._change.w.apply(this,[f,e,d]))},ne:function(f,e,d){return c.extend(this._change.n.apply(this,arguments),this._change.e.apply(this,[f,e,d]))},nw:function(f,e,d){return c.extend(this._change.n.apply(this,arguments),this._change.w.apply(this,[f,e,d]))}},_propagate:function(e,d){c.ui.plugin.call(this,e,[d,this.ui()]);(e!="resize"&&this._trigger(e,d,this.ui()))},plugins:{},ui:function(){return{originalElement:this.originalElement,element:this.element,helper:this.helper,position:this.position,size:this.size,originalSize:this.originalSize,originalPosition:this.originalPosition}}}));c.extend(c.ui.resizable,{version:"1.7.2",eventPrefix:"resize",defaults:{alsoResize:false,animate:false,animateDuration:"slow",animateEasing:"swing",aspectRatio:false,autoHide:false,cancel:":input,option",containment:false,delay:0,distance:1,ghost:false,grid:false,handles:"e,s,se",helper:false,maxHeight:null,maxWidth:null,minHeight:10,minWidth:10,zIndex:1000}});c.ui.plugin.add("resizable","alsoResize",{start:function(e,f){var d=c(this).data("resizable"),g=d.options;_store=function(h){c(h).each(function(){c(this).data("resizable-alsoresize",{width:parseInt(c(this).width(),10),height:parseInt(c(this).height(),10),left:parseInt(c(this).css("left"),10),top:parseInt(c(this).css("top"),10)})})};if(typeof(g.alsoResize)=="object"&&!g.alsoResize.parentNode){if(g.alsoResize.length){g.alsoResize=g.alsoResize[0];_store(g.alsoResize)}else{c.each(g.alsoResize,function(h,i){_store(h)})}}else{_store(g.alsoResize)}},resize:function(f,h){var e=c(this).data("resizable"),i=e.options,g=e.originalSize,k=e.originalPosition;var j={height:(e.size.height-g.height)||0,width:(e.size.width-g.width)||0,top:(e.position.top-k.top)||0,left:(e.position.left-k.left)||0},d=function(l,m){c(l).each(function(){var p=c(this),q=c(this).data("resizable-alsoresize"),o={},n=m&&m.length?m:["width","height","top","left"];c.each(n||["width","height","top","left"],function(r,t){var s=(q[t]||0)+(j[t]||0);if(s&&s>=0){o[t]=s||null}});if(/relative/.test(p.css("position"))&&c.browser.opera){e._revertToRelativePosition=true;p.css({position:"absolute",top:"auto",left:"auto"})}p.css(o)})};if(typeof(i.alsoResize)=="object"&&!i.alsoResize.nodeType){c.each(i.alsoResize,function(l,m){d(l,m)})}else{d(i.alsoResize)}},stop:function(e,f){var d=c(this).data("resizable");if(d._revertToRelativePosition&&c.browser.opera){d._revertToRelativePosition=false;el.css({position:"relative"})}c(this).removeData("resizable-alsoresize-start")}});c.ui.plugin.add("resizable","animate",{stop:function(h,m){var n=c(this).data("resizable"),i=n.options;var g=n._proportionallyResizeElements,d=g.length&&(/textarea/i).test(g[0].nodeName),e=d&&c.ui.hasScroll(g[0],"left")?0:n.sizeDiff.height,k=d?0:n.sizeDiff.width;var f={width:(n.size.width-k),height:(n.size.height-e)},j=(parseInt(n.element.css("left"),10)+(n.position.left-n.originalPosition.left))||null,l=(parseInt(n.element.css("top"),10)+(n.position.top-n.originalPosition.top))||null;n.element.animate(c.extend(f,l&&j?{top:l,left:j}:{}),{duration:i.animateDuration,easing:i.animateEasing,step:function(){var o={width:parseInt(n.element.css("width"),10),height:parseInt(n.element.css("height"),10),top:parseInt(n.element.css("top"),10),left:parseInt(n.element.css("left"),10)};if(g&&g.length){c(g[0]).css({width:o.width,height:o.height})}n._updateCache(o);n._propagate("resize",h)}})}});c.ui.plugin.add("resizable","containment",{start:function(e,q){var s=c(this).data("resizable"),i=s.options,k=s.element;var f=i.containment,j=(f instanceof c)?f.get(0):(/parent/.test(f))?k.parent().get(0):f;if(!j){return}s.containerElement=c(j);if(/document/.test(f)||f==document){s.containerOffset={left:0,top:0};s.containerPosition={left:0,top:0};s.parentData={element:c(document),left:0,top:0,width:c(document).width(),height:c(document).height()||document.body.parentNode.scrollHeight}}else{var m=c(j),h=[];c(["Top","Right","Left","Bottom"]).each(function(p,o){h[p]=b(m.css("padding"+o))});s.containerOffset=m.offset();s.containerPosition=m.position();s.containerSize={height:(m.innerHeight()-h[3]),width:(m.innerWidth()-h[1])};var n=s.containerOffset,d=s.containerSize.height,l=s.containerSize.width,g=(c.ui.hasScroll(j,"left")?j.scrollWidth:l),r=(c.ui.hasScroll(j)?j.scrollHeight:d);s.parentData={element:j,left:n.left,top:n.top,width:g,height:r}}},resize:function(f,p){var s=c(this).data("resizable"),h=s.options,e=s.containerSize,n=s.containerOffset,l=s.size,m=s.position,q=s._aspectRatio||f.shiftKey,d={top:0,left:0},g=s.containerElement;if(g[0]!=document&&(/static/).test(g.css("position"))){d=n}if(m.left<(s._helper?n.left:0)){s.size.width=s.size.width+(s._helper?(s.position.left-n.left):(s.position.left-d.left));if(q){s.size.height=s.size.width/h.aspectRatio}s.position.left=h.helper?n.left:0}if(m.top<(s._helper?n.top:0)) +{s.size.height=s.size.height+(s._helper?(s.position.top-n.top):s.position.top);if(q){s.size.width=s.size.height*h.aspectRatio}s.position.top=s._helper?n.top:0}s.offset.left=s.parentData.left+s.position.left;s.offset.top=s.parentData.top+s.position.top;var k=Math.abs((s._helper?s.offset.left-d.left:(s.offset.left-d.left))+s.sizeDiff.width),r=Math.abs((s._helper?s.offset.top-d.top:(s.offset.top-n.top))+s.sizeDiff.height);var j=s.containerElement.get(0)==s.element.parent().get(0),i=/relative|absolute/.test(s.containerElement.css("position"));if(j&&i){k-=s.parentData.left}if(k+s.size.width>=s.parentData.width){s.size.width=s.parentData.width-k;if(q){s.size.height=s.size.width/s.aspectRatio}}if(r+s.size.height>=s.parentData.height){s.size.height=s.parentData.height-r;if(q){s.size.width=s.size.height*s.aspectRatio}}},stop:function(e,m){var p=c(this).data("resizable"),f=p.options,k=p.position,l=p.containerOffset,d=p.containerPosition,g=p.containerElement;var i=c(p.helper),q=i.offset(),n=i.outerWidth()-p.sizeDiff.width,j=i.outerHeight()-p.sizeDiff.height;if(p._helper&&!f.animate&&(/relative/).test(g.css("position"))){c(this).css({left:q.left-d.left-l.left,width:n,height:j})}if(p._helper&&!f.animate&&(/static/).test(g.css("position"))){c(this).css({left:q.left-d.left-l.left,width:n,height:j})}}});c.ui.plugin.add("resizable","ghost",{start:function(f,g){var d=c(this).data("resizable"),h=d.options,e=d.size;d.ghost=d.originalElement.clone();d.ghost.css({opacity:0.25,display:"block",position:"relative",height:e.height,width:e.width,margin:0,left:0,top:0}).addClass("ui-resizable-ghost").addClass(typeof h.ghost=="string"?h.ghost:"");d.ghost.appendTo(d.helper)},resize:function(e,f){var d=c(this).data("resizable"),g=d.options;if(d.ghost){d.ghost.css({position:"relative",height:d.size.height,width:d.size.width})}},stop:function(e,f){var d=c(this).data("resizable"),g=d.options;if(d.ghost&&d.helper){d.helper.get(0).removeChild(d.ghost.get(0))}}});c.ui.plugin.add("resizable","grid",{resize:function(d,l){var n=c(this).data("resizable"),g=n.options,j=n.size,h=n.originalSize,i=n.originalPosition,m=n.axis,k=g._aspectRatio||d.shiftKey;g.grid=typeof g.grid=="number"?[g.grid,g.grid]:g.grid;var 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o=$.scrollTo=function(a,b,c){o.window().scrollTo(a,b,c)};o.defaults={axis:'y',duration:1};o.window=function(){return $($.browser.safari?'body':'html')};$.fn.scrollTo=function(l,m,n){if(typeof m=='object'){n=m;m=0}n=$.extend({},o.defaults,n);m=m||n.speed||n.duration;n.queue=n.queue&&n.axis.length>1;if(n.queue)m/=2;n.offset=j(n.offset);n.over=j(n.over);return this.each(function(){var a=this,b=$(a),t=l,c,d={},w=b.is('html,body');switch(typeof t){case'number':case'string':if(/^([+-]=)?\d+(px)?$/.test(t)){t=j(t);break}t=$(t,this);case'object':if(t.is||t.style)c=(t=$(t)).offset()}$.each(n.axis.split(''),function(i,f){var P=f=='x'?'Left':'Top',p=P.toLowerCase(),k='scroll'+P,e=a[k],D=f=='x'?'Width':'Height';if(c){d[k]=c[p]+(w?0:e-b.offset()[p]);if(n.margin){d[k]-=parseInt(t.css('margin'+P))||0;d[k]-=parseInt(t.css('border'+P+'Width'))||0}d[k]+=n.offset[p]||0;if(n.over[p])d[k]+=t[D.toLowerCase()]()*n.over[p]}else d[k]=t[p];if(/^\d+$/.test(d[k]))d[k]=d[k]<=0?0:Math.min(d[k],h(D));if(!i&&n.queue){if(e!=d[k])g(n.onAfterFirst);delete d[k]}});g(n.onAfter);function g(a){b.animate(d,m,n.easing,a&&function(){a.call(this,l)})};function h(D){var b=w?$.browser.opera?document.body:document.documentElement:a;return b['scroll'+D]-b['client'+D]}})};function j(a){return typeof a=='object'?a:{top:a,left:a}}})(jQuery); + diff --git a/Libraries/CMSIS/Documentation/SVD/html/modules.html b/Libraries/CMSIS/Documentation/SVD/html/modules.html new file mode 100644 index 0000000..cf33191 --- /dev/null +++ b/Libraries/CMSIS/Documentation/SVD/html/modules.html @@ -0,0 +1,119 @@ + + + + +Reference + + + + + + + + + + + +
    + +
    + + + + + + + + + + + +
    +
    CMSIS-SVD +  Version 1.10 +
    +
    CMSIS System View Description
    +
    +
    + +
    + +
    + + + +
    +
    + +
    +
    +
    + +
    +
    +
    +
    Reference
    +
    +
    +
    Here is a list of all modules:
    +
    +
    + + + + + diff --git a/Libraries/CMSIS/Documentation/SVD/html/nav_f.png b/Libraries/CMSIS/Documentation/SVD/html/nav_f.png new file mode 100644 index 0000000000000000000000000000000000000000..1b07a16207e67c95fe2ee17e7016e6d08ac7ac99 GIT binary patch literal 159 zcmeAS@N?(olHy`uVBq!ia0vp^j6iI`!2~2XGqLUlQfZzpjv*C{Z|{2YIT`Y>1X`Eg z-tTbne1`SITM8Q!Pb(<)UFZ(m>wMzvKZQqKM~~GcZ=A7j<~E6K62>ozFS=cD3)mf8 z9WX0+R&m(l9KUsLdTx4?9~({T__KA%`}olPJ^N;y|F^pHgs_K%!rj~{8>RwnWbkzL Kb6Mw<&;$VTdq1fF literal 0 HcmV?d00001 diff --git a/Libraries/CMSIS/Documentation/SVD/html/nav_h.png b/Libraries/CMSIS/Documentation/SVD/html/nav_h.png new file mode 100644 index 0000000000000000000000000000000000000000..01f5fa6a596e36bd12c2d6ceff1b0169fda7e699 GIT binary patch literal 97 zcmeAS@N?(olHy`uVBq!ia0vp^j6lr8!2~3AUOE6t1`SUa$B+ufw|6&kG8phMJMJ~w va4>Y+bZ&9QY?(VEUPY_cGd9nQ`um^ZSUyYpAAuKhL7F^W{an^LB{Ts5DmojT literal 0 HcmV?d00001 diff --git a/Libraries/CMSIS/Documentation/SVD/html/navtree.css b/Libraries/CMSIS/Documentation/SVD/html/navtree.css new file mode 100644 index 0000000..e46ffcd --- /dev/null +++ b/Libraries/CMSIS/Documentation/SVD/html/navtree.css @@ -0,0 +1,123 @@ +#nav-tree .children_ul { + margin:0; + padding:4px; +} + +#nav-tree ul { + list-style:none outside none; + margin:0px; + padding:0px; +} + +#nav-tree li { + white-space:nowrap; + margin:0px; + padding:0px; +} + +#nav-tree .plus { + margin:0px; +} + +#nav-tree .selected { + background-image: url('tab_a.png'); + background-repeat:repeat-x; + color: #fff; + text-shadow: 0px 1px 1px rgba(0, 0, 0, 1.0); +} + +#nav-tree img { + margin:0px; + padding:0px; + border:0px; + vertical-align: middle; +} + +#nav-tree a { + text-decoration:none; + padding:0px; + margin:0px; + outline:none; +} + +#nav-tree .label { + margin:0px; + padding:0px; +} + +#nav-tree .label a { + padding:2px; +} + +#nav-tree .selected a { + text-decoration:none; + padding:2px; + margin:0px; + color:#fff; +} + +#nav-tree .children_ul { + margin:0px; + padding:0px; +} + +#nav-tree .item { + margin:0px; + padding:0px; +} + +#nav-tree { + padding: 0px 0px; + background-color: #FAFAFF; + font-size:14px; + overflow:auto; +} + +#doc-content { + overflow:auto; + display:block; + padding:0px; + margin:0px; +} + +#side-nav { + padding:0 6px 0 0; + margin: 0px; + display:block; + position: absolute; + left: 0px; + width: 300px; +} + +.ui-resizable .ui-resizable-handle { + display:block; +} + +.ui-resizable-e { + background:url("ftv2splitbar.png") repeat scroll right center transparent; + cursor:e-resize; + height:100%; + right:0; + top:0; + width:6px; +} + +.ui-resizable-handle { + display:none; + font-size:0.1px; + position:absolute; + z-index:1; +} + +#nav-tree-contents { + margin: 6px 0px 0px 0px; +} + +#nav-tree { + background-image:url('nav_h.png'); + background-repeat:repeat-x; + background-color: #F9FAFC; +} + + + diff --git a/Libraries/CMSIS/Documentation/SVD/html/navtree.js b/Libraries/CMSIS/Documentation/SVD/html/navtree.js new file mode 100644 index 0000000..18ba992 --- /dev/null +++ b/Libraries/CMSIS/Documentation/SVD/html/navtree.js @@ -0,0 +1,285 @@ +var NAVTREE = +[ + [ "CMSIS-SVD", "index.html", [ + [ "System View Description", "index.html", [ + [ "CMSIS-SVD Web Interface User Guide", "svd_web_pg.html", [ + [ "Public Download Area", "svd_web_public_pg.html", null ], + [ "Restricted Management Area", "svd_web_restricted_pg.html", null ] + ] ], + [ "SVD File Description", "svd__outline_pg.html", null ] + ] ], + [ "Usage and Description", "pages.html", [ + [ "SVD File Validation", "svd_validate_file_pg.html", null ], + [ "SVD File Usage", "svd__usage_pg.html", null ], + [ "SVD File Example", "svd__example_pg.html", null ] + ] ], + [ "Reference", "modules.html", [ + [ "SVD File Schema Levels", "group__svd___format__gr.html", [ + [ "Device Level", "group__svd__xml__device__gr.html", null ], + [ "Peripherals Level", "group__svd__xml__peripherals__gr.html", null ], + [ "Registers Level", "group__svd__xml__registers__gr.html", null ], + [ "Fields Level", "group__svd__xml__fields__gr.html", null ], + [ "Enumerated Values Level", "group__svd__xml__enum__gr.html", null ] + ] ], + [ "Element Groups", "group__elem__type__gr.html", [ + [ "dimElementGroup", "group__dim_element_group__gr.html", null ], + [ "registerPropertiesGroup", "group__register_properties_group__gr.html", null ] + ] ], + [ "SVD Extension in Version 1.1", "group__svd___format__1__1__gr.html", [ + [ "Extensions to the Device Section", "group__device_section_extensions__gr.html", null ], + [ "CPU Section (New)", "group__cpu_section__gr.html", null ], + [ "Extensions to the Peripheral Section", "group__peripheral_section_extensions__gr.html", null ], + [ "Cluster Level (New)", "group__cluster_level__gr.html", null ], + [ "Extensions to the Register Section", "group__register_section_extensions__gr.html", null ] + ] ], + [ "CMSIS-SVD Schema File Ver. 1.0", "group__schema__gr.html", null ], + [ "CMSIS-SVD Schema File Ver. 1.1 (draft)", "group__schema__1__1__gr.html", null ] + ] ] + ] ] +]; + +function createIndent(o,domNode,node,level) +{ + if (node.parentNode && node.parentNode.parentNode) + { + createIndent(o,domNode,node.parentNode,level+1); + } + var imgNode = document.createElement("img"); + if (level==0 && node.childrenData) + { + node.plus_img = imgNode; + node.expandToggle = document.createElement("a"); + node.expandToggle.href = "javascript:void(0)"; + node.expandToggle.onclick = function() + { + if (node.expanded) + { + $(node.getChildrenUL()).slideUp("fast"); + if (node.isLast) + { + node.plus_img.src = node.relpath+"ftv2plastnode.png"; + } + else + { + node.plus_img.src = node.relpath+"ftv2pnode.png"; + } + node.expanded = false; + } + else + { + expandNode(o, node, false); + } + } + node.expandToggle.appendChild(imgNode); + domNode.appendChild(node.expandToggle); + } + else + { + domNode.appendChild(imgNode); + } + if (level==0) + { + if (node.isLast) + { + if (node.childrenData) + { + imgNode.src = node.relpath+"ftv2plastnode.png"; + } + else + { + imgNode.src = node.relpath+"ftv2lastnode.png"; + domNode.appendChild(imgNode); + } + } + else + { + if (node.childrenData) + { + imgNode.src = node.relpath+"ftv2pnode.png"; + } + else + { + imgNode.src = node.relpath+"ftv2node.png"; + domNode.appendChild(imgNode); + } + } + } + else + { + if (node.isLast) + { + imgNode.src = node.relpath+"ftv2blank.png"; + } + else + { + imgNode.src = node.relpath+"ftv2vertline.png"; + } + } + imgNode.border = "0"; +} + +function newNode(o, po, text, link, childrenData, lastNode) +{ + var node = new Object(); + node.children = Array(); + node.childrenData = childrenData; + node.depth = po.depth + 1; + node.relpath = po.relpath; + node.isLast = lastNode; + + node.li = document.createElement("li"); + po.getChildrenUL().appendChild(node.li); + node.parentNode = po; + + node.itemDiv = document.createElement("div"); + node.itemDiv.className = "item"; + + node.labelSpan = document.createElement("span"); + node.labelSpan.className = "label"; + + createIndent(o,node.itemDiv,node,0); + node.itemDiv.appendChild(node.labelSpan); + node.li.appendChild(node.itemDiv); + + var a = document.createElement("a"); + node.labelSpan.appendChild(a); + node.label = document.createTextNode(text); + a.appendChild(node.label); + if (link) + { + a.href = node.relpath+link; + } + else + { + if (childrenData != null) + { + a.className = "nolink"; + a.href = "javascript:void(0)"; + a.onclick = node.expandToggle.onclick; + node.expanded = false; + } + } + + node.childrenUL = null; + node.getChildrenUL = function() + { + if (!node.childrenUL) + { + node.childrenUL = document.createElement("ul"); + node.childrenUL.className = "children_ul"; + node.childrenUL.style.display = "none"; + node.li.appendChild(node.childrenUL); + } + return node.childrenUL; + }; + + return node; +} + +function showRoot() +{ + var headerHeight = $("#top").height(); + var footerHeight = $("#nav-path").height(); + var windowHeight = $(window).height() - headerHeight - footerHeight; + navtree.scrollTo('#selected',0,{offset:-windowHeight/2}); +} + +function expandNode(o, node, imm) +{ + if (node.childrenData && !node.expanded) + { + if (!node.childrenVisited) + { + getNode(o, node); + } + if (imm) + { + $(node.getChildrenUL()).show(); + } + else + { + $(node.getChildrenUL()).slideDown("fast",showRoot); + } + if (node.isLast) + { + node.plus_img.src = node.relpath+"ftv2mlastnode.png"; + } + else + { + node.plus_img.src = node.relpath+"ftv2mnode.png"; + } + node.expanded = true; + } +} + +function getNode(o, po) +{ + po.childrenVisited = true; + var l = po.childrenData.length-1; + for (var i in po.childrenData) + { + var nodeData = po.childrenData[i]; + po.children[i] = newNode(o, po, nodeData[0], nodeData[1], nodeData[2], + i==l); + } +} + +function findNavTreePage(url, data) +{ + var nodes = data; + var result = null; + for (var i in nodes) + { + var d = nodes[i]; + if (d[1] == url) + { + return new Array(i); + } + else if (d[2] != null) // array of children + { + result = findNavTreePage(url, d[2]); + if (result != null) + { + return (new Array(i).concat(result)); + } + } + } + return null; +} + +function initNavTree(toroot,relpath) +{ + var o = new Object(); + o.toroot = toroot; + o.node = new Object(); + o.node.li = document.getElementById("nav-tree-contents"); + o.node.childrenData = NAVTREE; + o.node.children = new Array(); + o.node.childrenUL = document.createElement("ul"); + o.node.getChildrenUL = function() { return o.node.childrenUL; }; + o.node.li.appendChild(o.node.childrenUL); + o.node.depth = 0; + o.node.relpath = relpath; + + getNode(o, o.node); + + o.breadcrumbs = findNavTreePage(toroot, NAVTREE); + if (o.breadcrumbs == null) + { + o.breadcrumbs = findNavTreePage("index.html",NAVTREE); + } + if (o.breadcrumbs != null && o.breadcrumbs.length>0) + { + var p = o.node; + for (var i in o.breadcrumbs) + { + var j = o.breadcrumbs[i]; + p = p.children[j]; + expandNode(o,p,true); + } + p.itemDiv.className = p.itemDiv.className + " selected"; + p.itemDiv.id = "selected"; + $(window).load(showRoot); + } +} + diff --git a/Libraries/CMSIS/Documentation/SVD/html/open.png b/Libraries/CMSIS/Documentation/SVD/html/open.png new file mode 100644 index 0000000000000000000000000000000000000000..7b35d2c2c389743089632fe24c3104f2173d97af GIT binary patch literal 118 zcmeAS@N?(olHy`uVBq!ia0vp^oFL4>1|%O$WD@{Vww^AIAr*{o=Nbw!DDW^(zOibV zl!F8B0?t?i!vld4k#$~0_AX3zElaokn + + + +Usage and Description + + + + + + + + + + + +
    + +
    + + + + + + + + + + + +
    +
    CMSIS-SVD +  Version 1.10 +
    +
    CMSIS System View Description
    +
    +
    + +
    + +
    + + + +
    +
    + +
    +
    +
    + +
    +
    +
    +
    Usage and Description
    +
    +
    +
    Here is a list of all related documentation pages:
    +
    +
    + + + + + diff --git a/Libraries/CMSIS/Documentation/SVD/html/resize.js b/Libraries/CMSIS/Documentation/SVD/html/resize.js new file mode 100644 index 0000000..04fa95c --- /dev/null +++ b/Libraries/CMSIS/Documentation/SVD/html/resize.js @@ -0,0 +1,81 @@ +var cookie_namespace = 'doxygen'; +var sidenav,navtree,content,header; + +function readCookie(cookie) +{ + var myCookie = cookie_namespace+"_"+cookie+"="; + if (document.cookie) + { + var index = document.cookie.indexOf(myCookie); + if (index != -1) + { + var valStart = index + myCookie.length; + var valEnd = document.cookie.indexOf(";", valStart); + if (valEnd == -1) + { + valEnd = document.cookie.length; + } + var val = document.cookie.substring(valStart, valEnd); + return val; + } + } + return 0; +} + +function writeCookie(cookie, val, expiration) +{ + if (val==undefined) return; + if (expiration == null) + { + var date = new Date(); + date.setTime(date.getTime()+(10*365*24*60*60*1000)); // default expiration is one week + expiration = date.toGMTString(); + } + document.cookie = cookie_namespace + "_" + cookie + "=" + val + "; expires=" + expiration+"; path=/"; +} + +function resizeWidth() +{ + var windowWidth = $(window).width() + "px"; + var sidenavWidth = $(sidenav).width(); + content.css({marginLeft:parseInt(sidenavWidth)+6+"px"}); //account for 6px-wide handle-bar + writeCookie('width',sidenavWidth, null); +} + +function restoreWidth(navWidth) +{ + var windowWidth = $(window).width() + "px"; + content.css({marginLeft:parseInt(navWidth)+6+"px"}); + sidenav.css({width:navWidth + "px"}); +} + +function resizeHeight() +{ + var headerHeight = header.height(); + var footerHeight = footer.height(); + var windowHeight = $(window).height() - headerHeight - footerHeight; + content.css({height:windowHeight + "px"}); + navtree.css({height:windowHeight + "px"}); + sidenav.css({height:windowHeight + "px",top: headerHeight+"px"}); +} + +function initResizable() +{ + header = $("#top"); + sidenav = $("#side-nav"); + content = $("#doc-content"); + navtree = $("#nav-tree"); + footer = $("#nav-path"); + $(".side-nav-resizable").resizable({resize: function(e, ui) { resizeWidth(); } }); + $(window).resize(function() { resizeHeight(); }); + var width = readCookie('width'); + if (width) { restoreWidth(width); } else { resizeWidth(); } + resizeHeight(); + var url = location.href; + var i=url.indexOf("#"); + if (i>=0) window.location.hash=url.substr(i); + var _preventDefault = function(evt) { evt.preventDefault(); }; + $("#splitbar").bind("dragstart", _preventDefault).bind("selectstart", _preventDefault); +} + + diff --git a/Libraries/CMSIS/Documentation/SVD/html/svd__example_pg.html b/Libraries/CMSIS/Documentation/SVD/html/svd__example_pg.html new file mode 100644 index 0000000..c81cae4 --- /dev/null +++ b/Libraries/CMSIS/Documentation/SVD/html/svd__example_pg.html @@ -0,0 +1,833 @@ + + + + +SVD File Example + + + + + + + + + + + +
    + +
    + + + + + + + + + + + +
    +
    CMSIS-SVD +  Version 1.10 +
    +
    CMSIS System View Description
    +
    +
    + +
    + +
    + + + +
    +
    + +
    +
    +
    + +
    +
    +
    +
    SVD File Example
    +
    +
    +
    <?xml version="1.0" encoding="utf-8"?>
+
+<!-- File naming: <vendor>_<part/series name>.svd -->
+
+<!--
+  Copyright (C) 2012 ARM Limited. All rights reserved.
+
+  Purpose: System Viewer Description (SVD) Example (Schema Version 1.0)
+           This is a description of a none-existent and incomplete device
+           for demonstration purposes only.
+ -->
+ 
+<device schemaVersion="1.0" xmlns:xs="http://www.w3.org/2001/XMLSchema-instance" xs:noNamespaceSchemaLocation="CMSIS-SVD_Schema_1_0.xsd" >
+  <name>ARMCM3xxx</name>                                          <!-- name of part or part series -->
+  <version>1.0</version>                                          <!-- version of this description -->
+  <description>ARM 32-bit Cortex-M3 Microcontroller based device, CPU clock up to 80MHz, etc. </description>
+  <addressUnitBits>8</addressUnitBits>                            <!-- byte addressable memory -->
+  <width>32</width>                                               <!-- bus width is 32 bits -->
+  <!-- default settings implicitly inherited by subsequent sections -->
+  <size>32</size>                                                 <!-- this is the default size (number of bits) of all peripherals
+                                                                       and register that do not define "size" themselves -->
+  <access>read-write</access>                                     <!-- default access permission for all subsequent registers -->
+  <resetValue>0x00000000</resetValue>                             <!-- by default all bits of the registers are initialized to 0 on reset -->
+  <resetMask>0xFFFFFFFF</resetMask>                               <!-- by default all 32Bits of the registers are used -->
+
+  <peripherals>
+    <!-- Timer 0 -->
+    <peripheral>
+      <name>TIMER0</name>
+      <version>1.0</version>
+      <description>32 Timer / Counter, counting up or down from different sources</description>
+      <groupName>TIMER</groupName>
+      <baseAddress>0x40010000</baseAddress>
+      <size>32</size>
+      <access>read-write</access>
+
+      <addressBlock>
+        <offset>0</offset>
+        <size>0x100</size>
+        <usage>registers</usage>
+      </addressBlock>
+
+      <interrupt>
+        <name>TIMER0</name>
+        <value>0</value>
+      </interrupt>
+
+      <registers>
+      <!-- CR: Control Register -->
+        <register>
+          <name>CR</name>
+          <description>Control Register</description>
+          <addressOffset>0x00</addressOffset>
+          <size>32</size>
+          <access>read-write</access>
+          <resetValue>0x00000000</resetValue>
+          <resetMask>0x1337F7F</resetMask>
+
+          <fields>
+            <!-- EN: Enable -->
+            <field>
+              <name>EN</name>
+              <description>Enable</description>
+              <bitRange>[0:0]</bitRange>
+              <access>read-write</access>
+              <enumeratedValues>
+                <enumeratedValue>
+                  <name>Disable</name>
+                  <description>Timer is disabled and does not operate</description>
+                  <value>0</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>Enable</name>
+                  <description>Timer is enabled and can operate</description>
+                  <value>1</value>
+                </enumeratedValue>
+              </enumeratedValues>
+            </field>
+
+            <!-- RST: Reset -->
+            <field>
+              <name>RST</name>
+              <description>Reset Timer</description>
+              <bitRange>[1:1]</bitRange>
+              <access>write-only</access>
+              <enumeratedValues>
+                <enumeratedValue>
+                  <name>Reserved</name>
+                  <description>Write as ZERO if necessary</description>
+                  <value>0</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>Reset_Timer</name>
+                  <description>Reset the Timer</description>
+                  <value>1</value>
+                </enumeratedValue>
+              </enumeratedValues>
+            </field>
+
+            <!-- CNT: Counting Direction -->
+            <field>
+              <name>CNT</name>
+              <description>Counting direction</description>
+              <bitRange>[3:2]</bitRange>
+              <access>read-write</access>
+              <enumeratedValues>
+                <enumeratedValue>
+                  <name>Count_UP</name>
+                  <description>Timer Counts UO and wraps, if no STOP condition is set</description>
+                  <value>0</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>Count_DOWN</name>
+                  <description>Timer Counts DOWN and wraps, if no STOP condition is set</description>
+                  <value>1</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>Toggle</name>
+                  <description>Timer Counts up to MAX, then DOWN to ZERO, if no STOP condition is set</description>
+                  <value>2</value>
+                </enumeratedValue>
+              </enumeratedValues>
+            </field>
+
+            <!-- MODE: Operation Mode -->
+            <field>
+              <name>MODE</name>
+              <description>Operation Mode</description>
+              <bitRange>[6:4]</bitRange>
+              <access>read-write</access>
+              <enumeratedValues>
+                <enumeratedValue>
+                  <name>Continous</name>
+                  <description>Timer runs continously</description>
+                  <value>0</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>Single_ZERO_MAX</name>
+                  <description>Timer counts to 0x00 or 0xFFFFFFFF (depending on CNT) and stops</description>
+                  <value>1</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>Single_MATCH</name>
+                  <description>Timer counts to the Value of MATCH Register and stops</description>
+                  <value>2</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>Reload_ZERO_MAX</name>
+                  <description>Timer counts to 0x00 or 0xFFFFFFFF (depending on CNT), loads the RELOAD Value and continues</description>
+                  <value>3</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>Reload_MATCH</name>
+                  <description>Timer counts to the Value of MATCH Register, loads the RELOAD Value and continues</description>
+                  <value>4</value>
+                </enumeratedValue>
+              </enumeratedValues>
+            </field>
+
+            <!-- PSC: Use Prescaler -->
+            <field>
+              <name>PSC</name>
+              <description>Use Prescaler</description>
+              <bitRange>[7:7]</bitRange>
+              <access>read-write</access>
+              <enumeratedValues>
+                <enumeratedValue>
+                  <name>Disabled</name>
+                  <description>Prescaler is not used</description>
+                  <value>0</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>Enabled</name>
+                  <description>Prescaler is used as divider</description>
+                  <value>1</value>
+                </enumeratedValue>
+              </enumeratedValues>
+            </field>
+
+            <!-- CNTSRC: Timer / Counter Soruce Divider -->
+            <field>
+              <name>CNTSRC</name>
+              <description>Timer / Counter Source Divider</description>
+              <bitRange>[11:8]</bitRange>
+              <access>read-write</access>
+              <enumeratedValues>
+                <enumeratedValue>
+                  <name>CAP_SRC</name>
+                  <description>Capture Source is used directly</description>
+                  <value>0</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>CAP_SRC_div2</name>
+                  <description>Capture Source is divided by 2</description>
+                  <value>1</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>CAP_SRC_div4</name>
+                  <description>Capture Source is divided by 4</description>
+                  <value>2</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>CAP_SRC_div8</name>
+                  <description>Capture Source is divided by 8</description>
+                  <value>3</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>CAP_SRC_div16</name>
+                  <description>Capture Source is divided by 16</description>
+                  <value>4</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>CAP_SRC_div32</name>
+                  <description>Capture Source is divided by 32</description>
+                  <value>5</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>CAP_SRC_div64</name>
+                  <description>Capture Source is divided by 64</description>
+                  <value>6</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>CAP_SRC_div128</name>
+                  <description>Capture Source is divided by 128</description>
+                  <value>7</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>CAP_SRC_div256</name>
+                  <description>Capture Source is divided by 256</description>
+                  <value>8</value>
+                </enumeratedValue>
+              </enumeratedValues>
+            </field>
+
+            <!-- CAPSRC: Timer / COunter Capture Source -->
+            <field>
+              <name>CAPSRC</name>
+              <description>Timer / Counter Capture Source</description>
+              <bitRange>[15:12]</bitRange>
+              <access>read-write</access>
+              <enumeratedValues>
+                <enumeratedValue>
+                  <name>CClk</name>
+                  <description>Core Clock</description>
+                  <value>0</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>GPIOA_0</name>
+                  <description>GPIO A, PIN 0</description>
+                  <value>1</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>GPIOA_1</name>
+                  <description>GPIO A, PIN 1</description>
+                  <value>2</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>GPIOA_2</name>
+                  <description>GPIO A, PIN 2</description>
+                  <value>3</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>GPIOA_3</name>
+                  <description>GPIO A, PIN 3</description>
+                  <value>4</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>GPIOA_4</name>
+                  <description>GPIO A, PIN 4</description>
+                  <value>5</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>GPIOA_5</name>
+                  <description>GPIO A, PIN 5</description>
+                  <value>6</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>GPIOA_6</name>
+                  <description>GPIO A, PIN 6</description>
+                  <value>7</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>GPIOA_7</name>
+                  <description>GPIO A, PIN 7</description>
+                  <value>8</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>GPIOB_0</name>
+                  <description>GPIO B, PIN 0</description>
+                  <value>9</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>GPIOB_1</name>
+                  <description>GPIO B, PIN 1</description>
+                  <value>10</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>GPIOB_2</name>
+                  <description>GPIO B, PIN 2</description>
+                  <value>11</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>GPIOB_3</name>
+                  <description>GPIO B, PIN 3</description>
+                  <value>12</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>GPIOC_0</name>
+                  <description>GPIO C, PIN 0</description>
+                  <value>13</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>GPIOC_5</name>
+                  <description>GPIO C, PIN 1</description>
+                  <value>14</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>GPIOC_6</name>
+                  <description>GPIO C, PIN 2</description>
+                  <value>15</value>
+                </enumeratedValue>
+              </enumeratedValues>
+            </field>
+
+            <!-- CAPEDGE: Capture Edge -->
+            <field>
+              <name>CAPEDGE</name>
+              <description>Capture Edge, select which Edge should result in a counter increment or decrement</description>
+              <bitRange>[17:16]</bitRange>
+              <access>read-write</access>
+              <enumeratedValues>
+                <enumeratedValue>
+                  <name>RISING</name>
+                  <description>Only rising edges result in a counter increment or decrement</description>
+                  <value>0</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>FALLING</name>
+                  <description>Only falling edges  result in a counter increment or decrement</description>
+                  <value>1</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>BOTH</name>
+                  <description>Rising and falling edges result in a counter increment or decrement</description>
+                  <value>2</value>
+                </enumeratedValue>
+              </enumeratedValues>
+            </field>
+
+            <!-- TRGEXT: Triggers an other Peripheral -->
+            <field>
+              <name>TRGEXT</name>
+              <description>Triggers an other Peripheral</description>
+              <bitRange>[21:20]</bitRange>
+              <access>read-write</access>
+              <enumeratedValues>
+                <enumeratedValue>
+                  <name>NONE</name>
+                  <description>No Trigger is emitted</description>
+                  <value>0</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>DMA1</name>
+                  <description>DMA Controller 1 is triggered, dependant on MODE</description>
+                  <value>1</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>DMA2</name>
+                  <description>DMA Controller 2 is triggered, dependant on MODE</description>
+                  <value>2</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>UART</name>
+                  <description>UART is triggered, dependant on MODE</description>
+                  <value>3</value>
+                </enumeratedValue>
+              </enumeratedValues>
+            </field>
+
+            <!-- Reload: Selects Reload Register n -->
+            <field>
+              <name>RELOAD</name>
+              <description>Select RELOAD Register n to reload Timer on condition</description>
+              <bitRange>[25:24]</bitRange>
+              <access>read-write</access>
+              <enumeratedValues>
+                <enumeratedValue>
+                  <name>RELOAD0</name>
+                  <description>Selects Reload Register number 0</description>
+                  <value>0</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>RELOAD1</name>
+                  <description>Selects Reload Register number 1</description>
+                  <value>1</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>RELOAD2</name>
+                  <description>Selects Reload Register number 2</description>
+                  <value>2</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>RELOAD3</name>
+                  <description>Selects Reload Register number 3</description>
+                  <value>3</value>
+                </enumeratedValue>
+              </enumeratedValues>
+            </field>
+
+            <!-- IDR: Inc or dec Reload Register Selection -->
+            <field>
+              <name>IDR</name>
+              <description>Selects, if Reload Register number is incremented, decremented or not modified</description>
+              <bitRange>[27:26]</bitRange>
+              <access>read-write</access>
+              <enumeratedValues>
+                <enumeratedValue>
+                  <name>KEEP</name>
+                  <description>Reload Register number does not change automatically</description>
+                  <value>0</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>INCREMENT</name>
+                  <description>Reload Register number is incremented on each match</description>
+                  <value>1</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>DECREMENT</name>
+                  <description>Reload Register number is decremented on each match</description>
+                  <value>2</value>
+                </enumeratedValue>
+              </enumeratedValues>
+            </field>
+
+            <!-- START: Starts / Stops the Timer/Counter -->
+            <field>
+              <name>S</name>
+              <description>Starts and Stops the Timer / Counter</description>
+              <bitRange>[31:31]</bitRange>
+              <access>read-write</access>
+              <enumeratedValues>
+                <enumeratedValue>
+                  <name>STOP</name>
+                  <description>Timer / Counter is stopped</description>
+                  <value>0</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>START</name>
+                  <description>Timer / Counter is started</description>
+                  <value>1</value>
+                </enumeratedValue>
+              </enumeratedValues>
+            </field>
+          </fields>
+        </register>
+
+        <!-- SR: Status Register -->
+        <register>
+          <name>SR</name>
+          <description>Status Register</description>
+          <addressOffset>0x04</addressOffset>
+          <size>16</size>
+          <access>read-write</access>
+          <resetValue>0x00000000</resetValue>
+          <resetMask>0xD701</resetMask>
+
+          <fields>
+            <!-- RUN: Shows if Timer is running -->
+            <field>
+              <name>RUN</name>
+              <description>Shows if Timer is running or not</description>
+              <bitRange>[0:0]</bitRange>
+              <access>read-only</access>
+              <enumeratedValues>
+                <enumeratedValue>
+                  <name>Stopped</name>
+                  <description>Timer is not running</description>
+                  <value>0</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>Running</name>
+                  <description>Timer is running</description>
+                  <value>1</value>
+                </enumeratedValue>
+              </enumeratedValues>
+            </field>
+
+            <!-- MATCH: Shows if a Match was hit -->
+            <field>
+              <name>MATCH</name>
+              <description>Shows if the MATCH was hit</description>
+              <bitRange>[8:8]</bitRange>
+              <access>read-write</access>
+              <enumeratedValues>
+                <enumeratedValue>
+                  <name>No_Match</name>
+                  <description>The MATCH condition was not hit</description>
+                  <value>0</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>Match_Hit</name>
+                  <description>The MATCH condition was hit</description>
+                  <value>1</value>
+                </enumeratedValue>
+              </enumeratedValues>
+            </field>
+
+            <!-- UN: Shows if an underflow occured -->
+            <field>
+              <name>UN</name>
+              <description>Shows if an underflow occured. This flag is sticky</description>
+              <bitRange>[9:9]</bitRange>
+              <access>read-write</access>
+              <enumeratedValues>
+                <enumeratedValue>
+                  <name>No_Underflow</name>
+                  <description>No underflow occured since last clear</description>
+                  <value>0</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>Underflow</name>
+                  <description>A minimum of one underflow occured since last clear</description>
+                  <value>1</value>
+                </enumeratedValue>
+              </enumeratedValues>
+            </field>
+
+            <!-- OV: Shows if an overflow occured -->
+            <field>
+              <name>OV</name>
+              <description>Shows if an overflow occured. This flag is sticky</description>
+              <bitRange>[10:10]</bitRange>
+              <access>read-write</access>
+              <enumeratedValues>
+                <enumeratedValue>
+                  <name>No_Overflow</name>
+                  <description>No overflow occured since last clear</description>
+                  <value>0</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>Overflow_occured</name>
+                  <description>A minimum of one overflow occured since last clear</description>
+                  <value>1</value>
+                </enumeratedValue>
+              </enumeratedValues>
+            </field>
+
+            <!-- RST: Shows if Timer is in RESET state -->
+            <field>
+              <name>RST</name>
+              <description>Shows if Timer is in RESET state</description>
+              <bitRange>[12:12]</bitRange>
+              <access>read-only</access>
+              <enumeratedValues>
+                <enumeratedValue>
+                  <name>Ready</name>
+                  <description>Timer is not in RESET state and can operate</description>
+                  <value>0</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>In_Reset</name>
+                  <description>Timer is in RESET state and can not operate</description>
+                  <value>1</value>
+                </enumeratedValue>
+              </enumeratedValues>
+            </field>
+
+            <!-- RELOAD: Shows the currently active Reload Register -->
+            <field>
+              <name>RELOAD</name>
+              <description>Shows the currently active RELOAD Register</description>
+              <bitRange>[15:14]</bitRange>
+              <access>read-only</access>
+              <enumeratedValues>
+                <enumeratedValue>
+                  <name>RELOAD0</name>
+                  <description>Reload Register number 0 is active</description>
+                  <value>0</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>RELOAD1</name>
+                  <description>Reload Register number 1 is active</description>
+                  <value>1</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>RELOAD2</name>
+                  <description>Reload Register number 2 is active</description>
+                  <value>2</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>RELOAD3</name>
+                  <description>Reload Register number 3 is active</description>
+                  <value>3</value>
+                </enumeratedValue>
+              </enumeratedValues>
+            </field>
+          </fields>
+        </register>
+
+        <!-- INT: Interrupt Register -->
+        <register>
+          <name>INT</name>
+          <description>Interrupt Register</description>
+          <addressOffset>0x10</addressOffset>
+          <size>16</size>
+          <access>read-write</access>
+          <resetValue>0x00000000</resetValue>
+          <resetMask>0x0771</resetMask>
+
+          <fields>
+            <!-- EN: Interrupt Enable -->
+            <field>
+              <name>EN</name>
+              <description>Interrupt Enable</description>
+              <bitRange>[0:0]</bitRange>
+              <access>read-write</access>
+              <enumeratedValues>
+                <enumeratedValue>
+                  <name>Disabled</name>
+                  <description>Timer does not generate Interrupts</description>
+                  <value>0</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>Enable</name>
+                  <description>Timer triggers the TIMERn Interrupt</description>
+                  <value>1</value>
+                </enumeratedValue>
+              </enumeratedValues>
+            </field>
+
+            <!-- MODE: Interrupt Mode -->
+            <field>
+              <name>MODE</name>
+              <description>Interrupt Mode, selects on which condition the Timer should generate an Interrupt</description>
+              <bitRange>[6:4]</bitRange>
+              <access>read-write</access>
+              <enumeratedValues>
+                <enumeratedValue>
+                  <name>Match</name>
+                  <description>Timer generates an Interrupt when the MATCH condition is hit</description>
+                  <value>0</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>Underflow</name>
+                  <description>Timer generates an Interrupt when it underflows</description>
+                  <value>1</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>Overflow</name>
+                  <description>Timer generates an Interrupt when it overflows</description>
+                  <value>2</value>
+                </enumeratedValue>
+              </enumeratedValues>
+            </field>
+          </fields>
+        </register>
+
+        <!-- COUNT: Counter Register -->
+        <register>
+          <name>COUNT</name>
+          <description>The Counter Register reflects the actual Value of the Timer/Counter</description>
+          <addressOffset>0x20</addressOffset>
+          <size>32</size>
+          <access>read-write</access>
+          <resetValue>0x00000000</resetValue>
+          <resetMask>0xFFFFFFFF</resetMask>
+        </register>
+
+        <!-- MATCH: Match Register -->
+        <register>
+          <name>MATCH</name>
+          <description>The Match Register stores the compare Value for the MATCH condition</description>
+          <addressOffset>0x24</addressOffset>
+          <size>32</size>
+          <access>read-write</access>
+          <resetValue>0x00000000</resetValue>
+          <resetMask>0xFFFFFFFF</resetMask>
+        </register>
+        
+        <!-- PRESCALE: Prescale Read Register -->
+        <register>
+          <name>PRESCALE_RD</name>
+          <description>The Prescale Register stores the Value for the prescaler. The cont event gets divided by this value</description>
+          <addressOffset>0x28</addressOffset>
+          <size>32</size>
+          <access>read-only</access>
+          <resetValue>0x00000000</resetValue>
+          <resetMask>0xFFFFFFFF</resetMask>
+        </register>
+        
+        <!-- PRESCALE: Prescale Write Register -->
+        <register>
+          <name>PRESCALE_WR</name>
+          <description>The Prescale Register stores the Value for the prescaler. The cont event gets divided by this value</description>
+          <addressOffset>0x28</addressOffset>
+          <size>32</size>
+          <access>write-only</access>
+          <resetValue>0x00000000</resetValue>
+          <resetMask>0xFFFFFFFF</resetMask>
+        </register>
+
+
+        <!-- RELOAD: Array of Reload Register with 4 elements-->
+        <register>
+          <dim>4</dim>
+          <dimIncrement>4</dimIncrement>
+          <dimIndex>0,1,2,3</dimIndex>
+          <name>RELOAD[%s]</name>
+          <description>The Reload Register stores the Value the COUNT Register gets reloaded on a when a condition was met.</description>
+          <addressOffset>0x50</addressOffset>
+          <size>32</size>
+          <access>read-write</access>
+          <resetValue>0x00000000</resetValue>
+          <resetMask>0xFFFFFFFF</resetMask>
+        </register>
+      </registers>
+    </peripheral>
+
+    <!-- Timer 1 -->
+    <peripheral derivedFrom="TIMER0">
+      <name>TIMER1</name>
+      <baseAddress>0x40010100</baseAddress>
+      <interrupt>
+        <name>TIMER1</name>
+        <value>4</value>
+      </interrupt>
+    </peripheral>
+
+    <!-- Timer 2 -->
+    <peripheral derivedFrom="TIMER0">
+      <name>TIMER2</name>
+      <baseAddress>0x40010200</baseAddress>
+      <interrupt>
+        <name>TIMER2</name>
+        <value>6</value>
+      </interrupt>
+    </peripheral>
+  </peripherals>
+</device>
+
    +
    + + + + + diff --git a/Libraries/CMSIS/Documentation/SVD/html/svd__outline_pg.html b/Libraries/CMSIS/Documentation/SVD/html/svd__outline_pg.html new file mode 100644 index 0000000..31ec9e6 --- /dev/null +++ b/Libraries/CMSIS/Documentation/SVD/html/svd__outline_pg.html @@ -0,0 +1,128 @@ + + + + +SVD File Description + + + + + + + + + + + +
    + +
    + + + + + + + + + + + +
    +
    CMSIS-SVD +  Version 1.10 +
    +
    CMSIS System View Description
    +
    +
    + +
    + +
    + + + +
    +
    + +
    +
    +
    + +
    +
    +
    +
    SVD File Description
    +
    +
    +

    The CMSIS-SVD format is based on XML. The specification of the System View Description format was influenced by IP-XACT, a design description format used in, for example, IP stitching and IP reuse. Due to the much wider scope and complexity of IP-XACT it was decided to specify a separate format, which is focused and tailored toward the description of the programmer's view of a device only.

    +

    CMSIS-SVD XML Hierarchy

    +
    +CMSIS_SVD_Schema_Gen.png +
    +CMSIS-SVD Hierarchy Levels
    +

    One CMSIS-SVD file contains the description of a single device. A device consists of a processor and at least one peripheral. Each peripheral contains at least one register. A register may consist of one or more fields. The range of values for a field may be further described with enumerated values.

    +
      +
    • Device Level: The top level of a System View Description is the device. On this level, information is captured that is specific to the device as a whole. For example, the device name, description, or version. The minimal addressable unit as well as the bit-width of the data bus are required by the debugger to perform the correct target accesses.
      +
      +Default values for register attributes like register size, reset value, and access permissions can be set for the whole device on this level and are implicitly inherited by the lower levels of the description. If however specified on a lower level, the default setting from a higher level will get overruled.
      • +
    +
      +
    • Peripherals Level: A peripheral is a named collection of registers. A peripheral is mapped to a defined base address within the device's address space. A peripheral allocates one or more exclusive address blocks relative to its base address, such that all described registers fit into the allocated address blocks. Allocated addresses without an associated register description are automatically considered reserved. The peripheral can be assigned to a group of peripherals and may be associated with one or more interrupts.
      • +
    +
      +
    • Registers Level: A register is a named, programmable resource that belongs to a peripheral. Registers are mapped to a defined address in the address space of the device. An address is specified relative to the peripheral base address. The description of a register documents the purpose and function of the resource. A debugger requires information about the permitted access to a resource as well as side effects triggered by read and write accesses respectively.
      • +
    +
      +
    • Fields Level: Registers may be partitioned into chunks of bits of distinct functionality. A chunk is referred to as field. The field names within a single register must be unique. Only architecturally defined fields shall be described. Any bits not being explicitly described are treated as reserved. They are not displayed in the System Viewer and are padded in the bit fields of the device header file. The case-insensitive field named "reserved" is treated as a keyword and each field with this name is ignored.
      • +
    +
      +
    • Enumerated Values Level: An enumeration maps an unsigned integer constant to a descriptive identifier and, optionally, to a description string. Enumerations are used in C to enhance the readability of source code. Similarly, it can be used by debuggers to provide more instructive information to the programmer, avoiding a lookup in the device documentation.
      • +
    +
      +
    • Vendor Extensions: The CMSIS-SVD format includes a section named vendorExtensions positioned after the closing tag peripherals. This allows silicon vendors and tool partners to innovate and expand the description beyond the current specification.
      • +
    +

    Multiple Instantiation

    +

    CMSIS-SVD supports the reuse of whole sections of the description. The attribute derivedFrom for the peripheral-, register-, and field-section specifies the source of the section to be copied from. Individual tags can be used to redefine specific elements within a copied section. In case the name of the description source is not unique, the name needs to be qualified hierarchically until the element composite name becomes unique. Hierarchies are separated by a dot. For example, <peripheral name>.<register name>.<field name>.

    +

    Peripheral Grouping

    +

    Peripherals that provide similar functionality (Simple Timer, Complex Timer) can be grouped with the element groupName. All peripherals associated with the same group name are collectively listed under this group in the order they have been specified in the file. Collecting similar or related peripherals into peripheral groups helps structuring the list of peripherals in the debugger.

    +

    Descriptions

    +

    On each level, the tag description provides verbose information about the respective element. The description field plays an important part in improving the software development productivity as it gives instant access to information that otherwise would need to be looked up in the device documentation.

    +
    +
    + + + + + diff --git a/Libraries/CMSIS/Documentation/SVD/html/svd__usage_pg.html b/Libraries/CMSIS/Documentation/SVD/html/svd__usage_pg.html new file mode 100644 index 0000000..9c1d7cd --- /dev/null +++ b/Libraries/CMSIS/Documentation/SVD/html/svd__usage_pg.html @@ -0,0 +1,110 @@ + + + + +SVD File Usage + + + + + + + + + + + +
    + +
    + + + + + + + + + + + +
    +
    CMSIS-SVD +  Version 1.10 +
    +
    CMSIS System View Description
    +
    +
    + +
    + +
    + + + +
    +
    + +
    +
    +
    + +
    +
    +
    +
    SVD File Usage
    +
    +
    +

    System Views
    + There are a number of tool vendors who are supporting the CMSIS-SVD format with their products. Refer to the tools documentation to find out how to use CMSIS-SVD descriptions with the debugger of your choice. You can download the latest versions of available CMSIS-SVD files from the Public Download Area on the ARM web.
    +

    +

    Device Header File Generation (<device_name>.h):
    + SVDConv generates CMSIS compliant device header files from a CMSIS-SVD description. Note that CMSIS device header files are developed and maintained by the silicon vendors. Therefore the expectation is that this conversion is only of interest to these parties.
    + In a first step, a consistency check of the description is performed. In a second step, the device header file is generated. The device header file is generated into the current directory and the file name is determined by the tag name on the device level from CMSIS-SVD input file.

    +
      SVDConv.exe myDevice.xml --generate=header 
+


    +

    +
      +
    • Additional options:
      + This option generates bit fields in the device header file for each field description contained in the CMSIS-SVD input file. 
          --fields=struct
+

      + This option generates position and mask C-Macros for each field description contained in the CMSIS-SVD input file. 
          --fields=macro
+
      • +
    +
    +
    + + + + + diff --git a/Libraries/CMSIS/Documentation/SVD/html/svd_validate_file_pg.html b/Libraries/CMSIS/Documentation/SVD/html/svd_validate_file_pg.html new file mode 100644 index 0000000..077017c --- /dev/null +++ b/Libraries/CMSIS/Documentation/SVD/html/svd_validate_file_pg.html @@ -0,0 +1,123 @@ + + + + +SVD File Validation + + + + + + + + + + + +
    + +
    + + + + + + + + + + + +
    +
    CMSIS-SVD +  Version 1.10 +
    +
    CMSIS System View Description
    +
    +
    + +
    + +
    + + + +
    +
    + +
    +
    +
    + +
    +
    +
    +
    SVD File Validation
    +
    +
    +

    The quality of the available descriptions is key to the success of the CMSIS-SVD format. Aspects of quality are:

    +
      +
    • Syntactical and structural compliance with the specified CMSIS-SVD format.
      • +
    • Consistency and correctness.
      • +
    • Completeness.
      • +
    • Level of detail.
      • +
    +

    Automated checks are done on two levels:

    +
      +
    1. The CMSIS-SVD Schema File: The schema file specifies the syntax and structure of an XML-based format. XML tools use the schema file for checking the syntactical and structural correctness of an XML file that claims compliance with a certain format. The schema file CMSIS-SVD_Schema_1_0.xsd can be found in the folder SVD of the CMSIS distribution.
      +
      +
      2. +
    2. SVD Conversion Utility: ARM provides the SVD Utility (SVDConv.exe) tool to check the semantics and consistency of the data contained in a CMSIS-SVD file. SVDConv is a command-line tool included in the CMSIS distribution. It is located in the SVD folder side by side with the CMSIS-SVD schema file. The SVDConv shall be used for checking CMSIS-SVD descriptions as well as for generating CMSIS-compliant device header files.
      +
      +
        +
      • Usage Information:
        + SVDConv provides usage information at the command line when invoked without arguments. 
         SVDConv.exe 
+

        +
        +
        • +
      • Consistency Check:
        + SVDConv is performing a consistency of the CMSIS-SVD file passed as the first command-line argument. The checks go beyond syntactical tests as they can be performed using the CMSIS-SVD schema file in combination with XML validation tools. Errors and warnings are printed to the command line.
        + 
          SVDConv.exe myDevice.xml 
+

        +
        +
        • +
      +
      3. +
    +
    +
    + + + + + diff --git a/Libraries/CMSIS/Documentation/SVD/html/svd_web_pg.html b/Libraries/CMSIS/Documentation/SVD/html/svd_web_pg.html new file mode 100644 index 0000000..4f51d29 --- /dev/null +++ b/Libraries/CMSIS/Documentation/SVD/html/svd_web_pg.html @@ -0,0 +1,104 @@ + + + + +CMSIS-SVD Web Interface User Guide + + + + + + + + + + + +
    + +
    + + + + + + + + + + + +
    +
    CMSIS-SVD +  Version 1.10 +
    +
    CMSIS System View Description
    +
    +
    + +
    + +
    + + + +
    +
    + +
    +
    +
    + +
    +
    +
    +
    CMSIS-SVD Web Interface User Guide
    +
    +
    +

    The CMSIS Web Interface provides functionalities for downloading and managing the CMSIS-SVD files.

    + +

    In any case, the ARM web page requires login credentials to grant access to the content.

    + +
    +
    + + + + + diff --git a/Libraries/CMSIS/Documentation/SVD/html/svd_web_public_pg.html b/Libraries/CMSIS/Documentation/SVD/html/svd_web_public_pg.html new file mode 100644 index 0000000..da40503 --- /dev/null +++ b/Libraries/CMSIS/Documentation/SVD/html/svd_web_public_pg.html @@ -0,0 +1,131 @@ + + + + +Public Download Area + + + + + + + + + + + +
    + +
    + + + + + + + + + + + +
    +
    CMSIS-SVD +  Version 1.10 +
    +
    CMSIS System View Description
    +
    +
    + +
    + +
    + + + +
    +
    + +
    +
    +
    + +
    +
    +
    +
    Public Download Area
    +
    +
    +

    Public access to the Device Database is provided from cmsis.arm.com. For the public download of the CMSIS-SVD files of published devices it is mandatory to:

    +
      +
    • Be logged in on the ARM web site.
      • +
    • Have accepted a silicon vendor specific End Users License Agreement (EULA).
      • +
    +

    +Logging in

    +
      +
    • Use your credentials to Login.
      • +
    +

    +Opening the CMSIS-SVD Download page

    +
    +Access_SVD_Vendor.png +
    +Access Silicon Vendor Device Database
    +
      +
    • Access the CMSIS webpage at cmsis.arm.com.
      • +
    • Select the "CMSIS-SVD" tab.
      • +
    • Click on a Silicon Vendor's name for getting redirected to the respective vendor device database.
      • +
    +

    +Accepting the Silicon Vendor's License terms

    +

    On your first visit to a vendor database page you will be asked to review and accept the vendor-specific "End User License Agreement" (EULA). If you do not accept the EULA, you will see the list of devices and associated CMSIS-SVD files, but you will not be able to download any of the files. Note, in case the EULA has changed, you will be asked to review and accept the EULA again.

    +

    +Downloading CMSIS-SVD files

    +
    +CMSIS_SVD_Vendor_DD.png +
    +Download Device Database Files
    +
      +
    • Select one, multiple, or all devices from the table.
      • +
    • Click the "download" button.
      • +
    +

    You will be asked to open or save the zip archive file containing the files. If you have selected multiple devices, the file contents.txt included in the archive will list the mapping between devices and CMSIS-SVD files. Multiple devices can share the same CMSIS-SVD file.

    +
    +
    + + + + + diff --git a/Libraries/CMSIS/Documentation/SVD/html/svd_web_restricted_pg.html b/Libraries/CMSIS/Documentation/SVD/html/svd_web_restricted_pg.html new file mode 100644 index 0000000..3de6cba --- /dev/null +++ b/Libraries/CMSIS/Documentation/SVD/html/svd_web_restricted_pg.html @@ -0,0 +1,157 @@ + + + + +Restricted Management Area + + + + + + + + + + + +
    + +
    + + + + + + + + + + + +
    +
    CMSIS-SVD +  Version 1.10 +
    +
    CMSIS System View Description
    +
    +
    + +
    + +
    + + + +
    +
    + +
    +
    +
    + +
    +
    +
    +
    Restricted Management Area
    +
    +
    +

    Access to the CMSIS-SVD device database management system is restricted to:

    +
      +
    • Silicon Vendors.
      • +
    • Companies who have signed an agreement with ARM about using the CMSIS-SVD device database.
      • +
    • ARM Cortex-M based microcontroller devices.
      • +
    +

    +Signing the agreement

    +
      +
    • The Silicon Vendor contacts the ARM sales representative or sends an email to cmsis@arm.com requesting to contribute to the CMSIS-SVD Database.
      • +
    • An agreement needs to be signed between the Silicon Vendor and ARM defining the terms of use and specifying the representatives authorized for managing the files and devices.
      • +
    • The login e-mail addresses for www.arm.com get listed in the contract. The representatives need to ensure that their login already exists.
      • +
    • As part of exercising the contract the representatives will be given CMSIS-SVD Upload permissions in the system.
      • +
    +

    +Logging in

    +
      +
    • Use your credentials to Login.
      • +
    +

    +Opening the CMSIS-SVD Device Database page

    +
    +Access_SVD_DD_Manage.png +
    +Management Access to Device Database
    +
      +
    • Access the CMSIS web page at cmsis.arm.com.
      • +
    • Click the button "Device Database"
      Note:
      If you do not see this button, you are either not logged in or you have not been granted CMSIS-SVD Upload permissions.
      +
      • +
    +

    +Managing the Device Database

    +

    The database lists microcontroller devices and their associated CMSIS-SVD files and, optionally, resource files. Multiple devices may share the same CMSIS-SVD and the optional resource file. For this reason, files and devices are managed separately. Files need to be uploaded and have to pass the check against the CMSIS-SVD Schema as well as the plausibility and consistency check by the SVDConv utility before they can be used to define a device. The SVDConv checking is scheduled. Therefore, it can take up to 15 minutes before the file status gets updated.

    +
    +Manage_SVD_DD.png +
    +Manage Device Database Entries
    +
      +
    • a) Manage Files
        +
      • Add file: Select the CMSIS-SVD file and start the upload process. The schema check will run immediately after the file upload is complete. If the check fails the file will not be stored and you are asked to upload a corrected file. The SVDConv check for this file is automatically scheduled and will take place within 15 minutes. The status of the file will be updated and reports errors and warnings in a text file that can be downloaded (click on error/warning respectively).
        • +
      • Delete file: Files can only be deleted if they are not associated with a device otherwise the system will list the devices the file is still associated with.
        • +
      • Replace file: Replace files allows you to update a file without the need to edit the device definition.
        • +
      +
      • +
    +
      +
    • b) Manage Devices
      + New devices can be added or existing devices can be edited. A device defines:
        +
      • Name of device
        • +
      • Filename CMSIS-SVD
        • +
      • Filename Resource zip archive
        • +
      • Reviewer List
        • +
      • Publishing Date
        + A checkbox is in front of each device to enable and disable a device. A disabled device will not show in the vendor-specific download area.
        • +
      +
      • +
    +
      +
    • c) Review Devices
      + Ask you reviewer for the login email address being used for the login on the ARM web. Add this email address into the field, one email address per line. You can add some text to the e-mail body however the email template already contains all relevant information like the device name as well as a link to the device database.
      • +
    +
    +
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All rights reserved. +* +* $Date: 11. November 2010 +* $Revision: V1.0.2 +* +* Project: CMSIS DSP Library +* Title: arm_common_tables.h +* +* Description: This file has extern declaration for common tables like Bitreverse, reciprocal etc which are used across different functions +* +* Target Processor: Cortex-M4/Cortex-M3 +* +* Version 1.0.2 2010/11/11 +* Documentation updated. +* +* Version 1.0.1 2010/10/05 +* Production release and review comments incorporated. +* +* Version 1.0.0 2010/09/20 +* Production release and review comments incorporated. +* -------------------------------------------------------------------- */ + +#ifndef _ARM_COMMON_TABLES_H +#define _ARM_COMMON_TABLES_H + +#include "arm_math.h" + +extern const uint16_t armBitRevTable[1024]; +extern const q15_t armRecipTableQ15[64]; +extern const q31_t armRecipTableQ31[64]; +extern const q31_t realCoefAQ31[1024]; +extern const q31_t realCoefBQ31[1024]; +extern const float32_t twiddleCoef[6144]; +extern const q31_t twiddleCoefQ31[6144]; +extern const q15_t twiddleCoefQ15[6144]; + +#endif /* ARM_COMMON_TABLES_H */ diff --git a/Libraries/CMSIS/Include/arm_math.h b/Libraries/CMSIS/Include/arm_math.h new file mode 100644 index 0000000..7266c3e --- /dev/null +++ b/Libraries/CMSIS/Include/arm_math.h @@ -0,0 +1,7557 @@ +/* ---------------------------------------------------------------------- + * Copyright (C) 2010-2011 ARM Limited. All rights reserved. + * + * $Date: 15. February 2012 + * $Revision: V1.1.0 + * + * Project: CMSIS DSP Library + * Title: arm_math.h + * + * Description: Public header file for CMSIS DSP Library + * + * Target Processor: Cortex-M4/Cortex-M3/Cortex-M0 + * + * Version 1.1.0 2012/02/15 + * Updated with more optimizations, bug fixes and minor API changes. + * + * Version 1.0.10 2011/7/15 + * Big Endian support added and Merged M0 and M3/M4 Source code. + * + * Version 1.0.3 2010/11/29 + * Re-organized the CMSIS folders and updated documentation. + * + * Version 1.0.2 2010/11/11 + * Documentation updated. + * + * Version 1.0.1 2010/10/05 + * Production release and review comments incorporated. + * + * Version 1.0.0 2010/09/20 + * Production release and review comments incorporated. + * -------------------------------------------------------------------- */ + +/** + \mainpage CMSIS DSP Software Library + * + * Introduction + * + * This user manual describes the CMSIS DSP software library, + * a suite of common signal processing functions for use on Cortex-M processor based devices. + * + * The library is divided into a number of functions each covering a specific category: + * - Basic math functions + * - Fast math functions + * - Complex math functions + * - Filters + * - Matrix functions + * - Transforms + * - Motor control functions + * - Statistical functions + * - Support functions + * - Interpolation functions + * + * The library has separate functions for operating on 8-bit integers, 16-bit integers, + * 32-bit integer and 32-bit floating-point values. + * + * Pre-processor Macros + * + * Each library project have differant pre-processor macros. + * + * - UNALIGNED_SUPPORT_DISABLE: + * + * Define macro UNALIGNED_SUPPORT_DISABLE, If the silicon does not support unaligned memory access + * + * - ARM_MATH_BIG_ENDIAN: + * + * Define macro ARM_MATH_BIG_ENDIAN to build the library for big endian targets. By default library builds for little endian targets. + * + * - ARM_MATH_MATRIX_CHECK: + * + * Define macro ARM_MATH_MATRIX_CHECK for checking on the input and output sizes of matrices + * + * - ARM_MATH_ROUNDING: + * + * Define macro ARM_MATH_ROUNDING for rounding on support functions + * + * - ARM_MATH_CMx: + * + * Define macro ARM_MATH_CM4 for building the library on Cortex-M4 target, ARM_MATH_CM3 for building library on Cortex-M3 target + * and ARM_MATH_CM0 for building library on cortex-M0 target. + * + * - __FPU_PRESENT: + * + * Initialize macro __FPU_PRESENT = 1 when building on FPU supported Targets. Enable this macro for M4bf and M4lf libraries + * + * Toolchain Support + * + * The library has been developed and tested with MDK-ARM version 4.23. + * The library is being tested in GCC and IAR toolchains and updates on this activity will be made available shortly. + * + * Using the Library + * + * The library installer contains prebuilt versions of the libraries in the Lib folder. + * - arm_cortexM4lf_math.lib (Little endian and Floating Point Unit on Cortex-M4) + * - arm_cortexM4bf_math.lib (Big endian and Floating Point Unit on Cortex-M4) + * - arm_cortexM4l_math.lib (Little endian on Cortex-M4) + * - arm_cortexM4b_math.lib (Big endian on Cortex-M4) + * - arm_cortexM3l_math.lib (Little endian on Cortex-M3) + * - arm_cortexM3b_math.lib (Big endian on Cortex-M3) + * - arm_cortexM0l_math.lib (Little endian on Cortex-M0) + * - arm_cortexM0b_math.lib (Big endian on Cortex-M3) + * + * The library functions are declared in the public file arm_math.h which is placed in the Include folder. + * Simply include this file and link the appropriate library in the application and begin calling the library functions. The Library supports single + * public header file arm_math.h for Cortex-M4/M3/M0 with little endian and big endian. Same header file will be used for floating point unit(FPU) variants. + * Define the appropriate pre processor MACRO ARM_MATH_CM4 or ARM_MATH_CM3 or + * ARM_MATH_CM0 depending on the target processor in the application. + * + * Examples + * + * The library ships with a number of examples which demonstrate how to use the library functions. + * + * Building the Library + * + * The library installer contains project files to re build libraries on MDK Tool chain in the CMSIS\\DSP_Lib\\Source\\ARM folder. + * - arm_cortexM0b_math.uvproj + * - arm_cortexM0l_math.uvproj + * - arm_cortexM3b_math.uvproj + * - arm_cortexM3l_math.uvproj + * - arm_cortexM4b_math.uvproj + * - arm_cortexM4l_math.uvproj + * - arm_cortexM4bf_math.uvproj + * - arm_cortexM4lf_math.uvproj + * + * + * The project can be built by opening the appropriate project in MDK-ARM 4.23 chain and defining the optional pre processor MACROs detailed above. + * + * Copyright Notice + * + * Copyright (C) 2010 ARM Limited. All rights reserved. + */ + + +/** + * @defgroup groupMath Basic Math Functions + */ + +/** + * @defgroup groupFastMath Fast Math Functions + * This set of functions provides a fast approximation to sine, cosine, and square root. + * As compared to most of the other functions in the CMSIS math library, the fast math functions + * operate on individual values and not arrays. + * There are separate functions for Q15, Q31, and floating-point data. + * + */ + +/** + * @defgroup groupCmplxMath Complex Math Functions + * This set of functions operates on complex data vectors. + * The data in the complex arrays is stored in an interleaved fashion + * (real, imag, real, imag, ...). + * In the API functions, the number of samples in a complex array refers + * to the number of complex values; the array contains twice this number of + * real values. + */ + +/** + * @defgroup groupFilters Filtering Functions + */ + +/** + * @defgroup groupMatrix Matrix Functions + * + * This set of functions provides basic matrix math operations. + * The functions operate on matrix data structures. For example, + * the type + * definition for the floating-point matrix structure is shown + * below: + * 
    + *     typedef struct
+ *     {
+ *       uint16_t numRows;     // number of rows of the matrix.
+ *       uint16_t numCols;     // number of columns of the matrix.
+ *       float32_t *pData;     // points to the data of the matrix.
+ *     } arm_matrix_instance_f32;
+ *
    + * There are similar definitions for Q15 and Q31 data types. + * + * The structure specifies the size of the matrix and then points to + * an array of data. The array is of size numRows X numCols + * and the values are arranged in row order. That is, the + * matrix element (i, j) is stored at: + * 
    + *     pData[i*numCols + j]
+ *
    + * + * \par Init Functions + * There is an associated initialization function for each type of matrix + * data structure. + * The initialization function sets the values of the internal structure fields. + * Refer to the function arm_mat_init_f32(), arm_mat_init_q31() + * and arm_mat_init_q15() for floating-point, Q31 and Q15 types, respectively. + * + * \par + * Use of the initialization function is optional. However, if initialization function is used + * then the instance structure cannot be placed into a const data section. + * To place the instance structure in a const data + * section, manually initialize the data structure. For example: + * 
    + * arm_matrix_instance_f32 S = {nRows, nColumns, pData};
+ * arm_matrix_instance_q31 S = {nRows, nColumns, pData};
+ * arm_matrix_instance_q15 S = {nRows, nColumns, pData};
+ *
    + * where nRows specifies the number of rows, nColumns + * specifies the number of columns, and pData points to the + * data array. + * + * \par Size Checking + * By default all of the matrix functions perform size checking on the input and + * output matrices. For example, the matrix addition function verifies that the + * two input matrices and the output matrix all have the same number of rows and + * columns. If the size check fails the functions return: + * 
    + *     ARM_MATH_SIZE_MISMATCH
+ *
    + * Otherwise the functions return + * 
    + *     ARM_MATH_SUCCESS
+ *
    + * There is some overhead associated with this matrix size checking. + * The matrix size checking is enabled via the \#define + * 
    + *     ARM_MATH_MATRIX_CHECK
+ *
    + * within the library project settings. By default this macro is defined + * and size checking is enabled. By changing the project settings and + * undefining this macro size checking is eliminated and the functions + * run a bit faster. With size checking disabled the functions always + * return ARM_MATH_SUCCESS. + */ + +/** + * @defgroup groupTransforms Transform Functions + */ + +/** + * @defgroup groupController Controller Functions + */ + +/** + * @defgroup groupStats Statistics Functions + */ +/** + * @defgroup groupSupport Support Functions + */ + +/** + * @defgroup groupInterpolation Interpolation Functions + * These functions perform 1- and 2-dimensional interpolation of data. + * Linear interpolation is used for 1-dimensional data and + * bilinear interpolation is used for 2-dimensional data. + */ + +/** + * @defgroup groupExamples Examples + */ +#ifndef _ARM_MATH_H +#define _ARM_MATH_H + +#define __CMSIS_GENERIC /* disable NVIC and Systick functions */ + +#if defined (ARM_MATH_CM4) +#include "core_cm4.h" +#elif defined (ARM_MATH_CM3) +#include "core_cm3.h" +#elif defined (ARM_MATH_CM0) +#include "core_cm0.h" +#else +#include "ARMCM4.h" +#warning "Define either ARM_MATH_CM4 OR ARM_MATH_CM3...By Default building on ARM_MATH_CM4....." +#endif + +#undef __CMSIS_GENERIC /* enable NVIC and Systick functions */ +#include "string.h" +#include "math.h" +#ifdef __cplusplus +extern "C" +{ +#endif + + + /** + * @brief Macros required for reciprocal calculation in Normalized LMS + */ + +#define DELTA_Q31 (0x100) +#define DELTA_Q15 0x5 +#define INDEX_MASK 0x0000003F +#ifndef PI +#define PI 3.14159265358979f +#endif + + /** + * @brief Macros required for SINE and COSINE Fast math approximations + */ + +#define TABLE_SIZE 256 +#define TABLE_SPACING_Q31 0x800000 +#define TABLE_SPACING_Q15 0x80 + + /** + * @brief Macros required for SINE and COSINE Controller functions + */ + /* 1.31(q31) Fixed value of 2/360 */ + /* -1 to +1 is divided into 360 values so total spacing is (2/360) */ +#define INPUT_SPACING 0xB60B61 + + /** + * @brief Macro for Unaligned Support + */ +#ifndef UNALIGNED_SUPPORT_DISABLE + #define ALIGN4 +#else + #if defined (__GNUC__) + #define ALIGN4 __attribute__((aligned(4))) + #else + #define ALIGN4 __align(4) + #endif +#endif /* #ifndef UNALIGNED_SUPPORT_DISABLE */ + + /** + * @brief Error status returned by some functions in the library. + */ + + typedef enum + { + ARM_MATH_SUCCESS = 0, /**< No error */ + ARM_MATH_ARGUMENT_ERROR = -1, /**< One or more arguments are incorrect */ + ARM_MATH_LENGTH_ERROR = -2, /**< Length of data buffer is incorrect */ + ARM_MATH_SIZE_MISMATCH = -3, /**< Size of matrices is not compatible with the operation. */ + ARM_MATH_NANINF = -4, /**< Not-a-number (NaN) or infinity is generated */ + ARM_MATH_SINGULAR = -5, /**< Generated by matrix inversion if the input matrix is singular and cannot be inverted. */ + ARM_MATH_TEST_FAILURE = -6 /**< Test Failed */ + } arm_status; + + /** + * @brief 8-bit fractional data type in 1.7 format. + */ + typedef int8_t q7_t; + + /** + * @brief 16-bit fractional data type in 1.15 format. + */ + typedef int16_t q15_t; + + /** + * @brief 32-bit fractional data type in 1.31 format. + */ + typedef int32_t q31_t; + + /** + * @brief 64-bit fractional data type in 1.63 format. + */ + typedef int64_t q63_t; + + /** + * @brief 32-bit floating-point type definition. + */ + typedef float float32_t; + + /** + * @brief 64-bit floating-point type definition. + */ + typedef double float64_t; + + /** + * @brief definition to read/write two 16 bit values. + */ +#if defined (__GNUC__) + #define __SIMD32(addr) (*( int32_t **) & (addr)) + #define _SIMD32_OFFSET(addr) (*( int32_t * ) (addr)) +#else + #define __SIMD32(addr) (*(__packed int32_t **) & (addr)) + #define _SIMD32_OFFSET(addr) (*(__packed int32_t * ) (addr)) +#endif + + #define __SIMD64(addr) (*(int64_t **) & (addr)) + +#if defined (ARM_MATH_CM3) || defined (ARM_MATH_CM0) + /** + * @brief definition to pack two 16 bit values. + */ +#define __PKHBT(ARG1, ARG2, ARG3) ( (((int32_t)(ARG1) << 0) & (int32_t)0x0000FFFF) | \ + (((int32_t)(ARG2) << ARG3) & (int32_t)0xFFFF0000) ) +#define __PKHTB(ARG1, ARG2, ARG3) ( (((int32_t)(ARG1) << 0) & (int32_t)0xFFFF0000) | \ + (((int32_t)(ARG2) >> ARG3) & (int32_t)0x0000FFFF) ) + +#endif + + + /** + * @brief definition to pack four 8 bit values. + */ +#ifndef ARM_MATH_BIG_ENDIAN + +#define __PACKq7(v0,v1,v2,v3) ( (((int32_t)(v0) << 0) & (int32_t)0x000000FF) | \ + (((int32_t)(v1) << 8) & (int32_t)0x0000FF00) | \ + (((int32_t)(v2) << 16) & (int32_t)0x00FF0000) | \ + (((int32_t)(v3) << 24) & (int32_t)0xFF000000) ) +#else + +#define __PACKq7(v0,v1,v2,v3) ( (((int32_t)(v3) << 0) & (int32_t)0x000000FF) | \ + (((int32_t)(v2) << 8) & (int32_t)0x0000FF00) | \ + (((int32_t)(v1) << 16) & (int32_t)0x00FF0000) | \ + (((int32_t)(v0) << 24) & (int32_t)0xFF000000) ) + +#endif + + + /** + * @brief Clips Q63 to Q31 values. + */ + __STATIC_INLINE q31_t clip_q63_to_q31( + q63_t x) + { + return ((q31_t) (x >> 32) != ((q31_t) x >> 31)) ? + ((0x7FFFFFFF ^ ((q31_t) (x >> 63)))) : (q31_t) x; + } + + /** + * @brief Clips Q63 to Q15 values. + */ + __STATIC_INLINE q15_t clip_q63_to_q15( + q63_t x) + { + return ((q31_t) (x >> 32) != ((q31_t) x >> 31)) ? + ((0x7FFF ^ ((q15_t) (x >> 63)))) : (q15_t) (x >> 15); + } + + /** + * @brief Clips Q31 to Q7 values. + */ + __STATIC_INLINE q7_t clip_q31_to_q7( + q31_t x) + { + return ((q31_t) (x >> 24) != ((q31_t) x >> 23)) ? + ((0x7F ^ ((q7_t) (x >> 31)))) : (q7_t) x; + } + + /** + * @brief Clips Q31 to Q15 values. + */ + __STATIC_INLINE q15_t clip_q31_to_q15( + q31_t x) + { + return ((q31_t) (x >> 16) != ((q31_t) x >> 15)) ? + ((0x7FFF ^ ((q15_t) (x >> 31)))) : (q15_t) x; + } + + /** + * @brief Multiplies 32 X 64 and returns 32 bit result in 2.30 format. + */ + + __STATIC_INLINE q63_t mult32x64( + q63_t x, + q31_t y) + { + return ((((q63_t) (x & 0x00000000FFFFFFFF) * y) >> 32) + + (((q63_t) (x >> 32) * y))); + } + + +#if defined (ARM_MATH_CM0) && defined ( __CC_ARM ) +#define __CLZ __clz +#endif + +#if defined (ARM_MATH_CM0) && defined ( __TASKING__ ) +/* No need to redefine __CLZ */ +#endif + +#if defined (ARM_MATH_CM0) && ((defined (__ICCARM__)) ||(defined (__GNUC__)) ) + + __STATIC_INLINE uint32_t __CLZ(q31_t data); + + + __STATIC_INLINE uint32_t __CLZ(q31_t data) + { + uint32_t count = 0; + uint32_t mask = 0x80000000; + + while((data & mask) == 0) + { + count += 1u; + mask = mask >> 1u; + } + + return (count); + + } + +#endif + + /** + * @brief Function to Calculates 1/in(reciprocal) value of Q31 Data type. + */ + + __STATIC_INLINE uint32_t arm_recip_q31( + q31_t in, + q31_t * dst, + q31_t * pRecipTable) + { + + uint32_t out, tempVal; + uint32_t index, i; + uint32_t signBits; + + if(in > 0) + { + signBits = __CLZ(in) - 1; + } + else + { + signBits = __CLZ(-in) - 1; + } + + /* Convert input sample to 1.31 format */ + in = in << signBits; + + /* calculation of index for initial approximated Val */ + index = (uint32_t) (in >> 24u); + index = (index & INDEX_MASK); + + /* 1.31 with exp 1 */ + out = pRecipTable[index]; + + /* calculation of reciprocal value */ + /* running approximation for two iterations */ + for (i = 0u; i < 2u; i++) + { + tempVal = (q31_t) (((q63_t) in * out) >> 31u); + tempVal = 0x7FFFFFFF - tempVal; + /* 1.31 with exp 1 */ + //out = (q31_t) (((q63_t) out * tempVal) >> 30u); + out = (q31_t) clip_q63_to_q31(((q63_t) out * tempVal) >> 30u); + } + + /* write output */ + *dst = out; + + /* return num of signbits of out = 1/in value */ + return (signBits + 1u); + + } + + /** + * @brief Function to Calculates 1/in(reciprocal) value of Q15 Data type. + */ + __STATIC_INLINE uint32_t arm_recip_q15( + q15_t in, + q15_t * dst, + q15_t * pRecipTable) + { + + uint32_t out = 0, tempVal = 0; + uint32_t index = 0, i = 0; + uint32_t signBits = 0; + + if(in > 0) + { + signBits = __CLZ(in) - 17; + } + else + { + signBits = __CLZ(-in) - 17; + } + + /* Convert input sample to 1.15 format */ + in = in << signBits; + + /* calculation of index for initial approximated Val */ + index = in >> 8; + index = (index & INDEX_MASK); + + /* 1.15 with exp 1 */ + out = pRecipTable[index]; + + /* calculation of reciprocal value */ + /* running approximation for two iterations */ + for (i = 0; i < 2; i++) + { + tempVal = (q15_t) (((q31_t) in * out) >> 15); + tempVal = 0x7FFF - tempVal; + /* 1.15 with exp 1 */ + out = (q15_t) (((q31_t) out * tempVal) >> 14); + } + + /* write output */ + *dst = out; + + /* return num of signbits of out = 1/in value */ + return (signBits + 1); + + } + + + /* + * @brief C custom defined intrinisic function for only M0 processors + */ +#if defined(ARM_MATH_CM0) + + __STATIC_INLINE q31_t __SSAT( + q31_t x, + uint32_t y) + { + int32_t posMax, negMin; + uint32_t i; + + posMax = 1; + for (i = 0; i < (y - 1); i++) + { + posMax = posMax * 2; + } + + if(x > 0) + { + posMax = (posMax - 1); + + if(x > posMax) + { + x = posMax; + } + } + else + { + negMin = -posMax; + + if(x < negMin) + { + x = negMin; + } + } + return (x); + + + } + +#endif /* end of ARM_MATH_CM0 */ + + + + /* + * @brief C custom defined intrinsic function for M3 and M0 processors + */ +#if defined (ARM_MATH_CM3) || defined (ARM_MATH_CM0) + + /* + * @brief C custom defined QADD8 for M3 and M0 processors + */ + __STATIC_INLINE q31_t __QADD8( + q31_t x, + q31_t y) + { + + q31_t sum; + q7_t r, s, t, u; + + r = (q7_t) x; + s = (q7_t) y; + + r = __SSAT((q31_t) (r + s), 8); + s = __SSAT(((q31_t) (((x << 16) >> 24) + ((y << 16) >> 24))), 8); + t = __SSAT(((q31_t) (((x << 8) >> 24) + ((y << 8) >> 24))), 8); + u = __SSAT(((q31_t) ((x >> 24) + (y >> 24))), 8); + + sum = + (((q31_t) u << 24) & 0xFF000000) | (((q31_t) t << 16) & 0x00FF0000) | + (((q31_t) s << 8) & 0x0000FF00) | (r & 0x000000FF); + + return sum; + + } + + /* + * @brief C custom defined QSUB8 for M3 and M0 processors + */ + __STATIC_INLINE q31_t __QSUB8( + q31_t x, + q31_t y) + { + + q31_t sum; + q31_t r, s, t, u; + + r = (q7_t) x; + s = (q7_t) y; + + r = __SSAT((r - s), 8); + s = __SSAT(((q31_t) (((x << 16) >> 24) - ((y << 16) >> 24))), 8) << 8; + t = __SSAT(((q31_t) (((x << 8) >> 24) - ((y << 8) >> 24))), 8) << 16; + u = __SSAT(((q31_t) ((x >> 24) - (y >> 24))), 8) << 24; + + sum = + (u & 0xFF000000) | (t & 0x00FF0000) | (s & 0x0000FF00) | (r & + 0x000000FF); + + return sum; + } + + /* + * @brief C custom defined QADD16 for M3 and M0 processors + */ + + /* + * @brief C custom defined QADD16 for M3 and M0 processors + */ + __STATIC_INLINE q31_t __QADD16( + q31_t x, + q31_t y) + { + + q31_t sum; + q31_t r, s; + + r = (short) x; + s = (short) y; + + r = __SSAT(r + s, 16); + s = __SSAT(((q31_t) ((x >> 16) + (y >> 16))), 16) << 16; + + sum = (s & 0xFFFF0000) | (r & 0x0000FFFF); + + return sum; + + } + + /* + * @brief C custom defined SHADD16 for M3 and M0 processors + */ + __STATIC_INLINE q31_t __SHADD16( + q31_t x, + q31_t y) + { + + q31_t sum; + q31_t r, s; + + r = (short) x; + s = (short) y; + + r = ((r >> 1) + (s >> 1)); + s = ((q31_t) ((x >> 17) + (y >> 17))) << 16; + + sum = (s & 0xFFFF0000) | (r & 0x0000FFFF); + + return sum; + + } + + /* + * @brief C custom defined QSUB16 for M3 and M0 processors + */ + __STATIC_INLINE q31_t __QSUB16( + q31_t x, + q31_t y) + { + + q31_t sum; + q31_t r, s; + + r = (short) x; + s = (short) y; + + r = __SSAT(r - s, 16); + s = __SSAT(((q31_t) ((x >> 16) - (y >> 16))), 16) << 16; + + sum = (s & 0xFFFF0000) | (r & 0x0000FFFF); + + return sum; + } + + /* + * @brief C custom defined SHSUB16 for M3 and M0 processors + */ + __STATIC_INLINE q31_t __SHSUB16( + q31_t x, + q31_t y) + { + + q31_t diff; + q31_t r, s; + + r = (short) x; + s = (short) y; + + r = ((r >> 1) - (s >> 1)); + s = (((x >> 17) - (y >> 17)) << 16); + + diff = (s & 0xFFFF0000) | (r & 0x0000FFFF); + + return diff; + } + + /* + * @brief C custom defined QASX for M3 and M0 processors + */ + __STATIC_INLINE q31_t __QASX( + q31_t x, + q31_t y) + { + + q31_t sum = 0; + + sum = + ((sum + + clip_q31_to_q15((q31_t) ((short) (x >> 16) + (short) y))) << 16) + + clip_q31_to_q15((q31_t) ((short) x - (short) (y >> 16))); + + return sum; + } + + /* + * @brief C custom defined SHASX for M3 and M0 processors + */ + __STATIC_INLINE q31_t __SHASX( + q31_t x, + q31_t y) + { + + q31_t sum; + q31_t r, s; + + r = (short) x; + s = (short) y; + + r = ((r >> 1) - (y >> 17)); + s = (((x >> 17) + (s >> 1)) << 16); + + sum = (s & 0xFFFF0000) | (r & 0x0000FFFF); + + return sum; + } + + + /* + * @brief C custom defined QSAX for M3 and M0 processors + */ + __STATIC_INLINE q31_t __QSAX( + q31_t x, + q31_t y) + { + + q31_t sum = 0; + + sum = + ((sum + + clip_q31_to_q15((q31_t) ((short) (x >> 16) - (short) y))) << 16) + + clip_q31_to_q15((q31_t) ((short) x + (short) (y >> 16))); + + return sum; + } + + /* + * @brief C custom defined SHSAX for M3 and M0 processors + */ + __STATIC_INLINE q31_t __SHSAX( + q31_t x, + q31_t y) + { + + q31_t sum; + q31_t r, s; + + r = (short) x; + s = (short) y; + + r = ((r >> 1) + (y >> 17)); + s = (((x >> 17) - (s >> 1)) << 16); + + sum = (s & 0xFFFF0000) | (r & 0x0000FFFF); + + return sum; + } + + /* + * @brief C custom defined SMUSDX for M3 and M0 processors + */ + __STATIC_INLINE q31_t __SMUSDX( + q31_t x, + q31_t y) + { + + return ((q31_t) (((short) x * (short) (y >> 16)) - + ((short) (x >> 16) * (short) y))); + } + + /* + * @brief C custom defined SMUADX for M3 and M0 processors + */ + __STATIC_INLINE q31_t __SMUADX( + q31_t x, + q31_t y) + { + + return ((q31_t) (((short) x * (short) (y >> 16)) + + ((short) (x >> 16) * (short) y))); + } + + /* + * @brief C custom defined QADD for M3 and M0 processors + */ + __STATIC_INLINE q31_t __QADD( + q31_t x, + q31_t y) + { + return clip_q63_to_q31((q63_t) x + y); + } + + /* + * @brief C custom defined QSUB for M3 and M0 processors + */ + __STATIC_INLINE q31_t __QSUB( + q31_t x, + q31_t y) + { + return clip_q63_to_q31((q63_t) x - y); + } + + /* + * @brief C custom defined SMLAD for M3 and M0 processors + */ + __STATIC_INLINE q31_t __SMLAD( + q31_t x, + q31_t y, + q31_t sum) + { + + return (sum + ((short) (x >> 16) * (short) (y >> 16)) + + ((short) x * (short) y)); + } + + /* + * @brief C custom defined SMLADX for M3 and M0 processors + */ + __STATIC_INLINE q31_t __SMLADX( + q31_t x, + q31_t y, + q31_t sum) + { + + return (sum + ((short) (x >> 16) * (short) (y)) + + ((short) x * (short) (y >> 16))); + } + + /* + * @brief C custom defined SMLSDX for M3 and M0 processors + */ + __STATIC_INLINE q31_t __SMLSDX( + q31_t x, + q31_t y, + q31_t sum) + { + + return (sum - ((short) (x >> 16) * (short) (y)) + + ((short) x * (short) (y >> 16))); + } + + /* + * @brief C custom defined SMLALD for M3 and M0 processors + */ + __STATIC_INLINE q63_t __SMLALD( + q31_t x, + q31_t y, + q63_t sum) + { + + return (sum + ((short) (x >> 16) * (short) (y >> 16)) + + ((short) x * (short) y)); + } + + /* + * @brief C custom defined SMLALDX for M3 and M0 processors + */ + __STATIC_INLINE q63_t __SMLALDX( + q31_t x, + q31_t y, + q63_t sum) + { + + return (sum + ((short) (x >> 16) * (short) y)) + + ((short) x * (short) (y >> 16)); + } + + /* + * @brief C custom defined SMUAD for M3 and M0 processors + */ + __STATIC_INLINE q31_t __SMUAD( + q31_t x, + q31_t y) + { + + return (((x >> 16) * (y >> 16)) + + (((x << 16) >> 16) * ((y << 16) >> 16))); + } + + /* + * @brief C custom defined SMUSD for M3 and M0 processors + */ + __STATIC_INLINE q31_t __SMUSD( + q31_t x, + q31_t y) + { + + return (-((x >> 16) * (y >> 16)) + + (((x << 16) >> 16) * ((y << 16) >> 16))); + } + + + /* + * @brief C custom defined SXTB16 for M3 and M0 processors + */ + __STATIC_INLINE q31_t __SXTB16( + q31_t x) + { + + return ((((x << 24) >> 24) & 0x0000FFFF) | + (((x << 8) >> 8) & 0xFFFF0000)); + } + + +#endif /* defined (ARM_MATH_CM3) || defined (ARM_MATH_CM0) */ + + + /** + * @brief Instance structure for the Q7 FIR filter. + */ + typedef struct + { + uint16_t numTaps; /**< number of filter coefficients in the filter. */ + q7_t *pState; /**< points to the state variable array. The array is of length numTaps+blockSize-1. */ + q7_t *pCoeffs; /**< points to the coefficient array. The array is of length numTaps.*/ + } arm_fir_instance_q7; + + /** + * @brief Instance structure for the Q15 FIR filter. + */ + typedef struct + { + uint16_t numTaps; /**< number of filter coefficients in the filter. */ + q15_t *pState; /**< points to the state variable array. The array is of length numTaps+blockSize-1. */ + q15_t *pCoeffs; /**< points to the coefficient array. The array is of length numTaps.*/ + } arm_fir_instance_q15; + + /** + * @brief Instance structure for the Q31 FIR filter. + */ + typedef struct + { + uint16_t numTaps; /**< number of filter coefficients in the filter. */ + q31_t *pState; /**< points to the state variable array. The array is of length numTaps+blockSize-1. */ + q31_t *pCoeffs; /**< points to the coefficient array. The array is of length numTaps. */ + } arm_fir_instance_q31; + + /** + * @brief Instance structure for the floating-point FIR filter. + */ + typedef struct + { + uint16_t numTaps; /**< number of filter coefficients in the filter. */ + float32_t *pState; /**< points to the state variable array. The array is of length numTaps+blockSize-1. */ + float32_t *pCoeffs; /**< points to the coefficient array. The array is of length numTaps. */ + } arm_fir_instance_f32; + + + /** + * @brief Processing function for the Q7 FIR filter. + * @param[in] *S points to an instance of the Q7 FIR filter structure. + * @param[in] *pSrc points to the block of input data. + * @param[out] *pDst points to the block of output data. + * @param[in] blockSize number of samples to process. + * @return none. + */ + void arm_fir_q7( + const arm_fir_instance_q7 * S, + q7_t * pSrc, + q7_t * pDst, + uint32_t blockSize); + + + /** + * @brief Initialization function for the Q7 FIR filter. + * @param[in,out] *S points to an instance of the Q7 FIR structure. + * @param[in] numTaps Number of filter coefficients in the filter. + * @param[in] *pCoeffs points to the filter coefficients. + * @param[in] *pState points to the state buffer. + * @param[in] blockSize number of samples that are processed. + * @return none + */ + void arm_fir_init_q7( + arm_fir_instance_q7 * S, + uint16_t numTaps, + q7_t * pCoeffs, + q7_t * pState, + uint32_t blockSize); + + + /** + * @brief Processing function for the Q15 FIR filter. + * @param[in] *S points to an instance of the Q15 FIR structure. + * @param[in] *pSrc points to the block of input data. + * @param[out] *pDst points to the block of output data. + * @param[in] blockSize number of samples to process. + * @return none. + */ + void arm_fir_q15( + const arm_fir_instance_q15 * S, + q15_t * pSrc, + q15_t * pDst, + uint32_t blockSize); + + /** + * @brief Processing function for the fast Q15 FIR filter for Cortex-M3 and Cortex-M4. + * @param[in] *S points to an instance of the Q15 FIR filter structure. + * @param[in] *pSrc points to the block of input data. + * @param[out] *pDst points to the block of output data. + * @param[in] blockSize number of samples to process. + * @return none. + */ + void arm_fir_fast_q15( + const arm_fir_instance_q15 * S, + q15_t * pSrc, + q15_t * pDst, + uint32_t blockSize); + + /** + * @brief Initialization function for the Q15 FIR filter. + * @param[in,out] *S points to an instance of the Q15 FIR filter structure. + * @param[in] numTaps Number of filter coefficients in the filter. Must be even and greater than or equal to 4. + * @param[in] *pCoeffs points to the filter coefficients. + * @param[in] *pState points to the state buffer. + * @param[in] blockSize number of samples that are processed at a time. + * @return The function returns ARM_MATH_SUCCESS if initialization was successful or ARM_MATH_ARGUMENT_ERROR if + * numTaps is not a supported value. + */ + + arm_status arm_fir_init_q15( + arm_fir_instance_q15 * S, + uint16_t numTaps, + q15_t * pCoeffs, + q15_t * pState, + uint32_t blockSize); + + /** + * @brief Processing function for the Q31 FIR filter. + * @param[in] *S points to an instance of the Q31 FIR filter structure. + * @param[in] *pSrc points to the block of input data. + * @param[out] *pDst points to the block of output data. + * @param[in] blockSize number of samples to process. + * @return none. + */ + void arm_fir_q31( + const arm_fir_instance_q31 * S, + q31_t * pSrc, + q31_t * pDst, + uint32_t blockSize); + + /** + * @brief Processing function for the fast Q31 FIR filter for Cortex-M3 and Cortex-M4. + * @param[in] *S points to an instance of the Q31 FIR structure. + * @param[in] *pSrc points to the block of input data. + * @param[out] *pDst points to the block of output data. + * @param[in] blockSize number of samples to process. + * @return none. + */ + void arm_fir_fast_q31( + const arm_fir_instance_q31 * S, + q31_t * pSrc, + q31_t * pDst, + uint32_t blockSize); + + /** + * @brief Initialization function for the Q31 FIR filter. + * @param[in,out] *S points to an instance of the Q31 FIR structure. + * @param[in] numTaps Number of filter coefficients in the filter. + * @param[in] *pCoeffs points to the filter coefficients. + * @param[in] *pState points to the state buffer. + * @param[in] blockSize number of samples that are processed at a time. + * @return none. + */ + void arm_fir_init_q31( + arm_fir_instance_q31 * S, + uint16_t numTaps, + q31_t * pCoeffs, + q31_t * pState, + uint32_t blockSize); + + /** + * @brief Processing function for the floating-point FIR filter. + * @param[in] *S points to an instance of the floating-point FIR structure. + * @param[in] *pSrc points to the block of input data. + * @param[out] *pDst points to the block of output data. + * @param[in] blockSize number of samples to process. + * @return none. + */ + void arm_fir_f32( + const arm_fir_instance_f32 * S, + float32_t * pSrc, + float32_t * pDst, + uint32_t blockSize); + + /** + * @brief Initialization function for the floating-point FIR filter. + * @param[in,out] *S points to an instance of the floating-point FIR filter structure. + * @param[in] numTaps Number of filter coefficients in the filter. + * @param[in] *pCoeffs points to the filter coefficients. + * @param[in] *pState points to the state buffer. + * @param[in] blockSize number of samples that are processed at a time. + * @return none. + */ + void arm_fir_init_f32( + arm_fir_instance_f32 * S, + uint16_t numTaps, + float32_t * pCoeffs, + float32_t * pState, + uint32_t blockSize); + + + /** + * @brief Instance structure for the Q15 Biquad cascade filter. + */ + typedef struct + { + int8_t numStages; /**< number of 2nd order stages in the filter. Overall order is 2*numStages. */ + q15_t *pState; /**< Points to the array of state coefficients. The array is of length 4*numStages. */ + q15_t *pCoeffs; /**< Points to the array of coefficients. The array is of length 5*numStages. */ + int8_t postShift; /**< Additional shift, in bits, applied to each output sample. */ + + } arm_biquad_casd_df1_inst_q15; + + + /** + * @brief Instance structure for the Q31 Biquad cascade filter. + */ + typedef struct + { + uint32_t numStages; /**< number of 2nd order stages in the filter. Overall order is 2*numStages. */ + q31_t *pState; /**< Points to the array of state coefficients. The array is of length 4*numStages. */ + q31_t *pCoeffs; /**< Points to the array of coefficients. The array is of length 5*numStages. */ + uint8_t postShift; /**< Additional shift, in bits, applied to each output sample. */ + + } arm_biquad_casd_df1_inst_q31; + + /** + * @brief Instance structure for the floating-point Biquad cascade filter. + */ + typedef struct + { + uint32_t numStages; /**< number of 2nd order stages in the filter. Overall order is 2*numStages. */ + float32_t *pState; /**< Points to the array of state coefficients. The array is of length 4*numStages. */ + float32_t *pCoeffs; /**< Points to the array of coefficients. The array is of length 5*numStages. */ + + + } arm_biquad_casd_df1_inst_f32; + + + + /** + * @brief Processing function for the Q15 Biquad cascade filter. + * @param[in] *S points to an instance of the Q15 Biquad cascade structure. + * @param[in] *pSrc points to the block of input data. + * @param[out] *pDst points to the block of output data. + * @param[in] blockSize number of samples to process. + * @return none. + */ + + void arm_biquad_cascade_df1_q15( + const arm_biquad_casd_df1_inst_q15 * S, + q15_t * pSrc, + q15_t * pDst, + uint32_t blockSize); + + /** + * @brief Initialization function for the Q15 Biquad cascade filter. + * @param[in,out] *S points to an instance of the Q15 Biquad cascade structure. + * @param[in] numStages number of 2nd order stages in the filter. + * @param[in] *pCoeffs points to the filter coefficients. + * @param[in] *pState points to the state buffer. + * @param[in] postShift Shift to be applied to the output. Varies according to the coefficients format + * @return none + */ + + void arm_biquad_cascade_df1_init_q15( + arm_biquad_casd_df1_inst_q15 * S, + uint8_t numStages, + q15_t * pCoeffs, + q15_t * pState, + int8_t postShift); + + + /** + * @brief Fast but less precise processing function for the Q15 Biquad cascade filter for Cortex-M3 and Cortex-M4. + * @param[in] *S points to an instance of the Q15 Biquad cascade structure. + * @param[in] *pSrc points to the block of input data. + * @param[out] *pDst points to the block of output data. + * @param[in] blockSize number of samples to process. + * @return none. + */ + + void arm_biquad_cascade_df1_fast_q15( + const arm_biquad_casd_df1_inst_q15 * S, + q15_t * pSrc, + q15_t * pDst, + uint32_t blockSize); + + + /** + * @brief Processing function for the Q31 Biquad cascade filter + * @param[in] *S points to an instance of the Q31 Biquad cascade structure. + * @param[in] *pSrc points to the block of input data. + * @param[out] *pDst points to the block of output data. + * @param[in] blockSize number of samples to process. + * @return none. + */ + + void arm_biquad_cascade_df1_q31( + const arm_biquad_casd_df1_inst_q31 * S, + q31_t * pSrc, + q31_t * pDst, + uint32_t blockSize); + + /** + * @brief Fast but less precise processing function for the Q31 Biquad cascade filter for Cortex-M3 and Cortex-M4. + * @param[in] *S points to an instance of the Q31 Biquad cascade structure. + * @param[in] *pSrc points to the block of input data. + * @param[out] *pDst points to the block of output data. + * @param[in] blockSize number of samples to process. + * @return none. + */ + + void arm_biquad_cascade_df1_fast_q31( + const arm_biquad_casd_df1_inst_q31 * S, + q31_t * pSrc, + q31_t * pDst, + uint32_t blockSize); + + /** + * @brief Initialization function for the Q31 Biquad cascade filter. + * @param[in,out] *S points to an instance of the Q31 Biquad cascade structure. + * @param[in] numStages number of 2nd order stages in the filter. + * @param[in] *pCoeffs points to the filter coefficients. + * @param[in] *pState points to the state buffer. + * @param[in] postShift Shift to be applied to the output. Varies according to the coefficients format + * @return none + */ + + void arm_biquad_cascade_df1_init_q31( + arm_biquad_casd_df1_inst_q31 * S, + uint8_t numStages, + q31_t * pCoeffs, + q31_t * pState, + int8_t postShift); + + /** + * @brief Processing function for the floating-point Biquad cascade filter. + * @param[in] *S points to an instance of the floating-point Biquad cascade structure. + * @param[in] *pSrc points to the block of input data. + * @param[out] *pDst points to the block of output data. + * @param[in] blockSize number of samples to process. + * @return none. + */ + + void arm_biquad_cascade_df1_f32( + const arm_biquad_casd_df1_inst_f32 * S, + float32_t * pSrc, + float32_t * pDst, + uint32_t blockSize); + + /** + * @brief Initialization function for the floating-point Biquad cascade filter. + * @param[in,out] *S points to an instance of the floating-point Biquad cascade structure. + * @param[in] numStages number of 2nd order stages in the filter. + * @param[in] *pCoeffs points to the filter coefficients. + * @param[in] *pState points to the state buffer. + * @return none + */ + + void arm_biquad_cascade_df1_init_f32( + arm_biquad_casd_df1_inst_f32 * S, + uint8_t numStages, + float32_t * pCoeffs, + float32_t * pState); + + + /** + * @brief Instance structure for the floating-point matrix structure. + */ + + typedef struct + { + uint16_t numRows; /**< number of rows of the matrix. */ + uint16_t numCols; /**< number of columns of the matrix. */ + float32_t *pData; /**< points to the data of the matrix. */ + } arm_matrix_instance_f32; + + /** + * @brief Instance structure for the Q15 matrix structure. + */ + + typedef struct + { + uint16_t numRows; /**< number of rows of the matrix. */ + uint16_t numCols; /**< number of columns of the matrix. */ + q15_t *pData; /**< points to the data of the matrix. */ + + } arm_matrix_instance_q15; + + /** + * @brief Instance structure for the Q31 matrix structure. + */ + + typedef struct + { + uint16_t numRows; /**< number of rows of the matrix. */ + uint16_t numCols; /**< number of columns of the matrix. */ + q31_t *pData; /**< points to the data of the matrix. */ + + } arm_matrix_instance_q31; + + + + /** + * @brief Floating-point matrix addition. + * @param[in] *pSrcA points to the first input matrix structure + * @param[in] *pSrcB points to the second input matrix structure + * @param[out] *pDst points to output matrix structure + * @return The function returns either + * ARM_MATH_SIZE_MISMATCH or ARM_MATH_SUCCESS based on the outcome of size checking. + */ + + arm_status arm_mat_add_f32( + const arm_matrix_instance_f32 * pSrcA, + const arm_matrix_instance_f32 * pSrcB, + arm_matrix_instance_f32 * pDst); + + /** + * @brief Q15 matrix addition. + * @param[in] *pSrcA points to the first input matrix structure + * @param[in] *pSrcB points to the second input matrix structure + * @param[out] *pDst points to output matrix structure + * @return The function returns either + * ARM_MATH_SIZE_MISMATCH or ARM_MATH_SUCCESS based on the outcome of size checking. + */ + + arm_status arm_mat_add_q15( + const arm_matrix_instance_q15 * pSrcA, + const arm_matrix_instance_q15 * pSrcB, + arm_matrix_instance_q15 * pDst); + + /** + * @brief Q31 matrix addition. + * @param[in] *pSrcA points to the first input matrix structure + * @param[in] *pSrcB points to the second input matrix structure + * @param[out] *pDst points to output matrix structure + * @return The function returns either + * ARM_MATH_SIZE_MISMATCH or ARM_MATH_SUCCESS based on the outcome of size checking. + */ + + arm_status arm_mat_add_q31( + const arm_matrix_instance_q31 * pSrcA, + const arm_matrix_instance_q31 * pSrcB, + arm_matrix_instance_q31 * pDst); + + + /** + * @brief Floating-point matrix transpose. + * @param[in] *pSrc points to the input matrix + * @param[out] *pDst points to the output matrix + * @return The function returns either ARM_MATH_SIZE_MISMATCH + * or ARM_MATH_SUCCESS based on the outcome of size checking. + */ + + arm_status arm_mat_trans_f32( + const arm_matrix_instance_f32 * pSrc, + arm_matrix_instance_f32 * pDst); + + + /** + * @brief Q15 matrix transpose. + * @param[in] *pSrc points to the input matrix + * @param[out] *pDst points to the output matrix + * @return The function returns either ARM_MATH_SIZE_MISMATCH + * or ARM_MATH_SUCCESS based on the outcome of size checking. + */ + + arm_status arm_mat_trans_q15( + const arm_matrix_instance_q15 * pSrc, + arm_matrix_instance_q15 * pDst); + + /** + * @brief Q31 matrix transpose. + * @param[in] *pSrc points to the input matrix + * @param[out] *pDst points to the output matrix + * @return The function returns either ARM_MATH_SIZE_MISMATCH + * or ARM_MATH_SUCCESS based on the outcome of size checking. + */ + + arm_status arm_mat_trans_q31( + const arm_matrix_instance_q31 * pSrc, + arm_matrix_instance_q31 * pDst); + + + /** + * @brief Floating-point matrix multiplication + * @param[in] *pSrcA points to the first input matrix structure + * @param[in] *pSrcB points to the second input matrix structure + * @param[out] *pDst points to output matrix structure + * @return The function returns either + * ARM_MATH_SIZE_MISMATCH or ARM_MATH_SUCCESS based on the outcome of size checking. + */ + + arm_status arm_mat_mult_f32( + const arm_matrix_instance_f32 * pSrcA, + const arm_matrix_instance_f32 * pSrcB, + arm_matrix_instance_f32 * pDst); + + /** + * @brief Q15 matrix multiplication + * @param[in] *pSrcA points to the first input matrix structure + * @param[in] *pSrcB points to the second input matrix structure + * @param[out] *pDst points to output matrix structure + * @return The function returns either + * ARM_MATH_SIZE_MISMATCH or ARM_MATH_SUCCESS based on the outcome of size checking. + */ + + arm_status arm_mat_mult_q15( + const arm_matrix_instance_q15 * pSrcA, + const arm_matrix_instance_q15 * pSrcB, + arm_matrix_instance_q15 * pDst, + q15_t * pState); + + /** + * @brief Q15 matrix multiplication (fast variant) for Cortex-M3 and Cortex-M4 + * @param[in] *pSrcA points to the first input matrix structure + * @param[in] *pSrcB points to the second input matrix structure + * @param[out] *pDst points to output matrix structure + * @param[in] *pState points to the array for storing intermediate results + * @return The function returns either + * ARM_MATH_SIZE_MISMATCH or ARM_MATH_SUCCESS based on the outcome of size checking. + */ + + arm_status arm_mat_mult_fast_q15( + const arm_matrix_instance_q15 * pSrcA, + const arm_matrix_instance_q15 * pSrcB, + arm_matrix_instance_q15 * pDst, + q15_t * pState); + + /** + * @brief Q31 matrix multiplication + * @param[in] *pSrcA points to the first input matrix structure + * @param[in] *pSrcB points to the second input matrix structure + * @param[out] *pDst points to output matrix structure + * @return The function returns either + * ARM_MATH_SIZE_MISMATCH or ARM_MATH_SUCCESS based on the outcome of size checking. + */ + + arm_status arm_mat_mult_q31( + const arm_matrix_instance_q31 * pSrcA, + const arm_matrix_instance_q31 * pSrcB, + arm_matrix_instance_q31 * pDst); + + /** + * @brief Q31 matrix multiplication (fast variant) for Cortex-M3 and Cortex-M4 + * @param[in] *pSrcA points to the first input matrix structure + * @param[in] *pSrcB points to the second input matrix structure + * @param[out] *pDst points to output matrix structure + * @return The function returns either + * ARM_MATH_SIZE_MISMATCH or ARM_MATH_SUCCESS based on the outcome of size checking. + */ + + arm_status arm_mat_mult_fast_q31( + const arm_matrix_instance_q31 * pSrcA, + const arm_matrix_instance_q31 * pSrcB, + arm_matrix_instance_q31 * pDst); + + + /** + * @brief Floating-point matrix subtraction + * @param[in] *pSrcA points to the first input matrix structure + * @param[in] *pSrcB points to the second input matrix structure + * @param[out] *pDst points to output matrix structure + * @return The function returns either + * ARM_MATH_SIZE_MISMATCH or ARM_MATH_SUCCESS based on the outcome of size checking. + */ + + arm_status arm_mat_sub_f32( + const arm_matrix_instance_f32 * pSrcA, + const arm_matrix_instance_f32 * pSrcB, + arm_matrix_instance_f32 * pDst); + + /** + * @brief Q15 matrix subtraction + * @param[in] *pSrcA points to the first input matrix structure + * @param[in] *pSrcB points to the second input matrix structure + * @param[out] *pDst points to output matrix structure + * @return The function returns either + * ARM_MATH_SIZE_MISMATCH or ARM_MATH_SUCCESS based on the outcome of size checking. + */ + + arm_status arm_mat_sub_q15( + const arm_matrix_instance_q15 * pSrcA, + const arm_matrix_instance_q15 * pSrcB, + arm_matrix_instance_q15 * pDst); + + /** + * @brief Q31 matrix subtraction + * @param[in] *pSrcA points to the first input matrix structure + * @param[in] *pSrcB points to the second input matrix structure + * @param[out] *pDst points to output matrix structure + * @return The function returns either + * ARM_MATH_SIZE_MISMATCH or ARM_MATH_SUCCESS based on the outcome of size checking. + */ + + arm_status arm_mat_sub_q31( + const arm_matrix_instance_q31 * pSrcA, + const arm_matrix_instance_q31 * pSrcB, + arm_matrix_instance_q31 * pDst); + + /** + * @brief Floating-point matrix scaling. + * @param[in] *pSrc points to the input matrix + * @param[in] scale scale factor + * @param[out] *pDst points to the output matrix + * @return The function returns either + * ARM_MATH_SIZE_MISMATCH or ARM_MATH_SUCCESS based on the outcome of size checking. + */ + + arm_status arm_mat_scale_f32( + const arm_matrix_instance_f32 * pSrc, + float32_t scale, + arm_matrix_instance_f32 * pDst); + + /** + * @brief Q15 matrix scaling. + * @param[in] *pSrc points to input matrix + * @param[in] scaleFract fractional portion of the scale factor + * @param[in] shift number of bits to shift the result by + * @param[out] *pDst points to output matrix + * @return The function returns either + * ARM_MATH_SIZE_MISMATCH or ARM_MATH_SUCCESS based on the outcome of size checking. + */ + + arm_status arm_mat_scale_q15( + const arm_matrix_instance_q15 * pSrc, + q15_t scaleFract, + int32_t shift, + arm_matrix_instance_q15 * pDst); + + /** + * @brief Q31 matrix scaling. + * @param[in] *pSrc points to input matrix + * @param[in] scaleFract fractional portion of the scale factor + * @param[in] shift number of bits to shift the result by + * @param[out] *pDst points to output matrix structure + * @return The function returns either + * ARM_MATH_SIZE_MISMATCH or ARM_MATH_SUCCESS based on the outcome of size checking. + */ + + arm_status arm_mat_scale_q31( + const arm_matrix_instance_q31 * pSrc, + q31_t scaleFract, + int32_t shift, + arm_matrix_instance_q31 * pDst); + + + /** + * @brief Q31 matrix initialization. + * @param[in,out] *S points to an instance of the floating-point matrix structure. + * @param[in] nRows number of rows in the matrix. + * @param[in] nColumns number of columns in the matrix. + * @param[in] *pData points to the matrix data array. + * @return none + */ + + void arm_mat_init_q31( + arm_matrix_instance_q31 * S, + uint16_t nRows, + uint16_t nColumns, + q31_t * pData); + + /** + * @brief Q15 matrix initialization. + * @param[in,out] *S points to an instance of the floating-point matrix structure. + * @param[in] nRows number of rows in the matrix. + * @param[in] nColumns number of columns in the matrix. + * @param[in] *pData points to the matrix data array. + * @return none + */ + + void arm_mat_init_q15( + arm_matrix_instance_q15 * S, + uint16_t nRows, + uint16_t nColumns, + q15_t * pData); + + /** + * @brief Floating-point matrix initialization. + * @param[in,out] *S points to an instance of the floating-point matrix structure. + * @param[in] nRows number of rows in the matrix. + * @param[in] nColumns number of columns in the matrix. + * @param[in] *pData points to the matrix data array. + * @return none + */ + + void arm_mat_init_f32( + arm_matrix_instance_f32 * S, + uint16_t nRows, + uint16_t nColumns, + float32_t * pData); + + + + /** + * @brief Instance structure for the Q15 PID Control. + */ + typedef struct + { + q15_t A0; /**< The derived gain, A0 = Kp + Ki + Kd . */ +#ifdef ARM_MATH_CM0 + q15_t A1; + q15_t A2; +#else + q31_t A1; /**< The derived gain A1 = -Kp - 2Kd | Kd.*/ +#endif + q15_t state[3]; /**< The state array of length 3. */ + q15_t Kp; /**< The proportional gain. */ + q15_t Ki; /**< The integral gain. */ + q15_t Kd; /**< The derivative gain. */ + } arm_pid_instance_q15; + + /** + * @brief Instance structure for the Q31 PID Control. + */ + typedef struct + { + q31_t A0; /**< The derived gain, A0 = Kp + Ki + Kd . */ + q31_t A1; /**< The derived gain, A1 = -Kp - 2Kd. */ + q31_t A2; /**< The derived gain, A2 = Kd . */ + q31_t state[3]; /**< The state array of length 3. */ + q31_t Kp; /**< The proportional gain. */ + q31_t Ki; /**< The integral gain. */ + q31_t Kd; /**< The derivative gain. */ + + } arm_pid_instance_q31; + + /** + * @brief Instance structure for the floating-point PID Control. + */ + typedef struct + { + float32_t A0; /**< The derived gain, A0 = Kp + Ki + Kd . */ + float32_t A1; /**< The derived gain, A1 = -Kp - 2Kd. */ + float32_t A2; /**< The derived gain, A2 = Kd . */ + float32_t state[3]; /**< The state array of length 3. */ + float32_t Kp; /**< The proportional gain. */ + float32_t Ki; /**< The integral gain. */ + float32_t Kd; /**< The derivative gain. */ + } arm_pid_instance_f32; + + + + /** + * @brief Initialization function for the floating-point PID Control. + * @param[in,out] *S points to an instance of the PID structure. + * @param[in] resetStateFlag flag to reset the state. 0 = no change in state 1 = reset the state. + * @return none. + */ + void arm_pid_init_f32( + arm_pid_instance_f32 * S, + int32_t resetStateFlag); + + /** + * @brief Reset function for the floating-point PID Control. + * @param[in,out] *S is an instance of the floating-point PID Control structure + * @return none + */ + void arm_pid_reset_f32( + arm_pid_instance_f32 * S); + + + /** + * @brief Initialization function for the Q31 PID Control. + * @param[in,out] *S points to an instance of the Q15 PID structure. + * @param[in] resetStateFlag flag to reset the state. 0 = no change in state 1 = reset the state. + * @return none. + */ + void arm_pid_init_q31( + arm_pid_instance_q31 * S, + int32_t resetStateFlag); + + + /** + * @brief Reset function for the Q31 PID Control. + * @param[in,out] *S points to an instance of the Q31 PID Control structure + * @return none + */ + + void arm_pid_reset_q31( + arm_pid_instance_q31 * S); + + /** + * @brief Initialization function for the Q15 PID Control. + * @param[in,out] *S points to an instance of the Q15 PID structure. + * @param[in] resetStateFlag flag to reset the state. 0 = no change in state 1 = reset the state. + * @return none. + */ + void arm_pid_init_q15( + arm_pid_instance_q15 * S, + int32_t resetStateFlag); + + /** + * @brief Reset function for the Q15 PID Control. + * @param[in,out] *S points to an instance of the q15 PID Control structure + * @return none + */ + void arm_pid_reset_q15( + arm_pid_instance_q15 * S); + + + /** + * @brief Instance structure for the floating-point Linear Interpolate function. + */ + typedef struct + { + uint32_t nValues; /**< nValues */ + float32_t x1; /**< x1 */ + float32_t xSpacing; /**< xSpacing */ + float32_t *pYData; /**< pointer to the table of Y values */ + } arm_linear_interp_instance_f32; + + /** + * @brief Instance structure for the floating-point bilinear interpolation function. + */ + + typedef struct + { + uint16_t numRows; /**< number of rows in the data table. */ + uint16_t numCols; /**< number of columns in the data table. */ + float32_t *pData; /**< points to the data table. */ + } arm_bilinear_interp_instance_f32; + + /** + * @brief Instance structure for the Q31 bilinear interpolation function. + */ + + typedef struct + { + uint16_t numRows; /**< number of rows in the data table. */ + uint16_t numCols; /**< number of columns in the data table. */ + q31_t *pData; /**< points to the data table. */ + } arm_bilinear_interp_instance_q31; + + /** + * @brief Instance structure for the Q15 bilinear interpolation function. + */ + + typedef struct + { + uint16_t numRows; /**< number of rows in the data table. */ + uint16_t numCols; /**< number of columns in the data table. */ + q15_t *pData; /**< points to the data table. */ + } arm_bilinear_interp_instance_q15; + + /** + * @brief Instance structure for the Q15 bilinear interpolation function. + */ + + typedef struct + { + uint16_t numRows; /**< number of rows in the data table. */ + uint16_t numCols; /**< number of columns in the data table. */ + q7_t *pData; /**< points to the data table. */ + } arm_bilinear_interp_instance_q7; + + + /** + * @brief Q7 vector multiplication. + * @param[in] *pSrcA points to the first input vector + * @param[in] *pSrcB points to the second input vector + * @param[out] *pDst points to the output vector + * @param[in] blockSize number of samples in each vector + * @return none. + */ + + void arm_mult_q7( + q7_t * pSrcA, + q7_t * pSrcB, + q7_t * pDst, + uint32_t blockSize); + + /** + * @brief Q15 vector multiplication. + * @param[in] *pSrcA points to the first input vector + * @param[in] *pSrcB points to the second input vector + * @param[out] *pDst points to the output vector + * @param[in] blockSize number of samples in each vector + * @return none. + */ + + void arm_mult_q15( + q15_t * pSrcA, + q15_t * pSrcB, + q15_t * pDst, + uint32_t blockSize); + + /** + * @brief Q31 vector multiplication. + * @param[in] *pSrcA points to the first input vector + * @param[in] *pSrcB points to the second input vector + * @param[out] *pDst points to the output vector + * @param[in] blockSize number of samples in each vector + * @return none. + */ + + void arm_mult_q31( + q31_t * pSrcA, + q31_t * pSrcB, + q31_t * pDst, + uint32_t blockSize); + + /** + * @brief Floating-point vector multiplication. + * @param[in] *pSrcA points to the first input vector + * @param[in] *pSrcB points to the second input vector + * @param[out] *pDst points to the output vector + * @param[in] blockSize number of samples in each vector + * @return none. + */ + + void arm_mult_f32( + float32_t * pSrcA, + float32_t * pSrcB, + float32_t * pDst, + uint32_t blockSize); + + + /** + * @brief Instance structure for the Q15 CFFT/CIFFT function. + */ + + typedef struct + { + uint16_t fftLen; /**< length of the FFT. */ + uint8_t ifftFlag; /**< flag that selects forward (ifftFlag=0) or inverse (ifftFlag=1) transform. */ + uint8_t bitReverseFlag; /**< flag that enables (bitReverseFlag=1) or disables (bitReverseFlag=0) bit reversal of output. */ + q15_t *pTwiddle; /**< points to the twiddle factor table. */ + uint16_t *pBitRevTable; /**< points to the bit reversal table. */ + uint16_t twidCoefModifier; /**< twiddle coefficient modifier that supports different size FFTs with the same twiddle factor table. */ + uint16_t bitRevFactor; /**< bit reversal modifier that supports different size FFTs with the same bit reversal table. */ + } arm_cfft_radix4_instance_q15; + + /** + * @brief Instance structure for the Q31 CFFT/CIFFT function. + */ + + typedef struct + { + uint16_t fftLen; /**< length of the FFT. */ + uint8_t ifftFlag; /**< flag that selects forward (ifftFlag=0) or inverse (ifftFlag=1) transform. */ + uint8_t bitReverseFlag; /**< flag that enables (bitReverseFlag=1) or disables (bitReverseFlag=0) bit reversal of output. */ + q31_t *pTwiddle; /**< points to the twiddle factor table. */ + uint16_t *pBitRevTable; /**< points to the bit reversal table. */ + uint16_t twidCoefModifier; /**< twiddle coefficient modifier that supports different size FFTs with the same twiddle factor table. */ + uint16_t bitRevFactor; /**< bit reversal modifier that supports different size FFTs with the same bit reversal table. */ + } arm_cfft_radix4_instance_q31; + + + /** + * @brief Instance structure for the floating-point CFFT/CIFFT function. + */ + + typedef struct + { + uint16_t fftLen; /**< length of the FFT. */ + uint8_t ifftFlag; /**< flag that selects forward (ifftFlag=0) or inverse (ifftFlag=1) transform. */ + uint8_t bitReverseFlag; /**< flag that enables (bitReverseFlag=1) or disables (bitReverseFlag=0) bit reversal of output. */ + float32_t *pTwiddle; /**< points to the twiddle factor table. */ + uint16_t *pBitRevTable; /**< points to the bit reversal table. */ + uint16_t twidCoefModifier; /**< twiddle coefficient modifier that supports different size FFTs with the same twiddle factor table. */ + uint16_t bitRevFactor; /**< bit reversal modifier that supports different size FFTs with the same bit reversal table. */ + float32_t onebyfftLen; /**< value of 1/fftLen. */ + } arm_cfft_radix4_instance_f32; + + + /** + * @brief Instance structure for the Q15 CFFT/CIFFT function. + */ + + typedef struct + { + uint16_t fftLen; /**< length of the FFT. */ + uint8_t ifftFlag; /**< flag that selects forward (ifftFlag=0) or inverse (ifftFlag=1) transform. */ + uint8_t bitReverseFlag; /**< flag that enables (bitReverseFlag=1) or disables (bitReverseFlag=0) bit reversal of output. */ + q15_t *pTwiddle; /**< points to the Sin twiddle factor table. */ + uint16_t *pBitRevTable; /**< points to the bit reversal table. */ + uint16_t twidCoefModifier; /**< twiddle coefficient modifier that supports different size FFTs with the same twiddle factor table. */ + uint16_t bitRevFactor; /**< bit reversal modifier that supports different size FFTs with the same bit reversal table. */ + } arm_cfft_radix2_instance_q15; + + /** + * @brief Instance structure for the Radix-2 Q31 CFFT/CIFFT function. + */ + + typedef struct + { + uint16_t fftLen; /**< length of the FFT. */ + uint8_t ifftFlag; /**< flag that selects forward (ifftFlag=0) or inverse (ifftFlag=1) transform. */ + uint8_t bitReverseFlag; /**< flag that enables (bitReverseFlag=1) or disables (bitReverseFlag=0) bit reversal of output. */ + q31_t *pTwiddle; /**< points to the Twiddle factor table. */ + uint16_t *pBitRevTable; /**< points to the bit reversal table. */ + uint16_t twidCoefModifier; /**< twiddle coefficient modifier that supports different size FFTs with the same twiddle factor table. */ + uint16_t bitRevFactor; /**< bit reversal modifier that supports different size FFTs with the same bit reversal table. */ + } arm_cfft_radix2_instance_q31; + + /** + * @brief Instance structure for the floating-point CFFT/CIFFT function. + */ + + typedef struct + { + uint16_t fftLen; /**< length of the FFT. */ + uint8_t ifftFlag; /**< flag that selects forward (ifftFlag=0) or inverse (ifftFlag=1) transform. */ + uint8_t bitReverseFlag; /**< flag that enables (bitReverseFlag=1) or disables (bitReverseFlag=0) bit reversal of output. */ + float32_t *pTwiddle; /**< points to the Twiddle factor table. */ + uint16_t *pBitRevTable; /**< points to the bit reversal table. */ + uint16_t twidCoefModifier; /**< twiddle coefficient modifier that supports different size FFTs with the same twiddle factor table. */ + uint16_t bitRevFactor; /**< bit reversal modifier that supports different size FFTs with the same bit reversal table. */ + float32_t onebyfftLen; /**< value of 1/fftLen. */ + } arm_cfft_radix2_instance_f32; + + + /** + * @brief Processing function for the Q15 CFFT/CIFFT. + * @param[in] *S points to an instance of the Q15 CFFT/CIFFT structure. + * @param[in, out] *pSrc points to the complex data buffer. Processing occurs in-place. + * @return none. + */ + + void arm_cfft_radix4_q15( + const arm_cfft_radix4_instance_q15 * S, + q15_t * pSrc); + + /** + * @brief Processing function for the Q15 CFFT/CIFFT. + * @param[in] *S points to an instance of the Q15 CFFT/CIFFT structure. + * @param[in, out] *pSrc points to the complex data buffer. Processing occurs in-place. + * @return none. + */ + + void arm_cfft_radix2_q15( + const arm_cfft_radix2_instance_q15 * S, + q15_t * pSrc); + + /** + * @brief Initialization function for the Q15 CFFT/CIFFT. + * @param[in,out] *S points to an instance of the Q15 CFFT/CIFFT structure. + * @param[in] fftLen length of the FFT. + * @param[in] ifftFlag flag that selects forward (ifftFlag=0) or inverse (ifftFlag=1) transform. + * @param[in] bitReverseFlag flag that enables (bitReverseFlag=1) or disables (bitReverseFlag=0) bit reversal of output. + * @return arm_status function returns ARM_MATH_SUCCESS if initialization is successful or ARM_MATH_ARGUMENT_ERROR if fftLen is not a supported value. + */ + + arm_status arm_cfft_radix4_init_q15( + arm_cfft_radix4_instance_q15 * S, + uint16_t fftLen, + uint8_t ifftFlag, + uint8_t bitReverseFlag); + + /** + * @brief Initialization function for the Q15 CFFT/CIFFT. + * @param[in,out] *S points to an instance of the Q15 CFFT/CIFFT structure. + * @param[in] fftLen length of the FFT. + * @param[in] ifftFlag flag that selects forward (ifftFlag=0) or inverse (ifftFlag=1) transform. + * @param[in] bitReverseFlag flag that enables (bitReverseFlag=1) or disables (bitReverseFlag=0) bit reversal of output. + * @return arm_status function returns ARM_MATH_SUCCESS if initialization is successful or ARM_MATH_ARGUMENT_ERROR if fftLen is not a supported value. + */ + + arm_status arm_cfft_radix2_init_q15( + arm_cfft_radix2_instance_q15 * S, + uint16_t fftLen, + uint8_t ifftFlag, + uint8_t bitReverseFlag); + + /** + * @brief Processing function for the Q31 CFFT/CIFFT. + * @param[in] *S points to an instance of the Q31 CFFT/CIFFT structure. + * @param[in, out] *pSrc points to the complex data buffer. Processing occurs in-place. + * @return none. + */ + + void arm_cfft_radix4_q31( + const arm_cfft_radix4_instance_q31 * S, + q31_t * pSrc); + + /** + * @brief Initialization function for the Q31 CFFT/CIFFT. + * @param[in,out] *S points to an instance of the Q31 CFFT/CIFFT structure. + * @param[in] fftLen length of the FFT. + * @param[in] ifftFlag flag that selects forward (ifftFlag=0) or inverse (ifftFlag=1) transform. + * @param[in] bitReverseFlag flag that enables (bitReverseFlag=1) or disables (bitReverseFlag=0) bit reversal of output. + * @return arm_status function returns ARM_MATH_SUCCESS if initialization is successful or ARM_MATH_ARGUMENT_ERROR if fftLen is not a supported value. + */ + + arm_status arm_cfft_radix4_init_q31( + arm_cfft_radix4_instance_q31 * S, + uint16_t fftLen, + uint8_t ifftFlag, + uint8_t bitReverseFlag); + + /** + * @brief Processing function for the Radix-2 Q31 CFFT/CIFFT. + * @param[in] *S points to an instance of the Radix-2 Q31 CFFT/CIFFT structure. + * @param[in, out] *pSrc points to the complex data buffer. Processing occurs in-place. + * @return none. + */ + + void arm_cfft_radix2_q31( + const arm_cfft_radix2_instance_q31 * S, + q31_t * pSrc); + + /** + * @brief Initialization function for the Radix-2 Q31 CFFT/CIFFT. + * @param[in,out] *S points to an instance of the Radix-2 Q31 CFFT/CIFFT structure. + * @param[in] fftLen length of the FFT. + * @param[in] ifftFlag flag that selects forward (ifftFlag=0) or inverse (ifftFlag=1) transform. + * @param[in] bitReverseFlag flag that enables (bitReverseFlag=1) or disables (bitReverseFlag=0) bit reversal of output. + * @return arm_status function returns ARM_MATH_SUCCESS if initialization is successful or ARM_MATH_ARGUMENT_ERROR if fftLen is not a supported value. + */ + + arm_status arm_cfft_radix2_init_q31( + arm_cfft_radix2_instance_q31 * S, + uint16_t fftLen, + uint8_t ifftFlag, + uint8_t bitReverseFlag); + + + + /** + * @brief Processing function for the floating-point CFFT/CIFFT. + * @param[in] *S points to an instance of the floating-point CFFT/CIFFT structure. + * @param[in, out] *pSrc points to the complex data buffer. Processing occurs in-place. + * @return none. + */ + + void arm_cfft_radix2_f32( + const arm_cfft_radix2_instance_f32 * S, + float32_t * pSrc); + + /** + * @brief Initialization function for the floating-point CFFT/CIFFT. + * @param[in,out] *S points to an instance of the floating-point CFFT/CIFFT structure. + * @param[in] fftLen length of the FFT. + * @param[in] ifftFlag flag that selects forward (ifftFlag=0) or inverse (ifftFlag=1) transform. + * @param[in] bitReverseFlag flag that enables (bitReverseFlag=1) or disables (bitReverseFlag=0) bit reversal of output. + * @return The function returns ARM_MATH_SUCCESS if initialization is successful or ARM_MATH_ARGUMENT_ERROR if fftLen is not a supported value. + */ + + arm_status arm_cfft_radix2_init_f32( + arm_cfft_radix2_instance_f32 * S, + uint16_t fftLen, + uint8_t ifftFlag, + uint8_t bitReverseFlag); + + /** + * @brief Processing function for the floating-point CFFT/CIFFT. + * @param[in] *S points to an instance of the floating-point CFFT/CIFFT structure. + * @param[in, out] *pSrc points to the complex data buffer. Processing occurs in-place. + * @return none. + */ + + void arm_cfft_radix4_f32( + const arm_cfft_radix4_instance_f32 * S, + float32_t * pSrc); + + /** + * @brief Initialization function for the floating-point CFFT/CIFFT. + * @param[in,out] *S points to an instance of the floating-point CFFT/CIFFT structure. + * @param[in] fftLen length of the FFT. + * @param[in] ifftFlag flag that selects forward (ifftFlag=0) or inverse (ifftFlag=1) transform. + * @param[in] bitReverseFlag flag that enables (bitReverseFlag=1) or disables (bitReverseFlag=0) bit reversal of output. + * @return The function returns ARM_MATH_SUCCESS if initialization is successful or ARM_MATH_ARGUMENT_ERROR if fftLen is not a supported value. + */ + + arm_status arm_cfft_radix4_init_f32( + arm_cfft_radix4_instance_f32 * S, + uint16_t fftLen, + uint8_t ifftFlag, + uint8_t bitReverseFlag); + + + + /*---------------------------------------------------------------------- + * Internal functions prototypes FFT function + ----------------------------------------------------------------------*/ + + /** + * @brief Core function for the floating-point CFFT butterfly process. + * @param[in, out] *pSrc points to the in-place buffer of floating-point data type. + * @param[in] fftLen length of the FFT. + * @param[in] *pCoef points to the twiddle coefficient buffer. + * @param[in] twidCoefModifier twiddle coefficient modifier that supports different size FFTs with the same twiddle factor table. + * @return none. + */ + + void arm_radix4_butterfly_f32( + float32_t * pSrc, + uint16_t fftLen, + float32_t * pCoef, + uint16_t twidCoefModifier); + + /** + * @brief Core function for the floating-point CIFFT butterfly process. + * @param[in, out] *pSrc points to the in-place buffer of floating-point data type. + * @param[in] fftLen length of the FFT. + * @param[in] *pCoef points to twiddle coefficient buffer. + * @param[in] twidCoefModifier twiddle coefficient modifier that supports different size FFTs with the same twiddle factor table. + * @param[in] onebyfftLen value of 1/fftLen. + * @return none. + */ + + void arm_radix4_butterfly_inverse_f32( + float32_t * pSrc, + uint16_t fftLen, + float32_t * pCoef, + uint16_t twidCoefModifier, + float32_t onebyfftLen); + + /** + * @brief In-place bit reversal function. + * @param[in, out] *pSrc points to the in-place buffer of floating-point data type. + * @param[in] fftSize length of the FFT. + * @param[in] bitRevFactor bit reversal modifier that supports different size FFTs with the same bit reversal table. + * @param[in] *pBitRevTab points to the bit reversal table. + * @return none. + */ + + void arm_bitreversal_f32( + float32_t * pSrc, + uint16_t fftSize, + uint16_t bitRevFactor, + uint16_t * pBitRevTab); + + /** + * @brief Core function for the Q31 CFFT butterfly process. + * @param[in, out] *pSrc points to the in-place buffer of Q31 data type. + * @param[in] fftLen length of the FFT. + * @param[in] *pCoef points to Twiddle coefficient buffer. + * @param[in] twidCoefModifier twiddle coefficient modifier that supports different size FFTs with the same twiddle factor table. + * @return none. + */ + + void arm_radix4_butterfly_q31( + q31_t * pSrc, + uint32_t fftLen, + q31_t * pCoef, + uint32_t twidCoefModifier); + + /** + * @brief Core function for the f32 FFT butterfly process. + * @param[in, out] *pSrc points to the in-place buffer of f32 data type. + * @param[in] fftLen length of the FFT. + * @param[in] *pCoef points to Twiddle coefficient buffer. + * @param[in] twidCoefModifier twiddle coefficient modifier that supports different size FFTs with the same twiddle factor table. + * @return none. + */ + + void arm_radix2_butterfly_f32( + float32_t * pSrc, + uint32_t fftLen, + float32_t * pCoef, + uint16_t twidCoefModifier); + + /** + * @brief Core function for the Radix-2 Q31 CFFT butterfly process. + * @param[in, out] *pSrc points to the in-place buffer of Q31 data type. + * @param[in] fftLen length of the FFT. + * @param[in] *pCoef points to Twiddle coefficient buffer. + * @param[in] twidCoefModifier twiddle coefficient modifier that supports different size FFTs with the same twiddle factor table. + * @return none. + */ + + void arm_radix2_butterfly_q31( + q31_t * pSrc, + uint32_t fftLen, + q31_t * pCoef, + uint16_t twidCoefModifier); + + /** + * @brief Core function for the Radix-2 Q15 CFFT butterfly process. + * @param[in, out] *pSrc points to the in-place buffer of Q15 data type. + * @param[in] fftLen length of the FFT. + * @param[in] *pCoef points to Twiddle coefficient buffer. + * @param[in] twidCoefModifier twiddle coefficient modifier that supports different size FFTs with the same twiddle factor table. + * @return none. + */ + + void arm_radix2_butterfly_q15( + q15_t * pSrc, + uint32_t fftLen, + q15_t * pCoef, + uint16_t twidCoefModifier); + + /** + * @brief Core function for the Radix-2 Q15 CFFT Inverse butterfly process. + * @param[in, out] *pSrc points to the in-place buffer of Q15 data type. + * @param[in] fftLen length of the FFT. + * @param[in] *pCoef points to Twiddle coefficient buffer. + * @param[in] twidCoefModifier twiddle coefficient modifier that supports different size FFTs with the same twiddle factor table. + * @return none. + */ + + void arm_radix2_butterfly_inverse_q15( + q15_t * pSrc, + uint32_t fftLen, + q15_t * pCoef, + uint16_t twidCoefModifier); + + /** + * @brief Core function for the Radix-2 Q31 CFFT Inverse butterfly process. + * @param[in, out] *pSrc points to the in-place buffer of Q31 data type. + * @param[in] fftLen length of the FFT. + * @param[in] *pCoef points to Twiddle coefficient buffer. + * @param[in] twidCoefModifier twiddle coefficient modifier that supports different size FFTs with the same twiddle factor table. + * @return none. + */ + + void arm_radix2_butterfly_inverse_q31( + q31_t * pSrc, + uint32_t fftLen, + q31_t * pCoef, + uint16_t twidCoefModifier); + + /** + * @brief Core function for the f32 IFFT butterfly process. + * @param[in, out] *pSrc points to the in-place buffer of f32 data type. + * @param[in] fftLen length of the FFT. + * @param[in] *pCoef points to Twiddle coefficient buffer. + * @param[in] twidCoefModifier twiddle coefficient modifier that supports different size FFTs with the same twiddle factor table. + * @param[in] onebyfftLen 1/fftLenfth + * @return none. + */ + + void arm_radix2_butterfly_inverse_f32( + float32_t * pSrc, + uint32_t fftLen, + float32_t * pCoef, + uint16_t twidCoefModifier, + float32_t onebyfftLen); + + /** + * @brief Core function for the Q31 CIFFT butterfly process. + * @param[in, out] *pSrc points to the in-place buffer of Q31 data type. + * @param[in] fftLen length of the FFT. + * @param[in] *pCoef points to twiddle coefficient buffer. + * @param[in] twidCoefModifier twiddle coefficient modifier that supports different size FFTs with the same twiddle factor table. + * @return none. + */ + + void arm_radix4_butterfly_inverse_q31( + q31_t * pSrc, + uint32_t fftLen, + q31_t * pCoef, + uint32_t twidCoefModifier); + + /** + * @brief In-place bit reversal function. + * @param[in, out] *pSrc points to the in-place buffer of Q31 data type. + * @param[in] fftLen length of the FFT. + * @param[in] bitRevFactor bit reversal modifier that supports different size FFTs with the same bit reversal table + * @param[in] *pBitRevTab points to bit reversal table. + * @return none. + */ + + void arm_bitreversal_q31( + q31_t * pSrc, + uint32_t fftLen, + uint16_t bitRevFactor, + uint16_t * pBitRevTab); + + /** + * @brief Core function for the Q15 CFFT butterfly process. + * @param[in, out] *pSrc16 points to the in-place buffer of Q15 data type. + * @param[in] fftLen length of the FFT. + * @param[in] *pCoef16 points to twiddle coefficient buffer. + * @param[in] twidCoefModifier twiddle coefficient modifier that supports different size FFTs with the same twiddle factor table. + * @return none. + */ + + void arm_radix4_butterfly_q15( + q15_t * pSrc16, + uint32_t fftLen, + q15_t * pCoef16, + uint32_t twidCoefModifier); + + + /** + * @brief Core function for the Q15 CIFFT butterfly process. + * @param[in, out] *pSrc16 points to the in-place buffer of Q15 data type. + * @param[in] fftLen length of the FFT. + * @param[in] *pCoef16 points to twiddle coefficient buffer. + * @param[in] twidCoefModifier twiddle coefficient modifier that supports different size FFTs with the same twiddle factor table. + * @return none. + */ + + void arm_radix4_butterfly_inverse_q15( + q15_t * pSrc16, + uint32_t fftLen, + q15_t * pCoef16, + uint32_t twidCoefModifier); + + /** + * @brief In-place bit reversal function. + * @param[in, out] *pSrc points to the in-place buffer of Q15 data type. + * @param[in] fftLen length of the FFT. + * @param[in] bitRevFactor bit reversal modifier that supports different size FFTs with the same bit reversal table + * @param[in] *pBitRevTab points to bit reversal table. + * @return none. + */ + + void arm_bitreversal_q15( + q15_t * pSrc, + uint32_t fftLen, + uint16_t bitRevFactor, + uint16_t * pBitRevTab); + + + /** + * @brief Instance structure for the Q15 RFFT/RIFFT function. + */ + + typedef struct + { + uint32_t fftLenReal; /**< length of the real FFT. */ + uint32_t fftLenBy2; /**< length of the complex FFT. */ + uint8_t ifftFlagR; /**< flag that selects forward (ifftFlagR=0) or inverse (ifftFlagR=1) transform. */ + uint8_t bitReverseFlagR; /**< flag that enables (bitReverseFlagR=1) or disables (bitReverseFlagR=0) bit reversal of output. */ + uint32_t twidCoefRModifier; /**< twiddle coefficient modifier that supports different size FFTs with the same twiddle factor table. */ + q15_t *pTwiddleAReal; /**< points to the real twiddle factor table. */ + q15_t *pTwiddleBReal; /**< points to the imag twiddle factor table. */ + arm_cfft_radix4_instance_q15 *pCfft; /**< points to the complex FFT instance. */ + } arm_rfft_instance_q15; + + /** + * @brief Instance structure for the Q31 RFFT/RIFFT function. + */ + + typedef struct + { + uint32_t fftLenReal; /**< length of the real FFT. */ + uint32_t fftLenBy2; /**< length of the complex FFT. */ + uint8_t ifftFlagR; /**< flag that selects forward (ifftFlagR=0) or inverse (ifftFlagR=1) transform. */ + uint8_t bitReverseFlagR; /**< flag that enables (bitReverseFlagR=1) or disables (bitReverseFlagR=0) bit reversal of output. */ + uint32_t twidCoefRModifier; /**< twiddle coefficient modifier that supports different size FFTs with the same twiddle factor table. */ + q31_t *pTwiddleAReal; /**< points to the real twiddle factor table. */ + q31_t *pTwiddleBReal; /**< points to the imag twiddle factor table. */ + arm_cfft_radix4_instance_q31 *pCfft; /**< points to the complex FFT instance. */ + } arm_rfft_instance_q31; + + /** + * @brief Instance structure for the floating-point RFFT/RIFFT function. + */ + + typedef struct + { + uint32_t fftLenReal; /**< length of the real FFT. */ + uint16_t fftLenBy2; /**< length of the complex FFT. */ + uint8_t ifftFlagR; /**< flag that selects forward (ifftFlagR=0) or inverse (ifftFlagR=1) transform. */ + uint8_t bitReverseFlagR; /**< flag that enables (bitReverseFlagR=1) or disables (bitReverseFlagR=0) bit reversal of output. */ + uint32_t twidCoefRModifier; /**< twiddle coefficient modifier that supports different size FFTs with the same twiddle factor table. */ + float32_t *pTwiddleAReal; /**< points to the real twiddle factor table. */ + float32_t *pTwiddleBReal; /**< points to the imag twiddle factor table. */ + arm_cfft_radix4_instance_f32 *pCfft; /**< points to the complex FFT instance. */ + } arm_rfft_instance_f32; + + /** + * @brief Processing function for the Q15 RFFT/RIFFT. + * @param[in] *S points to an instance of the Q15 RFFT/RIFFT structure. + * @param[in] *pSrc points to the input buffer. + * @param[out] *pDst points to the output buffer. + * @return none. + */ + + void arm_rfft_q15( + const arm_rfft_instance_q15 * S, + q15_t * pSrc, + q15_t * pDst); + + /** + * @brief Initialization function for the Q15 RFFT/RIFFT. + * @param[in, out] *S points to an instance of the Q15 RFFT/RIFFT structure. + * @param[in] *S_CFFT points to an instance of the Q15 CFFT/CIFFT structure. + * @param[in] fftLenReal length of the FFT. + * @param[in] ifftFlagR flag that selects forward (ifftFlagR=0) or inverse (ifftFlagR=1) transform. + * @param[in] bitReverseFlag flag that enables (bitReverseFlag=1) or disables (bitReverseFlag=0) bit reversal of output. + * @return The function returns ARM_MATH_SUCCESS if initialization is successful or ARM_MATH_ARGUMENT_ERROR if fftLenReal is not a supported value. + */ + + arm_status arm_rfft_init_q15( + arm_rfft_instance_q15 * S, + arm_cfft_radix4_instance_q15 * S_CFFT, + uint32_t fftLenReal, + uint32_t ifftFlagR, + uint32_t bitReverseFlag); + + /** + * @brief Processing function for the Q31 RFFT/RIFFT. + * @param[in] *S points to an instance of the Q31 RFFT/RIFFT structure. + * @param[in] *pSrc points to the input buffer. + * @param[out] *pDst points to the output buffer. + * @return none. + */ + + void arm_rfft_q31( + const arm_rfft_instance_q31 * S, + q31_t * pSrc, + q31_t * pDst); + + /** + * @brief Initialization function for the Q31 RFFT/RIFFT. + * @param[in, out] *S points to an instance of the Q31 RFFT/RIFFT structure. + * @param[in, out] *S_CFFT points to an instance of the Q31 CFFT/CIFFT structure. + * @param[in] fftLenReal length of the FFT. + * @param[in] ifftFlagR flag that selects forward (ifftFlagR=0) or inverse (ifftFlagR=1) transform. + * @param[in] bitReverseFlag flag that enables (bitReverseFlag=1) or disables (bitReverseFlag=0) bit reversal of output. + * @return The function returns ARM_MATH_SUCCESS if initialization is successful or ARM_MATH_ARGUMENT_ERROR if fftLenReal is not a supported value. + */ + + arm_status arm_rfft_init_q31( + arm_rfft_instance_q31 * S, + arm_cfft_radix4_instance_q31 * S_CFFT, + uint32_t fftLenReal, + uint32_t ifftFlagR, + uint32_t bitReverseFlag); + + /** + * @brief Initialization function for the floating-point RFFT/RIFFT. + * @param[in,out] *S points to an instance of the floating-point RFFT/RIFFT structure. + * @param[in,out] *S_CFFT points to an instance of the floating-point CFFT/CIFFT structure. + * @param[in] fftLenReal length of the FFT. + * @param[in] ifftFlagR flag that selects forward (ifftFlagR=0) or inverse (ifftFlagR=1) transform. + * @param[in] bitReverseFlag flag that enables (bitReverseFlag=1) or disables (bitReverseFlag=0) bit reversal of output. + * @return The function returns ARM_MATH_SUCCESS if initialization is successful or ARM_MATH_ARGUMENT_ERROR if fftLenReal is not a supported value. + */ + + arm_status arm_rfft_init_f32( + arm_rfft_instance_f32 * S, + arm_cfft_radix4_instance_f32 * S_CFFT, + uint32_t fftLenReal, + uint32_t ifftFlagR, + uint32_t bitReverseFlag); + + /** + * @brief Processing function for the floating-point RFFT/RIFFT. + * @param[in] *S points to an instance of the floating-point RFFT/RIFFT structure. + * @param[in] *pSrc points to the input buffer. + * @param[out] *pDst points to the output buffer. + * @return none. + */ + + void arm_rfft_f32( + const arm_rfft_instance_f32 * S, + float32_t * pSrc, + float32_t * pDst); + + /** + * @brief Instance structure for the floating-point DCT4/IDCT4 function. + */ + + typedef struct + { + uint16_t N; /**< length of the DCT4. */ + uint16_t Nby2; /**< half of the length of the DCT4. */ + float32_t normalize; /**< normalizing factor. */ + float32_t *pTwiddle; /**< points to the twiddle factor table. */ + float32_t *pCosFactor; /**< points to the cosFactor table. */ + arm_rfft_instance_f32 *pRfft; /**< points to the real FFT instance. */ + arm_cfft_radix4_instance_f32 *pCfft; /**< points to the complex FFT instance. */ + } arm_dct4_instance_f32; + + /** + * @brief Initialization function for the floating-point DCT4/IDCT4. + * @param[in,out] *S points to an instance of floating-point DCT4/IDCT4 structure. + * @param[in] *S_RFFT points to an instance of floating-point RFFT/RIFFT structure. + * @param[in] *S_CFFT points to an instance of floating-point CFFT/CIFFT structure. + * @param[in] N length of the DCT4. + * @param[in] Nby2 half of the length of the DCT4. + * @param[in] normalize normalizing factor. + * @return arm_status function returns ARM_MATH_SUCCESS if initialization is successful or ARM_MATH_ARGUMENT_ERROR if fftLenReal is not a supported transform length. + */ + + arm_status arm_dct4_init_f32( + arm_dct4_instance_f32 * S, + arm_rfft_instance_f32 * S_RFFT, + arm_cfft_radix4_instance_f32 * S_CFFT, + uint16_t N, + uint16_t Nby2, + float32_t normalize); + + /** + * @brief Processing function for the floating-point DCT4/IDCT4. + * @param[in] *S points to an instance of the floating-point DCT4/IDCT4 structure. + * @param[in] *pState points to state buffer. + * @param[in,out] *pInlineBuffer points to the in-place input and output buffer. + * @return none. + */ + + void arm_dct4_f32( + const arm_dct4_instance_f32 * S, + float32_t * pState, + float32_t * pInlineBuffer); + + /** + * @brief Instance structure for the Q31 DCT4/IDCT4 function. + */ + + typedef struct + { + uint16_t N; /**< length of the DCT4. */ + uint16_t Nby2; /**< half of the length of the DCT4. */ + q31_t normalize; /**< normalizing factor. */ + q31_t *pTwiddle; /**< points to the twiddle factor table. */ + q31_t *pCosFactor; /**< points to the cosFactor table. */ + arm_rfft_instance_q31 *pRfft; /**< points to the real FFT instance. */ + arm_cfft_radix4_instance_q31 *pCfft; /**< points to the complex FFT instance. */ + } arm_dct4_instance_q31; + + /** + * @brief Initialization function for the Q31 DCT4/IDCT4. + * @param[in,out] *S points to an instance of Q31 DCT4/IDCT4 structure. + * @param[in] *S_RFFT points to an instance of Q31 RFFT/RIFFT structure + * @param[in] *S_CFFT points to an instance of Q31 CFFT/CIFFT structure + * @param[in] N length of the DCT4. + * @param[in] Nby2 half of the length of the DCT4. + * @param[in] normalize normalizing factor. + * @return arm_status function returns ARM_MATH_SUCCESS if initialization is successful or ARM_MATH_ARGUMENT_ERROR if N is not a supported transform length. + */ + + arm_status arm_dct4_init_q31( + arm_dct4_instance_q31 * S, + arm_rfft_instance_q31 * S_RFFT, + arm_cfft_radix4_instance_q31 * S_CFFT, + uint16_t N, + uint16_t Nby2, + q31_t normalize); + + /** + * @brief Processing function for the Q31 DCT4/IDCT4. + * @param[in] *S points to an instance of the Q31 DCT4 structure. + * @param[in] *pState points to state buffer. + * @param[in,out] *pInlineBuffer points to the in-place input and output buffer. + * @return none. + */ + + void arm_dct4_q31( + const arm_dct4_instance_q31 * S, + q31_t * pState, + q31_t * pInlineBuffer); + + /** + * @brief Instance structure for the Q15 DCT4/IDCT4 function. + */ + + typedef struct + { + uint16_t N; /**< length of the DCT4. */ + uint16_t Nby2; /**< half of the length of the DCT4. */ + q15_t normalize; /**< normalizing factor. */ + q15_t *pTwiddle; /**< points to the twiddle factor table. */ + q15_t *pCosFactor; /**< points to the cosFactor table. */ + arm_rfft_instance_q15 *pRfft; /**< points to the real FFT instance. */ + arm_cfft_radix4_instance_q15 *pCfft; /**< points to the complex FFT instance. */ + } arm_dct4_instance_q15; + + /** + * @brief Initialization function for the Q15 DCT4/IDCT4. + * @param[in,out] *S points to an instance of Q15 DCT4/IDCT4 structure. + * @param[in] *S_RFFT points to an instance of Q15 RFFT/RIFFT structure. + * @param[in] *S_CFFT points to an instance of Q15 CFFT/CIFFT structure. + * @param[in] N length of the DCT4. + * @param[in] Nby2 half of the length of the DCT4. + * @param[in] normalize normalizing factor. + * @return arm_status function returns ARM_MATH_SUCCESS if initialization is successful or ARM_MATH_ARGUMENT_ERROR if N is not a supported transform length. + */ + + arm_status arm_dct4_init_q15( + arm_dct4_instance_q15 * S, + arm_rfft_instance_q15 * S_RFFT, + arm_cfft_radix4_instance_q15 * S_CFFT, + uint16_t N, + uint16_t Nby2, + q15_t normalize); + + /** + * @brief Processing function for the Q15 DCT4/IDCT4. + * @param[in] *S points to an instance of the Q15 DCT4 structure. + * @param[in] *pState points to state buffer. + * @param[in,out] *pInlineBuffer points to the in-place input and output buffer. + * @return none. + */ + + void arm_dct4_q15( + const arm_dct4_instance_q15 * S, + q15_t * pState, + q15_t * pInlineBuffer); + + /** + * @brief Floating-point vector addition. + * @param[in] *pSrcA points to the first input vector + * @param[in] *pSrcB points to the second input vector + * @param[out] *pDst points to the output vector + * @param[in] blockSize number of samples in each vector + * @return none. + */ + + void arm_add_f32( + float32_t * pSrcA, + float32_t * pSrcB, + float32_t * pDst, + uint32_t blockSize); + + /** + * @brief Q7 vector addition. + * @param[in] *pSrcA points to the first input vector + * @param[in] *pSrcB points to the second input vector + * @param[out] *pDst points to the output vector + * @param[in] blockSize number of samples in each vector + * @return none. + */ + + void arm_add_q7( + q7_t * pSrcA, + q7_t * pSrcB, + q7_t * pDst, + uint32_t blockSize); + + /** + * @brief Q15 vector addition. + * @param[in] *pSrcA points to the first input vector + * @param[in] *pSrcB points to the second input vector + * @param[out] *pDst points to the output vector + * @param[in] blockSize number of samples in each vector + * @return none. + */ + + void arm_add_q15( + q15_t * pSrcA, + q15_t * pSrcB, + q15_t * pDst, + uint32_t blockSize); + + /** + * @brief Q31 vector addition. + * @param[in] *pSrcA points to the first input vector + * @param[in] *pSrcB points to the second input vector + * @param[out] *pDst points to the output vector + * @param[in] blockSize number of samples in each vector + * @return none. + */ + + void arm_add_q31( + q31_t * pSrcA, + q31_t * pSrcB, + q31_t * pDst, + uint32_t blockSize); + + /** + * @brief Floating-point vector subtraction. + * @param[in] *pSrcA points to the first input vector + * @param[in] *pSrcB points to the second input vector + * @param[out] *pDst points to the output vector + * @param[in] blockSize number of samples in each vector + * @return none. + */ + + void arm_sub_f32( + float32_t * pSrcA, + float32_t * pSrcB, + float32_t * pDst, + uint32_t blockSize); + + /** + * @brief Q7 vector subtraction. + * @param[in] *pSrcA points to the first input vector + * @param[in] *pSrcB points to the second input vector + * @param[out] *pDst points to the output vector + * @param[in] blockSize number of samples in each vector + * @return none. + */ + + void arm_sub_q7( + q7_t * pSrcA, + q7_t * pSrcB, + q7_t * pDst, + uint32_t blockSize); + + /** + * @brief Q15 vector subtraction. + * @param[in] *pSrcA points to the first input vector + * @param[in] *pSrcB points to the second input vector + * @param[out] *pDst points to the output vector + * @param[in] blockSize number of samples in each vector + * @return none. + */ + + void arm_sub_q15( + q15_t * pSrcA, + q15_t * pSrcB, + q15_t * pDst, + uint32_t blockSize); + + /** + * @brief Q31 vector subtraction. + * @param[in] *pSrcA points to the first input vector + * @param[in] *pSrcB points to the second input vector + * @param[out] *pDst points to the output vector + * @param[in] blockSize number of samples in each vector + * @return none. + */ + + void arm_sub_q31( + q31_t * pSrcA, + q31_t * pSrcB, + q31_t * pDst, + uint32_t blockSize); + + /** + * @brief Multiplies a floating-point vector by a scalar. + * @param[in] *pSrc points to the input vector + * @param[in] scale scale factor to be applied + * @param[out] *pDst points to the output vector + * @param[in] blockSize number of samples in the vector + * @return none. + */ + + void arm_scale_f32( + float32_t * pSrc, + float32_t scale, + float32_t * pDst, + uint32_t blockSize); + + /** + * @brief Multiplies a Q7 vector by a scalar. + * @param[in] *pSrc points to the input vector + * @param[in] scaleFract fractional portion of the scale value + * @param[in] shift number of bits to shift the result by + * @param[out] *pDst points to the output vector + * @param[in] blockSize number of samples in the vector + * @return none. + */ + + void arm_scale_q7( + q7_t * pSrc, + q7_t scaleFract, + int8_t shift, + q7_t * pDst, + uint32_t blockSize); + + /** + * @brief Multiplies a Q15 vector by a scalar. + * @param[in] *pSrc points to the input vector + * @param[in] scaleFract fractional portion of the scale value + * @param[in] shift number of bits to shift the result by + * @param[out] *pDst points to the output vector + * @param[in] blockSize number of samples in the vector + * @return none. + */ + + void arm_scale_q15( + q15_t * pSrc, + q15_t scaleFract, + int8_t shift, + q15_t * pDst, + uint32_t blockSize); + + /** + * @brief Multiplies a Q31 vector by a scalar. + * @param[in] *pSrc points to the input vector + * @param[in] scaleFract fractional portion of the scale value + * @param[in] shift number of bits to shift the result by + * @param[out] *pDst points to the output vector + * @param[in] blockSize number of samples in the vector + * @return none. + */ + + void arm_scale_q31( + q31_t * pSrc, + q31_t scaleFract, + int8_t shift, + q31_t * pDst, + uint32_t blockSize); + + /** + * @brief Q7 vector absolute value. + * @param[in] *pSrc points to the input buffer + * @param[out] *pDst points to the output buffer + * @param[in] blockSize number of samples in each vector + * @return none. + */ + + void arm_abs_q7( + q7_t * pSrc, + q7_t * pDst, + uint32_t blockSize); + + /** + * @brief Floating-point vector absolute value. + * @param[in] *pSrc points to the input buffer + * @param[out] *pDst points to the output buffer + * @param[in] blockSize number of samples in each vector + * @return none. + */ + + void arm_abs_f32( + float32_t * pSrc, + float32_t * pDst, + uint32_t blockSize); + + /** + * @brief Q15 vector absolute value. + * @param[in] *pSrc points to the input buffer + * @param[out] *pDst points to the output buffer + * @param[in] blockSize number of samples in each vector + * @return none. + */ + + void arm_abs_q15( + q15_t * pSrc, + q15_t * pDst, + uint32_t blockSize); + + /** + * @brief Q31 vector absolute value. + * @param[in] *pSrc points to the input buffer + * @param[out] *pDst points to the output buffer + * @param[in] blockSize number of samples in each vector + * @return none. + */ + + void arm_abs_q31( + q31_t * pSrc, + q31_t * pDst, + uint32_t blockSize); + + /** + * @brief Dot product of floating-point vectors. + * @param[in] *pSrcA points to the first input vector + * @param[in] *pSrcB points to the second input vector + * @param[in] blockSize number of samples in each vector + * @param[out] *result output result returned here + * @return none. + */ + + void arm_dot_prod_f32( + float32_t * pSrcA, + float32_t * pSrcB, + uint32_t blockSize, + float32_t * result); + + /** + * @brief Dot product of Q7 vectors. + * @param[in] *pSrcA points to the first input vector + * @param[in] *pSrcB points to the second input vector + * @param[in] blockSize number of samples in each vector + * @param[out] *result output result returned here + * @return none. + */ + + void arm_dot_prod_q7( + q7_t * pSrcA, + q7_t * pSrcB, + uint32_t blockSize, + q31_t * result); + + /** + * @brief Dot product of Q15 vectors. + * @param[in] *pSrcA points to the first input vector + * @param[in] *pSrcB points to the second input vector + * @param[in] blockSize number of samples in each vector + * @param[out] *result output result returned here + * @return none. + */ + + void arm_dot_prod_q15( + q15_t * pSrcA, + q15_t * pSrcB, + uint32_t blockSize, + q63_t * result); + + /** + * @brief Dot product of Q31 vectors. + * @param[in] *pSrcA points to the first input vector + * @param[in] *pSrcB points to the second input vector + * @param[in] blockSize number of samples in each vector + * @param[out] *result output result returned here + * @return none. + */ + + void arm_dot_prod_q31( + q31_t * pSrcA, + q31_t * pSrcB, + uint32_t blockSize, + q63_t * result); + + /** + * @brief Shifts the elements of a Q7 vector a specified number of bits. + * @param[in] *pSrc points to the input vector + * @param[in] shiftBits number of bits to shift. A positive value shifts left; a negative value shifts right. + * @param[out] *pDst points to the output vector + * @param[in] blockSize number of samples in the vector + * @return none. + */ + + void arm_shift_q7( + q7_t * pSrc, + int8_t shiftBits, + q7_t * pDst, + uint32_t blockSize); + + /** + * @brief Shifts the elements of a Q15 vector a specified number of bits. + * @param[in] *pSrc points to the input vector + * @param[in] shiftBits number of bits to shift. A positive value shifts left; a negative value shifts right. + * @param[out] *pDst points to the output vector + * @param[in] blockSize number of samples in the vector + * @return none. + */ + + void arm_shift_q15( + q15_t * pSrc, + int8_t shiftBits, + q15_t * pDst, + uint32_t blockSize); + + /** + * @brief Shifts the elements of a Q31 vector a specified number of bits. + * @param[in] *pSrc points to the input vector + * @param[in] shiftBits number of bits to shift. A positive value shifts left; a negative value shifts right. + * @param[out] *pDst points to the output vector + * @param[in] blockSize number of samples in the vector + * @return none. + */ + + void arm_shift_q31( + q31_t * pSrc, + int8_t shiftBits, + q31_t * pDst, + uint32_t blockSize); + + /** + * @brief Adds a constant offset to a floating-point vector. + * @param[in] *pSrc points to the input vector + * @param[in] offset is the offset to be added + * @param[out] *pDst points to the output vector + * @param[in] blockSize number of samples in the vector + * @return none. + */ + + void arm_offset_f32( + float32_t * pSrc, + float32_t offset, + float32_t * pDst, + uint32_t blockSize); + + /** + * @brief Adds a constant offset to a Q7 vector. + * @param[in] *pSrc points to the input vector + * @param[in] offset is the offset to be added + * @param[out] *pDst points to the output vector + * @param[in] blockSize number of samples in the vector + * @return none. + */ + + void arm_offset_q7( + q7_t * pSrc, + q7_t offset, + q7_t * pDst, + uint32_t blockSize); + + /** + * @brief Adds a constant offset to a Q15 vector. + * @param[in] *pSrc points to the input vector + * @param[in] offset is the offset to be added + * @param[out] *pDst points to the output vector + * @param[in] blockSize number of samples in the vector + * @return none. + */ + + void arm_offset_q15( + q15_t * pSrc, + q15_t offset, + q15_t * pDst, + uint32_t blockSize); + + /** + * @brief Adds a constant offset to a Q31 vector. + * @param[in] *pSrc points to the input vector + * @param[in] offset is the offset to be added + * @param[out] *pDst points to the output vector + * @param[in] blockSize number of samples in the vector + * @return none. + */ + + void arm_offset_q31( + q31_t * pSrc, + q31_t offset, + q31_t * pDst, + uint32_t blockSize); + + /** + * @brief Negates the elements of a floating-point vector. + * @param[in] *pSrc points to the input vector + * @param[out] *pDst points to the output vector + * @param[in] blockSize number of samples in the vector + * @return none. + */ + + void arm_negate_f32( + float32_t * pSrc, + float32_t * pDst, + uint32_t blockSize); + + /** + * @brief Negates the elements of a Q7 vector. + * @param[in] *pSrc points to the input vector + * @param[out] *pDst points to the output vector + * @param[in] blockSize number of samples in the vector + * @return none. + */ + + void arm_negate_q7( + q7_t * pSrc, + q7_t * pDst, + uint32_t blockSize); + + /** + * @brief Negates the elements of a Q15 vector. + * @param[in] *pSrc points to the input vector + * @param[out] *pDst points to the output vector + * @param[in] blockSize number of samples in the vector + * @return none. + */ + + void arm_negate_q15( + q15_t * pSrc, + q15_t * pDst, + uint32_t blockSize); + + /** + * @brief Negates the elements of a Q31 vector. + * @param[in] *pSrc points to the input vector + * @param[out] *pDst points to the output vector + * @param[in] blockSize number of samples in the vector + * @return none. + */ + + void arm_negate_q31( + q31_t * pSrc, + q31_t * pDst, + uint32_t blockSize); + /** + * @brief Copies the elements of a floating-point vector. + * @param[in] *pSrc input pointer + * @param[out] *pDst output pointer + * @param[in] blockSize number of samples to process + * @return none. + */ + void arm_copy_f32( + float32_t * pSrc, + float32_t * pDst, + uint32_t blockSize); + + /** + * @brief Copies the elements of a Q7 vector. + * @param[in] *pSrc input pointer + * @param[out] *pDst output pointer + * @param[in] blockSize number of samples to process + * @return none. + */ + void arm_copy_q7( + q7_t * pSrc, + q7_t * pDst, + uint32_t blockSize); + + /** + * @brief Copies the elements of a Q15 vector. + * @param[in] *pSrc input pointer + * @param[out] *pDst output pointer + * @param[in] blockSize number of samples to process + * @return none. + */ + void arm_copy_q15( + q15_t * pSrc, + q15_t * pDst, + uint32_t blockSize); + + /** + * @brief Copies the elements of a Q31 vector. + * @param[in] *pSrc input pointer + * @param[out] *pDst output pointer + * @param[in] blockSize number of samples to process + * @return none. + */ + void arm_copy_q31( + q31_t * pSrc, + q31_t * pDst, + uint32_t blockSize); + /** + * @brief Fills a constant value into a floating-point vector. + * @param[in] value input value to be filled + * @param[out] *pDst output pointer + * @param[in] blockSize number of samples to process + * @return none. + */ + void arm_fill_f32( + float32_t value, + float32_t * pDst, + uint32_t blockSize); + + /** + * @brief Fills a constant value into a Q7 vector. + * @param[in] value input value to be filled + * @param[out] *pDst output pointer + * @param[in] blockSize number of samples to process + * @return none. + */ + void arm_fill_q7( + q7_t value, + q7_t * pDst, + uint32_t blockSize); + + /** + * @brief Fills a constant value into a Q15 vector. + * @param[in] value input value to be filled + * @param[out] *pDst output pointer + * @param[in] blockSize number of samples to process + * @return none. + */ + void arm_fill_q15( + q15_t value, + q15_t * pDst, + uint32_t blockSize); + + /** + * @brief Fills a constant value into a Q31 vector. + * @param[in] value input value to be filled + * @param[out] *pDst output pointer + * @param[in] blockSize number of samples to process + * @return none. + */ + void arm_fill_q31( + q31_t value, + q31_t * pDst, + uint32_t blockSize); + +/** + * @brief Convolution of floating-point sequences. + * @param[in] *pSrcA points to the first input sequence. + * @param[in] srcALen length of the first input sequence. + * @param[in] *pSrcB points to the second input sequence. + * @param[in] srcBLen length of the second input sequence. + * @param[out] *pDst points to the location where the output result is written. Length srcALen+srcBLen-1. + * @return none. + */ + + void arm_conv_f32( + float32_t * pSrcA, + uint32_t srcALen, + float32_t * pSrcB, + uint32_t srcBLen, + float32_t * pDst); + + + /** + * @brief Convolution of Q15 sequences. + * @param[in] *pSrcA points to the first input sequence. + * @param[in] srcALen length of the first input sequence. + * @param[in] *pSrcB points to the second input sequence. + * @param[in] srcBLen length of the second input sequence. + * @param[out] *pDst points to the block of output data Length srcALen+srcBLen-1. + * @param[in] *pScratch1 points to scratch buffer of size max(srcALen, srcBLen) + 2*min(srcALen, srcBLen) - 2. + * @param[in] *pScratch2 points to scratch buffer of size min(srcALen, srcBLen). + * @return none. + */ + + + void arm_conv_opt_q15( + q15_t * pSrcA, + uint32_t srcALen, + q15_t * pSrcB, + uint32_t srcBLen, + q15_t * pDst, + q15_t * pScratch1, + q15_t * pScratch2); + + +/** + * @brief Convolution of Q15 sequences. + * @param[in] *pSrcA points to the first input sequence. + * @param[in] srcALen length of the first input sequence. + * @param[in] *pSrcB points to the second input sequence. + * @param[in] srcBLen length of the second input sequence. + * @param[out] *pDst points to the location where the output result is written. Length srcALen+srcBLen-1. + * @return none. + */ + + void arm_conv_q15( + q15_t * pSrcA, + uint32_t srcALen, + q15_t * pSrcB, + uint32_t srcBLen, + q15_t * pDst); + + /** + * @brief Convolution of Q15 sequences (fast version) for Cortex-M3 and Cortex-M4 + * @param[in] *pSrcA points to the first input sequence. + * @param[in] srcALen length of the first input sequence. + * @param[in] *pSrcB points to the second input sequence. + * @param[in] srcBLen length of the second input sequence. + * @param[out] *pDst points to the block of output data Length srcALen+srcBLen-1. + * @return none. + */ + + void arm_conv_fast_q15( + q15_t * pSrcA, + uint32_t srcALen, + q15_t * pSrcB, + uint32_t srcBLen, + q15_t * pDst); + + /** + * @brief Convolution of Q15 sequences (fast version) for Cortex-M3 and Cortex-M4 + * @param[in] *pSrcA points to the first input sequence. + * @param[in] srcALen length of the first input sequence. + * @param[in] *pSrcB points to the second input sequence. + * @param[in] srcBLen length of the second input sequence. + * @param[out] *pDst points to the block of output data Length srcALen+srcBLen-1. + * @param[in] *pScratch1 points to scratch buffer of size max(srcALen, srcBLen) + 2*min(srcALen, srcBLen) - 2. + * @param[in] *pScratch2 points to scratch buffer of size min(srcALen, srcBLen). + * @return none. + */ + + void arm_conv_fast_opt_q15( + q15_t * pSrcA, + uint32_t srcALen, + q15_t * pSrcB, + uint32_t srcBLen, + q15_t * pDst, + q15_t * pScratch1, + q15_t * pScratch2); + + + + /** + * @brief Convolution of Q31 sequences. + * @param[in] *pSrcA points to the first input sequence. + * @param[in] srcALen length of the first input sequence. + * @param[in] *pSrcB points to the second input sequence. + * @param[in] srcBLen length of the second input sequence. + * @param[out] *pDst points to the block of output data Length srcALen+srcBLen-1. + * @return none. + */ + + void arm_conv_q31( + q31_t * pSrcA, + uint32_t srcALen, + q31_t * pSrcB, + uint32_t srcBLen, + q31_t * pDst); + + /** + * @brief Convolution of Q31 sequences (fast version) for Cortex-M3 and Cortex-M4 + * @param[in] *pSrcA points to the first input sequence. + * @param[in] srcALen length of the first input sequence. + * @param[in] *pSrcB points to the second input sequence. + * @param[in] srcBLen length of the second input sequence. + * @param[out] *pDst points to the block of output data Length srcALen+srcBLen-1. + * @return none. + */ + + void arm_conv_fast_q31( + q31_t * pSrcA, + uint32_t srcALen, + q31_t * pSrcB, + uint32_t srcBLen, + q31_t * pDst); + + + /** + * @brief Convolution of Q7 sequences. + * @param[in] *pSrcA points to the first input sequence. + * @param[in] srcALen length of the first input sequence. + * @param[in] *pSrcB points to the second input sequence. + * @param[in] srcBLen length of the second input sequence. + * @param[out] *pDst points to the block of output data Length srcALen+srcBLen-1. + * @param[in] *pScratch1 points to scratch buffer(of type q15_t) of size max(srcALen, srcBLen) + 2*min(srcALen, srcBLen) - 2. + * @param[in] *pScratch2 points to scratch buffer (of type q15_t) of size min(srcALen, srcBLen). + * @return none. + */ + + void arm_conv_opt_q7( + q7_t * pSrcA, + uint32_t srcALen, + q7_t * pSrcB, + uint32_t srcBLen, + q7_t * pDst, + q15_t * pScratch1, + q15_t * pScratch2); + + + + /** + * @brief Convolution of Q7 sequences. + * @param[in] *pSrcA points to the first input sequence. + * @param[in] srcALen length of the first input sequence. + * @param[in] *pSrcB points to the second input sequence. + * @param[in] srcBLen length of the second input sequence. + * @param[out] *pDst points to the block of output data Length srcALen+srcBLen-1. + * @return none. + */ + + void arm_conv_q7( + q7_t * pSrcA, + uint32_t srcALen, + q7_t * pSrcB, + uint32_t srcBLen, + q7_t * pDst); + + + /** + * @brief Partial convolution of floating-point sequences. + * @param[in] *pSrcA points to the first input sequence. + * @param[in] srcALen length of the first input sequence. + * @param[in] *pSrcB points to the second input sequence. + * @param[in] srcBLen length of the second input sequence. + * @param[out] *pDst points to the block of output data + * @param[in] firstIndex is the first output sample to start with. + * @param[in] numPoints is the number of output points to be computed. + * @return Returns either ARM_MATH_SUCCESS if the function completed correctly or ARM_MATH_ARGUMENT_ERROR if the requested subset is not in the range [0 srcALen+srcBLen-2]. + */ + + arm_status arm_conv_partial_f32( + float32_t * pSrcA, + uint32_t srcALen, + float32_t * pSrcB, + uint32_t srcBLen, + float32_t * pDst, + uint32_t firstIndex, + uint32_t numPoints); + + /** + * @brief Partial convolution of Q15 sequences. + * @param[in] *pSrcA points to the first input sequence. + * @param[in] srcALen length of the first input sequence. + * @param[in] *pSrcB points to the second input sequence. + * @param[in] srcBLen length of the second input sequence. + * @param[out] *pDst points to the block of output data + * @param[in] firstIndex is the first output sample to start with. + * @param[in] numPoints is the number of output points to be computed. + * @param[in] * pScratch1 points to scratch buffer of size max(srcALen, srcBLen) + 2*min(srcALen, srcBLen) - 2. + * @param[in] * pScratch2 points to scratch buffer of size min(srcALen, srcBLen). + * @return Returns either ARM_MATH_SUCCESS if the function completed correctly or ARM_MATH_ARGUMENT_ERROR if the requested subset is not in the range [0 srcALen+srcBLen-2]. + */ + + arm_status arm_conv_partial_opt_q15( + q15_t * pSrcA, + uint32_t srcALen, + q15_t * pSrcB, + uint32_t srcBLen, + q15_t * pDst, + uint32_t firstIndex, + uint32_t numPoints, + q15_t * pScratch1, + q15_t * pScratch2); + + +/** + * @brief Partial convolution of Q15 sequences. + * @param[in] *pSrcA points to the first input sequence. + * @param[in] srcALen length of the first input sequence. + * @param[in] *pSrcB points to the second input sequence. + * @param[in] srcBLen length of the second input sequence. + * @param[out] *pDst points to the block of output data + * @param[in] firstIndex is the first output sample to start with. + * @param[in] numPoints is the number of output points to be computed. + * @return Returns either ARM_MATH_SUCCESS if the function completed correctly or ARM_MATH_ARGUMENT_ERROR if the requested subset is not in the range [0 srcALen+srcBLen-2]. + */ + + arm_status arm_conv_partial_q15( + q15_t * pSrcA, + uint32_t srcALen, + q15_t * pSrcB, + uint32_t srcBLen, + q15_t * pDst, + uint32_t firstIndex, + uint32_t numPoints); + + /** + * @brief Partial convolution of Q15 sequences (fast version) for Cortex-M3 and Cortex-M4 + * @param[in] *pSrcA points to the first input sequence. + * @param[in] srcALen length of the first input sequence. + * @param[in] *pSrcB points to the second input sequence. + * @param[in] srcBLen length of the second input sequence. + * @param[out] *pDst points to the block of output data + * @param[in] firstIndex is the first output sample to start with. + * @param[in] numPoints is the number of output points to be computed. + * @return Returns either ARM_MATH_SUCCESS if the function completed correctly or ARM_MATH_ARGUMENT_ERROR if the requested subset is not in the range [0 srcALen+srcBLen-2]. + */ + + arm_status arm_conv_partial_fast_q15( + q15_t * pSrcA, + uint32_t srcALen, + q15_t * pSrcB, + uint32_t srcBLen, + q15_t * pDst, + uint32_t firstIndex, + uint32_t numPoints); + + + /** + * @brief Partial convolution of Q15 sequences (fast version) for Cortex-M3 and Cortex-M4 + * @param[in] *pSrcA points to the first input sequence. + * @param[in] srcALen length of the first input sequence. + * @param[in] *pSrcB points to the second input sequence. + * @param[in] srcBLen length of the second input sequence. + * @param[out] *pDst points to the block of output data + * @param[in] firstIndex is the first output sample to start with. + * @param[in] numPoints is the number of output points to be computed. + * @param[in] * pScratch1 points to scratch buffer of size max(srcALen, srcBLen) + 2*min(srcALen, srcBLen) - 2. + * @param[in] * pScratch2 points to scratch buffer of size min(srcALen, srcBLen). + * @return Returns either ARM_MATH_SUCCESS if the function completed correctly or ARM_MATH_ARGUMENT_ERROR if the requested subset is not in the range [0 srcALen+srcBLen-2]. + */ + + arm_status arm_conv_partial_fast_opt_q15( + q15_t * pSrcA, + uint32_t srcALen, + q15_t * pSrcB, + uint32_t srcBLen, + q15_t * pDst, + uint32_t firstIndex, + uint32_t numPoints, + q15_t * pScratch1, + q15_t * pScratch2); + + + /** + * @brief Partial convolution of Q31 sequences. + * @param[in] *pSrcA points to the first input sequence. + * @param[in] srcALen length of the first input sequence. + * @param[in] *pSrcB points to the second input sequence. + * @param[in] srcBLen length of the second input sequence. + * @param[out] *pDst points to the block of output data + * @param[in] firstIndex is the first output sample to start with. + * @param[in] numPoints is the number of output points to be computed. + * @return Returns either ARM_MATH_SUCCESS if the function completed correctly or ARM_MATH_ARGUMENT_ERROR if the requested subset is not in the range [0 srcALen+srcBLen-2]. + */ + + arm_status arm_conv_partial_q31( + q31_t * pSrcA, + uint32_t srcALen, + q31_t * pSrcB, + uint32_t srcBLen, + q31_t * pDst, + uint32_t firstIndex, + uint32_t numPoints); + + + /** + * @brief Partial convolution of Q31 sequences (fast version) for Cortex-M3 and Cortex-M4 + * @param[in] *pSrcA points to the first input sequence. + * @param[in] srcALen length of the first input sequence. + * @param[in] *pSrcB points to the second input sequence. + * @param[in] srcBLen length of the second input sequence. + * @param[out] *pDst points to the block of output data + * @param[in] firstIndex is the first output sample to start with. + * @param[in] numPoints is the number of output points to be computed. + * @return Returns either ARM_MATH_SUCCESS if the function completed correctly or ARM_MATH_ARGUMENT_ERROR if the requested subset is not in the range [0 srcALen+srcBLen-2]. + */ + + arm_status arm_conv_partial_fast_q31( + q31_t * pSrcA, + uint32_t srcALen, + q31_t * pSrcB, + uint32_t srcBLen, + q31_t * pDst, + uint32_t firstIndex, + uint32_t numPoints); + + + /** + * @brief Partial convolution of Q7 sequences + * @param[in] *pSrcA points to the first input sequence. + * @param[in] srcALen length of the first input sequence. + * @param[in] *pSrcB points to the second input sequence. + * @param[in] srcBLen length of the second input sequence. + * @param[out] *pDst points to the block of output data + * @param[in] firstIndex is the first output sample to start with. + * @param[in] numPoints is the number of output points to be computed. + * @param[in] *pScratch1 points to scratch buffer(of type q15_t) of size max(srcALen, srcBLen) + 2*min(srcALen, srcBLen) - 2. + * @param[in] *pScratch2 points to scratch buffer (of type q15_t) of size min(srcALen, srcBLen). + * @return Returns either ARM_MATH_SUCCESS if the function completed correctly or ARM_MATH_ARGUMENT_ERROR if the requested subset is not in the range [0 srcALen+srcBLen-2]. + */ + + arm_status arm_conv_partial_opt_q7( + q7_t * pSrcA, + uint32_t srcALen, + q7_t * pSrcB, + uint32_t srcBLen, + q7_t * pDst, + uint32_t firstIndex, + uint32_t numPoints, + q15_t * pScratch1, + q15_t * pScratch2); + + +/** + * @brief Partial convolution of Q7 sequences. + * @param[in] *pSrcA points to the first input sequence. + * @param[in] srcALen length of the first input sequence. + * @param[in] *pSrcB points to the second input sequence. + * @param[in] srcBLen length of the second input sequence. + * @param[out] *pDst points to the block of output data + * @param[in] firstIndex is the first output sample to start with. + * @param[in] numPoints is the number of output points to be computed. + * @return Returns either ARM_MATH_SUCCESS if the function completed correctly or ARM_MATH_ARGUMENT_ERROR if the requested subset is not in the range [0 srcALen+srcBLen-2]. + */ + + arm_status arm_conv_partial_q7( + q7_t * pSrcA, + uint32_t srcALen, + q7_t * pSrcB, + uint32_t srcBLen, + q7_t * pDst, + uint32_t firstIndex, + uint32_t numPoints); + + + + /** + * @brief Instance structure for the Q15 FIR decimator. + */ + + typedef struct + { + uint8_t M; /**< decimation factor. */ + uint16_t numTaps; /**< number of coefficients in the filter. */ + q15_t *pCoeffs; /**< points to the coefficient array. The array is of length numTaps.*/ + q15_t *pState; /**< points to the state variable array. The array is of length numTaps+blockSize-1. */ + } arm_fir_decimate_instance_q15; + + /** + * @brief Instance structure for the Q31 FIR decimator. + */ + + typedef struct + { + uint8_t M; /**< decimation factor. */ + uint16_t numTaps; /**< number of coefficients in the filter. */ + q31_t *pCoeffs; /**< points to the coefficient array. The array is of length numTaps.*/ + q31_t *pState; /**< points to the state variable array. The array is of length numTaps+blockSize-1. */ + + } arm_fir_decimate_instance_q31; + + /** + * @brief Instance structure for the floating-point FIR decimator. + */ + + typedef struct + { + uint8_t M; /**< decimation factor. */ + uint16_t numTaps; /**< number of coefficients in the filter. */ + float32_t *pCoeffs; /**< points to the coefficient array. The array is of length numTaps.*/ + float32_t *pState; /**< points to the state variable array. The array is of length numTaps+blockSize-1. */ + + } arm_fir_decimate_instance_f32; + + + + /** + * @brief Processing function for the floating-point FIR decimator. + * @param[in] *S points to an instance of the floating-point FIR decimator structure. + * @param[in] *pSrc points to the block of input data. + * @param[out] *pDst points to the block of output data + * @param[in] blockSize number of input samples to process per call. + * @return none + */ + + void arm_fir_decimate_f32( + const arm_fir_decimate_instance_f32 * S, + float32_t * pSrc, + float32_t * pDst, + uint32_t blockSize); + + + /** + * @brief Initialization function for the floating-point FIR decimator. + * @param[in,out] *S points to an instance of the floating-point FIR decimator structure. + * @param[in] numTaps number of coefficients in the filter. + * @param[in] M decimation factor. + * @param[in] *pCoeffs points to the filter coefficients. + * @param[in] *pState points to the state buffer. + * @param[in] blockSize number of input samples to process per call. + * @return The function returns ARM_MATH_SUCCESS if initialization is successful or ARM_MATH_LENGTH_ERROR if + * blockSize is not a multiple of M. + */ + + arm_status arm_fir_decimate_init_f32( + arm_fir_decimate_instance_f32 * S, + uint16_t numTaps, + uint8_t M, + float32_t * pCoeffs, + float32_t * pState, + uint32_t blockSize); + + /** + * @brief Processing function for the Q15 FIR decimator. + * @param[in] *S points to an instance of the Q15 FIR decimator structure. + * @param[in] *pSrc points to the block of input data. + * @param[out] *pDst points to the block of output data + * @param[in] blockSize number of input samples to process per call. + * @return none + */ + + void arm_fir_decimate_q15( + const arm_fir_decimate_instance_q15 * S, + q15_t * pSrc, + q15_t * pDst, + uint32_t blockSize); + + /** + * @brief Processing function for the Q15 FIR decimator (fast variant) for Cortex-M3 and Cortex-M4. + * @param[in] *S points to an instance of the Q15 FIR decimator structure. + * @param[in] *pSrc points to the block of input data. + * @param[out] *pDst points to the block of output data + * @param[in] blockSize number of input samples to process per call. + * @return none + */ + + void arm_fir_decimate_fast_q15( + const arm_fir_decimate_instance_q15 * S, + q15_t * pSrc, + q15_t * pDst, + uint32_t blockSize); + + + + /** + * @brief Initialization function for the Q15 FIR decimator. + * @param[in,out] *S points to an instance of the Q15 FIR decimator structure. + * @param[in] numTaps number of coefficients in the filter. + * @param[in] M decimation factor. + * @param[in] *pCoeffs points to the filter coefficients. + * @param[in] *pState points to the state buffer. + * @param[in] blockSize number of input samples to process per call. + * @return The function returns ARM_MATH_SUCCESS if initialization is successful or ARM_MATH_LENGTH_ERROR if + * blockSize is not a multiple of M. + */ + + arm_status arm_fir_decimate_init_q15( + arm_fir_decimate_instance_q15 * S, + uint16_t numTaps, + uint8_t M, + q15_t * pCoeffs, + q15_t * pState, + uint32_t blockSize); + + /** + * @brief Processing function for the Q31 FIR decimator. + * @param[in] *S points to an instance of the Q31 FIR decimator structure. + * @param[in] *pSrc points to the block of input data. + * @param[out] *pDst points to the block of output data + * @param[in] blockSize number of input samples to process per call. + * @return none + */ + + void arm_fir_decimate_q31( + const arm_fir_decimate_instance_q31 * S, + q31_t * pSrc, + q31_t * pDst, + uint32_t blockSize); + + /** + * @brief Processing function for the Q31 FIR decimator (fast variant) for Cortex-M3 and Cortex-M4. + * @param[in] *S points to an instance of the Q31 FIR decimator structure. + * @param[in] *pSrc points to the block of input data. + * @param[out] *pDst points to the block of output data + * @param[in] blockSize number of input samples to process per call. + * @return none + */ + + void arm_fir_decimate_fast_q31( + arm_fir_decimate_instance_q31 * S, + q31_t * pSrc, + q31_t * pDst, + uint32_t blockSize); + + + /** + * @brief Initialization function for the Q31 FIR decimator. + * @param[in,out] *S points to an instance of the Q31 FIR decimator structure. + * @param[in] numTaps number of coefficients in the filter. + * @param[in] M decimation factor. + * @param[in] *pCoeffs points to the filter coefficients. + * @param[in] *pState points to the state buffer. + * @param[in] blockSize number of input samples to process per call. + * @return The function returns ARM_MATH_SUCCESS if initialization is successful or ARM_MATH_LENGTH_ERROR if + * blockSize is not a multiple of M. + */ + + arm_status arm_fir_decimate_init_q31( + arm_fir_decimate_instance_q31 * S, + uint16_t numTaps, + uint8_t M, + q31_t * pCoeffs, + q31_t * pState, + uint32_t blockSize); + + + + /** + * @brief Instance structure for the Q15 FIR interpolator. + */ + + typedef struct + { + uint8_t L; /**< upsample factor. */ + uint16_t phaseLength; /**< length of each polyphase filter component. */ + q15_t *pCoeffs; /**< points to the coefficient array. The array is of length L*phaseLength. */ + q15_t *pState; /**< points to the state variable array. The array is of length blockSize+phaseLength-1. */ + } arm_fir_interpolate_instance_q15; + + /** + * @brief Instance structure for the Q31 FIR interpolator. + */ + + typedef struct + { + uint8_t L; /**< upsample factor. */ + uint16_t phaseLength; /**< length of each polyphase filter component. */ + q31_t *pCoeffs; /**< points to the coefficient array. The array is of length L*phaseLength. */ + q31_t *pState; /**< points to the state variable array. The array is of length blockSize+phaseLength-1. */ + } arm_fir_interpolate_instance_q31; + + /** + * @brief Instance structure for the floating-point FIR interpolator. + */ + + typedef struct + { + uint8_t L; /**< upsample factor. */ + uint16_t phaseLength; /**< length of each polyphase filter component. */ + float32_t *pCoeffs; /**< points to the coefficient array. The array is of length L*phaseLength. */ + float32_t *pState; /**< points to the state variable array. The array is of length phaseLength+numTaps-1. */ + } arm_fir_interpolate_instance_f32; + + + /** + * @brief Processing function for the Q15 FIR interpolator. + * @param[in] *S points to an instance of the Q15 FIR interpolator structure. + * @param[in] *pSrc points to the block of input data. + * @param[out] *pDst points to the block of output data. + * @param[in] blockSize number of input samples to process per call. + * @return none. + */ + + void arm_fir_interpolate_q15( + const arm_fir_interpolate_instance_q15 * S, + q15_t * pSrc, + q15_t * pDst, + uint32_t blockSize); + + + /** + * @brief Initialization function for the Q15 FIR interpolator. + * @param[in,out] *S points to an instance of the Q15 FIR interpolator structure. + * @param[in] L upsample factor. + * @param[in] numTaps number of filter coefficients in the filter. + * @param[in] *pCoeffs points to the filter coefficient buffer. + * @param[in] *pState points to the state buffer. + * @param[in] blockSize number of input samples to process per call. + * @return The function returns ARM_MATH_SUCCESS if initialization is successful or ARM_MATH_LENGTH_ERROR if + * the filter length numTaps is not a multiple of the interpolation factor L. + */ + + arm_status arm_fir_interpolate_init_q15( + arm_fir_interpolate_instance_q15 * S, + uint8_t L, + uint16_t numTaps, + q15_t * pCoeffs, + q15_t * pState, + uint32_t blockSize); + + /** + * @brief Processing function for the Q31 FIR interpolator. + * @param[in] *S points to an instance of the Q15 FIR interpolator structure. + * @param[in] *pSrc points to the block of input data. + * @param[out] *pDst points to the block of output data. + * @param[in] blockSize number of input samples to process per call. + * @return none. + */ + + void arm_fir_interpolate_q31( + const arm_fir_interpolate_instance_q31 * S, + q31_t * pSrc, + q31_t * pDst, + uint32_t blockSize); + + /** + * @brief Initialization function for the Q31 FIR interpolator. + * @param[in,out] *S points to an instance of the Q31 FIR interpolator structure. + * @param[in] L upsample factor. + * @param[in] numTaps number of filter coefficients in the filter. + * @param[in] *pCoeffs points to the filter coefficient buffer. + * @param[in] *pState points to the state buffer. + * @param[in] blockSize number of input samples to process per call. + * @return The function returns ARM_MATH_SUCCESS if initialization is successful or ARM_MATH_LENGTH_ERROR if + * the filter length numTaps is not a multiple of the interpolation factor L. + */ + + arm_status arm_fir_interpolate_init_q31( + arm_fir_interpolate_instance_q31 * S, + uint8_t L, + uint16_t numTaps, + q31_t * pCoeffs, + q31_t * pState, + uint32_t blockSize); + + + /** + * @brief Processing function for the floating-point FIR interpolator. + * @param[in] *S points to an instance of the floating-point FIR interpolator structure. + * @param[in] *pSrc points to the block of input data. + * @param[out] *pDst points to the block of output data. + * @param[in] blockSize number of input samples to process per call. + * @return none. + */ + + void arm_fir_interpolate_f32( + const arm_fir_interpolate_instance_f32 * S, + float32_t * pSrc, + float32_t * pDst, + uint32_t blockSize); + + /** + * @brief Initialization function for the floating-point FIR interpolator. + * @param[in,out] *S points to an instance of the floating-point FIR interpolator structure. + * @param[in] L upsample factor. + * @param[in] numTaps number of filter coefficients in the filter. + * @param[in] *pCoeffs points to the filter coefficient buffer. + * @param[in] *pState points to the state buffer. + * @param[in] blockSize number of input samples to process per call. + * @return The function returns ARM_MATH_SUCCESS if initialization is successful or ARM_MATH_LENGTH_ERROR if + * the filter length numTaps is not a multiple of the interpolation factor L. + */ + + arm_status arm_fir_interpolate_init_f32( + arm_fir_interpolate_instance_f32 * S, + uint8_t L, + uint16_t numTaps, + float32_t * pCoeffs, + float32_t * pState, + uint32_t blockSize); + + /** + * @brief Instance structure for the high precision Q31 Biquad cascade filter. + */ + + typedef struct + { + uint8_t numStages; /**< number of 2nd order stages in the filter. Overall order is 2*numStages. */ + q63_t *pState; /**< points to the array of state coefficients. The array is of length 4*numStages. */ + q31_t *pCoeffs; /**< points to the array of coefficients. The array is of length 5*numStages. */ + uint8_t postShift; /**< additional shift, in bits, applied to each output sample. */ + + } arm_biquad_cas_df1_32x64_ins_q31; + + + /** + * @param[in] *S points to an instance of the high precision Q31 Biquad cascade filter structure. + * @param[in] *pSrc points to the block of input data. + * @param[out] *pDst points to the block of output data + * @param[in] blockSize number of samples to process. + * @return none. + */ + + void arm_biquad_cas_df1_32x64_q31( + const arm_biquad_cas_df1_32x64_ins_q31 * S, + q31_t * pSrc, + q31_t * pDst, + uint32_t blockSize); + + + /** + * @param[in,out] *S points to an instance of the high precision Q31 Biquad cascade filter structure. + * @param[in] numStages number of 2nd order stages in the filter. + * @param[in] *pCoeffs points to the filter coefficients. + * @param[in] *pState points to the state buffer. + * @param[in] postShift shift to be applied to the output. Varies according to the coefficients format + * @return none + */ + + void arm_biquad_cas_df1_32x64_init_q31( + arm_biquad_cas_df1_32x64_ins_q31 * S, + uint8_t numStages, + q31_t * pCoeffs, + q63_t * pState, + uint8_t postShift); + + + + /** + * @brief Instance structure for the floating-point transposed direct form II Biquad cascade filter. + */ + + typedef struct + { + uint8_t numStages; /**< number of 2nd order stages in the filter. Overall order is 2*numStages. */ + float32_t *pState; /**< points to the array of state coefficients. The array is of length 2*numStages. */ + float32_t *pCoeffs; /**< points to the array of coefficients. The array is of length 5*numStages. */ + } arm_biquad_cascade_df2T_instance_f32; + + + /** + * @brief Processing function for the floating-point transposed direct form II Biquad cascade filter. + * @param[in] *S points to an instance of the filter data structure. + * @param[in] *pSrc points to the block of input data. + * @param[out] *pDst points to the block of output data + * @param[in] blockSize number of samples to process. + * @return none. + */ + + void arm_biquad_cascade_df2T_f32( + const arm_biquad_cascade_df2T_instance_f32 * S, + float32_t * pSrc, + float32_t * pDst, + uint32_t blockSize); + + + /** + * @brief Initialization function for the floating-point transposed direct form II Biquad cascade filter. + * @param[in,out] *S points to an instance of the filter data structure. + * @param[in] numStages number of 2nd order stages in the filter. + * @param[in] *pCoeffs points to the filter coefficients. + * @param[in] *pState points to the state buffer. + * @return none + */ + + void arm_biquad_cascade_df2T_init_f32( + arm_biquad_cascade_df2T_instance_f32 * S, + uint8_t numStages, + float32_t * pCoeffs, + float32_t * pState); + + + + /** + * @brief Instance structure for the Q15 FIR lattice filter. + */ + + typedef struct + { + uint16_t numStages; /**< number of filter stages. */ + q15_t *pState; /**< points to the state variable array. The array is of length numStages. */ + q15_t *pCoeffs; /**< points to the coefficient array. The array is of length numStages. */ + } arm_fir_lattice_instance_q15; + + /** + * @brief Instance structure for the Q31 FIR lattice filter. + */ + + typedef struct + { + uint16_t numStages; /**< number of filter stages. */ + q31_t *pState; /**< points to the state variable array. The array is of length numStages. */ + q31_t *pCoeffs; /**< points to the coefficient array. The array is of length numStages. */ + } arm_fir_lattice_instance_q31; + + /** + * @brief Instance structure for the floating-point FIR lattice filter. + */ + + typedef struct + { + uint16_t numStages; /**< number of filter stages. */ + float32_t *pState; /**< points to the state variable array. The array is of length numStages. */ + float32_t *pCoeffs; /**< points to the coefficient array. The array is of length numStages. */ + } arm_fir_lattice_instance_f32; + + /** + * @brief Initialization function for the Q15 FIR lattice filter. + * @param[in] *S points to an instance of the Q15 FIR lattice structure. + * @param[in] numStages number of filter stages. + * @param[in] *pCoeffs points to the coefficient buffer. The array is of length numStages. + * @param[in] *pState points to the state buffer. The array is of length numStages. + * @return none. + */ + + void arm_fir_lattice_init_q15( + arm_fir_lattice_instance_q15 * S, + uint16_t numStages, + q15_t * pCoeffs, + q15_t * pState); + + + /** + * @brief Processing function for the Q15 FIR lattice filter. + * @param[in] *S points to an instance of the Q15 FIR lattice structure. + * @param[in] *pSrc points to the block of input data. + * @param[out] *pDst points to the block of output data. + * @param[in] blockSize number of samples to process. + * @return none. + */ + void arm_fir_lattice_q15( + const arm_fir_lattice_instance_q15 * S, + q15_t * pSrc, + q15_t * pDst, + uint32_t blockSize); + + /** + * @brief Initialization function for the Q31 FIR lattice filter. + * @param[in] *S points to an instance of the Q31 FIR lattice structure. + * @param[in] numStages number of filter stages. + * @param[in] *pCoeffs points to the coefficient buffer. The array is of length numStages. + * @param[in] *pState points to the state buffer. The array is of length numStages. + * @return none. + */ + + void arm_fir_lattice_init_q31( + arm_fir_lattice_instance_q31 * S, + uint16_t numStages, + q31_t * pCoeffs, + q31_t * pState); + + + /** + * @brief Processing function for the Q31 FIR lattice filter. + * @param[in] *S points to an instance of the Q31 FIR lattice structure. + * @param[in] *pSrc points to the block of input data. + * @param[out] *pDst points to the block of output data + * @param[in] blockSize number of samples to process. + * @return none. + */ + + void arm_fir_lattice_q31( + const arm_fir_lattice_instance_q31 * S, + q31_t * pSrc, + q31_t * pDst, + uint32_t blockSize); + +/** + * @brief Initialization function for the floating-point FIR lattice filter. + * @param[in] *S points to an instance of the floating-point FIR lattice structure. + * @param[in] numStages number of filter stages. + * @param[in] *pCoeffs points to the coefficient buffer. The array is of length numStages. + * @param[in] *pState points to the state buffer. The array is of length numStages. + * @return none. + */ + + void arm_fir_lattice_init_f32( + arm_fir_lattice_instance_f32 * S, + uint16_t numStages, + float32_t * pCoeffs, + float32_t * pState); + + /** + * @brief Processing function for the floating-point FIR lattice filter. + * @param[in] *S points to an instance of the floating-point FIR lattice structure. + * @param[in] *pSrc points to the block of input data. + * @param[out] *pDst points to the block of output data + * @param[in] blockSize number of samples to process. + * @return none. + */ + + void arm_fir_lattice_f32( + const arm_fir_lattice_instance_f32 * S, + float32_t * pSrc, + float32_t * pDst, + uint32_t blockSize); + + /** + * @brief Instance structure for the Q15 IIR lattice filter. + */ + typedef struct + { + uint16_t numStages; /**< number of stages in the filter. */ + q15_t *pState; /**< points to the state variable array. The array is of length numStages+blockSize. */ + q15_t *pkCoeffs; /**< points to the reflection coefficient array. The array is of length numStages. */ + q15_t *pvCoeffs; /**< points to the ladder coefficient array. The array is of length numStages+1. */ + } arm_iir_lattice_instance_q15; + + /** + * @brief Instance structure for the Q31 IIR lattice filter. + */ + typedef struct + { + uint16_t numStages; /**< number of stages in the filter. */ + q31_t *pState; /**< points to the state variable array. The array is of length numStages+blockSize. */ + q31_t *pkCoeffs; /**< points to the reflection coefficient array. The array is of length numStages. */ + q31_t *pvCoeffs; /**< points to the ladder coefficient array. The array is of length numStages+1. */ + } arm_iir_lattice_instance_q31; + + /** + * @brief Instance structure for the floating-point IIR lattice filter. + */ + typedef struct + { + uint16_t numStages; /**< number of stages in the filter. */ + float32_t *pState; /**< points to the state variable array. The array is of length numStages+blockSize. */ + float32_t *pkCoeffs; /**< points to the reflection coefficient array. The array is of length numStages. */ + float32_t *pvCoeffs; /**< points to the ladder coefficient array. The array is of length numStages+1. */ + } arm_iir_lattice_instance_f32; + + /** + * @brief Processing function for the floating-point IIR lattice filter. + * @param[in] *S points to an instance of the floating-point IIR lattice structure. + * @param[in] *pSrc points to the block of input data. + * @param[out] *pDst points to the block of output data. + * @param[in] blockSize number of samples to process. + * @return none. + */ + + void arm_iir_lattice_f32( + const arm_iir_lattice_instance_f32 * S, + float32_t * pSrc, + float32_t * pDst, + uint32_t blockSize); + + /** + * @brief Initialization function for the floating-point IIR lattice filter. + * @param[in] *S points to an instance of the floating-point IIR lattice structure. + * @param[in] numStages number of stages in the filter. + * @param[in] *pkCoeffs points to the reflection coefficient buffer. The array is of length numStages. + * @param[in] *pvCoeffs points to the ladder coefficient buffer. The array is of length numStages+1. + * @param[in] *pState points to the state buffer. The array is of length numStages+blockSize-1. + * @param[in] blockSize number of samples to process. + * @return none. + */ + + void arm_iir_lattice_init_f32( + arm_iir_lattice_instance_f32 * S, + uint16_t numStages, + float32_t * pkCoeffs, + float32_t * pvCoeffs, + float32_t * pState, + uint32_t blockSize); + + + /** + * @brief Processing function for the Q31 IIR lattice filter. + * @param[in] *S points to an instance of the Q31 IIR lattice structure. + * @param[in] *pSrc points to the block of input data. + * @param[out] *pDst points to the block of output data. + * @param[in] blockSize number of samples to process. + * @return none. + */ + + void arm_iir_lattice_q31( + const arm_iir_lattice_instance_q31 * S, + q31_t * pSrc, + q31_t * pDst, + uint32_t blockSize); + + + /** + * @brief Initialization function for the Q31 IIR lattice filter. + * @param[in] *S points to an instance of the Q31 IIR lattice structure. + * @param[in] numStages number of stages in the filter. + * @param[in] *pkCoeffs points to the reflection coefficient buffer. The array is of length numStages. + * @param[in] *pvCoeffs points to the ladder coefficient buffer. The array is of length numStages+1. + * @param[in] *pState points to the state buffer. The array is of length numStages+blockSize. + * @param[in] blockSize number of samples to process. + * @return none. + */ + + void arm_iir_lattice_init_q31( + arm_iir_lattice_instance_q31 * S, + uint16_t numStages, + q31_t * pkCoeffs, + q31_t * pvCoeffs, + q31_t * pState, + uint32_t blockSize); + + + /** + * @brief Processing function for the Q15 IIR lattice filter. + * @param[in] *S points to an instance of the Q15 IIR lattice structure. + * @param[in] *pSrc points to the block of input data. + * @param[out] *pDst points to the block of output data. + * @param[in] blockSize number of samples to process. + * @return none. + */ + + void arm_iir_lattice_q15( + const arm_iir_lattice_instance_q15 * S, + q15_t * pSrc, + q15_t * pDst, + uint32_t blockSize); + + +/** + * @brief Initialization function for the Q15 IIR lattice filter. + * @param[in] *S points to an instance of the fixed-point Q15 IIR lattice structure. + * @param[in] numStages number of stages in the filter. + * @param[in] *pkCoeffs points to reflection coefficient buffer. The array is of length numStages. + * @param[in] *pvCoeffs points to ladder coefficient buffer. The array is of length numStages+1. + * @param[in] *pState points to state buffer. The array is of length numStages+blockSize. + * @param[in] blockSize number of samples to process per call. + * @return none. + */ + + void arm_iir_lattice_init_q15( + arm_iir_lattice_instance_q15 * S, + uint16_t numStages, + q15_t * pkCoeffs, + q15_t * pvCoeffs, + q15_t * pState, + uint32_t blockSize); + + /** + * @brief Instance structure for the floating-point LMS filter. + */ + + typedef struct + { + uint16_t numTaps; /**< number of coefficients in the filter. */ + float32_t *pState; /**< points to the state variable array. The array is of length numTaps+blockSize-1. */ + float32_t *pCoeffs; /**< points to the coefficient array. The array is of length numTaps. */ + float32_t mu; /**< step size that controls filter coefficient updates. */ + } arm_lms_instance_f32; + + /** + * @brief Processing function for floating-point LMS filter. + * @param[in] *S points to an instance of the floating-point LMS filter structure. + * @param[in] *pSrc points to the block of input data. + * @param[in] *pRef points to the block of reference data. + * @param[out] *pOut points to the block of output data. + * @param[out] *pErr points to the block of error data. + * @param[in] blockSize number of samples to process. + * @return none. + */ + + void arm_lms_f32( + const arm_lms_instance_f32 * S, + float32_t * pSrc, + float32_t * pRef, + float32_t * pOut, + float32_t * pErr, + uint32_t blockSize); + + /** + * @brief Initialization function for floating-point LMS filter. + * @param[in] *S points to an instance of the floating-point LMS filter structure. + * @param[in] numTaps number of filter coefficients. + * @param[in] *pCoeffs points to the coefficient buffer. + * @param[in] *pState points to state buffer. + * @param[in] mu step size that controls filter coefficient updates. + * @param[in] blockSize number of samples to process. + * @return none. + */ + + void arm_lms_init_f32( + arm_lms_instance_f32 * S, + uint16_t numTaps, + float32_t * pCoeffs, + float32_t * pState, + float32_t mu, + uint32_t blockSize); + + /** + * @brief Instance structure for the Q15 LMS filter. + */ + + typedef struct + { + uint16_t numTaps; /**< number of coefficients in the filter. */ + q15_t *pState; /**< points to the state variable array. The array is of length numTaps+blockSize-1. */ + q15_t *pCoeffs; /**< points to the coefficient array. The array is of length numTaps. */ + q15_t mu; /**< step size that controls filter coefficient updates. */ + uint32_t postShift; /**< bit shift applied to coefficients. */ + } arm_lms_instance_q15; + + + /** + * @brief Initialization function for the Q15 LMS filter. + * @param[in] *S points to an instance of the Q15 LMS filter structure. + * @param[in] numTaps number of filter coefficients. + * @param[in] *pCoeffs points to the coefficient buffer. + * @param[in] *pState points to the state buffer. + * @param[in] mu step size that controls filter coefficient updates. + * @param[in] blockSize number of samples to process. + * @param[in] postShift bit shift applied to coefficients. + * @return none. + */ + + void arm_lms_init_q15( + arm_lms_instance_q15 * S, + uint16_t numTaps, + q15_t * pCoeffs, + q15_t * pState, + q15_t mu, + uint32_t blockSize, + uint32_t postShift); + + /** + * @brief Processing function for Q15 LMS filter. + * @param[in] *S points to an instance of the Q15 LMS filter structure. + * @param[in] *pSrc points to the block of input data. + * @param[in] *pRef points to the block of reference data. + * @param[out] *pOut points to the block of output data. + * @param[out] *pErr points to the block of error data. + * @param[in] blockSize number of samples to process. + * @return none. + */ + + void arm_lms_q15( + const arm_lms_instance_q15 * S, + q15_t * pSrc, + q15_t * pRef, + q15_t * pOut, + q15_t * pErr, + uint32_t blockSize); + + + /** + * @brief Instance structure for the Q31 LMS filter. + */ + + typedef struct + { + uint16_t numTaps; /**< number of coefficients in the filter. */ + q31_t *pState; /**< points to the state variable array. The array is of length numTaps+blockSize-1. */ + q31_t *pCoeffs; /**< points to the coefficient array. The array is of length numTaps. */ + q31_t mu; /**< step size that controls filter coefficient updates. */ + uint32_t postShift; /**< bit shift applied to coefficients. */ + + } arm_lms_instance_q31; + + /** + * @brief Processing function for Q31 LMS filter. + * @param[in] *S points to an instance of the Q15 LMS filter structure. + * @param[in] *pSrc points to the block of input data. + * @param[in] *pRef points to the block of reference data. + * @param[out] *pOut points to the block of output data. + * @param[out] *pErr points to the block of error data. + * @param[in] blockSize number of samples to process. + * @return none. + */ + + void arm_lms_q31( + const arm_lms_instance_q31 * S, + q31_t * pSrc, + q31_t * pRef, + q31_t * pOut, + q31_t * pErr, + uint32_t blockSize); + + /** + * @brief Initialization function for Q31 LMS filter. + * @param[in] *S points to an instance of the Q31 LMS filter structure. + * @param[in] numTaps number of filter coefficients. + * @param[in] *pCoeffs points to coefficient buffer. + * @param[in] *pState points to state buffer. + * @param[in] mu step size that controls filter coefficient updates. + * @param[in] blockSize number of samples to process. + * @param[in] postShift bit shift applied to coefficients. + * @return none. + */ + + void arm_lms_init_q31( + arm_lms_instance_q31 * S, + uint16_t numTaps, + q31_t * pCoeffs, + q31_t * pState, + q31_t mu, + uint32_t blockSize, + uint32_t postShift); + + /** + * @brief Instance structure for the floating-point normalized LMS filter. + */ + + typedef struct + { + uint16_t numTaps; /**< number of coefficients in the filter. */ + float32_t *pState; /**< points to the state variable array. The array is of length numTaps+blockSize-1. */ + float32_t *pCoeffs; /**< points to the coefficient array. The array is of length numTaps. */ + float32_t mu; /**< step size that control filter coefficient updates. */ + float32_t energy; /**< saves previous frame energy. */ + float32_t x0; /**< saves previous input sample. */ + } arm_lms_norm_instance_f32; + + /** + * @brief Processing function for floating-point normalized LMS filter. + * @param[in] *S points to an instance of the floating-point normalized LMS filter structure. + * @param[in] *pSrc points to the block of input data. + * @param[in] *pRef points to the block of reference data. + * @param[out] *pOut points to the block of output data. + * @param[out] *pErr points to the block of error data. + * @param[in] blockSize number of samples to process. + * @return none. + */ + + void arm_lms_norm_f32( + arm_lms_norm_instance_f32 * S, + float32_t * pSrc, + float32_t * pRef, + float32_t * pOut, + float32_t * pErr, + uint32_t blockSize); + + /** + * @brief Initialization function for floating-point normalized LMS filter. + * @param[in] *S points to an instance of the floating-point LMS filter structure. + * @param[in] numTaps number of filter coefficients. + * @param[in] *pCoeffs points to coefficient buffer. + * @param[in] *pState points to state buffer. + * @param[in] mu step size that controls filter coefficient updates. + * @param[in] blockSize number of samples to process. + * @return none. + */ + + void arm_lms_norm_init_f32( + arm_lms_norm_instance_f32 * S, + uint16_t numTaps, + float32_t * pCoeffs, + float32_t * pState, + float32_t mu, + uint32_t blockSize); + + + /** + * @brief Instance structure for the Q31 normalized LMS filter. + */ + typedef struct + { + uint16_t numTaps; /**< number of coefficients in the filter. */ + q31_t *pState; /**< points to the state variable array. The array is of length numTaps+blockSize-1. */ + q31_t *pCoeffs; /**< points to the coefficient array. The array is of length numTaps. */ + q31_t mu; /**< step size that controls filter coefficient updates. */ + uint8_t postShift; /**< bit shift applied to coefficients. */ + q31_t *recipTable; /**< points to the reciprocal initial value table. */ + q31_t energy; /**< saves previous frame energy. */ + q31_t x0; /**< saves previous input sample. */ + } arm_lms_norm_instance_q31; + + /** + * @brief Processing function for Q31 normalized LMS filter. + * @param[in] *S points to an instance of the Q31 normalized LMS filter structure. + * @param[in] *pSrc points to the block of input data. + * @param[in] *pRef points to the block of reference data. + * @param[out] *pOut points to the block of output data. + * @param[out] *pErr points to the block of error data. + * @param[in] blockSize number of samples to process. + * @return none. + */ + + void arm_lms_norm_q31( + arm_lms_norm_instance_q31 * S, + q31_t * pSrc, + q31_t * pRef, + q31_t * pOut, + q31_t * pErr, + uint32_t blockSize); + + /** + * @brief Initialization function for Q31 normalized LMS filter. + * @param[in] *S points to an instance of the Q31 normalized LMS filter structure. + * @param[in] numTaps number of filter coefficients. + * @param[in] *pCoeffs points to coefficient buffer. + * @param[in] *pState points to state buffer. + * @param[in] mu step size that controls filter coefficient updates. + * @param[in] blockSize number of samples to process. + * @param[in] postShift bit shift applied to coefficients. + * @return none. + */ + + void arm_lms_norm_init_q31( + arm_lms_norm_instance_q31 * S, + uint16_t numTaps, + q31_t * pCoeffs, + q31_t * pState, + q31_t mu, + uint32_t blockSize, + uint8_t postShift); + + /** + * @brief Instance structure for the Q15 normalized LMS filter. + */ + + typedef struct + { + uint16_t numTaps; /**< Number of coefficients in the filter. */ + q15_t *pState; /**< points to the state variable array. The array is of length numTaps+blockSize-1. */ + q15_t *pCoeffs; /**< points to the coefficient array. The array is of length numTaps. */ + q15_t mu; /**< step size that controls filter coefficient updates. */ + uint8_t postShift; /**< bit shift applied to coefficients. */ + q15_t *recipTable; /**< Points to the reciprocal initial value table. */ + q15_t energy; /**< saves previous frame energy. */ + q15_t x0; /**< saves previous input sample. */ + } arm_lms_norm_instance_q15; + + /** + * @brief Processing function for Q15 normalized LMS filter. + * @param[in] *S points to an instance of the Q15 normalized LMS filter structure. + * @param[in] *pSrc points to the block of input data. + * @param[in] *pRef points to the block of reference data. + * @param[out] *pOut points to the block of output data. + * @param[out] *pErr points to the block of error data. + * @param[in] blockSize number of samples to process. + * @return none. + */ + + void arm_lms_norm_q15( + arm_lms_norm_instance_q15 * S, + q15_t * pSrc, + q15_t * pRef, + q15_t * pOut, + q15_t * pErr, + uint32_t blockSize); + + + /** + * @brief Initialization function for Q15 normalized LMS filter. + * @param[in] *S points to an instance of the Q15 normalized LMS filter structure. + * @param[in] numTaps number of filter coefficients. + * @param[in] *pCoeffs points to coefficient buffer. + * @param[in] *pState points to state buffer. + * @param[in] mu step size that controls filter coefficient updates. + * @param[in] blockSize number of samples to process. + * @param[in] postShift bit shift applied to coefficients. + * @return none. + */ + + void arm_lms_norm_init_q15( + arm_lms_norm_instance_q15 * S, + uint16_t numTaps, + q15_t * pCoeffs, + q15_t * pState, + q15_t mu, + uint32_t blockSize, + uint8_t postShift); + + /** + * @brief Correlation of floating-point sequences. + * @param[in] *pSrcA points to the first input sequence. + * @param[in] srcALen length of the first input sequence. + * @param[in] *pSrcB points to the second input sequence. + * @param[in] srcBLen length of the second input sequence. + * @param[out] *pDst points to the block of output data Length 2 * max(srcALen, srcBLen) - 1. + * @return none. + */ + + void arm_correlate_f32( + float32_t * pSrcA, + uint32_t srcALen, + float32_t * pSrcB, + uint32_t srcBLen, + float32_t * pDst); + + + /** + * @brief Correlation of Q15 sequences + * @param[in] *pSrcA points to the first input sequence. + * @param[in] srcALen length of the first input sequence. + * @param[in] *pSrcB points to the second input sequence. + * @param[in] srcBLen length of the second input sequence. + * @param[out] *pDst points to the block of output data Length 2 * max(srcALen, srcBLen) - 1. + * @param[in] *pScratch points to scratch buffer of size max(srcALen, srcBLen) + 2*min(srcALen, srcBLen) - 2. + * @return none. + */ + void arm_correlate_opt_q15( + q15_t * pSrcA, + uint32_t srcALen, + q15_t * pSrcB, + uint32_t srcBLen, + q15_t * pDst, + q15_t * pScratch); + + + /** + * @brief Correlation of Q15 sequences. + * @param[in] *pSrcA points to the first input sequence. + * @param[in] srcALen length of the first input sequence. + * @param[in] *pSrcB points to the second input sequence. + * @param[in] srcBLen length of the second input sequence. + * @param[out] *pDst points to the block of output data Length 2 * max(srcALen, srcBLen) - 1. + * @return none. + */ + + void arm_correlate_q15( + q15_t * pSrcA, + uint32_t srcALen, + q15_t * pSrcB, + uint32_t srcBLen, + q15_t * pDst); + + /** + * @brief Correlation of Q15 sequences (fast version) for Cortex-M3 and Cortex-M4. + * @param[in] *pSrcA points to the first input sequence. + * @param[in] srcALen length of the first input sequence. + * @param[in] *pSrcB points to the second input sequence. + * @param[in] srcBLen length of the second input sequence. + * @param[out] *pDst points to the block of output data Length 2 * max(srcALen, srcBLen) - 1. + * @return none. + */ + + void arm_correlate_fast_q15( + q15_t * pSrcA, + uint32_t srcALen, + q15_t * pSrcB, + uint32_t srcBLen, + q15_t * pDst); + + + + /** + * @brief Correlation of Q15 sequences (fast version) for Cortex-M3 and Cortex-M4. + * @param[in] *pSrcA points to the first input sequence. + * @param[in] srcALen length of the first input sequence. + * @param[in] *pSrcB points to the second input sequence. + * @param[in] srcBLen length of the second input sequence. + * @param[out] *pDst points to the block of output data Length 2 * max(srcALen, srcBLen) - 1. + * @param[in] *pScratch points to scratch buffer of size max(srcALen, srcBLen) + 2*min(srcALen, srcBLen) - 2. + * @return none. + */ + + void arm_correlate_fast_opt_q15( + q15_t * pSrcA, + uint32_t srcALen, + q15_t * pSrcB, + uint32_t srcBLen, + q15_t * pDst, + q15_t * pScratch); + + /** + * @brief Correlation of Q31 sequences. + * @param[in] *pSrcA points to the first input sequence. + * @param[in] srcALen length of the first input sequence. + * @param[in] *pSrcB points to the second input sequence. + * @param[in] srcBLen length of the second input sequence. + * @param[out] *pDst points to the block of output data Length 2 * max(srcALen, srcBLen) - 1. + * @return none. + */ + + void arm_correlate_q31( + q31_t * pSrcA, + uint32_t srcALen, + q31_t * pSrcB, + uint32_t srcBLen, + q31_t * pDst); + + /** + * @brief Correlation of Q31 sequences (fast version) for Cortex-M3 and Cortex-M4 + * @param[in] *pSrcA points to the first input sequence. + * @param[in] srcALen length of the first input sequence. + * @param[in] *pSrcB points to the second input sequence. + * @param[in] srcBLen length of the second input sequence. + * @param[out] *pDst points to the block of output data Length 2 * max(srcALen, srcBLen) - 1. + * @return none. + */ + + void arm_correlate_fast_q31( + q31_t * pSrcA, + uint32_t srcALen, + q31_t * pSrcB, + uint32_t srcBLen, + q31_t * pDst); + + + + /** + * @brief Correlation of Q7 sequences. + * @param[in] *pSrcA points to the first input sequence. + * @param[in] srcALen length of the first input sequence. + * @param[in] *pSrcB points to the second input sequence. + * @param[in] srcBLen length of the second input sequence. + * @param[out] *pDst points to the block of output data Length 2 * max(srcALen, srcBLen) - 1. + * @param[in] *pScratch1 points to scratch buffer(of type q15_t) of size max(srcALen, srcBLen) + 2*min(srcALen, srcBLen) - 2. + * @param[in] *pScratch2 points to scratch buffer (of type q15_t) of size min(srcALen, srcBLen). + * @return none. + */ + + void arm_correlate_opt_q7( + q7_t * pSrcA, + uint32_t srcALen, + q7_t * pSrcB, + uint32_t srcBLen, + q7_t * pDst, + q15_t * pScratch1, + q15_t * pScratch2); + + + /** + * @brief Correlation of Q7 sequences. + * @param[in] *pSrcA points to the first input sequence. + * @param[in] srcALen length of the first input sequence. + * @param[in] *pSrcB points to the second input sequence. + * @param[in] srcBLen length of the second input sequence. + * @param[out] *pDst points to the block of output data Length 2 * max(srcALen, srcBLen) - 1. + * @return none. + */ + + void arm_correlate_q7( + q7_t * pSrcA, + uint32_t srcALen, + q7_t * pSrcB, + uint32_t srcBLen, + q7_t * pDst); + + + /** + * @brief Instance structure for the floating-point sparse FIR filter. + */ + typedef struct + { + uint16_t numTaps; /**< number of coefficients in the filter. */ + uint16_t stateIndex; /**< state buffer index. Points to the oldest sample in the state buffer. */ + float32_t *pState; /**< points to the state buffer array. The array is of length maxDelay+blockSize-1. */ + float32_t *pCoeffs; /**< points to the coefficient array. The array is of length numTaps.*/ + uint16_t maxDelay; /**< maximum offset specified by the pTapDelay array. */ + int32_t *pTapDelay; /**< points to the array of delay values. The array is of length numTaps. */ + } arm_fir_sparse_instance_f32; + + /** + * @brief Instance structure for the Q31 sparse FIR filter. + */ + + typedef struct + { + uint16_t numTaps; /**< number of coefficients in the filter. */ + uint16_t stateIndex; /**< state buffer index. Points to the oldest sample in the state buffer. */ + q31_t *pState; /**< points to the state buffer array. The array is of length maxDelay+blockSize-1. */ + q31_t *pCoeffs; /**< points to the coefficient array. The array is of length numTaps.*/ + uint16_t maxDelay; /**< maximum offset specified by the pTapDelay array. */ + int32_t *pTapDelay; /**< points to the array of delay values. The array is of length numTaps. */ + } arm_fir_sparse_instance_q31; + + /** + * @brief Instance structure for the Q15 sparse FIR filter. + */ + + typedef struct + { + uint16_t numTaps; /**< number of coefficients in the filter. */ + uint16_t stateIndex; /**< state buffer index. Points to the oldest sample in the state buffer. */ + q15_t *pState; /**< points to the state buffer array. The array is of length maxDelay+blockSize-1. */ + q15_t *pCoeffs; /**< points to the coefficient array. The array is of length numTaps.*/ + uint16_t maxDelay; /**< maximum offset specified by the pTapDelay array. */ + int32_t *pTapDelay; /**< points to the array of delay values. The array is of length numTaps. */ + } arm_fir_sparse_instance_q15; + + /** + * @brief Instance structure for the Q7 sparse FIR filter. + */ + + typedef struct + { + uint16_t numTaps; /**< number of coefficients in the filter. */ + uint16_t stateIndex; /**< state buffer index. Points to the oldest sample in the state buffer. */ + q7_t *pState; /**< points to the state buffer array. The array is of length maxDelay+blockSize-1. */ + q7_t *pCoeffs; /**< points to the coefficient array. The array is of length numTaps.*/ + uint16_t maxDelay; /**< maximum offset specified by the pTapDelay array. */ + int32_t *pTapDelay; /**< points to the array of delay values. The array is of length numTaps. */ + } arm_fir_sparse_instance_q7; + + /** + * @brief Processing function for the floating-point sparse FIR filter. + * @param[in] *S points to an instance of the floating-point sparse FIR structure. + * @param[in] *pSrc points to the block of input data. + * @param[out] *pDst points to the block of output data + * @param[in] *pScratchIn points to a temporary buffer of size blockSize. + * @param[in] blockSize number of input samples to process per call. + * @return none. + */ + + void arm_fir_sparse_f32( + arm_fir_sparse_instance_f32 * S, + float32_t * pSrc, + float32_t * pDst, + float32_t * pScratchIn, + uint32_t blockSize); + + /** + * @brief Initialization function for the floating-point sparse FIR filter. + * @param[in,out] *S points to an instance of the floating-point sparse FIR structure. + * @param[in] numTaps number of nonzero coefficients in the filter. + * @param[in] *pCoeffs points to the array of filter coefficients. + * @param[in] *pState points to the state buffer. + * @param[in] *pTapDelay points to the array of offset times. + * @param[in] maxDelay maximum offset time supported. + * @param[in] blockSize number of samples that will be processed per block. + * @return none + */ + + void arm_fir_sparse_init_f32( + arm_fir_sparse_instance_f32 * S, + uint16_t numTaps, + float32_t * pCoeffs, + float32_t * pState, + int32_t * pTapDelay, + uint16_t maxDelay, + uint32_t blockSize); + + /** + * @brief Processing function for the Q31 sparse FIR filter. + * @param[in] *S points to an instance of the Q31 sparse FIR structure. + * @param[in] *pSrc points to the block of input data. + * @param[out] *pDst points to the block of output data + * @param[in] *pScratchIn points to a temporary buffer of size blockSize. + * @param[in] blockSize number of input samples to process per call. + * @return none. + */ + + void arm_fir_sparse_q31( + arm_fir_sparse_instance_q31 * S, + q31_t * pSrc, + q31_t * pDst, + q31_t * pScratchIn, + uint32_t blockSize); + + /** + * @brief Initialization function for the Q31 sparse FIR filter. + * @param[in,out] *S points to an instance of the Q31 sparse FIR structure. + * @param[in] numTaps number of nonzero coefficients in the filter. + * @param[in] *pCoeffs points to the array of filter coefficients. + * @param[in] *pState points to the state buffer. + * @param[in] *pTapDelay points to the array of offset times. + * @param[in] maxDelay maximum offset time supported. + * @param[in] blockSize number of samples that will be processed per block. + * @return none + */ + + void arm_fir_sparse_init_q31( + arm_fir_sparse_instance_q31 * S, + uint16_t numTaps, + q31_t * pCoeffs, + q31_t * pState, + int32_t * pTapDelay, + uint16_t maxDelay, + uint32_t blockSize); + + /** + * @brief Processing function for the Q15 sparse FIR filter. + * @param[in] *S points to an instance of the Q15 sparse FIR structure. + * @param[in] *pSrc points to the block of input data. + * @param[out] *pDst points to the block of output data + * @param[in] *pScratchIn points to a temporary buffer of size blockSize. + * @param[in] *pScratchOut points to a temporary buffer of size blockSize. + * @param[in] blockSize number of input samples to process per call. + * @return none. + */ + + void arm_fir_sparse_q15( + arm_fir_sparse_instance_q15 * S, + q15_t * pSrc, + q15_t * pDst, + q15_t * pScratchIn, + q31_t * pScratchOut, + uint32_t blockSize); + + + /** + * @brief Initialization function for the Q15 sparse FIR filter. + * @param[in,out] *S points to an instance of the Q15 sparse FIR structure. + * @param[in] numTaps number of nonzero coefficients in the filter. + * @param[in] *pCoeffs points to the array of filter coefficients. + * @param[in] *pState points to the state buffer. + * @param[in] *pTapDelay points to the array of offset times. + * @param[in] maxDelay maximum offset time supported. + * @param[in] blockSize number of samples that will be processed per block. + * @return none + */ + + void arm_fir_sparse_init_q15( + arm_fir_sparse_instance_q15 * S, + uint16_t numTaps, + q15_t * pCoeffs, + q15_t * pState, + int32_t * pTapDelay, + uint16_t maxDelay, + uint32_t blockSize); + + /** + * @brief Processing function for the Q7 sparse FIR filter. + * @param[in] *S points to an instance of the Q7 sparse FIR structure. + * @param[in] *pSrc points to the block of input data. + * @param[out] *pDst points to the block of output data + * @param[in] *pScratchIn points to a temporary buffer of size blockSize. + * @param[in] *pScratchOut points to a temporary buffer of size blockSize. + * @param[in] blockSize number of input samples to process per call. + * @return none. + */ + + void arm_fir_sparse_q7( + arm_fir_sparse_instance_q7 * S, + q7_t * pSrc, + q7_t * pDst, + q7_t * pScratchIn, + q31_t * pScratchOut, + uint32_t blockSize); + + /** + * @brief Initialization function for the Q7 sparse FIR filter. + * @param[in,out] *S points to an instance of the Q7 sparse FIR structure. + * @param[in] numTaps number of nonzero coefficients in the filter. + * @param[in] *pCoeffs points to the array of filter coefficients. + * @param[in] *pState points to the state buffer. + * @param[in] *pTapDelay points to the array of offset times. + * @param[in] maxDelay maximum offset time supported. + * @param[in] blockSize number of samples that will be processed per block. + * @return none + */ + + void arm_fir_sparse_init_q7( + arm_fir_sparse_instance_q7 * S, + uint16_t numTaps, + q7_t * pCoeffs, + q7_t * pState, + int32_t * pTapDelay, + uint16_t maxDelay, + uint32_t blockSize); + + + /* + * @brief Floating-point sin_cos function. + * @param[in] theta input value in degrees + * @param[out] *pSinVal points to the processed sine output. + * @param[out] *pCosVal points to the processed cos output. + * @return none. + */ + + void arm_sin_cos_f32( + float32_t theta, + float32_t * pSinVal, + float32_t * pCcosVal); + + /* + * @brief Q31 sin_cos function. + * @param[in] theta scaled input value in degrees + * @param[out] *pSinVal points to the processed sine output. + * @param[out] *pCosVal points to the processed cosine output. + * @return none. + */ + + void arm_sin_cos_q31( + q31_t theta, + q31_t * pSinVal, + q31_t * pCosVal); + + + /** + * @brief Floating-point complex conjugate. + * @param[in] *pSrc points to the input vector + * @param[out] *pDst points to the output vector + * @param[in] numSamples number of complex samples in each vector + * @return none. + */ + + void arm_cmplx_conj_f32( + float32_t * pSrc, + float32_t * pDst, + uint32_t numSamples); + + /** + * @brief Q31 complex conjugate. + * @param[in] *pSrc points to the input vector + * @param[out] *pDst points to the output vector + * @param[in] numSamples number of complex samples in each vector + * @return none. + */ + + void arm_cmplx_conj_q31( + q31_t * pSrc, + q31_t * pDst, + uint32_t numSamples); + + /** + * @brief Q15 complex conjugate. + * @param[in] *pSrc points to the input vector + * @param[out] *pDst points to the output vector + * @param[in] numSamples number of complex samples in each vector + * @return none. + */ + + void arm_cmplx_conj_q15( + q15_t * pSrc, + q15_t * pDst, + uint32_t numSamples); + + + + /** + * @brief Floating-point complex magnitude squared + * @param[in] *pSrc points to the complex input vector + * @param[out] *pDst points to the real output vector + * @param[in] numSamples number of complex samples in the input vector + * @return none. + */ + + void arm_cmplx_mag_squared_f32( + float32_t * pSrc, + float32_t * pDst, + uint32_t numSamples); + + /** + * @brief Q31 complex magnitude squared + * @param[in] *pSrc points to the complex input vector + * @param[out] *pDst points to the real output vector + * @param[in] numSamples number of complex samples in the input vector + * @return none. + */ + + void arm_cmplx_mag_squared_q31( + q31_t * pSrc, + q31_t * pDst, + uint32_t numSamples); + + /** + * @brief Q15 complex magnitude squared + * @param[in] *pSrc points to the complex input vector + * @param[out] *pDst points to the real output vector + * @param[in] numSamples number of complex samples in the input vector + * @return none. + */ + + void arm_cmplx_mag_squared_q15( + q15_t * pSrc, + q15_t * pDst, + uint32_t numSamples); + + + /** + * @ingroup groupController + */ + + /** + * @defgroup PID PID Motor Control + * + * A Proportional Integral Derivative (PID) controller is a generic feedback control + * loop mechanism widely used in industrial control systems. + * A PID controller is the most commonly used type of feedback controller. + * + * This set of functions implements (PID) controllers + * for Q15, Q31, and floating-point data types. The functions operate on a single sample + * of data and each call to the function returns a single processed value. + * S points to an instance of the PID control data structure. in + * is the input sample value. The functions return the output value. + * + * \par Algorithm: + * 
    +   *    y[n] = y[n-1] + A0 * x[n] + A1 * x[n-1] + A2 * x[n-2]
+   *    A0 = Kp + Ki + Kd
+   *    A1 = (-Kp ) - (2 * Kd )
+   *    A2 = Kd
    + * + * \par + * where \c Kp is proportional constant, \c Ki is Integral constant and \c Kd is Derivative constant + * + * \par + * \image html PID.gif "Proportional Integral Derivative Controller" + * + * \par + * The PID controller calculates an "error" value as the difference between + * the measured output and the reference input. + * The controller attempts to minimize the error by adjusting the process control inputs. + * The proportional value determines the reaction to the current error, + * the integral value determines the reaction based on the sum of recent errors, + * and the derivative value determines the reaction based on the rate at which the error has been changing. + * + * \par Instance Structure + * The Gains A0, A1, A2 and state variables for a PID controller are stored together in an instance data structure. + * A separate instance structure must be defined for each PID Controller. + * There are separate instance structure declarations for each of the 3 supported data types. + * + * \par Reset Functions + * There is also an associated reset function for each data type which clears the state array. + * + * \par Initialization Functions + * There is also an associated initialization function for each data type. + * The initialization function performs the following operations: + * - Initializes the Gains A0, A1, A2 from Kp,Ki, Kd gains. + * - Zeros out the values in the state buffer. + * + * \par + * Instance structure cannot be placed into a const data section and it is recommended to use the initialization function. + * + * \par Fixed-Point Behavior + * Care must be taken when using the fixed-point versions of the PID Controller functions. + * In particular, the overflow and saturation behavior of the accumulator used in each function must be considered. + * Refer to the function specific documentation below for usage guidelines. + */ + + /** + * @addtogroup PID + * @{ + */ + + /** + * @brief Process function for the floating-point PID Control. + * @param[in,out] *S is an instance of the floating-point PID Control structure + * @param[in] in input sample to process + * @return out processed output sample. + */ + + + __STATIC_INLINE float32_t arm_pid_f32( + arm_pid_instance_f32 * S, + float32_t in) + { + float32_t out; + + /* y[n] = y[n-1] + A0 * x[n] + A1 * x[n-1] + A2 * x[n-2] */ + out = (S->A0 * in) + + (S->A1 * S->state[0]) + (S->A2 * S->state[1]) + (S->state[2]); + + /* Update state */ + S->state[1] = S->state[0]; + S->state[0] = in; + S->state[2] = out; + + /* return to application */ + return (out); + + } + + /** + * @brief Process function for the Q31 PID Control. + * @param[in,out] *S points to an instance of the Q31 PID Control structure + * @param[in] in input sample to process + * @return out processed output sample. + * + * Scaling and Overflow Behavior: + * \par + * The function is implemented using an internal 64-bit accumulator. + * The accumulator has a 2.62 format and maintains full precision of the intermediate multiplication results but provides only a single guard bit. + * Thus, if the accumulator result overflows it wraps around rather than clip. + * In order to avoid overflows completely the input signal must be scaled down by 2 bits as there are four additions. + * After all multiply-accumulates are performed, the 2.62 accumulator is truncated to 1.32 format and then saturated to 1.31 format. + */ + + __STATIC_INLINE q31_t arm_pid_q31( + arm_pid_instance_q31 * S, + q31_t in) + { + q63_t acc; + q31_t out; + + /* acc = A0 * x[n] */ + acc = (q63_t) S->A0 * in; + + /* acc += A1 * x[n-1] */ + acc += (q63_t) S->A1 * S->state[0]; + + /* acc += A2 * x[n-2] */ + acc += (q63_t) S->A2 * S->state[1]; + + /* convert output to 1.31 format to add y[n-1] */ + out = (q31_t) (acc >> 31u); + + /* out += y[n-1] */ + out += S->state[2]; + + /* Update state */ + S->state[1] = S->state[0]; + S->state[0] = in; + S->state[2] = out; + + /* return to application */ + return (out); + + } + + /** + * @brief Process function for the Q15 PID Control. + * @param[in,out] *S points to an instance of the Q15 PID Control structure + * @param[in] in input sample to process + * @return out processed output sample. + * + * Scaling and Overflow Behavior: + * \par + * The function is implemented using a 64-bit internal accumulator. + * Both Gains and state variables are represented in 1.15 format and multiplications yield a 2.30 result. + * The 2.30 intermediate results are accumulated in a 64-bit accumulator in 34.30 format. + * There is no risk of internal overflow with this approach and the full precision of intermediate multiplications is preserved. + * After all additions have been performed, the accumulator is truncated to 34.15 format by discarding low 15 bits. + * Lastly, the accumulator is saturated to yield a result in 1.15 format. + */ + + __STATIC_INLINE q15_t arm_pid_q15( + arm_pid_instance_q15 * S, + q15_t in) + { + q63_t acc; + q15_t out; + + /* Implementation of PID controller */ + +#ifdef ARM_MATH_CM0 + + /* acc = A0 * x[n] */ + acc = ((q31_t) S->A0) * in; + +#else + + /* acc = A0 * x[n] */ + acc = (q31_t) __SMUAD(S->A0, in); + +#endif + +#ifdef ARM_MATH_CM0 + + /* acc += A1 * x[n-1] + A2 * x[n-2] */ + acc += (q31_t) S->A1 * S->state[0]; + acc += (q31_t) S->A2 * S->state[1]; + +#else + + /* acc += A1 * x[n-1] + A2 * x[n-2] */ + acc = __SMLALD(S->A1, (q31_t) __SIMD32(S->state), acc); + +#endif + + /* acc += y[n-1] */ + acc += (q31_t) S->state[2] << 15; + + /* saturate the output */ + out = (q15_t) (__SSAT((acc >> 15), 16)); + + /* Update state */ + S->state[1] = S->state[0]; + S->state[0] = in; + S->state[2] = out; + + /* return to application */ + return (out); + + } + + /** + * @} end of PID group + */ + + + /** + * @brief Floating-point matrix inverse. + * @param[in] *src points to the instance of the input floating-point matrix structure. + * @param[out] *dst points to the instance of the output floating-point matrix structure. + * @return The function returns ARM_MATH_SIZE_MISMATCH, if the dimensions do not match. + * If the input matrix is singular (does not have an inverse), then the algorithm terminates and returns error status ARM_MATH_SINGULAR. + */ + + arm_status arm_mat_inverse_f32( + const arm_matrix_instance_f32 * src, + arm_matrix_instance_f32 * dst); + + + + /** + * @ingroup groupController + */ + + + /** + * @defgroup clarke Vector Clarke Transform + * Forward Clarke transform converts the instantaneous stator phases into a two-coordinate time invariant vector. + * Generally the Clarke transform uses three-phase currents Ia, Ib and Ic to calculate currents + * in the two-phase orthogonal stator axis Ialpha and Ibeta. + * When Ialpha is superposed with Ia as shown in the figure below + * \image html clarke.gif Stator current space vector and its components in (a,b). + * and Ia + Ib + Ic = 0, in this condition Ialpha and Ibeta + * can be calculated using only Ia and Ib. + * + * The function operates on a single sample of data and each call to the function returns the processed output. + * The library provides separate functions for Q31 and floating-point data types. + * \par Algorithm + * \image html clarkeFormula.gif + * where Ia and Ib are the instantaneous stator phases and + * pIalpha and pIbeta are the two coordinates of time invariant vector. + * \par Fixed-Point Behavior + * Care must be taken when using the Q31 version of the Clarke transform. + * In particular, the overflow and saturation behavior of the accumulator used must be considered. + * Refer to the function specific documentation below for usage guidelines. + */ + + /** + * @addtogroup clarke + * @{ + */ + + /** + * + * @brief Floating-point Clarke transform + * @param[in] Ia input three-phase coordinate a + * @param[in] Ib input three-phase coordinate b + * @param[out] *pIalpha points to output two-phase orthogonal vector axis alpha + * @param[out] *pIbeta points to output two-phase orthogonal vector axis beta + * @return none. + */ + + __STATIC_INLINE void arm_clarke_f32( + float32_t Ia, + float32_t Ib, + float32_t * pIalpha, + float32_t * pIbeta) + { + /* Calculate pIalpha using the equation, pIalpha = Ia */ + *pIalpha = Ia; + + /* Calculate pIbeta using the equation, pIbeta = (1/sqrt(3)) * Ia + (2/sqrt(3)) * Ib */ + *pIbeta = + ((float32_t) 0.57735026919 * Ia + (float32_t) 1.15470053838 * Ib); + + } + + /** + * @brief Clarke transform for Q31 version + * @param[in] Ia input three-phase coordinate a + * @param[in] Ib input three-phase coordinate b + * @param[out] *pIalpha points to output two-phase orthogonal vector axis alpha + * @param[out] *pIbeta points to output two-phase orthogonal vector axis beta + * @return none. + * + * Scaling and Overflow Behavior: + * \par + * The function is implemented using an internal 32-bit accumulator. + * The accumulator maintains 1.31 format by truncating lower 31 bits of the intermediate multiplication in 2.62 format. + * There is saturation on the addition, hence there is no risk of overflow. + */ + + __STATIC_INLINE void arm_clarke_q31( + q31_t Ia, + q31_t Ib, + q31_t * pIalpha, + q31_t * pIbeta) + { + q31_t product1, product2; /* Temporary variables used to store intermediate results */ + + /* Calculating pIalpha from Ia by equation pIalpha = Ia */ + *pIalpha = Ia; + + /* Intermediate product is calculated by (1/(sqrt(3)) * Ia) */ + product1 = (q31_t) (((q63_t) Ia * 0x24F34E8B) >> 30); + + /* Intermediate product is calculated by (2/sqrt(3) * Ib) */ + product2 = (q31_t) (((q63_t) Ib * 0x49E69D16) >> 30); + + /* pIbeta is calculated by adding the intermediate products */ + *pIbeta = __QADD(product1, product2); + } + + /** + * @} end of clarke group + */ + + /** + * @brief Converts the elements of the Q7 vector to Q31 vector. + * @param[in] *pSrc input pointer + * @param[out] *pDst output pointer + * @param[in] blockSize number of samples to process + * @return none. + */ + void arm_q7_to_q31( + q7_t * pSrc, + q31_t * pDst, + uint32_t blockSize); + + + + + /** + * @ingroup groupController + */ + + /** + * @defgroup inv_clarke Vector Inverse Clarke Transform + * Inverse Clarke transform converts the two-coordinate time invariant vector into instantaneous stator phases. + * + * The function operates on a single sample of data and each call to the function returns the processed output. + * The library provides separate functions for Q31 and floating-point data types. + * \par Algorithm + * \image html clarkeInvFormula.gif + * where pIa and pIb are the instantaneous stator phases and + * Ialpha and Ibeta are the two coordinates of time invariant vector. + * \par Fixed-Point Behavior + * Care must be taken when using the Q31 version of the Clarke transform. + * In particular, the overflow and saturation behavior of the accumulator used must be considered. + * Refer to the function specific documentation below for usage guidelines. + */ + + /** + * @addtogroup inv_clarke + * @{ + */ + + /** + * @brief Floating-point Inverse Clarke transform + * @param[in] Ialpha input two-phase orthogonal vector axis alpha + * @param[in] Ibeta input two-phase orthogonal vector axis beta + * @param[out] *pIa points to output three-phase coordinate a + * @param[out] *pIb points to output three-phase coordinate b + * @return none. + */ + + + __STATIC_INLINE void arm_inv_clarke_f32( + float32_t Ialpha, + float32_t Ibeta, + float32_t * pIa, + float32_t * pIb) + { + /* Calculating pIa from Ialpha by equation pIa = Ialpha */ + *pIa = Ialpha; + + /* Calculating pIb from Ialpha and Ibeta by equation pIb = -(1/2) * Ialpha + (sqrt(3)/2) * Ibeta */ + *pIb = -0.5 * Ialpha + (float32_t) 0.8660254039 *Ibeta; + + } + + /** + * @brief Inverse Clarke transform for Q31 version + * @param[in] Ialpha input two-phase orthogonal vector axis alpha + * @param[in] Ibeta input two-phase orthogonal vector axis beta + * @param[out] *pIa points to output three-phase coordinate a + * @param[out] *pIb points to output three-phase coordinate b + * @return none. + * + * Scaling and Overflow Behavior: + * \par + * The function is implemented using an internal 32-bit accumulator. + * The accumulator maintains 1.31 format by truncating lower 31 bits of the intermediate multiplication in 2.62 format. + * There is saturation on the subtraction, hence there is no risk of overflow. + */ + + __STATIC_INLINE void arm_inv_clarke_q31( + q31_t Ialpha, + q31_t Ibeta, + q31_t * pIa, + q31_t * pIb) + { + q31_t product1, product2; /* Temporary variables used to store intermediate results */ + + /* Calculating pIa from Ialpha by equation pIa = Ialpha */ + *pIa = Ialpha; + + /* Intermediate product is calculated by (1/(2*sqrt(3)) * Ia) */ + product1 = (q31_t) (((q63_t) (Ialpha) * (0x40000000)) >> 31); + + /* Intermediate product is calculated by (1/sqrt(3) * pIb) */ + product2 = (q31_t) (((q63_t) (Ibeta) * (0x6ED9EBA1)) >> 31); + + /* pIb is calculated by subtracting the products */ + *pIb = __QSUB(product2, product1); + + } + + /** + * @} end of inv_clarke group + */ + + /** + * @brief Converts the elements of the Q7 vector to Q15 vector. + * @param[in] *pSrc input pointer + * @param[out] *pDst output pointer + * @param[in] blockSize number of samples to process + * @return none. + */ + void arm_q7_to_q15( + q7_t * pSrc, + q15_t * pDst, + uint32_t blockSize); + + + + /** + * @ingroup groupController + */ + + /** + * @defgroup park Vector Park Transform + * + * Forward Park transform converts the input two-coordinate vector to flux and torque components. + * The Park transform can be used to realize the transformation of the Ialpha and the Ibeta currents + * from the stationary to the moving reference frame and control the spatial relationship between + * the stator vector current and rotor flux vector. + * If we consider the d axis aligned with the rotor flux, the diagram below shows the + * current vector and the relationship from the two reference frames: + * \image html park.gif "Stator current space vector and its component in (a,b) and in the d,q rotating reference frame" + * + * The function operates on a single sample of data and each call to the function returns the processed output. + * The library provides separate functions for Q31 and floating-point data types. + * \par Algorithm + * \image html parkFormula.gif + * where Ialpha and Ibeta are the stator vector components, + * pId and pIq are rotor vector components and cosVal and sinVal are the + * cosine and sine values of theta (rotor flux position). + * \par Fixed-Point Behavior + * Care must be taken when using the Q31 version of the Park transform. + * In particular, the overflow and saturation behavior of the accumulator used must be considered. + * Refer to the function specific documentation below for usage guidelines. + */ + + /** + * @addtogroup park + * @{ + */ + + /** + * @brief Floating-point Park transform + * @param[in] Ialpha input two-phase vector coordinate alpha + * @param[in] Ibeta input two-phase vector coordinate beta + * @param[out] *pId points to output rotor reference frame d + * @param[out] *pIq points to output rotor reference frame q + * @param[in] sinVal sine value of rotation angle theta + * @param[in] cosVal cosine value of rotation angle theta + * @return none. + * + * The function implements the forward Park transform. + * + */ + + __STATIC_INLINE void arm_park_f32( + float32_t Ialpha, + float32_t Ibeta, + float32_t * pId, + float32_t * pIq, + float32_t sinVal, + float32_t cosVal) + { + /* Calculate pId using the equation, pId = Ialpha * cosVal + Ibeta * sinVal */ + *pId = Ialpha * cosVal + Ibeta * sinVal; + + /* Calculate pIq using the equation, pIq = - Ialpha * sinVal + Ibeta * cosVal */ + *pIq = -Ialpha * sinVal + Ibeta * cosVal; + + } + + /** + * @brief Park transform for Q31 version + * @param[in] Ialpha input two-phase vector coordinate alpha + * @param[in] Ibeta input two-phase vector coordinate beta + * @param[out] *pId points to output rotor reference frame d + * @param[out] *pIq points to output rotor reference frame q + * @param[in] sinVal sine value of rotation angle theta + * @param[in] cosVal cosine value of rotation angle theta + * @return none. + * + * Scaling and Overflow Behavior: + * \par + * The function is implemented using an internal 32-bit accumulator. + * The accumulator maintains 1.31 format by truncating lower 31 bits of the intermediate multiplication in 2.62 format. + * There is saturation on the addition and subtraction, hence there is no risk of overflow. + */ + + + __STATIC_INLINE void arm_park_q31( + q31_t Ialpha, + q31_t Ibeta, + q31_t * pId, + q31_t * pIq, + q31_t sinVal, + q31_t cosVal) + { + q31_t product1, product2; /* Temporary variables used to store intermediate results */ + q31_t product3, product4; /* Temporary variables used to store intermediate results */ + + /* Intermediate product is calculated by (Ialpha * cosVal) */ + product1 = (q31_t) (((q63_t) (Ialpha) * (cosVal)) >> 31); + + /* Intermediate product is calculated by (Ibeta * sinVal) */ + product2 = (q31_t) (((q63_t) (Ibeta) * (sinVal)) >> 31); + + + /* Intermediate product is calculated by (Ialpha * sinVal) */ + product3 = (q31_t) (((q63_t) (Ialpha) * (sinVal)) >> 31); + + /* Intermediate product is calculated by (Ibeta * cosVal) */ + product4 = (q31_t) (((q63_t) (Ibeta) * (cosVal)) >> 31); + + /* Calculate pId by adding the two intermediate products 1 and 2 */ + *pId = __QADD(product1, product2); + + /* Calculate pIq by subtracting the two intermediate products 3 from 4 */ + *pIq = __QSUB(product4, product3); + } + + /** + * @} end of park group + */ + + /** + * @brief Converts the elements of the Q7 vector to floating-point vector. + * @param[in] *pSrc is input pointer + * @param[out] *pDst is output pointer + * @param[in] blockSize is the number of samples to process + * @return none. + */ + void arm_q7_to_float( + q7_t * pSrc, + float32_t * pDst, + uint32_t blockSize); + + + /** + * @ingroup groupController + */ + + /** + * @defgroup inv_park Vector Inverse Park transform + * Inverse Park transform converts the input flux and torque components to two-coordinate vector. + * + * The function operates on a single sample of data and each call to the function returns the processed output. + * The library provides separate functions for Q31 and floating-point data types. + * \par Algorithm + * \image html parkInvFormula.gif + * where pIalpha and pIbeta are the stator vector components, + * Id and Iq are rotor vector components and cosVal and sinVal are the + * cosine and sine values of theta (rotor flux position). + * \par Fixed-Point Behavior + * Care must be taken when using the Q31 version of the Park transform. + * In particular, the overflow and saturation behavior of the accumulator used must be considered. + * Refer to the function specific documentation below for usage guidelines. + */ + + /** + * @addtogroup inv_park + * @{ + */ + + /** + * @brief Floating-point Inverse Park transform + * @param[in] Id input coordinate of rotor reference frame d + * @param[in] Iq input coordinate of rotor reference frame q + * @param[out] *pIalpha points to output two-phase orthogonal vector axis alpha + * @param[out] *pIbeta points to output two-phase orthogonal vector axis beta + * @param[in] sinVal sine value of rotation angle theta + * @param[in] cosVal cosine value of rotation angle theta + * @return none. + */ + + __STATIC_INLINE void arm_inv_park_f32( + float32_t Id, + float32_t Iq, + float32_t * pIalpha, + float32_t * pIbeta, + float32_t sinVal, + float32_t cosVal) + { + /* Calculate pIalpha using the equation, pIalpha = Id * cosVal - Iq * sinVal */ + *pIalpha = Id * cosVal - Iq * sinVal; + + /* Calculate pIbeta using the equation, pIbeta = Id * sinVal + Iq * cosVal */ + *pIbeta = Id * sinVal + Iq * cosVal; + + } + + + /** + * @brief Inverse Park transform for Q31 version + * @param[in] Id input coordinate of rotor reference frame d + * @param[in] Iq input coordinate of rotor reference frame q + * @param[out] *pIalpha points to output two-phase orthogonal vector axis alpha + * @param[out] *pIbeta points to output two-phase orthogonal vector axis beta + * @param[in] sinVal sine value of rotation angle theta + * @param[in] cosVal cosine value of rotation angle theta + * @return none. + * + * Scaling and Overflow Behavior: + * \par + * The function is implemented using an internal 32-bit accumulator. + * The accumulator maintains 1.31 format by truncating lower 31 bits of the intermediate multiplication in 2.62 format. + * There is saturation on the addition, hence there is no risk of overflow. + */ + + + __STATIC_INLINE void arm_inv_park_q31( + q31_t Id, + q31_t Iq, + q31_t * pIalpha, + q31_t * pIbeta, + q31_t sinVal, + q31_t cosVal) + { + q31_t product1, product2; /* Temporary variables used to store intermediate results */ + q31_t product3, product4; /* Temporary variables used to store intermediate results */ + + /* Intermediate product is calculated by (Id * cosVal) */ + product1 = (q31_t) (((q63_t) (Id) * (cosVal)) >> 31); + + /* Intermediate product is calculated by (Iq * sinVal) */ + product2 = (q31_t) (((q63_t) (Iq) * (sinVal)) >> 31); + + + /* Intermediate product is calculated by (Id * sinVal) */ + product3 = (q31_t) (((q63_t) (Id) * (sinVal)) >> 31); + + /* Intermediate product is calculated by (Iq * cosVal) */ + product4 = (q31_t) (((q63_t) (Iq) * (cosVal)) >> 31); + + /* Calculate pIalpha by using the two intermediate products 1 and 2 */ + *pIalpha = __QSUB(product1, product2); + + /* Calculate pIbeta by using the two intermediate products 3 and 4 */ + *pIbeta = __QADD(product4, product3); + + } + + /** + * @} end of Inverse park group + */ + + + /** + * @brief Converts the elements of the Q31 vector to floating-point vector. + * @param[in] *pSrc is input pointer + * @param[out] *pDst is output pointer + * @param[in] blockSize is the number of samples to process + * @return none. + */ + void arm_q31_to_float( + q31_t * pSrc, + float32_t * pDst, + uint32_t blockSize); + + /** + * @ingroup groupInterpolation + */ + + /** + * @defgroup LinearInterpolate Linear Interpolation + * + * Linear interpolation is a method of curve fitting using linear polynomials. + * Linear interpolation works by effectively drawing a straight line between two neighboring samples and returning the appropriate point along that line + * + * \par + * \image html LinearInterp.gif "Linear interpolation" + * + * \par + * A Linear Interpolate function calculates an output value(y), for the input(x) + * using linear interpolation of the input values x0, x1( nearest input values) and the output values y0 and y1(nearest output values) + * + * \par Algorithm: + * 
    +   *       y = y0 + (x - x0) * ((y1 - y0)/(x1-x0))
+   *       where x0, x1 are nearest values of input x
+   *             y0, y1 are nearest values to output y
+   *
    + * + * \par + * This set of functions implements Linear interpolation process + * for Q7, Q15, Q31, and floating-point data types. The functions operate on a single + * sample of data and each call to the function returns a single processed value. + * S points to an instance of the Linear Interpolate function data structure. + * x is the input sample value. The functions returns the output value. + * + * \par + * if x is outside of the table boundary, Linear interpolation returns first value of the table + * if x is below input range and returns last value of table if x is above range. + */ + + /** + * @addtogroup LinearInterpolate + * @{ + */ + + /** + * @brief Process function for the floating-point Linear Interpolation Function. + * @param[in,out] *S is an instance of the floating-point Linear Interpolation structure + * @param[in] x input sample to process + * @return y processed output sample. + * + */ + + __STATIC_INLINE float32_t arm_linear_interp_f32( + arm_linear_interp_instance_f32 * S, + float32_t x) + { + + float32_t y; + float32_t x0, x1; /* Nearest input values */ + float32_t y0, y1; /* Nearest output values */ + float32_t xSpacing = S->xSpacing; /* spacing between input values */ + int32_t i; /* Index variable */ + float32_t *pYData = S->pYData; /* pointer to output table */ + + /* Calculation of index */ + i = (x - S->x1) / xSpacing; + + if(i < 0) + { + /* Iniatilize output for below specified range as least output value of table */ + y = pYData[0]; + } + else if(i >= S->nValues) + { + /* Iniatilize output for above specified range as last output value of table */ + y = pYData[S->nValues - 1]; + } + else + { + /* Calculation of nearest input values */ + x0 = S->x1 + i * xSpacing; + x1 = S->x1 + (i + 1) * xSpacing; + + /* Read of nearest output values */ + y0 = pYData[i]; + y1 = pYData[i + 1]; + + /* Calculation of output */ + y = y0 + (x - x0) * ((y1 - y0) / (x1 - x0)); + + } + + /* returns output value */ + return (y); + } + + /** + * + * @brief Process function for the Q31 Linear Interpolation Function. + * @param[in] *pYData pointer to Q31 Linear Interpolation table + * @param[in] x input sample to process + * @param[in] nValues number of table values + * @return y processed output sample. + * + * \par + * Input sample x is in 12.20 format which contains 12 bits for table index and 20 bits for fractional part. + * This function can support maximum of table size 2^12. + * + */ + + + __STATIC_INLINE q31_t arm_linear_interp_q31( + q31_t * pYData, + q31_t x, + uint32_t nValues) + { + q31_t y; /* output */ + q31_t y0, y1; /* Nearest output values */ + q31_t fract; /* fractional part */ + int32_t index; /* Index to read nearest output values */ + + /* Input is in 12.20 format */ + /* 12 bits for the table index */ + /* Index value calculation */ + index = ((x & 0xFFF00000) >> 20); + + if(index >= (nValues - 1)) + { + return (pYData[nValues - 1]); + } + else if(index < 0) + { + return (pYData[0]); + } + else + { + + /* 20 bits for the fractional part */ + /* shift left by 11 to keep fract in 1.31 format */ + fract = (x & 0x000FFFFF) << 11; + + /* Read two nearest output values from the index in 1.31(q31) format */ + y0 = pYData[index]; + y1 = pYData[index + 1u]; + + /* Calculation of y0 * (1-fract) and y is in 2.30 format */ + y = ((q31_t) ((q63_t) y0 * (0x7FFFFFFF - fract) >> 32)); + + /* Calculation of y0 * (1-fract) + y1 *fract and y is in 2.30 format */ + y += ((q31_t) (((q63_t) y1 * fract) >> 32)); + + /* Convert y to 1.31 format */ + return (y << 1u); + + } + + } + + /** + * + * @brief Process function for the Q15 Linear Interpolation Function. + * @param[in] *pYData pointer to Q15 Linear Interpolation table + * @param[in] x input sample to process + * @param[in] nValues number of table values + * @return y processed output sample. + * + * \par + * Input sample x is in 12.20 format which contains 12 bits for table index and 20 bits for fractional part. + * This function can support maximum of table size 2^12. + * + */ + + + __STATIC_INLINE q15_t arm_linear_interp_q15( + q15_t * pYData, + q31_t x, + uint32_t nValues) + { + q63_t y; /* output */ + q15_t y0, y1; /* Nearest output values */ + q31_t fract; /* fractional part */ + int32_t index; /* Index to read nearest output values */ + + /* Input is in 12.20 format */ + /* 12 bits for the table index */ + /* Index value calculation */ + index = ((x & 0xFFF00000) >> 20u); + + if(index >= (nValues - 1)) + { + return (pYData[nValues - 1]); + } + else if(index < 0) + { + return (pYData[0]); + } + else + { + /* 20 bits for the fractional part */ + /* fract is in 12.20 format */ + fract = (x & 0x000FFFFF); + + /* Read two nearest output values from the index */ + y0 = pYData[index]; + y1 = pYData[index + 1u]; + + /* Calculation of y0 * (1-fract) and y is in 13.35 format */ + y = ((q63_t) y0 * (0xFFFFF - fract)); + + /* Calculation of (y0 * (1-fract) + y1 * fract) and y is in 13.35 format */ + y += ((q63_t) y1 * (fract)); + + /* convert y to 1.15 format */ + return (y >> 20); + } + + + } + + /** + * + * @brief Process function for the Q7 Linear Interpolation Function. + * @param[in] *pYData pointer to Q7 Linear Interpolation table + * @param[in] x input sample to process + * @param[in] nValues number of table values + * @return y processed output sample. + * + * \par + * Input sample x is in 12.20 format which contains 12 bits for table index and 20 bits for fractional part. + * This function can support maximum of table size 2^12. + */ + + + __STATIC_INLINE q7_t arm_linear_interp_q7( + q7_t * pYData, + q31_t x, + uint32_t nValues) + { + q31_t y; /* output */ + q7_t y0, y1; /* Nearest output values */ + q31_t fract; /* fractional part */ + int32_t index; /* Index to read nearest output values */ + + /* Input is in 12.20 format */ + /* 12 bits for the table index */ + /* Index value calculation */ + index = ((x & 0xFFF00000) >> 20u); + + + if(index >= (nValues - 1)) + { + return (pYData[nValues - 1]); + } + else if(index < 0) + { + return (pYData[0]); + } + else + { + + /* 20 bits for the fractional part */ + /* fract is in 12.20 format */ + fract = (x & 0x000FFFFF); + + /* Read two nearest output values from the index and are in 1.7(q7) format */ + y0 = pYData[index]; + y1 = pYData[index + 1u]; + + /* Calculation of y0 * (1-fract ) and y is in 13.27(q27) format */ + y = ((y0 * (0xFFFFF - fract))); + + /* Calculation of y1 * fract + y0 * (1-fract) and y is in 13.27(q27) format */ + y += (y1 * fract); + + /* convert y to 1.7(q7) format */ + return (y >> 20u); + + } + + } + /** + * @} end of LinearInterpolate group + */ + + /** + * @brief Fast approximation to the trigonometric sine function for floating-point data. + * @param[in] x input value in radians. + * @return sin(x). + */ + + float32_t arm_sin_f32( + float32_t x); + + /** + * @brief Fast approximation to the trigonometric sine function for Q31 data. + * @param[in] x Scaled input value in radians. + * @return sin(x). + */ + + q31_t arm_sin_q31( + q31_t x); + + /** + * @brief Fast approximation to the trigonometric sine function for Q15 data. + * @param[in] x Scaled input value in radians. + * @return sin(x). + */ + + q15_t arm_sin_q15( + q15_t x); + + /** + * @brief Fast approximation to the trigonometric cosine function for floating-point data. + * @param[in] x input value in radians. + * @return cos(x). + */ + + float32_t arm_cos_f32( + float32_t x); + + /** + * @brief Fast approximation to the trigonometric cosine function for Q31 data. + * @param[in] x Scaled input value in radians. + * @return cos(x). + */ + + q31_t arm_cos_q31( + q31_t x); + + /** + * @brief Fast approximation to the trigonometric cosine function for Q15 data. + * @param[in] x Scaled input value in radians. + * @return cos(x). + */ + + q15_t arm_cos_q15( + q15_t x); + + + /** + * @ingroup groupFastMath + */ + + + /** + * @defgroup SQRT Square Root + * + * Computes the square root of a number. + * There are separate functions for Q15, Q31, and floating-point data types. + * The square root function is computed using the Newton-Raphson algorithm. + * This is an iterative algorithm of the form: + * 
    +   *      x1 = x0 - f(x0)/f'(x0)
+   *
    + * where x1 is the current estimate, + * x0 is the previous estimate and + * f'(x0) is the derivative of f() evaluated at x0. + * For the square root function, the algorithm reduces to: + * 
    +   *     x0 = in/2                         [initial guess]
+   *     x1 = 1/2 * ( x0 + in / x0)        [each iteration]
+   *
    + */ + + + /** + * @addtogroup SQRT + * @{ + */ + + /** + * @brief Floating-point square root function. + * @param[in] in input value. + * @param[out] *pOut square root of input value. + * @return The function returns ARM_MATH_SUCCESS if input value is positive value or ARM_MATH_ARGUMENT_ERROR if + * in is negative value and returns zero output for negative values. + */ + + __STATIC_INLINE arm_status arm_sqrt_f32( + float32_t in, + float32_t * pOut) + { + if(in > 0) + { + +// #if __FPU_USED + #if (__FPU_USED == 1) && defined ( __CC_ARM ) + *pOut = __sqrtf(in); + #elif (__FPU_USED == 1) && defined ( __TMS_740 ) + *pOut = __builtin_sqrtf(in); + #else + *pOut = sqrtf(in); + #endif + + return (ARM_MATH_SUCCESS); + } + else + { + *pOut = 0.0f; + return (ARM_MATH_ARGUMENT_ERROR); + } + + } + + + /** + * @brief Q31 square root function. + * @param[in] in input value. The range of the input value is [0 +1) or 0x00000000 to 0x7FFFFFFF. + * @param[out] *pOut square root of input value. + * @return The function returns ARM_MATH_SUCCESS if input value is positive value or ARM_MATH_ARGUMENT_ERROR if + * in is negative value and returns zero output for negative values. + */ + arm_status arm_sqrt_q31( + q31_t in, + q31_t * pOut); + + /** + * @brief Q15 square root function. + * @param[in] in input value. The range of the input value is [0 +1) or 0x0000 to 0x7FFF. + * @param[out] *pOut square root of input value. + * @return The function returns ARM_MATH_SUCCESS if input value is positive value or ARM_MATH_ARGUMENT_ERROR if + * in is negative value and returns zero output for negative values. + */ + arm_status arm_sqrt_q15( + q15_t in, + q15_t * pOut); + + /** + * @} end of SQRT group + */ + + + + + + + /** + * @brief floating-point Circular write function. + */ + + __STATIC_INLINE void arm_circularWrite_f32( + int32_t * circBuffer, + int32_t L, + uint16_t * writeOffset, + int32_t bufferInc, + const int32_t * src, + int32_t srcInc, + uint32_t blockSize) + { + uint32_t i = 0u; + int32_t wOffset; + + /* Copy the value of Index pointer that points + * to the current location where the input samples to be copied */ + wOffset = *writeOffset; + + /* Loop over the blockSize */ + i = blockSize; + + while(i > 0u) + { + /* copy the input sample to the circular buffer */ + circBuffer[wOffset] = *src; + + /* Update the input pointer */ + src += srcInc; + + /* Circularly update wOffset. Watch out for positive and negative value */ + wOffset += bufferInc; + if(wOffset >= L) + wOffset -= L; + + /* Decrement the loop counter */ + i--; + } + + /* Update the index pointer */ + *writeOffset = wOffset; + } + + + + /** + * @brief floating-point Circular Read function. + */ + __STATIC_INLINE void arm_circularRead_f32( + int32_t * circBuffer, + int32_t L, + int32_t * readOffset, + int32_t bufferInc, + int32_t * dst, + int32_t * dst_base, + int32_t dst_length, + int32_t dstInc, + uint32_t blockSize) + { + uint32_t i = 0u; + int32_t rOffset, dst_end; + + /* Copy the value of Index pointer that points + * to the current location from where the input samples to be read */ + rOffset = *readOffset; + dst_end = (int32_t) (dst_base + dst_length); + + /* Loop over the blockSize */ + i = blockSize; + + while(i > 0u) + { + /* copy the sample from the circular buffer to the destination buffer */ + *dst = circBuffer[rOffset]; + + /* Update the input pointer */ + dst += dstInc; + + if(dst == (int32_t *) dst_end) + { + dst = dst_base; + } + + /* Circularly update rOffset. Watch out for positive and negative value */ + rOffset += bufferInc; + + if(rOffset >= L) + { + rOffset -= L; + } + + /* Decrement the loop counter */ + i--; + } + + /* Update the index pointer */ + *readOffset = rOffset; + } + + /** + * @brief Q15 Circular write function. + */ + + __STATIC_INLINE void arm_circularWrite_q15( + q15_t * circBuffer, + int32_t L, + uint16_t * writeOffset, + int32_t bufferInc, + const q15_t * src, + int32_t srcInc, + uint32_t blockSize) + { + uint32_t i = 0u; + int32_t wOffset; + + /* Copy the value of Index pointer that points + * to the current location where the input samples to be copied */ + wOffset = *writeOffset; + + /* Loop over the blockSize */ + i = blockSize; + + while(i > 0u) + { + /* copy the input sample to the circular buffer */ + circBuffer[wOffset] = *src; + + /* Update the input pointer */ + src += srcInc; + + /* Circularly update wOffset. Watch out for positive and negative value */ + wOffset += bufferInc; + if(wOffset >= L) + wOffset -= L; + + /* Decrement the loop counter */ + i--; + } + + /* Update the index pointer */ + *writeOffset = wOffset; + } + + + + /** + * @brief Q15 Circular Read function. + */ + __STATIC_INLINE void arm_circularRead_q15( + q15_t * circBuffer, + int32_t L, + int32_t * readOffset, + int32_t bufferInc, + q15_t * dst, + q15_t * dst_base, + int32_t dst_length, + int32_t dstInc, + uint32_t blockSize) + { + uint32_t i = 0; + int32_t rOffset, dst_end; + + /* Copy the value of Index pointer that points + * to the current location from where the input samples to be read */ + rOffset = *readOffset; + + dst_end = (int32_t) (dst_base + dst_length); + + /* Loop over the blockSize */ + i = blockSize; + + while(i > 0u) + { + /* copy the sample from the circular buffer to the destination buffer */ + *dst = circBuffer[rOffset]; + + /* Update the input pointer */ + dst += dstInc; + + if(dst == (q15_t *) dst_end) + { + dst = dst_base; + } + + /* Circularly update wOffset. Watch out for positive and negative value */ + rOffset += bufferInc; + + if(rOffset >= L) + { + rOffset -= L; + } + + /* Decrement the loop counter */ + i--; + } + + /* Update the index pointer */ + *readOffset = rOffset; + } + + + /** + * @brief Q7 Circular write function. + */ + + __STATIC_INLINE void arm_circularWrite_q7( + q7_t * circBuffer, + int32_t L, + uint16_t * writeOffset, + int32_t bufferInc, + const q7_t * src, + int32_t srcInc, + uint32_t blockSize) + { + uint32_t i = 0u; + int32_t wOffset; + + /* Copy the value of Index pointer that points + * to the current location where the input samples to be copied */ + wOffset = *writeOffset; + + /* Loop over the blockSize */ + i = blockSize; + + while(i > 0u) + { + /* copy the input sample to the circular buffer */ + circBuffer[wOffset] = *src; + + /* Update the input pointer */ + src += srcInc; + + /* Circularly update wOffset. Watch out for positive and negative value */ + wOffset += bufferInc; + if(wOffset >= L) + wOffset -= L; + + /* Decrement the loop counter */ + i--; + } + + /* Update the index pointer */ + *writeOffset = wOffset; + } + + + + /** + * @brief Q7 Circular Read function. + */ + __STATIC_INLINE void arm_circularRead_q7( + q7_t * circBuffer, + int32_t L, + int32_t * readOffset, + int32_t bufferInc, + q7_t * dst, + q7_t * dst_base, + int32_t dst_length, + int32_t dstInc, + uint32_t blockSize) + { + uint32_t i = 0; + int32_t rOffset, dst_end; + + /* Copy the value of Index pointer that points + * to the current location from where the input samples to be read */ + rOffset = *readOffset; + + dst_end = (int32_t) (dst_base + dst_length); + + /* Loop over the blockSize */ + i = blockSize; + + while(i > 0u) + { + /* copy the sample from the circular buffer to the destination buffer */ + *dst = circBuffer[rOffset]; + + /* Update the input pointer */ + dst += dstInc; + + if(dst == (q7_t *) dst_end) + { + dst = dst_base; + } + + /* Circularly update rOffset. Watch out for positive and negative value */ + rOffset += bufferInc; + + if(rOffset >= L) + { + rOffset -= L; + } + + /* Decrement the loop counter */ + i--; + } + + /* Update the index pointer */ + *readOffset = rOffset; + } + + + /** + * @brief Sum of the squares of the elements of a Q31 vector. + * @param[in] *pSrc is input pointer + * @param[in] blockSize is the number of samples to process + * @param[out] *pResult is output value. + * @return none. + */ + + void arm_power_q31( + q31_t * pSrc, + uint32_t blockSize, + q63_t * pResult); + + /** + * @brief Sum of the squares of the elements of a floating-point vector. + * @param[in] *pSrc is input pointer + * @param[in] blockSize is the number of samples to process + * @param[out] *pResult is output value. + * @return none. + */ + + void arm_power_f32( + float32_t * pSrc, + uint32_t blockSize, + float32_t * pResult); + + /** + * @brief Sum of the squares of the elements of a Q15 vector. + * @param[in] *pSrc is input pointer + * @param[in] blockSize is the number of samples to process + * @param[out] *pResult is output value. + * @return none. + */ + + void arm_power_q15( + q15_t * pSrc, + uint32_t blockSize, + q63_t * pResult); + + /** + * @brief Sum of the squares of the elements of a Q7 vector. + * @param[in] *pSrc is input pointer + * @param[in] blockSize is the number of samples to process + * @param[out] *pResult is output value. + * @return none. + */ + + void arm_power_q7( + q7_t * pSrc, + uint32_t blockSize, + q31_t * pResult); + + /** + * @brief Mean value of a Q7 vector. + * @param[in] *pSrc is input pointer + * @param[in] blockSize is the number of samples to process + * @param[out] *pResult is output value. + * @return none. + */ + + void arm_mean_q7( + q7_t * pSrc, + uint32_t blockSize, + q7_t * pResult); + + /** + * @brief Mean value of a Q15 vector. + * @param[in] *pSrc is input pointer + * @param[in] blockSize is the number of samples to process + * @param[out] *pResult is output value. + * @return none. + */ + void arm_mean_q15( + q15_t * pSrc, + uint32_t blockSize, + q15_t * pResult); + + /** + * @brief Mean value of a Q31 vector. + * @param[in] *pSrc is input pointer + * @param[in] blockSize is the number of samples to process + * @param[out] *pResult is output value. + * @return none. + */ + void arm_mean_q31( + q31_t * pSrc, + uint32_t blockSize, + q31_t * pResult); + + /** + * @brief Mean value of a floating-point vector. + * @param[in] *pSrc is input pointer + * @param[in] blockSize is the number of samples to process + * @param[out] *pResult is output value. + * @return none. + */ + void arm_mean_f32( + float32_t * pSrc, + uint32_t blockSize, + float32_t * pResult); + + /** + * @brief Variance of the elements of a floating-point vector. + * @param[in] *pSrc is input pointer + * @param[in] blockSize is the number of samples to process + * @param[out] *pResult is output value. + * @return none. + */ + + void arm_var_f32( + float32_t * pSrc, + uint32_t blockSize, + float32_t * pResult); + + /** + * @brief Variance of the elements of a Q31 vector. + * @param[in] *pSrc is input pointer + * @param[in] blockSize is the number of samples to process + * @param[out] *pResult is output value. + * @return none. + */ + + void arm_var_q31( + q31_t * pSrc, + uint32_t blockSize, + q63_t * pResult); + + /** + * @brief Variance of the elements of a Q15 vector. + * @param[in] *pSrc is input pointer + * @param[in] blockSize is the number of samples to process + * @param[out] *pResult is output value. + * @return none. + */ + + void arm_var_q15( + q15_t * pSrc, + uint32_t blockSize, + q31_t * pResult); + + /** + * @brief Root Mean Square of the elements of a floating-point vector. + * @param[in] *pSrc is input pointer + * @param[in] blockSize is the number of samples to process + * @param[out] *pResult is output value. + * @return none. + */ + + void arm_rms_f32( + float32_t * pSrc, + uint32_t blockSize, + float32_t * pResult); + + /** + * @brief Root Mean Square of the elements of a Q31 vector. + * @param[in] *pSrc is input pointer + * @param[in] blockSize is the number of samples to process + * @param[out] *pResult is output value. + * @return none. + */ + + void arm_rms_q31( + q31_t * pSrc, + uint32_t blockSize, + q31_t * pResult); + + /** + * @brief Root Mean Square of the elements of a Q15 vector. + * @param[in] *pSrc is input pointer + * @param[in] blockSize is the number of samples to process + * @param[out] *pResult is output value. + * @return none. + */ + + void arm_rms_q15( + q15_t * pSrc, + uint32_t blockSize, + q15_t * pResult); + + /** + * @brief Standard deviation of the elements of a floating-point vector. + * @param[in] *pSrc is input pointer + * @param[in] blockSize is the number of samples to process + * @param[out] *pResult is output value. + * @return none. + */ + + void arm_std_f32( + float32_t * pSrc, + uint32_t blockSize, + float32_t * pResult); + + /** + * @brief Standard deviation of the elements of a Q31 vector. + * @param[in] *pSrc is input pointer + * @param[in] blockSize is the number of samples to process + * @param[out] *pResult is output value. + * @return none. + */ + + void arm_std_q31( + q31_t * pSrc, + uint32_t blockSize, + q31_t * pResult); + + /** + * @brief Standard deviation of the elements of a Q15 vector. + * @param[in] *pSrc is input pointer + * @param[in] blockSize is the number of samples to process + * @param[out] *pResult is output value. + * @return none. + */ + + void arm_std_q15( + q15_t * pSrc, + uint32_t blockSize, + q15_t * pResult); + + /** + * @brief Floating-point complex magnitude + * @param[in] *pSrc points to the complex input vector + * @param[out] *pDst points to the real output vector + * @param[in] numSamples number of complex samples in the input vector + * @return none. + */ + + void arm_cmplx_mag_f32( + float32_t * pSrc, + float32_t * pDst, + uint32_t numSamples); + + /** + * @brief Q31 complex magnitude + * @param[in] *pSrc points to the complex input vector + * @param[out] *pDst points to the real output vector + * @param[in] numSamples number of complex samples in the input vector + * @return none. + */ + + void arm_cmplx_mag_q31( + q31_t * pSrc, + q31_t * pDst, + uint32_t numSamples); + + /** + * @brief Q15 complex magnitude + * @param[in] *pSrc points to the complex input vector + * @param[out] *pDst points to the real output vector + * @param[in] numSamples number of complex samples in the input vector + * @return none. + */ + + void arm_cmplx_mag_q15( + q15_t * pSrc, + q15_t * pDst, + uint32_t numSamples); + + /** + * @brief Q15 complex dot product + * @param[in] *pSrcA points to the first input vector + * @param[in] *pSrcB points to the second input vector + * @param[in] numSamples number of complex samples in each vector + * @param[out] *realResult real part of the result returned here + * @param[out] *imagResult imaginary part of the result returned here + * @return none. + */ + + void arm_cmplx_dot_prod_q15( + q15_t * pSrcA, + q15_t * pSrcB, + uint32_t numSamples, + q31_t * realResult, + q31_t * imagResult); + + /** + * @brief Q31 complex dot product + * @param[in] *pSrcA points to the first input vector + * @param[in] *pSrcB points to the second input vector + * @param[in] numSamples number of complex samples in each vector + * @param[out] *realResult real part of the result returned here + * @param[out] *imagResult imaginary part of the result returned here + * @return none. + */ + + void arm_cmplx_dot_prod_q31( + q31_t * pSrcA, + q31_t * pSrcB, + uint32_t numSamples, + q63_t * realResult, + q63_t * imagResult); + + /** + * @brief Floating-point complex dot product + * @param[in] *pSrcA points to the first input vector + * @param[in] *pSrcB points to the second input vector + * @param[in] numSamples number of complex samples in each vector + * @param[out] *realResult real part of the result returned here + * @param[out] *imagResult imaginary part of the result returned here + * @return none. + */ + + void arm_cmplx_dot_prod_f32( + float32_t * pSrcA, + float32_t * pSrcB, + uint32_t numSamples, + float32_t * realResult, + float32_t * imagResult); + + /** + * @brief Q15 complex-by-real multiplication + * @param[in] *pSrcCmplx points to the complex input vector + * @param[in] *pSrcReal points to the real input vector + * @param[out] *pCmplxDst points to the complex output vector + * @param[in] numSamples number of samples in each vector + * @return none. + */ + + void arm_cmplx_mult_real_q15( + q15_t * pSrcCmplx, + q15_t * pSrcReal, + q15_t * pCmplxDst, + uint32_t numSamples); + + /** + * @brief Q31 complex-by-real multiplication + * @param[in] *pSrcCmplx points to the complex input vector + * @param[in] *pSrcReal points to the real input vector + * @param[out] *pCmplxDst points to the complex output vector + * @param[in] numSamples number of samples in each vector + * @return none. + */ + + void arm_cmplx_mult_real_q31( + q31_t * pSrcCmplx, + q31_t * pSrcReal, + q31_t * pCmplxDst, + uint32_t numSamples); + + /** + * @brief Floating-point complex-by-real multiplication + * @param[in] *pSrcCmplx points to the complex input vector + * @param[in] *pSrcReal points to the real input vector + * @param[out] *pCmplxDst points to the complex output vector + * @param[in] numSamples number of samples in each vector + * @return none. + */ + + void arm_cmplx_mult_real_f32( + float32_t * pSrcCmplx, + float32_t * pSrcReal, + float32_t * pCmplxDst, + uint32_t numSamples); + + /** + * @brief Minimum value of a Q7 vector. + * @param[in] *pSrc is input pointer + * @param[in] blockSize is the number of samples to process + * @param[out] *result is output pointer + * @param[in] index is the array index of the minimum value in the input buffer. + * @return none. + */ + + void arm_min_q7( + q7_t * pSrc, + uint32_t blockSize, + q7_t * result, + uint32_t * index); + + /** + * @brief Minimum value of a Q15 vector. + * @param[in] *pSrc is input pointer + * @param[in] blockSize is the number of samples to process + * @param[out] *pResult is output pointer + * @param[in] *pIndex is the array index of the minimum value in the input buffer. + * @return none. + */ + + void arm_min_q15( + q15_t * pSrc, + uint32_t blockSize, + q15_t * pResult, + uint32_t * pIndex); + + /** + * @brief Minimum value of a Q31 vector. + * @param[in] *pSrc is input pointer + * @param[in] blockSize is the number of samples to process + * @param[out] *pResult is output pointer + * @param[out] *pIndex is the array index of the minimum value in the input buffer. + * @return none. + */ + void arm_min_q31( + q31_t * pSrc, + uint32_t blockSize, + q31_t * pResult, + uint32_t * pIndex); + + /** + * @brief Minimum value of a floating-point vector. + * @param[in] *pSrc is input pointer + * @param[in] blockSize is the number of samples to process + * @param[out] *pResult is output pointer + * @param[out] *pIndex is the array index of the minimum value in the input buffer. + * @return none. + */ + + void arm_min_f32( + float32_t * pSrc, + uint32_t blockSize, + float32_t * pResult, + uint32_t * pIndex); + +/** + * @brief Maximum value of a Q7 vector. + * @param[in] *pSrc points to the input buffer + * @param[in] blockSize length of the input vector + * @param[out] *pResult maximum value returned here + * @param[out] *pIndex index of maximum value returned here + * @return none. + */ + + void arm_max_q7( + q7_t * pSrc, + uint32_t blockSize, + q7_t * pResult, + uint32_t * pIndex); + +/** + * @brief Maximum value of a Q15 vector. + * @param[in] *pSrc points to the input buffer + * @param[in] blockSize length of the input vector + * @param[out] *pResult maximum value returned here + * @param[out] *pIndex index of maximum value returned here + * @return none. + */ + + void arm_max_q15( + q15_t * pSrc, + uint32_t blockSize, + q15_t * pResult, + uint32_t * pIndex); + +/** + * @brief Maximum value of a Q31 vector. + * @param[in] *pSrc points to the input buffer + * @param[in] blockSize length of the input vector + * @param[out] *pResult maximum value returned here + * @param[out] *pIndex index of maximum value returned here + * @return none. + */ + + void arm_max_q31( + q31_t * pSrc, + uint32_t blockSize, + q31_t * pResult, + uint32_t * pIndex); + +/** + * @brief Maximum value of a floating-point vector. + * @param[in] *pSrc points to the input buffer + * @param[in] blockSize length of the input vector + * @param[out] *pResult maximum value returned here + * @param[out] *pIndex index of maximum value returned here + * @return none. + */ + + void arm_max_f32( + float32_t * pSrc, + uint32_t blockSize, + float32_t * pResult, + uint32_t * pIndex); + + /** + * @brief Q15 complex-by-complex multiplication + * @param[in] *pSrcA points to the first input vector + * @param[in] *pSrcB points to the second input vector + * @param[out] *pDst points to the output vector + * @param[in] numSamples number of complex samples in each vector + * @return none. + */ + + void arm_cmplx_mult_cmplx_q15( + q15_t * pSrcA, + q15_t * pSrcB, + q15_t * pDst, + uint32_t numSamples); + + /** + * @brief Q31 complex-by-complex multiplication + * @param[in] *pSrcA points to the first input vector + * @param[in] *pSrcB points to the second input vector + * @param[out] *pDst points to the output vector + * @param[in] numSamples number of complex samples in each vector + * @return none. + */ + + void arm_cmplx_mult_cmplx_q31( + q31_t * pSrcA, + q31_t * pSrcB, + q31_t * pDst, + uint32_t numSamples); + + /** + * @brief Floating-point complex-by-complex multiplication + * @param[in] *pSrcA points to the first input vector + * @param[in] *pSrcB points to the second input vector + * @param[out] *pDst points to the output vector + * @param[in] numSamples number of complex samples in each vector + * @return none. + */ + + void arm_cmplx_mult_cmplx_f32( + float32_t * pSrcA, + float32_t * pSrcB, + float32_t * pDst, + uint32_t numSamples); + + /** + * @brief Converts the elements of the floating-point vector to Q31 vector. + * @param[in] *pSrc points to the floating-point input vector + * @param[out] *pDst points to the Q31 output vector + * @param[in] blockSize length of the input vector + * @return none. + */ + void arm_float_to_q31( + float32_t * pSrc, + q31_t * pDst, + uint32_t blockSize); + + /** + * @brief Converts the elements of the floating-point vector to Q15 vector. + * @param[in] *pSrc points to the floating-point input vector + * @param[out] *pDst points to the Q15 output vector + * @param[in] blockSize length of the input vector + * @return none + */ + void arm_float_to_q15( + float32_t * pSrc, + q15_t * pDst, + uint32_t blockSize); + + /** + * @brief Converts the elements of the floating-point vector to Q7 vector. + * @param[in] *pSrc points to the floating-point input vector + * @param[out] *pDst points to the Q7 output vector + * @param[in] blockSize length of the input vector + * @return none + */ + void arm_float_to_q7( + float32_t * pSrc, + q7_t * pDst, + uint32_t blockSize); + + + /** + * @brief Converts the elements of the Q31 vector to Q15 vector. + * @param[in] *pSrc is input pointer + * @param[out] *pDst is output pointer + * @param[in] blockSize is the number of samples to process + * @return none. + */ + void arm_q31_to_q15( + q31_t * pSrc, + q15_t * pDst, + uint32_t blockSize); + + /** + * @brief Converts the elements of the Q31 vector to Q7 vector. + * @param[in] *pSrc is input pointer + * @param[out] *pDst is output pointer + * @param[in] blockSize is the number of samples to process + * @return none. + */ + void arm_q31_to_q7( + q31_t * pSrc, + q7_t * pDst, + uint32_t blockSize); + + /** + * @brief Converts the elements of the Q15 vector to floating-point vector. + * @param[in] *pSrc is input pointer + * @param[out] *pDst is output pointer + * @param[in] blockSize is the number of samples to process + * @return none. + */ + void arm_q15_to_float( + q15_t * pSrc, + float32_t * pDst, + uint32_t blockSize); + + + /** + * @brief Converts the elements of the Q15 vector to Q31 vector. + * @param[in] *pSrc is input pointer + * @param[out] *pDst is output pointer + * @param[in] blockSize is the number of samples to process + * @return none. + */ + void arm_q15_to_q31( + q15_t * pSrc, + q31_t * pDst, + uint32_t blockSize); + + + /** + * @brief Converts the elements of the Q15 vector to Q7 vector. + * @param[in] *pSrc is input pointer + * @param[out] *pDst is output pointer + * @param[in] blockSize is the number of samples to process + * @return none. + */ + void arm_q15_to_q7( + q15_t * pSrc, + q7_t * pDst, + uint32_t blockSize); + + + /** + * @ingroup groupInterpolation + */ + + /** + * @defgroup BilinearInterpolate Bilinear Interpolation + * + * Bilinear interpolation is an extension of linear interpolation applied to a two dimensional grid. + * The underlying function f(x, y) is sampled on a regular grid and the interpolation process + * determines values between the grid points. + * Bilinear interpolation is equivalent to two step linear interpolation, first in the x-dimension and then in the y-dimension. + * Bilinear interpolation is often used in image processing to rescale images. + * The CMSIS DSP library provides bilinear interpolation functions for Q7, Q15, Q31, and floating-point data types. + * + * Algorithm + * \par + * The instance structure used by the bilinear interpolation functions describes a two dimensional data table. + * For floating-point, the instance structure is defined as: + * 
    +   *   typedef struct
+   *   {
+   *     uint16_t numRows;
+   *     uint16_t numCols;
+   *     float32_t *pData;
+   * } arm_bilinear_interp_instance_f32;
+   *
    + * + * \par + * where numRows specifies the number of rows in the table; + * numCols specifies the number of columns in the table; + * and pData points to an array of size numRows*numCols values. + * The data table pTable is organized in row order and the supplied data values fall on integer indexes. + * That is, table element (x,y) is located at pTable[x + y*numCols] where x and y are integers. + * + * \par + * Let (x, y) specify the desired interpolation point. Then define: + * 
    +   *     XF = floor(x)
+   *     YF = floor(y)
+   *
    + * \par + * The interpolated output point is computed as: + * 
    +   *  f(x, y) = f(XF, YF) * (1-(x-XF)) * (1-(y-YF))
+   *           + f(XF+1, YF) * (x-XF)*(1-(y-YF))
+   *           + f(XF, YF+1) * (1-(x-XF))*(y-YF)
+   *           + f(XF+1, YF+1) * (x-XF)*(y-YF)
+   *
    + * Note that the coordinates (x, y) contain integer and fractional components. + * The integer components specify which portion of the table to use while the + * fractional components control the interpolation processor. + * + * \par + * if (x,y) are outside of the table boundary, Bilinear interpolation returns zero output. + */ + + /** + * @addtogroup BilinearInterpolate + * @{ + */ + + /** + * + * @brief Floating-point bilinear interpolation. + * @param[in,out] *S points to an instance of the interpolation structure. + * @param[in] X interpolation coordinate. + * @param[in] Y interpolation coordinate. + * @return out interpolated value. + */ + + + __STATIC_INLINE float32_t arm_bilinear_interp_f32( + const arm_bilinear_interp_instance_f32 * S, + float32_t X, + float32_t Y) + { + float32_t out; + float32_t f00, f01, f10, f11; + float32_t *pData = S->pData; + int32_t xIndex, yIndex, index; + float32_t xdiff, ydiff; + float32_t b1, b2, b3, b4; + + xIndex = (int32_t) X; + yIndex = (int32_t) Y; + + /* Care taken for table outside boundary */ + /* Returns zero output when values are outside table boundary */ + if(xIndex < 0 || xIndex > (S->numRows - 1) || yIndex < 0 + || yIndex > (S->numCols - 1)) + { + return (0); + } + + /* Calculation of index for two nearest points in X-direction */ + index = (xIndex - 1) + (yIndex - 1) * S->numCols; + + + /* Read two nearest points in X-direction */ + f00 = pData[index]; + f01 = pData[index + 1]; + + /* Calculation of index for two nearest points in Y-direction */ + index = (xIndex - 1) + (yIndex) * S->numCols; + + + /* Read two nearest points in Y-direction */ + f10 = pData[index]; + f11 = pData[index + 1]; + + /* Calculation of intermediate values */ + b1 = f00; + b2 = f01 - f00; + b3 = f10 - f00; + b4 = f00 - f01 - f10 + f11; + + /* Calculation of fractional part in X */ + xdiff = X - xIndex; + + /* Calculation of fractional part in Y */ + ydiff = Y - yIndex; + + /* Calculation of bi-linear interpolated output */ + out = b1 + b2 * xdiff + b3 * ydiff + b4 * xdiff * ydiff; + + /* return to application */ + return (out); + + } + + /** + * + * @brief Q31 bilinear interpolation. + * @param[in,out] *S points to an instance of the interpolation structure. + * @param[in] X interpolation coordinate in 12.20 format. + * @param[in] Y interpolation coordinate in 12.20 format. + * @return out interpolated value. + */ + + __STATIC_INLINE q31_t arm_bilinear_interp_q31( + arm_bilinear_interp_instance_q31 * S, + q31_t X, + q31_t Y) + { + q31_t out; /* Temporary output */ + q31_t acc = 0; /* output */ + q31_t xfract, yfract; /* X, Y fractional parts */ + q31_t x1, x2, y1, y2; /* Nearest output values */ + int32_t rI, cI; /* Row and column indices */ + q31_t *pYData = S->pData; /* pointer to output table values */ + uint32_t nCols = S->numCols; /* num of rows */ + + + /* Input is in 12.20 format */ + /* 12 bits for the table index */ + /* Index value calculation */ + rI = ((X & 0xFFF00000) >> 20u); + + /* Input is in 12.20 format */ + /* 12 bits for the table index */ + /* Index value calculation */ + cI = ((Y & 0xFFF00000) >> 20u); + + /* Care taken for table outside boundary */ + /* Returns zero output when values are outside table boundary */ + if(rI < 0 || rI > (S->numRows - 1) || cI < 0 || cI > (S->numCols - 1)) + { + return (0); + } + + /* 20 bits for the fractional part */ + /* shift left xfract by 11 to keep 1.31 format */ + xfract = (X & 0x000FFFFF) << 11u; + + /* Read two nearest output values from the index */ + x1 = pYData[(rI) + nCols * (cI)]; + x2 = pYData[(rI) + nCols * (cI) + 1u]; + + /* 20 bits for the fractional part */ + /* shift left yfract by 11 to keep 1.31 format */ + yfract = (Y & 0x000FFFFF) << 11u; + + /* Read two nearest output values from the index */ + y1 = pYData[(rI) + nCols * (cI + 1)]; + y2 = pYData[(rI) + nCols * (cI + 1) + 1u]; + + /* Calculation of x1 * (1-xfract ) * (1-yfract) and acc is in 3.29(q29) format */ + out = ((q31_t) (((q63_t) x1 * (0x7FFFFFFF - xfract)) >> 32)); + acc = ((q31_t) (((q63_t) out * (0x7FFFFFFF - yfract)) >> 32)); + + /* x2 * (xfract) * (1-yfract) in 3.29(q29) and adding to acc */ + out = ((q31_t) ((q63_t) x2 * (0x7FFFFFFF - yfract) >> 32)); + acc += ((q31_t) ((q63_t) out * (xfract) >> 32)); + + /* y1 * (1 - xfract) * (yfract) in 3.29(q29) and adding to acc */ + out = ((q31_t) ((q63_t) y1 * (0x7FFFFFFF - xfract) >> 32)); + acc += ((q31_t) ((q63_t) out * (yfract) >> 32)); + + /* y2 * (xfract) * (yfract) in 3.29(q29) and adding to acc */ + out = ((q31_t) ((q63_t) y2 * (xfract) >> 32)); + acc += ((q31_t) ((q63_t) out * (yfract) >> 32)); + + /* Convert acc to 1.31(q31) format */ + return (acc << 2u); + + } + + /** + * @brief Q15 bilinear interpolation. + * @param[in,out] *S points to an instance of the interpolation structure. + * @param[in] X interpolation coordinate in 12.20 format. + * @param[in] Y interpolation coordinate in 12.20 format. + * @return out interpolated value. + */ + + __STATIC_INLINE q15_t arm_bilinear_interp_q15( + arm_bilinear_interp_instance_q15 * S, + q31_t X, + q31_t Y) + { + q63_t acc = 0; /* output */ + q31_t out; /* Temporary output */ + q15_t x1, x2, y1, y2; /* Nearest output values */ + q31_t xfract, yfract; /* X, Y fractional parts */ + int32_t rI, cI; /* Row and column indices */ + q15_t *pYData = S->pData; /* pointer to output table values */ + uint32_t nCols = S->numCols; /* num of rows */ + + /* Input is in 12.20 format */ + /* 12 bits for the table index */ + /* Index value calculation */ + rI = ((X & 0xFFF00000) >> 20); + + /* Input is in 12.20 format */ + /* 12 bits for the table index */ + /* Index value calculation */ + cI = ((Y & 0xFFF00000) >> 20); + + /* Care taken for table outside boundary */ + /* Returns zero output when values are outside table boundary */ + if(rI < 0 || rI > (S->numRows - 1) || cI < 0 || cI > (S->numCols - 1)) + { + return (0); + } + + /* 20 bits for the fractional part */ + /* xfract should be in 12.20 format */ + xfract = (X & 0x000FFFFF); + + /* Read two nearest output values from the index */ + x1 = pYData[(rI) + nCols * (cI)]; + x2 = pYData[(rI) + nCols * (cI) + 1u]; + + + /* 20 bits for the fractional part */ + /* yfract should be in 12.20 format */ + yfract = (Y & 0x000FFFFF); + + /* Read two nearest output values from the index */ + y1 = pYData[(rI) + nCols * (cI + 1)]; + y2 = pYData[(rI) + nCols * (cI + 1) + 1u]; + + /* Calculation of x1 * (1-xfract ) * (1-yfract) and acc is in 13.51 format */ + + /* x1 is in 1.15(q15), xfract in 12.20 format and out is in 13.35 format */ + /* convert 13.35 to 13.31 by right shifting and out is in 1.31 */ + out = (q31_t) (((q63_t) x1 * (0xFFFFF - xfract)) >> 4u); + acc = ((q63_t) out * (0xFFFFF - yfract)); + + /* x2 * (xfract) * (1-yfract) in 1.51 and adding to acc */ + out = (q31_t) (((q63_t) x2 * (0xFFFFF - yfract)) >> 4u); + acc += ((q63_t) out * (xfract)); + + /* y1 * (1 - xfract) * (yfract) in 1.51 and adding to acc */ + out = (q31_t) (((q63_t) y1 * (0xFFFFF - xfract)) >> 4u); + acc += ((q63_t) out * (yfract)); + + /* y2 * (xfract) * (yfract) in 1.51 and adding to acc */ + out = (q31_t) (((q63_t) y2 * (xfract)) >> 4u); + acc += ((q63_t) out * (yfract)); + + /* acc is in 13.51 format and down shift acc by 36 times */ + /* Convert out to 1.15 format */ + return (acc >> 36); + + } + + /** + * @brief Q7 bilinear interpolation. + * @param[in,out] *S points to an instance of the interpolation structure. + * @param[in] X interpolation coordinate in 12.20 format. + * @param[in] Y interpolation coordinate in 12.20 format. + * @return out interpolated value. + */ + + __STATIC_INLINE q7_t arm_bilinear_interp_q7( + arm_bilinear_interp_instance_q7 * S, + q31_t X, + q31_t Y) + { + q63_t acc = 0; /* output */ + q31_t out; /* Temporary output */ + q31_t xfract, yfract; /* X, Y fractional parts */ + q7_t x1, x2, y1, y2; /* Nearest output values */ + int32_t rI, cI; /* Row and column indices */ + q7_t *pYData = S->pData; /* pointer to output table values */ + uint32_t nCols = S->numCols; /* num of rows */ + + /* Input is in 12.20 format */ + /* 12 bits for the table index */ + /* Index value calculation */ + rI = ((X & 0xFFF00000) >> 20); + + /* Input is in 12.20 format */ + /* 12 bits for the table index */ + /* Index value calculation */ + cI = ((Y & 0xFFF00000) >> 20); + + /* Care taken for table outside boundary */ + /* Returns zero output when values are outside table boundary */ + if(rI < 0 || rI > (S->numRows - 1) || cI < 0 || cI > (S->numCols - 1)) + { + return (0); + } + + /* 20 bits for the fractional part */ + /* xfract should be in 12.20 format */ + xfract = (X & 0x000FFFFF); + + /* Read two nearest output values from the index */ + x1 = pYData[(rI) + nCols * (cI)]; + x2 = pYData[(rI) + nCols * (cI) + 1u]; + + + /* 20 bits for the fractional part */ + /* yfract should be in 12.20 format */ + yfract = (Y & 0x000FFFFF); + + /* Read two nearest output values from the index */ + y1 = pYData[(rI) + nCols * (cI + 1)]; + y2 = pYData[(rI) + nCols * (cI + 1) + 1u]; + + /* Calculation of x1 * (1-xfract ) * (1-yfract) and acc is in 16.47 format */ + out = ((x1 * (0xFFFFF - xfract))); + acc = (((q63_t) out * (0xFFFFF - yfract))); + + /* x2 * (xfract) * (1-yfract) in 2.22 and adding to acc */ + out = ((x2 * (0xFFFFF - yfract))); + acc += (((q63_t) out * (xfract))); + + /* y1 * (1 - xfract) * (yfract) in 2.22 and adding to acc */ + out = ((y1 * (0xFFFFF - xfract))); + acc += (((q63_t) out * (yfract))); + + /* y2 * (xfract) * (yfract) in 2.22 and adding to acc */ + out = ((y2 * (yfract))); + acc += (((q63_t) out * (xfract))); + + /* acc in 16.47 format and down shift by 40 to convert to 1.7 format */ + return (acc >> 40); + + } + + /** + * @} end of BilinearInterpolate group + */ + + + + + + +#ifdef __cplusplus +} +#endif + + +#endif /* _ARM_MATH_H */ + + +/** + * + * End of file. + */ diff --git a/Libraries/CMSIS/Include/core_cm0.h b/Libraries/CMSIS/Include/core_cm0.h new file mode 100644 index 0000000..19bad5e --- /dev/null +++ b/Libraries/CMSIS/Include/core_cm0.h @@ -0,0 +1,667 @@ +/**************************************************************************//** + * @file core_cm0.h + * @brief CMSIS Cortex-M0 Core Peripheral Access Layer Header File + * @version V3.01 + * @date 13. March 2012 + * + * @note + * Copyright (C) 2009-2012 ARM Limited. All rights reserved. + * + * @par + * ARM Limited (ARM) is supplying this software for use with Cortex-M + * processor based microcontrollers. This file can be freely distributed + * within development tools that are supporting such ARM based processors. + * + * @par + * THIS SOFTWARE IS PROVIDED "AS IS". NO WARRANTIES, WHETHER EXPRESS, IMPLIED + * OR STATUTORY, INCLUDING, BUT NOT LIMITED TO, IMPLIED WARRANTIES OF + * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE APPLY TO THIS SOFTWARE. + * ARM SHALL NOT, IN ANY CIRCUMSTANCES, BE LIABLE FOR SPECIAL, INCIDENTAL, OR + * CONSEQUENTIAL DAMAGES, FOR ANY REASON WHATSOEVER. + * + ******************************************************************************/ +#if defined ( __ICCARM__ ) + #pragma system_include /* treat file as system include file for MISRA check */ +#endif + +#ifdef __cplusplus + extern "C" { +#endif + +#ifndef __CORE_CM0_H_GENERIC +#define __CORE_CM0_H_GENERIC + +/** \page CMSIS_MISRA_Exceptions MISRA-C:2004 Compliance Exceptions + CMSIS violates the following MISRA-C:2004 rules: + + \li Required Rule 8.5, object/function definition in header file.
    + Function definitions in header files are used to allow 'inlining'. + + \li Required Rule 18.4, declaration of union type or object of union type: '{...}'.
    + Unions are used for effective representation of core registers. + + \li Advisory Rule 19.7, Function-like macro defined.
    + Function-like macros are used to allow more efficient code. + */ + + +/******************************************************************************* + * CMSIS definitions + ******************************************************************************/ +/** \ingroup Cortex_M0 + @{ + */ + +/* CMSIS CM0 definitions */ +#define __CM0_CMSIS_VERSION_MAIN (0x03) /*!< [31:16] CMSIS HAL main version */ +#define __CM0_CMSIS_VERSION_SUB (0x01) /*!< [15:0] CMSIS HAL sub version */ +#define __CM0_CMSIS_VERSION ((__CM0_CMSIS_VERSION_MAIN << 16) | \ + __CM0_CMSIS_VERSION_SUB ) /*!< CMSIS HAL version number */ + +#define __CORTEX_M (0x00) /*!< Cortex-M Core */ + + +#if defined ( __CC_ARM ) + #define __ASM __asm /*!< asm keyword for ARM Compiler */ + #define __INLINE __inline /*!< inline keyword for ARM Compiler */ + #define __STATIC_INLINE static __inline + +#elif defined ( __ICCARM__ ) + #define __ASM __asm /*!< asm keyword for IAR Compiler */ + #define __INLINE inline /*!< inline keyword for IAR Compiler. Only available in High optimization mode! */ + #define __STATIC_INLINE static inline + +#elif defined ( __GNUC__ ) + #define __ASM __asm /*!< asm keyword for GNU Compiler */ + #define __INLINE inline /*!< inline keyword for GNU Compiler */ + #define __STATIC_INLINE static inline + +#elif defined ( __TASKING__ ) + #define __ASM __asm /*!< asm keyword for TASKING Compiler */ + #define __INLINE inline /*!< inline keyword for TASKING Compiler */ + #define __STATIC_INLINE static inline + +#endif + +/** __FPU_USED indicates whether an FPU is used or not. This core does not support an FPU at all +*/ +#define __FPU_USED 0 + +#if defined ( __CC_ARM ) + #if defined __TARGET_FPU_VFP + #warning "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #endif + +#elif defined ( __ICCARM__ ) + #if defined __ARMVFP__ + #warning "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #endif + +#elif defined ( __GNUC__ ) + #if defined (__VFP_FP__) && !defined(__SOFTFP__) + #warning "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #endif + +#elif defined ( __TASKING__ ) + #if defined __FPU_VFP__ + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #endif +#endif + +#include /* standard types definitions */ +#include /* Core Instruction Access */ +#include /* Core Function Access */ + +#endif /* __CORE_CM0_H_GENERIC */ + +#ifndef __CMSIS_GENERIC + +#ifndef __CORE_CM0_H_DEPENDANT +#define __CORE_CM0_H_DEPENDANT + +/* check device defines and use defaults */ +#if defined __CHECK_DEVICE_DEFINES + #ifndef __CM0_REV + #define __CM0_REV 0x0000 + #warning "__CM0_REV not defined in device header file; using default!" + #endif + + #ifndef __NVIC_PRIO_BITS + #define __NVIC_PRIO_BITS 2 + #warning "__NVIC_PRIO_BITS not defined in device header file; using default!" + #endif + + #ifndef __Vendor_SysTickConfig + #define __Vendor_SysTickConfig 0 + #warning "__Vendor_SysTickConfig not defined in device header file; using default!" + #endif +#endif + +/* IO definitions (access restrictions to peripheral registers) */ +/** + \defgroup CMSIS_glob_defs CMSIS Global Defines + + IO Type Qualifiers are used + \li to specify the access to peripheral variables. + \li for automatic generation of peripheral register debug information. +*/ +#ifdef __cplusplus + #define __I volatile /*!< Defines 'read only' permissions */ +#else + #define __I volatile const /*!< Defines 'read only' permissions */ +#endif +#define __O volatile /*!< Defines 'write only' permissions */ +#define __IO volatile /*!< Defines 'read / write' permissions */ + +/*@} end of group Cortex_M0 */ + + + +/******************************************************************************* + * Register Abstraction + Core Register contain: + - Core Register + - Core NVIC Register + - Core SCB Register + - Core SysTick Register + ******************************************************************************/ +/** \defgroup CMSIS_core_register Defines and Type Definitions + \brief Type definitions and defines for Cortex-M processor based devices. +*/ + +/** \ingroup CMSIS_core_register + \defgroup CMSIS_CORE Status and Control Registers + \brief Core Register type definitions. + @{ + */ + +/** \brief Union type to access the Application Program Status Register (APSR). + */ +typedef union +{ + struct + { +#if (__CORTEX_M != 0x04) + uint32_t _reserved0:27; /*!< bit: 0..26 Reserved */ +#else + uint32_t _reserved0:16; /*!< bit: 0..15 Reserved */ + uint32_t GE:4; /*!< bit: 16..19 Greater than or Equal flags */ + uint32_t _reserved1:7; /*!< bit: 20..26 Reserved */ +#endif + uint32_t Q:1; /*!< bit: 27 Saturation condition flag */ + uint32_t V:1; /*!< bit: 28 Overflow condition code flag */ + uint32_t C:1; /*!< bit: 29 Carry condition code flag */ + uint32_t Z:1; /*!< bit: 30 Zero condition code flag */ + uint32_t N:1; /*!< bit: 31 Negative condition code flag */ + } b; /*!< Structure used for bit access */ + uint32_t w; /*!< Type used for word access */ +} APSR_Type; + + +/** \brief Union type to access the Interrupt Program Status Register (IPSR). + */ +typedef union +{ + struct + { + uint32_t ISR:9; /*!< bit: 0.. 8 Exception number */ + uint32_t _reserved0:23; /*!< bit: 9..31 Reserved */ + } b; /*!< Structure used for bit access */ + uint32_t w; /*!< Type used for word access */ +} IPSR_Type; + + +/** \brief Union type to access the Special-Purpose Program Status Registers (xPSR). + */ +typedef union +{ + struct + { + uint32_t ISR:9; /*!< bit: 0.. 8 Exception number */ +#if (__CORTEX_M != 0x04) + uint32_t _reserved0:15; /*!< bit: 9..23 Reserved */ +#else + uint32_t _reserved0:7; /*!< bit: 9..15 Reserved */ + uint32_t GE:4; /*!< bit: 16..19 Greater than or Equal flags */ + uint32_t _reserved1:4; /*!< bit: 20..23 Reserved */ +#endif + uint32_t T:1; /*!< bit: 24 Thumb bit (read 0) */ + uint32_t IT:2; /*!< bit: 25..26 saved IT state (read 0) */ + uint32_t Q:1; /*!< bit: 27 Saturation condition flag */ + uint32_t V:1; /*!< bit: 28 Overflow condition code flag */ + uint32_t C:1; /*!< bit: 29 Carry condition code flag */ + uint32_t Z:1; /*!< bit: 30 Zero condition code flag */ + uint32_t N:1; /*!< bit: 31 Negative condition code flag */ + } b; /*!< Structure used for bit access */ + uint32_t w; /*!< Type used for word access */ +} xPSR_Type; + + +/** \brief Union type to access the Control Registers (CONTROL). + */ +typedef union +{ + struct + { + uint32_t nPRIV:1; /*!< bit: 0 Execution privilege in Thread mode */ + uint32_t SPSEL:1; /*!< bit: 1 Stack to be used */ + uint32_t FPCA:1; /*!< bit: 2 FP extension active flag */ + uint32_t _reserved0:29; /*!< bit: 3..31 Reserved */ + } b; /*!< Structure used for bit access */ + uint32_t w; /*!< Type used for word access */ +} CONTROL_Type; + +/*@} end of group CMSIS_CORE */ + + +/** \ingroup CMSIS_core_register + \defgroup CMSIS_NVIC Nested Vectored Interrupt Controller (NVIC) + \brief Type definitions for the NVIC Registers + @{ + */ + +/** \brief Structure type to access the Nested Vectored Interrupt Controller (NVIC). + */ +typedef struct +{ + __IO uint32_t ISER[1]; /*!< Offset: 0x000 (R/W) Interrupt Set Enable Register */ + uint32_t RESERVED0[31]; + __IO uint32_t ICER[1]; /*!< Offset: 0x080 (R/W) Interrupt Clear Enable Register */ + uint32_t RSERVED1[31]; + __IO uint32_t ISPR[1]; /*!< Offset: 0x100 (R/W) Interrupt Set Pending Register */ + uint32_t RESERVED2[31]; + __IO uint32_t ICPR[1]; /*!< Offset: 0x180 (R/W) Interrupt Clear Pending Register */ + uint32_t RESERVED3[31]; + uint32_t RESERVED4[64]; + __IO uint32_t IP[8]; /*!< Offset: 0x300 (R/W) Interrupt Priority Register */ +} NVIC_Type; + +/*@} end of group CMSIS_NVIC */ + + +/** \ingroup CMSIS_core_register + \defgroup CMSIS_SCB System Control Block (SCB) + \brief Type definitions for the System Control Block Registers + @{ + */ + +/** \brief Structure type to access the System Control Block (SCB). + */ +typedef struct +{ + __I uint32_t CPUID; /*!< Offset: 0x000 (R/ ) CPUID Base Register */ + __IO uint32_t ICSR; /*!< Offset: 0x004 (R/W) Interrupt Control and State Register */ + uint32_t RESERVED0; + __IO uint32_t AIRCR; /*!< Offset: 0x00C (R/W) Application Interrupt and Reset Control Register */ + __IO uint32_t SCR; /*!< Offset: 0x010 (R/W) System Control Register */ + __IO uint32_t CCR; /*!< Offset: 0x014 (R/W) Configuration Control Register */ + uint32_t RESERVED1; + __IO uint32_t SHP[2]; /*!< Offset: 0x01C (R/W) System Handlers Priority Registers. [0] is RESERVED */ + __IO uint32_t SHCSR; /*!< Offset: 0x024 (R/W) System Handler Control and State Register */ +} SCB_Type; + +/* SCB CPUID Register Definitions */ +#define SCB_CPUID_IMPLEMENTER_Pos 24 /*!< SCB CPUID: IMPLEMENTER Position */ +#define SCB_CPUID_IMPLEMENTER_Msk (0xFFUL << SCB_CPUID_IMPLEMENTER_Pos) /*!< SCB CPUID: IMPLEMENTER Mask */ + +#define SCB_CPUID_VARIANT_Pos 20 /*!< SCB CPUID: VARIANT Position */ +#define SCB_CPUID_VARIANT_Msk (0xFUL << SCB_CPUID_VARIANT_Pos) /*!< SCB CPUID: VARIANT Mask */ + +#define SCB_CPUID_ARCHITECTURE_Pos 16 /*!< SCB CPUID: ARCHITECTURE Position */ +#define SCB_CPUID_ARCHITECTURE_Msk (0xFUL << SCB_CPUID_ARCHITECTURE_Pos) /*!< SCB CPUID: ARCHITECTURE Mask */ + +#define SCB_CPUID_PARTNO_Pos 4 /*!< SCB CPUID: PARTNO Position */ +#define SCB_CPUID_PARTNO_Msk (0xFFFUL << SCB_CPUID_PARTNO_Pos) /*!< SCB CPUID: PARTNO Mask */ + +#define SCB_CPUID_REVISION_Pos 0 /*!< SCB CPUID: REVISION Position */ +#define SCB_CPUID_REVISION_Msk (0xFUL << SCB_CPUID_REVISION_Pos) /*!< SCB CPUID: REVISION Mask */ + +/* SCB Interrupt Control State Register Definitions */ +#define SCB_ICSR_NMIPENDSET_Pos 31 /*!< SCB ICSR: NMIPENDSET Position */ +#define SCB_ICSR_NMIPENDSET_Msk (1UL << SCB_ICSR_NMIPENDSET_Pos) /*!< SCB ICSR: NMIPENDSET Mask */ + +#define SCB_ICSR_PENDSVSET_Pos 28 /*!< SCB ICSR: PENDSVSET Position */ +#define SCB_ICSR_PENDSVSET_Msk (1UL << SCB_ICSR_PENDSVSET_Pos) /*!< SCB ICSR: PENDSVSET Mask */ + +#define SCB_ICSR_PENDSVCLR_Pos 27 /*!< SCB ICSR: PENDSVCLR Position */ +#define SCB_ICSR_PENDSVCLR_Msk (1UL << SCB_ICSR_PENDSVCLR_Pos) /*!< SCB ICSR: PENDSVCLR Mask */ + +#define SCB_ICSR_PENDSTSET_Pos 26 /*!< SCB ICSR: PENDSTSET Position */ +#define SCB_ICSR_PENDSTSET_Msk (1UL << SCB_ICSR_PENDSTSET_Pos) /*!< SCB ICSR: PENDSTSET Mask */ + +#define SCB_ICSR_PENDSTCLR_Pos 25 /*!< SCB ICSR: PENDSTCLR Position */ +#define SCB_ICSR_PENDSTCLR_Msk (1UL << SCB_ICSR_PENDSTCLR_Pos) /*!< SCB ICSR: PENDSTCLR Mask */ + +#define SCB_ICSR_ISRPREEMPT_Pos 23 /*!< SCB ICSR: ISRPREEMPT Position */ +#define SCB_ICSR_ISRPREEMPT_Msk (1UL << SCB_ICSR_ISRPREEMPT_Pos) /*!< SCB ICSR: ISRPREEMPT Mask */ + +#define SCB_ICSR_ISRPENDING_Pos 22 /*!< SCB ICSR: ISRPENDING Position */ +#define SCB_ICSR_ISRPENDING_Msk (1UL << SCB_ICSR_ISRPENDING_Pos) /*!< SCB ICSR: ISRPENDING Mask */ + +#define SCB_ICSR_VECTPENDING_Pos 12 /*!< SCB ICSR: VECTPENDING Position */ +#define SCB_ICSR_VECTPENDING_Msk (0x1FFUL << SCB_ICSR_VECTPENDING_Pos) /*!< SCB ICSR: VECTPENDING Mask */ + +#define SCB_ICSR_VECTACTIVE_Pos 0 /*!< SCB ICSR: VECTACTIVE Position */ +#define SCB_ICSR_VECTACTIVE_Msk (0x1FFUL << SCB_ICSR_VECTACTIVE_Pos) /*!< SCB ICSR: VECTACTIVE Mask */ + +/* SCB Application Interrupt and Reset Control Register Definitions */ +#define SCB_AIRCR_VECTKEY_Pos 16 /*!< SCB AIRCR: VECTKEY Position */ +#define SCB_AIRCR_VECTKEY_Msk (0xFFFFUL << SCB_AIRCR_VECTKEY_Pos) /*!< SCB AIRCR: VECTKEY Mask */ + +#define SCB_AIRCR_VECTKEYSTAT_Pos 16 /*!< SCB AIRCR: VECTKEYSTAT Position */ +#define SCB_AIRCR_VECTKEYSTAT_Msk (0xFFFFUL << SCB_AIRCR_VECTKEYSTAT_Pos) /*!< SCB AIRCR: VECTKEYSTAT Mask */ + +#define SCB_AIRCR_ENDIANESS_Pos 15 /*!< SCB AIRCR: ENDIANESS Position */ +#define SCB_AIRCR_ENDIANESS_Msk (1UL << SCB_AIRCR_ENDIANESS_Pos) /*!< SCB AIRCR: ENDIANESS Mask */ + +#define SCB_AIRCR_SYSRESETREQ_Pos 2 /*!< SCB AIRCR: SYSRESETREQ Position */ +#define SCB_AIRCR_SYSRESETREQ_Msk (1UL << SCB_AIRCR_SYSRESETREQ_Pos) /*!< SCB AIRCR: SYSRESETREQ Mask */ + +#define SCB_AIRCR_VECTCLRACTIVE_Pos 1 /*!< SCB AIRCR: VECTCLRACTIVE Position */ +#define SCB_AIRCR_VECTCLRACTIVE_Msk (1UL << SCB_AIRCR_VECTCLRACTIVE_Pos) /*!< SCB AIRCR: VECTCLRACTIVE Mask */ + +/* SCB System Control Register Definitions */ +#define SCB_SCR_SEVONPEND_Pos 4 /*!< SCB SCR: SEVONPEND Position */ +#define SCB_SCR_SEVONPEND_Msk (1UL << SCB_SCR_SEVONPEND_Pos) /*!< SCB SCR: SEVONPEND Mask */ + +#define SCB_SCR_SLEEPDEEP_Pos 2 /*!< SCB SCR: SLEEPDEEP Position */ +#define SCB_SCR_SLEEPDEEP_Msk (1UL << SCB_SCR_SLEEPDEEP_Pos) /*!< SCB SCR: SLEEPDEEP Mask */ + +#define SCB_SCR_SLEEPONEXIT_Pos 1 /*!< SCB SCR: SLEEPONEXIT Position */ +#define SCB_SCR_SLEEPONEXIT_Msk (1UL << SCB_SCR_SLEEPONEXIT_Pos) /*!< SCB SCR: SLEEPONEXIT Mask */ + +/* SCB Configuration Control Register Definitions */ +#define SCB_CCR_STKALIGN_Pos 9 /*!< SCB CCR: STKALIGN Position */ +#define SCB_CCR_STKALIGN_Msk (1UL << SCB_CCR_STKALIGN_Pos) /*!< SCB CCR: STKALIGN Mask */ + +#define SCB_CCR_UNALIGN_TRP_Pos 3 /*!< SCB CCR: UNALIGN_TRP Position */ +#define SCB_CCR_UNALIGN_TRP_Msk (1UL << SCB_CCR_UNALIGN_TRP_Pos) /*!< SCB CCR: UNALIGN_TRP Mask */ + +/* SCB System Handler Control and State Register Definitions */ +#define SCB_SHCSR_SVCALLPENDED_Pos 15 /*!< SCB SHCSR: SVCALLPENDED Position */ +#define SCB_SHCSR_SVCALLPENDED_Msk (1UL << SCB_SHCSR_SVCALLPENDED_Pos) /*!< SCB SHCSR: SVCALLPENDED Mask */ + +/*@} end of group CMSIS_SCB */ + + +/** \ingroup CMSIS_core_register + \defgroup CMSIS_SysTick System Tick Timer (SysTick) + \brief Type definitions for the System Timer Registers. + @{ + */ + +/** \brief Structure type to access the System Timer (SysTick). + */ +typedef struct +{ + __IO uint32_t CTRL; /*!< Offset: 0x000 (R/W) SysTick Control and Status Register */ + __IO uint32_t LOAD; /*!< Offset: 0x004 (R/W) SysTick Reload Value Register */ + __IO uint32_t VAL; /*!< Offset: 0x008 (R/W) SysTick Current Value Register */ + __I uint32_t CALIB; /*!< Offset: 0x00C (R/ ) SysTick Calibration Register */ +} SysTick_Type; + +/* SysTick Control / Status Register Definitions */ +#define SysTick_CTRL_COUNTFLAG_Pos 16 /*!< SysTick CTRL: COUNTFLAG Position */ +#define SysTick_CTRL_COUNTFLAG_Msk (1UL << SysTick_CTRL_COUNTFLAG_Pos) /*!< SysTick CTRL: COUNTFLAG Mask */ + +#define SysTick_CTRL_CLKSOURCE_Pos 2 /*!< SysTick CTRL: CLKSOURCE Position */ +#define SysTick_CTRL_CLKSOURCE_Msk (1UL << SysTick_CTRL_CLKSOURCE_Pos) /*!< SysTick CTRL: CLKSOURCE Mask */ + +#define SysTick_CTRL_TICKINT_Pos 1 /*!< SysTick CTRL: TICKINT Position */ +#define SysTick_CTRL_TICKINT_Msk (1UL << SysTick_CTRL_TICKINT_Pos) /*!< SysTick CTRL: TICKINT Mask */ + +#define SysTick_CTRL_ENABLE_Pos 0 /*!< SysTick CTRL: ENABLE Position */ +#define SysTick_CTRL_ENABLE_Msk (1UL << SysTick_CTRL_ENABLE_Pos) /*!< SysTick CTRL: ENABLE Mask */ + +/* SysTick Reload Register Definitions */ +#define SysTick_LOAD_RELOAD_Pos 0 /*!< SysTick LOAD: RELOAD Position */ +#define SysTick_LOAD_RELOAD_Msk (0xFFFFFFUL << SysTick_LOAD_RELOAD_Pos) /*!< SysTick LOAD: RELOAD Mask */ + +/* SysTick Current Register Definitions */ +#define SysTick_VAL_CURRENT_Pos 0 /*!< SysTick VAL: CURRENT Position */ +#define SysTick_VAL_CURRENT_Msk (0xFFFFFFUL << SysTick_VAL_CURRENT_Pos) /*!< SysTick VAL: CURRENT Mask */ + +/* SysTick Calibration Register Definitions */ +#define SysTick_CALIB_NOREF_Pos 31 /*!< SysTick CALIB: NOREF Position */ +#define SysTick_CALIB_NOREF_Msk (1UL << SysTick_CALIB_NOREF_Pos) /*!< SysTick CALIB: NOREF Mask */ + +#define SysTick_CALIB_SKEW_Pos 30 /*!< SysTick CALIB: SKEW Position */ +#define SysTick_CALIB_SKEW_Msk (1UL << SysTick_CALIB_SKEW_Pos) /*!< SysTick CALIB: SKEW Mask */ + +#define SysTick_CALIB_TENMS_Pos 0 /*!< SysTick CALIB: TENMS Position */ +#define SysTick_CALIB_TENMS_Msk (0xFFFFFFUL << SysTick_VAL_CURRENT_Pos) /*!< SysTick CALIB: TENMS Mask */ + +/*@} end of group CMSIS_SysTick */ + + +/** \ingroup CMSIS_core_register + \defgroup CMSIS_CoreDebug Core Debug Registers (CoreDebug) + \brief Cortex-M0 Core Debug Registers (DCB registers, SHCSR, and DFSR) + are only accessible over DAP and not via processor. Therefore + they are not covered by the Cortex-M0 header file. + @{ + */ +/*@} end of group CMSIS_CoreDebug */ + + +/** \ingroup CMSIS_core_register + \defgroup CMSIS_core_base Core Definitions + \brief Definitions for base addresses, unions, and structures. + @{ + */ + +/* Memory mapping of Cortex-M0 Hardware */ +#define SCS_BASE (0xE000E000UL) /*!< System Control Space Base Address */ +#define SysTick_BASE (SCS_BASE + 0x0010UL) /*!< SysTick Base Address */ +#define NVIC_BASE (SCS_BASE + 0x0100UL) /*!< NVIC Base Address */ +#define SCB_BASE (SCS_BASE + 0x0D00UL) /*!< System Control Block Base Address */ + +#define SCB ((SCB_Type *) SCB_BASE ) /*!< SCB configuration struct */ +#define SysTick ((SysTick_Type *) SysTick_BASE ) /*!< SysTick configuration struct */ +#define NVIC ((NVIC_Type *) NVIC_BASE ) /*!< NVIC configuration struct */ + + +/*@} */ + + + +/******************************************************************************* + * Hardware Abstraction Layer + Core Function Interface contains: + - Core NVIC Functions + - Core SysTick Functions + - Core Register Access Functions + ******************************************************************************/ +/** \defgroup CMSIS_Core_FunctionInterface Functions and Instructions Reference +*/ + + + +/* ########################## NVIC functions #################################### */ +/** \ingroup CMSIS_Core_FunctionInterface + \defgroup CMSIS_Core_NVICFunctions NVIC Functions + \brief Functions that manage interrupts and exceptions via the NVIC. + @{ + */ + +/* Interrupt Priorities are WORD accessible only under ARMv6M */ +/* The following MACROS handle generation of the register offset and byte masks */ +#define _BIT_SHIFT(IRQn) ( (((uint32_t)(IRQn) ) & 0x03) * 8 ) +#define _SHP_IDX(IRQn) ( ((((uint32_t)(IRQn) & 0x0F)-8) >> 2) ) +#define _IP_IDX(IRQn) ( ((uint32_t)(IRQn) >> 2) ) + + +/** \brief Enable External Interrupt + + The function enables a device-specific interrupt in the NVIC interrupt controller. + + \param [in] IRQn External interrupt number. Value cannot be negative. + */ +__STATIC_INLINE void NVIC_EnableIRQ(IRQn_Type IRQn) +{ + NVIC->ISER[0] = (1 << ((uint32_t)(IRQn) & 0x1F)); +} + + +/** \brief Disable External Interrupt + + The function disables a device-specific interrupt in the NVIC interrupt controller. + + \param [in] IRQn External interrupt number. Value cannot be negative. + */ +__STATIC_INLINE void NVIC_DisableIRQ(IRQn_Type IRQn) +{ + NVIC->ICER[0] = (1 << ((uint32_t)(IRQn) & 0x1F)); +} + + +/** \brief Get Pending Interrupt + + The function reads the pending register in the NVIC and returns the pending bit + for the specified interrupt. + + \param [in] IRQn Interrupt number. + + \return 0 Interrupt status is not pending. + \return 1 Interrupt status is pending. + */ +__STATIC_INLINE uint32_t NVIC_GetPendingIRQ(IRQn_Type IRQn) +{ + return((uint32_t) ((NVIC->ISPR[0] & (1 << ((uint32_t)(IRQn) & 0x1F)))?1:0)); +} + + +/** \brief Set Pending Interrupt + + The function sets the pending bit of an external interrupt. + + \param [in] IRQn Interrupt number. Value cannot be negative. + */ +__STATIC_INLINE void NVIC_SetPendingIRQ(IRQn_Type IRQn) +{ + NVIC->ISPR[0] = (1 << ((uint32_t)(IRQn) & 0x1F)); +} + + +/** \brief Clear Pending Interrupt + + The function clears the pending bit of an external interrupt. + + \param [in] IRQn External interrupt number. Value cannot be negative. + */ +__STATIC_INLINE void NVIC_ClearPendingIRQ(IRQn_Type IRQn) +{ + NVIC->ICPR[0] = (1 << ((uint32_t)(IRQn) & 0x1F)); /* Clear pending interrupt */ +} + + +/** \brief Set Interrupt Priority + + The function sets the priority of an interrupt. + + \note The priority cannot be set for every core interrupt. + + \param [in] IRQn Interrupt number. + \param [in] priority Priority to set. + */ +__STATIC_INLINE void NVIC_SetPriority(IRQn_Type IRQn, uint32_t priority) +{ + if(IRQn < 0) { + SCB->SHP[_SHP_IDX(IRQn)] = (SCB->SHP[_SHP_IDX(IRQn)] & ~(0xFF << _BIT_SHIFT(IRQn))) | + (((priority << (8 - __NVIC_PRIO_BITS)) & 0xFF) << _BIT_SHIFT(IRQn)); } + else { + NVIC->IP[_IP_IDX(IRQn)] = (NVIC->IP[_IP_IDX(IRQn)] & ~(0xFF << _BIT_SHIFT(IRQn))) | + (((priority << (8 - __NVIC_PRIO_BITS)) & 0xFF) << _BIT_SHIFT(IRQn)); } +} + + +/** \brief Get Interrupt Priority + + The function reads the priority of an interrupt. The interrupt + number can be positive to specify an external (device specific) + interrupt, or negative to specify an internal (core) interrupt. + + + \param [in] IRQn Interrupt number. + \return Interrupt Priority. Value is aligned automatically to the implemented + priority bits of the microcontroller. + */ +__STATIC_INLINE uint32_t NVIC_GetPriority(IRQn_Type IRQn) +{ + + if(IRQn < 0) { + return((uint32_t)((SCB->SHP[_SHP_IDX(IRQn)] >> _BIT_SHIFT(IRQn) ) >> (8 - __NVIC_PRIO_BITS))); } /* get priority for Cortex-M0 system interrupts */ + else { + return((uint32_t)((NVIC->IP[ _IP_IDX(IRQn)] >> _BIT_SHIFT(IRQn) ) >> (8 - __NVIC_PRIO_BITS))); } /* get priority for device specific interrupts */ +} + + +/** \brief System Reset + + The function initiates a system reset request to reset the MCU. + */ +__STATIC_INLINE void NVIC_SystemReset(void) +{ + __DSB(); /* Ensure all outstanding memory accesses included + buffered write are completed before reset */ + SCB->AIRCR = ((0x5FA << SCB_AIRCR_VECTKEY_Pos) | + SCB_AIRCR_SYSRESETREQ_Msk); + __DSB(); /* Ensure completion of memory access */ + while(1); /* wait until reset */ +} + +/*@} end of CMSIS_Core_NVICFunctions */ + + + +/* ################################## SysTick function ############################################ */ +/** \ingroup CMSIS_Core_FunctionInterface + \defgroup CMSIS_Core_SysTickFunctions SysTick Functions + \brief Functions that configure the System. + @{ + */ + +#if (__Vendor_SysTickConfig == 0) + +/** \brief System Tick Configuration + + The function initializes the System Timer and its interrupt, and starts the System Tick Timer. + Counter is in free running mode to generate periodic interrupts. + + \param [in] ticks Number of ticks between two interrupts. + + \return 0 Function succeeded. + \return 1 Function failed. + + \note When the variable __Vendor_SysTickConfig is set to 1, then the + function SysTick_Config is not included. In this case, the file device.h + must contain a vendor-specific implementation of this function. + + */ +__STATIC_INLINE uint32_t SysTick_Config(uint32_t ticks) +{ + if (ticks > SysTick_LOAD_RELOAD_Msk) return (1); /* Reload value impossible */ + + SysTick->LOAD = (ticks & SysTick_LOAD_RELOAD_Msk) - 1; /* set reload register */ + NVIC_SetPriority (SysTick_IRQn, (1<<__NVIC_PRIO_BITS) - 1); /* set Priority for Systick Interrupt */ + SysTick->VAL = 0; /* Load the SysTick Counter Value */ + SysTick->CTRL = SysTick_CTRL_CLKSOURCE_Msk | + SysTick_CTRL_TICKINT_Msk | + SysTick_CTRL_ENABLE_Msk; /* Enable SysTick IRQ and SysTick Timer */ + return (0); /* Function successful */ +} + +#endif + +/*@} end of CMSIS_Core_SysTickFunctions */ + + + + +#endif /* __CORE_CM0_H_DEPENDANT */ + +#endif /* __CMSIS_GENERIC */ + +#ifdef __cplusplus +} +#endif diff --git a/Libraries/CMSIS/Include/core_cm0plus.h b/Libraries/CMSIS/Include/core_cm0plus.h new file mode 100644 index 0000000..aa20e68 --- /dev/null +++ b/Libraries/CMSIS/Include/core_cm0plus.h @@ -0,0 +1,778 @@ +/**************************************************************************//** + * @file core_cm0plus.h + * @brief CMSIS Cortex-M0+ Core Peripheral Access Layer Header File + * @version V3.01 + * @date 22. March 2012 + * + * @note + * Copyright (C) 2009-2012 ARM Limited. All rights reserved. + * + * @par + * ARM Limited (ARM) is supplying this software for use with Cortex-M + * processor based microcontrollers. This file can be freely distributed + * within development tools that are supporting such ARM based processors. + * + * @par + * THIS SOFTWARE IS PROVIDED "AS IS". NO WARRANTIES, WHETHER EXPRESS, IMPLIED + * OR STATUTORY, INCLUDING, BUT NOT LIMITED TO, IMPLIED WARRANTIES OF + * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE APPLY TO THIS SOFTWARE. + * ARM SHALL NOT, IN ANY CIRCUMSTANCES, BE LIABLE FOR SPECIAL, INCIDENTAL, OR + * CONSEQUENTIAL DAMAGES, FOR ANY REASON WHATSOEVER. + * + ******************************************************************************/ +#if defined ( __ICCARM__ ) + #pragma system_include /* treat file as system include file for MISRA check */ +#endif + +#ifdef __cplusplus + extern "C" { +#endif + +#ifndef __CORE_CM0PLUS_H_GENERIC +#define __CORE_CM0PLUS_H_GENERIC + +/** \page CMSIS_MISRA_Exceptions MISRA-C:2004 Compliance Exceptions + CMSIS violates the following MISRA-C:2004 rules: + + \li Required Rule 8.5, object/function definition in header file.
    + Function definitions in header files are used to allow 'inlining'. + + \li Required Rule 18.4, declaration of union type or object of union type: '{...}'.
    + Unions are used for effective representation of core registers. + + \li Advisory Rule 19.7, Function-like macro defined.
    + Function-like macros are used to allow more efficient code. + */ + + +/******************************************************************************* + * CMSIS definitions + ******************************************************************************/ +/** \ingroup Cortex-M0+ + @{ + */ + +/* CMSIS CM0P definitions */ +#define __CM0PLUS_CMSIS_VERSION_MAIN (0x03) /*!< [31:16] CMSIS HAL main version */ +#define __CM0PLUS_CMSIS_VERSION_SUB (0x01) /*!< [15:0] CMSIS HAL sub version */ +#define __CM0PLUS_CMSIS_VERSION ((__CM0PLUS_CMSIS_VERSION_MAIN << 16) | \ + __CM0PLUS_CMSIS_VERSION_SUB) /*!< CMSIS HAL version number */ + +#define __CORTEX_M (0x00) /*!< Cortex-M Core */ + + +#if defined ( __CC_ARM ) + #define __ASM __asm /*!< asm keyword for ARM Compiler */ + #define __INLINE __inline /*!< inline keyword for ARM Compiler */ + #define __STATIC_INLINE static __inline + +#elif defined ( __ICCARM__ ) + #define __ASM __asm /*!< asm keyword for IAR Compiler */ + #define __INLINE inline /*!< inline keyword for IAR Compiler. Only available in High optimization mode! */ + #define __STATIC_INLINE static inline + +#elif defined ( __GNUC__ ) + #define __ASM __asm /*!< asm keyword for GNU Compiler */ + #define __INLINE inline /*!< inline keyword for GNU Compiler */ + #define __STATIC_INLINE static inline + +#elif defined ( __TASKING__ ) + #define __ASM __asm /*!< asm keyword for TASKING Compiler */ + #define __INLINE inline /*!< inline keyword for TASKING Compiler */ + #define __STATIC_INLINE static inline + +#endif + +/** __FPU_USED indicates whether an FPU is used or not. This core does not support an FPU at all +*/ +#define __FPU_USED 0 + +#if defined ( __CC_ARM ) + #if defined __TARGET_FPU_VFP + #warning "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #endif + +#elif defined ( __ICCARM__ ) + #if defined __ARMVFP__ + #warning "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #endif + +#elif defined ( __GNUC__ ) + #if defined (__VFP_FP__) && !defined(__SOFTFP__) + #warning "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #endif + +#elif defined ( __TASKING__ ) + #if defined __FPU_VFP__ + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #endif +#endif + +#include /* standard types definitions */ +#include /* Core Instruction Access */ +#include /* Core Function Access */ + +#endif /* __CORE_CM0PLUS_H_GENERIC */ + +#ifndef __CMSIS_GENERIC + +#ifndef __CORE_CM0PLUS_H_DEPENDANT +#define __CORE_CM0PLUS_H_DEPENDANT + +/* check device defines and use defaults */ +#if defined __CHECK_DEVICE_DEFINES + #ifndef __CM0PLUS_REV + #define __CM0PLUS_REV 0x0000 + #warning "__CM0PLUS_REV not defined in device header file; using default!" + #endif + + #ifndef __MPU_PRESENT + #define __MPU_PRESENT 0 + #warning "__MPU_PRESENT not defined in device header file; using default!" + #endif + + #ifndef __VTOR_PRESENT + #define __VTOR_PRESENT 0 + #warning "__VTOR_PRESENT not defined in device header file; using default!" + #endif + + #ifndef __NVIC_PRIO_BITS + #define __NVIC_PRIO_BITS 2 + #warning "__NVIC_PRIO_BITS not defined in device header file; using default!" + #endif + + #ifndef __Vendor_SysTickConfig + #define __Vendor_SysTickConfig 0 + #warning "__Vendor_SysTickConfig not defined in device header file; using default!" + #endif +#endif + +/* IO definitions (access restrictions to peripheral registers) */ +/** + \defgroup CMSIS_glob_defs CMSIS Global Defines + + IO Type Qualifiers are used + \li to specify the access to peripheral variables. + \li for automatic generation of peripheral register debug information. +*/ +#ifdef __cplusplus + #define __I volatile /*!< Defines 'read only' permissions */ +#else + #define __I volatile const /*!< Defines 'read only' permissions */ +#endif +#define __O volatile /*!< Defines 'write only' permissions */ +#define __IO volatile /*!< Defines 'read / write' permissions */ + +/*@} end of group Cortex-M0+ */ + + + +/******************************************************************************* + * Register Abstraction + Core Register contain: + - Core Register + - Core NVIC Register + - Core SCB Register + - Core SysTick Register + - Core MPU Register + ******************************************************************************/ +/** \defgroup CMSIS_core_register Defines and Type Definitions + \brief Type definitions and defines for Cortex-M processor based devices. +*/ + +/** \ingroup CMSIS_core_register + \defgroup CMSIS_CORE Status and Control Registers + \brief Core Register type definitions. + @{ + */ + +/** \brief Union type to access the Application Program Status Register (APSR). + */ +typedef union +{ + struct + { +#if (__CORTEX_M != 0x04) + uint32_t _reserved0:27; /*!< bit: 0..26 Reserved */ +#else + uint32_t _reserved0:16; /*!< bit: 0..15 Reserved */ + uint32_t GE:4; /*!< bit: 16..19 Greater than or Equal flags */ + uint32_t _reserved1:7; /*!< bit: 20..26 Reserved */ +#endif + uint32_t Q:1; /*!< bit: 27 Saturation condition flag */ + uint32_t V:1; /*!< bit: 28 Overflow condition code flag */ + uint32_t C:1; /*!< bit: 29 Carry condition code flag */ + uint32_t Z:1; /*!< bit: 30 Zero condition code flag */ + uint32_t N:1; /*!< bit: 31 Negative condition code flag */ + } b; /*!< Structure used for bit access */ + uint32_t w; /*!< Type used for word access */ +} APSR_Type; + + +/** \brief Union type to access the Interrupt Program Status Register (IPSR). + */ +typedef union +{ + struct + { + uint32_t ISR:9; /*!< bit: 0.. 8 Exception number */ + uint32_t _reserved0:23; /*!< bit: 9..31 Reserved */ + } b; /*!< Structure used for bit access */ + uint32_t w; /*!< Type used for word access */ +} IPSR_Type; + + +/** \brief Union type to access the Special-Purpose Program Status Registers (xPSR). + */ +typedef union +{ + struct + { + uint32_t ISR:9; /*!< bit: 0.. 8 Exception number */ +#if (__CORTEX_M != 0x04) + uint32_t _reserved0:15; /*!< bit: 9..23 Reserved */ +#else + uint32_t _reserved0:7; /*!< bit: 9..15 Reserved */ + uint32_t GE:4; /*!< bit: 16..19 Greater than or Equal flags */ + uint32_t _reserved1:4; /*!< bit: 20..23 Reserved */ +#endif + uint32_t T:1; /*!< bit: 24 Thumb bit (read 0) */ + uint32_t IT:2; /*!< bit: 25..26 saved IT state (read 0) */ + uint32_t Q:1; /*!< bit: 27 Saturation condition flag */ + uint32_t V:1; /*!< bit: 28 Overflow condition code flag */ + uint32_t C:1; /*!< bit: 29 Carry condition code flag */ + uint32_t Z:1; /*!< bit: 30 Zero condition code flag */ + uint32_t N:1; /*!< bit: 31 Negative condition code flag */ + } b; /*!< Structure used for bit access */ + uint32_t w; /*!< Type used for word access */ +} xPSR_Type; + + +/** \brief Union type to access the Control Registers (CONTROL). + */ +typedef union +{ + struct + { + uint32_t nPRIV:1; /*!< bit: 0 Execution privilege in Thread mode */ + uint32_t SPSEL:1; /*!< bit: 1 Stack to be used */ + uint32_t FPCA:1; /*!< bit: 2 FP extension active flag */ + uint32_t _reserved0:29; /*!< bit: 3..31 Reserved */ + } b; /*!< Structure used for bit access */ + uint32_t w; /*!< Type used for word access */ +} CONTROL_Type; + +/*@} end of group CMSIS_CORE */ + + +/** \ingroup CMSIS_core_register + \defgroup CMSIS_NVIC Nested Vectored Interrupt Controller (NVIC) + \brief Type definitions for the NVIC Registers + @{ + */ + +/** \brief Structure type to access the Nested Vectored Interrupt Controller (NVIC). + */ +typedef struct +{ + __IO uint32_t ISER[1]; /*!< Offset: 0x000 (R/W) Interrupt Set Enable Register */ + uint32_t RESERVED0[31]; + __IO uint32_t ICER[1]; /*!< Offset: 0x080 (R/W) Interrupt Clear Enable Register */ + uint32_t RSERVED1[31]; + __IO uint32_t ISPR[1]; /*!< Offset: 0x100 (R/W) Interrupt Set Pending Register */ + uint32_t RESERVED2[31]; + __IO uint32_t ICPR[1]; /*!< Offset: 0x180 (R/W) Interrupt Clear Pending Register */ + uint32_t RESERVED3[31]; + uint32_t RESERVED4[64]; + __IO uint32_t IP[8]; /*!< Offset: 0x300 (R/W) Interrupt Priority Register */ +} NVIC_Type; + +/*@} end of group CMSIS_NVIC */ + + +/** \ingroup CMSIS_core_register + \defgroup CMSIS_SCB System Control Block (SCB) + \brief Type definitions for the System Control Block Registers + @{ + */ + +/** \brief Structure type to access the System Control Block (SCB). + */ +typedef struct +{ + __I uint32_t CPUID; /*!< Offset: 0x000 (R/ ) CPUID Base Register */ + __IO uint32_t ICSR; /*!< Offset: 0x004 (R/W) Interrupt Control and State Register */ +#if (__VTOR_PRESENT == 1) + __IO uint32_t VTOR; /*!< Offset: 0x008 (R/W) Vector Table Offset Register */ +#else + uint32_t RESERVED0; +#endif + __IO uint32_t AIRCR; /*!< Offset: 0x00C (R/W) Application Interrupt and Reset Control Register */ + __IO uint32_t SCR; /*!< Offset: 0x010 (R/W) System Control Register */ + __IO uint32_t CCR; /*!< Offset: 0x014 (R/W) Configuration Control Register */ + uint32_t RESERVED1; + __IO uint32_t SHP[2]; /*!< Offset: 0x01C (R/W) System Handlers Priority Registers. [0] is RESERVED */ + __IO uint32_t SHCSR; /*!< Offset: 0x024 (R/W) System Handler Control and State Register */ +} SCB_Type; + +/* SCB CPUID Register Definitions */ +#define SCB_CPUID_IMPLEMENTER_Pos 24 /*!< SCB CPUID: IMPLEMENTER Position */ +#define SCB_CPUID_IMPLEMENTER_Msk (0xFFUL << SCB_CPUID_IMPLEMENTER_Pos) /*!< SCB CPUID: IMPLEMENTER Mask */ + +#define SCB_CPUID_VARIANT_Pos 20 /*!< SCB CPUID: VARIANT Position */ +#define SCB_CPUID_VARIANT_Msk (0xFUL << SCB_CPUID_VARIANT_Pos) /*!< SCB CPUID: VARIANT Mask */ + +#define SCB_CPUID_ARCHITECTURE_Pos 16 /*!< SCB CPUID: ARCHITECTURE Position */ +#define SCB_CPUID_ARCHITECTURE_Msk (0xFUL << SCB_CPUID_ARCHITECTURE_Pos) /*!< SCB CPUID: ARCHITECTURE Mask */ + +#define SCB_CPUID_PARTNO_Pos 4 /*!< SCB CPUID: PARTNO Position */ +#define SCB_CPUID_PARTNO_Msk (0xFFFUL << SCB_CPUID_PARTNO_Pos) /*!< SCB CPUID: PARTNO Mask */ + +#define SCB_CPUID_REVISION_Pos 0 /*!< SCB CPUID: REVISION Position */ +#define SCB_CPUID_REVISION_Msk (0xFUL << SCB_CPUID_REVISION_Pos) /*!< SCB CPUID: REVISION Mask */ + +/* SCB Interrupt Control State Register Definitions */ +#define SCB_ICSR_NMIPENDSET_Pos 31 /*!< SCB ICSR: NMIPENDSET Position */ +#define SCB_ICSR_NMIPENDSET_Msk (1UL << SCB_ICSR_NMIPENDSET_Pos) /*!< SCB ICSR: NMIPENDSET Mask */ + +#define SCB_ICSR_PENDSVSET_Pos 28 /*!< SCB ICSR: PENDSVSET Position */ +#define SCB_ICSR_PENDSVSET_Msk (1UL << SCB_ICSR_PENDSVSET_Pos) /*!< SCB ICSR: PENDSVSET Mask */ + +#define SCB_ICSR_PENDSVCLR_Pos 27 /*!< SCB ICSR: PENDSVCLR Position */ +#define SCB_ICSR_PENDSVCLR_Msk (1UL << SCB_ICSR_PENDSVCLR_Pos) /*!< SCB ICSR: PENDSVCLR Mask */ + +#define SCB_ICSR_PENDSTSET_Pos 26 /*!< SCB ICSR: PENDSTSET Position */ +#define SCB_ICSR_PENDSTSET_Msk (1UL << SCB_ICSR_PENDSTSET_Pos) /*!< SCB ICSR: PENDSTSET Mask */ + +#define SCB_ICSR_PENDSTCLR_Pos 25 /*!< SCB ICSR: PENDSTCLR Position */ +#define SCB_ICSR_PENDSTCLR_Msk (1UL << SCB_ICSR_PENDSTCLR_Pos) /*!< SCB ICSR: PENDSTCLR Mask */ + +#define SCB_ICSR_ISRPREEMPT_Pos 23 /*!< SCB ICSR: ISRPREEMPT Position */ +#define SCB_ICSR_ISRPREEMPT_Msk (1UL << SCB_ICSR_ISRPREEMPT_Pos) /*!< SCB ICSR: ISRPREEMPT Mask */ + +#define SCB_ICSR_ISRPENDING_Pos 22 /*!< SCB ICSR: ISRPENDING Position */ +#define SCB_ICSR_ISRPENDING_Msk (1UL << SCB_ICSR_ISRPENDING_Pos) /*!< SCB ICSR: ISRPENDING Mask */ + +#define SCB_ICSR_VECTPENDING_Pos 12 /*!< SCB ICSR: VECTPENDING Position */ +#define SCB_ICSR_VECTPENDING_Msk (0x1FFUL << SCB_ICSR_VECTPENDING_Pos) /*!< SCB ICSR: VECTPENDING Mask */ + +#define SCB_ICSR_VECTACTIVE_Pos 0 /*!< SCB ICSR: VECTACTIVE Position */ +#define SCB_ICSR_VECTACTIVE_Msk (0x1FFUL << SCB_ICSR_VECTACTIVE_Pos) /*!< SCB ICSR: VECTACTIVE Mask */ + +#if (__VTOR_PRESENT == 1) +/* SCB Interrupt Control State Register Definitions */ +#define SCB_VTOR_TBLOFF_Pos 7 /*!< SCB VTOR: TBLOFF Position */ +#define SCB_VTOR_TBLOFF_Msk (0x1FFFFFFUL << SCB_VTOR_TBLOFF_Pos) /*!< SCB VTOR: TBLOFF Mask */ +#endif + +/* SCB Application Interrupt and Reset Control Register Definitions */ +#define SCB_AIRCR_VECTKEY_Pos 16 /*!< SCB AIRCR: VECTKEY Position */ +#define SCB_AIRCR_VECTKEY_Msk (0xFFFFUL << SCB_AIRCR_VECTKEY_Pos) /*!< SCB AIRCR: VECTKEY Mask */ + +#define SCB_AIRCR_VECTKEYSTAT_Pos 16 /*!< SCB AIRCR: VECTKEYSTAT Position */ +#define SCB_AIRCR_VECTKEYSTAT_Msk (0xFFFFUL << SCB_AIRCR_VECTKEYSTAT_Pos) /*!< SCB AIRCR: VECTKEYSTAT Mask */ + +#define SCB_AIRCR_ENDIANESS_Pos 15 /*!< SCB AIRCR: ENDIANESS Position */ +#define SCB_AIRCR_ENDIANESS_Msk (1UL << SCB_AIRCR_ENDIANESS_Pos) /*!< SCB AIRCR: ENDIANESS Mask */ + +#define SCB_AIRCR_SYSRESETREQ_Pos 2 /*!< SCB AIRCR: SYSRESETREQ Position */ +#define SCB_AIRCR_SYSRESETREQ_Msk (1UL << SCB_AIRCR_SYSRESETREQ_Pos) /*!< SCB AIRCR: SYSRESETREQ Mask */ + +#define SCB_AIRCR_VECTCLRACTIVE_Pos 1 /*!< SCB AIRCR: VECTCLRACTIVE Position */ +#define SCB_AIRCR_VECTCLRACTIVE_Msk (1UL << SCB_AIRCR_VECTCLRACTIVE_Pos) /*!< SCB AIRCR: VECTCLRACTIVE Mask */ + +/* SCB System Control Register Definitions */ +#define SCB_SCR_SEVONPEND_Pos 4 /*!< SCB SCR: SEVONPEND Position */ +#define SCB_SCR_SEVONPEND_Msk (1UL << SCB_SCR_SEVONPEND_Pos) /*!< SCB SCR: SEVONPEND Mask */ + +#define SCB_SCR_SLEEPDEEP_Pos 2 /*!< SCB SCR: SLEEPDEEP Position */ +#define SCB_SCR_SLEEPDEEP_Msk (1UL << SCB_SCR_SLEEPDEEP_Pos) /*!< SCB SCR: SLEEPDEEP Mask */ + +#define SCB_SCR_SLEEPONEXIT_Pos 1 /*!< SCB SCR: SLEEPONEXIT Position */ +#define SCB_SCR_SLEEPONEXIT_Msk (1UL << SCB_SCR_SLEEPONEXIT_Pos) /*!< SCB SCR: SLEEPONEXIT Mask */ + +/* SCB Configuration Control Register Definitions */ +#define SCB_CCR_STKALIGN_Pos 9 /*!< SCB CCR: STKALIGN Position */ +#define SCB_CCR_STKALIGN_Msk (1UL << SCB_CCR_STKALIGN_Pos) /*!< SCB CCR: STKALIGN Mask */ + +#define SCB_CCR_UNALIGN_TRP_Pos 3 /*!< SCB CCR: UNALIGN_TRP Position */ +#define SCB_CCR_UNALIGN_TRP_Msk (1UL << SCB_CCR_UNALIGN_TRP_Pos) /*!< SCB CCR: UNALIGN_TRP Mask */ + +/* SCB System Handler Control and State Register Definitions */ +#define SCB_SHCSR_SVCALLPENDED_Pos 15 /*!< SCB SHCSR: SVCALLPENDED Position */ +#define SCB_SHCSR_SVCALLPENDED_Msk (1UL << SCB_SHCSR_SVCALLPENDED_Pos) /*!< SCB SHCSR: SVCALLPENDED Mask */ + +/*@} end of group CMSIS_SCB */ + + +/** \ingroup CMSIS_core_register + \defgroup CMSIS_SysTick System Tick Timer (SysTick) + \brief Type definitions for the System Timer Registers. + @{ + */ + +/** \brief Structure type to access the System Timer (SysTick). + */ +typedef struct +{ + __IO uint32_t CTRL; /*!< Offset: 0x000 (R/W) SysTick Control and Status Register */ + __IO uint32_t LOAD; /*!< Offset: 0x004 (R/W) SysTick Reload Value Register */ + __IO uint32_t VAL; /*!< Offset: 0x008 (R/W) SysTick Current Value Register */ + __I uint32_t CALIB; /*!< Offset: 0x00C (R/ ) SysTick Calibration Register */ +} SysTick_Type; + +/* SysTick Control / Status Register Definitions */ +#define SysTick_CTRL_COUNTFLAG_Pos 16 /*!< SysTick CTRL: COUNTFLAG Position */ +#define SysTick_CTRL_COUNTFLAG_Msk (1UL << SysTick_CTRL_COUNTFLAG_Pos) /*!< SysTick CTRL: COUNTFLAG Mask */ + +#define SysTick_CTRL_CLKSOURCE_Pos 2 /*!< SysTick CTRL: CLKSOURCE Position */ +#define SysTick_CTRL_CLKSOURCE_Msk (1UL << SysTick_CTRL_CLKSOURCE_Pos) /*!< SysTick CTRL: CLKSOURCE Mask */ + +#define SysTick_CTRL_TICKINT_Pos 1 /*!< SysTick CTRL: TICKINT Position */ +#define SysTick_CTRL_TICKINT_Msk (1UL << SysTick_CTRL_TICKINT_Pos) /*!< SysTick CTRL: TICKINT Mask */ + +#define SysTick_CTRL_ENABLE_Pos 0 /*!< SysTick CTRL: ENABLE Position */ +#define SysTick_CTRL_ENABLE_Msk (1UL << SysTick_CTRL_ENABLE_Pos) /*!< SysTick CTRL: ENABLE Mask */ + +/* SysTick Reload Register Definitions */ +#define SysTick_LOAD_RELOAD_Pos 0 /*!< SysTick LOAD: RELOAD Position */ +#define SysTick_LOAD_RELOAD_Msk (0xFFFFFFUL << SysTick_LOAD_RELOAD_Pos) /*!< SysTick LOAD: RELOAD Mask */ + +/* SysTick Current Register Definitions */ +#define SysTick_VAL_CURRENT_Pos 0 /*!< SysTick VAL: CURRENT Position */ +#define SysTick_VAL_CURRENT_Msk (0xFFFFFFUL << SysTick_VAL_CURRENT_Pos) /*!< SysTick VAL: CURRENT Mask */ + +/* SysTick Calibration Register Definitions */ +#define SysTick_CALIB_NOREF_Pos 31 /*!< SysTick CALIB: NOREF Position */ +#define SysTick_CALIB_NOREF_Msk (1UL << SysTick_CALIB_NOREF_Pos) /*!< SysTick CALIB: NOREF Mask */ + +#define SysTick_CALIB_SKEW_Pos 30 /*!< SysTick CALIB: SKEW Position */ +#define SysTick_CALIB_SKEW_Msk (1UL << SysTick_CALIB_SKEW_Pos) /*!< SysTick CALIB: SKEW Mask */ + +#define SysTick_CALIB_TENMS_Pos 0 /*!< SysTick CALIB: TENMS Position */ +#define SysTick_CALIB_TENMS_Msk (0xFFFFFFUL << SysTick_VAL_CURRENT_Pos) /*!< SysTick CALIB: TENMS Mask */ + +/*@} end of group CMSIS_SysTick */ + +#if (__MPU_PRESENT == 1) +/** \ingroup CMSIS_core_register + \defgroup CMSIS_MPU Memory Protection Unit (MPU) + \brief Type definitions for the Memory Protection Unit (MPU) + @{ + */ + +/** \brief Structure type to access the Memory Protection Unit (MPU). + */ +typedef struct +{ + __I uint32_t TYPE; /*!< Offset: 0x000 (R/ ) MPU Type Register */ + __IO uint32_t CTRL; /*!< Offset: 0x004 (R/W) MPU Control Register */ + __IO uint32_t RNR; /*!< Offset: 0x008 (R/W) MPU Region RNRber Register */ + __IO uint32_t RBAR; /*!< Offset: 0x00C (R/W) MPU Region Base Address Register */ + __IO uint32_t RASR; /*!< Offset: 0x010 (R/W) MPU Region Attribute and Size Register */ +} MPU_Type; + +/* MPU Type Register */ +#define MPU_TYPE_IREGION_Pos 16 /*!< MPU TYPE: IREGION Position */ +#define MPU_TYPE_IREGION_Msk (0xFFUL << MPU_TYPE_IREGION_Pos) /*!< MPU TYPE: IREGION Mask */ + +#define MPU_TYPE_DREGION_Pos 8 /*!< MPU TYPE: DREGION Position */ +#define MPU_TYPE_DREGION_Msk (0xFFUL << MPU_TYPE_DREGION_Pos) /*!< MPU TYPE: DREGION Mask */ + +#define MPU_TYPE_SEPARATE_Pos 0 /*!< MPU TYPE: SEPARATE Position */ +#define MPU_TYPE_SEPARATE_Msk (1UL << MPU_TYPE_SEPARATE_Pos) /*!< MPU TYPE: SEPARATE Mask */ + +/* MPU Control Register */ +#define MPU_CTRL_PRIVDEFENA_Pos 2 /*!< MPU CTRL: PRIVDEFENA Position */ +#define MPU_CTRL_PRIVDEFENA_Msk (1UL << MPU_CTRL_PRIVDEFENA_Pos) /*!< MPU CTRL: PRIVDEFENA Mask */ + +#define MPU_CTRL_HFNMIENA_Pos 1 /*!< MPU CTRL: HFNMIENA Position */ +#define MPU_CTRL_HFNMIENA_Msk (1UL << MPU_CTRL_HFNMIENA_Pos) /*!< MPU CTRL: HFNMIENA Mask */ + +#define MPU_CTRL_ENABLE_Pos 0 /*!< MPU CTRL: ENABLE Position */ +#define MPU_CTRL_ENABLE_Msk (1UL << MPU_CTRL_ENABLE_Pos) /*!< MPU CTRL: ENABLE Mask */ + +/* MPU Region Number Register */ +#define MPU_RNR_REGION_Pos 0 /*!< MPU RNR: REGION Position */ +#define MPU_RNR_REGION_Msk (0xFFUL << MPU_RNR_REGION_Pos) /*!< MPU RNR: REGION Mask */ + +/* MPU Region Base Address Register */ +#define MPU_RBAR_ADDR_Pos 8 /*!< MPU RBAR: ADDR Position */ +#define MPU_RBAR_ADDR_Msk (0xFFFFFFUL << MPU_RBAR_ADDR_Pos) /*!< MPU RBAR: ADDR Mask */ + +#define MPU_RBAR_VALID_Pos 4 /*!< MPU RBAR: VALID Position */ +#define MPU_RBAR_VALID_Msk (1UL << MPU_RBAR_VALID_Pos) /*!< MPU RBAR: VALID Mask */ + +#define MPU_RBAR_REGION_Pos 0 /*!< MPU RBAR: REGION Position */ +#define MPU_RBAR_REGION_Msk (0xFUL << MPU_RBAR_REGION_Pos) /*!< MPU RBAR: REGION Mask */ + +/* MPU Region Attribute and Size Register */ +#define MPU_RASR_ATTRS_Pos 16 /*!< MPU RASR: MPU Region Attribute field Position */ +#define MPU_RASR_ATTRS_Msk (0xFFFFUL << MPU_RASR_ATTRS_Pos) /*!< MPU RASR: MPU Region Attribute field Mask */ + +#define MPU_RASR_XN_Pos 28 /*!< MPU RASR: ATTRS.XN Position */ +#define MPU_RASR_XN_Msk (1UL << MPU_RASR_XN_Pos) /*!< MPU RASR: ATTRS.XN Mask */ + +#define MPU_RASR_AP_Pos 24 /*!< MPU RASR: ATTRS.AP Position */ +#define MPU_RASR_AP_Msk (0x7UL << MPU_RASR_AP_Pos) /*!< MPU RASR: ATTRS.AP Mask */ + +#define MPU_RASR_TEX_Pos 19 /*!< MPU RASR: ATTRS.TEX Position */ +#define MPU_RASR_TEX_Msk (0x7UL << MPU_RASR_TEX_Pos) /*!< MPU RASR: ATTRS.TEX Mask */ + +#define MPU_RASR_S_Pos 18 /*!< MPU RASR: ATTRS.S Position */ +#define MPU_RASR_S_Msk (1UL << MPU_RASR_S_Pos) /*!< MPU RASR: ATTRS.S Mask */ + +#define MPU_RASR_C_Pos 17 /*!< MPU RASR: ATTRS.C Position */ +#define MPU_RASR_C_Msk (1UL << MPU_RASR_C_Pos) /*!< MPU RASR: ATTRS.C Mask */ + +#define MPU_RASR_B_Pos 16 /*!< MPU RASR: ATTRS.B Position */ +#define MPU_RASR_B_Msk (1UL << MPU_RASR_B_Pos) /*!< MPU RASR: ATTRS.B Mask */ + +#define MPU_RASR_SRD_Pos 8 /*!< MPU RASR: Sub-Region Disable Position */ +#define MPU_RASR_SRD_Msk (0xFFUL << MPU_RASR_SRD_Pos) /*!< MPU RASR: Sub-Region Disable Mask */ + +#define MPU_RASR_SIZE_Pos 1 /*!< MPU RASR: Region Size Field Position */ +#define MPU_RASR_SIZE_Msk (0x1FUL << MPU_RASR_SIZE_Pos) /*!< MPU RASR: Region Size Field Mask */ + +#define MPU_RASR_ENABLE_Pos 0 /*!< MPU RASR: Region enable bit Position */ +#define MPU_RASR_ENABLE_Msk (1UL << MPU_RASR_ENABLE_Pos) /*!< MPU RASR: Region enable bit Disable Mask */ + +/*@} end of group CMSIS_MPU */ +#endif + + +/** \ingroup CMSIS_core_register + \defgroup CMSIS_CoreDebug Core Debug Registers (CoreDebug) + \brief Cortex-M0+ Core Debug Registers (DCB registers, SHCSR, and DFSR) + are only accessible over DAP and not via processor. Therefore + they are not covered by the Cortex-M0 header file. + @{ + */ +/*@} end of group CMSIS_CoreDebug */ + + +/** \ingroup CMSIS_core_register + \defgroup CMSIS_core_base Core Definitions + \brief Definitions for base addresses, unions, and structures. + @{ + */ + +/* Memory mapping of Cortex-M0+ Hardware */ +#define SCS_BASE (0xE000E000UL) /*!< System Control Space Base Address */ +#define SysTick_BASE (SCS_BASE + 0x0010UL) /*!< SysTick Base Address */ +#define NVIC_BASE (SCS_BASE + 0x0100UL) /*!< NVIC Base Address */ +#define SCB_BASE (SCS_BASE + 0x0D00UL) /*!< System Control Block Base Address */ + +#define SCB ((SCB_Type *) SCB_BASE ) /*!< SCB configuration struct */ +#define SysTick ((SysTick_Type *) SysTick_BASE ) /*!< SysTick configuration struct */ +#define NVIC ((NVIC_Type *) NVIC_BASE ) /*!< NVIC configuration struct */ + +#if (__MPU_PRESENT == 1) + #define MPU_BASE (SCS_BASE + 0x0D90UL) /*!< Memory Protection Unit */ + #define MPU ((MPU_Type *) MPU_BASE ) /*!< Memory Protection Unit */ +#endif + +/*@} */ + + + +/******************************************************************************* + * Hardware Abstraction Layer + Core Function Interface contains: + - Core NVIC Functions + - Core SysTick Functions + - Core Register Access Functions + ******************************************************************************/ +/** \defgroup CMSIS_Core_FunctionInterface Functions and Instructions Reference +*/ + + + +/* ########################## NVIC functions #################################### */ +/** \ingroup CMSIS_Core_FunctionInterface + \defgroup CMSIS_Core_NVICFunctions NVIC Functions + \brief Functions that manage interrupts and exceptions via the NVIC. + @{ + */ + +/* Interrupt Priorities are WORD accessible only under ARMv6M */ +/* The following MACROS handle generation of the register offset and byte masks */ +#define _BIT_SHIFT(IRQn) ( (((uint32_t)(IRQn) ) & 0x03) * 8 ) +#define _SHP_IDX(IRQn) ( ((((uint32_t)(IRQn) & 0x0F)-8) >> 2) ) +#define _IP_IDX(IRQn) ( ((uint32_t)(IRQn) >> 2) ) + + +/** \brief Enable External Interrupt + + The function enables a device-specific interrupt in the NVIC interrupt controller. + + \param [in] IRQn External interrupt number. Value cannot be negative. + */ +__STATIC_INLINE void NVIC_EnableIRQ(IRQn_Type IRQn) +{ + NVIC->ISER[0] = (1 << ((uint32_t)(IRQn) & 0x1F)); +} + + +/** \brief Disable External Interrupt + + The function disables a device-specific interrupt in the NVIC interrupt controller. + + \param [in] IRQn External interrupt number. Value cannot be negative. + */ +__STATIC_INLINE void NVIC_DisableIRQ(IRQn_Type IRQn) +{ + NVIC->ICER[0] = (1 << ((uint32_t)(IRQn) & 0x1F)); +} + + +/** \brief Get Pending Interrupt + + The function reads the pending register in the NVIC and returns the pending bit + for the specified interrupt. + + \param [in] IRQn Interrupt number. + + \return 0 Interrupt status is not pending. + \return 1 Interrupt status is pending. + */ +__STATIC_INLINE uint32_t NVIC_GetPendingIRQ(IRQn_Type IRQn) +{ + return((uint32_t) ((NVIC->ISPR[0] & (1 << ((uint32_t)(IRQn) & 0x1F)))?1:0)); +} + + +/** \brief Set Pending Interrupt + + The function sets the pending bit of an external interrupt. + + \param [in] IRQn Interrupt number. Value cannot be negative. + */ +__STATIC_INLINE void NVIC_SetPendingIRQ(IRQn_Type IRQn) +{ + NVIC->ISPR[0] = (1 << ((uint32_t)(IRQn) & 0x1F)); +} + + +/** \brief Clear Pending Interrupt + + The function clears the pending bit of an external interrupt. + + \param [in] IRQn External interrupt number. Value cannot be negative. + */ +__STATIC_INLINE void NVIC_ClearPendingIRQ(IRQn_Type IRQn) +{ + NVIC->ICPR[0] = (1 << ((uint32_t)(IRQn) & 0x1F)); /* Clear pending interrupt */ +} + + +/** \brief Set Interrupt Priority + + The function sets the priority of an interrupt. + + \note The priority cannot be set for every core interrupt. + + \param [in] IRQn Interrupt number. + \param [in] priority Priority to set. + */ +__STATIC_INLINE void NVIC_SetPriority(IRQn_Type IRQn, uint32_t priority) +{ + if(IRQn < 0) { + SCB->SHP[_SHP_IDX(IRQn)] = (SCB->SHP[_SHP_IDX(IRQn)] & ~(0xFF << _BIT_SHIFT(IRQn))) | + (((priority << (8 - __NVIC_PRIO_BITS)) & 0xFF) << _BIT_SHIFT(IRQn)); } + else { + NVIC->IP[_IP_IDX(IRQn)] = (NVIC->IP[_IP_IDX(IRQn)] & ~(0xFF << _BIT_SHIFT(IRQn))) | + (((priority << (8 - __NVIC_PRIO_BITS)) & 0xFF) << _BIT_SHIFT(IRQn)); } +} + + +/** \brief Get Interrupt Priority + + The function reads the priority of an interrupt. The interrupt + number can be positive to specify an external (device specific) + interrupt, or negative to specify an internal (core) interrupt. + + + \param [in] IRQn Interrupt number. + \return Interrupt Priority. Value is aligned automatically to the implemented + priority bits of the microcontroller. + */ +__STATIC_INLINE uint32_t NVIC_GetPriority(IRQn_Type IRQn) +{ + + if(IRQn < 0) { + return((uint32_t)((SCB->SHP[_SHP_IDX(IRQn)] >> _BIT_SHIFT(IRQn) ) >> (8 - __NVIC_PRIO_BITS))); } /* get priority for Cortex-M0+ system interrupts */ + else { + return((uint32_t)((NVIC->IP[ _IP_IDX(IRQn)] >> _BIT_SHIFT(IRQn) ) >> (8 - __NVIC_PRIO_BITS))); } /* get priority for device specific interrupts */ +} + + +/** \brief System Reset + + The function initiates a system reset request to reset the MCU. + */ +__STATIC_INLINE void NVIC_SystemReset(void) +{ + __DSB(); /* Ensure all outstanding memory accesses included + buffered write are completed before reset */ + SCB->AIRCR = ((0x5FA << SCB_AIRCR_VECTKEY_Pos) | + SCB_AIRCR_SYSRESETREQ_Msk); + __DSB(); /* Ensure completion of memory access */ + while(1); /* wait until reset */ +} + +/*@} end of CMSIS_Core_NVICFunctions */ + + + +/* ################################## SysTick function ############################################ */ +/** \ingroup CMSIS_Core_FunctionInterface + \defgroup CMSIS_Core_SysTickFunctions SysTick Functions + \brief Functions that configure the System. + @{ + */ + +#if (__Vendor_SysTickConfig == 0) + +/** \brief System Tick Configuration + + The function initializes the System Timer and its interrupt, and starts the System Tick Timer. + Counter is in free running mode to generate periodic interrupts. + + \param [in] ticks Number of ticks between two interrupts. + + \return 0 Function succeeded. + \return 1 Function failed. + + \note When the variable __Vendor_SysTickConfig is set to 1, then the + function SysTick_Config is not included. In this case, the file device.h + must contain a vendor-specific implementation of this function. + + */ +__STATIC_INLINE uint32_t SysTick_Config(uint32_t ticks) +{ + if (ticks > SysTick_LOAD_RELOAD_Msk) return (1); /* Reload value impossible */ + + SysTick->LOAD = (ticks & SysTick_LOAD_RELOAD_Msk) - 1; /* set reload register */ + NVIC_SetPriority (SysTick_IRQn, (1<<__NVIC_PRIO_BITS) - 1); /* set Priority for Systick Interrupt */ + SysTick->VAL = 0; /* Load the SysTick Counter Value */ + SysTick->CTRL = SysTick_CTRL_CLKSOURCE_Msk | + SysTick_CTRL_TICKINT_Msk | + SysTick_CTRL_ENABLE_Msk; /* Enable SysTick IRQ and SysTick Timer */ + return (0); /* Function successful */ +} + +#endif + +/*@} end of CMSIS_Core_SysTickFunctions */ + + + + +#endif /* __CORE_CM0PLUS_H_DEPENDANT */ + +#endif /* __CMSIS_GENERIC */ + +#ifdef __cplusplus +} +#endif diff --git a/Libraries/CMSIS/Include/core_cm3.h b/Libraries/CMSIS/Include/core_cm3.h new file mode 100644 index 0000000..0173893 --- /dev/null +++ b/Libraries/CMSIS/Include/core_cm3.h @@ -0,0 +1,1612 @@ +/**************************************************************************//** + * @file core_cm3.h + * @brief CMSIS Cortex-M3 Core Peripheral Access Layer Header File + * @version V3.01 + * @date 22. March 2012 + * + * @note + * Copyright (C) 2009-2012 ARM Limited. All rights reserved. + * + * @par + * ARM Limited (ARM) is supplying this software for use with Cortex-M + * processor based microcontrollers. This file can be freely distributed + * within development tools that are supporting such ARM based processors. + * + * @par + * THIS SOFTWARE IS PROVIDED "AS IS". NO WARRANTIES, WHETHER EXPRESS, IMPLIED + * OR STATUTORY, INCLUDING, BUT NOT LIMITED TO, IMPLIED WARRANTIES OF + * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE APPLY TO THIS SOFTWARE. + * ARM SHALL NOT, IN ANY CIRCUMSTANCES, BE LIABLE FOR SPECIAL, INCIDENTAL, OR + * CONSEQUENTIAL DAMAGES, FOR ANY REASON WHATSOEVER. + * + ******************************************************************************/ +#if defined ( __ICCARM__ ) + #pragma system_include /* treat file as system include file for MISRA check */ +#endif + +#ifdef __cplusplus + extern "C" { +#endif + +#ifndef __CORE_CM3_H_GENERIC +#define __CORE_CM3_H_GENERIC + +/** \page CMSIS_MISRA_Exceptions MISRA-C:2004 Compliance Exceptions + CMSIS violates the following MISRA-C:2004 rules: + + \li Required Rule 8.5, object/function definition in header file.
    + Function definitions in header files are used to allow 'inlining'. + + \li Required Rule 18.4, declaration of union type or object of union type: '{...}'.
    + Unions are used for effective representation of core registers. + + \li Advisory Rule 19.7, Function-like macro defined.
    + Function-like macros are used to allow more efficient code. + */ + + +/******************************************************************************* + * CMSIS definitions + ******************************************************************************/ +/** \ingroup Cortex_M3 + @{ + */ + +/* CMSIS CM3 definitions */ +#define __CM3_CMSIS_VERSION_MAIN (0x03) /*!< [31:16] CMSIS HAL main version */ +#define __CM3_CMSIS_VERSION_SUB (0x01) /*!< [15:0] CMSIS HAL sub version */ +#define __CM3_CMSIS_VERSION ((__CM3_CMSIS_VERSION_MAIN << 16) | \ + __CM3_CMSIS_VERSION_SUB ) /*!< CMSIS HAL version number */ + +#define __CORTEX_M (0x03) /*!< Cortex-M Core */ + + +#if defined ( __CC_ARM ) + #define __ASM __asm /*!< asm keyword for ARM Compiler */ + #define __INLINE __inline /*!< inline keyword for ARM Compiler */ + #define __STATIC_INLINE static __inline + +#elif defined ( __ICCARM__ ) + #define __ASM __asm /*!< asm keyword for IAR Compiler */ + #define __INLINE inline /*!< inline keyword for IAR Compiler. Only available in High optimization mode! */ + #define __STATIC_INLINE static inline + +#elif defined ( __TMS470__ ) + #define __ASM __asm /*!< asm keyword for TI CCS Compiler */ + #define __STATIC_INLINE static inline + +#elif defined ( __GNUC__ ) + #define __ASM __asm /*!< asm keyword for GNU Compiler */ + #define __INLINE inline /*!< inline keyword for GNU Compiler */ + #define __STATIC_INLINE static inline + +#elif defined ( __TASKING__ ) + #define __ASM __asm /*!< asm keyword for TASKING Compiler */ + #define __INLINE inline /*!< inline keyword for TASKING Compiler */ + #define __STATIC_INLINE static inline + +#endif + +/** __FPU_USED indicates whether an FPU is used or not. This core does not support an FPU at all +*/ +#define __FPU_USED 0 + +#if defined ( __CC_ARM ) + #if defined __TARGET_FPU_VFP + #warning "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #endif + +#elif defined ( __ICCARM__ ) + #if defined __ARMVFP__ + #warning "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #endif + +#elif defined ( __TMS470__ ) + #if defined __TI__VFP_SUPPORT____ + #warning "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #endif + +#elif defined ( __GNUC__ ) + #if defined (__VFP_FP__) && !defined(__SOFTFP__) + #warning "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #endif + +#elif defined ( __TASKING__ ) + #if defined __FPU_VFP__ + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #endif +#endif + +#include /* standard types definitions */ +#include /* Core Instruction Access */ +#include /* Core Function Access */ + +#endif /* __CORE_CM3_H_GENERIC */ + +#ifndef __CMSIS_GENERIC + +#ifndef __CORE_CM3_H_DEPENDANT +#define __CORE_CM3_H_DEPENDANT + +/* check device defines and use defaults */ +#if defined __CHECK_DEVICE_DEFINES + #ifndef __CM3_REV + #define __CM3_REV 0x0200 + #warning "__CM3_REV not defined in device header file; using default!" + #endif + + #ifndef __MPU_PRESENT + #define __MPU_PRESENT 0 + #warning "__MPU_PRESENT not defined in device header file; using default!" + #endif + + #ifndef __NVIC_PRIO_BITS + #define __NVIC_PRIO_BITS 4 + #warning "__NVIC_PRIO_BITS not defined in device header file; using default!" + #endif + + #ifndef __Vendor_SysTickConfig + #define __Vendor_SysTickConfig 0 + #warning "__Vendor_SysTickConfig not defined in device header file; using default!" + #endif +#endif + +/* IO definitions (access restrictions to peripheral registers) */ +/** + \defgroup CMSIS_glob_defs CMSIS Global Defines + + IO Type Qualifiers are used + \li to specify the access to peripheral variables. + \li for automatic generation of peripheral register debug information. +*/ +#ifdef __cplusplus + #define __I volatile /*!< Defines 'read only' permissions */ +#else + #define __I volatile const /*!< Defines 'read only' permissions */ +#endif +#define __O volatile /*!< Defines 'write only' permissions */ +#define __IO volatile /*!< Defines 'read / write' permissions */ + +/*@} end of group Cortex_M3 */ + + + +/******************************************************************************* + * Register Abstraction + Core Register contain: + - Core Register + - Core NVIC Register + - Core SCB Register + - Core SysTick Register + - Core Debug Register + - Core MPU Register + ******************************************************************************/ +/** \defgroup CMSIS_core_register Defines and Type Definitions + \brief Type definitions and defines for Cortex-M processor based devices. +*/ + +/** \ingroup CMSIS_core_register + \defgroup CMSIS_CORE Status and Control Registers + \brief Core Register type definitions. + @{ + */ + +/** \brief Union type to access the Application Program Status Register (APSR). + */ +typedef union +{ + struct + { +#if (__CORTEX_M != 0x04) + uint32_t _reserved0:27; /*!< bit: 0..26 Reserved */ +#else + uint32_t _reserved0:16; /*!< bit: 0..15 Reserved */ + uint32_t GE:4; /*!< bit: 16..19 Greater than or Equal flags */ + uint32_t _reserved1:7; /*!< bit: 20..26 Reserved */ +#endif + uint32_t Q:1; /*!< bit: 27 Saturation condition flag */ + uint32_t V:1; /*!< bit: 28 Overflow condition code flag */ + uint32_t C:1; /*!< bit: 29 Carry condition code flag */ + uint32_t Z:1; /*!< bit: 30 Zero condition code flag */ + uint32_t N:1; /*!< bit: 31 Negative condition code flag */ + } b; /*!< Structure used for bit access */ + uint32_t w; /*!< Type used for word access */ +} APSR_Type; + + +/** \brief Union type to access the Interrupt Program Status Register (IPSR). + */ +typedef union +{ + struct + { + uint32_t ISR:9; /*!< bit: 0.. 8 Exception number */ + uint32_t _reserved0:23; /*!< bit: 9..31 Reserved */ + } b; /*!< Structure used for bit access */ + uint32_t w; /*!< Type used for word access */ +} IPSR_Type; + + +/** \brief Union type to access the Special-Purpose Program Status Registers (xPSR). + */ +typedef union +{ + struct + { + uint32_t ISR:9; /*!< bit: 0.. 8 Exception number */ +#if (__CORTEX_M != 0x04) + uint32_t _reserved0:15; /*!< bit: 9..23 Reserved */ +#else + uint32_t _reserved0:7; /*!< bit: 9..15 Reserved */ + uint32_t GE:4; /*!< bit: 16..19 Greater than or Equal flags */ + uint32_t _reserved1:4; /*!< bit: 20..23 Reserved */ +#endif + uint32_t T:1; /*!< bit: 24 Thumb bit (read 0) */ + uint32_t IT:2; /*!< bit: 25..26 saved IT state (read 0) */ + uint32_t Q:1; /*!< bit: 27 Saturation condition flag */ + uint32_t V:1; /*!< bit: 28 Overflow condition code flag */ + uint32_t C:1; /*!< bit: 29 Carry condition code flag */ + uint32_t Z:1; /*!< bit: 30 Zero condition code flag */ + uint32_t N:1; /*!< bit: 31 Negative condition code flag */ + } b; /*!< Structure used for bit access */ + uint32_t w; /*!< Type used for word access */ +} xPSR_Type; + + +/** \brief Union type to access the Control Registers (CONTROL). + */ +typedef union +{ + struct + { + uint32_t nPRIV:1; /*!< bit: 0 Execution privilege in Thread mode */ + uint32_t SPSEL:1; /*!< bit: 1 Stack to be used */ + uint32_t FPCA:1; /*!< bit: 2 FP extension active flag */ + uint32_t _reserved0:29; /*!< bit: 3..31 Reserved */ + } b; /*!< Structure used for bit access */ + uint32_t w; /*!< Type used for word access */ +} CONTROL_Type; + +/*@} end of group CMSIS_CORE */ + + +/** \ingroup CMSIS_core_register + \defgroup CMSIS_NVIC Nested Vectored Interrupt Controller (NVIC) + \brief Type definitions for the NVIC Registers + @{ + */ + +/** \brief Structure type to access the Nested Vectored Interrupt Controller (NVIC). + */ +typedef struct +{ + __IO uint32_t ISER[8]; /*!< Offset: 0x000 (R/W) Interrupt Set Enable Register */ + uint32_t RESERVED0[24]; + __IO uint32_t ICER[8]; /*!< Offset: 0x080 (R/W) Interrupt Clear Enable Register */ + uint32_t RSERVED1[24]; + __IO uint32_t ISPR[8]; /*!< Offset: 0x100 (R/W) Interrupt Set Pending Register */ + uint32_t RESERVED2[24]; + __IO uint32_t ICPR[8]; /*!< Offset: 0x180 (R/W) Interrupt Clear Pending Register */ + uint32_t RESERVED3[24]; + __IO uint32_t IABR[8]; /*!< Offset: 0x200 (R/W) Interrupt Active bit Register */ + uint32_t RESERVED4[56]; + __IO uint8_t IP[240]; /*!< Offset: 0x300 (R/W) Interrupt Priority Register (8Bit wide) */ + uint32_t RESERVED5[644]; + __O uint32_t STIR; /*!< Offset: 0xE00 ( /W) Software Trigger Interrupt Register */ +} NVIC_Type; + +/* Software Triggered Interrupt Register Definitions */ +#define NVIC_STIR_INTID_Pos 0 /*!< STIR: INTLINESNUM Position */ +#define NVIC_STIR_INTID_Msk (0x1FFUL << NVIC_STIR_INTID_Pos) /*!< STIR: INTLINESNUM Mask */ + +/*@} end of group CMSIS_NVIC */ + + +/** \ingroup CMSIS_core_register + \defgroup CMSIS_SCB System Control Block (SCB) + \brief Type definitions for the System Control Block Registers + @{ + */ + +/** \brief Structure type to access the System Control Block (SCB). + */ +typedef struct +{ + __I uint32_t CPUID; /*!< Offset: 0x000 (R/ ) CPUID Base Register */ + __IO uint32_t ICSR; /*!< Offset: 0x004 (R/W) Interrupt Control and State Register */ + __IO uint32_t VTOR; /*!< Offset: 0x008 (R/W) Vector Table Offset Register */ + __IO uint32_t AIRCR; /*!< Offset: 0x00C (R/W) Application Interrupt and Reset Control Register */ + __IO uint32_t SCR; /*!< Offset: 0x010 (R/W) System Control Register */ + __IO uint32_t CCR; /*!< Offset: 0x014 (R/W) Configuration Control Register */ + __IO uint8_t SHP[12]; /*!< Offset: 0x018 (R/W) System Handlers Priority Registers (4-7, 8-11, 12-15) */ + __IO uint32_t SHCSR; /*!< Offset: 0x024 (R/W) System Handler Control and State Register */ + __IO uint32_t CFSR; /*!< Offset: 0x028 (R/W) Configurable Fault Status Register */ + __IO uint32_t HFSR; /*!< Offset: 0x02C (R/W) HardFault Status Register */ + __IO uint32_t DFSR; /*!< Offset: 0x030 (R/W) Debug Fault Status Register */ + __IO uint32_t MMFAR; /*!< Offset: 0x034 (R/W) MemManage Fault Address Register */ + __IO uint32_t BFAR; /*!< Offset: 0x038 (R/W) BusFault Address Register */ + __IO uint32_t AFSR; /*!< Offset: 0x03C (R/W) Auxiliary Fault Status Register */ + __I uint32_t PFR[2]; /*!< Offset: 0x040 (R/ ) Processor Feature Register */ + __I uint32_t DFR; /*!< Offset: 0x048 (R/ ) Debug Feature Register */ + __I uint32_t ADR; /*!< Offset: 0x04C (R/ ) Auxiliary Feature Register */ + __I uint32_t MMFR[4]; /*!< Offset: 0x050 (R/ ) Memory Model Feature Register */ + __I uint32_t ISAR[5]; /*!< Offset: 0x060 (R/ ) Instruction Set Attributes Register */ + uint32_t RESERVED0[5]; + __IO uint32_t CPACR; /*!< Offset: 0x088 (R/W) Coprocessor Access Control Register */ +} SCB_Type; + +/* SCB CPUID Register Definitions */ +#define SCB_CPUID_IMPLEMENTER_Pos 24 /*!< SCB CPUID: IMPLEMENTER Position */ +#define SCB_CPUID_IMPLEMENTER_Msk (0xFFUL << SCB_CPUID_IMPLEMENTER_Pos) /*!< SCB CPUID: IMPLEMENTER Mask */ + +#define SCB_CPUID_VARIANT_Pos 20 /*!< SCB CPUID: VARIANT Position */ +#define SCB_CPUID_VARIANT_Msk (0xFUL << SCB_CPUID_VARIANT_Pos) /*!< SCB CPUID: VARIANT Mask */ + +#define SCB_CPUID_ARCHITECTURE_Pos 16 /*!< SCB CPUID: ARCHITECTURE Position */ +#define SCB_CPUID_ARCHITECTURE_Msk (0xFUL << SCB_CPUID_ARCHITECTURE_Pos) /*!< SCB CPUID: ARCHITECTURE Mask */ + +#define SCB_CPUID_PARTNO_Pos 4 /*!< SCB CPUID: PARTNO Position */ +#define SCB_CPUID_PARTNO_Msk (0xFFFUL << SCB_CPUID_PARTNO_Pos) /*!< SCB CPUID: PARTNO Mask */ + +#define SCB_CPUID_REVISION_Pos 0 /*!< SCB CPUID: REVISION Position */ +#define SCB_CPUID_REVISION_Msk (0xFUL << SCB_CPUID_REVISION_Pos) /*!< SCB CPUID: REVISION Mask */ + +/* SCB Interrupt Control State Register Definitions */ +#define SCB_ICSR_NMIPENDSET_Pos 31 /*!< SCB ICSR: NMIPENDSET Position */ +#define SCB_ICSR_NMIPENDSET_Msk (1UL << SCB_ICSR_NMIPENDSET_Pos) /*!< SCB ICSR: NMIPENDSET Mask */ + +#define SCB_ICSR_PENDSVSET_Pos 28 /*!< SCB ICSR: PENDSVSET Position */ +#define SCB_ICSR_PENDSVSET_Msk (1UL << SCB_ICSR_PENDSVSET_Pos) /*!< SCB ICSR: PENDSVSET Mask */ + +#define SCB_ICSR_PENDSVCLR_Pos 27 /*!< SCB ICSR: PENDSVCLR Position */ +#define SCB_ICSR_PENDSVCLR_Msk (1UL << SCB_ICSR_PENDSVCLR_Pos) /*!< SCB ICSR: PENDSVCLR Mask */ + +#define SCB_ICSR_PENDSTSET_Pos 26 /*!< SCB ICSR: PENDSTSET Position */ +#define SCB_ICSR_PENDSTSET_Msk (1UL << SCB_ICSR_PENDSTSET_Pos) /*!< SCB ICSR: PENDSTSET Mask */ + +#define SCB_ICSR_PENDSTCLR_Pos 25 /*!< SCB ICSR: PENDSTCLR Position */ +#define SCB_ICSR_PENDSTCLR_Msk (1UL << SCB_ICSR_PENDSTCLR_Pos) /*!< SCB ICSR: PENDSTCLR Mask */ + +#define SCB_ICSR_ISRPREEMPT_Pos 23 /*!< SCB ICSR: ISRPREEMPT Position */ +#define SCB_ICSR_ISRPREEMPT_Msk (1UL << SCB_ICSR_ISRPREEMPT_Pos) /*!< SCB ICSR: ISRPREEMPT Mask */ + +#define SCB_ICSR_ISRPENDING_Pos 22 /*!< SCB ICSR: ISRPENDING Position */ +#define SCB_ICSR_ISRPENDING_Msk (1UL << SCB_ICSR_ISRPENDING_Pos) /*!< SCB ICSR: ISRPENDING Mask */ + +#define SCB_ICSR_VECTPENDING_Pos 12 /*!< SCB ICSR: VECTPENDING Position */ +#define SCB_ICSR_VECTPENDING_Msk (0x1FFUL << SCB_ICSR_VECTPENDING_Pos) /*!< SCB ICSR: VECTPENDING Mask */ + +#define SCB_ICSR_RETTOBASE_Pos 11 /*!< SCB ICSR: RETTOBASE Position */ +#define SCB_ICSR_RETTOBASE_Msk (1UL << SCB_ICSR_RETTOBASE_Pos) /*!< SCB ICSR: RETTOBASE Mask */ + +#define SCB_ICSR_VECTACTIVE_Pos 0 /*!< SCB ICSR: VECTACTIVE Position */ +#define SCB_ICSR_VECTACTIVE_Msk (0x1FFUL << SCB_ICSR_VECTACTIVE_Pos) /*!< SCB ICSR: VECTACTIVE Mask */ + +/* SCB Vector Table Offset Register Definitions */ +#if (__CM3_REV < 0x0201) /* core r2p1 */ +#define SCB_VTOR_TBLBASE_Pos 29 /*!< SCB VTOR: TBLBASE Position */ +#define SCB_VTOR_TBLBASE_Msk (1UL << SCB_VTOR_TBLBASE_Pos) /*!< SCB VTOR: TBLBASE Mask */ + +#define SCB_VTOR_TBLOFF_Pos 7 /*!< SCB VTOR: TBLOFF Position */ +#define SCB_VTOR_TBLOFF_Msk (0x3FFFFFUL << SCB_VTOR_TBLOFF_Pos) /*!< SCB VTOR: TBLOFF Mask */ +#else +#define SCB_VTOR_TBLOFF_Pos 7 /*!< SCB VTOR: TBLOFF Position */ +#define SCB_VTOR_TBLOFF_Msk (0x1FFFFFFUL << SCB_VTOR_TBLOFF_Pos) /*!< SCB VTOR: TBLOFF Mask */ +#endif + +/* SCB Application Interrupt and Reset Control Register Definitions */ +#define SCB_AIRCR_VECTKEY_Pos 16 /*!< SCB AIRCR: VECTKEY Position */ +#define SCB_AIRCR_VECTKEY_Msk (0xFFFFUL << SCB_AIRCR_VECTKEY_Pos) /*!< SCB AIRCR: VECTKEY Mask */ + +#define SCB_AIRCR_VECTKEYSTAT_Pos 16 /*!< SCB AIRCR: VECTKEYSTAT Position */ +#define SCB_AIRCR_VECTKEYSTAT_Msk (0xFFFFUL << SCB_AIRCR_VECTKEYSTAT_Pos) /*!< SCB AIRCR: VECTKEYSTAT Mask */ + +#define SCB_AIRCR_ENDIANESS_Pos 15 /*!< SCB AIRCR: ENDIANESS Position */ +#define SCB_AIRCR_ENDIANESS_Msk (1UL << SCB_AIRCR_ENDIANESS_Pos) /*!< SCB AIRCR: ENDIANESS Mask */ + +#define SCB_AIRCR_PRIGROUP_Pos 8 /*!< SCB AIRCR: PRIGROUP Position */ +#define SCB_AIRCR_PRIGROUP_Msk (7UL << SCB_AIRCR_PRIGROUP_Pos) /*!< SCB AIRCR: PRIGROUP Mask */ + +#define SCB_AIRCR_SYSRESETREQ_Pos 2 /*!< SCB AIRCR: SYSRESETREQ Position */ +#define SCB_AIRCR_SYSRESETREQ_Msk (1UL << SCB_AIRCR_SYSRESETREQ_Pos) /*!< SCB AIRCR: SYSRESETREQ Mask */ + +#define SCB_AIRCR_VECTCLRACTIVE_Pos 1 /*!< SCB AIRCR: VECTCLRACTIVE Position */ +#define SCB_AIRCR_VECTCLRACTIVE_Msk (1UL << SCB_AIRCR_VECTCLRACTIVE_Pos) /*!< SCB AIRCR: VECTCLRACTIVE Mask */ + +#define SCB_AIRCR_VECTRESET_Pos 0 /*!< SCB AIRCR: VECTRESET Position */ +#define SCB_AIRCR_VECTRESET_Msk (1UL << SCB_AIRCR_VECTRESET_Pos) /*!< SCB AIRCR: VECTRESET Mask */ + +/* SCB System Control Register Definitions */ +#define SCB_SCR_SEVONPEND_Pos 4 /*!< SCB SCR: SEVONPEND Position */ +#define SCB_SCR_SEVONPEND_Msk (1UL << SCB_SCR_SEVONPEND_Pos) /*!< SCB SCR: SEVONPEND Mask */ + +#define SCB_SCR_SLEEPDEEP_Pos 2 /*!< SCB SCR: SLEEPDEEP Position */ +#define SCB_SCR_SLEEPDEEP_Msk (1UL << SCB_SCR_SLEEPDEEP_Pos) /*!< SCB SCR: SLEEPDEEP Mask */ + +#define SCB_SCR_SLEEPONEXIT_Pos 1 /*!< SCB SCR: SLEEPONEXIT Position */ +#define SCB_SCR_SLEEPONEXIT_Msk (1UL << SCB_SCR_SLEEPONEXIT_Pos) /*!< SCB SCR: SLEEPONEXIT Mask */ + +/* SCB Configuration Control Register Definitions */ +#define SCB_CCR_STKALIGN_Pos 9 /*!< SCB CCR: STKALIGN Position */ +#define SCB_CCR_STKALIGN_Msk (1UL << SCB_CCR_STKALIGN_Pos) /*!< SCB CCR: STKALIGN Mask */ + +#define SCB_CCR_BFHFNMIGN_Pos 8 /*!< SCB CCR: BFHFNMIGN Position */ +#define SCB_CCR_BFHFNMIGN_Msk (1UL << SCB_CCR_BFHFNMIGN_Pos) /*!< SCB CCR: BFHFNMIGN Mask */ + +#define SCB_CCR_DIV_0_TRP_Pos 4 /*!< SCB CCR: DIV_0_TRP Position */ +#define SCB_CCR_DIV_0_TRP_Msk (1UL << SCB_CCR_DIV_0_TRP_Pos) /*!< SCB CCR: DIV_0_TRP Mask */ + +#define SCB_CCR_UNALIGN_TRP_Pos 3 /*!< SCB CCR: UNALIGN_TRP Position */ +#define SCB_CCR_UNALIGN_TRP_Msk (1UL << SCB_CCR_UNALIGN_TRP_Pos) /*!< SCB CCR: UNALIGN_TRP Mask */ + +#define SCB_CCR_USERSETMPEND_Pos 1 /*!< SCB CCR: USERSETMPEND Position */ +#define SCB_CCR_USERSETMPEND_Msk (1UL << SCB_CCR_USERSETMPEND_Pos) /*!< SCB CCR: USERSETMPEND Mask */ + +#define SCB_CCR_NONBASETHRDENA_Pos 0 /*!< SCB CCR: NONBASETHRDENA Position */ +#define SCB_CCR_NONBASETHRDENA_Msk (1UL << SCB_CCR_NONBASETHRDENA_Pos) /*!< SCB CCR: NONBASETHRDENA Mask */ + +/* SCB System Handler Control and State Register Definitions */ +#define SCB_SHCSR_USGFAULTENA_Pos 18 /*!< SCB SHCSR: USGFAULTENA Position */ +#define SCB_SHCSR_USGFAULTENA_Msk (1UL << SCB_SHCSR_USGFAULTENA_Pos) /*!< SCB SHCSR: USGFAULTENA Mask */ + +#define SCB_SHCSR_BUSFAULTENA_Pos 17 /*!< SCB SHCSR: BUSFAULTENA Position */ +#define SCB_SHCSR_BUSFAULTENA_Msk (1UL << SCB_SHCSR_BUSFAULTENA_Pos) /*!< SCB SHCSR: BUSFAULTENA Mask */ + +#define SCB_SHCSR_MEMFAULTENA_Pos 16 /*!< SCB SHCSR: MEMFAULTENA Position */ +#define SCB_SHCSR_MEMFAULTENA_Msk (1UL << SCB_SHCSR_MEMFAULTENA_Pos) /*!< SCB SHCSR: MEMFAULTENA Mask */ + +#define SCB_SHCSR_SVCALLPENDED_Pos 15 /*!< SCB SHCSR: SVCALLPENDED Position */ +#define SCB_SHCSR_SVCALLPENDED_Msk (1UL << SCB_SHCSR_SVCALLPENDED_Pos) /*!< SCB SHCSR: SVCALLPENDED Mask */ + +#define SCB_SHCSR_BUSFAULTPENDED_Pos 14 /*!< SCB SHCSR: BUSFAULTPENDED Position */ +#define SCB_SHCSR_BUSFAULTPENDED_Msk (1UL << SCB_SHCSR_BUSFAULTPENDED_Pos) /*!< SCB SHCSR: BUSFAULTPENDED Mask */ + +#define SCB_SHCSR_MEMFAULTPENDED_Pos 13 /*!< SCB SHCSR: MEMFAULTPENDED Position */ +#define SCB_SHCSR_MEMFAULTPENDED_Msk (1UL << SCB_SHCSR_MEMFAULTPENDED_Pos) /*!< SCB SHCSR: MEMFAULTPENDED Mask */ + +#define SCB_SHCSR_USGFAULTPENDED_Pos 12 /*!< SCB SHCSR: USGFAULTPENDED Position */ +#define SCB_SHCSR_USGFAULTPENDED_Msk (1UL << SCB_SHCSR_USGFAULTPENDED_Pos) /*!< SCB SHCSR: USGFAULTPENDED Mask */ + +#define SCB_SHCSR_SYSTICKACT_Pos 11 /*!< SCB SHCSR: SYSTICKACT Position */ +#define SCB_SHCSR_SYSTICKACT_Msk (1UL << SCB_SHCSR_SYSTICKACT_Pos) /*!< SCB SHCSR: SYSTICKACT Mask */ + +#define SCB_SHCSR_PENDSVACT_Pos 10 /*!< SCB SHCSR: PENDSVACT Position */ +#define SCB_SHCSR_PENDSVACT_Msk (1UL << SCB_SHCSR_PENDSVACT_Pos) /*!< SCB SHCSR: PENDSVACT Mask */ + +#define SCB_SHCSR_MONITORACT_Pos 8 /*!< SCB SHCSR: MONITORACT Position */ +#define SCB_SHCSR_MONITORACT_Msk (1UL << SCB_SHCSR_MONITORACT_Pos) /*!< SCB SHCSR: MONITORACT Mask */ + +#define SCB_SHCSR_SVCALLACT_Pos 7 /*!< SCB SHCSR: SVCALLACT Position */ +#define SCB_SHCSR_SVCALLACT_Msk (1UL << SCB_SHCSR_SVCALLACT_Pos) /*!< SCB SHCSR: SVCALLACT Mask */ + +#define SCB_SHCSR_USGFAULTACT_Pos 3 /*!< SCB SHCSR: USGFAULTACT Position */ +#define SCB_SHCSR_USGFAULTACT_Msk (1UL << SCB_SHCSR_USGFAULTACT_Pos) /*!< SCB SHCSR: USGFAULTACT Mask */ + +#define SCB_SHCSR_BUSFAULTACT_Pos 1 /*!< SCB SHCSR: BUSFAULTACT Position */ +#define SCB_SHCSR_BUSFAULTACT_Msk (1UL << SCB_SHCSR_BUSFAULTACT_Pos) /*!< SCB SHCSR: BUSFAULTACT Mask */ + +#define SCB_SHCSR_MEMFAULTACT_Pos 0 /*!< SCB SHCSR: MEMFAULTACT Position */ +#define SCB_SHCSR_MEMFAULTACT_Msk (1UL << SCB_SHCSR_MEMFAULTACT_Pos) /*!< SCB SHCSR: MEMFAULTACT Mask */ + +/* SCB Configurable Fault Status Registers Definitions */ +#define SCB_CFSR_USGFAULTSR_Pos 16 /*!< SCB CFSR: Usage Fault Status Register Position */ +#define SCB_CFSR_USGFAULTSR_Msk (0xFFFFUL << SCB_CFSR_USGFAULTSR_Pos) /*!< SCB CFSR: Usage Fault Status Register Mask */ + +#define SCB_CFSR_BUSFAULTSR_Pos 8 /*!< SCB CFSR: Bus Fault Status Register Position */ +#define SCB_CFSR_BUSFAULTSR_Msk (0xFFUL << SCB_CFSR_BUSFAULTSR_Pos) /*!< SCB CFSR: Bus Fault Status Register Mask */ + +#define SCB_CFSR_MEMFAULTSR_Pos 0 /*!< SCB CFSR: Memory Manage Fault Status Register Position */ +#define SCB_CFSR_MEMFAULTSR_Msk (0xFFUL << SCB_CFSR_MEMFAULTSR_Pos) /*!< SCB CFSR: Memory Manage Fault Status Register Mask */ + +/* SCB Hard Fault Status Registers Definitions */ +#define SCB_HFSR_DEBUGEVT_Pos 31 /*!< SCB HFSR: DEBUGEVT Position */ +#define SCB_HFSR_DEBUGEVT_Msk (1UL << SCB_HFSR_DEBUGEVT_Pos) /*!< SCB HFSR: DEBUGEVT Mask */ + +#define SCB_HFSR_FORCED_Pos 30 /*!< SCB HFSR: FORCED Position */ +#define SCB_HFSR_FORCED_Msk (1UL << SCB_HFSR_FORCED_Pos) /*!< SCB HFSR: FORCED Mask */ + +#define SCB_HFSR_VECTTBL_Pos 1 /*!< SCB HFSR: VECTTBL Position */ +#define SCB_HFSR_VECTTBL_Msk (1UL << SCB_HFSR_VECTTBL_Pos) /*!< SCB HFSR: VECTTBL Mask */ + +/* SCB Debug Fault Status Register Definitions */ +#define SCB_DFSR_EXTERNAL_Pos 4 /*!< SCB DFSR: EXTERNAL Position */ +#define SCB_DFSR_EXTERNAL_Msk (1UL << SCB_DFSR_EXTERNAL_Pos) /*!< SCB DFSR: EXTERNAL Mask */ + +#define SCB_DFSR_VCATCH_Pos 3 /*!< SCB DFSR: VCATCH Position */ +#define SCB_DFSR_VCATCH_Msk (1UL << SCB_DFSR_VCATCH_Pos) /*!< SCB DFSR: VCATCH Mask */ + +#define SCB_DFSR_DWTTRAP_Pos 2 /*!< SCB DFSR: DWTTRAP Position */ +#define SCB_DFSR_DWTTRAP_Msk (1UL << SCB_DFSR_DWTTRAP_Pos) /*!< SCB DFSR: DWTTRAP Mask */ + +#define SCB_DFSR_BKPT_Pos 1 /*!< SCB DFSR: BKPT Position */ +#define SCB_DFSR_BKPT_Msk (1UL << SCB_DFSR_BKPT_Pos) /*!< SCB DFSR: BKPT Mask */ + +#define SCB_DFSR_HALTED_Pos 0 /*!< SCB DFSR: HALTED Position */ +#define SCB_DFSR_HALTED_Msk (1UL << SCB_DFSR_HALTED_Pos) /*!< SCB DFSR: HALTED Mask */ + +/*@} end of group CMSIS_SCB */ + + +/** \ingroup CMSIS_core_register + \defgroup CMSIS_SCnSCB System Controls not in SCB (SCnSCB) + \brief Type definitions for the System Control and ID Register not in the SCB + @{ + */ + +/** \brief Structure type to access the System Control and ID Register not in the SCB. + */ +typedef struct +{ + uint32_t RESERVED0[1]; + __I uint32_t ICTR; /*!< Offset: 0x004 (R/ ) Interrupt Controller Type Register */ +#if ((defined __CM3_REV) && (__CM3_REV >= 0x200)) + __IO uint32_t ACTLR; /*!< Offset: 0x008 (R/W) Auxiliary Control Register */ +#else + uint32_t RESERVED1[1]; +#endif +} SCnSCB_Type; + +/* Interrupt Controller Type Register Definitions */ +#define SCnSCB_ICTR_INTLINESNUM_Pos 0 /*!< ICTR: INTLINESNUM Position */ +#define SCnSCB_ICTR_INTLINESNUM_Msk (0xFUL << SCnSCB_ICTR_INTLINESNUM_Pos) /*!< ICTR: INTLINESNUM Mask */ + +/* Auxiliary Control Register Definitions */ + +#define SCnSCB_ACTLR_DISFOLD_Pos 2 /*!< ACTLR: DISFOLD Position */ +#define SCnSCB_ACTLR_DISFOLD_Msk (1UL << SCnSCB_ACTLR_DISFOLD_Pos) /*!< ACTLR: DISFOLD Mask */ + +#define SCnSCB_ACTLR_DISDEFWBUF_Pos 1 /*!< ACTLR: DISDEFWBUF Position */ +#define SCnSCB_ACTLR_DISDEFWBUF_Msk (1UL << SCnSCB_ACTLR_DISDEFWBUF_Pos) /*!< ACTLR: DISDEFWBUF Mask */ + +#define SCnSCB_ACTLR_DISMCYCINT_Pos 0 /*!< ACTLR: DISMCYCINT Position */ +#define SCnSCB_ACTLR_DISMCYCINT_Msk (1UL << SCnSCB_ACTLR_DISMCYCINT_Pos) /*!< ACTLR: DISMCYCINT Mask */ + +/*@} end of group CMSIS_SCnotSCB */ + + +/** \ingroup CMSIS_core_register + \defgroup CMSIS_SysTick System Tick Timer (SysTick) + \brief Type definitions for the System Timer Registers. + @{ + */ + +/** \brief Structure type to access the System Timer (SysTick). + */ +typedef struct +{ + __IO uint32_t CTRL; /*!< Offset: 0x000 (R/W) SysTick Control and Status Register */ + __IO uint32_t LOAD; /*!< Offset: 0x004 (R/W) SysTick Reload Value Register */ + __IO uint32_t VAL; /*!< Offset: 0x008 (R/W) SysTick Current Value Register */ + __I uint32_t CALIB; /*!< Offset: 0x00C (R/ ) SysTick Calibration Register */ +} SysTick_Type; + +/* SysTick Control / Status Register Definitions */ +#define SysTick_CTRL_COUNTFLAG_Pos 16 /*!< SysTick CTRL: COUNTFLAG Position */ +#define SysTick_CTRL_COUNTFLAG_Msk (1UL << SysTick_CTRL_COUNTFLAG_Pos) /*!< SysTick CTRL: COUNTFLAG Mask */ + +#define SysTick_CTRL_CLKSOURCE_Pos 2 /*!< SysTick CTRL: CLKSOURCE Position */ +#define SysTick_CTRL_CLKSOURCE_Msk (1UL << SysTick_CTRL_CLKSOURCE_Pos) /*!< SysTick CTRL: CLKSOURCE Mask */ + +#define SysTick_CTRL_TICKINT_Pos 1 /*!< SysTick CTRL: TICKINT Position */ +#define SysTick_CTRL_TICKINT_Msk (1UL << SysTick_CTRL_TICKINT_Pos) /*!< SysTick CTRL: TICKINT Mask */ + +#define SysTick_CTRL_ENABLE_Pos 0 /*!< SysTick CTRL: ENABLE Position */ +#define SysTick_CTRL_ENABLE_Msk (1UL << SysTick_CTRL_ENABLE_Pos) /*!< SysTick CTRL: ENABLE Mask */ + +/* SysTick Reload Register Definitions */ +#define SysTick_LOAD_RELOAD_Pos 0 /*!< SysTick LOAD: RELOAD Position */ +#define SysTick_LOAD_RELOAD_Msk (0xFFFFFFUL << SysTick_LOAD_RELOAD_Pos) /*!< SysTick LOAD: RELOAD Mask */ + +/* SysTick Current Register Definitions */ +#define SysTick_VAL_CURRENT_Pos 0 /*!< SysTick VAL: CURRENT Position */ +#define SysTick_VAL_CURRENT_Msk (0xFFFFFFUL << SysTick_VAL_CURRENT_Pos) /*!< SysTick VAL: CURRENT Mask */ + +/* SysTick Calibration Register Definitions */ +#define SysTick_CALIB_NOREF_Pos 31 /*!< SysTick CALIB: NOREF Position */ +#define SysTick_CALIB_NOREF_Msk (1UL << SysTick_CALIB_NOREF_Pos) /*!< SysTick CALIB: NOREF Mask */ + +#define SysTick_CALIB_SKEW_Pos 30 /*!< SysTick CALIB: SKEW Position */ +#define SysTick_CALIB_SKEW_Msk (1UL << SysTick_CALIB_SKEW_Pos) /*!< SysTick CALIB: SKEW Mask */ + +#define SysTick_CALIB_TENMS_Pos 0 /*!< SysTick CALIB: TENMS Position */ +#define SysTick_CALIB_TENMS_Msk (0xFFFFFFUL << SysTick_VAL_CURRENT_Pos) /*!< SysTick CALIB: TENMS Mask */ + +/*@} end of group CMSIS_SysTick */ + + +/** \ingroup CMSIS_core_register + \defgroup CMSIS_ITM Instrumentation Trace Macrocell (ITM) + \brief Type definitions for the Instrumentation Trace Macrocell (ITM) + @{ + */ + +/** \brief Structure type to access the Instrumentation Trace Macrocell Register (ITM). + */ +typedef struct +{ + __O union + { + __O uint8_t u8; /*!< Offset: 0x000 ( /W) ITM Stimulus Port 8-bit */ + __O uint16_t u16; /*!< Offset: 0x000 ( /W) ITM Stimulus Port 16-bit */ + __O uint32_t u32; /*!< Offset: 0x000 ( /W) ITM Stimulus Port 32-bit */ + } PORT [32]; /*!< Offset: 0x000 ( /W) ITM Stimulus Port Registers */ + uint32_t RESERVED0[864]; + __IO uint32_t TER; /*!< Offset: 0xE00 (R/W) ITM Trace Enable Register */ + uint32_t RESERVED1[15]; + __IO uint32_t TPR; /*!< Offset: 0xE40 (R/W) ITM Trace Privilege Register */ + uint32_t RESERVED2[15]; + __IO uint32_t TCR; /*!< Offset: 0xE80 (R/W) ITM Trace Control Register */ + uint32_t RESERVED3[29]; + __O uint32_t IWR; /*!< Offset: 0xEF8 ( /W) ITM Integration Write Register */ + __I uint32_t IRR; /*!< Offset: 0xEFC (R/ ) ITM Integration Read Register */ + __IO uint32_t IMCR; /*!< Offset: 0xF00 (R/W) ITM Integration Mode Control Register */ + uint32_t RESERVED4[43]; + __O uint32_t LAR; /*!< Offset: 0xFB0 ( /W) ITM Lock Access Register */ + __I uint32_t LSR; /*!< Offset: 0xFB4 (R/ ) ITM Lock Status Register */ + uint32_t RESERVED5[6]; + __I uint32_t PID4; /*!< Offset: 0xFD0 (R/ ) ITM Peripheral Identification Register #4 */ + __I uint32_t PID5; /*!< Offset: 0xFD4 (R/ ) ITM Peripheral Identification Register #5 */ + __I uint32_t PID6; /*!< Offset: 0xFD8 (R/ ) ITM Peripheral Identification Register #6 */ + __I uint32_t PID7; /*!< Offset: 0xFDC (R/ ) ITM Peripheral Identification Register #7 */ + __I uint32_t PID0; /*!< Offset: 0xFE0 (R/ ) ITM Peripheral Identification Register #0 */ + __I uint32_t PID1; /*!< Offset: 0xFE4 (R/ ) ITM Peripheral Identification Register #1 */ + __I uint32_t PID2; /*!< Offset: 0xFE8 (R/ ) ITM Peripheral Identification Register #2 */ + __I uint32_t PID3; /*!< Offset: 0xFEC (R/ ) ITM Peripheral Identification Register #3 */ + __I uint32_t CID0; /*!< Offset: 0xFF0 (R/ ) ITM Component Identification Register #0 */ + __I uint32_t CID1; /*!< Offset: 0xFF4 (R/ ) ITM Component Identification Register #1 */ + __I uint32_t CID2; /*!< Offset: 0xFF8 (R/ ) ITM Component Identification Register #2 */ + __I uint32_t CID3; /*!< Offset: 0xFFC (R/ ) ITM Component Identification Register #3 */ +} ITM_Type; + +/* ITM Trace Privilege Register Definitions */ +#define ITM_TPR_PRIVMASK_Pos 0 /*!< ITM TPR: PRIVMASK Position */ +#define ITM_TPR_PRIVMASK_Msk (0xFUL << ITM_TPR_PRIVMASK_Pos) /*!< ITM TPR: PRIVMASK Mask */ + +/* ITM Trace Control Register Definitions */ +#define ITM_TCR_BUSY_Pos 23 /*!< ITM TCR: BUSY Position */ +#define ITM_TCR_BUSY_Msk (1UL << ITM_TCR_BUSY_Pos) /*!< ITM TCR: BUSY Mask */ + +#define ITM_TCR_TraceBusID_Pos 16 /*!< ITM TCR: ATBID Position */ +#define ITM_TCR_TraceBusID_Msk (0x7FUL << ITM_TCR_TraceBusID_Pos) /*!< ITM TCR: ATBID Mask */ + +#define ITM_TCR_GTSFREQ_Pos 10 /*!< ITM TCR: Global timestamp frequency Position */ +#define ITM_TCR_GTSFREQ_Msk (3UL << ITM_TCR_GTSFREQ_Pos) /*!< ITM TCR: Global timestamp frequency Mask */ + +#define ITM_TCR_TSPrescale_Pos 8 /*!< ITM TCR: TSPrescale Position */ +#define ITM_TCR_TSPrescale_Msk (3UL << ITM_TCR_TSPrescale_Pos) /*!< ITM TCR: TSPrescale Mask */ + +#define ITM_TCR_SWOENA_Pos 4 /*!< ITM TCR: SWOENA Position */ +#define ITM_TCR_SWOENA_Msk (1UL << ITM_TCR_SWOENA_Pos) /*!< ITM TCR: SWOENA Mask */ + +#define ITM_TCR_DWTENA_Pos 3 /*!< ITM TCR: DWTENA Position */ +#define ITM_TCR_DWTENA_Msk (1UL << ITM_TCR_DWTENA_Pos) /*!< ITM TCR: DWTENA Mask */ + +#define ITM_TCR_SYNCENA_Pos 2 /*!< ITM TCR: SYNCENA Position */ +#define ITM_TCR_SYNCENA_Msk (1UL << ITM_TCR_SYNCENA_Pos) /*!< ITM TCR: SYNCENA Mask */ + +#define ITM_TCR_TSENA_Pos 1 /*!< ITM TCR: TSENA Position */ +#define ITM_TCR_TSENA_Msk (1UL << ITM_TCR_TSENA_Pos) /*!< ITM TCR: TSENA Mask */ + +#define ITM_TCR_ITMENA_Pos 0 /*!< ITM TCR: ITM Enable bit Position */ +#define ITM_TCR_ITMENA_Msk (1UL << ITM_TCR_ITMENA_Pos) /*!< ITM TCR: ITM Enable bit Mask */ + +/* ITM Integration Write Register Definitions */ +#define ITM_IWR_ATVALIDM_Pos 0 /*!< ITM IWR: ATVALIDM Position */ +#define ITM_IWR_ATVALIDM_Msk (1UL << ITM_IWR_ATVALIDM_Pos) /*!< ITM IWR: ATVALIDM Mask */ + +/* ITM Integration Read Register Definitions */ +#define ITM_IRR_ATREADYM_Pos 0 /*!< ITM IRR: ATREADYM Position */ +#define ITM_IRR_ATREADYM_Msk (1UL << ITM_IRR_ATREADYM_Pos) /*!< ITM IRR: ATREADYM Mask */ + +/* ITM Integration Mode Control Register Definitions */ +#define ITM_IMCR_INTEGRATION_Pos 0 /*!< ITM IMCR: INTEGRATION Position */ +#define ITM_IMCR_INTEGRATION_Msk (1UL << ITM_IMCR_INTEGRATION_Pos) /*!< ITM IMCR: INTEGRATION Mask */ + +/* ITM Lock Status Register Definitions */ +#define ITM_LSR_ByteAcc_Pos 2 /*!< ITM LSR: ByteAcc Position */ +#define ITM_LSR_ByteAcc_Msk (1UL << ITM_LSR_ByteAcc_Pos) /*!< ITM LSR: ByteAcc Mask */ + +#define ITM_LSR_Access_Pos 1 /*!< ITM LSR: Access Position */ +#define ITM_LSR_Access_Msk (1UL << ITM_LSR_Access_Pos) /*!< ITM LSR: Access Mask */ + +#define ITM_LSR_Present_Pos 0 /*!< ITM LSR: Present Position */ +#define ITM_LSR_Present_Msk (1UL << ITM_LSR_Present_Pos) /*!< ITM LSR: Present Mask */ + +/*@}*/ /* end of group CMSIS_ITM */ + + +/** \ingroup CMSIS_core_register + \defgroup CMSIS_DWT Data Watchpoint and Trace (DWT) + \brief Type definitions for the Data Watchpoint and Trace (DWT) + @{ + */ + +/** \brief Structure type to access the Data Watchpoint and Trace Register (DWT). + */ +typedef struct +{ + __IO uint32_t CTRL; /*!< Offset: 0x000 (R/W) Control Register */ + __IO uint32_t CYCCNT; /*!< Offset: 0x004 (R/W) Cycle Count Register */ + __IO uint32_t CPICNT; /*!< Offset: 0x008 (R/W) CPI Count Register */ + __IO uint32_t EXCCNT; /*!< Offset: 0x00C (R/W) Exception Overhead Count Register */ + __IO uint32_t SLEEPCNT; /*!< Offset: 0x010 (R/W) Sleep Count Register */ + __IO uint32_t LSUCNT; /*!< Offset: 0x014 (R/W) LSU Count Register */ + __IO uint32_t FOLDCNT; /*!< Offset: 0x018 (R/W) Folded-instruction Count Register */ + __I uint32_t PCSR; /*!< Offset: 0x01C (R/ ) Program Counter Sample Register */ + __IO uint32_t COMP0; /*!< Offset: 0x020 (R/W) Comparator Register 0 */ + __IO uint32_t MASK0; /*!< Offset: 0x024 (R/W) Mask Register 0 */ + __IO uint32_t FUNCTION0; /*!< Offset: 0x028 (R/W) Function Register 0 */ + uint32_t RESERVED0[1]; + __IO uint32_t COMP1; /*!< Offset: 0x030 (R/W) Comparator Register 1 */ + __IO uint32_t MASK1; /*!< Offset: 0x034 (R/W) Mask Register 1 */ + __IO uint32_t FUNCTION1; /*!< Offset: 0x038 (R/W) Function Register 1 */ + uint32_t RESERVED1[1]; + __IO uint32_t COMP2; /*!< Offset: 0x040 (R/W) Comparator Register 2 */ + __IO uint32_t MASK2; /*!< Offset: 0x044 (R/W) Mask Register 2 */ + __IO uint32_t FUNCTION2; /*!< Offset: 0x048 (R/W) Function Register 2 */ + uint32_t RESERVED2[1]; + __IO uint32_t COMP3; /*!< Offset: 0x050 (R/W) Comparator Register 3 */ + __IO uint32_t MASK3; /*!< Offset: 0x054 (R/W) Mask Register 3 */ + __IO uint32_t FUNCTION3; /*!< Offset: 0x058 (R/W) Function Register 3 */ +} DWT_Type; + +/* DWT Control Register Definitions */ +#define DWT_CTRL_NUMCOMP_Pos 28 /*!< DWT CTRL: NUMCOMP Position */ +#define DWT_CTRL_NUMCOMP_Msk (0xFUL << DWT_CTRL_NUMCOMP_Pos) /*!< DWT CTRL: NUMCOMP Mask */ + +#define DWT_CTRL_NOTRCPKT_Pos 27 /*!< DWT CTRL: NOTRCPKT Position */ +#define DWT_CTRL_NOTRCPKT_Msk (0x1UL << DWT_CTRL_NOTRCPKT_Pos) /*!< DWT CTRL: NOTRCPKT Mask */ + +#define DWT_CTRL_NOEXTTRIG_Pos 26 /*!< DWT CTRL: NOEXTTRIG Position */ +#define DWT_CTRL_NOEXTTRIG_Msk (0x1UL << DWT_CTRL_NOEXTTRIG_Pos) /*!< DWT CTRL: NOEXTTRIG Mask */ + +#define DWT_CTRL_NOCYCCNT_Pos 25 /*!< DWT CTRL: NOCYCCNT Position */ +#define DWT_CTRL_NOCYCCNT_Msk (0x1UL << DWT_CTRL_NOCYCCNT_Pos) /*!< DWT CTRL: NOCYCCNT Mask */ + +#define DWT_CTRL_NOPRFCNT_Pos 24 /*!< DWT CTRL: NOPRFCNT Position */ +#define DWT_CTRL_NOPRFCNT_Msk (0x1UL << DWT_CTRL_NOPRFCNT_Pos) /*!< DWT CTRL: NOPRFCNT Mask */ + +#define DWT_CTRL_CYCEVTENA_Pos 22 /*!< DWT CTRL: CYCEVTENA Position */ +#define DWT_CTRL_CYCEVTENA_Msk (0x1UL << DWT_CTRL_CYCEVTENA_Pos) /*!< DWT CTRL: CYCEVTENA Mask */ + +#define DWT_CTRL_FOLDEVTENA_Pos 21 /*!< DWT CTRL: FOLDEVTENA Position */ +#define DWT_CTRL_FOLDEVTENA_Msk (0x1UL << DWT_CTRL_FOLDEVTENA_Pos) /*!< DWT CTRL: FOLDEVTENA Mask */ + +#define DWT_CTRL_LSUEVTENA_Pos 20 /*!< DWT CTRL: LSUEVTENA Position */ +#define DWT_CTRL_LSUEVTENA_Msk (0x1UL << DWT_CTRL_LSUEVTENA_Pos) /*!< DWT CTRL: LSUEVTENA Mask */ + +#define DWT_CTRL_SLEEPEVTENA_Pos 19 /*!< DWT CTRL: SLEEPEVTENA Position */ +#define DWT_CTRL_SLEEPEVTENA_Msk (0x1UL << DWT_CTRL_SLEEPEVTENA_Pos) /*!< DWT CTRL: SLEEPEVTENA Mask */ + +#define DWT_CTRL_EXCEVTENA_Pos 18 /*!< DWT CTRL: EXCEVTENA Position */ +#define DWT_CTRL_EXCEVTENA_Msk (0x1UL << DWT_CTRL_EXCEVTENA_Pos) /*!< DWT CTRL: EXCEVTENA Mask */ + +#define DWT_CTRL_CPIEVTENA_Pos 17 /*!< DWT CTRL: CPIEVTENA Position */ +#define DWT_CTRL_CPIEVTENA_Msk (0x1UL << DWT_CTRL_CPIEVTENA_Pos) /*!< DWT CTRL: CPIEVTENA Mask */ + +#define DWT_CTRL_EXCTRCENA_Pos 16 /*!< DWT CTRL: EXCTRCENA Position */ +#define DWT_CTRL_EXCTRCENA_Msk (0x1UL << DWT_CTRL_EXCTRCENA_Pos) /*!< DWT CTRL: EXCTRCENA Mask */ + +#define DWT_CTRL_PCSAMPLENA_Pos 12 /*!< DWT CTRL: PCSAMPLENA Position */ +#define DWT_CTRL_PCSAMPLENA_Msk (0x1UL << DWT_CTRL_PCSAMPLENA_Pos) /*!< DWT CTRL: PCSAMPLENA Mask */ + +#define DWT_CTRL_SYNCTAP_Pos 10 /*!< DWT CTRL: SYNCTAP Position */ +#define DWT_CTRL_SYNCTAP_Msk (0x3UL << DWT_CTRL_SYNCTAP_Pos) /*!< DWT CTRL: SYNCTAP Mask */ + +#define DWT_CTRL_CYCTAP_Pos 9 /*!< DWT CTRL: CYCTAP Position */ +#define DWT_CTRL_CYCTAP_Msk (0x1UL << DWT_CTRL_CYCTAP_Pos) /*!< DWT CTRL: CYCTAP Mask */ + +#define DWT_CTRL_POSTINIT_Pos 5 /*!< DWT CTRL: POSTINIT Position */ +#define DWT_CTRL_POSTINIT_Msk (0xFUL << DWT_CTRL_POSTINIT_Pos) /*!< DWT CTRL: POSTINIT Mask */ + +#define DWT_CTRL_POSTPRESET_Pos 1 /*!< DWT CTRL: POSTPRESET Position */ +#define DWT_CTRL_POSTPRESET_Msk (0xFUL << DWT_CTRL_POSTPRESET_Pos) /*!< DWT CTRL: POSTPRESET Mask */ + +#define DWT_CTRL_CYCCNTENA_Pos 0 /*!< DWT CTRL: CYCCNTENA Position */ +#define DWT_CTRL_CYCCNTENA_Msk (0x1UL << DWT_CTRL_CYCCNTENA_Pos) /*!< DWT CTRL: CYCCNTENA Mask */ + +/* DWT CPI Count Register Definitions */ +#define DWT_CPICNT_CPICNT_Pos 0 /*!< DWT CPICNT: CPICNT Position */ +#define DWT_CPICNT_CPICNT_Msk (0xFFUL << DWT_CPICNT_CPICNT_Pos) /*!< DWT CPICNT: CPICNT Mask */ + +/* DWT Exception Overhead Count Register Definitions */ +#define DWT_EXCCNT_EXCCNT_Pos 0 /*!< DWT EXCCNT: EXCCNT Position */ +#define DWT_EXCCNT_EXCCNT_Msk (0xFFUL << DWT_EXCCNT_EXCCNT_Pos) /*!< DWT EXCCNT: EXCCNT Mask */ + +/* DWT Sleep Count Register Definitions */ +#define DWT_SLEEPCNT_SLEEPCNT_Pos 0 /*!< DWT SLEEPCNT: SLEEPCNT Position */ +#define DWT_SLEEPCNT_SLEEPCNT_Msk (0xFFUL << DWT_SLEEPCNT_SLEEPCNT_Pos) /*!< DWT SLEEPCNT: SLEEPCNT Mask */ + +/* DWT LSU Count Register Definitions */ +#define DWT_LSUCNT_LSUCNT_Pos 0 /*!< DWT LSUCNT: LSUCNT Position */ +#define DWT_LSUCNT_LSUCNT_Msk (0xFFUL << DWT_LSUCNT_LSUCNT_Pos) /*!< DWT LSUCNT: LSUCNT Mask */ + +/* DWT Folded-instruction Count Register Definitions */ +#define DWT_FOLDCNT_FOLDCNT_Pos 0 /*!< DWT FOLDCNT: FOLDCNT Position */ +#define DWT_FOLDCNT_FOLDCNT_Msk (0xFFUL << DWT_FOLDCNT_FOLDCNT_Pos) /*!< DWT FOLDCNT: FOLDCNT Mask */ + +/* DWT Comparator Mask Register Definitions */ +#define DWT_MASK_MASK_Pos 0 /*!< DWT MASK: MASK Position */ +#define DWT_MASK_MASK_Msk (0x1FUL << DWT_MASK_MASK_Pos) /*!< DWT MASK: MASK Mask */ + +/* DWT Comparator Function Register Definitions */ +#define DWT_FUNCTION_MATCHED_Pos 24 /*!< DWT FUNCTION: MATCHED Position */ +#define DWT_FUNCTION_MATCHED_Msk (0x1UL << DWT_FUNCTION_MATCHED_Pos) /*!< DWT FUNCTION: MATCHED Mask */ + +#define DWT_FUNCTION_DATAVADDR1_Pos 16 /*!< DWT FUNCTION: DATAVADDR1 Position */ +#define DWT_FUNCTION_DATAVADDR1_Msk (0xFUL << DWT_FUNCTION_DATAVADDR1_Pos) /*!< DWT FUNCTION: DATAVADDR1 Mask */ + +#define DWT_FUNCTION_DATAVADDR0_Pos 12 /*!< DWT FUNCTION: DATAVADDR0 Position */ +#define DWT_FUNCTION_DATAVADDR0_Msk (0xFUL << DWT_FUNCTION_DATAVADDR0_Pos) /*!< DWT FUNCTION: DATAVADDR0 Mask */ + +#define DWT_FUNCTION_DATAVSIZE_Pos 10 /*!< DWT FUNCTION: DATAVSIZE Position */ +#define DWT_FUNCTION_DATAVSIZE_Msk (0x3UL << DWT_FUNCTION_DATAVSIZE_Pos) /*!< DWT FUNCTION: DATAVSIZE Mask */ + +#define DWT_FUNCTION_LNK1ENA_Pos 9 /*!< DWT FUNCTION: LNK1ENA Position */ +#define DWT_FUNCTION_LNK1ENA_Msk (0x1UL << DWT_FUNCTION_LNK1ENA_Pos) /*!< DWT FUNCTION: LNK1ENA Mask */ + +#define DWT_FUNCTION_DATAVMATCH_Pos 8 /*!< DWT FUNCTION: DATAVMATCH Position */ +#define DWT_FUNCTION_DATAVMATCH_Msk (0x1UL << DWT_FUNCTION_DATAVMATCH_Pos) /*!< DWT FUNCTION: DATAVMATCH Mask */ + +#define DWT_FUNCTION_CYCMATCH_Pos 7 /*!< DWT FUNCTION: CYCMATCH Position */ +#define DWT_FUNCTION_CYCMATCH_Msk (0x1UL << DWT_FUNCTION_CYCMATCH_Pos) /*!< DWT FUNCTION: CYCMATCH Mask */ + +#define DWT_FUNCTION_EMITRANGE_Pos 5 /*!< DWT FUNCTION: EMITRANGE Position */ +#define DWT_FUNCTION_EMITRANGE_Msk (0x1UL << DWT_FUNCTION_EMITRANGE_Pos) /*!< DWT FUNCTION: EMITRANGE Mask */ + +#define DWT_FUNCTION_FUNCTION_Pos 0 /*!< DWT FUNCTION: FUNCTION Position */ +#define DWT_FUNCTION_FUNCTION_Msk (0xFUL << DWT_FUNCTION_FUNCTION_Pos) /*!< DWT FUNCTION: FUNCTION Mask */ + +/*@}*/ /* end of group CMSIS_DWT */ + + +/** \ingroup CMSIS_core_register + \defgroup CMSIS_TPI Trace Port Interface (TPI) + \brief Type definitions for the Trace Port Interface (TPI) + @{ + */ + +/** \brief Structure type to access the Trace Port Interface Register (TPI). + */ +typedef struct +{ + __IO uint32_t SSPSR; /*!< Offset: 0x000 (R/ ) Supported Parallel Port Size Register */ + __IO uint32_t CSPSR; /*!< Offset: 0x004 (R/W) Current Parallel Port Size Register */ + uint32_t RESERVED0[2]; + __IO uint32_t ACPR; /*!< Offset: 0x010 (R/W) Asynchronous Clock Prescaler Register */ + uint32_t RESERVED1[55]; + __IO uint32_t SPPR; /*!< Offset: 0x0F0 (R/W) Selected Pin Protocol Register */ + uint32_t RESERVED2[131]; + __I uint32_t FFSR; /*!< Offset: 0x300 (R/ ) Formatter and Flush Status Register */ + __IO uint32_t FFCR; /*!< Offset: 0x304 (R/W) Formatter and Flush Control Register */ + __I uint32_t FSCR; /*!< Offset: 0x308 (R/ ) Formatter Synchronization Counter Register */ + uint32_t RESERVED3[759]; + __I uint32_t TRIGGER; /*!< Offset: 0xEE8 (R/ ) TRIGGER */ + __I uint32_t FIFO0; /*!< Offset: 0xEEC (R/ ) Integration ETM Data */ + __I uint32_t ITATBCTR2; /*!< Offset: 0xEF0 (R/ ) ITATBCTR2 */ + uint32_t RESERVED4[1]; + __I uint32_t ITATBCTR0; /*!< Offset: 0xEF8 (R/ ) ITATBCTR0 */ + __I uint32_t FIFO1; /*!< Offset: 0xEFC (R/ ) Integration ITM Data */ + __IO uint32_t ITCTRL; /*!< Offset: 0xF00 (R/W) Integration Mode Control */ + uint32_t RESERVED5[39]; + __IO uint32_t CLAIMSET; /*!< Offset: 0xFA0 (R/W) Claim tag set */ + __IO uint32_t CLAIMCLR; /*!< Offset: 0xFA4 (R/W) Claim tag clear */ + uint32_t RESERVED7[8]; + __I uint32_t DEVID; /*!< Offset: 0xFC8 (R/ ) TPIU_DEVID */ + __I uint32_t DEVTYPE; /*!< Offset: 0xFCC (R/ ) TPIU_DEVTYPE */ +} TPI_Type; + +/* TPI Asynchronous Clock Prescaler Register Definitions */ +#define TPI_ACPR_PRESCALER_Pos 0 /*!< TPI ACPR: PRESCALER Position */ +#define TPI_ACPR_PRESCALER_Msk (0x1FFFUL << TPI_ACPR_PRESCALER_Pos) /*!< TPI ACPR: PRESCALER Mask */ + +/* TPI Selected Pin Protocol Register Definitions */ +#define TPI_SPPR_TXMODE_Pos 0 /*!< TPI SPPR: TXMODE Position */ +#define TPI_SPPR_TXMODE_Msk (0x3UL << TPI_SPPR_TXMODE_Pos) /*!< TPI SPPR: TXMODE Mask */ + +/* TPI Formatter and Flush Status Register Definitions */ +#define TPI_FFSR_FtNonStop_Pos 3 /*!< TPI FFSR: FtNonStop Position */ +#define TPI_FFSR_FtNonStop_Msk (0x1UL << TPI_FFSR_FtNonStop_Pos) /*!< TPI FFSR: FtNonStop Mask */ + +#define TPI_FFSR_TCPresent_Pos 2 /*!< TPI FFSR: TCPresent Position */ +#define TPI_FFSR_TCPresent_Msk (0x1UL << TPI_FFSR_TCPresent_Pos) /*!< TPI FFSR: TCPresent Mask */ + +#define TPI_FFSR_FtStopped_Pos 1 /*!< TPI FFSR: FtStopped Position */ +#define TPI_FFSR_FtStopped_Msk (0x1UL << TPI_FFSR_FtStopped_Pos) /*!< TPI FFSR: FtStopped Mask */ + +#define TPI_FFSR_FlInProg_Pos 0 /*!< TPI FFSR: FlInProg Position */ +#define TPI_FFSR_FlInProg_Msk (0x1UL << TPI_FFSR_FlInProg_Pos) /*!< TPI FFSR: FlInProg Mask */ + +/* TPI Formatter and Flush Control Register Definitions */ +#define TPI_FFCR_TrigIn_Pos 8 /*!< TPI FFCR: TrigIn Position */ +#define TPI_FFCR_TrigIn_Msk (0x1UL << TPI_FFCR_TrigIn_Pos) /*!< TPI FFCR: TrigIn Mask */ + +#define TPI_FFCR_EnFCont_Pos 1 /*!< TPI FFCR: EnFCont Position */ +#define TPI_FFCR_EnFCont_Msk (0x1UL << TPI_FFCR_EnFCont_Pos) /*!< TPI FFCR: EnFCont Mask */ + +/* TPI TRIGGER Register Definitions */ +#define TPI_TRIGGER_TRIGGER_Pos 0 /*!< TPI TRIGGER: TRIGGER Position */ +#define TPI_TRIGGER_TRIGGER_Msk (0x1UL << TPI_TRIGGER_TRIGGER_Pos) /*!< TPI TRIGGER: TRIGGER Mask */ + +/* TPI Integration ETM Data Register Definitions (FIFO0) */ +#define TPI_FIFO0_ITM_ATVALID_Pos 29 /*!< TPI FIFO0: ITM_ATVALID Position */ +#define TPI_FIFO0_ITM_ATVALID_Msk (0x3UL << TPI_FIFO0_ITM_ATVALID_Pos) /*!< TPI FIFO0: ITM_ATVALID Mask */ + +#define TPI_FIFO0_ITM_bytecount_Pos 27 /*!< TPI FIFO0: ITM_bytecount Position */ +#define TPI_FIFO0_ITM_bytecount_Msk (0x3UL << TPI_FIFO0_ITM_bytecount_Pos) /*!< TPI FIFO0: ITM_bytecount Mask */ + +#define TPI_FIFO0_ETM_ATVALID_Pos 26 /*!< TPI FIFO0: ETM_ATVALID Position */ +#define TPI_FIFO0_ETM_ATVALID_Msk (0x3UL << TPI_FIFO0_ETM_ATVALID_Pos) /*!< TPI FIFO0: ETM_ATVALID Mask */ + +#define TPI_FIFO0_ETM_bytecount_Pos 24 /*!< TPI FIFO0: ETM_bytecount Position */ +#define TPI_FIFO0_ETM_bytecount_Msk (0x3UL << TPI_FIFO0_ETM_bytecount_Pos) /*!< TPI FIFO0: ETM_bytecount Mask */ + +#define TPI_FIFO0_ETM2_Pos 16 /*!< TPI FIFO0: ETM2 Position */ +#define TPI_FIFO0_ETM2_Msk (0xFFUL << TPI_FIFO0_ETM2_Pos) /*!< TPI FIFO0: ETM2 Mask */ + +#define TPI_FIFO0_ETM1_Pos 8 /*!< TPI FIFO0: ETM1 Position */ +#define TPI_FIFO0_ETM1_Msk (0xFFUL << TPI_FIFO0_ETM1_Pos) /*!< TPI FIFO0: ETM1 Mask */ + +#define TPI_FIFO0_ETM0_Pos 0 /*!< TPI FIFO0: ETM0 Position */ +#define TPI_FIFO0_ETM0_Msk (0xFFUL << TPI_FIFO0_ETM0_Pos) /*!< TPI FIFO0: ETM0 Mask */ + +/* TPI ITATBCTR2 Register Definitions */ +#define TPI_ITATBCTR2_ATREADY_Pos 0 /*!< TPI ITATBCTR2: ATREADY Position */ +#define TPI_ITATBCTR2_ATREADY_Msk (0x1UL << TPI_ITATBCTR2_ATREADY_Pos) /*!< TPI ITATBCTR2: ATREADY Mask */ + +/* TPI Integration ITM Data Register Definitions (FIFO1) */ +#define TPI_FIFO1_ITM_ATVALID_Pos 29 /*!< TPI FIFO1: ITM_ATVALID Position */ +#define TPI_FIFO1_ITM_ATVALID_Msk (0x3UL << TPI_FIFO1_ITM_ATVALID_Pos) /*!< TPI FIFO1: ITM_ATVALID Mask */ + +#define TPI_FIFO1_ITM_bytecount_Pos 27 /*!< TPI FIFO1: ITM_bytecount Position */ +#define TPI_FIFO1_ITM_bytecount_Msk (0x3UL << TPI_FIFO1_ITM_bytecount_Pos) /*!< TPI FIFO1: ITM_bytecount Mask */ + +#define TPI_FIFO1_ETM_ATVALID_Pos 26 /*!< TPI FIFO1: ETM_ATVALID Position */ +#define TPI_FIFO1_ETM_ATVALID_Msk (0x3UL << TPI_FIFO1_ETM_ATVALID_Pos) /*!< TPI FIFO1: ETM_ATVALID Mask */ + +#define TPI_FIFO1_ETM_bytecount_Pos 24 /*!< TPI FIFO1: ETM_bytecount Position */ +#define TPI_FIFO1_ETM_bytecount_Msk (0x3UL << TPI_FIFO1_ETM_bytecount_Pos) /*!< TPI FIFO1: ETM_bytecount Mask */ + +#define TPI_FIFO1_ITM2_Pos 16 /*!< TPI FIFO1: ITM2 Position */ +#define TPI_FIFO1_ITM2_Msk (0xFFUL << TPI_FIFO1_ITM2_Pos) /*!< TPI FIFO1: ITM2 Mask */ + +#define TPI_FIFO1_ITM1_Pos 8 /*!< TPI FIFO1: ITM1 Position */ +#define TPI_FIFO1_ITM1_Msk (0xFFUL << TPI_FIFO1_ITM1_Pos) /*!< TPI FIFO1: ITM1 Mask */ + +#define TPI_FIFO1_ITM0_Pos 0 /*!< TPI FIFO1: ITM0 Position */ +#define TPI_FIFO1_ITM0_Msk (0xFFUL << TPI_FIFO1_ITM0_Pos) /*!< TPI FIFO1: ITM0 Mask */ + +/* TPI ITATBCTR0 Register Definitions */ +#define TPI_ITATBCTR0_ATREADY_Pos 0 /*!< TPI ITATBCTR0: ATREADY Position */ +#define TPI_ITATBCTR0_ATREADY_Msk (0x1UL << TPI_ITATBCTR0_ATREADY_Pos) /*!< TPI ITATBCTR0: ATREADY Mask */ + +/* TPI Integration Mode Control Register Definitions */ +#define TPI_ITCTRL_Mode_Pos 0 /*!< TPI ITCTRL: Mode Position */ +#define TPI_ITCTRL_Mode_Msk (0x1UL << TPI_ITCTRL_Mode_Pos) /*!< TPI ITCTRL: Mode Mask */ + +/* TPI DEVID Register Definitions */ +#define TPI_DEVID_NRZVALID_Pos 11 /*!< TPI DEVID: NRZVALID Position */ +#define TPI_DEVID_NRZVALID_Msk (0x1UL << TPI_DEVID_NRZVALID_Pos) /*!< TPI DEVID: NRZVALID Mask */ + +#define TPI_DEVID_MANCVALID_Pos 10 /*!< TPI DEVID: MANCVALID Position */ +#define TPI_DEVID_MANCVALID_Msk (0x1UL << TPI_DEVID_MANCVALID_Pos) /*!< TPI DEVID: MANCVALID Mask */ + +#define TPI_DEVID_PTINVALID_Pos 9 /*!< TPI DEVID: PTINVALID Position */ +#define TPI_DEVID_PTINVALID_Msk (0x1UL << TPI_DEVID_PTINVALID_Pos) /*!< TPI DEVID: PTINVALID Mask */ + +#define TPI_DEVID_MinBufSz_Pos 6 /*!< TPI DEVID: MinBufSz Position */ +#define TPI_DEVID_MinBufSz_Msk (0x7UL << TPI_DEVID_MinBufSz_Pos) /*!< TPI DEVID: MinBufSz Mask */ + +#define TPI_DEVID_AsynClkIn_Pos 5 /*!< TPI DEVID: AsynClkIn Position */ +#define TPI_DEVID_AsynClkIn_Msk (0x1UL << TPI_DEVID_AsynClkIn_Pos) /*!< TPI DEVID: AsynClkIn Mask */ + +#define TPI_DEVID_NrTraceInput_Pos 0 /*!< TPI DEVID: NrTraceInput Position */ +#define TPI_DEVID_NrTraceInput_Msk (0x1FUL << TPI_DEVID_NrTraceInput_Pos) /*!< TPI DEVID: NrTraceInput Mask */ + +/* TPI DEVTYPE Register Definitions */ +#define TPI_DEVTYPE_SubType_Pos 0 /*!< TPI DEVTYPE: SubType Position */ +#define TPI_DEVTYPE_SubType_Msk (0xFUL << TPI_DEVTYPE_SubType_Pos) /*!< TPI DEVTYPE: SubType Mask */ + +#define TPI_DEVTYPE_MajorType_Pos 4 /*!< TPI DEVTYPE: MajorType Position */ +#define TPI_DEVTYPE_MajorType_Msk (0xFUL << TPI_DEVTYPE_MajorType_Pos) /*!< TPI DEVTYPE: MajorType Mask */ + +/*@}*/ /* end of group CMSIS_TPI */ + + +#if (__MPU_PRESENT == 1) +/** \ingroup CMSIS_core_register + \defgroup CMSIS_MPU Memory Protection Unit (MPU) + \brief Type definitions for the Memory Protection Unit (MPU) + @{ + */ + +/** \brief Structure type to access the Memory Protection Unit (MPU). + */ +typedef struct +{ + __I uint32_t TYPE; /*!< Offset: 0x000 (R/ ) MPU Type Register */ + __IO uint32_t CTRL; /*!< Offset: 0x004 (R/W) MPU Control Register */ + __IO uint32_t RNR; /*!< Offset: 0x008 (R/W) MPU Region RNRber Register */ + __IO uint32_t RBAR; /*!< Offset: 0x00C (R/W) MPU Region Base Address Register */ + __IO uint32_t RASR; /*!< Offset: 0x010 (R/W) MPU Region Attribute and Size Register */ + __IO uint32_t RBAR_A1; /*!< Offset: 0x014 (R/W) MPU Alias 1 Region Base Address Register */ + __IO uint32_t RASR_A1; /*!< Offset: 0x018 (R/W) MPU Alias 1 Region Attribute and Size Register */ + __IO uint32_t RBAR_A2; /*!< Offset: 0x01C (R/W) MPU Alias 2 Region Base Address Register */ + __IO uint32_t RASR_A2; /*!< Offset: 0x020 (R/W) MPU Alias 2 Region Attribute and Size Register */ + __IO uint32_t RBAR_A3; /*!< Offset: 0x024 (R/W) MPU Alias 3 Region Base Address Register */ + __IO uint32_t RASR_A3; /*!< Offset: 0x028 (R/W) MPU Alias 3 Region Attribute and Size Register */ +} MPU_Type; + +/* MPU Type Register */ +#define MPU_TYPE_IREGION_Pos 16 /*!< MPU TYPE: IREGION Position */ +#define MPU_TYPE_IREGION_Msk (0xFFUL << MPU_TYPE_IREGION_Pos) /*!< MPU TYPE: IREGION Mask */ + +#define MPU_TYPE_DREGION_Pos 8 /*!< MPU TYPE: DREGION Position */ +#define MPU_TYPE_DREGION_Msk (0xFFUL << MPU_TYPE_DREGION_Pos) /*!< MPU TYPE: DREGION Mask */ + +#define MPU_TYPE_SEPARATE_Pos 0 /*!< MPU TYPE: SEPARATE Position */ +#define MPU_TYPE_SEPARATE_Msk (1UL << MPU_TYPE_SEPARATE_Pos) /*!< MPU TYPE: SEPARATE Mask */ + +/* MPU Control Register */ +#define MPU_CTRL_PRIVDEFENA_Pos 2 /*!< MPU CTRL: PRIVDEFENA Position */ +#define MPU_CTRL_PRIVDEFENA_Msk (1UL << MPU_CTRL_PRIVDEFENA_Pos) /*!< MPU CTRL: PRIVDEFENA Mask */ + +#define MPU_CTRL_HFNMIENA_Pos 1 /*!< MPU CTRL: HFNMIENA Position */ +#define MPU_CTRL_HFNMIENA_Msk (1UL << MPU_CTRL_HFNMIENA_Pos) /*!< MPU CTRL: HFNMIENA Mask */ + +#define MPU_CTRL_ENABLE_Pos 0 /*!< MPU CTRL: ENABLE Position */ +#define MPU_CTRL_ENABLE_Msk (1UL << MPU_CTRL_ENABLE_Pos) /*!< MPU CTRL: ENABLE Mask */ + +/* MPU Region Number Register */ +#define MPU_RNR_REGION_Pos 0 /*!< MPU RNR: REGION Position */ +#define MPU_RNR_REGION_Msk (0xFFUL << MPU_RNR_REGION_Pos) /*!< MPU RNR: REGION Mask */ + +/* MPU Region Base Address Register */ +#define MPU_RBAR_ADDR_Pos 5 /*!< MPU RBAR: ADDR Position */ +#define MPU_RBAR_ADDR_Msk (0x7FFFFFFUL << MPU_RBAR_ADDR_Pos) /*!< MPU RBAR: ADDR Mask */ + +#define MPU_RBAR_VALID_Pos 4 /*!< MPU RBAR: VALID Position */ +#define MPU_RBAR_VALID_Msk (1UL << MPU_RBAR_VALID_Pos) /*!< MPU RBAR: VALID Mask */ + +#define MPU_RBAR_REGION_Pos 0 /*!< MPU RBAR: REGION Position */ +#define MPU_RBAR_REGION_Msk (0xFUL << MPU_RBAR_REGION_Pos) /*!< MPU RBAR: REGION Mask */ + +/* MPU Region Attribute and Size Register */ +#define MPU_RASR_ATTRS_Pos 16 /*!< MPU RASR: MPU Region Attribute field Position */ +#define MPU_RASR_ATTRS_Msk (0xFFFFUL << MPU_RASR_ATTRS_Pos) /*!< MPU RASR: MPU Region Attribute field Mask */ + +#define MPU_RASR_XN_Pos 28 /*!< MPU RASR: ATTRS.XN Position */ +#define MPU_RASR_XN_Msk (1UL << MPU_RASR_XN_Pos) /*!< MPU RASR: ATTRS.XN Mask */ + +#define MPU_RASR_AP_Pos 24 /*!< MPU RASR: ATTRS.AP Position */ +#define MPU_RASR_AP_Msk (0x7UL << MPU_RASR_AP_Pos) /*!< MPU RASR: ATTRS.AP Mask */ + +#define MPU_RASR_TEX_Pos 19 /*!< MPU RASR: ATTRS.TEX Position */ +#define MPU_RASR_TEX_Msk (0x7UL << MPU_RASR_TEX_Pos) /*!< MPU RASR: ATTRS.TEX Mask */ + +#define MPU_RASR_S_Pos 18 /*!< MPU RASR: ATTRS.S Position */ +#define MPU_RASR_S_Msk (1UL << MPU_RASR_S_Pos) /*!< MPU RASR: ATTRS.S Mask */ + +#define MPU_RASR_C_Pos 17 /*!< MPU RASR: ATTRS.C Position */ +#define MPU_RASR_C_Msk (1UL << MPU_RASR_C_Pos) /*!< MPU RASR: ATTRS.C Mask */ + +#define MPU_RASR_B_Pos 16 /*!< MPU RASR: ATTRS.B Position */ +#define MPU_RASR_B_Msk (1UL << MPU_RASR_B_Pos) /*!< MPU RASR: ATTRS.B Mask */ + +#define MPU_RASR_SRD_Pos 8 /*!< MPU RASR: Sub-Region Disable Position */ +#define MPU_RASR_SRD_Msk (0xFFUL << MPU_RASR_SRD_Pos) /*!< MPU RASR: Sub-Region Disable Mask */ + +#define MPU_RASR_SIZE_Pos 1 /*!< MPU RASR: Region Size Field Position */ +#define MPU_RASR_SIZE_Msk (0x1FUL << MPU_RASR_SIZE_Pos) /*!< MPU RASR: Region Size Field Mask */ + +#define MPU_RASR_ENABLE_Pos 0 /*!< MPU RASR: Region enable bit Position */ +#define MPU_RASR_ENABLE_Msk (1UL << MPU_RASR_ENABLE_Pos) /*!< MPU RASR: Region enable bit Disable Mask */ + +/*@} end of group CMSIS_MPU */ +#endif + + +/** \ingroup CMSIS_core_register + \defgroup CMSIS_CoreDebug Core Debug Registers (CoreDebug) + \brief Type definitions for the Core Debug Registers + @{ + */ + +/** \brief Structure type to access the Core Debug Register (CoreDebug). + */ +typedef struct +{ + __IO uint32_t DHCSR; /*!< Offset: 0x000 (R/W) Debug Halting Control and Status Register */ + __O uint32_t DCRSR; /*!< Offset: 0x004 ( /W) Debug Core Register Selector Register */ + __IO uint32_t DCRDR; /*!< Offset: 0x008 (R/W) Debug Core Register Data Register */ + __IO uint32_t DEMCR; /*!< Offset: 0x00C (R/W) Debug Exception and Monitor Control Register */ +} CoreDebug_Type; + +/* Debug Halting Control and Status Register */ +#define CoreDebug_DHCSR_DBGKEY_Pos 16 /*!< CoreDebug DHCSR: DBGKEY Position */ +#define CoreDebug_DHCSR_DBGKEY_Msk (0xFFFFUL << CoreDebug_DHCSR_DBGKEY_Pos) /*!< CoreDebug DHCSR: DBGKEY Mask */ + +#define CoreDebug_DHCSR_S_RESET_ST_Pos 25 /*!< CoreDebug DHCSR: S_RESET_ST Position */ +#define CoreDebug_DHCSR_S_RESET_ST_Msk (1UL << CoreDebug_DHCSR_S_RESET_ST_Pos) /*!< CoreDebug DHCSR: S_RESET_ST Mask */ + +#define CoreDebug_DHCSR_S_RETIRE_ST_Pos 24 /*!< CoreDebug DHCSR: S_RETIRE_ST Position */ +#define CoreDebug_DHCSR_S_RETIRE_ST_Msk (1UL << CoreDebug_DHCSR_S_RETIRE_ST_Pos) /*!< CoreDebug DHCSR: S_RETIRE_ST Mask */ + +#define CoreDebug_DHCSR_S_LOCKUP_Pos 19 /*!< CoreDebug DHCSR: S_LOCKUP Position */ +#define CoreDebug_DHCSR_S_LOCKUP_Msk (1UL << CoreDebug_DHCSR_S_LOCKUP_Pos) /*!< CoreDebug DHCSR: S_LOCKUP Mask */ + +#define CoreDebug_DHCSR_S_SLEEP_Pos 18 /*!< CoreDebug DHCSR: S_SLEEP Position */ +#define CoreDebug_DHCSR_S_SLEEP_Msk (1UL << CoreDebug_DHCSR_S_SLEEP_Pos) /*!< CoreDebug DHCSR: S_SLEEP Mask */ + +#define CoreDebug_DHCSR_S_HALT_Pos 17 /*!< CoreDebug DHCSR: S_HALT Position */ +#define CoreDebug_DHCSR_S_HALT_Msk (1UL << CoreDebug_DHCSR_S_HALT_Pos) /*!< CoreDebug DHCSR: S_HALT Mask */ + +#define CoreDebug_DHCSR_S_REGRDY_Pos 16 /*!< CoreDebug DHCSR: S_REGRDY Position */ +#define CoreDebug_DHCSR_S_REGRDY_Msk (1UL << CoreDebug_DHCSR_S_REGRDY_Pos) /*!< CoreDebug DHCSR: S_REGRDY Mask */ + +#define CoreDebug_DHCSR_C_SNAPSTALL_Pos 5 /*!< CoreDebug DHCSR: C_SNAPSTALL Position */ +#define CoreDebug_DHCSR_C_SNAPSTALL_Msk (1UL << CoreDebug_DHCSR_C_SNAPSTALL_Pos) /*!< CoreDebug DHCSR: C_SNAPSTALL Mask */ + +#define CoreDebug_DHCSR_C_MASKINTS_Pos 3 /*!< CoreDebug DHCSR: C_MASKINTS Position */ +#define CoreDebug_DHCSR_C_MASKINTS_Msk (1UL << CoreDebug_DHCSR_C_MASKINTS_Pos) /*!< CoreDebug DHCSR: C_MASKINTS Mask */ + +#define CoreDebug_DHCSR_C_STEP_Pos 2 /*!< CoreDebug DHCSR: C_STEP Position */ +#define CoreDebug_DHCSR_C_STEP_Msk (1UL << CoreDebug_DHCSR_C_STEP_Pos) /*!< CoreDebug DHCSR: C_STEP Mask */ + +#define CoreDebug_DHCSR_C_HALT_Pos 1 /*!< CoreDebug DHCSR: C_HALT Position */ +#define CoreDebug_DHCSR_C_HALT_Msk (1UL << CoreDebug_DHCSR_C_HALT_Pos) /*!< CoreDebug DHCSR: C_HALT Mask */ + +#define CoreDebug_DHCSR_C_DEBUGEN_Pos 0 /*!< CoreDebug DHCSR: C_DEBUGEN Position */ +#define CoreDebug_DHCSR_C_DEBUGEN_Msk (1UL << CoreDebug_DHCSR_C_DEBUGEN_Pos) /*!< CoreDebug DHCSR: C_DEBUGEN Mask */ + +/* Debug Core Register Selector Register */ +#define CoreDebug_DCRSR_REGWnR_Pos 16 /*!< CoreDebug DCRSR: REGWnR Position */ +#define CoreDebug_DCRSR_REGWnR_Msk (1UL << CoreDebug_DCRSR_REGWnR_Pos) /*!< CoreDebug DCRSR: REGWnR Mask */ + +#define CoreDebug_DCRSR_REGSEL_Pos 0 /*!< CoreDebug DCRSR: REGSEL Position */ +#define CoreDebug_DCRSR_REGSEL_Msk (0x1FUL << CoreDebug_DCRSR_REGSEL_Pos) /*!< CoreDebug DCRSR: REGSEL Mask */ + +/* Debug Exception and Monitor Control Register */ +#define CoreDebug_DEMCR_TRCENA_Pos 24 /*!< CoreDebug DEMCR: TRCENA Position */ +#define CoreDebug_DEMCR_TRCENA_Msk (1UL << CoreDebug_DEMCR_TRCENA_Pos) /*!< CoreDebug DEMCR: TRCENA Mask */ + +#define CoreDebug_DEMCR_MON_REQ_Pos 19 /*!< CoreDebug DEMCR: MON_REQ Position */ +#define CoreDebug_DEMCR_MON_REQ_Msk (1UL << CoreDebug_DEMCR_MON_REQ_Pos) /*!< CoreDebug DEMCR: MON_REQ Mask */ + +#define CoreDebug_DEMCR_MON_STEP_Pos 18 /*!< CoreDebug DEMCR: MON_STEP Position */ +#define CoreDebug_DEMCR_MON_STEP_Msk (1UL << CoreDebug_DEMCR_MON_STEP_Pos) /*!< CoreDebug DEMCR: MON_STEP Mask */ + +#define CoreDebug_DEMCR_MON_PEND_Pos 17 /*!< CoreDebug DEMCR: MON_PEND Position */ +#define CoreDebug_DEMCR_MON_PEND_Msk (1UL << CoreDebug_DEMCR_MON_PEND_Pos) /*!< CoreDebug DEMCR: MON_PEND Mask */ + +#define CoreDebug_DEMCR_MON_EN_Pos 16 /*!< CoreDebug DEMCR: MON_EN Position */ +#define CoreDebug_DEMCR_MON_EN_Msk (1UL << CoreDebug_DEMCR_MON_EN_Pos) /*!< CoreDebug DEMCR: MON_EN Mask */ + +#define CoreDebug_DEMCR_VC_HARDERR_Pos 10 /*!< CoreDebug DEMCR: VC_HARDERR Position */ +#define CoreDebug_DEMCR_VC_HARDERR_Msk (1UL << CoreDebug_DEMCR_VC_HARDERR_Pos) /*!< CoreDebug DEMCR: VC_HARDERR Mask */ + +#define CoreDebug_DEMCR_VC_INTERR_Pos 9 /*!< CoreDebug DEMCR: VC_INTERR Position */ +#define CoreDebug_DEMCR_VC_INTERR_Msk (1UL << CoreDebug_DEMCR_VC_INTERR_Pos) /*!< CoreDebug DEMCR: VC_INTERR Mask */ + +#define CoreDebug_DEMCR_VC_BUSERR_Pos 8 /*!< CoreDebug DEMCR: VC_BUSERR Position */ +#define CoreDebug_DEMCR_VC_BUSERR_Msk (1UL << CoreDebug_DEMCR_VC_BUSERR_Pos) /*!< CoreDebug DEMCR: VC_BUSERR Mask */ + +#define CoreDebug_DEMCR_VC_STATERR_Pos 7 /*!< CoreDebug DEMCR: VC_STATERR Position */ +#define CoreDebug_DEMCR_VC_STATERR_Msk (1UL << CoreDebug_DEMCR_VC_STATERR_Pos) /*!< CoreDebug DEMCR: VC_STATERR Mask */ + +#define CoreDebug_DEMCR_VC_CHKERR_Pos 6 /*!< CoreDebug DEMCR: VC_CHKERR Position */ +#define CoreDebug_DEMCR_VC_CHKERR_Msk (1UL << CoreDebug_DEMCR_VC_CHKERR_Pos) /*!< CoreDebug DEMCR: VC_CHKERR Mask */ + +#define CoreDebug_DEMCR_VC_NOCPERR_Pos 5 /*!< CoreDebug DEMCR: VC_NOCPERR Position */ +#define CoreDebug_DEMCR_VC_NOCPERR_Msk (1UL << CoreDebug_DEMCR_VC_NOCPERR_Pos) /*!< CoreDebug DEMCR: VC_NOCPERR Mask */ + +#define CoreDebug_DEMCR_VC_MMERR_Pos 4 /*!< CoreDebug DEMCR: VC_MMERR Position */ +#define CoreDebug_DEMCR_VC_MMERR_Msk (1UL << CoreDebug_DEMCR_VC_MMERR_Pos) /*!< CoreDebug DEMCR: VC_MMERR Mask */ + +#define CoreDebug_DEMCR_VC_CORERESET_Pos 0 /*!< CoreDebug DEMCR: VC_CORERESET Position */ +#define CoreDebug_DEMCR_VC_CORERESET_Msk (1UL << CoreDebug_DEMCR_VC_CORERESET_Pos) /*!< CoreDebug DEMCR: VC_CORERESET Mask */ + +/*@} end of group CMSIS_CoreDebug */ + + +/** \ingroup CMSIS_core_register + \defgroup CMSIS_core_base Core Definitions + \brief Definitions for base addresses, unions, and structures. + @{ + */ + +/* Memory mapping of Cortex-M3 Hardware */ +#define SCS_BASE (0xE000E000UL) /*!< System Control Space Base Address */ +#define ITM_BASE (0xE0000000UL) /*!< ITM Base Address */ +#define DWT_BASE (0xE0001000UL) /*!< DWT Base Address */ +#define TPI_BASE (0xE0040000UL) /*!< TPI Base Address */ +#define CoreDebug_BASE (0xE000EDF0UL) /*!< Core Debug Base Address */ +#define SysTick_BASE (SCS_BASE + 0x0010UL) /*!< SysTick Base Address */ +#define NVIC_BASE (SCS_BASE + 0x0100UL) /*!< NVIC Base Address */ +#define SCB_BASE (SCS_BASE + 0x0D00UL) /*!< System Control Block Base Address */ + +#define SCnSCB ((SCnSCB_Type *) SCS_BASE ) /*!< System control Register not in SCB */ +#define SCB ((SCB_Type *) SCB_BASE ) /*!< SCB configuration struct */ +#define SysTick ((SysTick_Type *) SysTick_BASE ) /*!< SysTick configuration struct */ +#define NVIC ((NVIC_Type *) NVIC_BASE ) /*!< NVIC configuration struct */ +#define ITM ((ITM_Type *) ITM_BASE ) /*!< ITM configuration struct */ +#define DWT ((DWT_Type *) DWT_BASE ) /*!< DWT configuration struct */ +#define TPI ((TPI_Type *) TPI_BASE ) /*!< TPI configuration struct */ +#define CoreDebug ((CoreDebug_Type *) CoreDebug_BASE) /*!< Core Debug configuration struct */ + +#if (__MPU_PRESENT == 1) + #define MPU_BASE (SCS_BASE + 0x0D90UL) /*!< Memory Protection Unit */ + #define MPU ((MPU_Type *) MPU_BASE ) /*!< Memory Protection Unit */ +#endif + +/*@} */ + + + +/******************************************************************************* + * Hardware Abstraction Layer + Core Function Interface contains: + - Core NVIC Functions + - Core SysTick Functions + - Core Debug Functions + - Core Register Access Functions + ******************************************************************************/ +/** \defgroup CMSIS_Core_FunctionInterface Functions and Instructions Reference +*/ + + + +/* ########################## NVIC functions #################################### */ +/** \ingroup CMSIS_Core_FunctionInterface + \defgroup CMSIS_Core_NVICFunctions NVIC Functions + \brief Functions that manage interrupts and exceptions via the NVIC. + @{ + */ + +/** \brief Set Priority Grouping + + The function sets the priority grouping field using the required unlock sequence. + The parameter PriorityGroup is assigned to the field SCB->AIRCR [10:8] PRIGROUP field. + Only values from 0..7 are used. + In case of a conflict between priority grouping and available + priority bits (__NVIC_PRIO_BITS), the smallest possible priority group is set. + + \param [in] PriorityGroup Priority grouping field. + */ +__STATIC_INLINE void NVIC_SetPriorityGrouping(uint32_t PriorityGroup) +{ + uint32_t reg_value; + uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07); /* only values 0..7 are used */ + + reg_value = SCB->AIRCR; /* read old register configuration */ + reg_value &= ~(SCB_AIRCR_VECTKEY_Msk | SCB_AIRCR_PRIGROUP_Msk); /* clear bits to change */ + reg_value = (reg_value | + ((uint32_t)0x5FA << SCB_AIRCR_VECTKEY_Pos) | + (PriorityGroupTmp << 8)); /* Insert write key and priorty group */ + SCB->AIRCR = reg_value; +} + + +/** \brief Get Priority Grouping + + The function reads the priority grouping field from the NVIC Interrupt Controller. + + \return Priority grouping field (SCB->AIRCR [10:8] PRIGROUP field). + */ +__STATIC_INLINE uint32_t NVIC_GetPriorityGrouping(void) +{ + return ((SCB->AIRCR & SCB_AIRCR_PRIGROUP_Msk) >> SCB_AIRCR_PRIGROUP_Pos); /* read priority grouping field */ +} + + +/** \brief Enable External Interrupt + + The function enables a device-specific interrupt in the NVIC interrupt controller. + + \param [in] IRQn External interrupt number. Value cannot be negative. + */ +__STATIC_INLINE void NVIC_EnableIRQ(IRQn_Type IRQn) +{ + NVIC->ISER[((uint32_t)(IRQn) >> 5)] = (1 << ((uint32_t)(IRQn) & 0x1F)); /* enable interrupt */ +} + + +/** \brief Disable External Interrupt + + The function disables a device-specific interrupt in the NVIC interrupt controller. + + \param [in] IRQn External interrupt number. Value cannot be negative. + */ +__STATIC_INLINE void NVIC_DisableIRQ(IRQn_Type IRQn) +{ + NVIC->ICER[((uint32_t)(IRQn) >> 5)] = (1 << ((uint32_t)(IRQn) & 0x1F)); /* disable interrupt */ +} + + +/** \brief Get Pending Interrupt + + The function reads the pending register in the NVIC and returns the pending bit + for the specified interrupt. + + \param [in] IRQn Interrupt number. + + \return 0 Interrupt status is not pending. + \return 1 Interrupt status is pending. + */ +__STATIC_INLINE uint32_t NVIC_GetPendingIRQ(IRQn_Type IRQn) +{ + return((uint32_t) ((NVIC->ISPR[(uint32_t)(IRQn) >> 5] & (1 << ((uint32_t)(IRQn) & 0x1F)))?1:0)); /* Return 1 if pending else 0 */ +} + + +/** \brief Set Pending Interrupt + + The function sets the pending bit of an external interrupt. + + \param [in] IRQn Interrupt number. Value cannot be negative. + */ +__STATIC_INLINE void NVIC_SetPendingIRQ(IRQn_Type IRQn) +{ + NVIC->ISPR[((uint32_t)(IRQn) >> 5)] = (1 << ((uint32_t)(IRQn) & 0x1F)); /* set interrupt pending */ +} + + +/** \brief Clear Pending Interrupt + + The function clears the pending bit of an external interrupt. + + \param [in] IRQn External interrupt number. Value cannot be negative. + */ +__STATIC_INLINE void NVIC_ClearPendingIRQ(IRQn_Type IRQn) +{ + NVIC->ICPR[((uint32_t)(IRQn) >> 5)] = (1 << ((uint32_t)(IRQn) & 0x1F)); /* Clear pending interrupt */ +} + + +/** \brief Get Active Interrupt + + The function reads the active register in NVIC and returns the active bit. + + \param [in] IRQn Interrupt number. + + \return 0 Interrupt status is not active. + \return 1 Interrupt status is active. + */ +__STATIC_INLINE uint32_t NVIC_GetActive(IRQn_Type IRQn) +{ + return((uint32_t)((NVIC->IABR[(uint32_t)(IRQn) >> 5] & (1 << ((uint32_t)(IRQn) & 0x1F)))?1:0)); /* Return 1 if active else 0 */ +} + + +/** \brief Set Interrupt Priority + + The function sets the priority of an interrupt. + + \note The priority cannot be set for every core interrupt. + + \param [in] IRQn Interrupt number. + \param [in] priority Priority to set. + */ +__STATIC_INLINE void NVIC_SetPriority(IRQn_Type IRQn, uint32_t priority) +{ + if(IRQn < 0) { + SCB->SHP[((uint32_t)(IRQn) & 0xF)-4] = ((priority << (8 - __NVIC_PRIO_BITS)) & 0xff); } /* set Priority for Cortex-M System Interrupts */ + else { + NVIC->IP[(uint32_t)(IRQn)] = ((priority << (8 - __NVIC_PRIO_BITS)) & 0xff); } /* set Priority for device specific Interrupts */ +} + + +/** \brief Get Interrupt Priority + + The function reads the priority of an interrupt. The interrupt + number can be positive to specify an external (device specific) + interrupt, or negative to specify an internal (core) interrupt. + + + \param [in] IRQn Interrupt number. + \return Interrupt Priority. Value is aligned automatically to the implemented + priority bits of the microcontroller. + */ +__STATIC_INLINE uint32_t NVIC_GetPriority(IRQn_Type IRQn) +{ + + if(IRQn < 0) { + return((uint32_t)(SCB->SHP[((uint32_t)(IRQn) & 0xF)-4] >> (8 - __NVIC_PRIO_BITS))); } /* get priority for Cortex-M system interrupts */ + else { + return((uint32_t)(NVIC->IP[(uint32_t)(IRQn)] >> (8 - __NVIC_PRIO_BITS))); } /* get priority for device specific interrupts */ +} + + +/** \brief Encode Priority + + The function encodes the priority for an interrupt with the given priority group, + preemptive priority value, and subpriority value. + In case of a conflict between priority grouping and available + priority bits (__NVIC_PRIO_BITS), the samllest possible priority group is set. + + \param [in] PriorityGroup Used priority group. + \param [in] PreemptPriority Preemptive priority value (starting from 0). + \param [in] SubPriority Subpriority value (starting from 0). + \return Encoded priority. Value can be used in the function \ref NVIC_SetPriority(). + */ +__STATIC_INLINE uint32_t NVIC_EncodePriority (uint32_t PriorityGroup, uint32_t PreemptPriority, uint32_t SubPriority) +{ + uint32_t PriorityGroupTmp = (PriorityGroup & 0x07); /* only values 0..7 are used */ + uint32_t PreemptPriorityBits; + uint32_t SubPriorityBits; + + PreemptPriorityBits = ((7 - PriorityGroupTmp) > __NVIC_PRIO_BITS) ? __NVIC_PRIO_BITS : 7 - PriorityGroupTmp; + SubPriorityBits = ((PriorityGroupTmp + __NVIC_PRIO_BITS) < 7) ? 0 : PriorityGroupTmp - 7 + __NVIC_PRIO_BITS; + + return ( + ((PreemptPriority & ((1 << (PreemptPriorityBits)) - 1)) << SubPriorityBits) | + ((SubPriority & ((1 << (SubPriorityBits )) - 1))) + ); +} + + +/** \brief Decode Priority + + The function decodes an interrupt priority value with a given priority group to + preemptive priority value and subpriority value. + In case of a conflict between priority grouping and available + priority bits (__NVIC_PRIO_BITS) the samllest possible priority group is set. + + \param [in] Priority Priority value, which can be retrieved with the function \ref NVIC_GetPriority(). + \param [in] PriorityGroup Used priority group. + \param [out] pPreemptPriority Preemptive priority value (starting from 0). + \param [out] pSubPriority Subpriority value (starting from 0). + */ +__STATIC_INLINE void NVIC_DecodePriority (uint32_t Priority, uint32_t PriorityGroup, uint32_t* pPreemptPriority, uint32_t* pSubPriority) +{ + uint32_t PriorityGroupTmp = (PriorityGroup & 0x07); /* only values 0..7 are used */ + uint32_t PreemptPriorityBits; + uint32_t SubPriorityBits; + + PreemptPriorityBits = ((7 - PriorityGroupTmp) > __NVIC_PRIO_BITS) ? __NVIC_PRIO_BITS : 7 - PriorityGroupTmp; + SubPriorityBits = ((PriorityGroupTmp + __NVIC_PRIO_BITS) < 7) ? 0 : PriorityGroupTmp - 7 + __NVIC_PRIO_BITS; + + *pPreemptPriority = (Priority >> SubPriorityBits) & ((1 << (PreemptPriorityBits)) - 1); + *pSubPriority = (Priority ) & ((1 << (SubPriorityBits )) - 1); +} + + +/** \brief System Reset + + The function initiates a system reset request to reset the MCU. + */ +__STATIC_INLINE void NVIC_SystemReset(void) +{ + __DSB(); /* Ensure all outstanding memory accesses included + buffered write are completed before reset */ + SCB->AIRCR = ((0x5FA << SCB_AIRCR_VECTKEY_Pos) | + (SCB->AIRCR & SCB_AIRCR_PRIGROUP_Msk) | + SCB_AIRCR_SYSRESETREQ_Msk); /* Keep priority group unchanged */ + __DSB(); /* Ensure completion of memory access */ + while(1); /* wait until reset */ +} + +/*@} end of CMSIS_Core_NVICFunctions */ + + + +/* ################################## SysTick function ############################################ */ +/** \ingroup CMSIS_Core_FunctionInterface + \defgroup CMSIS_Core_SysTickFunctions SysTick Functions + \brief Functions that configure the System. + @{ + */ + +#if (__Vendor_SysTickConfig == 0) + +/** \brief System Tick Configuration + + The function initializes the System Timer and its interrupt, and starts the System Tick Timer. + Counter is in free running mode to generate periodic interrupts. + + \param [in] ticks Number of ticks between two interrupts. + + \return 0 Function succeeded. + \return 1 Function failed. + + \note When the variable __Vendor_SysTickConfig is set to 1, then the + function SysTick_Config is not included. In this case, the file device.h + must contain a vendor-specific implementation of this function. + + */ +__STATIC_INLINE uint32_t SysTick_Config(uint32_t ticks) +{ + if (ticks > SysTick_LOAD_RELOAD_Msk) return (1); /* Reload value impossible */ + + SysTick->LOAD = (ticks & SysTick_LOAD_RELOAD_Msk) - 1; /* set reload register */ + NVIC_SetPriority (SysTick_IRQn, (1<<__NVIC_PRIO_BITS) - 1); /* set Priority for Systick Interrupt */ + SysTick->VAL = 0; /* Load the SysTick Counter Value */ + SysTick->CTRL = SysTick_CTRL_CLKSOURCE_Msk | + SysTick_CTRL_TICKINT_Msk | + SysTick_CTRL_ENABLE_Msk; /* Enable SysTick IRQ and SysTick Timer */ + return (0); /* Function successful */ +} + +#endif + +/*@} end of CMSIS_Core_SysTickFunctions */ + + + +/* ##################################### Debug In/Output function ########################################### */ +/** \ingroup CMSIS_Core_FunctionInterface + \defgroup CMSIS_core_DebugFunctions ITM Functions + \brief Functions that access the ITM debug interface. + @{ + */ + +extern volatile int32_t ITM_RxBuffer; /*!< External variable to receive characters. */ +#define ITM_RXBUFFER_EMPTY 0x5AA55AA5 /*!< Value identifying \ref ITM_RxBuffer is ready for next character. */ + + +/** \brief ITM Send Character + + The function transmits a character via the ITM channel 0, and + \li Just returns when no debugger is connected that has booked the output. + \li Is blocking when a debugger is connected, but the previous character sent has not been transmitted. + + \param [in] ch Character to transmit. + + \returns Character to transmit. + */ +__STATIC_INLINE uint32_t ITM_SendChar (uint32_t ch) +{ + if ((ITM->TCR & ITM_TCR_ITMENA_Msk) && /* ITM enabled */ + (ITM->TER & (1UL << 0) ) ) /* ITM Port #0 enabled */ + { + while (ITM->PORT[0].u32 == 0); + ITM->PORT[0].u8 = (uint8_t) ch; + } + return (ch); +} + + +/** \brief ITM Receive Character + + The function inputs a character via the external variable \ref ITM_RxBuffer. + + \return Received character. + \return -1 No character pending. + */ +__STATIC_INLINE int32_t ITM_ReceiveChar (void) { + int32_t ch = -1; /* no character available */ + + if (ITM_RxBuffer != ITM_RXBUFFER_EMPTY) { + ch = ITM_RxBuffer; + ITM_RxBuffer = ITM_RXBUFFER_EMPTY; /* ready for next character */ + } + + return (ch); +} + + +/** \brief ITM Check Character + + The function checks whether a character is pending for reading in the variable \ref ITM_RxBuffer. + + \return 0 No character available. + \return 1 Character available. + */ +__STATIC_INLINE int32_t ITM_CheckChar (void) { + + if (ITM_RxBuffer == ITM_RXBUFFER_EMPTY) { + return (0); /* no character available */ + } else { + return (1); /* character available */ + } +} + +/*@} end of CMSIS_core_DebugFunctions */ + +#endif /* __CORE_CM3_H_DEPENDANT */ + +#endif /* __CMSIS_GENERIC */ + +#ifdef __cplusplus +} +#endif diff --git a/Libraries/CMSIS/Include/core_cm4.h b/Libraries/CMSIS/Include/core_cm4.h new file mode 100644 index 0000000..a965537 --- /dev/null +++ b/Libraries/CMSIS/Include/core_cm4.h @@ -0,0 +1,1757 @@ +/**************************************************************************//** + * @file core_cm4.h + * @brief CMSIS Cortex-M4 Core Peripheral Access Layer Header File + * @version V3.01 + * @date 22. March 2012 + * + * @note + * Copyright (C) 2009-2012 ARM Limited. All rights reserved. + * + * @par + * ARM Limited (ARM) is supplying this software for use with Cortex-M + * processor based microcontrollers. This file can be freely distributed + * within development tools that are supporting such ARM based processors. + * + * @par + * THIS SOFTWARE IS PROVIDED "AS IS". NO WARRANTIES, WHETHER EXPRESS, IMPLIED + * OR STATUTORY, INCLUDING, BUT NOT LIMITED TO, IMPLIED WARRANTIES OF + * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE APPLY TO THIS SOFTWARE. + * ARM SHALL NOT, IN ANY CIRCUMSTANCES, BE LIABLE FOR SPECIAL, INCIDENTAL, OR + * CONSEQUENTIAL DAMAGES, FOR ANY REASON WHATSOEVER. + * + ******************************************************************************/ +#if defined ( __ICCARM__ ) + #pragma system_include /* treat file as system include file for MISRA check */ +#endif + +#ifdef __cplusplus + extern "C" { +#endif + +#ifndef __CORE_CM4_H_GENERIC +#define __CORE_CM4_H_GENERIC + +/** \page CMSIS_MISRA_Exceptions MISRA-C:2004 Compliance Exceptions + CMSIS violates the following MISRA-C:2004 rules: + + \li Required Rule 8.5, object/function definition in header file.
    + Function definitions in header files are used to allow 'inlining'. + + \li Required Rule 18.4, declaration of union type or object of union type: '{...}'.
    + Unions are used for effective representation of core registers. + + \li Advisory Rule 19.7, Function-like macro defined.
    + Function-like macros are used to allow more efficient code. + */ + + +/******************************************************************************* + * CMSIS definitions + ******************************************************************************/ +/** \ingroup Cortex_M4 + @{ + */ + +/* CMSIS CM4 definitions */ +#define __CM4_CMSIS_VERSION_MAIN (0x03) /*!< [31:16] CMSIS HAL main version */ +#define __CM4_CMSIS_VERSION_SUB (0x01) /*!< [15:0] CMSIS HAL sub version */ +#define __CM4_CMSIS_VERSION ((__CM4_CMSIS_VERSION_MAIN << 16) | \ + __CM4_CMSIS_VERSION_SUB ) /*!< CMSIS HAL version number */ + +#define __CORTEX_M (0x04) /*!< Cortex-M Core */ + + +#if defined ( __CC_ARM ) + #define __ASM __asm /*!< asm keyword for ARM Compiler */ + #define __INLINE __inline /*!< inline keyword for ARM Compiler */ + #define __STATIC_INLINE static __inline + +#elif defined ( __ICCARM__ ) + #define __ASM __asm /*!< asm keyword for IAR Compiler */ + #define __INLINE inline /*!< inline keyword for IAR Compiler. Only available in High optimization mode! */ + #define __STATIC_INLINE static inline + +#elif defined ( __TMS470__ ) + #define __ASM __asm /*!< asm keyword for TI CCS Compiler */ + #define __STATIC_INLINE static inline + +#elif defined ( __GNUC__ ) + #define __ASM __asm /*!< asm keyword for GNU Compiler */ + #define __INLINE inline /*!< inline keyword for GNU Compiler */ + #define __STATIC_INLINE static inline + +#elif defined ( __TASKING__ ) + #define __ASM __asm /*!< asm keyword for TASKING Compiler */ + #define __INLINE inline /*!< inline keyword for TASKING Compiler */ + #define __STATIC_INLINE static inline + +#endif + +/** __FPU_USED indicates whether an FPU is used or not. For this, __FPU_PRESENT has to be checked prior to making use of FPU specific registers and functions. +*/ +#if defined ( __CC_ARM ) + #if defined __TARGET_FPU_VFP + #if (__FPU_PRESENT == 1) + #define __FPU_USED 1 + #else + #warning "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #define __FPU_USED 0 + #endif + #else + #define __FPU_USED 0 + #endif + +#elif defined ( __ICCARM__ ) + #if defined __ARMVFP__ + #if (__FPU_PRESENT == 1) + #define __FPU_USED 1 + #else + #warning "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #define __FPU_USED 0 + #endif + #else + #define __FPU_USED 0 + #endif + +#elif defined ( __TMS470__ ) + #if defined __TI_VFP_SUPPORT__ + #if (__FPU_PRESENT == 1) + #define __FPU_USED 1 + #else + #warning "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #define __FPU_USED 0 + #endif + #else + #define __FPU_USED 0 + #endif + +#elif defined ( __GNUC__ ) + #if defined (__VFP_FP__) && !defined(__SOFTFP__) + #if (__FPU_PRESENT == 1) + #define __FPU_USED 1 + #else + #warning "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #define __FPU_USED 0 + #endif + #else + #define __FPU_USED 0 + #endif + +#elif defined ( __TASKING__ ) + #if defined __FPU_VFP__ + #if (__FPU_PRESENT == 1) + #define __FPU_USED 1 + #else + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #define __FPU_USED 0 + #endif + #else + #define __FPU_USED 0 + #endif +#endif + +#include /* standard types definitions */ +#include /* Core Instruction Access */ +#include /* Core Function Access */ +#include /* Compiler specific SIMD Intrinsics */ + +#endif /* __CORE_CM4_H_GENERIC */ + +#ifndef __CMSIS_GENERIC + +#ifndef __CORE_CM4_H_DEPENDANT +#define __CORE_CM4_H_DEPENDANT + +/* check device defines and use defaults */ +#if defined __CHECK_DEVICE_DEFINES + #ifndef __CM4_REV + #define __CM4_REV 0x0000 + #warning "__CM4_REV not defined in device header file; using default!" + #endif + + #ifndef __FPU_PRESENT + #define __FPU_PRESENT 0 + #warning "__FPU_PRESENT not defined in device header file; using default!" + #endif + + #ifndef __MPU_PRESENT + #define __MPU_PRESENT 0 + #warning "__MPU_PRESENT not defined in device header file; using default!" + #endif + + #ifndef __NVIC_PRIO_BITS + #define __NVIC_PRIO_BITS 4 + #warning "__NVIC_PRIO_BITS not defined in device header file; using default!" + #endif + + #ifndef __Vendor_SysTickConfig + #define __Vendor_SysTickConfig 0 + #warning "__Vendor_SysTickConfig not defined in device header file; using default!" + #endif +#endif + +/* IO definitions (access restrictions to peripheral registers) */ +/** + \defgroup CMSIS_glob_defs CMSIS Global Defines + + IO Type Qualifiers are used + \li to specify the access to peripheral variables. + \li for automatic generation of peripheral register debug information. +*/ +#ifdef __cplusplus + #define __I volatile /*!< Defines 'read only' permissions */ +#else + #define __I volatile const /*!< Defines 'read only' permissions */ +#endif +#define __O volatile /*!< Defines 'write only' permissions */ +#define __IO volatile /*!< Defines 'read / write' permissions */ + +/*@} end of group Cortex_M4 */ + + + +/******************************************************************************* + * Register Abstraction + Core Register contain: + - Core Register + - Core NVIC Register + - Core SCB Register + - Core SysTick Register + - Core Debug Register + - Core MPU Register + - Core FPU Register + ******************************************************************************/ +/** \defgroup CMSIS_core_register Defines and Type Definitions + \brief Type definitions and defines for Cortex-M processor based devices. +*/ + +/** \ingroup CMSIS_core_register + \defgroup CMSIS_CORE Status and Control Registers + \brief Core Register type definitions. + @{ + */ + +/** \brief Union type to access the Application Program Status Register (APSR). + */ +typedef union +{ + struct + { +#if (__CORTEX_M != 0x04) + uint32_t _reserved0:27; /*!< bit: 0..26 Reserved */ +#else + uint32_t _reserved0:16; /*!< bit: 0..15 Reserved */ + uint32_t GE:4; /*!< bit: 16..19 Greater than or Equal flags */ + uint32_t _reserved1:7; /*!< bit: 20..26 Reserved */ +#endif + uint32_t Q:1; /*!< bit: 27 Saturation condition flag */ + uint32_t V:1; /*!< bit: 28 Overflow condition code flag */ + uint32_t C:1; /*!< bit: 29 Carry condition code flag */ + uint32_t Z:1; /*!< bit: 30 Zero condition code flag */ + uint32_t N:1; /*!< bit: 31 Negative condition code flag */ + } b; /*!< Structure used for bit access */ + uint32_t w; /*!< Type used for word access */ +} APSR_Type; + + +/** \brief Union type to access the Interrupt Program Status Register (IPSR). + */ +typedef union +{ + struct + { + uint32_t ISR:9; /*!< bit: 0.. 8 Exception number */ + uint32_t _reserved0:23; /*!< bit: 9..31 Reserved */ + } b; /*!< Structure used for bit access */ + uint32_t w; /*!< Type used for word access */ +} IPSR_Type; + + +/** \brief Union type to access the Special-Purpose Program Status Registers (xPSR). + */ +typedef union +{ + struct + { + uint32_t ISR:9; /*!< bit: 0.. 8 Exception number */ +#if (__CORTEX_M != 0x04) + uint32_t _reserved0:15; /*!< bit: 9..23 Reserved */ +#else + uint32_t _reserved0:7; /*!< bit: 9..15 Reserved */ + uint32_t GE:4; /*!< bit: 16..19 Greater than or Equal flags */ + uint32_t _reserved1:4; /*!< bit: 20..23 Reserved */ +#endif + uint32_t T:1; /*!< bit: 24 Thumb bit (read 0) */ + uint32_t IT:2; /*!< bit: 25..26 saved IT state (read 0) */ + uint32_t Q:1; /*!< bit: 27 Saturation condition flag */ + uint32_t V:1; /*!< bit: 28 Overflow condition code flag */ + uint32_t C:1; /*!< bit: 29 Carry condition code flag */ + uint32_t Z:1; /*!< bit: 30 Zero condition code flag */ + uint32_t N:1; /*!< bit: 31 Negative condition code flag */ + } b; /*!< Structure used for bit access */ + uint32_t w; /*!< Type used for word access */ +} xPSR_Type; + + +/** \brief Union type to access the Control Registers (CONTROL). + */ +typedef union +{ + struct + { + uint32_t nPRIV:1; /*!< bit: 0 Execution privilege in Thread mode */ + uint32_t SPSEL:1; /*!< bit: 1 Stack to be used */ + uint32_t FPCA:1; /*!< bit: 2 FP extension active flag */ + uint32_t _reserved0:29; /*!< bit: 3..31 Reserved */ + } b; /*!< Structure used for bit access */ + uint32_t w; /*!< Type used for word access */ +} CONTROL_Type; + +/*@} end of group CMSIS_CORE */ + + +/** \ingroup CMSIS_core_register + \defgroup CMSIS_NVIC Nested Vectored Interrupt Controller (NVIC) + \brief Type definitions for the NVIC Registers + @{ + */ + +/** \brief Structure type to access the Nested Vectored Interrupt Controller (NVIC). + */ +typedef struct +{ + __IO uint32_t ISER[8]; /*!< Offset: 0x000 (R/W) Interrupt Set Enable Register */ + uint32_t RESERVED0[24]; + __IO uint32_t ICER[8]; /*!< Offset: 0x080 (R/W) Interrupt Clear Enable Register */ + uint32_t RSERVED1[24]; + __IO uint32_t ISPR[8]; /*!< Offset: 0x100 (R/W) Interrupt Set Pending Register */ + uint32_t RESERVED2[24]; + __IO uint32_t ICPR[8]; /*!< Offset: 0x180 (R/W) Interrupt Clear Pending Register */ + uint32_t RESERVED3[24]; + __IO uint32_t IABR[8]; /*!< Offset: 0x200 (R/W) Interrupt Active bit Register */ + uint32_t RESERVED4[56]; + __IO uint8_t IP[240]; /*!< Offset: 0x300 (R/W) Interrupt Priority Register (8Bit wide) */ + uint32_t RESERVED5[644]; + __O uint32_t STIR; /*!< Offset: 0xE00 ( /W) Software Trigger Interrupt Register */ +} NVIC_Type; + +/* Software Triggered Interrupt Register Definitions */ +#define NVIC_STIR_INTID_Pos 0 /*!< STIR: INTLINESNUM Position */ +#define NVIC_STIR_INTID_Msk (0x1FFUL << NVIC_STIR_INTID_Pos) /*!< STIR: INTLINESNUM Mask */ + +/*@} end of group CMSIS_NVIC */ + + +/** \ingroup CMSIS_core_register + \defgroup CMSIS_SCB System Control Block (SCB) + \brief Type definitions for the System Control Block Registers + @{ + */ + +/** \brief Structure type to access the System Control Block (SCB). + */ +typedef struct +{ + __I uint32_t CPUID; /*!< Offset: 0x000 (R/ ) CPUID Base Register */ + __IO uint32_t ICSR; /*!< Offset: 0x004 (R/W) Interrupt Control and State Register */ + __IO uint32_t VTOR; /*!< Offset: 0x008 (R/W) Vector Table Offset Register */ + __IO uint32_t AIRCR; /*!< Offset: 0x00C (R/W) Application Interrupt and Reset Control Register */ + __IO uint32_t SCR; /*!< Offset: 0x010 (R/W) System Control Register */ + __IO uint32_t CCR; /*!< Offset: 0x014 (R/W) Configuration Control Register */ + __IO uint8_t SHP[12]; /*!< Offset: 0x018 (R/W) System Handlers Priority Registers (4-7, 8-11, 12-15) */ + __IO uint32_t SHCSR; /*!< Offset: 0x024 (R/W) System Handler Control and State Register */ + __IO uint32_t CFSR; /*!< Offset: 0x028 (R/W) Configurable Fault Status Register */ + __IO uint32_t HFSR; /*!< Offset: 0x02C (R/W) HardFault Status Register */ + __IO uint32_t DFSR; /*!< Offset: 0x030 (R/W) Debug Fault Status Register */ + __IO uint32_t MMFAR; /*!< Offset: 0x034 (R/W) MemManage Fault Address Register */ + __IO uint32_t BFAR; /*!< Offset: 0x038 (R/W) BusFault Address Register */ + __IO uint32_t AFSR; /*!< Offset: 0x03C (R/W) Auxiliary Fault Status Register */ + __I uint32_t PFR[2]; /*!< Offset: 0x040 (R/ ) Processor Feature Register */ + __I uint32_t DFR; /*!< Offset: 0x048 (R/ ) Debug Feature Register */ + __I uint32_t ADR; /*!< Offset: 0x04C (R/ ) Auxiliary Feature Register */ + __I uint32_t MMFR[4]; /*!< Offset: 0x050 (R/ ) Memory Model Feature Register */ + __I uint32_t ISAR[5]; /*!< Offset: 0x060 (R/ ) Instruction Set Attributes Register */ + uint32_t RESERVED0[5]; + __IO uint32_t CPACR; /*!< Offset: 0x088 (R/W) Coprocessor Access Control Register */ +} SCB_Type; + +/* SCB CPUID Register Definitions */ +#define SCB_CPUID_IMPLEMENTER_Pos 24 /*!< SCB CPUID: IMPLEMENTER Position */ +#define SCB_CPUID_IMPLEMENTER_Msk (0xFFUL << SCB_CPUID_IMPLEMENTER_Pos) /*!< SCB CPUID: IMPLEMENTER Mask */ + +#define SCB_CPUID_VARIANT_Pos 20 /*!< SCB CPUID: VARIANT Position */ +#define SCB_CPUID_VARIANT_Msk (0xFUL << SCB_CPUID_VARIANT_Pos) /*!< SCB CPUID: VARIANT Mask */ + +#define SCB_CPUID_ARCHITECTURE_Pos 16 /*!< SCB CPUID: ARCHITECTURE Position */ +#define SCB_CPUID_ARCHITECTURE_Msk (0xFUL << SCB_CPUID_ARCHITECTURE_Pos) /*!< SCB CPUID: ARCHITECTURE Mask */ + +#define SCB_CPUID_PARTNO_Pos 4 /*!< SCB CPUID: PARTNO Position */ +#define SCB_CPUID_PARTNO_Msk (0xFFFUL << SCB_CPUID_PARTNO_Pos) /*!< SCB CPUID: PARTNO Mask */ + +#define SCB_CPUID_REVISION_Pos 0 /*!< SCB CPUID: REVISION Position */ +#define SCB_CPUID_REVISION_Msk (0xFUL << SCB_CPUID_REVISION_Pos) /*!< SCB CPUID: REVISION Mask */ + +/* SCB Interrupt Control State Register Definitions */ +#define SCB_ICSR_NMIPENDSET_Pos 31 /*!< SCB ICSR: NMIPENDSET Position */ +#define SCB_ICSR_NMIPENDSET_Msk (1UL << SCB_ICSR_NMIPENDSET_Pos) /*!< SCB ICSR: NMIPENDSET Mask */ + +#define SCB_ICSR_PENDSVSET_Pos 28 /*!< SCB ICSR: PENDSVSET Position */ +#define SCB_ICSR_PENDSVSET_Msk (1UL << SCB_ICSR_PENDSVSET_Pos) /*!< SCB ICSR: PENDSVSET Mask */ + +#define SCB_ICSR_PENDSVCLR_Pos 27 /*!< SCB ICSR: PENDSVCLR Position */ +#define SCB_ICSR_PENDSVCLR_Msk (1UL << SCB_ICSR_PENDSVCLR_Pos) /*!< SCB ICSR: PENDSVCLR Mask */ + +#define SCB_ICSR_PENDSTSET_Pos 26 /*!< SCB ICSR: PENDSTSET Position */ +#define SCB_ICSR_PENDSTSET_Msk (1UL << SCB_ICSR_PENDSTSET_Pos) /*!< SCB ICSR: PENDSTSET Mask */ + +#define SCB_ICSR_PENDSTCLR_Pos 25 /*!< SCB ICSR: PENDSTCLR Position */ +#define SCB_ICSR_PENDSTCLR_Msk (1UL << SCB_ICSR_PENDSTCLR_Pos) /*!< SCB ICSR: PENDSTCLR Mask */ + +#define SCB_ICSR_ISRPREEMPT_Pos 23 /*!< SCB ICSR: ISRPREEMPT Position */ +#define SCB_ICSR_ISRPREEMPT_Msk (1UL << SCB_ICSR_ISRPREEMPT_Pos) /*!< SCB ICSR: ISRPREEMPT Mask */ + +#define SCB_ICSR_ISRPENDING_Pos 22 /*!< SCB ICSR: ISRPENDING Position */ +#define SCB_ICSR_ISRPENDING_Msk (1UL << SCB_ICSR_ISRPENDING_Pos) /*!< SCB ICSR: ISRPENDING Mask */ + +#define SCB_ICSR_VECTPENDING_Pos 12 /*!< SCB ICSR: VECTPENDING Position */ +#define SCB_ICSR_VECTPENDING_Msk (0x1FFUL << SCB_ICSR_VECTPENDING_Pos) /*!< SCB ICSR: VECTPENDING Mask */ + +#define SCB_ICSR_RETTOBASE_Pos 11 /*!< SCB ICSR: RETTOBASE Position */ +#define SCB_ICSR_RETTOBASE_Msk (1UL << SCB_ICSR_RETTOBASE_Pos) /*!< SCB ICSR: RETTOBASE Mask */ + +#define SCB_ICSR_VECTACTIVE_Pos 0 /*!< SCB ICSR: VECTACTIVE Position */ +#define SCB_ICSR_VECTACTIVE_Msk (0x1FFUL << SCB_ICSR_VECTACTIVE_Pos) /*!< SCB ICSR: VECTACTIVE Mask */ + +/* SCB Vector Table Offset Register Definitions */ +#define SCB_VTOR_TBLOFF_Pos 7 /*!< SCB VTOR: TBLOFF Position */ +#define SCB_VTOR_TBLOFF_Msk (0x1FFFFFFUL << SCB_VTOR_TBLOFF_Pos) /*!< SCB VTOR: TBLOFF Mask */ + +/* SCB Application Interrupt and Reset Control Register Definitions */ +#define SCB_AIRCR_VECTKEY_Pos 16 /*!< SCB AIRCR: VECTKEY Position */ +#define SCB_AIRCR_VECTKEY_Msk (0xFFFFUL << SCB_AIRCR_VECTKEY_Pos) /*!< SCB AIRCR: VECTKEY Mask */ + +#define SCB_AIRCR_VECTKEYSTAT_Pos 16 /*!< SCB AIRCR: VECTKEYSTAT Position */ +#define SCB_AIRCR_VECTKEYSTAT_Msk (0xFFFFUL << SCB_AIRCR_VECTKEYSTAT_Pos) /*!< SCB AIRCR: VECTKEYSTAT Mask */ + +#define SCB_AIRCR_ENDIANESS_Pos 15 /*!< SCB AIRCR: ENDIANESS Position */ +#define SCB_AIRCR_ENDIANESS_Msk (1UL << SCB_AIRCR_ENDIANESS_Pos) /*!< SCB AIRCR: ENDIANESS Mask */ + +#define SCB_AIRCR_PRIGROUP_Pos 8 /*!< SCB AIRCR: PRIGROUP Position */ +#define SCB_AIRCR_PRIGROUP_Msk (7UL << SCB_AIRCR_PRIGROUP_Pos) /*!< SCB AIRCR: PRIGROUP Mask */ + +#define SCB_AIRCR_SYSRESETREQ_Pos 2 /*!< SCB AIRCR: SYSRESETREQ Position */ +#define SCB_AIRCR_SYSRESETREQ_Msk (1UL << SCB_AIRCR_SYSRESETREQ_Pos) /*!< SCB AIRCR: SYSRESETREQ Mask */ + +#define SCB_AIRCR_VECTCLRACTIVE_Pos 1 /*!< SCB AIRCR: VECTCLRACTIVE Position */ +#define SCB_AIRCR_VECTCLRACTIVE_Msk (1UL << SCB_AIRCR_VECTCLRACTIVE_Pos) /*!< SCB AIRCR: VECTCLRACTIVE Mask */ + +#define SCB_AIRCR_VECTRESET_Pos 0 /*!< SCB AIRCR: VECTRESET Position */ +#define SCB_AIRCR_VECTRESET_Msk (1UL << SCB_AIRCR_VECTRESET_Pos) /*!< SCB AIRCR: VECTRESET Mask */ + +/* SCB System Control Register Definitions */ +#define SCB_SCR_SEVONPEND_Pos 4 /*!< SCB SCR: SEVONPEND Position */ +#define SCB_SCR_SEVONPEND_Msk (1UL << SCB_SCR_SEVONPEND_Pos) /*!< SCB SCR: SEVONPEND Mask */ + +#define SCB_SCR_SLEEPDEEP_Pos 2 /*!< SCB SCR: SLEEPDEEP Position */ +#define SCB_SCR_SLEEPDEEP_Msk (1UL << SCB_SCR_SLEEPDEEP_Pos) /*!< SCB SCR: SLEEPDEEP Mask */ + +#define SCB_SCR_SLEEPONEXIT_Pos 1 /*!< SCB SCR: SLEEPONEXIT Position */ +#define SCB_SCR_SLEEPONEXIT_Msk (1UL << SCB_SCR_SLEEPONEXIT_Pos) /*!< SCB SCR: SLEEPONEXIT Mask */ + +/* SCB Configuration Control Register Definitions */ +#define SCB_CCR_STKALIGN_Pos 9 /*!< SCB CCR: STKALIGN Position */ +#define SCB_CCR_STKALIGN_Msk (1UL << SCB_CCR_STKALIGN_Pos) /*!< SCB CCR: STKALIGN Mask */ + +#define SCB_CCR_BFHFNMIGN_Pos 8 /*!< SCB CCR: BFHFNMIGN Position */ +#define SCB_CCR_BFHFNMIGN_Msk (1UL << SCB_CCR_BFHFNMIGN_Pos) /*!< SCB CCR: BFHFNMIGN Mask */ + +#define SCB_CCR_DIV_0_TRP_Pos 4 /*!< SCB CCR: DIV_0_TRP Position */ +#define SCB_CCR_DIV_0_TRP_Msk (1UL << SCB_CCR_DIV_0_TRP_Pos) /*!< SCB CCR: DIV_0_TRP Mask */ + +#define SCB_CCR_UNALIGN_TRP_Pos 3 /*!< SCB CCR: UNALIGN_TRP Position */ +#define SCB_CCR_UNALIGN_TRP_Msk (1UL << SCB_CCR_UNALIGN_TRP_Pos) /*!< SCB CCR: UNALIGN_TRP Mask */ + +#define SCB_CCR_USERSETMPEND_Pos 1 /*!< SCB CCR: USERSETMPEND Position */ +#define SCB_CCR_USERSETMPEND_Msk (1UL << SCB_CCR_USERSETMPEND_Pos) /*!< SCB CCR: USERSETMPEND Mask */ + +#define SCB_CCR_NONBASETHRDENA_Pos 0 /*!< SCB CCR: NONBASETHRDENA Position */ +#define SCB_CCR_NONBASETHRDENA_Msk (1UL << SCB_CCR_NONBASETHRDENA_Pos) /*!< SCB CCR: NONBASETHRDENA Mask */ + +/* SCB System Handler Control and State Register Definitions */ +#define SCB_SHCSR_USGFAULTENA_Pos 18 /*!< SCB SHCSR: USGFAULTENA Position */ +#define SCB_SHCSR_USGFAULTENA_Msk (1UL << SCB_SHCSR_USGFAULTENA_Pos) /*!< SCB SHCSR: USGFAULTENA Mask */ + +#define SCB_SHCSR_BUSFAULTENA_Pos 17 /*!< SCB SHCSR: BUSFAULTENA Position */ +#define SCB_SHCSR_BUSFAULTENA_Msk (1UL << SCB_SHCSR_BUSFAULTENA_Pos) /*!< SCB SHCSR: BUSFAULTENA Mask */ + +#define SCB_SHCSR_MEMFAULTENA_Pos 16 /*!< SCB SHCSR: MEMFAULTENA Position */ +#define SCB_SHCSR_MEMFAULTENA_Msk (1UL << SCB_SHCSR_MEMFAULTENA_Pos) /*!< SCB SHCSR: MEMFAULTENA Mask */ + +#define SCB_SHCSR_SVCALLPENDED_Pos 15 /*!< SCB SHCSR: SVCALLPENDED Position */ +#define SCB_SHCSR_SVCALLPENDED_Msk (1UL << SCB_SHCSR_SVCALLPENDED_Pos) /*!< SCB SHCSR: SVCALLPENDED Mask */ + +#define SCB_SHCSR_BUSFAULTPENDED_Pos 14 /*!< SCB SHCSR: BUSFAULTPENDED Position */ +#define SCB_SHCSR_BUSFAULTPENDED_Msk (1UL << SCB_SHCSR_BUSFAULTPENDED_Pos) /*!< SCB SHCSR: BUSFAULTPENDED Mask */ + +#define SCB_SHCSR_MEMFAULTPENDED_Pos 13 /*!< SCB SHCSR: MEMFAULTPENDED Position */ +#define SCB_SHCSR_MEMFAULTPENDED_Msk (1UL << SCB_SHCSR_MEMFAULTPENDED_Pos) /*!< SCB SHCSR: MEMFAULTPENDED Mask */ + +#define SCB_SHCSR_USGFAULTPENDED_Pos 12 /*!< SCB SHCSR: USGFAULTPENDED Position */ +#define SCB_SHCSR_USGFAULTPENDED_Msk (1UL << SCB_SHCSR_USGFAULTPENDED_Pos) /*!< SCB SHCSR: USGFAULTPENDED Mask */ + +#define SCB_SHCSR_SYSTICKACT_Pos 11 /*!< SCB SHCSR: SYSTICKACT Position */ +#define SCB_SHCSR_SYSTICKACT_Msk (1UL << SCB_SHCSR_SYSTICKACT_Pos) /*!< SCB SHCSR: SYSTICKACT Mask */ + +#define SCB_SHCSR_PENDSVACT_Pos 10 /*!< SCB SHCSR: PENDSVACT Position */ +#define SCB_SHCSR_PENDSVACT_Msk (1UL << SCB_SHCSR_PENDSVACT_Pos) /*!< SCB SHCSR: PENDSVACT Mask */ + +#define SCB_SHCSR_MONITORACT_Pos 8 /*!< SCB SHCSR: MONITORACT Position */ +#define SCB_SHCSR_MONITORACT_Msk (1UL << SCB_SHCSR_MONITORACT_Pos) /*!< SCB SHCSR: MONITORACT Mask */ + +#define SCB_SHCSR_SVCALLACT_Pos 7 /*!< SCB SHCSR: SVCALLACT Position */ +#define SCB_SHCSR_SVCALLACT_Msk (1UL << SCB_SHCSR_SVCALLACT_Pos) /*!< SCB SHCSR: SVCALLACT Mask */ + +#define SCB_SHCSR_USGFAULTACT_Pos 3 /*!< SCB SHCSR: USGFAULTACT Position */ +#define SCB_SHCSR_USGFAULTACT_Msk (1UL << SCB_SHCSR_USGFAULTACT_Pos) /*!< SCB SHCSR: USGFAULTACT Mask */ + +#define SCB_SHCSR_BUSFAULTACT_Pos 1 /*!< SCB SHCSR: BUSFAULTACT Position */ +#define SCB_SHCSR_BUSFAULTACT_Msk (1UL << SCB_SHCSR_BUSFAULTACT_Pos) /*!< SCB SHCSR: BUSFAULTACT Mask */ + +#define SCB_SHCSR_MEMFAULTACT_Pos 0 /*!< SCB SHCSR: MEMFAULTACT Position */ +#define SCB_SHCSR_MEMFAULTACT_Msk (1UL << SCB_SHCSR_MEMFAULTACT_Pos) /*!< SCB SHCSR: MEMFAULTACT Mask */ + +/* SCB Configurable Fault Status Registers Definitions */ +#define SCB_CFSR_USGFAULTSR_Pos 16 /*!< SCB CFSR: Usage Fault Status Register Position */ +#define SCB_CFSR_USGFAULTSR_Msk (0xFFFFUL << SCB_CFSR_USGFAULTSR_Pos) /*!< SCB CFSR: Usage Fault Status Register Mask */ + +#define SCB_CFSR_BUSFAULTSR_Pos 8 /*!< SCB CFSR: Bus Fault Status Register Position */ +#define SCB_CFSR_BUSFAULTSR_Msk (0xFFUL << SCB_CFSR_BUSFAULTSR_Pos) /*!< SCB CFSR: Bus Fault Status Register Mask */ + +#define SCB_CFSR_MEMFAULTSR_Pos 0 /*!< SCB CFSR: Memory Manage Fault Status Register Position */ +#define SCB_CFSR_MEMFAULTSR_Msk (0xFFUL << SCB_CFSR_MEMFAULTSR_Pos) /*!< SCB CFSR: Memory Manage Fault Status Register Mask */ + +/* SCB Hard Fault Status Registers Definitions */ +#define SCB_HFSR_DEBUGEVT_Pos 31 /*!< SCB HFSR: DEBUGEVT Position */ +#define SCB_HFSR_DEBUGEVT_Msk (1UL << SCB_HFSR_DEBUGEVT_Pos) /*!< SCB HFSR: DEBUGEVT Mask */ + +#define SCB_HFSR_FORCED_Pos 30 /*!< SCB HFSR: FORCED Position */ +#define SCB_HFSR_FORCED_Msk (1UL << SCB_HFSR_FORCED_Pos) /*!< SCB HFSR: FORCED Mask */ + +#define SCB_HFSR_VECTTBL_Pos 1 /*!< SCB HFSR: VECTTBL Position */ +#define SCB_HFSR_VECTTBL_Msk (1UL << SCB_HFSR_VECTTBL_Pos) /*!< SCB HFSR: VECTTBL Mask */ + +/* SCB Debug Fault Status Register Definitions */ +#define SCB_DFSR_EXTERNAL_Pos 4 /*!< SCB DFSR: EXTERNAL Position */ +#define SCB_DFSR_EXTERNAL_Msk (1UL << SCB_DFSR_EXTERNAL_Pos) /*!< SCB DFSR: EXTERNAL Mask */ + +#define SCB_DFSR_VCATCH_Pos 3 /*!< SCB DFSR: VCATCH Position */ +#define SCB_DFSR_VCATCH_Msk (1UL << SCB_DFSR_VCATCH_Pos) /*!< SCB DFSR: VCATCH Mask */ + +#define SCB_DFSR_DWTTRAP_Pos 2 /*!< SCB DFSR: DWTTRAP Position */ +#define SCB_DFSR_DWTTRAP_Msk (1UL << SCB_DFSR_DWTTRAP_Pos) /*!< SCB DFSR: DWTTRAP Mask */ + +#define SCB_DFSR_BKPT_Pos 1 /*!< SCB DFSR: BKPT Position */ +#define SCB_DFSR_BKPT_Msk (1UL << SCB_DFSR_BKPT_Pos) /*!< SCB DFSR: BKPT Mask */ + +#define SCB_DFSR_HALTED_Pos 0 /*!< SCB DFSR: HALTED Position */ +#define SCB_DFSR_HALTED_Msk (1UL << SCB_DFSR_HALTED_Pos) /*!< SCB DFSR: HALTED Mask */ + +/*@} end of group CMSIS_SCB */ + + +/** \ingroup CMSIS_core_register + \defgroup CMSIS_SCnSCB System Controls not in SCB (SCnSCB) + \brief Type definitions for the System Control and ID Register not in the SCB + @{ + */ + +/** \brief Structure type to access the System Control and ID Register not in the SCB. + */ +typedef struct +{ + uint32_t RESERVED0[1]; + __I uint32_t ICTR; /*!< Offset: 0x004 (R/ ) Interrupt Controller Type Register */ + __IO uint32_t ACTLR; /*!< Offset: 0x008 (R/W) Auxiliary Control Register */ +} SCnSCB_Type; + +/* Interrupt Controller Type Register Definitions */ +#define SCnSCB_ICTR_INTLINESNUM_Pos 0 /*!< ICTR: INTLINESNUM Position */ +#define SCnSCB_ICTR_INTLINESNUM_Msk (0xFUL << SCnSCB_ICTR_INTLINESNUM_Pos) /*!< ICTR: INTLINESNUM Mask */ + +/* Auxiliary Control Register Definitions */ +#define SCnSCB_ACTLR_DISOOFP_Pos 9 /*!< ACTLR: DISOOFP Position */ +#define SCnSCB_ACTLR_DISOOFP_Msk (1UL << SCnSCB_ACTLR_DISOOFP_Pos) /*!< ACTLR: DISOOFP Mask */ + +#define SCnSCB_ACTLR_DISFPCA_Pos 8 /*!< ACTLR: DISFPCA Position */ +#define SCnSCB_ACTLR_DISFPCA_Msk (1UL << SCnSCB_ACTLR_DISFPCA_Pos) /*!< ACTLR: DISFPCA Mask */ + +#define SCnSCB_ACTLR_DISFOLD_Pos 2 /*!< ACTLR: DISFOLD Position */ +#define SCnSCB_ACTLR_DISFOLD_Msk (1UL << SCnSCB_ACTLR_DISFOLD_Pos) /*!< ACTLR: DISFOLD Mask */ + +#define SCnSCB_ACTLR_DISDEFWBUF_Pos 1 /*!< ACTLR: DISDEFWBUF Position */ +#define SCnSCB_ACTLR_DISDEFWBUF_Msk (1UL << SCnSCB_ACTLR_DISDEFWBUF_Pos) /*!< ACTLR: DISDEFWBUF Mask */ + +#define SCnSCB_ACTLR_DISMCYCINT_Pos 0 /*!< ACTLR: DISMCYCINT Position */ +#define SCnSCB_ACTLR_DISMCYCINT_Msk (1UL << SCnSCB_ACTLR_DISMCYCINT_Pos) /*!< ACTLR: DISMCYCINT Mask */ + +/*@} end of group CMSIS_SCnotSCB */ + + +/** \ingroup CMSIS_core_register + \defgroup CMSIS_SysTick System Tick Timer (SysTick) + \brief Type definitions for the System Timer Registers. + @{ + */ + +/** \brief Structure type to access the System Timer (SysTick). + */ +typedef struct +{ + __IO uint32_t CTRL; /*!< Offset: 0x000 (R/W) SysTick Control and Status Register */ + __IO uint32_t LOAD; /*!< Offset: 0x004 (R/W) SysTick Reload Value Register */ + __IO uint32_t VAL; /*!< Offset: 0x008 (R/W) SysTick Current Value Register */ + __I uint32_t CALIB; /*!< Offset: 0x00C (R/ ) SysTick Calibration Register */ +} SysTick_Type; + +/* SysTick Control / Status Register Definitions */ +#define SysTick_CTRL_COUNTFLAG_Pos 16 /*!< SysTick CTRL: COUNTFLAG Position */ +#define SysTick_CTRL_COUNTFLAG_Msk (1UL << SysTick_CTRL_COUNTFLAG_Pos) /*!< SysTick CTRL: COUNTFLAG Mask */ + +#define SysTick_CTRL_CLKSOURCE_Pos 2 /*!< SysTick CTRL: CLKSOURCE Position */ +#define SysTick_CTRL_CLKSOURCE_Msk (1UL << SysTick_CTRL_CLKSOURCE_Pos) /*!< SysTick CTRL: CLKSOURCE Mask */ + +#define SysTick_CTRL_TICKINT_Pos 1 /*!< SysTick CTRL: TICKINT Position */ +#define SysTick_CTRL_TICKINT_Msk (1UL << SysTick_CTRL_TICKINT_Pos) /*!< SysTick CTRL: TICKINT Mask */ + +#define SysTick_CTRL_ENABLE_Pos 0 /*!< SysTick CTRL: ENABLE Position */ +#define SysTick_CTRL_ENABLE_Msk (1UL << SysTick_CTRL_ENABLE_Pos) /*!< SysTick CTRL: ENABLE Mask */ + +/* SysTick Reload Register Definitions */ +#define SysTick_LOAD_RELOAD_Pos 0 /*!< SysTick LOAD: RELOAD Position */ +#define SysTick_LOAD_RELOAD_Msk (0xFFFFFFUL << SysTick_LOAD_RELOAD_Pos) /*!< SysTick LOAD: RELOAD Mask */ + +/* SysTick Current Register Definitions */ +#define SysTick_VAL_CURRENT_Pos 0 /*!< SysTick VAL: CURRENT Position */ +#define SysTick_VAL_CURRENT_Msk (0xFFFFFFUL << SysTick_VAL_CURRENT_Pos) /*!< SysTick VAL: CURRENT Mask */ + +/* SysTick Calibration Register Definitions */ +#define SysTick_CALIB_NOREF_Pos 31 /*!< SysTick CALIB: NOREF Position */ +#define SysTick_CALIB_NOREF_Msk (1UL << SysTick_CALIB_NOREF_Pos) /*!< SysTick CALIB: NOREF Mask */ + +#define SysTick_CALIB_SKEW_Pos 30 /*!< SysTick CALIB: SKEW Position */ +#define SysTick_CALIB_SKEW_Msk (1UL << SysTick_CALIB_SKEW_Pos) /*!< SysTick CALIB: SKEW Mask */ + +#define SysTick_CALIB_TENMS_Pos 0 /*!< SysTick CALIB: TENMS Position */ +#define SysTick_CALIB_TENMS_Msk (0xFFFFFFUL << SysTick_VAL_CURRENT_Pos) /*!< SysTick CALIB: TENMS Mask */ + +/*@} end of group CMSIS_SysTick */ + + +/** \ingroup CMSIS_core_register + \defgroup CMSIS_ITM Instrumentation Trace Macrocell (ITM) + \brief Type definitions for the Instrumentation Trace Macrocell (ITM) + @{ + */ + +/** \brief Structure type to access the Instrumentation Trace Macrocell Register (ITM). + */ +typedef struct +{ + __O union + { + __O uint8_t u8; /*!< Offset: 0x000 ( /W) ITM Stimulus Port 8-bit */ + __O uint16_t u16; /*!< Offset: 0x000 ( /W) ITM Stimulus Port 16-bit */ + __O uint32_t u32; /*!< Offset: 0x000 ( /W) ITM Stimulus Port 32-bit */ + } PORT [32]; /*!< Offset: 0x000 ( /W) ITM Stimulus Port Registers */ + uint32_t RESERVED0[864]; + __IO uint32_t TER; /*!< Offset: 0xE00 (R/W) ITM Trace Enable Register */ + uint32_t RESERVED1[15]; + __IO uint32_t TPR; /*!< Offset: 0xE40 (R/W) ITM Trace Privilege Register */ + uint32_t RESERVED2[15]; + __IO uint32_t TCR; /*!< Offset: 0xE80 (R/W) ITM Trace Control Register */ + uint32_t RESERVED3[29]; + __O uint32_t IWR; /*!< Offset: 0xEF8 ( /W) ITM Integration Write Register */ + __I uint32_t IRR; /*!< Offset: 0xEFC (R/ ) ITM Integration Read Register */ + __IO uint32_t IMCR; /*!< Offset: 0xF00 (R/W) ITM Integration Mode Control Register */ + uint32_t RESERVED4[43]; + __O uint32_t LAR; /*!< Offset: 0xFB0 ( /W) ITM Lock Access Register */ + __I uint32_t LSR; /*!< Offset: 0xFB4 (R/ ) ITM Lock Status Register */ + uint32_t RESERVED5[6]; + __I uint32_t PID4; /*!< Offset: 0xFD0 (R/ ) ITM Peripheral Identification Register #4 */ + __I uint32_t PID5; /*!< Offset: 0xFD4 (R/ ) ITM Peripheral Identification Register #5 */ + __I uint32_t PID6; /*!< Offset: 0xFD8 (R/ ) ITM Peripheral Identification Register #6 */ + __I uint32_t PID7; /*!< Offset: 0xFDC (R/ ) ITM Peripheral Identification Register #7 */ + __I uint32_t PID0; /*!< Offset: 0xFE0 (R/ ) ITM Peripheral Identification Register #0 */ + __I uint32_t PID1; /*!< Offset: 0xFE4 (R/ ) ITM Peripheral Identification Register #1 */ + __I uint32_t PID2; /*!< Offset: 0xFE8 (R/ ) ITM Peripheral Identification Register #2 */ + __I uint32_t PID3; /*!< Offset: 0xFEC (R/ ) ITM Peripheral Identification Register #3 */ + __I uint32_t CID0; /*!< Offset: 0xFF0 (R/ ) ITM Component Identification Register #0 */ + __I uint32_t CID1; /*!< Offset: 0xFF4 (R/ ) ITM Component Identification Register #1 */ + __I uint32_t CID2; /*!< Offset: 0xFF8 (R/ ) ITM Component Identification Register #2 */ + __I uint32_t CID3; /*!< Offset: 0xFFC (R/ ) ITM Component Identification Register #3 */ +} ITM_Type; + +/* ITM Trace Privilege Register Definitions */ +#define ITM_TPR_PRIVMASK_Pos 0 /*!< ITM TPR: PRIVMASK Position */ +#define ITM_TPR_PRIVMASK_Msk (0xFUL << ITM_TPR_PRIVMASK_Pos) /*!< ITM TPR: PRIVMASK Mask */ + +/* ITM Trace Control Register Definitions */ +#define ITM_TCR_BUSY_Pos 23 /*!< ITM TCR: BUSY Position */ +#define ITM_TCR_BUSY_Msk (1UL << ITM_TCR_BUSY_Pos) /*!< ITM TCR: BUSY Mask */ + +#define ITM_TCR_TraceBusID_Pos 16 /*!< ITM TCR: ATBID Position */ +#define ITM_TCR_TraceBusID_Msk (0x7FUL << ITM_TCR_TraceBusID_Pos) /*!< ITM TCR: ATBID Mask */ + +#define ITM_TCR_GTSFREQ_Pos 10 /*!< ITM TCR: Global timestamp frequency Position */ +#define ITM_TCR_GTSFREQ_Msk (3UL << ITM_TCR_GTSFREQ_Pos) /*!< ITM TCR: Global timestamp frequency Mask */ + +#define ITM_TCR_TSPrescale_Pos 8 /*!< ITM TCR: TSPrescale Position */ +#define ITM_TCR_TSPrescale_Msk (3UL << ITM_TCR_TSPrescale_Pos) /*!< ITM TCR: TSPrescale Mask */ + +#define ITM_TCR_SWOENA_Pos 4 /*!< ITM TCR: SWOENA Position */ +#define ITM_TCR_SWOENA_Msk (1UL << ITM_TCR_SWOENA_Pos) /*!< ITM TCR: SWOENA Mask */ + +#define ITM_TCR_DWTENA_Pos 3 /*!< ITM TCR: DWTENA Position */ +#define ITM_TCR_DWTENA_Msk (1UL << ITM_TCR_DWTENA_Pos) /*!< ITM TCR: DWTENA Mask */ + +#define ITM_TCR_SYNCENA_Pos 2 /*!< ITM TCR: SYNCENA Position */ +#define ITM_TCR_SYNCENA_Msk (1UL << ITM_TCR_SYNCENA_Pos) /*!< ITM TCR: SYNCENA Mask */ + +#define ITM_TCR_TSENA_Pos 1 /*!< ITM TCR: TSENA Position */ +#define ITM_TCR_TSENA_Msk (1UL << ITM_TCR_TSENA_Pos) /*!< ITM TCR: TSENA Mask */ + +#define ITM_TCR_ITMENA_Pos 0 /*!< ITM TCR: ITM Enable bit Position */ +#define ITM_TCR_ITMENA_Msk (1UL << ITM_TCR_ITMENA_Pos) /*!< ITM TCR: ITM Enable bit Mask */ + +/* ITM Integration Write Register Definitions */ +#define ITM_IWR_ATVALIDM_Pos 0 /*!< ITM IWR: ATVALIDM Position */ +#define ITM_IWR_ATVALIDM_Msk (1UL << ITM_IWR_ATVALIDM_Pos) /*!< ITM IWR: ATVALIDM Mask */ + +/* ITM Integration Read Register Definitions */ +#define ITM_IRR_ATREADYM_Pos 0 /*!< ITM IRR: ATREADYM Position */ +#define ITM_IRR_ATREADYM_Msk (1UL << ITM_IRR_ATREADYM_Pos) /*!< ITM IRR: ATREADYM Mask */ + +/* ITM Integration Mode Control Register Definitions */ +#define ITM_IMCR_INTEGRATION_Pos 0 /*!< ITM IMCR: INTEGRATION Position */ +#define ITM_IMCR_INTEGRATION_Msk (1UL << ITM_IMCR_INTEGRATION_Pos) /*!< ITM IMCR: INTEGRATION Mask */ + +/* ITM Lock Status Register Definitions */ +#define ITM_LSR_ByteAcc_Pos 2 /*!< ITM LSR: ByteAcc Position */ +#define ITM_LSR_ByteAcc_Msk (1UL << ITM_LSR_ByteAcc_Pos) /*!< ITM LSR: ByteAcc Mask */ + +#define ITM_LSR_Access_Pos 1 /*!< ITM LSR: Access Position */ +#define ITM_LSR_Access_Msk (1UL << ITM_LSR_Access_Pos) /*!< ITM LSR: Access Mask */ + +#define ITM_LSR_Present_Pos 0 /*!< ITM LSR: Present Position */ +#define ITM_LSR_Present_Msk (1UL << ITM_LSR_Present_Pos) /*!< ITM LSR: Present Mask */ + +/*@}*/ /* end of group CMSIS_ITM */ + + +/** \ingroup CMSIS_core_register + \defgroup CMSIS_DWT Data Watchpoint and Trace (DWT) + \brief Type definitions for the Data Watchpoint and Trace (DWT) + @{ + */ + +/** \brief Structure type to access the Data Watchpoint and Trace Register (DWT). + */ +typedef struct +{ + __IO uint32_t CTRL; /*!< Offset: 0x000 (R/W) Control Register */ + __IO uint32_t CYCCNT; /*!< Offset: 0x004 (R/W) Cycle Count Register */ + __IO uint32_t CPICNT; /*!< Offset: 0x008 (R/W) CPI Count Register */ + __IO uint32_t EXCCNT; /*!< Offset: 0x00C (R/W) Exception Overhead Count Register */ + __IO uint32_t SLEEPCNT; /*!< Offset: 0x010 (R/W) Sleep Count Register */ + __IO uint32_t LSUCNT; /*!< Offset: 0x014 (R/W) LSU Count Register */ + __IO uint32_t FOLDCNT; /*!< Offset: 0x018 (R/W) Folded-instruction Count Register */ + __I uint32_t PCSR; /*!< Offset: 0x01C (R/ ) Program Counter Sample Register */ + __IO uint32_t COMP0; /*!< Offset: 0x020 (R/W) Comparator Register 0 */ + __IO uint32_t MASK0; /*!< Offset: 0x024 (R/W) Mask Register 0 */ + __IO uint32_t FUNCTION0; /*!< Offset: 0x028 (R/W) Function Register 0 */ + uint32_t RESERVED0[1]; + __IO uint32_t COMP1; /*!< Offset: 0x030 (R/W) Comparator Register 1 */ + __IO uint32_t MASK1; /*!< Offset: 0x034 (R/W) Mask Register 1 */ + __IO uint32_t FUNCTION1; /*!< Offset: 0x038 (R/W) Function Register 1 */ + uint32_t RESERVED1[1]; + __IO uint32_t COMP2; /*!< Offset: 0x040 (R/W) Comparator Register 2 */ + __IO uint32_t MASK2; /*!< Offset: 0x044 (R/W) Mask Register 2 */ + __IO uint32_t FUNCTION2; /*!< Offset: 0x048 (R/W) Function Register 2 */ + uint32_t RESERVED2[1]; + __IO uint32_t COMP3; /*!< Offset: 0x050 (R/W) Comparator Register 3 */ + __IO uint32_t MASK3; /*!< Offset: 0x054 (R/W) Mask Register 3 */ + __IO uint32_t FUNCTION3; /*!< Offset: 0x058 (R/W) Function Register 3 */ +} DWT_Type; + +/* DWT Control Register Definitions */ +#define DWT_CTRL_NUMCOMP_Pos 28 /*!< DWT CTRL: NUMCOMP Position */ +#define DWT_CTRL_NUMCOMP_Msk (0xFUL << DWT_CTRL_NUMCOMP_Pos) /*!< DWT CTRL: NUMCOMP Mask */ + +#define DWT_CTRL_NOTRCPKT_Pos 27 /*!< DWT CTRL: NOTRCPKT Position */ +#define DWT_CTRL_NOTRCPKT_Msk (0x1UL << DWT_CTRL_NOTRCPKT_Pos) /*!< DWT CTRL: NOTRCPKT Mask */ + +#define DWT_CTRL_NOEXTTRIG_Pos 26 /*!< DWT CTRL: NOEXTTRIG Position */ +#define DWT_CTRL_NOEXTTRIG_Msk (0x1UL << DWT_CTRL_NOEXTTRIG_Pos) /*!< DWT CTRL: NOEXTTRIG Mask */ + +#define DWT_CTRL_NOCYCCNT_Pos 25 /*!< DWT CTRL: NOCYCCNT Position */ +#define DWT_CTRL_NOCYCCNT_Msk (0x1UL << DWT_CTRL_NOCYCCNT_Pos) /*!< DWT CTRL: NOCYCCNT Mask */ + +#define DWT_CTRL_NOPRFCNT_Pos 24 /*!< DWT CTRL: NOPRFCNT Position */ +#define DWT_CTRL_NOPRFCNT_Msk (0x1UL << DWT_CTRL_NOPRFCNT_Pos) /*!< DWT CTRL: NOPRFCNT Mask */ + +#define DWT_CTRL_CYCEVTENA_Pos 22 /*!< DWT CTRL: CYCEVTENA Position */ +#define DWT_CTRL_CYCEVTENA_Msk (0x1UL << DWT_CTRL_CYCEVTENA_Pos) /*!< DWT CTRL: CYCEVTENA Mask */ + +#define DWT_CTRL_FOLDEVTENA_Pos 21 /*!< DWT CTRL: FOLDEVTENA Position */ +#define DWT_CTRL_FOLDEVTENA_Msk (0x1UL << DWT_CTRL_FOLDEVTENA_Pos) /*!< DWT CTRL: FOLDEVTENA Mask */ + +#define DWT_CTRL_LSUEVTENA_Pos 20 /*!< DWT CTRL: LSUEVTENA Position */ +#define DWT_CTRL_LSUEVTENA_Msk (0x1UL << DWT_CTRL_LSUEVTENA_Pos) /*!< DWT CTRL: LSUEVTENA Mask */ + +#define DWT_CTRL_SLEEPEVTENA_Pos 19 /*!< DWT CTRL: SLEEPEVTENA Position */ +#define DWT_CTRL_SLEEPEVTENA_Msk (0x1UL << DWT_CTRL_SLEEPEVTENA_Pos) /*!< DWT CTRL: SLEEPEVTENA Mask */ + +#define DWT_CTRL_EXCEVTENA_Pos 18 /*!< DWT CTRL: EXCEVTENA Position */ +#define DWT_CTRL_EXCEVTENA_Msk (0x1UL << DWT_CTRL_EXCEVTENA_Pos) /*!< DWT CTRL: EXCEVTENA Mask */ + +#define DWT_CTRL_CPIEVTENA_Pos 17 /*!< DWT CTRL: CPIEVTENA Position */ +#define DWT_CTRL_CPIEVTENA_Msk (0x1UL << DWT_CTRL_CPIEVTENA_Pos) /*!< DWT CTRL: CPIEVTENA Mask */ + +#define DWT_CTRL_EXCTRCENA_Pos 16 /*!< DWT CTRL: EXCTRCENA Position */ +#define DWT_CTRL_EXCTRCENA_Msk (0x1UL << DWT_CTRL_EXCTRCENA_Pos) /*!< DWT CTRL: EXCTRCENA Mask */ + +#define DWT_CTRL_PCSAMPLENA_Pos 12 /*!< DWT CTRL: PCSAMPLENA Position */ +#define DWT_CTRL_PCSAMPLENA_Msk (0x1UL << DWT_CTRL_PCSAMPLENA_Pos) /*!< DWT CTRL: PCSAMPLENA Mask */ + +#define DWT_CTRL_SYNCTAP_Pos 10 /*!< DWT CTRL: SYNCTAP Position */ +#define DWT_CTRL_SYNCTAP_Msk (0x3UL << DWT_CTRL_SYNCTAP_Pos) /*!< DWT CTRL: SYNCTAP Mask */ + +#define DWT_CTRL_CYCTAP_Pos 9 /*!< DWT CTRL: CYCTAP Position */ +#define DWT_CTRL_CYCTAP_Msk (0x1UL << DWT_CTRL_CYCTAP_Pos) /*!< DWT CTRL: CYCTAP Mask */ + +#define DWT_CTRL_POSTINIT_Pos 5 /*!< DWT CTRL: POSTINIT Position */ +#define DWT_CTRL_POSTINIT_Msk (0xFUL << DWT_CTRL_POSTINIT_Pos) /*!< DWT CTRL: POSTINIT Mask */ + +#define DWT_CTRL_POSTPRESET_Pos 1 /*!< DWT CTRL: POSTPRESET Position */ +#define DWT_CTRL_POSTPRESET_Msk (0xFUL << DWT_CTRL_POSTPRESET_Pos) /*!< DWT CTRL: POSTPRESET Mask */ + +#define DWT_CTRL_CYCCNTENA_Pos 0 /*!< DWT CTRL: CYCCNTENA Position */ +#define DWT_CTRL_CYCCNTENA_Msk (0x1UL << DWT_CTRL_CYCCNTENA_Pos) /*!< DWT CTRL: CYCCNTENA Mask */ + +/* DWT CPI Count Register Definitions */ +#define DWT_CPICNT_CPICNT_Pos 0 /*!< DWT CPICNT: CPICNT Position */ +#define DWT_CPICNT_CPICNT_Msk (0xFFUL << DWT_CPICNT_CPICNT_Pos) /*!< DWT CPICNT: CPICNT Mask */ + +/* DWT Exception Overhead Count Register Definitions */ +#define DWT_EXCCNT_EXCCNT_Pos 0 /*!< DWT EXCCNT: EXCCNT Position */ +#define DWT_EXCCNT_EXCCNT_Msk (0xFFUL << DWT_EXCCNT_EXCCNT_Pos) /*!< DWT EXCCNT: EXCCNT Mask */ + +/* DWT Sleep Count Register Definitions */ +#define DWT_SLEEPCNT_SLEEPCNT_Pos 0 /*!< DWT SLEEPCNT: SLEEPCNT Position */ +#define DWT_SLEEPCNT_SLEEPCNT_Msk (0xFFUL << DWT_SLEEPCNT_SLEEPCNT_Pos) /*!< DWT SLEEPCNT: SLEEPCNT Mask */ + +/* DWT LSU Count Register Definitions */ +#define DWT_LSUCNT_LSUCNT_Pos 0 /*!< DWT LSUCNT: LSUCNT Position */ +#define DWT_LSUCNT_LSUCNT_Msk (0xFFUL << DWT_LSUCNT_LSUCNT_Pos) /*!< DWT LSUCNT: LSUCNT Mask */ + +/* DWT Folded-instruction Count Register Definitions */ +#define DWT_FOLDCNT_FOLDCNT_Pos 0 /*!< DWT FOLDCNT: FOLDCNT Position */ +#define DWT_FOLDCNT_FOLDCNT_Msk (0xFFUL << DWT_FOLDCNT_FOLDCNT_Pos) /*!< DWT FOLDCNT: FOLDCNT Mask */ + +/* DWT Comparator Mask Register Definitions */ +#define DWT_MASK_MASK_Pos 0 /*!< DWT MASK: MASK Position */ +#define DWT_MASK_MASK_Msk (0x1FUL << DWT_MASK_MASK_Pos) /*!< DWT MASK: MASK Mask */ + +/* DWT Comparator Function Register Definitions */ +#define DWT_FUNCTION_MATCHED_Pos 24 /*!< DWT FUNCTION: MATCHED Position */ +#define DWT_FUNCTION_MATCHED_Msk (0x1UL << DWT_FUNCTION_MATCHED_Pos) /*!< DWT FUNCTION: MATCHED Mask */ + +#define DWT_FUNCTION_DATAVADDR1_Pos 16 /*!< DWT FUNCTION: DATAVADDR1 Position */ +#define DWT_FUNCTION_DATAVADDR1_Msk (0xFUL << DWT_FUNCTION_DATAVADDR1_Pos) /*!< DWT FUNCTION: DATAVADDR1 Mask */ + +#define DWT_FUNCTION_DATAVADDR0_Pos 12 /*!< DWT FUNCTION: DATAVADDR0 Position */ +#define DWT_FUNCTION_DATAVADDR0_Msk (0xFUL << DWT_FUNCTION_DATAVADDR0_Pos) /*!< DWT FUNCTION: DATAVADDR0 Mask */ + +#define DWT_FUNCTION_DATAVSIZE_Pos 10 /*!< DWT FUNCTION: DATAVSIZE Position */ +#define DWT_FUNCTION_DATAVSIZE_Msk (0x3UL << DWT_FUNCTION_DATAVSIZE_Pos) /*!< DWT FUNCTION: DATAVSIZE Mask */ + +#define DWT_FUNCTION_LNK1ENA_Pos 9 /*!< DWT FUNCTION: LNK1ENA Position */ +#define DWT_FUNCTION_LNK1ENA_Msk (0x1UL << DWT_FUNCTION_LNK1ENA_Pos) /*!< DWT FUNCTION: LNK1ENA Mask */ + +#define DWT_FUNCTION_DATAVMATCH_Pos 8 /*!< DWT FUNCTION: DATAVMATCH Position */ +#define DWT_FUNCTION_DATAVMATCH_Msk (0x1UL << DWT_FUNCTION_DATAVMATCH_Pos) /*!< DWT FUNCTION: DATAVMATCH Mask */ + +#define DWT_FUNCTION_CYCMATCH_Pos 7 /*!< DWT FUNCTION: CYCMATCH Position */ +#define DWT_FUNCTION_CYCMATCH_Msk (0x1UL << DWT_FUNCTION_CYCMATCH_Pos) /*!< DWT FUNCTION: CYCMATCH Mask */ + +#define DWT_FUNCTION_EMITRANGE_Pos 5 /*!< DWT FUNCTION: EMITRANGE Position */ +#define DWT_FUNCTION_EMITRANGE_Msk (0x1UL << DWT_FUNCTION_EMITRANGE_Pos) /*!< DWT FUNCTION: EMITRANGE Mask */ + +#define DWT_FUNCTION_FUNCTION_Pos 0 /*!< DWT FUNCTION: FUNCTION Position */ +#define DWT_FUNCTION_FUNCTION_Msk (0xFUL << DWT_FUNCTION_FUNCTION_Pos) /*!< DWT FUNCTION: FUNCTION Mask */ + +/*@}*/ /* end of group CMSIS_DWT */ + + +/** \ingroup CMSIS_core_register + \defgroup CMSIS_TPI Trace Port Interface (TPI) + \brief Type definitions for the Trace Port Interface (TPI) + @{ + */ + +/** \brief Structure type to access the Trace Port Interface Register (TPI). + */ +typedef struct +{ + __IO uint32_t SSPSR; /*!< Offset: 0x000 (R/ ) Supported Parallel Port Size Register */ + __IO uint32_t CSPSR; /*!< Offset: 0x004 (R/W) Current Parallel Port Size Register */ + uint32_t RESERVED0[2]; + __IO uint32_t ACPR; /*!< Offset: 0x010 (R/W) Asynchronous Clock Prescaler Register */ + uint32_t RESERVED1[55]; + __IO uint32_t SPPR; /*!< Offset: 0x0F0 (R/W) Selected Pin Protocol Register */ + uint32_t RESERVED2[131]; + __I uint32_t FFSR; /*!< Offset: 0x300 (R/ ) Formatter and Flush Status Register */ + __IO uint32_t FFCR; /*!< Offset: 0x304 (R/W) Formatter and Flush Control Register */ + __I uint32_t FSCR; /*!< Offset: 0x308 (R/ ) Formatter Synchronization Counter Register */ + uint32_t RESERVED3[759]; + __I uint32_t TRIGGER; /*!< Offset: 0xEE8 (R/ ) TRIGGER */ + __I uint32_t FIFO0; /*!< Offset: 0xEEC (R/ ) Integration ETM Data */ + __I uint32_t ITATBCTR2; /*!< Offset: 0xEF0 (R/ ) ITATBCTR2 */ + uint32_t RESERVED4[1]; + __I uint32_t ITATBCTR0; /*!< Offset: 0xEF8 (R/ ) ITATBCTR0 */ + __I uint32_t FIFO1; /*!< Offset: 0xEFC (R/ ) Integration ITM Data */ + __IO uint32_t ITCTRL; /*!< Offset: 0xF00 (R/W) Integration Mode Control */ + uint32_t RESERVED5[39]; + __IO uint32_t CLAIMSET; /*!< Offset: 0xFA0 (R/W) Claim tag set */ + __IO uint32_t CLAIMCLR; /*!< Offset: 0xFA4 (R/W) Claim tag clear */ + uint32_t RESERVED7[8]; + __I uint32_t DEVID; /*!< Offset: 0xFC8 (R/ ) TPIU_DEVID */ + __I uint32_t DEVTYPE; /*!< Offset: 0xFCC (R/ ) TPIU_DEVTYPE */ +} TPI_Type; + +/* TPI Asynchronous Clock Prescaler Register Definitions */ +#define TPI_ACPR_PRESCALER_Pos 0 /*!< TPI ACPR: PRESCALER Position */ +#define TPI_ACPR_PRESCALER_Msk (0x1FFFUL << TPI_ACPR_PRESCALER_Pos) /*!< TPI ACPR: PRESCALER Mask */ + +/* TPI Selected Pin Protocol Register Definitions */ +#define TPI_SPPR_TXMODE_Pos 0 /*!< TPI SPPR: TXMODE Position */ +#define TPI_SPPR_TXMODE_Msk (0x3UL << TPI_SPPR_TXMODE_Pos) /*!< TPI SPPR: TXMODE Mask */ + +/* TPI Formatter and Flush Status Register Definitions */ +#define TPI_FFSR_FtNonStop_Pos 3 /*!< TPI FFSR: FtNonStop Position */ +#define TPI_FFSR_FtNonStop_Msk (0x1UL << TPI_FFSR_FtNonStop_Pos) /*!< TPI FFSR: FtNonStop Mask */ + +#define TPI_FFSR_TCPresent_Pos 2 /*!< TPI FFSR: TCPresent Position */ +#define TPI_FFSR_TCPresent_Msk (0x1UL << TPI_FFSR_TCPresent_Pos) /*!< TPI FFSR: TCPresent Mask */ + +#define TPI_FFSR_FtStopped_Pos 1 /*!< TPI FFSR: FtStopped Position */ +#define TPI_FFSR_FtStopped_Msk (0x1UL << TPI_FFSR_FtStopped_Pos) /*!< TPI FFSR: FtStopped Mask */ + +#define TPI_FFSR_FlInProg_Pos 0 /*!< TPI FFSR: FlInProg Position */ +#define TPI_FFSR_FlInProg_Msk (0x1UL << TPI_FFSR_FlInProg_Pos) /*!< TPI FFSR: FlInProg Mask */ + +/* TPI Formatter and Flush Control Register Definitions */ +#define TPI_FFCR_TrigIn_Pos 8 /*!< TPI FFCR: TrigIn Position */ +#define TPI_FFCR_TrigIn_Msk (0x1UL << TPI_FFCR_TrigIn_Pos) /*!< TPI FFCR: TrigIn Mask */ + +#define TPI_FFCR_EnFCont_Pos 1 /*!< TPI FFCR: EnFCont Position */ +#define TPI_FFCR_EnFCont_Msk (0x1UL << TPI_FFCR_EnFCont_Pos) /*!< TPI FFCR: EnFCont Mask */ + +/* TPI TRIGGER Register Definitions */ +#define TPI_TRIGGER_TRIGGER_Pos 0 /*!< TPI TRIGGER: TRIGGER Position */ +#define TPI_TRIGGER_TRIGGER_Msk (0x1UL << TPI_TRIGGER_TRIGGER_Pos) /*!< TPI TRIGGER: TRIGGER Mask */ + +/* TPI Integration ETM Data Register Definitions (FIFO0) */ +#define TPI_FIFO0_ITM_ATVALID_Pos 29 /*!< TPI FIFO0: ITM_ATVALID Position */ +#define TPI_FIFO0_ITM_ATVALID_Msk (0x3UL << TPI_FIFO0_ITM_ATVALID_Pos) /*!< TPI FIFO0: ITM_ATVALID Mask */ + +#define TPI_FIFO0_ITM_bytecount_Pos 27 /*!< TPI FIFO0: ITM_bytecount Position */ +#define TPI_FIFO0_ITM_bytecount_Msk (0x3UL << TPI_FIFO0_ITM_bytecount_Pos) /*!< TPI FIFO0: ITM_bytecount Mask */ + +#define TPI_FIFO0_ETM_ATVALID_Pos 26 /*!< TPI FIFO0: ETM_ATVALID Position */ +#define TPI_FIFO0_ETM_ATVALID_Msk (0x3UL << TPI_FIFO0_ETM_ATVALID_Pos) /*!< TPI FIFO0: ETM_ATVALID Mask */ + +#define TPI_FIFO0_ETM_bytecount_Pos 24 /*!< TPI FIFO0: ETM_bytecount Position */ +#define TPI_FIFO0_ETM_bytecount_Msk (0x3UL << TPI_FIFO0_ETM_bytecount_Pos) /*!< TPI FIFO0: ETM_bytecount Mask */ + +#define TPI_FIFO0_ETM2_Pos 16 /*!< TPI FIFO0: ETM2 Position */ +#define TPI_FIFO0_ETM2_Msk (0xFFUL << TPI_FIFO0_ETM2_Pos) /*!< TPI FIFO0: ETM2 Mask */ + +#define TPI_FIFO0_ETM1_Pos 8 /*!< TPI FIFO0: ETM1 Position */ +#define TPI_FIFO0_ETM1_Msk (0xFFUL << TPI_FIFO0_ETM1_Pos) /*!< TPI FIFO0: ETM1 Mask */ + +#define TPI_FIFO0_ETM0_Pos 0 /*!< TPI FIFO0: ETM0 Position */ +#define TPI_FIFO0_ETM0_Msk (0xFFUL << TPI_FIFO0_ETM0_Pos) /*!< TPI FIFO0: ETM0 Mask */ + +/* TPI ITATBCTR2 Register Definitions */ +#define TPI_ITATBCTR2_ATREADY_Pos 0 /*!< TPI ITATBCTR2: ATREADY Position */ +#define TPI_ITATBCTR2_ATREADY_Msk (0x1UL << TPI_ITATBCTR2_ATREADY_Pos) /*!< TPI ITATBCTR2: ATREADY Mask */ + +/* TPI Integration ITM Data Register Definitions (FIFO1) */ +#define TPI_FIFO1_ITM_ATVALID_Pos 29 /*!< TPI FIFO1: ITM_ATVALID Position */ +#define TPI_FIFO1_ITM_ATVALID_Msk (0x3UL << TPI_FIFO1_ITM_ATVALID_Pos) /*!< TPI FIFO1: ITM_ATVALID Mask */ + +#define TPI_FIFO1_ITM_bytecount_Pos 27 /*!< TPI FIFO1: ITM_bytecount Position */ +#define TPI_FIFO1_ITM_bytecount_Msk (0x3UL << TPI_FIFO1_ITM_bytecount_Pos) /*!< TPI FIFO1: ITM_bytecount Mask */ + +#define TPI_FIFO1_ETM_ATVALID_Pos 26 /*!< TPI FIFO1: ETM_ATVALID Position */ +#define TPI_FIFO1_ETM_ATVALID_Msk (0x3UL << TPI_FIFO1_ETM_ATVALID_Pos) /*!< TPI FIFO1: ETM_ATVALID Mask */ + +#define TPI_FIFO1_ETM_bytecount_Pos 24 /*!< TPI FIFO1: ETM_bytecount Position */ +#define TPI_FIFO1_ETM_bytecount_Msk (0x3UL << TPI_FIFO1_ETM_bytecount_Pos) /*!< TPI FIFO1: ETM_bytecount Mask */ + +#define TPI_FIFO1_ITM2_Pos 16 /*!< TPI FIFO1: ITM2 Position */ +#define TPI_FIFO1_ITM2_Msk (0xFFUL << TPI_FIFO1_ITM2_Pos) /*!< TPI FIFO1: ITM2 Mask */ + +#define TPI_FIFO1_ITM1_Pos 8 /*!< TPI FIFO1: ITM1 Position */ +#define TPI_FIFO1_ITM1_Msk (0xFFUL << TPI_FIFO1_ITM1_Pos) /*!< TPI FIFO1: ITM1 Mask */ + +#define TPI_FIFO1_ITM0_Pos 0 /*!< TPI FIFO1: ITM0 Position */ +#define TPI_FIFO1_ITM0_Msk (0xFFUL << TPI_FIFO1_ITM0_Pos) /*!< TPI FIFO1: ITM0 Mask */ + +/* TPI ITATBCTR0 Register Definitions */ +#define TPI_ITATBCTR0_ATREADY_Pos 0 /*!< TPI ITATBCTR0: ATREADY Position */ +#define TPI_ITATBCTR0_ATREADY_Msk (0x1UL << TPI_ITATBCTR0_ATREADY_Pos) /*!< TPI ITATBCTR0: ATREADY Mask */ + +/* TPI Integration Mode Control Register Definitions */ +#define TPI_ITCTRL_Mode_Pos 0 /*!< TPI ITCTRL: Mode Position */ +#define TPI_ITCTRL_Mode_Msk (0x1UL << TPI_ITCTRL_Mode_Pos) /*!< TPI ITCTRL: Mode Mask */ + +/* TPI DEVID Register Definitions */ +#define TPI_DEVID_NRZVALID_Pos 11 /*!< TPI DEVID: NRZVALID Position */ +#define TPI_DEVID_NRZVALID_Msk (0x1UL << TPI_DEVID_NRZVALID_Pos) /*!< TPI DEVID: NRZVALID Mask */ + +#define TPI_DEVID_MANCVALID_Pos 10 /*!< TPI DEVID: MANCVALID Position */ +#define TPI_DEVID_MANCVALID_Msk (0x1UL << TPI_DEVID_MANCVALID_Pos) /*!< TPI DEVID: MANCVALID Mask */ + +#define TPI_DEVID_PTINVALID_Pos 9 /*!< TPI DEVID: PTINVALID Position */ +#define TPI_DEVID_PTINVALID_Msk (0x1UL << TPI_DEVID_PTINVALID_Pos) /*!< TPI DEVID: PTINVALID Mask */ + +#define TPI_DEVID_MinBufSz_Pos 6 /*!< TPI DEVID: MinBufSz Position */ +#define TPI_DEVID_MinBufSz_Msk (0x7UL << TPI_DEVID_MinBufSz_Pos) /*!< TPI DEVID: MinBufSz Mask */ + +#define TPI_DEVID_AsynClkIn_Pos 5 /*!< TPI DEVID: AsynClkIn Position */ +#define TPI_DEVID_AsynClkIn_Msk (0x1UL << TPI_DEVID_AsynClkIn_Pos) /*!< TPI DEVID: AsynClkIn Mask */ + +#define TPI_DEVID_NrTraceInput_Pos 0 /*!< TPI DEVID: NrTraceInput Position */ +#define TPI_DEVID_NrTraceInput_Msk (0x1FUL << TPI_DEVID_NrTraceInput_Pos) /*!< TPI DEVID: NrTraceInput Mask */ + +/* TPI DEVTYPE Register Definitions */ +#define TPI_DEVTYPE_SubType_Pos 0 /*!< TPI DEVTYPE: SubType Position */ +#define TPI_DEVTYPE_SubType_Msk (0xFUL << TPI_DEVTYPE_SubType_Pos) /*!< TPI DEVTYPE: SubType Mask */ + +#define TPI_DEVTYPE_MajorType_Pos 4 /*!< TPI DEVTYPE: MajorType Position */ +#define TPI_DEVTYPE_MajorType_Msk (0xFUL << TPI_DEVTYPE_MajorType_Pos) /*!< TPI DEVTYPE: MajorType Mask */ + +/*@}*/ /* end of group CMSIS_TPI */ + + +#if (__MPU_PRESENT == 1) +/** \ingroup CMSIS_core_register + \defgroup CMSIS_MPU Memory Protection Unit (MPU) + \brief Type definitions for the Memory Protection Unit (MPU) + @{ + */ + +/** \brief Structure type to access the Memory Protection Unit (MPU). + */ +typedef struct +{ + __I uint32_t TYPE; /*!< Offset: 0x000 (R/ ) MPU Type Register */ + __IO uint32_t CTRL; /*!< Offset: 0x004 (R/W) MPU Control Register */ + __IO uint32_t RNR; /*!< Offset: 0x008 (R/W) MPU Region RNRber Register */ + __IO uint32_t RBAR; /*!< Offset: 0x00C (R/W) MPU Region Base Address Register */ + __IO uint32_t RASR; /*!< Offset: 0x010 (R/W) MPU Region Attribute and Size Register */ + __IO uint32_t RBAR_A1; /*!< Offset: 0x014 (R/W) MPU Alias 1 Region Base Address Register */ + __IO uint32_t RASR_A1; /*!< Offset: 0x018 (R/W) MPU Alias 1 Region Attribute and Size Register */ + __IO uint32_t RBAR_A2; /*!< Offset: 0x01C (R/W) MPU Alias 2 Region Base Address Register */ + __IO uint32_t RASR_A2; /*!< Offset: 0x020 (R/W) MPU Alias 2 Region Attribute and Size Register */ + __IO uint32_t RBAR_A3; /*!< Offset: 0x024 (R/W) MPU Alias 3 Region Base Address Register */ + __IO uint32_t RASR_A3; /*!< Offset: 0x028 (R/W) MPU Alias 3 Region Attribute and Size Register */ +} MPU_Type; + +/* MPU Type Register */ +#define MPU_TYPE_IREGION_Pos 16 /*!< MPU TYPE: IREGION Position */ +#define MPU_TYPE_IREGION_Msk (0xFFUL << MPU_TYPE_IREGION_Pos) /*!< MPU TYPE: IREGION Mask */ + +#define MPU_TYPE_DREGION_Pos 8 /*!< MPU TYPE: DREGION Position */ +#define MPU_TYPE_DREGION_Msk (0xFFUL << MPU_TYPE_DREGION_Pos) /*!< MPU TYPE: DREGION Mask */ + +#define MPU_TYPE_SEPARATE_Pos 0 /*!< MPU TYPE: SEPARATE Position */ +#define MPU_TYPE_SEPARATE_Msk (1UL << MPU_TYPE_SEPARATE_Pos) /*!< MPU TYPE: SEPARATE Mask */ + +/* MPU Control Register */ +#define MPU_CTRL_PRIVDEFENA_Pos 2 /*!< MPU CTRL: PRIVDEFENA Position */ +#define MPU_CTRL_PRIVDEFENA_Msk (1UL << MPU_CTRL_PRIVDEFENA_Pos) /*!< MPU CTRL: PRIVDEFENA Mask */ + +#define MPU_CTRL_HFNMIENA_Pos 1 /*!< MPU CTRL: HFNMIENA Position */ +#define MPU_CTRL_HFNMIENA_Msk (1UL << MPU_CTRL_HFNMIENA_Pos) /*!< MPU CTRL: HFNMIENA Mask */ + +#define MPU_CTRL_ENABLE_Pos 0 /*!< MPU CTRL: ENABLE Position */ +#define MPU_CTRL_ENABLE_Msk (1UL << MPU_CTRL_ENABLE_Pos) /*!< MPU CTRL: ENABLE Mask */ + +/* MPU Region Number Register */ +#define MPU_RNR_REGION_Pos 0 /*!< MPU RNR: REGION Position */ +#define MPU_RNR_REGION_Msk (0xFFUL << MPU_RNR_REGION_Pos) /*!< MPU RNR: REGION Mask */ + +/* MPU Region Base Address Register */ +#define MPU_RBAR_ADDR_Pos 5 /*!< MPU RBAR: ADDR Position */ +#define MPU_RBAR_ADDR_Msk (0x7FFFFFFUL << MPU_RBAR_ADDR_Pos) /*!< MPU RBAR: ADDR Mask */ + +#define MPU_RBAR_VALID_Pos 4 /*!< MPU RBAR: VALID Position */ +#define MPU_RBAR_VALID_Msk (1UL << MPU_RBAR_VALID_Pos) /*!< MPU RBAR: VALID Mask */ + +#define MPU_RBAR_REGION_Pos 0 /*!< MPU RBAR: REGION Position */ +#define MPU_RBAR_REGION_Msk (0xFUL << MPU_RBAR_REGION_Pos) /*!< MPU RBAR: REGION Mask */ + +/* MPU Region Attribute and Size Register */ +#define MPU_RASR_ATTRS_Pos 16 /*!< MPU RASR: MPU Region Attribute field Position */ +#define MPU_RASR_ATTRS_Msk (0xFFFFUL << MPU_RASR_ATTRS_Pos) /*!< MPU RASR: MPU Region Attribute field Mask */ + +#define MPU_RASR_XN_Pos 28 /*!< MPU RASR: ATTRS.XN Position */ +#define MPU_RASR_XN_Msk (1UL << MPU_RASR_XN_Pos) /*!< MPU RASR: ATTRS.XN Mask */ + +#define MPU_RASR_AP_Pos 24 /*!< MPU RASR: ATTRS.AP Position */ +#define MPU_RASR_AP_Msk (0x7UL << MPU_RASR_AP_Pos) /*!< MPU RASR: ATTRS.AP Mask */ + +#define MPU_RASR_TEX_Pos 19 /*!< MPU RASR: ATTRS.TEX Position */ +#define MPU_RASR_TEX_Msk (0x7UL << MPU_RASR_TEX_Pos) /*!< MPU RASR: ATTRS.TEX Mask */ + +#define MPU_RASR_S_Pos 18 /*!< MPU RASR: ATTRS.S Position */ +#define MPU_RASR_S_Msk (1UL << MPU_RASR_S_Pos) /*!< MPU RASR: ATTRS.S Mask */ + +#define MPU_RASR_C_Pos 17 /*!< MPU RASR: ATTRS.C Position */ +#define MPU_RASR_C_Msk (1UL << MPU_RASR_C_Pos) /*!< MPU RASR: ATTRS.C Mask */ + +#define MPU_RASR_B_Pos 16 /*!< MPU RASR: ATTRS.B Position */ +#define MPU_RASR_B_Msk (1UL << MPU_RASR_B_Pos) /*!< MPU RASR: ATTRS.B Mask */ + +#define MPU_RASR_SRD_Pos 8 /*!< MPU RASR: Sub-Region Disable Position */ +#define MPU_RASR_SRD_Msk (0xFFUL << MPU_RASR_SRD_Pos) /*!< MPU RASR: Sub-Region Disable Mask */ + +#define MPU_RASR_SIZE_Pos 1 /*!< MPU RASR: Region Size Field Position */ +#define MPU_RASR_SIZE_Msk (0x1FUL << MPU_RASR_SIZE_Pos) /*!< MPU RASR: Region Size Field Mask */ + +#define MPU_RASR_ENABLE_Pos 0 /*!< MPU RASR: Region enable bit Position */ +#define MPU_RASR_ENABLE_Msk (1UL << MPU_RASR_ENABLE_Pos) /*!< MPU RASR: Region enable bit Disable Mask */ + +/*@} end of group CMSIS_MPU */ +#endif + + +#if (__FPU_PRESENT == 1) +/** \ingroup CMSIS_core_register + \defgroup CMSIS_FPU Floating Point Unit (FPU) + \brief Type definitions for the Floating Point Unit (FPU) + @{ + */ + +/** \brief Structure type to access the Floating Point Unit (FPU). + */ +typedef struct +{ + uint32_t RESERVED0[1]; + __IO uint32_t FPCCR; /*!< Offset: 0x004 (R/W) Floating-Point Context Control Register */ + __IO uint32_t FPCAR; /*!< Offset: 0x008 (R/W) Floating-Point Context Address Register */ + __IO uint32_t FPDSCR; /*!< Offset: 0x00C (R/W) Floating-Point Default Status Control Register */ + __I uint32_t MVFR0; /*!< Offset: 0x010 (R/ ) Media and FP Feature Register 0 */ + __I uint32_t MVFR1; /*!< Offset: 0x014 (R/ ) Media and FP Feature Register 1 */ +} FPU_Type; + +/* Floating-Point Context Control Register */ +#define FPU_FPCCR_ASPEN_Pos 31 /*!< FPCCR: ASPEN bit Position */ +#define FPU_FPCCR_ASPEN_Msk (1UL << FPU_FPCCR_ASPEN_Pos) /*!< FPCCR: ASPEN bit Mask */ + +#define FPU_FPCCR_LSPEN_Pos 30 /*!< FPCCR: LSPEN Position */ +#define FPU_FPCCR_LSPEN_Msk (1UL << FPU_FPCCR_LSPEN_Pos) /*!< FPCCR: LSPEN bit Mask */ + +#define FPU_FPCCR_MONRDY_Pos 8 /*!< FPCCR: MONRDY Position */ +#define FPU_FPCCR_MONRDY_Msk (1UL << FPU_FPCCR_MONRDY_Pos) /*!< FPCCR: MONRDY bit Mask */ + +#define FPU_FPCCR_BFRDY_Pos 6 /*!< FPCCR: BFRDY Position */ +#define FPU_FPCCR_BFRDY_Msk (1UL << FPU_FPCCR_BFRDY_Pos) /*!< FPCCR: BFRDY bit Mask */ + +#define FPU_FPCCR_MMRDY_Pos 5 /*!< FPCCR: MMRDY Position */ +#define FPU_FPCCR_MMRDY_Msk (1UL << FPU_FPCCR_MMRDY_Pos) /*!< FPCCR: MMRDY bit Mask */ + +#define FPU_FPCCR_HFRDY_Pos 4 /*!< FPCCR: HFRDY Position */ +#define FPU_FPCCR_HFRDY_Msk (1UL << FPU_FPCCR_HFRDY_Pos) /*!< FPCCR: HFRDY bit Mask */ + +#define FPU_FPCCR_THREAD_Pos 3 /*!< FPCCR: processor mode bit Position */ +#define FPU_FPCCR_THREAD_Msk (1UL << FPU_FPCCR_THREAD_Pos) /*!< FPCCR: processor mode active bit Mask */ + +#define FPU_FPCCR_USER_Pos 1 /*!< FPCCR: privilege level bit Position */ +#define FPU_FPCCR_USER_Msk (1UL << FPU_FPCCR_USER_Pos) /*!< FPCCR: privilege level bit Mask */ + +#define FPU_FPCCR_LSPACT_Pos 0 /*!< FPCCR: Lazy state preservation active bit Position */ +#define FPU_FPCCR_LSPACT_Msk (1UL << FPU_FPCCR_LSPACT_Pos) /*!< FPCCR: Lazy state preservation active bit Mask */ + +/* Floating-Point Context Address Register */ +#define FPU_FPCAR_ADDRESS_Pos 3 /*!< FPCAR: ADDRESS bit Position */ +#define FPU_FPCAR_ADDRESS_Msk (0x1FFFFFFFUL << FPU_FPCAR_ADDRESS_Pos) /*!< FPCAR: ADDRESS bit Mask */ + +/* Floating-Point Default Status Control Register */ +#define FPU_FPDSCR_AHP_Pos 26 /*!< FPDSCR: AHP bit Position */ +#define FPU_FPDSCR_AHP_Msk (1UL << FPU_FPDSCR_AHP_Pos) /*!< FPDSCR: AHP bit Mask */ + +#define FPU_FPDSCR_DN_Pos 25 /*!< FPDSCR: DN bit Position */ +#define FPU_FPDSCR_DN_Msk (1UL << FPU_FPDSCR_DN_Pos) /*!< FPDSCR: DN bit Mask */ + +#define FPU_FPDSCR_FZ_Pos 24 /*!< FPDSCR: FZ bit Position */ +#define FPU_FPDSCR_FZ_Msk (1UL << FPU_FPDSCR_FZ_Pos) /*!< FPDSCR: FZ bit Mask */ + +#define FPU_FPDSCR_RMode_Pos 22 /*!< FPDSCR: RMode bit Position */ +#define FPU_FPDSCR_RMode_Msk (3UL << FPU_FPDSCR_RMode_Pos) /*!< FPDSCR: RMode bit Mask */ + +/* Media and FP Feature Register 0 */ +#define FPU_MVFR0_FP_rounding_modes_Pos 28 /*!< MVFR0: FP rounding modes bits Position */ +#define FPU_MVFR0_FP_rounding_modes_Msk (0xFUL << FPU_MVFR0_FP_rounding_modes_Pos) /*!< MVFR0: FP rounding modes bits Mask */ + +#define FPU_MVFR0_Short_vectors_Pos 24 /*!< MVFR0: Short vectors bits Position */ +#define FPU_MVFR0_Short_vectors_Msk (0xFUL << FPU_MVFR0_Short_vectors_Pos) /*!< MVFR0: Short vectors bits Mask */ + +#define FPU_MVFR0_Square_root_Pos 20 /*!< MVFR0: Square root bits Position */ +#define FPU_MVFR0_Square_root_Msk (0xFUL << FPU_MVFR0_Square_root_Pos) /*!< MVFR0: Square root bits Mask */ + +#define FPU_MVFR0_Divide_Pos 16 /*!< MVFR0: Divide bits Position */ +#define FPU_MVFR0_Divide_Msk (0xFUL << FPU_MVFR0_Divide_Pos) /*!< MVFR0: Divide bits Mask */ + +#define FPU_MVFR0_FP_excep_trapping_Pos 12 /*!< MVFR0: FP exception trapping bits Position */ +#define FPU_MVFR0_FP_excep_trapping_Msk (0xFUL << FPU_MVFR0_FP_excep_trapping_Pos) /*!< MVFR0: FP exception trapping bits Mask */ + +#define FPU_MVFR0_Double_precision_Pos 8 /*!< MVFR0: Double-precision bits Position */ +#define FPU_MVFR0_Double_precision_Msk (0xFUL << FPU_MVFR0_Double_precision_Pos) /*!< MVFR0: Double-precision bits Mask */ + +#define FPU_MVFR0_Single_precision_Pos 4 /*!< MVFR0: Single-precision bits Position */ +#define FPU_MVFR0_Single_precision_Msk (0xFUL << FPU_MVFR0_Single_precision_Pos) /*!< MVFR0: Single-precision bits Mask */ + +#define FPU_MVFR0_A_SIMD_registers_Pos 0 /*!< MVFR0: A_SIMD registers bits Position */ +#define FPU_MVFR0_A_SIMD_registers_Msk (0xFUL << FPU_MVFR0_A_SIMD_registers_Pos) /*!< MVFR0: A_SIMD registers bits Mask */ + +/* Media and FP Feature Register 1 */ +#define FPU_MVFR1_FP_fused_MAC_Pos 28 /*!< MVFR1: FP fused MAC bits Position */ +#define FPU_MVFR1_FP_fused_MAC_Msk (0xFUL << FPU_MVFR1_FP_fused_MAC_Pos) /*!< MVFR1: FP fused MAC bits Mask */ + +#define FPU_MVFR1_FP_HPFP_Pos 24 /*!< MVFR1: FP HPFP bits Position */ +#define FPU_MVFR1_FP_HPFP_Msk (0xFUL << FPU_MVFR1_FP_HPFP_Pos) /*!< MVFR1: FP HPFP bits Mask */ + +#define FPU_MVFR1_D_NaN_mode_Pos 4 /*!< MVFR1: D_NaN mode bits Position */ +#define FPU_MVFR1_D_NaN_mode_Msk (0xFUL << FPU_MVFR1_D_NaN_mode_Pos) /*!< MVFR1: D_NaN mode bits Mask */ + +#define FPU_MVFR1_FtZ_mode_Pos 0 /*!< MVFR1: FtZ mode bits Position */ +#define FPU_MVFR1_FtZ_mode_Msk (0xFUL << FPU_MVFR1_FtZ_mode_Pos) /*!< MVFR1: FtZ mode bits Mask */ + +/*@} end of group CMSIS_FPU */ +#endif + + +/** \ingroup CMSIS_core_register + \defgroup CMSIS_CoreDebug Core Debug Registers (CoreDebug) + \brief Type definitions for the Core Debug Registers + @{ + */ + +/** \brief Structure type to access the Core Debug Register (CoreDebug). + */ +typedef struct +{ + __IO uint32_t DHCSR; /*!< Offset: 0x000 (R/W) Debug Halting Control and Status Register */ + __O uint32_t DCRSR; /*!< Offset: 0x004 ( /W) Debug Core Register Selector Register */ + __IO uint32_t DCRDR; /*!< Offset: 0x008 (R/W) Debug Core Register Data Register */ + __IO uint32_t DEMCR; /*!< Offset: 0x00C (R/W) Debug Exception and Monitor Control Register */ +} CoreDebug_Type; + +/* Debug Halting Control and Status Register */ +#define CoreDebug_DHCSR_DBGKEY_Pos 16 /*!< CoreDebug DHCSR: DBGKEY Position */ +#define CoreDebug_DHCSR_DBGKEY_Msk (0xFFFFUL << CoreDebug_DHCSR_DBGKEY_Pos) /*!< CoreDebug DHCSR: DBGKEY Mask */ + +#define CoreDebug_DHCSR_S_RESET_ST_Pos 25 /*!< CoreDebug DHCSR: S_RESET_ST Position */ +#define CoreDebug_DHCSR_S_RESET_ST_Msk (1UL << CoreDebug_DHCSR_S_RESET_ST_Pos) /*!< CoreDebug DHCSR: S_RESET_ST Mask */ + +#define CoreDebug_DHCSR_S_RETIRE_ST_Pos 24 /*!< CoreDebug DHCSR: S_RETIRE_ST Position */ +#define CoreDebug_DHCSR_S_RETIRE_ST_Msk (1UL << CoreDebug_DHCSR_S_RETIRE_ST_Pos) /*!< CoreDebug DHCSR: S_RETIRE_ST Mask */ + +#define CoreDebug_DHCSR_S_LOCKUP_Pos 19 /*!< CoreDebug DHCSR: S_LOCKUP Position */ +#define CoreDebug_DHCSR_S_LOCKUP_Msk (1UL << CoreDebug_DHCSR_S_LOCKUP_Pos) /*!< CoreDebug DHCSR: S_LOCKUP Mask */ + +#define CoreDebug_DHCSR_S_SLEEP_Pos 18 /*!< CoreDebug DHCSR: S_SLEEP Position */ +#define CoreDebug_DHCSR_S_SLEEP_Msk (1UL << CoreDebug_DHCSR_S_SLEEP_Pos) /*!< CoreDebug DHCSR: S_SLEEP Mask */ + +#define CoreDebug_DHCSR_S_HALT_Pos 17 /*!< CoreDebug DHCSR: S_HALT Position */ +#define CoreDebug_DHCSR_S_HALT_Msk (1UL << CoreDebug_DHCSR_S_HALT_Pos) /*!< CoreDebug DHCSR: S_HALT Mask */ + +#define CoreDebug_DHCSR_S_REGRDY_Pos 16 /*!< CoreDebug DHCSR: S_REGRDY Position */ +#define CoreDebug_DHCSR_S_REGRDY_Msk (1UL << CoreDebug_DHCSR_S_REGRDY_Pos) /*!< CoreDebug DHCSR: S_REGRDY Mask */ + +#define CoreDebug_DHCSR_C_SNAPSTALL_Pos 5 /*!< CoreDebug DHCSR: C_SNAPSTALL Position */ +#define CoreDebug_DHCSR_C_SNAPSTALL_Msk (1UL << CoreDebug_DHCSR_C_SNAPSTALL_Pos) /*!< CoreDebug DHCSR: C_SNAPSTALL Mask */ + +#define CoreDebug_DHCSR_C_MASKINTS_Pos 3 /*!< CoreDebug DHCSR: C_MASKINTS Position */ +#define CoreDebug_DHCSR_C_MASKINTS_Msk (1UL << CoreDebug_DHCSR_C_MASKINTS_Pos) /*!< CoreDebug DHCSR: C_MASKINTS Mask */ + +#define CoreDebug_DHCSR_C_STEP_Pos 2 /*!< CoreDebug DHCSR: C_STEP Position */ +#define CoreDebug_DHCSR_C_STEP_Msk (1UL << CoreDebug_DHCSR_C_STEP_Pos) /*!< CoreDebug DHCSR: C_STEP Mask */ + +#define CoreDebug_DHCSR_C_HALT_Pos 1 /*!< CoreDebug DHCSR: C_HALT Position */ +#define CoreDebug_DHCSR_C_HALT_Msk (1UL << CoreDebug_DHCSR_C_HALT_Pos) /*!< CoreDebug DHCSR: C_HALT Mask */ + +#define CoreDebug_DHCSR_C_DEBUGEN_Pos 0 /*!< CoreDebug DHCSR: C_DEBUGEN Position */ +#define CoreDebug_DHCSR_C_DEBUGEN_Msk (1UL << CoreDebug_DHCSR_C_DEBUGEN_Pos) /*!< CoreDebug DHCSR: C_DEBUGEN Mask */ + +/* Debug Core Register Selector Register */ +#define CoreDebug_DCRSR_REGWnR_Pos 16 /*!< CoreDebug DCRSR: REGWnR Position */ +#define CoreDebug_DCRSR_REGWnR_Msk (1UL << CoreDebug_DCRSR_REGWnR_Pos) /*!< CoreDebug DCRSR: REGWnR Mask */ + +#define CoreDebug_DCRSR_REGSEL_Pos 0 /*!< CoreDebug DCRSR: REGSEL Position */ +#define CoreDebug_DCRSR_REGSEL_Msk (0x1FUL << CoreDebug_DCRSR_REGSEL_Pos) /*!< CoreDebug DCRSR: REGSEL Mask */ + +/* Debug Exception and Monitor Control Register */ +#define CoreDebug_DEMCR_TRCENA_Pos 24 /*!< CoreDebug DEMCR: TRCENA Position */ +#define CoreDebug_DEMCR_TRCENA_Msk (1UL << CoreDebug_DEMCR_TRCENA_Pos) /*!< CoreDebug DEMCR: TRCENA Mask */ + +#define CoreDebug_DEMCR_MON_REQ_Pos 19 /*!< CoreDebug DEMCR: MON_REQ Position */ +#define CoreDebug_DEMCR_MON_REQ_Msk (1UL << CoreDebug_DEMCR_MON_REQ_Pos) /*!< CoreDebug DEMCR: MON_REQ Mask */ + +#define CoreDebug_DEMCR_MON_STEP_Pos 18 /*!< CoreDebug DEMCR: MON_STEP Position */ +#define CoreDebug_DEMCR_MON_STEP_Msk (1UL << CoreDebug_DEMCR_MON_STEP_Pos) /*!< CoreDebug DEMCR: MON_STEP Mask */ + +#define CoreDebug_DEMCR_MON_PEND_Pos 17 /*!< CoreDebug DEMCR: MON_PEND Position */ +#define CoreDebug_DEMCR_MON_PEND_Msk (1UL << CoreDebug_DEMCR_MON_PEND_Pos) /*!< CoreDebug DEMCR: MON_PEND Mask */ + +#define CoreDebug_DEMCR_MON_EN_Pos 16 /*!< CoreDebug DEMCR: MON_EN Position */ +#define CoreDebug_DEMCR_MON_EN_Msk (1UL << CoreDebug_DEMCR_MON_EN_Pos) /*!< CoreDebug DEMCR: MON_EN Mask */ + +#define CoreDebug_DEMCR_VC_HARDERR_Pos 10 /*!< CoreDebug DEMCR: VC_HARDERR Position */ +#define CoreDebug_DEMCR_VC_HARDERR_Msk (1UL << CoreDebug_DEMCR_VC_HARDERR_Pos) /*!< CoreDebug DEMCR: VC_HARDERR Mask */ + +#define CoreDebug_DEMCR_VC_INTERR_Pos 9 /*!< CoreDebug DEMCR: VC_INTERR Position */ +#define CoreDebug_DEMCR_VC_INTERR_Msk (1UL << CoreDebug_DEMCR_VC_INTERR_Pos) /*!< CoreDebug DEMCR: VC_INTERR Mask */ + +#define CoreDebug_DEMCR_VC_BUSERR_Pos 8 /*!< CoreDebug DEMCR: VC_BUSERR Position */ +#define CoreDebug_DEMCR_VC_BUSERR_Msk (1UL << CoreDebug_DEMCR_VC_BUSERR_Pos) /*!< CoreDebug DEMCR: VC_BUSERR Mask */ + +#define CoreDebug_DEMCR_VC_STATERR_Pos 7 /*!< CoreDebug DEMCR: VC_STATERR Position */ +#define CoreDebug_DEMCR_VC_STATERR_Msk (1UL << CoreDebug_DEMCR_VC_STATERR_Pos) /*!< CoreDebug DEMCR: VC_STATERR Mask */ + +#define CoreDebug_DEMCR_VC_CHKERR_Pos 6 /*!< CoreDebug DEMCR: VC_CHKERR Position */ +#define CoreDebug_DEMCR_VC_CHKERR_Msk (1UL << CoreDebug_DEMCR_VC_CHKERR_Pos) /*!< CoreDebug DEMCR: VC_CHKERR Mask */ + +#define CoreDebug_DEMCR_VC_NOCPERR_Pos 5 /*!< CoreDebug DEMCR: VC_NOCPERR Position */ +#define CoreDebug_DEMCR_VC_NOCPERR_Msk (1UL << CoreDebug_DEMCR_VC_NOCPERR_Pos) /*!< CoreDebug DEMCR: VC_NOCPERR Mask */ + +#define CoreDebug_DEMCR_VC_MMERR_Pos 4 /*!< CoreDebug DEMCR: VC_MMERR Position */ +#define CoreDebug_DEMCR_VC_MMERR_Msk (1UL << CoreDebug_DEMCR_VC_MMERR_Pos) /*!< CoreDebug DEMCR: VC_MMERR Mask */ + +#define CoreDebug_DEMCR_VC_CORERESET_Pos 0 /*!< CoreDebug DEMCR: VC_CORERESET Position */ +#define CoreDebug_DEMCR_VC_CORERESET_Msk (1UL << CoreDebug_DEMCR_VC_CORERESET_Pos) /*!< CoreDebug DEMCR: VC_CORERESET Mask */ + +/*@} end of group CMSIS_CoreDebug */ + + +/** \ingroup CMSIS_core_register + \defgroup CMSIS_core_base Core Definitions + \brief Definitions for base addresses, unions, and structures. + @{ + */ + +/* Memory mapping of Cortex-M4 Hardware */ +#define SCS_BASE (0xE000E000UL) /*!< System Control Space Base Address */ +#define ITM_BASE (0xE0000000UL) /*!< ITM Base Address */ +#define DWT_BASE (0xE0001000UL) /*!< DWT Base Address */ +#define TPI_BASE (0xE0040000UL) /*!< TPI Base Address */ +#define CoreDebug_BASE (0xE000EDF0UL) /*!< Core Debug Base Address */ +#define SysTick_BASE (SCS_BASE + 0x0010UL) /*!< SysTick Base Address */ +#define NVIC_BASE (SCS_BASE + 0x0100UL) /*!< NVIC Base Address */ +#define SCB_BASE (SCS_BASE + 0x0D00UL) /*!< System Control Block Base Address */ + +#define SCnSCB ((SCnSCB_Type *) SCS_BASE ) /*!< System control Register not in SCB */ +#define SCB ((SCB_Type *) SCB_BASE ) /*!< SCB configuration struct */ +#define SysTick ((SysTick_Type *) SysTick_BASE ) /*!< SysTick configuration struct */ +#define NVIC ((NVIC_Type *) NVIC_BASE ) /*!< NVIC configuration struct */ +#define ITM ((ITM_Type *) ITM_BASE ) /*!< ITM configuration struct */ +#define DWT ((DWT_Type *) DWT_BASE ) /*!< DWT configuration struct */ +#define TPI ((TPI_Type *) TPI_BASE ) /*!< TPI configuration struct */ +#define CoreDebug ((CoreDebug_Type *) CoreDebug_BASE) /*!< Core Debug configuration struct */ + +#if (__MPU_PRESENT == 1) + #define MPU_BASE (SCS_BASE + 0x0D90UL) /*!< Memory Protection Unit */ + #define MPU ((MPU_Type *) MPU_BASE ) /*!< Memory Protection Unit */ +#endif + +#if (__FPU_PRESENT == 1) + #define FPU_BASE (SCS_BASE + 0x0F30UL) /*!< Floating Point Unit */ + #define FPU ((FPU_Type *) FPU_BASE ) /*!< Floating Point Unit */ +#endif + +/*@} */ + + + +/******************************************************************************* + * Hardware Abstraction Layer + Core Function Interface contains: + - Core NVIC Functions + - Core SysTick Functions + - Core Debug Functions + - Core Register Access Functions + ******************************************************************************/ +/** \defgroup CMSIS_Core_FunctionInterface Functions and Instructions Reference +*/ + + + +/* ########################## NVIC functions #################################### */ +/** \ingroup CMSIS_Core_FunctionInterface + \defgroup CMSIS_Core_NVICFunctions NVIC Functions + \brief Functions that manage interrupts and exceptions via the NVIC. + @{ + */ + +/** \brief Set Priority Grouping + + The function sets the priority grouping field using the required unlock sequence. + The parameter PriorityGroup is assigned to the field SCB->AIRCR [10:8] PRIGROUP field. + Only values from 0..7 are used. + In case of a conflict between priority grouping and available + priority bits (__NVIC_PRIO_BITS), the smallest possible priority group is set. + + \param [in] PriorityGroup Priority grouping field. + */ +__STATIC_INLINE void NVIC_SetPriorityGrouping(uint32_t PriorityGroup) +{ + uint32_t reg_value; + uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07); /* only values 0..7 are used */ + + reg_value = SCB->AIRCR; /* read old register configuration */ + reg_value &= ~(SCB_AIRCR_VECTKEY_Msk | SCB_AIRCR_PRIGROUP_Msk); /* clear bits to change */ + reg_value = (reg_value | + ((uint32_t)0x5FA << SCB_AIRCR_VECTKEY_Pos) | + (PriorityGroupTmp << 8)); /* Insert write key and priorty group */ + SCB->AIRCR = reg_value; +} + + +/** \brief Get Priority Grouping + + The function reads the priority grouping field from the NVIC Interrupt Controller. + + \return Priority grouping field (SCB->AIRCR [10:8] PRIGROUP field). + */ +__STATIC_INLINE uint32_t NVIC_GetPriorityGrouping(void) +{ + return ((SCB->AIRCR & SCB_AIRCR_PRIGROUP_Msk) >> SCB_AIRCR_PRIGROUP_Pos); /* read priority grouping field */ +} + + +/** \brief Enable External Interrupt + + The function enables a device-specific interrupt in the NVIC interrupt controller. + + \param [in] IRQn External interrupt number. Value cannot be negative. + */ +__STATIC_INLINE void NVIC_EnableIRQ(IRQn_Type IRQn) +{ +/* NVIC->ISER[((uint32_t)(IRQn) >> 5)] = (1 << ((uint32_t)(IRQn) & 0x1F)); enable interrupt */ + NVIC->ISER[(uint32_t)((int32_t)IRQn) >> 5] = (uint32_t)(1 << ((uint32_t)((int32_t)IRQn) & (uint32_t)0x1F)); /* enable interrupt */ +} + + +/** \brief Disable External Interrupt + + The function disables a device-specific interrupt in the NVIC interrupt controller. + + \param [in] IRQn External interrupt number. Value cannot be negative. + */ +__STATIC_INLINE void NVIC_DisableIRQ(IRQn_Type IRQn) +{ + NVIC->ICER[((uint32_t)(IRQn) >> 5)] = (1 << ((uint32_t)(IRQn) & 0x1F)); /* disable interrupt */ +} + + +/** \brief Get Pending Interrupt + + The function reads the pending register in the NVIC and returns the pending bit + for the specified interrupt. + + \param [in] IRQn Interrupt number. + + \return 0 Interrupt status is not pending. + \return 1 Interrupt status is pending. + */ +__STATIC_INLINE uint32_t NVIC_GetPendingIRQ(IRQn_Type IRQn) +{ + return((uint32_t) ((NVIC->ISPR[(uint32_t)(IRQn) >> 5] & (1 << ((uint32_t)(IRQn) & 0x1F)))?1:0)); /* Return 1 if pending else 0 */ +} + + +/** \brief Set Pending Interrupt + + The function sets the pending bit of an external interrupt. + + \param [in] IRQn Interrupt number. Value cannot be negative. + */ +__STATIC_INLINE void NVIC_SetPendingIRQ(IRQn_Type IRQn) +{ + NVIC->ISPR[((uint32_t)(IRQn) >> 5)] = (1 << ((uint32_t)(IRQn) & 0x1F)); /* set interrupt pending */ +} + + +/** \brief Clear Pending Interrupt + + The function clears the pending bit of an external interrupt. + + \param [in] IRQn External interrupt number. Value cannot be negative. + */ +__STATIC_INLINE void NVIC_ClearPendingIRQ(IRQn_Type IRQn) +{ + NVIC->ICPR[((uint32_t)(IRQn) >> 5)] = (1 << ((uint32_t)(IRQn) & 0x1F)); /* Clear pending interrupt */ +} + + +/** \brief Get Active Interrupt + + The function reads the active register in NVIC and returns the active bit. + + \param [in] IRQn Interrupt number. + + \return 0 Interrupt status is not active. + \return 1 Interrupt status is active. + */ +__STATIC_INLINE uint32_t NVIC_GetActive(IRQn_Type IRQn) +{ + return((uint32_t)((NVIC->IABR[(uint32_t)(IRQn) >> 5] & (1 << ((uint32_t)(IRQn) & 0x1F)))?1:0)); /* Return 1 if active else 0 */ +} + + +/** \brief Set Interrupt Priority + + The function sets the priority of an interrupt. + + \note The priority cannot be set for every core interrupt. + + \param [in] IRQn Interrupt number. + \param [in] priority Priority to set. + */ +__STATIC_INLINE void NVIC_SetPriority(IRQn_Type IRQn, uint32_t priority) +{ + if(IRQn < 0) { + SCB->SHP[((uint32_t)(IRQn) & 0xF)-4] = ((priority << (8 - __NVIC_PRIO_BITS)) & 0xff); } /* set Priority for Cortex-M System Interrupts */ + else { + NVIC->IP[(uint32_t)(IRQn)] = ((priority << (8 - __NVIC_PRIO_BITS)) & 0xff); } /* set Priority for device specific Interrupts */ +} + + +/** \brief Get Interrupt Priority + + The function reads the priority of an interrupt. The interrupt + number can be positive to specify an external (device specific) + interrupt, or negative to specify an internal (core) interrupt. + + + \param [in] IRQn Interrupt number. + \return Interrupt Priority. Value is aligned automatically to the implemented + priority bits of the microcontroller. + */ +__STATIC_INLINE uint32_t NVIC_GetPriority(IRQn_Type IRQn) +{ + + if(IRQn < 0) { + return((uint32_t)(SCB->SHP[((uint32_t)(IRQn) & 0xF)-4] >> (8 - __NVIC_PRIO_BITS))); } /* get priority for Cortex-M system interrupts */ + else { + return((uint32_t)(NVIC->IP[(uint32_t)(IRQn)] >> (8 - __NVIC_PRIO_BITS))); } /* get priority for device specific interrupts */ +} + + +/** \brief Encode Priority + + The function encodes the priority for an interrupt with the given priority group, + preemptive priority value, and subpriority value. + In case of a conflict between priority grouping and available + priority bits (__NVIC_PRIO_BITS), the samllest possible priority group is set. + + \param [in] PriorityGroup Used priority group. + \param [in] PreemptPriority Preemptive priority value (starting from 0). + \param [in] SubPriority Subpriority value (starting from 0). + \return Encoded priority. Value can be used in the function \ref NVIC_SetPriority(). + */ +__STATIC_INLINE uint32_t NVIC_EncodePriority (uint32_t PriorityGroup, uint32_t PreemptPriority, uint32_t SubPriority) +{ + uint32_t PriorityGroupTmp = (PriorityGroup & 0x07); /* only values 0..7 are used */ + uint32_t PreemptPriorityBits; + uint32_t SubPriorityBits; + + PreemptPriorityBits = ((7 - PriorityGroupTmp) > __NVIC_PRIO_BITS) ? __NVIC_PRIO_BITS : 7 - PriorityGroupTmp; + SubPriorityBits = ((PriorityGroupTmp + __NVIC_PRIO_BITS) < 7) ? 0 : PriorityGroupTmp - 7 + __NVIC_PRIO_BITS; + + return ( + ((PreemptPriority & ((1 << (PreemptPriorityBits)) - 1)) << SubPriorityBits) | + ((SubPriority & ((1 << (SubPriorityBits )) - 1))) + ); +} + + +/** \brief Decode Priority + + The function decodes an interrupt priority value with a given priority group to + preemptive priority value and subpriority value. + In case of a conflict between priority grouping and available + priority bits (__NVIC_PRIO_BITS) the samllest possible priority group is set. + + \param [in] Priority Priority value, which can be retrieved with the function \ref NVIC_GetPriority(). + \param [in] PriorityGroup Used priority group. + \param [out] pPreemptPriority Preemptive priority value (starting from 0). + \param [out] pSubPriority Subpriority value (starting from 0). + */ +__STATIC_INLINE void NVIC_DecodePriority (uint32_t Priority, uint32_t PriorityGroup, uint32_t* pPreemptPriority, uint32_t* pSubPriority) +{ + uint32_t PriorityGroupTmp = (PriorityGroup & 0x07); /* only values 0..7 are used */ + uint32_t PreemptPriorityBits; + uint32_t SubPriorityBits; + + PreemptPriorityBits = ((7 - PriorityGroupTmp) > __NVIC_PRIO_BITS) ? __NVIC_PRIO_BITS : 7 - PriorityGroupTmp; + SubPriorityBits = ((PriorityGroupTmp + __NVIC_PRIO_BITS) < 7) ? 0 : PriorityGroupTmp - 7 + __NVIC_PRIO_BITS; + + *pPreemptPriority = (Priority >> SubPriorityBits) & ((1 << (PreemptPriorityBits)) - 1); + *pSubPriority = (Priority ) & ((1 << (SubPriorityBits )) - 1); +} + + +/** \brief System Reset + + The function initiates a system reset request to reset the MCU. + */ +__STATIC_INLINE void NVIC_SystemReset(void) +{ + __DSB(); /* Ensure all outstanding memory accesses included + buffered write are completed before reset */ + SCB->AIRCR = ((0x5FA << SCB_AIRCR_VECTKEY_Pos) | + (SCB->AIRCR & SCB_AIRCR_PRIGROUP_Msk) | + SCB_AIRCR_SYSRESETREQ_Msk); /* Keep priority group unchanged */ + __DSB(); /* Ensure completion of memory access */ + while(1); /* wait until reset */ +} + +/*@} end of CMSIS_Core_NVICFunctions */ + + + +/* ################################## SysTick function ############################################ */ +/** \ingroup CMSIS_Core_FunctionInterface + \defgroup CMSIS_Core_SysTickFunctions SysTick Functions + \brief Functions that configure the System. + @{ + */ + +#if (__Vendor_SysTickConfig == 0) + +/** \brief System Tick Configuration + + The function initializes the System Timer and its interrupt, and starts the System Tick Timer. + Counter is in free running mode to generate periodic interrupts. + + \param [in] ticks Number of ticks between two interrupts. + + \return 0 Function succeeded. + \return 1 Function failed. + + \note When the variable __Vendor_SysTickConfig is set to 1, then the + function SysTick_Config is not included. In this case, the file device.h + must contain a vendor-specific implementation of this function. + + */ +__STATIC_INLINE uint32_t SysTick_Config(uint32_t ticks) +{ + if (ticks > SysTick_LOAD_RELOAD_Msk) return (1); /* Reload value impossible */ + + SysTick->LOAD = (ticks & SysTick_LOAD_RELOAD_Msk) - 1; /* set reload register */ + NVIC_SetPriority (SysTick_IRQn, (1<<__NVIC_PRIO_BITS) - 1); /* set Priority for Systick Interrupt */ + SysTick->VAL = 0; /* Load the SysTick Counter Value */ + SysTick->CTRL = SysTick_CTRL_CLKSOURCE_Msk | + SysTick_CTRL_TICKINT_Msk | + SysTick_CTRL_ENABLE_Msk; /* Enable SysTick IRQ and SysTick Timer */ + return (0); /* Function successful */ +} + +#endif + +/*@} end of CMSIS_Core_SysTickFunctions */ + + + +/* ##################################### Debug In/Output function ########################################### */ +/** \ingroup CMSIS_Core_FunctionInterface + \defgroup CMSIS_core_DebugFunctions ITM Functions + \brief Functions that access the ITM debug interface. + @{ + */ + +extern volatile int32_t ITM_RxBuffer; /*!< External variable to receive characters. */ +#define ITM_RXBUFFER_EMPTY 0x5AA55AA5 /*!< Value identifying \ref ITM_RxBuffer is ready for next character. */ + + +/** \brief ITM Send Character + + The function transmits a character via the ITM channel 0, and + \li Just returns when no debugger is connected that has booked the output. + \li Is blocking when a debugger is connected, but the previous character sent has not been transmitted. + + \param [in] ch Character to transmit. + + \returns Character to transmit. + */ +__STATIC_INLINE uint32_t ITM_SendChar (uint32_t ch) +{ + if ((ITM->TCR & ITM_TCR_ITMENA_Msk) && /* ITM enabled */ + (ITM->TER & (1UL << 0) ) ) /* ITM Port #0 enabled */ + { + while (ITM->PORT[0].u32 == 0); + ITM->PORT[0].u8 = (uint8_t) ch; + } + return (ch); +} + + +/** \brief ITM Receive Character + + The function inputs a character via the external variable \ref ITM_RxBuffer. + + \return Received character. + \return -1 No character pending. + */ +__STATIC_INLINE int32_t ITM_ReceiveChar (void) { + int32_t ch = -1; /* no character available */ + + if (ITM_RxBuffer != ITM_RXBUFFER_EMPTY) { + ch = ITM_RxBuffer; + ITM_RxBuffer = ITM_RXBUFFER_EMPTY; /* ready for next character */ + } + + return (ch); +} + + +/** \brief ITM Check Character + + The function checks whether a character is pending for reading in the variable \ref ITM_RxBuffer. + + \return 0 No character available. + \return 1 Character available. + */ +__STATIC_INLINE int32_t ITM_CheckChar (void) { + + if (ITM_RxBuffer == ITM_RXBUFFER_EMPTY) { + return (0); /* no character available */ + } else { + return (1); /* character available */ + } +} + +/*@} end of CMSIS_core_DebugFunctions */ + +#endif /* __CORE_CM4_H_DEPENDANT */ + +#endif /* __CMSIS_GENERIC */ + +#ifdef __cplusplus +} +#endif diff --git a/Libraries/CMSIS/Include/core_cm4_simd.h b/Libraries/CMSIS/Include/core_cm4_simd.h new file mode 100644 index 0000000..3bc7906 --- /dev/null +++ b/Libraries/CMSIS/Include/core_cm4_simd.h @@ -0,0 +1,649 @@ +/**************************************************************************//** + * @file core_cm4_simd.h + * @brief CMSIS Cortex-M4 SIMD Header File + * @version V3.01 + * @date 06. March 2012 + * + * @note + * Copyright (C) 2010-2012 ARM Limited. All rights reserved. + * + * @par + * ARM Limited (ARM) is supplying this software for use with Cortex-M + * processor based microcontrollers. This file can be freely distributed + * within development tools that are supporting such ARM based processors. + * + * @par + * THIS SOFTWARE IS PROVIDED "AS IS". NO WARRANTIES, WHETHER EXPRESS, IMPLIED + * OR STATUTORY, INCLUDING, BUT NOT LIMITED TO, IMPLIED WARRANTIES OF + * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE APPLY TO THIS SOFTWARE. + * ARM SHALL NOT, IN ANY CIRCUMSTANCES, BE LIABLE FOR SPECIAL, INCIDENTAL, OR + * CONSEQUENTIAL DAMAGES, FOR ANY REASON WHATSOEVER. + * + ******************************************************************************/ + +#ifdef __cplusplus + extern "C" { +#endif + +#ifndef __CORE_CM4_SIMD_H +#define __CORE_CM4_SIMD_H + + +/******************************************************************************* + * Hardware Abstraction Layer + ******************************************************************************/ + + +/* ################### Compiler specific Intrinsics ########################### */ +/** \defgroup CMSIS_SIMD_intrinsics CMSIS SIMD Intrinsics + Access to dedicated SIMD instructions + @{ +*/ + +#if defined ( __CC_ARM ) /*------------------RealView Compiler -----------------*/ +/* ARM armcc specific functions */ + +/*------ CM4 SIMD Intrinsics -----------------------------------------------------*/ +#define __SADD8 __sadd8 +#define __QADD8 __qadd8 +#define __SHADD8 __shadd8 +#define __UADD8 __uadd8 +#define __UQADD8 __uqadd8 +#define __UHADD8 __uhadd8 +#define __SSUB8 __ssub8 +#define __QSUB8 __qsub8 +#define __SHSUB8 __shsub8 +#define __USUB8 __usub8 +#define __UQSUB8 __uqsub8 +#define __UHSUB8 __uhsub8 +#define __SADD16 __sadd16 +#define __QADD16 __qadd16 +#define __SHADD16 __shadd16 +#define __UADD16 __uadd16 +#define __UQADD16 __uqadd16 +#define __UHADD16 __uhadd16 +#define __SSUB16 __ssub16 +#define __QSUB16 __qsub16 +#define __SHSUB16 __shsub16 +#define __USUB16 __usub16 +#define __UQSUB16 __uqsub16 +#define __UHSUB16 __uhsub16 +#define __SASX __sasx +#define __QASX __qasx +#define __SHASX __shasx +#define __UASX __uasx +#define __UQASX __uqasx +#define __UHASX __uhasx +#define __SSAX __ssax +#define __QSAX __qsax +#define __SHSAX __shsax +#define __USAX __usax +#define __UQSAX __uqsax +#define __UHSAX __uhsax +#define __USAD8 __usad8 +#define __USADA8 __usada8 +#define __SSAT16 __ssat16 +#define __USAT16 __usat16 +#define __UXTB16 __uxtb16 +#define __UXTAB16 __uxtab16 +#define __SXTB16 __sxtb16 +#define __SXTAB16 __sxtab16 +#define __SMUAD __smuad +#define __SMUADX __smuadx +#define __SMLAD __smlad +#define __SMLADX __smladx +#define __SMLALD __smlald +#define __SMLALDX __smlaldx +#define __SMUSD __smusd +#define __SMUSDX __smusdx +#define __SMLSD __smlsd +#define __SMLSDX __smlsdx +#define __SMLSLD __smlsld +#define __SMLSLDX __smlsldx +#define __SEL __sel +#define __QADD __qadd +#define __QSUB __qsub + +#define __PKHBT(ARG1,ARG2,ARG3) ( ((((uint32_t)(ARG1)) ) & 0x0000FFFFUL) | \ + ((((uint32_t)(ARG2)) << (ARG3)) & 0xFFFF0000UL) ) + +#define __PKHTB(ARG1,ARG2,ARG3) ( ((((uint32_t)(ARG1)) ) & 0xFFFF0000UL) | \ + ((((uint32_t)(ARG2)) >> (ARG3)) & 0x0000FFFFUL) ) + + +/*-- End CM4 SIMD Intrinsics -----------------------------------------------------*/ + + + +#elif defined ( __ICCARM__ ) /*------------------ ICC Compiler -------------------*/ +/* IAR iccarm specific functions */ + +/*------ CM4 SIMD Intrinsics -----------------------------------------------------*/ +#include + +/*-- End CM4 SIMD Intrinsics -----------------------------------------------------*/ + + + +#elif defined ( __TMS470__ ) /*---------------- TI CCS Compiler ------------------*/ +/* TI CCS specific functions */ + +/*------ CM4 SIMD Intrinsics -----------------------------------------------------*/ +#include + +/*-- End CM4 SIMD Intrinsics -----------------------------------------------------*/ + + + +#elif defined ( __GNUC__ ) /*------------------ GNU Compiler ---------------------*/ +/* GNU gcc specific functions */ + +/*------ CM4 SIMD Intrinsics -----------------------------------------------------*/ +__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __SADD8(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("sadd8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __QADD8(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("qadd8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __SHADD8(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("shadd8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __UADD8(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("uadd8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __UQADD8(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("uqadd8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __UHADD8(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("uhadd8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + + +__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __SSUB8(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("ssub8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __QSUB8(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("qsub8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __SHSUB8(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("shsub8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __USUB8(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("usub8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __UQSUB8(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("uqsub8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __UHSUB8(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("uhsub8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + + +__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __SADD16(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("sadd16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __QADD16(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("qadd16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __SHADD16(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("shadd16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __UADD16(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("uadd16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __UQADD16(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("uqadd16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __UHADD16(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("uhadd16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __SSUB16(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("ssub16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __QSUB16(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("qsub16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __SHSUB16(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("shsub16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __USUB16(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("usub16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __UQSUB16(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("uqsub16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __UHSUB16(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("uhsub16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __SASX(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("sasx %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __QASX(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("qasx %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __SHASX(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("shasx %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __UASX(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("uasx %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __UQASX(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("uqasx %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __UHASX(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("uhasx %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __SSAX(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("ssax %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __QSAX(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("qsax %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __SHSAX(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("shsax %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __USAX(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("usax %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __UQSAX(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("uqsax %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __UHSAX(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("uhsax %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __USAD8(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("usad8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __USADA8(uint32_t op1, uint32_t op2, uint32_t op3) +{ + uint32_t result; + + __ASM volatile ("usada8 %0, %1, %2, %3" : "=r" (result) : "r" (op1), "r" (op2), "r" (op3) ); + return(result); +} + +#define __SSAT16(ARG1,ARG2) \ +({ \ + uint32_t __RES, __ARG1 = (ARG1); \ + __ASM ("ssat16 %0, %1, %2" : "=r" (__RES) : "I" (ARG2), "r" (__ARG1) ); \ + __RES; \ + }) + +#define __USAT16(ARG1,ARG2) \ +({ \ + uint32_t __RES, __ARG1 = (ARG1); \ + __ASM ("usat16 %0, %1, %2" : "=r" (__RES) : "I" (ARG2), "r" (__ARG1) ); \ + __RES; \ + }) + +__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __UXTB16(uint32_t op1) +{ + uint32_t result; + + __ASM volatile ("uxtb16 %0, %1" : "=r" (result) : "r" (op1)); + return(result); +} + +__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __UXTAB16(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("uxtab16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __SXTB16(uint32_t op1) +{ + uint32_t result; + + __ASM volatile ("sxtb16 %0, %1" : "=r" (result) : "r" (op1)); + return(result); +} + +__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __SXTAB16(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("sxtab16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __SMUAD (uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("smuad %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __SMUADX (uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("smuadx %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __SMLAD (uint32_t op1, uint32_t op2, uint32_t op3) +{ + uint32_t result; + + __ASM volatile ("smlad %0, %1, %2, %3" : "=r" (result) : "r" (op1), "r" (op2), "r" (op3) ); + return(result); +} + +__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __SMLADX (uint32_t op1, uint32_t op2, uint32_t op3) +{ + uint32_t result; + + __ASM volatile ("smladx %0, %1, %2, %3" : "=r" (result) : "r" (op1), "r" (op2), "r" (op3) ); + return(result); +} + +#define __SMLALD(ARG1,ARG2,ARG3) \ +({ \ + uint32_t __ARG1 = (ARG1), __ARG2 = (ARG2), __ARG3_H = (uint32_t)((uint64_t)(ARG3) >> 32), __ARG3_L = (uint32_t)((uint64_t)(ARG3) & 0xFFFFFFFFUL); \ + __ASM volatile ("smlald %0, %1, %2, %3" : "=r" (__ARG3_L), "=r" (__ARG3_H) : "r" (__ARG1), "r" (__ARG2), "0" (__ARG3_L), "1" (__ARG3_H) ); \ + (uint64_t)(((uint64_t)__ARG3_H << 32) | __ARG3_L); \ + }) + +#define __SMLALDX(ARG1,ARG2,ARG3) \ +({ \ + uint32_t __ARG1 = (ARG1), __ARG2 = (ARG2), __ARG3_H = (uint32_t)((uint64_t)(ARG3) >> 32), __ARG3_L = (uint32_t)((uint64_t)(ARG3) & 0xFFFFFFFFUL); \ + __ASM volatile ("smlaldx %0, %1, %2, %3" : "=r" (__ARG3_L), "=r" (__ARG3_H) : "r" (__ARG1), "r" (__ARG2), "0" (__ARG3_L), "1" (__ARG3_H) ); \ + (uint64_t)(((uint64_t)__ARG3_H << 32) | __ARG3_L); \ + }) + +__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __SMUSD (uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("smusd %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __SMUSDX (uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("smusdx %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __SMLSD (uint32_t op1, uint32_t op2, uint32_t op3) +{ + uint32_t result; + + __ASM volatile ("smlsd %0, %1, %2, %3" : "=r" (result) : "r" (op1), "r" (op2), "r" (op3) ); + return(result); +} + +__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __SMLSDX (uint32_t op1, uint32_t op2, uint32_t op3) +{ + uint32_t result; + + __ASM volatile ("smlsdx %0, %1, %2, %3" : "=r" (result) : "r" (op1), "r" (op2), "r" (op3) ); + return(result); +} + +#define __SMLSLD(ARG1,ARG2,ARG3) \ +({ \ + uint32_t __ARG1 = (ARG1), __ARG2 = (ARG2), __ARG3_H = (uint32_t)((ARG3) >> 32), __ARG3_L = (uint32_t)((ARG3) & 0xFFFFFFFFUL); \ + __ASM volatile ("smlsld %0, %1, %2, %3" : "=r" (__ARG3_L), "=r" (__ARG3_H) : "r" (__ARG1), "r" (__ARG2), "0" (__ARG3_L), "1" (__ARG3_H) ); \ + (uint64_t)(((uint64_t)__ARG3_H << 32) | __ARG3_L); \ + }) + +#define __SMLSLDX(ARG1,ARG2,ARG3) \ +({ \ + uint32_t __ARG1 = (ARG1), __ARG2 = (ARG2), __ARG3_H = (uint32_t)((ARG3) >> 32), __ARG3_L = (uint32_t)((ARG3) & 0xFFFFFFFFUL); \ + __ASM volatile ("smlsldx %0, %1, %2, %3" : "=r" (__ARG3_L), "=r" (__ARG3_H) : "r" (__ARG1), "r" (__ARG2), "0" (__ARG3_L), "1" (__ARG3_H) ); \ + (uint64_t)(((uint64_t)__ARG3_H << 32) | __ARG3_L); \ + }) + +__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __SEL (uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("sel %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __QADD(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("qadd %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __QSUB(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("qsub %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +#define __PKHBT(ARG1,ARG2,ARG3) \ +({ \ + uint32_t __RES, __ARG1 = (ARG1), __ARG2 = (ARG2); \ + __ASM ("pkhbt %0, %1, %2, lsl %3" : "=r" (__RES) : "r" (__ARG1), "r" (__ARG2), "I" (ARG3) ); \ + __RES; \ + }) + +#define __PKHTB(ARG1,ARG2,ARG3) \ +({ \ + uint32_t __RES, __ARG1 = (ARG1), __ARG2 = (ARG2); \ + if (ARG3 == 0) \ + __ASM ("pkhtb %0, %1, %2" : "=r" (__RES) : "r" (__ARG1), "r" (__ARG2) ); \ + else \ + __ASM ("pkhtb %0, %1, %2, asr %3" : "=r" (__RES) : "r" (__ARG1), "r" (__ARG2), "I" (ARG3) ); \ + __RES; \ + }) + +/*-- End CM4 SIMD Intrinsics -----------------------------------------------------*/ + + + +#elif defined ( __TASKING__ ) /*------------------ TASKING Compiler --------------*/ +/* TASKING carm specific functions */ + + +/*------ CM4 SIMD Intrinsics -----------------------------------------------------*/ +/* not yet supported */ +/*-- End CM4 SIMD Intrinsics -----------------------------------------------------*/ + + +#endif + +/*@} end of group CMSIS_SIMD_intrinsics */ + + +#endif /* __CORE_CM4_SIMD_H */ + +#ifdef __cplusplus +} +#endif diff --git a/Libraries/CMSIS/Include/core_cmFunc.h b/Libraries/CMSIS/Include/core_cmFunc.h new file mode 100644 index 0000000..3c932e0 --- /dev/null +++ b/Libraries/CMSIS/Include/core_cmFunc.h @@ -0,0 +1,616 @@ +/**************************************************************************//** + * @file core_cmFunc.h + * @brief CMSIS Cortex-M Core Function Access Header File + * @version V3.01 + * @date 06. March 2012 + * + * @note + * Copyright (C) 2009-2012 ARM Limited. All rights reserved. + * + * @par + * ARM Limited (ARM) is supplying this software for use with Cortex-M + * processor based microcontrollers. This file can be freely distributed + * within development tools that are supporting such ARM based processors. + * + * @par + * THIS SOFTWARE IS PROVIDED "AS IS". NO WARRANTIES, WHETHER EXPRESS, IMPLIED + * OR STATUTORY, INCLUDING, BUT NOT LIMITED TO, IMPLIED WARRANTIES OF + * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE APPLY TO THIS SOFTWARE. + * ARM SHALL NOT, IN ANY CIRCUMSTANCES, BE LIABLE FOR SPECIAL, INCIDENTAL, OR + * CONSEQUENTIAL DAMAGES, FOR ANY REASON WHATSOEVER. + * + ******************************************************************************/ + +#ifndef __CORE_CMFUNC_H +#define __CORE_CMFUNC_H + + +/* ########################### Core Function Access ########################### */ +/** \ingroup CMSIS_Core_FunctionInterface + \defgroup CMSIS_Core_RegAccFunctions CMSIS Core Register Access Functions + @{ + */ + +#if defined ( __CC_ARM ) /*------------------RealView Compiler -----------------*/ +/* ARM armcc specific functions */ + +#if (__ARMCC_VERSION < 400677) + #error "Please use ARM Compiler Toolchain V4.0.677 or later!" +#endif + +/* intrinsic void __enable_irq(); */ +/* intrinsic void __disable_irq(); */ + +/** \brief Get Control Register + + This function returns the content of the Control Register. + + \return Control Register value + */ +__STATIC_INLINE uint32_t __get_CONTROL(void) +{ + register uint32_t __regControl __ASM("control"); + return(__regControl); +} + + +/** \brief Set Control Register + + This function writes the given value to the Control Register. + + \param [in] control Control Register value to set + */ +__STATIC_INLINE void __set_CONTROL(uint32_t control) +{ + register uint32_t __regControl __ASM("control"); + __regControl = control; +} + + +/** \brief Get IPSR Register + + This function returns the content of the IPSR Register. + + \return IPSR Register value + */ +__STATIC_INLINE uint32_t __get_IPSR(void) +{ + register uint32_t __regIPSR __ASM("ipsr"); + return(__regIPSR); +} + + +/** \brief Get APSR Register + + This function returns the content of the APSR Register. + + \return APSR Register value + */ +__STATIC_INLINE uint32_t __get_APSR(void) +{ + register uint32_t __regAPSR __ASM("apsr"); + return(__regAPSR); +} + + +/** \brief Get xPSR Register + + This function returns the content of the xPSR Register. + + \return xPSR Register value + */ +__STATIC_INLINE uint32_t __get_xPSR(void) +{ + register uint32_t __regXPSR __ASM("xpsr"); + return(__regXPSR); +} + + +/** \brief Get Process Stack Pointer + + This function returns the current value of the Process Stack Pointer (PSP). + + \return PSP Register value + */ +__STATIC_INLINE uint32_t __get_PSP(void) +{ + register uint32_t __regProcessStackPointer __ASM("psp"); + return(__regProcessStackPointer); +} + + +/** \brief Set Process Stack Pointer + + This function assigns the given value to the Process Stack Pointer (PSP). + + \param [in] topOfProcStack Process Stack Pointer value to set + */ +__STATIC_INLINE void __set_PSP(uint32_t topOfProcStack) +{ + register uint32_t __regProcessStackPointer __ASM("psp"); + __regProcessStackPointer = topOfProcStack; +} + + +/** \brief Get Main Stack Pointer + + This function returns the current value of the Main Stack Pointer (MSP). + + \return MSP Register value + */ +__STATIC_INLINE uint32_t __get_MSP(void) +{ + register uint32_t __regMainStackPointer __ASM("msp"); + return(__regMainStackPointer); +} + + +/** \brief Set Main Stack Pointer + + This function assigns the given value to the Main Stack Pointer (MSP). + + \param [in] topOfMainStack Main Stack Pointer value to set + */ +__STATIC_INLINE void __set_MSP(uint32_t topOfMainStack) +{ + register uint32_t __regMainStackPointer __ASM("msp"); + __regMainStackPointer = topOfMainStack; +} + + +/** \brief Get Priority Mask + + This function returns the current state of the priority mask bit from the Priority Mask Register. + + \return Priority Mask value + */ +__STATIC_INLINE uint32_t __get_PRIMASK(void) +{ + register uint32_t __regPriMask __ASM("primask"); + return(__regPriMask); +} + + +/** \brief Set Priority Mask + + This function assigns the given value to the Priority Mask Register. + + \param [in] priMask Priority Mask + */ +__STATIC_INLINE void __set_PRIMASK(uint32_t priMask) +{ + register uint32_t __regPriMask __ASM("primask"); + __regPriMask = (priMask); +} + + +#if (__CORTEX_M >= 0x03) + +/** \brief Enable FIQ + + This function enables FIQ interrupts by clearing the F-bit in the CPSR. + Can only be executed in Privileged modes. + */ +#define __enable_fault_irq __enable_fiq + + +/** \brief Disable FIQ + + This function disables FIQ interrupts by setting the F-bit in the CPSR. + Can only be executed in Privileged modes. + */ +#define __disable_fault_irq __disable_fiq + + +/** \brief Get Base Priority + + This function returns the current value of the Base Priority register. + + \return Base Priority register value + */ +__STATIC_INLINE uint32_t __get_BASEPRI(void) +{ + register uint32_t __regBasePri __ASM("basepri"); + return(__regBasePri); +} + + +/** \brief Set Base Priority + + This function assigns the given value to the Base Priority register. + + \param [in] basePri Base Priority value to set + */ +__STATIC_INLINE void __set_BASEPRI(uint32_t basePri) +{ + register uint32_t __regBasePri __ASM("basepri"); + __regBasePri = (basePri & 0xff); +} + + +/** \brief Get Fault Mask + + This function returns the current value of the Fault Mask register. + + \return Fault Mask register value + */ +__STATIC_INLINE uint32_t __get_FAULTMASK(void) +{ + register uint32_t __regFaultMask __ASM("faultmask"); + return(__regFaultMask); +} + + +/** \brief Set Fault Mask + + This function assigns the given value to the Fault Mask register. + + \param [in] faultMask Fault Mask value to set + */ +__STATIC_INLINE void __set_FAULTMASK(uint32_t faultMask) +{ + register uint32_t __regFaultMask __ASM("faultmask"); + __regFaultMask = (faultMask & (uint32_t)1); +} + +#endif /* (__CORTEX_M >= 0x03) */ + + +#if (__CORTEX_M == 0x04) + +/** \brief Get FPSCR + + This function returns the current value of the Floating Point Status/Control register. + + \return Floating Point Status/Control register value + */ +__STATIC_INLINE uint32_t __get_FPSCR(void) +{ +#if (__FPU_PRESENT == 1) && (__FPU_USED == 1) + register uint32_t __regfpscr __ASM("fpscr"); + return(__regfpscr); +#else + return(0); +#endif +} + + +/** \brief Set FPSCR + + This function assigns the given value to the Floating Point Status/Control register. + + \param [in] fpscr Floating Point Status/Control value to set + */ +__STATIC_INLINE void __set_FPSCR(uint32_t fpscr) +{ +#if (__FPU_PRESENT == 1) && (__FPU_USED == 1) + register uint32_t __regfpscr __ASM("fpscr"); + __regfpscr = (fpscr); +#endif +} + +#endif /* (__CORTEX_M == 0x04) */ + + +#elif defined ( __ICCARM__ ) /*------------------ ICC Compiler -------------------*/ +/* IAR iccarm specific functions */ + +#include + + +#elif defined ( __TMS470__ ) /*---------------- TI CCS Compiler ------------------*/ +/* TI CCS specific functions */ + +#include + + +#elif defined ( __GNUC__ ) /*------------------ GNU Compiler ---------------------*/ +/* GNU gcc specific functions */ + +/** \brief Enable IRQ Interrupts + + This function enables IRQ interrupts by clearing the I-bit in the CPSR. + Can only be executed in Privileged modes. + */ +__attribute__( ( always_inline ) ) __STATIC_INLINE void __enable_irq(void) +{ + __ASM volatile ("cpsie i"); +} + + +/** \brief Disable IRQ Interrupts + + This function disables IRQ interrupts by setting the I-bit in the CPSR. + Can only be executed in Privileged modes. + */ +__attribute__( ( always_inline ) ) __STATIC_INLINE void __disable_irq(void) +{ + __ASM volatile ("cpsid i"); +} + + +/** \brief Get Control Register + + This function returns the content of the Control Register. + + \return Control Register value + */ +__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __get_CONTROL(void) +{ + uint32_t result; + + __ASM volatile ("MRS %0, control" : "=r" (result) ); + return(result); +} + + +/** \brief Set Control Register + + This function writes the given value to the Control Register. + + \param [in] control Control Register value to set + */ +__attribute__( ( always_inline ) ) __STATIC_INLINE void __set_CONTROL(uint32_t control) +{ + __ASM volatile ("MSR control, %0" : : "r" (control) ); +} + + +/** \brief Get IPSR Register + + This function returns the content of the IPSR Register. + + \return IPSR Register value + */ +__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __get_IPSR(void) +{ + uint32_t result; + + __ASM volatile ("MRS %0, ipsr" : "=r" (result) ); + return(result); +} + + +/** \brief Get APSR Register + + This function returns the content of the APSR Register. + + \return APSR Register value + */ +__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __get_APSR(void) +{ + uint32_t result; + + __ASM volatile ("MRS %0, apsr" : "=r" (result) ); + return(result); +} + + +/** \brief Get xPSR Register + + This function returns the content of the xPSR Register. + + \return xPSR Register value + */ +__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __get_xPSR(void) +{ + uint32_t result; + + __ASM volatile ("MRS %0, xpsr" : "=r" (result) ); + return(result); +} + + +/** \brief Get Process Stack Pointer + + This function returns the current value of the Process Stack Pointer (PSP). + + \return PSP Register value + */ +__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __get_PSP(void) +{ + register uint32_t result; + + __ASM volatile ("MRS %0, psp\n" : "=r" (result) ); + return(result); +} + + +/** \brief Set Process Stack Pointer + + This function assigns the given value to the Process Stack Pointer (PSP). + + \param [in] topOfProcStack Process Stack Pointer value to set + */ +__attribute__( ( always_inline ) ) __STATIC_INLINE void __set_PSP(uint32_t topOfProcStack) +{ + __ASM volatile ("MSR psp, %0\n" : : "r" (topOfProcStack) ); +} + + +/** \brief Get Main Stack Pointer + + This function returns the current value of the Main Stack Pointer (MSP). + + \return MSP Register value + */ +__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __get_MSP(void) +{ + register uint32_t result; + + __ASM volatile ("MRS %0, msp\n" : "=r" (result) ); + return(result); +} + + +/** \brief Set Main Stack Pointer + + This function assigns the given value to the Main Stack Pointer (MSP). + + \param [in] topOfMainStack Main Stack Pointer value to set + */ +__attribute__( ( always_inline ) ) __STATIC_INLINE void __set_MSP(uint32_t topOfMainStack) +{ + __ASM volatile ("MSR msp, %0\n" : : "r" (topOfMainStack) ); +} + + +/** \brief Get Priority Mask + + This function returns the current state of the priority mask bit from the Priority Mask Register. + + \return Priority Mask value + */ +__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __get_PRIMASK(void) +{ + uint32_t result; + + __ASM volatile ("MRS %0, primask" : "=r" (result) ); + return(result); +} + + +/** \brief Set Priority Mask + + This function assigns the given value to the Priority Mask Register. + + \param [in] priMask Priority Mask + */ +__attribute__( ( always_inline ) ) __STATIC_INLINE void __set_PRIMASK(uint32_t priMask) +{ + __ASM volatile ("MSR primask, %0" : : "r" (priMask) ); +} + + +#if (__CORTEX_M >= 0x03) + +/** \brief Enable FIQ + + This function enables FIQ interrupts by clearing the F-bit in the CPSR. + Can only be executed in Privileged modes. + */ +__attribute__( ( always_inline ) ) __STATIC_INLINE void __enable_fault_irq(void) +{ + __ASM volatile ("cpsie f"); +} + + +/** \brief Disable FIQ + + This function disables FIQ interrupts by setting the F-bit in the CPSR. + Can only be executed in Privileged modes. + */ +__attribute__( ( always_inline ) ) __STATIC_INLINE void __disable_fault_irq(void) +{ + __ASM volatile ("cpsid f"); +} + + +/** \brief Get Base Priority + + This function returns the current value of the Base Priority register. + + \return Base Priority register value + */ +__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __get_BASEPRI(void) +{ + uint32_t result; + + __ASM volatile ("MRS %0, basepri_max" : "=r" (result) ); + return(result); +} + + +/** \brief Set Base Priority + + This function assigns the given value to the Base Priority register. + + \param [in] basePri Base Priority value to set + */ +__attribute__( ( always_inline ) ) __STATIC_INLINE void __set_BASEPRI(uint32_t value) +{ + __ASM volatile ("MSR basepri, %0" : : "r" (value) ); +} + + +/** \brief Get Fault Mask + + This function returns the current value of the Fault Mask register. + + \return Fault Mask register value + */ +__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __get_FAULTMASK(void) +{ + uint32_t result; + + __ASM volatile ("MRS %0, faultmask" : "=r" (result) ); + return(result); +} + + +/** \brief Set Fault Mask + + This function assigns the given value to the Fault Mask register. + + \param [in] faultMask Fault Mask value to set + */ +__attribute__( ( always_inline ) ) __STATIC_INLINE void __set_FAULTMASK(uint32_t faultMask) +{ + __ASM volatile ("MSR faultmask, %0" : : "r" (faultMask) ); +} + +#endif /* (__CORTEX_M >= 0x03) */ + + +#if (__CORTEX_M == 0x04) + +/** \brief Get FPSCR + + This function returns the current value of the Floating Point Status/Control register. + + \return Floating Point Status/Control register value + */ +__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __get_FPSCR(void) +{ +#if (__FPU_PRESENT == 1) && (__FPU_USED == 1) + uint32_t result; + + __ASM volatile ("VMRS %0, fpscr" : "=r" (result) ); + return(result); +#else + return(0); +#endif +} + + +/** \brief Set FPSCR + + This function assigns the given value to the Floating Point Status/Control register. + + \param [in] fpscr Floating Point Status/Control value to set + */ +__attribute__( ( always_inline ) ) __STATIC_INLINE void __set_FPSCR(uint32_t fpscr) +{ +#if (__FPU_PRESENT == 1) && (__FPU_USED == 1) + __ASM volatile ("VMSR fpscr, %0" : : "r" (fpscr) ); +#endif +} + +#endif /* (__CORTEX_M == 0x04) */ + + +#elif defined ( __TASKING__ ) /*------------------ TASKING Compiler --------------*/ +/* TASKING carm specific functions */ + +/* + * The CMSIS functions have been implemented as intrinsics in the compiler. + * Please use "carm -?i" to get an up to date list of all instrinsics, + * Including the CMSIS ones. + */ + +#endif + +/*@} end of CMSIS_Core_RegAccFunctions */ + + +#endif /* __CORE_CMFUNC_H */ diff --git a/Libraries/CMSIS/Include/core_cmInstr.h b/Libraries/CMSIS/Include/core_cmInstr.h new file mode 100644 index 0000000..597e64d --- /dev/null +++ b/Libraries/CMSIS/Include/core_cmInstr.h @@ -0,0 +1,618 @@ +/**************************************************************************//** + * @file core_cmInstr.h + * @brief CMSIS Cortex-M Core Instruction Access Header File + * @version V3.01 + * @date 06. March 2012 + * + * @note + * Copyright (C) 2009-2012 ARM Limited. All rights reserved. + * + * @par + * ARM Limited (ARM) is supplying this software for use with Cortex-M + * processor based microcontrollers. This file can be freely distributed + * within development tools that are supporting such ARM based processors. + * + * @par + * THIS SOFTWARE IS PROVIDED "AS IS". NO WARRANTIES, WHETHER EXPRESS, IMPLIED + * OR STATUTORY, INCLUDING, BUT NOT LIMITED TO, IMPLIED WARRANTIES OF + * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE APPLY TO THIS SOFTWARE. + * ARM SHALL NOT, IN ANY CIRCUMSTANCES, BE LIABLE FOR SPECIAL, INCIDENTAL, OR + * CONSEQUENTIAL DAMAGES, FOR ANY REASON WHATSOEVER. + * + ******************************************************************************/ + +#ifndef __CORE_CMINSTR_H +#define __CORE_CMINSTR_H + + +/* ########################## Core Instruction Access ######################### */ +/** \defgroup CMSIS_Core_InstructionInterface CMSIS Core Instruction Interface + Access to dedicated instructions + @{ +*/ + +#if defined ( __CC_ARM ) /*------------------RealView Compiler -----------------*/ +/* ARM armcc specific functions */ + +#if (__ARMCC_VERSION < 400677) + #error "Please use ARM Compiler Toolchain V4.0.677 or later!" +#endif + + +/** \brief No Operation + + No Operation does nothing. This instruction can be used for code alignment purposes. + */ +#define __NOP __nop + + +/** \brief Wait For Interrupt + + Wait For Interrupt is a hint instruction that suspends execution + until one of a number of events occurs. + */ +#define __WFI __wfi + + +/** \brief Wait For Event + + Wait For Event is a hint instruction that permits the processor to enter + a low-power state until one of a number of events occurs. + */ +#define __WFE __wfe + + +/** \brief Send Event + + Send Event is a hint instruction. It causes an event to be signaled to the CPU. + */ +#define __SEV __sev + + +/** \brief Instruction Synchronization Barrier + + Instruction Synchronization Barrier flushes the pipeline in the processor, + so that all instructions following the ISB are fetched from cache or + memory, after the instruction has been completed. + */ +#define __ISB() __isb(0xF) + + +/** \brief Data Synchronization Barrier + + This function acts as a special kind of Data Memory Barrier. + It completes when all explicit memory accesses before this instruction complete. + */ +#define __DSB() __dsb(0xF) + + +/** \brief Data Memory Barrier + + This function ensures the apparent order of the explicit memory operations before + and after the instruction, without ensuring their completion. + */ +#define __DMB() __dmb(0xF) + + +/** \brief Reverse byte order (32 bit) + + This function reverses the byte order in integer value. + + \param [in] value Value to reverse + \return Reversed value + */ +#define __REV __rev + + +/** \brief Reverse byte order (16 bit) + + This function reverses the byte order in two unsigned short values. + + \param [in] value Value to reverse + \return Reversed value + */ +__attribute__((section(".rev16_text"))) __STATIC_INLINE __ASM uint32_t __REV16(uint32_t value) +{ + rev16 r0, r0 + bx lr +} + + +/** \brief Reverse byte order in signed short value + + This function reverses the byte order in a signed short value with sign extension to integer. + + \param [in] value Value to reverse + \return Reversed value + */ +__attribute__((section(".revsh_text"))) __STATIC_INLINE __ASM int32_t __REVSH(int32_t value) +{ + revsh r0, r0 + bx lr +} + + +/** \brief Rotate Right in unsigned value (32 bit) + + This function Rotate Right (immediate) provides the value of the contents of a register rotated by a variable number of bits. + + \param [in] value Value to rotate + \param [in] value Number of Bits to rotate + \return Rotated value + */ +#define __ROR __ror + + +#if (__CORTEX_M >= 0x03) + +/** \brief Reverse bit order of value + + This function reverses the bit order of the given value. + + \param [in] value Value to reverse + \return Reversed value + */ +#define __RBIT __rbit + + +/** \brief LDR Exclusive (8 bit) + + This function performs a exclusive LDR command for 8 bit value. + + \param [in] ptr Pointer to data + \return value of type uint8_t at (*ptr) + */ +#define __LDREXB(ptr) ((uint8_t ) __ldrex(ptr)) + + +/** \brief LDR Exclusive (16 bit) + + This function performs a exclusive LDR command for 16 bit values. + + \param [in] ptr Pointer to data + \return value of type uint16_t at (*ptr) + */ +#define __LDREXH(ptr) ((uint16_t) __ldrex(ptr)) + + +/** \brief LDR Exclusive (32 bit) + + This function performs a exclusive LDR command for 32 bit values. + + \param [in] ptr Pointer to data + \return value of type uint32_t at (*ptr) + */ +#define __LDREXW(ptr) ((uint32_t ) __ldrex(ptr)) + + +/** \brief STR Exclusive (8 bit) + + This function performs a exclusive STR command for 8 bit values. + + \param [in] value Value to store + \param [in] ptr Pointer to location + \return 0 Function succeeded + \return 1 Function failed + */ +#define __STREXB(value, ptr) __strex(value, ptr) + + +/** \brief STR Exclusive (16 bit) + + This function performs a exclusive STR command for 16 bit values. + + \param [in] value Value to store + \param [in] ptr Pointer to location + \return 0 Function succeeded + \return 1 Function failed + */ +#define __STREXH(value, ptr) __strex(value, ptr) + + +/** \brief STR Exclusive (32 bit) + + This function performs a exclusive STR command for 32 bit values. + + \param [in] value Value to store + \param [in] ptr Pointer to location + \return 0 Function succeeded + \return 1 Function failed + */ +#define __STREXW(value, ptr) __strex(value, ptr) + + +/** \brief Remove the exclusive lock + + This function removes the exclusive lock which is created by LDREX. + + */ +#define __CLREX __clrex + + +/** \brief Signed Saturate + + This function saturates a signed value. + + \param [in] value Value to be saturated + \param [in] sat Bit position to saturate to (1..32) + \return Saturated value + */ +#define __SSAT __ssat + + +/** \brief Unsigned Saturate + + This function saturates an unsigned value. + + \param [in] value Value to be saturated + \param [in] sat Bit position to saturate to (0..31) + \return Saturated value + */ +#define __USAT __usat + + +/** \brief Count leading zeros + + This function counts the number of leading zeros of a data value. + + \param [in] value Value to count the leading zeros + \return number of leading zeros in value + */ +#define __CLZ __clz + +#endif /* (__CORTEX_M >= 0x03) */ + + + +#elif defined ( __ICCARM__ ) /*------------------ ICC Compiler -------------------*/ +/* IAR iccarm specific functions */ + +#include + + +#elif defined ( __TMS470__ ) /*---------------- TI CCS Compiler ------------------*/ +/* TI CCS specific functions */ + +#include + + +#elif defined ( __GNUC__ ) /*------------------ GNU Compiler ---------------------*/ +/* GNU gcc specific functions */ + +/** \brief No Operation + + No Operation does nothing. This instruction can be used for code alignment purposes. + */ +__attribute__( ( always_inline ) ) __STATIC_INLINE void __NOP(void) +{ + __ASM volatile ("nop"); +} + + +/** \brief Wait For Interrupt + + Wait For Interrupt is a hint instruction that suspends execution + until one of a number of events occurs. + */ +__attribute__( ( always_inline ) ) __STATIC_INLINE void __WFI(void) +{ + __ASM volatile ("wfi"); +} + + +/** \brief Wait For Event + + Wait For Event is a hint instruction that permits the processor to enter + a low-power state until one of a number of events occurs. + */ +__attribute__( ( always_inline ) ) __STATIC_INLINE void __WFE(void) +{ + __ASM volatile ("wfe"); +} + + +/** \brief Send Event + + Send Event is a hint instruction. It causes an event to be signaled to the CPU. + */ +__attribute__( ( always_inline ) ) __STATIC_INLINE void __SEV(void) +{ + __ASM volatile ("sev"); +} + + +/** \brief Instruction Synchronization Barrier + + Instruction Synchronization Barrier flushes the pipeline in the processor, + so that all instructions following the ISB are fetched from cache or + memory, after the instruction has been completed. + */ +__attribute__( ( always_inline ) ) __STATIC_INLINE void __ISB(void) +{ + __ASM volatile ("isb"); +} + + +/** \brief Data Synchronization Barrier + + This function acts as a special kind of Data Memory Barrier. + It completes when all explicit memory accesses before this instruction complete. + */ +__attribute__( ( always_inline ) ) __STATIC_INLINE void __DSB(void) +{ + __ASM volatile ("dsb"); +} + + +/** \brief Data Memory Barrier + + This function ensures the apparent order of the explicit memory operations before + and after the instruction, without ensuring their completion. + */ +__attribute__( ( always_inline ) ) __STATIC_INLINE void __DMB(void) +{ + __ASM volatile ("dmb"); +} + + +/** \brief Reverse byte order (32 bit) + + This function reverses the byte order in integer value. + + \param [in] value Value to reverse + \return Reversed value + */ +__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __REV(uint32_t value) +{ + uint32_t result; + + __ASM volatile ("rev %0, %1" : "=r" (result) : "r" (value) ); + return(result); +} + + +/** \brief Reverse byte order (16 bit) + + This function reverses the byte order in two unsigned short values. + + \param [in] value Value to reverse + \return Reversed value + */ +__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __REV16(uint32_t value) +{ + uint32_t result; + + __ASM volatile ("rev16 %0, %1" : "=r" (result) : "r" (value) ); + return(result); +} + + +/** \brief Reverse byte order in signed short value + + This function reverses the byte order in a signed short value with sign extension to integer. + + \param [in] value Value to reverse + \return Reversed value + */ +__attribute__( ( always_inline ) ) __STATIC_INLINE int32_t __REVSH(int32_t value) +{ + uint32_t result; + + __ASM volatile ("revsh %0, %1" : "=r" (result) : "r" (value) ); + return(result); +} + + +/** \brief Rotate Right in unsigned value (32 bit) + + This function Rotate Right (immediate) provides the value of the contents of a register rotated by a variable number of bits. + + \param [in] value Value to rotate + \param [in] value Number of Bits to rotate + \return Rotated value + */ +__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __ROR(uint32_t op1, uint32_t op2) +{ + + __ASM volatile ("ror %0, %0, %1" : "+r" (op1) : "r" (op2) ); + return(op1); +} + + +#if (__CORTEX_M >= 0x03) + +/** \brief Reverse bit order of value + + This function reverses the bit order of the given value. + + \param [in] value Value to reverse + \return Reversed value + */ +__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __RBIT(uint32_t value) +{ + uint32_t result; + + __ASM volatile ("rbit %0, %1" : "=r" (result) : "r" (value) ); + return(result); +} + + +/** \brief LDR Exclusive (8 bit) + + This function performs a exclusive LDR command for 8 bit value. + + \param [in] ptr Pointer to data + \return value of type uint8_t at (*ptr) + */ +__attribute__( ( always_inline ) ) __STATIC_INLINE uint8_t __LDREXB(volatile uint8_t *addr) +{ + uint8_t result; + + __ASM volatile ("ldrexb %0, [%1]" : "=r" (result) : "r" (addr) ); + return(result); +} + + +/** \brief LDR Exclusive (16 bit) + + This function performs a exclusive LDR command for 16 bit values. + + \param [in] ptr Pointer to data + \return value of type uint16_t at (*ptr) + */ +__attribute__( ( always_inline ) ) __STATIC_INLINE uint16_t __LDREXH(volatile uint16_t *addr) +{ + uint16_t result; + + __ASM volatile ("ldrexh %0, [%1]" : "=r" (result) : "r" (addr) ); + return(result); +} + + +/** \brief LDR Exclusive (32 bit) + + This function performs a exclusive LDR command for 32 bit values. + + \param [in] ptr Pointer to data + \return value of type uint32_t at (*ptr) + */ +__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __LDREXW(volatile uint32_t *addr) +{ + uint32_t result; + + __ASM volatile ("ldrex %0, [%1]" : "=r" (result) : "r" (addr) ); + return(result); +} + + +/** \brief STR Exclusive (8 bit) + + This function performs a exclusive STR command for 8 bit values. + + \param [in] value Value to store + \param [in] ptr Pointer to location + \return 0 Function succeeded + \return 1 Function failed + */ +__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __STREXB(uint8_t value, volatile uint8_t *addr) +{ + uint32_t result; + + __ASM volatile ("strexb %0, %2, [%1]" : "=&r" (result) : "r" (addr), "r" (value) ); + return(result); +} + + +/** \brief STR Exclusive (16 bit) + + This function performs a exclusive STR command for 16 bit values. + + \param [in] value Value to store + \param [in] ptr Pointer to location + \return 0 Function succeeded + \return 1 Function failed + */ +__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __STREXH(uint16_t value, volatile uint16_t *addr) +{ + uint32_t result; + + __ASM volatile ("strexh %0, %2, [%1]" : "=&r" (result) : "r" (addr), "r" (value) ); + return(result); +} + + +/** \brief STR Exclusive (32 bit) + + This function performs a exclusive STR command for 32 bit values. + + \param [in] value Value to store + \param [in] ptr Pointer to location + \return 0 Function succeeded + \return 1 Function failed + */ +__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __STREXW(uint32_t value, volatile uint32_t *addr) +{ + uint32_t result; + + __ASM volatile ("strex %0, %2, [%1]" : "=&r" (result) : "r" (addr), "r" (value) ); + return(result); +} + + +/** \brief Remove the exclusive lock + + This function removes the exclusive lock which is created by LDREX. + + */ +__attribute__( ( always_inline ) ) __STATIC_INLINE void __CLREX(void) +{ + __ASM volatile ("clrex"); +} + + +/** \brief Signed Saturate + + This function saturates a signed value. + + \param [in] value Value to be saturated + \param [in] sat Bit position to saturate to (1..32) + \return Saturated value + */ +#define __SSAT(ARG1,ARG2) \ +({ \ + uint32_t __RES, __ARG1 = (ARG1); \ + __ASM ("ssat %0, %1, %2" : "=r" (__RES) : "I" (ARG2), "r" (__ARG1) ); \ + __RES; \ + }) + + +/** \brief Unsigned Saturate + + This function saturates an unsigned value. + + \param [in] value Value to be saturated + \param [in] sat Bit position to saturate to (0..31) + \return Saturated value + */ +#define __USAT(ARG1,ARG2) \ +({ \ + uint32_t __RES, __ARG1 = (ARG1); \ + __ASM ("usat %0, %1, %2" : "=r" (__RES) : "I" (ARG2), "r" (__ARG1) ); \ + __RES; \ + }) + + +/** \brief Count leading zeros + + This function counts the number of leading zeros of a data value. + + \param [in] value Value to count the leading zeros + \return number of leading zeros in value + */ +__attribute__( ( always_inline ) ) __STATIC_INLINE uint8_t __CLZ(uint32_t value) +{ + uint8_t result; + + __ASM volatile ("clz %0, %1" : "=r" (result) : "r" (value) ); + return(result); +} + +#endif /* (__CORTEX_M >= 0x03) */ + + + + +#elif defined ( __TASKING__ ) /*------------------ TASKING Compiler --------------*/ +/* TASKING carm specific functions */ + +/* + * The CMSIS functions have been implemented as intrinsics in the compiler. + * Please use "carm -?i" to get an up to date list of all intrinsics, + * Including the CMSIS ones. + */ + +#endif + +/*@}*/ /* end of group CMSIS_Core_InstructionInterface */ + +#endif /* __CORE_CMINSTR_H */ diff --git a/Libraries/CMSIS/Include/core_sc000.h b/Libraries/CMSIS/Include/core_sc000.h new file mode 100644 index 0000000..39ee60c --- /dev/null +++ b/Libraries/CMSIS/Include/core_sc000.h @@ -0,0 +1,798 @@ +/**************************************************************************//** + * @file core_sc000.h + * @brief CMSIS SC000 Core Peripheral Access Layer Header File + * @version V3.01 + * @date 22. March 2012 + * + * @note + * Copyright (C) 2009-2012 ARM Limited. All rights reserved. + * + * @par + * ARM Limited (ARM) is supplying this software for use with Cortex-M + * processor based microcontrollers. This file can be freely distributed + * within development tools that are supporting such ARM based processors. + * + * @par + * THIS SOFTWARE IS PROVIDED "AS IS". NO WARRANTIES, WHETHER EXPRESS, IMPLIED + * OR STATUTORY, INCLUDING, BUT NOT LIMITED TO, IMPLIED WARRANTIES OF + * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE APPLY TO THIS SOFTWARE. + * ARM SHALL NOT, IN ANY CIRCUMSTANCES, BE LIABLE FOR SPECIAL, INCIDENTAL, OR + * CONSEQUENTIAL DAMAGES, FOR ANY REASON WHATSOEVER. + * + ******************************************************************************/ +#if defined ( __ICCARM__ ) + #pragma system_include /* treat file as system include file for MISRA check */ +#endif + +#ifdef __cplusplus + extern "C" { +#endif + +#ifndef __CORE_SC000_H_GENERIC +#define __CORE_SC000_H_GENERIC + +/** \page CMSIS_MISRA_Exceptions MISRA-C:2004 Compliance Exceptions + CMSIS violates the following MISRA-C:2004 rules: + + \li Required Rule 8.5, object/function definition in header file.
    + Function definitions in header files are used to allow 'inlining'. + + \li Required Rule 18.4, declaration of union type or object of union type: '{...}'.
    + Unions are used for effective representation of core registers. + + \li Advisory Rule 19.7, Function-like macro defined.
    + Function-like macros are used to allow more efficient code. + */ + + +/******************************************************************************* + * CMSIS definitions + ******************************************************************************/ +/** \ingroup SC000 + @{ + */ + +/* CMSIS SC000 definitions */ +#define __SC000_CMSIS_VERSION_MAIN (0x03) /*!< [31:16] CMSIS HAL main version */ +#define __SC000_CMSIS_VERSION_SUB (0x01) /*!< [15:0] CMSIS HAL sub version */ +#define __SC000_CMSIS_VERSION ((__SC000_CMSIS_VERSION_MAIN << 16) | \ + __SC000_CMSIS_VERSION_SUB ) /*!< CMSIS HAL version number */ + +#define __CORTEX_SC (0) /*!< Cortex secure core */ + + +#if defined ( __CC_ARM ) + #define __ASM __asm /*!< asm keyword for ARM Compiler */ + #define __INLINE __inline /*!< inline keyword for ARM Compiler */ + #define __STATIC_INLINE static __inline + +#elif defined ( __ICCARM__ ) + #define __ASM __asm /*!< asm keyword for IAR Compiler */ + #define __INLINE inline /*!< inline keyword for IAR Compiler. Only available in High optimization mode! */ + #define __STATIC_INLINE static inline + +#elif defined ( __GNUC__ ) + #define __ASM __asm /*!< asm keyword for GNU Compiler */ + #define __INLINE inline /*!< inline keyword for GNU Compiler */ + #define __STATIC_INLINE static inline + +#elif defined ( __TASKING__ ) + #define __ASM __asm /*!< asm keyword for TASKING Compiler */ + #define __INLINE inline /*!< inline keyword for TASKING Compiler */ + #define __STATIC_INLINE static inline + +#endif + +/** __FPU_USED indicates whether an FPU is used or not. This core does not support an FPU at all +*/ +#define __FPU_USED 0 + +#if defined ( __CC_ARM ) + #if defined __TARGET_FPU_VFP + #warning "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #endif + +#elif defined ( __ICCARM__ ) + #if defined __ARMVFP__ + #warning "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #endif + +#elif defined ( __GNUC__ ) + #if defined (__VFP_FP__) && !defined(__SOFTFP__) + #warning "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #endif + +#elif defined ( __TASKING__ ) + #if defined __FPU_VFP__ + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #endif +#endif + +#include /* standard types definitions */ +#include /* Core Instruction Access */ +#include /* Core Function Access */ + +#endif /* __CORE_SC000_H_GENERIC */ + +#ifndef __CMSIS_GENERIC + +#ifndef __CORE_SC000_H_DEPENDANT +#define __CORE_SC000_H_DEPENDANT + +/* check device defines and use defaults */ +#if defined __CHECK_DEVICE_DEFINES + #ifndef __SC000_REV + #define __SC000_REV 0x0000 + #warning "__SC000_REV not defined in device header file; using default!" + #endif + + #ifndef __MPU_PRESENT + #define __MPU_PRESENT 0 + #warning "__MPU_PRESENT not defined in device header file; using default!" + #endif + + #ifndef __NVIC_PRIO_BITS + #define __NVIC_PRIO_BITS 2 + #warning "__NVIC_PRIO_BITS not defined in device header file; using default!" + #endif + + #ifndef __Vendor_SysTickConfig + #define __Vendor_SysTickConfig 0 + #warning "__Vendor_SysTickConfig not defined in device header file; using default!" + #endif +#endif + +/* IO definitions (access restrictions to peripheral registers) */ +/** + \defgroup CMSIS_glob_defs CMSIS Global Defines + + IO Type Qualifiers are used + \li to specify the access to peripheral variables. + \li for automatic generation of peripheral register debug information. +*/ +#ifdef __cplusplus + #define __I volatile /*!< Defines 'read only' permissions */ +#else + #define __I volatile const /*!< Defines 'read only' permissions */ +#endif +#define __O volatile /*!< Defines 'write only' permissions */ +#define __IO volatile /*!< Defines 'read / write' permissions */ + +/*@} end of group SC000 */ + + + +/******************************************************************************* + * Register Abstraction + Core Register contain: + - Core Register + - Core NVIC Register + - Core SCB Register + - Core SysTick Register + - Core MPU Register + ******************************************************************************/ +/** \defgroup CMSIS_core_register Defines and Type Definitions + \brief Type definitions and defines for Cortex-M processor based devices. +*/ + +/** \ingroup CMSIS_core_register + \defgroup CMSIS_CORE Status and Control Registers + \brief Core Register type definitions. + @{ + */ + +/** \brief Union type to access the Application Program Status Register (APSR). + */ +typedef union +{ + struct + { +#if (__CORTEX_M != 0x04) + uint32_t _reserved0:27; /*!< bit: 0..26 Reserved */ +#else + uint32_t _reserved0:16; /*!< bit: 0..15 Reserved */ + uint32_t GE:4; /*!< bit: 16..19 Greater than or Equal flags */ + uint32_t _reserved1:7; /*!< bit: 20..26 Reserved */ +#endif + uint32_t Q:1; /*!< bit: 27 Saturation condition flag */ + uint32_t V:1; /*!< bit: 28 Overflow condition code flag */ + uint32_t C:1; /*!< bit: 29 Carry condition code flag */ + uint32_t Z:1; /*!< bit: 30 Zero condition code flag */ + uint32_t N:1; /*!< bit: 31 Negative condition code flag */ + } b; /*!< Structure used for bit access */ + uint32_t w; /*!< Type used for word access */ +} APSR_Type; + + +/** \brief Union type to access the Interrupt Program Status Register (IPSR). + */ +typedef union +{ + struct + { + uint32_t ISR:9; /*!< bit: 0.. 8 Exception number */ + uint32_t _reserved0:23; /*!< bit: 9..31 Reserved */ + } b; /*!< Structure used for bit access */ + uint32_t w; /*!< Type used for word access */ +} IPSR_Type; + + +/** \brief Union type to access the Special-Purpose Program Status Registers (xPSR). + */ +typedef union +{ + struct + { + uint32_t ISR:9; /*!< bit: 0.. 8 Exception number */ +#if (__CORTEX_M != 0x04) + uint32_t _reserved0:15; /*!< bit: 9..23 Reserved */ +#else + uint32_t _reserved0:7; /*!< bit: 9..15 Reserved */ + uint32_t GE:4; /*!< bit: 16..19 Greater than or Equal flags */ + uint32_t _reserved1:4; /*!< bit: 20..23 Reserved */ +#endif + uint32_t T:1; /*!< bit: 24 Thumb bit (read 0) */ + uint32_t IT:2; /*!< bit: 25..26 saved IT state (read 0) */ + uint32_t Q:1; /*!< bit: 27 Saturation condition flag */ + uint32_t V:1; /*!< bit: 28 Overflow condition code flag */ + uint32_t C:1; /*!< bit: 29 Carry condition code flag */ + uint32_t Z:1; /*!< bit: 30 Zero condition code flag */ + uint32_t N:1; /*!< bit: 31 Negative condition code flag */ + } b; /*!< Structure used for bit access */ + uint32_t w; /*!< Type used for word access */ +} xPSR_Type; + + +/** \brief Union type to access the Control Registers (CONTROL). + */ +typedef union +{ + struct + { + uint32_t nPRIV:1; /*!< bit: 0 Execution privilege in Thread mode */ + uint32_t SPSEL:1; /*!< bit: 1 Stack to be used */ + uint32_t FPCA:1; /*!< bit: 2 FP extension active flag */ + uint32_t _reserved0:29; /*!< bit: 3..31 Reserved */ + } b; /*!< Structure used for bit access */ + uint32_t w; /*!< Type used for word access */ +} CONTROL_Type; + +/*@} end of group CMSIS_CORE */ + + +/** \ingroup CMSIS_core_register + \defgroup CMSIS_NVIC Nested Vectored Interrupt Controller (NVIC) + \brief Type definitions for the NVIC Registers + @{ + */ + +/** \brief Structure type to access the Nested Vectored Interrupt Controller (NVIC). + */ +typedef struct +{ + __IO uint32_t ISER[1]; /*!< Offset: 0x000 (R/W) Interrupt Set Enable Register */ + uint32_t RESERVED0[31]; + __IO uint32_t ICER[1]; /*!< Offset: 0x080 (R/W) Interrupt Clear Enable Register */ + uint32_t RSERVED1[31]; + __IO uint32_t ISPR[1]; /*!< Offset: 0x100 (R/W) Interrupt Set Pending Register */ + uint32_t RESERVED2[31]; + __IO uint32_t ICPR[1]; /*!< Offset: 0x180 (R/W) Interrupt Clear Pending Register */ + uint32_t RESERVED3[31]; + uint32_t RESERVED4[64]; + __IO uint32_t IP[8]; /*!< Offset: 0x300 (R/W) Interrupt Priority Register */ +} NVIC_Type; + +/*@} end of group CMSIS_NVIC */ + + +/** \ingroup CMSIS_core_register + \defgroup CMSIS_SCB System Control Block (SCB) + \brief Type definitions for the System Control Block Registers + @{ + */ + +/** \brief Structure type to access the System Control Block (SCB). + */ +typedef struct +{ + __I uint32_t CPUID; /*!< Offset: 0x000 (R/ ) CPUID Base Register */ + __IO uint32_t ICSR; /*!< Offset: 0x004 (R/W) Interrupt Control and State Register */ + __IO uint32_t VTOR; /*!< Offset: 0x008 (R/W) Vector Table Offset Register */ + __IO uint32_t AIRCR; /*!< Offset: 0x00C (R/W) Application Interrupt and Reset Control Register */ + __IO uint32_t SCR; /*!< Offset: 0x010 (R/W) System Control Register */ + __IO uint32_t CCR; /*!< Offset: 0x014 (R/W) Configuration Control Register */ + uint32_t RESERVED0[1]; + __IO uint32_t SHP[2]; /*!< Offset: 0x01C (R/W) System Handlers Priority Registers. [0] is RESERVED */ + __IO uint32_t SHCSR; /*!< Offset: 0x024 (R/W) System Handler Control and State Register */ + uint32_t RESERVED1[154]; + __IO uint32_t SFCR; /*!< Offset: 0x290 (R/W) Security Features Register */ +} SCB_Type; + +/* SCB CPUID Register Definitions */ +#define SCB_CPUID_IMPLEMENTER_Pos 24 /*!< SCB CPUID: IMPLEMENTER Position */ +#define SCB_CPUID_IMPLEMENTER_Msk (0xFFUL << SCB_CPUID_IMPLEMENTER_Pos) /*!< SCB CPUID: IMPLEMENTER Mask */ + +#define SCB_CPUID_VARIANT_Pos 20 /*!< SCB CPUID: VARIANT Position */ +#define SCB_CPUID_VARIANT_Msk (0xFUL << SCB_CPUID_VARIANT_Pos) /*!< SCB CPUID: VARIANT Mask */ + +#define SCB_CPUID_ARCHITECTURE_Pos 16 /*!< SCB CPUID: ARCHITECTURE Position */ +#define SCB_CPUID_ARCHITECTURE_Msk (0xFUL << SCB_CPUID_ARCHITECTURE_Pos) /*!< SCB CPUID: ARCHITECTURE Mask */ + +#define SCB_CPUID_PARTNO_Pos 4 /*!< SCB CPUID: PARTNO Position */ +#define SCB_CPUID_PARTNO_Msk (0xFFFUL << SCB_CPUID_PARTNO_Pos) /*!< SCB CPUID: PARTNO Mask */ + +#define SCB_CPUID_REVISION_Pos 0 /*!< SCB CPUID: REVISION Position */ +#define SCB_CPUID_REVISION_Msk (0xFUL << SCB_CPUID_REVISION_Pos) /*!< SCB CPUID: REVISION Mask */ + +/* SCB Interrupt Control State Register Definitions */ +#define SCB_ICSR_NMIPENDSET_Pos 31 /*!< SCB ICSR: NMIPENDSET Position */ +#define SCB_ICSR_NMIPENDSET_Msk (1UL << SCB_ICSR_NMIPENDSET_Pos) /*!< SCB ICSR: NMIPENDSET Mask */ + +#define SCB_ICSR_PENDSVSET_Pos 28 /*!< SCB ICSR: PENDSVSET Position */ +#define SCB_ICSR_PENDSVSET_Msk (1UL << SCB_ICSR_PENDSVSET_Pos) /*!< SCB ICSR: PENDSVSET Mask */ + +#define SCB_ICSR_PENDSVCLR_Pos 27 /*!< SCB ICSR: PENDSVCLR Position */ +#define SCB_ICSR_PENDSVCLR_Msk (1UL << SCB_ICSR_PENDSVCLR_Pos) /*!< SCB ICSR: PENDSVCLR Mask */ + +#define SCB_ICSR_PENDSTSET_Pos 26 /*!< SCB ICSR: PENDSTSET Position */ +#define SCB_ICSR_PENDSTSET_Msk (1UL << SCB_ICSR_PENDSTSET_Pos) /*!< SCB ICSR: PENDSTSET Mask */ + +#define SCB_ICSR_PENDSTCLR_Pos 25 /*!< SCB ICSR: PENDSTCLR Position */ +#define SCB_ICSR_PENDSTCLR_Msk (1UL << SCB_ICSR_PENDSTCLR_Pos) /*!< SCB ICSR: PENDSTCLR Mask */ + +#define SCB_ICSR_ISRPREEMPT_Pos 23 /*!< SCB ICSR: ISRPREEMPT Position */ +#define SCB_ICSR_ISRPREEMPT_Msk (1UL << SCB_ICSR_ISRPREEMPT_Pos) /*!< SCB ICSR: ISRPREEMPT Mask */ + +#define SCB_ICSR_ISRPENDING_Pos 22 /*!< SCB ICSR: ISRPENDING Position */ +#define SCB_ICSR_ISRPENDING_Msk (1UL << SCB_ICSR_ISRPENDING_Pos) /*!< SCB ICSR: ISRPENDING Mask */ + +#define SCB_ICSR_VECTPENDING_Pos 12 /*!< SCB ICSR: VECTPENDING Position */ +#define SCB_ICSR_VECTPENDING_Msk (0x1FFUL << SCB_ICSR_VECTPENDING_Pos) /*!< SCB ICSR: VECTPENDING Mask */ + +#define SCB_ICSR_VECTACTIVE_Pos 0 /*!< SCB ICSR: VECTACTIVE Position */ +#define SCB_ICSR_VECTACTIVE_Msk (0x1FFUL << SCB_ICSR_VECTACTIVE_Pos) /*!< SCB ICSR: VECTACTIVE Mask */ + +/* SCB Interrupt Control State Register Definitions */ +#define SCB_VTOR_TBLOFF_Pos 7 /*!< SCB VTOR: TBLOFF Position */ +#define SCB_VTOR_TBLOFF_Msk (0x1FFFFFFUL << SCB_VTOR_TBLOFF_Pos) /*!< SCB VTOR: TBLOFF Mask */ + +/* SCB Application Interrupt and Reset Control Register Definitions */ +#define SCB_AIRCR_VECTKEY_Pos 16 /*!< SCB AIRCR: VECTKEY Position */ +#define SCB_AIRCR_VECTKEY_Msk (0xFFFFUL << SCB_AIRCR_VECTKEY_Pos) /*!< SCB AIRCR: VECTKEY Mask */ + +#define SCB_AIRCR_VECTKEYSTAT_Pos 16 /*!< SCB AIRCR: VECTKEYSTAT Position */ +#define SCB_AIRCR_VECTKEYSTAT_Msk (0xFFFFUL << SCB_AIRCR_VECTKEYSTAT_Pos) /*!< SCB AIRCR: VECTKEYSTAT Mask */ + +#define SCB_AIRCR_ENDIANESS_Pos 15 /*!< SCB AIRCR: ENDIANESS Position */ +#define SCB_AIRCR_ENDIANESS_Msk (1UL << SCB_AIRCR_ENDIANESS_Pos) /*!< SCB AIRCR: ENDIANESS Mask */ + +#define SCB_AIRCR_SYSRESETREQ_Pos 2 /*!< SCB AIRCR: SYSRESETREQ Position */ +#define SCB_AIRCR_SYSRESETREQ_Msk (1UL << SCB_AIRCR_SYSRESETREQ_Pos) /*!< SCB AIRCR: SYSRESETREQ Mask */ + +#define SCB_AIRCR_VECTCLRACTIVE_Pos 1 /*!< SCB AIRCR: VECTCLRACTIVE Position */ +#define SCB_AIRCR_VECTCLRACTIVE_Msk (1UL << SCB_AIRCR_VECTCLRACTIVE_Pos) /*!< SCB AIRCR: VECTCLRACTIVE Mask */ + +/* SCB System Control Register Definitions */ +#define SCB_SCR_SEVONPEND_Pos 4 /*!< SCB SCR: SEVONPEND Position */ +#define SCB_SCR_SEVONPEND_Msk (1UL << SCB_SCR_SEVONPEND_Pos) /*!< SCB SCR: SEVONPEND Mask */ + +#define SCB_SCR_SLEEPDEEP_Pos 2 /*!< SCB SCR: SLEEPDEEP Position */ +#define SCB_SCR_SLEEPDEEP_Msk (1UL << SCB_SCR_SLEEPDEEP_Pos) /*!< SCB SCR: SLEEPDEEP Mask */ + +#define SCB_SCR_SLEEPONEXIT_Pos 1 /*!< SCB SCR: SLEEPONEXIT Position */ +#define SCB_SCR_SLEEPONEXIT_Msk (1UL << SCB_SCR_SLEEPONEXIT_Pos) /*!< SCB SCR: SLEEPONEXIT Mask */ + +/* SCB Configuration Control Register Definitions */ +#define SCB_CCR_STKALIGN_Pos 9 /*!< SCB CCR: STKALIGN Position */ +#define SCB_CCR_STKALIGN_Msk (1UL << SCB_CCR_STKALIGN_Pos) /*!< SCB CCR: STKALIGN Mask */ + +#define SCB_CCR_UNALIGN_TRP_Pos 3 /*!< SCB CCR: UNALIGN_TRP Position */ +#define SCB_CCR_UNALIGN_TRP_Msk (1UL << SCB_CCR_UNALIGN_TRP_Pos) /*!< SCB CCR: UNALIGN_TRP Mask */ + +/* SCB System Handler Control and State Register Definitions */ +#define SCB_SHCSR_SVCALLPENDED_Pos 15 /*!< SCB SHCSR: SVCALLPENDED Position */ +#define SCB_SHCSR_SVCALLPENDED_Msk (1UL << SCB_SHCSR_SVCALLPENDED_Pos) /*!< SCB SHCSR: SVCALLPENDED Mask */ + +/* SCB Security Features Register Definitions */ +#define SCB_SFCR_UNIBRTIMING_Pos 0 /*!< SCB SFCR: UNIBRTIMING Position */ +#define SCB_SFCR_UNIBRTIMING_Msk (1UL << SCB_SHCSR_SVCALLPENDED_Pos) /*!< SCB SFCR: UNIBRTIMING Mask */ + +#define SCB_SFCR_SECKEY_Pos 16 /*!< SCB SFCR: SECKEY Position */ +#define SCB_SFCR_SECKEY_Msk (0xFFFFUL << SCB_SHCSR_SVCALLPENDED_Pos) /*!< SCB SFCR: SECKEY Mask */ + +/*@} end of group CMSIS_SCB */ + + +/** \ingroup CMSIS_core_register + \defgroup CMSIS_SCnSCB System Controls not in SCB (SCnSCB) + \brief Type definitions for the System Control and ID Register not in the SCB + @{ + */ + +/** \brief Structure type to access the System Control and ID Register not in the SCB. + */ +typedef struct +{ + uint32_t RESERVED0[2]; + __IO uint32_t ACTLR; /*!< Offset: 0x008 (R/W) Auxiliary Control Register */ +} SCnSCB_Type; + +/* Auxiliary Control Register Definitions */ +#define SCnSCB_ACTLR_DISMCYCINT_Pos 0 /*!< ACTLR: DISMCYCINT Position */ +#define SCnSCB_ACTLR_DISMCYCINT_Msk (1UL << SCnSCB_ACTLR_DISMCYCINT_Pos) /*!< ACTLR: DISMCYCINT Mask */ + +/*@} end of group CMSIS_SCnotSCB */ + + +/** \ingroup CMSIS_core_register + \defgroup CMSIS_SysTick System Tick Timer (SysTick) + \brief Type definitions for the System Timer Registers. + @{ + */ + +/** \brief Structure type to access the System Timer (SysTick). + */ +typedef struct +{ + __IO uint32_t CTRL; /*!< Offset: 0x000 (R/W) SysTick Control and Status Register */ + __IO uint32_t LOAD; /*!< Offset: 0x004 (R/W) SysTick Reload Value Register */ + __IO uint32_t VAL; /*!< Offset: 0x008 (R/W) SysTick Current Value Register */ + __I uint32_t CALIB; /*!< Offset: 0x00C (R/ ) SysTick Calibration Register */ +} SysTick_Type; + +/* SysTick Control / Status Register Definitions */ +#define SysTick_CTRL_COUNTFLAG_Pos 16 /*!< SysTick CTRL: COUNTFLAG Position */ +#define SysTick_CTRL_COUNTFLAG_Msk (1UL << SysTick_CTRL_COUNTFLAG_Pos) /*!< SysTick CTRL: COUNTFLAG Mask */ + +#define SysTick_CTRL_CLKSOURCE_Pos 2 /*!< SysTick CTRL: CLKSOURCE Position */ +#define SysTick_CTRL_CLKSOURCE_Msk (1UL << SysTick_CTRL_CLKSOURCE_Pos) /*!< SysTick CTRL: CLKSOURCE Mask */ + +#define SysTick_CTRL_TICKINT_Pos 1 /*!< SysTick CTRL: TICKINT Position */ +#define SysTick_CTRL_TICKINT_Msk (1UL << SysTick_CTRL_TICKINT_Pos) /*!< SysTick CTRL: TICKINT Mask */ + +#define SysTick_CTRL_ENABLE_Pos 0 /*!< SysTick CTRL: ENABLE Position */ +#define SysTick_CTRL_ENABLE_Msk (1UL << SysTick_CTRL_ENABLE_Pos) /*!< SysTick CTRL: ENABLE Mask */ + +/* SysTick Reload Register Definitions */ +#define SysTick_LOAD_RELOAD_Pos 0 /*!< SysTick LOAD: RELOAD Position */ +#define SysTick_LOAD_RELOAD_Msk (0xFFFFFFUL << SysTick_LOAD_RELOAD_Pos) /*!< SysTick LOAD: RELOAD Mask */ + +/* SysTick Current Register Definitions */ +#define SysTick_VAL_CURRENT_Pos 0 /*!< SysTick VAL: CURRENT Position */ +#define SysTick_VAL_CURRENT_Msk (0xFFFFFFUL << SysTick_VAL_CURRENT_Pos) /*!< SysTick VAL: CURRENT Mask */ + +/* SysTick Calibration Register Definitions */ +#define SysTick_CALIB_NOREF_Pos 31 /*!< SysTick CALIB: NOREF Position */ +#define SysTick_CALIB_NOREF_Msk (1UL << SysTick_CALIB_NOREF_Pos) /*!< SysTick CALIB: NOREF Mask */ + +#define SysTick_CALIB_SKEW_Pos 30 /*!< SysTick CALIB: SKEW Position */ +#define SysTick_CALIB_SKEW_Msk (1UL << SysTick_CALIB_SKEW_Pos) /*!< SysTick CALIB: SKEW Mask */ + +#define SysTick_CALIB_TENMS_Pos 0 /*!< SysTick CALIB: TENMS Position */ +#define SysTick_CALIB_TENMS_Msk (0xFFFFFFUL << SysTick_VAL_CURRENT_Pos) /*!< SysTick CALIB: TENMS Mask */ + +/*@} end of group CMSIS_SysTick */ + +#if (__MPU_PRESENT == 1) +/** \ingroup CMSIS_core_register + \defgroup CMSIS_MPU Memory Protection Unit (MPU) + \brief Type definitions for the Memory Protection Unit (MPU) + @{ + */ + +/** \brief Structure type to access the Memory Protection Unit (MPU). + */ +typedef struct +{ + __I uint32_t TYPE; /*!< Offset: 0x000 (R/ ) MPU Type Register */ + __IO uint32_t CTRL; /*!< Offset: 0x004 (R/W) MPU Control Register */ + __IO uint32_t RNR; /*!< Offset: 0x008 (R/W) MPU Region RNRber Register */ + __IO uint32_t RBAR; /*!< Offset: 0x00C (R/W) MPU Region Base Address Register */ + __IO uint32_t RASR; /*!< Offset: 0x010 (R/W) MPU Region Attribute and Size Register */ +} MPU_Type; + +/* MPU Type Register */ +#define MPU_TYPE_IREGION_Pos 16 /*!< MPU TYPE: IREGION Position */ +#define MPU_TYPE_IREGION_Msk (0xFFUL << MPU_TYPE_IREGION_Pos) /*!< MPU TYPE: IREGION Mask */ + +#define MPU_TYPE_DREGION_Pos 8 /*!< MPU TYPE: DREGION Position */ +#define MPU_TYPE_DREGION_Msk (0xFFUL << MPU_TYPE_DREGION_Pos) /*!< MPU TYPE: DREGION Mask */ + +#define MPU_TYPE_SEPARATE_Pos 0 /*!< MPU TYPE: SEPARATE Position */ +#define MPU_TYPE_SEPARATE_Msk (1UL << MPU_TYPE_SEPARATE_Pos) /*!< MPU TYPE: SEPARATE Mask */ + +/* MPU Control Register */ +#define MPU_CTRL_PRIVDEFENA_Pos 2 /*!< MPU CTRL: PRIVDEFENA Position */ +#define MPU_CTRL_PRIVDEFENA_Msk (1UL << MPU_CTRL_PRIVDEFENA_Pos) /*!< MPU CTRL: PRIVDEFENA Mask */ + +#define MPU_CTRL_HFNMIENA_Pos 1 /*!< MPU CTRL: HFNMIENA Position */ +#define MPU_CTRL_HFNMIENA_Msk (1UL << MPU_CTRL_HFNMIENA_Pos) /*!< MPU CTRL: HFNMIENA Mask */ + +#define MPU_CTRL_ENABLE_Pos 0 /*!< MPU CTRL: ENABLE Position */ +#define MPU_CTRL_ENABLE_Msk (1UL << MPU_CTRL_ENABLE_Pos) /*!< MPU CTRL: ENABLE Mask */ + +/* MPU Region Number Register */ +#define MPU_RNR_REGION_Pos 0 /*!< MPU RNR: REGION Position */ +#define MPU_RNR_REGION_Msk (0xFFUL << MPU_RNR_REGION_Pos) /*!< MPU RNR: REGION Mask */ + +/* MPU Region Base Address Register */ +#define MPU_RBAR_ADDR_Pos 8 /*!< MPU RBAR: ADDR Position */ +#define MPU_RBAR_ADDR_Msk (0xFFFFFFUL << MPU_RBAR_ADDR_Pos) /*!< MPU RBAR: ADDR Mask */ + +#define MPU_RBAR_VALID_Pos 4 /*!< MPU RBAR: VALID Position */ +#define MPU_RBAR_VALID_Msk (1UL << MPU_RBAR_VALID_Pos) /*!< MPU RBAR: VALID Mask */ + +#define MPU_RBAR_REGION_Pos 0 /*!< MPU RBAR: REGION Position */ +#define MPU_RBAR_REGION_Msk (0xFUL << MPU_RBAR_REGION_Pos) /*!< MPU RBAR: REGION Mask */ + +/* MPU Region Attribute and Size Register */ +#define MPU_RASR_ATTRS_Pos 16 /*!< MPU RASR: MPU Region Attribute field Position */ +#define MPU_RASR_ATTRS_Msk (0xFFFFUL << MPU_RASR_ATTRS_Pos) /*!< MPU RASR: MPU Region Attribute field Mask */ + +#define MPU_RASR_XN_Pos 28 /*!< MPU RASR: ATTRS.XN Position */ +#define MPU_RASR_XN_Msk (1UL << MPU_RASR_XN_Pos) /*!< MPU RASR: ATTRS.XN Mask */ + +#define MPU_RASR_AP_Pos 24 /*!< MPU RASR: ATTRS.AP Position */ +#define MPU_RASR_AP_Msk (0x7UL << MPU_RASR_AP_Pos) /*!< MPU RASR: ATTRS.AP Mask */ + +#define MPU_RASR_TEX_Pos 19 /*!< MPU RASR: ATTRS.TEX Position */ +#define MPU_RASR_TEX_Msk (0x7UL << MPU_RASR_TEX_Pos) /*!< MPU RASR: ATTRS.TEX Mask */ + +#define MPU_RASR_S_Pos 18 /*!< MPU RASR: ATTRS.S Position */ +#define MPU_RASR_S_Msk (1UL << MPU_RASR_S_Pos) /*!< MPU RASR: ATTRS.S Mask */ + +#define MPU_RASR_C_Pos 17 /*!< MPU RASR: ATTRS.C Position */ +#define MPU_RASR_C_Msk (1UL << MPU_RASR_C_Pos) /*!< MPU RASR: ATTRS.C Mask */ + +#define MPU_RASR_B_Pos 16 /*!< MPU RASR: ATTRS.B Position */ +#define MPU_RASR_B_Msk (1UL << MPU_RASR_B_Pos) /*!< MPU RASR: ATTRS.B Mask */ + +#define MPU_RASR_SRD_Pos 8 /*!< MPU RASR: Sub-Region Disable Position */ +#define MPU_RASR_SRD_Msk (0xFFUL << MPU_RASR_SRD_Pos) /*!< MPU RASR: Sub-Region Disable Mask */ + +#define MPU_RASR_SIZE_Pos 1 /*!< MPU RASR: Region Size Field Position */ +#define MPU_RASR_SIZE_Msk (0x1FUL << MPU_RASR_SIZE_Pos) /*!< MPU RASR: Region Size Field Mask */ + +#define MPU_RASR_ENABLE_Pos 0 /*!< MPU RASR: Region enable bit Position */ +#define MPU_RASR_ENABLE_Msk (1UL << MPU_RASR_ENABLE_Pos) /*!< MPU RASR: Region enable bit Disable Mask */ + +/*@} end of group CMSIS_MPU */ +#endif + + +/** \ingroup CMSIS_core_register + \defgroup CMSIS_CoreDebug Core Debug Registers (CoreDebug) + \brief SC000 Core Debug Registers (DCB registers, SHCSR, and DFSR) + are only accessible over DAP and not via processor. Therefore + they are not covered by the Cortex-M0 header file. + @{ + */ +/*@} end of group CMSIS_CoreDebug */ + + +/** \ingroup CMSIS_core_register + \defgroup CMSIS_core_base Core Definitions + \brief Definitions for base addresses, unions, and structures. + @{ + */ + +/* Memory mapping of SC000 Hardware */ +#define SCS_BASE (0xE000E000UL) /*!< System Control Space Base Address */ +#define SysTick_BASE (SCS_BASE + 0x0010UL) /*!< SysTick Base Address */ +#define NVIC_BASE (SCS_BASE + 0x0100UL) /*!< NVIC Base Address */ +#define SCB_BASE (SCS_BASE + 0x0D00UL) /*!< System Control Block Base Address */ + +#define SCnSCB ((SCnSCB_Type *) SCS_BASE ) /*!< System control Register not in SCB */ +#define SCB ((SCB_Type *) SCB_BASE ) /*!< SCB configuration struct */ +#define SysTick ((SysTick_Type *) SysTick_BASE ) /*!< SysTick configuration struct */ +#define NVIC ((NVIC_Type *) NVIC_BASE ) /*!< NVIC configuration struct */ + +#if (__MPU_PRESENT == 1) + #define MPU_BASE (SCS_BASE + 0x0D90UL) /*!< Memory Protection Unit */ + #define MPU ((MPU_Type *) MPU_BASE ) /*!< Memory Protection Unit */ +#endif + +/*@} */ + + + +/******************************************************************************* + * Hardware Abstraction Layer + Core Function Interface contains: + - Core NVIC Functions + - Core SysTick Functions + - Core Register Access Functions + ******************************************************************************/ +/** \defgroup CMSIS_Core_FunctionInterface Functions and Instructions Reference +*/ + + + +/* ########################## NVIC functions #################################### */ +/** \ingroup CMSIS_Core_FunctionInterface + \defgroup CMSIS_Core_NVICFunctions NVIC Functions + \brief Functions that manage interrupts and exceptions via the NVIC. + @{ + */ + +/* Interrupt Priorities are WORD accessible only under ARMv6M */ +/* The following MACROS handle generation of the register offset and byte masks */ +#define _BIT_SHIFT(IRQn) ( (((uint32_t)(IRQn) ) & 0x03) * 8 ) +#define _SHP_IDX(IRQn) ( ((((uint32_t)(IRQn) & 0x0F)-8) >> 2) ) +#define _IP_IDX(IRQn) ( ((uint32_t)(IRQn) >> 2) ) + + +/** \brief Enable External Interrupt + + The function enables a device-specific interrupt in the NVIC interrupt controller. + + \param [in] IRQn External interrupt number. Value cannot be negative. + */ +__STATIC_INLINE void NVIC_EnableIRQ(IRQn_Type IRQn) +{ + NVIC->ISER[0] = (1 << ((uint32_t)(IRQn) & 0x1F)); +} + + +/** \brief Disable External Interrupt + + The function disables a device-specific interrupt in the NVIC interrupt controller. + + \param [in] IRQn External interrupt number. Value cannot be negative. + */ +__STATIC_INLINE void NVIC_DisableIRQ(IRQn_Type IRQn) +{ + NVIC->ICER[0] = (1 << ((uint32_t)(IRQn) & 0x1F)); +} + + +/** \brief Get Pending Interrupt + + The function reads the pending register in the NVIC and returns the pending bit + for the specified interrupt. + + \param [in] IRQn Interrupt number. + + \return 0 Interrupt status is not pending. + \return 1 Interrupt status is pending. + */ +__STATIC_INLINE uint32_t NVIC_GetPendingIRQ(IRQn_Type IRQn) +{ + return((uint32_t) ((NVIC->ISPR[0] & (1 << ((uint32_t)(IRQn) & 0x1F)))?1:0)); +} + + +/** \brief Set Pending Interrupt + + The function sets the pending bit of an external interrupt. + + \param [in] IRQn Interrupt number. Value cannot be negative. + */ +__STATIC_INLINE void NVIC_SetPendingIRQ(IRQn_Type IRQn) +{ + NVIC->ISPR[0] = (1 << ((uint32_t)(IRQn) & 0x1F)); +} + + +/** \brief Clear Pending Interrupt + + The function clears the pending bit of an external interrupt. + + \param [in] IRQn External interrupt number. Value cannot be negative. + */ +__STATIC_INLINE void NVIC_ClearPendingIRQ(IRQn_Type IRQn) +{ + NVIC->ICPR[0] = (1 << ((uint32_t)(IRQn) & 0x1F)); /* Clear pending interrupt */ +} + + +/** \brief Set Interrupt Priority + + The function sets the priority of an interrupt. + + \note The priority cannot be set for every core interrupt. + + \param [in] IRQn Interrupt number. + \param [in] priority Priority to set. + */ +__STATIC_INLINE void NVIC_SetPriority(IRQn_Type IRQn, uint32_t priority) +{ + if(IRQn < 0) { + SCB->SHP[_SHP_IDX(IRQn)] = (SCB->SHP[_SHP_IDX(IRQn)] & ~(0xFF << _BIT_SHIFT(IRQn))) | + (((priority << (8 - __NVIC_PRIO_BITS)) & 0xFF) << _BIT_SHIFT(IRQn)); } + else { + NVIC->IP[_IP_IDX(IRQn)] = (NVIC->IP[_IP_IDX(IRQn)] & ~(0xFF << _BIT_SHIFT(IRQn))) | + (((priority << (8 - __NVIC_PRIO_BITS)) & 0xFF) << _BIT_SHIFT(IRQn)); } +} + + +/** \brief Get Interrupt Priority + + The function reads the priority of an interrupt. The interrupt + number can be positive to specify an external (device specific) + interrupt, or negative to specify an internal (core) interrupt. + + + \param [in] IRQn Interrupt number. + \return Interrupt Priority. Value is aligned automatically to the implemented + priority bits of the microcontroller. + */ +__STATIC_INLINE uint32_t NVIC_GetPriority(IRQn_Type IRQn) +{ + + if(IRQn < 0) { + return((uint32_t)((SCB->SHP[_SHP_IDX(IRQn)] >> _BIT_SHIFT(IRQn) ) >> (8 - __NVIC_PRIO_BITS))); } /* get priority for SC000 system interrupts */ + else { + return((uint32_t)((NVIC->IP[ _IP_IDX(IRQn)] >> _BIT_SHIFT(IRQn) ) >> (8 - __NVIC_PRIO_BITS))); } /* get priority for device specific interrupts */ +} + + +/** \brief System Reset + + The function initiates a system reset request to reset the MCU. + */ +__STATIC_INLINE void NVIC_SystemReset(void) +{ + __DSB(); /* Ensure all outstanding memory accesses included + buffered write are completed before reset */ + SCB->AIRCR = ((0x5FA << SCB_AIRCR_VECTKEY_Pos) | + SCB_AIRCR_SYSRESETREQ_Msk); + __DSB(); /* Ensure completion of memory access */ + while(1); /* wait until reset */ +} + +/*@} end of CMSIS_Core_NVICFunctions */ + + + +/* ################################## SysTick function ############################################ */ +/** \ingroup CMSIS_Core_FunctionInterface + \defgroup CMSIS_Core_SysTickFunctions SysTick Functions + \brief Functions that configure the System. + @{ + */ + +#if (__Vendor_SysTickConfig == 0) + +/** \brief System Tick Configuration + + The function initializes the System Timer and its interrupt, and starts the System Tick Timer. + Counter is in free running mode to generate periodic interrupts. + + \param [in] ticks Number of ticks between two interrupts. + + \return 0 Function succeeded. + \return 1 Function failed. + + \note When the variable __Vendor_SysTickConfig is set to 1, then the + function SysTick_Config is not included. In this case, the file device.h + must contain a vendor-specific implementation of this function. + + */ +__STATIC_INLINE uint32_t SysTick_Config(uint32_t ticks) +{ + if (ticks > SysTick_LOAD_RELOAD_Msk) return (1); /* Reload value impossible */ + + SysTick->LOAD = (ticks & SysTick_LOAD_RELOAD_Msk) - 1; /* set reload register */ + NVIC_SetPriority (SysTick_IRQn, (1<<__NVIC_PRIO_BITS) - 1); /* set Priority for Systick Interrupt */ + SysTick->VAL = 0; /* Load the SysTick Counter Value */ + SysTick->CTRL = SysTick_CTRL_CLKSOURCE_Msk | + SysTick_CTRL_TICKINT_Msk | + SysTick_CTRL_ENABLE_Msk; /* Enable SysTick IRQ and SysTick Timer */ + return (0); /* Function successful */ +} + +#endif + +/*@} end of CMSIS_Core_SysTickFunctions */ + + + + +#endif /* __CORE_SC000_H_DEPENDANT */ + +#endif /* __CMSIS_GENERIC */ + +#ifdef __cplusplus +} +#endif diff --git a/Libraries/CMSIS/Include/core_sc300.h b/Libraries/CMSIS/Include/core_sc300.h new file mode 100644 index 0000000..7e56b0f --- /dev/null +++ b/Libraries/CMSIS/Include/core_sc300.h @@ -0,0 +1,1583 @@ +/**************************************************************************//** + * @file core_sc300.h + * @brief CMSIS SC300 Core Peripheral Access Layer Header File + * @version V3.01 + * @date 22. March 2012 + * + * @note + * Copyright (C) 2009-2012 ARM Limited. All rights reserved. + * + * @par + * ARM Limited (ARM) is supplying this software for use with Cortex-M + * processor based microcontrollers. This file can be freely distributed + * within development tools that are supporting such ARM based processors. + * + * @par + * THIS SOFTWARE IS PROVIDED "AS IS". NO WARRANTIES, WHETHER EXPRESS, IMPLIED + * OR STATUTORY, INCLUDING, BUT NOT LIMITED TO, IMPLIED WARRANTIES OF + * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE APPLY TO THIS SOFTWARE. + * ARM SHALL NOT, IN ANY CIRCUMSTANCES, BE LIABLE FOR SPECIAL, INCIDENTAL, OR + * CONSEQUENTIAL DAMAGES, FOR ANY REASON WHATSOEVER. + * + ******************************************************************************/ +#if defined ( __ICCARM__ ) + #pragma system_include /* treat file as system include file for MISRA check */ +#endif + +#ifdef __cplusplus + extern "C" { +#endif + +#ifndef __CORE_SC300_H_GENERIC +#define __CORE_SC300_H_GENERIC + +/** \page CMSIS_MISRA_Exceptions MISRA-C:2004 Compliance Exceptions + CMSIS violates the following MISRA-C:2004 rules: + + \li Required Rule 8.5, object/function definition in header file.
    + Function definitions in header files are used to allow 'inlining'. + + \li Required Rule 18.4, declaration of union type or object of union type: '{...}'.
    + Unions are used for effective representation of core registers. + + \li Advisory Rule 19.7, Function-like macro defined.
    + Function-like macros are used to allow more efficient code. + */ + + +/******************************************************************************* + * CMSIS definitions + ******************************************************************************/ +/** \ingroup SC3000 + @{ + */ + +/* CMSIS SC300 definitions */ +#define __SC300_CMSIS_VERSION_MAIN (0x03) /*!< [31:16] CMSIS HAL main version */ +#define __SC300_CMSIS_VERSION_SUB (0x01) /*!< [15:0] CMSIS HAL sub version */ +#define __SC300_CMSIS_VERSION ((__SC300_CMSIS_VERSION_MAIN << 16) | \ + __SC300_CMSIS_VERSION_SUB ) /*!< CMSIS HAL version number */ + +#define __CORTEX_SC (300) /*!< Cortex secure core */ + + +#if defined ( __CC_ARM ) + #define __ASM __asm /*!< asm keyword for ARM Compiler */ + #define __INLINE __inline /*!< inline keyword for ARM Compiler */ + #define __STATIC_INLINE static __inline + +#elif defined ( __ICCARM__ ) + #define __ASM __asm /*!< asm keyword for IAR Compiler */ + #define __INLINE inline /*!< inline keyword for IAR Compiler. Only available in High optimization mode! */ + #define __STATIC_INLINE static inline + +#elif defined ( __GNUC__ ) + #define __ASM __asm /*!< asm keyword for GNU Compiler */ + #define __INLINE inline /*!< inline keyword for GNU Compiler */ + #define __STATIC_INLINE static inline + +#elif defined ( __TASKING__ ) + #define __ASM __asm /*!< asm keyword for TASKING Compiler */ + #define __INLINE inline /*!< inline keyword for TASKING Compiler */ + #define __STATIC_INLINE static inline + +#endif + +/** __FPU_USED indicates whether an FPU is used or not. This core does not support an FPU at all +*/ +#define __FPU_USED 0 + +#if defined ( __CC_ARM ) + #if defined __TARGET_FPU_VFP + #warning "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #endif + +#elif defined ( __ICCARM__ ) + #if defined __ARMVFP__ + #warning "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #endif + +#elif defined ( __GNUC__ ) + #if defined (__VFP_FP__) && !defined(__SOFTFP__) + #warning "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #endif + +#elif defined ( __TASKING__ ) + #if defined __FPU_VFP__ + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #endif +#endif + +#include /* standard types definitions */ +#include /* Core Instruction Access */ +#include /* Core Function Access */ + +#endif /* __CORE_SC300_H_GENERIC */ + +#ifndef __CMSIS_GENERIC + +#ifndef __CORE_SC300_H_DEPENDANT +#define __CORE_SC300_H_DEPENDANT + +/* check device defines and use defaults */ +#if defined __CHECK_DEVICE_DEFINES + #ifndef __SC300_REV + #define __SC300_REV 0x0000 + #warning "__SC300_REV not defined in device header file; using default!" + #endif + + #ifndef __MPU_PRESENT + #define __MPU_PRESENT 0 + #warning "__MPU_PRESENT not defined in device header file; using default!" + #endif + + #ifndef __NVIC_PRIO_BITS + #define __NVIC_PRIO_BITS 4 + #warning "__NVIC_PRIO_BITS not defined in device header file; using default!" + #endif + + #ifndef __Vendor_SysTickConfig + #define __Vendor_SysTickConfig 0 + #warning "__Vendor_SysTickConfig not defined in device header file; using default!" + #endif +#endif + +/* IO definitions (access restrictions to peripheral registers) */ +/** + \defgroup CMSIS_glob_defs CMSIS Global Defines + + IO Type Qualifiers are used + \li to specify the access to peripheral variables. + \li for automatic generation of peripheral register debug information. +*/ +#ifdef __cplusplus + #define __I volatile /*!< Defines 'read only' permissions */ +#else + #define __I volatile const /*!< Defines 'read only' permissions */ +#endif +#define __O volatile /*!< Defines 'write only' permissions */ +#define __IO volatile /*!< Defines 'read / write' permissions */ + +/*@} end of group SC300 */ + + + +/******************************************************************************* + * Register Abstraction + Core Register contain: + - Core Register + - Core NVIC Register + - Core SCB Register + - Core SysTick Register + - Core Debug Register + - Core MPU Register + ******************************************************************************/ +/** \defgroup CMSIS_core_register Defines and Type Definitions + \brief Type definitions and defines for Cortex-M processor based devices. +*/ + +/** \ingroup CMSIS_core_register + \defgroup CMSIS_CORE Status and Control Registers + \brief Core Register type definitions. + @{ + */ + +/** \brief Union type to access the Application Program Status Register (APSR). + */ +typedef union +{ + struct + { +#if (__CORTEX_M != 0x04) + uint32_t _reserved0:27; /*!< bit: 0..26 Reserved */ +#else + uint32_t _reserved0:16; /*!< bit: 0..15 Reserved */ + uint32_t GE:4; /*!< bit: 16..19 Greater than or Equal flags */ + uint32_t _reserved1:7; /*!< bit: 20..26 Reserved */ +#endif + uint32_t Q:1; /*!< bit: 27 Saturation condition flag */ + uint32_t V:1; /*!< bit: 28 Overflow condition code flag */ + uint32_t C:1; /*!< bit: 29 Carry condition code flag */ + uint32_t Z:1; /*!< bit: 30 Zero condition code flag */ + uint32_t N:1; /*!< bit: 31 Negative condition code flag */ + } b; /*!< Structure used for bit access */ + uint32_t w; /*!< Type used for word access */ +} APSR_Type; + + +/** \brief Union type to access the Interrupt Program Status Register (IPSR). + */ +typedef union +{ + struct + { + uint32_t ISR:9; /*!< bit: 0.. 8 Exception number */ + uint32_t _reserved0:23; /*!< bit: 9..31 Reserved */ + } b; /*!< Structure used for bit access */ + uint32_t w; /*!< Type used for word access */ +} IPSR_Type; + + +/** \brief Union type to access the Special-Purpose Program Status Registers (xPSR). + */ +typedef union +{ + struct + { + uint32_t ISR:9; /*!< bit: 0.. 8 Exception number */ +#if (__CORTEX_M != 0x04) + uint32_t _reserved0:15; /*!< bit: 9..23 Reserved */ +#else + uint32_t _reserved0:7; /*!< bit: 9..15 Reserved */ + uint32_t GE:4; /*!< bit: 16..19 Greater than or Equal flags */ + uint32_t _reserved1:4; /*!< bit: 20..23 Reserved */ +#endif + uint32_t T:1; /*!< bit: 24 Thumb bit (read 0) */ + uint32_t IT:2; /*!< bit: 25..26 saved IT state (read 0) */ + uint32_t Q:1; /*!< bit: 27 Saturation condition flag */ + uint32_t V:1; /*!< bit: 28 Overflow condition code flag */ + uint32_t C:1; /*!< bit: 29 Carry condition code flag */ + uint32_t Z:1; /*!< bit: 30 Zero condition code flag */ + uint32_t N:1; /*!< bit: 31 Negative condition code flag */ + } b; /*!< Structure used for bit access */ + uint32_t w; /*!< Type used for word access */ +} xPSR_Type; + + +/** \brief Union type to access the Control Registers (CONTROL). + */ +typedef union +{ + struct + { + uint32_t nPRIV:1; /*!< bit: 0 Execution privilege in Thread mode */ + uint32_t SPSEL:1; /*!< bit: 1 Stack to be used */ + uint32_t FPCA:1; /*!< bit: 2 FP extension active flag */ + uint32_t _reserved0:29; /*!< bit: 3..31 Reserved */ + } b; /*!< Structure used for bit access */ + uint32_t w; /*!< Type used for word access */ +} CONTROL_Type; + +/*@} end of group CMSIS_CORE */ + + +/** \ingroup CMSIS_core_register + \defgroup CMSIS_NVIC Nested Vectored Interrupt Controller (NVIC) + \brief Type definitions for the NVIC Registers + @{ + */ + +/** \brief Structure type to access the Nested Vectored Interrupt Controller (NVIC). + */ +typedef struct +{ + __IO uint32_t ISER[8]; /*!< Offset: 0x000 (R/W) Interrupt Set Enable Register */ + uint32_t RESERVED0[24]; + __IO uint32_t ICER[8]; /*!< Offset: 0x080 (R/W) Interrupt Clear Enable Register */ + uint32_t RSERVED1[24]; + __IO uint32_t ISPR[8]; /*!< Offset: 0x100 (R/W) Interrupt Set Pending Register */ + uint32_t RESERVED2[24]; + __IO uint32_t ICPR[8]; /*!< Offset: 0x180 (R/W) Interrupt Clear Pending Register */ + uint32_t RESERVED3[24]; + __IO uint32_t IABR[8]; /*!< Offset: 0x200 (R/W) Interrupt Active bit Register */ + uint32_t RESERVED4[56]; + __IO uint8_t IP[240]; /*!< Offset: 0x300 (R/W) Interrupt Priority Register (8Bit wide) */ + uint32_t RESERVED5[644]; + __O uint32_t STIR; /*!< Offset: 0xE00 ( /W) Software Trigger Interrupt Register */ +} NVIC_Type; + +/* Software Triggered Interrupt Register Definitions */ +#define NVIC_STIR_INTID_Pos 0 /*!< STIR: INTLINESNUM Position */ +#define NVIC_STIR_INTID_Msk (0x1FFUL << NVIC_STIR_INTID_Pos) /*!< STIR: INTLINESNUM Mask */ + +/*@} end of group CMSIS_NVIC */ + + +/** \ingroup CMSIS_core_register + \defgroup CMSIS_SCB System Control Block (SCB) + \brief Type definitions for the System Control Block Registers + @{ + */ + +/** \brief Structure type to access the System Control Block (SCB). + */ +typedef struct +{ + __I uint32_t CPUID; /*!< Offset: 0x000 (R/ ) CPUID Base Register */ + __IO uint32_t ICSR; /*!< Offset: 0x004 (R/W) Interrupt Control and State Register */ + __IO uint32_t VTOR; /*!< Offset: 0x008 (R/W) Vector Table Offset Register */ + __IO uint32_t AIRCR; /*!< Offset: 0x00C (R/W) Application Interrupt and Reset Control Register */ + __IO uint32_t SCR; /*!< Offset: 0x010 (R/W) System Control Register */ + __IO uint32_t CCR; /*!< Offset: 0x014 (R/W) Configuration Control Register */ + __IO uint8_t SHP[12]; /*!< Offset: 0x018 (R/W) System Handlers Priority Registers (4-7, 8-11, 12-15) */ + __IO uint32_t SHCSR; /*!< Offset: 0x024 (R/W) System Handler Control and State Register */ + __IO uint32_t CFSR; /*!< Offset: 0x028 (R/W) Configurable Fault Status Register */ + __IO uint32_t HFSR; /*!< Offset: 0x02C (R/W) HardFault Status Register */ + __IO uint32_t DFSR; /*!< Offset: 0x030 (R/W) Debug Fault Status Register */ + __IO uint32_t MMFAR; /*!< Offset: 0x034 (R/W) MemManage Fault Address Register */ + __IO uint32_t BFAR; /*!< Offset: 0x038 (R/W) BusFault Address Register */ + __IO uint32_t AFSR; /*!< Offset: 0x03C (R/W) Auxiliary Fault Status Register */ + __I uint32_t PFR[2]; /*!< Offset: 0x040 (R/ ) Processor Feature Register */ + __I uint32_t DFR; /*!< Offset: 0x048 (R/ ) Debug Feature Register */ + __I uint32_t ADR; /*!< Offset: 0x04C (R/ ) Auxiliary Feature Register */ + __I uint32_t MMFR[4]; /*!< Offset: 0x050 (R/ ) Memory Model Feature Register */ + __I uint32_t ISAR[5]; /*!< Offset: 0x060 (R/ ) Instruction Set Attributes Register */ + uint32_t RESERVED0[5]; + __IO uint32_t CPACR; /*!< Offset: 0x088 (R/W) Coprocessor Access Control Register */ +} SCB_Type; + +/* SCB CPUID Register Definitions */ +#define SCB_CPUID_IMPLEMENTER_Pos 24 /*!< SCB CPUID: IMPLEMENTER Position */ +#define SCB_CPUID_IMPLEMENTER_Msk (0xFFUL << SCB_CPUID_IMPLEMENTER_Pos) /*!< SCB CPUID: IMPLEMENTER Mask */ + +#define SCB_CPUID_VARIANT_Pos 20 /*!< SCB CPUID: VARIANT Position */ +#define SCB_CPUID_VARIANT_Msk (0xFUL << SCB_CPUID_VARIANT_Pos) /*!< SCB CPUID: VARIANT Mask */ + +#define SCB_CPUID_ARCHITECTURE_Pos 16 /*!< SCB CPUID: ARCHITECTURE Position */ +#define SCB_CPUID_ARCHITECTURE_Msk (0xFUL << SCB_CPUID_ARCHITECTURE_Pos) /*!< SCB CPUID: ARCHITECTURE Mask */ + +#define SCB_CPUID_PARTNO_Pos 4 /*!< SCB CPUID: PARTNO Position */ +#define SCB_CPUID_PARTNO_Msk (0xFFFUL << SCB_CPUID_PARTNO_Pos) /*!< SCB CPUID: PARTNO Mask */ + +#define SCB_CPUID_REVISION_Pos 0 /*!< SCB CPUID: REVISION Position */ +#define SCB_CPUID_REVISION_Msk (0xFUL << SCB_CPUID_REVISION_Pos) /*!< SCB CPUID: REVISION Mask */ + +/* SCB Interrupt Control State Register Definitions */ +#define SCB_ICSR_NMIPENDSET_Pos 31 /*!< SCB ICSR: NMIPENDSET Position */ +#define SCB_ICSR_NMIPENDSET_Msk (1UL << SCB_ICSR_NMIPENDSET_Pos) /*!< SCB ICSR: NMIPENDSET Mask */ + +#define SCB_ICSR_PENDSVSET_Pos 28 /*!< SCB ICSR: PENDSVSET Position */ +#define SCB_ICSR_PENDSVSET_Msk (1UL << SCB_ICSR_PENDSVSET_Pos) /*!< SCB ICSR: PENDSVSET Mask */ + +#define SCB_ICSR_PENDSVCLR_Pos 27 /*!< SCB ICSR: PENDSVCLR Position */ +#define SCB_ICSR_PENDSVCLR_Msk (1UL << SCB_ICSR_PENDSVCLR_Pos) /*!< SCB ICSR: PENDSVCLR Mask */ + +#define SCB_ICSR_PENDSTSET_Pos 26 /*!< SCB ICSR: PENDSTSET Position */ +#define SCB_ICSR_PENDSTSET_Msk (1UL << SCB_ICSR_PENDSTSET_Pos) /*!< SCB ICSR: PENDSTSET Mask */ + +#define SCB_ICSR_PENDSTCLR_Pos 25 /*!< SCB ICSR: PENDSTCLR Position */ +#define SCB_ICSR_PENDSTCLR_Msk (1UL << SCB_ICSR_PENDSTCLR_Pos) /*!< SCB ICSR: PENDSTCLR Mask */ + +#define SCB_ICSR_ISRPREEMPT_Pos 23 /*!< SCB ICSR: ISRPREEMPT Position */ +#define SCB_ICSR_ISRPREEMPT_Msk (1UL << SCB_ICSR_ISRPREEMPT_Pos) /*!< SCB ICSR: ISRPREEMPT Mask */ + +#define SCB_ICSR_ISRPENDING_Pos 22 /*!< SCB ICSR: ISRPENDING Position */ +#define SCB_ICSR_ISRPENDING_Msk (1UL << SCB_ICSR_ISRPENDING_Pos) /*!< SCB ICSR: ISRPENDING Mask */ + +#define SCB_ICSR_VECTPENDING_Pos 12 /*!< SCB ICSR: VECTPENDING Position */ +#define SCB_ICSR_VECTPENDING_Msk (0x1FFUL << SCB_ICSR_VECTPENDING_Pos) /*!< SCB ICSR: VECTPENDING Mask */ + +#define SCB_ICSR_RETTOBASE_Pos 11 /*!< SCB ICSR: RETTOBASE Position */ +#define SCB_ICSR_RETTOBASE_Msk (1UL << SCB_ICSR_RETTOBASE_Pos) /*!< SCB ICSR: RETTOBASE Mask */ + +#define SCB_ICSR_VECTACTIVE_Pos 0 /*!< SCB ICSR: VECTACTIVE Position */ +#define SCB_ICSR_VECTACTIVE_Msk (0x1FFUL << SCB_ICSR_VECTACTIVE_Pos) /*!< SCB ICSR: VECTACTIVE Mask */ + +/* SCB Vector Table Offset Register Definitions */ +#define SCB_VTOR_TBLBASE_Pos 29 /*!< SCB VTOR: TBLBASE Position */ +#define SCB_VTOR_TBLBASE_Msk (1UL << SCB_VTOR_TBLBASE_Pos) /*!< SCB VTOR: TBLBASE Mask */ + +#define SCB_VTOR_TBLOFF_Pos 7 /*!< SCB VTOR: TBLOFF Position */ +#define SCB_VTOR_TBLOFF_Msk (0x3FFFFFUL << SCB_VTOR_TBLOFF_Pos) /*!< SCB VTOR: TBLOFF Mask */ + +/* SCB Application Interrupt and Reset Control Register Definitions */ +#define SCB_AIRCR_VECTKEY_Pos 16 /*!< SCB AIRCR: VECTKEY Position */ +#define SCB_AIRCR_VECTKEY_Msk (0xFFFFUL << SCB_AIRCR_VECTKEY_Pos) /*!< SCB AIRCR: VECTKEY Mask */ + +#define SCB_AIRCR_VECTKEYSTAT_Pos 16 /*!< SCB AIRCR: VECTKEYSTAT Position */ +#define SCB_AIRCR_VECTKEYSTAT_Msk (0xFFFFUL << SCB_AIRCR_VECTKEYSTAT_Pos) /*!< SCB AIRCR: VECTKEYSTAT Mask */ + +#define SCB_AIRCR_ENDIANESS_Pos 15 /*!< SCB AIRCR: ENDIANESS Position */ +#define SCB_AIRCR_ENDIANESS_Msk (1UL << SCB_AIRCR_ENDIANESS_Pos) /*!< SCB AIRCR: ENDIANESS Mask */ + +#define SCB_AIRCR_PRIGROUP_Pos 8 /*!< SCB AIRCR: PRIGROUP Position */ +#define SCB_AIRCR_PRIGROUP_Msk (7UL << SCB_AIRCR_PRIGROUP_Pos) /*!< SCB AIRCR: PRIGROUP Mask */ + +#define SCB_AIRCR_SYSRESETREQ_Pos 2 /*!< SCB AIRCR: SYSRESETREQ Position */ +#define SCB_AIRCR_SYSRESETREQ_Msk (1UL << SCB_AIRCR_SYSRESETREQ_Pos) /*!< SCB AIRCR: SYSRESETREQ Mask */ + +#define SCB_AIRCR_VECTCLRACTIVE_Pos 1 /*!< SCB AIRCR: VECTCLRACTIVE Position */ +#define SCB_AIRCR_VECTCLRACTIVE_Msk (1UL << SCB_AIRCR_VECTCLRACTIVE_Pos) /*!< SCB AIRCR: VECTCLRACTIVE Mask */ + +#define SCB_AIRCR_VECTRESET_Pos 0 /*!< SCB AIRCR: VECTRESET Position */ +#define SCB_AIRCR_VECTRESET_Msk (1UL << SCB_AIRCR_VECTRESET_Pos) /*!< SCB AIRCR: VECTRESET Mask */ + +/* SCB System Control Register Definitions */ +#define SCB_SCR_SEVONPEND_Pos 4 /*!< SCB SCR: SEVONPEND Position */ +#define SCB_SCR_SEVONPEND_Msk (1UL << SCB_SCR_SEVONPEND_Pos) /*!< SCB SCR: SEVONPEND Mask */ + +#define SCB_SCR_SLEEPDEEP_Pos 2 /*!< SCB SCR: SLEEPDEEP Position */ +#define SCB_SCR_SLEEPDEEP_Msk (1UL << SCB_SCR_SLEEPDEEP_Pos) /*!< SCB SCR: SLEEPDEEP Mask */ + +#define SCB_SCR_SLEEPONEXIT_Pos 1 /*!< SCB SCR: SLEEPONEXIT Position */ +#define SCB_SCR_SLEEPONEXIT_Msk (1UL << SCB_SCR_SLEEPONEXIT_Pos) /*!< SCB SCR: SLEEPONEXIT Mask */ + +/* SCB Configuration Control Register Definitions */ +#define SCB_CCR_STKALIGN_Pos 9 /*!< SCB CCR: STKALIGN Position */ +#define SCB_CCR_STKALIGN_Msk (1UL << SCB_CCR_STKALIGN_Pos) /*!< SCB CCR: STKALIGN Mask */ + +#define SCB_CCR_BFHFNMIGN_Pos 8 /*!< SCB CCR: BFHFNMIGN Position */ +#define SCB_CCR_BFHFNMIGN_Msk (1UL << SCB_CCR_BFHFNMIGN_Pos) /*!< SCB CCR: BFHFNMIGN Mask */ + +#define SCB_CCR_DIV_0_TRP_Pos 4 /*!< SCB CCR: DIV_0_TRP Position */ +#define SCB_CCR_DIV_0_TRP_Msk (1UL << SCB_CCR_DIV_0_TRP_Pos) /*!< SCB CCR: DIV_0_TRP Mask */ + +#define SCB_CCR_UNALIGN_TRP_Pos 3 /*!< SCB CCR: UNALIGN_TRP Position */ +#define SCB_CCR_UNALIGN_TRP_Msk (1UL << SCB_CCR_UNALIGN_TRP_Pos) /*!< SCB CCR: UNALIGN_TRP Mask */ + +#define SCB_CCR_USERSETMPEND_Pos 1 /*!< SCB CCR: USERSETMPEND Position */ +#define SCB_CCR_USERSETMPEND_Msk (1UL << SCB_CCR_USERSETMPEND_Pos) /*!< SCB CCR: USERSETMPEND Mask */ + +#define SCB_CCR_NONBASETHRDENA_Pos 0 /*!< SCB CCR: NONBASETHRDENA Position */ +#define SCB_CCR_NONBASETHRDENA_Msk (1UL << SCB_CCR_NONBASETHRDENA_Pos) /*!< SCB CCR: NONBASETHRDENA Mask */ + +/* SCB System Handler Control and State Register Definitions */ +#define SCB_SHCSR_USGFAULTENA_Pos 18 /*!< SCB SHCSR: USGFAULTENA Position */ +#define SCB_SHCSR_USGFAULTENA_Msk (1UL << SCB_SHCSR_USGFAULTENA_Pos) /*!< SCB SHCSR: USGFAULTENA Mask */ + +#define SCB_SHCSR_BUSFAULTENA_Pos 17 /*!< SCB SHCSR: BUSFAULTENA Position */ +#define SCB_SHCSR_BUSFAULTENA_Msk (1UL << SCB_SHCSR_BUSFAULTENA_Pos) /*!< SCB SHCSR: BUSFAULTENA Mask */ + +#define SCB_SHCSR_MEMFAULTENA_Pos 16 /*!< SCB SHCSR: MEMFAULTENA Position */ +#define SCB_SHCSR_MEMFAULTENA_Msk (1UL << SCB_SHCSR_MEMFAULTENA_Pos) /*!< SCB SHCSR: MEMFAULTENA Mask */ + +#define SCB_SHCSR_SVCALLPENDED_Pos 15 /*!< SCB SHCSR: SVCALLPENDED Position */ +#define SCB_SHCSR_SVCALLPENDED_Msk (1UL << SCB_SHCSR_SVCALLPENDED_Pos) /*!< SCB SHCSR: SVCALLPENDED Mask */ + +#define SCB_SHCSR_BUSFAULTPENDED_Pos 14 /*!< SCB SHCSR: BUSFAULTPENDED Position */ +#define SCB_SHCSR_BUSFAULTPENDED_Msk (1UL << SCB_SHCSR_BUSFAULTPENDED_Pos) /*!< SCB SHCSR: BUSFAULTPENDED Mask */ + +#define SCB_SHCSR_MEMFAULTPENDED_Pos 13 /*!< SCB SHCSR: MEMFAULTPENDED Position */ +#define SCB_SHCSR_MEMFAULTPENDED_Msk (1UL << SCB_SHCSR_MEMFAULTPENDED_Pos) /*!< SCB SHCSR: MEMFAULTPENDED Mask */ + +#define SCB_SHCSR_USGFAULTPENDED_Pos 12 /*!< SCB SHCSR: USGFAULTPENDED Position */ +#define SCB_SHCSR_USGFAULTPENDED_Msk (1UL << SCB_SHCSR_USGFAULTPENDED_Pos) /*!< SCB SHCSR: USGFAULTPENDED Mask */ + +#define SCB_SHCSR_SYSTICKACT_Pos 11 /*!< SCB SHCSR: SYSTICKACT Position */ +#define SCB_SHCSR_SYSTICKACT_Msk (1UL << SCB_SHCSR_SYSTICKACT_Pos) /*!< SCB SHCSR: SYSTICKACT Mask */ + +#define SCB_SHCSR_PENDSVACT_Pos 10 /*!< SCB SHCSR: PENDSVACT Position */ +#define SCB_SHCSR_PENDSVACT_Msk (1UL << SCB_SHCSR_PENDSVACT_Pos) /*!< SCB SHCSR: PENDSVACT Mask */ + +#define SCB_SHCSR_MONITORACT_Pos 8 /*!< SCB SHCSR: MONITORACT Position */ +#define SCB_SHCSR_MONITORACT_Msk (1UL << SCB_SHCSR_MONITORACT_Pos) /*!< SCB SHCSR: MONITORACT Mask */ + +#define SCB_SHCSR_SVCALLACT_Pos 7 /*!< SCB SHCSR: SVCALLACT Position */ +#define SCB_SHCSR_SVCALLACT_Msk (1UL << SCB_SHCSR_SVCALLACT_Pos) /*!< SCB SHCSR: SVCALLACT Mask */ + +#define SCB_SHCSR_USGFAULTACT_Pos 3 /*!< SCB SHCSR: USGFAULTACT Position */ +#define SCB_SHCSR_USGFAULTACT_Msk (1UL << SCB_SHCSR_USGFAULTACT_Pos) /*!< SCB SHCSR: USGFAULTACT Mask */ + +#define SCB_SHCSR_BUSFAULTACT_Pos 1 /*!< SCB SHCSR: BUSFAULTACT Position */ +#define SCB_SHCSR_BUSFAULTACT_Msk (1UL << SCB_SHCSR_BUSFAULTACT_Pos) /*!< SCB SHCSR: BUSFAULTACT Mask */ + +#define SCB_SHCSR_MEMFAULTACT_Pos 0 /*!< SCB SHCSR: MEMFAULTACT Position */ +#define SCB_SHCSR_MEMFAULTACT_Msk (1UL << SCB_SHCSR_MEMFAULTACT_Pos) /*!< SCB SHCSR: MEMFAULTACT Mask */ + +/* SCB Configurable Fault Status Registers Definitions */ +#define SCB_CFSR_USGFAULTSR_Pos 16 /*!< SCB CFSR: Usage Fault Status Register Position */ +#define SCB_CFSR_USGFAULTSR_Msk (0xFFFFUL << SCB_CFSR_USGFAULTSR_Pos) /*!< SCB CFSR: Usage Fault Status Register Mask */ + +#define SCB_CFSR_BUSFAULTSR_Pos 8 /*!< SCB CFSR: Bus Fault Status Register Position */ +#define SCB_CFSR_BUSFAULTSR_Msk (0xFFUL << SCB_CFSR_BUSFAULTSR_Pos) /*!< SCB CFSR: Bus Fault Status Register Mask */ + +#define SCB_CFSR_MEMFAULTSR_Pos 0 /*!< SCB CFSR: Memory Manage Fault Status Register Position */ +#define SCB_CFSR_MEMFAULTSR_Msk (0xFFUL << SCB_CFSR_MEMFAULTSR_Pos) /*!< SCB CFSR: Memory Manage Fault Status Register Mask */ + +/* SCB Hard Fault Status Registers Definitions */ +#define SCB_HFSR_DEBUGEVT_Pos 31 /*!< SCB HFSR: DEBUGEVT Position */ +#define SCB_HFSR_DEBUGEVT_Msk (1UL << SCB_HFSR_DEBUGEVT_Pos) /*!< SCB HFSR: DEBUGEVT Mask */ + +#define SCB_HFSR_FORCED_Pos 30 /*!< SCB HFSR: FORCED Position */ +#define SCB_HFSR_FORCED_Msk (1UL << SCB_HFSR_FORCED_Pos) /*!< SCB HFSR: FORCED Mask */ + +#define SCB_HFSR_VECTTBL_Pos 1 /*!< SCB HFSR: VECTTBL Position */ +#define SCB_HFSR_VECTTBL_Msk (1UL << SCB_HFSR_VECTTBL_Pos) /*!< SCB HFSR: VECTTBL Mask */ + +/* SCB Debug Fault Status Register Definitions */ +#define SCB_DFSR_EXTERNAL_Pos 4 /*!< SCB DFSR: EXTERNAL Position */ +#define SCB_DFSR_EXTERNAL_Msk (1UL << SCB_DFSR_EXTERNAL_Pos) /*!< SCB DFSR: EXTERNAL Mask */ + +#define SCB_DFSR_VCATCH_Pos 3 /*!< SCB DFSR: VCATCH Position */ +#define SCB_DFSR_VCATCH_Msk (1UL << SCB_DFSR_VCATCH_Pos) /*!< SCB DFSR: VCATCH Mask */ + +#define SCB_DFSR_DWTTRAP_Pos 2 /*!< SCB DFSR: DWTTRAP Position */ +#define SCB_DFSR_DWTTRAP_Msk (1UL << SCB_DFSR_DWTTRAP_Pos) /*!< SCB DFSR: DWTTRAP Mask */ + +#define SCB_DFSR_BKPT_Pos 1 /*!< SCB DFSR: BKPT Position */ +#define SCB_DFSR_BKPT_Msk (1UL << SCB_DFSR_BKPT_Pos) /*!< SCB DFSR: BKPT Mask */ + +#define SCB_DFSR_HALTED_Pos 0 /*!< SCB DFSR: HALTED Position */ +#define SCB_DFSR_HALTED_Msk (1UL << SCB_DFSR_HALTED_Pos) /*!< SCB DFSR: HALTED Mask */ + +/*@} end of group CMSIS_SCB */ + + +/** \ingroup CMSIS_core_register + \defgroup CMSIS_SCnSCB System Controls not in SCB (SCnSCB) + \brief Type definitions for the System Control and ID Register not in the SCB + @{ + */ + +/** \brief Structure type to access the System Control and ID Register not in the SCB. + */ +typedef struct +{ + uint32_t RESERVED0[1]; + __I uint32_t ICTR; /*!< Offset: 0x004 (R/ ) Interrupt Controller Type Register */ + uint32_t RESERVED1[1]; +} SCnSCB_Type; + +/* Interrupt Controller Type Register Definitions */ +#define SCnSCB_ICTR_INTLINESNUM_Pos 0 /*!< ICTR: INTLINESNUM Position */ +#define SCnSCB_ICTR_INTLINESNUM_Msk (0xFUL << SCnSCB_ICTR_INTLINESNUM_Pos) /*!< ICTR: INTLINESNUM Mask */ + +/*@} end of group CMSIS_SCnotSCB */ + + +/** \ingroup CMSIS_core_register + \defgroup CMSIS_SysTick System Tick Timer (SysTick) + \brief Type definitions for the System Timer Registers. + @{ + */ + +/** \brief Structure type to access the System Timer (SysTick). + */ +typedef struct +{ + __IO uint32_t CTRL; /*!< Offset: 0x000 (R/W) SysTick Control and Status Register */ + __IO uint32_t LOAD; /*!< Offset: 0x004 (R/W) SysTick Reload Value Register */ + __IO uint32_t VAL; /*!< Offset: 0x008 (R/W) SysTick Current Value Register */ + __I uint32_t CALIB; /*!< Offset: 0x00C (R/ ) SysTick Calibration Register */ +} SysTick_Type; + +/* SysTick Control / Status Register Definitions */ +#define SysTick_CTRL_COUNTFLAG_Pos 16 /*!< SysTick CTRL: COUNTFLAG Position */ +#define SysTick_CTRL_COUNTFLAG_Msk (1UL << SysTick_CTRL_COUNTFLAG_Pos) /*!< SysTick CTRL: COUNTFLAG Mask */ + +#define SysTick_CTRL_CLKSOURCE_Pos 2 /*!< SysTick CTRL: CLKSOURCE Position */ +#define SysTick_CTRL_CLKSOURCE_Msk (1UL << SysTick_CTRL_CLKSOURCE_Pos) /*!< SysTick CTRL: CLKSOURCE Mask */ + +#define SysTick_CTRL_TICKINT_Pos 1 /*!< SysTick CTRL: TICKINT Position */ +#define SysTick_CTRL_TICKINT_Msk (1UL << SysTick_CTRL_TICKINT_Pos) /*!< SysTick CTRL: TICKINT Mask */ + +#define SysTick_CTRL_ENABLE_Pos 0 /*!< SysTick CTRL: ENABLE Position */ +#define SysTick_CTRL_ENABLE_Msk (1UL << SysTick_CTRL_ENABLE_Pos) /*!< SysTick CTRL: ENABLE Mask */ + +/* SysTick Reload Register Definitions */ +#define SysTick_LOAD_RELOAD_Pos 0 /*!< SysTick LOAD: RELOAD Position */ +#define SysTick_LOAD_RELOAD_Msk (0xFFFFFFUL << SysTick_LOAD_RELOAD_Pos) /*!< SysTick LOAD: RELOAD Mask */ + +/* SysTick Current Register Definitions */ +#define SysTick_VAL_CURRENT_Pos 0 /*!< SysTick VAL: CURRENT Position */ +#define SysTick_VAL_CURRENT_Msk (0xFFFFFFUL << SysTick_VAL_CURRENT_Pos) /*!< SysTick VAL: CURRENT Mask */ + +/* SysTick Calibration Register Definitions */ +#define SysTick_CALIB_NOREF_Pos 31 /*!< SysTick CALIB: NOREF Position */ +#define SysTick_CALIB_NOREF_Msk (1UL << SysTick_CALIB_NOREF_Pos) /*!< SysTick CALIB: NOREF Mask */ + +#define SysTick_CALIB_SKEW_Pos 30 /*!< SysTick CALIB: SKEW Position */ +#define SysTick_CALIB_SKEW_Msk (1UL << SysTick_CALIB_SKEW_Pos) /*!< SysTick CALIB: SKEW Mask */ + +#define SysTick_CALIB_TENMS_Pos 0 /*!< SysTick CALIB: TENMS Position */ +#define SysTick_CALIB_TENMS_Msk (0xFFFFFFUL << SysTick_VAL_CURRENT_Pos) /*!< SysTick CALIB: TENMS Mask */ + +/*@} end of group CMSIS_SysTick */ + + +/** \ingroup CMSIS_core_register + \defgroup CMSIS_ITM Instrumentation Trace Macrocell (ITM) + \brief Type definitions for the Instrumentation Trace Macrocell (ITM) + @{ + */ + +/** \brief Structure type to access the Instrumentation Trace Macrocell Register (ITM). + */ +typedef struct +{ + __O union + { + __O uint8_t u8; /*!< Offset: 0x000 ( /W) ITM Stimulus Port 8-bit */ + __O uint16_t u16; /*!< Offset: 0x000 ( /W) ITM Stimulus Port 16-bit */ + __O uint32_t u32; /*!< Offset: 0x000 ( /W) ITM Stimulus Port 32-bit */ + } PORT [32]; /*!< Offset: 0x000 ( /W) ITM Stimulus Port Registers */ + uint32_t RESERVED0[864]; + __IO uint32_t TER; /*!< Offset: 0xE00 (R/W) ITM Trace Enable Register */ + uint32_t RESERVED1[15]; + __IO uint32_t TPR; /*!< Offset: 0xE40 (R/W) ITM Trace Privilege Register */ + uint32_t RESERVED2[15]; + __IO uint32_t TCR; /*!< Offset: 0xE80 (R/W) ITM Trace Control Register */ + uint32_t RESERVED3[29]; + __O uint32_t IWR; /*!< Offset: 0xEF8 ( /W) ITM Integration Write Register */ + __I uint32_t IRR; /*!< Offset: 0xEFC (R/ ) ITM Integration Read Register */ + __IO uint32_t IMCR; /*!< Offset: 0xF00 (R/W) ITM Integration Mode Control Register */ + uint32_t RESERVED4[43]; + __O uint32_t LAR; /*!< Offset: 0xFB0 ( /W) ITM Lock Access Register */ + __I uint32_t LSR; /*!< Offset: 0xFB4 (R/ ) ITM Lock Status Register */ + uint32_t RESERVED5[6]; + __I uint32_t PID4; /*!< Offset: 0xFD0 (R/ ) ITM Peripheral Identification Register #4 */ + __I uint32_t PID5; /*!< Offset: 0xFD4 (R/ ) ITM Peripheral Identification Register #5 */ + __I uint32_t PID6; /*!< Offset: 0xFD8 (R/ ) ITM Peripheral Identification Register #6 */ + __I uint32_t PID7; /*!< Offset: 0xFDC (R/ ) ITM Peripheral Identification Register #7 */ + __I uint32_t PID0; /*!< Offset: 0xFE0 (R/ ) ITM Peripheral Identification Register #0 */ + __I uint32_t PID1; /*!< Offset: 0xFE4 (R/ ) ITM Peripheral Identification Register #1 */ + __I uint32_t PID2; /*!< Offset: 0xFE8 (R/ ) ITM Peripheral Identification Register #2 */ + __I uint32_t PID3; /*!< Offset: 0xFEC (R/ ) ITM Peripheral Identification Register #3 */ + __I uint32_t CID0; /*!< Offset: 0xFF0 (R/ ) ITM Component Identification Register #0 */ + __I uint32_t CID1; /*!< Offset: 0xFF4 (R/ ) ITM Component Identification Register #1 */ + __I uint32_t CID2; /*!< Offset: 0xFF8 (R/ ) ITM Component Identification Register #2 */ + __I uint32_t CID3; /*!< Offset: 0xFFC (R/ ) ITM Component Identification Register #3 */ +} ITM_Type; + +/* ITM Trace Privilege Register Definitions */ +#define ITM_TPR_PRIVMASK_Pos 0 /*!< ITM TPR: PRIVMASK Position */ +#define ITM_TPR_PRIVMASK_Msk (0xFUL << ITM_TPR_PRIVMASK_Pos) /*!< ITM TPR: PRIVMASK Mask */ + +/* ITM Trace Control Register Definitions */ +#define ITM_TCR_BUSY_Pos 23 /*!< ITM TCR: BUSY Position */ +#define ITM_TCR_BUSY_Msk (1UL << ITM_TCR_BUSY_Pos) /*!< ITM TCR: BUSY Mask */ + +#define ITM_TCR_TraceBusID_Pos 16 /*!< ITM TCR: ATBID Position */ +#define ITM_TCR_TraceBusID_Msk (0x7FUL << ITM_TCR_TraceBusID_Pos) /*!< ITM TCR: ATBID Mask */ + +#define ITM_TCR_GTSFREQ_Pos 10 /*!< ITM TCR: Global timestamp frequency Position */ +#define ITM_TCR_GTSFREQ_Msk (3UL << ITM_TCR_GTSFREQ_Pos) /*!< ITM TCR: Global timestamp frequency Mask */ + +#define ITM_TCR_TSPrescale_Pos 8 /*!< ITM TCR: TSPrescale Position */ +#define ITM_TCR_TSPrescale_Msk (3UL << ITM_TCR_TSPrescale_Pos) /*!< ITM TCR: TSPrescale Mask */ + +#define ITM_TCR_SWOENA_Pos 4 /*!< ITM TCR: SWOENA Position */ +#define ITM_TCR_SWOENA_Msk (1UL << ITM_TCR_SWOENA_Pos) /*!< ITM TCR: SWOENA Mask */ + +#define ITM_TCR_DWTENA_Pos 3 /*!< ITM TCR: DWTENA Position */ +#define ITM_TCR_DWTENA_Msk (1UL << ITM_TCR_DWTENA_Pos) /*!< ITM TCR: DWTENA Mask */ + +#define ITM_TCR_SYNCENA_Pos 2 /*!< ITM TCR: SYNCENA Position */ +#define ITM_TCR_SYNCENA_Msk (1UL << ITM_TCR_SYNCENA_Pos) /*!< ITM TCR: SYNCENA Mask */ + +#define ITM_TCR_TSENA_Pos 1 /*!< ITM TCR: TSENA Position */ +#define ITM_TCR_TSENA_Msk (1UL << ITM_TCR_TSENA_Pos) /*!< ITM TCR: TSENA Mask */ + +#define ITM_TCR_ITMENA_Pos 0 /*!< ITM TCR: ITM Enable bit Position */ +#define ITM_TCR_ITMENA_Msk (1UL << ITM_TCR_ITMENA_Pos) /*!< ITM TCR: ITM Enable bit Mask */ + +/* ITM Integration Write Register Definitions */ +#define ITM_IWR_ATVALIDM_Pos 0 /*!< ITM IWR: ATVALIDM Position */ +#define ITM_IWR_ATVALIDM_Msk (1UL << ITM_IWR_ATVALIDM_Pos) /*!< ITM IWR: ATVALIDM Mask */ + +/* ITM Integration Read Register Definitions */ +#define ITM_IRR_ATREADYM_Pos 0 /*!< ITM IRR: ATREADYM Position */ +#define ITM_IRR_ATREADYM_Msk (1UL << ITM_IRR_ATREADYM_Pos) /*!< ITM IRR: ATREADYM Mask */ + +/* ITM Integration Mode Control Register Definitions */ +#define ITM_IMCR_INTEGRATION_Pos 0 /*!< ITM IMCR: INTEGRATION Position */ +#define ITM_IMCR_INTEGRATION_Msk (1UL << ITM_IMCR_INTEGRATION_Pos) /*!< ITM IMCR: INTEGRATION Mask */ + +/* ITM Lock Status Register Definitions */ +#define ITM_LSR_ByteAcc_Pos 2 /*!< ITM LSR: ByteAcc Position */ +#define ITM_LSR_ByteAcc_Msk (1UL << ITM_LSR_ByteAcc_Pos) /*!< ITM LSR: ByteAcc Mask */ + +#define ITM_LSR_Access_Pos 1 /*!< ITM LSR: Access Position */ +#define ITM_LSR_Access_Msk (1UL << ITM_LSR_Access_Pos) /*!< ITM LSR: Access Mask */ + +#define ITM_LSR_Present_Pos 0 /*!< ITM LSR: Present Position */ +#define ITM_LSR_Present_Msk (1UL << ITM_LSR_Present_Pos) /*!< ITM LSR: Present Mask */ + +/*@}*/ /* end of group CMSIS_ITM */ + + +/** \ingroup CMSIS_core_register + \defgroup CMSIS_DWT Data Watchpoint and Trace (DWT) + \brief Type definitions for the Data Watchpoint and Trace (DWT) + @{ + */ + +/** \brief Structure type to access the Data Watchpoint and Trace Register (DWT). + */ +typedef struct +{ + __IO uint32_t CTRL; /*!< Offset: 0x000 (R/W) Control Register */ + __IO uint32_t CYCCNT; /*!< Offset: 0x004 (R/W) Cycle Count Register */ + __IO uint32_t CPICNT; /*!< Offset: 0x008 (R/W) CPI Count Register */ + __IO uint32_t EXCCNT; /*!< Offset: 0x00C (R/W) Exception Overhead Count Register */ + __IO uint32_t SLEEPCNT; /*!< Offset: 0x010 (R/W) Sleep Count Register */ + __IO uint32_t LSUCNT; /*!< Offset: 0x014 (R/W) LSU Count Register */ + __IO uint32_t FOLDCNT; /*!< Offset: 0x018 (R/W) Folded-instruction Count Register */ + __I uint32_t PCSR; /*!< Offset: 0x01C (R/ ) Program Counter Sample Register */ + __IO uint32_t COMP0; /*!< Offset: 0x020 (R/W) Comparator Register 0 */ + __IO uint32_t MASK0; /*!< Offset: 0x024 (R/W) Mask Register 0 */ + __IO uint32_t FUNCTION0; /*!< Offset: 0x028 (R/W) Function Register 0 */ + uint32_t RESERVED0[1]; + __IO uint32_t COMP1; /*!< Offset: 0x030 (R/W) Comparator Register 1 */ + __IO uint32_t MASK1; /*!< Offset: 0x034 (R/W) Mask Register 1 */ + __IO uint32_t FUNCTION1; /*!< Offset: 0x038 (R/W) Function Register 1 */ + uint32_t RESERVED1[1]; + __IO uint32_t COMP2; /*!< Offset: 0x040 (R/W) Comparator Register 2 */ + __IO uint32_t MASK2; /*!< Offset: 0x044 (R/W) Mask Register 2 */ + __IO uint32_t FUNCTION2; /*!< Offset: 0x048 (R/W) Function Register 2 */ + uint32_t RESERVED2[1]; + __IO uint32_t COMP3; /*!< Offset: 0x050 (R/W) Comparator Register 3 */ + __IO uint32_t MASK3; /*!< Offset: 0x054 (R/W) Mask Register 3 */ + __IO uint32_t FUNCTION3; /*!< Offset: 0x058 (R/W) Function Register 3 */ +} DWT_Type; + +/* DWT Control Register Definitions */ +#define DWT_CTRL_NUMCOMP_Pos 28 /*!< DWT CTRL: NUMCOMP Position */ +#define DWT_CTRL_NUMCOMP_Msk (0xFUL << DWT_CTRL_NUMCOMP_Pos) /*!< DWT CTRL: NUMCOMP Mask */ + +#define DWT_CTRL_NOTRCPKT_Pos 27 /*!< DWT CTRL: NOTRCPKT Position */ +#define DWT_CTRL_NOTRCPKT_Msk (0x1UL << DWT_CTRL_NOTRCPKT_Pos) /*!< DWT CTRL: NOTRCPKT Mask */ + +#define DWT_CTRL_NOEXTTRIG_Pos 26 /*!< DWT CTRL: NOEXTTRIG Position */ +#define DWT_CTRL_NOEXTTRIG_Msk (0x1UL << DWT_CTRL_NOEXTTRIG_Pos) /*!< DWT CTRL: NOEXTTRIG Mask */ + +#define DWT_CTRL_NOCYCCNT_Pos 25 /*!< DWT CTRL: NOCYCCNT Position */ +#define DWT_CTRL_NOCYCCNT_Msk (0x1UL << DWT_CTRL_NOCYCCNT_Pos) /*!< DWT CTRL: NOCYCCNT Mask */ + +#define DWT_CTRL_NOPRFCNT_Pos 24 /*!< DWT CTRL: NOPRFCNT Position */ +#define DWT_CTRL_NOPRFCNT_Msk (0x1UL << DWT_CTRL_NOPRFCNT_Pos) /*!< DWT CTRL: NOPRFCNT Mask */ + +#define DWT_CTRL_CYCEVTENA_Pos 22 /*!< DWT CTRL: CYCEVTENA Position */ +#define DWT_CTRL_CYCEVTENA_Msk (0x1UL << DWT_CTRL_CYCEVTENA_Pos) /*!< DWT CTRL: CYCEVTENA Mask */ + +#define DWT_CTRL_FOLDEVTENA_Pos 21 /*!< DWT CTRL: FOLDEVTENA Position */ +#define DWT_CTRL_FOLDEVTENA_Msk (0x1UL << DWT_CTRL_FOLDEVTENA_Pos) /*!< DWT CTRL: FOLDEVTENA Mask */ + +#define DWT_CTRL_LSUEVTENA_Pos 20 /*!< DWT CTRL: LSUEVTENA Position */ +#define DWT_CTRL_LSUEVTENA_Msk (0x1UL << DWT_CTRL_LSUEVTENA_Pos) /*!< DWT CTRL: LSUEVTENA Mask */ + +#define DWT_CTRL_SLEEPEVTENA_Pos 19 /*!< DWT CTRL: SLEEPEVTENA Position */ +#define DWT_CTRL_SLEEPEVTENA_Msk (0x1UL << DWT_CTRL_SLEEPEVTENA_Pos) /*!< DWT CTRL: SLEEPEVTENA Mask */ + +#define DWT_CTRL_EXCEVTENA_Pos 18 /*!< DWT CTRL: EXCEVTENA Position */ +#define DWT_CTRL_EXCEVTENA_Msk (0x1UL << DWT_CTRL_EXCEVTENA_Pos) /*!< DWT CTRL: EXCEVTENA Mask */ + +#define DWT_CTRL_CPIEVTENA_Pos 17 /*!< DWT CTRL: CPIEVTENA Position */ +#define DWT_CTRL_CPIEVTENA_Msk (0x1UL << DWT_CTRL_CPIEVTENA_Pos) /*!< DWT CTRL: CPIEVTENA Mask */ + +#define DWT_CTRL_EXCTRCENA_Pos 16 /*!< DWT CTRL: EXCTRCENA Position */ +#define DWT_CTRL_EXCTRCENA_Msk (0x1UL << DWT_CTRL_EXCTRCENA_Pos) /*!< DWT CTRL: EXCTRCENA Mask */ + +#define DWT_CTRL_PCSAMPLENA_Pos 12 /*!< DWT CTRL: PCSAMPLENA Position */ +#define DWT_CTRL_PCSAMPLENA_Msk (0x1UL << DWT_CTRL_PCSAMPLENA_Pos) /*!< DWT CTRL: PCSAMPLENA Mask */ + +#define DWT_CTRL_SYNCTAP_Pos 10 /*!< DWT CTRL: SYNCTAP Position */ +#define DWT_CTRL_SYNCTAP_Msk (0x3UL << DWT_CTRL_SYNCTAP_Pos) /*!< DWT CTRL: SYNCTAP Mask */ + +#define DWT_CTRL_CYCTAP_Pos 9 /*!< DWT CTRL: CYCTAP Position */ +#define DWT_CTRL_CYCTAP_Msk (0x1UL << DWT_CTRL_CYCTAP_Pos) /*!< DWT CTRL: CYCTAP Mask */ + +#define DWT_CTRL_POSTINIT_Pos 5 /*!< DWT CTRL: POSTINIT Position */ +#define DWT_CTRL_POSTINIT_Msk (0xFUL << DWT_CTRL_POSTINIT_Pos) /*!< DWT CTRL: POSTINIT Mask */ + +#define DWT_CTRL_POSTPRESET_Pos 1 /*!< DWT CTRL: POSTPRESET Position */ +#define DWT_CTRL_POSTPRESET_Msk (0xFUL << DWT_CTRL_POSTPRESET_Pos) /*!< DWT CTRL: POSTPRESET Mask */ + +#define DWT_CTRL_CYCCNTENA_Pos 0 /*!< DWT CTRL: CYCCNTENA Position */ +#define DWT_CTRL_CYCCNTENA_Msk (0x1UL << DWT_CTRL_CYCCNTENA_Pos) /*!< DWT CTRL: CYCCNTENA Mask */ + +/* DWT CPI Count Register Definitions */ +#define DWT_CPICNT_CPICNT_Pos 0 /*!< DWT CPICNT: CPICNT Position */ +#define DWT_CPICNT_CPICNT_Msk (0xFFUL << DWT_CPICNT_CPICNT_Pos) /*!< DWT CPICNT: CPICNT Mask */ + +/* DWT Exception Overhead Count Register Definitions */ +#define DWT_EXCCNT_EXCCNT_Pos 0 /*!< DWT EXCCNT: EXCCNT Position */ +#define DWT_EXCCNT_EXCCNT_Msk (0xFFUL << DWT_EXCCNT_EXCCNT_Pos) /*!< DWT EXCCNT: EXCCNT Mask */ + +/* DWT Sleep Count Register Definitions */ +#define DWT_SLEEPCNT_SLEEPCNT_Pos 0 /*!< DWT SLEEPCNT: SLEEPCNT Position */ +#define DWT_SLEEPCNT_SLEEPCNT_Msk (0xFFUL << DWT_SLEEPCNT_SLEEPCNT_Pos) /*!< DWT SLEEPCNT: SLEEPCNT Mask */ + +/* DWT LSU Count Register Definitions */ +#define DWT_LSUCNT_LSUCNT_Pos 0 /*!< DWT LSUCNT: LSUCNT Position */ +#define DWT_LSUCNT_LSUCNT_Msk (0xFFUL << DWT_LSUCNT_LSUCNT_Pos) /*!< DWT LSUCNT: LSUCNT Mask */ + +/* DWT Folded-instruction Count Register Definitions */ +#define DWT_FOLDCNT_FOLDCNT_Pos 0 /*!< DWT FOLDCNT: FOLDCNT Position */ +#define DWT_FOLDCNT_FOLDCNT_Msk (0xFFUL << DWT_FOLDCNT_FOLDCNT_Pos) /*!< DWT FOLDCNT: FOLDCNT Mask */ + +/* DWT Comparator Mask Register Definitions */ +#define DWT_MASK_MASK_Pos 0 /*!< DWT MASK: MASK Position */ +#define DWT_MASK_MASK_Msk (0x1FUL << DWT_MASK_MASK_Pos) /*!< DWT MASK: MASK Mask */ + +/* DWT Comparator Function Register Definitions */ +#define DWT_FUNCTION_MATCHED_Pos 24 /*!< DWT FUNCTION: MATCHED Position */ +#define DWT_FUNCTION_MATCHED_Msk (0x1UL << DWT_FUNCTION_MATCHED_Pos) /*!< DWT FUNCTION: MATCHED Mask */ + +#define DWT_FUNCTION_DATAVADDR1_Pos 16 /*!< DWT FUNCTION: DATAVADDR1 Position */ +#define DWT_FUNCTION_DATAVADDR1_Msk (0xFUL << DWT_FUNCTION_DATAVADDR1_Pos) /*!< DWT FUNCTION: DATAVADDR1 Mask */ + +#define DWT_FUNCTION_DATAVADDR0_Pos 12 /*!< DWT FUNCTION: DATAVADDR0 Position */ +#define DWT_FUNCTION_DATAVADDR0_Msk (0xFUL << DWT_FUNCTION_DATAVADDR0_Pos) /*!< DWT FUNCTION: DATAVADDR0 Mask */ + +#define DWT_FUNCTION_DATAVSIZE_Pos 10 /*!< DWT FUNCTION: DATAVSIZE Position */ +#define DWT_FUNCTION_DATAVSIZE_Msk (0x3UL << DWT_FUNCTION_DATAVSIZE_Pos) /*!< DWT FUNCTION: DATAVSIZE Mask */ + +#define DWT_FUNCTION_LNK1ENA_Pos 9 /*!< DWT FUNCTION: LNK1ENA Position */ +#define DWT_FUNCTION_LNK1ENA_Msk (0x1UL << DWT_FUNCTION_LNK1ENA_Pos) /*!< DWT FUNCTION: LNK1ENA Mask */ + +#define DWT_FUNCTION_DATAVMATCH_Pos 8 /*!< DWT FUNCTION: DATAVMATCH Position */ +#define DWT_FUNCTION_DATAVMATCH_Msk (0x1UL << DWT_FUNCTION_DATAVMATCH_Pos) /*!< DWT FUNCTION: DATAVMATCH Mask */ + +#define DWT_FUNCTION_CYCMATCH_Pos 7 /*!< DWT FUNCTION: CYCMATCH Position */ +#define DWT_FUNCTION_CYCMATCH_Msk (0x1UL << DWT_FUNCTION_CYCMATCH_Pos) /*!< DWT FUNCTION: CYCMATCH Mask */ + +#define DWT_FUNCTION_EMITRANGE_Pos 5 /*!< DWT FUNCTION: EMITRANGE Position */ +#define DWT_FUNCTION_EMITRANGE_Msk (0x1UL << DWT_FUNCTION_EMITRANGE_Pos) /*!< DWT FUNCTION: EMITRANGE Mask */ + +#define DWT_FUNCTION_FUNCTION_Pos 0 /*!< DWT FUNCTION: FUNCTION Position */ +#define DWT_FUNCTION_FUNCTION_Msk (0xFUL << DWT_FUNCTION_FUNCTION_Pos) /*!< DWT FUNCTION: FUNCTION Mask */ + +/*@}*/ /* end of group CMSIS_DWT */ + + +/** \ingroup CMSIS_core_register + \defgroup CMSIS_TPI Trace Port Interface (TPI) + \brief Type definitions for the Trace Port Interface (TPI) + @{ + */ + +/** \brief Structure type to access the Trace Port Interface Register (TPI). + */ +typedef struct +{ + __IO uint32_t SSPSR; /*!< Offset: 0x000 (R/ ) Supported Parallel Port Size Register */ + __IO uint32_t CSPSR; /*!< Offset: 0x004 (R/W) Current Parallel Port Size Register */ + uint32_t RESERVED0[2]; + __IO uint32_t ACPR; /*!< Offset: 0x010 (R/W) Asynchronous Clock Prescaler Register */ + uint32_t RESERVED1[55]; + __IO uint32_t SPPR; /*!< Offset: 0x0F0 (R/W) Selected Pin Protocol Register */ + uint32_t RESERVED2[131]; + __I uint32_t FFSR; /*!< Offset: 0x300 (R/ ) Formatter and Flush Status Register */ + __IO uint32_t FFCR; /*!< Offset: 0x304 (R/W) Formatter and Flush Control Register */ + __I uint32_t FSCR; /*!< Offset: 0x308 (R/ ) Formatter Synchronization Counter Register */ + uint32_t RESERVED3[759]; + __I uint32_t TRIGGER; /*!< Offset: 0xEE8 (R/ ) TRIGGER */ + __I uint32_t FIFO0; /*!< Offset: 0xEEC (R/ ) Integration ETM Data */ + __I uint32_t ITATBCTR2; /*!< Offset: 0xEF0 (R/ ) ITATBCTR2 */ + uint32_t RESERVED4[1]; + __I uint32_t ITATBCTR0; /*!< Offset: 0xEF8 (R/ ) ITATBCTR0 */ + __I uint32_t FIFO1; /*!< Offset: 0xEFC (R/ ) Integration ITM Data */ + __IO uint32_t ITCTRL; /*!< Offset: 0xF00 (R/W) Integration Mode Control */ + uint32_t RESERVED5[39]; + __IO uint32_t CLAIMSET; /*!< Offset: 0xFA0 (R/W) Claim tag set */ + __IO uint32_t CLAIMCLR; /*!< Offset: 0xFA4 (R/W) Claim tag clear */ + uint32_t RESERVED7[8]; + __I uint32_t DEVID; /*!< Offset: 0xFC8 (R/ ) TPIU_DEVID */ + __I uint32_t DEVTYPE; /*!< Offset: 0xFCC (R/ ) TPIU_DEVTYPE */ +} TPI_Type; + +/* TPI Asynchronous Clock Prescaler Register Definitions */ +#define TPI_ACPR_PRESCALER_Pos 0 /*!< TPI ACPR: PRESCALER Position */ +#define TPI_ACPR_PRESCALER_Msk (0x1FFFUL << TPI_ACPR_PRESCALER_Pos) /*!< TPI ACPR: PRESCALER Mask */ + +/* TPI Selected Pin Protocol Register Definitions */ +#define TPI_SPPR_TXMODE_Pos 0 /*!< TPI SPPR: TXMODE Position */ +#define TPI_SPPR_TXMODE_Msk (0x3UL << TPI_SPPR_TXMODE_Pos) /*!< TPI SPPR: TXMODE Mask */ + +/* TPI Formatter and Flush Status Register Definitions */ +#define TPI_FFSR_FtNonStop_Pos 3 /*!< TPI FFSR: FtNonStop Position */ +#define TPI_FFSR_FtNonStop_Msk (0x1UL << TPI_FFSR_FtNonStop_Pos) /*!< TPI FFSR: FtNonStop Mask */ + +#define TPI_FFSR_TCPresent_Pos 2 /*!< TPI FFSR: TCPresent Position */ +#define TPI_FFSR_TCPresent_Msk (0x1UL << TPI_FFSR_TCPresent_Pos) /*!< TPI FFSR: TCPresent Mask */ + +#define TPI_FFSR_FtStopped_Pos 1 /*!< TPI FFSR: FtStopped Position */ +#define TPI_FFSR_FtStopped_Msk (0x1UL << TPI_FFSR_FtStopped_Pos) /*!< TPI FFSR: FtStopped Mask */ + +#define TPI_FFSR_FlInProg_Pos 0 /*!< TPI FFSR: FlInProg Position */ +#define TPI_FFSR_FlInProg_Msk (0x1UL << TPI_FFSR_FlInProg_Pos) /*!< TPI FFSR: FlInProg Mask */ + +/* TPI Formatter and Flush Control Register Definitions */ +#define TPI_FFCR_TrigIn_Pos 8 /*!< TPI FFCR: TrigIn Position */ +#define TPI_FFCR_TrigIn_Msk (0x1UL << TPI_FFCR_TrigIn_Pos) /*!< TPI FFCR: TrigIn Mask */ + +#define TPI_FFCR_EnFCont_Pos 1 /*!< TPI FFCR: EnFCont Position */ +#define TPI_FFCR_EnFCont_Msk (0x1UL << TPI_FFCR_EnFCont_Pos) /*!< TPI FFCR: EnFCont Mask */ + +/* TPI TRIGGER Register Definitions */ +#define TPI_TRIGGER_TRIGGER_Pos 0 /*!< TPI TRIGGER: TRIGGER Position */ +#define TPI_TRIGGER_TRIGGER_Msk (0x1UL << TPI_TRIGGER_TRIGGER_Pos) /*!< TPI TRIGGER: TRIGGER Mask */ + +/* TPI Integration ETM Data Register Definitions (FIFO0) */ +#define TPI_FIFO0_ITM_ATVALID_Pos 29 /*!< TPI FIFO0: ITM_ATVALID Position */ +#define TPI_FIFO0_ITM_ATVALID_Msk (0x3UL << TPI_FIFO0_ITM_ATVALID_Pos) /*!< TPI FIFO0: ITM_ATVALID Mask */ + +#define TPI_FIFO0_ITM_bytecount_Pos 27 /*!< TPI FIFO0: ITM_bytecount Position */ +#define TPI_FIFO0_ITM_bytecount_Msk (0x3UL << TPI_FIFO0_ITM_bytecount_Pos) /*!< TPI FIFO0: ITM_bytecount Mask */ + +#define TPI_FIFO0_ETM_ATVALID_Pos 26 /*!< TPI FIFO0: ETM_ATVALID Position */ +#define TPI_FIFO0_ETM_ATVALID_Msk (0x3UL << TPI_FIFO0_ETM_ATVALID_Pos) /*!< TPI FIFO0: ETM_ATVALID Mask */ + +#define TPI_FIFO0_ETM_bytecount_Pos 24 /*!< TPI FIFO0: ETM_bytecount Position */ +#define TPI_FIFO0_ETM_bytecount_Msk (0x3UL << TPI_FIFO0_ETM_bytecount_Pos) /*!< TPI FIFO0: ETM_bytecount Mask */ + +#define TPI_FIFO0_ETM2_Pos 16 /*!< TPI FIFO0: ETM2 Position */ +#define TPI_FIFO0_ETM2_Msk (0xFFUL << TPI_FIFO0_ETM2_Pos) /*!< TPI FIFO0: ETM2 Mask */ + +#define TPI_FIFO0_ETM1_Pos 8 /*!< TPI FIFO0: ETM1 Position */ +#define TPI_FIFO0_ETM1_Msk (0xFFUL << TPI_FIFO0_ETM1_Pos) /*!< TPI FIFO0: ETM1 Mask */ + +#define TPI_FIFO0_ETM0_Pos 0 /*!< TPI FIFO0: ETM0 Position */ +#define TPI_FIFO0_ETM0_Msk (0xFFUL << TPI_FIFO0_ETM0_Pos) /*!< TPI FIFO0: ETM0 Mask */ + +/* TPI ITATBCTR2 Register Definitions */ +#define TPI_ITATBCTR2_ATREADY_Pos 0 /*!< TPI ITATBCTR2: ATREADY Position */ +#define TPI_ITATBCTR2_ATREADY_Msk (0x1UL << TPI_ITATBCTR2_ATREADY_Pos) /*!< TPI ITATBCTR2: ATREADY Mask */ + +/* TPI Integration ITM Data Register Definitions (FIFO1) */ +#define TPI_FIFO1_ITM_ATVALID_Pos 29 /*!< TPI FIFO1: ITM_ATVALID Position */ +#define TPI_FIFO1_ITM_ATVALID_Msk (0x3UL << TPI_FIFO1_ITM_ATVALID_Pos) /*!< TPI FIFO1: ITM_ATVALID Mask */ + +#define TPI_FIFO1_ITM_bytecount_Pos 27 /*!< TPI FIFO1: ITM_bytecount Position */ +#define TPI_FIFO1_ITM_bytecount_Msk (0x3UL << TPI_FIFO1_ITM_bytecount_Pos) /*!< TPI FIFO1: ITM_bytecount Mask */ + +#define TPI_FIFO1_ETM_ATVALID_Pos 26 /*!< TPI FIFO1: ETM_ATVALID Position */ +#define TPI_FIFO1_ETM_ATVALID_Msk (0x3UL << TPI_FIFO1_ETM_ATVALID_Pos) /*!< TPI FIFO1: ETM_ATVALID Mask */ + +#define TPI_FIFO1_ETM_bytecount_Pos 24 /*!< TPI FIFO1: ETM_bytecount Position */ +#define TPI_FIFO1_ETM_bytecount_Msk (0x3UL << TPI_FIFO1_ETM_bytecount_Pos) /*!< TPI FIFO1: ETM_bytecount Mask */ + +#define TPI_FIFO1_ITM2_Pos 16 /*!< TPI FIFO1: ITM2 Position */ +#define TPI_FIFO1_ITM2_Msk (0xFFUL << TPI_FIFO1_ITM2_Pos) /*!< TPI FIFO1: ITM2 Mask */ + +#define TPI_FIFO1_ITM1_Pos 8 /*!< TPI FIFO1: ITM1 Position */ +#define TPI_FIFO1_ITM1_Msk (0xFFUL << TPI_FIFO1_ITM1_Pos) /*!< TPI FIFO1: ITM1 Mask */ + +#define TPI_FIFO1_ITM0_Pos 0 /*!< TPI FIFO1: ITM0 Position */ +#define TPI_FIFO1_ITM0_Msk (0xFFUL << TPI_FIFO1_ITM0_Pos) /*!< TPI FIFO1: ITM0 Mask */ + +/* TPI ITATBCTR0 Register Definitions */ +#define TPI_ITATBCTR0_ATREADY_Pos 0 /*!< TPI ITATBCTR0: ATREADY Position */ +#define TPI_ITATBCTR0_ATREADY_Msk (0x1UL << TPI_ITATBCTR0_ATREADY_Pos) /*!< TPI ITATBCTR0: ATREADY Mask */ + +/* TPI Integration Mode Control Register Definitions */ +#define TPI_ITCTRL_Mode_Pos 0 /*!< TPI ITCTRL: Mode Position */ +#define TPI_ITCTRL_Mode_Msk (0x1UL << TPI_ITCTRL_Mode_Pos) /*!< TPI ITCTRL: Mode Mask */ + +/* TPI DEVID Register Definitions */ +#define TPI_DEVID_NRZVALID_Pos 11 /*!< TPI DEVID: NRZVALID Position */ +#define TPI_DEVID_NRZVALID_Msk (0x1UL << TPI_DEVID_NRZVALID_Pos) /*!< TPI DEVID: NRZVALID Mask */ + +#define TPI_DEVID_MANCVALID_Pos 10 /*!< TPI DEVID: MANCVALID Position */ +#define TPI_DEVID_MANCVALID_Msk (0x1UL << TPI_DEVID_MANCVALID_Pos) /*!< TPI DEVID: MANCVALID Mask */ + +#define TPI_DEVID_PTINVALID_Pos 9 /*!< TPI DEVID: PTINVALID Position */ +#define TPI_DEVID_PTINVALID_Msk (0x1UL << TPI_DEVID_PTINVALID_Pos) /*!< TPI DEVID: PTINVALID Mask */ + +#define TPI_DEVID_MinBufSz_Pos 6 /*!< TPI DEVID: MinBufSz Position */ +#define TPI_DEVID_MinBufSz_Msk (0x7UL << TPI_DEVID_MinBufSz_Pos) /*!< TPI DEVID: MinBufSz Mask */ + +#define TPI_DEVID_AsynClkIn_Pos 5 /*!< TPI DEVID: AsynClkIn Position */ +#define TPI_DEVID_AsynClkIn_Msk (0x1UL << TPI_DEVID_AsynClkIn_Pos) /*!< TPI DEVID: AsynClkIn Mask */ + +#define TPI_DEVID_NrTraceInput_Pos 0 /*!< TPI DEVID: NrTraceInput Position */ +#define TPI_DEVID_NrTraceInput_Msk (0x1FUL << TPI_DEVID_NrTraceInput_Pos) /*!< TPI DEVID: NrTraceInput Mask */ + +/* TPI DEVTYPE Register Definitions */ +#define TPI_DEVTYPE_SubType_Pos 0 /*!< TPI DEVTYPE: SubType Position */ +#define TPI_DEVTYPE_SubType_Msk (0xFUL << TPI_DEVTYPE_SubType_Pos) /*!< TPI DEVTYPE: SubType Mask */ + +#define TPI_DEVTYPE_MajorType_Pos 4 /*!< TPI DEVTYPE: MajorType Position */ +#define TPI_DEVTYPE_MajorType_Msk (0xFUL << TPI_DEVTYPE_MajorType_Pos) /*!< TPI DEVTYPE: MajorType Mask */ + +/*@}*/ /* end of group CMSIS_TPI */ + + +#if (__MPU_PRESENT == 1) +/** \ingroup CMSIS_core_register + \defgroup CMSIS_MPU Memory Protection Unit (MPU) + \brief Type definitions for the Memory Protection Unit (MPU) + @{ + */ + +/** \brief Structure type to access the Memory Protection Unit (MPU). + */ +typedef struct +{ + __I uint32_t TYPE; /*!< Offset: 0x000 (R/ ) MPU Type Register */ + __IO uint32_t CTRL; /*!< Offset: 0x004 (R/W) MPU Control Register */ + __IO uint32_t RNR; /*!< Offset: 0x008 (R/W) MPU Region RNRber Register */ + __IO uint32_t RBAR; /*!< Offset: 0x00C (R/W) MPU Region Base Address Register */ + __IO uint32_t RASR; /*!< Offset: 0x010 (R/W) MPU Region Attribute and Size Register */ + __IO uint32_t RBAR_A1; /*!< Offset: 0x014 (R/W) MPU Alias 1 Region Base Address Register */ + __IO uint32_t RASR_A1; /*!< Offset: 0x018 (R/W) MPU Alias 1 Region Attribute and Size Register */ + __IO uint32_t RBAR_A2; /*!< Offset: 0x01C (R/W) MPU Alias 2 Region Base Address Register */ + __IO uint32_t RASR_A2; /*!< Offset: 0x020 (R/W) MPU Alias 2 Region Attribute and Size Register */ + __IO uint32_t RBAR_A3; /*!< Offset: 0x024 (R/W) MPU Alias 3 Region Base Address Register */ + __IO uint32_t RASR_A3; /*!< Offset: 0x028 (R/W) MPU Alias 3 Region Attribute and Size Register */ +} MPU_Type; + +/* MPU Type Register */ +#define MPU_TYPE_IREGION_Pos 16 /*!< MPU TYPE: IREGION Position */ +#define MPU_TYPE_IREGION_Msk (0xFFUL << MPU_TYPE_IREGION_Pos) /*!< MPU TYPE: IREGION Mask */ + +#define MPU_TYPE_DREGION_Pos 8 /*!< MPU TYPE: DREGION Position */ +#define MPU_TYPE_DREGION_Msk (0xFFUL << MPU_TYPE_DREGION_Pos) /*!< MPU TYPE: DREGION Mask */ + +#define MPU_TYPE_SEPARATE_Pos 0 /*!< MPU TYPE: SEPARATE Position */ +#define MPU_TYPE_SEPARATE_Msk (1UL << MPU_TYPE_SEPARATE_Pos) /*!< MPU TYPE: SEPARATE Mask */ + +/* MPU Control Register */ +#define MPU_CTRL_PRIVDEFENA_Pos 2 /*!< MPU CTRL: PRIVDEFENA Position */ +#define MPU_CTRL_PRIVDEFENA_Msk (1UL << MPU_CTRL_PRIVDEFENA_Pos) /*!< MPU CTRL: PRIVDEFENA Mask */ + +#define MPU_CTRL_HFNMIENA_Pos 1 /*!< MPU CTRL: HFNMIENA Position */ +#define MPU_CTRL_HFNMIENA_Msk (1UL << MPU_CTRL_HFNMIENA_Pos) /*!< MPU CTRL: HFNMIENA Mask */ + +#define MPU_CTRL_ENABLE_Pos 0 /*!< MPU CTRL: ENABLE Position */ +#define MPU_CTRL_ENABLE_Msk (1UL << MPU_CTRL_ENABLE_Pos) /*!< MPU CTRL: ENABLE Mask */ + +/* MPU Region Number Register */ +#define MPU_RNR_REGION_Pos 0 /*!< MPU RNR: REGION Position */ +#define MPU_RNR_REGION_Msk (0xFFUL << MPU_RNR_REGION_Pos) /*!< MPU RNR: REGION Mask */ + +/* MPU Region Base Address Register */ +#define MPU_RBAR_ADDR_Pos 5 /*!< MPU RBAR: ADDR Position */ +#define MPU_RBAR_ADDR_Msk (0x7FFFFFFUL << MPU_RBAR_ADDR_Pos) /*!< MPU RBAR: ADDR Mask */ + +#define MPU_RBAR_VALID_Pos 4 /*!< MPU RBAR: VALID Position */ +#define MPU_RBAR_VALID_Msk (1UL << MPU_RBAR_VALID_Pos) /*!< MPU RBAR: VALID Mask */ + +#define MPU_RBAR_REGION_Pos 0 /*!< MPU RBAR: REGION Position */ +#define MPU_RBAR_REGION_Msk (0xFUL << MPU_RBAR_REGION_Pos) /*!< MPU RBAR: REGION Mask */ + +/* MPU Region Attribute and Size Register */ +#define MPU_RASR_ATTRS_Pos 16 /*!< MPU RASR: MPU Region Attribute field Position */ +#define MPU_RASR_ATTRS_Msk (0xFFFFUL << MPU_RASR_ATTRS_Pos) /*!< MPU RASR: MPU Region Attribute field Mask */ + +#define MPU_RASR_XN_Pos 28 /*!< MPU RASR: ATTRS.XN Position */ +#define MPU_RASR_XN_Msk (1UL << MPU_RASR_XN_Pos) /*!< MPU RASR: ATTRS.XN Mask */ + +#define MPU_RASR_AP_Pos 24 /*!< MPU RASR: ATTRS.AP Position */ +#define MPU_RASR_AP_Msk (0x7UL << MPU_RASR_AP_Pos) /*!< MPU RASR: ATTRS.AP Mask */ + +#define MPU_RASR_TEX_Pos 19 /*!< MPU RASR: ATTRS.TEX Position */ +#define MPU_RASR_TEX_Msk (0x7UL << MPU_RASR_TEX_Pos) /*!< MPU RASR: ATTRS.TEX Mask */ + +#define MPU_RASR_S_Pos 18 /*!< MPU RASR: ATTRS.S Position */ +#define MPU_RASR_S_Msk (1UL << MPU_RASR_S_Pos) /*!< MPU RASR: ATTRS.S Mask */ + +#define MPU_RASR_C_Pos 17 /*!< MPU RASR: ATTRS.C Position */ +#define MPU_RASR_C_Msk (1UL << MPU_RASR_C_Pos) /*!< MPU RASR: ATTRS.C Mask */ + +#define MPU_RASR_B_Pos 16 /*!< MPU RASR: ATTRS.B Position */ +#define MPU_RASR_B_Msk (1UL << MPU_RASR_B_Pos) /*!< MPU RASR: ATTRS.B Mask */ + +#define MPU_RASR_SRD_Pos 8 /*!< MPU RASR: Sub-Region Disable Position */ +#define MPU_RASR_SRD_Msk (0xFFUL << MPU_RASR_SRD_Pos) /*!< MPU RASR: Sub-Region Disable Mask */ + +#define MPU_RASR_SIZE_Pos 1 /*!< MPU RASR: Region Size Field Position */ +#define MPU_RASR_SIZE_Msk (0x1FUL << MPU_RASR_SIZE_Pos) /*!< MPU RASR: Region Size Field Mask */ + +#define MPU_RASR_ENABLE_Pos 0 /*!< MPU RASR: Region enable bit Position */ +#define MPU_RASR_ENABLE_Msk (1UL << MPU_RASR_ENABLE_Pos) /*!< MPU RASR: Region enable bit Disable Mask */ + +/*@} end of group CMSIS_MPU */ +#endif + + +/** \ingroup CMSIS_core_register + \defgroup CMSIS_CoreDebug Core Debug Registers (CoreDebug) + \brief Type definitions for the Core Debug Registers + @{ + */ + +/** \brief Structure type to access the Core Debug Register (CoreDebug). + */ +typedef struct +{ + __IO uint32_t DHCSR; /*!< Offset: 0x000 (R/W) Debug Halting Control and Status Register */ + __O uint32_t DCRSR; /*!< Offset: 0x004 ( /W) Debug Core Register Selector Register */ + __IO uint32_t DCRDR; /*!< Offset: 0x008 (R/W) Debug Core Register Data Register */ + __IO uint32_t DEMCR; /*!< Offset: 0x00C (R/W) Debug Exception and Monitor Control Register */ +} CoreDebug_Type; + +/* Debug Halting Control and Status Register */ +#define CoreDebug_DHCSR_DBGKEY_Pos 16 /*!< CoreDebug DHCSR: DBGKEY Position */ +#define CoreDebug_DHCSR_DBGKEY_Msk (0xFFFFUL << CoreDebug_DHCSR_DBGKEY_Pos) /*!< CoreDebug DHCSR: DBGKEY Mask */ + +#define CoreDebug_DHCSR_S_RESET_ST_Pos 25 /*!< CoreDebug DHCSR: S_RESET_ST Position */ +#define CoreDebug_DHCSR_S_RESET_ST_Msk (1UL << CoreDebug_DHCSR_S_RESET_ST_Pos) /*!< CoreDebug DHCSR: S_RESET_ST Mask */ + +#define CoreDebug_DHCSR_S_RETIRE_ST_Pos 24 /*!< CoreDebug DHCSR: S_RETIRE_ST Position */ +#define CoreDebug_DHCSR_S_RETIRE_ST_Msk (1UL << CoreDebug_DHCSR_S_RETIRE_ST_Pos) /*!< CoreDebug DHCSR: S_RETIRE_ST Mask */ + +#define CoreDebug_DHCSR_S_LOCKUP_Pos 19 /*!< CoreDebug DHCSR: S_LOCKUP Position */ +#define CoreDebug_DHCSR_S_LOCKUP_Msk (1UL << CoreDebug_DHCSR_S_LOCKUP_Pos) /*!< CoreDebug DHCSR: S_LOCKUP Mask */ + +#define CoreDebug_DHCSR_S_SLEEP_Pos 18 /*!< CoreDebug DHCSR: S_SLEEP Position */ +#define CoreDebug_DHCSR_S_SLEEP_Msk (1UL << CoreDebug_DHCSR_S_SLEEP_Pos) /*!< CoreDebug DHCSR: S_SLEEP Mask */ + +#define CoreDebug_DHCSR_S_HALT_Pos 17 /*!< CoreDebug DHCSR: S_HALT Position */ +#define CoreDebug_DHCSR_S_HALT_Msk (1UL << CoreDebug_DHCSR_S_HALT_Pos) /*!< CoreDebug DHCSR: S_HALT Mask */ + +#define CoreDebug_DHCSR_S_REGRDY_Pos 16 /*!< CoreDebug DHCSR: S_REGRDY Position */ +#define CoreDebug_DHCSR_S_REGRDY_Msk (1UL << CoreDebug_DHCSR_S_REGRDY_Pos) /*!< CoreDebug DHCSR: S_REGRDY Mask */ + +#define CoreDebug_DHCSR_C_SNAPSTALL_Pos 5 /*!< CoreDebug DHCSR: C_SNAPSTALL Position */ +#define CoreDebug_DHCSR_C_SNAPSTALL_Msk (1UL << CoreDebug_DHCSR_C_SNAPSTALL_Pos) /*!< CoreDebug DHCSR: C_SNAPSTALL Mask */ + +#define CoreDebug_DHCSR_C_MASKINTS_Pos 3 /*!< CoreDebug DHCSR: C_MASKINTS Position */ +#define CoreDebug_DHCSR_C_MASKINTS_Msk (1UL << CoreDebug_DHCSR_C_MASKINTS_Pos) /*!< CoreDebug DHCSR: C_MASKINTS Mask */ + +#define CoreDebug_DHCSR_C_STEP_Pos 2 /*!< CoreDebug DHCSR: C_STEP Position */ +#define CoreDebug_DHCSR_C_STEP_Msk (1UL << CoreDebug_DHCSR_C_STEP_Pos) /*!< CoreDebug DHCSR: C_STEP Mask */ + +#define CoreDebug_DHCSR_C_HALT_Pos 1 /*!< CoreDebug DHCSR: C_HALT Position */ +#define CoreDebug_DHCSR_C_HALT_Msk (1UL << CoreDebug_DHCSR_C_HALT_Pos) /*!< CoreDebug DHCSR: C_HALT Mask */ + +#define CoreDebug_DHCSR_C_DEBUGEN_Pos 0 /*!< CoreDebug DHCSR: C_DEBUGEN Position */ +#define CoreDebug_DHCSR_C_DEBUGEN_Msk (1UL << CoreDebug_DHCSR_C_DEBUGEN_Pos) /*!< CoreDebug DHCSR: C_DEBUGEN Mask */ + +/* Debug Core Register Selector Register */ +#define CoreDebug_DCRSR_REGWnR_Pos 16 /*!< CoreDebug DCRSR: REGWnR Position */ +#define CoreDebug_DCRSR_REGWnR_Msk (1UL << CoreDebug_DCRSR_REGWnR_Pos) /*!< CoreDebug DCRSR: REGWnR Mask */ + +#define CoreDebug_DCRSR_REGSEL_Pos 0 /*!< CoreDebug DCRSR: REGSEL Position */ +#define CoreDebug_DCRSR_REGSEL_Msk (0x1FUL << CoreDebug_DCRSR_REGSEL_Pos) /*!< CoreDebug DCRSR: REGSEL Mask */ + +/* Debug Exception and Monitor Control Register */ +#define CoreDebug_DEMCR_TRCENA_Pos 24 /*!< CoreDebug DEMCR: TRCENA Position */ +#define CoreDebug_DEMCR_TRCENA_Msk (1UL << CoreDebug_DEMCR_TRCENA_Pos) /*!< CoreDebug DEMCR: TRCENA Mask */ + +#define CoreDebug_DEMCR_MON_REQ_Pos 19 /*!< CoreDebug DEMCR: MON_REQ Position */ +#define CoreDebug_DEMCR_MON_REQ_Msk (1UL << CoreDebug_DEMCR_MON_REQ_Pos) /*!< CoreDebug DEMCR: MON_REQ Mask */ + +#define CoreDebug_DEMCR_MON_STEP_Pos 18 /*!< CoreDebug DEMCR: MON_STEP Position */ +#define CoreDebug_DEMCR_MON_STEP_Msk (1UL << CoreDebug_DEMCR_MON_STEP_Pos) /*!< CoreDebug DEMCR: MON_STEP Mask */ + +#define CoreDebug_DEMCR_MON_PEND_Pos 17 /*!< CoreDebug DEMCR: MON_PEND Position */ +#define CoreDebug_DEMCR_MON_PEND_Msk (1UL << CoreDebug_DEMCR_MON_PEND_Pos) /*!< CoreDebug DEMCR: MON_PEND Mask */ + +#define CoreDebug_DEMCR_MON_EN_Pos 16 /*!< CoreDebug DEMCR: MON_EN Position */ +#define CoreDebug_DEMCR_MON_EN_Msk (1UL << CoreDebug_DEMCR_MON_EN_Pos) /*!< CoreDebug DEMCR: MON_EN Mask */ + +#define CoreDebug_DEMCR_VC_HARDERR_Pos 10 /*!< CoreDebug DEMCR: VC_HARDERR Position */ +#define CoreDebug_DEMCR_VC_HARDERR_Msk (1UL << CoreDebug_DEMCR_VC_HARDERR_Pos) /*!< CoreDebug DEMCR: VC_HARDERR Mask */ + +#define CoreDebug_DEMCR_VC_INTERR_Pos 9 /*!< CoreDebug DEMCR: VC_INTERR Position */ +#define CoreDebug_DEMCR_VC_INTERR_Msk (1UL << CoreDebug_DEMCR_VC_INTERR_Pos) /*!< CoreDebug DEMCR: VC_INTERR Mask */ + +#define CoreDebug_DEMCR_VC_BUSERR_Pos 8 /*!< CoreDebug DEMCR: VC_BUSERR Position */ +#define CoreDebug_DEMCR_VC_BUSERR_Msk (1UL << CoreDebug_DEMCR_VC_BUSERR_Pos) /*!< CoreDebug DEMCR: VC_BUSERR Mask */ + +#define CoreDebug_DEMCR_VC_STATERR_Pos 7 /*!< CoreDebug DEMCR: VC_STATERR Position */ +#define CoreDebug_DEMCR_VC_STATERR_Msk (1UL << CoreDebug_DEMCR_VC_STATERR_Pos) /*!< CoreDebug DEMCR: VC_STATERR Mask */ + +#define CoreDebug_DEMCR_VC_CHKERR_Pos 6 /*!< CoreDebug DEMCR: VC_CHKERR Position */ +#define CoreDebug_DEMCR_VC_CHKERR_Msk (1UL << CoreDebug_DEMCR_VC_CHKERR_Pos) /*!< CoreDebug DEMCR: VC_CHKERR Mask */ + +#define CoreDebug_DEMCR_VC_NOCPERR_Pos 5 /*!< CoreDebug DEMCR: VC_NOCPERR Position */ +#define CoreDebug_DEMCR_VC_NOCPERR_Msk (1UL << CoreDebug_DEMCR_VC_NOCPERR_Pos) /*!< CoreDebug DEMCR: VC_NOCPERR Mask */ + +#define CoreDebug_DEMCR_VC_MMERR_Pos 4 /*!< CoreDebug DEMCR: VC_MMERR Position */ +#define CoreDebug_DEMCR_VC_MMERR_Msk (1UL << CoreDebug_DEMCR_VC_MMERR_Pos) /*!< CoreDebug DEMCR: VC_MMERR Mask */ + +#define CoreDebug_DEMCR_VC_CORERESET_Pos 0 /*!< CoreDebug DEMCR: VC_CORERESET Position */ +#define CoreDebug_DEMCR_VC_CORERESET_Msk (1UL << CoreDebug_DEMCR_VC_CORERESET_Pos) /*!< CoreDebug DEMCR: VC_CORERESET Mask */ + +/*@} end of group CMSIS_CoreDebug */ + + +/** \ingroup CMSIS_core_register + \defgroup CMSIS_core_base Core Definitions + \brief Definitions for base addresses, unions, and structures. + @{ + */ + +/* Memory mapping of Cortex-M3 Hardware */ +#define SCS_BASE (0xE000E000UL) /*!< System Control Space Base Address */ +#define ITM_BASE (0xE0000000UL) /*!< ITM Base Address */ +#define DWT_BASE (0xE0001000UL) /*!< DWT Base Address */ +#define TPI_BASE (0xE0040000UL) /*!< TPI Base Address */ +#define CoreDebug_BASE (0xE000EDF0UL) /*!< Core Debug Base Address */ +#define SysTick_BASE (SCS_BASE + 0x0010UL) /*!< SysTick Base Address */ +#define NVIC_BASE (SCS_BASE + 0x0100UL) /*!< NVIC Base Address */ +#define SCB_BASE (SCS_BASE + 0x0D00UL) /*!< System Control Block Base Address */ + +#define SCnSCB ((SCnSCB_Type *) SCS_BASE ) /*!< System control Register not in SCB */ +#define SCB ((SCB_Type *) SCB_BASE ) /*!< SCB configuration struct */ +#define SysTick ((SysTick_Type *) SysTick_BASE ) /*!< SysTick configuration struct */ +#define NVIC ((NVIC_Type *) NVIC_BASE ) /*!< NVIC configuration struct */ +#define ITM ((ITM_Type *) ITM_BASE ) /*!< ITM configuration struct */ +#define DWT ((DWT_Type *) DWT_BASE ) /*!< DWT configuration struct */ +#define TPI ((TPI_Type *) TPI_BASE ) /*!< TPI configuration struct */ +#define CoreDebug ((CoreDebug_Type *) CoreDebug_BASE) /*!< Core Debug configuration struct */ + +#if (__MPU_PRESENT == 1) + #define MPU_BASE (SCS_BASE + 0x0D90UL) /*!< Memory Protection Unit */ + #define MPU ((MPU_Type *) MPU_BASE ) /*!< Memory Protection Unit */ +#endif + +/*@} */ + + + +/******************************************************************************* + * Hardware Abstraction Layer + Core Function Interface contains: + - Core NVIC Functions + - Core SysTick Functions + - Core Debug Functions + - Core Register Access Functions + ******************************************************************************/ +/** \defgroup CMSIS_Core_FunctionInterface Functions and Instructions Reference +*/ + + + +/* ########################## NVIC functions #################################### */ +/** \ingroup CMSIS_Core_FunctionInterface + \defgroup CMSIS_Core_NVICFunctions NVIC Functions + \brief Functions that manage interrupts and exceptions via the NVIC. + @{ + */ + +/** \brief Set Priority Grouping + + The function sets the priority grouping field using the required unlock sequence. + The parameter PriorityGroup is assigned to the field SCB->AIRCR [10:8] PRIGROUP field. + Only values from 0..7 are used. + In case of a conflict between priority grouping and available + priority bits (__NVIC_PRIO_BITS), the smallest possible priority group is set. + + \param [in] PriorityGroup Priority grouping field. + */ +__STATIC_INLINE void NVIC_SetPriorityGrouping(uint32_t PriorityGroup) +{ + uint32_t reg_value; + uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07); /* only values 0..7 are used */ + + reg_value = SCB->AIRCR; /* read old register configuration */ + reg_value &= ~(SCB_AIRCR_VECTKEY_Msk | SCB_AIRCR_PRIGROUP_Msk); /* clear bits to change */ + reg_value = (reg_value | + ((uint32_t)0x5FA << SCB_AIRCR_VECTKEY_Pos) | + (PriorityGroupTmp << 8)); /* Insert write key and priorty group */ + SCB->AIRCR = reg_value; +} + + +/** \brief Get Priority Grouping + + The function reads the priority grouping field from the NVIC Interrupt Controller. + + \return Priority grouping field (SCB->AIRCR [10:8] PRIGROUP field). + */ +__STATIC_INLINE uint32_t NVIC_GetPriorityGrouping(void) +{ + return ((SCB->AIRCR & SCB_AIRCR_PRIGROUP_Msk) >> SCB_AIRCR_PRIGROUP_Pos); /* read priority grouping field */ +} + + +/** \brief Enable External Interrupt + + The function enables a device-specific interrupt in the NVIC interrupt controller. + + \param [in] IRQn External interrupt number. Value cannot be negative. + */ +__STATIC_INLINE void NVIC_EnableIRQ(IRQn_Type IRQn) +{ + NVIC->ISER[((uint32_t)(IRQn) >> 5)] = (1 << ((uint32_t)(IRQn) & 0x1F)); /* enable interrupt */ +} + + +/** \brief Disable External Interrupt + + The function disables a device-specific interrupt in the NVIC interrupt controller. + + \param [in] IRQn External interrupt number. Value cannot be negative. + */ +__STATIC_INLINE void NVIC_DisableIRQ(IRQn_Type IRQn) +{ + NVIC->ICER[((uint32_t)(IRQn) >> 5)] = (1 << ((uint32_t)(IRQn) & 0x1F)); /* disable interrupt */ +} + + +/** \brief Get Pending Interrupt + + The function reads the pending register in the NVIC and returns the pending bit + for the specified interrupt. + + \param [in] IRQn Interrupt number. + + \return 0 Interrupt status is not pending. + \return 1 Interrupt status is pending. + */ +__STATIC_INLINE uint32_t NVIC_GetPendingIRQ(IRQn_Type IRQn) +{ + return((uint32_t) ((NVIC->ISPR[(uint32_t)(IRQn) >> 5] & (1 << ((uint32_t)(IRQn) & 0x1F)))?1:0)); /* Return 1 if pending else 0 */ +} + + +/** \brief Set Pending Interrupt + + The function sets the pending bit of an external interrupt. + + \param [in] IRQn Interrupt number. Value cannot be negative. + */ +__STATIC_INLINE void NVIC_SetPendingIRQ(IRQn_Type IRQn) +{ + NVIC->ISPR[((uint32_t)(IRQn) >> 5)] = (1 << ((uint32_t)(IRQn) & 0x1F)); /* set interrupt pending */ +} + + +/** \brief Clear Pending Interrupt + + The function clears the pending bit of an external interrupt. + + \param [in] IRQn External interrupt number. Value cannot be negative. + */ +__STATIC_INLINE void NVIC_ClearPendingIRQ(IRQn_Type IRQn) +{ + NVIC->ICPR[((uint32_t)(IRQn) >> 5)] = (1 << ((uint32_t)(IRQn) & 0x1F)); /* Clear pending interrupt */ +} + + +/** \brief Get Active Interrupt + + The function reads the active register in NVIC and returns the active bit. + + \param [in] IRQn Interrupt number. + + \return 0 Interrupt status is not active. + \return 1 Interrupt status is active. + */ +__STATIC_INLINE uint32_t NVIC_GetActive(IRQn_Type IRQn) +{ + return((uint32_t)((NVIC->IABR[(uint32_t)(IRQn) >> 5] & (1 << ((uint32_t)(IRQn) & 0x1F)))?1:0)); /* Return 1 if active else 0 */ +} + + +/** \brief Set Interrupt Priority + + The function sets the priority of an interrupt. + + \note The priority cannot be set for every core interrupt. + + \param [in] IRQn Interrupt number. + \param [in] priority Priority to set. + */ +__STATIC_INLINE void NVIC_SetPriority(IRQn_Type IRQn, uint32_t priority) +{ + if(IRQn < 0) { + SCB->SHP[((uint32_t)(IRQn) & 0xF)-4] = ((priority << (8 - __NVIC_PRIO_BITS)) & 0xff); } /* set Priority for Cortex-M System Interrupts */ + else { + NVIC->IP[(uint32_t)(IRQn)] = ((priority << (8 - __NVIC_PRIO_BITS)) & 0xff); } /* set Priority for device specific Interrupts */ +} + + +/** \brief Get Interrupt Priority + + The function reads the priority of an interrupt. The interrupt + number can be positive to specify an external (device specific) + interrupt, or negative to specify an internal (core) interrupt. + + + \param [in] IRQn Interrupt number. + \return Interrupt Priority. Value is aligned automatically to the implemented + priority bits of the microcontroller. + */ +__STATIC_INLINE uint32_t NVIC_GetPriority(IRQn_Type IRQn) +{ + + if(IRQn < 0) { + return((uint32_t)(SCB->SHP[((uint32_t)(IRQn) & 0xF)-4] >> (8 - __NVIC_PRIO_BITS))); } /* get priority for Cortex-M system interrupts */ + else { + return((uint32_t)(NVIC->IP[(uint32_t)(IRQn)] >> (8 - __NVIC_PRIO_BITS))); } /* get priority for device specific interrupts */ +} + + +/** \brief Encode Priority + + The function encodes the priority for an interrupt with the given priority group, + preemptive priority value, and subpriority value. + In case of a conflict between priority grouping and available + priority bits (__NVIC_PRIO_BITS), the samllest possible priority group is set. + + \param [in] PriorityGroup Used priority group. + \param [in] PreemptPriority Preemptive priority value (starting from 0). + \param [in] SubPriority Subpriority value (starting from 0). + \return Encoded priority. Value can be used in the function \ref NVIC_SetPriority(). + */ +__STATIC_INLINE uint32_t NVIC_EncodePriority (uint32_t PriorityGroup, uint32_t PreemptPriority, uint32_t SubPriority) +{ + uint32_t PriorityGroupTmp = (PriorityGroup & 0x07); /* only values 0..7 are used */ + uint32_t PreemptPriorityBits; + uint32_t SubPriorityBits; + + PreemptPriorityBits = ((7 - PriorityGroupTmp) > __NVIC_PRIO_BITS) ? __NVIC_PRIO_BITS : 7 - PriorityGroupTmp; + SubPriorityBits = ((PriorityGroupTmp + __NVIC_PRIO_BITS) < 7) ? 0 : PriorityGroupTmp - 7 + __NVIC_PRIO_BITS; + + return ( + ((PreemptPriority & ((1 << (PreemptPriorityBits)) - 1)) << SubPriorityBits) | + ((SubPriority & ((1 << (SubPriorityBits )) - 1))) + ); +} + + +/** \brief Decode Priority + + The function decodes an interrupt priority value with a given priority group to + preemptive priority value and subpriority value. + In case of a conflict between priority grouping and available + priority bits (__NVIC_PRIO_BITS) the samllest possible priority group is set. + + \param [in] Priority Priority value, which can be retrieved with the function \ref NVIC_GetPriority(). + \param [in] PriorityGroup Used priority group. + \param [out] pPreemptPriority Preemptive priority value (starting from 0). + \param [out] pSubPriority Subpriority value (starting from 0). + */ +__STATIC_INLINE void NVIC_DecodePriority (uint32_t Priority, uint32_t PriorityGroup, uint32_t* pPreemptPriority, uint32_t* pSubPriority) +{ + uint32_t PriorityGroupTmp = (PriorityGroup & 0x07); /* only values 0..7 are used */ + uint32_t PreemptPriorityBits; + uint32_t SubPriorityBits; + + PreemptPriorityBits = ((7 - PriorityGroupTmp) > __NVIC_PRIO_BITS) ? __NVIC_PRIO_BITS : 7 - PriorityGroupTmp; + SubPriorityBits = ((PriorityGroupTmp + __NVIC_PRIO_BITS) < 7) ? 0 : PriorityGroupTmp - 7 + __NVIC_PRIO_BITS; + + *pPreemptPriority = (Priority >> SubPriorityBits) & ((1 << (PreemptPriorityBits)) - 1); + *pSubPriority = (Priority ) & ((1 << (SubPriorityBits )) - 1); +} + + +/** \brief System Reset + + The function initiates a system reset request to reset the MCU. + */ +__STATIC_INLINE void NVIC_SystemReset(void) +{ + __DSB(); /* Ensure all outstanding memory accesses included + buffered write are completed before reset */ + SCB->AIRCR = ((0x5FA << SCB_AIRCR_VECTKEY_Pos) | + (SCB->AIRCR & SCB_AIRCR_PRIGROUP_Msk) | + SCB_AIRCR_SYSRESETREQ_Msk); /* Keep priority group unchanged */ + __DSB(); /* Ensure completion of memory access */ + while(1); /* wait until reset */ +} + +/*@} end of CMSIS_Core_NVICFunctions */ + + + +/* ################################## SysTick function ############################################ */ +/** \ingroup CMSIS_Core_FunctionInterface + \defgroup CMSIS_Core_SysTickFunctions SysTick Functions + \brief Functions that configure the System. + @{ + */ + +#if (__Vendor_SysTickConfig == 0) + +/** \brief System Tick Configuration + + The function initializes the System Timer and its interrupt, and starts the System Tick Timer. + Counter is in free running mode to generate periodic interrupts. + + \param [in] ticks Number of ticks between two interrupts. + + \return 0 Function succeeded. + \return 1 Function failed. + + \note When the variable __Vendor_SysTickConfig is set to 1, then the + function SysTick_Config is not included. In this case, the file device.h + must contain a vendor-specific implementation of this function. + + */ +__STATIC_INLINE uint32_t SysTick_Config(uint32_t ticks) +{ + if (ticks > SysTick_LOAD_RELOAD_Msk) return (1); /* Reload value impossible */ + + SysTick->LOAD = (ticks & SysTick_LOAD_RELOAD_Msk) - 1; /* set reload register */ + NVIC_SetPriority (SysTick_IRQn, (1<<__NVIC_PRIO_BITS) - 1); /* set Priority for Systick Interrupt */ + SysTick->VAL = 0; /* Load the SysTick Counter Value */ + SysTick->CTRL = SysTick_CTRL_CLKSOURCE_Msk | + SysTick_CTRL_TICKINT_Msk | + SysTick_CTRL_ENABLE_Msk; /* Enable SysTick IRQ and SysTick Timer */ + return (0); /* Function successful */ +} + +#endif + +/*@} end of CMSIS_Core_SysTickFunctions */ + + + +/* ##################################### Debug In/Output function ########################################### */ +/** \ingroup CMSIS_Core_FunctionInterface + \defgroup CMSIS_core_DebugFunctions ITM Functions + \brief Functions that access the ITM debug interface. + @{ + */ + +extern volatile int32_t ITM_RxBuffer; /*!< External variable to receive characters. */ +#define ITM_RXBUFFER_EMPTY 0x5AA55AA5 /*!< Value identifying \ref ITM_RxBuffer is ready for next character. */ + + +/** \brief ITM Send Character + + The function transmits a character via the ITM channel 0, and + \li Just returns when no debugger is connected that has booked the output. + \li Is blocking when a debugger is connected, but the previous character sent has not been transmitted. + + \param [in] ch Character to transmit. + + \returns Character to transmit. + */ +__STATIC_INLINE uint32_t ITM_SendChar (uint32_t ch) +{ + if ((ITM->TCR & ITM_TCR_ITMENA_Msk) && /* ITM enabled */ + (ITM->TER & (1UL << 0) ) ) /* ITM Port #0 enabled */ + { + while (ITM->PORT[0].u32 == 0); + ITM->PORT[0].u8 = (uint8_t) ch; + } + return (ch); +} + + +/** \brief ITM Receive Character + + The function inputs a character via the external variable \ref ITM_RxBuffer. + + \return Received character. + \return -1 No character pending. + */ +__STATIC_INLINE int32_t ITM_ReceiveChar (void) { + int32_t ch = -1; /* no character available */ + + if (ITM_RxBuffer != ITM_RXBUFFER_EMPTY) { + ch = ITM_RxBuffer; + ITM_RxBuffer = ITM_RXBUFFER_EMPTY; /* ready for next character */ + } + + return (ch); +} + + +/** \brief ITM Check Character + + The function checks whether a character is pending for reading in the variable \ref ITM_RxBuffer. + + \return 0 No character available. + \return 1 Character available. + */ +__STATIC_INLINE int32_t ITM_CheckChar (void) { + + if (ITM_RxBuffer == ITM_RXBUFFER_EMPTY) { + return (0); /* no character available */ + } else { + return (1); /* character available */ + } +} + +/*@} end of CMSIS_core_DebugFunctions */ + +#endif /* __CORE_SC300_H_DEPENDANT */ + +#endif /* __CMSIS_GENERIC */ + +#ifdef __cplusplus +} +#endif diff --git a/Libraries/CMSIS/README.txt b/Libraries/CMSIS/README.txt new file mode 100644 index 0000000..9b92ccc --- /dev/null +++ b/Libraries/CMSIS/README.txt @@ -0,0 +1,37 @@ +* ------------------------------------------------------------------- +* Copyright (C) 2011-2012 ARM Limited. All rights reserved. +* +* Date: 07 March 2012 +* Revision: V3.01 +* +* Project: Cortex Microcontroller Software Interface Standard (CMSIS) +* Title: Release Note for CMSIS +* +* ------------------------------------------------------------------- + + +NOTE - Open the index.html file to access CMSIS documentation + + +The Cortex Microcontroller Software Interface Standard (CMSIS) provides a single standard across all +Cortex-Mx processor series vendors. It enables code re-use and code sharing across software projects +and reduces time-to-market for new embedded applications. + +CMSIS is released under the terms of the end user license agreement ("CMSIS END USER LICENCE AGREEMENT.pdf"). +Any user of the software package is bound to the terms and conditions of the end user license agreement. + + +You will find the following sub-directories: + +Documentation - Contains CMSIS documentation. + +DSP_Lib - MDK project files, Examples and source files etc.. to build the + CMSIS DSP Software Library for Cortex-M0, Cortex-M3, Cortex-M4 processors. + +Include - CMSIS Core Support and CMSIS DSP Include Files. + +Lib - CMSIS DSP Libraries. + +RTOS - CMSIS RTOS API template header file. + +SVD - CMSIS SVD Schema files and Conversion Utility. diff --git a/Libraries/CMSIS/RTOS/cmsis_os.h b/Libraries/CMSIS/RTOS/cmsis_os.h new file mode 100644 index 0000000..2ccfd17 --- /dev/null +++ b/Libraries/CMSIS/RTOS/cmsis_os.h @@ -0,0 +1,717 @@ +/* ---------------------------------------------------------------------- + * Copyright (C) 2012 ARM Limited. All rights reserved. + * + * $Date: 5. March 2012 + * $Revision: V0.03 + * + * Project: CMSIS-RTOS API + * Title: cmsis_os.h template header file + * + * Version 0.02 + * Initial Proposal Phase + * Version 0.03 + * osKernelStart added, optional feature: main started as thread + * osSemaphores have standard behaviour + * osTimerCreate does not start the timer, added osTimerStart + * osThreadPass is renamed to osThreadYield + * -------------------------------------------------------------------- */ + +/** +\page cmsis_os_h Header File Template: cmsis_os.h + +The file \b cmsis_os.h is a template header file for a CMSIS-RTOS compliant Real-Time Operating System (RTOS). +Each RTOS that is compliant with CMSIS-RTOS shall provide a specific \b cmsis_os.h header file that represents +its implementation. + +The file cmsis_os.h contains: + - CMSIS-RTOS API function definitions + - struct definitions for parameters and return types + - status and priority values used by CMSIS-RTOS API functions + - macros for defining threads and other kernel objects + + +Name conventions and header file modifications + +All definitions are prefixed with \b os to give an unique name space for CMSIS-RTOS functions. +Definitions that are prefixed \b os_ are not used in the application code but local to this header file. +All definitions and functions that belong to a module are grouped and have a common prefix, i.e. \b osThread. + +Definitions that are marked with CAN BE CHANGED can be adapted towards the needs of the actual CMSIS-RTOS implementation. +These definitions can be specific to the underlying RTOS kernel. + +Definitions that are marked with MUST REMAIN UNCHANGED cannot be altered. Otherwise the CMSIS-RTOS implementation is no longer +compliant to the standard. Note that some functions are optional and need not to be provided by every CMSIS-RTOS implementation. + + +Function calls from interrupt service routines + +The following CMSIS-RTOS functions can be called from threads and interrupt service routines (ISR): + - \ref osSignalSet + - \ref osSemaphoreRelease + - \ref osPoolAlloc, \ref osPoolCAlloc, \ref osPoolFree + - \ref osMessagePut, \ref osMessageGet + - \ref osMailAlloc, \ref osMailCAlloc, \ref osMailGet, \ref osMailPut, \ref osMailFree + +Functions that cannot be called from an ISR are verifying the interrupt status and return in case that they are called +from an ISR context the status code \b osErrorISR. In some implementations this condition might be caught using the HARD FAULT vector. + +Some CMSIS-RTOS implementations support CMSIS-RTOS function calls from multiple ISR at the same time. +If this is impossible, the CMSIS-RTOS rejects calls by nested ISR functions with the status code \b osErrorISRRecursive. + + +Define and reference object definitions + +With \#define osObjectsExternal objects are defined as external symbols. This allows to create a consistent header file +that is used troughtout a project as shown below: + +Header File +\code +#include // CMSIS RTOS header file + +// Thread definition +extern void thread_sample (void const *argument); // function prototype +osThreadDef (thread_sample, osPriorityBelowNormal, 1, 100); + +// Pool definition +osPoolDef(MyPool, 10, long); +\endcode + + +This header file defines all objects when included in a C/C++ source file. When \#define osObjectsExternal is +present before the header file, the objects are defined as external symbols. A single consistent header file can therefore be +used throughout the whole project. + +Example +\code +#include "osObjects.h" // Definition of the CMSIS-RTOS objects +\endcode + +\code +#define osObjectExternal // Objects will be defined as external symbols +#include "osObjects.h" // Reference to the CMSIS-RTOS objects +\endcode + +*/ + +#ifndef _CMSIS_OS_H +#define _CMSIS_OS_H + +/// \note MUST REMAIN UNCHANGED: \b osCMSIS identifies the CMSIS-RTOS API version +#define osCMSIS 0x00003 ///< API version (main [31:16] .sub [15:0]) + +/// \note CAN BE CHANGED: \b osCMSIS_KERNEL identifies the underlaying RTOS kernel and version number. +#define osCMSIS_KERNEL 0x10000 ///< RTOS identification and version (main [31:16] .sub [15:0]) + +/// \note MUST REMAIN UNCHANGED: \b osKernelSystemId shall be consistent in every CMSIS-RTOS. +#define osKernelSystemId "KERNEL V1.00" ///< RTOS identification string + +/// \note MUST REMAIN UNCHANGED: \b osFeature_xxx shall be consistent in every CMSIS-RTOS. +#define osFeature_MainThread 1 ///< main thread 1=main can be thread, 0=not available +#define osFeature_Pool 1 ///< Memory Pools: 1=available, 0=not available +#define osFeature_MailQ 1 ///< Mail Queues: 1=available, 0=not available +#define osFeature_MessageQ 1 ///< Message Queues: 1=available, 0=not available +#define osFeature_Signals 8 ///< maximum number of Signal Flags available per thread +#define osFeature_Semaphore 30 ///< maximum count for SemaphoreInit function +#define osFeature_Wait 1 ///< osWait function: 1=available, 0=not available + +#include +#include + +#ifdef __cplusplus +extern "C" +{ +#endif + + +// ==== Enumeration, structures, defines ==== + +/// Priority used for thread control. +/// \note MUST REMAIN UNCHANGED: \b osPriority shall be consistent in every CMSIS-RTOS. +typedef enum { + osPriorityIdle = -3, ///< priority: idle (lowest) + osPriorityLow = -2, ///< priority: low + osPriorityBelowNormal = -1, ///< priority: below normal + osPriorityNormal = 0, ///< priority: normal (default) + osPriorityAboveNormal = +1, ///< priority: above normal + osPriorityHigh = +2, ///< priority: high + osPriorityRealtime = +3, ///< priority: realtime (highest) + osPriorityError = 0x84 ///< system cannot determine priority or thread has illegal priority +} osPriority; + +/// Timeout value +/// \note MUST REMAIN UNCHANGED: \b osWaitForever shall be consistent in every CMSIS-RTOS. +#define osWaitForever 0xFFFFFFFF ///< wait forever timeout value + +/// Status code values returned by CMSIS-RTOS functions +/// \note MUST REMAIN UNCHANGED: \b osStatus shall be consistent in every CMSIS-RTOS. +typedef enum { + osOK = 0, ///< function completed; no event occurred. + osEventSignal = 0x08, ///< function completed; signal event occurred. + osEventMessage = 0x10, ///< function completed; message event occurred. + osEventMail = 0x20, ///< function completed; mail event occurred. + osEventTimeout = 0x40, ///< function completed; timeout occurred. + osErrorParameter = 0x80, ///< parameter error: a mandatory parameter was missing or specified an incorrect object. + osErrorResource = 0x81, ///< resource not available: a specified resource was not available. + osErrorTimeoutResource = 0xC1, ///< resource not available within given time: a specified resource was not available within the timeout period. + osErrorISR = 0x82, ///< not allowed in ISR context: the function cannot be called from interrupt service routines. + osErrorISRRecursive = 0x83, ///< function called multiple times from ISR with same object. + osErrorPriority = 0x84, ///< system cannot determine priority or thread has illegal priority. + osErrorNoMemory = 0x85, ///< system is out of memory: it was impossible to allocate or reserve memory for the operation. + osErrorValue = 0x86, ///< value of a parameter is out of range. + osErrorOS = 0xFF, ///< unspecified RTOS error: run-time error but no other error message fits. + os_status_reserved = 0x7FFFFFFF ///< prevent from enum down-size compiler optimization. +} osStatus; + + +/// Timer type value for the timer definition +/// \note MUST REMAIN UNCHANGED: \b os_timer_type shall be consistent in every CMSIS-RTOS. +typedef enum { + osTimerOnce = 0, ///< one-shot timer + osTimerPeriodic = 1 ///< repeating timer +} os_timer_type; + +/// Entry point of a thread. +/// \note MUST REMAIN UNCHANGED: \b os_pthread shall be consistent in every CMSIS-RTOS. +typedef void (*os_pthread) (void const *argument); + +/// Entry point of a timer call back function. +/// \note MUST REMAIN UNCHANGED: \b os_ptimer shall be consistent in every CMSIS-RTOS. +typedef void (*os_ptimer) (void const *argument); + +// >>> the following data type definitions may shall adapted towards a specific RTOS + +/// Thread ID identifies the thread (pointer to a thread control block). +/// \note CAN BE CHANGED: \b os_thread_cb is implementation specific in every CMSIS-RTOS. +typedef struct os_thread_cb *osThreadId; + +/// Timer ID identifies the timer (pointer to a timer control block). +/// \note CAN BE CHANGED: \b os_timer_cb is implementation specific in every CMSIS-RTOS. +typedef struct os_timer_cb *osTimerId; + +/// Mutex ID identifies the mutex (pointer to a mutex control block). +/// \note CAN BE CHANGED: \b os_mutex_cb is implementation specific in every CMSIS-RTOS. +typedef struct os_mutex_cb *osMutexId; + +/// Semaphore ID identifies the semaphore (pointer to a semaphore control block). +/// \note CAN BE CHANGED: \b os_semaphore_cb is implementation specific in every CMSIS-RTOS. +typedef struct os_semaphore_cb *osSemaphoreId; + +/// Pool ID identifies the memory pool (pointer to a memory pool control block). +/// \note CAN BE CHANGED: \b os_pool_cb is implementation specific in every CMSIS-RTOS. +typedef struct os_pool_cb *osPoolId; + +/// Message ID identifies the message queue (pointer to a message queue control block). +/// \note CAN BE CHANGED: \b os_messageQ_cb is implementation specific in every CMSIS-RTOS. +typedef struct os_messageQ_cb *osMessageQId; + +/// Mail ID identifies the mail queue (pointer to a mail queue control block). +/// \note CAN BE CHANGED: \b os_mailQ_cb is implementation specific in every CMSIS-RTOS. +typedef struct os_mailQ_cb *osMailQId; + + +/// Thread Definition structure contains startup information of a thread. +/// \note CAN BE CHANGED: \b os_thread_def is implementation specific in every CMSIS-RTOS. +typedef const struct os_thread_def { + os_pthread pthread; ///< start address of thread function + osPriority tpriority; ///< initial thread priority + uint32_t instances; ///< maximum number of instances of that thread function + uint32_t stacksize; ///< stack size requirements in bytes; 0 is default stack size +} osThreadDef_t; + +/// Timer Definition structure contains timer parameters. +/// \note CAN BE CHANGED: \b os_timer_def is implementation specific in every CMSIS-RTOS. +typedef const struct os_timer_def { + os_ptimer ptimer; ///< start address of a timer function +} osTimerDef_t; + +/// Mutex Definition structure contains setup information for a mutex. +/// \note CAN BE CHANGED: \b os_mutex_def is implementation specific in every CMSIS-RTOS. +typedef const struct os_mutex_def { + uint32_t dummy; ///< dummy value. +} osMutexDef_t; + +/// Semaphore Definition structure contains setup information for a semaphore. +/// \note CAN BE CHANGED: \b os_semaphore_def is implementation specific in every CMSIS-RTOS. +typedef const struct os_semaphore_def { + uint32_t dummy; ///< dummy value. +} osSemaphoreDef_t; + +/// Definition structure for memory block allocation +/// \note CAN BE CHANGED: \b os_pool_def is implementation specific in every CMSIS-RTOS. +typedef const struct os_pool_def { + uint32_t pool_sz; ///< number of items (elements) in the pool + uint32_t item_sz; ///< size of an item + void *pool; ///< pointer to memory for pool +} osPoolDef_t; + +/// Definition structure for message queue +/// \note CAN BE CHANGED: \b os_messageQ_def is implementation specific in every CMSIS-RTOS. +typedef const struct os_messageQ_def { + uint32_t queue_sz; ///< number of elements in the queue + uint32_t item_sz; ///< size of an item + void *pool; ///< memory array for messages +} osMessageQDef_t; + +/// Definition structure for mail queue +/// \note CAN BE CHANGED: \b os_mailQ_def is implementation specific in every CMSIS-RTOS. +typedef const struct os_mailQ_def { + uint32_t queue_sz; ///< number of elements in the queue + uint32_t item_sz; ///< size of an item + void *pool; ///< memory array for mail +} osMailQDef_t; + +/// Event structure contains detailed information about an event. +/// \note MUST REMAIN UNCHANGED: \b os_event shall be consistent in every CMSIS-RTOS. +/// However the struct may be extended at the end. +typedef struct { + osStatus status; ///< status code: event or error information + union { + uint32_t v; ///< message as 32-bit value + void *p; ///< message or mail as void pointer + int32_t signals; ///< signal flags + } value; ///< event value + union { + osMailQId mail_id; ///< mail id obtained by \ref osMailCreate + osMessageQId message_id; ///< message id obtained by \ref osMessageCreate + } def; ///< event definition +} osEvent; + + +// ==== Kernel Control Functions ==== + +/// Start the RTOS Kernel with executing the specified thread. +/// \param[in] thread_def thread definition referenced with \ref osThread. +/// \param[in] argument pointer that is passed to the thread function as start argument. +/// \return status code that indicates the execution status of the function. +/// \note MUST REMAIN UNCHANGED: \b osKernelStart shall be consistent in every CMSIS-RTOS. +osStatus osKernelStart (osThreadDef_t *thread_def, void *argument); + +/// Check if the RTOS kernel is already started. +/// \note MUST REMAIN UNCHANGED: \b osKernelRunning shall be consistent in every CMSIS-RTOS. +/// \return 0 RTOS is not started, 1 RTOS is started. +int32_t osKernelRunning(void); + + +// ==== Thread Management ==== + +/// Create a Thread Definition with function, priority, and stack requirements. +/// \param name name of the thread function. +/// \param priority initial priority of the thread function. +/// \param instances number of possible thread instances. +/// \param stacksz stack size (in bytes) requirements for the thread function. +/// \note CAN BE CHANGED: The parameters to \b osThreadDef shall be consistent but the +/// macro body is implementation specific in every CMSIS-RTOS. +#if defined (osObjectsExternal) // object is external +#define osThreadDef(name, priority, instances, stacksz) \ +extern osThreadDef_t os_thread_def_##name +#else // define the object +#define osThreadDef(name, priority, instances, stacksz) \ +osThreadDef_t os_thread_def_##name = \ +{ (name), (priority), (instances), (stacksz) } +#endif + +/// Access a Thread defintion. +/// \param name name of the thread definition object. +/// \note CAN BE CHANGED: The parameter to \b osThread shall be consistent but the +/// macro body is implementation specific in every CMSIS-RTOS. +#define osThread(name) \ +&os_thread_def_##name + + +/// Create a thread and add it to Active Threads and set it to state READY. +/// \param[in] thread_def thread definition referenced with \ref osThread. +/// \param[in] argument pointer that is passed to the thread function as start argument. +/// \return thread ID for reference by other functions or NULL in case of error. +/// \note MUST REMAIN UNCHANGED: \b osThreadCreate shall be consistent in every CMSIS-RTOS. +osThreadId osThreadCreate (osThreadDef_t *thread_def, void *argument); + +/// Return the thread ID of the current running thread. +/// \return thread ID for reference by other functions or NULL in case of error. +/// \note MUST REMAIN UNCHANGED: \b osThreadGetId shall be consistent in every CMSIS-RTOS. +osThreadId osThreadGetId (void); + +/// Terminate execution of a thread and remove it from Active Threads. +/// \param[in] thread_id thread ID obtained by \ref osThreadCreate or \ref osThreadGetId. +/// \return status code that indicates the execution status of the function. +/// \note MUST REMAIN UNCHANGED: \b osThreadTerminate shall be consistent in every CMSIS-RTOS. +osStatus osThreadTerminate (osThreadId thread_id); + +/// Pass control to next thread that is in state \b READY. +/// \return status code that indicates the execution status of the function. +/// \note MUST REMAIN UNCHANGED: \b osThreadYield shall be consistent in every CMSIS-RTOS. +osStatus osThreadYield (void); + +/// Change priority of an active thread. +/// \param[in] thread_id thread ID obtained by \ref osThreadCreate or \ref osThreadGetId. +/// \param[in] priority new priority value for the thread function. +/// \return status code that indicates the execution status of the function. +/// \note MUST REMAIN UNCHANGED: \b osThreadSetPriority shall be consistent in every CMSIS-RTOS. +osStatus osThreadSetPriority (osThreadId thread_id, osPriority priority); + +/// Get current priority of an active thread. +/// \param[in] thread_id thread ID obtained by \ref osThreadCreate or \ref osThreadGetId. +/// \return current priority value of the thread function. +/// \note MUST REMAIN UNCHANGED: \b osThreadGetPriority shall be consistent in every CMSIS-RTOS. +osPriority osThreadGetPriority (osThreadId thread_id); + + + +// ==== Generic Wait Functions ==== + +/// Wait for Timeout (Time Delay) +/// \param[in] millisec time delay value +/// \return status code that indicates the execution status of the function. +osStatus osDelay (uint32_t millisec); + +#if (defined (osFeature_Wait) && (osFeature_Wait != 0)) // Generic Wait available + +/// Wait for Signal, Message, Mail, or Timeout +/// \param[in] millisec timeout value or 0 in case of no time-out +/// \return event that contains signal, message, or mail information or error code. +/// \note MUST REMAIN UNCHANGED: \b osWait shall be consistent in every CMSIS-RTOS. +osEvent osWait (uint32_t millisec); + +#endif // Generic Wait available + + +// ==== Timer Management Functions ==== +/// Define a Timer object. +/// \param name name of the timer object. +/// \param function name of the timer call back function. +/// \note CAN BE CHANGED: The parameter to \b osTimerDef shall be consistent but the +/// macro body is implementation specific in every CMSIS-RTOS. +#if defined (osObjectsExternal) // object is external +#define osTimerDef(name, function) \ +extern osTimerDef_t os_timer_def_##name +#else // define the object +#define osTimerDef(name, function) \ +osTimerDef_t os_timer_def_##name = \ +{ (function) } +#endif + +/// Access a Timer definition. +/// \param name name of the timer object. +/// \note CAN BE CHANGED: The parameter to \b osTimer shall be consistent but the +/// macro body is implementation specific in every CMSIS-RTOS. +#define osTimer(name) \ +&os_timer_def_##name + +/// Create a timer. +/// \param[in] timer_def timer object referenced with \ref osTimer. +/// \param[in] type osTimerOnce for one-shot or osTimerPeriodic for periodic behavior. +/// \param[in] argument argument to the timer call back function. +/// \return timer ID for reference by other functions or NULL in case of error. +/// \note MUST REMAIN UNCHANGED: \b osTimerCreate shall be consistent in every CMSIS-RTOS. +osTimerId osTimerCreate (osTimerDef_t *timer_def, os_timer_type type, void *argument); + +/// Start or restart a timer. +/// \param[in] timer_id timer ID obtained by \ref osTimerCreate. +/// \param[in] millisec time delay value of the timer. +/// \return status code that indicates the execution status of the function. +/// \note MUST REMAIN UNCHANGED: \b osTimerStart shall be consistent in every CMSIS-RTOS. +osStatus osTimerStart (osTimerId timer_id, uint32_t millisec); + +/// Stop the timer. +/// \param[in] timer_id timer ID obtained by \ref osTimerCreate. +/// \return status code that indicates the execution status of the function. +/// \note MUST REMAIN UNCHANGED: \b osTimerStop shall be consistent in every CMSIS-RTOS. +osStatus osTimerStop (osTimerId timer_id); + + +// ==== Signal Management ==== + +/// Set the specified Signal Flags of an active thread. +/// \param[in] thread_id thread ID obtained by \ref osThreadCreate or \ref osThreadGetId. +/// \param[in] signals specifies the signal flags of the thread that should be set. +/// \return previous signal flags of the specified thread or 0x80000000 in case of incorrect parameters. +/// \note MUST REMAIN UNCHANGED: \b osSignalSet shall be consistent in every CMSIS-RTOS. +int32_t osSignalSet (osThreadId thread_id, int32_t signal); + +/// Clear the specified Signal Flags of an active thread. +/// \param[in] thread_id thread ID obtained by \ref osThreadCreate or \ref osThreadGetId. +/// \param[in] signals specifies the signal flags of the thread that shall be cleared. +/// \return previous signal flags of the specified thread or 0x80000000 in case of incorrect parameters. +/// \note MUST REMAIN UNCHANGED: \b osSignalClear shall be consistent in every CMSIS-RTOS. +int32_t osSignalClear (osThreadId thread_id, int32_t signal); + +/// Get Signal Flags status of an active thread. +/// \param[in] thread_id thread ID obtained by \ref osThreadCreate or \ref osThreadGetId. +/// \return previous signal flags of the specified thread or 0x80000000 in case of incorrect parameters. +/// \note MUST REMAIN UNCHANGED: \b osSignalGet shall be consistent in every CMSIS-RTOS. +int32_t osSignalGet (osThreadId thread_id); + +/// Wait for one or more Signal Flags to become signaled for the current \b RUNNING thread. +/// \param[in] signals wait until all specified signal flags set or 0 for any single signal flag. +/// \param[in] millisec timeout value or 0 in case of no time-out. +/// \return event flag information or error code. +/// \note MUST REMAIN UNCHANGED: \b osSignalWait shall be consistent in every CMSIS-RTOS. +osEvent osSignalWait (int32_t signals, uint32_t millisec); + + +// ==== Mutex Management ==== + +/// Define a Mutex. +/// \param name name of the mutex object. +/// \note CAN BE CHANGED: The parameter to \b osMutexDef shall be consistent but the +/// macro body is implementation specific in every CMSIS-RTOS. +#if defined (osObjectsExternal) // object is external +#define osMutexDef(name) \ +extern osMutexDef_t os_mutex_def_##name +#else // define the object +#define osMutexDef(name) \ +osMutexDef_t os_mutex_def_##name = { 0 } +#endif + +/// Access a Mutex defintion. +/// \param name name of the mutex object. +/// \note CAN BE CHANGED: The parameter to \b osMutex shall be consistent but the +/// macro body is implementation specific in every CMSIS-RTOS. +#define osMutex(name) \ +&os_mutex_def_##name + +/// Create and Initialize a Mutex object +/// \param[in] mutex_def mutex definition referenced with \ref osMutex. +/// \return mutex ID for reference by other functions or NULL in case of error. +/// \note MUST REMAIN UNCHANGED: \b osMutexCreate shall be consistent in every CMSIS-RTOS. +osMutexId osMutexCreate (osMutexDef_t *mutex_def); + +/// Wait until a Mutex becomes available +/// \param[in] mutex_id mutex ID obtained by \ref osMutexCreate. +/// \param[in] millisec timeout value or 0 in case of no time-out. +/// \return status code that indicates the execution status of the function. +/// \note MUST REMAIN UNCHANGED: \b osMutexWait shall be consistent in every CMSIS-RTOS. +osStatus osMutexWait (osMutexId mutex_id, uint32_t millisec); + +/// Release a Mutex that was obtained by \ref osMutexWait +/// \param[in] mutex_id mutex ID obtained by \ref osMutexCreate. +/// \return status code that indicates the execution status of the function. +/// \note MUST REMAIN UNCHANGED: \b osMutexRelease shall be consistent in every CMSIS-RTOS. +osStatus osMutexRelease (osMutexId mutex_id); + + +// ==== Semaphore Management Functions ==== + +#if (defined (osFeature_Semaphore) && (osFeature_Semaphore != 0)) // Semaphore available + +/// Define a Semaphore object. +/// \param name name of the semaphore object. +/// \note CAN BE CHANGED: The parameter to \b osSemaphoreDef shall be consistent but the +/// macro body is implementation specific in every CMSIS-RTOS. +#if defined (osObjectsExternal) // object is external +#define osSemaphoreDef(name) \ +extern osSemaphoreDef_t os_semaphore_def_##name +#else // define the object +#define osSemaphoreDef(name) \ +osSemaphoreDef_t os_semaphore_def_##name = { 0 } +#endif + +/// Access a Semaphore definition. +/// \param name name of the semaphore object. +/// \note CAN BE CHANGED: The parameter to \b osSemaphore shall be consistent but the +/// macro body is implementation specific in every CMSIS-RTOS. +#define osSemaphore(name) \ +&os_semaphore_def_##name + +/// Create and Initialize a Semaphore object used for managing resources +/// \param[in] semaphore_def semaphore definition referenced with \ref osSemaphore. +/// \param[in] count number of available resources. +/// \return semaphore ID for reference by other functions or NULL in case of error. +/// \note MUST REMAIN UNCHANGED: \b osSemaphoreCreate shall be consistent in every CMSIS-RTOS. +osSemaphoreId osSemaphoreCreate (osSemaphoreDef_t *semaphore_def, int32_t count); + +/// Wait until a Semaphore token becomes available +/// \param[in] semaphore_id semaphore object referenced with \ref osSemaphore. +/// \param[in] millisec timeout value or 0 in case of no time-out. +/// \return number of available tokens, or -1 in case of incorrect parameters. +/// \note MUST REMAIN UNCHANGED: \b osSemaphoreWait shall be consistent in every CMSIS-RTOS. +int32_t osSemaphoreWait (osSemaphoreId semaphore_id, uint32_t millisec); + +/// Release a Semaphore token +/// \param[in] semaphore_id semaphore object referenced with \ref osSemaphore. +/// \return status code that indicates the execution status of the function. +/// \note MUST REMAIN UNCHANGED: \b osSemaphoreRelease shall be consistent in every CMSIS-RTOS. +osStatus osSemaphoreRelease (osSemaphoreId semaphore_id); + +#endif // Semaphore available + +// ==== Memory Pool Management Functions ==== + +#if (defined (osFeature_Pool) && (osFeature_Pool != 0)) // Memory Pool Management available + +/// \brief Define a Memory Pool. +/// \param name name of the memory pool. +/// \param no maximum number of objects (elements) in the memory pool. +/// \param type data type of a single object (element). +/// \note CAN BE CHANGED: The parameter to \b osPoolDef shall be consistent but the +/// macro body is implementation specific in every CMSIS-RTOS. +#if defined (osObjectsExternal) // object is external +#define osPoolDef(name, no, type) \ +extern osPoolDef_t os_pool_def_##name +#else // define the object +#define osPoolDef(name, no, type) \ +osPoolDef_t os_pool_def_##name = \ +{ (no), sizeof(type), NULL } +#endif + +/// \brief Access a Memory Pool definition. +/// \param name name of the memory pool +/// \note CAN BE CHANGED: The parameter to \b osPool shall be consistent but the +/// macro body is implementation specific in every CMSIS-RTOS. +#define osPool(name) \ +&os_pool_def_##name + +/// Create and Initialize a memory pool +/// \param[in] pool_def memory pool definition referenced with \ref osPool. +/// \return memory pool ID for reference by other functions or NULL in case of error. +/// \note MUST REMAIN UNCHANGED: \b osPoolCreate shall be consistent in every CMSIS-RTOS. +osPoolId osPoolCreate (osPoolDef_t *pool_def); + +/// Allocate a memory block from a memory pool +/// \param[in] pool_id memory pool ID obtain referenced with \ref osPoolCreate. +/// \return address of the allocated memory block or NULL in case of no memory available. +/// \note MUST REMAIN UNCHANGED: \b osPoolAlloc shall be consistent in every CMSIS-RTOS. +void *osPoolAlloc (osPoolId pool_id); + +/// Allocate a memory block from a memory pool and set memory block to zero +/// \param[in] pool_id memory pool ID obtain referenced with \ref osPoolCreate. +/// \return address of the allocated memory block or NULL in case of no memory available. +/// \note MUST REMAIN UNCHANGED: \b osPoolCAlloc shall be consistent in every CMSIS-RTOS. +void *osPoolCAlloc (osPoolId pool_id); + +/// Return an allocated memory block back to a specific memory pool +/// \param[in] pool_id memory pool ID obtain referenced with \ref osPoolCreate. +/// \param[in] block address of the allocated memory block that is returned to the memory pool. +/// \return status code that indicates the execution status of the function. +/// \note MUST REMAIN UNCHANGED: \b osPoolFree shall be consistent in every CMSIS-RTOS. +osStatus osPoolFree (osPoolId pool_id, void *block); + +#endif // Memory Pool Management available + + +// ==== Message Queue Management Functions ==== + +#if (defined (osFeature_MessageQ) && (osFeature_MessageQ != 0)) // Message Queues available + +/// \brief Create a Message Queue Definition. +/// \param name name of the queue. +/// \param queue_sz maximum number of messages in the queue. +/// \param type data type of a single message element (for debugger). +/// \note CAN BE CHANGED: The parameter to \b osMessageQDef shall be consistent but the +/// macro body is implementation specific in every CMSIS-RTOS. +#if defined (osObjectsExternal) // object is external +#define osMessageQDef(name, queue_sz, type) \ +extern osMessageQDef_t os_messageQ_def_##name +#else // define the object +#define osMessageQDef(name, queue_sz, type) \ +osMessageQDef_t os_messageQ_def_##name = \ +{ (queue_sz), sizeof (type) } +#endif + +/// \brief Access a Message Queue Definition. +/// \param name name of the queue +/// \note CAN BE CHANGED: The parameter to \b osMessageQ shall be consistent but the +/// macro body is implementation specific in every CMSIS-RTOS. +#define osMessageQ(name) \ +&os_messageQ_def_##name + +/// Create and Initialize a Message Queue. +/// \param[in] queue_def queue definition referenced with \ref osMessageQ. +/// \param[in] thread_id thread ID (obtained by \ref osThreadCreate or \ref osThreadGetId) or NULL. +/// \return message queue ID for reference by other functions or NULL in case of error. +/// \note MUST REMAIN UNCHANGED: \b osMessageCreate shall be consistent in every CMSIS-RTOS. +osMessageQId osMessageCreate (osMessageQDef_t *queue_def, osThreadId thread_id); + +/// Put a Message to a Queue. +/// \param[in] queue_id message queue ID obtained with \ref osMessageCreate. +/// \param[in] info message information. +/// \param[in] millisec timeout value or 0 in case of no time-out. +/// \return status code that indicates the execution status of the function. +/// \note MUST REMAIN UNCHANGED: \b osMessagePut shall be consistent in every CMSIS-RTOS. +osStatus osMessagePut (osMessageQId queue_id, uint32_t info, uint32_t millisec); + +/// Get a Message or Wait for a Message from a Queue. +/// \param[in] queue_id message queue ID obtained with \ref osMessageCreate. +/// \param[in] millisec timeout value or 0 in case of no time-out. +/// \return event information that includes status code. +/// \note MUST REMAIN UNCHANGED: \b osMessageGet shall be consistent in every CMSIS-RTOS. +osEvent osMessageGet (osMessageQId queue_id, uint32_t millisec); + +#endif // Message Queues available + + +// ==== Mail Queue Management Functions ==== + +#if (defined (osFeature_MailQ) && (osFeature_MailQ != 0)) // Mail Queues available + +/// \brief Create a Mail Queue Definition +/// \param name name of the queue +/// \param queue_sz maximum number of messages in queue +/// \param type data type of a single message element +/// \note CAN BE CHANGED: The parameter to \b osMailQDef shall be consistent but the +/// macro body is implementation specific in every CMSIS-RTOS. +#if defined (osObjectsExternal) // object is external +#define osMailQDef(name, queue_sz, type) \ +extern osMailQDef_t os_mailQ_def_##name +#else // define the object +#define osMailQDef(name, queue_sz, type) \ +osMailQDef_t os_mailQ_def_##name = \ +{ (queue_sz), sizeof (type) } +#endif + +/// \brief Access a Mail Queue Definition +/// \param name name of the queue +/// \note CAN BE CHANGED: The parameter to \b osMailQ shall be consistent but the +/// macro body is implementation specific in every CMSIS-RTOS. +#define osMailQ(name) \ +&os_mailQ_def_##name + +/// Create and Initialize mail queue +/// \param[in] queue_def reference to the mail queue definition obtain with \ref osMailQ +/// \param[in] thread_id thread ID (obtained by \ref osThreadCreate or \ref osThreadGetId) or NULL. +/// \return mail queue ID for reference by other functions or NULL in case of error. +/// \note MUST REMAIN UNCHANGED: \b osMailCreate shall be consistent in every CMSIS-RTOS. +osMailQId osMailCreate (osMailQDef_t *queue_def, osThreadId thread_id); + +/// Allocate a memory block from a mail +/// \param[in] queue_id mail queue ID obtained with \ref osMailCreate. +/// \param[in] millisec timeout value or 0 in case of no time-out +/// \return pointer to memory block that can be filled with mail or NULL in case error. +/// \note MUST REMAIN UNCHANGED: \b osMailAlloc shall be consistent in every CMSIS-RTOS. +void *osMailAlloc (osMailQId queue_id, uint32_t millisec); + +/// Allocate a memory block from a mail and set memory block to zero +/// \param[in] queue_id mail queue ID obtained with \ref osMailCreate. +/// \param[in] millisec timeout value or 0 in case of no time-out +/// \return pointer to memory block that can shall filled with mail or NULL in case error. +/// \note MUST REMAIN UNCHANGED: \b osMailCAlloc shall be consistent in every CMSIS-RTOS. +void *osMailCAlloc (osMailQId queue_id, uint32_t millisec); + +/// Put a mail to a queue +/// \param[in] queue_id mail queue ID obtained with \ref osMailCreate. +/// \param[in] mail memory block previously allocated with \ref osMailAlloc or \ref osMailCAlloc. +/// \return status code that indicates the execution status of the function. +/// \note MUST REMAIN UNCHANGED: \b osMailPut shall be consistent in every CMSIS-RTOS. +osStatus osMailPut (osMailQId queue_id, void *mail); + +/// Get a mail from a queue +/// \param[in] queue_id mail queue ID obtained with \ref osMailCreate. +/// \param[in] millisec timeout value or 0 in case of no time-out +/// \return event that contains mail information or error code. +/// \note MUST REMAIN UNCHANGED: \b osMailGet shall be consistent in every CMSIS-RTOS. +osEvent osMailGet (osMailQId queue_id, uint32_t millisec); + +/// Free a memory block from a mail +/// \param[in] queue_id mail queue ID obtained with \ref osMailCreate. +/// \param[in] mail pointer to the memory block that was obtained with \ref osMailGet. +/// \return status code that indicates the execution status of the function. +/// \note MUST REMAIN UNCHANGED: \b osMailFree shall be consistent in every CMSIS-RTOS. +osStatus osMailFree (osMailQId queue_id, void *mail); + +#endif // Mail Queues available + + +#ifdef __cplusplus +} +#endif + +#endif // _CMSIS_OS_H diff --git a/Libraries/CMSIS/SVD/ARM_Sample.svd b/Libraries/CMSIS/SVD/ARM_Sample.svd new file mode 100644 index 0000000..03db1d4 --- /dev/null +++ b/Libraries/CMSIS/SVD/ARM_Sample.svd @@ -0,0 +1,739 @@ + + + + + + + + ARMCM3xxx + 1.0 + ARM 32-bit Cortex-M3 Microcontroller based device, CPU clock up to 80MHz, etc. + 8 + 32 + + 32 + read-write + 0x00000000 + 0xFFFFFFFF + + + + + TIMER0 + 1.0 + 32 Timer / Counter, counting up or down from different sources + TIMER + 0x40010000 + 32 + read-write + + + 0 + 0x100 + registers + + + + TIMER0 + 0 + + + + + + CR + Control Register + 0x00 + 32 + read-write + 0x00000000 + 0x1337F7F + + + + + EN + Enable + [0:0] + read-write + + + Disable + Timer is disabled and does not operate + 0 + + + Enable + Timer is enabled and can operate + 1 + + + + + + + RST + Reset Timer + [1:1] + write-only + + + Reserved + Write as ZERO if necessary + 0 + + + Reset_Timer + Reset the Timer + 1 + + + + + + + CNT + Counting direction + [3:2] + read-write + + + Count_UP + Timer Counts UO and wraps, if no STOP condition is set + 0 + + + Count_DOWN + Timer Counts DOWN and wraps, if no STOP condition is set + 1 + + + Toggle + Timer Counts up to MAX, then DOWN to ZERO, if no STOP condition is set + 2 + + + + + + + MODE + Operation Mode + [6:4] + read-write + + + Continous + Timer runs continously + 0 + + + Single_ZERO_MAX + Timer counts to 0x00 or 0xFFFFFFFF (depending on CNT) and stops + 1 + + + Single_MATCH + Timer counts to the Value of MATCH Register and stops + 2 + + + Reload_ZERO_MAX + Timer counts to 0x00 or 0xFFFFFFFF (depending on CNT), loads the RELOAD Value and continues + 3 + + + Reload_MATCH + Timer counts to the Value of MATCH Register, loads the RELOAD Value and continues + 4 + + + + + + + PSC + Use Prescaler + [7:7] + read-write + + + Disabled + Prescaler is not used + 0 + + + Enabled + Prescaler is used as divider + 1 + + + + + + + CNTSRC + Timer / Counter Source Divider + [11:8] + read-write + + + CAP_SRC + Capture Source is used directly + 0 + + + CAP_SRC_div2 + Capture Source is divided by 2 + 1 + + + CAP_SRC_div4 + Capture Source is divided by 4 + 2 + + + CAP_SRC_div8 + Capture Source is divided by 8 + 3 + + + CAP_SRC_div16 + Capture Source is divided by 16 + 4 + + + CAP_SRC_div32 + Capture Source is divided by 32 + 5 + + + CAP_SRC_div64 + Capture Source is divided by 64 + 6 + + + CAP_SRC_div128 + Capture Source is divided by 128 + 7 + + + CAP_SRC_div256 + Capture Source is divided by 256 + 8 + + + + + + + CAPSRC + Timer / Counter Capture Source + [15:12] + read-write + + + CClk + Core Clock + 0 + + + GPIOA_0 + GPIO A, PIN 0 + 1 + + + GPIOA_1 + GPIO A, PIN 1 + 2 + + + GPIOA_2 + GPIO A, PIN 2 + 3 + + + GPIOA_3 + GPIO A, PIN 3 + 4 + + + GPIOA_4 + GPIO A, PIN 4 + 5 + + + GPIOA_5 + GPIO A, PIN 5 + 6 + + + GPIOA_6 + GPIO A, PIN 6 + 7 + + + GPIOA_7 + GPIO A, PIN 7 + 8 + + + GPIOB_0 + GPIO B, PIN 0 + 9 + + + GPIOB_1 + GPIO B, PIN 1 + 10 + + + GPIOB_2 + GPIO B, PIN 2 + 11 + + + GPIOB_3 + GPIO B, PIN 3 + 12 + + + GPIOC_0 + GPIO C, PIN 0 + 13 + + + GPIOC_5 + GPIO C, PIN 1 + 14 + + + GPIOC_6 + GPIO C, PIN 2 + 15 + + + + + + + CAPEDGE + Capture Edge, select which Edge should result in a counter increment or decrement + [17:16] + read-write + + + RISING + Only rising edges result in a counter increment or decrement + 0 + + + FALLING + Only falling edges result in a counter increment or decrement + 1 + + + BOTH + Rising and falling edges result in a counter increment or decrement + 2 + + + + + + + TRGEXT + Triggers an other Peripheral + [21:20] + read-write + + + NONE + No Trigger is emitted + 0 + + + DMA1 + DMA Controller 1 is triggered, dependant on MODE + 1 + + + DMA2 + DMA Controller 2 is triggered, dependant on MODE + 2 + + + UART + UART is triggered, dependant on MODE + 3 + + + + + + + RELOAD + Select RELOAD Register n to reload Timer on condition + [25:24] + read-write + + + RELOAD0 + Selects Reload Register number 0 + 0 + + + RELOAD1 + Selects Reload Register number 1 + 1 + + + RELOAD2 + Selects Reload Register number 2 + 2 + + + RELOAD3 + Selects Reload Register number 3 + 3 + + + + + + + IDR + Selects, if Reload Register number is incremented, decremented or not modified + [27:26] + read-write + + + KEEP + Reload Register number does not change automatically + 0 + + + INCREMENT + Reload Register number is incremented on each match + 1 + + + DECREMENT + Reload Register number is decremented on each match + 2 + + + + + + + S + Starts and Stops the Timer / Counter + [31:31] + read-write + + + STOP + Timer / Counter is stopped + 0 + + + START + Timer / Counter is started + 1 + + + + + + + + + SR + Status Register + 0x04 + 16 + read-write + 0x00000000 + 0xD701 + + + + + RUN + Shows if Timer is running or not + [0:0] + read-only + + + Stopped + Timer is not running + 0 + + + Running + Timer is running + 1 + + + + + + + MATCH + Shows if the MATCH was hit + [8:8] + read-write + + + No_Match + The MATCH condition was not hit + 0 + + + Match_Hit + The MATCH condition was hit + 1 + + + + + + + UN + Shows if an underflow occured. This flag is sticky + [9:9] + read-write + + + No_Underflow + No underflow occured since last clear + 0 + + + Underflow + A minimum of one underflow occured since last clear + 1 + + + + + + + OV + Shows if an overflow occured. This flag is sticky + [10:10] + read-write + + + No_Overflow + No overflow occured since last clear + 0 + + + Overflow_occured + A minimum of one overflow occured since last clear + 1 + + + + + + + RST + Shows if Timer is in RESET state + [12:12] + read-only + + + Ready + Timer is not in RESET state and can operate + 0 + + + In_Reset + Timer is in RESET state and can not operate + 1 + + + + + + + RELOAD + Shows the currently active RELOAD Register + [15:14] + read-only + + + RELOAD0 + Reload Register number 0 is active + 0 + + + RELOAD1 + Reload Register number 1 is active + 1 + + + RELOAD2 + Reload Register number 2 is active + 2 + + + RELOAD3 + Reload Register number 3 is active + 3 + + + + + + + + + INT + Interrupt Register + 0x10 + 16 + read-write + 0x00000000 + 0x0771 + + + + + EN + Interrupt Enable + [0:0] + read-write + + + Disabled + Timer does not generate Interrupts + 0 + + + Enable + Timer triggers the TIMERn Interrupt + 1 + + + + + + + MODE + Interrupt Mode, selects on which condition the Timer should generate an Interrupt + [6:4] + read-write + + + Match + Timer generates an Interrupt when the MATCH condition is hit + 0 + + + Underflow + Timer generates an Interrupt when it underflows + 1 + + + Overflow + Timer generates an Interrupt when it overflows + 2 + + + + + + + + + COUNT + The Counter Register reflects the actual Value of the Timer/Counter + 0x20 + 32 + read-write + 0x00000000 + 0xFFFFFFFF + + + + + MATCH + The Match Register stores the compare Value for the MATCH condition + 0x24 + 32 + read-write + 0x00000000 + 0xFFFFFFFF + + + + + PRESCALE_RD + The Prescale Register stores the Value for the prescaler. The cont event gets divided by this value + 0x28 + 32 + read-only + 0x00000000 + 0xFFFFFFFF + + + + + PRESCALE_WR + The Prescale Register stores the Value for the prescaler. The cont event gets divided by this value + 0x28 + 32 + write-only + 0x00000000 + 0xFFFFFFFF + + + + + + 4 + 4 + 0,1,2,3 + RELOAD[%s] + The Reload Register stores the Value the COUNT Register gets reloaded on a when a condition was met. + 0x50 + 32 + read-write + 0x00000000 + 0xFFFFFFFF + + + + + + + TIMER1 + 0x40010100 + + TIMER1 + 4 + + + + + + TIMER2 + 0x40010200 + + TIMER2 + 6 + + + + diff --git a/Libraries/CMSIS/SVD/ARM_Sample_1_1.svd b/Libraries/CMSIS/SVD/ARM_Sample_1_1.svd new file mode 100644 index 0000000..b71d48b --- /dev/null +++ b/Libraries/CMSIS/SVD/ARM_Sample_1_1.svd @@ -0,0 +1,763 @@ + + + + + + + + ARM Ltd. + ARM + ARMCM3xxx + ARMCM3 + 1.2 + ARM 32-bit Cortex-M3 Microcontroller based device, CPU clock up to 80MHz, etc. + + ARM Limited (ARM) is supplying this software for use with Cortex-M\n + processor based microcontroller, but can be equally used for other\n + suitable processor architectures. This file can be freely distributed.\n + Modifications to this file shall be clearly marked.\n + \n + THIS SOFTWARE IS PROVIDED "AS IS". NO WARRANTIES, WHETHER EXPRESS, IMPLIED\n + OR STATUTORY, INCLUDING, BUT NOT LIMITED TO, IMPLIED WARRANTIES OF\n + MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE APPLY TO THIS SOFTWARE.\n + ARM SHALL NOT, IN ANY CIRCUMSTANCES, BE LIABLE FOR SPECIAL, INCIDENTAL, OR\n + CONSEQUENTIAL DAMAGES, FOR ANY REASON WHATSOEVER. + + + CM3 + r1p0 + little + true + false + 3 + false + + 8 + 32 + + 32 + read-write + 0x00000000 + 0xFFFFFFFF + + + + + TIMER0 + 1.0 + 32 Timer / Counter, counting up or down from different sources + TIMER + 0x40010000 + 32 + read-write + + + 0 + 0x100 + registers + + + + TIMER0 + 0 + + + + + + CR + Control Register + 0x00 + 32 + read-write + 0x00000000 + 0x1337F7F + + + + + EN + Enable + [0:0] + read-write + + + Disable + Timer is disabled and does not operate + 0 + + + Enable + Timer is enabled and can operate + 1 + + + + + + + RST + Reset Timer + [1:1] + write-only + + + Reserved + Write as ZERO if necessary + 0 + + + Reset_Timer + Reset the Timer + 1 + + + + + + + CNT + Counting direction + [3:2] + read-write + + + Count_UP + Timer Counts UO and wraps, if no STOP condition is set + 0 + + + Count_DOWN + Timer Counts DOWN and wraps, if no STOP condition is set + 1 + + + Toggle + Timer Counts up to MAX, then DOWN to ZERO, if no STOP condition is set + 2 + + + + + + + MODE + Operation Mode + [6:4] + read-write + + + Continous + Timer runs continously + 0 + + + Single_ZERO_MAX + Timer counts to 0x00 or 0xFFFFFFFF (depending on CNT) and stops + 1 + + + Single_MATCH + Timer counts to the Value of MATCH Register and stops + 2 + + + Reload_ZERO_MAX + Timer counts to 0x00 or 0xFFFFFFFF (depending on CNT), loads the RELOAD Value and continues + 3 + + + Reload_MATCH + Timer counts to the Value of MATCH Register, loads the RELOAD Value and continues + 4 + + + + + + + PSC + Use Prescaler + [7:7] + read-write + + + Disabled + Prescaler is not used + 0 + + + Enabled + Prescaler is used as divider + 1 + + + + + + + CNTSRC + Timer / Counter Source Divider + [11:8] + read-write + + + CAP_SRC + Capture Source is used directly + 0 + + + CAP_SRC_div2 + Capture Source is divided by 2 + 1 + + + CAP_SRC_div4 + Capture Source is divided by 4 + 2 + + + CAP_SRC_div8 + Capture Source is divided by 8 + 3 + + + CAP_SRC_div16 + Capture Source is divided by 16 + 4 + + + CAP_SRC_div32 + Capture Source is divided by 32 + 5 + + + CAP_SRC_div64 + Capture Source is divided by 64 + 6 + + + CAP_SRC_div128 + Capture Source is divided by 128 + 7 + + + CAP_SRC_div256 + Capture Source is divided by 256 + 8 + + + + + + + CAPSRC + Timer / Counter Capture Source + [15:12] + read-write + + + CClk + Core Clock + 0 + + + GPIOA_0 + GPIO A, PIN 0 + 1 + + + GPIOA_1 + GPIO A, PIN 1 + 2 + + + GPIOA_2 + GPIO A, PIN 2 + 3 + + + GPIOA_3 + GPIO A, PIN 3 + 4 + + + GPIOA_4 + GPIO A, PIN 4 + 5 + + + GPIOA_5 + GPIO A, PIN 5 + 6 + + + GPIOA_6 + GPIO A, PIN 6 + 7 + + + GPIOA_7 + GPIO A, PIN 7 + 8 + + + GPIOB_0 + GPIO B, PIN 0 + 9 + + + GPIOB_1 + GPIO B, PIN 1 + 10 + + + GPIOB_2 + GPIO B, PIN 2 + 11 + + + GPIOB_3 + GPIO B, PIN 3 + 12 + + + GPIOC_0 + GPIO C, PIN 0 + 13 + + + GPIOC_5 + GPIO C, PIN 1 + 14 + + + GPIOC_6 + GPIO C, PIN 2 + 15 + + + + + + + CAPEDGE + Capture Edge, select which Edge should result in a counter increment or decrement + [17:16] + read-write + + + RISING + Only rising edges result in a counter increment or decrement + 0 + + + FALLING + Only falling edges result in a counter increment or decrement + 1 + + + BOTH + Rising and falling edges result in a counter increment or decrement + 2 + + + + + + + TRGEXT + Triggers an other Peripheral + [21:20] + read-write + + + NONE + No Trigger is emitted + 0 + + + DMA1 + DMA Controller 1 is triggered, dependant on MODE + 1 + + + DMA2 + DMA Controller 2 is triggered, dependant on MODE + 2 + + + UART + UART is triggered, dependant on MODE + 3 + + + + + + + RELOAD + Select RELOAD Register n to reload Timer on condition + [25:24] + read-write + + + RELOAD0 + Selects Reload Register number 0 + 0 + + + RELOAD1 + Selects Reload Register number 1 + 1 + + + RELOAD2 + Selects Reload Register number 2 + 2 + + + RELOAD3 + Selects Reload Register number 3 + 3 + + + + + + + IDR + Selects, if Reload Register number is incremented, decremented or not modified + [27:26] + read-write + + + KEEP + Reload Register number does not change automatically + 0 + + + INCREMENT + Reload Register number is incremented on each match + 1 + + + DECREMENT + Reload Register number is decremented on each match + 2 + + + + + + + S + Starts and Stops the Timer / Counter + [31:31] + read-write + + + STOP + Timer / Counter is stopped + 0 + + + START + Timer / Counter is started + 1 + + + + + + + + + SR + Status Register + 0x04 + 16 + read-write + 0x00000000 + 0xD701 + + + + + RUN + Shows if Timer is running or not + [0:0] + read-only + + + Stopped + Timer is not running + 0 + + + Running + Timer is running + 1 + + + + + + + MATCH + Shows if the MATCH was hit + [8:8] + read-write + + + No_Match + The MATCH condition was not hit + 0 + + + Match_Hit + The MATCH condition was hit + 1 + + + + + + + UN + Shows if an underflow occured. This flag is sticky + [9:9] + read-write + + + No_Underflow + No underflow occured since last clear + 0 + + + Underflow + A minimum of one underflow occured since last clear + 1 + + + + + + + OV + Shows if an overflow occured. This flag is sticky + [10:10] + read-write + + + No_Overflow + No overflow occured since last clear + 0 + + + Overflow_occured + A minimum of one overflow occured since last clear + 1 + + + + + + + RST + Shows if Timer is in RESET state + [12:12] + read-only + + + Ready + Timer is not in RESET state and can operate + 0 + + + In_Reset + Timer is in RESET state and can not operate + 1 + + + + + + + RELOAD + Shows the currently active RELOAD Register + [15:14] + read-only + + + RELOAD0 + Reload Register number 0 is active + 0 + + + RELOAD1 + Reload Register number 1 is active + 1 + + + RELOAD2 + Reload Register number 2 is active + 2 + + + RELOAD3 + Reload Register number 3 is active + 3 + + + + + + + + + INT + Interrupt Register + 0x10 + 16 + read-write + 0x00000000 + 0x0771 + + + + + EN + Interrupt Enable + [0:0] + read-write + + + Disabled + Timer does not generate Interrupts + 0 + + + Enable + Timer triggers the TIMERn Interrupt + 1 + + + + + + + MODE + Interrupt Mode, selects on which condition the Timer should generate an Interrupt + [6:4] + read-write + + + Match + Timer generates an Interrupt when the MATCH condition is hit + 0 + + + Underflow + Timer generates an Interrupt when it underflows + 1 + + + Overflow + Timer generates an Interrupt when it overflows + 2 + + + + + + + + + COUNT + The Counter Register reflects the actual Value of the Timer/Counter + 0x20 + 32 + read-write + 0x00000000 + 0xFFFFFFFF + + + + + MATCH + The Match Register stores the compare Value for the MATCH condition + 0x24 + 32 + read-write + 0x00000000 + 0xFFFFFFFF + + + + + PRESCALE_RD + The Prescale Register stores the Value for the prescaler. The cont event gets divided by this value + 0x28 + 32 + read-only + 0x00000000 + 0xFFFFFFFF + + + + + PRESCALE_WR + The Prescale Register stores the Value for the prescaler. The cont event gets divided by this value + 0x28 + 32 + write-only + 0x00000000 + 0xFFFFFFFF + + + + + + 4 + 4 + 0,1,2,3 + RELOAD[%s] + The Reload Register stores the Value the COUNT Register gets reloaded on a when a condition was met. + 0x50 + 32 + read-write + 0x00000000 + 0xFFFFFFFF + + + + + + + TIMER1 + 0x40010100 + + TIMER1 + 4 + + + + + + TIMER2 + 0x40010200 + + TIMER2 + 6 + + + + diff --git a/Libraries/CMSIS/SVD/CMSIS-SVD_Schema_1_0.xsd b/Libraries/CMSIS/SVD/CMSIS-SVD_Schema_1_0.xsd new file mode 100644 index 0000000..ceabcb0 --- /dev/null +++ b/Libraries/CMSIS/SVD/CMSIS-SVD_Schema_1_0.xsd @@ -0,0 +1,274 @@ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + diff --git a/Libraries/CMSIS/SVD/CMSIS-SVD_Schema_1_1_draft.xsd b/Libraries/CMSIS/SVD/CMSIS-SVD_Schema_1_1_draft.xsd new file mode 100644 index 0000000..b42f73c --- /dev/null +++ b/Libraries/CMSIS/SVD/CMSIS-SVD_Schema_1_1_draft.xsd @@ -0,0 +1,509 @@ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + 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--- /dev/null +++ b/Libraries/CMSIS/index.html @@ -0,0 +1,14 @@ + + + +Redirect to the CMSIS main page after 0 seconds + + + + + + +If the automatic redirection is failing, click open CMSIS Documentation. + + + diff --git a/Libraries/STM32F10x_StdPeriph_Driver/Release_Notes.html b/Libraries/STM32F10x_StdPeriph_Driver/Release_Notes.html new file mode 100644 index 0000000..8999a27 --- /dev/null +++ b/Libraries/STM32F10x_StdPeriph_Driver/Release_Notes.html @@ -0,0 +1,340 @@ + + + + + + + + + + + + +Release Notes for STM32F10x Standard Peripherals Library Drivers + + + + + +
    +


    +

    +
    + + + + + + +
    + + + + + + + + + +
    Back to Release page
    +

    Release +Notes for STM32F10x Standard Peripherals Library Drivers

    +

    Copyright 2012 STMicroelectronics

    +

    +
    +

     

    + + + + + + +
    +

    Contents

    +
      +
    1. STM32F10x Standard Peripherals Library +Drivers update History
      2. +
    2. License
      3. +
    + + +

    STM32F10x Standard +Peripherals Library Drivers  update History

    V3.6.1 / 05-March-2012

    +

    Main +Changes

    + +
    • All source files: license disclaimer text update and add link to the License file on ST Internet.

    V3.6.0 / 27-January-2012

    Main +Changes

    +
    • All source files: update disclaimer to add reference to the new license agreement
    • stm32f10x_sdio.c
      • SDIO_SetPowerState() function: fix POWER register configuration, only one access (for read or write) is allowed
    • stm32f10x_usart.h/.c
      • Update procedure to check on overrun error interrupt pending bit, defines for the following flag are added:
        • USART_IT_ORE_RX: this flag is set if overrun error interrupt occurs and RXNEIE bit is set
        • USART_IT_ORE_ER: this flag is set if overrun error interrupt occurs and EIE bit is set
      • Remove IS_USART_PERIPH_FLAG macro (not used)
    • stm32f10x_rtc.c
      • Update RTC_GetCounter() function to fix issue when reading the RTC counter registers (CNTL & CNTH registers) and the counter rolls over
    • stm32f10x_flash.c
      • Flash keys moved from to stm32f10x.h file
    • stm32f10x_tim.c
      • TIM_UpdateRequestConfig(): correct function header's comment 
    • stm32f10x_exti.h
      • EXTI_InitTypeDef structure : for “EXTI_Trigger“ member, change “@ref EXTIMode_TypeDef”  by  “@ref EXTITrigger_TypeDef” 
    +

    V3.5.0 / 11-March-2011

    +

    Main +Changes

    + +
      +
    • stm32f10x_can.h/.c files:
      • +
        +
      • Add 5 new functions
        • +
          +
        • 3 +new functions controlling the counter errors: CAN_GetLastErrorCode(), +CAN_GetReceiveErrorCounter() and CAN_GetLSBTransmitErrorCounter().
          • +
        +
          +
        • 1 new function to select the CAN operating mode: CAN_OperatingModeRequest().
          • +
        +
          +
        • 1 new function to support CAN TT mode: CAN_TTComModeCmd().
          +
          • +
        +
      • CAN_TransmitStatus() function updated to support all CAN transmit intermediate states
        +
        • +
      +
    • stm32f10x_i2c.h/.c files:
      • +
        +
      • Add 1 new function:
        • +
          +
        • I2C_NACKPositionConfig(): +This function configures the same bit (POS) as I2C_PECPositionConfig() +but is intended to be used in I2C mode while I2C_PECPositionConfig() is +intended to used in SMBUS mode.
          • +
        +
      +
    • stm32f10x_tim.h/.c files:
      • +
        +
      • Change the TIM_DMABurstLength_xBytes definitions to TIM_DMABurstLength_xTansfers
        +
        • +
      + + +
    + +

    3.4.0 +- 10/15/2010

    + +
      +
    1. General
      2. +
    + +
      +
    • Add support for STM32F10x High-density value line devices.
      • +
    + +
      +
    1. STM32F10x_StdPeriph_Driver
      2. +
    + + +
      + +
    • stm32f10x_bkp.h/.c
      • +
        +
      • Delete BKP registers definition from stm32f10x_bkp.c and use defines within stm32f10x.h file.
        • +
      +
    • stm32f10x_can.h/.c
      • +
        +
      • Delete CAN registers definition from stm32f10x_can.c and use defines within stm32f10x.h file.
        +
        • +
      • Update the wording of some defines and Asserts macro.
        +
        • +
      • CAN_GetFlagStatus() +and CAN_ClearFlag() functions: updated to support new flags (were not +supported in previous version). These flags are:  CAN_FLAG_RQCP0, +CAN_FLAG_RQCP1, CAN_FLAG_RQCP2, CAN_FLAG_FMP1, CAN_FLAG_FF1, +CAN_FLAG_FOV1, CAN_FLAG_FMP0, CAN_FLAG_FF0,   CAN_FLAG_FOV0, +CAN_FLAG_WKU, CAN_FLAG_SLAK and CAN_FLAG_LEC.
        +
        • +
      • CAN_GetITStatus() +function: add a check of the interrupt enable bit before getting the +status of corresponding interrupt pending bit.
        +
        • +
      • CAN_ClearITPendingBit() function: correct the procedure to clear the interrupt pending bit.
        +
        • +
      +
    • stm32f10x_crc.h/.c
      • +
        +
      • Delete CRC registers definition from stm32f10x_crc.c and use defines within stm32f10x.h file.
        • +
      +
    • stm32f10x_dac.h/.c
      • +
        +
      • Delete DAC registers definition from stm32f10x_dac.c and use defines within stm32f10x.h file.
        • +
      +
    • stm32f10x_dbgmcu.h/.c
      • +
        +
      • Delete DBGMCU registers definition from stm32f10x_dbgmcu.c and use defines within stm32f10x.h file.
        • +
      +
    • stm32f10x_dma.h/.c
      • +
        +
      • Delete DMA registers definition from stm32f10x_dma.c and use defines within stm32f10x.h file.
        • +
      • Add new function "void DMA_SetCurrDataCounter(DMA_Channel_TypeDef* DMAy_Channelx, uint16_t DataNumber);"
        +
        • +
      +
    • stm32f10x_flash.h/.c
      • +
        +
      • FLASH functions (Erase and Program) updated to always clear the "PG", "MER" and "PER" bits even in case of TimeOut Error.
        • +
      +
    • stm32f10x_fsmc.h/.c
      • +
        +
      • Add new member "FSMC_AsynchronousWait" in "FSMC_NORSRAMInitTypeDef" structure.
        • +
      +
    • stm32f10x_gpio.h/.c
      • +
        +
      • GPIO_PinRemapConfig() function: add new values for GPIO_Remap parameter, to support new remap for TIM6, TIM7 and DAC DMA requests, TIM12 and DAC Triggers / DMA2_Channel5 Interrupt mapping.
        • +
      +
    • stm32f10x_pwr.h/.c
      • +
        +
      • Delete PWR registers definition from stm32f10x_pwr.c and use defines within stm32f10x.h and core_cm3.h files.
        • +
      +
    • stm32f10x_rtc.h/.c
      • +
        +
      • Delete RTC registers definition from stm32f10x_rtc.c and use defines within stm32f10x.h file.
        • +
      +
    • stm32f10x_spi.h/.c
      • +
        +
      • Add new definition for I2S Audio Clock frequencies "I2S_AudioFreq_192k".
        • +
      +
    • stm32f10x_tim.h/.c
      • +
      • Add new definition for TIM Input Capture Polarity "TIM_ICPolarity_BothEdge".
      + +
    + +

    3.3.0 +- 04/16/2010

    + +
    1. General
    +
    • Add support for STM32F10x XL-density devices.
    • I2C driver: events description and management enhancement.
    +
    1. STM32F10x_StdPeriph_Driver
    +
    • stm32f10x_dbgmcu.h/.c
      • DBGMCU_Config() function: add new values DBGMCU_TIMx_STOP (x: 9..14) for DBGMCU_Periph parameter.
    • stm32f10x_flash.h/.c: +updated to support Bank2 of XL-density devices (up to 1MByte of Flash +memory). For more details, refer to the description provided within +stm32f10x_flash.c file.
    • stm32f10x_gpio.h/.c
      • GPIO_PinRemapConfig() function: add new values for GPIO_Remap parameter, to support new remap for FSMC_NADV pin and TIM9..11,13,14.
    • stm32f10x_i2c.h/.c: I2C events description and management enhancement.
      • I2C_CheckEvent() +function: updated to check whether the last event contains the +I2C_EVENT  (instead of check whether the last event is equal to +I2C_EVENT)
      • Add +detailed description of I2C events and how to manage them using the +functions provided by this driver. For more information, refer to +stm32f10x_i2c.h and stm32f10x_i2c.c files.
    • stm32f10x_rcc.h/.c: updated to support TIM9..TIM14 APB clock and reset configuration
    • stm32f10x_tim.h/.c: updated to support new Timers TIM9..TIM14.
    • stm32f10x_sdio.h: 
      • SDIO_SetSDIOReadWaitMode() function: correct values of SDIO_ReadWaitMode parameter
        change
          +#define +SDIO_ReadWaitMode_CLK               +  ((uint32_t)0x00000000)
          #define +SDIO_ReadWaitMode_DATA2             +((uint32_t)0x00000001)
        by
          #define +SDIO_ReadWaitMode_CLK               +  ((uint32_t)0x00000001)
          #define +SDIO_ReadWaitMode_DATA2             +((uint32_t)0x00000000)
    +

    3.2.0 +- 03/01/2010

    +
      +
    1. General
      2. +
    +
      + +
    • Add support +for STM32 Low-density Value line (STM32F100x4/6) and +Medium-density Value line (STM32F100x8/B) devices.
      • +
    • Almost +peripherals drivers were updated to support Value +line devices features
      • +
    • Drivers limitations fix and enhancements.
      • + +
    +
      +
    1. STM32F10x_StdPeriph_Driver
      2. +
    +
      +
    • Add new +firmware driver for CEC peripheral: stm32f10x_cec.h and stm32f10x_cec.c
      • +
    • Timers drivers stm32f10x_tim.h/.c: add support for new General Purpose Timers: TIM15, TIM16 and TIM17.
      • +
    • RCC driver: add support for new Value peripherals: HDMI-CEC, TIM15, TIM16 and TIM17.
      • +
    • GPIO driver: add new remap parameters for TIM1, TIM15, TIM16, TIM17 and HDMI-CEC: GPIO_Remap_TIM1_DMA, GPIO_Remap_TIM15, GPIO_Remap_TIM16, GPIO_Remap_TIM17, GPIO_Remap_CEC.
      • +
    • USART +driver: add support for Oversampling by 8 mode and onebit method. 2 +functions has been added: USART_OverSampling8Cmd() and +USART_OneBitMethodCmd().
      +
      • +
    • DAC +driver: add new functions handling the DAC under run feature: +DAC_ITConfig(), DAC_GetFlagStatus(), DAC_ClearFlag(), DAC_GetITStatus() +and DAC_ClearITPendingBit().
      • +
    • DBGMCU driver: add new parameters for TIM15, TIM16 and TIM17: DBGMCU_TIM15_STOP, DBGMCU_TIM16_STOP, DBGMCU_TIM17_STOP.
      +
      • +
    • FLASH +driver: the FLASH_EraseOptionBytes() function updated. This is now just +erasing the option bytes without modifying the RDP status either +enabled or disabled.
      • +
    • PWR +driver: the PWR_EnterSTOPMode() function updated. When woken up from +STOP mode, this function resets again the SLEEPDEEP bit in the +Cortex-M3 System Control register to allow Sleep mode entering.
      • + + +
    +

    License

    +

    Licensed under MCD-ST Liberty SW License Agreement V2, (the "License"); You may not use this package except in compliance with the License. You may obtain a copy of the License at:


    Unless +required by applicable law or agreed to in writing, software +distributed under the License is distributed on an "AS IS" BASIS,
    WITHOUT +WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See +the License for the specific language governing permissions and +limitations under the License.

    +
    +
    +

    For +complete documentation on STM32(CORTEX M3) 32-Bit Microcontrollers +visit www.st.com/STM32

    +
    +

    +
    +
    +

     

    +
    + \ No newline at end of file diff --git a/Libraries/STM32F10x_StdPeriph_Driver/inc/misc.h b/Libraries/STM32F10x_StdPeriph_Driver/inc/misc.h new file mode 100644 index 0000000..0fea5b2 --- /dev/null +++ b/Libraries/STM32F10x_StdPeriph_Driver/inc/misc.h @@ -0,0 +1,226 @@ +/** + ****************************************************************************** + * @file misc.h + * @author MCD Application Team + * @version V3.6.1 + * @date 05-March-2012 + * @brief This file contains all the functions prototypes for the miscellaneous + * firmware library functions (add-on to CMSIS functions). + ****************************************************************************** + * @attention + * + *

    © COPYRIGHT 2012 STMicroelectronics

    + * + * Licensed under MCD-ST Liberty SW License Agreement V2, (the "License"); + * You may not use this file except in compliance with the License. + * You may obtain a copy of the License at: + * + * http://www.st.com/software_license_agreement_liberty_v2 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, + * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + * + ****************************************************************************** + */ + +/* Define to prevent recursive inclusion -------------------------------------*/ +#ifndef __MISC_H +#define __MISC_H + +#ifdef __cplusplus + extern "C" { +#endif + +/* Includes ------------------------------------------------------------------*/ +#include "stm32f10x.h" + +/** @addtogroup STM32F10x_StdPeriph_Driver + * @{ + */ + +/** @addtogroup MISC + * @{ + */ + +/** @defgroup MISC_Exported_Types + * @{ + */ + +/** + * @brief NVIC Init Structure definition + */ + +typedef struct +{ + uint8_t NVIC_IRQChannel; /*!< Specifies the IRQ channel to be enabled or disabled. + This parameter can be a value of @ref IRQn_Type + (For the complete STM32 Devices IRQ Channels list, please + refer to stm32f10x.h file) */ + + uint8_t NVIC_IRQChannelPreemptionPriority; /*!< Specifies the pre-emption priority for the IRQ channel + specified in NVIC_IRQChannel. This parameter can be a value + between 0 and 15 as described in the table @ref NVIC_Priority_Table */ + + uint8_t NVIC_IRQChannelSubPriority; /*!< Specifies the subpriority level for the IRQ channel specified + in NVIC_IRQChannel. This parameter can be a value + between 0 and 15 as described in the table @ref NVIC_Priority_Table */ + + FunctionalState NVIC_IRQChannelCmd; /*!< Specifies whether the IRQ channel defined in NVIC_IRQChannel + will be enabled or disabled. + This parameter can be set either to ENABLE or DISABLE */ +} NVIC_InitTypeDef; + +/** + * @} + */ + +/** @defgroup NVIC_Priority_Table + * @{ + */ + +/** +@code + The table below gives the allowed values of the pre-emption priority and subpriority according + to the Priority Grouping configuration performed by NVIC_PriorityGroupConfig function + ============================================================================================================================ + NVIC_PriorityGroup | NVIC_IRQChannelPreemptionPriority | NVIC_IRQChannelSubPriority | Description + ============================================================================================================================ + NVIC_PriorityGroup_0 | 0 | 0-15 | 0 bits for pre-emption priority + | | | 4 bits for subpriority + ---------------------------------------------------------------------------------------------------------------------------- + NVIC_PriorityGroup_1 | 0-1 | 0-7 | 1 bits for pre-emption priority + | | | 3 bits for subpriority + ---------------------------------------------------------------------------------------------------------------------------- + NVIC_PriorityGroup_2 | 0-3 | 0-3 | 2 bits for pre-emption priority + | | | 2 bits for subpriority + ---------------------------------------------------------------------------------------------------------------------------- + NVIC_PriorityGroup_3 | 0-7 | 0-1 | 3 bits for pre-emption priority + | | | 1 bits for subpriority + ---------------------------------------------------------------------------------------------------------------------------- + NVIC_PriorityGroup_4 | 0-15 | 0 | 4 bits for pre-emption priority + | | | 0 bits for subpriority + ============================================================================================================================ +@endcode +*/ + +/** + * @} + */ + +/** @defgroup MISC_Exported_Constants + * @{ + */ + +/** @defgroup Vector_Table_Base + * @{ + */ + +#define NVIC_VectTab_RAM ((uint32_t)0x20000000) +#define NVIC_VectTab_FLASH ((uint32_t)0x08000000) +#define IS_NVIC_VECTTAB(VECTTAB) (((VECTTAB) == NVIC_VectTab_RAM) || \ + ((VECTTAB) == NVIC_VectTab_FLASH)) +/** + * @} + */ + +/** @defgroup System_Low_Power + * @{ + */ + +#define NVIC_LP_SEVONPEND ((uint8_t)0x10) +#define NVIC_LP_SLEEPDEEP ((uint8_t)0x04) +#define NVIC_LP_SLEEPONEXIT ((uint8_t)0x02) +#define IS_NVIC_LP(LP) (((LP) == NVIC_LP_SEVONPEND) || \ + ((LP) == NVIC_LP_SLEEPDEEP) || \ + ((LP) == NVIC_LP_SLEEPONEXIT)) +/** + * @} + */ + +/** @defgroup Preemption_Priority_Group + * @{ + */ + +#define NVIC_PriorityGroup_0 ((uint32_t)0x700) /*!< 0 bits for pre-emption priority + 4 bits for subpriority */ +#define NVIC_PriorityGroup_1 ((uint32_t)0x600) /*!< 1 bits for pre-emption priority + 3 bits for subpriority */ +#define NVIC_PriorityGroup_2 ((uint32_t)0x500) /*!< 2 bits for pre-emption priority + 2 bits for subpriority */ +#define NVIC_PriorityGroup_3 ((uint32_t)0x400) /*!< 3 bits for pre-emption priority + 1 bits for subpriority */ +#define NVIC_PriorityGroup_4 ((uint32_t)0x300) /*!< 4 bits for pre-emption priority + 0 bits for subpriority */ + +#define IS_NVIC_PRIORITY_GROUP(GROUP) (((GROUP) == NVIC_PriorityGroup_0) || \ + ((GROUP) == NVIC_PriorityGroup_1) || \ + ((GROUP) == NVIC_PriorityGroup_2) || \ + ((GROUP) == NVIC_PriorityGroup_3) || \ + ((GROUP) == NVIC_PriorityGroup_4)) + +#define IS_NVIC_PREEMPTION_PRIORITY(PRIORITY) ((PRIORITY) < 0x10) + +#define IS_NVIC_SUB_PRIORITY(PRIORITY) ((PRIORITY) < 0x10) + +#define IS_NVIC_OFFSET(OFFSET) ((OFFSET) < 0x000FFFFF) + +/** + * @} + */ + +/** @defgroup SysTick_clock_source + * @{ + */ + +#define SysTick_CLKSource_HCLK_Div8 ((uint32_t)0xFFFFFFFB) +#define SysTick_CLKSource_HCLK ((uint32_t)0x00000004) +#define IS_SYSTICK_CLK_SOURCE(SOURCE) (((SOURCE) == SysTick_CLKSource_HCLK) || \ + ((SOURCE) == SysTick_CLKSource_HCLK_Div8)) +/** + * @} + */ + +/** + * @} + */ + +/** @defgroup MISC_Exported_Macros + * @{ + */ + +/** + * @} + */ + +/** @defgroup MISC_Exported_Functions + * @{ + */ + +void NVIC_PriorityGroupConfig(uint32_t NVIC_PriorityGroup); +void NVIC_Init(NVIC_InitTypeDef* NVIC_InitStruct); +void NVIC_SetVectorTable(uint32_t NVIC_VectTab, uint32_t Offset); +void NVIC_SystemLPConfig(uint8_t LowPowerMode, FunctionalState NewState); +void SysTick_CLKSourceConfig(uint32_t SysTick_CLKSource); + +#ifdef __cplusplus +} +#endif + +#endif /* __MISC_H */ + +/** + * @} + */ + +/** + * @} + */ + +/** + * @} + */ + +/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ diff --git a/Libraries/STM32F10x_StdPeriph_Driver/inc/stm32f10x_adc.h b/Libraries/STM32F10x_StdPeriph_Driver/inc/stm32f10x_adc.h new file mode 100644 index 0000000..5125a5b --- /dev/null +++ b/Libraries/STM32F10x_StdPeriph_Driver/inc/stm32f10x_adc.h @@ -0,0 +1,489 @@ +/** + ****************************************************************************** + * @file stm32f10x_adc.h + * @author MCD Application Team + * @version V3.6.1 + * @date 05-March-2012 + * @brief This file contains all the functions prototypes for the ADC firmware + * library. + ****************************************************************************** + * @attention + * + *

    © COPYRIGHT 2012 STMicroelectronics

    + * + * Licensed under MCD-ST Liberty SW License Agreement V2, (the "License"); + * You may not use this file except in compliance with the License. + * You may obtain a copy of the License at: + * + * http://www.st.com/software_license_agreement_liberty_v2 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, + * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + * + ****************************************************************************** + */ + +/* Define to prevent recursive inclusion -------------------------------------*/ +#ifndef __STM32F10x_ADC_H +#define __STM32F10x_ADC_H + +#ifdef __cplusplus + extern "C" { +#endif + +/* Includes ------------------------------------------------------------------*/ +#include "stm32f10x.h" + +/** @addtogroup STM32F10x_StdPeriph_Driver + * @{ + */ + +/** @addtogroup ADC + * @{ + */ + +/** @defgroup ADC_Exported_Types + * @{ + */ + +/** + * @brief ADC Init structure definition + */ + +typedef struct +{ + uint32_t ADC_Mode; /*!< Configures the ADC to operate in independent or + dual mode. + This parameter can be a value of @ref ADC_mode */ + + FunctionalState ADC_ScanConvMode; /*!< Specifies whether the conversion is performed in + Scan (multichannels) or Single (one channel) mode. + This parameter can be set to ENABLE or DISABLE */ + + FunctionalState ADC_ContinuousConvMode; /*!< Specifies whether the conversion is performed in + Continuous or Single mode. + This parameter can be set to ENABLE or DISABLE. */ + + uint32_t ADC_ExternalTrigConv; /*!< Defines the external trigger used to start the analog + to digital conversion of regular channels. This parameter + can be a value of @ref ADC_external_trigger_sources_for_regular_channels_conversion */ + + uint32_t ADC_DataAlign; /*!< Specifies whether the ADC data alignment is left or right. + This parameter can be a value of @ref ADC_data_align */ + + uint8_t ADC_NbrOfChannel; /*!< Specifies the number of ADC channels that will be converted + using the sequencer for regular channel group. + This parameter must range from 1 to 16. */ +}ADC_InitTypeDef; +/** + * @} + */ + +/** @defgroup ADC_Exported_Constants + * @{ + */ + +#define IS_ADC_ALL_PERIPH(PERIPH) (((PERIPH) == ADC1) || \ + ((PERIPH) == ADC2) || \ + ((PERIPH) == ADC3)) + +#define IS_ADC_DMA_PERIPH(PERIPH) (((PERIPH) == ADC1) || \ + ((PERIPH) == ADC3)) + +/** @defgroup ADC_mode + * @{ + */ + +#define ADC_Mode_Independent ((uint32_t)0x00000000) +#define ADC_Mode_RegInjecSimult ((uint32_t)0x00010000) +#define ADC_Mode_RegSimult_AlterTrig ((uint32_t)0x00020000) +#define ADC_Mode_InjecSimult_FastInterl ((uint32_t)0x00030000) +#define ADC_Mode_InjecSimult_SlowInterl ((uint32_t)0x00040000) +#define ADC_Mode_InjecSimult ((uint32_t)0x00050000) +#define ADC_Mode_RegSimult ((uint32_t)0x00060000) +#define ADC_Mode_FastInterl ((uint32_t)0x00070000) +#define ADC_Mode_SlowInterl ((uint32_t)0x00080000) +#define ADC_Mode_AlterTrig ((uint32_t)0x00090000) + +#define IS_ADC_MODE(MODE) (((MODE) == ADC_Mode_Independent) || \ + ((MODE) == ADC_Mode_RegInjecSimult) || \ + ((MODE) == ADC_Mode_RegSimult_AlterTrig) || \ + ((MODE) == ADC_Mode_InjecSimult_FastInterl) || \ + ((MODE) == ADC_Mode_InjecSimult_SlowInterl) || \ + ((MODE) == ADC_Mode_InjecSimult) || \ + ((MODE) == ADC_Mode_RegSimult) || \ + ((MODE) == ADC_Mode_FastInterl) || \ + ((MODE) == ADC_Mode_SlowInterl) || \ + ((MODE) == ADC_Mode_AlterTrig)) +/** + * @} + */ + +/** @defgroup ADC_external_trigger_sources_for_regular_channels_conversion + * @{ + */ + +#define ADC_ExternalTrigConv_T1_CC1 ((uint32_t)0x00000000) /*!< For ADC1 and ADC2 */ +#define ADC_ExternalTrigConv_T1_CC2 ((uint32_t)0x00020000) /*!< For ADC1 and ADC2 */ +#define ADC_ExternalTrigConv_T2_CC2 ((uint32_t)0x00060000) /*!< For ADC1 and ADC2 */ +#define ADC_ExternalTrigConv_T3_TRGO ((uint32_t)0x00080000) /*!< For ADC1 and ADC2 */ +#define ADC_ExternalTrigConv_T4_CC4 ((uint32_t)0x000A0000) /*!< For ADC1 and ADC2 */ +#define ADC_ExternalTrigConv_Ext_IT11_TIM8_TRGO ((uint32_t)0x000C0000) /*!< For ADC1 and ADC2 */ + +#define ADC_ExternalTrigConv_T1_CC3 ((uint32_t)0x00040000) /*!< For ADC1, ADC2 and ADC3 */ +#define ADC_ExternalTrigConv_None ((uint32_t)0x000E0000) /*!< For ADC1, ADC2 and ADC3 */ + +#define ADC_ExternalTrigConv_T3_CC1 ((uint32_t)0x00000000) /*!< For ADC3 only */ +#define ADC_ExternalTrigConv_T2_CC3 ((uint32_t)0x00020000) /*!< For ADC3 only */ +#define ADC_ExternalTrigConv_T8_CC1 ((uint32_t)0x00060000) /*!< For ADC3 only */ +#define ADC_ExternalTrigConv_T8_TRGO ((uint32_t)0x00080000) /*!< For ADC3 only */ +#define ADC_ExternalTrigConv_T5_CC1 ((uint32_t)0x000A0000) /*!< For ADC3 only */ +#define ADC_ExternalTrigConv_T5_CC3 ((uint32_t)0x000C0000) /*!< For ADC3 only */ + +#define IS_ADC_EXT_TRIG(REGTRIG) (((REGTRIG) == ADC_ExternalTrigConv_T1_CC1) || \ + ((REGTRIG) == ADC_ExternalTrigConv_T1_CC2) || \ + ((REGTRIG) == ADC_ExternalTrigConv_T1_CC3) || \ + ((REGTRIG) == ADC_ExternalTrigConv_T2_CC2) || \ + ((REGTRIG) == ADC_ExternalTrigConv_T3_TRGO) || \ + ((REGTRIG) == ADC_ExternalTrigConv_T4_CC4) || \ + ((REGTRIG) == ADC_ExternalTrigConv_Ext_IT11_TIM8_TRGO) || \ + ((REGTRIG) == ADC_ExternalTrigConv_None) || \ + ((REGTRIG) == ADC_ExternalTrigConv_T3_CC1) || \ + ((REGTRIG) == ADC_ExternalTrigConv_T2_CC3) || \ + ((REGTRIG) == ADC_ExternalTrigConv_T8_CC1) || \ + ((REGTRIG) == ADC_ExternalTrigConv_T8_TRGO) || \ + ((REGTRIG) == ADC_ExternalTrigConv_T5_CC1) || \ + ((REGTRIG) == ADC_ExternalTrigConv_T5_CC3)) +/** + * @} + */ + +/** @defgroup ADC_data_align + * @{ + */ + +#define ADC_DataAlign_Right ((uint32_t)0x00000000) +#define ADC_DataAlign_Left ((uint32_t)0x00000800) +#define IS_ADC_DATA_ALIGN(ALIGN) (((ALIGN) == ADC_DataAlign_Right) || \ + ((ALIGN) == ADC_DataAlign_Left)) +/** + * @} + */ + +/** @defgroup ADC_channels + * @{ + */ + +#define ADC_Channel_0 ((uint8_t)0x00) +#define ADC_Channel_1 ((uint8_t)0x01) +#define ADC_Channel_2 ((uint8_t)0x02) +#define ADC_Channel_3 ((uint8_t)0x03) +#define ADC_Channel_4 ((uint8_t)0x04) +#define ADC_Channel_5 ((uint8_t)0x05) +#define ADC_Channel_6 ((uint8_t)0x06) +#define ADC_Channel_7 ((uint8_t)0x07) +#define ADC_Channel_8 ((uint8_t)0x08) +#define ADC_Channel_9 ((uint8_t)0x09) +#define ADC_Channel_10 ((uint8_t)0x0A) +#define ADC_Channel_11 ((uint8_t)0x0B) +#define ADC_Channel_12 ((uint8_t)0x0C) +#define ADC_Channel_13 ((uint8_t)0x0D) +#define ADC_Channel_14 ((uint8_t)0x0E) +#define ADC_Channel_15 ((uint8_t)0x0F) +#define ADC_Channel_16 ((uint8_t)0x10) +#define ADC_Channel_17 ((uint8_t)0x11) + +#define ADC_Channel_TempSensor ((uint8_t)ADC_Channel_16) +#define ADC_Channel_Vrefint ((uint8_t)ADC_Channel_17) + +#define IS_ADC_CHANNEL(CHANNEL) (((CHANNEL) == ADC_Channel_0) || ((CHANNEL) == ADC_Channel_1) || \ + ((CHANNEL) == ADC_Channel_2) || ((CHANNEL) == ADC_Channel_3) || \ + ((CHANNEL) == ADC_Channel_4) || ((CHANNEL) == ADC_Channel_5) || \ + ((CHANNEL) == ADC_Channel_6) || ((CHANNEL) == ADC_Channel_7) || \ + ((CHANNEL) == ADC_Channel_8) || ((CHANNEL) == ADC_Channel_9) || \ + ((CHANNEL) == ADC_Channel_10) || ((CHANNEL) == ADC_Channel_11) || \ + ((CHANNEL) == ADC_Channel_12) || ((CHANNEL) == ADC_Channel_13) || \ + ((CHANNEL) == ADC_Channel_14) || ((CHANNEL) == ADC_Channel_15) || \ + ((CHANNEL) == ADC_Channel_16) || ((CHANNEL) == ADC_Channel_17)) +/** + * @} + */ + +/** @defgroup ADC_sampling_time + * @{ + */ + +#define ADC_SampleTime_1Cycles5 ((uint8_t)0x00) +#define ADC_SampleTime_7Cycles5 ((uint8_t)0x01) +#define ADC_SampleTime_13Cycles5 ((uint8_t)0x02) +#define ADC_SampleTime_28Cycles5 ((uint8_t)0x03) +#define ADC_SampleTime_41Cycles5 ((uint8_t)0x04) +#define ADC_SampleTime_55Cycles5 ((uint8_t)0x05) +#define ADC_SampleTime_71Cycles5 ((uint8_t)0x06) +#define ADC_SampleTime_239Cycles5 ((uint8_t)0x07) +#define IS_ADC_SAMPLE_TIME(TIME) (((TIME) == ADC_SampleTime_1Cycles5) || \ + ((TIME) == ADC_SampleTime_7Cycles5) || \ + ((TIME) == ADC_SampleTime_13Cycles5) || \ + ((TIME) == ADC_SampleTime_28Cycles5) || \ + ((TIME) == ADC_SampleTime_41Cycles5) || \ + ((TIME) == ADC_SampleTime_55Cycles5) || \ + ((TIME) == ADC_SampleTime_71Cycles5) || \ + ((TIME) == ADC_SampleTime_239Cycles5)) +/** + * @} + */ + +/** @defgroup ADC_external_trigger_sources_for_injected_channels_conversion + * @{ + */ + +#define ADC_ExternalTrigInjecConv_T2_TRGO ((uint32_t)0x00002000) /*!< For ADC1 and ADC2 */ +#define ADC_ExternalTrigInjecConv_T2_CC1 ((uint32_t)0x00003000) /*!< For ADC1 and ADC2 */ +#define ADC_ExternalTrigInjecConv_T3_CC4 ((uint32_t)0x00004000) /*!< For ADC1 and ADC2 */ +#define ADC_ExternalTrigInjecConv_T4_TRGO ((uint32_t)0x00005000) /*!< For ADC1 and ADC2 */ +#define ADC_ExternalTrigInjecConv_Ext_IT15_TIM8_CC4 ((uint32_t)0x00006000) /*!< For ADC1 and ADC2 */ + +#define ADC_ExternalTrigInjecConv_T1_TRGO ((uint32_t)0x00000000) /*!< For ADC1, ADC2 and ADC3 */ +#define ADC_ExternalTrigInjecConv_T1_CC4 ((uint32_t)0x00001000) /*!< For ADC1, ADC2 and ADC3 */ +#define ADC_ExternalTrigInjecConv_None ((uint32_t)0x00007000) /*!< For ADC1, ADC2 and ADC3 */ + +#define ADC_ExternalTrigInjecConv_T4_CC3 ((uint32_t)0x00002000) /*!< For ADC3 only */ +#define ADC_ExternalTrigInjecConv_T8_CC2 ((uint32_t)0x00003000) /*!< For ADC3 only */ +#define ADC_ExternalTrigInjecConv_T8_CC4 ((uint32_t)0x00004000) /*!< For ADC3 only */ +#define ADC_ExternalTrigInjecConv_T5_TRGO ((uint32_t)0x00005000) /*!< For ADC3 only */ +#define ADC_ExternalTrigInjecConv_T5_CC4 ((uint32_t)0x00006000) /*!< For ADC3 only */ + +#define IS_ADC_EXT_INJEC_TRIG(INJTRIG) (((INJTRIG) == ADC_ExternalTrigInjecConv_T1_TRGO) || \ + ((INJTRIG) == ADC_ExternalTrigInjecConv_T1_CC4) || \ + ((INJTRIG) == ADC_ExternalTrigInjecConv_T2_TRGO) || \ + ((INJTRIG) == ADC_ExternalTrigInjecConv_T2_CC1) || \ + ((INJTRIG) == ADC_ExternalTrigInjecConv_T3_CC4) || \ + ((INJTRIG) == ADC_ExternalTrigInjecConv_T4_TRGO) || \ + ((INJTRIG) == ADC_ExternalTrigInjecConv_Ext_IT15_TIM8_CC4) || \ + ((INJTRIG) == ADC_ExternalTrigInjecConv_None) || \ + ((INJTRIG) == ADC_ExternalTrigInjecConv_T4_CC3) || \ + ((INJTRIG) == ADC_ExternalTrigInjecConv_T8_CC2) || \ + ((INJTRIG) == ADC_ExternalTrigInjecConv_T8_CC4) || \ + ((INJTRIG) == ADC_ExternalTrigInjecConv_T5_TRGO) || \ + ((INJTRIG) == ADC_ExternalTrigInjecConv_T5_CC4)) +/** + * @} + */ + +/** @defgroup ADC_injected_channel_selection + * @{ + */ + +#define ADC_InjectedChannel_1 ((uint8_t)0x14) +#define ADC_InjectedChannel_2 ((uint8_t)0x18) +#define ADC_InjectedChannel_3 ((uint8_t)0x1C) +#define ADC_InjectedChannel_4 ((uint8_t)0x20) +#define IS_ADC_INJECTED_CHANNEL(CHANNEL) (((CHANNEL) == ADC_InjectedChannel_1) || \ + ((CHANNEL) == ADC_InjectedChannel_2) || \ + ((CHANNEL) == ADC_InjectedChannel_3) || \ + ((CHANNEL) == ADC_InjectedChannel_4)) +/** + * @} + */ + +/** @defgroup ADC_analog_watchdog_selection + * @{ + */ + +#define ADC_AnalogWatchdog_SingleRegEnable ((uint32_t)0x00800200) +#define ADC_AnalogWatchdog_SingleInjecEnable ((uint32_t)0x00400200) +#define ADC_AnalogWatchdog_SingleRegOrInjecEnable ((uint32_t)0x00C00200) +#define ADC_AnalogWatchdog_AllRegEnable ((uint32_t)0x00800000) +#define ADC_AnalogWatchdog_AllInjecEnable ((uint32_t)0x00400000) +#define ADC_AnalogWatchdog_AllRegAllInjecEnable ((uint32_t)0x00C00000) +#define ADC_AnalogWatchdog_None ((uint32_t)0x00000000) + +#define IS_ADC_ANALOG_WATCHDOG(WATCHDOG) (((WATCHDOG) == ADC_AnalogWatchdog_SingleRegEnable) || \ + ((WATCHDOG) == ADC_AnalogWatchdog_SingleInjecEnable) || \ + ((WATCHDOG) == ADC_AnalogWatchdog_SingleRegOrInjecEnable) || \ + ((WATCHDOG) == ADC_AnalogWatchdog_AllRegEnable) || \ + ((WATCHDOG) == ADC_AnalogWatchdog_AllInjecEnable) || \ + ((WATCHDOG) == ADC_AnalogWatchdog_AllRegAllInjecEnable) || \ + ((WATCHDOG) == ADC_AnalogWatchdog_None)) +/** + * @} + */ + +/** @defgroup ADC_interrupts_definition + * @{ + */ + +#define ADC_IT_EOC ((uint16_t)0x0220) +#define ADC_IT_AWD ((uint16_t)0x0140) +#define ADC_IT_JEOC ((uint16_t)0x0480) + +#define IS_ADC_IT(IT) ((((IT) & (uint16_t)0xF81F) == 0x00) && ((IT) != 0x00)) + +#define IS_ADC_GET_IT(IT) (((IT) == ADC_IT_EOC) || ((IT) == ADC_IT_AWD) || \ + ((IT) == ADC_IT_JEOC)) +/** + * @} + */ + +/** @defgroup ADC_flags_definition + * @{ + */ + +#define ADC_FLAG_AWD ((uint8_t)0x01) +#define ADC_FLAG_EOC ((uint8_t)0x02) +#define ADC_FLAG_JEOC ((uint8_t)0x04) +#define ADC_FLAG_JSTRT ((uint8_t)0x08) +#define ADC_FLAG_STRT ((uint8_t)0x10) +#define IS_ADC_CLEAR_FLAG(FLAG) ((((FLAG) & (uint8_t)0xE0) == 0x00) && ((FLAG) != 0x00)) +#define IS_ADC_GET_FLAG(FLAG) (((FLAG) == ADC_FLAG_AWD) || ((FLAG) == ADC_FLAG_EOC) || \ + ((FLAG) == ADC_FLAG_JEOC) || ((FLAG)== ADC_FLAG_JSTRT) || \ + ((FLAG) == ADC_FLAG_STRT)) +/** + * @} + */ + +/** @defgroup ADC_thresholds + * @{ + */ + +#define IS_ADC_THRESHOLD(THRESHOLD) ((THRESHOLD) <= 0xFFF) + +/** + * @} + */ + +/** @defgroup ADC_injected_offset + * @{ + */ + +#define IS_ADC_OFFSET(OFFSET) ((OFFSET) <= 0xFFF) + +/** + * @} + */ + +/** @defgroup ADC_injected_length + * @{ + */ + +#define IS_ADC_INJECTED_LENGTH(LENGTH) (((LENGTH) >= 0x1) && ((LENGTH) <= 0x4)) + +/** + * @} + */ + +/** @defgroup ADC_injected_rank + * @{ + */ + +#define IS_ADC_INJECTED_RANK(RANK) (((RANK) >= 0x1) && ((RANK) <= 0x4)) + +/** + * @} + */ + + +/** @defgroup ADC_regular_length + * @{ + */ + +#define IS_ADC_REGULAR_LENGTH(LENGTH) (((LENGTH) >= 0x1) && ((LENGTH) <= 0x10)) +/** + * @} + */ + +/** @defgroup ADC_regular_rank + * @{ + */ + +#define IS_ADC_REGULAR_RANK(RANK) (((RANK) >= 0x1) && ((RANK) <= 0x10)) + +/** + * @} + */ + +/** @defgroup ADC_regular_discontinuous_mode_number + * @{ + */ + +#define IS_ADC_REGULAR_DISC_NUMBER(NUMBER) (((NUMBER) >= 0x1) && ((NUMBER) <= 0x8)) + +/** + * @} + */ + +/** + * @} + */ + +/** @defgroup ADC_Exported_Macros + * @{ + */ + +/** + * @} + */ + +/** @defgroup ADC_Exported_Functions + * @{ + */ + +void ADC_DeInit(ADC_TypeDef* ADCx); +void ADC_Init(ADC_TypeDef* ADCx, ADC_InitTypeDef* ADC_InitStruct); +void ADC_StructInit(ADC_InitTypeDef* ADC_InitStruct); +void ADC_Cmd(ADC_TypeDef* ADCx, FunctionalState NewState); +void ADC_DMACmd(ADC_TypeDef* ADCx, FunctionalState NewState); +void ADC_ITConfig(ADC_TypeDef* ADCx, uint16_t ADC_IT, FunctionalState NewState); +void ADC_ResetCalibration(ADC_TypeDef* ADCx); +FlagStatus ADC_GetResetCalibrationStatus(ADC_TypeDef* ADCx); +void ADC_StartCalibration(ADC_TypeDef* ADCx); +FlagStatus ADC_GetCalibrationStatus(ADC_TypeDef* ADCx); +void ADC_SoftwareStartConvCmd(ADC_TypeDef* ADCx, FunctionalState NewState); +FlagStatus ADC_GetSoftwareStartConvStatus(ADC_TypeDef* ADCx); +void ADC_DiscModeChannelCountConfig(ADC_TypeDef* ADCx, uint8_t Number); +void ADC_DiscModeCmd(ADC_TypeDef* ADCx, FunctionalState NewState); +void ADC_RegularChannelConfig(ADC_TypeDef* ADCx, uint8_t ADC_Channel, uint8_t Rank, uint8_t ADC_SampleTime); +void ADC_ExternalTrigConvCmd(ADC_TypeDef* ADCx, FunctionalState NewState); +uint16_t ADC_GetConversionValue(ADC_TypeDef* ADCx); +uint32_t ADC_GetDualModeConversionValue(void); +void ADC_AutoInjectedConvCmd(ADC_TypeDef* ADCx, FunctionalState NewState); +void ADC_InjectedDiscModeCmd(ADC_TypeDef* ADCx, FunctionalState NewState); +void ADC_ExternalTrigInjectedConvConfig(ADC_TypeDef* ADCx, uint32_t ADC_ExternalTrigInjecConv); +void ADC_ExternalTrigInjectedConvCmd(ADC_TypeDef* ADCx, FunctionalState NewState); +void ADC_SoftwareStartInjectedConvCmd(ADC_TypeDef* ADCx, FunctionalState NewState); +FlagStatus ADC_GetSoftwareStartInjectedConvCmdStatus(ADC_TypeDef* ADCx); +void ADC_InjectedChannelConfig(ADC_TypeDef* ADCx, uint8_t ADC_Channel, uint8_t Rank, uint8_t ADC_SampleTime); +void ADC_InjectedSequencerLengthConfig(ADC_TypeDef* ADCx, uint8_t Length); +void ADC_SetInjectedOffset(ADC_TypeDef* ADCx, uint8_t ADC_InjectedChannel, uint16_t Offset); +uint16_t ADC_GetInjectedConversionValue(ADC_TypeDef* ADCx, uint8_t ADC_InjectedChannel); +void ADC_AnalogWatchdogCmd(ADC_TypeDef* ADCx, uint32_t ADC_AnalogWatchdog); +void ADC_AnalogWatchdogThresholdsConfig(ADC_TypeDef* ADCx, uint16_t HighThreshold, uint16_t LowThreshold); +void ADC_AnalogWatchdogSingleChannelConfig(ADC_TypeDef* ADCx, uint8_t ADC_Channel); +void ADC_TempSensorVrefintCmd(FunctionalState NewState); +FlagStatus ADC_GetFlagStatus(ADC_TypeDef* ADCx, uint8_t ADC_FLAG); +void ADC_ClearFlag(ADC_TypeDef* ADCx, uint8_t ADC_FLAG); +ITStatus ADC_GetITStatus(ADC_TypeDef* ADCx, uint16_t ADC_IT); +void ADC_ClearITPendingBit(ADC_TypeDef* ADCx, uint16_t ADC_IT); + +#ifdef __cplusplus +} +#endif + +#endif /*__STM32F10x_ADC_H */ + +/** + * @} + */ + +/** + * @} + */ + +/** + * @} + */ + +/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ diff --git a/Libraries/STM32F10x_StdPeriph_Driver/inc/stm32f10x_bkp.h b/Libraries/STM32F10x_StdPeriph_Driver/inc/stm32f10x_bkp.h new file mode 100644 index 0000000..47e8104 --- /dev/null +++ b/Libraries/STM32F10x_StdPeriph_Driver/inc/stm32f10x_bkp.h @@ -0,0 +1,201 @@ +/** + ****************************************************************************** + * @file stm32f10x_bkp.h + * @author MCD Application Team + * @version V3.6.1 + * @date 05-March-2012 + * @brief This file contains all the functions prototypes for the BKP firmware + * library. + ****************************************************************************** + * @attention + * + *

    © COPYRIGHT 2012 STMicroelectronics

    + * + * Licensed under MCD-ST Liberty SW License Agreement V2, (the "License"); + * You may not use this file except in compliance with the License. + * You may obtain a copy of the License at: + * + * http://www.st.com/software_license_agreement_liberty_v2 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, + * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + * + ****************************************************************************** + */ + +/* Define to prevent recursive inclusion -------------------------------------*/ +#ifndef __STM32F10x_BKP_H +#define __STM32F10x_BKP_H + +#ifdef __cplusplus + extern "C" { +#endif + +/* Includes ------------------------------------------------------------------*/ +#include "stm32f10x.h" + +/** @addtogroup STM32F10x_StdPeriph_Driver + * @{ + */ + +/** @addtogroup BKP + * @{ + */ + +/** @defgroup BKP_Exported_Types + * @{ + */ + +/** + * @} + */ + +/** @defgroup BKP_Exported_Constants + * @{ + */ + +/** @defgroup Tamper_Pin_active_level + * @{ + */ + +#define BKP_TamperPinLevel_High ((uint16_t)0x0000) +#define BKP_TamperPinLevel_Low ((uint16_t)0x0001) +#define IS_BKP_TAMPER_PIN_LEVEL(LEVEL) (((LEVEL) == BKP_TamperPinLevel_High) || \ + ((LEVEL) == BKP_TamperPinLevel_Low)) +/** + * @} + */ + +/** @defgroup RTC_output_source_to_output_on_the_Tamper_pin + * @{ + */ + +#define BKP_RTCOutputSource_None ((uint16_t)0x0000) +#define BKP_RTCOutputSource_CalibClock ((uint16_t)0x0080) +#define BKP_RTCOutputSource_Alarm ((uint16_t)0x0100) +#define BKP_RTCOutputSource_Second ((uint16_t)0x0300) +#define IS_BKP_RTC_OUTPUT_SOURCE(SOURCE) (((SOURCE) == BKP_RTCOutputSource_None) || \ + ((SOURCE) == BKP_RTCOutputSource_CalibClock) || \ + ((SOURCE) == BKP_RTCOutputSource_Alarm) || \ + ((SOURCE) == BKP_RTCOutputSource_Second)) +/** + * @} + */ + +/** @defgroup Data_Backup_Register + * @{ + */ + +#define BKP_DR1 ((uint16_t)0x0004) +#define BKP_DR2 ((uint16_t)0x0008) +#define BKP_DR3 ((uint16_t)0x000C) +#define BKP_DR4 ((uint16_t)0x0010) +#define BKP_DR5 ((uint16_t)0x0014) +#define BKP_DR6 ((uint16_t)0x0018) +#define BKP_DR7 ((uint16_t)0x001C) +#define BKP_DR8 ((uint16_t)0x0020) +#define BKP_DR9 ((uint16_t)0x0024) +#define BKP_DR10 ((uint16_t)0x0028) +#define BKP_DR11 ((uint16_t)0x0040) +#define BKP_DR12 ((uint16_t)0x0044) +#define BKP_DR13 ((uint16_t)0x0048) +#define BKP_DR14 ((uint16_t)0x004C) +#define BKP_DR15 ((uint16_t)0x0050) +#define BKP_DR16 ((uint16_t)0x0054) +#define BKP_DR17 ((uint16_t)0x0058) +#define BKP_DR18 ((uint16_t)0x005C) +#define BKP_DR19 ((uint16_t)0x0060) +#define BKP_DR20 ((uint16_t)0x0064) +#define BKP_DR21 ((uint16_t)0x0068) +#define BKP_DR22 ((uint16_t)0x006C) +#define BKP_DR23 ((uint16_t)0x0070) +#define BKP_DR24 ((uint16_t)0x0074) +#define BKP_DR25 ((uint16_t)0x0078) +#define BKP_DR26 ((uint16_t)0x007C) +#define BKP_DR27 ((uint16_t)0x0080) +#define BKP_DR28 ((uint16_t)0x0084) +#define BKP_DR29 ((uint16_t)0x0088) +#define BKP_DR30 ((uint16_t)0x008C) +#define BKP_DR31 ((uint16_t)0x0090) +#define BKP_DR32 ((uint16_t)0x0094) +#define BKP_DR33 ((uint16_t)0x0098) +#define BKP_DR34 ((uint16_t)0x009C) +#define BKP_DR35 ((uint16_t)0x00A0) +#define BKP_DR36 ((uint16_t)0x00A4) +#define BKP_DR37 ((uint16_t)0x00A8) +#define BKP_DR38 ((uint16_t)0x00AC) +#define BKP_DR39 ((uint16_t)0x00B0) +#define BKP_DR40 ((uint16_t)0x00B4) +#define BKP_DR41 ((uint16_t)0x00B8) +#define BKP_DR42 ((uint16_t)0x00BC) + +#define IS_BKP_DR(DR) (((DR) == BKP_DR1) || ((DR) == BKP_DR2) || ((DR) == BKP_DR3) || \ + ((DR) == BKP_DR4) || ((DR) == BKP_DR5) || ((DR) == BKP_DR6) || \ + ((DR) == BKP_DR7) || ((DR) == BKP_DR8) || ((DR) == BKP_DR9) || \ + ((DR) == BKP_DR10) || ((DR) == BKP_DR11) || ((DR) == BKP_DR12) || \ + ((DR) == BKP_DR13) || ((DR) == BKP_DR14) || ((DR) == BKP_DR15) || \ + ((DR) == BKP_DR16) || ((DR) == BKP_DR17) || ((DR) == BKP_DR18) || \ + ((DR) == BKP_DR19) || ((DR) == BKP_DR20) || ((DR) == BKP_DR21) || \ + ((DR) == BKP_DR22) || ((DR) == BKP_DR23) || ((DR) == BKP_DR24) || \ + ((DR) == BKP_DR25) || ((DR) == BKP_DR26) || ((DR) == BKP_DR27) || \ + ((DR) == BKP_DR28) || ((DR) == BKP_DR29) || ((DR) == BKP_DR30) || \ + ((DR) == BKP_DR31) || ((DR) == BKP_DR32) || ((DR) == BKP_DR33) || \ + ((DR) == BKP_DR34) || ((DR) == BKP_DR35) || ((DR) == BKP_DR36) || \ + ((DR) == BKP_DR37) || ((DR) == BKP_DR38) || ((DR) == BKP_DR39) || \ + ((DR) == BKP_DR40) || ((DR) == BKP_DR41) || ((DR) == BKP_DR42)) + +#define IS_BKP_CALIBRATION_VALUE(VALUE) ((VALUE) <= 0x7F) +/** + * @} + */ + +/** + * @} + */ + +/** @defgroup BKP_Exported_Macros + * @{ + */ + +/** + * @} + */ + +/** @defgroup BKP_Exported_Functions + * @{ + */ + +void BKP_DeInit(void); +void BKP_TamperPinLevelConfig(uint16_t BKP_TamperPinLevel); +void BKP_TamperPinCmd(FunctionalState NewState); +void BKP_ITConfig(FunctionalState NewState); +void BKP_RTCOutputConfig(uint16_t BKP_RTCOutputSource); +void BKP_SetRTCCalibrationValue(uint8_t CalibrationValue); +void BKP_WriteBackupRegister(uint16_t BKP_DR, uint16_t Data); +uint16_t BKP_ReadBackupRegister(uint16_t BKP_DR); +FlagStatus BKP_GetFlagStatus(void); +void BKP_ClearFlag(void); +ITStatus BKP_GetITStatus(void); +void BKP_ClearITPendingBit(void); + +#ifdef __cplusplus +} +#endif + +#endif /* __STM32F10x_BKP_H */ +/** + * @} + */ + +/** + * @} + */ + +/** + * @} + */ + +/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ diff --git a/Libraries/STM32F10x_StdPeriph_Driver/inc/stm32f10x_can.h b/Libraries/STM32F10x_StdPeriph_Driver/inc/stm32f10x_can.h new file mode 100644 index 0000000..6b41e40 --- /dev/null +++ b/Libraries/STM32F10x_StdPeriph_Driver/inc/stm32f10x_can.h @@ -0,0 +1,703 @@ +/** + ****************************************************************************** + * @file stm32f10x_can.h + * @author MCD Application Team + * @version V3.6.1 + * @date 05-March-2012 + * @brief This file contains all the functions prototypes for the CAN firmware + * library. + ****************************************************************************** + * @attention + * + *

    © COPYRIGHT 2012 STMicroelectronics

    + * + * Licensed under MCD-ST Liberty SW License Agreement V2, (the "License"); + * You may not use this file except in compliance with the License. + * You may obtain a copy of the License at: + * + * http://www.st.com/software_license_agreement_liberty_v2 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, + * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + * + ****************************************************************************** + */ + +/* Define to prevent recursive inclusion -------------------------------------*/ +#ifndef __STM32F10x_CAN_H +#define __STM32F10x_CAN_H + +#ifdef __cplusplus + extern "C" { +#endif + +/* Includes ------------------------------------------------------------------*/ +#include "stm32f10x.h" + +/** @addtogroup STM32F10x_StdPeriph_Driver + * @{ + */ + +/** @addtogroup CAN + * @{ + */ + +/** @defgroup CAN_Exported_Types + * @{ + */ + +#define IS_CAN_ALL_PERIPH(PERIPH) (((PERIPH) == CAN1) || \ + ((PERIPH) == CAN2)) + +/** + * @brief CAN init structure definition + */ + +typedef struct +{ + uint16_t CAN_Prescaler; /*!< Specifies the length of a time quantum. + It ranges from 1 to 1024. */ + + uint8_t CAN_Mode; /*!< Specifies the CAN operating mode. + This parameter can be a value of + @ref CAN_operating_mode */ + + uint8_t CAN_SJW; /*!< Specifies the maximum number of time quanta + the CAN hardware is allowed to lengthen or + shorten a bit to perform resynchronization. + This parameter can be a value of + @ref CAN_synchronisation_jump_width */ + + uint8_t CAN_BS1; /*!< Specifies the number of time quanta in Bit + Segment 1. This parameter can be a value of + @ref CAN_time_quantum_in_bit_segment_1 */ + + uint8_t CAN_BS2; /*!< Specifies the number of time quanta in Bit + Segment 2. + This parameter can be a value of + @ref CAN_time_quantum_in_bit_segment_2 */ + + FunctionalState CAN_TTCM; /*!< Enable or disable the time triggered + communication mode. This parameter can be set + either to ENABLE or DISABLE. */ + + FunctionalState CAN_ABOM; /*!< Enable or disable the automatic bus-off + management. This parameter can be set either + to ENABLE or DISABLE. */ + + FunctionalState CAN_AWUM; /*!< Enable or disable the automatic wake-up mode. + This parameter can be set either to ENABLE or + DISABLE. */ + + FunctionalState CAN_NART; /*!< Enable or disable the no-automatic + retransmission mode. This parameter can be + set either to ENABLE or DISABLE. */ + + FunctionalState CAN_RFLM; /*!< Enable or disable the Receive FIFO Locked mode. + This parameter can be set either to ENABLE + or DISABLE. */ + + FunctionalState CAN_TXFP; /*!< Enable or disable the transmit FIFO priority. + This parameter can be set either to ENABLE + or DISABLE. */ +} CAN_InitTypeDef; + +/** + * @brief CAN filter init structure definition + */ + +typedef struct +{ + uint16_t CAN_FilterIdHigh; /*!< Specifies the filter identification number (MSBs for a 32-bit + configuration, first one for a 16-bit configuration). + This parameter can be a value between 0x0000 and 0xFFFF */ + + uint16_t CAN_FilterIdLow; /*!< Specifies the filter identification number (LSBs for a 32-bit + configuration, second one for a 16-bit configuration). + This parameter can be a value between 0x0000 and 0xFFFF */ + + uint16_t CAN_FilterMaskIdHigh; /*!< Specifies the filter mask number or identification number, + according to the mode (MSBs for a 32-bit configuration, + first one for a 16-bit configuration). + This parameter can be a value between 0x0000 and 0xFFFF */ + + uint16_t CAN_FilterMaskIdLow; /*!< Specifies the filter mask number or identification number, + according to the mode (LSBs for a 32-bit configuration, + second one for a 16-bit configuration). + This parameter can be a value between 0x0000 and 0xFFFF */ + + uint16_t CAN_FilterFIFOAssignment; /*!< Specifies the FIFO (0 or 1) which will be assigned to the filter. + This parameter can be a value of @ref CAN_filter_FIFO */ + + uint8_t CAN_FilterNumber; /*!< Specifies the filter which will be initialized. It ranges from 0 to 13. */ + + uint8_t CAN_FilterMode; /*!< Specifies the filter mode to be initialized. + This parameter can be a value of @ref CAN_filter_mode */ + + uint8_t CAN_FilterScale; /*!< Specifies the filter scale. + This parameter can be a value of @ref CAN_filter_scale */ + + FunctionalState CAN_FilterActivation; /*!< Enable or disable the filter. + This parameter can be set either to ENABLE or DISABLE. */ +} CAN_FilterInitTypeDef; + +/** + * @brief CAN Tx message structure definition + */ + +typedef struct +{ + uint32_t StdId; /*!< Specifies the standard identifier. + This parameter can be a value between 0 to 0x7FF. */ + + uint32_t ExtId; /*!< Specifies the extended identifier. + This parameter can be a value between 0 to 0x1FFFFFFF. */ + + uint8_t IDE; /*!< Specifies the type of identifier for the message that + will be transmitted. This parameter can be a value + of @ref CAN_identifier_type */ + + uint8_t RTR; /*!< Specifies the type of frame for the message that will + be transmitted. This parameter can be a value of + @ref CAN_remote_transmission_request */ + + uint8_t DLC; /*!< Specifies the length of the frame that will be + transmitted. This parameter can be a value between + 0 to 8 */ + + uint8_t Data[8]; /*!< Contains the data to be transmitted. It ranges from 0 + to 0xFF. */ +} CanTxMsg; + +/** + * @brief CAN Rx message structure definition + */ + +typedef struct +{ + uint32_t StdId; /*!< Specifies the standard identifier. + This parameter can be a value between 0 to 0x7FF. */ + + uint32_t ExtId; /*!< Specifies the extended identifier. + This parameter can be a value between 0 to 0x1FFFFFFF. */ + + uint8_t IDE; /*!< Specifies the type of identifier for the message that + will be received. This parameter can be a value of + @ref CAN_identifier_type */ + + uint8_t RTR; /*!< Specifies the type of frame for the received message. + This parameter can be a value of + @ref CAN_remote_transmission_request */ + + uint8_t DLC; /*!< Specifies the length of the frame that will be received. + This parameter can be a value between 0 to 8 */ + + uint8_t Data[8]; /*!< Contains the data to be received. It ranges from 0 to + 0xFF. */ + + uint8_t FMI; /*!< Specifies the index of the filter the message stored in + the mailbox passes through. This parameter can be a + value between 0 to 0xFF */ +} CanRxMsg; + +/** + * @} + */ + +/** @defgroup CAN_Exported_Constants + * @{ + */ + +/** @defgroup CAN_sleep_constants + * @{ + */ + +#define CAN_InitStatus_Failed ((uint8_t)0x00) /*!< CAN initialization failed */ +#define CAN_InitStatus_Success ((uint8_t)0x01) /*!< CAN initialization OK */ + +/** + * @} + */ + +/** @defgroup CAN_Mode + * @{ + */ + +#define CAN_Mode_Normal ((uint8_t)0x00) /*!< normal mode */ +#define CAN_Mode_LoopBack ((uint8_t)0x01) /*!< loopback mode */ +#define CAN_Mode_Silent ((uint8_t)0x02) /*!< silent mode */ +#define CAN_Mode_Silent_LoopBack ((uint8_t)0x03) /*!< loopback combined with silent mode */ + +#define IS_CAN_MODE(MODE) (((MODE) == CAN_Mode_Normal) || \ + ((MODE) == CAN_Mode_LoopBack)|| \ + ((MODE) == CAN_Mode_Silent) || \ + ((MODE) == CAN_Mode_Silent_LoopBack)) +/** + * @} + */ + + +/** + * @defgroup CAN_Operating_Mode + * @{ + */ +#define CAN_OperatingMode_Initialization ((uint8_t)0x00) /*!< Initialization mode */ +#define CAN_OperatingMode_Normal ((uint8_t)0x01) /*!< Normal mode */ +#define CAN_OperatingMode_Sleep ((uint8_t)0x02) /*!< sleep mode */ + + +#define IS_CAN_OPERATING_MODE(MODE) (((MODE) == CAN_OperatingMode_Initialization) ||\ + ((MODE) == CAN_OperatingMode_Normal)|| \ + ((MODE) == CAN_OperatingMode_Sleep)) +/** + * @} + */ + +/** + * @defgroup CAN_Mode_Status + * @{ + */ + +#define CAN_ModeStatus_Failed ((uint8_t)0x00) /*!< CAN entering the specific mode failed */ +#define CAN_ModeStatus_Success ((uint8_t)!CAN_ModeStatus_Failed) /*!< CAN entering the specific mode Succeed */ + + +/** + * @} + */ + +/** @defgroup CAN_synchronisation_jump_width + * @{ + */ + +#define CAN_SJW_1tq ((uint8_t)0x00) /*!< 1 time quantum */ +#define CAN_SJW_2tq ((uint8_t)0x01) /*!< 2 time quantum */ +#define CAN_SJW_3tq ((uint8_t)0x02) /*!< 3 time quantum */ +#define CAN_SJW_4tq ((uint8_t)0x03) /*!< 4 time quantum */ + +#define IS_CAN_SJW(SJW) (((SJW) == CAN_SJW_1tq) || ((SJW) == CAN_SJW_2tq)|| \ + ((SJW) == CAN_SJW_3tq) || ((SJW) == CAN_SJW_4tq)) +/** + * @} + */ + +/** @defgroup CAN_time_quantum_in_bit_segment_1 + * @{ + */ + +#define CAN_BS1_1tq ((uint8_t)0x00) /*!< 1 time quantum */ +#define CAN_BS1_2tq ((uint8_t)0x01) /*!< 2 time quantum */ +#define CAN_BS1_3tq ((uint8_t)0x02) /*!< 3 time quantum */ +#define CAN_BS1_4tq ((uint8_t)0x03) /*!< 4 time quantum */ +#define CAN_BS1_5tq ((uint8_t)0x04) /*!< 5 time quantum */ +#define CAN_BS1_6tq ((uint8_t)0x05) /*!< 6 time quantum */ +#define CAN_BS1_7tq ((uint8_t)0x06) /*!< 7 time quantum */ +#define CAN_BS1_8tq ((uint8_t)0x07) /*!< 8 time quantum */ +#define CAN_BS1_9tq ((uint8_t)0x08) /*!< 9 time quantum */ +#define CAN_BS1_10tq ((uint8_t)0x09) /*!< 10 time quantum */ +#define CAN_BS1_11tq ((uint8_t)0x0A) /*!< 11 time quantum */ +#define CAN_BS1_12tq ((uint8_t)0x0B) /*!< 12 time quantum */ +#define CAN_BS1_13tq ((uint8_t)0x0C) /*!< 13 time quantum */ +#define CAN_BS1_14tq ((uint8_t)0x0D) /*!< 14 time quantum */ +#define CAN_BS1_15tq ((uint8_t)0x0E) /*!< 15 time quantum */ +#define CAN_BS1_16tq ((uint8_t)0x0F) /*!< 16 time quantum */ + +#define IS_CAN_BS1(BS1) ((BS1) <= CAN_BS1_16tq) +/** + * @} + */ + +/** @defgroup CAN_time_quantum_in_bit_segment_2 + * @{ + */ + +#define CAN_BS2_1tq ((uint8_t)0x00) /*!< 1 time quantum */ +#define CAN_BS2_2tq ((uint8_t)0x01) /*!< 2 time quantum */ +#define CAN_BS2_3tq ((uint8_t)0x02) /*!< 3 time quantum */ +#define CAN_BS2_4tq ((uint8_t)0x03) /*!< 4 time quantum */ +#define CAN_BS2_5tq ((uint8_t)0x04) /*!< 5 time quantum */ +#define CAN_BS2_6tq ((uint8_t)0x05) /*!< 6 time quantum */ +#define CAN_BS2_7tq ((uint8_t)0x06) /*!< 7 time quantum */ +#define CAN_BS2_8tq ((uint8_t)0x07) /*!< 8 time quantum */ + +#define IS_CAN_BS2(BS2) ((BS2) <= CAN_BS2_8tq) + +/** + * @} + */ + +/** @defgroup CAN_clock_prescaler + * @{ + */ + +#define IS_CAN_PRESCALER(PRESCALER) (((PRESCALER) >= 1) && ((PRESCALER) <= 1024)) + +/** + * @} + */ + +/** @defgroup CAN_filter_number + * @{ + */ +#ifndef STM32F10X_CL + #define IS_CAN_FILTER_NUMBER(NUMBER) ((NUMBER) <= 13) +#else + #define IS_CAN_FILTER_NUMBER(NUMBER) ((NUMBER) <= 27) +#endif /* STM32F10X_CL */ +/** + * @} + */ + +/** @defgroup CAN_filter_mode + * @{ + */ + +#define CAN_FilterMode_IdMask ((uint8_t)0x00) /*!< identifier/mask mode */ +#define CAN_FilterMode_IdList ((uint8_t)0x01) /*!< identifier list mode */ + +#define IS_CAN_FILTER_MODE(MODE) (((MODE) == CAN_FilterMode_IdMask) || \ + ((MODE) == CAN_FilterMode_IdList)) +/** + * @} + */ + +/** @defgroup CAN_filter_scale + * @{ + */ + +#define CAN_FilterScale_16bit ((uint8_t)0x00) /*!< Two 16-bit filters */ +#define CAN_FilterScale_32bit ((uint8_t)0x01) /*!< One 32-bit filter */ + +#define IS_CAN_FILTER_SCALE(SCALE) (((SCALE) == CAN_FilterScale_16bit) || \ + ((SCALE) == CAN_FilterScale_32bit)) + +/** + * @} + */ + +/** @defgroup CAN_filter_FIFO + * @{ + */ + +#define CAN_Filter_FIFO0 ((uint8_t)0x00) /*!< Filter FIFO 0 assignment for filter x */ +#define CAN_Filter_FIFO1 ((uint8_t)0x01) /*!< Filter FIFO 1 assignment for filter x */ +#define IS_CAN_FILTER_FIFO(FIFO) (((FIFO) == CAN_FilterFIFO0) || \ + ((FIFO) == CAN_FilterFIFO1)) +/** + * @} + */ + +/** @defgroup Start_bank_filter_for_slave_CAN + * @{ + */ +#define IS_CAN_BANKNUMBER(BANKNUMBER) (((BANKNUMBER) >= 1) && ((BANKNUMBER) <= 27)) +/** + * @} + */ + +/** @defgroup CAN_Tx + * @{ + */ + +#define IS_CAN_TRANSMITMAILBOX(TRANSMITMAILBOX) ((TRANSMITMAILBOX) <= ((uint8_t)0x02)) +#define IS_CAN_STDID(STDID) ((STDID) <= ((uint32_t)0x7FF)) +#define IS_CAN_EXTID(EXTID) ((EXTID) <= ((uint32_t)0x1FFFFFFF)) +#define IS_CAN_DLC(DLC) ((DLC) <= ((uint8_t)0x08)) + +/** + * @} + */ + +/** @defgroup CAN_identifier_type + * @{ + */ + +#define CAN_Id_Standard ((uint32_t)0x00000000) /*!< Standard Id */ +#define CAN_Id_Extended ((uint32_t)0x00000004) /*!< Extended Id */ +#define IS_CAN_IDTYPE(IDTYPE) (((IDTYPE) == CAN_Id_Standard) || \ + ((IDTYPE) == CAN_Id_Extended)) +/** + * @} + */ + +/** @defgroup CAN_remote_transmission_request + * @{ + */ + +#define CAN_RTR_Data ((uint32_t)0x00000000) /*!< Data frame */ +#define CAN_RTR_Remote ((uint32_t)0x00000002) /*!< Remote frame */ +#define IS_CAN_RTR(RTR) (((RTR) == CAN_RTR_Data) || ((RTR) == CAN_RTR_Remote)) + +/** + * @} + */ + +/** @defgroup CAN_transmit_constants + * @{ + */ + +#define CAN_TxStatus_Failed ((uint8_t)0x00)/*!< CAN transmission failed */ +#define CAN_TxStatus_Ok ((uint8_t)0x01) /*!< CAN transmission succeeded */ +#define CAN_TxStatus_Pending ((uint8_t)0x02) /*!< CAN transmission pending */ +#define CAN_TxStatus_NoMailBox ((uint8_t)0x04) /*!< CAN cell did not provide an empty mailbox */ + +/** + * @} + */ + +/** @defgroup CAN_receive_FIFO_number_constants + * @{ + */ + +#define CAN_FIFO0 ((uint8_t)0x00) /*!< CAN FIFO 0 used to receive */ +#define CAN_FIFO1 ((uint8_t)0x01) /*!< CAN FIFO 1 used to receive */ + +#define IS_CAN_FIFO(FIFO) (((FIFO) == CAN_FIFO0) || ((FIFO) == CAN_FIFO1)) + +/** + * @} + */ + +/** @defgroup CAN_sleep_constants + * @{ + */ + +#define CAN_Sleep_Failed ((uint8_t)0x00) /*!< CAN did not enter the sleep mode */ +#define CAN_Sleep_Ok ((uint8_t)0x01) /*!< CAN entered the sleep mode */ + +/** + * @} + */ + +/** @defgroup CAN_wake_up_constants + * @{ + */ + +#define CAN_WakeUp_Failed ((uint8_t)0x00) /*!< CAN did not leave the sleep mode */ +#define CAN_WakeUp_Ok ((uint8_t)0x01) /*!< CAN leaved the sleep mode */ + +/** + * @} + */ + +/** + * @defgroup CAN_Error_Code_constants + * @{ + */ + +#define CAN_ErrorCode_NoErr ((uint8_t)0x00) /*!< No Error */ +#define CAN_ErrorCode_StuffErr ((uint8_t)0x10) /*!< Stuff Error */ +#define CAN_ErrorCode_FormErr ((uint8_t)0x20) /*!< Form Error */ +#define CAN_ErrorCode_ACKErr ((uint8_t)0x30) /*!< Acknowledgment Error */ +#define CAN_ErrorCode_BitRecessiveErr ((uint8_t)0x40) /*!< Bit Recessive Error */ +#define CAN_ErrorCode_BitDominantErr ((uint8_t)0x50) /*!< Bit Dominant Error */ +#define CAN_ErrorCode_CRCErr ((uint8_t)0x60) /*!< CRC Error */ +#define CAN_ErrorCode_SoftwareSetErr ((uint8_t)0x70) /*!< Software Set Error */ + + +/** + * @} + */ + +/** @defgroup CAN_flags + * @{ + */ +/* If the flag is 0x3XXXXXXX, it means that it can be used with CAN_GetFlagStatus() + and CAN_ClearFlag() functions. */ +/* If the flag is 0x1XXXXXXX, it means that it can only be used with CAN_GetFlagStatus() function. */ + +/* Transmit Flags */ +#define CAN_FLAG_RQCP0 ((uint32_t)0x38000001) /*!< Request MailBox0 Flag */ +#define CAN_FLAG_RQCP1 ((uint32_t)0x38000100) /*!< Request MailBox1 Flag */ +#define CAN_FLAG_RQCP2 ((uint32_t)0x38010000) /*!< Request MailBox2 Flag */ + +/* Receive Flags */ +#define CAN_FLAG_FMP0 ((uint32_t)0x12000003) /*!< FIFO 0 Message Pending Flag */ +#define CAN_FLAG_FF0 ((uint32_t)0x32000008) /*!< FIFO 0 Full Flag */ +#define CAN_FLAG_FOV0 ((uint32_t)0x32000010) /*!< FIFO 0 Overrun Flag */ +#define CAN_FLAG_FMP1 ((uint32_t)0x14000003) /*!< FIFO 1 Message Pending Flag */ +#define CAN_FLAG_FF1 ((uint32_t)0x34000008) /*!< FIFO 1 Full Flag */ +#define CAN_FLAG_FOV1 ((uint32_t)0x34000010) /*!< FIFO 1 Overrun Flag */ + +/* Operating Mode Flags */ +#define CAN_FLAG_WKU ((uint32_t)0x31000008) /*!< Wake up Flag */ +#define CAN_FLAG_SLAK ((uint32_t)0x31000012) /*!< Sleep acknowledge Flag */ +/* Note: When SLAK intterupt is disabled (SLKIE=0), no polling on SLAKI is possible. + In this case the SLAK bit can be polled.*/ + +/* Error Flags */ +#define CAN_FLAG_EWG ((uint32_t)0x10F00001) /*!< Error Warning Flag */ +#define CAN_FLAG_EPV ((uint32_t)0x10F00002) /*!< Error Passive Flag */ +#define CAN_FLAG_BOF ((uint32_t)0x10F00004) /*!< Bus-Off Flag */ +#define CAN_FLAG_LEC ((uint32_t)0x30F00070) /*!< Last error code Flag */ + +#define IS_CAN_GET_FLAG(FLAG) (((FLAG) == CAN_FLAG_LEC) || ((FLAG) == CAN_FLAG_BOF) || \ + ((FLAG) == CAN_FLAG_EPV) || ((FLAG) == CAN_FLAG_EWG) || \ + ((FLAG) == CAN_FLAG_WKU) || ((FLAG) == CAN_FLAG_FOV0) || \ + ((FLAG) == CAN_FLAG_FF0) || ((FLAG) == CAN_FLAG_FMP0) || \ + ((FLAG) == CAN_FLAG_FOV1) || ((FLAG) == CAN_FLAG_FF1) || \ + ((FLAG) == CAN_FLAG_FMP1) || ((FLAG) == CAN_FLAG_RQCP2) || \ + ((FLAG) == CAN_FLAG_RQCP1)|| ((FLAG) == CAN_FLAG_RQCP0) || \ + ((FLAG) == CAN_FLAG_SLAK )) + +#define IS_CAN_CLEAR_FLAG(FLAG)(((FLAG) == CAN_FLAG_LEC) || ((FLAG) == CAN_FLAG_RQCP2) || \ + ((FLAG) == CAN_FLAG_RQCP1) || ((FLAG) == CAN_FLAG_RQCP0) || \ + ((FLAG) == CAN_FLAG_FF0) || ((FLAG) == CAN_FLAG_FOV0) ||\ + ((FLAG) == CAN_FLAG_FF1) || ((FLAG) == CAN_FLAG_FOV1) || \ + ((FLAG) == CAN_FLAG_WKU) || ((FLAG) == CAN_FLAG_SLAK)) +/** + * @} + */ + + +/** @defgroup CAN_interrupts + * @{ + */ + + + +#define CAN_IT_TME ((uint32_t)0x00000001) /*!< Transmit mailbox empty Interrupt*/ + +/* Receive Interrupts */ +#define CAN_IT_FMP0 ((uint32_t)0x00000002) /*!< FIFO 0 message pending Interrupt*/ +#define CAN_IT_FF0 ((uint32_t)0x00000004) /*!< FIFO 0 full Interrupt*/ +#define CAN_IT_FOV0 ((uint32_t)0x00000008) /*!< FIFO 0 overrun Interrupt*/ +#define CAN_IT_FMP1 ((uint32_t)0x00000010) /*!< FIFO 1 message pending Interrupt*/ +#define CAN_IT_FF1 ((uint32_t)0x00000020) /*!< FIFO 1 full Interrupt*/ +#define CAN_IT_FOV1 ((uint32_t)0x00000040) /*!< FIFO 1 overrun Interrupt*/ + +/* Operating Mode Interrupts */ +#define CAN_IT_WKU ((uint32_t)0x00010000) /*!< Wake-up Interrupt*/ +#define CAN_IT_SLK ((uint32_t)0x00020000) /*!< Sleep acknowledge Interrupt*/ + +/* Error Interrupts */ +#define CAN_IT_EWG ((uint32_t)0x00000100) /*!< Error warning Interrupt*/ +#define CAN_IT_EPV ((uint32_t)0x00000200) /*!< Error passive Interrupt*/ +#define CAN_IT_BOF ((uint32_t)0x00000400) /*!< Bus-off Interrupt*/ +#define CAN_IT_LEC ((uint32_t)0x00000800) /*!< Last error code Interrupt*/ +#define CAN_IT_ERR ((uint32_t)0x00008000) /*!< Error Interrupt*/ + +/* Flags named as Interrupts : kept only for FW compatibility */ +#define CAN_IT_RQCP0 CAN_IT_TME +#define CAN_IT_RQCP1 CAN_IT_TME +#define CAN_IT_RQCP2 CAN_IT_TME + + +#define IS_CAN_IT(IT) (((IT) == CAN_IT_TME) || ((IT) == CAN_IT_FMP0) ||\ + ((IT) == CAN_IT_FF0) || ((IT) == CAN_IT_FOV0) ||\ + ((IT) == CAN_IT_FMP1) || ((IT) == CAN_IT_FF1) ||\ + ((IT) == CAN_IT_FOV1) || ((IT) == CAN_IT_EWG) ||\ + ((IT) == CAN_IT_EPV) || ((IT) == CAN_IT_BOF) ||\ + ((IT) == CAN_IT_LEC) || ((IT) == CAN_IT_ERR) ||\ + ((IT) == CAN_IT_WKU) || ((IT) == CAN_IT_SLK)) + +#define IS_CAN_CLEAR_IT(IT) (((IT) == CAN_IT_TME) || ((IT) == CAN_IT_FF0) ||\ + ((IT) == CAN_IT_FOV0)|| ((IT) == CAN_IT_FF1) ||\ + ((IT) == CAN_IT_FOV1)|| ((IT) == CAN_IT_EWG) ||\ + ((IT) == CAN_IT_EPV) || ((IT) == CAN_IT_BOF) ||\ + ((IT) == CAN_IT_LEC) || ((IT) == CAN_IT_ERR) ||\ + ((IT) == CAN_IT_WKU) || ((IT) == CAN_IT_SLK)) + +/** + * @} + */ + +/** @defgroup CAN_Legacy + * @{ + */ +#define CANINITFAILED CAN_InitStatus_Failed +#define CANINITOK CAN_InitStatus_Success +#define CAN_FilterFIFO0 CAN_Filter_FIFO0 +#define CAN_FilterFIFO1 CAN_Filter_FIFO1 +#define CAN_ID_STD CAN_Id_Standard +#define CAN_ID_EXT CAN_Id_Extended +#define CAN_RTR_DATA CAN_RTR_Data +#define CAN_RTR_REMOTE CAN_RTR_Remote +#define CANTXFAILE CAN_TxStatus_Failed +#define CANTXOK CAN_TxStatus_Ok +#define CANTXPENDING CAN_TxStatus_Pending +#define CAN_NO_MB CAN_TxStatus_NoMailBox +#define CANSLEEPFAILED CAN_Sleep_Failed +#define CANSLEEPOK CAN_Sleep_Ok +#define CANWAKEUPFAILED CAN_WakeUp_Failed +#define CANWAKEUPOK CAN_WakeUp_Ok + +/** + * @} + */ + +/** + * @} + */ + +/** @defgroup CAN_Exported_Macros + * @{ + */ + +/** + * @} + */ + +/** @defgroup CAN_Exported_Functions + * @{ + */ +/* Function used to set the CAN configuration to the default reset state *****/ +void CAN_DeInit(CAN_TypeDef* CANx); + +/* Initialization and Configuration functions *********************************/ +uint8_t CAN_Init(CAN_TypeDef* CANx, CAN_InitTypeDef* CAN_InitStruct); +void CAN_FilterInit(CAN_FilterInitTypeDef* CAN_FilterInitStruct); +void CAN_StructInit(CAN_InitTypeDef* CAN_InitStruct); +void CAN_SlaveStartBank(uint8_t CAN_BankNumber); +void CAN_DBGFreeze(CAN_TypeDef* CANx, FunctionalState NewState); +void CAN_TTComModeCmd(CAN_TypeDef* CANx, FunctionalState NewState); + +/* Transmit functions *********************************************************/ +uint8_t CAN_Transmit(CAN_TypeDef* CANx, CanTxMsg* TxMessage); +uint8_t CAN_TransmitStatus(CAN_TypeDef* CANx, uint8_t TransmitMailbox); +void CAN_CancelTransmit(CAN_TypeDef* CANx, uint8_t Mailbox); + +/* Receive functions **********************************************************/ +void CAN_Receive(CAN_TypeDef* CANx, uint8_t FIFONumber, CanRxMsg* RxMessage); +void CAN_FIFORelease(CAN_TypeDef* CANx, uint8_t FIFONumber); +uint8_t CAN_MessagePending(CAN_TypeDef* CANx, uint8_t FIFONumber); + + +/* Operation modes functions **************************************************/ +uint8_t CAN_OperatingModeRequest(CAN_TypeDef* CANx, uint8_t CAN_OperatingMode); +uint8_t CAN_Sleep(CAN_TypeDef* CANx); +uint8_t CAN_WakeUp(CAN_TypeDef* CANx); + +/* Error management functions *************************************************/ +uint8_t CAN_GetLastErrorCode(CAN_TypeDef* CANx); +uint8_t CAN_GetReceiveErrorCounter(CAN_TypeDef* CANx); +uint8_t CAN_GetLSBTransmitErrorCounter(CAN_TypeDef* CANx); + +/* Interrupts and flags management functions **********************************/ +void CAN_ITConfig(CAN_TypeDef* CANx, uint32_t CAN_IT, FunctionalState NewState); +FlagStatus CAN_GetFlagStatus(CAN_TypeDef* CANx, uint32_t CAN_FLAG); +void CAN_ClearFlag(CAN_TypeDef* CANx, uint32_t CAN_FLAG); +ITStatus CAN_GetITStatus(CAN_TypeDef* CANx, uint32_t CAN_IT); +void CAN_ClearITPendingBit(CAN_TypeDef* CANx, uint32_t CAN_IT); + +#ifdef __cplusplus +} +#endif + +#endif /* __STM32F10x_CAN_H */ +/** + * @} + */ + +/** + * @} + */ + +/** + * @} + */ + +/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ diff --git a/Libraries/STM32F10x_StdPeriph_Driver/inc/stm32f10x_cec.h b/Libraries/STM32F10x_StdPeriph_Driver/inc/stm32f10x_cec.h new file mode 100644 index 0000000..7adc125 --- /dev/null +++ b/Libraries/STM32F10x_StdPeriph_Driver/inc/stm32f10x_cec.h @@ -0,0 +1,216 @@ +/** + ****************************************************************************** + * @file stm32f10x_cec.h + * @author MCD Application Team + * @version V3.6.1 + * @date 05-March-2012 + * @brief This file contains all the functions prototypes for the CEC firmware + * library. + ****************************************************************************** + * @attention + * + *

    © COPYRIGHT 2012 STMicroelectronics

    + * + * Licensed under MCD-ST Liberty SW License Agreement V2, (the "License"); + * You may not use this file except in compliance with the License. + * You may obtain a copy of the License at: + * + * http://www.st.com/software_license_agreement_liberty_v2 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, + * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + * + ****************************************************************************** + */ + +/* Define to prevent recursive inclusion -------------------------------------*/ +#ifndef __STM32F10x_CEC_H +#define __STM32F10x_CEC_H + +#ifdef __cplusplus + extern "C" { +#endif + +/* Includes ------------------------------------------------------------------*/ +#include "stm32f10x.h" + +/** @addtogroup STM32F10x_StdPeriph_Driver + * @{ + */ + +/** @addtogroup CEC + * @{ + */ + + +/** @defgroup CEC_Exported_Types + * @{ + */ + +/** + * @brief CEC Init structure definition + */ +typedef struct +{ + uint16_t CEC_BitTimingMode; /*!< Configures the CEC Bit Timing Error Mode. + This parameter can be a value of @ref CEC_BitTiming_Mode */ + uint16_t CEC_BitPeriodMode; /*!< Configures the CEC Bit Period Error Mode. + This parameter can be a value of @ref CEC_BitPeriod_Mode */ +}CEC_InitTypeDef; + +/** + * @} + */ + +/** @defgroup CEC_Exported_Constants + * @{ + */ + +/** @defgroup CEC_BitTiming_Mode + * @{ + */ +#define CEC_BitTimingStdMode ((uint16_t)0x00) /*!< Bit timing error Standard Mode */ +#define CEC_BitTimingErrFreeMode CEC_CFGR_BTEM /*!< Bit timing error Free Mode */ + +#define IS_CEC_BIT_TIMING_ERROR_MODE(MODE) (((MODE) == CEC_BitTimingStdMode) || \ + ((MODE) == CEC_BitTimingErrFreeMode)) +/** + * @} + */ + +/** @defgroup CEC_BitPeriod_Mode + * @{ + */ +#define CEC_BitPeriodStdMode ((uint16_t)0x00) /*!< Bit period error Standard Mode */ +#define CEC_BitPeriodFlexibleMode CEC_CFGR_BPEM /*!< Bit period error Flexible Mode */ + +#define IS_CEC_BIT_PERIOD_ERROR_MODE(MODE) (((MODE) == CEC_BitPeriodStdMode) || \ + ((MODE) == CEC_BitPeriodFlexibleMode)) +/** + * @} + */ + + +/** @defgroup CEC_interrupts_definition + * @{ + */ +#define CEC_IT_TERR CEC_CSR_TERR +#define CEC_IT_TBTRF CEC_CSR_TBTRF +#define CEC_IT_RERR CEC_CSR_RERR +#define CEC_IT_RBTF CEC_CSR_RBTF +#define IS_CEC_GET_IT(IT) (((IT) == CEC_IT_TERR) || ((IT) == CEC_IT_TBTRF) || \ + ((IT) == CEC_IT_RERR) || ((IT) == CEC_IT_RBTF)) +/** + * @} + */ + + +/** @defgroup CEC_Own_Address + * @{ + */ +#define IS_CEC_ADDRESS(ADDRESS) ((ADDRESS) < 0x10) +/** + * @} + */ + +/** @defgroup CEC_Prescaler + * @{ + */ +#define IS_CEC_PRESCALER(PRESCALER) ((PRESCALER) <= 0x3FFF) + +/** + * @} + */ + +/** @defgroup CEC_flags_definition + * @{ + */ + +/** + * @brief ESR register flags + */ +#define CEC_FLAG_BTE ((uint32_t)0x10010000) +#define CEC_FLAG_BPE ((uint32_t)0x10020000) +#define CEC_FLAG_RBTFE ((uint32_t)0x10040000) +#define CEC_FLAG_SBE ((uint32_t)0x10080000) +#define CEC_FLAG_ACKE ((uint32_t)0x10100000) +#define CEC_FLAG_LINE ((uint32_t)0x10200000) +#define CEC_FLAG_TBTFE ((uint32_t)0x10400000) + +/** + * @brief CSR register flags + */ +#define CEC_FLAG_TEOM ((uint32_t)0x00000002) +#define CEC_FLAG_TERR ((uint32_t)0x00000004) +#define CEC_FLAG_TBTRF ((uint32_t)0x00000008) +#define CEC_FLAG_RSOM ((uint32_t)0x00000010) +#define CEC_FLAG_REOM ((uint32_t)0x00000020) +#define CEC_FLAG_RERR ((uint32_t)0x00000040) +#define CEC_FLAG_RBTF ((uint32_t)0x00000080) + +#define IS_CEC_CLEAR_FLAG(FLAG) ((((FLAG) & (uint32_t)0xFFFFFF03) == 0x00) && ((FLAG) != 0x00)) + +#define IS_CEC_GET_FLAG(FLAG) (((FLAG) == CEC_FLAG_BTE) || ((FLAG) == CEC_FLAG_BPE) || \ + ((FLAG) == CEC_FLAG_RBTFE) || ((FLAG)== CEC_FLAG_SBE) || \ + ((FLAG) == CEC_FLAG_ACKE) || ((FLAG) == CEC_FLAG_LINE) || \ + ((FLAG) == CEC_FLAG_TBTFE) || ((FLAG) == CEC_FLAG_TEOM) || \ + ((FLAG) == CEC_FLAG_TERR) || ((FLAG) == CEC_FLAG_TBTRF) || \ + ((FLAG) == CEC_FLAG_RSOM) || ((FLAG) == CEC_FLAG_REOM) || \ + ((FLAG) == CEC_FLAG_RERR) || ((FLAG) == CEC_FLAG_RBTF)) + +/** + * @} + */ + +/** + * @} + */ + +/** @defgroup CEC_Exported_Macros + * @{ + */ + +/** + * @} + */ + +/** @defgroup CEC_Exported_Functions + * @{ + */ +void CEC_DeInit(void); +void CEC_Init(CEC_InitTypeDef* CEC_InitStruct); +void CEC_Cmd(FunctionalState NewState); +void CEC_ITConfig(FunctionalState NewState); +void CEC_OwnAddressConfig(uint8_t CEC_OwnAddress); +void CEC_SetPrescaler(uint16_t CEC_Prescaler); +void CEC_SendDataByte(uint8_t Data); +uint8_t CEC_ReceiveDataByte(void); +void CEC_StartOfMessage(void); +void CEC_EndOfMessageCmd(FunctionalState NewState); +FlagStatus CEC_GetFlagStatus(uint32_t CEC_FLAG); +void CEC_ClearFlag(uint32_t CEC_FLAG); +ITStatus CEC_GetITStatus(uint8_t CEC_IT); +void CEC_ClearITPendingBit(uint16_t CEC_IT); + +#ifdef __cplusplus +} +#endif + +#endif /* __STM32F10x_CEC_H */ + +/** + * @} + */ + +/** + * @} + */ + +/** + * @} + */ + +/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ diff --git a/Libraries/STM32F10x_StdPeriph_Driver/inc/stm32f10x_crc.h b/Libraries/STM32F10x_StdPeriph_Driver/inc/stm32f10x_crc.h new file mode 100644 index 0000000..355fb91 --- /dev/null +++ b/Libraries/STM32F10x_StdPeriph_Driver/inc/stm32f10x_crc.h @@ -0,0 +1,100 @@ +/** + ****************************************************************************** + * @file stm32f10x_crc.h + * @author MCD Application Team + * @version V3.6.1 + * @date 05-March-2012 + * @brief This file contains all the functions prototypes for the CRC firmware + * library. + ****************************************************************************** + * @attention + * + *

    © COPYRIGHT 2012 STMicroelectronics

    + * + * Licensed under MCD-ST Liberty SW License Agreement V2, (the "License"); + * You may not use this file except in compliance with the License. + * You may obtain a copy of the License at: + * + * http://www.st.com/software_license_agreement_liberty_v2 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, + * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + * + ****************************************************************************** + */ + +/* Define to prevent recursive inclusion -------------------------------------*/ +#ifndef __STM32F10x_CRC_H +#define __STM32F10x_CRC_H + +#ifdef __cplusplus + extern "C" { +#endif + +/* Includes ------------------------------------------------------------------*/ +#include "stm32f10x.h" + +/** @addtogroup STM32F10x_StdPeriph_Driver + * @{ + */ + +/** @addtogroup CRC + * @{ + */ + +/** @defgroup CRC_Exported_Types + * @{ + */ + +/** + * @} + */ + +/** @defgroup CRC_Exported_Constants + * @{ + */ + +/** + * @} + */ + +/** @defgroup CRC_Exported_Macros + * @{ + */ + +/** + * @} + */ + +/** @defgroup CRC_Exported_Functions + * @{ + */ + +void CRC_ResetDR(void); +uint32_t CRC_CalcCRC(uint32_t Data); +uint32_t CRC_CalcBlockCRC(uint32_t pBuffer[], uint32_t BufferLength); +uint32_t CRC_GetCRC(void); +void CRC_SetIDRegister(uint8_t IDValue); +uint8_t CRC_GetIDRegister(void); + +#ifdef __cplusplus +} +#endif + +#endif /* __STM32F10x_CRC_H */ +/** + * @} + */ + +/** + * @} + */ + +/** + * @} + */ + +/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ diff --git a/Libraries/STM32F10x_StdPeriph_Driver/inc/stm32f10x_dac.h b/Libraries/STM32F10x_StdPeriph_Driver/inc/stm32f10x_dac.h new file mode 100644 index 0000000..8268ac7 --- /dev/null +++ b/Libraries/STM32F10x_StdPeriph_Driver/inc/stm32f10x_dac.h @@ -0,0 +1,323 @@ +/** + ****************************************************************************** + * @file stm32f10x_dac.h + * @author MCD Application Team + * @version V3.6.1 + * @date 05-March-2012 + * @brief This file contains all the functions prototypes for the DAC firmware + * library. + ****************************************************************************** + * @attention + * + *

    © COPYRIGHT 2012 STMicroelectronics

    + * + * Licensed under MCD-ST Liberty SW License Agreement V2, (the "License"); + * You may not use this file except in compliance with the License. + * You may obtain a copy of the License at: + * + * http://www.st.com/software_license_agreement_liberty_v2 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, + * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + * + ****************************************************************************** + */ + +/* Define to prevent recursive inclusion -------------------------------------*/ +#ifndef __STM32F10x_DAC_H +#define __STM32F10x_DAC_H + +#ifdef __cplusplus + extern "C" { +#endif + +/* Includes ------------------------------------------------------------------*/ +#include "stm32f10x.h" + +/** @addtogroup STM32F10x_StdPeriph_Driver + * @{ + */ + +/** @addtogroup DAC + * @{ + */ + +/** @defgroup DAC_Exported_Types + * @{ + */ + +/** + * @brief DAC Init structure definition + */ + +typedef struct +{ + uint32_t DAC_Trigger; /*!< Specifies the external trigger for the selected DAC channel. + This parameter can be a value of @ref DAC_trigger_selection */ + + uint32_t DAC_WaveGeneration; /*!< Specifies whether DAC channel noise waves or triangle waves + are generated, or whether no wave is generated. + This parameter can be a value of @ref DAC_wave_generation */ + + uint32_t DAC_LFSRUnmask_TriangleAmplitude; /*!< Specifies the LFSR mask for noise wave generation or + the maximum amplitude triangle generation for the DAC channel. + This parameter can be a value of @ref DAC_lfsrunmask_triangleamplitude */ + + uint32_t DAC_OutputBuffer; /*!< Specifies whether the DAC channel output buffer is enabled or disabled. + This parameter can be a value of @ref DAC_output_buffer */ +}DAC_InitTypeDef; + +/** + * @} + */ + +/** @defgroup DAC_Exported_Constants + * @{ + */ + +/** @defgroup DAC_trigger_selection + * @{ + */ + +#define DAC_Trigger_None ((uint32_t)0x00000000) /*!< Conversion is automatic once the DAC1_DHRxxxx register + has been loaded, and not by external trigger */ +#define DAC_Trigger_T6_TRGO ((uint32_t)0x00000004) /*!< TIM6 TRGO selected as external conversion trigger for DAC channel */ +#define DAC_Trigger_T8_TRGO ((uint32_t)0x0000000C) /*!< TIM8 TRGO selected as external conversion trigger for DAC channel + only in High-density devices*/ +#define DAC_Trigger_T3_TRGO ((uint32_t)0x0000000C) /*!< TIM8 TRGO selected as external conversion trigger for DAC channel + only in Connectivity line, Medium-density and Low-density Value Line devices */ +#define DAC_Trigger_T7_TRGO ((uint32_t)0x00000014) /*!< TIM7 TRGO selected as external conversion trigger for DAC channel */ +#define DAC_Trigger_T5_TRGO ((uint32_t)0x0000001C) /*!< TIM5 TRGO selected as external conversion trigger for DAC channel */ +#define DAC_Trigger_T15_TRGO ((uint32_t)0x0000001C) /*!< TIM15 TRGO selected as external conversion trigger for DAC channel + only in Medium-density and Low-density Value Line devices*/ +#define DAC_Trigger_T2_TRGO ((uint32_t)0x00000024) /*!< TIM2 TRGO selected as external conversion trigger for DAC channel */ +#define DAC_Trigger_T4_TRGO ((uint32_t)0x0000002C) /*!< TIM4 TRGO selected as external conversion trigger for DAC channel */ +#define DAC_Trigger_Ext_IT9 ((uint32_t)0x00000034) /*!< EXTI Line9 event selected as external conversion trigger for DAC channel */ +#define DAC_Trigger_Software ((uint32_t)0x0000003C) /*!< Conversion started by software trigger for DAC channel */ + +#define IS_DAC_TRIGGER(TRIGGER) (((TRIGGER) == DAC_Trigger_None) || \ + ((TRIGGER) == DAC_Trigger_T6_TRGO) || \ + ((TRIGGER) == DAC_Trigger_T8_TRGO) || \ + ((TRIGGER) == DAC_Trigger_T7_TRGO) || \ + ((TRIGGER) == DAC_Trigger_T5_TRGO) || \ + ((TRIGGER) == DAC_Trigger_T2_TRGO) || \ + ((TRIGGER) == DAC_Trigger_T4_TRGO) || \ + ((TRIGGER) == DAC_Trigger_Ext_IT9) || \ + ((TRIGGER) == DAC_Trigger_Software)) + +/** + * @} + */ + +/** @defgroup DAC_wave_generation + * @{ + */ + +#define DAC_WaveGeneration_None ((uint32_t)0x00000000) +#define DAC_WaveGeneration_Noise ((uint32_t)0x00000040) +#define DAC_WaveGeneration_Triangle ((uint32_t)0x00000080) +#define IS_DAC_GENERATE_WAVE(WAVE) (((WAVE) == DAC_WaveGeneration_None) || \ + ((WAVE) == DAC_WaveGeneration_Noise) || \ + ((WAVE) == DAC_WaveGeneration_Triangle)) +/** + * @} + */ + +/** @defgroup DAC_lfsrunmask_triangleamplitude + * @{ + */ + +#define DAC_LFSRUnmask_Bit0 ((uint32_t)0x00000000) /*!< Unmask DAC channel LFSR bit0 for noise wave generation */ +#define DAC_LFSRUnmask_Bits1_0 ((uint32_t)0x00000100) /*!< Unmask DAC channel LFSR bit[1:0] for noise wave generation */ +#define DAC_LFSRUnmask_Bits2_0 ((uint32_t)0x00000200) /*!< Unmask DAC channel LFSR bit[2:0] for noise wave generation */ +#define DAC_LFSRUnmask_Bits3_0 ((uint32_t)0x00000300) /*!< Unmask DAC channel LFSR bit[3:0] for noise wave generation */ +#define DAC_LFSRUnmask_Bits4_0 ((uint32_t)0x00000400) /*!< Unmask DAC channel LFSR bit[4:0] for noise wave generation */ +#define DAC_LFSRUnmask_Bits5_0 ((uint32_t)0x00000500) /*!< Unmask DAC channel LFSR bit[5:0] for noise wave generation */ +#define DAC_LFSRUnmask_Bits6_0 ((uint32_t)0x00000600) /*!< Unmask DAC channel LFSR bit[6:0] for noise wave generation */ +#define DAC_LFSRUnmask_Bits7_0 ((uint32_t)0x00000700) /*!< Unmask DAC channel LFSR bit[7:0] for noise wave generation */ +#define DAC_LFSRUnmask_Bits8_0 ((uint32_t)0x00000800) /*!< Unmask DAC channel LFSR bit[8:0] for noise wave generation */ +#define DAC_LFSRUnmask_Bits9_0 ((uint32_t)0x00000900) /*!< Unmask DAC channel LFSR bit[9:0] for noise wave generation */ +#define DAC_LFSRUnmask_Bits10_0 ((uint32_t)0x00000A00) /*!< Unmask DAC channel LFSR bit[10:0] for noise wave generation */ +#define DAC_LFSRUnmask_Bits11_0 ((uint32_t)0x00000B00) /*!< Unmask DAC channel LFSR bit[11:0] for noise wave generation */ +#define DAC_TriangleAmplitude_1 ((uint32_t)0x00000000) /*!< Select max triangle amplitude of 1 */ +#define DAC_TriangleAmplitude_3 ((uint32_t)0x00000100) /*!< Select max triangle amplitude of 3 */ +#define DAC_TriangleAmplitude_7 ((uint32_t)0x00000200) /*!< Select max triangle amplitude of 7 */ +#define DAC_TriangleAmplitude_15 ((uint32_t)0x00000300) /*!< Select max triangle amplitude of 15 */ +#define DAC_TriangleAmplitude_31 ((uint32_t)0x00000400) /*!< Select max triangle amplitude of 31 */ +#define DAC_TriangleAmplitude_63 ((uint32_t)0x00000500) /*!< Select max triangle amplitude of 63 */ +#define DAC_TriangleAmplitude_127 ((uint32_t)0x00000600) /*!< Select max triangle amplitude of 127 */ +#define DAC_TriangleAmplitude_255 ((uint32_t)0x00000700) /*!< Select max triangle amplitude of 255 */ +#define DAC_TriangleAmplitude_511 ((uint32_t)0x00000800) /*!< Select max triangle amplitude of 511 */ +#define DAC_TriangleAmplitude_1023 ((uint32_t)0x00000900) /*!< Select max triangle amplitude of 1023 */ +#define DAC_TriangleAmplitude_2047 ((uint32_t)0x00000A00) /*!< Select max triangle amplitude of 2047 */ +#define DAC_TriangleAmplitude_4095 ((uint32_t)0x00000B00) /*!< Select max triangle amplitude of 4095 */ + +#define IS_DAC_LFSR_UNMASK_TRIANGLE_AMPLITUDE(VALUE) (((VALUE) == DAC_LFSRUnmask_Bit0) || \ + ((VALUE) == DAC_LFSRUnmask_Bits1_0) || \ + ((VALUE) == DAC_LFSRUnmask_Bits2_0) || \ + ((VALUE) == DAC_LFSRUnmask_Bits3_0) || \ + ((VALUE) == DAC_LFSRUnmask_Bits4_0) || \ + ((VALUE) == DAC_LFSRUnmask_Bits5_0) || \ + ((VALUE) == DAC_LFSRUnmask_Bits6_0) || \ + ((VALUE) == DAC_LFSRUnmask_Bits7_0) || \ + ((VALUE) == DAC_LFSRUnmask_Bits8_0) || \ + ((VALUE) == DAC_LFSRUnmask_Bits9_0) || \ + ((VALUE) == DAC_LFSRUnmask_Bits10_0) || \ + ((VALUE) == DAC_LFSRUnmask_Bits11_0) || \ + ((VALUE) == DAC_TriangleAmplitude_1) || \ + ((VALUE) == DAC_TriangleAmplitude_3) || \ + ((VALUE) == DAC_TriangleAmplitude_7) || \ + ((VALUE) == DAC_TriangleAmplitude_15) || \ + ((VALUE) == DAC_TriangleAmplitude_31) || \ + ((VALUE) == DAC_TriangleAmplitude_63) || \ + ((VALUE) == DAC_TriangleAmplitude_127) || \ + ((VALUE) == DAC_TriangleAmplitude_255) || \ + ((VALUE) == DAC_TriangleAmplitude_511) || \ + ((VALUE) == DAC_TriangleAmplitude_1023) || \ + ((VALUE) == DAC_TriangleAmplitude_2047) || \ + ((VALUE) == DAC_TriangleAmplitude_4095)) +/** + * @} + */ + +/** @defgroup DAC_output_buffer + * @{ + */ + +#define DAC_OutputBuffer_Enable ((uint32_t)0x00000000) +#define DAC_OutputBuffer_Disable ((uint32_t)0x00000002) +#define IS_DAC_OUTPUT_BUFFER_STATE(STATE) (((STATE) == DAC_OutputBuffer_Enable) || \ + ((STATE) == DAC_OutputBuffer_Disable)) +/** + * @} + */ + +/** @defgroup DAC_Channel_selection + * @{ + */ + +#define DAC_Channel_1 ((uint32_t)0x00000000) +#define DAC_Channel_2 ((uint32_t)0x00000010) +#define IS_DAC_CHANNEL(CHANNEL) (((CHANNEL) == DAC_Channel_1) || \ + ((CHANNEL) == DAC_Channel_2)) +/** + * @} + */ + +/** @defgroup DAC_data_alignment + * @{ + */ + +#define DAC_Align_12b_R ((uint32_t)0x00000000) +#define DAC_Align_12b_L ((uint32_t)0x00000004) +#define DAC_Align_8b_R ((uint32_t)0x00000008) +#define IS_DAC_ALIGN(ALIGN) (((ALIGN) == DAC_Align_12b_R) || \ + ((ALIGN) == DAC_Align_12b_L) || \ + ((ALIGN) == DAC_Align_8b_R)) +/** + * @} + */ + +/** @defgroup DAC_wave_generation + * @{ + */ + +#define DAC_Wave_Noise ((uint32_t)0x00000040) +#define DAC_Wave_Triangle ((uint32_t)0x00000080) +#define IS_DAC_WAVE(WAVE) (((WAVE) == DAC_Wave_Noise) || \ + ((WAVE) == DAC_Wave_Triangle)) +/** + * @} + */ + +/** @defgroup DAC_data + * @{ + */ + +#define IS_DAC_DATA(DATA) ((DATA) <= 0xFFF0) +/** + * @} + */ +#if defined (STM32F10X_LD_VL) || defined (STM32F10X_MD_VL) || defined (STM32F10X_HD_VL) +/** @defgroup DAC_interrupts_definition + * @{ + */ + +#define DAC_IT_DMAUDR ((uint32_t)0x00002000) +#define IS_DAC_IT(IT) (((IT) == DAC_IT_DMAUDR)) + +/** + * @} + */ + +/** @defgroup DAC_flags_definition + * @{ + */ + +#define DAC_FLAG_DMAUDR ((uint32_t)0x00002000) +#define IS_DAC_FLAG(FLAG) (((FLAG) == DAC_FLAG_DMAUDR)) + +/** + * @} + */ +#endif + +/** + * @} + */ + +/** @defgroup DAC_Exported_Macros + * @{ + */ + +/** + * @} + */ + +/** @defgroup DAC_Exported_Functions + * @{ + */ + +void DAC_DeInit(void); +void DAC_Init(uint32_t DAC_Channel, DAC_InitTypeDef* DAC_InitStruct); +void DAC_StructInit(DAC_InitTypeDef* DAC_InitStruct); +void DAC_Cmd(uint32_t DAC_Channel, FunctionalState NewState); +#if defined (STM32F10X_LD_VL) || defined (STM32F10X_MD_VL) || defined (STM32F10X_HD_VL) +void DAC_ITConfig(uint32_t DAC_Channel, uint32_t DAC_IT, FunctionalState NewState); +#endif +void DAC_DMACmd(uint32_t DAC_Channel, FunctionalState NewState); +void DAC_SoftwareTriggerCmd(uint32_t DAC_Channel, FunctionalState NewState); +void DAC_DualSoftwareTriggerCmd(FunctionalState NewState); +void DAC_WaveGenerationCmd(uint32_t DAC_Channel, uint32_t DAC_Wave, FunctionalState NewState); +void DAC_SetChannel1Data(uint32_t DAC_Align, uint16_t Data); +void DAC_SetChannel2Data(uint32_t DAC_Align, uint16_t Data); +void DAC_SetDualChannelData(uint32_t DAC_Align, uint16_t Data2, uint16_t Data1); +uint16_t DAC_GetDataOutputValue(uint32_t DAC_Channel); +#if defined (STM32F10X_LD_VL) || defined (STM32F10X_MD_VL) || defined (STM32F10X_HD_VL) +FlagStatus DAC_GetFlagStatus(uint32_t DAC_Channel, uint32_t DAC_FLAG); +void DAC_ClearFlag(uint32_t DAC_Channel, uint32_t DAC_FLAG); +ITStatus DAC_GetITStatus(uint32_t DAC_Channel, uint32_t DAC_IT); +void DAC_ClearITPendingBit(uint32_t DAC_Channel, uint32_t DAC_IT); +#endif + +#ifdef __cplusplus +} +#endif + +#endif /*__STM32F10x_DAC_H */ +/** + * @} + */ + +/** + * @} + */ + +/** + * @} + */ + +/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ diff --git a/Libraries/STM32F10x_StdPeriph_Driver/inc/stm32f10x_dbgmcu.h b/Libraries/STM32F10x_StdPeriph_Driver/inc/stm32f10x_dbgmcu.h new file mode 100644 index 0000000..ba7ffe2 --- /dev/null +++ b/Libraries/STM32F10x_StdPeriph_Driver/inc/stm32f10x_dbgmcu.h @@ -0,0 +1,125 @@ +/** + ****************************************************************************** + * @file stm32f10x_dbgmcu.h + * @author MCD Application Team + * @version V3.6.1 + * @date 05-March-2012 + * @brief This file contains all the functions prototypes for the DBGMCU + * firmware library. + ****************************************************************************** + * @attention + * + *

    © COPYRIGHT 2012 STMicroelectronics

    + * + * Licensed under MCD-ST Liberty SW License Agreement V2, (the "License"); + * You may not use this file except in compliance with the License. + * You may obtain a copy of the License at: + * + * http://www.st.com/software_license_agreement_liberty_v2 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, + * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + * + ****************************************************************************** + */ + +/* Define to prevent recursive inclusion -------------------------------------*/ +#ifndef __STM32F10x_DBGMCU_H +#define __STM32F10x_DBGMCU_H + +#ifdef __cplusplus + extern "C" { +#endif + +/* Includes ------------------------------------------------------------------*/ +#include "stm32f10x.h" + +/** @addtogroup STM32F10x_StdPeriph_Driver + * @{ + */ + +/** @addtogroup DBGMCU + * @{ + */ + +/** @defgroup DBGMCU_Exported_Types + * @{ + */ + +/** + * @} + */ + +/** @defgroup DBGMCU_Exported_Constants + * @{ + */ + +#define DBGMCU_SLEEP ((uint32_t)0x00000001) +#define DBGMCU_STOP ((uint32_t)0x00000002) +#define DBGMCU_STANDBY ((uint32_t)0x00000004) +#define DBGMCU_IWDG_STOP ((uint32_t)0x00000100) +#define DBGMCU_WWDG_STOP ((uint32_t)0x00000200) +#define DBGMCU_TIM1_STOP ((uint32_t)0x00000400) +#define DBGMCU_TIM2_STOP ((uint32_t)0x00000800) +#define DBGMCU_TIM3_STOP ((uint32_t)0x00001000) +#define DBGMCU_TIM4_STOP ((uint32_t)0x00002000) +#define DBGMCU_CAN1_STOP ((uint32_t)0x00004000) +#define DBGMCU_I2C1_SMBUS_TIMEOUT ((uint32_t)0x00008000) +#define DBGMCU_I2C2_SMBUS_TIMEOUT ((uint32_t)0x00010000) +#define DBGMCU_TIM8_STOP ((uint32_t)0x00020000) +#define DBGMCU_TIM5_STOP ((uint32_t)0x00040000) +#define DBGMCU_TIM6_STOP ((uint32_t)0x00080000) +#define DBGMCU_TIM7_STOP ((uint32_t)0x00100000) +#define DBGMCU_CAN2_STOP ((uint32_t)0x00200000) +#define DBGMCU_TIM15_STOP ((uint32_t)0x00400000) +#define DBGMCU_TIM16_STOP ((uint32_t)0x00800000) +#define DBGMCU_TIM17_STOP ((uint32_t)0x01000000) +#define DBGMCU_TIM12_STOP ((uint32_t)0x02000000) +#define DBGMCU_TIM13_STOP ((uint32_t)0x04000000) +#define DBGMCU_TIM14_STOP ((uint32_t)0x08000000) +#define DBGMCU_TIM9_STOP ((uint32_t)0x10000000) +#define DBGMCU_TIM10_STOP ((uint32_t)0x20000000) +#define DBGMCU_TIM11_STOP ((uint32_t)0x40000000) + +#define IS_DBGMCU_PERIPH(PERIPH) ((((PERIPH) & 0x800000F8) == 0x00) && ((PERIPH) != 0x00)) +/** + * @} + */ + +/** @defgroup DBGMCU_Exported_Macros + * @{ + */ + +/** + * @} + */ + +/** @defgroup DBGMCU_Exported_Functions + * @{ + */ + +uint32_t DBGMCU_GetREVID(void); +uint32_t DBGMCU_GetDEVID(void); +void DBGMCU_Config(uint32_t DBGMCU_Periph, FunctionalState NewState); + +#ifdef __cplusplus +} +#endif + +#endif /* __STM32F10x_DBGMCU_H */ +/** + * @} + */ + +/** + * @} + */ + +/** + * @} + */ + +/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ diff --git a/Libraries/STM32F10x_StdPeriph_Driver/inc/stm32f10x_dma.h b/Libraries/STM32F10x_StdPeriph_Driver/inc/stm32f10x_dma.h new file mode 100644 index 0000000..d691564 --- /dev/null +++ b/Libraries/STM32F10x_StdPeriph_Driver/inc/stm32f10x_dma.h @@ -0,0 +1,445 @@ +/** + ****************************************************************************** + * @file stm32f10x_dma.h + * @author MCD Application Team + * @version V3.6.1 + * @date 05-March-2012 + * @brief This file contains all the functions prototypes for the DMA firmware + * library. + ****************************************************************************** + * @attention + * + *

    © COPYRIGHT 2012 STMicroelectronics

    + * + * Licensed under MCD-ST Liberty SW License Agreement V2, (the "License"); + * You may not use this file except in compliance with the License. + * You may obtain a copy of the License at: + * + * http://www.st.com/software_license_agreement_liberty_v2 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, + * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + * + ****************************************************************************** + */ + +/* Define to prevent recursive inclusion -------------------------------------*/ +#ifndef __STM32F10x_DMA_H +#define __STM32F10x_DMA_H + +#ifdef __cplusplus + extern "C" { +#endif + +/* Includes ------------------------------------------------------------------*/ +#include "stm32f10x.h" + +/** @addtogroup STM32F10x_StdPeriph_Driver + * @{ + */ + +/** @addtogroup DMA + * @{ + */ + +/** @defgroup DMA_Exported_Types + * @{ + */ + +/** + * @brief DMA Init structure definition + */ + +typedef struct +{ + uint32_t DMA_PeripheralBaseAddr; /*!< Specifies the peripheral base address for DMAy Channelx. */ + + uint32_t DMA_MemoryBaseAddr; /*!< Specifies the memory base address for DMAy Channelx. */ + + uint32_t DMA_DIR; /*!< Specifies if the peripheral is the source or destination. + This parameter can be a value of @ref DMA_data_transfer_direction */ + + uint32_t DMA_BufferSize; /*!< Specifies the buffer size, in data unit, of the specified Channel. + The data unit is equal to the configuration set in DMA_PeripheralDataSize + or DMA_MemoryDataSize members depending in the transfer direction. */ + + uint32_t DMA_PeripheralInc; /*!< Specifies whether the Peripheral address register is incremented or not. + This parameter can be a value of @ref DMA_peripheral_incremented_mode */ + + uint32_t DMA_MemoryInc; /*!< Specifies whether the memory address register is incremented or not. + This parameter can be a value of @ref DMA_memory_incremented_mode */ + + uint32_t DMA_PeripheralDataSize; /*!< Specifies the Peripheral data width. + This parameter can be a value of @ref DMA_peripheral_data_size */ + + uint32_t DMA_MemoryDataSize; /*!< Specifies the Memory data width. + This parameter can be a value of @ref DMA_memory_data_size */ + + uint32_t DMA_Mode; /*!< Specifies the operation mode of the DMAy Channelx. + This parameter can be a value of @ref DMA_circular_normal_mode. + @note: The circular buffer mode cannot be used if the memory-to-memory + data transfer is configured on the selected Channel */ + + uint32_t DMA_Priority; /*!< Specifies the software priority for the DMAy Channelx. + This parameter can be a value of @ref DMA_priority_level */ + + uint32_t DMA_M2M; /*!< Specifies if the DMAy Channelx will be used in memory-to-memory transfer. + This parameter can be a value of @ref DMA_memory_to_memory */ +}DMA_InitTypeDef; + +/** + * @} + */ + +/** @defgroup DMA_Exported_Constants + * @{ + */ + +#define IS_DMA_ALL_PERIPH(PERIPH) (((PERIPH) == DMA1_Channel1) || \ + ((PERIPH) == DMA1_Channel2) || \ + ((PERIPH) == DMA1_Channel3) || \ + ((PERIPH) == DMA1_Channel4) || \ + ((PERIPH) == DMA1_Channel5) || \ + ((PERIPH) == DMA1_Channel6) || \ + ((PERIPH) == DMA1_Channel7) || \ + ((PERIPH) == DMA2_Channel1) || \ + ((PERIPH) == DMA2_Channel2) || \ + ((PERIPH) == DMA2_Channel3) || \ + ((PERIPH) == DMA2_Channel4) || \ + ((PERIPH) == DMA2_Channel5)) + +/** @defgroup DMA_data_transfer_direction + * @{ + */ + +#define DMA_DIR_PeripheralDST ((uint32_t)0x00000010) +#define DMA_DIR_PeripheralSRC ((uint32_t)0x00000000) +#define IS_DMA_DIR(DIR) (((DIR) == DMA_DIR_PeripheralDST) || \ + ((DIR) == DMA_DIR_PeripheralSRC)) +/** + * @} + */ + +/** @defgroup DMA_peripheral_incremented_mode + * @{ + */ + +#define DMA_PeripheralInc_Enable ((uint32_t)0x00000040) +#define DMA_PeripheralInc_Disable ((uint32_t)0x00000000) +#define IS_DMA_PERIPHERAL_INC_STATE(STATE) (((STATE) == DMA_PeripheralInc_Enable) || \ + ((STATE) == DMA_PeripheralInc_Disable)) +/** + * @} + */ + +/** @defgroup DMA_memory_incremented_mode + * @{ + */ + +#define DMA_MemoryInc_Enable ((uint32_t)0x00000080) +#define DMA_MemoryInc_Disable ((uint32_t)0x00000000) +#define IS_DMA_MEMORY_INC_STATE(STATE) (((STATE) == DMA_MemoryInc_Enable) || \ + ((STATE) == DMA_MemoryInc_Disable)) +/** + * @} + */ + +/** @defgroup DMA_peripheral_data_size + * @{ + */ + +#define DMA_PeripheralDataSize_Byte ((uint32_t)0x00000000) +#define DMA_PeripheralDataSize_HalfWord ((uint32_t)0x00000100) +#define DMA_PeripheralDataSize_Word ((uint32_t)0x00000200) +#define IS_DMA_PERIPHERAL_DATA_SIZE(SIZE) (((SIZE) == DMA_PeripheralDataSize_Byte) || \ + ((SIZE) == DMA_PeripheralDataSize_HalfWord) || \ + ((SIZE) == DMA_PeripheralDataSize_Word)) +/** + * @} + */ + +/** @defgroup DMA_memory_data_size + * @{ + */ + +#define DMA_MemoryDataSize_Byte ((uint32_t)0x00000000) +#define DMA_MemoryDataSize_HalfWord ((uint32_t)0x00000400) +#define DMA_MemoryDataSize_Word ((uint32_t)0x00000800) +#define IS_DMA_MEMORY_DATA_SIZE(SIZE) (((SIZE) == DMA_MemoryDataSize_Byte) || \ + ((SIZE) == DMA_MemoryDataSize_HalfWord) || \ + ((SIZE) == DMA_MemoryDataSize_Word)) +/** + * @} + */ + +/** @defgroup DMA_circular_normal_mode + * @{ + */ + +#define DMA_Mode_Circular ((uint32_t)0x00000020) +#define DMA_Mode_Normal ((uint32_t)0x00000000) +#define IS_DMA_MODE(MODE) (((MODE) == DMA_Mode_Circular) || ((MODE) == DMA_Mode_Normal)) +/** + * @} + */ + +/** @defgroup DMA_priority_level + * @{ + */ + +#define DMA_Priority_VeryHigh ((uint32_t)0x00003000) +#define DMA_Priority_High ((uint32_t)0x00002000) +#define DMA_Priority_Medium ((uint32_t)0x00001000) +#define DMA_Priority_Low ((uint32_t)0x00000000) +#define IS_DMA_PRIORITY(PRIORITY) (((PRIORITY) == DMA_Priority_VeryHigh) || \ + ((PRIORITY) == DMA_Priority_High) || \ + ((PRIORITY) == DMA_Priority_Medium) || \ + ((PRIORITY) == DMA_Priority_Low)) +/** + * @} + */ + +/** @defgroup DMA_memory_to_memory + * @{ + */ + +#define DMA_M2M_Enable ((uint32_t)0x00004000) +#define DMA_M2M_Disable ((uint32_t)0x00000000) +#define IS_DMA_M2M_STATE(STATE) (((STATE) == DMA_M2M_Enable) || ((STATE) == DMA_M2M_Disable)) + +/** + * @} + */ + +/** @defgroup DMA_interrupts_definition + * @{ + */ + +#define DMA_IT_TC ((uint32_t)0x00000002) +#define DMA_IT_HT ((uint32_t)0x00000004) +#define DMA_IT_TE ((uint32_t)0x00000008) +#define IS_DMA_CONFIG_IT(IT) ((((IT) & 0xFFFFFFF1) == 0x00) && ((IT) != 0x00)) + +#define DMA1_IT_GL1 ((uint32_t)0x00000001) +#define DMA1_IT_TC1 ((uint32_t)0x00000002) +#define DMA1_IT_HT1 ((uint32_t)0x00000004) +#define DMA1_IT_TE1 ((uint32_t)0x00000008) +#define DMA1_IT_GL2 ((uint32_t)0x00000010) +#define DMA1_IT_TC2 ((uint32_t)0x00000020) +#define DMA1_IT_HT2 ((uint32_t)0x00000040) +#define DMA1_IT_TE2 ((uint32_t)0x00000080) +#define DMA1_IT_GL3 ((uint32_t)0x00000100) +#define DMA1_IT_TC3 ((uint32_t)0x00000200) +#define DMA1_IT_HT3 ((uint32_t)0x00000400) +#define DMA1_IT_TE3 ((uint32_t)0x00000800) +#define DMA1_IT_GL4 ((uint32_t)0x00001000) +#define DMA1_IT_TC4 ((uint32_t)0x00002000) +#define DMA1_IT_HT4 ((uint32_t)0x00004000) +#define DMA1_IT_TE4 ((uint32_t)0x00008000) +#define DMA1_IT_GL5 ((uint32_t)0x00010000) +#define DMA1_IT_TC5 ((uint32_t)0x00020000) +#define DMA1_IT_HT5 ((uint32_t)0x00040000) +#define DMA1_IT_TE5 ((uint32_t)0x00080000) +#define DMA1_IT_GL6 ((uint32_t)0x00100000) +#define DMA1_IT_TC6 ((uint32_t)0x00200000) +#define DMA1_IT_HT6 ((uint32_t)0x00400000) +#define DMA1_IT_TE6 ((uint32_t)0x00800000) +#define DMA1_IT_GL7 ((uint32_t)0x01000000) +#define DMA1_IT_TC7 ((uint32_t)0x02000000) +#define DMA1_IT_HT7 ((uint32_t)0x04000000) +#define DMA1_IT_TE7 ((uint32_t)0x08000000) + +#define DMA2_IT_GL1 ((uint32_t)0x10000001) +#define DMA2_IT_TC1 ((uint32_t)0x10000002) +#define DMA2_IT_HT1 ((uint32_t)0x10000004) +#define DMA2_IT_TE1 ((uint32_t)0x10000008) +#define DMA2_IT_GL2 ((uint32_t)0x10000010) +#define DMA2_IT_TC2 ((uint32_t)0x10000020) +#define DMA2_IT_HT2 ((uint32_t)0x10000040) +#define DMA2_IT_TE2 ((uint32_t)0x10000080) +#define DMA2_IT_GL3 ((uint32_t)0x10000100) +#define DMA2_IT_TC3 ((uint32_t)0x10000200) +#define DMA2_IT_HT3 ((uint32_t)0x10000400) +#define DMA2_IT_TE3 ((uint32_t)0x10000800) +#define DMA2_IT_GL4 ((uint32_t)0x10001000) +#define DMA2_IT_TC4 ((uint32_t)0x10002000) +#define DMA2_IT_HT4 ((uint32_t)0x10004000) +#define DMA2_IT_TE4 ((uint32_t)0x10008000) +#define DMA2_IT_GL5 ((uint32_t)0x10010000) +#define DMA2_IT_TC5 ((uint32_t)0x10020000) +#define DMA2_IT_HT5 ((uint32_t)0x10040000) +#define DMA2_IT_TE5 ((uint32_t)0x10080000) + +#define IS_DMA_CLEAR_IT(IT) (((((IT) & 0xF0000000) == 0x00) || (((IT) & 0xEFF00000) == 0x00)) && ((IT) != 0x00)) + +#define IS_DMA_GET_IT(IT) (((IT) == DMA1_IT_GL1) || ((IT) == DMA1_IT_TC1) || \ + ((IT) == DMA1_IT_HT1) || ((IT) == DMA1_IT_TE1) || \ + ((IT) == DMA1_IT_GL2) || ((IT) == DMA1_IT_TC2) || \ + ((IT) == DMA1_IT_HT2) || ((IT) == DMA1_IT_TE2) || \ + ((IT) == DMA1_IT_GL3) || ((IT) == DMA1_IT_TC3) || \ + ((IT) == DMA1_IT_HT3) || ((IT) == DMA1_IT_TE3) || \ + ((IT) == DMA1_IT_GL4) || ((IT) == DMA1_IT_TC4) || \ + ((IT) == DMA1_IT_HT4) || ((IT) == DMA1_IT_TE4) || \ + ((IT) == DMA1_IT_GL5) || ((IT) == DMA1_IT_TC5) || \ + ((IT) == DMA1_IT_HT5) || ((IT) == DMA1_IT_TE5) || \ + ((IT) == DMA1_IT_GL6) || ((IT) == DMA1_IT_TC6) || \ + ((IT) == DMA1_IT_HT6) || ((IT) == DMA1_IT_TE6) || \ + ((IT) == DMA1_IT_GL7) || ((IT) == DMA1_IT_TC7) || \ + ((IT) == DMA1_IT_HT7) || ((IT) == DMA1_IT_TE7) || \ + ((IT) == DMA2_IT_GL1) || ((IT) == DMA2_IT_TC1) || \ + ((IT) == DMA2_IT_HT1) || ((IT) == DMA2_IT_TE1) || \ + ((IT) == DMA2_IT_GL2) || ((IT) == DMA2_IT_TC2) || \ + ((IT) == DMA2_IT_HT2) || ((IT) == DMA2_IT_TE2) || \ + ((IT) == DMA2_IT_GL3) || ((IT) == DMA2_IT_TC3) || \ + ((IT) == DMA2_IT_HT3) || ((IT) == DMA2_IT_TE3) || \ + ((IT) == DMA2_IT_GL4) || ((IT) == DMA2_IT_TC4) || \ + ((IT) == DMA2_IT_HT4) || ((IT) == DMA2_IT_TE4) || \ + ((IT) == DMA2_IT_GL5) || ((IT) == DMA2_IT_TC5) || \ + ((IT) == DMA2_IT_HT5) || ((IT) == DMA2_IT_TE5)) + +/** + * @} + */ + +/** @defgroup DMA_flags_definition + * @{ + */ +#define DMA1_FLAG_GL1 ((uint32_t)0x00000001) +#define DMA1_FLAG_TC1 ((uint32_t)0x00000002) +#define DMA1_FLAG_HT1 ((uint32_t)0x00000004) +#define DMA1_FLAG_TE1 ((uint32_t)0x00000008) +#define DMA1_FLAG_GL2 ((uint32_t)0x00000010) +#define DMA1_FLAG_TC2 ((uint32_t)0x00000020) +#define DMA1_FLAG_HT2 ((uint32_t)0x00000040) +#define DMA1_FLAG_TE2 ((uint32_t)0x00000080) +#define DMA1_FLAG_GL3 ((uint32_t)0x00000100) +#define DMA1_FLAG_TC3 ((uint32_t)0x00000200) +#define DMA1_FLAG_HT3 ((uint32_t)0x00000400) +#define DMA1_FLAG_TE3 ((uint32_t)0x00000800) +#define DMA1_FLAG_GL4 ((uint32_t)0x00001000) +#define DMA1_FLAG_TC4 ((uint32_t)0x00002000) +#define DMA1_FLAG_HT4 ((uint32_t)0x00004000) +#define DMA1_FLAG_TE4 ((uint32_t)0x00008000) +#define DMA1_FLAG_GL5 ((uint32_t)0x00010000) +#define DMA1_FLAG_TC5 ((uint32_t)0x00020000) +#define DMA1_FLAG_HT5 ((uint32_t)0x00040000) +#define DMA1_FLAG_TE5 ((uint32_t)0x00080000) +#define DMA1_FLAG_GL6 ((uint32_t)0x00100000) +#define DMA1_FLAG_TC6 ((uint32_t)0x00200000) +#define DMA1_FLAG_HT6 ((uint32_t)0x00400000) +#define DMA1_FLAG_TE6 ((uint32_t)0x00800000) +#define DMA1_FLAG_GL7 ((uint32_t)0x01000000) +#define DMA1_FLAG_TC7 ((uint32_t)0x02000000) +#define DMA1_FLAG_HT7 ((uint32_t)0x04000000) +#define DMA1_FLAG_TE7 ((uint32_t)0x08000000) + +#define DMA2_FLAG_GL1 ((uint32_t)0x10000001) +#define DMA2_FLAG_TC1 ((uint32_t)0x10000002) +#define DMA2_FLAG_HT1 ((uint32_t)0x10000004) +#define DMA2_FLAG_TE1 ((uint32_t)0x10000008) +#define DMA2_FLAG_GL2 ((uint32_t)0x10000010) +#define DMA2_FLAG_TC2 ((uint32_t)0x10000020) +#define DMA2_FLAG_HT2 ((uint32_t)0x10000040) +#define DMA2_FLAG_TE2 ((uint32_t)0x10000080) +#define DMA2_FLAG_GL3 ((uint32_t)0x10000100) +#define DMA2_FLAG_TC3 ((uint32_t)0x10000200) +#define DMA2_FLAG_HT3 ((uint32_t)0x10000400) +#define DMA2_FLAG_TE3 ((uint32_t)0x10000800) +#define DMA2_FLAG_GL4 ((uint32_t)0x10001000) +#define DMA2_FLAG_TC4 ((uint32_t)0x10002000) +#define DMA2_FLAG_HT4 ((uint32_t)0x10004000) +#define DMA2_FLAG_TE4 ((uint32_t)0x10008000) +#define DMA2_FLAG_GL5 ((uint32_t)0x10010000) +#define DMA2_FLAG_TC5 ((uint32_t)0x10020000) +#define DMA2_FLAG_HT5 ((uint32_t)0x10040000) +#define DMA2_FLAG_TE5 ((uint32_t)0x10080000) + +#define IS_DMA_CLEAR_FLAG(FLAG) (((((FLAG) & 0xF0000000) == 0x00) || (((FLAG) & 0xEFF00000) == 0x00)) && ((FLAG) != 0x00)) + +#define IS_DMA_GET_FLAG(FLAG) (((FLAG) == DMA1_FLAG_GL1) || ((FLAG) == DMA1_FLAG_TC1) || \ + ((FLAG) == DMA1_FLAG_HT1) || ((FLAG) == DMA1_FLAG_TE1) || \ + ((FLAG) == DMA1_FLAG_GL2) || ((FLAG) == DMA1_FLAG_TC2) || \ + ((FLAG) == DMA1_FLAG_HT2) || ((FLAG) == DMA1_FLAG_TE2) || \ + ((FLAG) == DMA1_FLAG_GL3) || ((FLAG) == DMA1_FLAG_TC3) || \ + ((FLAG) == DMA1_FLAG_HT3) || ((FLAG) == DMA1_FLAG_TE3) || \ + ((FLAG) == DMA1_FLAG_GL4) || ((FLAG) == DMA1_FLAG_TC4) || \ + ((FLAG) == DMA1_FLAG_HT4) || ((FLAG) == DMA1_FLAG_TE4) || \ + ((FLAG) == DMA1_FLAG_GL5) || ((FLAG) == DMA1_FLAG_TC5) || \ + ((FLAG) == DMA1_FLAG_HT5) || ((FLAG) == DMA1_FLAG_TE5) || \ + ((FLAG) == DMA1_FLAG_GL6) || ((FLAG) == DMA1_FLAG_TC6) || \ + ((FLAG) == DMA1_FLAG_HT6) || ((FLAG) == DMA1_FLAG_TE6) || \ + ((FLAG) == DMA1_FLAG_GL7) || ((FLAG) == DMA1_FLAG_TC7) || \ + ((FLAG) == DMA1_FLAG_HT7) || ((FLAG) == DMA1_FLAG_TE7) || \ + ((FLAG) == DMA2_FLAG_GL1) || ((FLAG) == DMA2_FLAG_TC1) || \ + ((FLAG) == DMA2_FLAG_HT1) || ((FLAG) == DMA2_FLAG_TE1) || \ + ((FLAG) == DMA2_FLAG_GL2) || ((FLAG) == DMA2_FLAG_TC2) || \ + ((FLAG) == DMA2_FLAG_HT2) || ((FLAG) == DMA2_FLAG_TE2) || \ + ((FLAG) == DMA2_FLAG_GL3) || ((FLAG) == DMA2_FLAG_TC3) || \ + ((FLAG) == DMA2_FLAG_HT3) || ((FLAG) == DMA2_FLAG_TE3) || \ + ((FLAG) == DMA2_FLAG_GL4) || ((FLAG) == DMA2_FLAG_TC4) || \ + ((FLAG) == DMA2_FLAG_HT4) || ((FLAG) == DMA2_FLAG_TE4) || \ + ((FLAG) == DMA2_FLAG_GL5) || ((FLAG) == DMA2_FLAG_TC5) || \ + ((FLAG) == DMA2_FLAG_HT5) || ((FLAG) == DMA2_FLAG_TE5)) +/** + * @} + */ + +/** @defgroup DMA_Buffer_Size + * @{ + */ + +#define IS_DMA_BUFFER_SIZE(SIZE) (((SIZE) >= 0x1) && ((SIZE) < 0x10000)) + +/** + * @} + */ + +/** + * @} + */ + +/** @defgroup DMA_Exported_Macros + * @{ + */ + +/** + * @} + */ + +/** @defgroup DMA_Exported_Functions + * @{ + */ + +void DMA_DeInit(DMA_Channel_TypeDef* DMAy_Channelx); +void DMA_Init(DMA_Channel_TypeDef* DMAy_Channelx, DMA_InitTypeDef* DMA_InitStruct); +void DMA_StructInit(DMA_InitTypeDef* DMA_InitStruct); +void DMA_Cmd(DMA_Channel_TypeDef* DMAy_Channelx, FunctionalState NewState); +void DMA_ITConfig(DMA_Channel_TypeDef* DMAy_Channelx, uint32_t DMA_IT, FunctionalState NewState); +void DMA_SetCurrDataCounter(DMA_Channel_TypeDef* DMAy_Channelx, uint16_t DataNumber); +uint16_t DMA_GetCurrDataCounter(DMA_Channel_TypeDef* DMAy_Channelx); +FlagStatus DMA_GetFlagStatus(uint32_t DMAy_FLAG); +void DMA_ClearFlag(uint32_t DMAy_FLAG); +ITStatus DMA_GetITStatus(uint32_t DMAy_IT); +void DMA_ClearITPendingBit(uint32_t DMAy_IT); + +#ifdef __cplusplus +} +#endif + +#endif /*__STM32F10x_DMA_H */ +/** + * @} + */ + +/** + * @} + */ + +/** + * @} + */ + +/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ diff --git a/Libraries/STM32F10x_StdPeriph_Driver/inc/stm32f10x_exti.h b/Libraries/STM32F10x_StdPeriph_Driver/inc/stm32f10x_exti.h new file mode 100644 index 0000000..2883c1e --- /dev/null +++ b/Libraries/STM32F10x_StdPeriph_Driver/inc/stm32f10x_exti.h @@ -0,0 +1,190 @@ +/** + ****************************************************************************** + * @file stm32f10x_exti.h + * @author MCD Application Team + * @version V3.6.1 + * @date 05-March-2012 + * @brief This file contains all the functions prototypes for the EXTI firmware + * library. + ****************************************************************************** + * @attention + * + *

    © COPYRIGHT 2012 STMicroelectronics

    + * + * Licensed under MCD-ST Liberty SW License Agreement V2, (the "License"); + * You may not use this file except in compliance with the License. + * You may obtain a copy of the License at: + * + * http://www.st.com/software_license_agreement_liberty_v2 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, + * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + * + ****************************************************************************** + */ + +/* Define to prevent recursive inclusion -------------------------------------*/ +#ifndef __STM32F10x_EXTI_H +#define __STM32F10x_EXTI_H + +#ifdef __cplusplus + extern "C" { +#endif + +/* Includes ------------------------------------------------------------------*/ +#include "stm32f10x.h" + +/** @addtogroup STM32F10x_StdPeriph_Driver + * @{ + */ + +/** @addtogroup EXTI + * @{ + */ + +/** @defgroup EXTI_Exported_Types + * @{ + */ + +/** + * @brief EXTI mode enumeration + */ + +typedef enum +{ + EXTI_Mode_Interrupt = 0x00, + EXTI_Mode_Event = 0x04 +}EXTIMode_TypeDef; + +#define IS_EXTI_MODE(MODE) (((MODE) == EXTI_Mode_Interrupt) || ((MODE) == EXTI_Mode_Event)) + +/** + * @brief EXTI Trigger enumeration + */ + +typedef enum +{ + EXTI_Trigger_Rising = 0x08, + EXTI_Trigger_Falling = 0x0C, + EXTI_Trigger_Rising_Falling = 0x10 +}EXTITrigger_TypeDef; + +#define IS_EXTI_TRIGGER(TRIGGER) (((TRIGGER) == EXTI_Trigger_Rising) || \ + ((TRIGGER) == EXTI_Trigger_Falling) || \ + ((TRIGGER) == EXTI_Trigger_Rising_Falling)) +/** + * @brief EXTI Init Structure definition + */ + +typedef struct +{ + uint32_t EXTI_Line; /*!< Specifies the EXTI lines to be enabled or disabled. + This parameter can be any combination of @ref EXTI_Lines */ + + EXTIMode_TypeDef EXTI_Mode; /*!< Specifies the mode for the EXTI lines. + This parameter can be a value of @ref EXTIMode_TypeDef */ + + EXTITrigger_TypeDef EXTI_Trigger; /*!< Specifies the trigger signal active edge for the EXTI lines. + This parameter can be a value of @ref EXTITrigger_TypeDef */ + + FunctionalState EXTI_LineCmd; /*!< Specifies the new state of the selected EXTI lines. + This parameter can be set either to ENABLE or DISABLE */ +}EXTI_InitTypeDef; + +/** + * @} + */ + +/** @defgroup EXTI_Exported_Constants + * @{ + */ + +/** @defgroup EXTI_Lines + * @{ + */ + +#define EXTI_Line0 ((uint32_t)0x00001) /*!< External interrupt line 0 */ +#define EXTI_Line1 ((uint32_t)0x00002) /*!< External interrupt line 1 */ +#define EXTI_Line2 ((uint32_t)0x00004) /*!< External interrupt line 2 */ +#define EXTI_Line3 ((uint32_t)0x00008) /*!< External interrupt line 3 */ +#define EXTI_Line4 ((uint32_t)0x00010) /*!< External interrupt line 4 */ +#define EXTI_Line5 ((uint32_t)0x00020) /*!< External interrupt line 5 */ +#define EXTI_Line6 ((uint32_t)0x00040) /*!< External interrupt line 6 */ +#define EXTI_Line7 ((uint32_t)0x00080) /*!< External interrupt line 7 */ +#define EXTI_Line8 ((uint32_t)0x00100) /*!< External interrupt line 8 */ +#define EXTI_Line9 ((uint32_t)0x00200) /*!< External interrupt line 9 */ +#define EXTI_Line10 ((uint32_t)0x00400) /*!< External interrupt line 10 */ +#define EXTI_Line11 ((uint32_t)0x00800) /*!< External interrupt line 11 */ +#define EXTI_Line12 ((uint32_t)0x01000) /*!< External interrupt line 12 */ +#define EXTI_Line13 ((uint32_t)0x02000) /*!< External interrupt line 13 */ +#define EXTI_Line14 ((uint32_t)0x04000) /*!< External interrupt line 14 */ +#define EXTI_Line15 ((uint32_t)0x08000) /*!< External interrupt line 15 */ +#define EXTI_Line16 ((uint32_t)0x10000) /*!< External interrupt line 16 Connected to the PVD Output */ +#define EXTI_Line17 ((uint32_t)0x20000) /*!< External interrupt line 17 Connected to the RTC Alarm event */ +#define EXTI_Line18 ((uint32_t)0x40000) /*!< External interrupt line 18 Connected to the USB Device/USB OTG FS + Wakeup from suspend event */ +#define EXTI_Line19 ((uint32_t)0x80000) /*!< External interrupt line 19 Connected to the Ethernet Wakeup event */ + +#define IS_EXTI_LINE(LINE) ((((LINE) & (uint32_t)0xFFF00000) == 0x00) && ((LINE) != (uint16_t)0x00)) +#define IS_GET_EXTI_LINE(LINE) (((LINE) == EXTI_Line0) || ((LINE) == EXTI_Line1) || \ + ((LINE) == EXTI_Line2) || ((LINE) == EXTI_Line3) || \ + ((LINE) == EXTI_Line4) || ((LINE) == EXTI_Line5) || \ + ((LINE) == EXTI_Line6) || ((LINE) == EXTI_Line7) || \ + ((LINE) == EXTI_Line8) || ((LINE) == EXTI_Line9) || \ + ((LINE) == EXTI_Line10) || ((LINE) == EXTI_Line11) || \ + ((LINE) == EXTI_Line12) || ((LINE) == EXTI_Line13) || \ + ((LINE) == EXTI_Line14) || ((LINE) == EXTI_Line15) || \ + ((LINE) == EXTI_Line16) || ((LINE) == EXTI_Line17) || \ + ((LINE) == EXTI_Line18) || ((LINE) == EXTI_Line19)) + + +/** + * @} + */ + +/** + * @} + */ + +/** @defgroup EXTI_Exported_Macros + * @{ + */ + +/** + * @} + */ + +/** @defgroup EXTI_Exported_Functions + * @{ + */ + +void EXTI_DeInit(void); +void EXTI_Init(EXTI_InitTypeDef* EXTI_InitStruct); +void EXTI_StructInit(EXTI_InitTypeDef* EXTI_InitStruct); +void EXTI_GenerateSWInterrupt(uint32_t EXTI_Line); +FlagStatus EXTI_GetFlagStatus(uint32_t EXTI_Line); +void EXTI_ClearFlag(uint32_t EXTI_Line); +ITStatus EXTI_GetITStatus(uint32_t EXTI_Line); +void EXTI_ClearITPendingBit(uint32_t EXTI_Line); + +#ifdef __cplusplus +} +#endif + +#endif /* __STM32F10x_EXTI_H */ +/** + * @} + */ + +/** + * @} + */ + +/** + * @} + */ + +/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ diff --git a/Libraries/STM32F10x_StdPeriph_Driver/inc/stm32f10x_flash.h b/Libraries/STM32F10x_StdPeriph_Driver/inc/stm32f10x_flash.h new file mode 100644 index 0000000..fa6f405 --- /dev/null +++ b/Libraries/STM32F10x_StdPeriph_Driver/inc/stm32f10x_flash.h @@ -0,0 +1,432 @@ +/** + ****************************************************************************** + * @file stm32f10x_flash.h + * @author MCD Application Team + * @version V3.6.1 + * @date 05-March-2012 + * @brief This file contains all the functions prototypes for the FLASH + * firmware library. + ****************************************************************************** + * @attention + * + *

    © COPYRIGHT 2012 STMicroelectronics

    + * + * Licensed under MCD-ST Liberty SW License Agreement V2, (the "License"); + * You may not use this file except in compliance with the License. + * You may obtain a copy of the License at: + * + * http://www.st.com/software_license_agreement_liberty_v2 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, + * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + * + ****************************************************************************** + */ + +/* Define to prevent recursive inclusion -------------------------------------*/ +#ifndef __STM32F10x_FLASH_H +#define __STM32F10x_FLASH_H + +#ifdef __cplusplus + extern "C" { +#endif + +/* Includes ------------------------------------------------------------------*/ +#include "stm32f10x.h" + +/** @addtogroup STM32F10x_StdPeriph_Driver + * @{ + */ + +/** @addtogroup FLASH + * @{ + */ + +/** @defgroup FLASH_Exported_Types + * @{ + */ + +/** + * @brief FLASH Status + */ + +typedef enum +{ + FLASH_BUSY = 1, + FLASH_ERROR_PG, + FLASH_ERROR_WRP, + FLASH_COMPLETE, + FLASH_TIMEOUT +}FLASH_Status; + +/** + * @} + */ + +/** @defgroup FLASH_Exported_Constants + * @{ + */ + +/** @defgroup Flash_Latency + * @{ + */ + +#define FLASH_Latency_0 ((uint32_t)0x00000000) /*!< FLASH Zero Latency cycle */ +#define FLASH_Latency_1 ((uint32_t)0x00000001) /*!< FLASH One Latency cycle */ +#define FLASH_Latency_2 ((uint32_t)0x00000002) /*!< FLASH Two Latency cycles */ +#define IS_FLASH_LATENCY(LATENCY) (((LATENCY) == FLASH_Latency_0) || \ + ((LATENCY) == FLASH_Latency_1) || \ + ((LATENCY) == FLASH_Latency_2)) +/** + * @} + */ + +/** @defgroup Half_Cycle_Enable_Disable + * @{ + */ + +#define FLASH_HalfCycleAccess_Enable ((uint32_t)0x00000008) /*!< FLASH Half Cycle Enable */ +#define FLASH_HalfCycleAccess_Disable ((uint32_t)0x00000000) /*!< FLASH Half Cycle Disable */ +#define IS_FLASH_HALFCYCLEACCESS_STATE(STATE) (((STATE) == FLASH_HalfCycleAccess_Enable) || \ + ((STATE) == FLASH_HalfCycleAccess_Disable)) +/** + * @} + */ + +/** @defgroup Prefetch_Buffer_Enable_Disable + * @{ + */ + +#define FLASH_PrefetchBuffer_Enable ((uint32_t)0x00000010) /*!< FLASH Prefetch Buffer Enable */ +#define FLASH_PrefetchBuffer_Disable ((uint32_t)0x00000000) /*!< FLASH Prefetch Buffer Disable */ +#define IS_FLASH_PREFETCHBUFFER_STATE(STATE) (((STATE) == FLASH_PrefetchBuffer_Enable) || \ + ((STATE) == FLASH_PrefetchBuffer_Disable)) +/** + * @} + */ + +/** @defgroup Option_Bytes_Write_Protection + * @{ + */ + +/* Values to be used with STM32 Low and Medium density devices */ +#define FLASH_WRProt_Pages0to3 ((uint32_t)0x00000001) /*!< STM32 Low and Medium density devices: Write protection of page 0 to 3 */ +#define FLASH_WRProt_Pages4to7 ((uint32_t)0x00000002) /*!< STM32 Low and Medium density devices: Write protection of page 4 to 7 */ +#define FLASH_WRProt_Pages8to11 ((uint32_t)0x00000004) /*!< STM32 Low and Medium density devices: Write protection of page 8 to 11 */ +#define FLASH_WRProt_Pages12to15 ((uint32_t)0x00000008) /*!< STM32 Low and Medium density devices: Write protection of page 12 to 15 */ +#define FLASH_WRProt_Pages16to19 ((uint32_t)0x00000010) /*!< STM32 Low and Medium density devices: Write protection of page 16 to 19 */ +#define FLASH_WRProt_Pages20to23 ((uint32_t)0x00000020) /*!< STM32 Low and Medium density devices: Write protection of page 20 to 23 */ +#define FLASH_WRProt_Pages24to27 ((uint32_t)0x00000040) /*!< STM32 Low and Medium density devices: Write protection of page 24 to 27 */ +#define FLASH_WRProt_Pages28to31 ((uint32_t)0x00000080) /*!< STM32 Low and Medium density devices: Write protection of page 28 to 31 */ + +/* Values to be used with STM32 Medium-density devices */ +#define FLASH_WRProt_Pages32to35 ((uint32_t)0x00000100) /*!< STM32 Medium-density devices: Write protection of page 32 to 35 */ +#define FLASH_WRProt_Pages36to39 ((uint32_t)0x00000200) /*!< STM32 Medium-density devices: Write protection of page 36 to 39 */ +#define FLASH_WRProt_Pages40to43 ((uint32_t)0x00000400) /*!< STM32 Medium-density devices: Write protection of page 40 to 43 */ +#define FLASH_WRProt_Pages44to47 ((uint32_t)0x00000800) /*!< STM32 Medium-density devices: Write protection of page 44 to 47 */ +#define FLASH_WRProt_Pages48to51 ((uint32_t)0x00001000) /*!< STM32 Medium-density devices: Write protection of page 48 to 51 */ +#define FLASH_WRProt_Pages52to55 ((uint32_t)0x00002000) /*!< STM32 Medium-density devices: Write protection of page 52 to 55 */ +#define FLASH_WRProt_Pages56to59 ((uint32_t)0x00004000) /*!< STM32 Medium-density devices: Write protection of page 56 to 59 */ +#define FLASH_WRProt_Pages60to63 ((uint32_t)0x00008000) /*!< STM32 Medium-density devices: Write protection of page 60 to 63 */ +#define FLASH_WRProt_Pages64to67 ((uint32_t)0x00010000) /*!< STM32 Medium-density devices: Write protection of page 64 to 67 */ +#define FLASH_WRProt_Pages68to71 ((uint32_t)0x00020000) /*!< STM32 Medium-density devices: Write protection of page 68 to 71 */ +#define FLASH_WRProt_Pages72to75 ((uint32_t)0x00040000) /*!< STM32 Medium-density devices: Write protection of page 72 to 75 */ +#define FLASH_WRProt_Pages76to79 ((uint32_t)0x00080000) /*!< STM32 Medium-density devices: Write protection of page 76 to 79 */ +#define FLASH_WRProt_Pages80to83 ((uint32_t)0x00100000) /*!< STM32 Medium-density devices: Write protection of page 80 to 83 */ +#define FLASH_WRProt_Pages84to87 ((uint32_t)0x00200000) /*!< STM32 Medium-density devices: Write protection of page 84 to 87 */ +#define FLASH_WRProt_Pages88to91 ((uint32_t)0x00400000) /*!< STM32 Medium-density devices: Write protection of page 88 to 91 */ +#define FLASH_WRProt_Pages92to95 ((uint32_t)0x00800000) /*!< STM32 Medium-density devices: Write protection of page 92 to 95 */ +#define FLASH_WRProt_Pages96to99 ((uint32_t)0x01000000) /*!< STM32 Medium-density devices: Write protection of page 96 to 99 */ +#define FLASH_WRProt_Pages100to103 ((uint32_t)0x02000000) /*!< STM32 Medium-density devices: Write protection of page 100 to 103 */ +#define FLASH_WRProt_Pages104to107 ((uint32_t)0x04000000) /*!< STM32 Medium-density devices: Write protection of page 104 to 107 */ +#define FLASH_WRProt_Pages108to111 ((uint32_t)0x08000000) /*!< STM32 Medium-density devices: Write protection of page 108 to 111 */ +#define FLASH_WRProt_Pages112to115 ((uint32_t)0x10000000) /*!< STM32 Medium-density devices: Write protection of page 112 to 115 */ +#define FLASH_WRProt_Pages116to119 ((uint32_t)0x20000000) /*!< STM32 Medium-density devices: Write protection of page 115 to 119 */ +#define FLASH_WRProt_Pages120to123 ((uint32_t)0x40000000) /*!< STM32 Medium-density devices: Write protection of page 120 to 123 */ +#define FLASH_WRProt_Pages124to127 ((uint32_t)0x80000000) /*!< STM32 Medium-density devices: Write protection of page 124 to 127 */ + +/* Values to be used with STM32 High-density and STM32F10X Connectivity line devices */ +#define FLASH_WRProt_Pages0to1 ((uint32_t)0x00000001) /*!< STM32 High-density, XL-density and Connectivity line devices: + Write protection of page 0 to 1 */ +#define FLASH_WRProt_Pages2to3 ((uint32_t)0x00000002) /*!< STM32 High-density, XL-density and Connectivity line devices: + Write protection of page 2 to 3 */ +#define FLASH_WRProt_Pages4to5 ((uint32_t)0x00000004) /*!< STM32 High-density, XL-density and Connectivity line devices: + Write protection of page 4 to 5 */ +#define FLASH_WRProt_Pages6to7 ((uint32_t)0x00000008) /*!< STM32 High-density, XL-density and Connectivity line devices: + Write protection of page 6 to 7 */ +#define FLASH_WRProt_Pages8to9 ((uint32_t)0x00000010) /*!< STM32 High-density, XL-density and Connectivity line devices: + Write protection of page 8 to 9 */ +#define FLASH_WRProt_Pages10to11 ((uint32_t)0x00000020) /*!< STM32 High-density, XL-density and Connectivity line devices: + Write protection of page 10 to 11 */ +#define FLASH_WRProt_Pages12to13 ((uint32_t)0x00000040) /*!< STM32 High-density, XL-density and Connectivity line devices: + Write protection of page 12 to 13 */ +#define FLASH_WRProt_Pages14to15 ((uint32_t)0x00000080) /*!< STM32 High-density, XL-density and Connectivity line devices: + Write protection of page 14 to 15 */ +#define FLASH_WRProt_Pages16to17 ((uint32_t)0x00000100) /*!< STM32 High-density, XL-density and Connectivity line devices: + Write protection of page 16 to 17 */ +#define FLASH_WRProt_Pages18to19 ((uint32_t)0x00000200) /*!< STM32 High-density, XL-density and Connectivity line devices: + Write protection of page 18 to 19 */ +#define FLASH_WRProt_Pages20to21 ((uint32_t)0x00000400) /*!< STM32 High-density, XL-density and Connectivity line devices: + Write protection of page 20 to 21 */ +#define FLASH_WRProt_Pages22to23 ((uint32_t)0x00000800) /*!< STM32 High-density, XL-density and Connectivity line devices: + Write protection of page 22 to 23 */ +#define FLASH_WRProt_Pages24to25 ((uint32_t)0x00001000) /*!< STM32 High-density, XL-density and Connectivity line devices: + Write protection of page 24 to 25 */ +#define FLASH_WRProt_Pages26to27 ((uint32_t)0x00002000) /*!< STM32 High-density, XL-density and Connectivity line devices: + Write protection of page 26 to 27 */ +#define FLASH_WRProt_Pages28to29 ((uint32_t)0x00004000) /*!< STM32 High-density, XL-density and Connectivity line devices: + Write protection of page 28 to 29 */ +#define FLASH_WRProt_Pages30to31 ((uint32_t)0x00008000) /*!< STM32 High-density, XL-density and Connectivity line devices: + Write protection of page 30 to 31 */ +#define FLASH_WRProt_Pages32to33 ((uint32_t)0x00010000) /*!< STM32 High-density, XL-density and Connectivity line devices: + Write protection of page 32 to 33 */ +#define FLASH_WRProt_Pages34to35 ((uint32_t)0x00020000) /*!< STM32 High-density, XL-density and Connectivity line devices: + Write protection of page 34 to 35 */ +#define FLASH_WRProt_Pages36to37 ((uint32_t)0x00040000) /*!< STM32 High-density, XL-density and Connectivity line devices: + Write protection of page 36 to 37 */ +#define FLASH_WRProt_Pages38to39 ((uint32_t)0x00080000) /*!< STM32 High-density, XL-density and Connectivity line devices: + Write protection of page 38 to 39 */ +#define FLASH_WRProt_Pages40to41 ((uint32_t)0x00100000) /*!< STM32 High-density, XL-density and Connectivity line devices: + Write protection of page 40 to 41 */ +#define FLASH_WRProt_Pages42to43 ((uint32_t)0x00200000) /*!< STM32 High-density, XL-density and Connectivity line devices: + Write protection of page 42 to 43 */ +#define FLASH_WRProt_Pages44to45 ((uint32_t)0x00400000) /*!< STM32 High-density, XL-density and Connectivity line devices: + Write protection of page 44 to 45 */ +#define FLASH_WRProt_Pages46to47 ((uint32_t)0x00800000) /*!< STM32 High-density, XL-density and Connectivity line devices: + Write protection of page 46 to 47 */ +#define FLASH_WRProt_Pages48to49 ((uint32_t)0x01000000) /*!< STM32 High-density, XL-density and Connectivity line devices: + Write protection of page 48 to 49 */ +#define FLASH_WRProt_Pages50to51 ((uint32_t)0x02000000) /*!< STM32 High-density, XL-density and Connectivity line devices: + Write protection of page 50 to 51 */ +#define FLASH_WRProt_Pages52to53 ((uint32_t)0x04000000) /*!< STM32 High-density, XL-density and Connectivity line devices: + Write protection of page 52 to 53 */ +#define FLASH_WRProt_Pages54to55 ((uint32_t)0x08000000) /*!< STM32 High-density, XL-density and Connectivity line devices: + Write protection of page 54 to 55 */ +#define FLASH_WRProt_Pages56to57 ((uint32_t)0x10000000) /*!< STM32 High-density, XL-density and Connectivity line devices: + Write protection of page 56 to 57 */ +#define FLASH_WRProt_Pages58to59 ((uint32_t)0x20000000) /*!< STM32 High-density, XL-density and Connectivity line devices: + Write protection of page 58 to 59 */ +#define FLASH_WRProt_Pages60to61 ((uint32_t)0x40000000) /*!< STM32 High-density, XL-density and Connectivity line devices: + Write protection of page 60 to 61 */ +#define FLASH_WRProt_Pages62to127 ((uint32_t)0x80000000) /*!< STM32 Connectivity line devices: Write protection of page 62 to 127 */ +#define FLASH_WRProt_Pages62to255 ((uint32_t)0x80000000) /*!< STM32 Medium-density devices: Write protection of page 62 to 255 */ +#define FLASH_WRProt_Pages62to511 ((uint32_t)0x80000000) /*!< STM32 XL-density devices: Write protection of page 62 to 511 */ + +#define FLASH_WRProt_AllPages ((uint32_t)0xFFFFFFFF) /*!< Write protection of all Pages */ + +#define IS_FLASH_WRPROT_PAGE(PAGE) (((PAGE) != 0x00000000)) + +#define IS_FLASH_ADDRESS(ADDRESS) (((ADDRESS) >= 0x08000000) && ((ADDRESS) < 0x080FFFFF)) + +#define IS_OB_DATA_ADDRESS(ADDRESS) (((ADDRESS) == 0x1FFFF804) || ((ADDRESS) == 0x1FFFF806)) + +/** + * @} + */ + +/** @defgroup Option_Bytes_IWatchdog + * @{ + */ + +#define OB_IWDG_SW ((uint16_t)0x0001) /*!< Software IWDG selected */ +#define OB_IWDG_HW ((uint16_t)0x0000) /*!< Hardware IWDG selected */ +#define IS_OB_IWDG_SOURCE(SOURCE) (((SOURCE) == OB_IWDG_SW) || ((SOURCE) == OB_IWDG_HW)) + +/** + * @} + */ + +/** @defgroup Option_Bytes_nRST_STOP + * @{ + */ + +#define OB_STOP_NoRST ((uint16_t)0x0002) /*!< No reset generated when entering in STOP */ +#define OB_STOP_RST ((uint16_t)0x0000) /*!< Reset generated when entering in STOP */ +#define IS_OB_STOP_SOURCE(SOURCE) (((SOURCE) == OB_STOP_NoRST) || ((SOURCE) == OB_STOP_RST)) + +/** + * @} + */ + +/** @defgroup Option_Bytes_nRST_STDBY + * @{ + */ + +#define OB_STDBY_NoRST ((uint16_t)0x0004) /*!< No reset generated when entering in STANDBY */ +#define OB_STDBY_RST ((uint16_t)0x0000) /*!< Reset generated when entering in STANDBY */ +#define IS_OB_STDBY_SOURCE(SOURCE) (((SOURCE) == OB_STDBY_NoRST) || ((SOURCE) == OB_STDBY_RST)) + +#ifdef STM32F10X_XL +/** + * @} + */ +/** @defgroup FLASH_Boot + * @{ + */ +#define FLASH_BOOT_Bank1 ((uint16_t)0x0000) /*!< At startup, if boot pins are set in boot from user Flash position + and this parameter is selected the device will boot from Bank1(Default) */ +#define FLASH_BOOT_Bank2 ((uint16_t)0x0001) /*!< At startup, if boot pins are set in boot from user Flash position + and this parameter is selected the device will boot from Bank 2 or Bank 1, + depending on the activation of the bank */ +#define IS_FLASH_BOOT(BOOT) (((BOOT) == FLASH_BOOT_Bank1) || ((BOOT) == FLASH_BOOT_Bank2)) +#endif +/** + * @} + */ +/** @defgroup FLASH_Interrupts + * @{ + */ +#ifdef STM32F10X_XL +#define FLASH_IT_BANK2_ERROR ((uint32_t)0x80000400) /*!< FPEC BANK2 error interrupt source */ +#define FLASH_IT_BANK2_EOP ((uint32_t)0x80001000) /*!< End of FLASH BANK2 Operation Interrupt source */ + +#define FLASH_IT_BANK1_ERROR FLASH_IT_ERROR /*!< FPEC BANK1 error interrupt source */ +#define FLASH_IT_BANK1_EOP FLASH_IT_EOP /*!< End of FLASH BANK1 Operation Interrupt source */ + +#define FLASH_IT_ERROR ((uint32_t)0x00000400) /*!< FPEC BANK1 error interrupt source */ +#define FLASH_IT_EOP ((uint32_t)0x00001000) /*!< End of FLASH BANK1 Operation Interrupt source */ +#define IS_FLASH_IT(IT) ((((IT) & (uint32_t)0x7FFFEBFF) == 0x00000000) && (((IT) != 0x00000000))) +#else +#define FLASH_IT_ERROR ((uint32_t)0x00000400) /*!< FPEC error interrupt source */ +#define FLASH_IT_EOP ((uint32_t)0x00001000) /*!< End of FLASH Operation Interrupt source */ +#define FLASH_IT_BANK1_ERROR FLASH_IT_ERROR /*!< FPEC BANK1 error interrupt source */ +#define FLASH_IT_BANK1_EOP FLASH_IT_EOP /*!< End of FLASH BANK1 Operation Interrupt source */ + +#define IS_FLASH_IT(IT) ((((IT) & (uint32_t)0xFFFFEBFF) == 0x00000000) && (((IT) != 0x00000000))) +#endif + +/** + * @} + */ + +/** @defgroup FLASH_Flags + * @{ + */ +#ifdef STM32F10X_XL +#define FLASH_FLAG_BANK2_BSY ((uint32_t)0x80000001) /*!< FLASH BANK2 Busy flag */ +#define FLASH_FLAG_BANK2_EOP ((uint32_t)0x80000020) /*!< FLASH BANK2 End of Operation flag */ +#define FLASH_FLAG_BANK2_PGERR ((uint32_t)0x80000004) /*!< FLASH BANK2 Program error flag */ +#define FLASH_FLAG_BANK2_WRPRTERR ((uint32_t)0x80000010) /*!< FLASH BANK2 Write protected error flag */ + +#define FLASH_FLAG_BANK1_BSY FLASH_FLAG_BSY /*!< FLASH BANK1 Busy flag*/ +#define FLASH_FLAG_BANK1_EOP FLASH_FLAG_EOP /*!< FLASH BANK1 End of Operation flag */ +#define FLASH_FLAG_BANK1_PGERR FLASH_FLAG_PGERR /*!< FLASH BANK1 Program error flag */ +#define FLASH_FLAG_BANK1_WRPRTERR FLASH_FLAG_WRPRTERR /*!< FLASH BANK1 Write protected error flag */ + +#define FLASH_FLAG_BSY ((uint32_t)0x00000001) /*!< FLASH Busy flag */ +#define FLASH_FLAG_EOP ((uint32_t)0x00000020) /*!< FLASH End of Operation flag */ +#define FLASH_FLAG_PGERR ((uint32_t)0x00000004) /*!< FLASH Program error flag */ +#define FLASH_FLAG_WRPRTERR ((uint32_t)0x00000010) /*!< FLASH Write protected error flag */ +#define FLASH_FLAG_OPTERR ((uint32_t)0x00000001) /*!< FLASH Option Byte error flag */ + +#define IS_FLASH_CLEAR_FLAG(FLAG) ((((FLAG) & (uint32_t)0x7FFFFFCA) == 0x00000000) && ((FLAG) != 0x00000000)) +#define IS_FLASH_GET_FLAG(FLAG) (((FLAG) == FLASH_FLAG_BSY) || ((FLAG) == FLASH_FLAG_EOP) || \ + ((FLAG) == FLASH_FLAG_PGERR) || ((FLAG) == FLASH_FLAG_WRPRTERR) || \ + ((FLAG) == FLASH_FLAG_OPTERR)|| \ + ((FLAG) == FLASH_FLAG_BANK1_BSY) || ((FLAG) == FLASH_FLAG_BANK1_EOP) || \ + ((FLAG) == FLASH_FLAG_BANK1_PGERR) || ((FLAG) == FLASH_FLAG_BANK1_WRPRTERR) || \ + ((FLAG) == FLASH_FLAG_BANK2_BSY) || ((FLAG) == FLASH_FLAG_BANK2_EOP) || \ + ((FLAG) == FLASH_FLAG_BANK2_PGERR) || ((FLAG) == FLASH_FLAG_BANK2_WRPRTERR)) +#else +#define FLASH_FLAG_BSY ((uint32_t)0x00000001) /*!< FLASH Busy flag */ +#define FLASH_FLAG_EOP ((uint32_t)0x00000020) /*!< FLASH End of Operation flag */ +#define FLASH_FLAG_PGERR ((uint32_t)0x00000004) /*!< FLASH Program error flag */ +#define FLASH_FLAG_WRPRTERR ((uint32_t)0x00000010) /*!< FLASH Write protected error flag */ +#define FLASH_FLAG_OPTERR ((uint32_t)0x00000001) /*!< FLASH Option Byte error flag */ + +#define FLASH_FLAG_BANK1_BSY FLASH_FLAG_BSY /*!< FLASH BANK1 Busy flag*/ +#define FLASH_FLAG_BANK1_EOP FLASH_FLAG_EOP /*!< FLASH BANK1 End of Operation flag */ +#define FLASH_FLAG_BANK1_PGERR FLASH_FLAG_PGERR /*!< FLASH BANK1 Program error flag */ +#define FLASH_FLAG_BANK1_WRPRTERR FLASH_FLAG_WRPRTERR /*!< FLASH BANK1 Write protected error flag */ + +#define IS_FLASH_CLEAR_FLAG(FLAG) ((((FLAG) & (uint32_t)0xFFFFFFCA) == 0x00000000) && ((FLAG) != 0x00000000)) +#define IS_FLASH_GET_FLAG(FLAG) (((FLAG) == FLASH_FLAG_BSY) || ((FLAG) == FLASH_FLAG_EOP) || \ + ((FLAG) == FLASH_FLAG_PGERR) || ((FLAG) == FLASH_FLAG_WRPRTERR) || \ + ((FLAG) == FLASH_FLAG_BANK1_BSY) || ((FLAG) == FLASH_FLAG_BANK1_EOP) || \ + ((FLAG) == FLASH_FLAG_BANK1_PGERR) || ((FLAG) == FLASH_FLAG_BANK1_WRPRTERR) || \ + ((FLAG) == FLASH_FLAG_OPTERR)) +#endif + +/** + * @} + */ + +/** + * @} + */ + +/** @defgroup FLASH_Exported_Macros + * @{ + */ + +/** + * @} + */ + +/** @defgroup FLASH_Exported_Functions + * @{ + */ + +/*------------ Functions used for all STM32F10x devices -----*/ +void FLASH_SetLatency(uint32_t FLASH_Latency); +void FLASH_HalfCycleAccessCmd(uint32_t FLASH_HalfCycleAccess); +void FLASH_PrefetchBufferCmd(uint32_t FLASH_PrefetchBuffer); +void FLASH_Unlock(void); +void FLASH_Lock(void); +FLASH_Status FLASH_ErasePage(uint32_t Page_Address); +FLASH_Status FLASH_EraseAllPages(void); +FLASH_Status FLASH_EraseOptionBytes(void); +FLASH_Status FLASH_ProgramWord(uint32_t Address, uint32_t Data); +FLASH_Status FLASH_ProgramHalfWord(uint32_t Address, uint16_t Data); +FLASH_Status FLASH_ProgramOptionByteData(uint32_t Address, uint8_t Data); +FLASH_Status FLASH_EnableWriteProtection(uint32_t FLASH_Pages); +FLASH_Status FLASH_ReadOutProtection(FunctionalState NewState); +FLASH_Status FLASH_UserOptionByteConfig(uint16_t OB_IWDG, uint16_t OB_STOP, uint16_t OB_STDBY); +uint32_t FLASH_GetUserOptionByte(void); +uint32_t FLASH_GetWriteProtectionOptionByte(void); +FlagStatus FLASH_GetReadOutProtectionStatus(void); +FlagStatus FLASH_GetPrefetchBufferStatus(void); +void FLASH_ITConfig(uint32_t FLASH_IT, FunctionalState NewState); +FlagStatus FLASH_GetFlagStatus(uint32_t FLASH_FLAG); +void FLASH_ClearFlag(uint32_t FLASH_FLAG); +FLASH_Status FLASH_GetStatus(void); +FLASH_Status FLASH_WaitForLastOperation(uint32_t Timeout); + +/*------------ New function used for all STM32F10x devices -----*/ +void FLASH_UnlockBank1(void); +void FLASH_LockBank1(void); +FLASH_Status FLASH_EraseAllBank1Pages(void); +FLASH_Status FLASH_GetBank1Status(void); +FLASH_Status FLASH_WaitForLastBank1Operation(uint32_t Timeout); + +#ifdef STM32F10X_XL +/*---- New Functions used only with STM32F10x_XL density devices -----*/ +void FLASH_UnlockBank2(void); +void FLASH_LockBank2(void); +FLASH_Status FLASH_EraseAllBank2Pages(void); +FLASH_Status FLASH_GetBank2Status(void); +FLASH_Status FLASH_WaitForLastBank2Operation(uint32_t Timeout); +FLASH_Status FLASH_BootConfig(uint16_t FLASH_BOOT); +#endif + +#ifdef __cplusplus +} +#endif + +#endif /* __STM32F10x_FLASH_H */ +/** + * @} + */ + +/** + * @} + */ + +/** + * @} + */ + +/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ diff --git a/Libraries/STM32F10x_StdPeriph_Driver/inc/stm32f10x_fsmc.h b/Libraries/STM32F10x_StdPeriph_Driver/inc/stm32f10x_fsmc.h new file mode 100644 index 0000000..1304d74 --- /dev/null +++ b/Libraries/STM32F10x_StdPeriph_Driver/inc/stm32f10x_fsmc.h @@ -0,0 +1,739 @@ +/** + ****************************************************************************** + * @file stm32f10x_fsmc.h + * @author MCD Application Team + * @version V3.6.1 + * @date 05-March-2012 + * @brief This file contains all the functions prototypes for the FSMC firmware + * library. + ****************************************************************************** + * @attention + * + *

    © COPYRIGHT 2012 STMicroelectronics

    + * + * Licensed under MCD-ST Liberty SW License Agreement V2, (the "License"); + * You may not use this file except in compliance with the License. + * You may obtain a copy of the License at: + * + * http://www.st.com/software_license_agreement_liberty_v2 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, + * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + * + ****************************************************************************** + */ + +/* Define to prevent recursive inclusion -------------------------------------*/ +#ifndef __STM32F10x_FSMC_H +#define __STM32F10x_FSMC_H + +#ifdef __cplusplus + extern "C" { +#endif + +/* Includes ------------------------------------------------------------------*/ +#include "stm32f10x.h" + +/** @addtogroup STM32F10x_StdPeriph_Driver + * @{ + */ + +/** @addtogroup FSMC + * @{ + */ + +/** @defgroup FSMC_Exported_Types + * @{ + */ + +/** + * @brief Timing parameters For NOR/SRAM Banks + */ + +typedef struct +{ + uint32_t FSMC_AddressSetupTime; /*!< Defines the number of HCLK cycles to configure + the duration of the address setup time. + This parameter can be a value between 0 and 0xF. + @note: It is not used with synchronous NOR Flash memories. */ + + uint32_t FSMC_AddressHoldTime; /*!< Defines the number of HCLK cycles to configure + the duration of the address hold time. + This parameter can be a value between 0 and 0xF. + @note: It is not used with synchronous NOR Flash memories.*/ + + uint32_t FSMC_DataSetupTime; /*!< Defines the number of HCLK cycles to configure + the duration of the data setup time. + This parameter can be a value between 0 and 0xFF. + @note: It is used for SRAMs, ROMs and asynchronous multiplexed NOR Flash memories. */ + + uint32_t FSMC_BusTurnAroundDuration; /*!< Defines the number of HCLK cycles to configure + the duration of the bus turnaround. + This parameter can be a value between 0 and 0xF. + @note: It is only used for multiplexed NOR Flash memories. */ + + uint32_t FSMC_CLKDivision; /*!< Defines the period of CLK clock output signal, expressed in number of HCLK cycles. + This parameter can be a value between 1 and 0xF. + @note: This parameter is not used for asynchronous NOR Flash, SRAM or ROM accesses. */ + + uint32_t FSMC_DataLatency; /*!< Defines the number of memory clock cycles to issue + to the memory before getting the first data. + The value of this parameter depends on the memory type as shown below: + - It must be set to 0 in case of a CRAM + - It is don't care in asynchronous NOR, SRAM or ROM accesses + - It may assume a value between 0 and 0xF in NOR Flash memories + with synchronous burst mode enable */ + + uint32_t FSMC_AccessMode; /*!< Specifies the asynchronous access mode. + This parameter can be a value of @ref FSMC_Access_Mode */ +}FSMC_NORSRAMTimingInitTypeDef; + +/** + * @brief FSMC NOR/SRAM Init structure definition + */ + +typedef struct +{ + uint32_t FSMC_Bank; /*!< Specifies the NOR/SRAM memory bank that will be used. + This parameter can be a value of @ref FSMC_NORSRAM_Bank */ + + uint32_t FSMC_DataAddressMux; /*!< Specifies whether the address and data values are + multiplexed on the databus or not. + This parameter can be a value of @ref FSMC_Data_Address_Bus_Multiplexing */ + + uint32_t FSMC_MemoryType; /*!< Specifies the type of external memory attached to + the corresponding memory bank. + This parameter can be a value of @ref FSMC_Memory_Type */ + + uint32_t FSMC_MemoryDataWidth; /*!< Specifies the external memory device width. + This parameter can be a value of @ref FSMC_Data_Width */ + + uint32_t FSMC_BurstAccessMode; /*!< Enables or disables the burst access mode for Flash memory, + valid only with synchronous burst Flash memories. + This parameter can be a value of @ref FSMC_Burst_Access_Mode */ + + uint32_t FSMC_AsynchronousWait; /*!< Enables or disables wait signal during asynchronous transfers, + valid only with asynchronous Flash memories. + This parameter can be a value of @ref FSMC_AsynchronousWait */ + + uint32_t FSMC_WaitSignalPolarity; /*!< Specifies the wait signal polarity, valid only when accessing + the Flash memory in burst mode. + This parameter can be a value of @ref FSMC_Wait_Signal_Polarity */ + + uint32_t FSMC_WrapMode; /*!< Enables or disables the Wrapped burst access mode for Flash + memory, valid only when accessing Flash memories in burst mode. + This parameter can be a value of @ref FSMC_Wrap_Mode */ + + uint32_t FSMC_WaitSignalActive; /*!< Specifies if the wait signal is asserted by the memory one + clock cycle before the wait state or during the wait state, + valid only when accessing memories in burst mode. + This parameter can be a value of @ref FSMC_Wait_Timing */ + + uint32_t FSMC_WriteOperation; /*!< Enables or disables the write operation in the selected bank by the FSMC. + This parameter can be a value of @ref FSMC_Write_Operation */ + + uint32_t FSMC_WaitSignal; /*!< Enables or disables the wait-state insertion via wait + signal, valid for Flash memory access in burst mode. + This parameter can be a value of @ref FSMC_Wait_Signal */ + + uint32_t FSMC_ExtendedMode; /*!< Enables or disables the extended mode. + This parameter can be a value of @ref FSMC_Extended_Mode */ + + uint32_t FSMC_WriteBurst; /*!< Enables or disables the write burst operation. + This parameter can be a value of @ref FSMC_Write_Burst */ + + FSMC_NORSRAMTimingInitTypeDef* FSMC_ReadWriteTimingStruct; /*!< Timing Parameters for write and read access if the ExtendedMode is not used*/ + + FSMC_NORSRAMTimingInitTypeDef* FSMC_WriteTimingStruct; /*!< Timing Parameters for write access if the ExtendedMode is used*/ +}FSMC_NORSRAMInitTypeDef; + +/** + * @brief Timing parameters For FSMC NAND and PCCARD Banks + */ + +typedef struct +{ + uint32_t FSMC_SetupTime; /*!< Defines the number of HCLK cycles to setup address before + the command assertion for NAND-Flash read or write access + to common/Attribute or I/O memory space (depending on + the memory space timing to be configured). + This parameter can be a value between 0 and 0xFF.*/ + + uint32_t FSMC_WaitSetupTime; /*!< Defines the minimum number of HCLK cycles to assert the + command for NAND-Flash read or write access to + common/Attribute or I/O memory space (depending on the + memory space timing to be configured). + This parameter can be a number between 0x00 and 0xFF */ + + uint32_t FSMC_HoldSetupTime; /*!< Defines the number of HCLK clock cycles to hold address + (and data for write access) after the command deassertion + for NAND-Flash read or write access to common/Attribute + or I/O memory space (depending on the memory space timing + to be configured). + This parameter can be a number between 0x00 and 0xFF */ + + uint32_t FSMC_HiZSetupTime; /*!< Defines the number of HCLK clock cycles during which the + databus is kept in HiZ after the start of a NAND-Flash + write access to common/Attribute or I/O memory space (depending + on the memory space timing to be configured). + This parameter can be a number between 0x00 and 0xFF */ +}FSMC_NAND_PCCARDTimingInitTypeDef; + +/** + * @brief FSMC NAND Init structure definition + */ + +typedef struct +{ + uint32_t FSMC_Bank; /*!< Specifies the NAND memory bank that will be used. + This parameter can be a value of @ref FSMC_NAND_Bank */ + + uint32_t FSMC_Waitfeature; /*!< Enables or disables the Wait feature for the NAND Memory Bank. + This parameter can be any value of @ref FSMC_Wait_feature */ + + uint32_t FSMC_MemoryDataWidth; /*!< Specifies the external memory device width. + This parameter can be any value of @ref FSMC_Data_Width */ + + uint32_t FSMC_ECC; /*!< Enables or disables the ECC computation. + This parameter can be any value of @ref FSMC_ECC */ + + uint32_t FSMC_ECCPageSize; /*!< Defines the page size for the extended ECC. + This parameter can be any value of @ref FSMC_ECC_Page_Size */ + + uint32_t FSMC_TCLRSetupTime; /*!< Defines the number of HCLK cycles to configure the + delay between CLE low and RE low. + This parameter can be a value between 0 and 0xFF. */ + + uint32_t FSMC_TARSetupTime; /*!< Defines the number of HCLK cycles to configure the + delay between ALE low and RE low. + This parameter can be a number between 0x0 and 0xFF */ + + FSMC_NAND_PCCARDTimingInitTypeDef* FSMC_CommonSpaceTimingStruct; /*!< FSMC Common Space Timing */ + + FSMC_NAND_PCCARDTimingInitTypeDef* FSMC_AttributeSpaceTimingStruct; /*!< FSMC Attribute Space Timing */ +}FSMC_NANDInitTypeDef; + +/** + * @brief FSMC PCCARD Init structure definition + */ + +typedef struct +{ + uint32_t FSMC_Waitfeature; /*!< Enables or disables the Wait feature for the Memory Bank. + This parameter can be any value of @ref FSMC_Wait_feature */ + + uint32_t FSMC_TCLRSetupTime; /*!< Defines the number of HCLK cycles to configure the + delay between CLE low and RE low. + This parameter can be a value between 0 and 0xFF. */ + + uint32_t FSMC_TARSetupTime; /*!< Defines the number of HCLK cycles to configure the + delay between ALE low and RE low. + This parameter can be a number between 0x0 and 0xFF */ + + + FSMC_NAND_PCCARDTimingInitTypeDef* FSMC_CommonSpaceTimingStruct; /*!< FSMC Common Space Timing */ + + FSMC_NAND_PCCARDTimingInitTypeDef* FSMC_AttributeSpaceTimingStruct; /*!< FSMC Attribute Space Timing */ + + FSMC_NAND_PCCARDTimingInitTypeDef* FSMC_IOSpaceTimingStruct; /*!< FSMC IO Space Timing */ +}FSMC_PCCARDInitTypeDef; + +/** + * @} + */ + +/** @defgroup FSMC_Exported_Constants + * @{ + */ + +/** @defgroup FSMC_NORSRAM_Bank + * @{ + */ +#define FSMC_Bank1_NORSRAM1 ((uint32_t)0x00000000) +#define FSMC_Bank1_NORSRAM2 ((uint32_t)0x00000002) +#define FSMC_Bank1_NORSRAM3 ((uint32_t)0x00000004) +#define FSMC_Bank1_NORSRAM4 ((uint32_t)0x00000006) +/** + * @} + */ + +/** @defgroup FSMC_NAND_Bank + * @{ + */ +#define FSMC_Bank2_NAND ((uint32_t)0x00000010) +#define FSMC_Bank3_NAND ((uint32_t)0x00000100) +/** + * @} + */ + +/** @defgroup FSMC_PCCARD_Bank + * @{ + */ +#define FSMC_Bank4_PCCARD ((uint32_t)0x00001000) +/** + * @} + */ + +#define IS_FSMC_NORSRAM_BANK(BANK) (((BANK) == FSMC_Bank1_NORSRAM1) || \ + ((BANK) == FSMC_Bank1_NORSRAM2) || \ + ((BANK) == FSMC_Bank1_NORSRAM3) || \ + ((BANK) == FSMC_Bank1_NORSRAM4)) + +#define IS_FSMC_NAND_BANK(BANK) (((BANK) == FSMC_Bank2_NAND) || \ + ((BANK) == FSMC_Bank3_NAND)) + +#define IS_FSMC_GETFLAG_BANK(BANK) (((BANK) == FSMC_Bank2_NAND) || \ + ((BANK) == FSMC_Bank3_NAND) || \ + ((BANK) == FSMC_Bank4_PCCARD)) + +#define IS_FSMC_IT_BANK(BANK) (((BANK) == FSMC_Bank2_NAND) || \ + ((BANK) == FSMC_Bank3_NAND) || \ + ((BANK) == FSMC_Bank4_PCCARD)) + +/** @defgroup NOR_SRAM_Controller + * @{ + */ + +/** @defgroup FSMC_Data_Address_Bus_Multiplexing + * @{ + */ + +#define FSMC_DataAddressMux_Disable ((uint32_t)0x00000000) +#define FSMC_DataAddressMux_Enable ((uint32_t)0x00000002) +#define IS_FSMC_MUX(MUX) (((MUX) == FSMC_DataAddressMux_Disable) || \ + ((MUX) == FSMC_DataAddressMux_Enable)) + +/** + * @} + */ + +/** @defgroup FSMC_Memory_Type + * @{ + */ + +#define FSMC_MemoryType_SRAM ((uint32_t)0x00000000) +#define FSMC_MemoryType_PSRAM ((uint32_t)0x00000004) +#define FSMC_MemoryType_NOR ((uint32_t)0x00000008) +#define IS_FSMC_MEMORY(MEMORY) (((MEMORY) == FSMC_MemoryType_SRAM) || \ + ((MEMORY) == FSMC_MemoryType_PSRAM)|| \ + ((MEMORY) == FSMC_MemoryType_NOR)) + +/** + * @} + */ + +/** @defgroup FSMC_Data_Width + * @{ + */ + +#define FSMC_MemoryDataWidth_8b ((uint32_t)0x00000000) +#define FSMC_MemoryDataWidth_16b ((uint32_t)0x00000010) +#define IS_FSMC_MEMORY_WIDTH(WIDTH) (((WIDTH) == FSMC_MemoryDataWidth_8b) || \ + ((WIDTH) == FSMC_MemoryDataWidth_16b)) + +/** + * @} + */ + +/** @defgroup FSMC_Burst_Access_Mode + * @{ + */ + +#define FSMC_BurstAccessMode_Disable ((uint32_t)0x00000000) +#define FSMC_BurstAccessMode_Enable ((uint32_t)0x00000100) +#define IS_FSMC_BURSTMODE(STATE) (((STATE) == FSMC_BurstAccessMode_Disable) || \ + ((STATE) == FSMC_BurstAccessMode_Enable)) +/** + * @} + */ + +/** @defgroup FSMC_AsynchronousWait + * @{ + */ +#define FSMC_AsynchronousWait_Disable ((uint32_t)0x00000000) +#define FSMC_AsynchronousWait_Enable ((uint32_t)0x00008000) +#define IS_FSMC_ASYNWAIT(STATE) (((STATE) == FSMC_AsynchronousWait_Disable) || \ + ((STATE) == FSMC_AsynchronousWait_Enable)) + +/** + * @} + */ + +/** @defgroup FSMC_Wait_Signal_Polarity + * @{ + */ + +#define FSMC_WaitSignalPolarity_Low ((uint32_t)0x00000000) +#define FSMC_WaitSignalPolarity_High ((uint32_t)0x00000200) +#define IS_FSMC_WAIT_POLARITY(POLARITY) (((POLARITY) == FSMC_WaitSignalPolarity_Low) || \ + ((POLARITY) == FSMC_WaitSignalPolarity_High)) + +/** + * @} + */ + +/** @defgroup FSMC_Wrap_Mode + * @{ + */ + +#define FSMC_WrapMode_Disable ((uint32_t)0x00000000) +#define FSMC_WrapMode_Enable ((uint32_t)0x00000400) +#define IS_FSMC_WRAP_MODE(MODE) (((MODE) == FSMC_WrapMode_Disable) || \ + ((MODE) == FSMC_WrapMode_Enable)) + +/** + * @} + */ + +/** @defgroup FSMC_Wait_Timing + * @{ + */ + +#define FSMC_WaitSignalActive_BeforeWaitState ((uint32_t)0x00000000) +#define FSMC_WaitSignalActive_DuringWaitState ((uint32_t)0x00000800) +#define IS_FSMC_WAIT_SIGNAL_ACTIVE(ACTIVE) (((ACTIVE) == FSMC_WaitSignalActive_BeforeWaitState) || \ + ((ACTIVE) == FSMC_WaitSignalActive_DuringWaitState)) + +/** + * @} + */ + +/** @defgroup FSMC_Write_Operation + * @{ + */ + +#define FSMC_WriteOperation_Disable ((uint32_t)0x00000000) +#define FSMC_WriteOperation_Enable ((uint32_t)0x00001000) +#define IS_FSMC_WRITE_OPERATION(OPERATION) (((OPERATION) == FSMC_WriteOperation_Disable) || \ + ((OPERATION) == FSMC_WriteOperation_Enable)) + +/** + * @} + */ + +/** @defgroup FSMC_Wait_Signal + * @{ + */ + +#define FSMC_WaitSignal_Disable ((uint32_t)0x00000000) +#define FSMC_WaitSignal_Enable ((uint32_t)0x00002000) +#define IS_FSMC_WAITE_SIGNAL(SIGNAL) (((SIGNAL) == FSMC_WaitSignal_Disable) || \ + ((SIGNAL) == FSMC_WaitSignal_Enable)) +/** + * @} + */ + +/** @defgroup FSMC_Extended_Mode + * @{ + */ + +#define FSMC_ExtendedMode_Disable ((uint32_t)0x00000000) +#define FSMC_ExtendedMode_Enable ((uint32_t)0x00004000) + +#define IS_FSMC_EXTENDED_MODE(MODE) (((MODE) == FSMC_ExtendedMode_Disable) || \ + ((MODE) == FSMC_ExtendedMode_Enable)) + +/** + * @} + */ + +/** @defgroup FSMC_Write_Burst + * @{ + */ + +#define FSMC_WriteBurst_Disable ((uint32_t)0x00000000) +#define FSMC_WriteBurst_Enable ((uint32_t)0x00080000) +#define IS_FSMC_WRITE_BURST(BURST) (((BURST) == FSMC_WriteBurst_Disable) || \ + ((BURST) == FSMC_WriteBurst_Enable)) +/** + * @} + */ + +/** @defgroup FSMC_Address_Setup_Time + * @{ + */ + +#define IS_FSMC_ADDRESS_SETUP_TIME(TIME) ((TIME) <= 0xF) + +/** + * @} + */ + +/** @defgroup FSMC_Address_Hold_Time + * @{ + */ + +#define IS_FSMC_ADDRESS_HOLD_TIME(TIME) ((TIME) <= 0xF) + +/** + * @} + */ + +/** @defgroup FSMC_Data_Setup_Time + * @{ + */ + +#define IS_FSMC_DATASETUP_TIME(TIME) (((TIME) > 0) && ((TIME) <= 0xFF)) + +/** + * @} + */ + +/** @defgroup FSMC_Bus_Turn_around_Duration + * @{ + */ + +#define IS_FSMC_TURNAROUND_TIME(TIME) ((TIME) <= 0xF) + +/** + * @} + */ + +/** @defgroup FSMC_CLK_Division + * @{ + */ + +#define IS_FSMC_CLK_DIV(DIV) ((DIV) <= 0xF) + +/** + * @} + */ + +/** @defgroup FSMC_Data_Latency + * @{ + */ + +#define IS_FSMC_DATA_LATENCY(LATENCY) ((LATENCY) <= 0xF) + +/** + * @} + */ + +/** @defgroup FSMC_Access_Mode + * @{ + */ + +#define FSMC_AccessMode_A ((uint32_t)0x00000000) +#define FSMC_AccessMode_B ((uint32_t)0x10000000) +#define FSMC_AccessMode_C ((uint32_t)0x20000000) +#define FSMC_AccessMode_D ((uint32_t)0x30000000) +#define IS_FSMC_ACCESS_MODE(MODE) (((MODE) == FSMC_AccessMode_A) || \ + ((MODE) == FSMC_AccessMode_B) || \ + ((MODE) == FSMC_AccessMode_C) || \ + ((MODE) == FSMC_AccessMode_D)) + +/** + * @} + */ + +/** + * @} + */ + +/** @defgroup NAND_PCCARD_Controller + * @{ + */ + +/** @defgroup FSMC_Wait_feature + * @{ + */ + +#define FSMC_Waitfeature_Disable ((uint32_t)0x00000000) +#define FSMC_Waitfeature_Enable ((uint32_t)0x00000002) +#define IS_FSMC_WAIT_FEATURE(FEATURE) (((FEATURE) == FSMC_Waitfeature_Disable) || \ + ((FEATURE) == FSMC_Waitfeature_Enable)) + +/** + * @} + */ + + +/** @defgroup FSMC_ECC + * @{ + */ + +#define FSMC_ECC_Disable ((uint32_t)0x00000000) +#define FSMC_ECC_Enable ((uint32_t)0x00000040) +#define IS_FSMC_ECC_STATE(STATE) (((STATE) == FSMC_ECC_Disable) || \ + ((STATE) == FSMC_ECC_Enable)) + +/** + * @} + */ + +/** @defgroup FSMC_ECC_Page_Size + * @{ + */ + +#define FSMC_ECCPageSize_256Bytes ((uint32_t)0x00000000) +#define FSMC_ECCPageSize_512Bytes ((uint32_t)0x00020000) +#define FSMC_ECCPageSize_1024Bytes ((uint32_t)0x00040000) +#define FSMC_ECCPageSize_2048Bytes ((uint32_t)0x00060000) +#define FSMC_ECCPageSize_4096Bytes ((uint32_t)0x00080000) +#define FSMC_ECCPageSize_8192Bytes ((uint32_t)0x000A0000) +#define IS_FSMC_ECCPAGE_SIZE(SIZE) (((SIZE) == FSMC_ECCPageSize_256Bytes) || \ + ((SIZE) == FSMC_ECCPageSize_512Bytes) || \ + ((SIZE) == FSMC_ECCPageSize_1024Bytes) || \ + ((SIZE) == FSMC_ECCPageSize_2048Bytes) || \ + ((SIZE) == FSMC_ECCPageSize_4096Bytes) || \ + ((SIZE) == FSMC_ECCPageSize_8192Bytes)) + +/** + * @} + */ + +/** @defgroup FSMC_TCLR_Setup_Time + * @{ + */ + +#define IS_FSMC_TCLR_TIME(TIME) ((TIME) <= 0xFF) + +/** + * @} + */ + +/** @defgroup FSMC_TAR_Setup_Time + * @{ + */ + +#define IS_FSMC_TAR_TIME(TIME) ((TIME) <= 0xFF) + +/** + * @} + */ + +/** @defgroup FSMC_Setup_Time + * @{ + */ + +#define IS_FSMC_SETUP_TIME(TIME) ((TIME) <= 0xFF) + +/** + * @} + */ + +/** @defgroup FSMC_Wait_Setup_Time + * @{ + */ + +#define IS_FSMC_WAIT_TIME(TIME) ((TIME) <= 0xFF) + +/** + * @} + */ + +/** @defgroup FSMC_Hold_Setup_Time + * @{ + */ + +#define IS_FSMC_HOLD_TIME(TIME) ((TIME) <= 0xFF) + +/** + * @} + */ + +/** @defgroup FSMC_HiZ_Setup_Time + * @{ + */ + +#define IS_FSMC_HIZ_TIME(TIME) ((TIME) <= 0xFF) + +/** + * @} + */ + +/** @defgroup FSMC_Interrupt_sources + * @{ + */ + +#define FSMC_IT_RisingEdge ((uint32_t)0x00000008) +#define FSMC_IT_Level ((uint32_t)0x00000010) +#define FSMC_IT_FallingEdge ((uint32_t)0x00000020) +#define IS_FSMC_IT(IT) ((((IT) & (uint32_t)0xFFFFFFC7) == 0x00000000) && ((IT) != 0x00000000)) +#define IS_FSMC_GET_IT(IT) (((IT) == FSMC_IT_RisingEdge) || \ + ((IT) == FSMC_IT_Level) || \ + ((IT) == FSMC_IT_FallingEdge)) +/** + * @} + */ + +/** @defgroup FSMC_Flags + * @{ + */ + +#define FSMC_FLAG_RisingEdge ((uint32_t)0x00000001) +#define FSMC_FLAG_Level ((uint32_t)0x00000002) +#define FSMC_FLAG_FallingEdge ((uint32_t)0x00000004) +#define FSMC_FLAG_FEMPT ((uint32_t)0x00000040) +#define IS_FSMC_GET_FLAG(FLAG) (((FLAG) == FSMC_FLAG_RisingEdge) || \ + ((FLAG) == FSMC_FLAG_Level) || \ + ((FLAG) == FSMC_FLAG_FallingEdge) || \ + ((FLAG) == FSMC_FLAG_FEMPT)) + +#define IS_FSMC_CLEAR_FLAG(FLAG) ((((FLAG) & (uint32_t)0xFFFFFFF8) == 0x00000000) && ((FLAG) != 0x00000000)) + +/** + * @} + */ + +/** + * @} + */ + +/** + * @} + */ + +/** @defgroup FSMC_Exported_Macros + * @{ + */ + +/** + * @} + */ + +/** @defgroup FSMC_Exported_Functions + * @{ + */ + +void FSMC_NORSRAMDeInit(uint32_t FSMC_Bank); +void FSMC_NANDDeInit(uint32_t FSMC_Bank); +void FSMC_PCCARDDeInit(void); +void FSMC_NORSRAMInit(FSMC_NORSRAMInitTypeDef* FSMC_NORSRAMInitStruct); +void FSMC_NANDInit(FSMC_NANDInitTypeDef* FSMC_NANDInitStruct); +void FSMC_PCCARDInit(FSMC_PCCARDInitTypeDef* FSMC_PCCARDInitStruct); +void FSMC_NORSRAMStructInit(FSMC_NORSRAMInitTypeDef* FSMC_NORSRAMInitStruct); +void FSMC_NANDStructInit(FSMC_NANDInitTypeDef* FSMC_NANDInitStruct); +void FSMC_PCCARDStructInit(FSMC_PCCARDInitTypeDef* FSMC_PCCARDInitStruct); +void FSMC_NORSRAMCmd(uint32_t FSMC_Bank, FunctionalState NewState); +void FSMC_NANDCmd(uint32_t FSMC_Bank, FunctionalState NewState); +void FSMC_PCCARDCmd(FunctionalState NewState); +void FSMC_NANDECCCmd(uint32_t FSMC_Bank, FunctionalState NewState); +uint32_t FSMC_GetECC(uint32_t FSMC_Bank); +void FSMC_ITConfig(uint32_t FSMC_Bank, uint32_t FSMC_IT, FunctionalState NewState); +FlagStatus FSMC_GetFlagStatus(uint32_t FSMC_Bank, uint32_t FSMC_FLAG); +void FSMC_ClearFlag(uint32_t FSMC_Bank, uint32_t FSMC_FLAG); +ITStatus FSMC_GetITStatus(uint32_t FSMC_Bank, uint32_t FSMC_IT); +void FSMC_ClearITPendingBit(uint32_t FSMC_Bank, uint32_t FSMC_IT); + +#ifdef __cplusplus +} +#endif + +#endif /*__STM32F10x_FSMC_H */ +/** + * @} + */ + +/** + * @} + */ + +/** + * @} + */ + +/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ diff --git a/Libraries/STM32F10x_StdPeriph_Driver/inc/stm32f10x_gpio.h b/Libraries/STM32F10x_StdPeriph_Driver/inc/stm32f10x_gpio.h new file mode 100644 index 0000000..f67cc0e --- /dev/null +++ b/Libraries/STM32F10x_StdPeriph_Driver/inc/stm32f10x_gpio.h @@ -0,0 +1,391 @@ +/** + ****************************************************************************** + * @file stm32f10x_gpio.h + * @author MCD Application Team + * @version V3.6.1 + * @date 05-March-2012 + * @brief This file contains all the functions prototypes for the GPIO + * firmware library. + ****************************************************************************** + * @attention + * + *

    © COPYRIGHT 2012 STMicroelectronics

    + * + * Licensed under MCD-ST Liberty SW License Agreement V2, (the "License"); + * You may not use this file except in compliance with the License. + * You may obtain a copy of the License at: + * + * http://www.st.com/software_license_agreement_liberty_v2 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, + * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + * + ****************************************************************************** + */ + +/* Define to prevent recursive inclusion -------------------------------------*/ +#ifndef __STM32F10x_GPIO_H +#define __STM32F10x_GPIO_H + +#ifdef __cplusplus + extern "C" { +#endif + +/* Includes ------------------------------------------------------------------*/ +#include "stm32f10x.h" + +/** @addtogroup STM32F10x_StdPeriph_Driver + * @{ + */ + +/** @addtogroup GPIO + * @{ + */ + +/** @defgroup GPIO_Exported_Types + * @{ + */ + +#define IS_GPIO_ALL_PERIPH(PERIPH) (((PERIPH) == GPIOA) || \ + ((PERIPH) == GPIOB) || \ + ((PERIPH) == GPIOC) || \ + ((PERIPH) == GPIOD) || \ + ((PERIPH) == GPIOE) || \ + ((PERIPH) == GPIOF) || \ + ((PERIPH) == GPIOG)) + +/** + * @brief Output Maximum frequency selection + */ + +typedef enum +{ + GPIO_Speed_10MHz = 1, + GPIO_Speed_2MHz, + GPIO_Speed_50MHz +}GPIOSpeed_TypeDef; +#define IS_GPIO_SPEED(SPEED) (((SPEED) == GPIO_Speed_10MHz) || ((SPEED) == GPIO_Speed_2MHz) || \ + ((SPEED) == GPIO_Speed_50MHz)) + +/** + * @brief Configuration Mode enumeration + */ + +typedef enum +{ GPIO_Mode_AIN = 0x0, + GPIO_Mode_IN_FLOATING = 0x04, + GPIO_Mode_IPD = 0x28, + GPIO_Mode_IPU = 0x48, + GPIO_Mode_Out_OD = 0x14, + GPIO_Mode_Out_PP = 0x10, + GPIO_Mode_AF_OD = 0x1C, + GPIO_Mode_AF_PP = 0x18 +}GPIOMode_TypeDef; + +#define IS_GPIO_MODE(MODE) (((MODE) == GPIO_Mode_AIN) || ((MODE) == GPIO_Mode_IN_FLOATING) || \ + ((MODE) == GPIO_Mode_IPD) || ((MODE) == GPIO_Mode_IPU) || \ + ((MODE) == GPIO_Mode_Out_OD) || ((MODE) == GPIO_Mode_Out_PP) || \ + ((MODE) == GPIO_Mode_AF_OD) || ((MODE) == GPIO_Mode_AF_PP)) + +/** + * @brief GPIO Init structure definition + */ + +typedef struct +{ + uint16_t GPIO_Pin; /*!< Specifies the GPIO pins to be configured. + This parameter can be any value of @ref GPIO_pins_define */ + + GPIOSpeed_TypeDef GPIO_Speed; /*!< Specifies the speed for the selected pins. + This parameter can be a value of @ref GPIOSpeed_TypeDef */ + + GPIOMode_TypeDef GPIO_Mode; /*!< Specifies the operating mode for the selected pins. + This parameter can be a value of @ref GPIOMode_TypeDef */ +}GPIO_InitTypeDef; + + +/** + * @brief Bit_SET and Bit_RESET enumeration + */ + +typedef enum +{ Bit_RESET = 0, + Bit_SET +}BitAction; + +#define IS_GPIO_BIT_ACTION(ACTION) (((ACTION) == Bit_RESET) || ((ACTION) == Bit_SET)) + +/** + * @} + */ + +/** @defgroup GPIO_Exported_Constants + * @{ + */ + +/** @defgroup GPIO_pins_define + * @{ + */ + +#define GPIO_Pin_0 ((uint16_t)0x0001) /*!< Pin 0 selected */ +#define GPIO_Pin_1 ((uint16_t)0x0002) /*!< Pin 1 selected */ +#define GPIO_Pin_2 ((uint16_t)0x0004) /*!< Pin 2 selected */ +#define GPIO_Pin_3 ((uint16_t)0x0008) /*!< Pin 3 selected */ +#define GPIO_Pin_4 ((uint16_t)0x0010) /*!< Pin 4 selected */ +#define GPIO_Pin_5 ((uint16_t)0x0020) /*!< Pin 5 selected */ +#define GPIO_Pin_6 ((uint16_t)0x0040) /*!< Pin 6 selected */ +#define GPIO_Pin_7 ((uint16_t)0x0080) /*!< Pin 7 selected */ +#define GPIO_Pin_8 ((uint16_t)0x0100) /*!< Pin 8 selected */ +#define GPIO_Pin_9 ((uint16_t)0x0200) /*!< Pin 9 selected */ +#define GPIO_Pin_10 ((uint16_t)0x0400) /*!< Pin 10 selected */ +#define GPIO_Pin_11 ((uint16_t)0x0800) /*!< Pin 11 selected */ +#define GPIO_Pin_12 ((uint16_t)0x1000) /*!< Pin 12 selected */ +#define GPIO_Pin_13 ((uint16_t)0x2000) /*!< Pin 13 selected */ +#define GPIO_Pin_14 ((uint16_t)0x4000) /*!< Pin 14 selected */ +#define GPIO_Pin_15 ((uint16_t)0x8000) /*!< Pin 15 selected */ +#define GPIO_Pin_All ((uint16_t)0xFFFF) /*!< All pins selected */ + +#define IS_GPIO_PIN(PIN) ((((PIN) & (uint16_t)0x00) == 0x00) && ((PIN) != (uint16_t)0x00)) + +#define IS_GET_GPIO_PIN(PIN) (((PIN) == GPIO_Pin_0) || \ + ((PIN) == GPIO_Pin_1) || \ + ((PIN) == GPIO_Pin_2) || \ + ((PIN) == GPIO_Pin_3) || \ + ((PIN) == GPIO_Pin_4) || \ + ((PIN) == GPIO_Pin_5) || \ + ((PIN) == GPIO_Pin_6) || \ + ((PIN) == GPIO_Pin_7) || \ + ((PIN) == GPIO_Pin_8) || \ + ((PIN) == GPIO_Pin_9) || \ + ((PIN) == GPIO_Pin_10) || \ + ((PIN) == GPIO_Pin_11) || \ + ((PIN) == GPIO_Pin_12) || \ + ((PIN) == GPIO_Pin_13) || \ + ((PIN) == GPIO_Pin_14) || \ + ((PIN) == GPIO_Pin_15)) + +/** + * @} + */ + +/** @defgroup GPIO_Remap_define + * @{ + */ + +#define GPIO_Remap_SPI1 ((uint32_t)0x00000001) /*!< SPI1 Alternate Function mapping */ +#define GPIO_Remap_I2C1 ((uint32_t)0x00000002) /*!< I2C1 Alternate Function mapping */ +#define GPIO_Remap_USART1 ((uint32_t)0x00000004) /*!< USART1 Alternate Function mapping */ +#define GPIO_Remap_USART2 ((uint32_t)0x00000008) /*!< USART2 Alternate Function mapping */ +#define GPIO_PartialRemap_USART3 ((uint32_t)0x00140010) /*!< USART3 Partial Alternate Function mapping */ +#define GPIO_FullRemap_USART3 ((uint32_t)0x00140030) /*!< USART3 Full Alternate Function mapping */ +#define GPIO_PartialRemap_TIM1 ((uint32_t)0x00160040) /*!< TIM1 Partial Alternate Function mapping */ +#define GPIO_FullRemap_TIM1 ((uint32_t)0x001600C0) /*!< TIM1 Full Alternate Function mapping */ +#define GPIO_PartialRemap1_TIM2 ((uint32_t)0x00180100) /*!< TIM2 Partial1 Alternate Function mapping */ +#define GPIO_PartialRemap2_TIM2 ((uint32_t)0x00180200) /*!< TIM2 Partial2 Alternate Function mapping */ +#define GPIO_FullRemap_TIM2 ((uint32_t)0x00180300) /*!< TIM2 Full Alternate Function mapping */ +#define GPIO_PartialRemap_TIM3 ((uint32_t)0x001A0800) /*!< TIM3 Partial Alternate Function mapping */ +#define GPIO_FullRemap_TIM3 ((uint32_t)0x001A0C00) /*!< TIM3 Full Alternate Function mapping */ +#define GPIO_Remap_TIM4 ((uint32_t)0x00001000) /*!< TIM4 Alternate Function mapping */ +#define GPIO_Remap1_CAN1 ((uint32_t)0x001D4000) /*!< CAN1 Alternate Function mapping */ +#define GPIO_Remap2_CAN1 ((uint32_t)0x001D6000) /*!< CAN1 Alternate Function mapping */ +#define GPIO_Remap_PD01 ((uint32_t)0x00008000) /*!< PD01 Alternate Function mapping */ +#define GPIO_Remap_TIM5CH4_LSI ((uint32_t)0x00200001) /*!< LSI connected to TIM5 Channel4 input capture for calibration */ +#define GPIO_Remap_ADC1_ETRGINJ ((uint32_t)0x00200002) /*!< ADC1 External Trigger Injected Conversion remapping */ +#define GPIO_Remap_ADC1_ETRGREG ((uint32_t)0x00200004) /*!< ADC1 External Trigger Regular Conversion remapping */ +#define GPIO_Remap_ADC2_ETRGINJ ((uint32_t)0x00200008) /*!< ADC2 External Trigger Injected Conversion remapping */ +#define GPIO_Remap_ADC2_ETRGREG ((uint32_t)0x00200010) /*!< ADC2 External Trigger Regular Conversion remapping */ +#define GPIO_Remap_ETH ((uint32_t)0x00200020) /*!< Ethernet remapping (only for Connectivity line devices) */ +#define GPIO_Remap_CAN2 ((uint32_t)0x00200040) /*!< CAN2 remapping (only for Connectivity line devices) */ +#define GPIO_Remap_SWJ_NoJTRST ((uint32_t)0x00300100) /*!< Full SWJ Enabled (JTAG-DP + SW-DP) but without JTRST */ +#define GPIO_Remap_SWJ_JTAGDisable ((uint32_t)0x00300200) /*!< JTAG-DP Disabled and SW-DP Enabled */ +#define GPIO_Remap_SWJ_Disable ((uint32_t)0x00300400) /*!< Full SWJ Disabled (JTAG-DP + SW-DP) */ +#define GPIO_Remap_SPI3 ((uint32_t)0x00201100) /*!< SPI3/I2S3 Alternate Function mapping (only for Connectivity line devices) */ +#define GPIO_Remap_TIM2ITR1_PTP_SOF ((uint32_t)0x00202000) /*!< Ethernet PTP output or USB OTG SOF (Start of Frame) connected + to TIM2 Internal Trigger 1 for calibration + (only for Connectivity line devices) */ +#define GPIO_Remap_PTP_PPS ((uint32_t)0x00204000) /*!< Ethernet MAC PPS_PTS output on PB05 (only for Connectivity line devices) */ + +#define GPIO_Remap_TIM15 ((uint32_t)0x80000001) /*!< TIM15 Alternate Function mapping (only for Value line devices) */ +#define GPIO_Remap_TIM16 ((uint32_t)0x80000002) /*!< TIM16 Alternate Function mapping (only for Value line devices) */ +#define GPIO_Remap_TIM17 ((uint32_t)0x80000004) /*!< TIM17 Alternate Function mapping (only for Value line devices) */ +#define GPIO_Remap_CEC ((uint32_t)0x80000008) /*!< CEC Alternate Function mapping (only for Value line devices) */ +#define GPIO_Remap_TIM1_DMA ((uint32_t)0x80000010) /*!< TIM1 DMA requests mapping (only for Value line devices) */ + +#define GPIO_Remap_TIM9 ((uint32_t)0x80000020) /*!< TIM9 Alternate Function mapping (only for XL-density devices) */ +#define GPIO_Remap_TIM10 ((uint32_t)0x80000040) /*!< TIM10 Alternate Function mapping (only for XL-density devices) */ +#define GPIO_Remap_TIM11 ((uint32_t)0x80000080) /*!< TIM11 Alternate Function mapping (only for XL-density devices) */ +#define GPIO_Remap_TIM13 ((uint32_t)0x80000100) /*!< TIM13 Alternate Function mapping (only for High density Value line and XL-density devices) */ +#define GPIO_Remap_TIM14 ((uint32_t)0x80000200) /*!< TIM14 Alternate Function mapping (only for High density Value line and XL-density devices) */ +#define GPIO_Remap_FSMC_NADV ((uint32_t)0x80000400) /*!< FSMC_NADV Alternate Function mapping (only for High density Value line and XL-density devices) */ + +#define GPIO_Remap_TIM67_DAC_DMA ((uint32_t)0x80000800) /*!< TIM6/TIM7 and DAC DMA requests remapping (only for High density Value line devices) */ +#define GPIO_Remap_TIM12 ((uint32_t)0x80001000) /*!< TIM12 Alternate Function mapping (only for High density Value line devices) */ +#define GPIO_Remap_MISC ((uint32_t)0x80002000) /*!< Miscellaneous Remap (DMA2 Channel5 Position and DAC Trigger remapping, + only for High density Value line devices) */ + +#define IS_GPIO_REMAP(REMAP) (((REMAP) == GPIO_Remap_SPI1) || ((REMAP) == GPIO_Remap_I2C1) || \ + ((REMAP) == GPIO_Remap_USART1) || ((REMAP) == GPIO_Remap_USART2) || \ + ((REMAP) == GPIO_PartialRemap_USART3) || ((REMAP) == GPIO_FullRemap_USART3) || \ + ((REMAP) == GPIO_PartialRemap_TIM1) || ((REMAP) == GPIO_FullRemap_TIM1) || \ + ((REMAP) == GPIO_PartialRemap1_TIM2) || ((REMAP) == GPIO_PartialRemap2_TIM2) || \ + ((REMAP) == GPIO_FullRemap_TIM2) || ((REMAP) == GPIO_PartialRemap_TIM3) || \ + ((REMAP) == GPIO_FullRemap_TIM3) || ((REMAP) == GPIO_Remap_TIM4) || \ + ((REMAP) == GPIO_Remap1_CAN1) || ((REMAP) == GPIO_Remap2_CAN1) || \ + ((REMAP) == GPIO_Remap_PD01) || ((REMAP) == GPIO_Remap_TIM5CH4_LSI) || \ + ((REMAP) == GPIO_Remap_ADC1_ETRGINJ) ||((REMAP) == GPIO_Remap_ADC1_ETRGREG) || \ + ((REMAP) == GPIO_Remap_ADC2_ETRGINJ) ||((REMAP) == GPIO_Remap_ADC2_ETRGREG) || \ + ((REMAP) == GPIO_Remap_ETH) ||((REMAP) == GPIO_Remap_CAN2) || \ + ((REMAP) == GPIO_Remap_SWJ_NoJTRST) || ((REMAP) == GPIO_Remap_SWJ_JTAGDisable) || \ + ((REMAP) == GPIO_Remap_SWJ_Disable)|| ((REMAP) == GPIO_Remap_SPI3) || \ + ((REMAP) == GPIO_Remap_TIM2ITR1_PTP_SOF) || ((REMAP) == GPIO_Remap_PTP_PPS) || \ + ((REMAP) == GPIO_Remap_TIM15) || ((REMAP) == GPIO_Remap_TIM16) || \ + ((REMAP) == GPIO_Remap_TIM17) || ((REMAP) == GPIO_Remap_CEC) || \ + ((REMAP) == GPIO_Remap_TIM1_DMA) || ((REMAP) == GPIO_Remap_TIM9) || \ + ((REMAP) == GPIO_Remap_TIM10) || ((REMAP) == GPIO_Remap_TIM11) || \ + ((REMAP) == GPIO_Remap_TIM13) || ((REMAP) == GPIO_Remap_TIM14) || \ + ((REMAP) == GPIO_Remap_FSMC_NADV) || ((REMAP) == GPIO_Remap_TIM67_DAC_DMA) || \ + ((REMAP) == GPIO_Remap_TIM12) || ((REMAP) == GPIO_Remap_MISC)) + +/** + * @} + */ + +/** @defgroup GPIO_Port_Sources + * @{ + */ + +#define GPIO_PortSourceGPIOA ((uint8_t)0x00) +#define GPIO_PortSourceGPIOB ((uint8_t)0x01) +#define GPIO_PortSourceGPIOC ((uint8_t)0x02) +#define GPIO_PortSourceGPIOD ((uint8_t)0x03) +#define GPIO_PortSourceGPIOE ((uint8_t)0x04) +#define GPIO_PortSourceGPIOF ((uint8_t)0x05) +#define GPIO_PortSourceGPIOG ((uint8_t)0x06) +#define IS_GPIO_EVENTOUT_PORT_SOURCE(PORTSOURCE) (((PORTSOURCE) == GPIO_PortSourceGPIOA) || \ + ((PORTSOURCE) == GPIO_PortSourceGPIOB) || \ + ((PORTSOURCE) == GPIO_PortSourceGPIOC) || \ + ((PORTSOURCE) == GPIO_PortSourceGPIOD) || \ + ((PORTSOURCE) == GPIO_PortSourceGPIOE)) + +#define IS_GPIO_EXTI_PORT_SOURCE(PORTSOURCE) (((PORTSOURCE) == GPIO_PortSourceGPIOA) || \ + ((PORTSOURCE) == GPIO_PortSourceGPIOB) || \ + ((PORTSOURCE) == GPIO_PortSourceGPIOC) || \ + ((PORTSOURCE) == GPIO_PortSourceGPIOD) || \ + ((PORTSOURCE) == GPIO_PortSourceGPIOE) || \ + ((PORTSOURCE) == GPIO_PortSourceGPIOF) || \ + ((PORTSOURCE) == GPIO_PortSourceGPIOG)) + +/** + * @} + */ + +/** @defgroup GPIO_Pin_sources + * @{ + */ + +#define GPIO_PinSource0 ((uint8_t)0x00) +#define GPIO_PinSource1 ((uint8_t)0x01) +#define GPIO_PinSource2 ((uint8_t)0x02) +#define GPIO_PinSource3 ((uint8_t)0x03) +#define GPIO_PinSource4 ((uint8_t)0x04) +#define GPIO_PinSource5 ((uint8_t)0x05) +#define GPIO_PinSource6 ((uint8_t)0x06) +#define GPIO_PinSource7 ((uint8_t)0x07) +#define GPIO_PinSource8 ((uint8_t)0x08) +#define GPIO_PinSource9 ((uint8_t)0x09) +#define GPIO_PinSource10 ((uint8_t)0x0A) +#define GPIO_PinSource11 ((uint8_t)0x0B) +#define GPIO_PinSource12 ((uint8_t)0x0C) +#define GPIO_PinSource13 ((uint8_t)0x0D) +#define GPIO_PinSource14 ((uint8_t)0x0E) +#define GPIO_PinSource15 ((uint8_t)0x0F) + +#define IS_GPIO_PIN_SOURCE(PINSOURCE) (((PINSOURCE) == GPIO_PinSource0) || \ + ((PINSOURCE) == GPIO_PinSource1) || \ + ((PINSOURCE) == GPIO_PinSource2) || \ + ((PINSOURCE) == GPIO_PinSource3) || \ + ((PINSOURCE) == GPIO_PinSource4) || \ + ((PINSOURCE) == GPIO_PinSource5) || \ + ((PINSOURCE) == GPIO_PinSource6) || \ + ((PINSOURCE) == GPIO_PinSource7) || \ + ((PINSOURCE) == GPIO_PinSource8) || \ + ((PINSOURCE) == GPIO_PinSource9) || \ + ((PINSOURCE) == GPIO_PinSource10) || \ + ((PINSOURCE) == GPIO_PinSource11) || \ + ((PINSOURCE) == GPIO_PinSource12) || \ + ((PINSOURCE) == GPIO_PinSource13) || \ + ((PINSOURCE) == GPIO_PinSource14) || \ + ((PINSOURCE) == GPIO_PinSource15)) + +/** + * @} + */ + +/** @defgroup Ethernet_Media_Interface + * @{ + */ +#define GPIO_ETH_MediaInterface_MII ((u32)0x00000000) +#define GPIO_ETH_MediaInterface_RMII ((u32)0x00000001) + +#define IS_GPIO_ETH_MEDIA_INTERFACE(INTERFACE) (((INTERFACE) == GPIO_ETH_MediaInterface_MII) || \ + ((INTERFACE) == GPIO_ETH_MediaInterface_RMII)) + +/** + * @} + */ +/** + * @} + */ + +/** @defgroup GPIO_Exported_Macros + * @{ + */ + +/** + * @} + */ + +/** @defgroup GPIO_Exported_Functions + * @{ + */ + +void GPIO_DeInit(GPIO_TypeDef* GPIOx); +void GPIO_AFIODeInit(void); +void GPIO_Init(GPIO_TypeDef* GPIOx, GPIO_InitTypeDef* GPIO_InitStruct); +void GPIO_StructInit(GPIO_InitTypeDef* GPIO_InitStruct); +uint8_t GPIO_ReadInputDataBit(GPIO_TypeDef* GPIOx, uint16_t GPIO_Pin); +uint16_t GPIO_ReadInputData(GPIO_TypeDef* GPIOx); +uint8_t GPIO_ReadOutputDataBit(GPIO_TypeDef* GPIOx, uint16_t GPIO_Pin); +uint16_t GPIO_ReadOutputData(GPIO_TypeDef* GPIOx); +void GPIO_SetBits(GPIO_TypeDef* GPIOx, uint16_t GPIO_Pin); +void GPIO_ResetBits(GPIO_TypeDef* GPIOx, uint16_t GPIO_Pin); +void GPIO_WriteBit(GPIO_TypeDef* GPIOx, uint16_t GPIO_Pin, BitAction BitVal); +void GPIO_Write(GPIO_TypeDef* GPIOx, uint16_t PortVal); +void GPIO_PinLockConfig(GPIO_TypeDef* GPIOx, uint16_t GPIO_Pin); +void GPIO_EventOutputConfig(uint8_t GPIO_PortSource, uint8_t GPIO_PinSource); +void GPIO_EventOutputCmd(FunctionalState NewState); +void GPIO_PinRemapConfig(uint32_t GPIO_Remap, FunctionalState NewState); +void GPIO_EXTILineConfig(uint8_t GPIO_PortSource, uint8_t GPIO_PinSource); +void GPIO_ETH_MediaInterfaceConfig(uint32_t GPIO_ETH_MediaInterface); + +#ifdef __cplusplus +} +#endif + +#endif /* __STM32F10x_GPIO_H */ +/** + * @} + */ + +/** + * @} + */ + +/** + * @} + */ + +/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ diff --git a/Libraries/STM32F10x_StdPeriph_Driver/inc/stm32f10x_i2c.h b/Libraries/STM32F10x_StdPeriph_Driver/inc/stm32f10x_i2c.h new file mode 100644 index 0000000..ce92b20 --- /dev/null +++ b/Libraries/STM32F10x_StdPeriph_Driver/inc/stm32f10x_i2c.h @@ -0,0 +1,690 @@ +/** + ****************************************************************************** + * @file stm32f10x_i2c.h + * @author MCD Application Team + * @version V3.6.1 + * @date 05-March-2012 + * @brief This file contains all the functions prototypes for the I2C firmware + * library. + ****************************************************************************** + * @attention + * + *

    © COPYRIGHT 2012 STMicroelectronics

    + * + * Licensed under MCD-ST Liberty SW License Agreement V2, (the "License"); + * You may not use this file except in compliance with the License. + * You may obtain a copy of the License at: + * + * http://www.st.com/software_license_agreement_liberty_v2 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, + * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + * + ****************************************************************************** + */ + +/* Define to prevent recursive inclusion -------------------------------------*/ +#ifndef __STM32F10x_I2C_H +#define __STM32F10x_I2C_H + +#ifdef __cplusplus + extern "C" { +#endif + +/* Includes ------------------------------------------------------------------*/ +#include "stm32f10x.h" + +/** @addtogroup STM32F10x_StdPeriph_Driver + * @{ + */ + +/** @addtogroup I2C + * @{ + */ + +/** @defgroup I2C_Exported_Types + * @{ + */ + +/** + * @brief I2C Init structure definition + */ + +typedef struct +{ + uint32_t I2C_ClockSpeed; /*!< Specifies the clock frequency. + This parameter must be set to a value lower than 400kHz */ + + uint16_t I2C_Mode; /*!< Specifies the I2C mode. + This parameter can be a value of @ref I2C_mode */ + + uint16_t I2C_DutyCycle; /*!< Specifies the I2C fast mode duty cycle. + This parameter can be a value of @ref I2C_duty_cycle_in_fast_mode */ + + uint16_t I2C_OwnAddress1; /*!< Specifies the first device own address. + This parameter can be a 7-bit or 10-bit address. */ + + uint16_t I2C_Ack; /*!< Enables or disables the acknowledgement. + This parameter can be a value of @ref I2C_acknowledgement */ + + uint16_t I2C_AcknowledgedAddress; /*!< Specifies if 7-bit or 10-bit address is acknowledged. + This parameter can be a value of @ref I2C_acknowledged_address */ +}I2C_InitTypeDef; + +/** + * @} + */ + + +/** @defgroup I2C_Exported_Constants + * @{ + */ + +#define IS_I2C_ALL_PERIPH(PERIPH) (((PERIPH) == I2C1) || \ + ((PERIPH) == I2C2)) +/** @defgroup I2C_mode + * @{ + */ + +#define I2C_Mode_I2C ((uint16_t)0x0000) +#define I2C_Mode_SMBusDevice ((uint16_t)0x0002) +#define I2C_Mode_SMBusHost ((uint16_t)0x000A) +#define IS_I2C_MODE(MODE) (((MODE) == I2C_Mode_I2C) || \ + ((MODE) == I2C_Mode_SMBusDevice) || \ + ((MODE) == I2C_Mode_SMBusHost)) +/** + * @} + */ + +/** @defgroup I2C_duty_cycle_in_fast_mode + * @{ + */ + +#define I2C_DutyCycle_16_9 ((uint16_t)0x4000) /*!< I2C fast mode Tlow/Thigh = 16/9 */ +#define I2C_DutyCycle_2 ((uint16_t)0xBFFF) /*!< I2C fast mode Tlow/Thigh = 2 */ +#define IS_I2C_DUTY_CYCLE(CYCLE) (((CYCLE) == I2C_DutyCycle_16_9) || \ + ((CYCLE) == I2C_DutyCycle_2)) +/** + * @} + */ + +/** @defgroup I2C_acknowledgement + * @{ + */ + +#define I2C_Ack_Enable ((uint16_t)0x0400) +#define I2C_Ack_Disable ((uint16_t)0x0000) +#define IS_I2C_ACK_STATE(STATE) (((STATE) == I2C_Ack_Enable) || \ + ((STATE) == I2C_Ack_Disable)) +/** + * @} + */ + +/** @defgroup I2C_transfer_direction + * @{ + */ + +#define I2C_Direction_Transmitter ((uint8_t)0x00) +#define I2C_Direction_Receiver ((uint8_t)0x01) +#define IS_I2C_DIRECTION(DIRECTION) (((DIRECTION) == I2C_Direction_Transmitter) || \ + ((DIRECTION) == I2C_Direction_Receiver)) +/** + * @} + */ + +/** @defgroup I2C_acknowledged_address + * @{ + */ + +#define I2C_AcknowledgedAddress_7bit ((uint16_t)0x4000) +#define I2C_AcknowledgedAddress_10bit ((uint16_t)0xC000) +#define IS_I2C_ACKNOWLEDGE_ADDRESS(ADDRESS) (((ADDRESS) == I2C_AcknowledgedAddress_7bit) || \ + ((ADDRESS) == I2C_AcknowledgedAddress_10bit)) +/** + * @} + */ + +/** @defgroup I2C_registers + * @{ + */ + +#define I2C_Register_CR1 ((uint8_t)0x00) +#define I2C_Register_CR2 ((uint8_t)0x04) +#define I2C_Register_OAR1 ((uint8_t)0x08) +#define I2C_Register_OAR2 ((uint8_t)0x0C) +#define I2C_Register_DR ((uint8_t)0x10) +#define I2C_Register_SR1 ((uint8_t)0x14) +#define I2C_Register_SR2 ((uint8_t)0x18) +#define I2C_Register_CCR ((uint8_t)0x1C) +#define I2C_Register_TRISE ((uint8_t)0x20) +#define IS_I2C_REGISTER(REGISTER) (((REGISTER) == I2C_Register_CR1) || \ + ((REGISTER) == I2C_Register_CR2) || \ + ((REGISTER) == I2C_Register_OAR1) || \ + ((REGISTER) == I2C_Register_OAR2) || \ + ((REGISTER) == I2C_Register_DR) || \ + ((REGISTER) == I2C_Register_SR1) || \ + ((REGISTER) == I2C_Register_SR2) || \ + ((REGISTER) == I2C_Register_CCR) || \ + ((REGISTER) == I2C_Register_TRISE)) +/** + * @} + */ + +/** @defgroup I2C_SMBus_alert_pin_level + * @{ + */ + +#define I2C_SMBusAlert_Low ((uint16_t)0x2000) +#define I2C_SMBusAlert_High ((uint16_t)0xDFFF) +#define IS_I2C_SMBUS_ALERT(ALERT) (((ALERT) == I2C_SMBusAlert_Low) || \ + ((ALERT) == I2C_SMBusAlert_High)) +/** + * @} + */ + +/** @defgroup I2C_PEC_position + * @{ + */ + +#define I2C_PECPosition_Next ((uint16_t)0x0800) +#define I2C_PECPosition_Current ((uint16_t)0xF7FF) +#define IS_I2C_PEC_POSITION(POSITION) (((POSITION) == I2C_PECPosition_Next) || \ + ((POSITION) == I2C_PECPosition_Current)) +/** + * @} + */ + +/** @defgroup I2C_NCAK_position + * @{ + */ + +#define I2C_NACKPosition_Next ((uint16_t)0x0800) +#define I2C_NACKPosition_Current ((uint16_t)0xF7FF) +#define IS_I2C_NACK_POSITION(POSITION) (((POSITION) == I2C_NACKPosition_Next) || \ + ((POSITION) == I2C_NACKPosition_Current)) +/** + * @} + */ + +/** @defgroup I2C_interrupts_definition + * @{ + */ + +#define I2C_IT_BUF ((uint16_t)0x0400) +#define I2C_IT_EVT ((uint16_t)0x0200) +#define I2C_IT_ERR ((uint16_t)0x0100) +#define IS_I2C_CONFIG_IT(IT) ((((IT) & (uint16_t)0xF8FF) == 0x00) && ((IT) != 0x00)) +/** + * @} + */ + +/** @defgroup I2C_interrupts_definition + * @{ + */ + +#define I2C_IT_SMBALERT ((uint32_t)0x01008000) +#define I2C_IT_TIMEOUT ((uint32_t)0x01004000) +#define I2C_IT_PECERR ((uint32_t)0x01001000) +#define I2C_IT_OVR ((uint32_t)0x01000800) +#define I2C_IT_AF ((uint32_t)0x01000400) +#define I2C_IT_ARLO ((uint32_t)0x01000200) +#define I2C_IT_BERR ((uint32_t)0x01000100) +#define I2C_IT_TXE ((uint32_t)0x06000080) +#define I2C_IT_RXNE ((uint32_t)0x06000040) +#define I2C_IT_STOPF ((uint32_t)0x02000010) +#define I2C_IT_ADD10 ((uint32_t)0x02000008) +#define I2C_IT_BTF ((uint32_t)0x02000004) +#define I2C_IT_ADDR ((uint32_t)0x02000002) +#define I2C_IT_SB ((uint32_t)0x02000001) + +#define IS_I2C_CLEAR_IT(IT) ((((IT) & (uint16_t)0x20FF) == 0x00) && ((IT) != (uint16_t)0x00)) + +#define IS_I2C_GET_IT(IT) (((IT) == I2C_IT_SMBALERT) || ((IT) == I2C_IT_TIMEOUT) || \ + ((IT) == I2C_IT_PECERR) || ((IT) == I2C_IT_OVR) || \ + ((IT) == I2C_IT_AF) || ((IT) == I2C_IT_ARLO) || \ + ((IT) == I2C_IT_BERR) || ((IT) == I2C_IT_TXE) || \ + ((IT) == I2C_IT_RXNE) || ((IT) == I2C_IT_STOPF) || \ + ((IT) == I2C_IT_ADD10) || ((IT) == I2C_IT_BTF) || \ + ((IT) == I2C_IT_ADDR) || ((IT) == I2C_IT_SB)) +/** + * @} + */ + +/** @defgroup I2C_flags_definition + * @{ + */ + +/** + * @brief SR2 register flags + */ + +#define I2C_FLAG_DUALF ((uint32_t)0x00800000) +#define I2C_FLAG_SMBHOST ((uint32_t)0x00400000) +#define I2C_FLAG_SMBDEFAULT ((uint32_t)0x00200000) +#define I2C_FLAG_GENCALL ((uint32_t)0x00100000) +#define I2C_FLAG_TRA ((uint32_t)0x00040000) +#define I2C_FLAG_BUSY ((uint32_t)0x00020000) +#define I2C_FLAG_MSL ((uint32_t)0x00010000) + +/** + * @brief SR1 register flags + */ + +#define I2C_FLAG_SMBALERT ((uint32_t)0x10008000) +#define I2C_FLAG_TIMEOUT ((uint32_t)0x10004000) +#define I2C_FLAG_PECERR ((uint32_t)0x10001000) +#define I2C_FLAG_OVR ((uint32_t)0x10000800) +#define I2C_FLAG_AF ((uint32_t)0x10000400) +#define I2C_FLAG_ARLO ((uint32_t)0x10000200) +#define I2C_FLAG_BERR ((uint32_t)0x10000100) +#define I2C_FLAG_TXE ((uint32_t)0x10000080) +#define I2C_FLAG_RXNE ((uint32_t)0x10000040) +#define I2C_FLAG_STOPF ((uint32_t)0x10000010) +#define I2C_FLAG_ADD10 ((uint32_t)0x10000008) +#define I2C_FLAG_BTF ((uint32_t)0x10000004) +#define I2C_FLAG_ADDR ((uint32_t)0x10000002) +#define I2C_FLAG_SB ((uint32_t)0x10000001) + +#define IS_I2C_CLEAR_FLAG(FLAG) ((((FLAG) & (uint16_t)0x20FF) == 0x00) && ((FLAG) != (uint16_t)0x00)) + +#define IS_I2C_GET_FLAG(FLAG) (((FLAG) == I2C_FLAG_DUALF) || ((FLAG) == I2C_FLAG_SMBHOST) || \ + ((FLAG) == I2C_FLAG_SMBDEFAULT) || ((FLAG) == I2C_FLAG_GENCALL) || \ + ((FLAG) == I2C_FLAG_TRA) || ((FLAG) == I2C_FLAG_BUSY) || \ + ((FLAG) == I2C_FLAG_MSL) || ((FLAG) == I2C_FLAG_SMBALERT) || \ + ((FLAG) == I2C_FLAG_TIMEOUT) || ((FLAG) == I2C_FLAG_PECERR) || \ + ((FLAG) == I2C_FLAG_OVR) || ((FLAG) == I2C_FLAG_AF) || \ + ((FLAG) == I2C_FLAG_ARLO) || ((FLAG) == I2C_FLAG_BERR) || \ + ((FLAG) == I2C_FLAG_TXE) || ((FLAG) == I2C_FLAG_RXNE) || \ + ((FLAG) == I2C_FLAG_STOPF) || ((FLAG) == I2C_FLAG_ADD10) || \ + ((FLAG) == I2C_FLAG_BTF) || ((FLAG) == I2C_FLAG_ADDR) || \ + ((FLAG) == I2C_FLAG_SB)) +/** + * @} + */ + +/** @defgroup I2C_Events + * @{ + */ + +/*======================================== + + I2C Master Events (Events grouped in order of communication) + ==========================================*/ +/** + * @brief Communication start + * + * After sending the START condition (I2C_GenerateSTART() function) the master + * has to wait for this event. It means that the Start condition has been correctly + * released on the I2C bus (the bus is free, no other devices is communicating). + * + */ +/* --EV5 */ +#define I2C_EVENT_MASTER_MODE_SELECT ((uint32_t)0x00030001) /* BUSY, MSL and SB flag */ + +/** + * @brief Address Acknowledge + * + * After checking on EV5 (start condition correctly released on the bus), the + * master sends the address of the slave(s) with which it will communicate + * (I2C_Send7bitAddress() function, it also determines the direction of the communication: + * Master transmitter or Receiver). Then the master has to wait that a slave acknowledges + * his address. If an acknowledge is sent on the bus, one of the following events will + * be set: + * + * 1) In case of Master Receiver (7-bit addressing): the I2C_EVENT_MASTER_RECEIVER_MODE_SELECTED + * event is set. + * + * 2) In case of Master Transmitter (7-bit addressing): the I2C_EVENT_MASTER_TRANSMITTER_MODE_SELECTED + * is set + * + * 3) In case of 10-Bit addressing mode, the master (just after generating the START + * and checking on EV5) has to send the header of 10-bit addressing mode (I2C_SendData() + * function). Then master should wait on EV9. It means that the 10-bit addressing + * header has been correctly sent on the bus. Then master should send the second part of + * the 10-bit address (LSB) using the function I2C_Send7bitAddress(). Then master + * should wait for event EV6. + * + */ + +/* --EV6 */ +#define I2C_EVENT_MASTER_TRANSMITTER_MODE_SELECTED ((uint32_t)0x00070082) /* BUSY, MSL, ADDR, TXE and TRA flags */ +#define I2C_EVENT_MASTER_RECEIVER_MODE_SELECTED ((uint32_t)0x00030002) /* BUSY, MSL and ADDR flags */ +/* --EV9 */ +#define I2C_EVENT_MASTER_MODE_ADDRESS10 ((uint32_t)0x00030008) /* BUSY, MSL and ADD10 flags */ + +/** + * @brief Communication events + * + * If a communication is established (START condition generated and slave address + * acknowledged) then the master has to check on one of the following events for + * communication procedures: + * + * 1) Master Receiver mode: The master has to wait on the event EV7 then to read + * the data received from the slave (I2C_ReceiveData() function). + * + * 2) Master Transmitter mode: The master has to send data (I2C_SendData() + * function) then to wait on event EV8 or EV8_2. + * These two events are similar: + * - EV8 means that the data has been written in the data register and is + * being shifted out. + * - EV8_2 means that the data has been physically shifted out and output + * on the bus. + * In most cases, using EV8 is sufficient for the application. + * Using EV8_2 leads to a slower communication but ensure more reliable test. + * EV8_2 is also more suitable than EV8 for testing on the last data transmission + * (before Stop condition generation). + * + * @note In case the user software does not guarantee that this event EV7 is + * managed before the current byte end of transfer, then user may check on EV7 + * and BTF flag at the same time (ie. (I2C_EVENT_MASTER_BYTE_RECEIVED | I2C_FLAG_BTF)). + * In this case the communication may be slower. + * + */ + +/* Master RECEIVER mode -----------------------------*/ +/* --EV7 */ +#define I2C_EVENT_MASTER_BYTE_RECEIVED ((uint32_t)0x00030040) /* BUSY, MSL and RXNE flags */ + +/* Master TRANSMITTER mode --------------------------*/ +/* --EV8 */ +#define I2C_EVENT_MASTER_BYTE_TRANSMITTING ((uint32_t)0x00070080) /* TRA, BUSY, MSL, TXE flags */ +/* --EV8_2 */ +#define I2C_EVENT_MASTER_BYTE_TRANSMITTED ((uint32_t)0x00070084) /* TRA, BUSY, MSL, TXE and BTF flags */ + + +/*======================================== + + I2C Slave Events (Events grouped in order of communication) + ==========================================*/ + +/** + * @brief Communication start events + * + * Wait on one of these events at the start of the communication. It means that + * the I2C peripheral detected a Start condition on the bus (generated by master + * device) followed by the peripheral address. The peripheral generates an ACK + * condition on the bus (if the acknowledge feature is enabled through function + * I2C_AcknowledgeConfig()) and the events listed above are set : + * + * 1) In normal case (only one address managed by the slave), when the address + * sent by the master matches the own address of the peripheral (configured by + * I2C_OwnAddress1 field) the I2C_EVENT_SLAVE_XXX_ADDRESS_MATCHED event is set + * (where XXX could be TRANSMITTER or RECEIVER). + * + * 2) In case the address sent by the master matches the second address of the + * peripheral (configured by the function I2C_OwnAddress2Config() and enabled + * by the function I2C_DualAddressCmd()) the events I2C_EVENT_SLAVE_XXX_SECONDADDRESS_MATCHED + * (where XXX could be TRANSMITTER or RECEIVER) are set. + * + * 3) In case the address sent by the master is General Call (address 0x00) and + * if the General Call is enabled for the peripheral (using function I2C_GeneralCallCmd()) + * the following event is set I2C_EVENT_SLAVE_GENERALCALLADDRESS_MATCHED. + * + */ + +/* --EV1 (all the events below are variants of EV1) */ +/* 1) Case of One Single Address managed by the slave */ +#define I2C_EVENT_SLAVE_RECEIVER_ADDRESS_MATCHED ((uint32_t)0x00020002) /* BUSY and ADDR flags */ +#define I2C_EVENT_SLAVE_TRANSMITTER_ADDRESS_MATCHED ((uint32_t)0x00060082) /* TRA, BUSY, TXE and ADDR flags */ + +/* 2) Case of Dual address managed by the slave */ +#define I2C_EVENT_SLAVE_RECEIVER_SECONDADDRESS_MATCHED ((uint32_t)0x00820000) /* DUALF and BUSY flags */ +#define I2C_EVENT_SLAVE_TRANSMITTER_SECONDADDRESS_MATCHED ((uint32_t)0x00860080) /* DUALF, TRA, BUSY and TXE flags */ + +/* 3) Case of General Call enabled for the slave */ +#define I2C_EVENT_SLAVE_GENERALCALLADDRESS_MATCHED ((uint32_t)0x00120000) /* GENCALL and BUSY flags */ + +/** + * @brief Communication events + * + * Wait on one of these events when EV1 has already been checked and: + * + * - Slave RECEIVER mode: + * - EV2: When the application is expecting a data byte to be received. + * - EV4: When the application is expecting the end of the communication: master + * sends a stop condition and data transmission is stopped. + * + * - Slave Transmitter mode: + * - EV3: When a byte has been transmitted by the slave and the application is expecting + * the end of the byte transmission. The two events I2C_EVENT_SLAVE_BYTE_TRANSMITTED and + * I2C_EVENT_SLAVE_BYTE_TRANSMITTING are similar. The second one can optionally be + * used when the user software doesn't guarantee the EV3 is managed before the + * current byte end of transfer. + * - EV3_2: When the master sends a NACK in order to tell slave that data transmission + * shall end (before sending the STOP condition). In this case slave has to stop sending + * data bytes and expect a Stop condition on the bus. + * + * @note In case the user software does not guarantee that the event EV2 is + * managed before the current byte end of transfer, then user may check on EV2 + * and BTF flag at the same time (ie. (I2C_EVENT_SLAVE_BYTE_RECEIVED | I2C_FLAG_BTF)). + * In this case the communication may be slower. + * + */ + +/* Slave RECEIVER mode --------------------------*/ +/* --EV2 */ +#define I2C_EVENT_SLAVE_BYTE_RECEIVED ((uint32_t)0x00020040) /* BUSY and RXNE flags */ +/* --EV4 */ +#define I2C_EVENT_SLAVE_STOP_DETECTED ((uint32_t)0x00000010) /* STOPF flag */ + +/* Slave TRANSMITTER mode -----------------------*/ +/* --EV3 */ +#define I2C_EVENT_SLAVE_BYTE_TRANSMITTED ((uint32_t)0x00060084) /* TRA, BUSY, TXE and BTF flags */ +#define I2C_EVENT_SLAVE_BYTE_TRANSMITTING ((uint32_t)0x00060080) /* TRA, BUSY and TXE flags */ +/* --EV3_2 */ +#define I2C_EVENT_SLAVE_ACK_FAILURE ((uint32_t)0x00000400) /* AF flag */ + +/*=========================== End of Events Description ==========================================*/ + +#define IS_I2C_EVENT(EVENT) (((EVENT) == I2C_EVENT_SLAVE_TRANSMITTER_ADDRESS_MATCHED) || \ + ((EVENT) == I2C_EVENT_SLAVE_RECEIVER_ADDRESS_MATCHED) || \ + ((EVENT) == I2C_EVENT_SLAVE_TRANSMITTER_SECONDADDRESS_MATCHED) || \ + ((EVENT) == I2C_EVENT_SLAVE_RECEIVER_SECONDADDRESS_MATCHED) || \ + ((EVENT) == I2C_EVENT_SLAVE_GENERALCALLADDRESS_MATCHED) || \ + ((EVENT) == I2C_EVENT_SLAVE_BYTE_RECEIVED) || \ + ((EVENT) == (I2C_EVENT_SLAVE_BYTE_RECEIVED | I2C_FLAG_DUALF)) || \ + ((EVENT) == (I2C_EVENT_SLAVE_BYTE_RECEIVED | I2C_FLAG_GENCALL)) || \ + ((EVENT) == I2C_EVENT_SLAVE_BYTE_TRANSMITTED) || \ + ((EVENT) == (I2C_EVENT_SLAVE_BYTE_TRANSMITTED | I2C_FLAG_DUALF)) || \ + ((EVENT) == (I2C_EVENT_SLAVE_BYTE_TRANSMITTED | I2C_FLAG_GENCALL)) || \ + ((EVENT) == I2C_EVENT_SLAVE_STOP_DETECTED) || \ + ((EVENT) == I2C_EVENT_MASTER_MODE_SELECT) || \ + ((EVENT) == I2C_EVENT_MASTER_TRANSMITTER_MODE_SELECTED) || \ + ((EVENT) == I2C_EVENT_MASTER_RECEIVER_MODE_SELECTED) || \ + ((EVENT) == I2C_EVENT_MASTER_BYTE_RECEIVED) || \ + ((EVENT) == I2C_EVENT_MASTER_BYTE_TRANSMITTED) || \ + ((EVENT) == I2C_EVENT_MASTER_BYTE_TRANSMITTING) || \ + ((EVENT) == I2C_EVENT_MASTER_MODE_ADDRESS10) || \ + ((EVENT) == I2C_EVENT_SLAVE_ACK_FAILURE)) +/** + * @} + */ + +/** @defgroup I2C_own_address1 + * @{ + */ + +#define IS_I2C_OWN_ADDRESS1(ADDRESS1) ((ADDRESS1) <= 0x3FF) +/** + * @} + */ + +/** @defgroup I2C_clock_speed + * @{ + */ + +#define IS_I2C_CLOCK_SPEED(SPEED) (((SPEED) >= 0x1) && ((SPEED) <= 400000)) +/** + * @} + */ + +/** + * @} + */ + +/** @defgroup I2C_Exported_Macros + * @{ + */ + +/** + * @} + */ + +/** @defgroup I2C_Exported_Functions + * @{ + */ + +void I2C_DeInit(I2C_TypeDef* I2Cx); +void I2C_Init(I2C_TypeDef* I2Cx, I2C_InitTypeDef* I2C_InitStruct); +void I2C_StructInit(I2C_InitTypeDef* I2C_InitStruct); +void I2C_Cmd(I2C_TypeDef* I2Cx, FunctionalState NewState); +void I2C_DMACmd(I2C_TypeDef* I2Cx, FunctionalState NewState); +void I2C_DMALastTransferCmd(I2C_TypeDef* I2Cx, FunctionalState NewState); +void I2C_GenerateSTART(I2C_TypeDef* I2Cx, FunctionalState NewState); +void I2C_GenerateSTOP(I2C_TypeDef* I2Cx, FunctionalState NewState); +void I2C_AcknowledgeConfig(I2C_TypeDef* I2Cx, FunctionalState NewState); +void I2C_OwnAddress2Config(I2C_TypeDef* I2Cx, uint8_t Address); +void I2C_DualAddressCmd(I2C_TypeDef* I2Cx, FunctionalState NewState); +void I2C_GeneralCallCmd(I2C_TypeDef* I2Cx, FunctionalState NewState); +void I2C_ITConfig(I2C_TypeDef* I2Cx, uint16_t I2C_IT, FunctionalState NewState); +void I2C_SendData(I2C_TypeDef* I2Cx, uint8_t Data); +uint8_t I2C_ReceiveData(I2C_TypeDef* I2Cx); +void I2C_Send7bitAddress(I2C_TypeDef* I2Cx, uint8_t Address, uint8_t I2C_Direction); +uint16_t I2C_ReadRegister(I2C_TypeDef* I2Cx, uint8_t I2C_Register); +void I2C_SoftwareResetCmd(I2C_TypeDef* I2Cx, FunctionalState NewState); +void I2C_NACKPositionConfig(I2C_TypeDef* I2Cx, uint16_t I2C_NACKPosition); +void I2C_SMBusAlertConfig(I2C_TypeDef* I2Cx, uint16_t I2C_SMBusAlert); +void I2C_TransmitPEC(I2C_TypeDef* I2Cx, FunctionalState NewState); +void I2C_PECPositionConfig(I2C_TypeDef* I2Cx, uint16_t I2C_PECPosition); +void I2C_CalculatePEC(I2C_TypeDef* I2Cx, FunctionalState NewState); +uint8_t I2C_GetPEC(I2C_TypeDef* I2Cx); +void I2C_ARPCmd(I2C_TypeDef* I2Cx, FunctionalState NewState); +void I2C_StretchClockCmd(I2C_TypeDef* I2Cx, FunctionalState NewState); +void I2C_FastModeDutyCycleConfig(I2C_TypeDef* I2Cx, uint16_t I2C_DutyCycle); + +/** + * @brief + **************************************************************************************** + * + * I2C State Monitoring Functions + * + **************************************************************************************** + * This I2C driver provides three different ways for I2C state monitoring + * depending on the application requirements and constraints: + * + * + * 1) Basic state monitoring: + * Using I2C_CheckEvent() function: + * It compares the status registers (SR1 and SR2) content to a given event + * (can be the combination of one or more flags). + * It returns SUCCESS if the current status includes the given flags + * and returns ERROR if one or more flags are missing in the current status. + * - When to use: + * - This function is suitable for most applications as well as for startup + * activity since the events are fully described in the product reference manual + * (RM0008). + * - It is also suitable for users who need to define their own events. + * - Limitations: + * - If an error occurs (ie. error flags are set besides to the monitored flags), + * the I2C_CheckEvent() function may return SUCCESS despite the communication + * hold or corrupted real state. + * In this case, it is advised to use error interrupts to monitor the error + * events and handle them in the interrupt IRQ handler. + * + * @note + * For error management, it is advised to use the following functions: + * - I2C_ITConfig() to configure and enable the error interrupts (I2C_IT_ERR). + * - I2Cx_ER_IRQHandler() which is called when the error interrupt occurs. + * Where x is the peripheral instance (I2C1, I2C2 ...) + * - I2C_GetFlagStatus() or I2C_GetITStatus() to be called into I2Cx_ER_IRQHandler() + * in order to determine which error occurred. + * - I2C_ClearFlag() or I2C_ClearITPendingBit() and/or I2C_SoftwareResetCmd() + * and/or I2C_GenerateStop() in order to clear the error flag and source, + * and return to correct communication status. + * + * + * 2) Advanced state monitoring: + * Using the function I2C_GetLastEvent() which returns the image of both status + * registers in a single word (uint32_t) (Status Register 2 value is shifted left + * by 16 bits and concatenated to Status Register 1). + * - When to use: + * - This function is suitable for the same applications above but it allows to + * overcome the limitations of I2C_GetFlagStatus() function (see below). + * The returned value could be compared to events already defined in the + * library (stm32f10x_i2c.h) or to custom values defined by user. + * - This function is suitable when multiple flags are monitored at the same time. + * - At the opposite of I2C_CheckEvent() function, this function allows user to + * choose when an event is accepted (when all events flags are set and no + * other flags are set or just when the needed flags are set like + * I2C_CheckEvent() function). + * - Limitations: + * - User may need to define his own events. + * - Same remark concerning the error management is applicable for this + * function if user decides to check only regular communication flags (and + * ignores error flags). + * + * + * 3) Flag-based state monitoring: + * Using the function I2C_GetFlagStatus() which simply returns the status of + * one single flag (ie. I2C_FLAG_RXNE ...). + * - When to use: + * - This function could be used for specific applications or in debug phase. + * - It is suitable when only one flag checking is needed (most I2C events + * are monitored through multiple flags). + * - Limitations: + * - When calling this function, the Status register is accessed. Some flags are + * cleared when the status register is accessed. So checking the status + * of one Flag, may clear other ones. + * - Function may need to be called twice or more in order to monitor one + * single event. + * + */ + +/** + * + * 1) Basic state monitoring + ******************************************************************************* + */ +ErrorStatus I2C_CheckEvent(I2C_TypeDef* I2Cx, uint32_t I2C_EVENT); +/** + * + * 2) Advanced state monitoring + ******************************************************************************* + */ +uint32_t I2C_GetLastEvent(I2C_TypeDef* I2Cx); +/** + * + * 3) Flag-based state monitoring + ******************************************************************************* + */ +FlagStatus I2C_GetFlagStatus(I2C_TypeDef* I2Cx, uint32_t I2C_FLAG); +/** + * + ******************************************************************************* + */ + +void I2C_ClearFlag(I2C_TypeDef* I2Cx, uint32_t I2C_FLAG); +ITStatus I2C_GetITStatus(I2C_TypeDef* I2Cx, uint32_t I2C_IT); +void I2C_ClearITPendingBit(I2C_TypeDef* I2Cx, uint32_t I2C_IT); + +#ifdef __cplusplus +} +#endif + +#endif /*__STM32F10x_I2C_H */ +/** + * @} + */ + +/** + * @} + */ + +/** + * @} + */ + +/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ diff --git a/Libraries/STM32F10x_StdPeriph_Driver/inc/stm32f10x_iwdg.h b/Libraries/STM32F10x_StdPeriph_Driver/inc/stm32f10x_iwdg.h new file mode 100644 index 0000000..971ab42 --- /dev/null +++ b/Libraries/STM32F10x_StdPeriph_Driver/inc/stm32f10x_iwdg.h @@ -0,0 +1,146 @@ +/** + ****************************************************************************** + * @file stm32f10x_iwdg.h + * @author MCD Application Team + * @version V3.6.1 + * @date 05-March-2012 + * @brief This file contains all the functions prototypes for the IWDG + * firmware library. + ****************************************************************************** + * @attention + * + *

    © COPYRIGHT 2012 STMicroelectronics

    + * + * Licensed under MCD-ST Liberty SW License Agreement V2, (the "License"); + * You may not use this file except in compliance with the License. + * You may obtain a copy of the License at: + * + * http://www.st.com/software_license_agreement_liberty_v2 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, + * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + * + ****************************************************************************** + */ + +/* Define to prevent recursive inclusion -------------------------------------*/ +#ifndef __STM32F10x_IWDG_H +#define __STM32F10x_IWDG_H + +#ifdef __cplusplus + extern "C" { +#endif + +/* Includes ------------------------------------------------------------------*/ +#include "stm32f10x.h" + +/** @addtogroup STM32F10x_StdPeriph_Driver + * @{ + */ + +/** @addtogroup IWDG + * @{ + */ + +/** @defgroup IWDG_Exported_Types + * @{ + */ + +/** + * @} + */ + +/** @defgroup IWDG_Exported_Constants + * @{ + */ + +/** @defgroup IWDG_WriteAccess + * @{ + */ + +#define IWDG_WriteAccess_Enable ((uint16_t)0x5555) +#define IWDG_WriteAccess_Disable ((uint16_t)0x0000) +#define IS_IWDG_WRITE_ACCESS(ACCESS) (((ACCESS) == IWDG_WriteAccess_Enable) || \ + ((ACCESS) == IWDG_WriteAccess_Disable)) +/** + * @} + */ + +/** @defgroup IWDG_prescaler + * @{ + */ + +#define IWDG_Prescaler_4 ((uint8_t)0x00) +#define IWDG_Prescaler_8 ((uint8_t)0x01) +#define IWDG_Prescaler_16 ((uint8_t)0x02) +#define IWDG_Prescaler_32 ((uint8_t)0x03) +#define IWDG_Prescaler_64 ((uint8_t)0x04) +#define IWDG_Prescaler_128 ((uint8_t)0x05) +#define IWDG_Prescaler_256 ((uint8_t)0x06) +#define IS_IWDG_PRESCALER(PRESCALER) (((PRESCALER) == IWDG_Prescaler_4) || \ + ((PRESCALER) == IWDG_Prescaler_8) || \ + ((PRESCALER) == IWDG_Prescaler_16) || \ + ((PRESCALER) == IWDG_Prescaler_32) || \ + ((PRESCALER) == IWDG_Prescaler_64) || \ + ((PRESCALER) == IWDG_Prescaler_128)|| \ + ((PRESCALER) == IWDG_Prescaler_256)) +/** + * @} + */ + +/** @defgroup IWDG_Flag + * @{ + */ + +#define IWDG_FLAG_PVU ((uint16_t)0x0001) +#define IWDG_FLAG_RVU ((uint16_t)0x0002) +#define IS_IWDG_FLAG(FLAG) (((FLAG) == IWDG_FLAG_PVU) || ((FLAG) == IWDG_FLAG_RVU)) +#define IS_IWDG_RELOAD(RELOAD) ((RELOAD) <= 0xFFF) +/** + * @} + */ + +/** + * @} + */ + +/** @defgroup IWDG_Exported_Macros + * @{ + */ + +/** + * @} + */ + +/** @defgroup IWDG_Exported_Functions + * @{ + */ + +void IWDG_WriteAccessCmd(uint16_t IWDG_WriteAccess); +void IWDG_SetPrescaler(uint8_t IWDG_Prescaler); +void IWDG_SetReload(uint16_t Reload); +void IWDG_ReloadCounter(void); +void IWDG_Enable(void); +FlagStatus IWDG_GetFlagStatus(uint16_t IWDG_FLAG); + +#ifdef __cplusplus +} +#endif + +#endif /* __STM32F10x_IWDG_H */ +/** + * @} + */ + +/** + * @} + */ + +/** + * @} + */ + +/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ diff --git a/Libraries/STM32F10x_StdPeriph_Driver/inc/stm32f10x_pwr.h b/Libraries/STM32F10x_StdPeriph_Driver/inc/stm32f10x_pwr.h new file mode 100644 index 0000000..ad7d2fc --- /dev/null +++ b/Libraries/STM32F10x_StdPeriph_Driver/inc/stm32f10x_pwr.h @@ -0,0 +1,162 @@ +/** + ****************************************************************************** + * @file stm32f10x_pwr.h + * @author MCD Application Team + * @version V3.6.1 + * @date 05-March-2012 + * @brief This file contains all the functions prototypes for the PWR firmware + * library. + ****************************************************************************** + * @attention + * + *

    © COPYRIGHT 2012 STMicroelectronics

    + * + * Licensed under MCD-ST Liberty SW License Agreement V2, (the "License"); + * You may not use this file except in compliance with the License. + * You may obtain a copy of the License at: + * + * http://www.st.com/software_license_agreement_liberty_v2 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, + * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + * + ****************************************************************************** + */ + +/* Define to prevent recursive inclusion -------------------------------------*/ +#ifndef __STM32F10x_PWR_H +#define __STM32F10x_PWR_H + +#ifdef __cplusplus + extern "C" { +#endif + +/* Includes ------------------------------------------------------------------*/ +#include "stm32f10x.h" + +/** @addtogroup STM32F10x_StdPeriph_Driver + * @{ + */ + +/** @addtogroup PWR + * @{ + */ + +/** @defgroup PWR_Exported_Types + * @{ + */ + +/** + * @} + */ + +/** @defgroup PWR_Exported_Constants + * @{ + */ + +/** @defgroup PVD_detection_level + * @{ + */ + +#define PWR_PVDLevel_2V2 ((uint32_t)0x00000000) +#define PWR_PVDLevel_2V3 ((uint32_t)0x00000020) +#define PWR_PVDLevel_2V4 ((uint32_t)0x00000040) +#define PWR_PVDLevel_2V5 ((uint32_t)0x00000060) +#define PWR_PVDLevel_2V6 ((uint32_t)0x00000080) +#define PWR_PVDLevel_2V7 ((uint32_t)0x000000A0) +#define PWR_PVDLevel_2V8 ((uint32_t)0x000000C0) +#define PWR_PVDLevel_2V9 ((uint32_t)0x000000E0) +#define IS_PWR_PVD_LEVEL(LEVEL) (((LEVEL) == PWR_PVDLevel_2V2) || ((LEVEL) == PWR_PVDLevel_2V3)|| \ + ((LEVEL) == PWR_PVDLevel_2V4) || ((LEVEL) == PWR_PVDLevel_2V5)|| \ + ((LEVEL) == PWR_PVDLevel_2V6) || ((LEVEL) == PWR_PVDLevel_2V7)|| \ + ((LEVEL) == PWR_PVDLevel_2V8) || ((LEVEL) == PWR_PVDLevel_2V9)) +/** + * @} + */ + +/** @defgroup Regulator_state_is_STOP_mode + * @{ + */ + +#define PWR_Regulator_ON ((uint32_t)0x00000000) +#define PWR_Regulator_LowPower ((uint32_t)0x00000001) +#define IS_PWR_REGULATOR(REGULATOR) (((REGULATOR) == PWR_Regulator_ON) || \ + ((REGULATOR) == PWR_Regulator_LowPower)) +/** + * @} + */ + +/** @defgroup STOP_mode_entry + * @{ + */ + +#define PWR_STOPEntry_WFI ((uint8_t)0x01) +#define PWR_STOPEntry_WFE ((uint8_t)0x02) +#define IS_PWR_STOP_ENTRY(ENTRY) (((ENTRY) == PWR_STOPEntry_WFI) || ((ENTRY) == PWR_STOPEntry_WFE)) + +/** + * @} + */ + +/** @defgroup PWR_Flag + * @{ + */ + +#define PWR_FLAG_WU ((uint32_t)0x00000001) +#define PWR_FLAG_SB ((uint32_t)0x00000002) +#define PWR_FLAG_PVDO ((uint32_t)0x00000004) +#define IS_PWR_GET_FLAG(FLAG) (((FLAG) == PWR_FLAG_WU) || ((FLAG) == PWR_FLAG_SB) || \ + ((FLAG) == PWR_FLAG_PVDO)) + +#define IS_PWR_CLEAR_FLAG(FLAG) (((FLAG) == PWR_FLAG_WU) || ((FLAG) == PWR_FLAG_SB)) +/** + * @} + */ + +/** + * @} + */ + +/** @defgroup PWR_Exported_Macros + * @{ + */ + +/** + * @} + */ + +/** @defgroup PWR_Exported_Functions + * @{ + */ + +void PWR_DeInit(void); +void PWR_BackupAccessCmd(FunctionalState NewState); +void PWR_PVDCmd(FunctionalState NewState); +void PWR_PVDLevelConfig(uint32_t PWR_PVDLevel); +void PWR_WakeUpPinCmd(FunctionalState NewState); +void PWR_EnterSTOPMode(uint32_t PWR_Regulator, uint8_t PWR_STOPEntry); +void PWR_EnterSTANDBYMode(void); +FlagStatus PWR_GetFlagStatus(uint32_t PWR_FLAG); +void PWR_ClearFlag(uint32_t PWR_FLAG); + +#ifdef __cplusplus +} +#endif + +#endif /* __STM32F10x_PWR_H */ +/** + * @} + */ + +/** + * @} + */ + +/** + * @} + */ + +/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ diff --git a/Libraries/STM32F10x_StdPeriph_Driver/inc/stm32f10x_rcc.h b/Libraries/STM32F10x_StdPeriph_Driver/inc/stm32f10x_rcc.h new file mode 100644 index 0000000..ffa9a45 --- /dev/null +++ b/Libraries/STM32F10x_StdPeriph_Driver/inc/stm32f10x_rcc.h @@ -0,0 +1,733 @@ +/** + ****************************************************************************** + * @file stm32f10x_rcc.h + * @author MCD Application Team + * @version V3.6.1 + * @date 05-March-2012 + * @brief This file contains all the functions prototypes for the RCC firmware + * library. + ****************************************************************************** + * @attention + * + *

    © COPYRIGHT 2012 STMicroelectronics

    + * + * Licensed under MCD-ST Liberty SW License Agreement V2, (the "License"); + * You may not use this file except in compliance with the License. + * You may obtain a copy of the License at: + * + * http://www.st.com/software_license_agreement_liberty_v2 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, + * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + * + ****************************************************************************** + */ + +/* Define to prevent recursive inclusion -------------------------------------*/ +#ifndef __STM32F10x_RCC_H +#define __STM32F10x_RCC_H + +#ifdef __cplusplus + extern "C" { +#endif + +/* Includes ------------------------------------------------------------------*/ +#include "stm32f10x.h" + +/** @addtogroup STM32F10x_StdPeriph_Driver + * @{ + */ + +/** @addtogroup RCC + * @{ + */ + +/** @defgroup RCC_Exported_Types + * @{ + */ + +typedef struct +{ + uint32_t SYSCLK_Frequency; /*!< returns SYSCLK clock frequency expressed in Hz */ + uint32_t HCLK_Frequency; /*!< returns HCLK clock frequency expressed in Hz */ + uint32_t PCLK1_Frequency; /*!< returns PCLK1 clock frequency expressed in Hz */ + uint32_t PCLK2_Frequency; /*!< returns PCLK2 clock frequency expressed in Hz */ + uint32_t ADCCLK_Frequency; /*!< returns ADCCLK clock frequency expressed in Hz */ +}RCC_ClocksTypeDef; + +/** + * @} + */ + +/** @defgroup RCC_Exported_Constants + * @{ + */ + +/** @defgroup HSE_configuration + * @{ + */ + +#define RCC_HSE_OFF ((uint32_t)0x00000000) +#define RCC_HSE_ON ((uint32_t)0x00010000) +#define RCC_HSE_Bypass ((uint32_t)0x00040000) +#define IS_RCC_HSE(HSE) (((HSE) == RCC_HSE_OFF) || ((HSE) == RCC_HSE_ON) || \ + ((HSE) == RCC_HSE_Bypass)) + +/** + * @} + */ + +/** @defgroup PLL_entry_clock_source + * @{ + */ + +#define RCC_PLLSource_HSI_Div2 ((uint32_t)0x00000000) + +#if !defined (STM32F10X_LD_VL) && !defined (STM32F10X_MD_VL) && !defined (STM32F10X_HD_VL) && !defined (STM32F10X_CL) + #define RCC_PLLSource_HSE_Div1 ((uint32_t)0x00010000) + #define RCC_PLLSource_HSE_Div2 ((uint32_t)0x00030000) + #define IS_RCC_PLL_SOURCE(SOURCE) (((SOURCE) == RCC_PLLSource_HSI_Div2) || \ + ((SOURCE) == RCC_PLLSource_HSE_Div1) || \ + ((SOURCE) == RCC_PLLSource_HSE_Div2)) +#else + #define RCC_PLLSource_PREDIV1 ((uint32_t)0x00010000) + #define IS_RCC_PLL_SOURCE(SOURCE) (((SOURCE) == RCC_PLLSource_HSI_Div2) || \ + ((SOURCE) == RCC_PLLSource_PREDIV1)) +#endif /* STM32F10X_CL */ + +/** + * @} + */ + +/** @defgroup PLL_multiplication_factor + * @{ + */ +#ifndef STM32F10X_CL + #define RCC_PLLMul_2 ((uint32_t)0x00000000) + #define RCC_PLLMul_3 ((uint32_t)0x00040000) + #define RCC_PLLMul_4 ((uint32_t)0x00080000) + #define RCC_PLLMul_5 ((uint32_t)0x000C0000) + #define RCC_PLLMul_6 ((uint32_t)0x00100000) + #define RCC_PLLMul_7 ((uint32_t)0x00140000) + #define RCC_PLLMul_8 ((uint32_t)0x00180000) + #define RCC_PLLMul_9 ((uint32_t)0x001C0000) + #define RCC_PLLMul_10 ((uint32_t)0x00200000) + #define RCC_PLLMul_11 ((uint32_t)0x00240000) + #define RCC_PLLMul_12 ((uint32_t)0x00280000) + #define RCC_PLLMul_13 ((uint32_t)0x002C0000) + #define RCC_PLLMul_14 ((uint32_t)0x00300000) + #define RCC_PLLMul_15 ((uint32_t)0x00340000) + #define RCC_PLLMul_16 ((uint32_t)0x00380000) + #define IS_RCC_PLL_MUL(MUL) (((MUL) == RCC_PLLMul_2) || ((MUL) == RCC_PLLMul_3) || \ + ((MUL) == RCC_PLLMul_4) || ((MUL) == RCC_PLLMul_5) || \ + ((MUL) == RCC_PLLMul_6) || ((MUL) == RCC_PLLMul_7) || \ + ((MUL) == RCC_PLLMul_8) || ((MUL) == RCC_PLLMul_9) || \ + ((MUL) == RCC_PLLMul_10) || ((MUL) == RCC_PLLMul_11) || \ + ((MUL) == RCC_PLLMul_12) || ((MUL) == RCC_PLLMul_13) || \ + ((MUL) == RCC_PLLMul_14) || ((MUL) == RCC_PLLMul_15) || \ + ((MUL) == RCC_PLLMul_16)) + +#else + #define RCC_PLLMul_4 ((uint32_t)0x00080000) + #define RCC_PLLMul_5 ((uint32_t)0x000C0000) + #define RCC_PLLMul_6 ((uint32_t)0x00100000) + #define RCC_PLLMul_7 ((uint32_t)0x00140000) + #define RCC_PLLMul_8 ((uint32_t)0x00180000) + #define RCC_PLLMul_9 ((uint32_t)0x001C0000) + #define RCC_PLLMul_6_5 ((uint32_t)0x00340000) + + #define IS_RCC_PLL_MUL(MUL) (((MUL) == RCC_PLLMul_4) || ((MUL) == RCC_PLLMul_5) || \ + ((MUL) == RCC_PLLMul_6) || ((MUL) == RCC_PLLMul_7) || \ + ((MUL) == RCC_PLLMul_8) || ((MUL) == RCC_PLLMul_9) || \ + ((MUL) == RCC_PLLMul_6_5)) +#endif /* STM32F10X_CL */ +/** + * @} + */ + +/** @defgroup PREDIV1_division_factor + * @{ + */ +#if defined (STM32F10X_LD_VL) || defined (STM32F10X_MD_VL) || defined (STM32F10X_HD_VL) || defined (STM32F10X_CL) + #define RCC_PREDIV1_Div1 ((uint32_t)0x00000000) + #define RCC_PREDIV1_Div2 ((uint32_t)0x00000001) + #define RCC_PREDIV1_Div3 ((uint32_t)0x00000002) + #define RCC_PREDIV1_Div4 ((uint32_t)0x00000003) + #define RCC_PREDIV1_Div5 ((uint32_t)0x00000004) + #define RCC_PREDIV1_Div6 ((uint32_t)0x00000005) + #define RCC_PREDIV1_Div7 ((uint32_t)0x00000006) + #define RCC_PREDIV1_Div8 ((uint32_t)0x00000007) + #define RCC_PREDIV1_Div9 ((uint32_t)0x00000008) + #define RCC_PREDIV1_Div10 ((uint32_t)0x00000009) + #define RCC_PREDIV1_Div11 ((uint32_t)0x0000000A) + #define RCC_PREDIV1_Div12 ((uint32_t)0x0000000B) + #define RCC_PREDIV1_Div13 ((uint32_t)0x0000000C) + #define RCC_PREDIV1_Div14 ((uint32_t)0x0000000D) + #define RCC_PREDIV1_Div15 ((uint32_t)0x0000000E) + #define RCC_PREDIV1_Div16 ((uint32_t)0x0000000F) + + #define IS_RCC_PREDIV1(PREDIV1) (((PREDIV1) == RCC_PREDIV1_Div1) || ((PREDIV1) == RCC_PREDIV1_Div2) || \ + ((PREDIV1) == RCC_PREDIV1_Div3) || ((PREDIV1) == RCC_PREDIV1_Div4) || \ + ((PREDIV1) == RCC_PREDIV1_Div5) || ((PREDIV1) == RCC_PREDIV1_Div6) || \ + ((PREDIV1) == RCC_PREDIV1_Div7) || ((PREDIV1) == RCC_PREDIV1_Div8) || \ + ((PREDIV1) == RCC_PREDIV1_Div9) || ((PREDIV1) == RCC_PREDIV1_Div10) || \ + ((PREDIV1) == RCC_PREDIV1_Div11) || ((PREDIV1) == RCC_PREDIV1_Div12) || \ + ((PREDIV1) == RCC_PREDIV1_Div13) || ((PREDIV1) == RCC_PREDIV1_Div14) || \ + ((PREDIV1) == RCC_PREDIV1_Div15) || ((PREDIV1) == RCC_PREDIV1_Div16)) +#endif +/** + * @} + */ + + +/** @defgroup PREDIV1_clock_source + * @{ + */ +#ifdef STM32F10X_CL +/* PREDIV1 clock source (for STM32 connectivity line devices) */ + #define RCC_PREDIV1_Source_HSE ((uint32_t)0x00000000) + #define RCC_PREDIV1_Source_PLL2 ((uint32_t)0x00010000) + + #define IS_RCC_PREDIV1_SOURCE(SOURCE) (((SOURCE) == RCC_PREDIV1_Source_HSE) || \ + ((SOURCE) == RCC_PREDIV1_Source_PLL2)) +#elif defined (STM32F10X_LD_VL) || defined (STM32F10X_MD_VL) || defined (STM32F10X_HD_VL) +/* PREDIV1 clock source (for STM32 Value line devices) */ + #define RCC_PREDIV1_Source_HSE ((uint32_t)0x00000000) + + #define IS_RCC_PREDIV1_SOURCE(SOURCE) (((SOURCE) == RCC_PREDIV1_Source_HSE)) +#endif +/** + * @} + */ + +#ifdef STM32F10X_CL +/** @defgroup PREDIV2_division_factor + * @{ + */ + + #define RCC_PREDIV2_Div1 ((uint32_t)0x00000000) + #define RCC_PREDIV2_Div2 ((uint32_t)0x00000010) + #define RCC_PREDIV2_Div3 ((uint32_t)0x00000020) + #define RCC_PREDIV2_Div4 ((uint32_t)0x00000030) + #define RCC_PREDIV2_Div5 ((uint32_t)0x00000040) + #define RCC_PREDIV2_Div6 ((uint32_t)0x00000050) + #define RCC_PREDIV2_Div7 ((uint32_t)0x00000060) + #define RCC_PREDIV2_Div8 ((uint32_t)0x00000070) + #define RCC_PREDIV2_Div9 ((uint32_t)0x00000080) + #define RCC_PREDIV2_Div10 ((uint32_t)0x00000090) + #define RCC_PREDIV2_Div11 ((uint32_t)0x000000A0) + #define RCC_PREDIV2_Div12 ((uint32_t)0x000000B0) + #define RCC_PREDIV2_Div13 ((uint32_t)0x000000C0) + #define RCC_PREDIV2_Div14 ((uint32_t)0x000000D0) + #define RCC_PREDIV2_Div15 ((uint32_t)0x000000E0) + #define RCC_PREDIV2_Div16 ((uint32_t)0x000000F0) + + #define IS_RCC_PREDIV2(PREDIV2) (((PREDIV2) == RCC_PREDIV2_Div1) || ((PREDIV2) == RCC_PREDIV2_Div2) || \ + ((PREDIV2) == RCC_PREDIV2_Div3) || ((PREDIV2) == RCC_PREDIV2_Div4) || \ + ((PREDIV2) == RCC_PREDIV2_Div5) || ((PREDIV2) == RCC_PREDIV2_Div6) || \ + ((PREDIV2) == RCC_PREDIV2_Div7) || ((PREDIV2) == RCC_PREDIV2_Div8) || \ + ((PREDIV2) == RCC_PREDIV2_Div9) || ((PREDIV2) == RCC_PREDIV2_Div10) || \ + ((PREDIV2) == RCC_PREDIV2_Div11) || ((PREDIV2) == RCC_PREDIV2_Div12) || \ + ((PREDIV2) == RCC_PREDIV2_Div13) || ((PREDIV2) == RCC_PREDIV2_Div14) || \ + ((PREDIV2) == RCC_PREDIV2_Div15) || ((PREDIV2) == RCC_PREDIV2_Div16)) +/** + * @} + */ + + +/** @defgroup PLL2_multiplication_factor + * @{ + */ + + #define RCC_PLL2Mul_8 ((uint32_t)0x00000600) + #define RCC_PLL2Mul_9 ((uint32_t)0x00000700) + #define RCC_PLL2Mul_10 ((uint32_t)0x00000800) + #define RCC_PLL2Mul_11 ((uint32_t)0x00000900) + #define RCC_PLL2Mul_12 ((uint32_t)0x00000A00) + #define RCC_PLL2Mul_13 ((uint32_t)0x00000B00) + #define RCC_PLL2Mul_14 ((uint32_t)0x00000C00) + #define RCC_PLL2Mul_16 ((uint32_t)0x00000E00) + #define RCC_PLL2Mul_20 ((uint32_t)0x00000F00) + + #define IS_RCC_PLL2_MUL(MUL) (((MUL) == RCC_PLL2Mul_8) || ((MUL) == RCC_PLL2Mul_9) || \ + ((MUL) == RCC_PLL2Mul_10) || ((MUL) == RCC_PLL2Mul_11) || \ + ((MUL) == RCC_PLL2Mul_12) || ((MUL) == RCC_PLL2Mul_13) || \ + ((MUL) == RCC_PLL2Mul_14) || ((MUL) == RCC_PLL2Mul_16) || \ + ((MUL) == RCC_PLL2Mul_20)) +/** + * @} + */ + + +/** @defgroup PLL3_multiplication_factor + * @{ + */ + + #define RCC_PLL3Mul_8 ((uint32_t)0x00006000) + #define RCC_PLL3Mul_9 ((uint32_t)0x00007000) + #define RCC_PLL3Mul_10 ((uint32_t)0x00008000) + #define RCC_PLL3Mul_11 ((uint32_t)0x00009000) + #define RCC_PLL3Mul_12 ((uint32_t)0x0000A000) + #define RCC_PLL3Mul_13 ((uint32_t)0x0000B000) + #define RCC_PLL3Mul_14 ((uint32_t)0x0000C000) + #define RCC_PLL3Mul_16 ((uint32_t)0x0000E000) + #define RCC_PLL3Mul_20 ((uint32_t)0x0000F000) + + #define IS_RCC_PLL3_MUL(MUL) (((MUL) == RCC_PLL3Mul_8) || ((MUL) == RCC_PLL3Mul_9) || \ + ((MUL) == RCC_PLL3Mul_10) || ((MUL) == RCC_PLL3Mul_11) || \ + ((MUL) == RCC_PLL3Mul_12) || ((MUL) == RCC_PLL3Mul_13) || \ + ((MUL) == RCC_PLL3Mul_14) || ((MUL) == RCC_PLL3Mul_16) || \ + ((MUL) == RCC_PLL3Mul_20)) +/** + * @} + */ + +#endif /* STM32F10X_CL */ + + +/** @defgroup System_clock_source + * @{ + */ + +#define RCC_SYSCLKSource_HSI ((uint32_t)0x00000000) +#define RCC_SYSCLKSource_HSE ((uint32_t)0x00000001) +#define RCC_SYSCLKSource_PLLCLK ((uint32_t)0x00000002) +#define IS_RCC_SYSCLK_SOURCE(SOURCE) (((SOURCE) == RCC_SYSCLKSource_HSI) || \ + ((SOURCE) == RCC_SYSCLKSource_HSE) || \ + ((SOURCE) == RCC_SYSCLKSource_PLLCLK)) +/** + * @} + */ + +/** @defgroup AHB_clock_source + * @{ + */ + +#define RCC_SYSCLK_Div1 ((uint32_t)0x00000000) +#define RCC_SYSCLK_Div2 ((uint32_t)0x00000080) +#define RCC_SYSCLK_Div4 ((uint32_t)0x00000090) +#define RCC_SYSCLK_Div8 ((uint32_t)0x000000A0) +#define RCC_SYSCLK_Div16 ((uint32_t)0x000000B0) +#define RCC_SYSCLK_Div64 ((uint32_t)0x000000C0) +#define RCC_SYSCLK_Div128 ((uint32_t)0x000000D0) +#define RCC_SYSCLK_Div256 ((uint32_t)0x000000E0) +#define RCC_SYSCLK_Div512 ((uint32_t)0x000000F0) +#define IS_RCC_HCLK(HCLK) (((HCLK) == RCC_SYSCLK_Div1) || ((HCLK) == RCC_SYSCLK_Div2) || \ + ((HCLK) == RCC_SYSCLK_Div4) || ((HCLK) == RCC_SYSCLK_Div8) || \ + ((HCLK) == RCC_SYSCLK_Div16) || ((HCLK) == RCC_SYSCLK_Div64) || \ + ((HCLK) == RCC_SYSCLK_Div128) || ((HCLK) == RCC_SYSCLK_Div256) || \ + ((HCLK) == RCC_SYSCLK_Div512)) +/** + * @} + */ + +/** @defgroup APB1_APB2_clock_source + * @{ + */ + +#define RCC_HCLK_Div1 ((uint32_t)0x00000000) +#define RCC_HCLK_Div2 ((uint32_t)0x00000400) +#define RCC_HCLK_Div4 ((uint32_t)0x00000500) +#define RCC_HCLK_Div8 ((uint32_t)0x00000600) +#define RCC_HCLK_Div16 ((uint32_t)0x00000700) +#define IS_RCC_PCLK(PCLK) (((PCLK) == RCC_HCLK_Div1) || ((PCLK) == RCC_HCLK_Div2) || \ + ((PCLK) == RCC_HCLK_Div4) || ((PCLK) == RCC_HCLK_Div8) || \ + ((PCLK) == RCC_HCLK_Div16)) +/** + * @} + */ + +/** @defgroup RCC_Interrupt_source + * @{ + */ + +#define RCC_IT_LSIRDY ((uint8_t)0x01) +#define RCC_IT_LSERDY ((uint8_t)0x02) +#define RCC_IT_HSIRDY ((uint8_t)0x04) +#define RCC_IT_HSERDY ((uint8_t)0x08) +#define RCC_IT_PLLRDY ((uint8_t)0x10) +#define RCC_IT_CSS ((uint8_t)0x80) + +#ifndef STM32F10X_CL + #define IS_RCC_IT(IT) ((((IT) & (uint8_t)0xE0) == 0x00) && ((IT) != 0x00)) + #define IS_RCC_GET_IT(IT) (((IT) == RCC_IT_LSIRDY) || ((IT) == RCC_IT_LSERDY) || \ + ((IT) == RCC_IT_HSIRDY) || ((IT) == RCC_IT_HSERDY) || \ + ((IT) == RCC_IT_PLLRDY) || ((IT) == RCC_IT_CSS)) + #define IS_RCC_CLEAR_IT(IT) ((((IT) & (uint8_t)0x60) == 0x00) && ((IT) != 0x00)) +#else + #define RCC_IT_PLL2RDY ((uint8_t)0x20) + #define RCC_IT_PLL3RDY ((uint8_t)0x40) + #define IS_RCC_IT(IT) ((((IT) & (uint8_t)0x80) == 0x00) && ((IT) != 0x00)) + #define IS_RCC_GET_IT(IT) (((IT) == RCC_IT_LSIRDY) || ((IT) == RCC_IT_LSERDY) || \ + ((IT) == RCC_IT_HSIRDY) || ((IT) == RCC_IT_HSERDY) || \ + ((IT) == RCC_IT_PLLRDY) || ((IT) == RCC_IT_CSS) || \ + ((IT) == RCC_IT_PLL2RDY) || ((IT) == RCC_IT_PLL3RDY)) + #define IS_RCC_CLEAR_IT(IT) ((IT) != 0x00) +#endif /* STM32F10X_CL */ + + +/** + * @} + */ + +#ifndef STM32F10X_CL +/** @defgroup USB_Device_clock_source + * @{ + */ + + #define RCC_USBCLKSource_PLLCLK_1Div5 ((uint8_t)0x00) + #define RCC_USBCLKSource_PLLCLK_Div1 ((uint8_t)0x01) + + #define IS_RCC_USBCLK_SOURCE(SOURCE) (((SOURCE) == RCC_USBCLKSource_PLLCLK_1Div5) || \ + ((SOURCE) == RCC_USBCLKSource_PLLCLK_Div1)) +/** + * @} + */ +#else +/** @defgroup USB_OTG_FS_clock_source + * @{ + */ + #define RCC_OTGFSCLKSource_PLLVCO_Div3 ((uint8_t)0x00) + #define RCC_OTGFSCLKSource_PLLVCO_Div2 ((uint8_t)0x01) + + #define IS_RCC_OTGFSCLK_SOURCE(SOURCE) (((SOURCE) == RCC_OTGFSCLKSource_PLLVCO_Div3) || \ + ((SOURCE) == RCC_OTGFSCLKSource_PLLVCO_Div2)) +/** + * @} + */ +#endif /* STM32F10X_CL */ + + +#ifdef STM32F10X_CL +/** @defgroup I2S2_clock_source + * @{ + */ + #define RCC_I2S2CLKSource_SYSCLK ((uint8_t)0x00) + #define RCC_I2S2CLKSource_PLL3_VCO ((uint8_t)0x01) + + #define IS_RCC_I2S2CLK_SOURCE(SOURCE) (((SOURCE) == RCC_I2S2CLKSource_SYSCLK) || \ + ((SOURCE) == RCC_I2S2CLKSource_PLL3_VCO)) +/** + * @} + */ + +/** @defgroup I2S3_clock_source + * @{ + */ + #define RCC_I2S3CLKSource_SYSCLK ((uint8_t)0x00) + #define RCC_I2S3CLKSource_PLL3_VCO ((uint8_t)0x01) + + #define IS_RCC_I2S3CLK_SOURCE(SOURCE) (((SOURCE) == RCC_I2S3CLKSource_SYSCLK) || \ + ((SOURCE) == RCC_I2S3CLKSource_PLL3_VCO)) +/** + * @} + */ +#endif /* STM32F10X_CL */ + + +/** @defgroup ADC_clock_source + * @{ + */ + +#define RCC_PCLK2_Div2 ((uint32_t)0x00000000) +#define RCC_PCLK2_Div4 ((uint32_t)0x00004000) +#define RCC_PCLK2_Div6 ((uint32_t)0x00008000) +#define RCC_PCLK2_Div8 ((uint32_t)0x0000C000) +#define IS_RCC_ADCCLK(ADCCLK) (((ADCCLK) == RCC_PCLK2_Div2) || ((ADCCLK) == RCC_PCLK2_Div4) || \ + ((ADCCLK) == RCC_PCLK2_Div6) || ((ADCCLK) == RCC_PCLK2_Div8)) +/** + * @} + */ + +/** @defgroup LSE_configuration + * @{ + */ + +#define RCC_LSE_OFF ((uint8_t)0x00) +#define RCC_LSE_ON ((uint8_t)0x01) +#define RCC_LSE_Bypass ((uint8_t)0x04) +#define IS_RCC_LSE(LSE) (((LSE) == RCC_LSE_OFF) || ((LSE) == RCC_LSE_ON) || \ + ((LSE) == RCC_LSE_Bypass)) +/** + * @} + */ + +/** @defgroup RTC_clock_source + * @{ + */ + +#define RCC_RTCCLKSource_LSE ((uint32_t)0x00000100) +#define RCC_RTCCLKSource_LSI ((uint32_t)0x00000200) +#define RCC_RTCCLKSource_HSE_Div128 ((uint32_t)0x00000300) +#define IS_RCC_RTCCLK_SOURCE(SOURCE) (((SOURCE) == RCC_RTCCLKSource_LSE) || \ + ((SOURCE) == RCC_RTCCLKSource_LSI) || \ + ((SOURCE) == RCC_RTCCLKSource_HSE_Div128)) +/** + * @} + */ + +/** @defgroup AHB_peripheral + * @{ + */ + +#define RCC_AHBPeriph_DMA1 ((uint32_t)0x00000001) +#define RCC_AHBPeriph_DMA2 ((uint32_t)0x00000002) +#define RCC_AHBPeriph_SRAM ((uint32_t)0x00000004) +#define RCC_AHBPeriph_FLITF ((uint32_t)0x00000010) +#define RCC_AHBPeriph_CRC ((uint32_t)0x00000040) + +#ifndef STM32F10X_CL + #define RCC_AHBPeriph_FSMC ((uint32_t)0x00000100) + #define RCC_AHBPeriph_SDIO ((uint32_t)0x00000400) + #define IS_RCC_AHB_PERIPH(PERIPH) ((((PERIPH) & 0xFFFFFAA8) == 0x00) && ((PERIPH) != 0x00)) +#else + #define RCC_AHBPeriph_OTG_FS ((uint32_t)0x00001000) + #define RCC_AHBPeriph_ETH_MAC ((uint32_t)0x00004000) + #define RCC_AHBPeriph_ETH_MAC_Tx ((uint32_t)0x00008000) + #define RCC_AHBPeriph_ETH_MAC_Rx ((uint32_t)0x00010000) + + #define IS_RCC_AHB_PERIPH(PERIPH) ((((PERIPH) & 0xFFFE2FA8) == 0x00) && ((PERIPH) != 0x00)) + #define IS_RCC_AHB_PERIPH_RESET(PERIPH) ((((PERIPH) & 0xFFFFAFFF) == 0x00) && ((PERIPH) != 0x00)) +#endif /* STM32F10X_CL */ +/** + * @} + */ + +/** @defgroup APB2_peripheral + * @{ + */ + +#define RCC_APB2Periph_AFIO ((uint32_t)0x00000001) +#define RCC_APB2Periph_GPIOA ((uint32_t)0x00000004) +#define RCC_APB2Periph_GPIOB ((uint32_t)0x00000008) +#define RCC_APB2Periph_GPIOC ((uint32_t)0x00000010) +#define RCC_APB2Periph_GPIOD ((uint32_t)0x00000020) +#define RCC_APB2Periph_GPIOE ((uint32_t)0x00000040) +#define RCC_APB2Periph_GPIOF ((uint32_t)0x00000080) +#define RCC_APB2Periph_GPIOG ((uint32_t)0x00000100) +#define RCC_APB2Periph_ADC1 ((uint32_t)0x00000200) +#define RCC_APB2Periph_ADC2 ((uint32_t)0x00000400) +#define RCC_APB2Periph_TIM1 ((uint32_t)0x00000800) +#define RCC_APB2Periph_SPI1 ((uint32_t)0x00001000) +#define RCC_APB2Periph_TIM8 ((uint32_t)0x00002000) +#define RCC_APB2Periph_USART1 ((uint32_t)0x00004000) +#define RCC_APB2Periph_ADC3 ((uint32_t)0x00008000) +#define RCC_APB2Periph_TIM15 ((uint32_t)0x00010000) +#define RCC_APB2Periph_TIM16 ((uint32_t)0x00020000) +#define RCC_APB2Periph_TIM17 ((uint32_t)0x00040000) +#define RCC_APB2Periph_TIM9 ((uint32_t)0x00080000) +#define RCC_APB2Periph_TIM10 ((uint32_t)0x00100000) +#define RCC_APB2Periph_TIM11 ((uint32_t)0x00200000) + +#define IS_RCC_APB2_PERIPH(PERIPH) ((((PERIPH) & 0xFFC00002) == 0x00) && ((PERIPH) != 0x00)) +/** + * @} + */ + +/** @defgroup APB1_peripheral + * @{ + */ + +#define RCC_APB1Periph_TIM2 ((uint32_t)0x00000001) +#define RCC_APB1Periph_TIM3 ((uint32_t)0x00000002) +#define RCC_APB1Periph_TIM4 ((uint32_t)0x00000004) +#define RCC_APB1Periph_TIM5 ((uint32_t)0x00000008) +#define RCC_APB1Periph_TIM6 ((uint32_t)0x00000010) +#define RCC_APB1Periph_TIM7 ((uint32_t)0x00000020) +#define RCC_APB1Periph_TIM12 ((uint32_t)0x00000040) +#define RCC_APB1Periph_TIM13 ((uint32_t)0x00000080) +#define RCC_APB1Periph_TIM14 ((uint32_t)0x00000100) +#define RCC_APB1Periph_WWDG ((uint32_t)0x00000800) +#define RCC_APB1Periph_SPI2 ((uint32_t)0x00004000) +#define RCC_APB1Periph_SPI3 ((uint32_t)0x00008000) +#define RCC_APB1Periph_USART2 ((uint32_t)0x00020000) +#define RCC_APB1Periph_USART3 ((uint32_t)0x00040000) +#define RCC_APB1Periph_UART4 ((uint32_t)0x00080000) +#define RCC_APB1Periph_UART5 ((uint32_t)0x00100000) +#define RCC_APB1Periph_I2C1 ((uint32_t)0x00200000) +#define RCC_APB1Periph_I2C2 ((uint32_t)0x00400000) +#define RCC_APB1Periph_USB ((uint32_t)0x00800000) +#define RCC_APB1Periph_CAN1 ((uint32_t)0x02000000) +#define RCC_APB1Periph_CAN2 ((uint32_t)0x04000000) +#define RCC_APB1Periph_BKP ((uint32_t)0x08000000) +#define RCC_APB1Periph_PWR ((uint32_t)0x10000000) +#define RCC_APB1Periph_DAC ((uint32_t)0x20000000) +#define RCC_APB1Periph_CEC ((uint32_t)0x40000000) + +#define IS_RCC_APB1_PERIPH(PERIPH) ((((PERIPH) & 0x81013600) == 0x00) && ((PERIPH) != 0x00)) + +/** + * @} + */ + +/** @defgroup Clock_source_to_output_on_MCO_pin + * @{ + */ + +#define RCC_MCO_NoClock ((uint8_t)0x00) +#define RCC_MCO_SYSCLK ((uint8_t)0x04) +#define RCC_MCO_HSI ((uint8_t)0x05) +#define RCC_MCO_HSE ((uint8_t)0x06) +#define RCC_MCO_PLLCLK_Div2 ((uint8_t)0x07) + +#ifndef STM32F10X_CL + #define IS_RCC_MCO(MCO) (((MCO) == RCC_MCO_NoClock) || ((MCO) == RCC_MCO_HSI) || \ + ((MCO) == RCC_MCO_SYSCLK) || ((MCO) == RCC_MCO_HSE) || \ + ((MCO) == RCC_MCO_PLLCLK_Div2)) +#else + #define RCC_MCO_PLL2CLK ((uint8_t)0x08) + #define RCC_MCO_PLL3CLK_Div2 ((uint8_t)0x09) + #define RCC_MCO_XT1 ((uint8_t)0x0A) + #define RCC_MCO_PLL3CLK ((uint8_t)0x0B) + + #define IS_RCC_MCO(MCO) (((MCO) == RCC_MCO_NoClock) || ((MCO) == RCC_MCO_HSI) || \ + ((MCO) == RCC_MCO_SYSCLK) || ((MCO) == RCC_MCO_HSE) || \ + ((MCO) == RCC_MCO_PLLCLK_Div2) || ((MCO) == RCC_MCO_PLL2CLK) || \ + ((MCO) == RCC_MCO_PLL3CLK_Div2) || ((MCO) == RCC_MCO_XT1) || \ + ((MCO) == RCC_MCO_PLL3CLK)) +#endif /* STM32F10X_CL */ + +/** + * @} + */ + +/** @defgroup RCC_Flag + * @{ + */ + +#define RCC_FLAG_HSIRDY ((uint8_t)0x21) +#define RCC_FLAG_HSERDY ((uint8_t)0x31) +#define RCC_FLAG_PLLRDY ((uint8_t)0x39) +#define RCC_FLAG_LSERDY ((uint8_t)0x41) +#define RCC_FLAG_LSIRDY ((uint8_t)0x61) +#define RCC_FLAG_PINRST ((uint8_t)0x7A) +#define RCC_FLAG_PORRST ((uint8_t)0x7B) +#define RCC_FLAG_SFTRST ((uint8_t)0x7C) +#define RCC_FLAG_IWDGRST ((uint8_t)0x7D) +#define RCC_FLAG_WWDGRST ((uint8_t)0x7E) +#define RCC_FLAG_LPWRRST ((uint8_t)0x7F) + +#ifndef STM32F10X_CL + #define IS_RCC_FLAG(FLAG) (((FLAG) == RCC_FLAG_HSIRDY) || ((FLAG) == RCC_FLAG_HSERDY) || \ + ((FLAG) == RCC_FLAG_PLLRDY) || ((FLAG) == RCC_FLAG_LSERDY) || \ + ((FLAG) == RCC_FLAG_LSIRDY) || ((FLAG) == RCC_FLAG_PINRST) || \ + ((FLAG) == RCC_FLAG_PORRST) || ((FLAG) == RCC_FLAG_SFTRST) || \ + ((FLAG) == RCC_FLAG_IWDGRST)|| ((FLAG) == RCC_FLAG_WWDGRST)|| \ + ((FLAG) == RCC_FLAG_LPWRRST)) +#else + #define RCC_FLAG_PLL2RDY ((uint8_t)0x3B) + #define RCC_FLAG_PLL3RDY ((uint8_t)0x3D) + #define IS_RCC_FLAG(FLAG) (((FLAG) == RCC_FLAG_HSIRDY) || ((FLAG) == RCC_FLAG_HSERDY) || \ + ((FLAG) == RCC_FLAG_PLLRDY) || ((FLAG) == RCC_FLAG_LSERDY) || \ + ((FLAG) == RCC_FLAG_PLL2RDY) || ((FLAG) == RCC_FLAG_PLL3RDY) || \ + ((FLAG) == RCC_FLAG_LSIRDY) || ((FLAG) == RCC_FLAG_PINRST) || \ + ((FLAG) == RCC_FLAG_PORRST) || ((FLAG) == RCC_FLAG_SFTRST) || \ + ((FLAG) == RCC_FLAG_IWDGRST)|| ((FLAG) == RCC_FLAG_WWDGRST)|| \ + ((FLAG) == RCC_FLAG_LPWRRST)) +#endif /* STM32F10X_CL */ + +#define IS_RCC_CALIBRATION_VALUE(VALUE) ((VALUE) <= 0x1F) +/** + * @} + */ + +/** + * @} + */ + +/** @defgroup RCC_Exported_Macros + * @{ + */ + +/** + * @} + */ + +/** @defgroup RCC_Exported_Functions + * @{ + */ + +void RCC_DeInit(void); +void RCC_HSEConfig(uint32_t RCC_HSE); +ErrorStatus RCC_WaitForHSEStartUp(void); +void RCC_AdjustHSICalibrationValue(uint8_t HSICalibrationValue); +void RCC_HSICmd(FunctionalState NewState); +void RCC_PLLConfig(uint32_t RCC_PLLSource, uint32_t RCC_PLLMul); +void RCC_PLLCmd(FunctionalState NewState); + +#if defined (STM32F10X_LD_VL) || defined (STM32F10X_MD_VL) || defined (STM32F10X_HD_VL) || defined (STM32F10X_CL) + void RCC_PREDIV1Config(uint32_t RCC_PREDIV1_Source, uint32_t RCC_PREDIV1_Div); +#endif + +#ifdef STM32F10X_CL + void RCC_PREDIV2Config(uint32_t RCC_PREDIV2_Div); + void RCC_PLL2Config(uint32_t RCC_PLL2Mul); + void RCC_PLL2Cmd(FunctionalState NewState); + void RCC_PLL3Config(uint32_t RCC_PLL3Mul); + void RCC_PLL3Cmd(FunctionalState NewState); +#endif /* STM32F10X_CL */ + +void RCC_SYSCLKConfig(uint32_t RCC_SYSCLKSource); +uint8_t RCC_GetSYSCLKSource(void); +void RCC_HCLKConfig(uint32_t RCC_SYSCLK); +void RCC_PCLK1Config(uint32_t RCC_HCLK); +void RCC_PCLK2Config(uint32_t RCC_HCLK); +void RCC_ITConfig(uint8_t RCC_IT, FunctionalState NewState); + +#ifndef STM32F10X_CL + void RCC_USBCLKConfig(uint32_t RCC_USBCLKSource); +#else + void RCC_OTGFSCLKConfig(uint32_t RCC_OTGFSCLKSource); +#endif /* STM32F10X_CL */ + +void RCC_ADCCLKConfig(uint32_t RCC_PCLK2); + +#ifdef STM32F10X_CL + void RCC_I2S2CLKConfig(uint32_t RCC_I2S2CLKSource); + void RCC_I2S3CLKConfig(uint32_t RCC_I2S3CLKSource); +#endif /* STM32F10X_CL */ + +void RCC_LSEConfig(uint8_t RCC_LSE); +void RCC_LSICmd(FunctionalState NewState); +void RCC_RTCCLKConfig(uint32_t RCC_RTCCLKSource); +void RCC_RTCCLKCmd(FunctionalState NewState); +void RCC_GetClocksFreq(RCC_ClocksTypeDef* RCC_Clocks); +void RCC_AHBPeriphClockCmd(uint32_t RCC_AHBPeriph, FunctionalState NewState); +void RCC_APB2PeriphClockCmd(uint32_t RCC_APB2Periph, FunctionalState NewState); +void RCC_APB1PeriphClockCmd(uint32_t RCC_APB1Periph, FunctionalState NewState); + +#ifdef STM32F10X_CL +void RCC_AHBPeriphResetCmd(uint32_t RCC_AHBPeriph, FunctionalState NewState); +#endif /* STM32F10X_CL */ + +void RCC_APB2PeriphResetCmd(uint32_t RCC_APB2Periph, FunctionalState NewState); +void RCC_APB1PeriphResetCmd(uint32_t RCC_APB1Periph, FunctionalState NewState); +void RCC_BackupResetCmd(FunctionalState NewState); +void RCC_ClockSecuritySystemCmd(FunctionalState NewState); +void RCC_MCOConfig(uint8_t RCC_MCO); +FlagStatus RCC_GetFlagStatus(uint8_t RCC_FLAG); +void RCC_ClearFlag(void); +ITStatus RCC_GetITStatus(uint8_t RCC_IT); +void RCC_ClearITPendingBit(uint8_t RCC_IT); + +#ifdef __cplusplus +} +#endif + +#endif /* __STM32F10x_RCC_H */ +/** + * @} + */ + +/** + * @} + */ + +/** + * @} + */ + +/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ diff --git a/Libraries/STM32F10x_StdPeriph_Driver/inc/stm32f10x_rtc.h b/Libraries/STM32F10x_StdPeriph_Driver/inc/stm32f10x_rtc.h new file mode 100644 index 0000000..ad5c2c9 --- /dev/null +++ b/Libraries/STM32F10x_StdPeriph_Driver/inc/stm32f10x_rtc.h @@ -0,0 +1,141 @@ +/** + ****************************************************************************** + * @file stm32f10x_rtc.h + * @author MCD Application Team + * @version V3.6.1 + * @date 05-March-2012 + * @brief This file contains all the functions prototypes for the RTC firmware + * library. + ****************************************************************************** + * @attention + * + *

    © COPYRIGHT 2012 STMicroelectronics

    + * + * Licensed under MCD-ST Liberty SW License Agreement V2, (the "License"); + * You may not use this file except in compliance with the License. + * You may obtain a copy of the License at: + * + * http://www.st.com/software_license_agreement_liberty_v2 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, + * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + * + ****************************************************************************** + */ + +/* Define to prevent recursive inclusion -------------------------------------*/ +#ifndef __STM32F10x_RTC_H +#define __STM32F10x_RTC_H + +#ifdef __cplusplus + extern "C" { +#endif + +/* Includes ------------------------------------------------------------------*/ +#include "stm32f10x.h" + +/** @addtogroup STM32F10x_StdPeriph_Driver + * @{ + */ + +/** @addtogroup RTC + * @{ + */ + +/** @defgroup RTC_Exported_Types + * @{ + */ + +/** + * @} + */ + +/** @defgroup RTC_Exported_Constants + * @{ + */ + +/** @defgroup RTC_interrupts_define + * @{ + */ + +#define RTC_IT_OW ((uint16_t)0x0004) /*!< Overflow interrupt */ +#define RTC_IT_ALR ((uint16_t)0x0002) /*!< Alarm interrupt */ +#define RTC_IT_SEC ((uint16_t)0x0001) /*!< Second interrupt */ +#define IS_RTC_IT(IT) ((((IT) & (uint16_t)0xFFF8) == 0x00) && ((IT) != 0x00)) +#define IS_RTC_GET_IT(IT) (((IT) == RTC_IT_OW) || ((IT) == RTC_IT_ALR) || \ + ((IT) == RTC_IT_SEC)) +/** + * @} + */ + +/** @defgroup RTC_interrupts_flags + * @{ + */ + +#define RTC_FLAG_RTOFF ((uint16_t)0x0020) /*!< RTC Operation OFF flag */ +#define RTC_FLAG_RSF ((uint16_t)0x0008) /*!< Registers Synchronized flag */ +#define RTC_FLAG_OW ((uint16_t)0x0004) /*!< Overflow flag */ +#define RTC_FLAG_ALR ((uint16_t)0x0002) /*!< Alarm flag */ +#define RTC_FLAG_SEC ((uint16_t)0x0001) /*!< Second flag */ +#define IS_RTC_CLEAR_FLAG(FLAG) ((((FLAG) & (uint16_t)0xFFF0) == 0x00) && ((FLAG) != 0x00)) +#define IS_RTC_GET_FLAG(FLAG) (((FLAG) == RTC_FLAG_RTOFF) || ((FLAG) == RTC_FLAG_RSF) || \ + ((FLAG) == RTC_FLAG_OW) || ((FLAG) == RTC_FLAG_ALR) || \ + ((FLAG) == RTC_FLAG_SEC)) +#define IS_RTC_PRESCALER(PRESCALER) ((PRESCALER) <= 0xFFFFF) + +/** + * @} + */ + +/** + * @} + */ + +/** @defgroup RTC_Exported_Macros + * @{ + */ + +/** + * @} + */ + +/** @defgroup RTC_Exported_Functions + * @{ + */ + +void RTC_ITConfig(uint16_t RTC_IT, FunctionalState NewState); +void RTC_EnterConfigMode(void); +void RTC_ExitConfigMode(void); +uint32_t RTC_GetCounter(void); +void RTC_SetCounter(uint32_t CounterValue); +void RTC_SetPrescaler(uint32_t PrescalerValue); +void RTC_SetAlarm(uint32_t AlarmValue); +uint32_t RTC_GetDivider(void); +void RTC_WaitForLastTask(void); +void RTC_WaitForSynchro(void); +FlagStatus RTC_GetFlagStatus(uint16_t RTC_FLAG); +void RTC_ClearFlag(uint16_t RTC_FLAG); +ITStatus RTC_GetITStatus(uint16_t RTC_IT); +void RTC_ClearITPendingBit(uint16_t RTC_IT); + +#ifdef __cplusplus +} +#endif + +#endif /* __STM32F10x_RTC_H */ +/** + * @} + */ + +/** + * @} + */ + +/** + * @} + */ + +/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ diff --git a/Libraries/STM32F10x_StdPeriph_Driver/inc/stm32f10x_sdio.h b/Libraries/STM32F10x_StdPeriph_Driver/inc/stm32f10x_sdio.h new file mode 100644 index 0000000..d0bfe1c --- /dev/null +++ b/Libraries/STM32F10x_StdPeriph_Driver/inc/stm32f10x_sdio.h @@ -0,0 +1,537 @@ +/** + ****************************************************************************** + * @file stm32f10x_sdio.h + * @author MCD Application Team + * @version V3.6.1 + * @date 05-March-2012 + * @brief This file contains all the functions prototypes for the SDIO firmware + * library. + ****************************************************************************** + * @attention + * + *

    © COPYRIGHT 2012 STMicroelectronics

    + * + * Licensed under MCD-ST Liberty SW License Agreement V2, (the "License"); + * You may not use this file except in compliance with the License. + * You may obtain a copy of the License at: + * + * http://www.st.com/software_license_agreement_liberty_v2 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, + * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + * + ****************************************************************************** + */ + +/* Define to prevent recursive inclusion -------------------------------------*/ +#ifndef __STM32F10x_SDIO_H +#define __STM32F10x_SDIO_H + +#ifdef __cplusplus + extern "C" { +#endif + +/* Includes ------------------------------------------------------------------*/ +#include "stm32f10x.h" + +/** @addtogroup STM32F10x_StdPeriph_Driver + * @{ + */ + +/** @addtogroup SDIO + * @{ + */ + +/** @defgroup SDIO_Exported_Types + * @{ + */ + +typedef struct +{ + uint32_t SDIO_ClockEdge; /*!< Specifies the clock transition on which the bit capture is made. + This parameter can be a value of @ref SDIO_Clock_Edge */ + + uint32_t SDIO_ClockBypass; /*!< Specifies whether the SDIO Clock divider bypass is + enabled or disabled. + This parameter can be a value of @ref SDIO_Clock_Bypass */ + + uint32_t SDIO_ClockPowerSave; /*!< Specifies whether SDIO Clock output is enabled or + disabled when the bus is idle. + This parameter can be a value of @ref SDIO_Clock_Power_Save */ + + uint32_t SDIO_BusWide; /*!< Specifies the SDIO bus width. + This parameter can be a value of @ref SDIO_Bus_Wide */ + + uint32_t SDIO_HardwareFlowControl; /*!< Specifies whether the SDIO hardware flow control is enabled or disabled. + This parameter can be a value of @ref SDIO_Hardware_Flow_Control */ + + uint8_t SDIO_ClockDiv; /*!< Specifies the clock frequency of the SDIO controller. + This parameter can be a value between 0x00 and 0xFF. */ + +} SDIO_InitTypeDef; + +typedef struct +{ + uint32_t SDIO_Argument; /*!< Specifies the SDIO command argument which is sent + to a card as part of a command message. If a command + contains an argument, it must be loaded into this register + before writing the command to the command register */ + + uint32_t SDIO_CmdIndex; /*!< Specifies the SDIO command index. It must be lower than 0x40. */ + + uint32_t SDIO_Response; /*!< Specifies the SDIO response type. + This parameter can be a value of @ref SDIO_Response_Type */ + + uint32_t SDIO_Wait; /*!< Specifies whether SDIO wait-for-interrupt request is enabled or disabled. + This parameter can be a value of @ref SDIO_Wait_Interrupt_State */ + + uint32_t SDIO_CPSM; /*!< Specifies whether SDIO Command path state machine (CPSM) + is enabled or disabled. + This parameter can be a value of @ref SDIO_CPSM_State */ +} SDIO_CmdInitTypeDef; + +typedef struct +{ + uint32_t SDIO_DataTimeOut; /*!< Specifies the data timeout period in card bus clock periods. */ + + uint32_t SDIO_DataLength; /*!< Specifies the number of data bytes to be transferred. */ + + uint32_t SDIO_DataBlockSize; /*!< Specifies the data block size for block transfer. + This parameter can be a value of @ref SDIO_Data_Block_Size */ + + uint32_t SDIO_TransferDir; /*!< Specifies the data transfer direction, whether the transfer + is a read or write. + This parameter can be a value of @ref SDIO_Transfer_Direction */ + + uint32_t SDIO_TransferMode; /*!< Specifies whether data transfer is in stream or block mode. + This parameter can be a value of @ref SDIO_Transfer_Type */ + + uint32_t SDIO_DPSM; /*!< Specifies whether SDIO Data path state machine (DPSM) + is enabled or disabled. + This parameter can be a value of @ref SDIO_DPSM_State */ +} SDIO_DataInitTypeDef; + +/** + * @} + */ + +/** @defgroup SDIO_Exported_Constants + * @{ + */ + +/** @defgroup SDIO_Clock_Edge + * @{ + */ + +#define SDIO_ClockEdge_Rising ((uint32_t)0x00000000) +#define SDIO_ClockEdge_Falling ((uint32_t)0x00002000) +#define IS_SDIO_CLOCK_EDGE(EDGE) (((EDGE) == SDIO_ClockEdge_Rising) || \ + ((EDGE) == SDIO_ClockEdge_Falling)) +/** + * @} + */ + +/** @defgroup SDIO_Clock_Bypass + * @{ + */ + +#define SDIO_ClockBypass_Disable ((uint32_t)0x00000000) +#define SDIO_ClockBypass_Enable ((uint32_t)0x00000400) +#define IS_SDIO_CLOCK_BYPASS(BYPASS) (((BYPASS) == SDIO_ClockBypass_Disable) || \ + ((BYPASS) == SDIO_ClockBypass_Enable)) +/** + * @} + */ + +/** @defgroup SDIO_Clock_Power_Save + * @{ + */ + +#define SDIO_ClockPowerSave_Disable ((uint32_t)0x00000000) +#define SDIO_ClockPowerSave_Enable ((uint32_t)0x00000200) +#define IS_SDIO_CLOCK_POWER_SAVE(SAVE) (((SAVE) == SDIO_ClockPowerSave_Disable) || \ + ((SAVE) == SDIO_ClockPowerSave_Enable)) +/** + * @} + */ + +/** @defgroup SDIO_Bus_Wide + * @{ + */ + +#define SDIO_BusWide_1b ((uint32_t)0x00000000) +#define SDIO_BusWide_4b ((uint32_t)0x00000800) +#define SDIO_BusWide_8b ((uint32_t)0x00001000) +#define IS_SDIO_BUS_WIDE(WIDE) (((WIDE) == SDIO_BusWide_1b) || ((WIDE) == SDIO_BusWide_4b) || \ + ((WIDE) == SDIO_BusWide_8b)) + +/** + * @} + */ + +/** @defgroup SDIO_Hardware_Flow_Control + * @{ + */ + +#define SDIO_HardwareFlowControl_Disable ((uint32_t)0x00000000) +#define SDIO_HardwareFlowControl_Enable ((uint32_t)0x00004000) +#define IS_SDIO_HARDWARE_FLOW_CONTROL(CONTROL) (((CONTROL) == SDIO_HardwareFlowControl_Disable) || \ + ((CONTROL) == SDIO_HardwareFlowControl_Enable)) +/** + * @} + */ + +/** @defgroup SDIO_Power_State + * @{ + */ + +#define SDIO_PowerState_OFF ((uint32_t)0x00000000) +#define SDIO_PowerState_ON ((uint32_t)0x00000003) +#define IS_SDIO_POWER_STATE(STATE) (((STATE) == SDIO_PowerState_OFF) || ((STATE) == SDIO_PowerState_ON)) +/** + * @} + */ + + +/** @defgroup SDIO_Interrupt_sources + * @{ + */ + +#define SDIO_IT_CCRCFAIL ((uint32_t)0x00000001) +#define SDIO_IT_DCRCFAIL ((uint32_t)0x00000002) +#define SDIO_IT_CTIMEOUT ((uint32_t)0x00000004) +#define SDIO_IT_DTIMEOUT ((uint32_t)0x00000008) +#define SDIO_IT_TXUNDERR ((uint32_t)0x00000010) +#define SDIO_IT_RXOVERR ((uint32_t)0x00000020) +#define SDIO_IT_CMDREND ((uint32_t)0x00000040) +#define SDIO_IT_CMDSENT ((uint32_t)0x00000080) +#define SDIO_IT_DATAEND ((uint32_t)0x00000100) +#define SDIO_IT_STBITERR ((uint32_t)0x00000200) +#define SDIO_IT_DBCKEND ((uint32_t)0x00000400) +#define SDIO_IT_CMDACT ((uint32_t)0x00000800) +#define SDIO_IT_TXACT ((uint32_t)0x00001000) +#define SDIO_IT_RXACT ((uint32_t)0x00002000) +#define SDIO_IT_TXFIFOHE ((uint32_t)0x00004000) +#define SDIO_IT_RXFIFOHF ((uint32_t)0x00008000) +#define SDIO_IT_TXFIFOF ((uint32_t)0x00010000) +#define SDIO_IT_RXFIFOF ((uint32_t)0x00020000) +#define SDIO_IT_TXFIFOE ((uint32_t)0x00040000) +#define SDIO_IT_RXFIFOE ((uint32_t)0x00080000) +#define SDIO_IT_TXDAVL ((uint32_t)0x00100000) +#define SDIO_IT_RXDAVL ((uint32_t)0x00200000) +#define SDIO_IT_SDIOIT ((uint32_t)0x00400000) +#define SDIO_IT_CEATAEND ((uint32_t)0x00800000) +#define IS_SDIO_IT(IT) ((((IT) & (uint32_t)0xFF000000) == 0x00) && ((IT) != (uint32_t)0x00)) +/** + * @} + */ + +/** @defgroup SDIO_Command_Index + * @{ + */ + +#define IS_SDIO_CMD_INDEX(INDEX) ((INDEX) < 0x40) +/** + * @} + */ + +/** @defgroup SDIO_Response_Type + * @{ + */ + +#define SDIO_Response_No ((uint32_t)0x00000000) +#define SDIO_Response_Short ((uint32_t)0x00000040) +#define SDIO_Response_Long ((uint32_t)0x000000C0) +#define IS_SDIO_RESPONSE(RESPONSE) (((RESPONSE) == SDIO_Response_No) || \ + ((RESPONSE) == SDIO_Response_Short) || \ + ((RESPONSE) == SDIO_Response_Long)) +/** + * @} + */ + +/** @defgroup SDIO_Wait_Interrupt_State + * @{ + */ + +#define SDIO_Wait_No ((uint32_t)0x00000000) /*!< SDIO No Wait, TimeOut is enabled */ +#define SDIO_Wait_IT ((uint32_t)0x00000100) /*!< SDIO Wait Interrupt Request */ +#define SDIO_Wait_Pend ((uint32_t)0x00000200) /*!< SDIO Wait End of transfer */ +#define IS_SDIO_WAIT(WAIT) (((WAIT) == SDIO_Wait_No) || ((WAIT) == SDIO_Wait_IT) || \ + ((WAIT) == SDIO_Wait_Pend)) +/** + * @} + */ + +/** @defgroup SDIO_CPSM_State + * @{ + */ + +#define SDIO_CPSM_Disable ((uint32_t)0x00000000) +#define SDIO_CPSM_Enable ((uint32_t)0x00000400) +#define IS_SDIO_CPSM(CPSM) (((CPSM) == SDIO_CPSM_Enable) || ((CPSM) == SDIO_CPSM_Disable)) +/** + * @} + */ + +/** @defgroup SDIO_Response_Registers + * @{ + */ + +#define SDIO_RESP1 ((uint32_t)0x00000000) +#define SDIO_RESP2 ((uint32_t)0x00000004) +#define SDIO_RESP3 ((uint32_t)0x00000008) +#define SDIO_RESP4 ((uint32_t)0x0000000C) +#define IS_SDIO_RESP(RESP) (((RESP) == SDIO_RESP1) || ((RESP) == SDIO_RESP2) || \ + ((RESP) == SDIO_RESP3) || ((RESP) == SDIO_RESP4)) +/** + * @} + */ + +/** @defgroup SDIO_Data_Length + * @{ + */ + +#define IS_SDIO_DATA_LENGTH(LENGTH) ((LENGTH) <= 0x01FFFFFF) +/** + * @} + */ + +/** @defgroup SDIO_Data_Block_Size + * @{ + */ + +#define SDIO_DataBlockSize_1b ((uint32_t)0x00000000) +#define SDIO_DataBlockSize_2b ((uint32_t)0x00000010) +#define SDIO_DataBlockSize_4b ((uint32_t)0x00000020) +#define SDIO_DataBlockSize_8b ((uint32_t)0x00000030) +#define SDIO_DataBlockSize_16b ((uint32_t)0x00000040) +#define SDIO_DataBlockSize_32b ((uint32_t)0x00000050) +#define SDIO_DataBlockSize_64b ((uint32_t)0x00000060) +#define SDIO_DataBlockSize_128b ((uint32_t)0x00000070) +#define SDIO_DataBlockSize_256b ((uint32_t)0x00000080) +#define SDIO_DataBlockSize_512b ((uint32_t)0x00000090) +#define SDIO_DataBlockSize_1024b ((uint32_t)0x000000A0) +#define SDIO_DataBlockSize_2048b ((uint32_t)0x000000B0) +#define SDIO_DataBlockSize_4096b ((uint32_t)0x000000C0) +#define SDIO_DataBlockSize_8192b ((uint32_t)0x000000D0) +#define SDIO_DataBlockSize_16384b ((uint32_t)0x000000E0) +#define IS_SDIO_BLOCK_SIZE(SIZE) (((SIZE) == SDIO_DataBlockSize_1b) || \ + ((SIZE) == SDIO_DataBlockSize_2b) || \ + ((SIZE) == SDIO_DataBlockSize_4b) || \ + ((SIZE) == SDIO_DataBlockSize_8b) || \ + ((SIZE) == SDIO_DataBlockSize_16b) || \ + ((SIZE) == SDIO_DataBlockSize_32b) || \ + ((SIZE) == SDIO_DataBlockSize_64b) || \ + ((SIZE) == SDIO_DataBlockSize_128b) || \ + ((SIZE) == SDIO_DataBlockSize_256b) || \ + ((SIZE) == SDIO_DataBlockSize_512b) || \ + ((SIZE) == SDIO_DataBlockSize_1024b) || \ + ((SIZE) == SDIO_DataBlockSize_2048b) || \ + ((SIZE) == SDIO_DataBlockSize_4096b) || \ + ((SIZE) == SDIO_DataBlockSize_8192b) || \ + ((SIZE) == SDIO_DataBlockSize_16384b)) +/** + * @} + */ + +/** @defgroup SDIO_Transfer_Direction + * @{ + */ + +#define SDIO_TransferDir_ToCard ((uint32_t)0x00000000) +#define SDIO_TransferDir_ToSDIO ((uint32_t)0x00000002) +#define IS_SDIO_TRANSFER_DIR(DIR) (((DIR) == SDIO_TransferDir_ToCard) || \ + ((DIR) == SDIO_TransferDir_ToSDIO)) +/** + * @} + */ + +/** @defgroup SDIO_Transfer_Type + * @{ + */ + +#define SDIO_TransferMode_Block ((uint32_t)0x00000000) +#define SDIO_TransferMode_Stream ((uint32_t)0x00000004) +#define IS_SDIO_TRANSFER_MODE(MODE) (((MODE) == SDIO_TransferMode_Stream) || \ + ((MODE) == SDIO_TransferMode_Block)) +/** + * @} + */ + +/** @defgroup SDIO_DPSM_State + * @{ + */ + +#define SDIO_DPSM_Disable ((uint32_t)0x00000000) +#define SDIO_DPSM_Enable ((uint32_t)0x00000001) +#define IS_SDIO_DPSM(DPSM) (((DPSM) == SDIO_DPSM_Enable) || ((DPSM) == SDIO_DPSM_Disable)) +/** + * @} + */ + +/** @defgroup SDIO_Flags + * @{ + */ + +#define SDIO_FLAG_CCRCFAIL ((uint32_t)0x00000001) +#define SDIO_FLAG_DCRCFAIL ((uint32_t)0x00000002) +#define SDIO_FLAG_CTIMEOUT ((uint32_t)0x00000004) +#define SDIO_FLAG_DTIMEOUT ((uint32_t)0x00000008) +#define SDIO_FLAG_TXUNDERR ((uint32_t)0x00000010) +#define SDIO_FLAG_RXOVERR ((uint32_t)0x00000020) +#define SDIO_FLAG_CMDREND ((uint32_t)0x00000040) +#define SDIO_FLAG_CMDSENT ((uint32_t)0x00000080) +#define SDIO_FLAG_DATAEND ((uint32_t)0x00000100) +#define SDIO_FLAG_STBITERR ((uint32_t)0x00000200) +#define SDIO_FLAG_DBCKEND ((uint32_t)0x00000400) +#define SDIO_FLAG_CMDACT ((uint32_t)0x00000800) +#define SDIO_FLAG_TXACT ((uint32_t)0x00001000) +#define SDIO_FLAG_RXACT ((uint32_t)0x00002000) +#define SDIO_FLAG_TXFIFOHE ((uint32_t)0x00004000) +#define SDIO_FLAG_RXFIFOHF ((uint32_t)0x00008000) +#define SDIO_FLAG_TXFIFOF ((uint32_t)0x00010000) +#define SDIO_FLAG_RXFIFOF ((uint32_t)0x00020000) +#define SDIO_FLAG_TXFIFOE ((uint32_t)0x00040000) +#define SDIO_FLAG_RXFIFOE ((uint32_t)0x00080000) +#define SDIO_FLAG_TXDAVL ((uint32_t)0x00100000) +#define SDIO_FLAG_RXDAVL ((uint32_t)0x00200000) +#define SDIO_FLAG_SDIOIT ((uint32_t)0x00400000) +#define SDIO_FLAG_CEATAEND ((uint32_t)0x00800000) +#define IS_SDIO_FLAG(FLAG) (((FLAG) == SDIO_FLAG_CCRCFAIL) || \ + ((FLAG) == SDIO_FLAG_DCRCFAIL) || \ + ((FLAG) == SDIO_FLAG_CTIMEOUT) || \ + ((FLAG) == SDIO_FLAG_DTIMEOUT) || \ + ((FLAG) == SDIO_FLAG_TXUNDERR) || \ + ((FLAG) == SDIO_FLAG_RXOVERR) || \ + ((FLAG) == SDIO_FLAG_CMDREND) || \ + ((FLAG) == SDIO_FLAG_CMDSENT) || \ + ((FLAG) == SDIO_FLAG_DATAEND) || \ + ((FLAG) == SDIO_FLAG_STBITERR) || \ + ((FLAG) == SDIO_FLAG_DBCKEND) || \ + ((FLAG) == SDIO_FLAG_CMDACT) || \ + ((FLAG) == SDIO_FLAG_TXACT) || \ + ((FLAG) == SDIO_FLAG_RXACT) || \ + ((FLAG) == SDIO_FLAG_TXFIFOHE) || \ + ((FLAG) == SDIO_FLAG_RXFIFOHF) || \ + ((FLAG) == SDIO_FLAG_TXFIFOF) || \ + ((FLAG) == SDIO_FLAG_RXFIFOF) || \ + ((FLAG) == SDIO_FLAG_TXFIFOE) || \ + ((FLAG) == SDIO_FLAG_RXFIFOE) || \ + ((FLAG) == SDIO_FLAG_TXDAVL) || \ + ((FLAG) == SDIO_FLAG_RXDAVL) || \ + ((FLAG) == SDIO_FLAG_SDIOIT) || \ + ((FLAG) == SDIO_FLAG_CEATAEND)) + +#define IS_SDIO_CLEAR_FLAG(FLAG) ((((FLAG) & (uint32_t)0xFF3FF800) == 0x00) && ((FLAG) != (uint32_t)0x00)) + +#define IS_SDIO_GET_IT(IT) (((IT) == SDIO_IT_CCRCFAIL) || \ + ((IT) == SDIO_IT_DCRCFAIL) || \ + ((IT) == SDIO_IT_CTIMEOUT) || \ + ((IT) == SDIO_IT_DTIMEOUT) || \ + ((IT) == SDIO_IT_TXUNDERR) || \ + ((IT) == SDIO_IT_RXOVERR) || \ + ((IT) == SDIO_IT_CMDREND) || \ + ((IT) == SDIO_IT_CMDSENT) || \ + ((IT) == SDIO_IT_DATAEND) || \ + ((IT) == SDIO_IT_STBITERR) || \ + ((IT) == SDIO_IT_DBCKEND) || \ + ((IT) == SDIO_IT_CMDACT) || \ + ((IT) == SDIO_IT_TXACT) || \ + ((IT) == SDIO_IT_RXACT) || \ + ((IT) == SDIO_IT_TXFIFOHE) || \ + ((IT) == SDIO_IT_RXFIFOHF) || \ + ((IT) == SDIO_IT_TXFIFOF) || \ + ((IT) == SDIO_IT_RXFIFOF) || \ + ((IT) == SDIO_IT_TXFIFOE) || \ + ((IT) == SDIO_IT_RXFIFOE) || \ + ((IT) == SDIO_IT_TXDAVL) || \ + ((IT) == SDIO_IT_RXDAVL) || \ + ((IT) == SDIO_IT_SDIOIT) || \ + ((IT) == SDIO_IT_CEATAEND)) + +#define IS_SDIO_CLEAR_IT(IT) ((((IT) & (uint32_t)0xFF3FF800) == 0x00) && ((IT) != (uint32_t)0x00)) + +/** + * @} + */ + +/** @defgroup SDIO_Read_Wait_Mode + * @{ + */ + +#define SDIO_ReadWaitMode_CLK ((uint32_t)0x00000001) +#define SDIO_ReadWaitMode_DATA2 ((uint32_t)0x00000000) +#define IS_SDIO_READWAIT_MODE(MODE) (((MODE) == SDIO_ReadWaitMode_CLK) || \ + ((MODE) == SDIO_ReadWaitMode_DATA2)) +/** + * @} + */ + +/** + * @} + */ + +/** @defgroup SDIO_Exported_Macros + * @{ + */ + +/** + * @} + */ + +/** @defgroup SDIO_Exported_Functions + * @{ + */ + +void SDIO_DeInit(void); +void SDIO_Init(SDIO_InitTypeDef* SDIO_InitStruct); +void SDIO_StructInit(SDIO_InitTypeDef* SDIO_InitStruct); +void SDIO_ClockCmd(FunctionalState NewState); +void SDIO_SetPowerState(uint32_t SDIO_PowerState); +uint32_t SDIO_GetPowerState(void); +void SDIO_ITConfig(uint32_t SDIO_IT, FunctionalState NewState); +void SDIO_DMACmd(FunctionalState NewState); +void SDIO_SendCommand(SDIO_CmdInitTypeDef *SDIO_CmdInitStruct); +void SDIO_CmdStructInit(SDIO_CmdInitTypeDef* SDIO_CmdInitStruct); +uint8_t SDIO_GetCommandResponse(void); +uint32_t SDIO_GetResponse(uint32_t SDIO_RESP); +void SDIO_DataConfig(SDIO_DataInitTypeDef* SDIO_DataInitStruct); +void SDIO_DataStructInit(SDIO_DataInitTypeDef* SDIO_DataInitStruct); +uint32_t SDIO_GetDataCounter(void); +uint32_t SDIO_ReadData(void); +void SDIO_WriteData(uint32_t Data); +uint32_t SDIO_GetFIFOCount(void); +void SDIO_StartSDIOReadWait(FunctionalState NewState); +void SDIO_StopSDIOReadWait(FunctionalState NewState); +void SDIO_SetSDIOReadWaitMode(uint32_t SDIO_ReadWaitMode); +void SDIO_SetSDIOOperation(FunctionalState NewState); +void SDIO_SendSDIOSuspendCmd(FunctionalState NewState); +void SDIO_CommandCompletionCmd(FunctionalState NewState); +void SDIO_CEATAITCmd(FunctionalState NewState); +void SDIO_SendCEATACmd(FunctionalState NewState); +FlagStatus SDIO_GetFlagStatus(uint32_t SDIO_FLAG); +void SDIO_ClearFlag(uint32_t SDIO_FLAG); +ITStatus SDIO_GetITStatus(uint32_t SDIO_IT); +void SDIO_ClearITPendingBit(uint32_t SDIO_IT); + +#ifdef __cplusplus +} +#endif + +#endif /* __STM32F10x_SDIO_H */ +/** + * @} + */ + +/** + * @} + */ + +/** + * @} + */ + +/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ diff --git a/Libraries/STM32F10x_StdPeriph_Driver/inc/stm32f10x_spi.h b/Libraries/STM32F10x_StdPeriph_Driver/inc/stm32f10x_spi.h new file mode 100644 index 0000000..aeedaeb --- /dev/null +++ b/Libraries/STM32F10x_StdPeriph_Driver/inc/stm32f10x_spi.h @@ -0,0 +1,493 @@ +/** + ****************************************************************************** + * @file stm32f10x_spi.h + * @author MCD Application Team + * @version V3.6.1 + * @date 05-March-2012 + * @brief This file contains all the functions prototypes for the SPI firmware + * library. + ****************************************************************************** + * @attention + * + *

    © COPYRIGHT 2012 STMicroelectronics

    + * + * Licensed under MCD-ST Liberty SW License Agreement V2, (the "License"); + * You may not use this file except in compliance with the License. + * You may obtain a copy of the License at: + * + * http://www.st.com/software_license_agreement_liberty_v2 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, + * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + * + ****************************************************************************** + */ + +/* Define to prevent recursive inclusion -------------------------------------*/ +#ifndef __STM32F10x_SPI_H +#define __STM32F10x_SPI_H + +#ifdef __cplusplus + extern "C" { +#endif + +/* Includes ------------------------------------------------------------------*/ +#include "stm32f10x.h" + +/** @addtogroup STM32F10x_StdPeriph_Driver + * @{ + */ + +/** @addtogroup SPI + * @{ + */ + +/** @defgroup SPI_Exported_Types + * @{ + */ + +/** + * @brief SPI Init structure definition + */ + +typedef struct +{ + uint16_t SPI_Direction; /*!< Specifies the SPI unidirectional or bidirectional data mode. + This parameter can be a value of @ref SPI_data_direction */ + + uint16_t SPI_Mode; /*!< Specifies the SPI operating mode. + This parameter can be a value of @ref SPI_mode */ + + uint16_t SPI_DataSize; /*!< Specifies the SPI data size. + This parameter can be a value of @ref SPI_data_size */ + + uint16_t SPI_CPOL; /*!< Specifies the serial clock steady state. + This parameter can be a value of @ref SPI_Clock_Polarity */ + + uint16_t SPI_CPHA; /*!< Specifies the clock active edge for the bit capture. + This parameter can be a value of @ref SPI_Clock_Phase */ + + uint16_t SPI_NSS; /*!< Specifies whether the NSS signal is managed by + hardware (NSS pin) or by software using the SSI bit. + This parameter can be a value of @ref SPI_Slave_Select_management */ + + uint16_t SPI_BaudRatePrescaler; /*!< Specifies the Baud Rate prescaler value which will be + used to configure the transmit and receive SCK clock. + This parameter can be a value of @ref SPI_BaudRate_Prescaler. + @note The communication clock is derived from the master + clock. The slave clock does not need to be set. */ + + uint16_t SPI_FirstBit; /*!< Specifies whether data transfers start from MSB or LSB bit. + This parameter can be a value of @ref SPI_MSB_LSB_transmission */ + + uint16_t SPI_CRCPolynomial; /*!< Specifies the polynomial used for the CRC calculation. */ +}SPI_InitTypeDef; + +/** + * @brief I2S Init structure definition + */ + +typedef struct +{ + + uint16_t I2S_Mode; /*!< Specifies the I2S operating mode. + This parameter can be a value of @ref I2S_Mode */ + + uint16_t I2S_Standard; /*!< Specifies the standard used for the I2S communication. + This parameter can be a value of @ref I2S_Standard */ + + uint16_t I2S_DataFormat; /*!< Specifies the data format for the I2S communication. + This parameter can be a value of @ref I2S_Data_Format */ + + uint16_t I2S_MCLKOutput; /*!< Specifies whether the I2S MCLK output is enabled or not. + This parameter can be a value of @ref I2S_MCLK_Output */ + + uint32_t I2S_AudioFreq; /*!< Specifies the frequency selected for the I2S communication. + This parameter can be a value of @ref I2S_Audio_Frequency */ + + uint16_t I2S_CPOL; /*!< Specifies the idle state of the I2S clock. + This parameter can be a value of @ref I2S_Clock_Polarity */ +}I2S_InitTypeDef; + +/** + * @} + */ + +/** @defgroup SPI_Exported_Constants + * @{ + */ + +#define IS_SPI_ALL_PERIPH(PERIPH) (((PERIPH) == SPI1) || \ + ((PERIPH) == SPI2) || \ + ((PERIPH) == SPI3)) + +#define IS_SPI_23_PERIPH(PERIPH) (((PERIPH) == SPI2) || \ + ((PERIPH) == SPI3)) + +/** @defgroup SPI_data_direction + * @{ + */ + +#define SPI_Direction_2Lines_FullDuplex ((uint16_t)0x0000) +#define SPI_Direction_2Lines_RxOnly ((uint16_t)0x0400) +#define SPI_Direction_1Line_Rx ((uint16_t)0x8000) +#define SPI_Direction_1Line_Tx ((uint16_t)0xC000) +#define IS_SPI_DIRECTION_MODE(MODE) (((MODE) == SPI_Direction_2Lines_FullDuplex) || \ + ((MODE) == SPI_Direction_2Lines_RxOnly) || \ + ((MODE) == SPI_Direction_1Line_Rx) || \ + ((MODE) == SPI_Direction_1Line_Tx)) +/** + * @} + */ + +/** @defgroup SPI_mode + * @{ + */ + +#define SPI_Mode_Master ((uint16_t)0x0104) +#define SPI_Mode_Slave ((uint16_t)0x0000) +#define IS_SPI_MODE(MODE) (((MODE) == SPI_Mode_Master) || \ + ((MODE) == SPI_Mode_Slave)) +/** + * @} + */ + +/** @defgroup SPI_data_size + * @{ + */ + +#define SPI_DataSize_16b ((uint16_t)0x0800) +#define SPI_DataSize_8b ((uint16_t)0x0000) +#define IS_SPI_DATASIZE(DATASIZE) (((DATASIZE) == SPI_DataSize_16b) || \ + ((DATASIZE) == SPI_DataSize_8b)) +/** + * @} + */ + +/** @defgroup SPI_Clock_Polarity + * @{ + */ + +#define SPI_CPOL_Low ((uint16_t)0x0000) +#define SPI_CPOL_High ((uint16_t)0x0002) +#define IS_SPI_CPOL(CPOL) (((CPOL) == SPI_CPOL_Low) || \ + ((CPOL) == SPI_CPOL_High)) +/** + * @} + */ + +/** @defgroup SPI_Clock_Phase + * @{ + */ + +#define SPI_CPHA_1Edge ((uint16_t)0x0000) +#define SPI_CPHA_2Edge ((uint16_t)0x0001) +#define IS_SPI_CPHA(CPHA) (((CPHA) == SPI_CPHA_1Edge) || \ + ((CPHA) == SPI_CPHA_2Edge)) +/** + * @} + */ + +/** @defgroup SPI_Slave_Select_management + * @{ + */ + +#define SPI_NSS_Soft ((uint16_t)0x0200) +#define SPI_NSS_Hard ((uint16_t)0x0000) +#define IS_SPI_NSS(NSS) (((NSS) == SPI_NSS_Soft) || \ + ((NSS) == SPI_NSS_Hard)) +/** + * @} + */ + +/** @defgroup SPI_BaudRate_Prescaler + * @{ + */ + +#define SPI_BaudRatePrescaler_2 ((uint16_t)0x0000) +#define SPI_BaudRatePrescaler_4 ((uint16_t)0x0008) +#define SPI_BaudRatePrescaler_8 ((uint16_t)0x0010) +#define SPI_BaudRatePrescaler_16 ((uint16_t)0x0018) +#define SPI_BaudRatePrescaler_32 ((uint16_t)0x0020) +#define SPI_BaudRatePrescaler_64 ((uint16_t)0x0028) +#define SPI_BaudRatePrescaler_128 ((uint16_t)0x0030) +#define SPI_BaudRatePrescaler_256 ((uint16_t)0x0038) +#define IS_SPI_BAUDRATE_PRESCALER(PRESCALER) (((PRESCALER) == SPI_BaudRatePrescaler_2) || \ + ((PRESCALER) == SPI_BaudRatePrescaler_4) || \ + ((PRESCALER) == SPI_BaudRatePrescaler_8) || \ + ((PRESCALER) == SPI_BaudRatePrescaler_16) || \ + ((PRESCALER) == SPI_BaudRatePrescaler_32) || \ + ((PRESCALER) == SPI_BaudRatePrescaler_64) || \ + ((PRESCALER) == SPI_BaudRatePrescaler_128) || \ + ((PRESCALER) == SPI_BaudRatePrescaler_256)) +/** + * @} + */ + +/** @defgroup SPI_MSB_LSB_transmission + * @{ + */ + +#define SPI_FirstBit_MSB ((uint16_t)0x0000) +#define SPI_FirstBit_LSB ((uint16_t)0x0080) +#define IS_SPI_FIRST_BIT(BIT) (((BIT) == SPI_FirstBit_MSB) || \ + ((BIT) == SPI_FirstBit_LSB)) +/** + * @} + */ + +/** @defgroup I2S_Mode + * @{ + */ + +#define I2S_Mode_SlaveTx ((uint16_t)0x0000) +#define I2S_Mode_SlaveRx ((uint16_t)0x0100) +#define I2S_Mode_MasterTx ((uint16_t)0x0200) +#define I2S_Mode_MasterRx ((uint16_t)0x0300) +#define IS_I2S_MODE(MODE) (((MODE) == I2S_Mode_SlaveTx) || \ + ((MODE) == I2S_Mode_SlaveRx) || \ + ((MODE) == I2S_Mode_MasterTx) || \ + ((MODE) == I2S_Mode_MasterRx) ) +/** + * @} + */ + +/** @defgroup I2S_Standard + * @{ + */ + +#define I2S_Standard_Phillips ((uint16_t)0x0000) +#define I2S_Standard_MSB ((uint16_t)0x0010) +#define I2S_Standard_LSB ((uint16_t)0x0020) +#define I2S_Standard_PCMShort ((uint16_t)0x0030) +#define I2S_Standard_PCMLong ((uint16_t)0x00B0) +#define IS_I2S_STANDARD(STANDARD) (((STANDARD) == I2S_Standard_Phillips) || \ + ((STANDARD) == I2S_Standard_MSB) || \ + ((STANDARD) == I2S_Standard_LSB) || \ + ((STANDARD) == I2S_Standard_PCMShort) || \ + ((STANDARD) == I2S_Standard_PCMLong)) +/** + * @} + */ + +/** @defgroup I2S_Data_Format + * @{ + */ + +#define I2S_DataFormat_16b ((uint16_t)0x0000) +#define I2S_DataFormat_16bextended ((uint16_t)0x0001) +#define I2S_DataFormat_24b ((uint16_t)0x0003) +#define I2S_DataFormat_32b ((uint16_t)0x0005) +#define IS_I2S_DATA_FORMAT(FORMAT) (((FORMAT) == I2S_DataFormat_16b) || \ + ((FORMAT) == I2S_DataFormat_16bextended) || \ + ((FORMAT) == I2S_DataFormat_24b) || \ + ((FORMAT) == I2S_DataFormat_32b)) +/** + * @} + */ + +/** @defgroup I2S_MCLK_Output + * @{ + */ + +#define I2S_MCLKOutput_Enable ((uint16_t)0x0200) +#define I2S_MCLKOutput_Disable ((uint16_t)0x0000) +#define IS_I2S_MCLK_OUTPUT(OUTPUT) (((OUTPUT) == I2S_MCLKOutput_Enable) || \ + ((OUTPUT) == I2S_MCLKOutput_Disable)) +/** + * @} + */ + +/** @defgroup I2S_Audio_Frequency + * @{ + */ + +#define I2S_AudioFreq_192k ((uint32_t)192000) +#define I2S_AudioFreq_96k ((uint32_t)96000) +#define I2S_AudioFreq_48k ((uint32_t)48000) +#define I2S_AudioFreq_44k ((uint32_t)44100) +#define I2S_AudioFreq_32k ((uint32_t)32000) +#define I2S_AudioFreq_22k ((uint32_t)22050) +#define I2S_AudioFreq_16k ((uint32_t)16000) +#define I2S_AudioFreq_11k ((uint32_t)11025) +#define I2S_AudioFreq_8k ((uint32_t)8000) +#define I2S_AudioFreq_Default ((uint32_t)2) + +#define IS_I2S_AUDIO_FREQ(FREQ) ((((FREQ) >= I2S_AudioFreq_8k) && \ + ((FREQ) <= I2S_AudioFreq_192k)) || \ + ((FREQ) == I2S_AudioFreq_Default)) +/** + * @} + */ + +/** @defgroup I2S_Clock_Polarity + * @{ + */ + +#define I2S_CPOL_Low ((uint16_t)0x0000) +#define I2S_CPOL_High ((uint16_t)0x0008) +#define IS_I2S_CPOL(CPOL) (((CPOL) == I2S_CPOL_Low) || \ + ((CPOL) == I2S_CPOL_High)) +/** + * @} + */ + +/** @defgroup SPI_I2S_DMA_transfer_requests + * @{ + */ + +#define SPI_I2S_DMAReq_Tx ((uint16_t)0x0002) +#define SPI_I2S_DMAReq_Rx ((uint16_t)0x0001) +#define IS_SPI_I2S_DMAREQ(DMAREQ) ((((DMAREQ) & (uint16_t)0xFFFC) == 0x00) && ((DMAREQ) != 0x00)) +/** + * @} + */ + +/** @defgroup SPI_NSS_internal_software_management + * @{ + */ + +#define SPI_NSSInternalSoft_Set ((uint16_t)0x0100) +#define SPI_NSSInternalSoft_Reset ((uint16_t)0xFEFF) +#define IS_SPI_NSS_INTERNAL(INTERNAL) (((INTERNAL) == SPI_NSSInternalSoft_Set) || \ + ((INTERNAL) == SPI_NSSInternalSoft_Reset)) +/** + * @} + */ + +/** @defgroup SPI_CRC_Transmit_Receive + * @{ + */ + +#define SPI_CRC_Tx ((uint8_t)0x00) +#define SPI_CRC_Rx ((uint8_t)0x01) +#define IS_SPI_CRC(CRC) (((CRC) == SPI_CRC_Tx) || ((CRC) == SPI_CRC_Rx)) +/** + * @} + */ + +/** @defgroup SPI_direction_transmit_receive + * @{ + */ + +#define SPI_Direction_Rx ((uint16_t)0xBFFF) +#define SPI_Direction_Tx ((uint16_t)0x4000) +#define IS_SPI_DIRECTION(DIRECTION) (((DIRECTION) == SPI_Direction_Rx) || \ + ((DIRECTION) == SPI_Direction_Tx)) +/** + * @} + */ + +/** @defgroup SPI_I2S_interrupts_definition + * @{ + */ + +#define SPI_I2S_IT_TXE ((uint8_t)0x71) +#define SPI_I2S_IT_RXNE ((uint8_t)0x60) +#define SPI_I2S_IT_ERR ((uint8_t)0x50) +#define IS_SPI_I2S_CONFIG_IT(IT) (((IT) == SPI_I2S_IT_TXE) || \ + ((IT) == SPI_I2S_IT_RXNE) || \ + ((IT) == SPI_I2S_IT_ERR)) +#define SPI_I2S_IT_OVR ((uint8_t)0x56) +#define SPI_IT_MODF ((uint8_t)0x55) +#define SPI_IT_CRCERR ((uint8_t)0x54) +#define I2S_IT_UDR ((uint8_t)0x53) +#define IS_SPI_I2S_CLEAR_IT(IT) (((IT) == SPI_IT_CRCERR)) +#define IS_SPI_I2S_GET_IT(IT) (((IT) == SPI_I2S_IT_RXNE) || ((IT) == SPI_I2S_IT_TXE) || \ + ((IT) == I2S_IT_UDR) || ((IT) == SPI_IT_CRCERR) || \ + ((IT) == SPI_IT_MODF) || ((IT) == SPI_I2S_IT_OVR)) +/** + * @} + */ + +/** @defgroup SPI_I2S_flags_definition + * @{ + */ + +#define SPI_I2S_FLAG_RXNE ((uint16_t)0x0001) +#define SPI_I2S_FLAG_TXE ((uint16_t)0x0002) +#define I2S_FLAG_CHSIDE ((uint16_t)0x0004) +#define I2S_FLAG_UDR ((uint16_t)0x0008) +#define SPI_FLAG_CRCERR ((uint16_t)0x0010) +#define SPI_FLAG_MODF ((uint16_t)0x0020) +#define SPI_I2S_FLAG_OVR ((uint16_t)0x0040) +#define SPI_I2S_FLAG_BSY ((uint16_t)0x0080) +#define IS_SPI_I2S_CLEAR_FLAG(FLAG) (((FLAG) == SPI_FLAG_CRCERR)) +#define IS_SPI_I2S_GET_FLAG(FLAG) (((FLAG) == SPI_I2S_FLAG_BSY) || ((FLAG) == SPI_I2S_FLAG_OVR) || \ + ((FLAG) == SPI_FLAG_MODF) || ((FLAG) == SPI_FLAG_CRCERR) || \ + ((FLAG) == I2S_FLAG_UDR) || ((FLAG) == I2S_FLAG_CHSIDE) || \ + ((FLAG) == SPI_I2S_FLAG_TXE) || ((FLAG) == SPI_I2S_FLAG_RXNE)) +/** + * @} + */ + +/** @defgroup SPI_CRC_polynomial + * @{ + */ + +#define IS_SPI_CRC_POLYNOMIAL(POLYNOMIAL) ((POLYNOMIAL) >= 0x1) +/** + * @} + */ + +/** + * @} + */ + +/** @defgroup SPI_Exported_Macros + * @{ + */ + +/** + * @} + */ + +/** @defgroup SPI_Exported_Functions + * @{ + */ + +void SPI_I2S_DeInit(SPI_TypeDef* SPIx); +void SPI_Init(SPI_TypeDef* SPIx, SPI_InitTypeDef* SPI_InitStruct); +void I2S_Init(SPI_TypeDef* SPIx, I2S_InitTypeDef* I2S_InitStruct); +void SPI_StructInit(SPI_InitTypeDef* SPI_InitStruct); +void I2S_StructInit(I2S_InitTypeDef* I2S_InitStruct); +void SPI_Cmd(SPI_TypeDef* SPIx, FunctionalState NewState); +void I2S_Cmd(SPI_TypeDef* SPIx, FunctionalState NewState); +void SPI_I2S_ITConfig(SPI_TypeDef* SPIx, uint8_t SPI_I2S_IT, FunctionalState NewState); +void SPI_I2S_DMACmd(SPI_TypeDef* SPIx, uint16_t SPI_I2S_DMAReq, FunctionalState NewState); +void SPI_I2S_SendData(SPI_TypeDef* SPIx, uint16_t Data); +uint16_t SPI_I2S_ReceiveData(SPI_TypeDef* SPIx); +void SPI_NSSInternalSoftwareConfig(SPI_TypeDef* SPIx, uint16_t SPI_NSSInternalSoft); +void SPI_SSOutputCmd(SPI_TypeDef* SPIx, FunctionalState NewState); +void SPI_DataSizeConfig(SPI_TypeDef* SPIx, uint16_t SPI_DataSize); +void SPI_TransmitCRC(SPI_TypeDef* SPIx); +void SPI_CalculateCRC(SPI_TypeDef* SPIx, FunctionalState NewState); +uint16_t SPI_GetCRC(SPI_TypeDef* SPIx, uint8_t SPI_CRC); +uint16_t SPI_GetCRCPolynomial(SPI_TypeDef* SPIx); +void SPI_BiDirectionalLineConfig(SPI_TypeDef* SPIx, uint16_t SPI_Direction); +FlagStatus SPI_I2S_GetFlagStatus(SPI_TypeDef* SPIx, uint16_t SPI_I2S_FLAG); +void SPI_I2S_ClearFlag(SPI_TypeDef* SPIx, uint16_t SPI_I2S_FLAG); +ITStatus SPI_I2S_GetITStatus(SPI_TypeDef* SPIx, uint8_t SPI_I2S_IT); +void SPI_I2S_ClearITPendingBit(SPI_TypeDef* SPIx, uint8_t SPI_I2S_IT); + +#ifdef __cplusplus +} +#endif + +#endif /*__STM32F10x_SPI_H */ +/** + * @} + */ + +/** + * @} + */ + +/** + * @} + */ + +/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ diff --git a/Libraries/STM32F10x_StdPeriph_Driver/inc/stm32f10x_tim.h b/Libraries/STM32F10x_StdPeriph_Driver/inc/stm32f10x_tim.h new file mode 100644 index 0000000..077832f --- /dev/null +++ b/Libraries/STM32F10x_StdPeriph_Driver/inc/stm32f10x_tim.h @@ -0,0 +1,1170 @@ +/** + ****************************************************************************** + * @file stm32f10x_tim.h + * @author MCD Application Team + * @version V3.6.1 + * @date 05-March-2012 + * @brief This file contains all the functions prototypes for the TIM firmware + * library. + ****************************************************************************** + * @attention + * + *

    © COPYRIGHT 2012 STMicroelectronics

    + * + * Licensed under MCD-ST Liberty SW License Agreement V2, (the "License"); + * You may not use this file except in compliance with the License. + * You may obtain a copy of the License at: + * + * http://www.st.com/software_license_agreement_liberty_v2 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, + * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + * + ****************************************************************************** + */ + +/* Define to prevent recursive inclusion -------------------------------------*/ +#ifndef __STM32F10x_TIM_H +#define __STM32F10x_TIM_H + +#ifdef __cplusplus + extern "C" { +#endif + +/* Includes ------------------------------------------------------------------*/ +#include "stm32f10x.h" + +/** @addtogroup STM32F10x_StdPeriph_Driver + * @{ + */ + +/** @addtogroup TIM + * @{ + */ + +/** @defgroup TIM_Exported_Types + * @{ + */ + +/** + * @brief TIM Time Base Init structure definition + * @note This structure is used with all TIMx except for TIM6 and TIM7. + */ + +typedef struct +{ + uint16_t TIM_Prescaler; /*!< Specifies the prescaler value used to divide the TIM clock. + This parameter can be a number between 0x0000 and 0xFFFF */ + + uint16_t TIM_CounterMode; /*!< Specifies the counter mode. + This parameter can be a value of @ref TIM_Counter_Mode */ + + uint16_t TIM_Period; /*!< Specifies the period value to be loaded into the active + Auto-Reload Register at the next update event. + This parameter must be a number between 0x0000 and 0xFFFF. */ + + uint16_t TIM_ClockDivision; /*!< Specifies the clock division. + This parameter can be a value of @ref TIM_Clock_Division_CKD */ + + uint8_t TIM_RepetitionCounter; /*!< Specifies the repetition counter value. Each time the RCR downcounter + reaches zero, an update event is generated and counting restarts + from the RCR value (N). + This means in PWM mode that (N+1) corresponds to: + - the number of PWM periods in edge-aligned mode + - the number of half PWM period in center-aligned mode + This parameter must be a number between 0x00 and 0xFF. + @note This parameter is valid only for TIM1 and TIM8. */ +} TIM_TimeBaseInitTypeDef; + +/** + * @brief TIM Output Compare Init structure definition + */ + +typedef struct +{ + uint16_t TIM_OCMode; /*!< Specifies the TIM mode. + This parameter can be a value of @ref TIM_Output_Compare_and_PWM_modes */ + + uint16_t TIM_OutputState; /*!< Specifies the TIM Output Compare state. + This parameter can be a value of @ref TIM_Output_Compare_state */ + + uint16_t TIM_OutputNState; /*!< Specifies the TIM complementary Output Compare state. + This parameter can be a value of @ref TIM_Output_Compare_N_state + @note This parameter is valid only for TIM1 and TIM8. */ + + uint16_t TIM_Pulse; /*!< Specifies the pulse value to be loaded into the Capture Compare Register. + This parameter can be a number between 0x0000 and 0xFFFF */ + + uint16_t TIM_OCPolarity; /*!< Specifies the output polarity. + This parameter can be a value of @ref TIM_Output_Compare_Polarity */ + + uint16_t TIM_OCNPolarity; /*!< Specifies the complementary output polarity. + This parameter can be a value of @ref TIM_Output_Compare_N_Polarity + @note This parameter is valid only for TIM1 and TIM8. */ + + uint16_t TIM_OCIdleState; /*!< Specifies the TIM Output Compare pin state during Idle state. + This parameter can be a value of @ref TIM_Output_Compare_Idle_State + @note This parameter is valid only for TIM1 and TIM8. */ + + uint16_t TIM_OCNIdleState; /*!< Specifies the TIM Output Compare pin state during Idle state. + This parameter can be a value of @ref TIM_Output_Compare_N_Idle_State + @note This parameter is valid only for TIM1 and TIM8. */ +} TIM_OCInitTypeDef; + +/** + * @brief TIM Input Capture Init structure definition + */ + +typedef struct +{ + + uint16_t TIM_Channel; /*!< Specifies the TIM channel. + This parameter can be a value of @ref TIM_Channel */ + + uint16_t TIM_ICPolarity; /*!< Specifies the active edge of the input signal. + This parameter can be a value of @ref TIM_Input_Capture_Polarity */ + + uint16_t TIM_ICSelection; /*!< Specifies the input. + This parameter can be a value of @ref TIM_Input_Capture_Selection */ + + uint16_t TIM_ICPrescaler; /*!< Specifies the Input Capture Prescaler. + This parameter can be a value of @ref TIM_Input_Capture_Prescaler */ + + uint16_t TIM_ICFilter; /*!< Specifies the input capture filter. + This parameter can be a number between 0x0 and 0xF */ +} TIM_ICInitTypeDef; + +/** + * @brief BDTR structure definition + * @note This structure is used only with TIM1 and TIM8. + */ + +typedef struct +{ + + uint16_t TIM_OSSRState; /*!< Specifies the Off-State selection used in Run mode. + This parameter can be a value of @ref OSSR_Off_State_Selection_for_Run_mode_state */ + + uint16_t TIM_OSSIState; /*!< Specifies the Off-State used in Idle state. + This parameter can be a value of @ref OSSI_Off_State_Selection_for_Idle_mode_state */ + + uint16_t TIM_LOCKLevel; /*!< Specifies the LOCK level parameters. + This parameter can be a value of @ref Lock_level */ + + uint16_t TIM_DeadTime; /*!< Specifies the delay time between the switching-off and the + switching-on of the outputs. + This parameter can be a number between 0x00 and 0xFF */ + + uint16_t TIM_Break; /*!< Specifies whether the TIM Break input is enabled or not. + This parameter can be a value of @ref Break_Input_enable_disable */ + + uint16_t TIM_BreakPolarity; /*!< Specifies the TIM Break Input pin polarity. + This parameter can be a value of @ref Break_Polarity */ + + uint16_t TIM_AutomaticOutput; /*!< Specifies whether the TIM Automatic Output feature is enabled or not. + This parameter can be a value of @ref TIM_AOE_Bit_Set_Reset */ +} TIM_BDTRInitTypeDef; + +/** @defgroup TIM_Exported_constants + * @{ + */ + +#define IS_TIM_ALL_PERIPH(PERIPH) (((PERIPH) == TIM1) || \ + ((PERIPH) == TIM2) || \ + ((PERIPH) == TIM3) || \ + ((PERIPH) == TIM4) || \ + ((PERIPH) == TIM5) || \ + ((PERIPH) == TIM6) || \ + ((PERIPH) == TIM7) || \ + ((PERIPH) == TIM8) || \ + ((PERIPH) == TIM9) || \ + ((PERIPH) == TIM10)|| \ + ((PERIPH) == TIM11)|| \ + ((PERIPH) == TIM12)|| \ + ((PERIPH) == TIM13)|| \ + ((PERIPH) == TIM14)|| \ + ((PERIPH) == TIM15)|| \ + ((PERIPH) == TIM16)|| \ + ((PERIPH) == TIM17)) + +/* LIST1: TIM 1 and 8 */ +#define IS_TIM_LIST1_PERIPH(PERIPH) (((PERIPH) == TIM1) || \ + ((PERIPH) == TIM8)) + +/* LIST2: TIM 1, 8, 15 16 and 17 */ +#define IS_TIM_LIST2_PERIPH(PERIPH) (((PERIPH) == TIM1) || \ + ((PERIPH) == TIM8) || \ + ((PERIPH) == TIM15)|| \ + ((PERIPH) == TIM16)|| \ + ((PERIPH) == TIM17)) + +/* LIST3: TIM 1, 2, 3, 4, 5 and 8 */ +#define IS_TIM_LIST3_PERIPH(PERIPH) (((PERIPH) == TIM1) || \ + ((PERIPH) == TIM2) || \ + ((PERIPH) == TIM3) || \ + ((PERIPH) == TIM4) || \ + ((PERIPH) == TIM5) || \ + ((PERIPH) == TIM8)) + +/* LIST4: TIM 1, 2, 3, 4, 5, 8, 15, 16 and 17 */ +#define IS_TIM_LIST4_PERIPH(PERIPH) (((PERIPH) == TIM1) || \ + ((PERIPH) == TIM2) || \ + ((PERIPH) == TIM3) || \ + ((PERIPH) == TIM4) || \ + ((PERIPH) == TIM5) || \ + ((PERIPH) == TIM8) || \ + ((PERIPH) == TIM15)|| \ + ((PERIPH) == TIM16)|| \ + ((PERIPH) == TIM17)) + +/* LIST5: TIM 1, 2, 3, 4, 5, 8 and 15 */ +#define IS_TIM_LIST5_PERIPH(PERIPH) (((PERIPH) == TIM1) || \ + ((PERIPH) == TIM2) || \ + ((PERIPH) == TIM3) || \ + ((PERIPH) == TIM4) || \ + ((PERIPH) == TIM5) || \ + ((PERIPH) == TIM8) || \ + ((PERIPH) == TIM15)) + +/* LIST6: TIM 1, 2, 3, 4, 5, 8, 9, 12 and 15 */ +#define IS_TIM_LIST6_PERIPH(PERIPH) (((PERIPH) == TIM1) || \ + ((PERIPH) == TIM2) || \ + ((PERIPH) == TIM3) || \ + ((PERIPH) == TIM4) || \ + ((PERIPH) == TIM5) || \ + ((PERIPH) == TIM8) || \ + ((PERIPH) == TIM9) || \ + ((PERIPH) == TIM12)|| \ + ((PERIPH) == TIM15)) + +/* LIST7: TIM 1, 2, 3, 4, 5, 6, 7, 8, 9, 12 and 15 */ +#define IS_TIM_LIST7_PERIPH(PERIPH) (((PERIPH) == TIM1) || \ + ((PERIPH) == TIM2) || \ + ((PERIPH) == TIM3) || \ + ((PERIPH) == TIM4) || \ + ((PERIPH) == TIM5) || \ + ((PERIPH) == TIM6) || \ + ((PERIPH) == TIM7) || \ + ((PERIPH) == TIM8) || \ + ((PERIPH) == TIM9) || \ + ((PERIPH) == TIM12)|| \ + ((PERIPH) == TIM15)) + +/* LIST8: TIM 1, 2, 3, 4, 5, 8, 9, 10, 11, 12, 13, 14, 15, 16 and 17 */ +#define IS_TIM_LIST8_PERIPH(PERIPH) (((PERIPH) == TIM1) || \ + ((PERIPH) == TIM2) || \ + ((PERIPH) == TIM3) || \ + ((PERIPH) == TIM4) || \ + ((PERIPH) == TIM5) || \ + ((PERIPH) == TIM8) || \ + ((PERIPH) == TIM9) || \ + ((PERIPH) == TIM10)|| \ + ((PERIPH) == TIM11)|| \ + ((PERIPH) == TIM12)|| \ + ((PERIPH) == TIM13)|| \ + ((PERIPH) == TIM14)|| \ + ((PERIPH) == TIM15)|| \ + ((PERIPH) == TIM16)|| \ + ((PERIPH) == TIM17)) + +/* LIST9: TIM 1, 2, 3, 4, 5, 6, 7, 8, 15, 16, and 17 */ +#define IS_TIM_LIST9_PERIPH(PERIPH) (((PERIPH) == TIM1) || \ + ((PERIPH) == TIM2) || \ + ((PERIPH) == TIM3) || \ + ((PERIPH) == TIM4) || \ + ((PERIPH) == TIM5) || \ + ((PERIPH) == TIM6) || \ + ((PERIPH) == TIM7) || \ + ((PERIPH) == TIM8) || \ + ((PERIPH) == TIM15)|| \ + ((PERIPH) == TIM16)|| \ + ((PERIPH) == TIM17)) + +/** + * @} + */ + +/** @defgroup TIM_Output_Compare_and_PWM_modes + * @{ + */ + +#define TIM_OCMode_Timing ((uint16_t)0x0000) +#define TIM_OCMode_Active ((uint16_t)0x0010) +#define TIM_OCMode_Inactive ((uint16_t)0x0020) +#define TIM_OCMode_Toggle ((uint16_t)0x0030) +#define TIM_OCMode_PWM1 ((uint16_t)0x0060) +#define TIM_OCMode_PWM2 ((uint16_t)0x0070) +#define IS_TIM_OC_MODE(MODE) (((MODE) == TIM_OCMode_Timing) || \ + ((MODE) == TIM_OCMode_Active) || \ + ((MODE) == TIM_OCMode_Inactive) || \ + ((MODE) == TIM_OCMode_Toggle)|| \ + ((MODE) == TIM_OCMode_PWM1) || \ + ((MODE) == TIM_OCMode_PWM2)) +#define IS_TIM_OCM(MODE) (((MODE) == TIM_OCMode_Timing) || \ + ((MODE) == TIM_OCMode_Active) || \ + ((MODE) == TIM_OCMode_Inactive) || \ + ((MODE) == TIM_OCMode_Toggle)|| \ + ((MODE) == TIM_OCMode_PWM1) || \ + ((MODE) == TIM_OCMode_PWM2) || \ + ((MODE) == TIM_ForcedAction_Active) || \ + ((MODE) == TIM_ForcedAction_InActive)) +/** + * @} + */ + +/** @defgroup TIM_One_Pulse_Mode + * @{ + */ + +#define TIM_OPMode_Single ((uint16_t)0x0008) +#define TIM_OPMode_Repetitive ((uint16_t)0x0000) +#define IS_TIM_OPM_MODE(MODE) (((MODE) == TIM_OPMode_Single) || \ + ((MODE) == TIM_OPMode_Repetitive)) +/** + * @} + */ + +/** @defgroup TIM_Channel + * @{ + */ + +#define TIM_Channel_1 ((uint16_t)0x0000) +#define TIM_Channel_2 ((uint16_t)0x0004) +#define TIM_Channel_3 ((uint16_t)0x0008) +#define TIM_Channel_4 ((uint16_t)0x000C) +#define IS_TIM_CHANNEL(CHANNEL) (((CHANNEL) == TIM_Channel_1) || \ + ((CHANNEL) == TIM_Channel_2) || \ + ((CHANNEL) == TIM_Channel_3) || \ + ((CHANNEL) == TIM_Channel_4)) +#define IS_TIM_PWMI_CHANNEL(CHANNEL) (((CHANNEL) == TIM_Channel_1) || \ + ((CHANNEL) == TIM_Channel_2)) +#define IS_TIM_COMPLEMENTARY_CHANNEL(CHANNEL) (((CHANNEL) == TIM_Channel_1) || \ + ((CHANNEL) == TIM_Channel_2) || \ + ((CHANNEL) == TIM_Channel_3)) +/** + * @} + */ + +/** @defgroup TIM_Clock_Division_CKD + * @{ + */ + +#define TIM_CKD_DIV1 ((uint16_t)0x0000) +#define TIM_CKD_DIV2 ((uint16_t)0x0100) +#define TIM_CKD_DIV4 ((uint16_t)0x0200) +#define IS_TIM_CKD_DIV(DIV) (((DIV) == TIM_CKD_DIV1) || \ + ((DIV) == TIM_CKD_DIV2) || \ + ((DIV) == TIM_CKD_DIV4)) +/** + * @} + */ + +/** @defgroup TIM_Counter_Mode + * @{ + */ + +#define TIM_CounterMode_Up ((uint16_t)0x0000) +#define TIM_CounterMode_Down ((uint16_t)0x0010) +#define TIM_CounterMode_CenterAligned1 ((uint16_t)0x0020) +#define TIM_CounterMode_CenterAligned2 ((uint16_t)0x0040) +#define TIM_CounterMode_CenterAligned3 ((uint16_t)0x0060) +#define IS_TIM_COUNTER_MODE(MODE) (((MODE) == TIM_CounterMode_Up) || \ + ((MODE) == TIM_CounterMode_Down) || \ + ((MODE) == TIM_CounterMode_CenterAligned1) || \ + ((MODE) == TIM_CounterMode_CenterAligned2) || \ + ((MODE) == TIM_CounterMode_CenterAligned3)) +/** + * @} + */ + +/** @defgroup TIM_Output_Compare_Polarity + * @{ + */ + +#define TIM_OCPolarity_High ((uint16_t)0x0000) +#define TIM_OCPolarity_Low ((uint16_t)0x0002) +#define IS_TIM_OC_POLARITY(POLARITY) (((POLARITY) == TIM_OCPolarity_High) || \ + ((POLARITY) == TIM_OCPolarity_Low)) +/** + * @} + */ + +/** @defgroup TIM_Output_Compare_N_Polarity + * @{ + */ + +#define TIM_OCNPolarity_High ((uint16_t)0x0000) +#define TIM_OCNPolarity_Low ((uint16_t)0x0008) +#define IS_TIM_OCN_POLARITY(POLARITY) (((POLARITY) == TIM_OCNPolarity_High) || \ + ((POLARITY) == TIM_OCNPolarity_Low)) +/** + * @} + */ + +/** @defgroup TIM_Output_Compare_state + * @{ + */ + +#define TIM_OutputState_Disable ((uint16_t)0x0000) +#define TIM_OutputState_Enable ((uint16_t)0x0001) +#define IS_TIM_OUTPUT_STATE(STATE) (((STATE) == TIM_OutputState_Disable) || \ + ((STATE) == TIM_OutputState_Enable)) +/** + * @} + */ + +/** @defgroup TIM_Output_Compare_N_state + * @{ + */ + +#define TIM_OutputNState_Disable ((uint16_t)0x0000) +#define TIM_OutputNState_Enable ((uint16_t)0x0004) +#define IS_TIM_OUTPUTN_STATE(STATE) (((STATE) == TIM_OutputNState_Disable) || \ + ((STATE) == TIM_OutputNState_Enable)) +/** + * @} + */ + +/** @defgroup TIM_Capture_Compare_state + * @{ + */ + +#define TIM_CCx_Enable ((uint16_t)0x0001) +#define TIM_CCx_Disable ((uint16_t)0x0000) +#define IS_TIM_CCX(CCX) (((CCX) == TIM_CCx_Enable) || \ + ((CCX) == TIM_CCx_Disable)) +/** + * @} + */ + +/** @defgroup TIM_Capture_Compare_N_state + * @{ + */ + +#define TIM_CCxN_Enable ((uint16_t)0x0004) +#define TIM_CCxN_Disable ((uint16_t)0x0000) +#define IS_TIM_CCXN(CCXN) (((CCXN) == TIM_CCxN_Enable) || \ + ((CCXN) == TIM_CCxN_Disable)) +/** + * @} + */ + +/** @defgroup Break_Input_enable_disable + * @{ + */ + +#define TIM_Break_Enable ((uint16_t)0x1000) +#define TIM_Break_Disable ((uint16_t)0x0000) +#define IS_TIM_BREAK_STATE(STATE) (((STATE) == TIM_Break_Enable) || \ + ((STATE) == TIM_Break_Disable)) +/** + * @} + */ + +/** @defgroup Break_Polarity + * @{ + */ + +#define TIM_BreakPolarity_Low ((uint16_t)0x0000) +#define TIM_BreakPolarity_High ((uint16_t)0x2000) +#define IS_TIM_BREAK_POLARITY(POLARITY) (((POLARITY) == TIM_BreakPolarity_Low) || \ + ((POLARITY) == TIM_BreakPolarity_High)) +/** + * @} + */ + +/** @defgroup TIM_AOE_Bit_Set_Reset + * @{ + */ + +#define TIM_AutomaticOutput_Enable ((uint16_t)0x4000) +#define TIM_AutomaticOutput_Disable ((uint16_t)0x0000) +#define IS_TIM_AUTOMATIC_OUTPUT_STATE(STATE) (((STATE) == TIM_AutomaticOutput_Enable) || \ + ((STATE) == TIM_AutomaticOutput_Disable)) +/** + * @} + */ + +/** @defgroup Lock_level + * @{ + */ + +#define TIM_LOCKLevel_OFF ((uint16_t)0x0000) +#define TIM_LOCKLevel_1 ((uint16_t)0x0100) +#define TIM_LOCKLevel_2 ((uint16_t)0x0200) +#define TIM_LOCKLevel_3 ((uint16_t)0x0300) +#define IS_TIM_LOCK_LEVEL(LEVEL) (((LEVEL) == TIM_LOCKLevel_OFF) || \ + ((LEVEL) == TIM_LOCKLevel_1) || \ + ((LEVEL) == TIM_LOCKLevel_2) || \ + ((LEVEL) == TIM_LOCKLevel_3)) +/** + * @} + */ + +/** @defgroup OSSI_Off_State_Selection_for_Idle_mode_state + * @{ + */ + +#define TIM_OSSIState_Enable ((uint16_t)0x0400) +#define TIM_OSSIState_Disable ((uint16_t)0x0000) +#define IS_TIM_OSSI_STATE(STATE) (((STATE) == TIM_OSSIState_Enable) || \ + ((STATE) == TIM_OSSIState_Disable)) +/** + * @} + */ + +/** @defgroup OSSR_Off_State_Selection_for_Run_mode_state + * @{ + */ + +#define TIM_OSSRState_Enable ((uint16_t)0x0800) +#define TIM_OSSRState_Disable ((uint16_t)0x0000) +#define IS_TIM_OSSR_STATE(STATE) (((STATE) == TIM_OSSRState_Enable) || \ + ((STATE) == TIM_OSSRState_Disable)) +/** + * @} + */ + +/** @defgroup TIM_Output_Compare_Idle_State + * @{ + */ + +#define TIM_OCIdleState_Set ((uint16_t)0x0100) +#define TIM_OCIdleState_Reset ((uint16_t)0x0000) +#define IS_TIM_OCIDLE_STATE(STATE) (((STATE) == TIM_OCIdleState_Set) || \ + ((STATE) == TIM_OCIdleState_Reset)) +/** + * @} + */ + +/** @defgroup TIM_Output_Compare_N_Idle_State + * @{ + */ + +#define TIM_OCNIdleState_Set ((uint16_t)0x0200) +#define TIM_OCNIdleState_Reset ((uint16_t)0x0000) +#define IS_TIM_OCNIDLE_STATE(STATE) (((STATE) == TIM_OCNIdleState_Set) || \ + ((STATE) == TIM_OCNIdleState_Reset)) +/** + * @} + */ + +/** @defgroup TIM_Input_Capture_Polarity + * @{ + */ + +#define TIM_ICPolarity_Rising ((uint16_t)0x0000) +#define TIM_ICPolarity_Falling ((uint16_t)0x0002) +#define TIM_ICPolarity_BothEdge ((uint16_t)0x000A) +#define IS_TIM_IC_POLARITY(POLARITY) (((POLARITY) == TIM_ICPolarity_Rising) || \ + ((POLARITY) == TIM_ICPolarity_Falling)) +#define IS_TIM_IC_POLARITY_LITE(POLARITY) (((POLARITY) == TIM_ICPolarity_Rising) || \ + ((POLARITY) == TIM_ICPolarity_Falling)|| \ + ((POLARITY) == TIM_ICPolarity_BothEdge)) +/** + * @} + */ + +/** @defgroup TIM_Input_Capture_Selection + * @{ + */ + +#define TIM_ICSelection_DirectTI ((uint16_t)0x0001) /*!< TIM Input 1, 2, 3 or 4 is selected to be + connected to IC1, IC2, IC3 or IC4, respectively */ +#define TIM_ICSelection_IndirectTI ((uint16_t)0x0002) /*!< TIM Input 1, 2, 3 or 4 is selected to be + connected to IC2, IC1, IC4 or IC3, respectively. */ +#define TIM_ICSelection_TRC ((uint16_t)0x0003) /*!< TIM Input 1, 2, 3 or 4 is selected to be connected to TRC. */ +#define IS_TIM_IC_SELECTION(SELECTION) (((SELECTION) == TIM_ICSelection_DirectTI) || \ + ((SELECTION) == TIM_ICSelection_IndirectTI) || \ + ((SELECTION) == TIM_ICSelection_TRC)) +/** + * @} + */ + +/** @defgroup TIM_Input_Capture_Prescaler + * @{ + */ + +#define TIM_ICPSC_DIV1 ((uint16_t)0x0000) /*!< Capture performed each time an edge is detected on the capture input. */ +#define TIM_ICPSC_DIV2 ((uint16_t)0x0004) /*!< Capture performed once every 2 events. */ +#define TIM_ICPSC_DIV4 ((uint16_t)0x0008) /*!< Capture performed once every 4 events. */ +#define TIM_ICPSC_DIV8 ((uint16_t)0x000C) /*!< Capture performed once every 8 events. */ +#define IS_TIM_IC_PRESCALER(PRESCALER) (((PRESCALER) == TIM_ICPSC_DIV1) || \ + ((PRESCALER) == TIM_ICPSC_DIV2) || \ + ((PRESCALER) == TIM_ICPSC_DIV4) || \ + ((PRESCALER) == TIM_ICPSC_DIV8)) +/** + * @} + */ + +/** @defgroup TIM_interrupt_sources + * @{ + */ + +#define TIM_IT_Update ((uint16_t)0x0001) +#define TIM_IT_CC1 ((uint16_t)0x0002) +#define TIM_IT_CC2 ((uint16_t)0x0004) +#define TIM_IT_CC3 ((uint16_t)0x0008) +#define TIM_IT_CC4 ((uint16_t)0x0010) +#define TIM_IT_COM ((uint16_t)0x0020) +#define TIM_IT_Trigger ((uint16_t)0x0040) +#define TIM_IT_Break ((uint16_t)0x0080) +#define IS_TIM_IT(IT) ((((IT) & (uint16_t)0xFF00) == 0x0000) && ((IT) != 0x0000)) + +#define IS_TIM_GET_IT(IT) (((IT) == TIM_IT_Update) || \ + ((IT) == TIM_IT_CC1) || \ + ((IT) == TIM_IT_CC2) || \ + ((IT) == TIM_IT_CC3) || \ + ((IT) == TIM_IT_CC4) || \ + ((IT) == TIM_IT_COM) || \ + ((IT) == TIM_IT_Trigger) || \ + ((IT) == TIM_IT_Break)) +/** + * @} + */ + +/** @defgroup TIM_DMA_Base_address + * @{ + */ + +#define TIM_DMABase_CR1 ((uint16_t)0x0000) +#define TIM_DMABase_CR2 ((uint16_t)0x0001) +#define TIM_DMABase_SMCR ((uint16_t)0x0002) +#define TIM_DMABase_DIER ((uint16_t)0x0003) +#define TIM_DMABase_SR ((uint16_t)0x0004) +#define TIM_DMABase_EGR ((uint16_t)0x0005) +#define TIM_DMABase_CCMR1 ((uint16_t)0x0006) +#define TIM_DMABase_CCMR2 ((uint16_t)0x0007) +#define TIM_DMABase_CCER ((uint16_t)0x0008) +#define TIM_DMABase_CNT ((uint16_t)0x0009) +#define TIM_DMABase_PSC ((uint16_t)0x000A) +#define TIM_DMABase_ARR ((uint16_t)0x000B) +#define TIM_DMABase_RCR ((uint16_t)0x000C) +#define TIM_DMABase_CCR1 ((uint16_t)0x000D) +#define TIM_DMABase_CCR2 ((uint16_t)0x000E) +#define TIM_DMABase_CCR3 ((uint16_t)0x000F) +#define TIM_DMABase_CCR4 ((uint16_t)0x0010) +#define TIM_DMABase_BDTR ((uint16_t)0x0011) +#define TIM_DMABase_DCR ((uint16_t)0x0012) +#define IS_TIM_DMA_BASE(BASE) (((BASE) == TIM_DMABase_CR1) || \ + ((BASE) == TIM_DMABase_CR2) || \ + ((BASE) == TIM_DMABase_SMCR) || \ + ((BASE) == TIM_DMABase_DIER) || \ + ((BASE) == TIM_DMABase_SR) || \ + ((BASE) == TIM_DMABase_EGR) || \ + ((BASE) == TIM_DMABase_CCMR1) || \ + ((BASE) == TIM_DMABase_CCMR2) || \ + ((BASE) == TIM_DMABase_CCER) || \ + ((BASE) == TIM_DMABase_CNT) || \ + ((BASE) == TIM_DMABase_PSC) || \ + ((BASE) == TIM_DMABase_ARR) || \ + ((BASE) == TIM_DMABase_RCR) || \ + ((BASE) == TIM_DMABase_CCR1) || \ + ((BASE) == TIM_DMABase_CCR2) || \ + ((BASE) == TIM_DMABase_CCR3) || \ + ((BASE) == TIM_DMABase_CCR4) || \ + ((BASE) == TIM_DMABase_BDTR) || \ + ((BASE) == TIM_DMABase_DCR)) +/** + * @} + */ + +/** @defgroup TIM_DMA_Burst_Length + * @{ + */ + +#define TIM_DMABurstLength_1Transfer ((uint16_t)0x0000) +#define TIM_DMABurstLength_2Transfers ((uint16_t)0x0100) +#define TIM_DMABurstLength_3Transfers ((uint16_t)0x0200) +#define TIM_DMABurstLength_4Transfers ((uint16_t)0x0300) +#define TIM_DMABurstLength_5Transfers ((uint16_t)0x0400) +#define TIM_DMABurstLength_6Transfers ((uint16_t)0x0500) +#define TIM_DMABurstLength_7Transfers ((uint16_t)0x0600) +#define TIM_DMABurstLength_8Transfers ((uint16_t)0x0700) +#define TIM_DMABurstLength_9Transfers ((uint16_t)0x0800) +#define TIM_DMABurstLength_10Transfers ((uint16_t)0x0900) +#define TIM_DMABurstLength_11Transfers ((uint16_t)0x0A00) +#define TIM_DMABurstLength_12Transfers ((uint16_t)0x0B00) +#define TIM_DMABurstLength_13Transfers ((uint16_t)0x0C00) +#define TIM_DMABurstLength_14Transfers ((uint16_t)0x0D00) +#define TIM_DMABurstLength_15Transfers ((uint16_t)0x0E00) +#define TIM_DMABurstLength_16Transfers ((uint16_t)0x0F00) +#define TIM_DMABurstLength_17Transfers ((uint16_t)0x1000) +#define TIM_DMABurstLength_18Transfers ((uint16_t)0x1100) +#define IS_TIM_DMA_LENGTH(LENGTH) (((LENGTH) == TIM_DMABurstLength_1Transfer) || \ + ((LENGTH) == TIM_DMABurstLength_2Transfers) || \ + ((LENGTH) == TIM_DMABurstLength_3Transfers) || \ + ((LENGTH) == TIM_DMABurstLength_4Transfers) || \ + ((LENGTH) == TIM_DMABurstLength_5Transfers) || \ + ((LENGTH) == TIM_DMABurstLength_6Transfers) || \ + ((LENGTH) == TIM_DMABurstLength_7Transfers) || \ + ((LENGTH) == TIM_DMABurstLength_8Transfers) || \ + ((LENGTH) == TIM_DMABurstLength_9Transfers) || \ + ((LENGTH) == TIM_DMABurstLength_10Transfers) || \ + ((LENGTH) == TIM_DMABurstLength_11Transfers) || \ + ((LENGTH) == TIM_DMABurstLength_12Transfers) || \ + ((LENGTH) == TIM_DMABurstLength_13Transfers) || \ + ((LENGTH) == TIM_DMABurstLength_14Transfers) || \ + ((LENGTH) == TIM_DMABurstLength_15Transfers) || \ + ((LENGTH) == TIM_DMABurstLength_16Transfers) || \ + ((LENGTH) == TIM_DMABurstLength_17Transfers) || \ + ((LENGTH) == TIM_DMABurstLength_18Transfers)) +/** + * @} + */ + +/** @defgroup TIM_DMA_sources + * @{ + */ + +#define TIM_DMA_Update ((uint16_t)0x0100) +#define TIM_DMA_CC1 ((uint16_t)0x0200) +#define TIM_DMA_CC2 ((uint16_t)0x0400) +#define TIM_DMA_CC3 ((uint16_t)0x0800) +#define TIM_DMA_CC4 ((uint16_t)0x1000) +#define TIM_DMA_COM ((uint16_t)0x2000) +#define TIM_DMA_Trigger ((uint16_t)0x4000) +#define IS_TIM_DMA_SOURCE(SOURCE) ((((SOURCE) & (uint16_t)0x80FF) == 0x0000) && ((SOURCE) != 0x0000)) + +/** + * @} + */ + +/** @defgroup TIM_External_Trigger_Prescaler + * @{ + */ + +#define TIM_ExtTRGPSC_OFF ((uint16_t)0x0000) +#define TIM_ExtTRGPSC_DIV2 ((uint16_t)0x1000) +#define TIM_ExtTRGPSC_DIV4 ((uint16_t)0x2000) +#define TIM_ExtTRGPSC_DIV8 ((uint16_t)0x3000) +#define IS_TIM_EXT_PRESCALER(PRESCALER) (((PRESCALER) == TIM_ExtTRGPSC_OFF) || \ + ((PRESCALER) == TIM_ExtTRGPSC_DIV2) || \ + ((PRESCALER) == TIM_ExtTRGPSC_DIV4) || \ + ((PRESCALER) == TIM_ExtTRGPSC_DIV8)) +/** + * @} + */ + +/** @defgroup TIM_Internal_Trigger_Selection + * @{ + */ + +#define TIM_TS_ITR0 ((uint16_t)0x0000) +#define TIM_TS_ITR1 ((uint16_t)0x0010) +#define TIM_TS_ITR2 ((uint16_t)0x0020) +#define TIM_TS_ITR3 ((uint16_t)0x0030) +#define TIM_TS_TI1F_ED ((uint16_t)0x0040) +#define TIM_TS_TI1FP1 ((uint16_t)0x0050) +#define TIM_TS_TI2FP2 ((uint16_t)0x0060) +#define TIM_TS_ETRF ((uint16_t)0x0070) +#define IS_TIM_TRIGGER_SELECTION(SELECTION) (((SELECTION) == TIM_TS_ITR0) || \ + ((SELECTION) == TIM_TS_ITR1) || \ + ((SELECTION) == TIM_TS_ITR2) || \ + ((SELECTION) == TIM_TS_ITR3) || \ + ((SELECTION) == TIM_TS_TI1F_ED) || \ + ((SELECTION) == TIM_TS_TI1FP1) || \ + ((SELECTION) == TIM_TS_TI2FP2) || \ + ((SELECTION) == TIM_TS_ETRF)) +#define IS_TIM_INTERNAL_TRIGGER_SELECTION(SELECTION) (((SELECTION) == TIM_TS_ITR0) || \ + ((SELECTION) == TIM_TS_ITR1) || \ + ((SELECTION) == TIM_TS_ITR2) || \ + ((SELECTION) == TIM_TS_ITR3)) +/** + * @} + */ + +/** @defgroup TIM_TIx_External_Clock_Source + * @{ + */ + +#define TIM_TIxExternalCLK1Source_TI1 ((uint16_t)0x0050) +#define TIM_TIxExternalCLK1Source_TI2 ((uint16_t)0x0060) +#define TIM_TIxExternalCLK1Source_TI1ED ((uint16_t)0x0040) +#define IS_TIM_TIXCLK_SOURCE(SOURCE) (((SOURCE) == TIM_TIxExternalCLK1Source_TI1) || \ + ((SOURCE) == TIM_TIxExternalCLK1Source_TI2) || \ + ((SOURCE) == TIM_TIxExternalCLK1Source_TI1ED)) +/** + * @} + */ + +/** @defgroup TIM_External_Trigger_Polarity + * @{ + */ +#define TIM_ExtTRGPolarity_Inverted ((uint16_t)0x8000) +#define TIM_ExtTRGPolarity_NonInverted ((uint16_t)0x0000) +#define IS_TIM_EXT_POLARITY(POLARITY) (((POLARITY) == TIM_ExtTRGPolarity_Inverted) || \ + ((POLARITY) == TIM_ExtTRGPolarity_NonInverted)) +/** + * @} + */ + +/** @defgroup TIM_Prescaler_Reload_Mode + * @{ + */ + +#define TIM_PSCReloadMode_Update ((uint16_t)0x0000) +#define TIM_PSCReloadMode_Immediate ((uint16_t)0x0001) +#define IS_TIM_PRESCALER_RELOAD(RELOAD) (((RELOAD) == TIM_PSCReloadMode_Update) || \ + ((RELOAD) == TIM_PSCReloadMode_Immediate)) +/** + * @} + */ + +/** @defgroup TIM_Forced_Action + * @{ + */ + +#define TIM_ForcedAction_Active ((uint16_t)0x0050) +#define TIM_ForcedAction_InActive ((uint16_t)0x0040) +#define IS_TIM_FORCED_ACTION(ACTION) (((ACTION) == TIM_ForcedAction_Active) || \ + ((ACTION) == TIM_ForcedAction_InActive)) +/** + * @} + */ + +/** @defgroup TIM_Encoder_Mode + * @{ + */ + +#define TIM_EncoderMode_TI1 ((uint16_t)0x0001) +#define TIM_EncoderMode_TI2 ((uint16_t)0x0002) +#define TIM_EncoderMode_TI12 ((uint16_t)0x0003) +#define IS_TIM_ENCODER_MODE(MODE) (((MODE) == TIM_EncoderMode_TI1) || \ + ((MODE) == TIM_EncoderMode_TI2) || \ + ((MODE) == TIM_EncoderMode_TI12)) +/** + * @} + */ + + +/** @defgroup TIM_Event_Source + * @{ + */ + +#define TIM_EventSource_Update ((uint16_t)0x0001) +#define TIM_EventSource_CC1 ((uint16_t)0x0002) +#define TIM_EventSource_CC2 ((uint16_t)0x0004) +#define TIM_EventSource_CC3 ((uint16_t)0x0008) +#define TIM_EventSource_CC4 ((uint16_t)0x0010) +#define TIM_EventSource_COM ((uint16_t)0x0020) +#define TIM_EventSource_Trigger ((uint16_t)0x0040) +#define TIM_EventSource_Break ((uint16_t)0x0080) +#define IS_TIM_EVENT_SOURCE(SOURCE) ((((SOURCE) & (uint16_t)0xFF00) == 0x0000) && ((SOURCE) != 0x0000)) + +/** + * @} + */ + +/** @defgroup TIM_Update_Source + * @{ + */ + +#define TIM_UpdateSource_Global ((uint16_t)0x0000) /*!< Source of update is the counter overflow/underflow + or the setting of UG bit, or an update generation + through the slave mode controller. */ +#define TIM_UpdateSource_Regular ((uint16_t)0x0001) /*!< Source of update is counter overflow/underflow. */ +#define IS_TIM_UPDATE_SOURCE(SOURCE) (((SOURCE) == TIM_UpdateSource_Global) || \ + ((SOURCE) == TIM_UpdateSource_Regular)) +/** + * @} + */ + +/** @defgroup TIM_Output_Compare_Preload_State + * @{ + */ + +#define TIM_OCPreload_Enable ((uint16_t)0x0008) +#define TIM_OCPreload_Disable ((uint16_t)0x0000) +#define IS_TIM_OCPRELOAD_STATE(STATE) (((STATE) == TIM_OCPreload_Enable) || \ + ((STATE) == TIM_OCPreload_Disable)) +/** + * @} + */ + +/** @defgroup TIM_Output_Compare_Fast_State + * @{ + */ + +#define TIM_OCFast_Enable ((uint16_t)0x0004) +#define TIM_OCFast_Disable ((uint16_t)0x0000) +#define IS_TIM_OCFAST_STATE(STATE) (((STATE) == TIM_OCFast_Enable) || \ + ((STATE) == TIM_OCFast_Disable)) + +/** + * @} + */ + +/** @defgroup TIM_Output_Compare_Clear_State + * @{ + */ + +#define TIM_OCClear_Enable ((uint16_t)0x0080) +#define TIM_OCClear_Disable ((uint16_t)0x0000) +#define IS_TIM_OCCLEAR_STATE(STATE) (((STATE) == TIM_OCClear_Enable) || \ + ((STATE) == TIM_OCClear_Disable)) +/** + * @} + */ + +/** @defgroup TIM_Trigger_Output_Source + * @{ + */ + +#define TIM_TRGOSource_Reset ((uint16_t)0x0000) +#define TIM_TRGOSource_Enable ((uint16_t)0x0010) +#define TIM_TRGOSource_Update ((uint16_t)0x0020) +#define TIM_TRGOSource_OC1 ((uint16_t)0x0030) +#define TIM_TRGOSource_OC1Ref ((uint16_t)0x0040) +#define TIM_TRGOSource_OC2Ref ((uint16_t)0x0050) +#define TIM_TRGOSource_OC3Ref ((uint16_t)0x0060) +#define TIM_TRGOSource_OC4Ref ((uint16_t)0x0070) +#define IS_TIM_TRGO_SOURCE(SOURCE) (((SOURCE) == TIM_TRGOSource_Reset) || \ + ((SOURCE) == TIM_TRGOSource_Enable) || \ + ((SOURCE) == TIM_TRGOSource_Update) || \ + ((SOURCE) == TIM_TRGOSource_OC1) || \ + ((SOURCE) == TIM_TRGOSource_OC1Ref) || \ + ((SOURCE) == TIM_TRGOSource_OC2Ref) || \ + ((SOURCE) == TIM_TRGOSource_OC3Ref) || \ + ((SOURCE) == TIM_TRGOSource_OC4Ref)) +/** + * @} + */ + +/** @defgroup TIM_Slave_Mode + * @{ + */ + +#define TIM_SlaveMode_Reset ((uint16_t)0x0004) +#define TIM_SlaveMode_Gated ((uint16_t)0x0005) +#define TIM_SlaveMode_Trigger ((uint16_t)0x0006) +#define TIM_SlaveMode_External1 ((uint16_t)0x0007) +#define IS_TIM_SLAVE_MODE(MODE) (((MODE) == TIM_SlaveMode_Reset) || \ + ((MODE) == TIM_SlaveMode_Gated) || \ + ((MODE) == TIM_SlaveMode_Trigger) || \ + ((MODE) == TIM_SlaveMode_External1)) +/** + * @} + */ + +/** @defgroup TIM_Master_Slave_Mode + * @{ + */ + +#define TIM_MasterSlaveMode_Enable ((uint16_t)0x0080) +#define TIM_MasterSlaveMode_Disable ((uint16_t)0x0000) +#define IS_TIM_MSM_STATE(STATE) (((STATE) == TIM_MasterSlaveMode_Enable) || \ + ((STATE) == TIM_MasterSlaveMode_Disable)) +/** + * @} + */ + +/** @defgroup TIM_Flags + * @{ + */ + +#define TIM_FLAG_Update ((uint16_t)0x0001) +#define TIM_FLAG_CC1 ((uint16_t)0x0002) +#define TIM_FLAG_CC2 ((uint16_t)0x0004) +#define TIM_FLAG_CC3 ((uint16_t)0x0008) +#define TIM_FLAG_CC4 ((uint16_t)0x0010) +#define TIM_FLAG_COM ((uint16_t)0x0020) +#define TIM_FLAG_Trigger ((uint16_t)0x0040) +#define TIM_FLAG_Break ((uint16_t)0x0080) +#define TIM_FLAG_CC1OF ((uint16_t)0x0200) +#define TIM_FLAG_CC2OF ((uint16_t)0x0400) +#define TIM_FLAG_CC3OF ((uint16_t)0x0800) +#define TIM_FLAG_CC4OF ((uint16_t)0x1000) +#define IS_TIM_GET_FLAG(FLAG) (((FLAG) == TIM_FLAG_Update) || \ + ((FLAG) == TIM_FLAG_CC1) || \ + ((FLAG) == TIM_FLAG_CC2) || \ + ((FLAG) == TIM_FLAG_CC3) || \ + ((FLAG) == TIM_FLAG_CC4) || \ + ((FLAG) == TIM_FLAG_COM) || \ + ((FLAG) == TIM_FLAG_Trigger) || \ + ((FLAG) == TIM_FLAG_Break) || \ + ((FLAG) == TIM_FLAG_CC1OF) || \ + ((FLAG) == TIM_FLAG_CC2OF) || \ + ((FLAG) == TIM_FLAG_CC3OF) || \ + ((FLAG) == TIM_FLAG_CC4OF)) + + +#define IS_TIM_CLEAR_FLAG(TIM_FLAG) ((((TIM_FLAG) & (uint16_t)0xE100) == 0x0000) && ((TIM_FLAG) != 0x0000)) +/** + * @} + */ + +/** @defgroup TIM_Input_Capture_Filer_Value + * @{ + */ + +#define IS_TIM_IC_FILTER(ICFILTER) ((ICFILTER) <= 0xF) +/** + * @} + */ + +/** @defgroup TIM_External_Trigger_Filter + * @{ + */ + +#define IS_TIM_EXT_FILTER(EXTFILTER) ((EXTFILTER) <= 0xF) +/** + * @} + */ + +/** @defgroup TIM_Legacy + * @{ + */ + +#define TIM_DMABurstLength_1Byte TIM_DMABurstLength_1Transfer +#define TIM_DMABurstLength_2Bytes TIM_DMABurstLength_2Transfers +#define TIM_DMABurstLength_3Bytes TIM_DMABurstLength_3Transfers +#define TIM_DMABurstLength_4Bytes TIM_DMABurstLength_4Transfers +#define TIM_DMABurstLength_5Bytes TIM_DMABurstLength_5Transfers +#define TIM_DMABurstLength_6Bytes TIM_DMABurstLength_6Transfers +#define TIM_DMABurstLength_7Bytes TIM_DMABurstLength_7Transfers +#define TIM_DMABurstLength_8Bytes TIM_DMABurstLength_8Transfers +#define TIM_DMABurstLength_9Bytes TIM_DMABurstLength_9Transfers +#define TIM_DMABurstLength_10Bytes TIM_DMABurstLength_10Transfers +#define TIM_DMABurstLength_11Bytes TIM_DMABurstLength_11Transfers +#define TIM_DMABurstLength_12Bytes TIM_DMABurstLength_12Transfers +#define TIM_DMABurstLength_13Bytes TIM_DMABurstLength_13Transfers +#define TIM_DMABurstLength_14Bytes TIM_DMABurstLength_14Transfers +#define TIM_DMABurstLength_15Bytes TIM_DMABurstLength_15Transfers +#define TIM_DMABurstLength_16Bytes TIM_DMABurstLength_16Transfers +#define TIM_DMABurstLength_17Bytes TIM_DMABurstLength_17Transfers +#define TIM_DMABurstLength_18Bytes TIM_DMABurstLength_18Transfers +/** + * @} + */ + +/** + * @} + */ + +/** @defgroup TIM_Exported_Macros + * @{ + */ + +/** + * @} + */ + +/** @defgroup TIM_Exported_Functions + * @{ + */ + +void TIM_DeInit(TIM_TypeDef* TIMx); +void TIM_TimeBaseInit(TIM_TypeDef* TIMx, TIM_TimeBaseInitTypeDef* TIM_TimeBaseInitStruct); +void TIM_OC1Init(TIM_TypeDef* TIMx, TIM_OCInitTypeDef* TIM_OCInitStruct); +void TIM_OC2Init(TIM_TypeDef* TIMx, TIM_OCInitTypeDef* TIM_OCInitStruct); +void TIM_OC3Init(TIM_TypeDef* TIMx, TIM_OCInitTypeDef* TIM_OCInitStruct); +void TIM_OC4Init(TIM_TypeDef* TIMx, TIM_OCInitTypeDef* TIM_OCInitStruct); +void TIM_ICInit(TIM_TypeDef* TIMx, TIM_ICInitTypeDef* TIM_ICInitStruct); +void TIM_PWMIConfig(TIM_TypeDef* TIMx, TIM_ICInitTypeDef* TIM_ICInitStruct); +void TIM_BDTRConfig(TIM_TypeDef* TIMx, TIM_BDTRInitTypeDef *TIM_BDTRInitStruct); +void TIM_TimeBaseStructInit(TIM_TimeBaseInitTypeDef* TIM_TimeBaseInitStruct); +void TIM_OCStructInit(TIM_OCInitTypeDef* TIM_OCInitStruct); +void TIM_ICStructInit(TIM_ICInitTypeDef* TIM_ICInitStruct); +void TIM_BDTRStructInit(TIM_BDTRInitTypeDef* TIM_BDTRInitStruct); +void TIM_Cmd(TIM_TypeDef* TIMx, FunctionalState NewState); +void TIM_CtrlPWMOutputs(TIM_TypeDef* TIMx, FunctionalState NewState); +void TIM_ITConfig(TIM_TypeDef* TIMx, uint16_t TIM_IT, FunctionalState NewState); +void TIM_GenerateEvent(TIM_TypeDef* TIMx, uint16_t TIM_EventSource); +void TIM_DMAConfig(TIM_TypeDef* TIMx, uint16_t TIM_DMABase, uint16_t TIM_DMABurstLength); +void TIM_DMACmd(TIM_TypeDef* TIMx, uint16_t TIM_DMASource, FunctionalState NewState); +void TIM_InternalClockConfig(TIM_TypeDef* TIMx); +void TIM_ITRxExternalClockConfig(TIM_TypeDef* TIMx, uint16_t TIM_InputTriggerSource); +void TIM_TIxExternalClockConfig(TIM_TypeDef* TIMx, uint16_t TIM_TIxExternalCLKSource, + uint16_t TIM_ICPolarity, uint16_t ICFilter); +void TIM_ETRClockMode1Config(TIM_TypeDef* TIMx, uint16_t TIM_ExtTRGPrescaler, uint16_t TIM_ExtTRGPolarity, + uint16_t ExtTRGFilter); +void TIM_ETRClockMode2Config(TIM_TypeDef* TIMx, uint16_t TIM_ExtTRGPrescaler, + uint16_t TIM_ExtTRGPolarity, uint16_t ExtTRGFilter); +void TIM_ETRConfig(TIM_TypeDef* TIMx, uint16_t TIM_ExtTRGPrescaler, uint16_t TIM_ExtTRGPolarity, + uint16_t ExtTRGFilter); +void TIM_PrescalerConfig(TIM_TypeDef* TIMx, uint16_t Prescaler, uint16_t TIM_PSCReloadMode); +void TIM_CounterModeConfig(TIM_TypeDef* TIMx, uint16_t TIM_CounterMode); +void TIM_SelectInputTrigger(TIM_TypeDef* TIMx, uint16_t TIM_InputTriggerSource); +void TIM_EncoderInterfaceConfig(TIM_TypeDef* TIMx, uint16_t TIM_EncoderMode, + uint16_t TIM_IC1Polarity, uint16_t TIM_IC2Polarity); +void TIM_ForcedOC1Config(TIM_TypeDef* TIMx, uint16_t TIM_ForcedAction); +void TIM_ForcedOC2Config(TIM_TypeDef* TIMx, uint16_t TIM_ForcedAction); +void TIM_ForcedOC3Config(TIM_TypeDef* TIMx, uint16_t TIM_ForcedAction); +void TIM_ForcedOC4Config(TIM_TypeDef* TIMx, uint16_t TIM_ForcedAction); +void TIM_ARRPreloadConfig(TIM_TypeDef* TIMx, FunctionalState NewState); +void TIM_SelectCOM(TIM_TypeDef* TIMx, FunctionalState NewState); +void TIM_SelectCCDMA(TIM_TypeDef* TIMx, FunctionalState NewState); +void TIM_CCPreloadControl(TIM_TypeDef* TIMx, FunctionalState NewState); +void TIM_OC1PreloadConfig(TIM_TypeDef* TIMx, uint16_t TIM_OCPreload); +void TIM_OC2PreloadConfig(TIM_TypeDef* TIMx, uint16_t TIM_OCPreload); +void TIM_OC3PreloadConfig(TIM_TypeDef* TIMx, uint16_t TIM_OCPreload); +void TIM_OC4PreloadConfig(TIM_TypeDef* TIMx, uint16_t TIM_OCPreload); +void TIM_OC1FastConfig(TIM_TypeDef* TIMx, uint16_t TIM_OCFast); +void TIM_OC2FastConfig(TIM_TypeDef* TIMx, uint16_t TIM_OCFast); +void TIM_OC3FastConfig(TIM_TypeDef* TIMx, uint16_t TIM_OCFast); +void TIM_OC4FastConfig(TIM_TypeDef* TIMx, uint16_t TIM_OCFast); +void TIM_ClearOC1Ref(TIM_TypeDef* TIMx, uint16_t TIM_OCClear); +void TIM_ClearOC2Ref(TIM_TypeDef* TIMx, uint16_t TIM_OCClear); +void TIM_ClearOC3Ref(TIM_TypeDef* TIMx, uint16_t TIM_OCClear); +void TIM_ClearOC4Ref(TIM_TypeDef* TIMx, uint16_t TIM_OCClear); +void TIM_OC1PolarityConfig(TIM_TypeDef* TIMx, uint16_t TIM_OCPolarity); +void TIM_OC1NPolarityConfig(TIM_TypeDef* TIMx, uint16_t TIM_OCNPolarity); +void TIM_OC2PolarityConfig(TIM_TypeDef* TIMx, uint16_t TIM_OCPolarity); +void TIM_OC2NPolarityConfig(TIM_TypeDef* TIMx, uint16_t TIM_OCNPolarity); +void TIM_OC3PolarityConfig(TIM_TypeDef* TIMx, uint16_t TIM_OCPolarity); +void TIM_OC3NPolarityConfig(TIM_TypeDef* TIMx, uint16_t TIM_OCNPolarity); +void TIM_OC4PolarityConfig(TIM_TypeDef* TIMx, uint16_t TIM_OCPolarity); +void TIM_CCxCmd(TIM_TypeDef* TIMx, uint16_t TIM_Channel, uint16_t TIM_CCx); +void TIM_CCxNCmd(TIM_TypeDef* TIMx, uint16_t TIM_Channel, uint16_t TIM_CCxN); +void TIM_SelectOCxM(TIM_TypeDef* TIMx, uint16_t TIM_Channel, uint16_t TIM_OCMode); +void TIM_UpdateDisableConfig(TIM_TypeDef* TIMx, FunctionalState NewState); +void TIM_UpdateRequestConfig(TIM_TypeDef* TIMx, uint16_t TIM_UpdateSource); +void TIM_SelectHallSensor(TIM_TypeDef* TIMx, FunctionalState NewState); +void TIM_SelectOnePulseMode(TIM_TypeDef* TIMx, uint16_t TIM_OPMode); +void TIM_SelectOutputTrigger(TIM_TypeDef* TIMx, uint16_t TIM_TRGOSource); +void TIM_SelectSlaveMode(TIM_TypeDef* TIMx, uint16_t TIM_SlaveMode); +void TIM_SelectMasterSlaveMode(TIM_TypeDef* TIMx, uint16_t TIM_MasterSlaveMode); +void TIM_SetCounter(TIM_TypeDef* TIMx, uint16_t Counter); +void TIM_SetAutoreload(TIM_TypeDef* TIMx, uint16_t Autoreload); +void TIM_SetCompare1(TIM_TypeDef* TIMx, uint16_t Compare1); +void TIM_SetCompare2(TIM_TypeDef* TIMx, uint16_t Compare2); +void TIM_SetCompare3(TIM_TypeDef* TIMx, uint16_t Compare3); +void TIM_SetCompare4(TIM_TypeDef* TIMx, uint16_t Compare4); +void TIM_SetIC1Prescaler(TIM_TypeDef* TIMx, uint16_t TIM_ICPSC); +void TIM_SetIC2Prescaler(TIM_TypeDef* TIMx, uint16_t TIM_ICPSC); +void TIM_SetIC3Prescaler(TIM_TypeDef* TIMx, uint16_t TIM_ICPSC); +void TIM_SetIC4Prescaler(TIM_TypeDef* TIMx, uint16_t TIM_ICPSC); +void TIM_SetClockDivision(TIM_TypeDef* TIMx, uint16_t TIM_CKD); +uint16_t TIM_GetCapture1(TIM_TypeDef* TIMx); +uint16_t TIM_GetCapture2(TIM_TypeDef* TIMx); +uint16_t TIM_GetCapture3(TIM_TypeDef* TIMx); +uint16_t TIM_GetCapture4(TIM_TypeDef* TIMx); +uint16_t TIM_GetCounter(TIM_TypeDef* TIMx); +uint16_t TIM_GetPrescaler(TIM_TypeDef* TIMx); +FlagStatus TIM_GetFlagStatus(TIM_TypeDef* TIMx, uint16_t TIM_FLAG); +void TIM_ClearFlag(TIM_TypeDef* TIMx, uint16_t TIM_FLAG); +ITStatus TIM_GetITStatus(TIM_TypeDef* TIMx, uint16_t TIM_IT); +void TIM_ClearITPendingBit(TIM_TypeDef* TIMx, uint16_t TIM_IT); + +#ifdef __cplusplus +} +#endif + +#endif /*__STM32F10x_TIM_H */ +/** + * @} + */ + +/** + * @} + */ + +/** + * @} + */ + +/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ diff --git a/Libraries/STM32F10x_StdPeriph_Driver/inc/stm32f10x_usart.h b/Libraries/STM32F10x_StdPeriph_Driver/inc/stm32f10x_usart.h new file mode 100644 index 0000000..25137c4 --- /dev/null +++ b/Libraries/STM32F10x_StdPeriph_Driver/inc/stm32f10x_usart.h @@ -0,0 +1,429 @@ +/** + ****************************************************************************** + * @file stm32f10x_usart.h + * @author MCD Application Team + * @version V3.6.1 + * @date 05-March-2012 + * @brief This file contains all the functions prototypes for the USART + * firmware library. + ****************************************************************************** + * @attention + * + *

    © COPYRIGHT 2012 STMicroelectronics

    + * + * Licensed under MCD-ST Liberty SW License Agreement V2, (the "License"); + * You may not use this file except in compliance with the License. + * You may obtain a copy of the License at: + * + * http://www.st.com/software_license_agreement_liberty_v2 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, + * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + * + ****************************************************************************** + */ + +/* Define to prevent recursive inclusion -------------------------------------*/ +#ifndef __STM32F10x_USART_H +#define __STM32F10x_USART_H + +#ifdef __cplusplus + extern "C" { +#endif + +/* Includes ------------------------------------------------------------------*/ +#include "stm32f10x.h" + +/** @addtogroup STM32F10x_StdPeriph_Driver + * @{ + */ + +/** @addtogroup USART + * @{ + */ + +/** @defgroup USART_Exported_Types + * @{ + */ + +/** + * @brief USART Init Structure definition + */ + +typedef struct +{ + uint32_t USART_BaudRate; /*!< This member configures the USART communication baud rate. + The baud rate is computed using the following formula: + - IntegerDivider = ((PCLKx) / (16 * (USART_InitStruct->USART_BaudRate))) + - FractionalDivider = ((IntegerDivider - ((u32) IntegerDivider)) * 16) + 0.5 */ + + uint16_t USART_WordLength; /*!< Specifies the number of data bits transmitted or received in a frame. + This parameter can be a value of @ref USART_Word_Length */ + + uint16_t USART_StopBits; /*!< Specifies the number of stop bits transmitted. + This parameter can be a value of @ref USART_Stop_Bits */ + + uint16_t USART_Parity; /*!< Specifies the parity mode. + This parameter can be a value of @ref USART_Parity + @note When parity is enabled, the computed parity is inserted + at the MSB position of the transmitted data (9th bit when + the word length is set to 9 data bits; 8th bit when the + word length is set to 8 data bits). */ + + uint16_t USART_Mode; /*!< Specifies wether the Receive or Transmit mode is enabled or disabled. + This parameter can be a value of @ref USART_Mode */ + + uint16_t USART_HardwareFlowControl; /*!< Specifies wether the hardware flow control mode is enabled + or disabled. + This parameter can be a value of @ref USART_Hardware_Flow_Control */ +} USART_InitTypeDef; + +/** + * @brief USART Clock Init Structure definition + */ + +typedef struct +{ + + uint16_t USART_Clock; /*!< Specifies whether the USART clock is enabled or disabled. + This parameter can be a value of @ref USART_Clock */ + + uint16_t USART_CPOL; /*!< Specifies the steady state value of the serial clock. + This parameter can be a value of @ref USART_Clock_Polarity */ + + uint16_t USART_CPHA; /*!< Specifies the clock transition on which the bit capture is made. + This parameter can be a value of @ref USART_Clock_Phase */ + + uint16_t USART_LastBit; /*!< Specifies whether the clock pulse corresponding to the last transmitted + data bit (MSB) has to be output on the SCLK pin in synchronous mode. + This parameter can be a value of @ref USART_Last_Bit */ +} USART_ClockInitTypeDef; + +/** + * @} + */ + +/** @defgroup USART_Exported_Constants + * @{ + */ + +#define IS_USART_ALL_PERIPH(PERIPH) (((PERIPH) == USART1) || \ + ((PERIPH) == USART2) || \ + ((PERIPH) == USART3) || \ + ((PERIPH) == UART4) || \ + ((PERIPH) == UART5)) + +#define IS_USART_123_PERIPH(PERIPH) (((PERIPH) == USART1) || \ + ((PERIPH) == USART2) || \ + ((PERIPH) == USART3)) + +#define IS_USART_1234_PERIPH(PERIPH) (((PERIPH) == USART1) || \ + ((PERIPH) == USART2) || \ + ((PERIPH) == USART3) || \ + ((PERIPH) == UART4)) +/** @defgroup USART_Word_Length + * @{ + */ + +#define USART_WordLength_8b ((uint16_t)0x0000) +#define USART_WordLength_9b ((uint16_t)0x1000) + +#define IS_USART_WORD_LENGTH(LENGTH) (((LENGTH) == USART_WordLength_8b) || \ + ((LENGTH) == USART_WordLength_9b)) +/** + * @} + */ + +/** @defgroup USART_Stop_Bits + * @{ + */ + +#define USART_StopBits_1 ((uint16_t)0x0000) +#define USART_StopBits_0_5 ((uint16_t)0x1000) +#define USART_StopBits_2 ((uint16_t)0x2000) +#define USART_StopBits_1_5 ((uint16_t)0x3000) +#define IS_USART_STOPBITS(STOPBITS) (((STOPBITS) == USART_StopBits_1) || \ + ((STOPBITS) == USART_StopBits_0_5) || \ + ((STOPBITS) == USART_StopBits_2) || \ + ((STOPBITS) == USART_StopBits_1_5)) +/** + * @} + */ + +/** @defgroup USART_Parity + * @{ + */ + +#define USART_Parity_No ((uint16_t)0x0000) +#define USART_Parity_Even ((uint16_t)0x0400) +#define USART_Parity_Odd ((uint16_t)0x0600) +#define IS_USART_PARITY(PARITY) (((PARITY) == USART_Parity_No) || \ + ((PARITY) == USART_Parity_Even) || \ + ((PARITY) == USART_Parity_Odd)) +/** + * @} + */ + +/** @defgroup USART_Mode + * @{ + */ + +#define USART_Mode_Rx ((uint16_t)0x0004) +#define USART_Mode_Tx ((uint16_t)0x0008) +#define IS_USART_MODE(MODE) ((((MODE) & (uint16_t)0xFFF3) == 0x00) && ((MODE) != (uint16_t)0x00)) +/** + * @} + */ + +/** @defgroup USART_Hardware_Flow_Control + * @{ + */ +#define USART_HardwareFlowControl_None ((uint16_t)0x0000) +#define USART_HardwareFlowControl_RTS ((uint16_t)0x0100) +#define USART_HardwareFlowControl_CTS ((uint16_t)0x0200) +#define USART_HardwareFlowControl_RTS_CTS ((uint16_t)0x0300) +#define IS_USART_HARDWARE_FLOW_CONTROL(CONTROL)\ + (((CONTROL) == USART_HardwareFlowControl_None) || \ + ((CONTROL) == USART_HardwareFlowControl_RTS) || \ + ((CONTROL) == USART_HardwareFlowControl_CTS) || \ + ((CONTROL) == USART_HardwareFlowControl_RTS_CTS)) +/** + * @} + */ + +/** @defgroup USART_Clock + * @{ + */ +#define USART_Clock_Disable ((uint16_t)0x0000) +#define USART_Clock_Enable ((uint16_t)0x0800) +#define IS_USART_CLOCK(CLOCK) (((CLOCK) == USART_Clock_Disable) || \ + ((CLOCK) == USART_Clock_Enable)) +/** + * @} + */ + +/** @defgroup USART_Clock_Polarity + * @{ + */ + +#define USART_CPOL_Low ((uint16_t)0x0000) +#define USART_CPOL_High ((uint16_t)0x0400) +#define IS_USART_CPOL(CPOL) (((CPOL) == USART_CPOL_Low) || ((CPOL) == USART_CPOL_High)) + +/** + * @} + */ + +/** @defgroup USART_Clock_Phase + * @{ + */ + +#define USART_CPHA_1Edge ((uint16_t)0x0000) +#define USART_CPHA_2Edge ((uint16_t)0x0200) +#define IS_USART_CPHA(CPHA) (((CPHA) == USART_CPHA_1Edge) || ((CPHA) == USART_CPHA_2Edge)) + +/** + * @} + */ + +/** @defgroup USART_Last_Bit + * @{ + */ + +#define USART_LastBit_Disable ((uint16_t)0x0000) +#define USART_LastBit_Enable ((uint16_t)0x0100) +#define IS_USART_LASTBIT(LASTBIT) (((LASTBIT) == USART_LastBit_Disable) || \ + ((LASTBIT) == USART_LastBit_Enable)) +/** + * @} + */ + +/** @defgroup USART_Interrupt_definition + * @{ + */ + +#define USART_IT_PE ((uint16_t)0x0028) +#define USART_IT_TXE ((uint16_t)0x0727) +#define USART_IT_TC ((uint16_t)0x0626) +#define USART_IT_RXNE ((uint16_t)0x0525) +#define USART_IT_ORE_RX ((uint16_t)0x0325) /* In case interrupt is generated if the RXNEIE bit is set */ +#define USART_IT_IDLE ((uint16_t)0x0424) +#define USART_IT_LBD ((uint16_t)0x0846) +#define USART_IT_CTS ((uint16_t)0x096A) +#define USART_IT_ERR ((uint16_t)0x0060) +#define USART_IT_ORE_ER ((uint16_t)0x0360) /* In case interrupt is generated if the EIE bit is set */ +#define USART_IT_NE ((uint16_t)0x0260) +#define USART_IT_FE ((uint16_t)0x0160) + +/** @defgroup USART_Legacy + * @{ + */ +#define USART_IT_ORE USART_IT_ORE_ER +/** + * @} + */ + +#define IS_USART_CONFIG_IT(IT) (((IT) == USART_IT_PE) || ((IT) == USART_IT_TXE) || \ + ((IT) == USART_IT_TC) || ((IT) == USART_IT_RXNE) || \ + ((IT) == USART_IT_IDLE) || ((IT) == USART_IT_LBD) || \ + ((IT) == USART_IT_CTS) || ((IT) == USART_IT_ERR)) + +#define IS_USART_GET_IT(IT) (((IT) == USART_IT_PE) || ((IT) == USART_IT_TXE) || \ + ((IT) == USART_IT_TC) || ((IT) == USART_IT_RXNE) || \ + ((IT) == USART_IT_IDLE) || ((IT) == USART_IT_LBD) || \ + ((IT) == USART_IT_CTS) || ((IT) == USART_IT_ORE) || \ + ((IT) == USART_IT_ORE_RX) || ((IT) == USART_IT_ORE_ER) || \ + ((IT) == USART_IT_NE) || ((IT) == USART_IT_FE)) + +#define IS_USART_CLEAR_IT(IT) (((IT) == USART_IT_TC) || ((IT) == USART_IT_RXNE) || \ + ((IT) == USART_IT_LBD) || ((IT) == USART_IT_CTS)) +/** + * @} + */ + +/** @defgroup USART_DMA_Requests + * @{ + */ + +#define USART_DMAReq_Tx ((uint16_t)0x0080) +#define USART_DMAReq_Rx ((uint16_t)0x0040) +#define IS_USART_DMAREQ(DMAREQ) ((((DMAREQ) & (uint16_t)0xFF3F) == 0x00) && ((DMAREQ) != (uint16_t)0x00)) + +/** + * @} + */ + +/** @defgroup USART_WakeUp_methods + * @{ + */ + +#define USART_WakeUp_IdleLine ((uint16_t)0x0000) +#define USART_WakeUp_AddressMark ((uint16_t)0x0800) +#define IS_USART_WAKEUP(WAKEUP) (((WAKEUP) == USART_WakeUp_IdleLine) || \ + ((WAKEUP) == USART_WakeUp_AddressMark)) +/** + * @} + */ + +/** @defgroup USART_LIN_Break_Detection_Length + * @{ + */ + +#define USART_LINBreakDetectLength_10b ((uint16_t)0x0000) +#define USART_LINBreakDetectLength_11b ((uint16_t)0x0020) +#define IS_USART_LIN_BREAK_DETECT_LENGTH(LENGTH) \ + (((LENGTH) == USART_LINBreakDetectLength_10b) || \ + ((LENGTH) == USART_LINBreakDetectLength_11b)) +/** + * @} + */ + +/** @defgroup USART_IrDA_Low_Power + * @{ + */ + +#define USART_IrDAMode_LowPower ((uint16_t)0x0004) +#define USART_IrDAMode_Normal ((uint16_t)0x0000) +#define IS_USART_IRDA_MODE(MODE) (((MODE) == USART_IrDAMode_LowPower) || \ + ((MODE) == USART_IrDAMode_Normal)) +/** + * @} + */ + +/** @defgroup USART_Flags + * @{ + */ + +#define USART_FLAG_CTS ((uint16_t)0x0200) +#define USART_FLAG_LBD ((uint16_t)0x0100) +#define USART_FLAG_TXE ((uint16_t)0x0080) +#define USART_FLAG_TC ((uint16_t)0x0040) +#define USART_FLAG_RXNE ((uint16_t)0x0020) +#define USART_FLAG_IDLE ((uint16_t)0x0010) +#define USART_FLAG_ORE ((uint16_t)0x0008) +#define USART_FLAG_NE ((uint16_t)0x0004) +#define USART_FLAG_FE ((uint16_t)0x0002) +#define USART_FLAG_PE ((uint16_t)0x0001) +#define IS_USART_FLAG(FLAG) (((FLAG) == USART_FLAG_PE) || ((FLAG) == USART_FLAG_TXE) || \ + ((FLAG) == USART_FLAG_TC) || ((FLAG) == USART_FLAG_RXNE) || \ + ((FLAG) == USART_FLAG_IDLE) || ((FLAG) == USART_FLAG_LBD) || \ + ((FLAG) == USART_FLAG_CTS) || ((FLAG) == USART_FLAG_ORE) || \ + ((FLAG) == USART_FLAG_NE) || ((FLAG) == USART_FLAG_FE)) + +#define IS_USART_CLEAR_FLAG(FLAG) ((((FLAG) & (uint16_t)0xFC9F) == 0x00) && ((FLAG) != (uint16_t)0x00)) + +#define IS_USART_BAUDRATE(BAUDRATE) (((BAUDRATE) > 0) && ((BAUDRATE) < 0x0044AA21)) +#define IS_USART_ADDRESS(ADDRESS) ((ADDRESS) <= 0xF) +#define IS_USART_DATA(DATA) ((DATA) <= 0x1FF) + +/** + * @} + */ + +/** + * @} + */ + +/** @defgroup USART_Exported_Macros + * @{ + */ + +/** + * @} + */ + +/** @defgroup USART_Exported_Functions + * @{ + */ + +void USART_DeInit(USART_TypeDef* USARTx); +void USART_Init(USART_TypeDef* USARTx, USART_InitTypeDef* USART_InitStruct); +void USART_StructInit(USART_InitTypeDef* USART_InitStruct); +void USART_ClockInit(USART_TypeDef* USARTx, USART_ClockInitTypeDef* USART_ClockInitStruct); +void USART_ClockStructInit(USART_ClockInitTypeDef* USART_ClockInitStruct); +void USART_Cmd(USART_TypeDef* USARTx, FunctionalState NewState); +void USART_ITConfig(USART_TypeDef* USARTx, uint16_t USART_IT, FunctionalState NewState); +void USART_DMACmd(USART_TypeDef* USARTx, uint16_t USART_DMAReq, FunctionalState NewState); +void USART_SetAddress(USART_TypeDef* USARTx, uint8_t USART_Address); +void USART_WakeUpConfig(USART_TypeDef* USARTx, uint16_t USART_WakeUp); +void USART_ReceiverWakeUpCmd(USART_TypeDef* USARTx, FunctionalState NewState); +void USART_LINBreakDetectLengthConfig(USART_TypeDef* USARTx, uint16_t USART_LINBreakDetectLength); +void USART_LINCmd(USART_TypeDef* USARTx, FunctionalState NewState); +void USART_SendData(USART_TypeDef* USARTx, uint16_t Data); +uint16_t USART_ReceiveData(USART_TypeDef* USARTx); +void USART_SendBreak(USART_TypeDef* USARTx); +void USART_SetGuardTime(USART_TypeDef* USARTx, uint8_t USART_GuardTime); +void USART_SetPrescaler(USART_TypeDef* USARTx, uint8_t USART_Prescaler); +void USART_SmartCardCmd(USART_TypeDef* USARTx, FunctionalState NewState); +void USART_SmartCardNACKCmd(USART_TypeDef* USARTx, FunctionalState NewState); +void USART_HalfDuplexCmd(USART_TypeDef* USARTx, FunctionalState NewState); +void USART_OverSampling8Cmd(USART_TypeDef* USARTx, FunctionalState NewState); +void USART_OneBitMethodCmd(USART_TypeDef* USARTx, FunctionalState NewState); +void USART_IrDAConfig(USART_TypeDef* USARTx, uint16_t USART_IrDAMode); +void USART_IrDACmd(USART_TypeDef* USARTx, FunctionalState NewState); +FlagStatus USART_GetFlagStatus(USART_TypeDef* USARTx, uint16_t USART_FLAG); +void USART_ClearFlag(USART_TypeDef* USARTx, uint16_t USART_FLAG); +ITStatus USART_GetITStatus(USART_TypeDef* USARTx, uint16_t USART_IT); +void USART_ClearITPendingBit(USART_TypeDef* USARTx, uint16_t USART_IT); + +#ifdef __cplusplus +} +#endif + +#endif /* __STM32F10x_USART_H */ +/** + * @} + */ + +/** + * @} + */ + +/** + * @} + */ + +/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ diff --git a/Libraries/STM32F10x_StdPeriph_Driver/inc/stm32f10x_wwdg.h b/Libraries/STM32F10x_StdPeriph_Driver/inc/stm32f10x_wwdg.h new file mode 100644 index 0000000..1ace8b2 --- /dev/null +++ b/Libraries/STM32F10x_StdPeriph_Driver/inc/stm32f10x_wwdg.h @@ -0,0 +1,121 @@ +/** + ****************************************************************************** + * @file stm32f10x_wwdg.h + * @author MCD Application Team + * @version V3.6.1 + * @date 05-March-2012 + * @brief This file contains all the functions prototypes for the WWDG firmware + * library. + ****************************************************************************** + * @attention + * + *

    © COPYRIGHT 2012 STMicroelectronics

    + * + * Licensed under MCD-ST Liberty SW License Agreement V2, (the "License"); + * You may not use this file except in compliance with the License. + * You may obtain a copy of the License at: + * + * http://www.st.com/software_license_agreement_liberty_v2 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, + * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + * + ****************************************************************************** + */ + +/* Define to prevent recursive inclusion -------------------------------------*/ +#ifndef __STM32F10x_WWDG_H +#define __STM32F10x_WWDG_H + +#ifdef __cplusplus + extern "C" { +#endif + +/* Includes ------------------------------------------------------------------*/ +#include "stm32f10x.h" + +/** @addtogroup STM32F10x_StdPeriph_Driver + * @{ + */ + +/** @addtogroup WWDG + * @{ + */ + +/** @defgroup WWDG_Exported_Types + * @{ + */ + +/** + * @} + */ + +/** @defgroup WWDG_Exported_Constants + * @{ + */ + +/** @defgroup WWDG_Prescaler + * @{ + */ + +#define WWDG_Prescaler_1 ((uint32_t)0x00000000) +#define WWDG_Prescaler_2 ((uint32_t)0x00000080) +#define WWDG_Prescaler_4 ((uint32_t)0x00000100) +#define WWDG_Prescaler_8 ((uint32_t)0x00000180) +#define IS_WWDG_PRESCALER(PRESCALER) (((PRESCALER) == WWDG_Prescaler_1) || \ + ((PRESCALER) == WWDG_Prescaler_2) || \ + ((PRESCALER) == WWDG_Prescaler_4) || \ + ((PRESCALER) == WWDG_Prescaler_8)) +#define IS_WWDG_WINDOW_VALUE(VALUE) ((VALUE) <= 0x7F) +#define IS_WWDG_COUNTER(COUNTER) (((COUNTER) >= 0x40) && ((COUNTER) <= 0x7F)) + +/** + * @} + */ + +/** + * @} + */ + +/** @defgroup WWDG_Exported_Macros + * @{ + */ +/** + * @} + */ + +/** @defgroup WWDG_Exported_Functions + * @{ + */ + +void WWDG_DeInit(void); +void WWDG_SetPrescaler(uint32_t WWDG_Prescaler); +void WWDG_SetWindowValue(uint8_t WindowValue); +void WWDG_EnableIT(void); +void WWDG_SetCounter(uint8_t Counter); +void WWDG_Enable(uint8_t Counter); +FlagStatus WWDG_GetFlagStatus(void); +void WWDG_ClearFlag(void); + +#ifdef __cplusplus +} +#endif + +#endif /* __STM32F10x_WWDG_H */ + +/** + * @} + */ + +/** + * @} + */ + +/** + * @} + */ + +/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ diff --git a/Libraries/STM32F10x_StdPeriph_Driver/src/misc.c b/Libraries/STM32F10x_StdPeriph_Driver/src/misc.c new file mode 100644 index 0000000..b252f35 --- /dev/null +++ b/Libraries/STM32F10x_StdPeriph_Driver/src/misc.c @@ -0,0 +1,231 @@ +/** + ****************************************************************************** + * @file misc.c + * @author MCD Application Team + * @version V3.6.1 + * @date 05-March-2012 + * @brief This file provides all the miscellaneous firmware functions (add-on + * to CMSIS functions). + ****************************************************************************** + * @attention + * + *

    © COPYRIGHT 2012 STMicroelectronics

    + * + * Licensed under MCD-ST Liberty SW License Agreement V2, (the "License"); + * You may not use this file except in compliance with the License. + * You may obtain a copy of the License at: + * + * http://www.st.com/software_license_agreement_liberty_v2 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, + * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + * + ****************************************************************************** + */ + +/* Includes ------------------------------------------------------------------*/ +#include "misc.h" + +/** @addtogroup STM32F10x_StdPeriph_Driver + * @{ + */ + +/** @defgroup MISC + * @brief MISC driver modules + * @{ + */ + +/** @defgroup MISC_Private_TypesDefinitions + * @{ + */ + +/** + * @} + */ + +/** @defgroup MISC_Private_Defines + * @{ + */ + +#define AIRCR_VECTKEY_MASK ((uint32_t)0x05FA0000) +/** + * @} + */ + +/** @defgroup MISC_Private_Macros + * @{ + */ + +/** + * @} + */ + +/** @defgroup MISC_Private_Variables + * @{ + */ + +/** + * @} + */ + +/** @defgroup MISC_Private_FunctionPrototypes + * @{ + */ + +/** + * @} + */ + +/** @defgroup MISC_Private_Functions + * @{ + */ + +/** + * @brief Configures the priority grouping: pre-emption priority and subpriority. + * @param NVIC_PriorityGroup: specifies the priority grouping bits length. + * This parameter can be one of the following values: + * @arg NVIC_PriorityGroup_0: 0 bits for pre-emption priority + * 4 bits for subpriority + * @arg NVIC_PriorityGroup_1: 1 bits for pre-emption priority + * 3 bits for subpriority + * @arg NVIC_PriorityGroup_2: 2 bits for pre-emption priority + * 2 bits for subpriority + * @arg NVIC_PriorityGroup_3: 3 bits for pre-emption priority + * 1 bits for subpriority + * @arg NVIC_PriorityGroup_4: 4 bits for pre-emption priority + * 0 bits for subpriority + * @retval None + */ +void NVIC_PriorityGroupConfig(uint32_t NVIC_PriorityGroup) +{ + /* Check the parameters */ + assert_param(IS_NVIC_PRIORITY_GROUP(NVIC_PriorityGroup)); + + /* Set the PRIGROUP[10:8] bits according to NVIC_PriorityGroup value */ + SCB->AIRCR = AIRCR_VECTKEY_MASK | NVIC_PriorityGroup; +} + +/** + * @brief Initializes the NVIC peripheral according to the specified + * parameters in the NVIC_InitStruct. + * @param NVIC_InitStruct: pointer to a NVIC_InitTypeDef structure that contains + * the configuration information for the specified NVIC peripheral. + * @retval None + */ +void NVIC_Init(NVIC_InitTypeDef* NVIC_InitStruct) +{ + uint32_t tmppriority = 0x00, tmppre = 0x00, tmpsub = 0x0F; + + /* Check the parameters */ + assert_param(IS_FUNCTIONAL_STATE(NVIC_InitStruct->NVIC_IRQChannelCmd)); + assert_param(IS_NVIC_PREEMPTION_PRIORITY(NVIC_InitStruct->NVIC_IRQChannelPreemptionPriority)); + assert_param(IS_NVIC_SUB_PRIORITY(NVIC_InitStruct->NVIC_IRQChannelSubPriority)); + + if (NVIC_InitStruct->NVIC_IRQChannelCmd != DISABLE) + { + /* Compute the Corresponding IRQ Priority --------------------------------*/ + tmppriority = (0x700 - ((SCB->AIRCR) & (uint32_t)0x700))>> 0x08; + tmppre = (0x4 - tmppriority); + tmpsub = tmpsub >> tmppriority; + + tmppriority = (uint32_t)NVIC_InitStruct->NVIC_IRQChannelPreemptionPriority << tmppre; + tmppriority |= NVIC_InitStruct->NVIC_IRQChannelSubPriority & tmpsub; + tmppriority = tmppriority << 0x04; + + NVIC->IP[NVIC_InitStruct->NVIC_IRQChannel] = tmppriority; + + /* Enable the Selected IRQ Channels --------------------------------------*/ + NVIC->ISER[NVIC_InitStruct->NVIC_IRQChannel >> 0x05] = + (uint32_t)0x01 << (NVIC_InitStruct->NVIC_IRQChannel & (uint8_t)0x1F); + } + else + { + /* Disable the Selected IRQ Channels -------------------------------------*/ + NVIC->ICER[NVIC_InitStruct->NVIC_IRQChannel >> 0x05] = + (uint32_t)0x01 << (NVIC_InitStruct->NVIC_IRQChannel & (uint8_t)0x1F); + } +} + +/** + * @brief Sets the vector table location and Offset. + * @param NVIC_VectTab: specifies if the vector table is in RAM or FLASH memory. + * This parameter can be one of the following values: + * @arg NVIC_VectTab_RAM + * @arg NVIC_VectTab_FLASH + * @param Offset: Vector Table base offset field. This value must be a multiple + * of 0x200. + * @retval None + */ +void NVIC_SetVectorTable(uint32_t NVIC_VectTab, uint32_t Offset) +{ + /* Check the parameters */ + assert_param(IS_NVIC_VECTTAB(NVIC_VectTab)); + assert_param(IS_NVIC_OFFSET(Offset)); + + SCB->VTOR = NVIC_VectTab | (Offset & (uint32_t)0x1FFFFF80); +} + +/** + * @brief Selects the condition for the system to enter low power mode. + * @param LowPowerMode: Specifies the new mode for the system to enter low power mode. + * This parameter can be one of the following values: + * @arg NVIC_LP_SEVONPEND + * @arg NVIC_LP_SLEEPDEEP + * @arg NVIC_LP_SLEEPONEXIT + * @param NewState: new state of LP condition. This parameter can be: ENABLE or DISABLE. + * @retval None + */ +void NVIC_SystemLPConfig(uint8_t LowPowerMode, FunctionalState NewState) +{ + /* Check the parameters */ + assert_param(IS_NVIC_LP(LowPowerMode)); + assert_param(IS_FUNCTIONAL_STATE(NewState)); + + if (NewState != DISABLE) + { + SCB->SCR |= LowPowerMode; + } + else + { + SCB->SCR &= (uint32_t)(~(uint32_t)LowPowerMode); + } +} + +/** + * @brief Configures the SysTick clock source. + * @param SysTick_CLKSource: specifies the SysTick clock source. + * This parameter can be one of the following values: + * @arg SysTick_CLKSource_HCLK_Div8: AHB clock divided by 8 selected as SysTick clock source. + * @arg SysTick_CLKSource_HCLK: AHB clock selected as SysTick clock source. + * @retval None + */ +void SysTick_CLKSourceConfig(uint32_t SysTick_CLKSource) +{ + /* Check the parameters */ + assert_param(IS_SYSTICK_CLK_SOURCE(SysTick_CLKSource)); + if (SysTick_CLKSource == SysTick_CLKSource_HCLK) + { + SysTick->CTRL |= SysTick_CLKSource_HCLK; + } + else + { + SysTick->CTRL &= SysTick_CLKSource_HCLK_Div8; + } +} + +/** + * @} + */ + +/** + * @} + */ + +/** + * @} + */ + +/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ diff --git a/Libraries/STM32F10x_StdPeriph_Driver/src/stm32f10x_adc.c b/Libraries/STM32F10x_StdPeriph_Driver/src/stm32f10x_adc.c new file mode 100644 index 0000000..51952c1 --- /dev/null +++ b/Libraries/STM32F10x_StdPeriph_Driver/src/stm32f10x_adc.c @@ -0,0 +1,1313 @@ +/** + ****************************************************************************** + * @file stm32f10x_adc.c + * @author MCD Application Team + * @version V3.6.1 + * @date 05-March-2012 + * @brief This file provides all the ADC firmware functions. + ****************************************************************************** + * @attention + * + *

    © COPYRIGHT 2012 STMicroelectronics

    + * + * Licensed under MCD-ST Liberty SW License Agreement V2, (the "License"); + * You may not use this file except in compliance with the License. + * You may obtain a copy of the License at: + * + * http://www.st.com/software_license_agreement_liberty_v2 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, + * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + * + ****************************************************************************** + */ + +/* Includes ------------------------------------------------------------------*/ +#include "stm32f10x_adc.h" +#include "stm32f10x_rcc.h" + +/** @addtogroup STM32F10x_StdPeriph_Driver + * @{ + */ + +/** @defgroup ADC + * @brief ADC driver modules + * @{ + */ + +/** @defgroup ADC_Private_TypesDefinitions + * @{ + */ + +/** + * @} + */ + +/** @defgroup ADC_Private_Defines + * @{ + */ + +/* ADC DISCNUM mask */ +#define CR1_DISCNUM_Reset ((uint32_t)0xFFFF1FFF) + +/* ADC DISCEN mask */ +#define CR1_DISCEN_Set ((uint32_t)0x00000800) +#define CR1_DISCEN_Reset ((uint32_t)0xFFFFF7FF) + +/* ADC JAUTO mask */ +#define CR1_JAUTO_Set ((uint32_t)0x00000400) +#define CR1_JAUTO_Reset ((uint32_t)0xFFFFFBFF) + +/* ADC JDISCEN mask */ +#define CR1_JDISCEN_Set ((uint32_t)0x00001000) +#define CR1_JDISCEN_Reset ((uint32_t)0xFFFFEFFF) + +/* ADC AWDCH mask */ +#define CR1_AWDCH_Reset ((uint32_t)0xFFFFFFE0) + +/* ADC Analog watchdog enable mode mask */ +#define CR1_AWDMode_Reset ((uint32_t)0xFF3FFDFF) + +/* CR1 register Mask */ +#define CR1_CLEAR_Mask ((uint32_t)0xFFF0FEFF) + +/* ADC ADON mask */ +#define CR2_ADON_Set ((uint32_t)0x00000001) +#define CR2_ADON_Reset ((uint32_t)0xFFFFFFFE) + +/* ADC DMA mask */ +#define CR2_DMA_Set ((uint32_t)0x00000100) +#define CR2_DMA_Reset ((uint32_t)0xFFFFFEFF) + +/* ADC RSTCAL mask */ +#define CR2_RSTCAL_Set ((uint32_t)0x00000008) + +/* ADC CAL mask */ +#define CR2_CAL_Set ((uint32_t)0x00000004) + +/* ADC SWSTART mask */ +#define CR2_SWSTART_Set ((uint32_t)0x00400000) + +/* ADC EXTTRIG mask */ +#define CR2_EXTTRIG_Set ((uint32_t)0x00100000) +#define CR2_EXTTRIG_Reset ((uint32_t)0xFFEFFFFF) + +/* ADC Software start mask */ +#define CR2_EXTTRIG_SWSTART_Set ((uint32_t)0x00500000) +#define CR2_EXTTRIG_SWSTART_Reset ((uint32_t)0xFFAFFFFF) + +/* ADC JEXTSEL mask */ +#define CR2_JEXTSEL_Reset ((uint32_t)0xFFFF8FFF) + +/* ADC JEXTTRIG mask */ +#define CR2_JEXTTRIG_Set ((uint32_t)0x00008000) +#define CR2_JEXTTRIG_Reset ((uint32_t)0xFFFF7FFF) + +/* ADC JSWSTART mask */ +#define CR2_JSWSTART_Set ((uint32_t)0x00200000) + +/* ADC injected software start mask */ +#define CR2_JEXTTRIG_JSWSTART_Set ((uint32_t)0x00208000) +#define CR2_JEXTTRIG_JSWSTART_Reset ((uint32_t)0xFFDF7FFF) + +/* ADC TSPD mask */ +#define CR2_TSVREFE_Set ((uint32_t)0x00800000) +#define CR2_TSVREFE_Reset ((uint32_t)0xFF7FFFFF) + +/* CR2 register Mask */ +#define CR2_CLEAR_Mask ((uint32_t)0xFFF1F7FD) + +/* ADC SQx mask */ +#define SQR3_SQ_Set ((uint32_t)0x0000001F) +#define SQR2_SQ_Set ((uint32_t)0x0000001F) +#define SQR1_SQ_Set ((uint32_t)0x0000001F) + +/* SQR1 register Mask */ +#define SQR1_CLEAR_Mask ((uint32_t)0xFF0FFFFF) + +/* ADC JSQx mask */ +#define JSQR_JSQ_Set ((uint32_t)0x0000001F) + +/* ADC JL mask */ +#define JSQR_JL_Set ((uint32_t)0x00300000) +#define JSQR_JL_Reset ((uint32_t)0xFFCFFFFF) + +/* ADC SMPx mask */ +#define SMPR1_SMP_Set ((uint32_t)0x00000007) +#define SMPR2_SMP_Set ((uint32_t)0x00000007) + +/* ADC JDRx registers offset */ +#define JDR_Offset ((uint8_t)0x28) + +/* ADC1 DR register base address */ +#define DR_ADDRESS ((uint32_t)0x4001244C) + +/** + * @} + */ + +/** @defgroup ADC_Private_Macros + * @{ + */ + +/** + * @} + */ + +/** @defgroup ADC_Private_Variables + * @{ + */ + +/** + * @} + */ + +/** @defgroup ADC_Private_FunctionPrototypes + * @{ + */ + +/** + * @} + */ + +/** @defgroup ADC_Private_Functions + * @{ + */ + +/** + * @brief Deinitializes the ADCx peripheral registers to their default reset values. + * @param ADCx: where x can be 1, 2 or 3 to select the ADC peripheral. + * @retval None + */ +void ADC_DeInit(ADC_TypeDef* ADCx) +{ + /* Check the parameters */ + assert_param(IS_ADC_ALL_PERIPH(ADCx)); + + if (ADCx == ADC1) + { + /* Enable ADC1 reset state */ + RCC_APB2PeriphResetCmd(RCC_APB2Periph_ADC1, ENABLE); + /* Release ADC1 from reset state */ + RCC_APB2PeriphResetCmd(RCC_APB2Periph_ADC1, DISABLE); + } + else if (ADCx == ADC2) + { + /* Enable ADC2 reset state */ + RCC_APB2PeriphResetCmd(RCC_APB2Periph_ADC2, ENABLE); + /* Release ADC2 from reset state */ + RCC_APB2PeriphResetCmd(RCC_APB2Periph_ADC2, DISABLE); + } + else + { + if (ADCx == ADC3) + { + /* Enable ADC3 reset state */ + RCC_APB2PeriphResetCmd(RCC_APB2Periph_ADC3, ENABLE); + /* Release ADC3 from reset state */ + RCC_APB2PeriphResetCmd(RCC_APB2Periph_ADC3, DISABLE); + } + } +} + +/** + * @brief Initializes the ADCx peripheral according to the specified parameters + * in the ADC_InitStruct. + * @param ADCx: where x can be 1, 2 or 3 to select the ADC peripheral. + * @param ADC_InitStruct: pointer to an ADC_InitTypeDef structure that contains + * the configuration information for the specified ADC peripheral. + * @retval None + */ +void ADC_Init(ADC_TypeDef* ADCx, ADC_InitTypeDef* ADC_InitStruct) +{ + uint32_t tmpreg1 = 0; + uint8_t tmpreg2 = 0; + /* Check the parameters */ + assert_param(IS_ADC_ALL_PERIPH(ADCx)); + assert_param(IS_ADC_MODE(ADC_InitStruct->ADC_Mode)); + assert_param(IS_FUNCTIONAL_STATE(ADC_InitStruct->ADC_ScanConvMode)); + assert_param(IS_FUNCTIONAL_STATE(ADC_InitStruct->ADC_ContinuousConvMode)); + assert_param(IS_ADC_EXT_TRIG(ADC_InitStruct->ADC_ExternalTrigConv)); + assert_param(IS_ADC_DATA_ALIGN(ADC_InitStruct->ADC_DataAlign)); + assert_param(IS_ADC_REGULAR_LENGTH(ADC_InitStruct->ADC_NbrOfChannel)); + + /*---------------------------- ADCx CR1 Configuration -----------------*/ + /* Get the ADCx CR1 value */ + tmpreg1 = ADCx->CR1; + /* Clear DUALMOD and SCAN bits */ + tmpreg1 &= CR1_CLEAR_Mask; + /* Configure ADCx: Dual mode and scan conversion mode */ + /* Set DUALMOD bits according to ADC_Mode value */ + /* Set SCAN bit according to ADC_ScanConvMode value */ + tmpreg1 |= (uint32_t)(ADC_InitStruct->ADC_Mode | ((uint32_t)ADC_InitStruct->ADC_ScanConvMode << 8)); + /* Write to ADCx CR1 */ + ADCx->CR1 = tmpreg1; + + /*---------------------------- ADCx CR2 Configuration -----------------*/ + /* Get the ADCx CR2 value */ + tmpreg1 = ADCx->CR2; + /* Clear CONT, ALIGN and EXTSEL bits */ + tmpreg1 &= CR2_CLEAR_Mask; + /* Configure ADCx: external trigger event and continuous conversion mode */ + /* Set ALIGN bit according to ADC_DataAlign value */ + /* Set EXTSEL bits according to ADC_ExternalTrigConv value */ + /* Set CONT bit according to ADC_ContinuousConvMode value */ + tmpreg1 |= (uint32_t)(ADC_InitStruct->ADC_DataAlign | ADC_InitStruct->ADC_ExternalTrigConv | + ((uint32_t)ADC_InitStruct->ADC_ContinuousConvMode << 1)); + /* Write to ADCx CR2 */ + ADCx->CR2 = tmpreg1; + + /*---------------------------- ADCx SQR1 Configuration -----------------*/ + /* Get the ADCx SQR1 value */ + tmpreg1 = ADCx->SQR1; + /* Clear L bits */ + tmpreg1 &= SQR1_CLEAR_Mask; + /* Configure ADCx: regular channel sequence length */ + /* Set L bits according to ADC_NbrOfChannel value */ + tmpreg2 |= (uint8_t) (ADC_InitStruct->ADC_NbrOfChannel - (uint8_t)1); + tmpreg1 |= (uint32_t)tmpreg2 << 20; + /* Write to ADCx SQR1 */ + ADCx->SQR1 = tmpreg1; +} + +/** + * @brief Fills each ADC_InitStruct member with its default value. + * @param ADC_InitStruct : pointer to an ADC_InitTypeDef structure which will be initialized. + * @retval None + */ +void ADC_StructInit(ADC_InitTypeDef* ADC_InitStruct) +{ + /* Reset ADC init structure parameters values */ + /* Initialize the ADC_Mode member */ + ADC_InitStruct->ADC_Mode = ADC_Mode_Independent; + /* initialize the ADC_ScanConvMode member */ + ADC_InitStruct->ADC_ScanConvMode = DISABLE; + /* Initialize the ADC_ContinuousConvMode member */ + ADC_InitStruct->ADC_ContinuousConvMode = DISABLE; + /* Initialize the ADC_ExternalTrigConv member */ + ADC_InitStruct->ADC_ExternalTrigConv = ADC_ExternalTrigConv_T1_CC1; + /* Initialize the ADC_DataAlign member */ + ADC_InitStruct->ADC_DataAlign = ADC_DataAlign_Right; + /* Initialize the ADC_NbrOfChannel member */ + ADC_InitStruct->ADC_NbrOfChannel = 1; +} + +/** + * @brief Enables or disables the specified ADC peripheral. + * @param ADCx: where x can be 1, 2 or 3 to select the ADC peripheral. + * @param NewState: new state of the ADCx peripheral. + * This parameter can be: ENABLE or DISABLE. + * @retval None + */ +void ADC_Cmd(ADC_TypeDef* ADCx, FunctionalState NewState) +{ + /* Check the parameters */ + assert_param(IS_ADC_ALL_PERIPH(ADCx)); + assert_param(IS_FUNCTIONAL_STATE(NewState)); + if (NewState != DISABLE) + { + /* Set the ADON bit to wake up the ADC from power down mode */ + ADCx->CR2 |= CR2_ADON_Set; + } + else + { + /* Disable the selected ADC peripheral */ + ADCx->CR2 &= CR2_ADON_Reset; + } +} + +/** + * @brief Enables or disables the specified ADC DMA request. + * @param ADCx: where x can be 1 or 3 to select the ADC peripheral. + * Note: ADC2 hasn't a DMA capability. + * @param NewState: new state of the selected ADC DMA transfer. + * This parameter can be: ENABLE or DISABLE. + * @retval None + */ +void ADC_DMACmd(ADC_TypeDef* ADCx, FunctionalState NewState) +{ + /* Check the parameters */ + assert_param(IS_ADC_DMA_PERIPH(ADCx)); + assert_param(IS_FUNCTIONAL_STATE(NewState)); + if (NewState != DISABLE) + { + /* Enable the selected ADC DMA request */ + ADCx->CR2 |= CR2_DMA_Set; + } + else + { + /* Disable the selected ADC DMA request */ + ADCx->CR2 &= CR2_DMA_Reset; + } +} + +/** + * @brief Enables or disables the specified ADC interrupts. + * @param ADCx: where x can be 1, 2 or 3 to select the ADC peripheral. + * @param ADC_IT: specifies the ADC interrupt sources to be enabled or disabled. + * This parameter can be any combination of the following values: + * @arg ADC_IT_EOC: End of conversion interrupt mask + * @arg ADC_IT_AWD: Analog watchdog interrupt mask + * @arg ADC_IT_JEOC: End of injected conversion interrupt mask + * @param NewState: new state of the specified ADC interrupts. + * This parameter can be: ENABLE or DISABLE. + * @retval None + */ +void ADC_ITConfig(ADC_TypeDef* ADCx, uint16_t ADC_IT, FunctionalState NewState) +{ + uint8_t itmask = 0; + /* Check the parameters */ + assert_param(IS_ADC_ALL_PERIPH(ADCx)); + assert_param(IS_FUNCTIONAL_STATE(NewState)); + assert_param(IS_ADC_IT(ADC_IT)); + /* Get the ADC IT index */ + itmask = (uint8_t)ADC_IT; + if (NewState != DISABLE) + { + /* Enable the selected ADC interrupts */ + ADCx->CR1 |= itmask; + } + else + { + /* Disable the selected ADC interrupts */ + ADCx->CR1 &= (~(uint32_t)itmask); + } +} + +/** + * @brief Resets the selected ADC calibration registers. + * @param ADCx: where x can be 1, 2 or 3 to select the ADC peripheral. + * @retval None + */ +void ADC_ResetCalibration(ADC_TypeDef* ADCx) +{ + /* Check the parameters */ + assert_param(IS_ADC_ALL_PERIPH(ADCx)); + /* Resets the selected ADC calibration registers */ + ADCx->CR2 |= CR2_RSTCAL_Set; +} + +/** + * @brief Gets the selected ADC reset calibration registers status. + * @param ADCx: where x can be 1, 2 or 3 to select the ADC peripheral. + * @retval The new state of ADC reset calibration registers (SET or RESET). + */ +FlagStatus ADC_GetResetCalibrationStatus(ADC_TypeDef* ADCx) +{ + FlagStatus bitstatus = RESET; + /* Check the parameters */ + assert_param(IS_ADC_ALL_PERIPH(ADCx)); + /* Check the status of RSTCAL bit */ + if ((ADCx->CR2 & CR2_RSTCAL_Set) != (uint32_t)RESET) + { + /* RSTCAL bit is set */ + bitstatus = SET; + } + else + { + /* RSTCAL bit is reset */ + bitstatus = RESET; + } + /* Return the RSTCAL bit status */ + return bitstatus; +} + +/** + * @brief Starts the selected ADC calibration process. + * @param ADCx: where x can be 1, 2 or 3 to select the ADC peripheral. + * @retval None + */ +void ADC_StartCalibration(ADC_TypeDef* ADCx) +{ + /* Check the parameters */ + assert_param(IS_ADC_ALL_PERIPH(ADCx)); + /* Enable the selected ADC calibration process */ + ADCx->CR2 |= CR2_CAL_Set; +} + +/** + * @brief Gets the selected ADC calibration status. + * @param ADCx: where x can be 1, 2 or 3 to select the ADC peripheral. + * @retval The new state of ADC calibration (SET or RESET). + */ +FlagStatus ADC_GetCalibrationStatus(ADC_TypeDef* ADCx) +{ + FlagStatus bitstatus = RESET; + /* Check the parameters */ + assert_param(IS_ADC_ALL_PERIPH(ADCx)); + /* Check the status of CAL bit */ + if ((ADCx->CR2 & CR2_CAL_Set) != (uint32_t)RESET) + { + /* CAL bit is set: calibration on going */ + bitstatus = SET; + } + else + { + /* CAL bit is reset: end of calibration */ + bitstatus = RESET; + } + /* Return the CAL bit status */ + return bitstatus; +} + +/** + * @brief Enables or disables the selected ADC software start conversion . + * @param ADCx: where x can be 1, 2 or 3 to select the ADC peripheral. + * @param NewState: new state of the selected ADC software start conversion. + * This parameter can be: ENABLE or DISABLE. + * @retval None + */ +void ADC_SoftwareStartConvCmd(ADC_TypeDef* ADCx, FunctionalState NewState) +{ + /* Check the parameters */ + assert_param(IS_ADC_ALL_PERIPH(ADCx)); + assert_param(IS_FUNCTIONAL_STATE(NewState)); + if (NewState != DISABLE) + { + /* Enable the selected ADC conversion on external event and start the selected + ADC conversion */ + ADCx->CR2 |= CR2_EXTTRIG_SWSTART_Set; + } + else + { + /* Disable the selected ADC conversion on external event and stop the selected + ADC conversion */ + ADCx->CR2 &= CR2_EXTTRIG_SWSTART_Reset; + } +} + +/** + * @brief Gets the selected ADC Software start conversion Status. + * @param ADCx: where x can be 1, 2 or 3 to select the ADC peripheral. + * @retval The new state of ADC software start conversion (SET or RESET). + */ +FlagStatus ADC_GetSoftwareStartConvStatus(ADC_TypeDef* ADCx) +{ + FlagStatus bitstatus = RESET; + /* Check the parameters */ + assert_param(IS_ADC_ALL_PERIPH(ADCx)); + /* Check the status of SWSTART bit */ + if ((ADCx->CR2 & CR2_SWSTART_Set) != (uint32_t)RESET) + { + /* SWSTART bit is set */ + bitstatus = SET; + } + else + { + /* SWSTART bit is reset */ + bitstatus = RESET; + } + /* Return the SWSTART bit status */ + return bitstatus; +} + +/** + * @brief Configures the discontinuous mode for the selected ADC regular + * group channel. + * @param ADCx: where x can be 1, 2 or 3 to select the ADC peripheral. + * @param Number: specifies the discontinuous mode regular channel + * count value. This number must be between 1 and 8. + * @retval None + */ +void ADC_DiscModeChannelCountConfig(ADC_TypeDef* ADCx, uint8_t Number) +{ + uint32_t tmpreg1 = 0; + uint32_t tmpreg2 = 0; + /* Check the parameters */ + assert_param(IS_ADC_ALL_PERIPH(ADCx)); + assert_param(IS_ADC_REGULAR_DISC_NUMBER(Number)); + /* Get the old register value */ + tmpreg1 = ADCx->CR1; + /* Clear the old discontinuous mode channel count */ + tmpreg1 &= CR1_DISCNUM_Reset; + /* Set the discontinuous mode channel count */ + tmpreg2 = Number - 1; + tmpreg1 |= tmpreg2 << 13; + /* Store the new register value */ + ADCx->CR1 = tmpreg1; +} + +/** + * @brief Enables or disables the discontinuous mode on regular group + * channel for the specified ADC + * @param ADCx: where x can be 1, 2 or 3 to select the ADC peripheral. + * @param NewState: new state of the selected ADC discontinuous mode + * on regular group channel. + * This parameter can be: ENABLE or DISABLE. + * @retval None + */ +void ADC_DiscModeCmd(ADC_TypeDef* ADCx, FunctionalState NewState) +{ + /* Check the parameters */ + assert_param(IS_ADC_ALL_PERIPH(ADCx)); + assert_param(IS_FUNCTIONAL_STATE(NewState)); + if (NewState != DISABLE) + { + /* Enable the selected ADC regular discontinuous mode */ + ADCx->CR1 |= CR1_DISCEN_Set; + } + else + { + /* Disable the selected ADC regular discontinuous mode */ + ADCx->CR1 &= CR1_DISCEN_Reset; + } +} + +/** + * @brief Configures for the selected ADC regular channel its corresponding + * rank in the sequencer and its sample time. + * @param ADCx: where x can be 1, 2 or 3 to select the ADC peripheral. + * @param ADC_Channel: the ADC channel to configure. + * This parameter can be one of the following values: + * @arg ADC_Channel_0: ADC Channel0 selected + * @arg ADC_Channel_1: ADC Channel1 selected + * @arg ADC_Channel_2: ADC Channel2 selected + * @arg ADC_Channel_3: ADC Channel3 selected + * @arg ADC_Channel_4: ADC Channel4 selected + * @arg ADC_Channel_5: ADC Channel5 selected + * @arg ADC_Channel_6: ADC Channel6 selected + * @arg ADC_Channel_7: ADC Channel7 selected + * @arg ADC_Channel_8: ADC Channel8 selected + * @arg ADC_Channel_9: ADC Channel9 selected + * @arg ADC_Channel_10: ADC Channel10 selected + * @arg ADC_Channel_11: ADC Channel11 selected + * @arg ADC_Channel_12: ADC Channel12 selected + * @arg ADC_Channel_13: ADC Channel13 selected + * @arg ADC_Channel_14: ADC Channel14 selected + * @arg ADC_Channel_15: ADC Channel15 selected + * @arg ADC_Channel_16: ADC Channel16 selected + * @arg ADC_Channel_17: ADC Channel17 selected + * @param Rank: The rank in the regular group sequencer. This parameter must be between 1 to 16. + * @param ADC_SampleTime: The sample time value to be set for the selected channel. + * This parameter can be one of the following values: + * @arg ADC_SampleTime_1Cycles5: Sample time equal to 1.5 cycles + * @arg ADC_SampleTime_7Cycles5: Sample time equal to 7.5 cycles + * @arg ADC_SampleTime_13Cycles5: Sample time equal to 13.5 cycles + * @arg ADC_SampleTime_28Cycles5: Sample time equal to 28.5 cycles + * @arg ADC_SampleTime_41Cycles5: Sample time equal to 41.5 cycles + * @arg ADC_SampleTime_55Cycles5: Sample time equal to 55.5 cycles + * @arg ADC_SampleTime_71Cycles5: Sample time equal to 71.5 cycles + * @arg ADC_SampleTime_239Cycles5: Sample time equal to 239.5 cycles + * @retval None + */ +void ADC_RegularChannelConfig(ADC_TypeDef* ADCx, uint8_t ADC_Channel, uint8_t Rank, uint8_t ADC_SampleTime) +{ + uint32_t tmpreg1 = 0, tmpreg2 = 0; + /* Check the parameters */ + assert_param(IS_ADC_ALL_PERIPH(ADCx)); + assert_param(IS_ADC_CHANNEL(ADC_Channel)); + assert_param(IS_ADC_REGULAR_RANK(Rank)); + assert_param(IS_ADC_SAMPLE_TIME(ADC_SampleTime)); + /* if ADC_Channel_10 ... ADC_Channel_17 is selected */ + if (ADC_Channel > ADC_Channel_9) + { + /* Get the old register value */ + tmpreg1 = ADCx->SMPR1; + /* Calculate the mask to clear */ + tmpreg2 = SMPR1_SMP_Set << (3 * (ADC_Channel - 10)); + /* Clear the old channel sample time */ + tmpreg1 &= ~tmpreg2; + /* Calculate the mask to set */ + tmpreg2 = (uint32_t)ADC_SampleTime << (3 * (ADC_Channel - 10)); + /* Set the new channel sample time */ + tmpreg1 |= tmpreg2; + /* Store the new register value */ + ADCx->SMPR1 = tmpreg1; + } + else /* ADC_Channel include in ADC_Channel_[0..9] */ + { + /* Get the old register value */ + tmpreg1 = ADCx->SMPR2; + /* Calculate the mask to clear */ + tmpreg2 = SMPR2_SMP_Set << (3 * ADC_Channel); + /* Clear the old channel sample time */ + tmpreg1 &= ~tmpreg2; + /* Calculate the mask to set */ + tmpreg2 = (uint32_t)ADC_SampleTime << (3 * ADC_Channel); + /* Set the new channel sample time */ + tmpreg1 |= tmpreg2; + /* Store the new register value */ + ADCx->SMPR2 = tmpreg1; + } + /* For Rank 1 to 6 */ + if (Rank < 7) + { + /* Get the old register value */ + tmpreg1 = ADCx->SQR3; + /* Calculate the mask to clear */ + tmpreg2 = SQR3_SQ_Set << (5 * (Rank - 1)); + /* Clear the old SQx bits for the selected rank */ + tmpreg1 &= ~tmpreg2; + /* Calculate the mask to set */ + tmpreg2 = (uint32_t)ADC_Channel << (5 * (Rank - 1)); + /* Set the SQx bits for the selected rank */ + tmpreg1 |= tmpreg2; + /* Store the new register value */ + ADCx->SQR3 = tmpreg1; + } + /* For Rank 7 to 12 */ + else if (Rank < 13) + { + /* Get the old register value */ + tmpreg1 = ADCx->SQR2; + /* Calculate the mask to clear */ + tmpreg2 = SQR2_SQ_Set << (5 * (Rank - 7)); + /* Clear the old SQx bits for the selected rank */ + tmpreg1 &= ~tmpreg2; + /* Calculate the mask to set */ + tmpreg2 = (uint32_t)ADC_Channel << (5 * (Rank - 7)); + /* Set the SQx bits for the selected rank */ + tmpreg1 |= tmpreg2; + /* Store the new register value */ + ADCx->SQR2 = tmpreg1; + } + /* For Rank 13 to 16 */ + else + { + /* Get the old register value */ + tmpreg1 = ADCx->SQR1; + /* Calculate the mask to clear */ + tmpreg2 = SQR1_SQ_Set << (5 * (Rank - 13)); + /* Clear the old SQx bits for the selected rank */ + tmpreg1 &= ~tmpreg2; + /* Calculate the mask to set */ + tmpreg2 = (uint32_t)ADC_Channel << (5 * (Rank - 13)); + /* Set the SQx bits for the selected rank */ + tmpreg1 |= tmpreg2; + /* Store the new register value */ + ADCx->SQR1 = tmpreg1; + } +} + +/** + * @brief Enables or disables the ADCx conversion through external trigger. + * @param ADCx: where x can be 1, 2 or 3 to select the ADC peripheral. + * @param NewState: new state of the selected ADC external trigger start of conversion. + * This parameter can be: ENABLE or DISABLE. + * @retval None + */ +void ADC_ExternalTrigConvCmd(ADC_TypeDef* ADCx, FunctionalState NewState) +{ + /* Check the parameters */ + assert_param(IS_ADC_ALL_PERIPH(ADCx)); + assert_param(IS_FUNCTIONAL_STATE(NewState)); + if (NewState != DISABLE) + { + /* Enable the selected ADC conversion on external event */ + ADCx->CR2 |= CR2_EXTTRIG_Set; + } + else + { + /* Disable the selected ADC conversion on external event */ + ADCx->CR2 &= CR2_EXTTRIG_Reset; + } +} + +/** + * @brief Returns the last ADCx conversion result data for regular channel. + * @param ADCx: where x can be 1, 2 or 3 to select the ADC peripheral. + * @retval The Data conversion value. + */ +uint16_t ADC_GetConversionValue(ADC_TypeDef* ADCx) +{ + /* Check the parameters */ + assert_param(IS_ADC_ALL_PERIPH(ADCx)); + /* Return the selected ADC conversion value */ + return (uint16_t) ADCx->DR; +} + +/** + * @brief Returns the last ADC1 and ADC2 conversion result data in dual mode. + * @retval The Data conversion value. + */ +uint32_t ADC_GetDualModeConversionValue(void) +{ + /* Return the dual mode conversion value */ + return (*(__IO uint32_t *) DR_ADDRESS); +} + +/** + * @brief Enables or disables the selected ADC automatic injected group + * conversion after regular one. + * @param ADCx: where x can be 1, 2 or 3 to select the ADC peripheral. + * @param NewState: new state of the selected ADC auto injected conversion + * This parameter can be: ENABLE or DISABLE. + * @retval None + */ +void ADC_AutoInjectedConvCmd(ADC_TypeDef* ADCx, FunctionalState NewState) +{ + /* Check the parameters */ + assert_param(IS_ADC_ALL_PERIPH(ADCx)); + assert_param(IS_FUNCTIONAL_STATE(NewState)); + if (NewState != DISABLE) + { + /* Enable the selected ADC automatic injected group conversion */ + ADCx->CR1 |= CR1_JAUTO_Set; + } + else + { + /* Disable the selected ADC automatic injected group conversion */ + ADCx->CR1 &= CR1_JAUTO_Reset; + } +} + +/** + * @brief Enables or disables the discontinuous mode for injected group + * channel for the specified ADC + * @param ADCx: where x can be 1, 2 or 3 to select the ADC peripheral. + * @param NewState: new state of the selected ADC discontinuous mode + * on injected group channel. + * This parameter can be: ENABLE or DISABLE. + * @retval None + */ +void ADC_InjectedDiscModeCmd(ADC_TypeDef* ADCx, FunctionalState NewState) +{ + /* Check the parameters */ + assert_param(IS_ADC_ALL_PERIPH(ADCx)); + assert_param(IS_FUNCTIONAL_STATE(NewState)); + if (NewState != DISABLE) + { + /* Enable the selected ADC injected discontinuous mode */ + ADCx->CR1 |= CR1_JDISCEN_Set; + } + else + { + /* Disable the selected ADC injected discontinuous mode */ + ADCx->CR1 &= CR1_JDISCEN_Reset; + } +} + +/** + * @brief Configures the ADCx external trigger for injected channels conversion. + * @param ADCx: where x can be 1, 2 or 3 to select the ADC peripheral. + * @param ADC_ExternalTrigInjecConv: specifies the ADC trigger to start injected conversion. + * This parameter can be one of the following values: + * @arg ADC_ExternalTrigInjecConv_T1_TRGO: Timer1 TRGO event selected (for ADC1, ADC2 and ADC3) + * @arg ADC_ExternalTrigInjecConv_T1_CC4: Timer1 capture compare4 selected (for ADC1, ADC2 and ADC3) + * @arg ADC_ExternalTrigInjecConv_T2_TRGO: Timer2 TRGO event selected (for ADC1 and ADC2) + * @arg ADC_ExternalTrigInjecConv_T2_CC1: Timer2 capture compare1 selected (for ADC1 and ADC2) + * @arg ADC_ExternalTrigInjecConv_T3_CC4: Timer3 capture compare4 selected (for ADC1 and ADC2) + * @arg ADC_ExternalTrigInjecConv_T4_TRGO: Timer4 TRGO event selected (for ADC1 and ADC2) + * @arg ADC_ExternalTrigInjecConv_Ext_IT15_TIM8_CC4: External interrupt line 15 or Timer8 + * capture compare4 event selected (for ADC1 and ADC2) + * @arg ADC_ExternalTrigInjecConv_T4_CC3: Timer4 capture compare3 selected (for ADC3 only) + * @arg ADC_ExternalTrigInjecConv_T8_CC2: Timer8 capture compare2 selected (for ADC3 only) + * @arg ADC_ExternalTrigInjecConv_T8_CC4: Timer8 capture compare4 selected (for ADC3 only) + * @arg ADC_ExternalTrigInjecConv_T5_TRGO: Timer5 TRGO event selected (for ADC3 only) + * @arg ADC_ExternalTrigInjecConv_T5_CC4: Timer5 capture compare4 selected (for ADC3 only) + * @arg ADC_ExternalTrigInjecConv_None: Injected conversion started by software and not + * by external trigger (for ADC1, ADC2 and ADC3) + * @retval None + */ +void ADC_ExternalTrigInjectedConvConfig(ADC_TypeDef* ADCx, uint32_t ADC_ExternalTrigInjecConv) +{ + uint32_t tmpreg = 0; + /* Check the parameters */ + assert_param(IS_ADC_ALL_PERIPH(ADCx)); + assert_param(IS_ADC_EXT_INJEC_TRIG(ADC_ExternalTrigInjecConv)); + /* Get the old register value */ + tmpreg = ADCx->CR2; + /* Clear the old external event selection for injected group */ + tmpreg &= CR2_JEXTSEL_Reset; + /* Set the external event selection for injected group */ + tmpreg |= ADC_ExternalTrigInjecConv; + /* Store the new register value */ + ADCx->CR2 = tmpreg; +} + +/** + * @brief Enables or disables the ADCx injected channels conversion through + * external trigger + * @param ADCx: where x can be 1, 2 or 3 to select the ADC peripheral. + * @param NewState: new state of the selected ADC external trigger start of + * injected conversion. + * This parameter can be: ENABLE or DISABLE. + * @retval None + */ +void ADC_ExternalTrigInjectedConvCmd(ADC_TypeDef* ADCx, FunctionalState NewState) +{ + /* Check the parameters */ + assert_param(IS_ADC_ALL_PERIPH(ADCx)); + assert_param(IS_FUNCTIONAL_STATE(NewState)); + if (NewState != DISABLE) + { + /* Enable the selected ADC external event selection for injected group */ + ADCx->CR2 |= CR2_JEXTTRIG_Set; + } + else + { + /* Disable the selected ADC external event selection for injected group */ + ADCx->CR2 &= CR2_JEXTTRIG_Reset; + } +} + +/** + * @brief Enables or disables the selected ADC start of the injected + * channels conversion. + * @param ADCx: where x can be 1, 2 or 3 to select the ADC peripheral. + * @param NewState: new state of the selected ADC software start injected conversion. + * This parameter can be: ENABLE or DISABLE. + * @retval None + */ +void ADC_SoftwareStartInjectedConvCmd(ADC_TypeDef* ADCx, FunctionalState NewState) +{ + /* Check the parameters */ + assert_param(IS_ADC_ALL_PERIPH(ADCx)); + assert_param(IS_FUNCTIONAL_STATE(NewState)); + if (NewState != DISABLE) + { + /* Enable the selected ADC conversion for injected group on external event and start the selected + ADC injected conversion */ + ADCx->CR2 |= CR2_JEXTTRIG_JSWSTART_Set; + } + else + { + /* Disable the selected ADC conversion on external event for injected group and stop the selected + ADC injected conversion */ + ADCx->CR2 &= CR2_JEXTTRIG_JSWSTART_Reset; + } +} + +/** + * @brief Gets the selected ADC Software start injected conversion Status. + * @param ADCx: where x can be 1, 2 or 3 to select the ADC peripheral. + * @retval The new state of ADC software start injected conversion (SET or RESET). + */ +FlagStatus ADC_GetSoftwareStartInjectedConvCmdStatus(ADC_TypeDef* ADCx) +{ + FlagStatus bitstatus = RESET; + /* Check the parameters */ + assert_param(IS_ADC_ALL_PERIPH(ADCx)); + /* Check the status of JSWSTART bit */ + if ((ADCx->CR2 & CR2_JSWSTART_Set) != (uint32_t)RESET) + { + /* JSWSTART bit is set */ + bitstatus = SET; + } + else + { + /* JSWSTART bit is reset */ + bitstatus = RESET; + } + /* Return the JSWSTART bit status */ + return bitstatus; +} + +/** + * @brief Configures for the selected ADC injected channel its corresponding + * rank in the sequencer and its sample time. + * @param ADCx: where x can be 1, 2 or 3 to select the ADC peripheral. + * @param ADC_Channel: the ADC channel to configure. + * This parameter can be one of the following values: + * @arg ADC_Channel_0: ADC Channel0 selected + * @arg ADC_Channel_1: ADC Channel1 selected + * @arg ADC_Channel_2: ADC Channel2 selected + * @arg ADC_Channel_3: ADC Channel3 selected + * @arg ADC_Channel_4: ADC Channel4 selected + * @arg ADC_Channel_5: ADC Channel5 selected + * @arg ADC_Channel_6: ADC Channel6 selected + * @arg ADC_Channel_7: ADC Channel7 selected + * @arg ADC_Channel_8: ADC Channel8 selected + * @arg ADC_Channel_9: ADC Channel9 selected + * @arg ADC_Channel_10: ADC Channel10 selected + * @arg ADC_Channel_11: ADC Channel11 selected + * @arg ADC_Channel_12: ADC Channel12 selected + * @arg ADC_Channel_13: ADC Channel13 selected + * @arg ADC_Channel_14: ADC Channel14 selected + * @arg ADC_Channel_15: ADC Channel15 selected + * @arg ADC_Channel_16: ADC Channel16 selected + * @arg ADC_Channel_17: ADC Channel17 selected + * @param Rank: The rank in the injected group sequencer. This parameter must be between 1 and 4. + * @param ADC_SampleTime: The sample time value to be set for the selected channel. + * This parameter can be one of the following values: + * @arg ADC_SampleTime_1Cycles5: Sample time equal to 1.5 cycles + * @arg ADC_SampleTime_7Cycles5: Sample time equal to 7.5 cycles + * @arg ADC_SampleTime_13Cycles5: Sample time equal to 13.5 cycles + * @arg ADC_SampleTime_28Cycles5: Sample time equal to 28.5 cycles + * @arg ADC_SampleTime_41Cycles5: Sample time equal to 41.5 cycles + * @arg ADC_SampleTime_55Cycles5: Sample time equal to 55.5 cycles + * @arg ADC_SampleTime_71Cycles5: Sample time equal to 71.5 cycles + * @arg ADC_SampleTime_239Cycles5: Sample time equal to 239.5 cycles + * @retval None + */ +void ADC_InjectedChannelConfig(ADC_TypeDef* ADCx, uint8_t ADC_Channel, uint8_t Rank, uint8_t ADC_SampleTime) +{ + uint32_t tmpreg1 = 0, tmpreg2 = 0, tmpreg3 = 0; + /* Check the parameters */ + assert_param(IS_ADC_ALL_PERIPH(ADCx)); + assert_param(IS_ADC_CHANNEL(ADC_Channel)); + assert_param(IS_ADC_INJECTED_RANK(Rank)); + assert_param(IS_ADC_SAMPLE_TIME(ADC_SampleTime)); + /* if ADC_Channel_10 ... ADC_Channel_17 is selected */ + if (ADC_Channel > ADC_Channel_9) + { + /* Get the old register value */ + tmpreg1 = ADCx->SMPR1; + /* Calculate the mask to clear */ + tmpreg2 = SMPR1_SMP_Set << (3*(ADC_Channel - 10)); + /* Clear the old channel sample time */ + tmpreg1 &= ~tmpreg2; + /* Calculate the mask to set */ + tmpreg2 = (uint32_t)ADC_SampleTime << (3*(ADC_Channel - 10)); + /* Set the new channel sample time */ + tmpreg1 |= tmpreg2; + /* Store the new register value */ + ADCx->SMPR1 = tmpreg1; + } + else /* ADC_Channel include in ADC_Channel_[0..9] */ + { + /* Get the old register value */ + tmpreg1 = ADCx->SMPR2; + /* Calculate the mask to clear */ + tmpreg2 = SMPR2_SMP_Set << (3 * ADC_Channel); + /* Clear the old channel sample time */ + tmpreg1 &= ~tmpreg2; + /* Calculate the mask to set */ + tmpreg2 = (uint32_t)ADC_SampleTime << (3 * ADC_Channel); + /* Set the new channel sample time */ + tmpreg1 |= tmpreg2; + /* Store the new register value */ + ADCx->SMPR2 = tmpreg1; + } + /* Rank configuration */ + /* Get the old register value */ + tmpreg1 = ADCx->JSQR; + /* Get JL value: Number = JL+1 */ + tmpreg3 = (tmpreg1 & JSQR_JL_Set)>> 20; + /* Calculate the mask to clear: ((Rank-1)+(4-JL-1)) */ + tmpreg2 = JSQR_JSQ_Set << (5 * (uint8_t)((Rank + 3) - (tmpreg3 + 1))); + /* Clear the old JSQx bits for the selected rank */ + tmpreg1 &= ~tmpreg2; + /* Calculate the mask to set: ((Rank-1)+(4-JL-1)) */ + tmpreg2 = (uint32_t)ADC_Channel << (5 * (uint8_t)((Rank + 3) - (tmpreg3 + 1))); + /* Set the JSQx bits for the selected rank */ + tmpreg1 |= tmpreg2; + /* Store the new register value */ + ADCx->JSQR = tmpreg1; +} + +/** + * @brief Configures the sequencer length for injected channels + * @param ADCx: where x can be 1, 2 or 3 to select the ADC peripheral. + * @param Length: The sequencer length. + * This parameter must be a number between 1 to 4. + * @retval None + */ +void ADC_InjectedSequencerLengthConfig(ADC_TypeDef* ADCx, uint8_t Length) +{ + uint32_t tmpreg1 = 0; + uint32_t tmpreg2 = 0; + /* Check the parameters */ + assert_param(IS_ADC_ALL_PERIPH(ADCx)); + assert_param(IS_ADC_INJECTED_LENGTH(Length)); + + /* Get the old register value */ + tmpreg1 = ADCx->JSQR; + /* Clear the old injected sequnence lenght JL bits */ + tmpreg1 &= JSQR_JL_Reset; + /* Set the injected sequnence lenght JL bits */ + tmpreg2 = Length - 1; + tmpreg1 |= tmpreg2 << 20; + /* Store the new register value */ + ADCx->JSQR = tmpreg1; +} + +/** + * @brief Set the injected channels conversion value offset + * @param ADCx: where x can be 1, 2 or 3 to select the ADC peripheral. + * @param ADC_InjectedChannel: the ADC injected channel to set its offset. + * This parameter can be one of the following values: + * @arg ADC_InjectedChannel_1: Injected Channel1 selected + * @arg ADC_InjectedChannel_2: Injected Channel2 selected + * @arg ADC_InjectedChannel_3: Injected Channel3 selected + * @arg ADC_InjectedChannel_4: Injected Channel4 selected + * @param Offset: the offset value for the selected ADC injected channel + * This parameter must be a 12bit value. + * @retval None + */ +void ADC_SetInjectedOffset(ADC_TypeDef* ADCx, uint8_t ADC_InjectedChannel, uint16_t Offset) +{ + __IO uint32_t tmp = 0; + + /* Check the parameters */ + assert_param(IS_ADC_ALL_PERIPH(ADCx)); + assert_param(IS_ADC_INJECTED_CHANNEL(ADC_InjectedChannel)); + assert_param(IS_ADC_OFFSET(Offset)); + + tmp = (uint32_t)ADCx; + tmp += ADC_InjectedChannel; + + /* Set the selected injected channel data offset */ + *(__IO uint32_t *) tmp = (uint32_t)Offset; +} + +/** + * @brief Returns the ADC injected channel conversion result + * @param ADCx: where x can be 1, 2 or 3 to select the ADC peripheral. + * @param ADC_InjectedChannel: the converted ADC injected channel. + * This parameter can be one of the following values: + * @arg ADC_InjectedChannel_1: Injected Channel1 selected + * @arg ADC_InjectedChannel_2: Injected Channel2 selected + * @arg ADC_InjectedChannel_3: Injected Channel3 selected + * @arg ADC_InjectedChannel_4: Injected Channel4 selected + * @retval The Data conversion value. + */ +uint16_t ADC_GetInjectedConversionValue(ADC_TypeDef* ADCx, uint8_t ADC_InjectedChannel) +{ + __IO uint32_t tmp = 0; + + /* Check the parameters */ + assert_param(IS_ADC_ALL_PERIPH(ADCx)); + assert_param(IS_ADC_INJECTED_CHANNEL(ADC_InjectedChannel)); + + tmp = (uint32_t)ADCx; + tmp += ADC_InjectedChannel + JDR_Offset; + + /* Returns the selected injected channel conversion data value */ + return (uint16_t) (*(__IO uint32_t*) tmp); +} + +/** + * @brief Enables or disables the analog watchdog on single/all regular + * or injected channels + * @param ADCx: where x can be 1, 2 or 3 to select the ADC peripheral. + * @param ADC_AnalogWatchdog: the ADC analog watchdog configuration. + * This parameter can be one of the following values: + * @arg ADC_AnalogWatchdog_SingleRegEnable: Analog watchdog on a single regular channel + * @arg ADC_AnalogWatchdog_SingleInjecEnable: Analog watchdog on a single injected channel + * @arg ADC_AnalogWatchdog_SingleRegOrInjecEnable: Analog watchdog on a single regular or injected channel + * @arg ADC_AnalogWatchdog_AllRegEnable: Analog watchdog on all regular channel + * @arg ADC_AnalogWatchdog_AllInjecEnable: Analog watchdog on all injected channel + * @arg ADC_AnalogWatchdog_AllRegAllInjecEnable: Analog watchdog on all regular and injected channels + * @arg ADC_AnalogWatchdog_None: No channel guarded by the analog watchdog + * @retval None + */ +void ADC_AnalogWatchdogCmd(ADC_TypeDef* ADCx, uint32_t ADC_AnalogWatchdog) +{ + uint32_t tmpreg = 0; + /* Check the parameters */ + assert_param(IS_ADC_ALL_PERIPH(ADCx)); + assert_param(IS_ADC_ANALOG_WATCHDOG(ADC_AnalogWatchdog)); + /* Get the old register value */ + tmpreg = ADCx->CR1; + /* Clear AWDEN, AWDENJ and AWDSGL bits */ + tmpreg &= CR1_AWDMode_Reset; + /* Set the analog watchdog enable mode */ + tmpreg |= ADC_AnalogWatchdog; + /* Store the new register value */ + ADCx->CR1 = tmpreg; +} + +/** + * @brief Configures the high and low thresholds of the analog watchdog. + * @param ADCx: where x can be 1, 2 or 3 to select the ADC peripheral. + * @param HighThreshold: the ADC analog watchdog High threshold value. + * This parameter must be a 12bit value. + * @param LowThreshold: the ADC analog watchdog Low threshold value. + * This parameter must be a 12bit value. + * @retval None + */ +void ADC_AnalogWatchdogThresholdsConfig(ADC_TypeDef* ADCx, uint16_t HighThreshold, + uint16_t LowThreshold) +{ + /* Check the parameters */ + assert_param(IS_ADC_ALL_PERIPH(ADCx)); + assert_param(IS_ADC_THRESHOLD(HighThreshold)); + assert_param(IS_ADC_THRESHOLD(LowThreshold)); + /* Set the ADCx high threshold */ + ADCx->HTR = HighThreshold; + /* Set the ADCx low threshold */ + ADCx->LTR = LowThreshold; +} + +/** + * @brief Configures the analog watchdog guarded single channel + * @param ADCx: where x can be 1, 2 or 3 to select the ADC peripheral. + * @param ADC_Channel: the ADC channel to configure for the analog watchdog. + * This parameter can be one of the following values: + * @arg ADC_Channel_0: ADC Channel0 selected + * @arg ADC_Channel_1: ADC Channel1 selected + * @arg ADC_Channel_2: ADC Channel2 selected + * @arg ADC_Channel_3: ADC Channel3 selected + * @arg ADC_Channel_4: ADC Channel4 selected + * @arg ADC_Channel_5: ADC Channel5 selected + * @arg ADC_Channel_6: ADC Channel6 selected + * @arg ADC_Channel_7: ADC Channel7 selected + * @arg ADC_Channel_8: ADC Channel8 selected + * @arg ADC_Channel_9: ADC Channel9 selected + * @arg ADC_Channel_10: ADC Channel10 selected + * @arg ADC_Channel_11: ADC Channel11 selected + * @arg ADC_Channel_12: ADC Channel12 selected + * @arg ADC_Channel_13: ADC Channel13 selected + * @arg ADC_Channel_14: ADC Channel14 selected + * @arg ADC_Channel_15: ADC Channel15 selected + * @arg ADC_Channel_16: ADC Channel16 selected + * @arg ADC_Channel_17: ADC Channel17 selected + * @retval None + */ +void ADC_AnalogWatchdogSingleChannelConfig(ADC_TypeDef* ADCx, uint8_t ADC_Channel) +{ + uint32_t tmpreg = 0; + /* Check the parameters */ + assert_param(IS_ADC_ALL_PERIPH(ADCx)); + assert_param(IS_ADC_CHANNEL(ADC_Channel)); + /* Get the old register value */ + tmpreg = ADCx->CR1; + /* Clear the Analog watchdog channel select bits */ + tmpreg &= CR1_AWDCH_Reset; + /* Set the Analog watchdog channel */ + tmpreg |= ADC_Channel; + /* Store the new register value */ + ADCx->CR1 = tmpreg; +} + +/** + * @brief Enables or disables the temperature sensor and Vrefint channel. + * @param NewState: new state of the temperature sensor. + * This parameter can be: ENABLE or DISABLE. + * @retval None + */ +void ADC_TempSensorVrefintCmd(FunctionalState NewState) +{ + /* Check the parameters */ + assert_param(IS_FUNCTIONAL_STATE(NewState)); + if (NewState != DISABLE) + { + /* Enable the temperature sensor and Vrefint channel*/ + ADC1->CR2 |= CR2_TSVREFE_Set; + } + else + { + /* Disable the temperature sensor and Vrefint channel*/ + ADC1->CR2 &= CR2_TSVREFE_Reset; + } +} + +/** + * @brief Checks whether the specified ADC flag is set or not. + * @param ADCx: where x can be 1, 2 or 3 to select the ADC peripheral. + * @param ADC_FLAG: specifies the flag to check. + * This parameter can be one of the following values: + * @arg ADC_FLAG_AWD: Analog watchdog flag + * @arg ADC_FLAG_EOC: End of conversion flag + * @arg ADC_FLAG_JEOC: End of injected group conversion flag + * @arg ADC_FLAG_JSTRT: Start of injected group conversion flag + * @arg ADC_FLAG_STRT: Start of regular group conversion flag + * @retval The new state of ADC_FLAG (SET or RESET). + */ +FlagStatus ADC_GetFlagStatus(ADC_TypeDef* ADCx, uint8_t ADC_FLAG) +{ + FlagStatus bitstatus = RESET; + /* Check the parameters */ + assert_param(IS_ADC_ALL_PERIPH(ADCx)); + assert_param(IS_ADC_GET_FLAG(ADC_FLAG)); + /* Check the status of the specified ADC flag */ + if ((ADCx->SR & ADC_FLAG) != (uint8_t)RESET) + { + /* ADC_FLAG is set */ + bitstatus = SET; + } + else + { + /* ADC_FLAG is reset */ + bitstatus = RESET; + } + /* Return the ADC_FLAG status */ + return bitstatus; +} + +/** + * @brief Clears the ADCx's pending flags. + * @param ADCx: where x can be 1, 2 or 3 to select the ADC peripheral. + * @param ADC_FLAG: specifies the flag to clear. + * This parameter can be any combination of the following values: + * @arg ADC_FLAG_AWD: Analog watchdog flag + * @arg ADC_FLAG_EOC: End of conversion flag + * @arg ADC_FLAG_JEOC: End of injected group conversion flag + * @arg ADC_FLAG_JSTRT: Start of injected group conversion flag + * @arg ADC_FLAG_STRT: Start of regular group conversion flag + * @retval None + */ +void ADC_ClearFlag(ADC_TypeDef* ADCx, uint8_t ADC_FLAG) +{ + /* Check the parameters */ + assert_param(IS_ADC_ALL_PERIPH(ADCx)); + assert_param(IS_ADC_CLEAR_FLAG(ADC_FLAG)); + /* Clear the selected ADC flags */ + ADCx->SR = ~(uint32_t)ADC_FLAG; +} + +/** + * @brief Checks whether the specified ADC interrupt has occurred or not. + * @param ADCx: where x can be 1, 2 or 3 to select the ADC peripheral. + * @param ADC_IT: specifies the ADC interrupt source to check. + * This parameter can be one of the following values: + * @arg ADC_IT_EOC: End of conversion interrupt mask + * @arg ADC_IT_AWD: Analog watchdog interrupt mask + * @arg ADC_IT_JEOC: End of injected conversion interrupt mask + * @retval The new state of ADC_IT (SET or RESET). + */ +ITStatus ADC_GetITStatus(ADC_TypeDef* ADCx, uint16_t ADC_IT) +{ + ITStatus bitstatus = RESET; + uint32_t itmask = 0, enablestatus = 0; + /* Check the parameters */ + assert_param(IS_ADC_ALL_PERIPH(ADCx)); + assert_param(IS_ADC_GET_IT(ADC_IT)); + /* Get the ADC IT index */ + itmask = ADC_IT >> 8; + /* Get the ADC_IT enable bit status */ + enablestatus = (ADCx->CR1 & (uint8_t)ADC_IT) ; + /* Check the status of the specified ADC interrupt */ + if (((ADCx->SR & itmask) != (uint32_t)RESET) && enablestatus) + { + /* ADC_IT is set */ + bitstatus = SET; + } + else + { + /* ADC_IT is reset */ + bitstatus = RESET; + } + /* Return the ADC_IT status */ + return bitstatus; +} + +/** + * @brief Clears the ADCx's interrupt pending bits. + * @param ADCx: where x can be 1, 2 or 3 to select the ADC peripheral. + * @param ADC_IT: specifies the ADC interrupt pending bit to clear. + * This parameter can be any combination of the following values: + * @arg ADC_IT_EOC: End of conversion interrupt mask + * @arg ADC_IT_AWD: Analog watchdog interrupt mask + * @arg ADC_IT_JEOC: End of injected conversion interrupt mask + * @retval None + */ +void ADC_ClearITPendingBit(ADC_TypeDef* ADCx, uint16_t ADC_IT) +{ + uint8_t itmask = 0; + /* Check the parameters */ + assert_param(IS_ADC_ALL_PERIPH(ADCx)); + assert_param(IS_ADC_IT(ADC_IT)); + /* Get the ADC IT index */ + itmask = (uint8_t)(ADC_IT >> 8); + /* Clear the selected ADC interrupt pending bits */ + ADCx->SR = ~(uint32_t)itmask; +} + +/** + * @} + */ + +/** + * @} + */ + +/** + * @} + */ + +/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ diff --git a/Libraries/STM32F10x_StdPeriph_Driver/src/stm32f10x_bkp.c b/Libraries/STM32F10x_StdPeriph_Driver/src/stm32f10x_bkp.c new file mode 100644 index 0000000..49c9ae3 --- /dev/null +++ b/Libraries/STM32F10x_StdPeriph_Driver/src/stm32f10x_bkp.c @@ -0,0 +1,314 @@ +/** + ****************************************************************************** + * @file stm32f10x_bkp.c + * @author MCD Application Team + * @version V3.6.1 + * @date 05-March-2012 + * @brief This file provides all the BKP firmware functions. + ****************************************************************************** + * @attention + * + *

    © COPYRIGHT 2012 STMicroelectronics

    + * + * Licensed under MCD-ST Liberty SW License Agreement V2, (the "License"); + * You may not use this file except in compliance with the License. + * You may obtain a copy of the License at: + * + * http://www.st.com/software_license_agreement_liberty_v2 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, + * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + * + ****************************************************************************** + */ + +/* Includes ------------------------------------------------------------------*/ +#include "stm32f10x_bkp.h" +#include "stm32f10x_rcc.h" + +/** @addtogroup STM32F10x_StdPeriph_Driver + * @{ + */ + +/** @defgroup BKP + * @brief BKP driver modules + * @{ + */ + +/** @defgroup BKP_Private_TypesDefinitions + * @{ + */ + +/** + * @} + */ + +/** @defgroup BKP_Private_Defines + * @{ + */ + +/* ------------ BKP registers bit address in the alias region --------------- */ +#define BKP_OFFSET (BKP_BASE - PERIPH_BASE) + +/* --- CR Register ----*/ + +/* Alias word address of TPAL bit */ +#define CR_OFFSET (BKP_OFFSET + 0x30) +#define TPAL_BitNumber 0x01 +#define CR_TPAL_BB (PERIPH_BB_BASE + (CR_OFFSET * 32) + (TPAL_BitNumber * 4)) + +/* Alias word address of TPE bit */ +#define TPE_BitNumber 0x00 +#define CR_TPE_BB (PERIPH_BB_BASE + (CR_OFFSET * 32) + (TPE_BitNumber * 4)) + +/* --- CSR Register ---*/ + +/* Alias word address of TPIE bit */ +#define CSR_OFFSET (BKP_OFFSET + 0x34) +#define TPIE_BitNumber 0x02 +#define CSR_TPIE_BB (PERIPH_BB_BASE + (CSR_OFFSET * 32) + (TPIE_BitNumber * 4)) + +/* Alias word address of TIF bit */ +#define TIF_BitNumber 0x09 +#define CSR_TIF_BB (PERIPH_BB_BASE + (CSR_OFFSET * 32) + (TIF_BitNumber * 4)) + +/* Alias word address of TEF bit */ +#define TEF_BitNumber 0x08 +#define CSR_TEF_BB (PERIPH_BB_BASE + (CSR_OFFSET * 32) + (TEF_BitNumber * 4)) + +/* ---------------------- BKP registers bit mask ------------------------ */ + +/* RTCCR register bit mask */ +#define RTCCR_CAL_MASK ((uint16_t)0xFF80) +#define RTCCR_MASK ((uint16_t)0xFC7F) + +/** + * @} + */ + + +/** @defgroup BKP_Private_Macros + * @{ + */ + +/** + * @} + */ + +/** @defgroup BKP_Private_Variables + * @{ + */ + +/** + * @} + */ + +/** @defgroup BKP_Private_FunctionPrototypes + * @{ + */ + +/** + * @} + */ + +/** @defgroup BKP_Private_Functions + * @{ + */ + +/** + * @brief Deinitializes the BKP peripheral registers to their default reset values. + * @param None + * @retval None + */ +void BKP_DeInit(void) +{ + RCC_BackupResetCmd(ENABLE); + RCC_BackupResetCmd(DISABLE); +} + +/** + * @brief Configures the Tamper Pin active level. + * @param BKP_TamperPinLevel: specifies the Tamper Pin active level. + * This parameter can be one of the following values: + * @arg BKP_TamperPinLevel_High: Tamper pin active on high level + * @arg BKP_TamperPinLevel_Low: Tamper pin active on low level + * @retval None + */ +void BKP_TamperPinLevelConfig(uint16_t BKP_TamperPinLevel) +{ + /* Check the parameters */ + assert_param(IS_BKP_TAMPER_PIN_LEVEL(BKP_TamperPinLevel)); + *(__IO uint32_t *) CR_TPAL_BB = BKP_TamperPinLevel; +} + +/** + * @brief Enables or disables the Tamper Pin activation. + * @param NewState: new state of the Tamper Pin activation. + * This parameter can be: ENABLE or DISABLE. + * @retval None + */ +void BKP_TamperPinCmd(FunctionalState NewState) +{ + /* Check the parameters */ + assert_param(IS_FUNCTIONAL_STATE(NewState)); + *(__IO uint32_t *) CR_TPE_BB = (uint32_t)NewState; +} + +/** + * @brief Enables or disables the Tamper Pin Interrupt. + * @param NewState: new state of the Tamper Pin Interrupt. + * This parameter can be: ENABLE or DISABLE. + * @retval None + */ +void BKP_ITConfig(FunctionalState NewState) +{ + /* Check the parameters */ + assert_param(IS_FUNCTIONAL_STATE(NewState)); + *(__IO uint32_t *) CSR_TPIE_BB = (uint32_t)NewState; +} + +/** + * @brief Select the RTC output source to output on the Tamper pin. + * @param BKP_RTCOutputSource: specifies the RTC output source. + * This parameter can be one of the following values: + * @arg BKP_RTCOutputSource_None: no RTC output on the Tamper pin. + * @arg BKP_RTCOutputSource_CalibClock: output the RTC clock with frequency + * divided by 64 on the Tamper pin. + * @arg BKP_RTCOutputSource_Alarm: output the RTC Alarm pulse signal on + * the Tamper pin. + * @arg BKP_RTCOutputSource_Second: output the RTC Second pulse signal on + * the Tamper pin. + * @retval None + */ +void BKP_RTCOutputConfig(uint16_t BKP_RTCOutputSource) +{ + uint16_t tmpreg = 0; + /* Check the parameters */ + assert_param(IS_BKP_RTC_OUTPUT_SOURCE(BKP_RTCOutputSource)); + tmpreg = BKP->RTCCR; + /* Clear CCO, ASOE and ASOS bits */ + tmpreg &= RTCCR_MASK; + + /* Set CCO, ASOE and ASOS bits according to BKP_RTCOutputSource value */ + tmpreg |= BKP_RTCOutputSource; + /* Store the new value */ + BKP->RTCCR = tmpreg; +} + +/** + * @brief Sets RTC Clock Calibration value. + * @param CalibrationValue: specifies the RTC Clock Calibration value. + * This parameter must be a number between 0 and 0x7F. + * @retval None + */ +void BKP_SetRTCCalibrationValue(uint8_t CalibrationValue) +{ + uint16_t tmpreg = 0; + /* Check the parameters */ + assert_param(IS_BKP_CALIBRATION_VALUE(CalibrationValue)); + tmpreg = BKP->RTCCR; + /* Clear CAL[6:0] bits */ + tmpreg &= RTCCR_CAL_MASK; + /* Set CAL[6:0] bits according to CalibrationValue value */ + tmpreg |= CalibrationValue; + /* Store the new value */ + BKP->RTCCR = tmpreg; +} + +/** + * @brief Writes user data to the specified Data Backup Register. + * @param BKP_DR: specifies the Data Backup Register. + * This parameter can be BKP_DRx where x:[1, 42] + * @param Data: data to write + * @retval None + */ +void BKP_WriteBackupRegister(uint16_t BKP_DR, uint16_t Data) +{ + __IO uint32_t tmp = 0; + + /* Check the parameters */ + assert_param(IS_BKP_DR(BKP_DR)); + + tmp = (uint32_t)BKP_BASE; + tmp += BKP_DR; + + *(__IO uint32_t *) tmp = Data; +} + +/** + * @brief Reads data from the specified Data Backup Register. + * @param BKP_DR: specifies the Data Backup Register. + * This parameter can be BKP_DRx where x:[1, 42] + * @retval The content of the specified Data Backup Register + */ +uint16_t BKP_ReadBackupRegister(uint16_t BKP_DR) +{ + __IO uint32_t tmp = 0; + + /* Check the parameters */ + assert_param(IS_BKP_DR(BKP_DR)); + + tmp = (uint32_t)BKP_BASE; + tmp += BKP_DR; + + return (*(__IO uint16_t *) tmp); +} + +/** + * @brief Checks whether the Tamper Pin Event flag is set or not. + * @param None + * @retval The new state of the Tamper Pin Event flag (SET or RESET). + */ +FlagStatus BKP_GetFlagStatus(void) +{ + return (FlagStatus)(*(__IO uint32_t *) CSR_TEF_BB); +} + +/** + * @brief Clears Tamper Pin Event pending flag. + * @param None + * @retval None + */ +void BKP_ClearFlag(void) +{ + /* Set CTE bit to clear Tamper Pin Event flag */ + BKP->CSR |= BKP_CSR_CTE; +} + +/** + * @brief Checks whether the Tamper Pin Interrupt has occurred or not. + * @param None + * @retval The new state of the Tamper Pin Interrupt (SET or RESET). + */ +ITStatus BKP_GetITStatus(void) +{ + return (ITStatus)(*(__IO uint32_t *) CSR_TIF_BB); +} + +/** + * @brief Clears Tamper Pin Interrupt pending bit. + * @param None + * @retval None + */ +void BKP_ClearITPendingBit(void) +{ + /* Set CTI bit to clear Tamper Pin Interrupt pending bit */ + BKP->CSR |= BKP_CSR_CTI; +} + +/** + * @} + */ + +/** + * @} + */ + +/** + * @} + */ + +/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ diff --git a/Libraries/STM32F10x_StdPeriph_Driver/src/stm32f10x_can.c b/Libraries/STM32F10x_StdPeriph_Driver/src/stm32f10x_can.c new file mode 100644 index 0000000..2b1924b --- /dev/null +++ b/Libraries/STM32F10x_StdPeriph_Driver/src/stm32f10x_can.c @@ -0,0 +1,1421 @@ +/** + ****************************************************************************** + * @file stm32f10x_can.c + * @author MCD Application Team + * @version V3.6.1 + * @date 05-March-2012 + * @brief This file provides all the CAN firmware functions. + ****************************************************************************** + * @attention + * + *

    © COPYRIGHT 2012 STMicroelectronics

    + * + * Licensed under MCD-ST Liberty SW License Agreement V2, (the "License"); + * You may not use this file except in compliance with the License. + * You may obtain a copy of the License at: + * + * http://www.st.com/software_license_agreement_liberty_v2 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, + * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + * + ****************************************************************************** + */ + +/* Includes ------------------------------------------------------------------*/ +#include "stm32f10x_can.h" +#include "stm32f10x_rcc.h" + +/** @addtogroup STM32F10x_StdPeriph_Driver + * @{ + */ + +/** @defgroup CAN + * @brief CAN driver modules + * @{ + */ + +/** @defgroup CAN_Private_TypesDefinitions + * @{ + */ + +/** + * @} + */ + +/** @defgroup CAN_Private_Defines + * @{ + */ + +/* CAN Master Control Register bits */ + +#define MCR_DBF ((uint32_t)0x00010000) /* software master reset */ + +/* CAN Mailbox Transmit Request */ +#define TMIDxR_TXRQ ((uint32_t)0x00000001) /* Transmit mailbox request */ + +/* CAN Filter Master Register bits */ +#define FMR_FINIT ((uint32_t)0x00000001) /* Filter init mode */ + +/* Time out for INAK bit */ +#define INAK_TIMEOUT ((uint32_t)0x0000FFFF) +/* Time out for SLAK bit */ +#define SLAK_TIMEOUT ((uint32_t)0x0000FFFF) + + + +/* Flags in TSR register */ +#define CAN_FLAGS_TSR ((uint32_t)0x08000000) +/* Flags in RF1R register */ +#define CAN_FLAGS_RF1R ((uint32_t)0x04000000) +/* Flags in RF0R register */ +#define CAN_FLAGS_RF0R ((uint32_t)0x02000000) +/* Flags in MSR register */ +#define CAN_FLAGS_MSR ((uint32_t)0x01000000) +/* Flags in ESR register */ +#define CAN_FLAGS_ESR ((uint32_t)0x00F00000) + +/* Mailboxes definition */ +#define CAN_TXMAILBOX_0 ((uint8_t)0x00) +#define CAN_TXMAILBOX_1 ((uint8_t)0x01) +#define CAN_TXMAILBOX_2 ((uint8_t)0x02) + + + +#define CAN_MODE_MASK ((uint32_t) 0x00000003) +/** + * @} + */ + +/** @defgroup CAN_Private_Macros + * @{ + */ + +/** + * @} + */ + +/** @defgroup CAN_Private_Variables + * @{ + */ + +/** + * @} + */ + +/** @defgroup CAN_Private_FunctionPrototypes + * @{ + */ + +static ITStatus CheckITStatus(uint32_t CAN_Reg, uint32_t It_Bit); + +/** + * @} + */ + +/** @defgroup CAN_Private_Functions + * @{ + */ + +/** + * @brief Deinitializes the CAN peripheral registers to their default reset values. + * @param CANx: where x can be 1 or 2 to select the CAN peripheral. + * @retval None. + */ +void CAN_DeInit(CAN_TypeDef* CANx) +{ + /* Check the parameters */ + assert_param(IS_CAN_ALL_PERIPH(CANx)); + + if (CANx == CAN1) + { + /* Enable CAN1 reset state */ + RCC_APB1PeriphResetCmd(RCC_APB1Periph_CAN1, ENABLE); + /* Release CAN1 from reset state */ + RCC_APB1PeriphResetCmd(RCC_APB1Periph_CAN1, DISABLE); + } + else + { + /* Enable CAN2 reset state */ + RCC_APB1PeriphResetCmd(RCC_APB1Periph_CAN2, ENABLE); + /* Release CAN2 from reset state */ + RCC_APB1PeriphResetCmd(RCC_APB1Periph_CAN2, DISABLE); + } +} + +/** + * @brief Initializes the CAN peripheral according to the specified + * parameters in the CAN_InitStruct. + * @param CANx: where x can be 1 or 2 to to select the CAN + * peripheral. + * @param CAN_InitStruct: pointer to a CAN_InitTypeDef structure that + * contains the configuration information for the + * CAN peripheral. + * @retval Constant indicates initialization succeed which will be + * CAN_InitStatus_Failed or CAN_InitStatus_Success. + */ +uint8_t CAN_Init(CAN_TypeDef* CANx, CAN_InitTypeDef* CAN_InitStruct) +{ + uint8_t InitStatus = CAN_InitStatus_Failed; + uint32_t wait_ack = 0x00000000; + /* Check the parameters */ + assert_param(IS_CAN_ALL_PERIPH(CANx)); + assert_param(IS_FUNCTIONAL_STATE(CAN_InitStruct->CAN_TTCM)); + assert_param(IS_FUNCTIONAL_STATE(CAN_InitStruct->CAN_ABOM)); + assert_param(IS_FUNCTIONAL_STATE(CAN_InitStruct->CAN_AWUM)); + assert_param(IS_FUNCTIONAL_STATE(CAN_InitStruct->CAN_NART)); + assert_param(IS_FUNCTIONAL_STATE(CAN_InitStruct->CAN_RFLM)); + assert_param(IS_FUNCTIONAL_STATE(CAN_InitStruct->CAN_TXFP)); + assert_param(IS_CAN_MODE(CAN_InitStruct->CAN_Mode)); + assert_param(IS_CAN_SJW(CAN_InitStruct->CAN_SJW)); + assert_param(IS_CAN_BS1(CAN_InitStruct->CAN_BS1)); + assert_param(IS_CAN_BS2(CAN_InitStruct->CAN_BS2)); + assert_param(IS_CAN_PRESCALER(CAN_InitStruct->CAN_Prescaler)); + + /* Exit from sleep mode */ + CANx->MCR &= (~(uint32_t)CAN_MCR_SLEEP); + + /* Request initialisation */ + CANx->MCR |= CAN_MCR_INRQ ; + + /* Wait the acknowledge */ + while (((CANx->MSR & CAN_MSR_INAK) != CAN_MSR_INAK) && (wait_ack != INAK_TIMEOUT)) + { + wait_ack++; + } + + /* Check acknowledge */ + if ((CANx->MSR & CAN_MSR_INAK) != CAN_MSR_INAK) + { + InitStatus = CAN_InitStatus_Failed; + } + else + { + /* Set the time triggered communication mode */ + if (CAN_InitStruct->CAN_TTCM == ENABLE) + { + CANx->MCR |= CAN_MCR_TTCM; + } + else + { + CANx->MCR &= ~(uint32_t)CAN_MCR_TTCM; + } + + /* Set the automatic bus-off management */ + if (CAN_InitStruct->CAN_ABOM == ENABLE) + { + CANx->MCR |= CAN_MCR_ABOM; + } + else + { + CANx->MCR &= ~(uint32_t)CAN_MCR_ABOM; + } + + /* Set the automatic wake-up mode */ + if (CAN_InitStruct->CAN_AWUM == ENABLE) + { + CANx->MCR |= CAN_MCR_AWUM; + } + else + { + CANx->MCR &= ~(uint32_t)CAN_MCR_AWUM; + } + + /* Set the no automatic retransmission */ + if (CAN_InitStruct->CAN_NART == ENABLE) + { + CANx->MCR |= CAN_MCR_NART; + } + else + { + CANx->MCR &= ~(uint32_t)CAN_MCR_NART; + } + + /* Set the receive FIFO locked mode */ + if (CAN_InitStruct->CAN_RFLM == ENABLE) + { + CANx->MCR |= CAN_MCR_RFLM; + } + else + { + CANx->MCR &= ~(uint32_t)CAN_MCR_RFLM; + } + + /* Set the transmit FIFO priority */ + if (CAN_InitStruct->CAN_TXFP == ENABLE) + { + CANx->MCR |= CAN_MCR_TXFP; + } + else + { + CANx->MCR &= ~(uint32_t)CAN_MCR_TXFP; + } + + /* Set the bit timing register */ + CANx->BTR = (uint32_t)((uint32_t)CAN_InitStruct->CAN_Mode << 30) | \ + ((uint32_t)CAN_InitStruct->CAN_SJW << 24) | \ + ((uint32_t)CAN_InitStruct->CAN_BS1 << 16) | \ + ((uint32_t)CAN_InitStruct->CAN_BS2 << 20) | \ + ((uint32_t)CAN_InitStruct->CAN_Prescaler - 1); + + /* Request leave initialisation */ + CANx->MCR &= ~(uint32_t)CAN_MCR_INRQ; + + /* Wait the acknowledge */ + wait_ack = 0; + + while (((CANx->MSR & CAN_MSR_INAK) == CAN_MSR_INAK) && (wait_ack != INAK_TIMEOUT)) + { + wait_ack++; + } + + /* ...and check acknowledged */ + if ((CANx->MSR & CAN_MSR_INAK) == CAN_MSR_INAK) + { + InitStatus = CAN_InitStatus_Failed; + } + else + { + InitStatus = CAN_InitStatus_Success ; + } + } + + /* At this step, return the status of initialization */ + return InitStatus; +} + +/** + * @brief Initializes the CAN peripheral according to the specified + * parameters in the CAN_FilterInitStruct. + * @param CAN_FilterInitStruct: pointer to a CAN_FilterInitTypeDef + * structure that contains the configuration + * information. + * @retval None. + */ +void CAN_FilterInit(CAN_FilterInitTypeDef* CAN_FilterInitStruct) +{ + uint32_t filter_number_bit_pos = 0; + /* Check the parameters */ + assert_param(IS_CAN_FILTER_NUMBER(CAN_FilterInitStruct->CAN_FilterNumber)); + assert_param(IS_CAN_FILTER_MODE(CAN_FilterInitStruct->CAN_FilterMode)); + assert_param(IS_CAN_FILTER_SCALE(CAN_FilterInitStruct->CAN_FilterScale)); + assert_param(IS_CAN_FILTER_FIFO(CAN_FilterInitStruct->CAN_FilterFIFOAssignment)); + assert_param(IS_FUNCTIONAL_STATE(CAN_FilterInitStruct->CAN_FilterActivation)); + + filter_number_bit_pos = ((uint32_t)1) << CAN_FilterInitStruct->CAN_FilterNumber; + + /* Initialisation mode for the filter */ + CAN1->FMR |= FMR_FINIT; + + /* Filter Deactivation */ + CAN1->FA1R &= ~(uint32_t)filter_number_bit_pos; + + /* Filter Scale */ + if (CAN_FilterInitStruct->CAN_FilterScale == CAN_FilterScale_16bit) + { + /* 16-bit scale for the filter */ + CAN1->FS1R &= ~(uint32_t)filter_number_bit_pos; + + /* First 16-bit identifier and First 16-bit mask */ + /* Or First 16-bit identifier and Second 16-bit identifier */ + CAN1->sFilterRegister[CAN_FilterInitStruct->CAN_FilterNumber].FR1 = + ((0x0000FFFF & (uint32_t)CAN_FilterInitStruct->CAN_FilterMaskIdLow) << 16) | + (0x0000FFFF & (uint32_t)CAN_FilterInitStruct->CAN_FilterIdLow); + + /* Second 16-bit identifier and Second 16-bit mask */ + /* Or Third 16-bit identifier and Fourth 16-bit identifier */ + CAN1->sFilterRegister[CAN_FilterInitStruct->CAN_FilterNumber].FR2 = + ((0x0000FFFF & (uint32_t)CAN_FilterInitStruct->CAN_FilterMaskIdHigh) << 16) | + (0x0000FFFF & (uint32_t)CAN_FilterInitStruct->CAN_FilterIdHigh); + } + + if (CAN_FilterInitStruct->CAN_FilterScale == CAN_FilterScale_32bit) + { + /* 32-bit scale for the filter */ + CAN1->FS1R |= filter_number_bit_pos; + /* 32-bit identifier or First 32-bit identifier */ + CAN1->sFilterRegister[CAN_FilterInitStruct->CAN_FilterNumber].FR1 = + ((0x0000FFFF & (uint32_t)CAN_FilterInitStruct->CAN_FilterIdHigh) << 16) | + (0x0000FFFF & (uint32_t)CAN_FilterInitStruct->CAN_FilterIdLow); + /* 32-bit mask or Second 32-bit identifier */ + CAN1->sFilterRegister[CAN_FilterInitStruct->CAN_FilterNumber].FR2 = + ((0x0000FFFF & (uint32_t)CAN_FilterInitStruct->CAN_FilterMaskIdHigh) << 16) | + (0x0000FFFF & (uint32_t)CAN_FilterInitStruct->CAN_FilterMaskIdLow); + } + + /* Filter Mode */ + if (CAN_FilterInitStruct->CAN_FilterMode == CAN_FilterMode_IdMask) + { + /*Id/Mask mode for the filter*/ + CAN1->FM1R &= ~(uint32_t)filter_number_bit_pos; + } + else /* CAN_FilterInitStruct->CAN_FilterMode == CAN_FilterMode_IdList */ + { + /*Identifier list mode for the filter*/ + CAN1->FM1R |= (uint32_t)filter_number_bit_pos; + } + + /* Filter FIFO assignment */ + if (CAN_FilterInitStruct->CAN_FilterFIFOAssignment == CAN_Filter_FIFO0) + { + /* FIFO 0 assignation for the filter */ + CAN1->FFA1R &= ~(uint32_t)filter_number_bit_pos; + } + + if (CAN_FilterInitStruct->CAN_FilterFIFOAssignment == CAN_Filter_FIFO1) + { + /* FIFO 1 assignation for the filter */ + CAN1->FFA1R |= (uint32_t)filter_number_bit_pos; + } + + /* Filter activation */ + if (CAN_FilterInitStruct->CAN_FilterActivation == ENABLE) + { + CAN1->FA1R |= filter_number_bit_pos; + } + + /* Leave the initialisation mode for the filter */ + CAN1->FMR &= ~FMR_FINIT; +} + +/** + * @brief Fills each CAN_InitStruct member with its default value. + * @param CAN_InitStruct: pointer to a CAN_InitTypeDef structure which + * will be initialized. + * @retval None. + */ +void CAN_StructInit(CAN_InitTypeDef* CAN_InitStruct) +{ + /* Reset CAN init structure parameters values */ + + /* Initialize the time triggered communication mode */ + CAN_InitStruct->CAN_TTCM = DISABLE; + + /* Initialize the automatic bus-off management */ + CAN_InitStruct->CAN_ABOM = DISABLE; + + /* Initialize the automatic wake-up mode */ + CAN_InitStruct->CAN_AWUM = DISABLE; + + /* Initialize the no automatic retransmission */ + CAN_InitStruct->CAN_NART = DISABLE; + + /* Initialize the receive FIFO locked mode */ + CAN_InitStruct->CAN_RFLM = DISABLE; + + /* Initialize the transmit FIFO priority */ + CAN_InitStruct->CAN_TXFP = DISABLE; + + /* Initialize the CAN_Mode member */ + CAN_InitStruct->CAN_Mode = CAN_Mode_Normal; + + /* Initialize the CAN_SJW member */ + CAN_InitStruct->CAN_SJW = CAN_SJW_1tq; + + /* Initialize the CAN_BS1 member */ + CAN_InitStruct->CAN_BS1 = CAN_BS1_4tq; + + /* Initialize the CAN_BS2 member */ + CAN_InitStruct->CAN_BS2 = CAN_BS2_3tq; + + /* Initialize the CAN_Prescaler member */ + CAN_InitStruct->CAN_Prescaler = 1; +} + +/** + * @brief Select the start bank filter for slave CAN. + * @note This function applies only to STM32 Connectivity line devices. + * @param CAN_BankNumber: Select the start slave bank filter from 1..27. + * @retval None. + */ +void CAN_SlaveStartBank(uint8_t CAN_BankNumber) +{ + /* Check the parameters */ + assert_param(IS_CAN_BANKNUMBER(CAN_BankNumber)); + + /* Enter Initialisation mode for the filter */ + CAN1->FMR |= FMR_FINIT; + + /* Select the start slave bank */ + CAN1->FMR &= (uint32_t)0xFFFFC0F1 ; + CAN1->FMR |= (uint32_t)(CAN_BankNumber)<<8; + + /* Leave Initialisation mode for the filter */ + CAN1->FMR &= ~FMR_FINIT; +} + +/** + * @brief Enables or disables the DBG Freeze for CAN. + * @param CANx: where x can be 1 or 2 to to select the CAN peripheral. + * @param NewState: new state of the CAN peripheral. This parameter can + * be: ENABLE or DISABLE. + * @retval None. + */ +void CAN_DBGFreeze(CAN_TypeDef* CANx, FunctionalState NewState) +{ + /* Check the parameters */ + assert_param(IS_CAN_ALL_PERIPH(CANx)); + assert_param(IS_FUNCTIONAL_STATE(NewState)); + + if (NewState != DISABLE) + { + /* Enable Debug Freeze */ + CANx->MCR |= MCR_DBF; + } + else + { + /* Disable Debug Freeze */ + CANx->MCR &= ~MCR_DBF; + } +} + + +/** + * @brief Enables or disabes the CAN Time TriggerOperation communication mode. + * @param CANx: where x can be 1 or 2 to to select the CAN peripheral. + * @param NewState : Mode new state , can be one of @ref FunctionalState. + * @note when enabled, Time stamp (TIME[15:0]) value is sent in the last + * two data bytes of the 8-byte message: TIME[7:0] in data byte 6 + * and TIME[15:8] in data byte 7 + * @note DLC must be programmed as 8 in order Time Stamp (2 bytes) to be + * sent over the CAN bus. + * @retval None + */ +void CAN_TTComModeCmd(CAN_TypeDef* CANx, FunctionalState NewState) +{ + /* Check the parameters */ + assert_param(IS_CAN_ALL_PERIPH(CANx)); + assert_param(IS_FUNCTIONAL_STATE(NewState)); + if (NewState != DISABLE) + { + /* Enable the TTCM mode */ + CANx->MCR |= CAN_MCR_TTCM; + + /* Set TGT bits */ + CANx->sTxMailBox[0].TDTR |= ((uint32_t)CAN_TDT0R_TGT); + CANx->sTxMailBox[1].TDTR |= ((uint32_t)CAN_TDT1R_TGT); + CANx->sTxMailBox[2].TDTR |= ((uint32_t)CAN_TDT2R_TGT); + } + else + { + /* Disable the TTCM mode */ + CANx->MCR &= (uint32_t)(~(uint32_t)CAN_MCR_TTCM); + + /* Reset TGT bits */ + CANx->sTxMailBox[0].TDTR &= ((uint32_t)~CAN_TDT0R_TGT); + CANx->sTxMailBox[1].TDTR &= ((uint32_t)~CAN_TDT1R_TGT); + CANx->sTxMailBox[2].TDTR &= ((uint32_t)~CAN_TDT2R_TGT); + } +} +/** + * @brief Initiates the transmission of a message. + * @param CANx: where x can be 1 or 2 to to select the CAN peripheral. + * @param TxMessage: pointer to a structure which contains CAN Id, CAN + * DLC and CAN data. + * @retval The number of the mailbox that is used for transmission + * or CAN_TxStatus_NoMailBox if there is no empty mailbox. + */ +uint8_t CAN_Transmit(CAN_TypeDef* CANx, CanTxMsg* TxMessage) +{ + uint8_t transmit_mailbox = 0; + /* Check the parameters */ + assert_param(IS_CAN_ALL_PERIPH(CANx)); + assert_param(IS_CAN_IDTYPE(TxMessage->IDE)); + assert_param(IS_CAN_RTR(TxMessage->RTR)); + assert_param(IS_CAN_DLC(TxMessage->DLC)); + + /* Select one empty transmit mailbox */ + if ((CANx->TSR&CAN_TSR_TME0) == CAN_TSR_TME0) + { + transmit_mailbox = 0; + } + else if ((CANx->TSR&CAN_TSR_TME1) == CAN_TSR_TME1) + { + transmit_mailbox = 1; + } + else if ((CANx->TSR&CAN_TSR_TME2) == CAN_TSR_TME2) + { + transmit_mailbox = 2; + } + else + { + transmit_mailbox = CAN_TxStatus_NoMailBox; + } + + if (transmit_mailbox != CAN_TxStatus_NoMailBox) + { + /* Set up the Id */ + CANx->sTxMailBox[transmit_mailbox].TIR &= TMIDxR_TXRQ; + if (TxMessage->IDE == CAN_Id_Standard) + { + assert_param(IS_CAN_STDID(TxMessage->StdId)); + CANx->sTxMailBox[transmit_mailbox].TIR |= ((TxMessage->StdId << 21) | \ + TxMessage->RTR); + } + else + { + assert_param(IS_CAN_EXTID(TxMessage->ExtId)); + CANx->sTxMailBox[transmit_mailbox].TIR |= ((TxMessage->ExtId << 3) | \ + TxMessage->IDE | \ + TxMessage->RTR); + } + + /* Set up the DLC */ + TxMessage->DLC &= (uint8_t)0x0000000F; + CANx->sTxMailBox[transmit_mailbox].TDTR &= (uint32_t)0xFFFFFFF0; + CANx->sTxMailBox[transmit_mailbox].TDTR |= TxMessage->DLC; + + /* Set up the data field */ + CANx->sTxMailBox[transmit_mailbox].TDLR = (((uint32_t)TxMessage->Data[3] << 24) | + ((uint32_t)TxMessage->Data[2] << 16) | + ((uint32_t)TxMessage->Data[1] << 8) | + ((uint32_t)TxMessage->Data[0])); + CANx->sTxMailBox[transmit_mailbox].TDHR = (((uint32_t)TxMessage->Data[7] << 24) | + ((uint32_t)TxMessage->Data[6] << 16) | + ((uint32_t)TxMessage->Data[5] << 8) | + ((uint32_t)TxMessage->Data[4])); + /* Request transmission */ + CANx->sTxMailBox[transmit_mailbox].TIR |= TMIDxR_TXRQ; + } + return transmit_mailbox; +} + +/** + * @brief Checks the transmission of a message. + * @param CANx: where x can be 1 or 2 to to select the + * CAN peripheral. + * @param TransmitMailbox: the number of the mailbox that is used for + * transmission. + * @retval CAN_TxStatus_Ok if the CAN driver transmits the message, CAN_TxStatus_Failed + * in an other case. + */ +uint8_t CAN_TransmitStatus(CAN_TypeDef* CANx, uint8_t TransmitMailbox) +{ + uint32_t state = 0; + + /* Check the parameters */ + assert_param(IS_CAN_ALL_PERIPH(CANx)); + assert_param(IS_CAN_TRANSMITMAILBOX(TransmitMailbox)); + + switch (TransmitMailbox) + { + case (CAN_TXMAILBOX_0): + state = CANx->TSR & (CAN_TSR_RQCP0 | CAN_TSR_TXOK0 | CAN_TSR_TME0); + break; + case (CAN_TXMAILBOX_1): + state = CANx->TSR & (CAN_TSR_RQCP1 | CAN_TSR_TXOK1 | CAN_TSR_TME1); + break; + case (CAN_TXMAILBOX_2): + state = CANx->TSR & (CAN_TSR_RQCP2 | CAN_TSR_TXOK2 | CAN_TSR_TME2); + break; + default: + state = CAN_TxStatus_Failed; + break; + } + switch (state) + { + /* transmit pending */ + case (0x0): state = CAN_TxStatus_Pending; + break; + /* transmit failed */ + case (CAN_TSR_RQCP0 | CAN_TSR_TME0): state = CAN_TxStatus_Failed; + break; + case (CAN_TSR_RQCP1 | CAN_TSR_TME1): state = CAN_TxStatus_Failed; + break; + case (CAN_TSR_RQCP2 | CAN_TSR_TME2): state = CAN_TxStatus_Failed; + break; + /* transmit succeeded */ + case (CAN_TSR_RQCP0 | CAN_TSR_TXOK0 | CAN_TSR_TME0):state = CAN_TxStatus_Ok; + break; + case (CAN_TSR_RQCP1 | CAN_TSR_TXOK1 | CAN_TSR_TME1):state = CAN_TxStatus_Ok; + break; + case (CAN_TSR_RQCP2 | CAN_TSR_TXOK2 | CAN_TSR_TME2):state = CAN_TxStatus_Ok; + break; + default: state = CAN_TxStatus_Failed; + break; + } + return (uint8_t) state; +} + +/** + * @brief Cancels a transmit request. + * @param CANx: where x can be 1 or 2 to to select the CAN peripheral. + * @param Mailbox: Mailbox number. + * @retval None. + */ +void CAN_CancelTransmit(CAN_TypeDef* CANx, uint8_t Mailbox) +{ + /* Check the parameters */ + assert_param(IS_CAN_ALL_PERIPH(CANx)); + assert_param(IS_CAN_TRANSMITMAILBOX(Mailbox)); + /* abort transmission */ + switch (Mailbox) + { + case (CAN_TXMAILBOX_0): CANx->TSR |= CAN_TSR_ABRQ0; + break; + case (CAN_TXMAILBOX_1): CANx->TSR |= CAN_TSR_ABRQ1; + break; + case (CAN_TXMAILBOX_2): CANx->TSR |= CAN_TSR_ABRQ2; + break; + default: + break; + } +} + + +/** + * @brief Receives a message. + * @param CANx: where x can be 1 or 2 to to select the CAN peripheral. + * @param FIFONumber: Receive FIFO number, CAN_FIFO0 or CAN_FIFO1. + * @param RxMessage: pointer to a structure receive message which contains + * CAN Id, CAN DLC, CAN datas and FMI number. + * @retval None. + */ +void CAN_Receive(CAN_TypeDef* CANx, uint8_t FIFONumber, CanRxMsg* RxMessage) +{ + /* Check the parameters */ + assert_param(IS_CAN_ALL_PERIPH(CANx)); + assert_param(IS_CAN_FIFO(FIFONumber)); + /* Get the Id */ + RxMessage->IDE = (uint8_t)0x04 & CANx->sFIFOMailBox[FIFONumber].RIR; + if (RxMessage->IDE == CAN_Id_Standard) + { + RxMessage->StdId = (uint32_t)0x000007FF & (CANx->sFIFOMailBox[FIFONumber].RIR >> 21); + } + else + { + RxMessage->ExtId = (uint32_t)0x1FFFFFFF & (CANx->sFIFOMailBox[FIFONumber].RIR >> 3); + } + + RxMessage->RTR = (uint8_t)0x02 & CANx->sFIFOMailBox[FIFONumber].RIR; + /* Get the DLC */ + RxMessage->DLC = (uint8_t)0x0F & CANx->sFIFOMailBox[FIFONumber].RDTR; + /* Get the FMI */ + RxMessage->FMI = (uint8_t)0xFF & (CANx->sFIFOMailBox[FIFONumber].RDTR >> 8); + /* Get the data field */ + RxMessage->Data[0] = (uint8_t)0xFF & CANx->sFIFOMailBox[FIFONumber].RDLR; + RxMessage->Data[1] = (uint8_t)0xFF & (CANx->sFIFOMailBox[FIFONumber].RDLR >> 8); + RxMessage->Data[2] = (uint8_t)0xFF & (CANx->sFIFOMailBox[FIFONumber].RDLR >> 16); + RxMessage->Data[3] = (uint8_t)0xFF & (CANx->sFIFOMailBox[FIFONumber].RDLR >> 24); + RxMessage->Data[4] = (uint8_t)0xFF & CANx->sFIFOMailBox[FIFONumber].RDHR; + RxMessage->Data[5] = (uint8_t)0xFF & (CANx->sFIFOMailBox[FIFONumber].RDHR >> 8); + RxMessage->Data[6] = (uint8_t)0xFF & (CANx->sFIFOMailBox[FIFONumber].RDHR >> 16); + RxMessage->Data[7] = (uint8_t)0xFF & (CANx->sFIFOMailBox[FIFONumber].RDHR >> 24); + /* Release the FIFO */ + /* Release FIFO0 */ + if (FIFONumber == CAN_FIFO0) + { + CANx->RF0R |= CAN_RF0R_RFOM0; + } + /* Release FIFO1 */ + else /* FIFONumber == CAN_FIFO1 */ + { + CANx->RF1R |= CAN_RF1R_RFOM1; + } +} + +/** + * @brief Releases the specified FIFO. + * @param CANx: where x can be 1 or 2 to to select the CAN peripheral. + * @param FIFONumber: FIFO to release, CAN_FIFO0 or CAN_FIFO1. + * @retval None. + */ +void CAN_FIFORelease(CAN_TypeDef* CANx, uint8_t FIFONumber) +{ + /* Check the parameters */ + assert_param(IS_CAN_ALL_PERIPH(CANx)); + assert_param(IS_CAN_FIFO(FIFONumber)); + /* Release FIFO0 */ + if (FIFONumber == CAN_FIFO0) + { + CANx->RF0R |= CAN_RF0R_RFOM0; + } + /* Release FIFO1 */ + else /* FIFONumber == CAN_FIFO1 */ + { + CANx->RF1R |= CAN_RF1R_RFOM1; + } +} + +/** + * @brief Returns the number of pending messages. + * @param CANx: where x can be 1 or 2 to to select the CAN peripheral. + * @param FIFONumber: Receive FIFO number, CAN_FIFO0 or CAN_FIFO1. + * @retval NbMessage : which is the number of pending message. + */ +uint8_t CAN_MessagePending(CAN_TypeDef* CANx, uint8_t FIFONumber) +{ + uint8_t message_pending=0; + /* Check the parameters */ + assert_param(IS_CAN_ALL_PERIPH(CANx)); + assert_param(IS_CAN_FIFO(FIFONumber)); + if (FIFONumber == CAN_FIFO0) + { + message_pending = (uint8_t)(CANx->RF0R&(uint32_t)0x03); + } + else if (FIFONumber == CAN_FIFO1) + { + message_pending = (uint8_t)(CANx->RF1R&(uint32_t)0x03); + } + else + { + message_pending = 0; + } + return message_pending; +} + + +/** + * @brief Select the CAN Operation mode. + * @param CAN_OperatingMode : CAN Operating Mode. This parameter can be one + * of @ref CAN_OperatingMode_TypeDef enumeration. + * @retval status of the requested mode which can be + * - CAN_ModeStatus_Failed CAN failed entering the specific mode + * - CAN_ModeStatus_Success CAN Succeed entering the specific mode + + */ +uint8_t CAN_OperatingModeRequest(CAN_TypeDef* CANx, uint8_t CAN_OperatingMode) +{ + uint8_t status = CAN_ModeStatus_Failed; + + /* Timeout for INAK or also for SLAK bits*/ + uint32_t timeout = INAK_TIMEOUT; + + /* Check the parameters */ + assert_param(IS_CAN_ALL_PERIPH(CANx)); + assert_param(IS_CAN_OPERATING_MODE(CAN_OperatingMode)); + + if (CAN_OperatingMode == CAN_OperatingMode_Initialization) + { + /* Request initialisation */ + CANx->MCR = (uint32_t)((CANx->MCR & (uint32_t)(~(uint32_t)CAN_MCR_SLEEP)) | CAN_MCR_INRQ); + + /* Wait the acknowledge */ + while (((CANx->MSR & CAN_MODE_MASK) != CAN_MSR_INAK) && (timeout != 0)) + { + timeout--; + } + if ((CANx->MSR & CAN_MODE_MASK) != CAN_MSR_INAK) + { + status = CAN_ModeStatus_Failed; + } + else + { + status = CAN_ModeStatus_Success; + } + } + else if (CAN_OperatingMode == CAN_OperatingMode_Normal) + { + /* Request leave initialisation and sleep mode and enter Normal mode */ + CANx->MCR &= (uint32_t)(~(CAN_MCR_SLEEP|CAN_MCR_INRQ)); + + /* Wait the acknowledge */ + while (((CANx->MSR & CAN_MODE_MASK) != 0) && (timeout!=0)) + { + timeout--; + } + if ((CANx->MSR & CAN_MODE_MASK) != 0) + { + status = CAN_ModeStatus_Failed; + } + else + { + status = CAN_ModeStatus_Success; + } + } + else if (CAN_OperatingMode == CAN_OperatingMode_Sleep) + { + /* Request Sleep mode */ + CANx->MCR = (uint32_t)((CANx->MCR & (uint32_t)(~(uint32_t)CAN_MCR_INRQ)) | CAN_MCR_SLEEP); + + /* Wait the acknowledge */ + while (((CANx->MSR & CAN_MODE_MASK) != CAN_MSR_SLAK) && (timeout!=0)) + { + timeout--; + } + if ((CANx->MSR & CAN_MODE_MASK) != CAN_MSR_SLAK) + { + status = CAN_ModeStatus_Failed; + } + else + { + status = CAN_ModeStatus_Success; + } + } + else + { + status = CAN_ModeStatus_Failed; + } + + return (uint8_t) status; +} + +/** + * @brief Enters the low power mode. + * @param CANx: where x can be 1 or 2 to to select the CAN peripheral. + * @retval status: CAN_Sleep_Ok if sleep entered, CAN_Sleep_Failed in an + * other case. + */ +uint8_t CAN_Sleep(CAN_TypeDef* CANx) +{ + uint8_t sleepstatus = CAN_Sleep_Failed; + + /* Check the parameters */ + assert_param(IS_CAN_ALL_PERIPH(CANx)); + + /* Request Sleep mode */ + CANx->MCR = (((CANx->MCR) & (uint32_t)(~(uint32_t)CAN_MCR_INRQ)) | CAN_MCR_SLEEP); + + /* Sleep mode status */ + if ((CANx->MSR & (CAN_MSR_SLAK|CAN_MSR_INAK)) == CAN_MSR_SLAK) + { + /* Sleep mode not entered */ + sleepstatus = CAN_Sleep_Ok; + } + /* return sleep mode status */ + return (uint8_t)sleepstatus; +} + +/** + * @brief Wakes the CAN up. + * @param CANx: where x can be 1 or 2 to to select the CAN peripheral. + * @retval status: CAN_WakeUp_Ok if sleep mode left, CAN_WakeUp_Failed in an + * other case. + */ +uint8_t CAN_WakeUp(CAN_TypeDef* CANx) +{ + uint32_t wait_slak = SLAK_TIMEOUT; + uint8_t wakeupstatus = CAN_WakeUp_Failed; + + /* Check the parameters */ + assert_param(IS_CAN_ALL_PERIPH(CANx)); + + /* Wake up request */ + CANx->MCR &= ~(uint32_t)CAN_MCR_SLEEP; + + /* Sleep mode status */ + while(((CANx->MSR & CAN_MSR_SLAK) == CAN_MSR_SLAK)&&(wait_slak!=0x00)) + { + wait_slak--; + } + if((CANx->MSR & CAN_MSR_SLAK) != CAN_MSR_SLAK) + { + /* wake up done : Sleep mode exited */ + wakeupstatus = CAN_WakeUp_Ok; + } + /* return wakeup status */ + return (uint8_t)wakeupstatus; +} + + +/** + * @brief Returns the CANx's last error code (LEC). + * @param CANx: where x can be 1 or 2 to to select the CAN peripheral. + * @retval CAN_ErrorCode: specifies the Error code : + * - CAN_ERRORCODE_NoErr No Error + * - CAN_ERRORCODE_StuffErr Stuff Error + * - CAN_ERRORCODE_FormErr Form Error + * - CAN_ERRORCODE_ACKErr Acknowledgment Error + * - CAN_ERRORCODE_BitRecessiveErr Bit Recessive Error + * - CAN_ERRORCODE_BitDominantErr Bit Dominant Error + * - CAN_ERRORCODE_CRCErr CRC Error + * - CAN_ERRORCODE_SoftwareSetErr Software Set Error + */ + +uint8_t CAN_GetLastErrorCode(CAN_TypeDef* CANx) +{ + uint8_t errorcode=0; + + /* Check the parameters */ + assert_param(IS_CAN_ALL_PERIPH(CANx)); + + /* Get the error code*/ + errorcode = (((uint8_t)CANx->ESR) & (uint8_t)CAN_ESR_LEC); + + /* Return the error code*/ + return errorcode; +} +/** + * @brief Returns the CANx Receive Error Counter (REC). + * @note In case of an error during reception, this counter is incremented + * by 1 or by 8 depending on the error condition as defined by the CAN + * standard. After every successful reception, the counter is + * decremented by 1 or reset to 120 if its value was higher than 128. + * When the counter value exceeds 127, the CAN controller enters the + * error passive state. + * @param CANx: where x can be 1 or 2 to to select the CAN peripheral. + * @retval CAN Receive Error Counter. + */ +uint8_t CAN_GetReceiveErrorCounter(CAN_TypeDef* CANx) +{ + uint8_t counter=0; + + /* Check the parameters */ + assert_param(IS_CAN_ALL_PERIPH(CANx)); + + /* Get the Receive Error Counter*/ + counter = (uint8_t)((CANx->ESR & CAN_ESR_REC)>> 24); + + /* Return the Receive Error Counter*/ + return counter; +} + + +/** + * @brief Returns the LSB of the 9-bit CANx Transmit Error Counter(TEC). + * @param CANx: where x can be 1 or 2 to to select the CAN peripheral. + * @retval LSB of the 9-bit CAN Transmit Error Counter. + */ +uint8_t CAN_GetLSBTransmitErrorCounter(CAN_TypeDef* CANx) +{ + uint8_t counter=0; + + /* Check the parameters */ + assert_param(IS_CAN_ALL_PERIPH(CANx)); + + /* Get the LSB of the 9-bit CANx Transmit Error Counter(TEC) */ + counter = (uint8_t)((CANx->ESR & CAN_ESR_TEC)>> 16); + + /* Return the LSB of the 9-bit CANx Transmit Error Counter(TEC) */ + return counter; +} + + +/** + * @brief Enables or disables the specified CANx interrupts. + * @param CANx: where x can be 1 or 2 to to select the CAN peripheral. + * @param CAN_IT: specifies the CAN interrupt sources to be enabled or disabled. + * This parameter can be: + * - CAN_IT_TME, + * - CAN_IT_FMP0, + * - CAN_IT_FF0, + * - CAN_IT_FOV0, + * - CAN_IT_FMP1, + * - CAN_IT_FF1, + * - CAN_IT_FOV1, + * - CAN_IT_EWG, + * - CAN_IT_EPV, + * - CAN_IT_LEC, + * - CAN_IT_ERR, + * - CAN_IT_WKU or + * - CAN_IT_SLK. + * @param NewState: new state of the CAN interrupts. + * This parameter can be: ENABLE or DISABLE. + * @retval None. + */ +void CAN_ITConfig(CAN_TypeDef* CANx, uint32_t CAN_IT, FunctionalState NewState) +{ + /* Check the parameters */ + assert_param(IS_CAN_ALL_PERIPH(CANx)); + assert_param(IS_CAN_IT(CAN_IT)); + assert_param(IS_FUNCTIONAL_STATE(NewState)); + + if (NewState != DISABLE) + { + /* Enable the selected CANx interrupt */ + CANx->IER |= CAN_IT; + } + else + { + /* Disable the selected CANx interrupt */ + CANx->IER &= ~CAN_IT; + } +} +/** + * @brief Checks whether the specified CAN flag is set or not. + * @param CANx: where x can be 1 or 2 to to select the CAN peripheral. + * @param CAN_FLAG: specifies the flag to check. + * This parameter can be one of the following flags: + * - CAN_FLAG_EWG + * - CAN_FLAG_EPV + * - CAN_FLAG_BOF + * - CAN_FLAG_RQCP0 + * - CAN_FLAG_RQCP1 + * - CAN_FLAG_RQCP2 + * - CAN_FLAG_FMP1 + * - CAN_FLAG_FF1 + * - CAN_FLAG_FOV1 + * - CAN_FLAG_FMP0 + * - CAN_FLAG_FF0 + * - CAN_FLAG_FOV0 + * - CAN_FLAG_WKU + * - CAN_FLAG_SLAK + * - CAN_FLAG_LEC + * @retval The new state of CAN_FLAG (SET or RESET). + */ +FlagStatus CAN_GetFlagStatus(CAN_TypeDef* CANx, uint32_t CAN_FLAG) +{ + FlagStatus bitstatus = RESET; + + /* Check the parameters */ + assert_param(IS_CAN_ALL_PERIPH(CANx)); + assert_param(IS_CAN_GET_FLAG(CAN_FLAG)); + + + if((CAN_FLAG & CAN_FLAGS_ESR) != (uint32_t)RESET) + { + /* Check the status of the specified CAN flag */ + if ((CANx->ESR & (CAN_FLAG & 0x000FFFFF)) != (uint32_t)RESET) + { + /* CAN_FLAG is set */ + bitstatus = SET; + } + else + { + /* CAN_FLAG is reset */ + bitstatus = RESET; + } + } + else if((CAN_FLAG & CAN_FLAGS_MSR) != (uint32_t)RESET) + { + /* Check the status of the specified CAN flag */ + if ((CANx->MSR & (CAN_FLAG & 0x000FFFFF)) != (uint32_t)RESET) + { + /* CAN_FLAG is set */ + bitstatus = SET; + } + else + { + /* CAN_FLAG is reset */ + bitstatus = RESET; + } + } + else if((CAN_FLAG & CAN_FLAGS_TSR) != (uint32_t)RESET) + { + /* Check the status of the specified CAN flag */ + if ((CANx->TSR & (CAN_FLAG & 0x000FFFFF)) != (uint32_t)RESET) + { + /* CAN_FLAG is set */ + bitstatus = SET; + } + else + { + /* CAN_FLAG is reset */ + bitstatus = RESET; + } + } + else if((CAN_FLAG & CAN_FLAGS_RF0R) != (uint32_t)RESET) + { + /* Check the status of the specified CAN flag */ + if ((CANx->RF0R & (CAN_FLAG & 0x000FFFFF)) != (uint32_t)RESET) + { + /* CAN_FLAG is set */ + bitstatus = SET; + } + else + { + /* CAN_FLAG is reset */ + bitstatus = RESET; + } + } + else /* If(CAN_FLAG & CAN_FLAGS_RF1R != (uint32_t)RESET) */ + { + /* Check the status of the specified CAN flag */ + if ((uint32_t)(CANx->RF1R & (CAN_FLAG & 0x000FFFFF)) != (uint32_t)RESET) + { + /* CAN_FLAG is set */ + bitstatus = SET; + } + else + { + /* CAN_FLAG is reset */ + bitstatus = RESET; + } + } + /* Return the CAN_FLAG status */ + return bitstatus; +} + +/** + * @brief Clears the CAN's pending flags. + * @param CANx: where x can be 1 or 2 to to select the CAN peripheral. + * @param CAN_FLAG: specifies the flag to clear. + * This parameter can be one of the following flags: + * - CAN_FLAG_RQCP0 + * - CAN_FLAG_RQCP1 + * - CAN_FLAG_RQCP2 + * - CAN_FLAG_FF1 + * - CAN_FLAG_FOV1 + * - CAN_FLAG_FF0 + * - CAN_FLAG_FOV0 + * - CAN_FLAG_WKU + * - CAN_FLAG_SLAK + * - CAN_FLAG_LEC + * @retval None. + */ +void CAN_ClearFlag(CAN_TypeDef* CANx, uint32_t CAN_FLAG) +{ + uint32_t flagtmp=0; + /* Check the parameters */ + assert_param(IS_CAN_ALL_PERIPH(CANx)); + assert_param(IS_CAN_CLEAR_FLAG(CAN_FLAG)); + + if (CAN_FLAG == CAN_FLAG_LEC) /* ESR register */ + { + /* Clear the selected CAN flags */ + CANx->ESR = (uint32_t)RESET; + } + else /* MSR or TSR or RF0R or RF1R */ + { + flagtmp = CAN_FLAG & 0x000FFFFF; + + if ((CAN_FLAG & CAN_FLAGS_RF0R)!=(uint32_t)RESET) + { + /* Receive Flags */ + CANx->RF0R = (uint32_t)(flagtmp); + } + else if ((CAN_FLAG & CAN_FLAGS_RF1R)!=(uint32_t)RESET) + { + /* Receive Flags */ + CANx->RF1R = (uint32_t)(flagtmp); + } + else if ((CAN_FLAG & CAN_FLAGS_TSR)!=(uint32_t)RESET) + { + /* Transmit Flags */ + CANx->TSR = (uint32_t)(flagtmp); + } + else /* If((CAN_FLAG & CAN_FLAGS_MSR)!=(uint32_t)RESET) */ + { + /* Operating mode Flags */ + CANx->MSR = (uint32_t)(flagtmp); + } + } +} + +/** + * @brief Checks whether the specified CANx interrupt has occurred or not. + * @param CANx: where x can be 1 or 2 to to select the CAN peripheral. + * @param CAN_IT: specifies the CAN interrupt source to check. + * This parameter can be one of the following flags: + * - CAN_IT_TME + * - CAN_IT_FMP0 + * - CAN_IT_FF0 + * - CAN_IT_FOV0 + * - CAN_IT_FMP1 + * - CAN_IT_FF1 + * - CAN_IT_FOV1 + * - CAN_IT_WKU + * - CAN_IT_SLK + * - CAN_IT_EWG + * - CAN_IT_EPV + * - CAN_IT_BOF + * - CAN_IT_LEC + * - CAN_IT_ERR + * @retval The current state of CAN_IT (SET or RESET). + */ +ITStatus CAN_GetITStatus(CAN_TypeDef* CANx, uint32_t CAN_IT) +{ + ITStatus itstatus = RESET; + /* Check the parameters */ + assert_param(IS_CAN_ALL_PERIPH(CANx)); + assert_param(IS_CAN_IT(CAN_IT)); + + /* check the enable interrupt bit */ + if((CANx->IER & CAN_IT) != RESET) + { + /* in case the Interrupt is enabled, .... */ + switch (CAN_IT) + { + case CAN_IT_TME: + /* Check CAN_TSR_RQCPx bits */ + itstatus = CheckITStatus(CANx->TSR, CAN_TSR_RQCP0|CAN_TSR_RQCP1|CAN_TSR_RQCP2); + break; + case CAN_IT_FMP0: + /* Check CAN_RF0R_FMP0 bit */ + itstatus = CheckITStatus(CANx->RF0R, CAN_RF0R_FMP0); + break; + case CAN_IT_FF0: + /* Check CAN_RF0R_FULL0 bit */ + itstatus = CheckITStatus(CANx->RF0R, CAN_RF0R_FULL0); + break; + case CAN_IT_FOV0: + /* Check CAN_RF0R_FOVR0 bit */ + itstatus = CheckITStatus(CANx->RF0R, CAN_RF0R_FOVR0); + break; + case CAN_IT_FMP1: + /* Check CAN_RF1R_FMP1 bit */ + itstatus = CheckITStatus(CANx->RF1R, CAN_RF1R_FMP1); + break; + case CAN_IT_FF1: + /* Check CAN_RF1R_FULL1 bit */ + itstatus = CheckITStatus(CANx->RF1R, CAN_RF1R_FULL1); + break; + case CAN_IT_FOV1: + /* Check CAN_RF1R_FOVR1 bit */ + itstatus = CheckITStatus(CANx->RF1R, CAN_RF1R_FOVR1); + break; + case CAN_IT_WKU: + /* Check CAN_MSR_WKUI bit */ + itstatus = CheckITStatus(CANx->MSR, CAN_MSR_WKUI); + break; + case CAN_IT_SLK: + /* Check CAN_MSR_SLAKI bit */ + itstatus = CheckITStatus(CANx->MSR, CAN_MSR_SLAKI); + break; + case CAN_IT_EWG: + /* Check CAN_ESR_EWGF bit */ + itstatus = CheckITStatus(CANx->ESR, CAN_ESR_EWGF); + break; + case CAN_IT_EPV: + /* Check CAN_ESR_EPVF bit */ + itstatus = CheckITStatus(CANx->ESR, CAN_ESR_EPVF); + break; + case CAN_IT_BOF: + /* Check CAN_ESR_BOFF bit */ + itstatus = CheckITStatus(CANx->ESR, CAN_ESR_BOFF); + break; + case CAN_IT_LEC: + /* Check CAN_ESR_LEC bit */ + itstatus = CheckITStatus(CANx->ESR, CAN_ESR_LEC); + break; + case CAN_IT_ERR: + /* Check CAN_MSR_ERRI bit */ + itstatus = CheckITStatus(CANx->MSR, CAN_MSR_ERRI); + break; + default : + /* in case of error, return RESET */ + itstatus = RESET; + break; + } + } + else + { + /* in case the Interrupt is not enabled, return RESET */ + itstatus = RESET; + } + + /* Return the CAN_IT status */ + return itstatus; +} + +/** + * @brief Clears the CANx's interrupt pending bits. + * @param CANx: where x can be 1 or 2 to to select the CAN peripheral. + * @param CAN_IT: specifies the interrupt pending bit to clear. + * - CAN_IT_TME + * - CAN_IT_FF0 + * - CAN_IT_FOV0 + * - CAN_IT_FF1 + * - CAN_IT_FOV1 + * - CAN_IT_WKU + * - CAN_IT_SLK + * - CAN_IT_EWG + * - CAN_IT_EPV + * - CAN_IT_BOF + * - CAN_IT_LEC + * - CAN_IT_ERR + * @retval None. + */ +void CAN_ClearITPendingBit(CAN_TypeDef* CANx, uint32_t CAN_IT) +{ + /* Check the parameters */ + assert_param(IS_CAN_ALL_PERIPH(CANx)); + assert_param(IS_CAN_CLEAR_IT(CAN_IT)); + + switch (CAN_IT) + { + case CAN_IT_TME: + /* Clear CAN_TSR_RQCPx (rc_w1)*/ + CANx->TSR = CAN_TSR_RQCP0|CAN_TSR_RQCP1|CAN_TSR_RQCP2; + break; + case CAN_IT_FF0: + /* Clear CAN_RF0R_FULL0 (rc_w1)*/ + CANx->RF0R = CAN_RF0R_FULL0; + break; + case CAN_IT_FOV0: + /* Clear CAN_RF0R_FOVR0 (rc_w1)*/ + CANx->RF0R = CAN_RF0R_FOVR0; + break; + case CAN_IT_FF1: + /* Clear CAN_RF1R_FULL1 (rc_w1)*/ + CANx->RF1R = CAN_RF1R_FULL1; + break; + case CAN_IT_FOV1: + /* Clear CAN_RF1R_FOVR1 (rc_w1)*/ + CANx->RF1R = CAN_RF1R_FOVR1; + break; + case CAN_IT_WKU: + /* Clear CAN_MSR_WKUI (rc_w1)*/ + CANx->MSR = CAN_MSR_WKUI; + break; + case CAN_IT_SLK: + /* Clear CAN_MSR_SLAKI (rc_w1)*/ + CANx->MSR = CAN_MSR_SLAKI; + break; + case CAN_IT_EWG: + /* Clear CAN_MSR_ERRI (rc_w1) */ + CANx->MSR = CAN_MSR_ERRI; + /* Note : the corresponding Flag is cleared by hardware depending + of the CAN Bus status*/ + break; + case CAN_IT_EPV: + /* Clear CAN_MSR_ERRI (rc_w1) */ + CANx->MSR = CAN_MSR_ERRI; + /* Note : the corresponding Flag is cleared by hardware depending + of the CAN Bus status*/ + break; + case CAN_IT_BOF: + /* Clear CAN_MSR_ERRI (rc_w1) */ + CANx->MSR = CAN_MSR_ERRI; + /* Note : the corresponding Flag is cleared by hardware depending + of the CAN Bus status*/ + break; + case CAN_IT_LEC: + /* Clear LEC bits */ + CANx->ESR = RESET; + /* Clear CAN_MSR_ERRI (rc_w1) */ + CANx->MSR = CAN_MSR_ERRI; + break; + case CAN_IT_ERR: + /*Clear LEC bits */ + CANx->ESR = RESET; + /* Clear CAN_MSR_ERRI (rc_w1) */ + CANx->MSR = CAN_MSR_ERRI; + /* Note : BOFF, EPVF and EWGF Flags are cleared by hardware depending + of the CAN Bus status*/ + break; + default : + break; + } +} + +/** + * @brief Checks whether the CAN interrupt has occurred or not. + * @param CAN_Reg: specifies the CAN interrupt register to check. + * @param It_Bit: specifies the interrupt source bit to check. + * @retval The new state of the CAN Interrupt (SET or RESET). + */ +static ITStatus CheckITStatus(uint32_t CAN_Reg, uint32_t It_Bit) +{ + ITStatus pendingbitstatus = RESET; + + if ((CAN_Reg & It_Bit) != (uint32_t)RESET) + { + /* CAN_IT is set */ + pendingbitstatus = SET; + } + else + { + /* CAN_IT is reset */ + pendingbitstatus = RESET; + } + return pendingbitstatus; +} + + +/** + * @} + */ + +/** + * @} + */ + +/** + * @} + */ + +/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ diff --git a/Libraries/STM32F10x_StdPeriph_Driver/src/stm32f10x_cec.c b/Libraries/STM32F10x_StdPeriph_Driver/src/stm32f10x_cec.c new file mode 100644 index 0000000..ac731dd --- /dev/null +++ b/Libraries/STM32F10x_StdPeriph_Driver/src/stm32f10x_cec.c @@ -0,0 +1,439 @@ +/** + ****************************************************************************** + * @file stm32f10x_cec.c + * @author MCD Application Team + * @version V3.6.1 + * @date 05-March-2012 + * @brief This file provides all the CEC firmware functions. + ****************************************************************************** + * @attention + * + *

    © COPYRIGHT 2012 STMicroelectronics

    + * + * Licensed under MCD-ST Liberty SW License Agreement V2, (the "License"); + * You may not use this file except in compliance with the License. + * You may obtain a copy of the License at: + * + * http://www.st.com/software_license_agreement_liberty_v2 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, + * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + * + ****************************************************************************** + */ + +/* Includes ------------------------------------------------------------------*/ +#include "stm32f10x_cec.h" +#include "stm32f10x_rcc.h" + +/** @addtogroup STM32F10x_StdPeriph_Driver + * @{ + */ + +/** @defgroup CEC + * @brief CEC driver modules + * @{ + */ + +/** @defgroup CEC_Private_TypesDefinitions + * @{ + */ + +/** + * @} + */ + + +/** @defgroup CEC_Private_Defines + * @{ + */ + +/* ------------ CEC registers bit address in the alias region ----------- */ +#define CEC_OFFSET (CEC_BASE - PERIPH_BASE) + +/* --- CFGR Register ---*/ + +/* Alias word address of PE bit */ +#define CFGR_OFFSET (CEC_OFFSET + 0x00) +#define PE_BitNumber 0x00 +#define CFGR_PE_BB (PERIPH_BB_BASE + (CFGR_OFFSET * 32) + (PE_BitNumber * 4)) + +/* Alias word address of IE bit */ +#define IE_BitNumber 0x01 +#define CFGR_IE_BB (PERIPH_BB_BASE + (CFGR_OFFSET * 32) + (IE_BitNumber * 4)) + +/* --- CSR Register ---*/ + +/* Alias word address of TSOM bit */ +#define CSR_OFFSET (CEC_OFFSET + 0x10) +#define TSOM_BitNumber 0x00 +#define CSR_TSOM_BB (PERIPH_BB_BASE + (CSR_OFFSET * 32) + (TSOM_BitNumber * 4)) + +/* Alias word address of TEOM bit */ +#define TEOM_BitNumber 0x01 +#define CSR_TEOM_BB (PERIPH_BB_BASE + (CSR_OFFSET * 32) + (TEOM_BitNumber * 4)) + +#define CFGR_CLEAR_Mask (uint8_t)(0xF3) /* CFGR register Mask */ +#define FLAG_Mask ((uint32_t)0x00FFFFFF) /* CEC FLAG mask */ + +/** + * @} + */ + + +/** @defgroup CEC_Private_Macros + * @{ + */ + +/** + * @} + */ + + +/** @defgroup CEC_Private_Variables + * @{ + */ + +/** + * @} + */ + + +/** @defgroup CEC_Private_FunctionPrototypes + * @{ + */ + +/** + * @} + */ + + +/** @defgroup CEC_Private_Functions + * @{ + */ + +/** + * @brief Deinitializes the CEC peripheral registers to their default reset + * values. + * @param None + * @retval None + */ +void CEC_DeInit(void) +{ + /* Enable CEC reset state */ + RCC_APB1PeriphResetCmd(RCC_APB1Periph_CEC, ENABLE); + /* Release CEC from reset state */ + RCC_APB1PeriphResetCmd(RCC_APB1Periph_CEC, DISABLE); +} + + +/** + * @brief Initializes the CEC peripheral according to the specified + * parameters in the CEC_InitStruct. + * @param CEC_InitStruct: pointer to an CEC_InitTypeDef structure that + * contains the configuration information for the specified + * CEC peripheral. + * @retval None + */ +void CEC_Init(CEC_InitTypeDef* CEC_InitStruct) +{ + uint16_t tmpreg = 0; + + /* Check the parameters */ + assert_param(IS_CEC_BIT_TIMING_ERROR_MODE(CEC_InitStruct->CEC_BitTimingMode)); + assert_param(IS_CEC_BIT_PERIOD_ERROR_MODE(CEC_InitStruct->CEC_BitPeriodMode)); + + /*---------------------------- CEC CFGR Configuration -----------------*/ + /* Get the CEC CFGR value */ + tmpreg = CEC->CFGR; + + /* Clear BTEM and BPEM bits */ + tmpreg &= CFGR_CLEAR_Mask; + + /* Configure CEC: Bit Timing Error and Bit Period Error */ + tmpreg |= (uint16_t)(CEC_InitStruct->CEC_BitTimingMode | CEC_InitStruct->CEC_BitPeriodMode); + + /* Write to CEC CFGR register*/ + CEC->CFGR = tmpreg; + +} + +/** + * @brief Enables or disables the specified CEC peripheral. + * @param NewState: new state of the CEC peripheral. + * This parameter can be: ENABLE or DISABLE. + * @retval None + */ +void CEC_Cmd(FunctionalState NewState) +{ + /* Check the parameters */ + assert_param(IS_FUNCTIONAL_STATE(NewState)); + + *(__IO uint32_t *) CFGR_PE_BB = (uint32_t)NewState; + + if(NewState == DISABLE) + { + /* Wait until the PE bit is cleared by hardware (Idle Line detected) */ + while((CEC->CFGR & CEC_CFGR_PE) != (uint32_t)RESET) + { + } + } +} + +/** + * @brief Enables or disables the CEC interrupt. + * @param NewState: new state of the CEC interrupt. + * This parameter can be: ENABLE or DISABLE. + * @retval None + */ +void CEC_ITConfig(FunctionalState NewState) +{ + /* Check the parameters */ + assert_param(IS_FUNCTIONAL_STATE(NewState)); + + *(__IO uint32_t *) CFGR_IE_BB = (uint32_t)NewState; +} + +/** + * @brief Defines the Own Address of the CEC device. + * @param CEC_OwnAddress: The CEC own address + * @retval None + */ +void CEC_OwnAddressConfig(uint8_t CEC_OwnAddress) +{ + /* Check the parameters */ + assert_param(IS_CEC_ADDRESS(CEC_OwnAddress)); + + /* Set the CEC own address */ + CEC->OAR = CEC_OwnAddress; +} + +/** + * @brief Sets the CEC prescaler value. + * @param CEC_Prescaler: CEC prescaler new value + * @retval None + */ +void CEC_SetPrescaler(uint16_t CEC_Prescaler) +{ + /* Check the parameters */ + assert_param(IS_CEC_PRESCALER(CEC_Prescaler)); + + /* Set the Prescaler value*/ + CEC->PRES = CEC_Prescaler; +} + +/** + * @brief Transmits single data through the CEC peripheral. + * @param Data: the data to transmit. + * @retval None + */ +void CEC_SendDataByte(uint8_t Data) +{ + /* Transmit Data */ + CEC->TXD = Data ; +} + + +/** + * @brief Returns the most recent received data by the CEC peripheral. + * @param None + * @retval The received data. + */ +uint8_t CEC_ReceiveDataByte(void) +{ + /* Receive Data */ + return (uint8_t)(CEC->RXD); +} + +/** + * @brief Starts a new message. + * @param None + * @retval None + */ +void CEC_StartOfMessage(void) +{ + /* Starts of new message */ + *(__IO uint32_t *) CSR_TSOM_BB = (uint32_t)0x1; +} + +/** + * @brief Transmits message with or without an EOM bit. + * @param NewState: new state of the CEC Tx End Of Message. + * This parameter can be: ENABLE or DISABLE. + * @retval None + */ +void CEC_EndOfMessageCmd(FunctionalState NewState) +{ + /* Check the parameters */ + assert_param(IS_FUNCTIONAL_STATE(NewState)); + + /* The data byte will be transmitted with or without an EOM bit*/ + *(__IO uint32_t *) CSR_TEOM_BB = (uint32_t)NewState; +} + +/** + * @brief Gets the CEC flag status + * @param CEC_FLAG: specifies the CEC flag to check. + * This parameter can be one of the following values: + * @arg CEC_FLAG_BTE: Bit Timing Error + * @arg CEC_FLAG_BPE: Bit Period Error + * @arg CEC_FLAG_RBTFE: Rx Block Transfer Finished Error + * @arg CEC_FLAG_SBE: Start Bit Error + * @arg CEC_FLAG_ACKE: Block Acknowledge Error + * @arg CEC_FLAG_LINE: Line Error + * @arg CEC_FLAG_TBTFE: Tx Block Transfer Finished Error + * @arg CEC_FLAG_TEOM: Tx End Of Message + * @arg CEC_FLAG_TERR: Tx Error + * @arg CEC_FLAG_TBTRF: Tx Byte Transfer Request or Block Transfer Finished + * @arg CEC_FLAG_RSOM: Rx Start Of Message + * @arg CEC_FLAG_REOM: Rx End Of Message + * @arg CEC_FLAG_RERR: Rx Error + * @arg CEC_FLAG_RBTF: Rx Byte/Block Transfer Finished + * @retval The new state of CEC_FLAG (SET or RESET) + */ +FlagStatus CEC_GetFlagStatus(uint32_t CEC_FLAG) +{ + FlagStatus bitstatus = RESET; + uint32_t cecreg = 0, cecbase = 0; + + /* Check the parameters */ + assert_param(IS_CEC_GET_FLAG(CEC_FLAG)); + + /* Get the CEC peripheral base address */ + cecbase = (uint32_t)(CEC_BASE); + + /* Read flag register index */ + cecreg = CEC_FLAG >> 28; + + /* Get bit[23:0] of the flag */ + CEC_FLAG &= FLAG_Mask; + + if(cecreg != 0) + { + /* Flag in CEC ESR Register */ + CEC_FLAG = (uint32_t)(CEC_FLAG >> 16); + + /* Get the CEC ESR register address */ + cecbase += 0xC; + } + else + { + /* Get the CEC CSR register address */ + cecbase += 0x10; + } + + if(((*(__IO uint32_t *)cecbase) & CEC_FLAG) != (uint32_t)RESET) + { + /* CEC_FLAG is set */ + bitstatus = SET; + } + else + { + /* CEC_FLAG is reset */ + bitstatus = RESET; + } + + /* Return the CEC_FLAG status */ + return bitstatus; +} + +/** + * @brief Clears the CEC's pending flags. + * @param CEC_FLAG: specifies the flag to clear. + * This parameter can be any combination of the following values: + * @arg CEC_FLAG_TERR: Tx Error + * @arg CEC_FLAG_TBTRF: Tx Byte Transfer Request or Block Transfer Finished + * @arg CEC_FLAG_RSOM: Rx Start Of Message + * @arg CEC_FLAG_REOM: Rx End Of Message + * @arg CEC_FLAG_RERR: Rx Error + * @arg CEC_FLAG_RBTF: Rx Byte/Block Transfer Finished + * @retval None + */ +void CEC_ClearFlag(uint32_t CEC_FLAG) +{ + uint32_t tmp = 0x0; + + /* Check the parameters */ + assert_param(IS_CEC_CLEAR_FLAG(CEC_FLAG)); + + tmp = CEC->CSR & 0x2; + + /* Clear the selected CEC flags */ + CEC->CSR &= (uint32_t)(((~(uint32_t)CEC_FLAG) & 0xFFFFFFFC) | tmp); +} + +/** + * @brief Checks whether the specified CEC interrupt has occurred or not. + * @param CEC_IT: specifies the CEC interrupt source to check. + * This parameter can be one of the following values: + * @arg CEC_IT_TERR: Tx Error + * @arg CEC_IT_TBTF: Tx Block Transfer Finished + * @arg CEC_IT_RERR: Rx Error + * @arg CEC_IT_RBTF: Rx Block Transfer Finished + * @retval The new state of CEC_IT (SET or RESET). + */ +ITStatus CEC_GetITStatus(uint8_t CEC_IT) +{ + ITStatus bitstatus = RESET; + uint32_t enablestatus = 0; + + /* Check the parameters */ + assert_param(IS_CEC_GET_IT(CEC_IT)); + + /* Get the CEC IT enable bit status */ + enablestatus = (CEC->CFGR & (uint8_t)CEC_CFGR_IE) ; + + /* Check the status of the specified CEC interrupt */ + if (((CEC->CSR & CEC_IT) != (uint32_t)RESET) && enablestatus) + { + /* CEC_IT is set */ + bitstatus = SET; + } + else + { + /* CEC_IT is reset */ + bitstatus = RESET; + } + /* Return the CEC_IT status */ + return bitstatus; +} + +/** + * @brief Clears the CEC's interrupt pending bits. + * @param CEC_IT: specifies the CEC interrupt pending bit to clear. + * This parameter can be any combination of the following values: + * @arg CEC_IT_TERR: Tx Error + * @arg CEC_IT_TBTF: Tx Block Transfer Finished + * @arg CEC_IT_RERR: Rx Error + * @arg CEC_IT_RBTF: Rx Block Transfer Finished + * @retval None + */ +void CEC_ClearITPendingBit(uint16_t CEC_IT) +{ + uint32_t tmp = 0x0; + + /* Check the parameters */ + assert_param(IS_CEC_GET_IT(CEC_IT)); + + tmp = CEC->CSR & 0x2; + + /* Clear the selected CEC interrupt pending bits */ + CEC->CSR &= (uint32_t)(((~(uint32_t)CEC_IT) & 0xFFFFFFFC) | tmp); +} + +/** + * @} + */ + +/** + * @} + */ + +/** + * @} + */ + +/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ diff --git a/Libraries/STM32F10x_StdPeriph_Driver/src/stm32f10x_crc.c b/Libraries/STM32F10x_StdPeriph_Driver/src/stm32f10x_crc.c new file mode 100644 index 0000000..70cabd5 --- /dev/null +++ b/Libraries/STM32F10x_StdPeriph_Driver/src/stm32f10x_crc.c @@ -0,0 +1,166 @@ +/** + ****************************************************************************** + * @file stm32f10x_crc.c + * @author MCD Application Team + * @version V3.6.1 + * @date 05-March-2012 + * @brief This file provides all the CRC firmware functions. + ****************************************************************************** + * @attention + * + *

    © COPYRIGHT 2012 STMicroelectronics

    + * + * Licensed under MCD-ST Liberty SW License Agreement V2, (the "License"); + * You may not use this file except in compliance with the License. + * You may obtain a copy of the License at: + * + * http://www.st.com/software_license_agreement_liberty_v2 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, + * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + * + ****************************************************************************** + */ + +/* Includes ------------------------------------------------------------------*/ +#include "stm32f10x_crc.h" + +/** @addtogroup STM32F10x_StdPeriph_Driver + * @{ + */ + +/** @defgroup CRC + * @brief CRC driver modules + * @{ + */ + +/** @defgroup CRC_Private_TypesDefinitions + * @{ + */ + +/** + * @} + */ + +/** @defgroup CRC_Private_Defines + * @{ + */ + +/** + * @} + */ + +/** @defgroup CRC_Private_Macros + * @{ + */ + +/** + * @} + */ + +/** @defgroup CRC_Private_Variables + * @{ + */ + +/** + * @} + */ + +/** @defgroup CRC_Private_FunctionPrototypes + * @{ + */ + +/** + * @} + */ + +/** @defgroup CRC_Private_Functions + * @{ + */ + +/** + * @brief Resets the CRC Data register (DR). + * @param None + * @retval None + */ +void CRC_ResetDR(void) +{ + /* Reset CRC generator */ + CRC->CR = CRC_CR_RESET; +} + +/** + * @brief Computes the 32-bit CRC of a given data word(32-bit). + * @param Data: data word(32-bit) to compute its CRC + * @retval 32-bit CRC + */ +uint32_t CRC_CalcCRC(uint32_t Data) +{ + CRC->DR = Data; + + return (CRC->DR); +} + +/** + * @brief Computes the 32-bit CRC of a given buffer of data word(32-bit). + * @param pBuffer: pointer to the buffer containing the data to be computed + * @param BufferLength: length of the buffer to be computed + * @retval 32-bit CRC + */ +uint32_t CRC_CalcBlockCRC(uint32_t pBuffer[], uint32_t BufferLength) +{ + uint32_t index = 0; + + for(index = 0; index < BufferLength; index++) + { + CRC->DR = pBuffer[index]; + } + return (CRC->DR); +} + +/** + * @brief Returns the current CRC value. + * @param None + * @retval 32-bit CRC + */ +uint32_t CRC_GetCRC(void) +{ + return (CRC->DR); +} + +/** + * @brief Stores a 8-bit data in the Independent Data(ID) register. + * @param IDValue: 8-bit value to be stored in the ID register + * @retval None + */ +void CRC_SetIDRegister(uint8_t IDValue) +{ + CRC->IDR = IDValue; +} + +/** + * @brief Returns the 8-bit data stored in the Independent Data(ID) register + * @param None + * @retval 8-bit value of the ID register + */ +uint8_t CRC_GetIDRegister(void) +{ + return (CRC->IDR); +} + +/** + * @} + */ + +/** + * @} + */ + +/** + * @} + */ + +/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ diff --git a/Libraries/STM32F10x_StdPeriph_Driver/src/stm32f10x_dac.c b/Libraries/STM32F10x_StdPeriph_Driver/src/stm32f10x_dac.c new file mode 100644 index 0000000..bc56ef1 --- /dev/null +++ b/Libraries/STM32F10x_StdPeriph_Driver/src/stm32f10x_dac.c @@ -0,0 +1,577 @@ +/** + ****************************************************************************** + * @file stm32f10x_dac.c + * @author MCD Application Team + * @version V3.6.1 + * @date 05-March-2012 + * @brief This file provides all the DAC firmware functions. + ****************************************************************************** + * @attention + * + *

    © COPYRIGHT 2012 STMicroelectronics

    + * + * Licensed under MCD-ST Liberty SW License Agreement V2, (the "License"); + * You may not use this file except in compliance with the License. + * You may obtain a copy of the License at: + * + * http://www.st.com/software_license_agreement_liberty_v2 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, + * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + * + ****************************************************************************** + */ + +/* Includes ------------------------------------------------------------------*/ +#include "stm32f10x_dac.h" +#include "stm32f10x_rcc.h" + +/** @addtogroup STM32F10x_StdPeriph_Driver + * @{ + */ + +/** @defgroup DAC + * @brief DAC driver modules + * @{ + */ + +/** @defgroup DAC_Private_TypesDefinitions + * @{ + */ + +/** + * @} + */ + +/** @defgroup DAC_Private_Defines + * @{ + */ + +/* CR register Mask */ +#define CR_CLEAR_MASK ((uint32_t)0x00000FFE) + +/* DAC Dual Channels SWTRIG masks */ +#define DUAL_SWTRIG_SET ((uint32_t)0x00000003) +#define DUAL_SWTRIG_RESET ((uint32_t)0xFFFFFFFC) + +/* DHR registers offsets */ +#define DHR12R1_OFFSET ((uint32_t)0x00000008) +#define DHR12R2_OFFSET ((uint32_t)0x00000014) +#define DHR12RD_OFFSET ((uint32_t)0x00000020) + +/* DOR register offset */ +#define DOR_OFFSET ((uint32_t)0x0000002C) +/** + * @} + */ + +/** @defgroup DAC_Private_Macros + * @{ + */ + +/** + * @} + */ + +/** @defgroup DAC_Private_Variables + * @{ + */ + +/** + * @} + */ + +/** @defgroup DAC_Private_FunctionPrototypes + * @{ + */ + +/** + * @} + */ + +/** @defgroup DAC_Private_Functions + * @{ + */ + +/** + * @brief Deinitializes the DAC peripheral registers to their default reset values. + * @param None + * @retval None + */ +void DAC_DeInit(void) +{ + /* Enable DAC reset state */ + RCC_APB1PeriphResetCmd(RCC_APB1Periph_DAC, ENABLE); + /* Release DAC from reset state */ + RCC_APB1PeriphResetCmd(RCC_APB1Periph_DAC, DISABLE); +} + +/** + * @brief Initializes the DAC peripheral according to the specified + * parameters in the DAC_InitStruct. + * @param DAC_Channel: the selected DAC channel. + * This parameter can be one of the following values: + * @arg DAC_Channel_1: DAC Channel1 selected + * @arg DAC_Channel_2: DAC Channel2 selected + * @param DAC_InitStruct: pointer to a DAC_InitTypeDef structure that + * contains the configuration information for the specified DAC channel. + * @retval None + */ +void DAC_Init(uint32_t DAC_Channel, DAC_InitTypeDef* DAC_InitStruct) +{ + uint32_t tmpreg1 = 0, tmpreg2 = 0; + /* Check the DAC parameters */ + assert_param(IS_DAC_TRIGGER(DAC_InitStruct->DAC_Trigger)); + assert_param(IS_DAC_GENERATE_WAVE(DAC_InitStruct->DAC_WaveGeneration)); + assert_param(IS_DAC_LFSR_UNMASK_TRIANGLE_AMPLITUDE(DAC_InitStruct->DAC_LFSRUnmask_TriangleAmplitude)); + assert_param(IS_DAC_OUTPUT_BUFFER_STATE(DAC_InitStruct->DAC_OutputBuffer)); +/*---------------------------- DAC CR Configuration --------------------------*/ + /* Get the DAC CR value */ + tmpreg1 = DAC->CR; + /* Clear BOFFx, TENx, TSELx, WAVEx and MAMPx bits */ + tmpreg1 &= ~(CR_CLEAR_MASK << DAC_Channel); + /* Configure for the selected DAC channel: buffer output, trigger, wave generation, + mask/amplitude for wave generation */ + /* Set TSELx and TENx bits according to DAC_Trigger value */ + /* Set WAVEx bits according to DAC_WaveGeneration value */ + /* Set MAMPx bits according to DAC_LFSRUnmask_TriangleAmplitude value */ + /* Set BOFFx bit according to DAC_OutputBuffer value */ + tmpreg2 = (DAC_InitStruct->DAC_Trigger | DAC_InitStruct->DAC_WaveGeneration | + DAC_InitStruct->DAC_LFSRUnmask_TriangleAmplitude | DAC_InitStruct->DAC_OutputBuffer); + /* Calculate CR register value depending on DAC_Channel */ + tmpreg1 |= tmpreg2 << DAC_Channel; + /* Write to DAC CR */ + DAC->CR = tmpreg1; +} + +/** + * @brief Fills each DAC_InitStruct member with its default value. + * @param DAC_InitStruct : pointer to a DAC_InitTypeDef structure which will + * be initialized. + * @retval None + */ +void DAC_StructInit(DAC_InitTypeDef* DAC_InitStruct) +{ +/*--------------- Reset DAC init structure parameters values -----------------*/ + /* Initialize the DAC_Trigger member */ + DAC_InitStruct->DAC_Trigger = DAC_Trigger_None; + /* Initialize the DAC_WaveGeneration member */ + DAC_InitStruct->DAC_WaveGeneration = DAC_WaveGeneration_None; + /* Initialize the DAC_LFSRUnmask_TriangleAmplitude member */ + DAC_InitStruct->DAC_LFSRUnmask_TriangleAmplitude = DAC_LFSRUnmask_Bit0; + /* Initialize the DAC_OutputBuffer member */ + DAC_InitStruct->DAC_OutputBuffer = DAC_OutputBuffer_Enable; +} + +/** + * @brief Enables or disables the specified DAC channel. + * @param DAC_Channel: the selected DAC channel. + * This parameter can be one of the following values: + * @arg DAC_Channel_1: DAC Channel1 selected + * @arg DAC_Channel_2: DAC Channel2 selected + * @param NewState: new state of the DAC channel. + * This parameter can be: ENABLE or DISABLE. + * @retval None + */ +void DAC_Cmd(uint32_t DAC_Channel, FunctionalState NewState) +{ + /* Check the parameters */ + assert_param(IS_DAC_CHANNEL(DAC_Channel)); + assert_param(IS_FUNCTIONAL_STATE(NewState)); + if (NewState != DISABLE) + { + /* Enable the selected DAC channel */ + DAC->CR |= (DAC_CR_EN1 << DAC_Channel); + } + else + { + /* Disable the selected DAC channel */ + DAC->CR &= ~(DAC_CR_EN1 << DAC_Channel); + } +} +#if defined (STM32F10X_LD_VL) || defined (STM32F10X_MD_VL) || defined (STM32F10X_HD_VL) +/** + * @brief Enables or disables the specified DAC interrupts. + * @param DAC_Channel: the selected DAC channel. + * This parameter can be one of the following values: + * @arg DAC_Channel_1: DAC Channel1 selected + * @arg DAC_Channel_2: DAC Channel2 selected + * @param DAC_IT: specifies the DAC interrupt sources to be enabled or disabled. + * This parameter can be the following values: + * @arg DAC_IT_DMAUDR: DMA underrun interrupt mask + * @param NewState: new state of the specified DAC interrupts. + * This parameter can be: ENABLE or DISABLE. + * @retval None + */ +void DAC_ITConfig(uint32_t DAC_Channel, uint32_t DAC_IT, FunctionalState NewState) +{ + /* Check the parameters */ + assert_param(IS_DAC_CHANNEL(DAC_Channel)); + assert_param(IS_FUNCTIONAL_STATE(NewState)); + assert_param(IS_DAC_IT(DAC_IT)); + + if (NewState != DISABLE) + { + /* Enable the selected DAC interrupts */ + DAC->CR |= (DAC_IT << DAC_Channel); + } + else + { + /* Disable the selected DAC interrupts */ + DAC->CR &= (~(uint32_t)(DAC_IT << DAC_Channel)); + } +} +#endif + +/** + * @brief Enables or disables the specified DAC channel DMA request. + * @param DAC_Channel: the selected DAC channel. + * This parameter can be one of the following values: + * @arg DAC_Channel_1: DAC Channel1 selected + * @arg DAC_Channel_2: DAC Channel2 selected + * @param NewState: new state of the selected DAC channel DMA request. + * This parameter can be: ENABLE or DISABLE. + * @retval None + */ +void DAC_DMACmd(uint32_t DAC_Channel, FunctionalState NewState) +{ + /* Check the parameters */ + assert_param(IS_DAC_CHANNEL(DAC_Channel)); + assert_param(IS_FUNCTIONAL_STATE(NewState)); + if (NewState != DISABLE) + { + /* Enable the selected DAC channel DMA request */ + DAC->CR |= (DAC_CR_DMAEN1 << DAC_Channel); + } + else + { + /* Disable the selected DAC channel DMA request */ + DAC->CR &= ~(DAC_CR_DMAEN1 << DAC_Channel); + } +} + +/** + * @brief Enables or disables the selected DAC channel software trigger. + * @param DAC_Channel: the selected DAC channel. + * This parameter can be one of the following values: + * @arg DAC_Channel_1: DAC Channel1 selected + * @arg DAC_Channel_2: DAC Channel2 selected + * @param NewState: new state of the selected DAC channel software trigger. + * This parameter can be: ENABLE or DISABLE. + * @retval None + */ +void DAC_SoftwareTriggerCmd(uint32_t DAC_Channel, FunctionalState NewState) +{ + /* Check the parameters */ + assert_param(IS_DAC_CHANNEL(DAC_Channel)); + assert_param(IS_FUNCTIONAL_STATE(NewState)); + if (NewState != DISABLE) + { + /* Enable software trigger for the selected DAC channel */ + DAC->SWTRIGR |= (uint32_t)DAC_SWTRIGR_SWTRIG1 << (DAC_Channel >> 4); + } + else + { + /* Disable software trigger for the selected DAC channel */ + DAC->SWTRIGR &= ~((uint32_t)DAC_SWTRIGR_SWTRIG1 << (DAC_Channel >> 4)); + } +} + +/** + * @brief Enables or disables simultaneously the two DAC channels software + * triggers. + * @param NewState: new state of the DAC channels software triggers. + * This parameter can be: ENABLE or DISABLE. + * @retval None + */ +void DAC_DualSoftwareTriggerCmd(FunctionalState NewState) +{ + /* Check the parameters */ + assert_param(IS_FUNCTIONAL_STATE(NewState)); + if (NewState != DISABLE) + { + /* Enable software trigger for both DAC channels */ + DAC->SWTRIGR |= DUAL_SWTRIG_SET ; + } + else + { + /* Disable software trigger for both DAC channels */ + DAC->SWTRIGR &= DUAL_SWTRIG_RESET; + } +} + +/** + * @brief Enables or disables the selected DAC channel wave generation. + * @param DAC_Channel: the selected DAC channel. + * This parameter can be one of the following values: + * @arg DAC_Channel_1: DAC Channel1 selected + * @arg DAC_Channel_2: DAC Channel2 selected + * @param DAC_Wave: Specifies the wave type to enable or disable. + * This parameter can be one of the following values: + * @arg DAC_Wave_Noise: noise wave generation + * @arg DAC_Wave_Triangle: triangle wave generation + * @param NewState: new state of the selected DAC channel wave generation. + * This parameter can be: ENABLE or DISABLE. + * @retval None + */ +void DAC_WaveGenerationCmd(uint32_t DAC_Channel, uint32_t DAC_Wave, FunctionalState NewState) +{ + /* Check the parameters */ + assert_param(IS_DAC_CHANNEL(DAC_Channel)); + assert_param(IS_DAC_WAVE(DAC_Wave)); + assert_param(IS_FUNCTIONAL_STATE(NewState)); + if (NewState != DISABLE) + { + /* Enable the selected wave generation for the selected DAC channel */ + DAC->CR |= DAC_Wave << DAC_Channel; + } + else + { + /* Disable the selected wave generation for the selected DAC channel */ + DAC->CR &= ~(DAC_Wave << DAC_Channel); + } +} + +/** + * @brief Set the specified data holding register value for DAC channel1. + * @param DAC_Align: Specifies the data alignment for DAC channel1. + * This parameter can be one of the following values: + * @arg DAC_Align_8b_R: 8bit right data alignment selected + * @arg DAC_Align_12b_L: 12bit left data alignment selected + * @arg DAC_Align_12b_R: 12bit right data alignment selected + * @param Data : Data to be loaded in the selected data holding register. + * @retval None + */ +void DAC_SetChannel1Data(uint32_t DAC_Align, uint16_t Data) +{ + __IO uint32_t tmp = 0; + + /* Check the parameters */ + assert_param(IS_DAC_ALIGN(DAC_Align)); + assert_param(IS_DAC_DATA(Data)); + + tmp = (uint32_t)DAC_BASE; + tmp += DHR12R1_OFFSET + DAC_Align; + + /* Set the DAC channel1 selected data holding register */ + *(__IO uint32_t *) tmp = Data; +} + +/** + * @brief Set the specified data holding register value for DAC channel2. + * @param DAC_Align: Specifies the data alignment for DAC channel2. + * This parameter can be one of the following values: + * @arg DAC_Align_8b_R: 8bit right data alignment selected + * @arg DAC_Align_12b_L: 12bit left data alignment selected + * @arg DAC_Align_12b_R: 12bit right data alignment selected + * @param Data : Data to be loaded in the selected data holding register. + * @retval None + */ +void DAC_SetChannel2Data(uint32_t DAC_Align, uint16_t Data) +{ + __IO uint32_t tmp = 0; + + /* Check the parameters */ + assert_param(IS_DAC_ALIGN(DAC_Align)); + assert_param(IS_DAC_DATA(Data)); + + tmp = (uint32_t)DAC_BASE; + tmp += DHR12R2_OFFSET + DAC_Align; + + /* Set the DAC channel2 selected data holding register */ + *(__IO uint32_t *)tmp = Data; +} + +/** + * @brief Set the specified data holding register value for dual channel + * DAC. + * @param DAC_Align: Specifies the data alignment for dual channel DAC. + * This parameter can be one of the following values: + * @arg DAC_Align_8b_R: 8bit right data alignment selected + * @arg DAC_Align_12b_L: 12bit left data alignment selected + * @arg DAC_Align_12b_R: 12bit right data alignment selected + * @param Data2: Data for DAC Channel2 to be loaded in the selected data + * holding register. + * @param Data1: Data for DAC Channel1 to be loaded in the selected data + * holding register. + * @retval None + */ +void DAC_SetDualChannelData(uint32_t DAC_Align, uint16_t Data2, uint16_t Data1) +{ + uint32_t data = 0, tmp = 0; + + /* Check the parameters */ + assert_param(IS_DAC_ALIGN(DAC_Align)); + assert_param(IS_DAC_DATA(Data1)); + assert_param(IS_DAC_DATA(Data2)); + + /* Calculate and set dual DAC data holding register value */ + if (DAC_Align == DAC_Align_8b_R) + { + data = ((uint32_t)Data2 << 8) | Data1; + } + else + { + data = ((uint32_t)Data2 << 16) | Data1; + } + + tmp = (uint32_t)DAC_BASE; + tmp += DHR12RD_OFFSET + DAC_Align; + + /* Set the dual DAC selected data holding register */ + *(__IO uint32_t *)tmp = data; +} + +/** + * @brief Returns the last data output value of the selected DAC channel. + * @param DAC_Channel: the selected DAC channel. + * This parameter can be one of the following values: + * @arg DAC_Channel_1: DAC Channel1 selected + * @arg DAC_Channel_2: DAC Channel2 selected + * @retval The selected DAC channel data output value. + */ +uint16_t DAC_GetDataOutputValue(uint32_t DAC_Channel) +{ + __IO uint32_t tmp = 0; + + /* Check the parameters */ + assert_param(IS_DAC_CHANNEL(DAC_Channel)); + + tmp = (uint32_t) DAC_BASE ; + tmp += DOR_OFFSET + ((uint32_t)DAC_Channel >> 2); + + /* Returns the DAC channel data output register value */ + return (uint16_t) (*(__IO uint32_t*) tmp); +} + +#if defined (STM32F10X_LD_VL) || defined (STM32F10X_MD_VL) || defined (STM32F10X_HD_VL) +/** + * @brief Checks whether the specified DAC flag is set or not. + * @param DAC_Channel: thee selected DAC channel. + * This parameter can be one of the following values: + * @arg DAC_Channel_1: DAC Channel1 selected + * @arg DAC_Channel_2: DAC Channel2 selected + * @param DAC_FLAG: specifies the flag to check. + * This parameter can be only of the following value: + * @arg DAC_FLAG_DMAUDR: DMA underrun flag + * @retval The new state of DAC_FLAG (SET or RESET). + */ +FlagStatus DAC_GetFlagStatus(uint32_t DAC_Channel, uint32_t DAC_FLAG) +{ + FlagStatus bitstatus = RESET; + /* Check the parameters */ + assert_param(IS_DAC_CHANNEL(DAC_Channel)); + assert_param(IS_DAC_FLAG(DAC_FLAG)); + + /* Check the status of the specified DAC flag */ + if ((DAC->SR & (DAC_FLAG << DAC_Channel)) != (uint8_t)RESET) + { + /* DAC_FLAG is set */ + bitstatus = SET; + } + else + { + /* DAC_FLAG is reset */ + bitstatus = RESET; + } + /* Return the DAC_FLAG status */ + return bitstatus; +} + +/** + * @brief Clears the DAC channelx's pending flags. + * @param DAC_Channel: the selected DAC channel. + * This parameter can be one of the following values: + * @arg DAC_Channel_1: DAC Channel1 selected + * @arg DAC_Channel_2: DAC Channel2 selected + * @param DAC_FLAG: specifies the flag to clear. + * This parameter can be of the following value: + * @arg DAC_FLAG_DMAUDR: DMA underrun flag + * @retval None + */ +void DAC_ClearFlag(uint32_t DAC_Channel, uint32_t DAC_FLAG) +{ + /* Check the parameters */ + assert_param(IS_DAC_CHANNEL(DAC_Channel)); + assert_param(IS_DAC_FLAG(DAC_FLAG)); + + /* Clear the selected DAC flags */ + DAC->SR = (DAC_FLAG << DAC_Channel); +} + +/** + * @brief Checks whether the specified DAC interrupt has occurred or not. + * @param DAC_Channel: the selected DAC channel. + * This parameter can be one of the following values: + * @arg DAC_Channel_1: DAC Channel1 selected + * @arg DAC_Channel_2: DAC Channel2 selected + * @param DAC_IT: specifies the DAC interrupt source to check. + * This parameter can be the following values: + * @arg DAC_IT_DMAUDR: DMA underrun interrupt mask + * @retval The new state of DAC_IT (SET or RESET). + */ +ITStatus DAC_GetITStatus(uint32_t DAC_Channel, uint32_t DAC_IT) +{ + ITStatus bitstatus = RESET; + uint32_t enablestatus = 0; + + /* Check the parameters */ + assert_param(IS_DAC_CHANNEL(DAC_Channel)); + assert_param(IS_DAC_IT(DAC_IT)); + + /* Get the DAC_IT enable bit status */ + enablestatus = (DAC->CR & (DAC_IT << DAC_Channel)) ; + + /* Check the status of the specified DAC interrupt */ + if (((DAC->SR & (DAC_IT << DAC_Channel)) != (uint32_t)RESET) && enablestatus) + { + /* DAC_IT is set */ + bitstatus = SET; + } + else + { + /* DAC_IT is reset */ + bitstatus = RESET; + } + /* Return the DAC_IT status */ + return bitstatus; +} + +/** + * @brief Clears the DAC channelx's interrupt pending bits. + * @param DAC_Channel: the selected DAC channel. + * This parameter can be one of the following values: + * @arg DAC_Channel_1: DAC Channel1 selected + * @arg DAC_Channel_2: DAC Channel2 selected + * @param DAC_IT: specifies the DAC interrupt pending bit to clear. + * This parameter can be the following values: + * @arg DAC_IT_DMAUDR: DMA underrun interrupt mask + * @retval None + */ +void DAC_ClearITPendingBit(uint32_t DAC_Channel, uint32_t DAC_IT) +{ + /* Check the parameters */ + assert_param(IS_DAC_CHANNEL(DAC_Channel)); + assert_param(IS_DAC_IT(DAC_IT)); + + /* Clear the selected DAC interrupt pending bits */ + DAC->SR = (DAC_IT << DAC_Channel); +} +#endif + +/** + * @} + */ + +/** + * @} + */ + +/** + * @} + */ + +/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ diff --git a/Libraries/STM32F10x_StdPeriph_Driver/src/stm32f10x_dbgmcu.c b/Libraries/STM32F10x_StdPeriph_Driver/src/stm32f10x_dbgmcu.c new file mode 100644 index 0000000..6278093 --- /dev/null +++ b/Libraries/STM32F10x_StdPeriph_Driver/src/stm32f10x_dbgmcu.c @@ -0,0 +1,168 @@ +/** + ****************************************************************************** + * @file stm32f10x_dbgmcu.c + * @author MCD Application Team + * @version V3.6.1 + * @date 05-March-2012 + * @brief This file provides all the DBGMCU firmware functions. + ****************************************************************************** + * @attention + * + *

    © COPYRIGHT 2012 STMicroelectronics

    + * + * Licensed under MCD-ST Liberty SW License Agreement V2, (the "License"); + * You may not use this file except in compliance with the License. + * You may obtain a copy of the License at: + * + * http://www.st.com/software_license_agreement_liberty_v2 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, + * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + * + ****************************************************************************** + */ + +/* Includes ------------------------------------------------------------------*/ +#include "stm32f10x_dbgmcu.h" + +/** @addtogroup STM32F10x_StdPeriph_Driver + * @{ + */ + +/** @defgroup DBGMCU + * @brief DBGMCU driver modules + * @{ + */ + +/** @defgroup DBGMCU_Private_TypesDefinitions + * @{ + */ + +/** + * @} + */ + +/** @defgroup DBGMCU_Private_Defines + * @{ + */ + +#define IDCODE_DEVID_MASK ((uint32_t)0x00000FFF) +/** + * @} + */ + +/** @defgroup DBGMCU_Private_Macros + * @{ + */ + +/** + * @} + */ + +/** @defgroup DBGMCU_Private_Variables + * @{ + */ + +/** + * @} + */ + +/** @defgroup DBGMCU_Private_FunctionPrototypes + * @{ + */ + +/** + * @} + */ + +/** @defgroup DBGMCU_Private_Functions + * @{ + */ + +/** + * @brief Returns the device revision identifier. + * @param None + * @retval Device revision identifier + */ +uint32_t DBGMCU_GetREVID(void) +{ + return(DBGMCU->IDCODE >> 16); +} + +/** + * @brief Returns the device identifier. + * @param None + * @retval Device identifier + */ +uint32_t DBGMCU_GetDEVID(void) +{ + return(DBGMCU->IDCODE & IDCODE_DEVID_MASK); +} + +/** + * @brief Configures the specified peripheral and low power mode behavior + * when the MCU under Debug mode. + * @param DBGMCU_Periph: specifies the peripheral and low power mode. + * This parameter can be any combination of the following values: + * @arg DBGMCU_SLEEP: Keep debugger connection during SLEEP mode + * @arg DBGMCU_STOP: Keep debugger connection during STOP mode + * @arg DBGMCU_STANDBY: Keep debugger connection during STANDBY mode + * @arg DBGMCU_IWDG_STOP: Debug IWDG stopped when Core is halted + * @arg DBGMCU_WWDG_STOP: Debug WWDG stopped when Core is halted + * @arg DBGMCU_TIM1_STOP: TIM1 counter stopped when Core is halted + * @arg DBGMCU_TIM2_STOP: TIM2 counter stopped when Core is halted + * @arg DBGMCU_TIM3_STOP: TIM3 counter stopped when Core is halted + * @arg DBGMCU_TIM4_STOP: TIM4 counter stopped when Core is halted + * @arg DBGMCU_CAN1_STOP: Debug CAN2 stopped when Core is halted + * @arg DBGMCU_I2C1_SMBUS_TIMEOUT: I2C1 SMBUS timeout mode stopped when Core is halted + * @arg DBGMCU_I2C2_SMBUS_TIMEOUT: I2C2 SMBUS timeout mode stopped when Core is halted + * @arg DBGMCU_TIM5_STOP: TIM5 counter stopped when Core is halted + * @arg DBGMCU_TIM6_STOP: TIM6 counter stopped when Core is halted + * @arg DBGMCU_TIM7_STOP: TIM7 counter stopped when Core is halted + * @arg DBGMCU_TIM8_STOP: TIM8 counter stopped when Core is halted + * @arg DBGMCU_CAN2_STOP: Debug CAN2 stopped when Core is halted + * @arg DBGMCU_TIM15_STOP: TIM15 counter stopped when Core is halted + * @arg DBGMCU_TIM16_STOP: TIM16 counter stopped when Core is halted + * @arg DBGMCU_TIM17_STOP: TIM17 counter stopped when Core is halted + * @arg DBGMCU_TIM9_STOP: TIM9 counter stopped when Core is halted + * @arg DBGMCU_TIM10_STOP: TIM10 counter stopped when Core is halted + * @arg DBGMCU_TIM11_STOP: TIM11 counter stopped when Core is halted + * @arg DBGMCU_TIM12_STOP: TIM12 counter stopped when Core is halted + * @arg DBGMCU_TIM13_STOP: TIM13 counter stopped when Core is halted + * @arg DBGMCU_TIM14_STOP: TIM14 counter stopped when Core is halted + * @param NewState: new state of the specified peripheral in Debug mode. + * This parameter can be: ENABLE or DISABLE. + * @retval None + */ +void DBGMCU_Config(uint32_t DBGMCU_Periph, FunctionalState NewState) +{ + /* Check the parameters */ + assert_param(IS_DBGMCU_PERIPH(DBGMCU_Periph)); + assert_param(IS_FUNCTIONAL_STATE(NewState)); + + if (NewState != DISABLE) + { + DBGMCU->CR |= DBGMCU_Periph; + } + else + { + DBGMCU->CR &= ~DBGMCU_Periph; + } +} + +/** + * @} + */ + +/** + * @} + */ + +/** + * @} + */ + +/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ diff --git a/Libraries/STM32F10x_StdPeriph_Driver/src/stm32f10x_dma.c b/Libraries/STM32F10x_StdPeriph_Driver/src/stm32f10x_dma.c new file mode 100644 index 0000000..cc27774 --- /dev/null +++ b/Libraries/STM32F10x_StdPeriph_Driver/src/stm32f10x_dma.c @@ -0,0 +1,720 @@ +/** + ****************************************************************************** + * @file stm32f10x_dma.c + * @author MCD Application Team + * @version V3.6.1 + * @date 05-March-2012 + * @brief This file provides all the DMA firmware functions. + ****************************************************************************** + * @attention + * + *

    © COPYRIGHT 2012 STMicroelectronics

    + * + * Licensed under MCD-ST Liberty SW License Agreement V2, (the "License"); + * You may not use this file except in compliance with the License. + * You may obtain a copy of the License at: + * + * http://www.st.com/software_license_agreement_liberty_v2 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, + * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + * + ****************************************************************************** + */ + +/* Includes ------------------------------------------------------------------*/ +#include "stm32f10x_dma.h" +#include "stm32f10x_rcc.h" + +/** @addtogroup STM32F10x_StdPeriph_Driver + * @{ + */ + +/** @defgroup DMA + * @brief DMA driver modules + * @{ + */ + +/** @defgroup DMA_Private_TypesDefinitions + * @{ + */ +/** + * @} + */ + +/** @defgroup DMA_Private_Defines + * @{ + */ + + +/* DMA1 Channelx interrupt pending bit masks */ +#define DMA1_Channel1_IT_Mask ((uint32_t)(DMA_ISR_GIF1 | DMA_ISR_TCIF1 | DMA_ISR_HTIF1 | DMA_ISR_TEIF1)) +#define DMA1_Channel2_IT_Mask ((uint32_t)(DMA_ISR_GIF2 | DMA_ISR_TCIF2 | DMA_ISR_HTIF2 | DMA_ISR_TEIF2)) +#define DMA1_Channel3_IT_Mask ((uint32_t)(DMA_ISR_GIF3 | DMA_ISR_TCIF3 | DMA_ISR_HTIF3 | DMA_ISR_TEIF3)) +#define DMA1_Channel4_IT_Mask ((uint32_t)(DMA_ISR_GIF4 | DMA_ISR_TCIF4 | DMA_ISR_HTIF4 | DMA_ISR_TEIF4)) +#define DMA1_Channel5_IT_Mask ((uint32_t)(DMA_ISR_GIF5 | DMA_ISR_TCIF5 | DMA_ISR_HTIF5 | DMA_ISR_TEIF5)) +#define DMA1_Channel6_IT_Mask ((uint32_t)(DMA_ISR_GIF6 | DMA_ISR_TCIF6 | DMA_ISR_HTIF6 | DMA_ISR_TEIF6)) +#define DMA1_Channel7_IT_Mask ((uint32_t)(DMA_ISR_GIF7 | DMA_ISR_TCIF7 | DMA_ISR_HTIF7 | DMA_ISR_TEIF7)) + +/* DMA2 Channelx interrupt pending bit masks */ +#define DMA2_Channel1_IT_Mask ((uint32_t)(DMA_ISR_GIF1 | DMA_ISR_TCIF1 | DMA_ISR_HTIF1 | DMA_ISR_TEIF1)) +#define DMA2_Channel2_IT_Mask ((uint32_t)(DMA_ISR_GIF2 | DMA_ISR_TCIF2 | DMA_ISR_HTIF2 | DMA_ISR_TEIF2)) +#define DMA2_Channel3_IT_Mask ((uint32_t)(DMA_ISR_GIF3 | DMA_ISR_TCIF3 | DMA_ISR_HTIF3 | DMA_ISR_TEIF3)) +#define DMA2_Channel4_IT_Mask ((uint32_t)(DMA_ISR_GIF4 | DMA_ISR_TCIF4 | DMA_ISR_HTIF4 | DMA_ISR_TEIF4)) +#define DMA2_Channel5_IT_Mask ((uint32_t)(DMA_ISR_GIF5 | DMA_ISR_TCIF5 | DMA_ISR_HTIF5 | DMA_ISR_TEIF5)) + +/* DMA2 FLAG mask */ +#define FLAG_Mask ((uint32_t)0x10000000) + +/* DMA registers Masks */ +#define CCR_CLEAR_Mask ((uint32_t)0xFFFF800F) + +/** + * @} + */ + +/** @defgroup DMA_Private_Macros + * @{ + */ + +/** + * @} + */ + +/** @defgroup DMA_Private_Variables + * @{ + */ + +/** + * @} + */ + +/** @defgroup DMA_Private_FunctionPrototypes + * @{ + */ + +/** + * @} + */ + +/** @defgroup DMA_Private_Functions + * @{ + */ + +/** + * @brief Deinitializes the DMAy Channelx registers to their default reset + * values. + * @param DMAy_Channelx: where y can be 1 or 2 to select the DMA and + * x can be 1 to 7 for DMA1 and 1 to 5 for DMA2 to select the DMA Channel. + * @retval None + */ +void DMA_DeInit(DMA_Channel_TypeDef* DMAy_Channelx) +{ + /* Check the parameters */ + assert_param(IS_DMA_ALL_PERIPH(DMAy_Channelx)); + + /* Disable the selected DMAy Channelx */ + DMAy_Channelx->CCR &= (uint16_t)(~DMA_CCR1_EN); + + /* Reset DMAy Channelx control register */ + DMAy_Channelx->CCR = 0; + + /* Reset DMAy Channelx remaining bytes register */ + DMAy_Channelx->CNDTR = 0; + + /* Reset DMAy Channelx peripheral address register */ + DMAy_Channelx->CPAR = 0; + + /* Reset DMAy Channelx memory address register */ + DMAy_Channelx->CMAR = 0; + + if (DMAy_Channelx == DMA1_Channel1) + { + /* Reset interrupt pending bits for DMA1 Channel1 */ + DMA1->IFCR |= DMA1_Channel1_IT_Mask; + } + else if (DMAy_Channelx == DMA1_Channel2) + { + /* Reset interrupt pending bits for DMA1 Channel2 */ + DMA1->IFCR |= DMA1_Channel2_IT_Mask; + } + else if (DMAy_Channelx == DMA1_Channel3) + { + /* Reset interrupt pending bits for DMA1 Channel3 */ + DMA1->IFCR |= DMA1_Channel3_IT_Mask; + } + else if (DMAy_Channelx == DMA1_Channel4) + { + /* Reset interrupt pending bits for DMA1 Channel4 */ + DMA1->IFCR |= DMA1_Channel4_IT_Mask; + } + else if (DMAy_Channelx == DMA1_Channel5) + { + /* Reset interrupt pending bits for DMA1 Channel5 */ + DMA1->IFCR |= DMA1_Channel5_IT_Mask; + } + else if (DMAy_Channelx == DMA1_Channel6) + { + /* Reset interrupt pending bits for DMA1 Channel6 */ + DMA1->IFCR |= DMA1_Channel6_IT_Mask; + } + else if (DMAy_Channelx == DMA1_Channel7) + { + /* Reset interrupt pending bits for DMA1 Channel7 */ + DMA1->IFCR |= DMA1_Channel7_IT_Mask; + } + else if (DMAy_Channelx == DMA2_Channel1) + { + /* Reset interrupt pending bits for DMA2 Channel1 */ + DMA2->IFCR |= DMA2_Channel1_IT_Mask; + } + else if (DMAy_Channelx == DMA2_Channel2) + { + /* Reset interrupt pending bits for DMA2 Channel2 */ + DMA2->IFCR |= DMA2_Channel2_IT_Mask; + } + else if (DMAy_Channelx == DMA2_Channel3) + { + /* Reset interrupt pending bits for DMA2 Channel3 */ + DMA2->IFCR |= DMA2_Channel3_IT_Mask; + } + else if (DMAy_Channelx == DMA2_Channel4) + { + /* Reset interrupt pending bits for DMA2 Channel4 */ + DMA2->IFCR |= DMA2_Channel4_IT_Mask; + } + else + { + if (DMAy_Channelx == DMA2_Channel5) + { + /* Reset interrupt pending bits for DMA2 Channel5 */ + DMA2->IFCR |= DMA2_Channel5_IT_Mask; + } + } +} + +/** + * @brief Initializes the DMAy Channelx according to the specified + * parameters in the DMA_InitStruct. + * @param DMAy_Channelx: where y can be 1 or 2 to select the DMA and + * x can be 1 to 7 for DMA1 and 1 to 5 for DMA2 to select the DMA Channel. + * @param DMA_InitStruct: pointer to a DMA_InitTypeDef structure that + * contains the configuration information for the specified DMA Channel. + * @retval None + */ +void DMA_Init(DMA_Channel_TypeDef* DMAy_Channelx, DMA_InitTypeDef* DMA_InitStruct) +{ + uint32_t tmpreg = 0; + + /* Check the parameters */ + assert_param(IS_DMA_ALL_PERIPH(DMAy_Channelx)); + assert_param(IS_DMA_DIR(DMA_InitStruct->DMA_DIR)); + assert_param(IS_DMA_BUFFER_SIZE(DMA_InitStruct->DMA_BufferSize)); + assert_param(IS_DMA_PERIPHERAL_INC_STATE(DMA_InitStruct->DMA_PeripheralInc)); + assert_param(IS_DMA_MEMORY_INC_STATE(DMA_InitStruct->DMA_MemoryInc)); + assert_param(IS_DMA_PERIPHERAL_DATA_SIZE(DMA_InitStruct->DMA_PeripheralDataSize)); + assert_param(IS_DMA_MEMORY_DATA_SIZE(DMA_InitStruct->DMA_MemoryDataSize)); + assert_param(IS_DMA_MODE(DMA_InitStruct->DMA_Mode)); + assert_param(IS_DMA_PRIORITY(DMA_InitStruct->DMA_Priority)); + assert_param(IS_DMA_M2M_STATE(DMA_InitStruct->DMA_M2M)); + +/*--------------------------- DMAy Channelx CCR Configuration -----------------*/ + /* Get the DMAy_Channelx CCR value */ + tmpreg = DMAy_Channelx->CCR; + /* Clear MEM2MEM, PL, MSIZE, PSIZE, MINC, PINC, CIRC and DIR bits */ + tmpreg &= CCR_CLEAR_Mask; + /* Configure DMAy Channelx: data transfer, data size, priority level and mode */ + /* Set DIR bit according to DMA_DIR value */ + /* Set CIRC bit according to DMA_Mode value */ + /* Set PINC bit according to DMA_PeripheralInc value */ + /* Set MINC bit according to DMA_MemoryInc value */ + /* Set PSIZE bits according to DMA_PeripheralDataSize value */ + /* Set MSIZE bits according to DMA_MemoryDataSize value */ + /* Set PL bits according to DMA_Priority value */ + /* Set the MEM2MEM bit according to DMA_M2M value */ + tmpreg |= DMA_InitStruct->DMA_DIR | DMA_InitStruct->DMA_Mode | + DMA_InitStruct->DMA_PeripheralInc | DMA_InitStruct->DMA_MemoryInc | + DMA_InitStruct->DMA_PeripheralDataSize | DMA_InitStruct->DMA_MemoryDataSize | + DMA_InitStruct->DMA_Priority | DMA_InitStruct->DMA_M2M; + + /* Write to DMAy Channelx CCR */ + DMAy_Channelx->CCR = tmpreg; + +/*--------------------------- DMAy Channelx CNDTR Configuration ---------------*/ + /* Write to DMAy Channelx CNDTR */ + DMAy_Channelx->CNDTR = DMA_InitStruct->DMA_BufferSize; + +/*--------------------------- DMAy Channelx CPAR Configuration ----------------*/ + /* Write to DMAy Channelx CPAR */ + DMAy_Channelx->CPAR = DMA_InitStruct->DMA_PeripheralBaseAddr; + +/*--------------------------- DMAy Channelx CMAR Configuration ----------------*/ + /* Write to DMAy Channelx CMAR */ + DMAy_Channelx->CMAR = DMA_InitStruct->DMA_MemoryBaseAddr; +} + +/** + * @brief Fills each DMA_InitStruct member with its default value. + * @param DMA_InitStruct : pointer to a DMA_InitTypeDef structure which will + * be initialized. + * @retval None + */ +void DMA_StructInit(DMA_InitTypeDef* DMA_InitStruct) +{ +/*-------------- Reset DMA init structure parameters values ------------------*/ + /* Initialize the DMA_PeripheralBaseAddr member */ + DMA_InitStruct->DMA_PeripheralBaseAddr = 0; + /* Initialize the DMA_MemoryBaseAddr member */ + DMA_InitStruct->DMA_MemoryBaseAddr = 0; + /* Initialize the DMA_DIR member */ + DMA_InitStruct->DMA_DIR = DMA_DIR_PeripheralSRC; + /* Initialize the DMA_BufferSize member */ + DMA_InitStruct->DMA_BufferSize = 0; + /* Initialize the DMA_PeripheralInc member */ + DMA_InitStruct->DMA_PeripheralInc = DMA_PeripheralInc_Disable; + /* Initialize the DMA_MemoryInc member */ + DMA_InitStruct->DMA_MemoryInc = DMA_MemoryInc_Disable; + /* Initialize the DMA_PeripheralDataSize member */ + DMA_InitStruct->DMA_PeripheralDataSize = DMA_PeripheralDataSize_Byte; + /* Initialize the DMA_MemoryDataSize member */ + DMA_InitStruct->DMA_MemoryDataSize = DMA_MemoryDataSize_Byte; + /* Initialize the DMA_Mode member */ + DMA_InitStruct->DMA_Mode = DMA_Mode_Normal; + /* Initialize the DMA_Priority member */ + DMA_InitStruct->DMA_Priority = DMA_Priority_Low; + /* Initialize the DMA_M2M member */ + DMA_InitStruct->DMA_M2M = DMA_M2M_Disable; +} + +/** + * @brief Enables or disables the specified DMAy Channelx. + * @param DMAy_Channelx: where y can be 1 or 2 to select the DMA and + * x can be 1 to 7 for DMA1 and 1 to 5 for DMA2 to select the DMA Channel. + * @param NewState: new state of the DMAy Channelx. + * This parameter can be: ENABLE or DISABLE. + * @retval None + */ +void DMA_Cmd(DMA_Channel_TypeDef* DMAy_Channelx, FunctionalState NewState) +{ + /* Check the parameters */ + assert_param(IS_DMA_ALL_PERIPH(DMAy_Channelx)); + assert_param(IS_FUNCTIONAL_STATE(NewState)); + + if (NewState != DISABLE) + { + /* Enable the selected DMAy Channelx */ + DMAy_Channelx->CCR |= DMA_CCR1_EN; + } + else + { + /* Disable the selected DMAy Channelx */ + DMAy_Channelx->CCR &= (uint16_t)(~DMA_CCR1_EN); + } +} + +/** + * @brief Enables or disables the specified DMAy Channelx interrupts. + * @param DMAy_Channelx: where y can be 1 or 2 to select the DMA and + * x can be 1 to 7 for DMA1 and 1 to 5 for DMA2 to select the DMA Channel. + * @param DMA_IT: specifies the DMA interrupts sources to be enabled + * or disabled. + * This parameter can be any combination of the following values: + * @arg DMA_IT_TC: Transfer complete interrupt mask + * @arg DMA_IT_HT: Half transfer interrupt mask + * @arg DMA_IT_TE: Transfer error interrupt mask + * @param NewState: new state of the specified DMA interrupts. + * This parameter can be: ENABLE or DISABLE. + * @retval None + */ +void DMA_ITConfig(DMA_Channel_TypeDef* DMAy_Channelx, uint32_t DMA_IT, FunctionalState NewState) +{ + /* Check the parameters */ + assert_param(IS_DMA_ALL_PERIPH(DMAy_Channelx)); + assert_param(IS_DMA_CONFIG_IT(DMA_IT)); + assert_param(IS_FUNCTIONAL_STATE(NewState)); + if (NewState != DISABLE) + { + /* Enable the selected DMA interrupts */ + DMAy_Channelx->CCR |= DMA_IT; + } + else + { + /* Disable the selected DMA interrupts */ + DMAy_Channelx->CCR &= ~DMA_IT; + } +} + +/** + * @brief Sets the number of data units in the current DMAy Channelx transfer. + * @param DMAy_Channelx: where y can be 1 or 2 to select the DMA and + * x can be 1 to 7 for DMA1 and 1 to 5 for DMA2 to select the DMA Channel. + * @param DataNumber: The number of data units in the current DMAy Channelx + * transfer. + * @note This function can only be used when the DMAy_Channelx is disabled. + * @retval None. + */ +void DMA_SetCurrDataCounter(DMA_Channel_TypeDef* DMAy_Channelx, uint16_t DataNumber) +{ + /* Check the parameters */ + assert_param(IS_DMA_ALL_PERIPH(DMAy_Channelx)); + +/*--------------------------- DMAy Channelx CNDTR Configuration ---------------*/ + /* Write to DMAy Channelx CNDTR */ + DMAy_Channelx->CNDTR = DataNumber; +} + +/** + * @brief Returns the number of remaining data units in the current + * DMAy Channelx transfer. + * @param DMAy_Channelx: where y can be 1 or 2 to select the DMA and + * x can be 1 to 7 for DMA1 and 1 to 5 for DMA2 to select the DMA Channel. + * @retval The number of remaining data units in the current DMAy Channelx + * transfer. + */ +uint16_t DMA_GetCurrDataCounter(DMA_Channel_TypeDef* DMAy_Channelx) +{ + /* Check the parameters */ + assert_param(IS_DMA_ALL_PERIPH(DMAy_Channelx)); + /* Return the number of remaining data units for DMAy Channelx */ + return ((uint16_t)(DMAy_Channelx->CNDTR)); +} + +/** + * @brief Checks whether the specified DMAy Channelx flag is set or not. + * @param DMAy_FLAG: specifies the flag to check. + * This parameter can be one of the following values: + * @arg DMA1_FLAG_GL1: DMA1 Channel1 global flag. + * @arg DMA1_FLAG_TC1: DMA1 Channel1 transfer complete flag. + * @arg DMA1_FLAG_HT1: DMA1 Channel1 half transfer flag. + * @arg DMA1_FLAG_TE1: DMA1 Channel1 transfer error flag. + * @arg DMA1_FLAG_GL2: DMA1 Channel2 global flag. + * @arg DMA1_FLAG_TC2: DMA1 Channel2 transfer complete flag. + * @arg DMA1_FLAG_HT2: DMA1 Channel2 half transfer flag. + * @arg DMA1_FLAG_TE2: DMA1 Channel2 transfer error flag. + * @arg DMA1_FLAG_GL3: DMA1 Channel3 global flag. + * @arg DMA1_FLAG_TC3: DMA1 Channel3 transfer complete flag. + * @arg DMA1_FLAG_HT3: DMA1 Channel3 half transfer flag. + * @arg DMA1_FLAG_TE3: DMA1 Channel3 transfer error flag. + * @arg DMA1_FLAG_GL4: DMA1 Channel4 global flag. + * @arg DMA1_FLAG_TC4: DMA1 Channel4 transfer complete flag. + * @arg DMA1_FLAG_HT4: DMA1 Channel4 half transfer flag. + * @arg DMA1_FLAG_TE4: DMA1 Channel4 transfer error flag. + * @arg DMA1_FLAG_GL5: DMA1 Channel5 global flag. + * @arg DMA1_FLAG_TC5: DMA1 Channel5 transfer complete flag. + * @arg DMA1_FLAG_HT5: DMA1 Channel5 half transfer flag. + * @arg DMA1_FLAG_TE5: DMA1 Channel5 transfer error flag. + * @arg DMA1_FLAG_GL6: DMA1 Channel6 global flag. + * @arg DMA1_FLAG_TC6: DMA1 Channel6 transfer complete flag. + * @arg DMA1_FLAG_HT6: DMA1 Channel6 half transfer flag. + * @arg DMA1_FLAG_TE6: DMA1 Channel6 transfer error flag. + * @arg DMA1_FLAG_GL7: DMA1 Channel7 global flag. + * @arg DMA1_FLAG_TC7: DMA1 Channel7 transfer complete flag. + * @arg DMA1_FLAG_HT7: DMA1 Channel7 half transfer flag. + * @arg DMA1_FLAG_TE7: DMA1 Channel7 transfer error flag. + * @arg DMA2_FLAG_GL1: DMA2 Channel1 global flag. + * @arg DMA2_FLAG_TC1: DMA2 Channel1 transfer complete flag. + * @arg DMA2_FLAG_HT1: DMA2 Channel1 half transfer flag. + * @arg DMA2_FLAG_TE1: DMA2 Channel1 transfer error flag. + * @arg DMA2_FLAG_GL2: DMA2 Channel2 global flag. + * @arg DMA2_FLAG_TC2: DMA2 Channel2 transfer complete flag. + * @arg DMA2_FLAG_HT2: DMA2 Channel2 half transfer flag. + * @arg DMA2_FLAG_TE2: DMA2 Channel2 transfer error flag. + * @arg DMA2_FLAG_GL3: DMA2 Channel3 global flag. + * @arg DMA2_FLAG_TC3: DMA2 Channel3 transfer complete flag. + * @arg DMA2_FLAG_HT3: DMA2 Channel3 half transfer flag. + * @arg DMA2_FLAG_TE3: DMA2 Channel3 transfer error flag. + * @arg DMA2_FLAG_GL4: DMA2 Channel4 global flag. + * @arg DMA2_FLAG_TC4: DMA2 Channel4 transfer complete flag. + * @arg DMA2_FLAG_HT4: DMA2 Channel4 half transfer flag. + * @arg DMA2_FLAG_TE4: DMA2 Channel4 transfer error flag. + * @arg DMA2_FLAG_GL5: DMA2 Channel5 global flag. + * @arg DMA2_FLAG_TC5: DMA2 Channel5 transfer complete flag. + * @arg DMA2_FLAG_HT5: DMA2 Channel5 half transfer flag. + * @arg DMA2_FLAG_TE5: DMA2 Channel5 transfer error flag. + * @retval The new state of DMAy_FLAG (SET or RESET). + */ +FlagStatus DMA_GetFlagStatus(uint32_t DMAy_FLAG) +{ + FlagStatus bitstatus = RESET; + uint32_t tmpreg = 0; + + /* Check the parameters */ + assert_param(IS_DMA_GET_FLAG(DMAy_FLAG)); + + /* Calculate the used DMAy */ + if ((DMAy_FLAG & FLAG_Mask) != (uint32_t)RESET) + { + /* Get DMA2 ISR register value */ + tmpreg = DMA2->ISR ; + } + else + { + /* Get DMA1 ISR register value */ + tmpreg = DMA1->ISR ; + } + + /* Check the status of the specified DMAy flag */ + if ((tmpreg & DMAy_FLAG) != (uint32_t)RESET) + { + /* DMAy_FLAG is set */ + bitstatus = SET; + } + else + { + /* DMAy_FLAG is reset */ + bitstatus = RESET; + } + + /* Return the DMAy_FLAG status */ + return bitstatus; +} + +/** + * @brief Clears the DMAy Channelx's pending flags. + * @param DMAy_FLAG: specifies the flag to clear. + * This parameter can be any combination (for the same DMA) of the following values: + * @arg DMA1_FLAG_GL1: DMA1 Channel1 global flag. + * @arg DMA1_FLAG_TC1: DMA1 Channel1 transfer complete flag. + * @arg DMA1_FLAG_HT1: DMA1 Channel1 half transfer flag. + * @arg DMA1_FLAG_TE1: DMA1 Channel1 transfer error flag. + * @arg DMA1_FLAG_GL2: DMA1 Channel2 global flag. + * @arg DMA1_FLAG_TC2: DMA1 Channel2 transfer complete flag. + * @arg DMA1_FLAG_HT2: DMA1 Channel2 half transfer flag. + * @arg DMA1_FLAG_TE2: DMA1 Channel2 transfer error flag. + * @arg DMA1_FLAG_GL3: DMA1 Channel3 global flag. + * @arg DMA1_FLAG_TC3: DMA1 Channel3 transfer complete flag. + * @arg DMA1_FLAG_HT3: DMA1 Channel3 half transfer flag. + * @arg DMA1_FLAG_TE3: DMA1 Channel3 transfer error flag. + * @arg DMA1_FLAG_GL4: DMA1 Channel4 global flag. + * @arg DMA1_FLAG_TC4: DMA1 Channel4 transfer complete flag. + * @arg DMA1_FLAG_HT4: DMA1 Channel4 half transfer flag. + * @arg DMA1_FLAG_TE4: DMA1 Channel4 transfer error flag. + * @arg DMA1_FLAG_GL5: DMA1 Channel5 global flag. + * @arg DMA1_FLAG_TC5: DMA1 Channel5 transfer complete flag. + * @arg DMA1_FLAG_HT5: DMA1 Channel5 half transfer flag. + * @arg DMA1_FLAG_TE5: DMA1 Channel5 transfer error flag. + * @arg DMA1_FLAG_GL6: DMA1 Channel6 global flag. + * @arg DMA1_FLAG_TC6: DMA1 Channel6 transfer complete flag. + * @arg DMA1_FLAG_HT6: DMA1 Channel6 half transfer flag. + * @arg DMA1_FLAG_TE6: DMA1 Channel6 transfer error flag. + * @arg DMA1_FLAG_GL7: DMA1 Channel7 global flag. + * @arg DMA1_FLAG_TC7: DMA1 Channel7 transfer complete flag. + * @arg DMA1_FLAG_HT7: DMA1 Channel7 half transfer flag. + * @arg DMA1_FLAG_TE7: DMA1 Channel7 transfer error flag. + * @arg DMA2_FLAG_GL1: DMA2 Channel1 global flag. + * @arg DMA2_FLAG_TC1: DMA2 Channel1 transfer complete flag. + * @arg DMA2_FLAG_HT1: DMA2 Channel1 half transfer flag. + * @arg DMA2_FLAG_TE1: DMA2 Channel1 transfer error flag. + * @arg DMA2_FLAG_GL2: DMA2 Channel2 global flag. + * @arg DMA2_FLAG_TC2: DMA2 Channel2 transfer complete flag. + * @arg DMA2_FLAG_HT2: DMA2 Channel2 half transfer flag. + * @arg DMA2_FLAG_TE2: DMA2 Channel2 transfer error flag. + * @arg DMA2_FLAG_GL3: DMA2 Channel3 global flag. + * @arg DMA2_FLAG_TC3: DMA2 Channel3 transfer complete flag. + * @arg DMA2_FLAG_HT3: DMA2 Channel3 half transfer flag. + * @arg DMA2_FLAG_TE3: DMA2 Channel3 transfer error flag. + * @arg DMA2_FLAG_GL4: DMA2 Channel4 global flag. + * @arg DMA2_FLAG_TC4: DMA2 Channel4 transfer complete flag. + * @arg DMA2_FLAG_HT4: DMA2 Channel4 half transfer flag. + * @arg DMA2_FLAG_TE4: DMA2 Channel4 transfer error flag. + * @arg DMA2_FLAG_GL5: DMA2 Channel5 global flag. + * @arg DMA2_FLAG_TC5: DMA2 Channel5 transfer complete flag. + * @arg DMA2_FLAG_HT5: DMA2 Channel5 half transfer flag. + * @arg DMA2_FLAG_TE5: DMA2 Channel5 transfer error flag. + * @retval None + */ +void DMA_ClearFlag(uint32_t DMAy_FLAG) +{ + /* Check the parameters */ + assert_param(IS_DMA_CLEAR_FLAG(DMAy_FLAG)); + + /* Calculate the used DMAy */ + if ((DMAy_FLAG & FLAG_Mask) != (uint32_t)RESET) + { + /* Clear the selected DMAy flags */ + DMA2->IFCR = DMAy_FLAG; + } + else + { + /* Clear the selected DMAy flags */ + DMA1->IFCR = DMAy_FLAG; + } +} + +/** + * @brief Checks whether the specified DMAy Channelx interrupt has occurred or not. + * @param DMAy_IT: specifies the DMAy interrupt source to check. + * This parameter can be one of the following values: + * @arg DMA1_IT_GL1: DMA1 Channel1 global interrupt. + * @arg DMA1_IT_TC1: DMA1 Channel1 transfer complete interrupt. + * @arg DMA1_IT_HT1: DMA1 Channel1 half transfer interrupt. + * @arg DMA1_IT_TE1: DMA1 Channel1 transfer error interrupt. + * @arg DMA1_IT_GL2: DMA1 Channel2 global interrupt. + * @arg DMA1_IT_TC2: DMA1 Channel2 transfer complete interrupt. + * @arg DMA1_IT_HT2: DMA1 Channel2 half transfer interrupt. + * @arg DMA1_IT_TE2: DMA1 Channel2 transfer error interrupt. + * @arg DMA1_IT_GL3: DMA1 Channel3 global interrupt. + * @arg DMA1_IT_TC3: DMA1 Channel3 transfer complete interrupt. + * @arg DMA1_IT_HT3: DMA1 Channel3 half transfer interrupt. + * @arg DMA1_IT_TE3: DMA1 Channel3 transfer error interrupt. + * @arg DMA1_IT_GL4: DMA1 Channel4 global interrupt. + * @arg DMA1_IT_TC4: DMA1 Channel4 transfer complete interrupt. + * @arg DMA1_IT_HT4: DMA1 Channel4 half transfer interrupt. + * @arg DMA1_IT_TE4: DMA1 Channel4 transfer error interrupt. + * @arg DMA1_IT_GL5: DMA1 Channel5 global interrupt. + * @arg DMA1_IT_TC5: DMA1 Channel5 transfer complete interrupt. + * @arg DMA1_IT_HT5: DMA1 Channel5 half transfer interrupt. + * @arg DMA1_IT_TE5: DMA1 Channel5 transfer error interrupt. + * @arg DMA1_IT_GL6: DMA1 Channel6 global interrupt. + * @arg DMA1_IT_TC6: DMA1 Channel6 transfer complete interrupt. + * @arg DMA1_IT_HT6: DMA1 Channel6 half transfer interrupt. + * @arg DMA1_IT_TE6: DMA1 Channel6 transfer error interrupt. + * @arg DMA1_IT_GL7: DMA1 Channel7 global interrupt. + * @arg DMA1_IT_TC7: DMA1 Channel7 transfer complete interrupt. + * @arg DMA1_IT_HT7: DMA1 Channel7 half transfer interrupt. + * @arg DMA1_IT_TE7: DMA1 Channel7 transfer error interrupt. + * @arg DMA2_IT_GL1: DMA2 Channel1 global interrupt. + * @arg DMA2_IT_TC1: DMA2 Channel1 transfer complete interrupt. + * @arg DMA2_IT_HT1: DMA2 Channel1 half transfer interrupt. + * @arg DMA2_IT_TE1: DMA2 Channel1 transfer error interrupt. + * @arg DMA2_IT_GL2: DMA2 Channel2 global interrupt. + * @arg DMA2_IT_TC2: DMA2 Channel2 transfer complete interrupt. + * @arg DMA2_IT_HT2: DMA2 Channel2 half transfer interrupt. + * @arg DMA2_IT_TE2: DMA2 Channel2 transfer error interrupt. + * @arg DMA2_IT_GL3: DMA2 Channel3 global interrupt. + * @arg DMA2_IT_TC3: DMA2 Channel3 transfer complete interrupt. + * @arg DMA2_IT_HT3: DMA2 Channel3 half transfer interrupt. + * @arg DMA2_IT_TE3: DMA2 Channel3 transfer error interrupt. + * @arg DMA2_IT_GL4: DMA2 Channel4 global interrupt. + * @arg DMA2_IT_TC4: DMA2 Channel4 transfer complete interrupt. + * @arg DMA2_IT_HT4: DMA2 Channel4 half transfer interrupt. + * @arg DMA2_IT_TE4: DMA2 Channel4 transfer error interrupt. + * @arg DMA2_IT_GL5: DMA2 Channel5 global interrupt. + * @arg DMA2_IT_TC5: DMA2 Channel5 transfer complete interrupt. + * @arg DMA2_IT_HT5: DMA2 Channel5 half transfer interrupt. + * @arg DMA2_IT_TE5: DMA2 Channel5 transfer error interrupt. + * @retval The new state of DMAy_IT (SET or RESET). + */ +ITStatus DMA_GetITStatus(uint32_t DMAy_IT) +{ + ITStatus bitstatus = RESET; + uint32_t tmpreg = 0; + + /* Check the parameters */ + assert_param(IS_DMA_GET_IT(DMAy_IT)); + + /* Calculate the used DMA */ + if ((DMAy_IT & FLAG_Mask) != (uint32_t)RESET) + { + /* Get DMA2 ISR register value */ + tmpreg = DMA2->ISR; + } + else + { + /* Get DMA1 ISR register value */ + tmpreg = DMA1->ISR; + } + + /* Check the status of the specified DMAy interrupt */ + if ((tmpreg & DMAy_IT) != (uint32_t)RESET) + { + /* DMAy_IT is set */ + bitstatus = SET; + } + else + { + /* DMAy_IT is reset */ + bitstatus = RESET; + } + /* Return the DMA_IT status */ + return bitstatus; +} + +/** + * @brief Clears the DMAy Channelx's interrupt pending bits. + * @param DMAy_IT: specifies the DMAy interrupt pending bit to clear. + * This parameter can be any combination (for the same DMA) of the following values: + * @arg DMA1_IT_GL1: DMA1 Channel1 global interrupt. + * @arg DMA1_IT_TC1: DMA1 Channel1 transfer complete interrupt. + * @arg DMA1_IT_HT1: DMA1 Channel1 half transfer interrupt. + * @arg DMA1_IT_TE1: DMA1 Channel1 transfer error interrupt. + * @arg DMA1_IT_GL2: DMA1 Channel2 global interrupt. + * @arg DMA1_IT_TC2: DMA1 Channel2 transfer complete interrupt. + * @arg DMA1_IT_HT2: DMA1 Channel2 half transfer interrupt. + * @arg DMA1_IT_TE2: DMA1 Channel2 transfer error interrupt. + * @arg DMA1_IT_GL3: DMA1 Channel3 global interrupt. + * @arg DMA1_IT_TC3: DMA1 Channel3 transfer complete interrupt. + * @arg DMA1_IT_HT3: DMA1 Channel3 half transfer interrupt. + * @arg DMA1_IT_TE3: DMA1 Channel3 transfer error interrupt. + * @arg DMA1_IT_GL4: DMA1 Channel4 global interrupt. + * @arg DMA1_IT_TC4: DMA1 Channel4 transfer complete interrupt. + * @arg DMA1_IT_HT4: DMA1 Channel4 half transfer interrupt. + * @arg DMA1_IT_TE4: DMA1 Channel4 transfer error interrupt. + * @arg DMA1_IT_GL5: DMA1 Channel5 global interrupt. + * @arg DMA1_IT_TC5: DMA1 Channel5 transfer complete interrupt. + * @arg DMA1_IT_HT5: DMA1 Channel5 half transfer interrupt. + * @arg DMA1_IT_TE5: DMA1 Channel5 transfer error interrupt. + * @arg DMA1_IT_GL6: DMA1 Channel6 global interrupt. + * @arg DMA1_IT_TC6: DMA1 Channel6 transfer complete interrupt. + * @arg DMA1_IT_HT6: DMA1 Channel6 half transfer interrupt. + * @arg DMA1_IT_TE6: DMA1 Channel6 transfer error interrupt. + * @arg DMA1_IT_GL7: DMA1 Channel7 global interrupt. + * @arg DMA1_IT_TC7: DMA1 Channel7 transfer complete interrupt. + * @arg DMA1_IT_HT7: DMA1 Channel7 half transfer interrupt. + * @arg DMA1_IT_TE7: DMA1 Channel7 transfer error interrupt. + * @arg DMA2_IT_GL1: DMA2 Channel1 global interrupt. + * @arg DMA2_IT_TC1: DMA2 Channel1 transfer complete interrupt. + * @arg DMA2_IT_HT1: DMA2 Channel1 half transfer interrupt. + * @arg DMA2_IT_TE1: DMA2 Channel1 transfer error interrupt. + * @arg DMA2_IT_GL2: DMA2 Channel2 global interrupt. + * @arg DMA2_IT_TC2: DMA2 Channel2 transfer complete interrupt. + * @arg DMA2_IT_HT2: DMA2 Channel2 half transfer interrupt. + * @arg DMA2_IT_TE2: DMA2 Channel2 transfer error interrupt. + * @arg DMA2_IT_GL3: DMA2 Channel3 global interrupt. + * @arg DMA2_IT_TC3: DMA2 Channel3 transfer complete interrupt. + * @arg DMA2_IT_HT3: DMA2 Channel3 half transfer interrupt. + * @arg DMA2_IT_TE3: DMA2 Channel3 transfer error interrupt. + * @arg DMA2_IT_GL4: DMA2 Channel4 global interrupt. + * @arg DMA2_IT_TC4: DMA2 Channel4 transfer complete interrupt. + * @arg DMA2_IT_HT4: DMA2 Channel4 half transfer interrupt. + * @arg DMA2_IT_TE4: DMA2 Channel4 transfer error interrupt. + * @arg DMA2_IT_GL5: DMA2 Channel5 global interrupt. + * @arg DMA2_IT_TC5: DMA2 Channel5 transfer complete interrupt. + * @arg DMA2_IT_HT5: DMA2 Channel5 half transfer interrupt. + * @arg DMA2_IT_TE5: DMA2 Channel5 transfer error interrupt. + * @retval None + */ +void DMA_ClearITPendingBit(uint32_t DMAy_IT) +{ + /* Check the parameters */ + assert_param(IS_DMA_CLEAR_IT(DMAy_IT)); + + /* Calculate the used DMAy */ + if ((DMAy_IT & FLAG_Mask) != (uint32_t)RESET) + { + /* Clear the selected DMAy interrupt pending bits */ + DMA2->IFCR = DMAy_IT; + } + else + { + /* Clear the selected DMAy interrupt pending bits */ + DMA1->IFCR = DMAy_IT; + } +} + +/** + * @} + */ + +/** + * @} + */ + +/** + * @} + */ + +/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ diff --git a/Libraries/STM32F10x_StdPeriph_Driver/src/stm32f10x_exti.c b/Libraries/STM32F10x_StdPeriph_Driver/src/stm32f10x_exti.c new file mode 100644 index 0000000..a29fdda --- /dev/null +++ b/Libraries/STM32F10x_StdPeriph_Driver/src/stm32f10x_exti.c @@ -0,0 +1,275 @@ +/** + ****************************************************************************** + * @file stm32f10x_exti.c + * @author MCD Application Team + * @version V3.6.1 + * @date 05-March-2012 + * @brief This file provides all the EXTI firmware functions. + ****************************************************************************** + * @attention + * + *

    © COPYRIGHT 2012 STMicroelectronics

    + * + * Licensed under MCD-ST Liberty SW License Agreement V2, (the "License"); + * You may not use this file except in compliance with the License. + * You may obtain a copy of the License at: + * + * http://www.st.com/software_license_agreement_liberty_v2 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, + * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + * + ****************************************************************************** + */ + +/* Includes ------------------------------------------------------------------*/ +#include "stm32f10x_exti.h" + +/** @addtogroup STM32F10x_StdPeriph_Driver + * @{ + */ + +/** @defgroup EXTI + * @brief EXTI driver modules + * @{ + */ + +/** @defgroup EXTI_Private_TypesDefinitions + * @{ + */ + +/** + * @} + */ + +/** @defgroup EXTI_Private_Defines + * @{ + */ + +#define EXTI_LINENONE ((uint32_t)0x00000) /* No interrupt selected */ + +/** + * @} + */ + +/** @defgroup EXTI_Private_Macros + * @{ + */ + +/** + * @} + */ + +/** @defgroup EXTI_Private_Variables + * @{ + */ + +/** + * @} + */ + +/** @defgroup EXTI_Private_FunctionPrototypes + * @{ + */ + +/** + * @} + */ + +/** @defgroup EXTI_Private_Functions + * @{ + */ + +/** + * @brief Deinitializes the EXTI peripheral registers to their default reset values. + * @param None + * @retval None + */ +void EXTI_DeInit(void) +{ + EXTI->IMR = 0x00000000; + EXTI->EMR = 0x00000000; + EXTI->RTSR = 0x00000000; + EXTI->FTSR = 0x00000000; + EXTI->PR = 0x000FFFFF; +} + +/** + * @brief Initializes the EXTI peripheral according to the specified + * parameters in the EXTI_InitStruct. + * @param EXTI_InitStruct: pointer to a EXTI_InitTypeDef structure + * that contains the configuration information for the EXTI peripheral. + * @retval None + */ +void EXTI_Init(EXTI_InitTypeDef* EXTI_InitStruct) +{ + uint32_t tmp = 0; + + /* Check the parameters */ + assert_param(IS_EXTI_MODE(EXTI_InitStruct->EXTI_Mode)); + assert_param(IS_EXTI_TRIGGER(EXTI_InitStruct->EXTI_Trigger)); + assert_param(IS_EXTI_LINE(EXTI_InitStruct->EXTI_Line)); + assert_param(IS_FUNCTIONAL_STATE(EXTI_InitStruct->EXTI_LineCmd)); + + tmp = (uint32_t)EXTI_BASE; + + if (EXTI_InitStruct->EXTI_LineCmd != DISABLE) + { + /* Clear EXTI line configuration */ + EXTI->IMR &= ~EXTI_InitStruct->EXTI_Line; + EXTI->EMR &= ~EXTI_InitStruct->EXTI_Line; + + tmp += EXTI_InitStruct->EXTI_Mode; + + *(__IO uint32_t *) tmp |= EXTI_InitStruct->EXTI_Line; + + /* Clear Rising Falling edge configuration */ + EXTI->RTSR &= ~EXTI_InitStruct->EXTI_Line; + EXTI->FTSR &= ~EXTI_InitStruct->EXTI_Line; + + /* Select the trigger for the selected external interrupts */ + if (EXTI_InitStruct->EXTI_Trigger == EXTI_Trigger_Rising_Falling) + { + /* Rising Falling edge */ + EXTI->RTSR |= EXTI_InitStruct->EXTI_Line; + EXTI->FTSR |= EXTI_InitStruct->EXTI_Line; + } + else + { + tmp = (uint32_t)EXTI_BASE; + tmp += EXTI_InitStruct->EXTI_Trigger; + + *(__IO uint32_t *) tmp |= EXTI_InitStruct->EXTI_Line; + } + } + else + { + tmp += EXTI_InitStruct->EXTI_Mode; + + /* Disable the selected external lines */ + *(__IO uint32_t *) tmp &= ~EXTI_InitStruct->EXTI_Line; + } +} + +/** + * @brief Fills each EXTI_InitStruct member with its reset value. + * @param EXTI_InitStruct: pointer to a EXTI_InitTypeDef structure which will + * be initialized. + * @retval None + */ +void EXTI_StructInit(EXTI_InitTypeDef* EXTI_InitStruct) +{ + EXTI_InitStruct->EXTI_Line = EXTI_LINENONE; + EXTI_InitStruct->EXTI_Mode = EXTI_Mode_Interrupt; + EXTI_InitStruct->EXTI_Trigger = EXTI_Trigger_Falling; + EXTI_InitStruct->EXTI_LineCmd = DISABLE; +} + +/** + * @brief Generates a Software interrupt. + * @param EXTI_Line: specifies the EXTI lines to be enabled or disabled. + * This parameter can be any combination of EXTI_Linex where x can be (0..19). + * @retval None + */ +void EXTI_GenerateSWInterrupt(uint32_t EXTI_Line) +{ + /* Check the parameters */ + assert_param(IS_EXTI_LINE(EXTI_Line)); + + EXTI->SWIER |= EXTI_Line; +} + +/** + * @brief Checks whether the specified EXTI line flag is set or not. + * @param EXTI_Line: specifies the EXTI line flag to check. + * This parameter can be: + * @arg EXTI_Linex: External interrupt line x where x(0..19) + * @retval The new state of EXTI_Line (SET or RESET). + */ +FlagStatus EXTI_GetFlagStatus(uint32_t EXTI_Line) +{ + FlagStatus bitstatus = RESET; + /* Check the parameters */ + assert_param(IS_GET_EXTI_LINE(EXTI_Line)); + + if ((EXTI->PR & EXTI_Line) != (uint32_t)RESET) + { + bitstatus = SET; + } + else + { + bitstatus = RESET; + } + return bitstatus; +} + +/** + * @brief Clears the EXTI's line pending flags. + * @param EXTI_Line: specifies the EXTI lines flags to clear. + * This parameter can be any combination of EXTI_Linex where x can be (0..19). + * @retval None + */ +void EXTI_ClearFlag(uint32_t EXTI_Line) +{ + /* Check the parameters */ + assert_param(IS_EXTI_LINE(EXTI_Line)); + + EXTI->PR = EXTI_Line; +} + +/** + * @brief Checks whether the specified EXTI line is asserted or not. + * @param EXTI_Line: specifies the EXTI line to check. + * This parameter can be: + * @arg EXTI_Linex: External interrupt line x where x(0..19) + * @retval The new state of EXTI_Line (SET or RESET). + */ +ITStatus EXTI_GetITStatus(uint32_t EXTI_Line) +{ + ITStatus bitstatus = RESET; + uint32_t enablestatus = 0; + /* Check the parameters */ + assert_param(IS_GET_EXTI_LINE(EXTI_Line)); + + enablestatus = EXTI->IMR & EXTI_Line; + if (((EXTI->PR & EXTI_Line) != (uint32_t)RESET) && (enablestatus != (uint32_t)RESET)) + { + bitstatus = SET; + } + else + { + bitstatus = RESET; + } + return bitstatus; +} + +/** + * @brief Clears the EXTI's line pending bits. + * @param EXTI_Line: specifies the EXTI lines to clear. + * This parameter can be any combination of EXTI_Linex where x can be (0..19). + * @retval None + */ +void EXTI_ClearITPendingBit(uint32_t EXTI_Line) +{ + /* Check the parameters */ + assert_param(IS_EXTI_LINE(EXTI_Line)); + + EXTI->PR = EXTI_Line; +} + +/** + * @} + */ + +/** + * @} + */ + +/** + * @} + */ + +/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ diff --git a/Libraries/STM32F10x_StdPeriph_Driver/src/stm32f10x_flash.c b/Libraries/STM32F10x_StdPeriph_Driver/src/stm32f10x_flash.c new file mode 100644 index 0000000..0b5fd3a --- /dev/null +++ b/Libraries/STM32F10x_StdPeriph_Driver/src/stm32f10x_flash.c @@ -0,0 +1,1685 @@ +/** + ****************************************************************************** + * @file stm32f10x_flash.c + * @author MCD Application Team + * @version V3.6.1 + * @date 05-March-2012 + * @brief This file provides all the FLASH firmware functions. + ****************************************************************************** + * @attention + * + *

    © COPYRIGHT 2012 STMicroelectronics

    + * + * Licensed under MCD-ST Liberty SW License Agreement V2, (the "License"); + * You may not use this file except in compliance with the License. + * You may obtain a copy of the License at: + * + * http://www.st.com/software_license_agreement_liberty_v2 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, + * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + * + ****************************************************************************** + */ + +/* Includes ------------------------------------------------------------------*/ +#include "stm32f10x_flash.h" + +/** @addtogroup STM32F10x_StdPeriph_Driver + * @{ + */ + +/** @defgroup FLASH + * @brief FLASH driver modules + * @{ + */ + +/** @defgroup FLASH_Private_TypesDefinitions + * @{ + */ + +/** + * @} + */ + +/** @defgroup FLASH_Private_Defines + * @{ + */ + +/* Flash Access Control Register bits */ +#define ACR_LATENCY_Mask ((uint32_t)0x00000038) +#define ACR_HLFCYA_Mask ((uint32_t)0xFFFFFFF7) +#define ACR_PRFTBE_Mask ((uint32_t)0xFFFFFFEF) + +/* Flash Access Control Register bits */ +#define ACR_PRFTBS_Mask ((uint32_t)0x00000020) + +/* Flash Control Register bits */ +#define CR_PG_Set ((uint32_t)0x00000001) +#define CR_PG_Reset ((uint32_t)0x00001FFE) +#define CR_PER_Set ((uint32_t)0x00000002) +#define CR_PER_Reset ((uint32_t)0x00001FFD) +#define CR_MER_Set ((uint32_t)0x00000004) +#define CR_MER_Reset ((uint32_t)0x00001FFB) +#define CR_OPTPG_Set ((uint32_t)0x00000010) +#define CR_OPTPG_Reset ((uint32_t)0x00001FEF) +#define CR_OPTER_Set ((uint32_t)0x00000020) +#define CR_OPTER_Reset ((uint32_t)0x00001FDF) +#define CR_STRT_Set ((uint32_t)0x00000040) +#define CR_LOCK_Set ((uint32_t)0x00000080) + +/* FLASH Mask */ +#define RDPRT_Mask ((uint32_t)0x00000002) +#define WRP0_Mask ((uint32_t)0x000000FF) +#define WRP1_Mask ((uint32_t)0x0000FF00) +#define WRP2_Mask ((uint32_t)0x00FF0000) +#define WRP3_Mask ((uint32_t)0xFF000000) +#define OB_USER_BFB2 ((uint16_t)0x0008) + +/* FLASH BANK address */ +#define FLASH_BANK1_END_ADDRESS ((uint32_t)0x807FFFF) + +/* Delay definition */ +#define EraseTimeout ((uint32_t)0x000B0000) +#define ProgramTimeout ((uint32_t)0x00002000) +/** + * @} + */ + +/** @defgroup FLASH_Private_Macros + * @{ + */ + +/** + * @} + */ + +/** @defgroup FLASH_Private_Variables + * @{ + */ + +/** + * @} + */ + +/** @defgroup FLASH_Private_FunctionPrototypes + * @{ + */ + +/** + * @} + */ + +/** @defgroup FLASH_Private_Functions + * @{ + */ + +/** +@code + + This driver provides functions to configure and program the Flash memory of all STM32F10x devices, + including the latest STM32F10x_XL density devices. + + STM32F10x_XL devices feature up to 1 Mbyte with dual bank architecture for read-while-write (RWW) capability: + - bank1: fixed size of 512 Kbytes (256 pages of 2Kbytes each) + - bank2: up to 512 Kbytes (up to 256 pages of 2Kbytes each) + While other STM32F10x devices features only one bank with memory up to 512 Kbytes. + + In version V3.3.0, some functions were updated and new ones were added to support + STM32F10x_XL devices. Thus some functions manages all devices, while other are + dedicated for XL devices only. + + The table below presents the list of available functions depending on the used STM32F10x devices. + + *************************************************** + * Legacy functions used for all STM32F10x devices * + *************************************************** + +----------------------------------------------------------------------------------------------------------------------------------+ + | Functions prototypes |STM32F10x_XL|Other STM32F10x| Comments | + | | devices | devices | | + |----------------------------------------------------------------------------------------------------------------------------------| + |FLASH_SetLatency | Yes | Yes | No change | + |----------------------------------------------------------------------------------------------------------------------------------| + |FLASH_HalfCycleAccessCmd | Yes | Yes | No change | + |----------------------------------------------------------------------------------------------------------------------------------| + |FLASH_PrefetchBufferCmd | Yes | Yes | No change | + |----------------------------------------------------------------------------------------------------------------------------------| + |FLASH_Unlock | Yes | Yes | - For STM32F10X_XL devices: unlock Bank1 and Bank2. | + | | | | - For other devices: unlock Bank1 and it is equivalent | + | | | | to FLASH_UnlockBank1 function. | + |----------------------------------------------------------------------------------------------------------------------------------| + |FLASH_Lock | Yes | Yes | - For STM32F10X_XL devices: lock Bank1 and Bank2. | + | | | | - For other devices: lock Bank1 and it is equivalent | + | | | | to FLASH_LockBank1 function. | + |----------------------------------------------------------------------------------------------------------------------------------| + |FLASH_ErasePage | Yes | Yes | - For STM32F10x_XL devices: erase a page in Bank1 and Bank2 | + | | | | - For other devices: erase a page in Bank1 | + |----------------------------------------------------------------------------------------------------------------------------------| + |FLASH_EraseAllPages | Yes | Yes | - For STM32F10x_XL devices: erase all pages in Bank1 and Bank2 | + | | | | - For other devices: erase all pages in Bank1 | + |----------------------------------------------------------------------------------------------------------------------------------| + |FLASH_EraseOptionBytes | Yes | Yes | No change | + |----------------------------------------------------------------------------------------------------------------------------------| + |FLASH_ProgramWord | Yes | Yes | Updated to program up to 1MByte (depending on the used device) | + |----------------------------------------------------------------------------------------------------------------------------------| + |FLASH_ProgramHalfWord | Yes | Yes | Updated to program up to 1MByte (depending on the used device) | + |----------------------------------------------------------------------------------------------------------------------------------| + |FLASH_ProgramOptionByteData | Yes | Yes | No change | + |----------------------------------------------------------------------------------------------------------------------------------| + |FLASH_EnableWriteProtection | Yes | Yes | No change | + |----------------------------------------------------------------------------------------------------------------------------------| + |FLASH_ReadOutProtection | Yes | Yes | No change | + |----------------------------------------------------------------------------------------------------------------------------------| + |FLASH_UserOptionByteConfig | Yes | Yes | No change | + |----------------------------------------------------------------------------------------------------------------------------------| + |FLASH_GetUserOptionByte | Yes | Yes | No change | + |----------------------------------------------------------------------------------------------------------------------------------| + |FLASH_GetWriteProtectionOptionByte | Yes | Yes | No change | + |----------------------------------------------------------------------------------------------------------------------------------| + |FLASH_GetReadOutProtectionStatus | Yes | Yes | No change | + |----------------------------------------------------------------------------------------------------------------------------------| + |FLASH_GetPrefetchBufferStatus | Yes | Yes | No change | + |----------------------------------------------------------------------------------------------------------------------------------| + |FLASH_ITConfig | Yes | Yes | - For STM32F10x_XL devices: enable Bank1 and Bank2's interrupts| + | | | | - For other devices: enable Bank1's interrupts | + |----------------------------------------------------------------------------------------------------------------------------------| + |FLASH_GetFlagStatus | Yes | Yes | - For STM32F10x_XL devices: return Bank1 and Bank2's flag status| + | | | | - For other devices: return Bank1's flag status | + |----------------------------------------------------------------------------------------------------------------------------------| + |FLASH_ClearFlag | Yes | Yes | - For STM32F10x_XL devices: clear Bank1 and Bank2's flag | + | | | | - For other devices: clear Bank1's flag | + |----------------------------------------------------------------------------------------------------------------------------------| + |FLASH_GetStatus | Yes | Yes | - Return the status of Bank1 (for all devices) | + | | | | equivalent to FLASH_GetBank1Status function | + |----------------------------------------------------------------------------------------------------------------------------------| + |FLASH_WaitForLastOperation | Yes | Yes | - Wait for Bank1 last operation (for all devices) | + | | | | equivalent to: FLASH_WaitForLastBank1Operation function | + +----------------------------------------------------------------------------------------------------------------------------------+ + + ************************************************************************************************************************ + * New functions used for all STM32F10x devices to manage Bank1: * + * - These functions are mainly useful for STM32F10x_XL density devices, to have separate control for Bank1 and bank2 * + * - For other devices, these functions are optional (covered by functions listed above) * + ************************************************************************************************************************ + +----------------------------------------------------------------------------------------------------------------------------------+ + | Functions prototypes |STM32F10x_XL|Other STM32F10x| Comments | + | | devices | devices | | + |----------------------------------------------------------------------------------------------------------------------------------| + | FLASH_UnlockBank1 | Yes | Yes | - Unlock Bank1 | + |----------------------------------------------------------------------------------------------------------------------------------| + |FLASH_LockBank1 | Yes | Yes | - Lock Bank1 | + |----------------------------------------------------------------------------------------------------------------------------------| + | FLASH_EraseAllBank1Pages | Yes | Yes | - Erase all pages in Bank1 | + |----------------------------------------------------------------------------------------------------------------------------------| + | FLASH_GetBank1Status | Yes | Yes | - Return the status of Bank1 | + |----------------------------------------------------------------------------------------------------------------------------------| + | FLASH_WaitForLastBank1Operation | Yes | Yes | - Wait for Bank1 last operation | + +----------------------------------------------------------------------------------------------------------------------------------+ + + ***************************************************************************** + * New Functions used only with STM32F10x_XL density devices to manage Bank2 * + ***************************************************************************** + +----------------------------------------------------------------------------------------------------------------------------------+ + | Functions prototypes |STM32F10x_XL|Other STM32F10x| Comments | + | | devices | devices | | + |----------------------------------------------------------------------------------------------------------------------------------| + | FLASH_UnlockBank2 | Yes | No | - Unlock Bank2 | + |----------------------------------------------------------------------------------------------------------------------------------| + |FLASH_LockBank2 | Yes | No | - Lock Bank2 | + |----------------------------------------------------------------------------------------------------------------------------------| + | FLASH_EraseAllBank2Pages | Yes | No | - Erase all pages in Bank2 | + |----------------------------------------------------------------------------------------------------------------------------------| + | FLASH_GetBank2Status | Yes | No | - Return the status of Bank2 | + |----------------------------------------------------------------------------------------------------------------------------------| + | FLASH_WaitForLastBank2Operation | Yes | No | - Wait for Bank2 last operation | + |----------------------------------------------------------------------------------------------------------------------------------| + | FLASH_BootConfig | Yes | No | - Configure to boot from Bank1 or Bank2 | + +----------------------------------------------------------------------------------------------------------------------------------+ +@endcode +*/ + + +/** + * @brief Sets the code latency value. + * @note This function can be used for all STM32F10x devices. + * @param FLASH_Latency: specifies the FLASH Latency value. + * This parameter can be one of the following values: + * @arg FLASH_Latency_0: FLASH Zero Latency cycle + * @arg FLASH_Latency_1: FLASH One Latency cycle + * @arg FLASH_Latency_2: FLASH Two Latency cycles + * @retval None + */ +void FLASH_SetLatency(uint32_t FLASH_Latency) +{ + uint32_t tmpreg = 0; + + /* Check the parameters */ + assert_param(IS_FLASH_LATENCY(FLASH_Latency)); + + /* Read the ACR register */ + tmpreg = FLASH->ACR; + + /* Sets the Latency value */ + tmpreg &= ACR_LATENCY_Mask; + tmpreg |= FLASH_Latency; + + /* Write the ACR register */ + FLASH->ACR = tmpreg; +} + +/** + * @brief Enables or disables the Half cycle flash access. + * @note This function can be used for all STM32F10x devices. + * @param FLASH_HalfCycleAccess: specifies the FLASH Half cycle Access mode. + * This parameter can be one of the following values: + * @arg FLASH_HalfCycleAccess_Enable: FLASH Half Cycle Enable + * @arg FLASH_HalfCycleAccess_Disable: FLASH Half Cycle Disable + * @retval None + */ +void FLASH_HalfCycleAccessCmd(uint32_t FLASH_HalfCycleAccess) +{ + /* Check the parameters */ + assert_param(IS_FLASH_HALFCYCLEACCESS_STATE(FLASH_HalfCycleAccess)); + + /* Enable or disable the Half cycle access */ + FLASH->ACR &= ACR_HLFCYA_Mask; + FLASH->ACR |= FLASH_HalfCycleAccess; +} + +/** + * @brief Enables or disables the Prefetch Buffer. + * @note This function can be used for all STM32F10x devices. + * @param FLASH_PrefetchBuffer: specifies the Prefetch buffer status. + * This parameter can be one of the following values: + * @arg FLASH_PrefetchBuffer_Enable: FLASH Prefetch Buffer Enable + * @arg FLASH_PrefetchBuffer_Disable: FLASH Prefetch Buffer Disable + * @retval None + */ +void FLASH_PrefetchBufferCmd(uint32_t FLASH_PrefetchBuffer) +{ + /* Check the parameters */ + assert_param(IS_FLASH_PREFETCHBUFFER_STATE(FLASH_PrefetchBuffer)); + + /* Enable or disable the Prefetch Buffer */ + FLASH->ACR &= ACR_PRFTBE_Mask; + FLASH->ACR |= FLASH_PrefetchBuffer; +} + +/** + * @brief Unlocks the FLASH Program Erase Controller. + * @note This function can be used for all STM32F10x devices. + * - For STM32F10X_XL devices this function unlocks Bank1 and Bank2. + * - For all other devices it unlocks Bank1 and it is equivalent + * to FLASH_UnlockBank1 function.. + * @param None + * @retval None + */ +void FLASH_Unlock(void) +{ + /* Authorize the FPEC of Bank1 Access */ + FLASH->KEYR = FLASH_KEY1; + FLASH->KEYR = FLASH_KEY2; + +#ifdef STM32F10X_XL + /* Authorize the FPEC of Bank2 Access */ + FLASH->KEYR2 = FLASH_KEY1; + FLASH->KEYR2 = FLASH_KEY2; +#endif /* STM32F10X_XL */ +} +/** + * @brief Unlocks the FLASH Bank1 Program Erase Controller. + * @note This function can be used for all STM32F10x devices. + * - For STM32F10X_XL devices this function unlocks Bank1. + * - For all other devices it unlocks Bank1 and it is + * equivalent to FLASH_Unlock function. + * @param None + * @retval None + */ +void FLASH_UnlockBank1(void) +{ + /* Authorize the FPEC of Bank1 Access */ + FLASH->KEYR = FLASH_KEY1; + FLASH->KEYR = FLASH_KEY2; +} + +#ifdef STM32F10X_XL +/** + * @brief Unlocks the FLASH Bank2 Program Erase Controller. + * @note This function can be used only for STM32F10X_XL density devices. + * @param None + * @retval None + */ +void FLASH_UnlockBank2(void) +{ + /* Authorize the FPEC of Bank2 Access */ + FLASH->KEYR2 = FLASH_KEY1; + FLASH->KEYR2 = FLASH_KEY2; + +} +#endif /* STM32F10X_XL */ + +/** + * @brief Locks the FLASH Program Erase Controller. + * @note This function can be used for all STM32F10x devices. + * - For STM32F10X_XL devices this function Locks Bank1 and Bank2. + * - For all other devices it Locks Bank1 and it is equivalent + * to FLASH_LockBank1 function. + * @param None + * @retval None + */ +void FLASH_Lock(void) +{ + /* Set the Lock Bit to lock the FPEC and the CR of Bank1 */ + FLASH->CR |= CR_LOCK_Set; + +#ifdef STM32F10X_XL + /* Set the Lock Bit to lock the FPEC and the CR of Bank2 */ + FLASH->CR2 |= CR_LOCK_Set; +#endif /* STM32F10X_XL */ +} + +/** + * @brief Locks the FLASH Bank1 Program Erase Controller. + * @note this function can be used for all STM32F10x devices. + * - For STM32F10X_XL devices this function Locks Bank1. + * - For all other devices it Locks Bank1 and it is equivalent + * to FLASH_Lock function. + * @param None + * @retval None + */ +void FLASH_LockBank1(void) +{ + /* Set the Lock Bit to lock the FPEC and the CR of Bank1 */ + FLASH->CR |= CR_LOCK_Set; +} + +#ifdef STM32F10X_XL +/** + * @brief Locks the FLASH Bank2 Program Erase Controller. + * @note This function can be used only for STM32F10X_XL density devices. + * @param None + * @retval None + */ +void FLASH_LockBank2(void) +{ + /* Set the Lock Bit to lock the FPEC and the CR of Bank2 */ + FLASH->CR2 |= CR_LOCK_Set; +} +#endif /* STM32F10X_XL */ + +/** + * @brief Erases a specified FLASH page. + * @note This function can be used for all STM32F10x devices. + * @param Page_Address: The page address to be erased. + * @retval FLASH Status: The returned value can be: FLASH_BUSY, FLASH_ERROR_PG, + * FLASH_ERROR_WRP, FLASH_COMPLETE or FLASH_TIMEOUT. + */ +FLASH_Status FLASH_ErasePage(uint32_t Page_Address) +{ + FLASH_Status status = FLASH_COMPLETE; + /* Check the parameters */ + assert_param(IS_FLASH_ADDRESS(Page_Address)); + +#ifdef STM32F10X_XL + if(Page_Address < FLASH_BANK1_END_ADDRESS) + { + /* Wait for last operation to be completed */ + status = FLASH_WaitForLastBank1Operation(EraseTimeout); + if(status == FLASH_COMPLETE) + { + /* if the previous operation is completed, proceed to erase the page */ + FLASH->CR|= CR_PER_Set; + FLASH->AR = Page_Address; + FLASH->CR|= CR_STRT_Set; + + /* Wait for last operation to be completed */ + status = FLASH_WaitForLastBank1Operation(EraseTimeout); + + /* Disable the PER Bit */ + FLASH->CR &= CR_PER_Reset; + } + } + else + { + /* Wait for last operation to be completed */ + status = FLASH_WaitForLastBank2Operation(EraseTimeout); + if(status == FLASH_COMPLETE) + { + /* if the previous operation is completed, proceed to erase the page */ + FLASH->CR2|= CR_PER_Set; + FLASH->AR2 = Page_Address; + FLASH->CR2|= CR_STRT_Set; + + /* Wait for last operation to be completed */ + status = FLASH_WaitForLastBank2Operation(EraseTimeout); + + /* Disable the PER Bit */ + FLASH->CR2 &= CR_PER_Reset; + } + } +#else + /* Wait for last operation to be completed */ + status = FLASH_WaitForLastOperation(EraseTimeout); + + if(status == FLASH_COMPLETE) + { + /* if the previous operation is completed, proceed to erase the page */ + FLASH->CR|= CR_PER_Set; + FLASH->AR = Page_Address; + FLASH->CR|= CR_STRT_Set; + + /* Wait for last operation to be completed */ + status = FLASH_WaitForLastOperation(EraseTimeout); + + /* Disable the PER Bit */ + FLASH->CR &= CR_PER_Reset; + } +#endif /* STM32F10X_XL */ + + /* Return the Erase Status */ + return status; +} + +/** + * @brief Erases all FLASH pages. + * @note This function can be used for all STM32F10x devices. + * @param None + * @retval FLASH Status: The returned value can be: FLASH_ERROR_PG, + * FLASH_ERROR_WRP, FLASH_COMPLETE or FLASH_TIMEOUT. + */ +FLASH_Status FLASH_EraseAllPages(void) +{ + FLASH_Status status = FLASH_COMPLETE; + +#ifdef STM32F10X_XL + /* Wait for last operation to be completed */ + status = FLASH_WaitForLastBank1Operation(EraseTimeout); + + if(status == FLASH_COMPLETE) + { + /* if the previous operation is completed, proceed to erase all pages */ + FLASH->CR |= CR_MER_Set; + FLASH->CR |= CR_STRT_Set; + + /* Wait for last operation to be completed */ + status = FLASH_WaitForLastBank1Operation(EraseTimeout); + + /* Disable the MER Bit */ + FLASH->CR &= CR_MER_Reset; + } + if(status == FLASH_COMPLETE) + { + /* if the previous operation is completed, proceed to erase all pages */ + FLASH->CR2 |= CR_MER_Set; + FLASH->CR2 |= CR_STRT_Set; + + /* Wait for last operation to be completed */ + status = FLASH_WaitForLastBank2Operation(EraseTimeout); + + /* Disable the MER Bit */ + FLASH->CR2 &= CR_MER_Reset; + } +#else + /* Wait for last operation to be completed */ + status = FLASH_WaitForLastOperation(EraseTimeout); + if(status == FLASH_COMPLETE) + { + /* if the previous operation is completed, proceed to erase all pages */ + FLASH->CR |= CR_MER_Set; + FLASH->CR |= CR_STRT_Set; + + /* Wait for last operation to be completed */ + status = FLASH_WaitForLastOperation(EraseTimeout); + + /* Disable the MER Bit */ + FLASH->CR &= CR_MER_Reset; + } +#endif /* STM32F10X_XL */ + + /* Return the Erase Status */ + return status; +} + +/** + * @brief Erases all Bank1 FLASH pages. + * @note This function can be used for all STM32F10x devices. + * - For STM32F10X_XL devices this function erases all Bank1 pages. + * - For all other devices it erases all Bank1 pages and it is equivalent + * to FLASH_EraseAllPages function. + * @param None + * @retval FLASH Status: The returned value can be: FLASH_ERROR_PG, + * FLASH_ERROR_WRP, FLASH_COMPLETE or FLASH_TIMEOUT. + */ +FLASH_Status FLASH_EraseAllBank1Pages(void) +{ + FLASH_Status status = FLASH_COMPLETE; + /* Wait for last operation to be completed */ + status = FLASH_WaitForLastBank1Operation(EraseTimeout); + + if(status == FLASH_COMPLETE) + { + /* if the previous operation is completed, proceed to erase all pages */ + FLASH->CR |= CR_MER_Set; + FLASH->CR |= CR_STRT_Set; + + /* Wait for last operation to be completed */ + status = FLASH_WaitForLastBank1Operation(EraseTimeout); + + /* Disable the MER Bit */ + FLASH->CR &= CR_MER_Reset; + } + /* Return the Erase Status */ + return status; +} + +#ifdef STM32F10X_XL +/** + * @brief Erases all Bank2 FLASH pages. + * @note This function can be used only for STM32F10x_XL density devices. + * @param None + * @retval FLASH Status: The returned value can be: FLASH_ERROR_PG, + * FLASH_ERROR_WRP, FLASH_COMPLETE or FLASH_TIMEOUT. + */ +FLASH_Status FLASH_EraseAllBank2Pages(void) +{ + FLASH_Status status = FLASH_COMPLETE; + /* Wait for last operation to be completed */ + status = FLASH_WaitForLastBank2Operation(EraseTimeout); + + if(status == FLASH_COMPLETE) + { + /* if the previous operation is completed, proceed to erase all pages */ + FLASH->CR2 |= CR_MER_Set; + FLASH->CR2 |= CR_STRT_Set; + + /* Wait for last operation to be completed */ + status = FLASH_WaitForLastBank2Operation(EraseTimeout); + + /* Disable the MER Bit */ + FLASH->CR2 &= CR_MER_Reset; + } + /* Return the Erase Status */ + return status; +} +#endif /* STM32F10X_XL */ + +/** + * @brief Erases the FLASH option bytes. + * @note This functions erases all option bytes except the Read protection (RDP). + * @note This function can be used for all STM32F10x devices. + * @param None + * @retval FLASH Status: The returned value can be: FLASH_ERROR_PG, + * FLASH_ERROR_WRP, FLASH_COMPLETE or FLASH_TIMEOUT. + */ +FLASH_Status FLASH_EraseOptionBytes(void) +{ + uint16_t rdptmp = RDP_Key; + + FLASH_Status status = FLASH_COMPLETE; + + /* Get the actual read protection Option Byte value */ + if(FLASH_GetReadOutProtectionStatus() != RESET) + { + rdptmp = 0x00; + } + + /* Wait for last operation to be completed */ + status = FLASH_WaitForLastOperation(EraseTimeout); + if(status == FLASH_COMPLETE) + { + /* Authorize the small information block programming */ + FLASH->OPTKEYR = FLASH_KEY1; + FLASH->OPTKEYR = FLASH_KEY2; + + /* if the previous operation is completed, proceed to erase the option bytes */ + FLASH->CR |= CR_OPTER_Set; + FLASH->CR |= CR_STRT_Set; + /* Wait for last operation to be completed */ + status = FLASH_WaitForLastOperation(EraseTimeout); + + if(status == FLASH_COMPLETE) + { + /* if the erase operation is completed, disable the OPTER Bit */ + FLASH->CR &= CR_OPTER_Reset; + + /* Enable the Option Bytes Programming operation */ + FLASH->CR |= CR_OPTPG_Set; + /* Restore the last read protection Option Byte value */ + OB->RDP = (uint16_t)rdptmp; + /* Wait for last operation to be completed */ + status = FLASH_WaitForLastOperation(ProgramTimeout); + + if(status != FLASH_TIMEOUT) + { + /* if the program operation is completed, disable the OPTPG Bit */ + FLASH->CR &= CR_OPTPG_Reset; + } + } + else + { + if (status != FLASH_TIMEOUT) + { + /* Disable the OPTPG Bit */ + FLASH->CR &= CR_OPTPG_Reset; + } + } + } + /* Return the erase status */ + return status; +} + +/** + * @brief Programs a word at a specified address. + * @note This function can be used for all STM32F10x devices. + * @param Address: specifies the address to be programmed. + * @param Data: specifies the data to be programmed. + * @retval FLASH Status: The returned value can be: FLASH_ERROR_PG, + * FLASH_ERROR_WRP, FLASH_COMPLETE or FLASH_TIMEOUT. + */ +FLASH_Status FLASH_ProgramWord(uint32_t Address, uint32_t Data) +{ + FLASH_Status status = FLASH_COMPLETE; + __IO uint32_t tmp = 0; + + /* Check the parameters */ + assert_param(IS_FLASH_ADDRESS(Address)); + +#ifdef STM32F10X_XL + if(Address < FLASH_BANK1_END_ADDRESS - 2) + { + /* Wait for last operation to be completed */ + status = FLASH_WaitForLastBank1Operation(ProgramTimeout); + if(status == FLASH_COMPLETE) + { + /* if the previous operation is completed, proceed to program the new first + half word */ + FLASH->CR |= CR_PG_Set; + + *(__IO uint16_t*)Address = (uint16_t)Data; + /* Wait for last operation to be completed */ + status = FLASH_WaitForLastOperation(ProgramTimeout); + + if(status == FLASH_COMPLETE) + { + /* if the previous operation is completed, proceed to program the new second + half word */ + tmp = Address + 2; + + *(__IO uint16_t*) tmp = Data >> 16; + + /* Wait for last operation to be completed */ + status = FLASH_WaitForLastOperation(ProgramTimeout); + + /* Disable the PG Bit */ + FLASH->CR &= CR_PG_Reset; + } + else + { + /* Disable the PG Bit */ + FLASH->CR &= CR_PG_Reset; + } + } + } + else if(Address == (FLASH_BANK1_END_ADDRESS - 1)) + { + /* Wait for last operation to be completed */ + status = FLASH_WaitForLastBank1Operation(ProgramTimeout); + + if(status == FLASH_COMPLETE) + { + /* if the previous operation is completed, proceed to program the new first + half word */ + FLASH->CR |= CR_PG_Set; + + *(__IO uint16_t*)Address = (uint16_t)Data; + + /* Wait for last operation to be completed */ + status = FLASH_WaitForLastBank1Operation(ProgramTimeout); + + /* Disable the PG Bit */ + FLASH->CR &= CR_PG_Reset; + } + else + { + /* Disable the PG Bit */ + FLASH->CR &= CR_PG_Reset; + } + + /* Wait for last operation to be completed */ + status = FLASH_WaitForLastBank2Operation(ProgramTimeout); + + if(status == FLASH_COMPLETE) + { + /* if the previous operation is completed, proceed to program the new second + half word */ + FLASH->CR2 |= CR_PG_Set; + tmp = Address + 2; + + *(__IO uint16_t*) tmp = Data >> 16; + + /* Wait for last operation to be completed */ + status = FLASH_WaitForLastBank2Operation(ProgramTimeout); + + /* Disable the PG Bit */ + FLASH->CR2 &= CR_PG_Reset; + } + else + { + /* Disable the PG Bit */ + FLASH->CR2 &= CR_PG_Reset; + } + } + else + { + /* Wait for last operation to be completed */ + status = FLASH_WaitForLastBank2Operation(ProgramTimeout); + + if(status == FLASH_COMPLETE) + { + /* if the previous operation is completed, proceed to program the new first + half word */ + FLASH->CR2 |= CR_PG_Set; + + *(__IO uint16_t*)Address = (uint16_t)Data; + /* Wait for last operation to be completed */ + status = FLASH_WaitForLastBank2Operation(ProgramTimeout); + + if(status == FLASH_COMPLETE) + { + /* if the previous operation is completed, proceed to program the new second + half word */ + tmp = Address + 2; + + *(__IO uint16_t*) tmp = Data >> 16; + + /* Wait for last operation to be completed */ + status = FLASH_WaitForLastBank2Operation(ProgramTimeout); + + /* Disable the PG Bit */ + FLASH->CR2 &= CR_PG_Reset; + } + else + { + /* Disable the PG Bit */ + FLASH->CR2 &= CR_PG_Reset; + } + } + } +#else + /* Wait for last operation to be completed */ + status = FLASH_WaitForLastOperation(ProgramTimeout); + + if(status == FLASH_COMPLETE) + { + /* if the previous operation is completed, proceed to program the new first + half word */ + FLASH->CR |= CR_PG_Set; + + *(__IO uint16_t*)Address = (uint16_t)Data; + /* Wait for last operation to be completed */ + status = FLASH_WaitForLastOperation(ProgramTimeout); + + if(status == FLASH_COMPLETE) + { + /* if the previous operation is completed, proceed to program the new second + half word */ + tmp = Address + 2; + + *(__IO uint16_t*) tmp = Data >> 16; + + /* Wait for last operation to be completed */ + status = FLASH_WaitForLastOperation(ProgramTimeout); + + /* Disable the PG Bit */ + FLASH->CR &= CR_PG_Reset; + } + else + { + /* Disable the PG Bit */ + FLASH->CR &= CR_PG_Reset; + } + } +#endif /* STM32F10X_XL */ + + /* Return the Program Status */ + return status; +} + +/** + * @brief Programs a half word at a specified address. + * @note This function can be used for all STM32F10x devices. + * @param Address: specifies the address to be programmed. + * @param Data: specifies the data to be programmed. + * @retval FLASH Status: The returned value can be: FLASH_ERROR_PG, + * FLASH_ERROR_WRP, FLASH_COMPLETE or FLASH_TIMEOUT. + */ +FLASH_Status FLASH_ProgramHalfWord(uint32_t Address, uint16_t Data) +{ + FLASH_Status status = FLASH_COMPLETE; + /* Check the parameters */ + assert_param(IS_FLASH_ADDRESS(Address)); + +#ifdef STM32F10X_XL + /* Wait for last operation to be completed */ + status = FLASH_WaitForLastOperation(ProgramTimeout); + + if(Address < FLASH_BANK1_END_ADDRESS) + { + if(status == FLASH_COMPLETE) + { + /* if the previous operation is completed, proceed to program the new data */ + FLASH->CR |= CR_PG_Set; + + *(__IO uint16_t*)Address = Data; + /* Wait for last operation to be completed */ + status = FLASH_WaitForLastBank1Operation(ProgramTimeout); + + /* Disable the PG Bit */ + FLASH->CR &= CR_PG_Reset; + } + } + else + { + if(status == FLASH_COMPLETE) + { + /* if the previous operation is completed, proceed to program the new data */ + FLASH->CR2 |= CR_PG_Set; + + *(__IO uint16_t*)Address = Data; + /* Wait for last operation to be completed */ + status = FLASH_WaitForLastBank2Operation(ProgramTimeout); + + /* Disable the PG Bit */ + FLASH->CR2 &= CR_PG_Reset; + } + } +#else + /* Wait for last operation to be completed */ + status = FLASH_WaitForLastOperation(ProgramTimeout); + + if(status == FLASH_COMPLETE) + { + /* if the previous operation is completed, proceed to program the new data */ + FLASH->CR |= CR_PG_Set; + + *(__IO uint16_t*)Address = Data; + /* Wait for last operation to be completed */ + status = FLASH_WaitForLastOperation(ProgramTimeout); + + /* Disable the PG Bit */ + FLASH->CR &= CR_PG_Reset; + } +#endif /* STM32F10X_XL */ + + /* Return the Program Status */ + return status; +} + +/** + * @brief Programs a half word at a specified Option Byte Data address. + * @note This function can be used for all STM32F10x devices. + * @param Address: specifies the address to be programmed. + * This parameter can be 0x1FFFF804 or 0x1FFFF806. + * @param Data: specifies the data to be programmed. + * @retval FLASH Status: The returned value can be: FLASH_ERROR_PG, + * FLASH_ERROR_WRP, FLASH_COMPLETE or FLASH_TIMEOUT. + */ +FLASH_Status FLASH_ProgramOptionByteData(uint32_t Address, uint8_t Data) +{ + FLASH_Status status = FLASH_COMPLETE; + /* Check the parameters */ + assert_param(IS_OB_DATA_ADDRESS(Address)); + status = FLASH_WaitForLastOperation(ProgramTimeout); + + if(status == FLASH_COMPLETE) + { + /* Authorize the small information block programming */ + FLASH->OPTKEYR = FLASH_KEY1; + FLASH->OPTKEYR = FLASH_KEY2; + /* Enables the Option Bytes Programming operation */ + FLASH->CR |= CR_OPTPG_Set; + *(__IO uint16_t*)Address = Data; + + /* Wait for last operation to be completed */ + status = FLASH_WaitForLastOperation(ProgramTimeout); + if(status != FLASH_TIMEOUT) + { + /* if the program operation is completed, disable the OPTPG Bit */ + FLASH->CR &= CR_OPTPG_Reset; + } + } + /* Return the Option Byte Data Program Status */ + return status; +} + +/** + * @brief Write protects the desired pages + * @note This function can be used for all STM32F10x devices. + * @param FLASH_Pages: specifies the address of the pages to be write protected. + * This parameter can be: + * @arg For @b STM32_Low-density_devices: value between FLASH_WRProt_Pages0to3 and FLASH_WRProt_Pages28to31 + * @arg For @b STM32_Medium-density_devices: value between FLASH_WRProt_Pages0to3 + * and FLASH_WRProt_Pages124to127 + * @arg For @b STM32_High-density_devices: value between FLASH_WRProt_Pages0to1 and + * FLASH_WRProt_Pages60to61 or FLASH_WRProt_Pages62to255 + * @arg For @b STM32_Connectivity_line_devices: value between FLASH_WRProt_Pages0to1 and + * FLASH_WRProt_Pages60to61 or FLASH_WRProt_Pages62to127 + * @arg For @b STM32_XL-density_devices: value between FLASH_WRProt_Pages0to1 and + * FLASH_WRProt_Pages60to61 or FLASH_WRProt_Pages62to511 + * @arg FLASH_WRProt_AllPages + * @retval FLASH Status: The returned value can be: FLASH_ERROR_PG, + * FLASH_ERROR_WRP, FLASH_COMPLETE or FLASH_TIMEOUT. + */ +FLASH_Status FLASH_EnableWriteProtection(uint32_t FLASH_Pages) +{ + uint16_t WRP0_Data = 0xFFFF, WRP1_Data = 0xFFFF, WRP2_Data = 0xFFFF, WRP3_Data = 0xFFFF; + + FLASH_Status status = FLASH_COMPLETE; + + /* Check the parameters */ + assert_param(IS_FLASH_WRPROT_PAGE(FLASH_Pages)); + + FLASH_Pages = (uint32_t)(~FLASH_Pages); + WRP0_Data = (uint16_t)(FLASH_Pages & WRP0_Mask); + WRP1_Data = (uint16_t)((FLASH_Pages & WRP1_Mask) >> 8); + WRP2_Data = (uint16_t)((FLASH_Pages & WRP2_Mask) >> 16); + WRP3_Data = (uint16_t)((FLASH_Pages & WRP3_Mask) >> 24); + + /* Wait for last operation to be completed */ + status = FLASH_WaitForLastOperation(ProgramTimeout); + + if(status == FLASH_COMPLETE) + { + /* Authorizes the small information block programming */ + FLASH->OPTKEYR = FLASH_KEY1; + FLASH->OPTKEYR = FLASH_KEY2; + FLASH->CR |= CR_OPTPG_Set; + if(WRP0_Data != 0xFF) + { + OB->WRP0 = WRP0_Data; + + /* Wait for last operation to be completed */ + status = FLASH_WaitForLastOperation(ProgramTimeout); + } + if((status == FLASH_COMPLETE) && (WRP1_Data != 0xFF)) + { + OB->WRP1 = WRP1_Data; + + /* Wait for last operation to be completed */ + status = FLASH_WaitForLastOperation(ProgramTimeout); + } + if((status == FLASH_COMPLETE) && (WRP2_Data != 0xFF)) + { + OB->WRP2 = WRP2_Data; + + /* Wait for last operation to be completed */ + status = FLASH_WaitForLastOperation(ProgramTimeout); + } + + if((status == FLASH_COMPLETE)&& (WRP3_Data != 0xFF)) + { + OB->WRP3 = WRP3_Data; + + /* Wait for last operation to be completed */ + status = FLASH_WaitForLastOperation(ProgramTimeout); + } + + if(status != FLASH_TIMEOUT) + { + /* if the program operation is completed, disable the OPTPG Bit */ + FLASH->CR &= CR_OPTPG_Reset; + } + } + /* Return the write protection operation Status */ + return status; +} + +/** + * @brief Enables or disables the read out protection. + * @note If the user has already programmed the other option bytes before calling + * this function, he must re-program them since this function erases all option bytes. + * @note This function can be used for all STM32F10x devices. + * @param Newstate: new state of the ReadOut Protection. + * This parameter can be: ENABLE or DISABLE. + * @retval FLASH Status: The returned value can be: FLASH_ERROR_PG, + * FLASH_ERROR_WRP, FLASH_COMPLETE or FLASH_TIMEOUT. + */ +FLASH_Status FLASH_ReadOutProtection(FunctionalState NewState) +{ + FLASH_Status status = FLASH_COMPLETE; + /* Check the parameters */ + assert_param(IS_FUNCTIONAL_STATE(NewState)); + status = FLASH_WaitForLastOperation(EraseTimeout); + if(status == FLASH_COMPLETE) + { + /* Authorizes the small information block programming */ + FLASH->OPTKEYR = FLASH_KEY1; + FLASH->OPTKEYR = FLASH_KEY2; + FLASH->CR |= CR_OPTER_Set; + FLASH->CR |= CR_STRT_Set; + /* Wait for last operation to be completed */ + status = FLASH_WaitForLastOperation(EraseTimeout); + if(status == FLASH_COMPLETE) + { + /* if the erase operation is completed, disable the OPTER Bit */ + FLASH->CR &= CR_OPTER_Reset; + /* Enable the Option Bytes Programming operation */ + FLASH->CR |= CR_OPTPG_Set; + if(NewState != DISABLE) + { + OB->RDP = 0x00; + } + else + { + OB->RDP = RDP_Key; + } + /* Wait for last operation to be completed */ + status = FLASH_WaitForLastOperation(EraseTimeout); + + if(status != FLASH_TIMEOUT) + { + /* if the program operation is completed, disable the OPTPG Bit */ + FLASH->CR &= CR_OPTPG_Reset; + } + } + else + { + if(status != FLASH_TIMEOUT) + { + /* Disable the OPTER Bit */ + FLASH->CR &= CR_OPTER_Reset; + } + } + } + /* Return the protection operation Status */ + return status; +} + +/** + * @brief Programs the FLASH User Option Byte: IWDG_SW / RST_STOP / RST_STDBY. + * @note This function can be used for all STM32F10x devices. + * @param OB_IWDG: Selects the IWDG mode + * This parameter can be one of the following values: + * @arg OB_IWDG_SW: Software IWDG selected + * @arg OB_IWDG_HW: Hardware IWDG selected + * @param OB_STOP: Reset event when entering STOP mode. + * This parameter can be one of the following values: + * @arg OB_STOP_NoRST: No reset generated when entering in STOP + * @arg OB_STOP_RST: Reset generated when entering in STOP + * @param OB_STDBY: Reset event when entering Standby mode. + * This parameter can be one of the following values: + * @arg OB_STDBY_NoRST: No reset generated when entering in STANDBY + * @arg OB_STDBY_RST: Reset generated when entering in STANDBY + * @retval FLASH Status: The returned value can be: FLASH_ERROR_PG, + * FLASH_ERROR_WRP, FLASH_COMPLETE or FLASH_TIMEOUT. + */ +FLASH_Status FLASH_UserOptionByteConfig(uint16_t OB_IWDG, uint16_t OB_STOP, uint16_t OB_STDBY) +{ + FLASH_Status status = FLASH_COMPLETE; + + /* Check the parameters */ + assert_param(IS_OB_IWDG_SOURCE(OB_IWDG)); + assert_param(IS_OB_STOP_SOURCE(OB_STOP)); + assert_param(IS_OB_STDBY_SOURCE(OB_STDBY)); + + /* Authorize the small information block programming */ + FLASH->OPTKEYR = FLASH_KEY1; + FLASH->OPTKEYR = FLASH_KEY2; + + /* Wait for last operation to be completed */ + status = FLASH_WaitForLastOperation(ProgramTimeout); + + if(status == FLASH_COMPLETE) + { + /* Enable the Option Bytes Programming operation */ + FLASH->CR |= CR_OPTPG_Set; + + OB->USER = OB_IWDG | (uint16_t)(OB_STOP | (uint16_t)(OB_STDBY | ((uint16_t)0xF8))); + + /* Wait for last operation to be completed */ + status = FLASH_WaitForLastOperation(ProgramTimeout); + if(status != FLASH_TIMEOUT) + { + /* if the program operation is completed, disable the OPTPG Bit */ + FLASH->CR &= CR_OPTPG_Reset; + } + } + /* Return the Option Byte program Status */ + return status; +} + +#ifdef STM32F10X_XL +/** + * @brief Configures to boot from Bank1 or Bank2. + * @note This function can be used only for STM32F10x_XL density devices. + * @param FLASH_BOOT: select the FLASH Bank to boot from. + * This parameter can be one of the following values: + * @arg FLASH_BOOT_Bank1: At startup, if boot pins are set in boot from user Flash + * position and this parameter is selected the device will boot from Bank1(Default). + * @arg FLASH_BOOT_Bank2: At startup, if boot pins are set in boot from user Flash + * position and this parameter is selected the device will boot from Bank2 or Bank1, + * depending on the activation of the bank. The active banks are checked in + * the following order: Bank2, followed by Bank1. + * The active bank is recognized by the value programmed at the base address + * of the respective bank (corresponding to the initial stack pointer value + * in the interrupt vector table). + * For more information, please refer to AN2606 from www.st.com. + * @retval FLASH Status: The returned value can be: FLASH_ERROR_PG, + * FLASH_ERROR_WRP, FLASH_COMPLETE or FLASH_TIMEOUT. + */ +FLASH_Status FLASH_BootConfig(uint16_t FLASH_BOOT) +{ + FLASH_Status status = FLASH_COMPLETE; + assert_param(IS_FLASH_BOOT(FLASH_BOOT)); + /* Authorize the small information block programming */ + FLASH->OPTKEYR = FLASH_KEY1; + FLASH->OPTKEYR = FLASH_KEY2; + + /* Wait for last operation to be completed */ + status = FLASH_WaitForLastOperation(ProgramTimeout); + + if(status == FLASH_COMPLETE) + { + /* Enable the Option Bytes Programming operation */ + FLASH->CR |= CR_OPTPG_Set; + + if(FLASH_BOOT == FLASH_BOOT_Bank1) + { + OB->USER |= OB_USER_BFB2; + } + else + { + OB->USER &= (uint16_t)(~(uint16_t)(OB_USER_BFB2)); + } + /* Wait for last operation to be completed */ + status = FLASH_WaitForLastOperation(ProgramTimeout); + if(status != FLASH_TIMEOUT) + { + /* if the program operation is completed, disable the OPTPG Bit */ + FLASH->CR &= CR_OPTPG_Reset; + } + } + /* Return the Option Byte program Status */ + return status; +} +#endif /* STM32F10X_XL */ + +/** + * @brief Returns the FLASH User Option Bytes values. + * @note This function can be used for all STM32F10x devices. + * @param None + * @retval The FLASH User Option Bytes values:IWDG_SW(Bit0), RST_STOP(Bit1) + * and RST_STDBY(Bit2). + */ +uint32_t FLASH_GetUserOptionByte(void) +{ + /* Return the User Option Byte */ + return (uint32_t)(FLASH->OBR >> 2); +} + +/** + * @brief Returns the FLASH Write Protection Option Bytes Register value. + * @note This function can be used for all STM32F10x devices. + * @param None + * @retval The FLASH Write Protection Option Bytes Register value + */ +uint32_t FLASH_GetWriteProtectionOptionByte(void) +{ + /* Return the Flash write protection Register value */ + return (uint32_t)(FLASH->WRPR); +} + +/** + * @brief Checks whether the FLASH Read Out Protection Status is set or not. + * @note This function can be used for all STM32F10x devices. + * @param None + * @retval FLASH ReadOut Protection Status(SET or RESET) + */ +FlagStatus FLASH_GetReadOutProtectionStatus(void) +{ + FlagStatus readoutstatus = RESET; + if ((FLASH->OBR & RDPRT_Mask) != (uint32_t)RESET) + { + readoutstatus = SET; + } + else + { + readoutstatus = RESET; + } + return readoutstatus; +} + +/** + * @brief Checks whether the FLASH Prefetch Buffer status is set or not. + * @note This function can be used for all STM32F10x devices. + * @param None + * @retval FLASH Prefetch Buffer Status (SET or RESET). + */ +FlagStatus FLASH_GetPrefetchBufferStatus(void) +{ + FlagStatus bitstatus = RESET; + + if ((FLASH->ACR & ACR_PRFTBS_Mask) != (uint32_t)RESET) + { + bitstatus = SET; + } + else + { + bitstatus = RESET; + } + /* Return the new state of FLASH Prefetch Buffer Status (SET or RESET) */ + return bitstatus; +} + +/** + * @brief Enables or disables the specified FLASH interrupts. + * @note This function can be used for all STM32F10x devices. + * - For STM32F10X_XL devices, enables or disables the specified FLASH interrupts + for Bank1 and Bank2. + * - For other devices it enables or disables the specified FLASH interrupts for Bank1. + * @param FLASH_IT: specifies the FLASH interrupt sources to be enabled or disabled. + * This parameter can be any combination of the following values: + * @arg FLASH_IT_ERROR: FLASH Error Interrupt + * @arg FLASH_IT_EOP: FLASH end of operation Interrupt + * @param NewState: new state of the specified Flash interrupts. + * This parameter can be: ENABLE or DISABLE. + * @retval None + */ +void FLASH_ITConfig(uint32_t FLASH_IT, FunctionalState NewState) +{ +#ifdef STM32F10X_XL + /* Check the parameters */ + assert_param(IS_FLASH_IT(FLASH_IT)); + assert_param(IS_FUNCTIONAL_STATE(NewState)); + + if((FLASH_IT & 0x80000000) != 0x0) + { + if(NewState != DISABLE) + { + /* Enable the interrupt sources */ + FLASH->CR2 |= (FLASH_IT & 0x7FFFFFFF); + } + else + { + /* Disable the interrupt sources */ + FLASH->CR2 &= ~(uint32_t)(FLASH_IT & 0x7FFFFFFF); + } + } + else + { + if(NewState != DISABLE) + { + /* Enable the interrupt sources */ + FLASH->CR |= FLASH_IT; + } + else + { + /* Disable the interrupt sources */ + FLASH->CR &= ~(uint32_t)FLASH_IT; + } + } +#else + /* Check the parameters */ + assert_param(IS_FLASH_IT(FLASH_IT)); + assert_param(IS_FUNCTIONAL_STATE(NewState)); + + if(NewState != DISABLE) + { + /* Enable the interrupt sources */ + FLASH->CR |= FLASH_IT; + } + else + { + /* Disable the interrupt sources */ + FLASH->CR &= ~(uint32_t)FLASH_IT; + } +#endif /* STM32F10X_XL */ +} + +/** + * @brief Checks whether the specified FLASH flag is set or not. + * @note This function can be used for all STM32F10x devices. + * - For STM32F10X_XL devices, this function checks whether the specified + * Bank1 or Bank2 flag is set or not. + * - For other devices, it checks whether the specified Bank1 flag is + * set or not. + * @param FLASH_FLAG: specifies the FLASH flag to check. + * This parameter can be one of the following values: + * @arg FLASH_FLAG_BSY: FLASH Busy flag + * @arg FLASH_FLAG_PGERR: FLASH Program error flag + * @arg FLASH_FLAG_WRPRTERR: FLASH Write protected error flag + * @arg FLASH_FLAG_EOP: FLASH End of Operation flag + * @arg FLASH_FLAG_OPTERR: FLASH Option Byte error flag + * @retval The new state of FLASH_FLAG (SET or RESET). + */ +FlagStatus FLASH_GetFlagStatus(uint32_t FLASH_FLAG) +{ + FlagStatus bitstatus = RESET; + +#ifdef STM32F10X_XL + /* Check the parameters */ + assert_param(IS_FLASH_GET_FLAG(FLASH_FLAG)) ; + if(FLASH_FLAG == FLASH_FLAG_OPTERR) + { + if((FLASH->OBR & FLASH_FLAG_OPTERR) != (uint32_t)RESET) + { + bitstatus = SET; + } + else + { + bitstatus = RESET; + } + } + else + { + if((FLASH_FLAG & 0x80000000) != 0x0) + { + if((FLASH->SR2 & FLASH_FLAG) != (uint32_t)RESET) + { + bitstatus = SET; + } + else + { + bitstatus = RESET; + } + } + else + { + if((FLASH->SR & FLASH_FLAG) != (uint32_t)RESET) + { + bitstatus = SET; + } + else + { + bitstatus = RESET; + } + } + } +#else + /* Check the parameters */ + assert_param(IS_FLASH_GET_FLAG(FLASH_FLAG)) ; + if(FLASH_FLAG == FLASH_FLAG_OPTERR) + { + if((FLASH->OBR & FLASH_FLAG_OPTERR) != (uint32_t)RESET) + { + bitstatus = SET; + } + else + { + bitstatus = RESET; + } + } + else + { + if((FLASH->SR & FLASH_FLAG) != (uint32_t)RESET) + { + bitstatus = SET; + } + else + { + bitstatus = RESET; + } + } +#endif /* STM32F10X_XL */ + + /* Return the new state of FLASH_FLAG (SET or RESET) */ + return bitstatus; +} + +/** + * @brief Clears the FLASH's pending flags. + * @note This function can be used for all STM32F10x devices. + * - For STM32F10X_XL devices, this function clears Bank1 or Bank2s pending flags + * - For other devices, it clears Bank1s pending flags. + * @param FLASH_FLAG: specifies the FLASH flags to clear. + * This parameter can be any combination of the following values: + * @arg FLASH_FLAG_PGERR: FLASH Program error flag + * @arg FLASH_FLAG_WRPRTERR: FLASH Write protected error flag + * @arg FLASH_FLAG_EOP: FLASH End of Operation flag + * @retval None + */ +void FLASH_ClearFlag(uint32_t FLASH_FLAG) +{ +#ifdef STM32F10X_XL + /* Check the parameters */ + assert_param(IS_FLASH_CLEAR_FLAG(FLASH_FLAG)) ; + + if((FLASH_FLAG & 0x80000000) != 0x0) + { + /* Clear the flags */ + FLASH->SR2 = FLASH_FLAG; + } + else + { + /* Clear the flags */ + FLASH->SR = FLASH_FLAG; + } + +#else + /* Check the parameters */ + assert_param(IS_FLASH_CLEAR_FLAG(FLASH_FLAG)) ; + + /* Clear the flags */ + FLASH->SR = FLASH_FLAG; +#endif /* STM32F10X_XL */ +} + +/** + * @brief Returns the FLASH Status. + * @note This function can be used for all STM32F10x devices, it is equivalent + * to FLASH_GetBank1Status function. + * @param None + * @retval FLASH Status: The returned value can be: FLASH_BUSY, FLASH_ERROR_PG, + * FLASH_ERROR_WRP or FLASH_COMPLETE + */ +FLASH_Status FLASH_GetStatus(void) +{ + FLASH_Status flashstatus = FLASH_COMPLETE; + + if((FLASH->SR & FLASH_FLAG_BSY) == FLASH_FLAG_BSY) + { + flashstatus = FLASH_BUSY; + } + else + { + if((FLASH->SR & FLASH_FLAG_PGERR) != 0) + { + flashstatus = FLASH_ERROR_PG; + } + else + { + if((FLASH->SR & FLASH_FLAG_WRPRTERR) != 0 ) + { + flashstatus = FLASH_ERROR_WRP; + } + else + { + flashstatus = FLASH_COMPLETE; + } + } + } + /* Return the Flash Status */ + return flashstatus; +} + +/** + * @brief Returns the FLASH Bank1 Status. + * @note This function can be used for all STM32F10x devices, it is equivalent + * to FLASH_GetStatus function. + * @param None + * @retval FLASH Status: The returned value can be: FLASH_BUSY, FLASH_ERROR_PG, + * FLASH_ERROR_WRP or FLASH_COMPLETE + */ +FLASH_Status FLASH_GetBank1Status(void) +{ + FLASH_Status flashstatus = FLASH_COMPLETE; + + if((FLASH->SR & FLASH_FLAG_BANK1_BSY) == FLASH_FLAG_BSY) + { + flashstatus = FLASH_BUSY; + } + else + { + if((FLASH->SR & FLASH_FLAG_BANK1_PGERR) != 0) + { + flashstatus = FLASH_ERROR_PG; + } + else + { + if((FLASH->SR & FLASH_FLAG_BANK1_WRPRTERR) != 0 ) + { + flashstatus = FLASH_ERROR_WRP; + } + else + { + flashstatus = FLASH_COMPLETE; + } + } + } + /* Return the Flash Status */ + return flashstatus; +} + +#ifdef STM32F10X_XL +/** + * @brief Returns the FLASH Bank2 Status. + * @note This function can be used for STM32F10x_XL density devices. + * @param None + * @retval FLASH Status: The returned value can be: FLASH_BUSY, FLASH_ERROR_PG, + * FLASH_ERROR_WRP or FLASH_COMPLETE + */ +FLASH_Status FLASH_GetBank2Status(void) +{ + FLASH_Status flashstatus = FLASH_COMPLETE; + + if((FLASH->SR2 & (FLASH_FLAG_BANK2_BSY & 0x7FFFFFFF)) == (FLASH_FLAG_BANK2_BSY & 0x7FFFFFFF)) + { + flashstatus = FLASH_BUSY; + } + else + { + if((FLASH->SR2 & (FLASH_FLAG_BANK2_PGERR & 0x7FFFFFFF)) != 0) + { + flashstatus = FLASH_ERROR_PG; + } + else + { + if((FLASH->SR2 & (FLASH_FLAG_BANK2_WRPRTERR & 0x7FFFFFFF)) != 0 ) + { + flashstatus = FLASH_ERROR_WRP; + } + else + { + flashstatus = FLASH_COMPLETE; + } + } + } + /* Return the Flash Status */ + return flashstatus; +} +#endif /* STM32F10X_XL */ +/** + * @brief Waits for a Flash operation to complete or a TIMEOUT to occur. + * @note This function can be used for all STM32F10x devices, + * it is equivalent to FLASH_WaitForLastBank1Operation. + * - For STM32F10X_XL devices this function waits for a Bank1 Flash operation + * to complete or a TIMEOUT to occur. + * - For all other devices it waits for a Flash operation to complete + * or a TIMEOUT to occur. + * @param Timeout: FLASH programming Timeout + * @retval FLASH Status: The returned value can be: FLASH_ERROR_PG, + * FLASH_ERROR_WRP, FLASH_COMPLETE or FLASH_TIMEOUT. + */ +FLASH_Status FLASH_WaitForLastOperation(uint32_t Timeout) +{ + FLASH_Status status = FLASH_COMPLETE; + + /* Check for the Flash Status */ + status = FLASH_GetBank1Status(); + /* Wait for a Flash operation to complete or a TIMEOUT to occur */ + while((status == FLASH_BUSY) && (Timeout != 0x00)) + { + status = FLASH_GetBank1Status(); + Timeout--; + } + if(Timeout == 0x00 ) + { + status = FLASH_TIMEOUT; + } + /* Return the operation status */ + return status; +} + +/** + * @brief Waits for a Flash operation on Bank1 to complete or a TIMEOUT to occur. + * @note This function can be used for all STM32F10x devices, + * it is equivalent to FLASH_WaitForLastOperation. + * @param Timeout: FLASH programming Timeout + * @retval FLASH Status: The returned value can be: FLASH_ERROR_PG, + * FLASH_ERROR_WRP, FLASH_COMPLETE or FLASH_TIMEOUT. + */ +FLASH_Status FLASH_WaitForLastBank1Operation(uint32_t Timeout) +{ + FLASH_Status status = FLASH_COMPLETE; + + /* Check for the Flash Status */ + status = FLASH_GetBank1Status(); + /* Wait for a Flash operation to complete or a TIMEOUT to occur */ + while((status == FLASH_FLAG_BANK1_BSY) && (Timeout != 0x00)) + { + status = FLASH_GetBank1Status(); + Timeout--; + } + if(Timeout == 0x00 ) + { + status = FLASH_TIMEOUT; + } + /* Return the operation status */ + return status; +} + +#ifdef STM32F10X_XL +/** + * @brief Waits for a Flash operation on Bank2 to complete or a TIMEOUT to occur. + * @note This function can be used only for STM32F10x_XL density devices. + * @param Timeout: FLASH programming Timeout + * @retval FLASH Status: The returned value can be: FLASH_ERROR_PG, + * FLASH_ERROR_WRP, FLASH_COMPLETE or FLASH_TIMEOUT. + */ +FLASH_Status FLASH_WaitForLastBank2Operation(uint32_t Timeout) +{ + FLASH_Status status = FLASH_COMPLETE; + + /* Check for the Flash Status */ + status = FLASH_GetBank2Status(); + /* Wait for a Flash operation to complete or a TIMEOUT to occur */ + while((status == (FLASH_FLAG_BANK2_BSY & 0x7FFFFFFF)) && (Timeout != 0x00)) + { + status = FLASH_GetBank2Status(); + Timeout--; + } + if(Timeout == 0x00 ) + { + status = FLASH_TIMEOUT; + } + /* Return the operation status */ + return status; +} +#endif /* STM32F10X_XL */ + +/** + * @} + */ + +/** + * @} + */ + +/** + * @} + */ + +/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ diff --git a/Libraries/STM32F10x_StdPeriph_Driver/src/stm32f10x_fsmc.c b/Libraries/STM32F10x_StdPeriph_Driver/src/stm32f10x_fsmc.c new file mode 100644 index 0000000..de73841 --- /dev/null +++ b/Libraries/STM32F10x_StdPeriph_Driver/src/stm32f10x_fsmc.c @@ -0,0 +1,872 @@ +/** + ****************************************************************************** + * @file stm32f10x_fsmc.c + * @author MCD Application Team + * @version V3.6.1 + * @date 05-March-2012 + * @brief This file provides all the FSMC firmware functions. + ****************************************************************************** + * @attention + * + *

    © COPYRIGHT 2012 STMicroelectronics

    + * + * Licensed under MCD-ST Liberty SW License Agreement V2, (the "License"); + * You may not use this file except in compliance with the License. + * You may obtain a copy of the License at: + * + * http://www.st.com/software_license_agreement_liberty_v2 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, + * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + * + ****************************************************************************** + */ + +/* Includes ------------------------------------------------------------------*/ +#include "stm32f10x_fsmc.h" +#include "stm32f10x_rcc.h" + +/** @addtogroup STM32F10x_StdPeriph_Driver + * @{ + */ + +/** @defgroup FSMC + * @brief FSMC driver modules + * @{ + */ + +/** @defgroup FSMC_Private_TypesDefinitions + * @{ + */ +/** + * @} + */ + +/** @defgroup FSMC_Private_Defines + * @{ + */ + +/* --------------------- FSMC registers bit mask ---------------------------- */ + +/* FSMC BCRx Mask */ +#define BCR_MBKEN_Set ((uint32_t)0x00000001) +#define BCR_MBKEN_Reset ((uint32_t)0x000FFFFE) +#define BCR_FACCEN_Set ((uint32_t)0x00000040) + +/* FSMC PCRx Mask */ +#define PCR_PBKEN_Set ((uint32_t)0x00000004) +#define PCR_PBKEN_Reset ((uint32_t)0x000FFFFB) +#define PCR_ECCEN_Set ((uint32_t)0x00000040) +#define PCR_ECCEN_Reset ((uint32_t)0x000FFFBF) +#define PCR_MemoryType_NAND ((uint32_t)0x00000008) +/** + * @} + */ + +/** @defgroup FSMC_Private_Macros + * @{ + */ + +/** + * @} + */ + +/** @defgroup FSMC_Private_Variables + * @{ + */ + +/** + * @} + */ + +/** @defgroup FSMC_Private_FunctionPrototypes + * @{ + */ + +/** + * @} + */ + +/** @defgroup FSMC_Private_Functions + * @{ + */ + +/** + * @brief Deinitializes the FSMC NOR/SRAM Banks registers to their default + * reset values. + * @param FSMC_Bank: specifies the FSMC Bank to be used + * This parameter can be one of the following values: + * @arg FSMC_Bank1_NORSRAM1: FSMC Bank1 NOR/SRAM1 + * @arg FSMC_Bank1_NORSRAM2: FSMC Bank1 NOR/SRAM2 + * @arg FSMC_Bank1_NORSRAM3: FSMC Bank1 NOR/SRAM3 + * @arg FSMC_Bank1_NORSRAM4: FSMC Bank1 NOR/SRAM4 + * @retval None + */ +void FSMC_NORSRAMDeInit(uint32_t FSMC_Bank) +{ + /* Check the parameter */ + assert_param(IS_FSMC_NORSRAM_BANK(FSMC_Bank)); + + /* FSMC_Bank1_NORSRAM1 */ + if(FSMC_Bank == FSMC_Bank1_NORSRAM1) + { + FSMC_Bank1->BTCR[FSMC_Bank] = 0x000030DB; + } + /* FSMC_Bank1_NORSRAM2, FSMC_Bank1_NORSRAM3 or FSMC_Bank1_NORSRAM4 */ + else + { + FSMC_Bank1->BTCR[FSMC_Bank] = 0x000030D2; + } + FSMC_Bank1->BTCR[FSMC_Bank + 1] = 0x0FFFFFFF; + FSMC_Bank1E->BWTR[FSMC_Bank] = 0x0FFFFFFF; +} + +/** + * @brief Deinitializes the FSMC NAND Banks registers to their default reset values. + * @param FSMC_Bank: specifies the FSMC Bank to be used + * This parameter can be one of the following values: + * @arg FSMC_Bank2_NAND: FSMC Bank2 NAND + * @arg FSMC_Bank3_NAND: FSMC Bank3 NAND + * @retval None + */ +void FSMC_NANDDeInit(uint32_t FSMC_Bank) +{ + /* Check the parameter */ + assert_param(IS_FSMC_NAND_BANK(FSMC_Bank)); + + if(FSMC_Bank == FSMC_Bank2_NAND) + { + /* Set the FSMC_Bank2 registers to their reset values */ + FSMC_Bank2->PCR2 = 0x00000018; + FSMC_Bank2->SR2 = 0x00000040; + FSMC_Bank2->PMEM2 = 0xFCFCFCFC; + FSMC_Bank2->PATT2 = 0xFCFCFCFC; + } + /* FSMC_Bank3_NAND */ + else + { + /* Set the FSMC_Bank3 registers to their reset values */ + FSMC_Bank3->PCR3 = 0x00000018; + FSMC_Bank3->SR3 = 0x00000040; + FSMC_Bank3->PMEM3 = 0xFCFCFCFC; + FSMC_Bank3->PATT3 = 0xFCFCFCFC; + } +} + +/** + * @brief Deinitializes the FSMC PCCARD Bank registers to their default reset values. + * @param None + * @retval None + */ +void FSMC_PCCARDDeInit(void) +{ + /* Set the FSMC_Bank4 registers to their reset values */ + FSMC_Bank4->PCR4 = 0x00000018; + FSMC_Bank4->SR4 = 0x00000000; + FSMC_Bank4->PMEM4 = 0xFCFCFCFC; + FSMC_Bank4->PATT4 = 0xFCFCFCFC; + FSMC_Bank4->PIO4 = 0xFCFCFCFC; +} + +/** + * @brief Initializes the FSMC NOR/SRAM Banks according to the specified + * parameters in the FSMC_NORSRAMInitStruct. + * @param FSMC_NORSRAMInitStruct : pointer to a FSMC_NORSRAMInitTypeDef + * structure that contains the configuration information for + * the FSMC NOR/SRAM specified Banks. + * @retval None + */ +void FSMC_NORSRAMInit(FSMC_NORSRAMInitTypeDef* FSMC_NORSRAMInitStruct) +{ + /* Check the parameters */ + assert_param(IS_FSMC_NORSRAM_BANK(FSMC_NORSRAMInitStruct->FSMC_Bank)); + assert_param(IS_FSMC_MUX(FSMC_NORSRAMInitStruct->FSMC_DataAddressMux)); + assert_param(IS_FSMC_MEMORY(FSMC_NORSRAMInitStruct->FSMC_MemoryType)); + assert_param(IS_FSMC_MEMORY_WIDTH(FSMC_NORSRAMInitStruct->FSMC_MemoryDataWidth)); + assert_param(IS_FSMC_BURSTMODE(FSMC_NORSRAMInitStruct->FSMC_BurstAccessMode)); + assert_param(IS_FSMC_ASYNWAIT(FSMC_NORSRAMInitStruct->FSMC_AsynchronousWait)); + assert_param(IS_FSMC_WAIT_POLARITY(FSMC_NORSRAMInitStruct->FSMC_WaitSignalPolarity)); + assert_param(IS_FSMC_WRAP_MODE(FSMC_NORSRAMInitStruct->FSMC_WrapMode)); + assert_param(IS_FSMC_WAIT_SIGNAL_ACTIVE(FSMC_NORSRAMInitStruct->FSMC_WaitSignalActive)); + assert_param(IS_FSMC_WRITE_OPERATION(FSMC_NORSRAMInitStruct->FSMC_WriteOperation)); + assert_param(IS_FSMC_WAITE_SIGNAL(FSMC_NORSRAMInitStruct->FSMC_WaitSignal)); + assert_param(IS_FSMC_EXTENDED_MODE(FSMC_NORSRAMInitStruct->FSMC_ExtendedMode)); + assert_param(IS_FSMC_WRITE_BURST(FSMC_NORSRAMInitStruct->FSMC_WriteBurst)); + assert_param(IS_FSMC_ADDRESS_SETUP_TIME(FSMC_NORSRAMInitStruct->FSMC_ReadWriteTimingStruct->FSMC_AddressSetupTime)); + assert_param(IS_FSMC_ADDRESS_HOLD_TIME(FSMC_NORSRAMInitStruct->FSMC_ReadWriteTimingStruct->FSMC_AddressHoldTime)); + assert_param(IS_FSMC_DATASETUP_TIME(FSMC_NORSRAMInitStruct->FSMC_ReadWriteTimingStruct->FSMC_DataSetupTime)); + assert_param(IS_FSMC_TURNAROUND_TIME(FSMC_NORSRAMInitStruct->FSMC_ReadWriteTimingStruct->FSMC_BusTurnAroundDuration)); + assert_param(IS_FSMC_CLK_DIV(FSMC_NORSRAMInitStruct->FSMC_ReadWriteTimingStruct->FSMC_CLKDivision)); + assert_param(IS_FSMC_DATA_LATENCY(FSMC_NORSRAMInitStruct->FSMC_ReadWriteTimingStruct->FSMC_DataLatency)); + assert_param(IS_FSMC_ACCESS_MODE(FSMC_NORSRAMInitStruct->FSMC_ReadWriteTimingStruct->FSMC_AccessMode)); + + /* Bank1 NOR/SRAM control register configuration */ + FSMC_Bank1->BTCR[FSMC_NORSRAMInitStruct->FSMC_Bank] = + (uint32_t)FSMC_NORSRAMInitStruct->FSMC_DataAddressMux | + FSMC_NORSRAMInitStruct->FSMC_MemoryType | + FSMC_NORSRAMInitStruct->FSMC_MemoryDataWidth | + FSMC_NORSRAMInitStruct->FSMC_BurstAccessMode | + FSMC_NORSRAMInitStruct->FSMC_AsynchronousWait | + FSMC_NORSRAMInitStruct->FSMC_WaitSignalPolarity | + FSMC_NORSRAMInitStruct->FSMC_WrapMode | + FSMC_NORSRAMInitStruct->FSMC_WaitSignalActive | + FSMC_NORSRAMInitStruct->FSMC_WriteOperation | + FSMC_NORSRAMInitStruct->FSMC_WaitSignal | + FSMC_NORSRAMInitStruct->FSMC_ExtendedMode | + FSMC_NORSRAMInitStruct->FSMC_WriteBurst; + + if(FSMC_NORSRAMInitStruct->FSMC_MemoryType == FSMC_MemoryType_NOR) + { + FSMC_Bank1->BTCR[FSMC_NORSRAMInitStruct->FSMC_Bank] |= (uint32_t)BCR_FACCEN_Set; + } + + /* Bank1 NOR/SRAM timing register configuration */ + FSMC_Bank1->BTCR[FSMC_NORSRAMInitStruct->FSMC_Bank+1] = + (uint32_t)FSMC_NORSRAMInitStruct->FSMC_ReadWriteTimingStruct->FSMC_AddressSetupTime | + (FSMC_NORSRAMInitStruct->FSMC_ReadWriteTimingStruct->FSMC_AddressHoldTime << 4) | + (FSMC_NORSRAMInitStruct->FSMC_ReadWriteTimingStruct->FSMC_DataSetupTime << 8) | + (FSMC_NORSRAMInitStruct->FSMC_ReadWriteTimingStruct->FSMC_BusTurnAroundDuration << 16) | + (FSMC_NORSRAMInitStruct->FSMC_ReadWriteTimingStruct->FSMC_CLKDivision << 20) | + (FSMC_NORSRAMInitStruct->FSMC_ReadWriteTimingStruct->FSMC_DataLatency << 24) | + FSMC_NORSRAMInitStruct->FSMC_ReadWriteTimingStruct->FSMC_AccessMode; + + + /* Bank1 NOR/SRAM timing register for write configuration, if extended mode is used */ + if(FSMC_NORSRAMInitStruct->FSMC_ExtendedMode == FSMC_ExtendedMode_Enable) + { + assert_param(IS_FSMC_ADDRESS_SETUP_TIME(FSMC_NORSRAMInitStruct->FSMC_WriteTimingStruct->FSMC_AddressSetupTime)); + assert_param(IS_FSMC_ADDRESS_HOLD_TIME(FSMC_NORSRAMInitStruct->FSMC_WriteTimingStruct->FSMC_AddressHoldTime)); + assert_param(IS_FSMC_DATASETUP_TIME(FSMC_NORSRAMInitStruct->FSMC_WriteTimingStruct->FSMC_DataSetupTime)); + assert_param(IS_FSMC_CLK_DIV(FSMC_NORSRAMInitStruct->FSMC_WriteTimingStruct->FSMC_CLKDivision)); + assert_param(IS_FSMC_DATA_LATENCY(FSMC_NORSRAMInitStruct->FSMC_WriteTimingStruct->FSMC_DataLatency)); + assert_param(IS_FSMC_ACCESS_MODE(FSMC_NORSRAMInitStruct->FSMC_WriteTimingStruct->FSMC_AccessMode)); + FSMC_Bank1E->BWTR[FSMC_NORSRAMInitStruct->FSMC_Bank] = + (uint32_t)FSMC_NORSRAMInitStruct->FSMC_WriteTimingStruct->FSMC_AddressSetupTime | + (FSMC_NORSRAMInitStruct->FSMC_WriteTimingStruct->FSMC_AddressHoldTime << 4 )| + (FSMC_NORSRAMInitStruct->FSMC_WriteTimingStruct->FSMC_DataSetupTime << 8) | + (FSMC_NORSRAMInitStruct->FSMC_WriteTimingStruct->FSMC_CLKDivision << 20) | + (FSMC_NORSRAMInitStruct->FSMC_WriteTimingStruct->FSMC_DataLatency << 24) | + FSMC_NORSRAMInitStruct->FSMC_WriteTimingStruct->FSMC_AccessMode; + } + else + { + FSMC_Bank1E->BWTR[FSMC_NORSRAMInitStruct->FSMC_Bank] = 0x0FFFFFFF; + } +} + +/** + * @brief Initializes the FSMC NAND Banks according to the specified + * parameters in the FSMC_NANDInitStruct. + * @param FSMC_NANDInitStruct : pointer to a FSMC_NANDInitTypeDef + * structure that contains the configuration information for the FSMC + * NAND specified Banks. + * @retval None + */ +void FSMC_NANDInit(FSMC_NANDInitTypeDef* FSMC_NANDInitStruct) +{ + uint32_t tmppcr = 0x00000000, tmppmem = 0x00000000, tmppatt = 0x00000000; + + /* Check the parameters */ + assert_param( IS_FSMC_NAND_BANK(FSMC_NANDInitStruct->FSMC_Bank)); + assert_param( IS_FSMC_WAIT_FEATURE(FSMC_NANDInitStruct->FSMC_Waitfeature)); + assert_param( IS_FSMC_MEMORY_WIDTH(FSMC_NANDInitStruct->FSMC_MemoryDataWidth)); + assert_param( IS_FSMC_ECC_STATE(FSMC_NANDInitStruct->FSMC_ECC)); + assert_param( IS_FSMC_ECCPAGE_SIZE(FSMC_NANDInitStruct->FSMC_ECCPageSize)); + assert_param( IS_FSMC_TCLR_TIME(FSMC_NANDInitStruct->FSMC_TCLRSetupTime)); + assert_param( IS_FSMC_TAR_TIME(FSMC_NANDInitStruct->FSMC_TARSetupTime)); + assert_param(IS_FSMC_SETUP_TIME(FSMC_NANDInitStruct->FSMC_CommonSpaceTimingStruct->FSMC_SetupTime)); + assert_param(IS_FSMC_WAIT_TIME(FSMC_NANDInitStruct->FSMC_CommonSpaceTimingStruct->FSMC_WaitSetupTime)); + assert_param(IS_FSMC_HOLD_TIME(FSMC_NANDInitStruct->FSMC_CommonSpaceTimingStruct->FSMC_HoldSetupTime)); + assert_param(IS_FSMC_HIZ_TIME(FSMC_NANDInitStruct->FSMC_CommonSpaceTimingStruct->FSMC_HiZSetupTime)); + assert_param(IS_FSMC_SETUP_TIME(FSMC_NANDInitStruct->FSMC_AttributeSpaceTimingStruct->FSMC_SetupTime)); + assert_param(IS_FSMC_WAIT_TIME(FSMC_NANDInitStruct->FSMC_AttributeSpaceTimingStruct->FSMC_WaitSetupTime)); + assert_param(IS_FSMC_HOLD_TIME(FSMC_NANDInitStruct->FSMC_AttributeSpaceTimingStruct->FSMC_HoldSetupTime)); + assert_param(IS_FSMC_HIZ_TIME(FSMC_NANDInitStruct->FSMC_AttributeSpaceTimingStruct->FSMC_HiZSetupTime)); + + /* Set the tmppcr value according to FSMC_NANDInitStruct parameters */ + tmppcr = (uint32_t)FSMC_NANDInitStruct->FSMC_Waitfeature | + PCR_MemoryType_NAND | + FSMC_NANDInitStruct->FSMC_MemoryDataWidth | + FSMC_NANDInitStruct->FSMC_ECC | + FSMC_NANDInitStruct->FSMC_ECCPageSize | + (FSMC_NANDInitStruct->FSMC_TCLRSetupTime << 9 )| + (FSMC_NANDInitStruct->FSMC_TARSetupTime << 13); + + /* Set tmppmem value according to FSMC_CommonSpaceTimingStructure parameters */ + tmppmem = (uint32_t)FSMC_NANDInitStruct->FSMC_CommonSpaceTimingStruct->FSMC_SetupTime | + (FSMC_NANDInitStruct->FSMC_CommonSpaceTimingStruct->FSMC_WaitSetupTime << 8) | + (FSMC_NANDInitStruct->FSMC_CommonSpaceTimingStruct->FSMC_HoldSetupTime << 16)| + (FSMC_NANDInitStruct->FSMC_CommonSpaceTimingStruct->FSMC_HiZSetupTime << 24); + + /* Set tmppatt value according to FSMC_AttributeSpaceTimingStructure parameters */ + tmppatt = (uint32_t)FSMC_NANDInitStruct->FSMC_AttributeSpaceTimingStruct->FSMC_SetupTime | + (FSMC_NANDInitStruct->FSMC_AttributeSpaceTimingStruct->FSMC_WaitSetupTime << 8) | + (FSMC_NANDInitStruct->FSMC_AttributeSpaceTimingStruct->FSMC_HoldSetupTime << 16)| + (FSMC_NANDInitStruct->FSMC_AttributeSpaceTimingStruct->FSMC_HiZSetupTime << 24); + + if(FSMC_NANDInitStruct->FSMC_Bank == FSMC_Bank2_NAND) + { + /* FSMC_Bank2_NAND registers configuration */ + FSMC_Bank2->PCR2 = tmppcr; + FSMC_Bank2->PMEM2 = tmppmem; + FSMC_Bank2->PATT2 = tmppatt; + } + else + { + /* FSMC_Bank3_NAND registers configuration */ + FSMC_Bank3->PCR3 = tmppcr; + FSMC_Bank3->PMEM3 = tmppmem; + FSMC_Bank3->PATT3 = tmppatt; + } +} + +/** + * @brief Initializes the FSMC PCCARD Bank according to the specified + * parameters in the FSMC_PCCARDInitStruct. + * @param FSMC_PCCARDInitStruct : pointer to a FSMC_PCCARDInitTypeDef + * structure that contains the configuration information for the FSMC + * PCCARD Bank. + * @retval None + */ +void FSMC_PCCARDInit(FSMC_PCCARDInitTypeDef* FSMC_PCCARDInitStruct) +{ + /* Check the parameters */ + assert_param(IS_FSMC_WAIT_FEATURE(FSMC_PCCARDInitStruct->FSMC_Waitfeature)); + assert_param(IS_FSMC_TCLR_TIME(FSMC_PCCARDInitStruct->FSMC_TCLRSetupTime)); + assert_param(IS_FSMC_TAR_TIME(FSMC_PCCARDInitStruct->FSMC_TARSetupTime)); + + assert_param(IS_FSMC_SETUP_TIME(FSMC_PCCARDInitStruct->FSMC_CommonSpaceTimingStruct->FSMC_SetupTime)); + assert_param(IS_FSMC_WAIT_TIME(FSMC_PCCARDInitStruct->FSMC_CommonSpaceTimingStruct->FSMC_WaitSetupTime)); + assert_param(IS_FSMC_HOLD_TIME(FSMC_PCCARDInitStruct->FSMC_CommonSpaceTimingStruct->FSMC_HoldSetupTime)); + assert_param(IS_FSMC_HIZ_TIME(FSMC_PCCARDInitStruct->FSMC_CommonSpaceTimingStruct->FSMC_HiZSetupTime)); + + assert_param(IS_FSMC_SETUP_TIME(FSMC_PCCARDInitStruct->FSMC_AttributeSpaceTimingStruct->FSMC_SetupTime)); + assert_param(IS_FSMC_WAIT_TIME(FSMC_PCCARDInitStruct->FSMC_AttributeSpaceTimingStruct->FSMC_WaitSetupTime)); + assert_param(IS_FSMC_HOLD_TIME(FSMC_PCCARDInitStruct->FSMC_AttributeSpaceTimingStruct->FSMC_HoldSetupTime)); + assert_param(IS_FSMC_HIZ_TIME(FSMC_PCCARDInitStruct->FSMC_AttributeSpaceTimingStruct->FSMC_HiZSetupTime)); + assert_param(IS_FSMC_SETUP_TIME(FSMC_PCCARDInitStruct->FSMC_IOSpaceTimingStruct->FSMC_SetupTime)); + assert_param(IS_FSMC_WAIT_TIME(FSMC_PCCARDInitStruct->FSMC_IOSpaceTimingStruct->FSMC_WaitSetupTime)); + assert_param(IS_FSMC_HOLD_TIME(FSMC_PCCARDInitStruct->FSMC_IOSpaceTimingStruct->FSMC_HoldSetupTime)); + assert_param(IS_FSMC_HIZ_TIME(FSMC_PCCARDInitStruct->FSMC_IOSpaceTimingStruct->FSMC_HiZSetupTime)); + + /* Set the PCR4 register value according to FSMC_PCCARDInitStruct parameters */ + FSMC_Bank4->PCR4 = (uint32_t)FSMC_PCCARDInitStruct->FSMC_Waitfeature | + FSMC_MemoryDataWidth_16b | + (FSMC_PCCARDInitStruct->FSMC_TCLRSetupTime << 9) | + (FSMC_PCCARDInitStruct->FSMC_TARSetupTime << 13); + + /* Set PMEM4 register value according to FSMC_CommonSpaceTimingStructure parameters */ + FSMC_Bank4->PMEM4 = (uint32_t)FSMC_PCCARDInitStruct->FSMC_CommonSpaceTimingStruct->FSMC_SetupTime | + (FSMC_PCCARDInitStruct->FSMC_CommonSpaceTimingStruct->FSMC_WaitSetupTime << 8) | + (FSMC_PCCARDInitStruct->FSMC_CommonSpaceTimingStruct->FSMC_HoldSetupTime << 16)| + (FSMC_PCCARDInitStruct->FSMC_CommonSpaceTimingStruct->FSMC_HiZSetupTime << 24); + + /* Set PATT4 register value according to FSMC_AttributeSpaceTimingStructure parameters */ + FSMC_Bank4->PATT4 = (uint32_t)FSMC_PCCARDInitStruct->FSMC_AttributeSpaceTimingStruct->FSMC_SetupTime | + (FSMC_PCCARDInitStruct->FSMC_AttributeSpaceTimingStruct->FSMC_WaitSetupTime << 8) | + (FSMC_PCCARDInitStruct->FSMC_AttributeSpaceTimingStruct->FSMC_HoldSetupTime << 16)| + (FSMC_PCCARDInitStruct->FSMC_AttributeSpaceTimingStruct->FSMC_HiZSetupTime << 24); + + /* Set PIO4 register value according to FSMC_IOSpaceTimingStructure parameters */ + FSMC_Bank4->PIO4 = (uint32_t)FSMC_PCCARDInitStruct->FSMC_IOSpaceTimingStruct->FSMC_SetupTime | + (FSMC_PCCARDInitStruct->FSMC_IOSpaceTimingStruct->FSMC_WaitSetupTime << 8) | + (FSMC_PCCARDInitStruct->FSMC_IOSpaceTimingStruct->FSMC_HoldSetupTime << 16)| + (FSMC_PCCARDInitStruct->FSMC_IOSpaceTimingStruct->FSMC_HiZSetupTime << 24); +} + +/** + * @brief Fills each FSMC_NORSRAMInitStruct member with its default value. + * @param FSMC_NORSRAMInitStruct: pointer to a FSMC_NORSRAMInitTypeDef + * structure which will be initialized. + * @retval None + */ +void FSMC_NORSRAMStructInit(FSMC_NORSRAMInitTypeDef* FSMC_NORSRAMInitStruct) +{ + /* Reset NOR/SRAM Init structure parameters values */ + FSMC_NORSRAMInitStruct->FSMC_Bank = FSMC_Bank1_NORSRAM1; + FSMC_NORSRAMInitStruct->FSMC_DataAddressMux = FSMC_DataAddressMux_Enable; + FSMC_NORSRAMInitStruct->FSMC_MemoryType = FSMC_MemoryType_SRAM; + FSMC_NORSRAMInitStruct->FSMC_MemoryDataWidth = FSMC_MemoryDataWidth_8b; + FSMC_NORSRAMInitStruct->FSMC_BurstAccessMode = FSMC_BurstAccessMode_Disable; + FSMC_NORSRAMInitStruct->FSMC_AsynchronousWait = FSMC_AsynchronousWait_Disable; + FSMC_NORSRAMInitStruct->FSMC_WaitSignalPolarity = FSMC_WaitSignalPolarity_Low; + FSMC_NORSRAMInitStruct->FSMC_WrapMode = FSMC_WrapMode_Disable; + FSMC_NORSRAMInitStruct->FSMC_WaitSignalActive = FSMC_WaitSignalActive_BeforeWaitState; + FSMC_NORSRAMInitStruct->FSMC_WriteOperation = FSMC_WriteOperation_Enable; + FSMC_NORSRAMInitStruct->FSMC_WaitSignal = FSMC_WaitSignal_Enable; + FSMC_NORSRAMInitStruct->FSMC_ExtendedMode = FSMC_ExtendedMode_Disable; + FSMC_NORSRAMInitStruct->FSMC_WriteBurst = FSMC_WriteBurst_Disable; + FSMC_NORSRAMInitStruct->FSMC_ReadWriteTimingStruct->FSMC_AddressSetupTime = 0xF; + FSMC_NORSRAMInitStruct->FSMC_ReadWriteTimingStruct->FSMC_AddressHoldTime = 0xF; + FSMC_NORSRAMInitStruct->FSMC_ReadWriteTimingStruct->FSMC_DataSetupTime = 0xFF; + FSMC_NORSRAMInitStruct->FSMC_ReadWriteTimingStruct->FSMC_BusTurnAroundDuration = 0xF; + FSMC_NORSRAMInitStruct->FSMC_ReadWriteTimingStruct->FSMC_CLKDivision = 0xF; + FSMC_NORSRAMInitStruct->FSMC_ReadWriteTimingStruct->FSMC_DataLatency = 0xF; + FSMC_NORSRAMInitStruct->FSMC_ReadWriteTimingStruct->FSMC_AccessMode = FSMC_AccessMode_A; + FSMC_NORSRAMInitStruct->FSMC_WriteTimingStruct->FSMC_AddressSetupTime = 0xF; + FSMC_NORSRAMInitStruct->FSMC_WriteTimingStruct->FSMC_AddressHoldTime = 0xF; + FSMC_NORSRAMInitStruct->FSMC_WriteTimingStruct->FSMC_DataSetupTime = 0xFF; + FSMC_NORSRAMInitStruct->FSMC_WriteTimingStruct->FSMC_BusTurnAroundDuration = 0xF; + FSMC_NORSRAMInitStruct->FSMC_WriteTimingStruct->FSMC_CLKDivision = 0xF; + FSMC_NORSRAMInitStruct->FSMC_WriteTimingStruct->FSMC_DataLatency = 0xF; + FSMC_NORSRAMInitStruct->FSMC_WriteTimingStruct->FSMC_AccessMode = FSMC_AccessMode_A; +} + +/** + * @brief Fills each FSMC_NANDInitStruct member with its default value. + * @param FSMC_NANDInitStruct: pointer to a FSMC_NANDInitTypeDef + * structure which will be initialized. + * @retval None + */ +void FSMC_NANDStructInit(FSMC_NANDInitTypeDef* FSMC_NANDInitStruct) +{ + /* Reset NAND Init structure parameters values */ + FSMC_NANDInitStruct->FSMC_Bank = FSMC_Bank2_NAND; + FSMC_NANDInitStruct->FSMC_Waitfeature = FSMC_Waitfeature_Disable; + FSMC_NANDInitStruct->FSMC_MemoryDataWidth = FSMC_MemoryDataWidth_8b; + FSMC_NANDInitStruct->FSMC_ECC = FSMC_ECC_Disable; + FSMC_NANDInitStruct->FSMC_ECCPageSize = FSMC_ECCPageSize_256Bytes; + FSMC_NANDInitStruct->FSMC_TCLRSetupTime = 0x0; + FSMC_NANDInitStruct->FSMC_TARSetupTime = 0x0; + FSMC_NANDInitStruct->FSMC_CommonSpaceTimingStruct->FSMC_SetupTime = 0xFC; + FSMC_NANDInitStruct->FSMC_CommonSpaceTimingStruct->FSMC_WaitSetupTime = 0xFC; + FSMC_NANDInitStruct->FSMC_CommonSpaceTimingStruct->FSMC_HoldSetupTime = 0xFC; + FSMC_NANDInitStruct->FSMC_CommonSpaceTimingStruct->FSMC_HiZSetupTime = 0xFC; + FSMC_NANDInitStruct->FSMC_AttributeSpaceTimingStruct->FSMC_SetupTime = 0xFC; + FSMC_NANDInitStruct->FSMC_AttributeSpaceTimingStruct->FSMC_WaitSetupTime = 0xFC; + FSMC_NANDInitStruct->FSMC_AttributeSpaceTimingStruct->FSMC_HoldSetupTime = 0xFC; + FSMC_NANDInitStruct->FSMC_AttributeSpaceTimingStruct->FSMC_HiZSetupTime = 0xFC; +} + +/** + * @brief Fills each FSMC_PCCARDInitStruct member with its default value. + * @param FSMC_PCCARDInitStruct: pointer to a FSMC_PCCARDInitTypeDef + * structure which will be initialized. + * @retval None + */ +void FSMC_PCCARDStructInit(FSMC_PCCARDInitTypeDef* FSMC_PCCARDInitStruct) +{ + /* Reset PCCARD Init structure parameters values */ + FSMC_PCCARDInitStruct->FSMC_Waitfeature = FSMC_Waitfeature_Disable; + FSMC_PCCARDInitStruct->FSMC_TCLRSetupTime = 0x0; + FSMC_PCCARDInitStruct->FSMC_TARSetupTime = 0x0; + FSMC_PCCARDInitStruct->FSMC_CommonSpaceTimingStruct->FSMC_SetupTime = 0xFC; + FSMC_PCCARDInitStruct->FSMC_CommonSpaceTimingStruct->FSMC_WaitSetupTime = 0xFC; + FSMC_PCCARDInitStruct->FSMC_CommonSpaceTimingStruct->FSMC_HoldSetupTime = 0xFC; + FSMC_PCCARDInitStruct->FSMC_CommonSpaceTimingStruct->FSMC_HiZSetupTime = 0xFC; + FSMC_PCCARDInitStruct->FSMC_AttributeSpaceTimingStruct->FSMC_SetupTime = 0xFC; + FSMC_PCCARDInitStruct->FSMC_AttributeSpaceTimingStruct->FSMC_WaitSetupTime = 0xFC; + FSMC_PCCARDInitStruct->FSMC_AttributeSpaceTimingStruct->FSMC_HoldSetupTime = 0xFC; + FSMC_PCCARDInitStruct->FSMC_AttributeSpaceTimingStruct->FSMC_HiZSetupTime = 0xFC; + FSMC_PCCARDInitStruct->FSMC_IOSpaceTimingStruct->FSMC_SetupTime = 0xFC; + FSMC_PCCARDInitStruct->FSMC_IOSpaceTimingStruct->FSMC_WaitSetupTime = 0xFC; + FSMC_PCCARDInitStruct->FSMC_IOSpaceTimingStruct->FSMC_HoldSetupTime = 0xFC; + FSMC_PCCARDInitStruct->FSMC_IOSpaceTimingStruct->FSMC_HiZSetupTime = 0xFC; +} + +/** + * @brief Enables or disables the specified NOR/SRAM Memory Bank. + * @param FSMC_Bank: specifies the FSMC Bank to be used + * This parameter can be one of the following values: + * @arg FSMC_Bank1_NORSRAM1: FSMC Bank1 NOR/SRAM1 + * @arg FSMC_Bank1_NORSRAM2: FSMC Bank1 NOR/SRAM2 + * @arg FSMC_Bank1_NORSRAM3: FSMC Bank1 NOR/SRAM3 + * @arg FSMC_Bank1_NORSRAM4: FSMC Bank1 NOR/SRAM4 + * @param NewState: new state of the FSMC_Bank. This parameter can be: ENABLE or DISABLE. + * @retval None + */ +void FSMC_NORSRAMCmd(uint32_t FSMC_Bank, FunctionalState NewState) +{ + assert_param(IS_FSMC_NORSRAM_BANK(FSMC_Bank)); + assert_param(IS_FUNCTIONAL_STATE(NewState)); + + if (NewState != DISABLE) + { + /* Enable the selected NOR/SRAM Bank by setting the PBKEN bit in the BCRx register */ + FSMC_Bank1->BTCR[FSMC_Bank] |= BCR_MBKEN_Set; + } + else + { + /* Disable the selected NOR/SRAM Bank by clearing the PBKEN bit in the BCRx register */ + FSMC_Bank1->BTCR[FSMC_Bank] &= BCR_MBKEN_Reset; + } +} + +/** + * @brief Enables or disables the specified NAND Memory Bank. + * @param FSMC_Bank: specifies the FSMC Bank to be used + * This parameter can be one of the following values: + * @arg FSMC_Bank2_NAND: FSMC Bank2 NAND + * @arg FSMC_Bank3_NAND: FSMC Bank3 NAND + * @param NewState: new state of the FSMC_Bank. This parameter can be: ENABLE or DISABLE. + * @retval None + */ +void FSMC_NANDCmd(uint32_t FSMC_Bank, FunctionalState NewState) +{ + assert_param(IS_FSMC_NAND_BANK(FSMC_Bank)); + assert_param(IS_FUNCTIONAL_STATE(NewState)); + + if (NewState != DISABLE) + { + /* Enable the selected NAND Bank by setting the PBKEN bit in the PCRx register */ + if(FSMC_Bank == FSMC_Bank2_NAND) + { + FSMC_Bank2->PCR2 |= PCR_PBKEN_Set; + } + else + { + FSMC_Bank3->PCR3 |= PCR_PBKEN_Set; + } + } + else + { + /* Disable the selected NAND Bank by clearing the PBKEN bit in the PCRx register */ + if(FSMC_Bank == FSMC_Bank2_NAND) + { + FSMC_Bank2->PCR2 &= PCR_PBKEN_Reset; + } + else + { + FSMC_Bank3->PCR3 &= PCR_PBKEN_Reset; + } + } +} + +/** + * @brief Enables or disables the PCCARD Memory Bank. + * @param NewState: new state of the PCCARD Memory Bank. + * This parameter can be: ENABLE or DISABLE. + * @retval None + */ +void FSMC_PCCARDCmd(FunctionalState NewState) +{ + assert_param(IS_FUNCTIONAL_STATE(NewState)); + + if (NewState != DISABLE) + { + /* Enable the PCCARD Bank by setting the PBKEN bit in the PCR4 register */ + FSMC_Bank4->PCR4 |= PCR_PBKEN_Set; + } + else + { + /* Disable the PCCARD Bank by clearing the PBKEN bit in the PCR4 register */ + FSMC_Bank4->PCR4 &= PCR_PBKEN_Reset; + } +} + +/** + * @brief Enables or disables the FSMC NAND ECC feature. + * @param FSMC_Bank: specifies the FSMC Bank to be used + * This parameter can be one of the following values: + * @arg FSMC_Bank2_NAND: FSMC Bank2 NAND + * @arg FSMC_Bank3_NAND: FSMC Bank3 NAND + * @param NewState: new state of the FSMC NAND ECC feature. + * This parameter can be: ENABLE or DISABLE. + * @retval None + */ +void FSMC_NANDECCCmd(uint32_t FSMC_Bank, FunctionalState NewState) +{ + assert_param(IS_FSMC_NAND_BANK(FSMC_Bank)); + assert_param(IS_FUNCTIONAL_STATE(NewState)); + + if (NewState != DISABLE) + { + /* Enable the selected NAND Bank ECC function by setting the ECCEN bit in the PCRx register */ + if(FSMC_Bank == FSMC_Bank2_NAND) + { + FSMC_Bank2->PCR2 |= PCR_ECCEN_Set; + } + else + { + FSMC_Bank3->PCR3 |= PCR_ECCEN_Set; + } + } + else + { + /* Disable the selected NAND Bank ECC function by clearing the ECCEN bit in the PCRx register */ + if(FSMC_Bank == FSMC_Bank2_NAND) + { + FSMC_Bank2->PCR2 &= PCR_ECCEN_Reset; + } + else + { + FSMC_Bank3->PCR3 &= PCR_ECCEN_Reset; + } + } +} + +/** + * @brief Returns the error correction code register value. + * @param FSMC_Bank: specifies the FSMC Bank to be used + * This parameter can be one of the following values: + * @arg FSMC_Bank2_NAND: FSMC Bank2 NAND + * @arg FSMC_Bank3_NAND: FSMC Bank3 NAND + * @retval The Error Correction Code (ECC) value. + */ +uint32_t FSMC_GetECC(uint32_t FSMC_Bank) +{ + uint32_t eccval = 0x00000000; + + if(FSMC_Bank == FSMC_Bank2_NAND) + { + /* Get the ECCR2 register value */ + eccval = FSMC_Bank2->ECCR2; + } + else + { + /* Get the ECCR3 register value */ + eccval = FSMC_Bank3->ECCR3; + } + /* Return the error correction code value */ + return(eccval); +} + +/** + * @brief Enables or disables the specified FSMC interrupts. + * @param FSMC_Bank: specifies the FSMC Bank to be used + * This parameter can be one of the following values: + * @arg FSMC_Bank2_NAND: FSMC Bank2 NAND + * @arg FSMC_Bank3_NAND: FSMC Bank3 NAND + * @arg FSMC_Bank4_PCCARD: FSMC Bank4 PCCARD + * @param FSMC_IT: specifies the FSMC interrupt sources to be enabled or disabled. + * This parameter can be any combination of the following values: + * @arg FSMC_IT_RisingEdge: Rising edge detection interrupt. + * @arg FSMC_IT_Level: Level edge detection interrupt. + * @arg FSMC_IT_FallingEdge: Falling edge detection interrupt. + * @param NewState: new state of the specified FSMC interrupts. + * This parameter can be: ENABLE or DISABLE. + * @retval None + */ +void FSMC_ITConfig(uint32_t FSMC_Bank, uint32_t FSMC_IT, FunctionalState NewState) +{ + assert_param(IS_FSMC_IT_BANK(FSMC_Bank)); + assert_param(IS_FSMC_IT(FSMC_IT)); + assert_param(IS_FUNCTIONAL_STATE(NewState)); + + if (NewState != DISABLE) + { + /* Enable the selected FSMC_Bank2 interrupts */ + if(FSMC_Bank == FSMC_Bank2_NAND) + { + FSMC_Bank2->SR2 |= FSMC_IT; + } + /* Enable the selected FSMC_Bank3 interrupts */ + else if (FSMC_Bank == FSMC_Bank3_NAND) + { + FSMC_Bank3->SR3 |= FSMC_IT; + } + /* Enable the selected FSMC_Bank4 interrupts */ + else + { + FSMC_Bank4->SR4 |= FSMC_IT; + } + } + else + { + /* Disable the selected FSMC_Bank2 interrupts */ + if(FSMC_Bank == FSMC_Bank2_NAND) + { + + FSMC_Bank2->SR2 &= (uint32_t)~FSMC_IT; + } + /* Disable the selected FSMC_Bank3 interrupts */ + else if (FSMC_Bank == FSMC_Bank3_NAND) + { + FSMC_Bank3->SR3 &= (uint32_t)~FSMC_IT; + } + /* Disable the selected FSMC_Bank4 interrupts */ + else + { + FSMC_Bank4->SR4 &= (uint32_t)~FSMC_IT; + } + } +} + +/** + * @brief Checks whether the specified FSMC flag is set or not. + * @param FSMC_Bank: specifies the FSMC Bank to be used + * This parameter can be one of the following values: + * @arg FSMC_Bank2_NAND: FSMC Bank2 NAND + * @arg FSMC_Bank3_NAND: FSMC Bank3 NAND + * @arg FSMC_Bank4_PCCARD: FSMC Bank4 PCCARD + * @param FSMC_FLAG: specifies the flag to check. + * This parameter can be one of the following values: + * @arg FSMC_FLAG_RisingEdge: Rising egde detection Flag. + * @arg FSMC_FLAG_Level: Level detection Flag. + * @arg FSMC_FLAG_FallingEdge: Falling egde detection Flag. + * @arg FSMC_FLAG_FEMPT: Fifo empty Flag. + * @retval The new state of FSMC_FLAG (SET or RESET). + */ +FlagStatus FSMC_GetFlagStatus(uint32_t FSMC_Bank, uint32_t FSMC_FLAG) +{ + FlagStatus bitstatus = RESET; + uint32_t tmpsr = 0x00000000; + + /* Check the parameters */ + assert_param(IS_FSMC_GETFLAG_BANK(FSMC_Bank)); + assert_param(IS_FSMC_GET_FLAG(FSMC_FLAG)); + + if(FSMC_Bank == FSMC_Bank2_NAND) + { + tmpsr = FSMC_Bank2->SR2; + } + else if(FSMC_Bank == FSMC_Bank3_NAND) + { + tmpsr = FSMC_Bank3->SR3; + } + /* FSMC_Bank4_PCCARD*/ + else + { + tmpsr = FSMC_Bank4->SR4; + } + + /* Get the flag status */ + if ((tmpsr & FSMC_FLAG) != (uint16_t)RESET ) + { + bitstatus = SET; + } + else + { + bitstatus = RESET; + } + /* Return the flag status */ + return bitstatus; +} + +/** + * @brief Clears the FSMC's pending flags. + * @param FSMC_Bank: specifies the FSMC Bank to be used + * This parameter can be one of the following values: + * @arg FSMC_Bank2_NAND: FSMC Bank2 NAND + * @arg FSMC_Bank3_NAND: FSMC Bank3 NAND + * @arg FSMC_Bank4_PCCARD: FSMC Bank4 PCCARD + * @param FSMC_FLAG: specifies the flag to clear. + * This parameter can be any combination of the following values: + * @arg FSMC_FLAG_RisingEdge: Rising egde detection Flag. + * @arg FSMC_FLAG_Level: Level detection Flag. + * @arg FSMC_FLAG_FallingEdge: Falling egde detection Flag. + * @retval None + */ +void FSMC_ClearFlag(uint32_t FSMC_Bank, uint32_t FSMC_FLAG) +{ + /* Check the parameters */ + assert_param(IS_FSMC_GETFLAG_BANK(FSMC_Bank)); + assert_param(IS_FSMC_CLEAR_FLAG(FSMC_FLAG)) ; + + if(FSMC_Bank == FSMC_Bank2_NAND) + { + FSMC_Bank2->SR2 &= ~FSMC_FLAG; + } + else if(FSMC_Bank == FSMC_Bank3_NAND) + { + FSMC_Bank3->SR3 &= ~FSMC_FLAG; + } + /* FSMC_Bank4_PCCARD*/ + else + { + FSMC_Bank4->SR4 &= ~FSMC_FLAG; + } +} + +/** + * @brief Checks whether the specified FSMC interrupt has occurred or not. + * @param FSMC_Bank: specifies the FSMC Bank to be used + * This parameter can be one of the following values: + * @arg FSMC_Bank2_NAND: FSMC Bank2 NAND + * @arg FSMC_Bank3_NAND: FSMC Bank3 NAND + * @arg FSMC_Bank4_PCCARD: FSMC Bank4 PCCARD + * @param FSMC_IT: specifies the FSMC interrupt source to check. + * This parameter can be one of the following values: + * @arg FSMC_IT_RisingEdge: Rising edge detection interrupt. + * @arg FSMC_IT_Level: Level edge detection interrupt. + * @arg FSMC_IT_FallingEdge: Falling edge detection interrupt. + * @retval The new state of FSMC_IT (SET or RESET). + */ +ITStatus FSMC_GetITStatus(uint32_t FSMC_Bank, uint32_t FSMC_IT) +{ + ITStatus bitstatus = RESET; + uint32_t tmpsr = 0x0, itstatus = 0x0, itenable = 0x0; + + /* Check the parameters */ + assert_param(IS_FSMC_IT_BANK(FSMC_Bank)); + assert_param(IS_FSMC_GET_IT(FSMC_IT)); + + if(FSMC_Bank == FSMC_Bank2_NAND) + { + tmpsr = FSMC_Bank2->SR2; + } + else if(FSMC_Bank == FSMC_Bank3_NAND) + { + tmpsr = FSMC_Bank3->SR3; + } + /* FSMC_Bank4_PCCARD*/ + else + { + tmpsr = FSMC_Bank4->SR4; + } + + itstatus = tmpsr & FSMC_IT; + + itenable = tmpsr & (FSMC_IT >> 3); + if ((itstatus != (uint32_t)RESET) && (itenable != (uint32_t)RESET)) + { + bitstatus = SET; + } + else + { + bitstatus = RESET; + } + return bitstatus; +} + +/** + * @brief Clears the FSMC's interrupt pending bits. + * @param FSMC_Bank: specifies the FSMC Bank to be used + * This parameter can be one of the following values: + * @arg FSMC_Bank2_NAND: FSMC Bank2 NAND + * @arg FSMC_Bank3_NAND: FSMC Bank3 NAND + * @arg FSMC_Bank4_PCCARD: FSMC Bank4 PCCARD + * @param FSMC_IT: specifies the interrupt pending bit to clear. + * This parameter can be any combination of the following values: + * @arg FSMC_IT_RisingEdge: Rising edge detection interrupt. + * @arg FSMC_IT_Level: Level edge detection interrupt. + * @arg FSMC_IT_FallingEdge: Falling edge detection interrupt. + * @retval None + */ +void FSMC_ClearITPendingBit(uint32_t FSMC_Bank, uint32_t FSMC_IT) +{ + /* Check the parameters */ + assert_param(IS_FSMC_IT_BANK(FSMC_Bank)); + assert_param(IS_FSMC_IT(FSMC_IT)); + + if(FSMC_Bank == FSMC_Bank2_NAND) + { + FSMC_Bank2->SR2 &= ~(FSMC_IT >> 3); + } + else if(FSMC_Bank == FSMC_Bank3_NAND) + { + FSMC_Bank3->SR3 &= ~(FSMC_IT >> 3); + } + /* FSMC_Bank4_PCCARD*/ + else + { + FSMC_Bank4->SR4 &= ~(FSMC_IT >> 3); + } +} + +/** + * @} + */ + +/** + * @} + */ + +/** + * @} + */ + +/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ diff --git a/Libraries/STM32F10x_StdPeriph_Driver/src/stm32f10x_gpio.c b/Libraries/STM32F10x_StdPeriph_Driver/src/stm32f10x_gpio.c new file mode 100644 index 0000000..1b7e0d5 --- /dev/null +++ b/Libraries/STM32F10x_StdPeriph_Driver/src/stm32f10x_gpio.c @@ -0,0 +1,654 @@ +/** + ****************************************************************************** + * @file stm32f10x_gpio.c + * @author MCD Application Team + * @version V3.6.1 + * @date 05-March-2012 + * @brief This file provides all the GPIO firmware functions. + ****************************************************************************** + * @attention + * + *

    © COPYRIGHT 2012 STMicroelectronics

    + * + * Licensed under MCD-ST Liberty SW License Agreement V2, (the "License"); + * You may not use this file except in compliance with the License. + * You may obtain a copy of the License at: + * + * http://www.st.com/software_license_agreement_liberty_v2 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, + * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + * + ****************************************************************************** + */ + +/* Includes ------------------------------------------------------------------*/ +#include "stm32f10x_gpio.h" +#include "stm32f10x_rcc.h" + +/** @addtogroup STM32F10x_StdPeriph_Driver + * @{ + */ + +/** @defgroup GPIO + * @brief GPIO driver modules + * @{ + */ + +/** @defgroup GPIO_Private_TypesDefinitions + * @{ + */ + +/** + * @} + */ + +/** @defgroup GPIO_Private_Defines + * @{ + */ + +/* ------------ RCC registers bit address in the alias region ----------------*/ +#define AFIO_OFFSET (AFIO_BASE - PERIPH_BASE) + +/* --- EVENTCR Register -----*/ + +/* Alias word address of EVOE bit */ +#define EVCR_OFFSET (AFIO_OFFSET + 0x00) +#define EVOE_BitNumber ((uint8_t)0x07) +#define EVCR_EVOE_BB (PERIPH_BB_BASE + (EVCR_OFFSET * 32) + (EVOE_BitNumber * 4)) + +/* --- MAPR Register ---*/ +/* Alias word address of MII_RMII_SEL bit */ +#define MAPR_OFFSET (AFIO_OFFSET + 0x04) +#define MII_RMII_SEL_BitNumber ((u8)0x17) +#define MAPR_MII_RMII_SEL_BB (PERIPH_BB_BASE + (MAPR_OFFSET * 32) + (MII_RMII_SEL_BitNumber * 4)) + +#define EVCR_PORTPINCONFIG_MASK ((uint16_t)0xFF80) +#define LSB_MASK ((uint16_t)0xFFFF) +#define DBGAFR_POSITION_MASK ((uint32_t)0x000F0000) +#define DBGAFR_SWJCFG_MASK ((uint32_t)0xF0FFFFFF) +#define DBGAFR_LOCATION_MASK ((uint32_t)0x00200000) +#define DBGAFR_NUMBITS_MASK ((uint32_t)0x00100000) +/** + * @} + */ + +/** @defgroup GPIO_Private_Macros + * @{ + */ + +/** + * @} + */ + +/** @defgroup GPIO_Private_Variables + * @{ + */ + +/** + * @} + */ + +/** @defgroup GPIO_Private_FunctionPrototypes + * @{ + */ + +/** + * @} + */ + +/** @defgroup GPIO_Private_Functions + * @{ + */ + +/** + * @brief Deinitializes the GPIOx peripheral registers to their default reset values. + * @param GPIOx: where x can be (A..G) to select the GPIO peripheral. + * @retval None + */ +void GPIO_DeInit(GPIO_TypeDef *GPIOx) +{ + /* Check the parameters */ + assert_param(IS_GPIO_ALL_PERIPH(GPIOx)); + + if (GPIOx == GPIOA) + { + RCC_APB2PeriphResetCmd(RCC_APB2Periph_GPIOA, ENABLE); + RCC_APB2PeriphResetCmd(RCC_APB2Periph_GPIOA, DISABLE); + } + else if (GPIOx == GPIOB) + { + RCC_APB2PeriphResetCmd(RCC_APB2Periph_GPIOB, ENABLE); + RCC_APB2PeriphResetCmd(RCC_APB2Periph_GPIOB, DISABLE); + } + else if (GPIOx == GPIOC) + { + RCC_APB2PeriphResetCmd(RCC_APB2Periph_GPIOC, ENABLE); + RCC_APB2PeriphResetCmd(RCC_APB2Periph_GPIOC, DISABLE); + } + else if (GPIOx == GPIOD) + { + RCC_APB2PeriphResetCmd(RCC_APB2Periph_GPIOD, ENABLE); + RCC_APB2PeriphResetCmd(RCC_APB2Periph_GPIOD, DISABLE); + } + else if (GPIOx == GPIOE) + { + RCC_APB2PeriphResetCmd(RCC_APB2Periph_GPIOE, ENABLE); + RCC_APB2PeriphResetCmd(RCC_APB2Periph_GPIOE, DISABLE); + } + else if (GPIOx == GPIOF) + { + RCC_APB2PeriphResetCmd(RCC_APB2Periph_GPIOF, ENABLE); + RCC_APB2PeriphResetCmd(RCC_APB2Periph_GPIOF, DISABLE); + } + else + { + if (GPIOx == GPIOG) + { + RCC_APB2PeriphResetCmd(RCC_APB2Periph_GPIOG, ENABLE); + RCC_APB2PeriphResetCmd(RCC_APB2Periph_GPIOG, DISABLE); + } + } +} + +/** + * @brief Deinitializes the Alternate Functions (remap, event control + * and EXTI configuration) registers to their default reset values. + * @param None + * @retval None + */ +void GPIO_AFIODeInit(void) +{ + RCC_APB2PeriphResetCmd(RCC_APB2Periph_AFIO, ENABLE); + RCC_APB2PeriphResetCmd(RCC_APB2Periph_AFIO, DISABLE); +} + +/** + * @brief Initializes the GPIOx peripheral according to the specified + * parameters in the GPIO_InitStruct. + * @param GPIOx: where x can be (A..G) to select the GPIO peripheral. + * @param GPIO_InitStruct: pointer to a GPIO_InitTypeDef structure that + * contains the configuration information for the specified GPIO peripheral. + * @retval None + */ +void GPIO_Init(GPIO_TypeDef *GPIOx, GPIO_InitTypeDef *GPIO_InitStruct) +{ + uint32_t currentmode = 0x00, currentpin = 0x00, pinpos = 0x00, pos = 0x00; + uint32_t tmpreg = 0x00, pinmask = 0x00; + /* Check the parameters */ + assert_param(IS_GPIO_ALL_PERIPH(GPIOx)); + assert_param(IS_GPIO_MODE(GPIO_InitStruct->GPIO_Mode)); + assert_param(IS_GPIO_PIN(GPIO_InitStruct->GPIO_Pin)); + + /*---------------------------- GPIO Mode Configuration -----------------------*/ + currentmode = ((uint32_t)GPIO_InitStruct->GPIO_Mode) & ((uint32_t)0x0F); + if ((((uint32_t)GPIO_InitStruct->GPIO_Mode) & ((uint32_t)0x10)) != 0x00) + { + /* Check the parameters */ + assert_param(IS_GPIO_SPEED(GPIO_InitStruct->GPIO_Speed)); + /* Output mode */ + currentmode |= (uint32_t)GPIO_InitStruct->GPIO_Speed; + } + /*---------------------------- GPIO CRL Configuration ------------------------*/ + /* Configure the eight low port pins */ + if (((uint32_t)GPIO_InitStruct->GPIO_Pin & ((uint32_t)0x00FF)) != 0x00) + { + tmpreg = GPIOx->CRL; + for (pinpos = 0x00; pinpos < 0x08; pinpos++) + { + pos = ((uint32_t)0x01) << pinpos; + /* Get the port pins position */ + currentpin = (GPIO_InitStruct->GPIO_Pin) & pos; + if (currentpin == pos) + { + pos = pinpos << 2; + /* Clear the corresponding low control register bits */ + pinmask = ((uint32_t)0x0F) << pos; + tmpreg &= ~pinmask; + /* Write the mode configuration in the corresponding bits */ + tmpreg |= (currentmode << pos); + /* Reset the corresponding ODR bit */ + if (GPIO_InitStruct->GPIO_Mode == GPIO_Mode_IPD) + { + GPIOx->BRR = (((uint32_t)0x01) << pinpos); + } + else + { + /* Set the corresponding ODR bit */ + if (GPIO_InitStruct->GPIO_Mode == GPIO_Mode_IPU) + { + GPIOx->BSRR = (((uint32_t)0x01) << pinpos); + } + } + } + } + GPIOx->CRL = tmpreg; + } + /*---------------------------- GPIO CRH Configuration ------------------------*/ + /* Configure the eight high port pins */ + if (GPIO_InitStruct->GPIO_Pin > 0x00FF) + { + tmpreg = GPIOx->CRH; + for (pinpos = 0x00; pinpos < 0x08; pinpos++) + { + pos = (((uint32_t)0x01) << (pinpos + 0x08)); + /* Get the port pins position */ + currentpin = ((GPIO_InitStruct->GPIO_Pin) & pos); + if (currentpin == pos) + { + pos = pinpos << 2; + /* Clear the corresponding high control register bits */ + pinmask = ((uint32_t)0x0F) << pos; + tmpreg &= ~pinmask; + /* Write the mode configuration in the corresponding bits */ + tmpreg |= (currentmode << pos); + /* Reset the corresponding ODR bit */ + if (GPIO_InitStruct->GPIO_Mode == GPIO_Mode_IPD) + { + GPIOx->BRR = (((uint32_t)0x01) << (pinpos + 0x08)); + } + /* Set the corresponding ODR bit */ + if (GPIO_InitStruct->GPIO_Mode == GPIO_Mode_IPU) + { + GPIOx->BSRR = (((uint32_t)0x01) << (pinpos + 0x08)); + } + } + } + GPIOx->CRH = tmpreg; + } +} + +/** + * @brief Fills each GPIO_InitStruct member with its default value. + * @param GPIO_InitStruct : pointer to a GPIO_InitTypeDef structure which will + * be initialized. + * @retval None + */ +void GPIO_StructInit(GPIO_InitTypeDef *GPIO_InitStruct) +{ + /* Reset GPIO init structure parameters values */ + GPIO_InitStruct->GPIO_Pin = GPIO_Pin_All; + GPIO_InitStruct->GPIO_Speed = GPIO_Speed_2MHz; + GPIO_InitStruct->GPIO_Mode = GPIO_Mode_IN_FLOATING; +} + +/** + * @brief Reads the specified input port pin. + * @param GPIOx: where x can be (A..G) to select the GPIO peripheral. + * @param GPIO_Pin: specifies the port bit to read. + * This parameter can be GPIO_Pin_x where x can be (0..15). + * @retval The input port pin value. + */ +uint8_t GPIO_ReadInputDataBit(GPIO_TypeDef *GPIOx, uint16_t GPIO_Pin) +{ + uint8_t bitstatus = 0x00; + + /* Check the parameters */ + assert_param(IS_GPIO_ALL_PERIPH(GPIOx)); + assert_param(IS_GET_GPIO_PIN(GPIO_Pin)); + + if ((GPIOx->IDR & GPIO_Pin) != (uint32_t)Bit_RESET) + { + bitstatus = (uint8_t)Bit_SET; + } + else + { + bitstatus = (uint8_t)Bit_RESET; + } + return bitstatus; +} + +/** + * @brief Reads the specified GPIO input data port. + * @param GPIOx: where x can be (A..G) to select the GPIO peripheral. + * @retval GPIO input data port value. + */ +uint16_t GPIO_ReadInputData(GPIO_TypeDef *GPIOx) +{ + /* Check the parameters */ + assert_param(IS_GPIO_ALL_PERIPH(GPIOx)); + + return ((uint16_t)GPIOx->IDR); +} + +/** + * @brief Reads the specified output data port bit. + * @param GPIOx: where x can be (A..G) to select the GPIO peripheral. + * @param GPIO_Pin: specifies the port bit to read. + * This parameter can be GPIO_Pin_x where x can be (0..15). + * @retval The output port pin value. + */ +uint8_t GPIO_ReadOutputDataBit(GPIO_TypeDef *GPIOx, uint16_t GPIO_Pin) +{ + uint8_t bitstatus = 0x00; + /* Check the parameters */ + assert_param(IS_GPIO_ALL_PERIPH(GPIOx)); + assert_param(IS_GET_GPIO_PIN(GPIO_Pin)); + + if ((GPIOx->ODR & GPIO_Pin) != (uint32_t)Bit_RESET) + { + bitstatus = (uint8_t)Bit_SET; + } + else + { + bitstatus = (uint8_t)Bit_RESET; + } + return bitstatus; +} + +/** + * @brief Reads the specified GPIO output data port. + * @param GPIOx: where x can be (A..G) to select the GPIO peripheral. + * @retval GPIO output data port value. + */ +uint16_t GPIO_ReadOutputData(GPIO_TypeDef *GPIOx) +{ + /* Check the parameters */ + assert_param(IS_GPIO_ALL_PERIPH(GPIOx)); + + return ((uint16_t)GPIOx->ODR); +} + +/** + * @brief Sets the selected data port bits. + * @param GPIOx: where x can be (A..G) to select the GPIO peripheral. + * @param GPIO_Pin: specifies the port bits to be written. + * This parameter can be any combination of GPIO_Pin_x where x can be (0..15). + * @retval None + */ +void GPIO_SetBits(GPIO_TypeDef *GPIOx, uint16_t GPIO_Pin) +{ + /* Check the parameters */ + assert_param(IS_GPIO_ALL_PERIPH(GPIOx)); + assert_param(IS_GPIO_PIN(GPIO_Pin)); + + GPIOx->BSRR = GPIO_Pin; +} + +/** + * @brief Clears the selected data port bits. + * @param GPIOx: where x can be (A..G) to select the GPIO peripheral. + * @param GPIO_Pin: specifies the port bits to be written. + * This parameter can be any combination of GPIO_Pin_x where x can be (0..15). + * @retval None + */ +void GPIO_ResetBits(GPIO_TypeDef *GPIOx, uint16_t GPIO_Pin) +{ + /* Check the parameters */ + assert_param(IS_GPIO_ALL_PERIPH(GPIOx)); + assert_param(IS_GPIO_PIN(GPIO_Pin)); + + GPIOx->BRR = GPIO_Pin; +} + +/** + * @brief Sets or clears the selected data port bit. + * @param GPIOx: where x can be (A..G) to select the GPIO peripheral. + * @param GPIO_Pin: specifies the port bit to be written. + * This parameter can be one of GPIO_Pin_x where x can be (0..15). + * @param BitVal: specifies the value to be written to the selected bit. + * This parameter can be one of the BitAction enum values: + * @arg Bit_RESET: to clear the port pin + * @arg Bit_SET: to set the port pin + * @retval None + */ +void GPIO_WriteBit(GPIO_TypeDef *GPIOx, uint16_t GPIO_Pin, BitAction BitVal) +{ + /* Check the parameters */ + assert_param(IS_GPIO_ALL_PERIPH(GPIOx)); + assert_param(IS_GET_GPIO_PIN(GPIO_Pin)); + assert_param(IS_GPIO_BIT_ACTION(BitVal)); + + if (BitVal != Bit_RESET) + { + GPIOx->BSRR = GPIO_Pin; + } + else + { + GPIOx->BRR = GPIO_Pin; + } +} + +/** + * @brief Writes data to the specified GPIO data port. + * @param GPIOx: where x can be (A..G) to select the GPIO peripheral. + * @param PortVal: specifies the value to be written to the port output data register. + * @retval None + */ +void GPIO_Write(GPIO_TypeDef *GPIOx, uint16_t PortVal) +{ + /* Check the parameters */ + assert_param(IS_GPIO_ALL_PERIPH(GPIOx)); + + GPIOx->ODR = PortVal; +} + +/** + * @brief Locks GPIO Pins configuration registers. + * @param GPIOx: where x can be (A..G) to select the GPIO peripheral. + * @param GPIO_Pin: specifies the port bit to be written. + * This parameter can be any combination of GPIO_Pin_x where x can be (0..15). + * @retval None + */ +void GPIO_PinLockConfig(GPIO_TypeDef *GPIOx, uint16_t GPIO_Pin) +{ + uint32_t tmp = 0x00010000; + + /* Check the parameters */ + assert_param(IS_GPIO_ALL_PERIPH(GPIOx)); + assert_param(IS_GPIO_PIN(GPIO_Pin)); + + tmp |= GPIO_Pin; + /* Set LCKK bit */ + GPIOx->LCKR = tmp; + /* Reset LCKK bit */ + GPIOx->LCKR = GPIO_Pin; + /* Set LCKK bit */ + GPIOx->LCKR = tmp; + /* Read LCKK bit*/ + tmp = GPIOx->LCKR; + /* Read LCKK bit*/ + tmp = GPIOx->LCKR; +} + +/** + * @brief Selects the GPIO pin used as Event output. + * @param GPIO_PortSource: selects the GPIO port to be used as source + * for Event output. + * This parameter can be GPIO_PortSourceGPIOx where x can be (A..E). + * @param GPIO_PinSource: specifies the pin for the Event output. + * This parameter can be GPIO_PinSourcex where x can be (0..15). + * @retval None + */ +void GPIO_EventOutputConfig(uint8_t GPIO_PortSource, uint8_t GPIO_PinSource) +{ + uint32_t tmpreg = 0x00; + /* Check the parameters */ + assert_param(IS_GPIO_EVENTOUT_PORT_SOURCE(GPIO_PortSource)); + assert_param(IS_GPIO_PIN_SOURCE(GPIO_PinSource)); + + tmpreg = AFIO->EVCR; + /* Clear the PORT[6:4] and PIN[3:0] bits */ + tmpreg &= EVCR_PORTPINCONFIG_MASK; + tmpreg |= (uint32_t)GPIO_PortSource << 0x04; + tmpreg |= GPIO_PinSource; + AFIO->EVCR = tmpreg; +} + +/** + * @brief Enables or disables the Event Output. + * @param NewState: new state of the Event output. + * This parameter can be: ENABLE or DISABLE. + * @retval None + */ +void GPIO_EventOutputCmd(FunctionalState NewState) +{ + /* Check the parameters */ + assert_param(IS_FUNCTIONAL_STATE(NewState)); + + *(__IO uint32_t *)EVCR_EVOE_BB = (uint32_t)NewState; +} + +/** + * @brief Changes the mapping of the specified pin. + * @param GPIO_Remap: selects the pin to remap. + * This parameter can be one of the following values: + * @arg GPIO_Remap_SPI1 : SPI1 Alternate Function mapping + * @arg GPIO_Remap_I2C1 : I2C1 Alternate Function mapping + * @arg GPIO_Remap_USART1 : USART1 Alternate Function mapping + * @arg GPIO_Remap_USART2 : USART2 Alternate Function mapping + * @arg GPIO_PartialRemap_USART3 : USART3 Partial Alternate Function mapping + * @arg GPIO_FullRemap_USART3 : USART3 Full Alternate Function mapping + * @arg GPIO_PartialRemap_TIM1 : TIM1 Partial Alternate Function mapping + * @arg GPIO_FullRemap_TIM1 : TIM1 Full Alternate Function mapping + * @arg GPIO_PartialRemap1_TIM2 : TIM2 Partial1 Alternate Function mapping + * @arg GPIO_PartialRemap2_TIM2 : TIM2 Partial2 Alternate Function mapping + * @arg GPIO_FullRemap_TIM2 : TIM2 Full Alternate Function mapping + * @arg GPIO_PartialRemap_TIM3 : TIM3 Partial Alternate Function mapping + * @arg GPIO_FullRemap_TIM3 : TIM3 Full Alternate Function mapping + * @arg GPIO_Remap_TIM4 : TIM4 Alternate Function mapping + * @arg GPIO_Remap1_CAN1 : CAN1 Alternate Function mapping + * @arg GPIO_Remap2_CAN1 : CAN1 Alternate Function mapping + * @arg GPIO_Remap_PD01 : PD01 Alternate Function mapping + * @arg GPIO_Remap_TIM5CH4_LSI : LSI connected to TIM5 Channel4 input capture for calibration + * @arg GPIO_Remap_ADC1_ETRGINJ : ADC1 External Trigger Injected Conversion remapping + * @arg GPIO_Remap_ADC1_ETRGREG : ADC1 External Trigger Regular Conversion remapping + * @arg GPIO_Remap_ADC2_ETRGINJ : ADC2 External Trigger Injected Conversion remapping + * @arg GPIO_Remap_ADC2_ETRGREG : ADC2 External Trigger Regular Conversion remapping + * @arg GPIO_Remap_ETH : Ethernet remapping (only for Connectivity line devices) + * @arg GPIO_Remap_CAN2 : CAN2 remapping (only for Connectivity line devices) + * @arg GPIO_Remap_SWJ_NoJTRST : Full SWJ Enabled (JTAG-DP + SW-DP) but without JTRST + * @arg GPIO_Remap_SWJ_JTAGDisable : JTAG-DP Disabled and SW-DP Enabled + * @arg GPIO_Remap_SWJ_Disable : Full SWJ Disabled (JTAG-DP + SW-DP) + * @arg GPIO_Remap_SPI3 : SPI3/I2S3 Alternate Function mapping (only for Connectivity line devices) + * When the SPI3/I2S3 is remapped using this function, the SWJ is configured + * to Full SWJ Enabled (JTAG-DP + SW-DP) but without JTRST. + * @arg GPIO_Remap_TIM2ITR1_PTP_SOF : Ethernet PTP output or USB OTG SOF (Start of Frame) connected + * to TIM2 Internal Trigger 1 for calibration (only for Connectivity line devices) + * If the GPIO_Remap_TIM2ITR1_PTP_SOF is enabled the TIM2 ITR1 is connected to + * Ethernet PTP output. When Reset TIM2 ITR1 is connected to USB OTG SOF output. + * @arg GPIO_Remap_PTP_PPS : Ethernet MAC PPS_PTS output on PB05 (only for Connectivity line devices) + * @arg GPIO_Remap_TIM15 : TIM15 Alternate Function mapping (only for Value line devices) + * @arg GPIO_Remap_TIM16 : TIM16 Alternate Function mapping (only for Value line devices) + * @arg GPIO_Remap_TIM17 : TIM17 Alternate Function mapping (only for Value line devices) + * @arg GPIO_Remap_CEC : CEC Alternate Function mapping (only for Value line devices) + * @arg GPIO_Remap_TIM1_DMA : TIM1 DMA requests mapping (only for Value line devices) + * @arg GPIO_Remap_TIM9 : TIM9 Alternate Function mapping (only for XL-density devices) + * @arg GPIO_Remap_TIM10 : TIM10 Alternate Function mapping (only for XL-density devices) + * @arg GPIO_Remap_TIM11 : TIM11 Alternate Function mapping (only for XL-density devices) + * @arg GPIO_Remap_TIM13 : TIM13 Alternate Function mapping (only for High density Value line and XL-density devices) + * @arg GPIO_Remap_TIM14 : TIM14 Alternate Function mapping (only for High density Value line and XL-density devices) + * @arg GPIO_Remap_FSMC_NADV : FSMC_NADV Alternate Function mapping (only for High density Value line and XL-density devices) + * @arg GPIO_Remap_TIM67_DAC_DMA : TIM6/TIM7 and DAC DMA requests remapping (only for High density Value line devices) + * @arg GPIO_Remap_TIM12 : TIM12 Alternate Function mapping (only for High density Value line devices) + * @arg GPIO_Remap_MISC : Miscellaneous Remap (DMA2 Channel5 Position and DAC Trigger remapping, + * only for High density Value line devices) + * @param NewState: new state of the port pin remapping. + * This parameter can be: ENABLE or DISABLE. + * @retval None + */ +void GPIO_PinRemapConfig(uint32_t GPIO_Remap, FunctionalState NewState) +{ + uint32_t tmp = 0x00, tmp1 = 0x00, tmpreg = 0x00, tmpmask = 0x00; + + /* Check the parameters */ + assert_param(IS_GPIO_REMAP(GPIO_Remap)); + assert_param(IS_FUNCTIONAL_STATE(NewState)); + + if ((GPIO_Remap & 0x80000000) == 0x80000000) + { + tmpreg = AFIO->MAPR2; + } + else + { + tmpreg = AFIO->MAPR; + } + + tmpmask = (GPIO_Remap & DBGAFR_POSITION_MASK) >> 0x10; + tmp = GPIO_Remap & LSB_MASK; + + if ((GPIO_Remap & (DBGAFR_LOCATION_MASK | DBGAFR_NUMBITS_MASK)) == (DBGAFR_LOCATION_MASK | DBGAFR_NUMBITS_MASK)) + { + tmpreg &= DBGAFR_SWJCFG_MASK; + AFIO->MAPR &= DBGAFR_SWJCFG_MASK; + } + else if ((GPIO_Remap & DBGAFR_NUMBITS_MASK) == DBGAFR_NUMBITS_MASK) + { + tmp1 = ((uint32_t)0x03) << tmpmask; + tmpreg &= ~tmp1; + tmpreg |= ~DBGAFR_SWJCFG_MASK; + } + else + { + tmpreg &= ~(tmp << ((GPIO_Remap >> 0x15) * 0x10)); + tmpreg |= ~DBGAFR_SWJCFG_MASK; + } + + if (NewState != DISABLE) + { + tmpreg |= (tmp << ((GPIO_Remap >> 0x15) * 0x10)); + } + + if ((GPIO_Remap & 0x80000000) == 0x80000000) + { + AFIO->MAPR2 = tmpreg; + } + else + { + AFIO->MAPR = tmpreg; + } +} + +/** + * @brief Selects the GPIO pin used as EXTI Line. + * @param GPIO_PortSource: selects the GPIO port to be used as source for EXTI lines. + * This parameter can be GPIO_PortSourceGPIOx where x can be (A..G). + * @param GPIO_PinSource: specifies the EXTI line to be configured. + * This parameter can be GPIO_PinSourcex where x can be (0..15). + * @retval None + */ +void GPIO_EXTILineConfig(uint8_t GPIO_PortSource, uint8_t GPIO_PinSource) +{ + uint32_t tmp = 0x00; + /* Check the parameters */ + assert_param(IS_GPIO_EXTI_PORT_SOURCE(GPIO_PortSource)); + assert_param(IS_GPIO_PIN_SOURCE(GPIO_PinSource)); + + tmp = ((uint32_t)0x0F) << (0x04 * (GPIO_PinSource & (uint8_t)0x03)); + AFIO->EXTICR[GPIO_PinSource >> 0x02] &= ~tmp; + AFIO->EXTICR[GPIO_PinSource >> 0x02] |= (((uint32_t)GPIO_PortSource) << (0x04 * (GPIO_PinSource & (uint8_t)0x03))); +} + +/** + * @brief Selects the Ethernet media interface. + * @note This function applies only to STM32 Connectivity line devices. + * @param GPIO_ETH_MediaInterface: specifies the Media Interface mode. + * This parameter can be one of the following values: + * @arg GPIO_ETH_MediaInterface_MII: MII mode + * @arg GPIO_ETH_MediaInterface_RMII: RMII mode + * @retval None + */ +void GPIO_ETH_MediaInterfaceConfig(uint32_t GPIO_ETH_MediaInterface) +{ + assert_param(IS_GPIO_ETH_MEDIA_INTERFACE(GPIO_ETH_MediaInterface)); + + /* Configure MII_RMII selection bit */ + *(__IO uint32_t *)MAPR_MII_RMII_SEL_BB = GPIO_ETH_MediaInterface; +} + +/** + * @} + */ + +/** + * @} + */ + +/** + * @} + */ + +/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ diff --git a/Libraries/STM32F10x_StdPeriph_Driver/src/stm32f10x_i2c.c b/Libraries/STM32F10x_StdPeriph_Driver/src/stm32f10x_i2c.c new file mode 100644 index 0000000..b28cab3 --- /dev/null +++ b/Libraries/STM32F10x_StdPeriph_Driver/src/stm32f10x_i2c.c @@ -0,0 +1,1337 @@ +/** + ****************************************************************************** + * @file stm32f10x_i2c.c + * @author MCD Application Team + * @version V3.6.1 + * @date 05-March-2012 + * @brief This file provides all the I2C firmware functions. + ****************************************************************************** + * @attention + * + *

    © COPYRIGHT 2012 STMicroelectronics

    + * + * Licensed under MCD-ST Liberty SW License Agreement V2, (the "License"); + * You may not use this file except in compliance with the License. + * You may obtain a copy of the License at: + * + * http://www.st.com/software_license_agreement_liberty_v2 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, + * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + * + ****************************************************************************** + */ + +/* Includes ------------------------------------------------------------------*/ +#include "stm32f10x_i2c.h" +#include "stm32f10x_rcc.h" + + +/** @addtogroup STM32F10x_StdPeriph_Driver + * @{ + */ + +/** @defgroup I2C + * @brief I2C driver modules + * @{ + */ + +/** @defgroup I2C_Private_TypesDefinitions + * @{ + */ + +/** + * @} + */ + +/** @defgroup I2C_Private_Defines + * @{ + */ + +/* I2C SPE mask */ +#define CR1_PE_Set ((uint16_t)0x0001) +#define CR1_PE_Reset ((uint16_t)0xFFFE) + +/* I2C START mask */ +#define CR1_START_Set ((uint16_t)0x0100) +#define CR1_START_Reset ((uint16_t)0xFEFF) + +/* I2C STOP mask */ +#define CR1_STOP_Set ((uint16_t)0x0200) +#define CR1_STOP_Reset ((uint16_t)0xFDFF) + +/* I2C ACK mask */ +#define CR1_ACK_Set ((uint16_t)0x0400) +#define CR1_ACK_Reset ((uint16_t)0xFBFF) + +/* I2C ENGC mask */ +#define CR1_ENGC_Set ((uint16_t)0x0040) +#define CR1_ENGC_Reset ((uint16_t)0xFFBF) + +/* I2C SWRST mask */ +#define CR1_SWRST_Set ((uint16_t)0x8000) +#define CR1_SWRST_Reset ((uint16_t)0x7FFF) + +/* I2C PEC mask */ +#define CR1_PEC_Set ((uint16_t)0x1000) +#define CR1_PEC_Reset ((uint16_t)0xEFFF) + +/* I2C ENPEC mask */ +#define CR1_ENPEC_Set ((uint16_t)0x0020) +#define CR1_ENPEC_Reset ((uint16_t)0xFFDF) + +/* I2C ENARP mask */ +#define CR1_ENARP_Set ((uint16_t)0x0010) +#define CR1_ENARP_Reset ((uint16_t)0xFFEF) + +/* I2C NOSTRETCH mask */ +#define CR1_NOSTRETCH_Set ((uint16_t)0x0080) +#define CR1_NOSTRETCH_Reset ((uint16_t)0xFF7F) + +/* I2C registers Masks */ +#define CR1_CLEAR_Mask ((uint16_t)0xFBF5) + +/* I2C DMAEN mask */ +#define CR2_DMAEN_Set ((uint16_t)0x0800) +#define CR2_DMAEN_Reset ((uint16_t)0xF7FF) + +/* I2C LAST mask */ +#define CR2_LAST_Set ((uint16_t)0x1000) +#define CR2_LAST_Reset ((uint16_t)0xEFFF) + +/* I2C FREQ mask */ +#define CR2_FREQ_Reset ((uint16_t)0xFFC0) + +/* I2C ADD0 mask */ +#define OAR1_ADD0_Set ((uint16_t)0x0001) +#define OAR1_ADD0_Reset ((uint16_t)0xFFFE) + +/* I2C ENDUAL mask */ +#define OAR2_ENDUAL_Set ((uint16_t)0x0001) +#define OAR2_ENDUAL_Reset ((uint16_t)0xFFFE) + +/* I2C ADD2 mask */ +#define OAR2_ADD2_Reset ((uint16_t)0xFF01) + +/* I2C F/S mask */ +#define CCR_FS_Set ((uint16_t)0x8000) + +/* I2C CCR mask */ +#define CCR_CCR_Set ((uint16_t)0x0FFF) + +/* I2C FLAG mask */ +#define FLAG_Mask ((uint32_t)0x00FFFFFF) + +/* I2C Interrupt Enable mask */ +#define ITEN_Mask ((uint32_t)0x07000000) + +/** + * @} + */ + +/** @defgroup I2C_Private_Macros + * @{ + */ + +/** + * @} + */ + +/** @defgroup I2C_Private_Variables + * @{ + */ + +/** + * @} + */ + +/** @defgroup I2C_Private_FunctionPrototypes + * @{ + */ + +/** + * @} + */ + +/** @defgroup I2C_Private_Functions + * @{ + */ + +/** + * @brief Deinitializes the I2Cx peripheral registers to their default reset values. + * @param I2Cx: where x can be 1 or 2 to select the I2C peripheral. + * @retval None + */ +void I2C_DeInit(I2C_TypeDef* I2Cx) +{ + /* Check the parameters */ + assert_param(IS_I2C_ALL_PERIPH(I2Cx)); + + if (I2Cx == I2C1) + { + /* Enable I2C1 reset state */ + RCC_APB1PeriphResetCmd(RCC_APB1Periph_I2C1, ENABLE); + /* Release I2C1 from reset state */ + RCC_APB1PeriphResetCmd(RCC_APB1Periph_I2C1, DISABLE); + } + else + { + /* Enable I2C2 reset state */ + RCC_APB1PeriphResetCmd(RCC_APB1Periph_I2C2, ENABLE); + /* Release I2C2 from reset state */ + RCC_APB1PeriphResetCmd(RCC_APB1Periph_I2C2, DISABLE); + } +} + +/** + * @brief Initializes the I2Cx peripheral according to the specified + * parameters in the I2C_InitStruct. + * @param I2Cx: where x can be 1 or 2 to select the I2C peripheral. + * @param I2C_InitStruct: pointer to a I2C_InitTypeDef structure that + * contains the configuration information for the specified I2C peripheral. + * @retval None + */ +void I2C_Init(I2C_TypeDef* I2Cx, I2C_InitTypeDef* I2C_InitStruct) +{ + uint16_t tmpreg = 0, freqrange = 0; + uint16_t result = 0x04; + uint32_t pclk1 = 8000000; + RCC_ClocksTypeDef rcc_clocks; + /* Check the parameters */ + assert_param(IS_I2C_ALL_PERIPH(I2Cx)); + assert_param(IS_I2C_CLOCK_SPEED(I2C_InitStruct->I2C_ClockSpeed)); + assert_param(IS_I2C_MODE(I2C_InitStruct->I2C_Mode)); + assert_param(IS_I2C_DUTY_CYCLE(I2C_InitStruct->I2C_DutyCycle)); + assert_param(IS_I2C_OWN_ADDRESS1(I2C_InitStruct->I2C_OwnAddress1)); + assert_param(IS_I2C_ACK_STATE(I2C_InitStruct->I2C_Ack)); + assert_param(IS_I2C_ACKNOWLEDGE_ADDRESS(I2C_InitStruct->I2C_AcknowledgedAddress)); + +/*---------------------------- I2Cx CR2 Configuration ------------------------*/ + /* Get the I2Cx CR2 value */ + tmpreg = I2Cx->CR2; + /* Clear frequency FREQ[5:0] bits */ + tmpreg &= CR2_FREQ_Reset; + /* Get pclk1 frequency value */ + RCC_GetClocksFreq(&rcc_clocks); + pclk1 = rcc_clocks.PCLK1_Frequency; + /* Set frequency bits depending on pclk1 value */ + freqrange = (uint16_t)(pclk1 / 1000000); + tmpreg |= freqrange; + /* Write to I2Cx CR2 */ + I2Cx->CR2 = tmpreg; + +/*---------------------------- I2Cx CCR Configuration ------------------------*/ + /* Disable the selected I2C peripheral to configure TRISE */ + I2Cx->CR1 &= CR1_PE_Reset; + /* Reset tmpreg value */ + /* Clear F/S, DUTY and CCR[11:0] bits */ + tmpreg = 0; + + /* Configure speed in standard mode */ + if (I2C_InitStruct->I2C_ClockSpeed <= 100000) + { + /* Standard mode speed calculate */ + result = (uint16_t)(pclk1 / (I2C_InitStruct->I2C_ClockSpeed << 1)); + /* Test if CCR value is under 0x4*/ + if (result < 0x04) + { + /* Set minimum allowed value */ + result = 0x04; + } + /* Set speed value for standard mode */ + tmpreg |= result; + /* Set Maximum Rise Time for standard mode */ + I2Cx->TRISE = freqrange + 1; + } + /* Configure speed in fast mode */ + else /*(I2C_InitStruct->I2C_ClockSpeed <= 400000)*/ + { + if (I2C_InitStruct->I2C_DutyCycle == I2C_DutyCycle_2) + { + /* Fast mode speed calculate: Tlow/Thigh = 2 */ + result = (uint16_t)(pclk1 / (I2C_InitStruct->I2C_ClockSpeed * 3)); + } + else /*I2C_InitStruct->I2C_DutyCycle == I2C_DutyCycle_16_9*/ + { + /* Fast mode speed calculate: Tlow/Thigh = 16/9 */ + result = (uint16_t)(pclk1 / (I2C_InitStruct->I2C_ClockSpeed * 25)); + /* Set DUTY bit */ + result |= I2C_DutyCycle_16_9; + } + + /* Test if CCR value is under 0x1*/ + if ((result & CCR_CCR_Set) == 0) + { + /* Set minimum allowed value */ + result |= (uint16_t)0x0001; + } + /* Set speed value and set F/S bit for fast mode */ + tmpreg |= (uint16_t)(result | CCR_FS_Set); + /* Set Maximum Rise Time for fast mode */ + I2Cx->TRISE = (uint16_t)(((freqrange * (uint16_t)300) / (uint16_t)1000) + (uint16_t)1); + } + + /* Write to I2Cx CCR */ + I2Cx->CCR = tmpreg; + /* Enable the selected I2C peripheral */ + I2Cx->CR1 |= CR1_PE_Set; + +/*---------------------------- I2Cx CR1 Configuration ------------------------*/ + /* Get the I2Cx CR1 value */ + tmpreg = I2Cx->CR1; + /* Clear ACK, SMBTYPE and SMBUS bits */ + tmpreg &= CR1_CLEAR_Mask; + /* Configure I2Cx: mode and acknowledgement */ + /* Set SMBTYPE and SMBUS bits according to I2C_Mode value */ + /* Set ACK bit according to I2C_Ack value */ + tmpreg |= (uint16_t)((uint32_t)I2C_InitStruct->I2C_Mode | I2C_InitStruct->I2C_Ack); + /* Write to I2Cx CR1 */ + I2Cx->CR1 = tmpreg; + +/*---------------------------- I2Cx OAR1 Configuration -----------------------*/ + /* Set I2Cx Own Address1 and acknowledged address */ + I2Cx->OAR1 = (I2C_InitStruct->I2C_AcknowledgedAddress | I2C_InitStruct->I2C_OwnAddress1); +} + +/** + * @brief Fills each I2C_InitStruct member with its default value. + * @param I2C_InitStruct: pointer to an I2C_InitTypeDef structure which will be initialized. + * @retval None + */ +void I2C_StructInit(I2C_InitTypeDef* I2C_InitStruct) +{ +/*---------------- Reset I2C init structure parameters values ----------------*/ + /* initialize the I2C_ClockSpeed member */ + I2C_InitStruct->I2C_ClockSpeed = 5000; + /* Initialize the I2C_Mode member */ + I2C_InitStruct->I2C_Mode = I2C_Mode_I2C; + /* Initialize the I2C_DutyCycle member */ + I2C_InitStruct->I2C_DutyCycle = I2C_DutyCycle_2; + /* Initialize the I2C_OwnAddress1 member */ + I2C_InitStruct->I2C_OwnAddress1 = 0; + /* Initialize the I2C_Ack member */ + I2C_InitStruct->I2C_Ack = I2C_Ack_Disable; + /* Initialize the I2C_AcknowledgedAddress member */ + I2C_InitStruct->I2C_AcknowledgedAddress = I2C_AcknowledgedAddress_7bit; +} + +/** + * @brief Enables or disables the specified I2C peripheral. + * @param I2Cx: where x can be 1 or 2 to select the I2C peripheral. + * @param NewState: new state of the I2Cx peripheral. + * This parameter can be: ENABLE or DISABLE. + * @retval None + */ +void I2C_Cmd(I2C_TypeDef* I2Cx, FunctionalState NewState) +{ + /* Check the parameters */ + assert_param(IS_I2C_ALL_PERIPH(I2Cx)); + assert_param(IS_FUNCTIONAL_STATE(NewState)); + if (NewState != DISABLE) + { + /* Enable the selected I2C peripheral */ + I2Cx->CR1 |= CR1_PE_Set; + } + else + { + /* Disable the selected I2C peripheral */ + I2Cx->CR1 &= CR1_PE_Reset; + } +} + +/** + * @brief Enables or disables the specified I2C DMA requests. + * @param I2Cx: where x can be 1 or 2 to select the I2C peripheral. + * @param NewState: new state of the I2C DMA transfer. + * This parameter can be: ENABLE or DISABLE. + * @retval None + */ +void I2C_DMACmd(I2C_TypeDef* I2Cx, FunctionalState NewState) +{ + /* Check the parameters */ + assert_param(IS_I2C_ALL_PERIPH(I2Cx)); + assert_param(IS_FUNCTIONAL_STATE(NewState)); + if (NewState != DISABLE) + { + /* Enable the selected I2C DMA requests */ + I2Cx->CR2 |= CR2_DMAEN_Set; + } + else + { + /* Disable the selected I2C DMA requests */ + I2Cx->CR2 &= CR2_DMAEN_Reset; + } +} + +/** + * @brief Specifies if the next DMA transfer will be the last one. + * @param I2Cx: where x can be 1 or 2 to select the I2C peripheral. + * @param NewState: new state of the I2C DMA last transfer. + * This parameter can be: ENABLE or DISABLE. + * @retval None + */ +void I2C_DMALastTransferCmd(I2C_TypeDef* I2Cx, FunctionalState NewState) +{ + /* Check the parameters */ + assert_param(IS_I2C_ALL_PERIPH(I2Cx)); + assert_param(IS_FUNCTIONAL_STATE(NewState)); + if (NewState != DISABLE) + { + /* Next DMA transfer is the last transfer */ + I2Cx->CR2 |= CR2_LAST_Set; + } + else + { + /* Next DMA transfer is not the last transfer */ + I2Cx->CR2 &= CR2_LAST_Reset; + } +} + +/** + * @brief Generates I2Cx communication START condition. + * @param I2Cx: where x can be 1 or 2 to select the I2C peripheral. + * @param NewState: new state of the I2C START condition generation. + * This parameter can be: ENABLE or DISABLE. + * @retval None. + */ +void I2C_GenerateSTART(I2C_TypeDef* I2Cx, FunctionalState NewState) +{ + /* Check the parameters */ + assert_param(IS_I2C_ALL_PERIPH(I2Cx)); + assert_param(IS_FUNCTIONAL_STATE(NewState)); + if (NewState != DISABLE) + { + /* Generate a START condition */ + I2Cx->CR1 |= CR1_START_Set; + } + else + { + /* Disable the START condition generation */ + I2Cx->CR1 &= CR1_START_Reset; + } +} + +/** + * @brief Generates I2Cx communication STOP condition. + * @param I2Cx: where x can be 1 or 2 to select the I2C peripheral. + * @param NewState: new state of the I2C STOP condition generation. + * This parameter can be: ENABLE or DISABLE. + * @retval None. + */ +void I2C_GenerateSTOP(I2C_TypeDef* I2Cx, FunctionalState NewState) +{ + /* Check the parameters */ + assert_param(IS_I2C_ALL_PERIPH(I2Cx)); + assert_param(IS_FUNCTIONAL_STATE(NewState)); + if (NewState != DISABLE) + { + /* Generate a STOP condition */ + I2Cx->CR1 |= CR1_STOP_Set; + } + else + { + /* Disable the STOP condition generation */ + I2Cx->CR1 &= CR1_STOP_Reset; + } +} + +/** + * @brief Enables or disables the specified I2C acknowledge feature. + * @param I2Cx: where x can be 1 or 2 to select the I2C peripheral. + * @param NewState: new state of the I2C Acknowledgement. + * This parameter can be: ENABLE or DISABLE. + * @retval None. + */ +void I2C_AcknowledgeConfig(I2C_TypeDef* I2Cx, FunctionalState NewState) +{ + /* Check the parameters */ + assert_param(IS_I2C_ALL_PERIPH(I2Cx)); + assert_param(IS_FUNCTIONAL_STATE(NewState)); + if (NewState != DISABLE) + { + /* Enable the acknowledgement */ + I2Cx->CR1 |= CR1_ACK_Set; + } + else + { + /* Disable the acknowledgement */ + I2Cx->CR1 &= CR1_ACK_Reset; + } +} + +/** + * @brief Configures the specified I2C own address2. + * @param I2Cx: where x can be 1 or 2 to select the I2C peripheral. + * @param Address: specifies the 7bit I2C own address2. + * @retval None. + */ +void I2C_OwnAddress2Config(I2C_TypeDef* I2Cx, uint8_t Address) +{ + uint16_t tmpreg = 0; + + /* Check the parameters */ + assert_param(IS_I2C_ALL_PERIPH(I2Cx)); + + /* Get the old register value */ + tmpreg = I2Cx->OAR2; + + /* Reset I2Cx Own address2 bit [7:1] */ + tmpreg &= OAR2_ADD2_Reset; + + /* Set I2Cx Own address2 */ + tmpreg |= (uint16_t)((uint16_t)Address & (uint16_t)0x00FE); + + /* Store the new register value */ + I2Cx->OAR2 = tmpreg; +} + +/** + * @brief Enables or disables the specified I2C dual addressing mode. + * @param I2Cx: where x can be 1 or 2 to select the I2C peripheral. + * @param NewState: new state of the I2C dual addressing mode. + * This parameter can be: ENABLE or DISABLE. + * @retval None + */ +void I2C_DualAddressCmd(I2C_TypeDef* I2Cx, FunctionalState NewState) +{ + /* Check the parameters */ + assert_param(IS_I2C_ALL_PERIPH(I2Cx)); + assert_param(IS_FUNCTIONAL_STATE(NewState)); + if (NewState != DISABLE) + { + /* Enable dual addressing mode */ + I2Cx->OAR2 |= OAR2_ENDUAL_Set; + } + else + { + /* Disable dual addressing mode */ + I2Cx->OAR2 &= OAR2_ENDUAL_Reset; + } +} + +/** + * @brief Enables or disables the specified I2C general call feature. + * @param I2Cx: where x can be 1 or 2 to select the I2C peripheral. + * @param NewState: new state of the I2C General call. + * This parameter can be: ENABLE or DISABLE. + * @retval None + */ +void I2C_GeneralCallCmd(I2C_TypeDef* I2Cx, FunctionalState NewState) +{ + /* Check the parameters */ + assert_param(IS_I2C_ALL_PERIPH(I2Cx)); + assert_param(IS_FUNCTIONAL_STATE(NewState)); + if (NewState != DISABLE) + { + /* Enable generall call */ + I2Cx->CR1 |= CR1_ENGC_Set; + } + else + { + /* Disable generall call */ + I2Cx->CR1 &= CR1_ENGC_Reset; + } +} + +/** + * @brief Enables or disables the specified I2C interrupts. + * @param I2Cx: where x can be 1 or 2 to select the I2C peripheral. + * @param I2C_IT: specifies the I2C interrupts sources to be enabled or disabled. + * This parameter can be any combination of the following values: + * @arg I2C_IT_BUF: Buffer interrupt mask + * @arg I2C_IT_EVT: Event interrupt mask + * @arg I2C_IT_ERR: Error interrupt mask + * @param NewState: new state of the specified I2C interrupts. + * This parameter can be: ENABLE or DISABLE. + * @retval None + */ +void I2C_ITConfig(I2C_TypeDef* I2Cx, uint16_t I2C_IT, FunctionalState NewState) +{ + /* Check the parameters */ + assert_param(IS_I2C_ALL_PERIPH(I2Cx)); + assert_param(IS_FUNCTIONAL_STATE(NewState)); + assert_param(IS_I2C_CONFIG_IT(I2C_IT)); + + if (NewState != DISABLE) + { + /* Enable the selected I2C interrupts */ + I2Cx->CR2 |= I2C_IT; + } + else + { + /* Disable the selected I2C interrupts */ + I2Cx->CR2 &= (uint16_t)~I2C_IT; + } +} + +/** + * @brief Sends a data byte through the I2Cx peripheral. + * @param I2Cx: where x can be 1 or 2 to select the I2C peripheral. + * @param Data: Byte to be transmitted.. + * @retval None + */ +void I2C_SendData(I2C_TypeDef* I2Cx, uint8_t Data) +{ + /* Check the parameters */ + assert_param(IS_I2C_ALL_PERIPH(I2Cx)); + /* Write in the DR register the data to be sent */ + I2Cx->DR = Data; +} + +/** + * @brief Returns the most recent received data by the I2Cx peripheral. + * @param I2Cx: where x can be 1 or 2 to select the I2C peripheral. + * @retval The value of the received data. + */ +uint8_t I2C_ReceiveData(I2C_TypeDef* I2Cx) +{ + /* Check the parameters */ + assert_param(IS_I2C_ALL_PERIPH(I2Cx)); + /* Return the data in the DR register */ + return (uint8_t)I2Cx->DR; +} + +/** + * @brief Transmits the address byte to select the slave device. + * @param I2Cx: where x can be 1 or 2 to select the I2C peripheral. + * @param Address: specifies the slave address which will be transmitted + * @param I2C_Direction: specifies whether the I2C device will be a + * Transmitter or a Receiver. This parameter can be one of the following values + * @arg I2C_Direction_Transmitter: Transmitter mode + * @arg I2C_Direction_Receiver: Receiver mode + * @retval None. + */ +void I2C_Send7bitAddress(I2C_TypeDef* I2Cx, uint8_t Address, uint8_t I2C_Direction) +{ + /* Check the parameters */ + assert_param(IS_I2C_ALL_PERIPH(I2Cx)); + assert_param(IS_I2C_DIRECTION(I2C_Direction)); + /* Test on the direction to set/reset the read/write bit */ + if (I2C_Direction != I2C_Direction_Transmitter) + { + /* Set the address bit0 for read */ + Address |= OAR1_ADD0_Set; + } + else + { + /* Reset the address bit0 for write */ + Address &= OAR1_ADD0_Reset; + } + /* Send the address */ + I2Cx->DR = Address; +} + +/** + * @brief Reads the specified I2C register and returns its value. + * @param I2C_Register: specifies the register to read. + * This parameter can be one of the following values: + * @arg I2C_Register_CR1: CR1 register. + * @arg I2C_Register_CR2: CR2 register. + * @arg I2C_Register_OAR1: OAR1 register. + * @arg I2C_Register_OAR2: OAR2 register. + * @arg I2C_Register_DR: DR register. + * @arg I2C_Register_SR1: SR1 register. + * @arg I2C_Register_SR2: SR2 register. + * @arg I2C_Register_CCR: CCR register. + * @arg I2C_Register_TRISE: TRISE register. + * @retval The value of the read register. + */ +uint16_t I2C_ReadRegister(I2C_TypeDef* I2Cx, uint8_t I2C_Register) +{ + __IO uint32_t tmp = 0; + + /* Check the parameters */ + assert_param(IS_I2C_ALL_PERIPH(I2Cx)); + assert_param(IS_I2C_REGISTER(I2C_Register)); + + tmp = (uint32_t) I2Cx; + tmp += I2C_Register; + + /* Return the selected register value */ + return (*(__IO uint16_t *) tmp); +} + +/** + * @brief Enables or disables the specified I2C software reset. + * @param I2Cx: where x can be 1 or 2 to select the I2C peripheral. + * @param NewState: new state of the I2C software reset. + * This parameter can be: ENABLE or DISABLE. + * @retval None + */ +void I2C_SoftwareResetCmd(I2C_TypeDef* I2Cx, FunctionalState NewState) +{ + /* Check the parameters */ + assert_param(IS_I2C_ALL_PERIPH(I2Cx)); + assert_param(IS_FUNCTIONAL_STATE(NewState)); + if (NewState != DISABLE) + { + /* Peripheral under reset */ + I2Cx->CR1 |= CR1_SWRST_Set; + } + else + { + /* Peripheral not under reset */ + I2Cx->CR1 &= CR1_SWRST_Reset; + } +} + +/** + * @brief Selects the specified I2C NACK position in master receiver mode. + * This function is useful in I2C Master Receiver mode when the number + * of data to be received is equal to 2. In this case, this function + * should be called (with parameter I2C_NACKPosition_Next) before data + * reception starts,as described in the 2-byte reception procedure + * recommended in Reference Manual in Section: Master receiver. + * @param I2Cx: where x can be 1 or 2 to select the I2C peripheral. + * @param I2C_NACKPosition: specifies the NACK position. + * This parameter can be one of the following values: + * @arg I2C_NACKPosition_Next: indicates that the next byte will be the last + * received byte. + * @arg I2C_NACKPosition_Current: indicates that current byte is the last + * received byte. + * + * @note This function configures the same bit (POS) as I2C_PECPositionConfig() + * but is intended to be used in I2C mode while I2C_PECPositionConfig() + * is intended to used in SMBUS mode. + * + * @retval None + */ +void I2C_NACKPositionConfig(I2C_TypeDef* I2Cx, uint16_t I2C_NACKPosition) +{ + /* Check the parameters */ + assert_param(IS_I2C_ALL_PERIPH(I2Cx)); + assert_param(IS_I2C_NACK_POSITION(I2C_NACKPosition)); + + /* Check the input parameter */ + if (I2C_NACKPosition == I2C_NACKPosition_Next) + { + /* Next byte in shift register is the last received byte */ + I2Cx->CR1 |= I2C_NACKPosition_Next; + } + else + { + /* Current byte in shift register is the last received byte */ + I2Cx->CR1 &= I2C_NACKPosition_Current; + } +} + +/** + * @brief Drives the SMBusAlert pin high or low for the specified I2C. + * @param I2Cx: where x can be 1 or 2 to select the I2C peripheral. + * @param I2C_SMBusAlert: specifies SMBAlert pin level. + * This parameter can be one of the following values: + * @arg I2C_SMBusAlert_Low: SMBAlert pin driven low + * @arg I2C_SMBusAlert_High: SMBAlert pin driven high + * @retval None + */ +void I2C_SMBusAlertConfig(I2C_TypeDef* I2Cx, uint16_t I2C_SMBusAlert) +{ + /* Check the parameters */ + assert_param(IS_I2C_ALL_PERIPH(I2Cx)); + assert_param(IS_I2C_SMBUS_ALERT(I2C_SMBusAlert)); + if (I2C_SMBusAlert == I2C_SMBusAlert_Low) + { + /* Drive the SMBusAlert pin Low */ + I2Cx->CR1 |= I2C_SMBusAlert_Low; + } + else + { + /* Drive the SMBusAlert pin High */ + I2Cx->CR1 &= I2C_SMBusAlert_High; + } +} + +/** + * @brief Enables or disables the specified I2C PEC transfer. + * @param I2Cx: where x can be 1 or 2 to select the I2C peripheral. + * @param NewState: new state of the I2C PEC transmission. + * This parameter can be: ENABLE or DISABLE. + * @retval None + */ +void I2C_TransmitPEC(I2C_TypeDef* I2Cx, FunctionalState NewState) +{ + /* Check the parameters */ + assert_param(IS_I2C_ALL_PERIPH(I2Cx)); + assert_param(IS_FUNCTIONAL_STATE(NewState)); + if (NewState != DISABLE) + { + /* Enable the selected I2C PEC transmission */ + I2Cx->CR1 |= CR1_PEC_Set; + } + else + { + /* Disable the selected I2C PEC transmission */ + I2Cx->CR1 &= CR1_PEC_Reset; + } +} + +/** + * @brief Selects the specified I2C PEC position. + * @param I2Cx: where x can be 1 or 2 to select the I2C peripheral. + * @param I2C_PECPosition: specifies the PEC position. + * This parameter can be one of the following values: + * @arg I2C_PECPosition_Next: indicates that the next byte is PEC + * @arg I2C_PECPosition_Current: indicates that current byte is PEC + * + * @note This function configures the same bit (POS) as I2C_NACKPositionConfig() + * but is intended to be used in SMBUS mode while I2C_NACKPositionConfig() + * is intended to used in I2C mode. + * + * @retval None + */ +void I2C_PECPositionConfig(I2C_TypeDef* I2Cx, uint16_t I2C_PECPosition) +{ + /* Check the parameters */ + assert_param(IS_I2C_ALL_PERIPH(I2Cx)); + assert_param(IS_I2C_PEC_POSITION(I2C_PECPosition)); + if (I2C_PECPosition == I2C_PECPosition_Next) + { + /* Next byte in shift register is PEC */ + I2Cx->CR1 |= I2C_PECPosition_Next; + } + else + { + /* Current byte in shift register is PEC */ + I2Cx->CR1 &= I2C_PECPosition_Current; + } +} + +/** + * @brief Enables or disables the PEC value calculation of the transferred bytes. + * @param I2Cx: where x can be 1 or 2 to select the I2C peripheral. + * @param NewState: new state of the I2Cx PEC value calculation. + * This parameter can be: ENABLE or DISABLE. + * @retval None + */ +void I2C_CalculatePEC(I2C_TypeDef* I2Cx, FunctionalState NewState) +{ + /* Check the parameters */ + assert_param(IS_I2C_ALL_PERIPH(I2Cx)); + assert_param(IS_FUNCTIONAL_STATE(NewState)); + if (NewState != DISABLE) + { + /* Enable the selected I2C PEC calculation */ + I2Cx->CR1 |= CR1_ENPEC_Set; + } + else + { + /* Disable the selected I2C PEC calculation */ + I2Cx->CR1 &= CR1_ENPEC_Reset; + } +} + +/** + * @brief Returns the PEC value for the specified I2C. + * @param I2Cx: where x can be 1 or 2 to select the I2C peripheral. + * @retval The PEC value. + */ +uint8_t I2C_GetPEC(I2C_TypeDef* I2Cx) +{ + /* Check the parameters */ + assert_param(IS_I2C_ALL_PERIPH(I2Cx)); + /* Return the selected I2C PEC value */ + return ((I2Cx->SR2) >> 8); +} + +/** + * @brief Enables or disables the specified I2C ARP. + * @param I2Cx: where x can be 1 or 2 to select the I2C peripheral. + * @param NewState: new state of the I2Cx ARP. + * This parameter can be: ENABLE or DISABLE. + * @retval None + */ +void I2C_ARPCmd(I2C_TypeDef* I2Cx, FunctionalState NewState) +{ + /* Check the parameters */ + assert_param(IS_I2C_ALL_PERIPH(I2Cx)); + assert_param(IS_FUNCTIONAL_STATE(NewState)); + if (NewState != DISABLE) + { + /* Enable the selected I2C ARP */ + I2Cx->CR1 |= CR1_ENARP_Set; + } + else + { + /* Disable the selected I2C ARP */ + I2Cx->CR1 &= CR1_ENARP_Reset; + } +} + +/** + * @brief Enables or disables the specified I2C Clock stretching. + * @param I2Cx: where x can be 1 or 2 to select the I2C peripheral. + * @param NewState: new state of the I2Cx Clock stretching. + * This parameter can be: ENABLE or DISABLE. + * @retval None + */ +void I2C_StretchClockCmd(I2C_TypeDef* I2Cx, FunctionalState NewState) +{ + /* Check the parameters */ + assert_param(IS_I2C_ALL_PERIPH(I2Cx)); + assert_param(IS_FUNCTIONAL_STATE(NewState)); + if (NewState == DISABLE) + { + /* Enable the selected I2C Clock stretching */ + I2Cx->CR1 |= CR1_NOSTRETCH_Set; + } + else + { + /* Disable the selected I2C Clock stretching */ + I2Cx->CR1 &= CR1_NOSTRETCH_Reset; + } +} + +/** + * @brief Selects the specified I2C fast mode duty cycle. + * @param I2Cx: where x can be 1 or 2 to select the I2C peripheral. + * @param I2C_DutyCycle: specifies the fast mode duty cycle. + * This parameter can be one of the following values: + * @arg I2C_DutyCycle_2: I2C fast mode Tlow/Thigh = 2 + * @arg I2C_DutyCycle_16_9: I2C fast mode Tlow/Thigh = 16/9 + * @retval None + */ +void I2C_FastModeDutyCycleConfig(I2C_TypeDef* I2Cx, uint16_t I2C_DutyCycle) +{ + /* Check the parameters */ + assert_param(IS_I2C_ALL_PERIPH(I2Cx)); + assert_param(IS_I2C_DUTY_CYCLE(I2C_DutyCycle)); + if (I2C_DutyCycle != I2C_DutyCycle_16_9) + { + /* I2C fast mode Tlow/Thigh=2 */ + I2Cx->CCR &= I2C_DutyCycle_2; + } + else + { + /* I2C fast mode Tlow/Thigh=16/9 */ + I2Cx->CCR |= I2C_DutyCycle_16_9; + } +} + + + +/** + * @brief + **************************************************************************************** + * + * I2C State Monitoring Functions + * + **************************************************************************************** + * This I2C driver provides three different ways for I2C state monitoring + * depending on the application requirements and constraints: + * + * + * 1) Basic state monitoring: + * Using I2C_CheckEvent() function: + * It compares the status registers (SR1 and SR2) content to a given event + * (can be the combination of one or more flags). + * It returns SUCCESS if the current status includes the given flags + * and returns ERROR if one or more flags are missing in the current status. + * - When to use: + * - This function is suitable for most applications as well as for startup + * activity since the events are fully described in the product reference manual + * (RM0008). + * - It is also suitable for users who need to define their own events. + * - Limitations: + * - If an error occurs (ie. error flags are set besides to the monitored flags), + * the I2C_CheckEvent() function may return SUCCESS despite the communication + * hold or corrupted real state. + * In this case, it is advised to use error interrupts to monitor the error + * events and handle them in the interrupt IRQ handler. + * + * @note + * For error management, it is advised to use the following functions: + * - I2C_ITConfig() to configure and enable the error interrupts (I2C_IT_ERR). + * - I2Cx_ER_IRQHandler() which is called when the error interrupt occurs. + * Where x is the peripheral instance (I2C1, I2C2 ...) + * - I2C_GetFlagStatus() or I2C_GetITStatus() to be called into I2Cx_ER_IRQHandler() + * in order to determine which error occured. + * - I2C_ClearFlag() or I2C_ClearITPendingBit() and/or I2C_SoftwareResetCmd() + * and/or I2C_GenerateStop() in order to clear the error flag and source, + * and return to correct communication status. + * + * + * 2) Advanced state monitoring: + * Using the function I2C_GetLastEvent() which returns the image of both status + * registers in a single word (uint32_t) (Status Register 2 value is shifted left + * by 16 bits and concatenated to Status Register 1). + * - When to use: + * - This function is suitable for the same applications above but it allows to + * overcome the mentioned limitation of I2C_GetFlagStatus() function. + * The returned value could be compared to events already defined in the + * library (stm32f10x_i2c.h) or to custom values defined by user. + * - This function is suitable when multiple flags are monitored at the same time. + * - At the opposite of I2C_CheckEvent() function, this function allows user to + * choose when an event is accepted (when all events flags are set and no + * other flags are set or just when the needed flags are set like + * I2C_CheckEvent() function). + * - Limitations: + * - User may need to define his own events. + * - Same remark concerning the error management is applicable for this + * function if user decides to check only regular communication flags (and + * ignores error flags). + * + * + * 3) Flag-based state monitoring: + * Using the function I2C_GetFlagStatus() which simply returns the status of + * one single flag (ie. I2C_FLAG_RXNE ...). + * - When to use: + * - This function could be used for specific applications or in debug phase. + * - It is suitable when only one flag checking is needed (most I2C events + * are monitored through multiple flags). + * - Limitations: + * - When calling this function, the Status register is accessed. Some flags are + * cleared when the status register is accessed. So checking the status + * of one Flag, may clear other ones. + * - Function may need to be called twice or more in order to monitor one + * single event. + * + * For detailed description of Events, please refer to section I2C_Events in + * stm32f10x_i2c.h file. + * + */ + +/** + * + * 1) Basic state monitoring + ******************************************************************************* + */ + +/** + * @brief Checks whether the last I2Cx Event is equal to the one passed + * as parameter. + * @param I2Cx: where x can be 1 or 2 to select the I2C peripheral. + * @param I2C_EVENT: specifies the event to be checked. + * This parameter can be one of the following values: + * @arg I2C_EVENT_SLAVE_TRANSMITTER_ADDRESS_MATCHED : EV1 + * @arg I2C_EVENT_SLAVE_RECEIVER_ADDRESS_MATCHED : EV1 + * @arg I2C_EVENT_SLAVE_TRANSMITTER_SECONDADDRESS_MATCHED : EV1 + * @arg I2C_EVENT_SLAVE_RECEIVER_SECONDADDRESS_MATCHED : EV1 + * @arg I2C_EVENT_SLAVE_GENERALCALLADDRESS_MATCHED : EV1 + * @arg I2C_EVENT_SLAVE_BYTE_RECEIVED : EV2 + * @arg (I2C_EVENT_SLAVE_BYTE_RECEIVED | I2C_FLAG_DUALF) : EV2 + * @arg (I2C_EVENT_SLAVE_BYTE_RECEIVED | I2C_FLAG_GENCALL) : EV2 + * @arg I2C_EVENT_SLAVE_BYTE_TRANSMITTED : EV3 + * @arg (I2C_EVENT_SLAVE_BYTE_TRANSMITTED | I2C_FLAG_DUALF) : EV3 + * @arg (I2C_EVENT_SLAVE_BYTE_TRANSMITTED | I2C_FLAG_GENCALL) : EV3 + * @arg I2C_EVENT_SLAVE_ACK_FAILURE : EV3_2 + * @arg I2C_EVENT_SLAVE_STOP_DETECTED : EV4 + * @arg I2C_EVENT_MASTER_MODE_SELECT : EV5 + * @arg I2C_EVENT_MASTER_TRANSMITTER_MODE_SELECTED : EV6 + * @arg I2C_EVENT_MASTER_RECEIVER_MODE_SELECTED : EV6 + * @arg I2C_EVENT_MASTER_BYTE_RECEIVED : EV7 + * @arg I2C_EVENT_MASTER_BYTE_TRANSMITTING : EV8 + * @arg I2C_EVENT_MASTER_BYTE_TRANSMITTED : EV8_2 + * @arg I2C_EVENT_MASTER_MODE_ADDRESS10 : EV9 + * + * @note: For detailed description of Events, please refer to section + * I2C_Events in stm32f10x_i2c.h file. + * + * @retval An ErrorStatus enumeration value: + * - SUCCESS: Last event is equal to the I2C_EVENT + * - ERROR: Last event is different from the I2C_EVENT + */ +ErrorStatus I2C_CheckEvent(I2C_TypeDef* I2Cx, uint32_t I2C_EVENT) +{ + uint32_t lastevent = 0; + uint32_t flag1 = 0, flag2 = 0; + ErrorStatus status = ERROR; + + /* Check the parameters */ + assert_param(IS_I2C_ALL_PERIPH(I2Cx)); + assert_param(IS_I2C_EVENT(I2C_EVENT)); + + /* Read the I2Cx status register */ + flag1 = I2Cx->SR1; + flag2 = I2Cx->SR2; + flag2 = flag2 << 16; + + /* Get the last event value from I2C status register */ + lastevent = (flag1 | flag2) & FLAG_Mask; + + /* Check whether the last event contains the I2C_EVENT */ + if ((lastevent & I2C_EVENT) == I2C_EVENT) + { + /* SUCCESS: last event is equal to I2C_EVENT */ + status = SUCCESS; + } + else + { + /* ERROR: last event is different from I2C_EVENT */ + status = ERROR; + } + /* Return status */ + return status; +} + +/** + * + * 2) Advanced state monitoring + ******************************************************************************* + */ + +/** + * @brief Returns the last I2Cx Event. + * @param I2Cx: where x can be 1 or 2 to select the I2C peripheral. + * + * @note: For detailed description of Events, please refer to section + * I2C_Events in stm32f10x_i2c.h file. + * + * @retval The last event + */ +uint32_t I2C_GetLastEvent(I2C_TypeDef* I2Cx) +{ + uint32_t lastevent = 0; + uint32_t flag1 = 0, flag2 = 0; + + /* Check the parameters */ + assert_param(IS_I2C_ALL_PERIPH(I2Cx)); + + /* Read the I2Cx status register */ + flag1 = I2Cx->SR1; + flag2 = I2Cx->SR2; + flag2 = flag2 << 16; + + /* Get the last event value from I2C status register */ + lastevent = (flag1 | flag2) & FLAG_Mask; + + /* Return status */ + return lastevent; +} + +/** + * + * 3) Flag-based state monitoring + ******************************************************************************* + */ + +/** + * @brief Checks whether the specified I2C flag is set or not. + * @param I2Cx: where x can be 1 or 2 to select the I2C peripheral. + * @param I2C_FLAG: specifies the flag to check. + * This parameter can be one of the following values: + * @arg I2C_FLAG_DUALF: Dual flag (Slave mode) + * @arg I2C_FLAG_SMBHOST: SMBus host header (Slave mode) + * @arg I2C_FLAG_SMBDEFAULT: SMBus default header (Slave mode) + * @arg I2C_FLAG_GENCALL: General call header flag (Slave mode) + * @arg I2C_FLAG_TRA: Transmitter/Receiver flag + * @arg I2C_FLAG_BUSY: Bus busy flag + * @arg I2C_FLAG_MSL: Master/Slave flag + * @arg I2C_FLAG_SMBALERT: SMBus Alert flag + * @arg I2C_FLAG_TIMEOUT: Timeout or Tlow error flag + * @arg I2C_FLAG_PECERR: PEC error in reception flag + * @arg I2C_FLAG_OVR: Overrun/Underrun flag (Slave mode) + * @arg I2C_FLAG_AF: Acknowledge failure flag + * @arg I2C_FLAG_ARLO: Arbitration lost flag (Master mode) + * @arg I2C_FLAG_BERR: Bus error flag + * @arg I2C_FLAG_TXE: Data register empty flag (Transmitter) + * @arg I2C_FLAG_RXNE: Data register not empty (Receiver) flag + * @arg I2C_FLAG_STOPF: Stop detection flag (Slave mode) + * @arg I2C_FLAG_ADD10: 10-bit header sent flag (Master mode) + * @arg I2C_FLAG_BTF: Byte transfer finished flag + * @arg I2C_FLAG_ADDR: Address sent flag (Master mode) "ADSL" + * Address matched flag (Slave mode)"ENDA" + * @arg I2C_FLAG_SB: Start bit flag (Master mode) + * @retval The new state of I2C_FLAG (SET or RESET). + */ +FlagStatus I2C_GetFlagStatus(I2C_TypeDef* I2Cx, uint32_t I2C_FLAG) +{ + FlagStatus bitstatus = RESET; + __IO uint32_t i2creg = 0, i2cxbase = 0; + + /* Check the parameters */ + assert_param(IS_I2C_ALL_PERIPH(I2Cx)); + assert_param(IS_I2C_GET_FLAG(I2C_FLAG)); + + /* Get the I2Cx peripheral base address */ + i2cxbase = (uint32_t)I2Cx; + + /* Read flag register index */ + i2creg = I2C_FLAG >> 28; + + /* Get bit[23:0] of the flag */ + I2C_FLAG &= FLAG_Mask; + + if(i2creg != 0) + { + /* Get the I2Cx SR1 register address */ + i2cxbase += 0x14; + } + else + { + /* Flag in I2Cx SR2 Register */ + I2C_FLAG = (uint32_t)(I2C_FLAG >> 16); + /* Get the I2Cx SR2 register address */ + i2cxbase += 0x18; + } + + if(((*(__IO uint32_t *)i2cxbase) & I2C_FLAG) != (uint32_t)RESET) + { + /* I2C_FLAG is set */ + bitstatus = SET; + } + else + { + /* I2C_FLAG is reset */ + bitstatus = RESET; + } + + /* Return the I2C_FLAG status */ + return bitstatus; +} + + + +/** + * @brief Clears the I2Cx's pending flags. + * @param I2Cx: where x can be 1 or 2 to select the I2C peripheral. + * @param I2C_FLAG: specifies the flag to clear. + * This parameter can be any combination of the following values: + * @arg I2C_FLAG_SMBALERT: SMBus Alert flag + * @arg I2C_FLAG_TIMEOUT: Timeout or Tlow error flag + * @arg I2C_FLAG_PECERR: PEC error in reception flag + * @arg I2C_FLAG_OVR: Overrun/Underrun flag (Slave mode) + * @arg I2C_FLAG_AF: Acknowledge failure flag + * @arg I2C_FLAG_ARLO: Arbitration lost flag (Master mode) + * @arg I2C_FLAG_BERR: Bus error flag + * + * @note + * - STOPF (STOP detection) is cleared by software sequence: a read operation + * to I2C_SR1 register (I2C_GetFlagStatus()) followed by a write operation + * to I2C_CR1 register (I2C_Cmd() to re-enable the I2C peripheral). + * - ADD10 (10-bit header sent) is cleared by software sequence: a read + * operation to I2C_SR1 (I2C_GetFlagStatus()) followed by writing the + * second byte of the address in DR register. + * - BTF (Byte Transfer Finished) is cleared by software sequence: a read + * operation to I2C_SR1 register (I2C_GetFlagStatus()) followed by a + * read/write to I2C_DR register (I2C_SendData()). + * - ADDR (Address sent) is cleared by software sequence: a read operation to + * I2C_SR1 register (I2C_GetFlagStatus()) followed by a read operation to + * I2C_SR2 register ((void)(I2Cx->SR2)). + * - SB (Start Bit) is cleared software sequence: a read operation to I2C_SR1 + * register (I2C_GetFlagStatus()) followed by a write operation to I2C_DR + * register (I2C_SendData()). + * @retval None + */ +void I2C_ClearFlag(I2C_TypeDef* I2Cx, uint32_t I2C_FLAG) +{ + uint32_t flagpos = 0; + /* Check the parameters */ + assert_param(IS_I2C_ALL_PERIPH(I2Cx)); + assert_param(IS_I2C_CLEAR_FLAG(I2C_FLAG)); + /* Get the I2C flag position */ + flagpos = I2C_FLAG & FLAG_Mask; + /* Clear the selected I2C flag */ + I2Cx->SR1 = (uint16_t)~flagpos; +} + +/** + * @brief Checks whether the specified I2C interrupt has occurred or not. + * @param I2Cx: where x can be 1 or 2 to select the I2C peripheral. + * @param I2C_IT: specifies the interrupt source to check. + * This parameter can be one of the following values: + * @arg I2C_IT_SMBALERT: SMBus Alert flag + * @arg I2C_IT_TIMEOUT: Timeout or Tlow error flag + * @arg I2C_IT_PECERR: PEC error in reception flag + * @arg I2C_IT_OVR: Overrun/Underrun flag (Slave mode) + * @arg I2C_IT_AF: Acknowledge failure flag + * @arg I2C_IT_ARLO: Arbitration lost flag (Master mode) + * @arg I2C_IT_BERR: Bus error flag + * @arg I2C_IT_TXE: Data register empty flag (Transmitter) + * @arg I2C_IT_RXNE: Data register not empty (Receiver) flag + * @arg I2C_IT_STOPF: Stop detection flag (Slave mode) + * @arg I2C_IT_ADD10: 10-bit header sent flag (Master mode) + * @arg I2C_IT_BTF: Byte transfer finished flag + * @arg I2C_IT_ADDR: Address sent flag (Master mode) "ADSL" + * Address matched flag (Slave mode)"ENDAD" + * @arg I2C_IT_SB: Start bit flag (Master mode) + * @retval The new state of I2C_IT (SET or RESET). + */ +ITStatus I2C_GetITStatus(I2C_TypeDef* I2Cx, uint32_t I2C_IT) +{ + ITStatus bitstatus = RESET; + uint32_t enablestatus = 0; + + /* Check the parameters */ + assert_param(IS_I2C_ALL_PERIPH(I2Cx)); + assert_param(IS_I2C_GET_IT(I2C_IT)); + + /* Check if the interrupt source is enabled or not */ + enablestatus = (uint32_t)(((I2C_IT & ITEN_Mask) >> 16) & (I2Cx->CR2)) ; + + /* Get bit[23:0] of the flag */ + I2C_IT &= FLAG_Mask; + + /* Check the status of the specified I2C flag */ + if (((I2Cx->SR1 & I2C_IT) != (uint32_t)RESET) && enablestatus) + { + /* I2C_IT is set */ + bitstatus = SET; + } + else + { + /* I2C_IT is reset */ + bitstatus = RESET; + } + /* Return the I2C_IT status */ + return bitstatus; +} + +/** + * @brief Clears the I2Cxs interrupt pending bits. + * @param I2Cx: where x can be 1 or 2 to select the I2C peripheral. + * @param I2C_IT: specifies the interrupt pending bit to clear. + * This parameter can be any combination of the following values: + * @arg I2C_IT_SMBALERT: SMBus Alert interrupt + * @arg I2C_IT_TIMEOUT: Timeout or Tlow error interrupt + * @arg I2C_IT_PECERR: PEC error in reception interrupt + * @arg I2C_IT_OVR: Overrun/Underrun interrupt (Slave mode) + * @arg I2C_IT_AF: Acknowledge failure interrupt + * @arg I2C_IT_ARLO: Arbitration lost interrupt (Master mode) + * @arg I2C_IT_BERR: Bus error interrupt + * + * @note + * - STOPF (STOP detection) is cleared by software sequence: a read operation + * to I2C_SR1 register (I2C_GetITStatus()) followed by a write operation to + * I2C_CR1 register (I2C_Cmd() to re-enable the I2C peripheral). + * - ADD10 (10-bit header sent) is cleared by software sequence: a read + * operation to I2C_SR1 (I2C_GetITStatus()) followed by writing the second + * byte of the address in I2C_DR register. + * - BTF (Byte Transfer Finished) is cleared by software sequence: a read + * operation to I2C_SR1 register (I2C_GetITStatus()) followed by a + * read/write to I2C_DR register (I2C_SendData()). + * - ADDR (Address sent) is cleared by software sequence: a read operation to + * I2C_SR1 register (I2C_GetITStatus()) followed by a read operation to + * I2C_SR2 register ((void)(I2Cx->SR2)). + * - SB (Start Bit) is cleared by software sequence: a read operation to + * I2C_SR1 register (I2C_GetITStatus()) followed by a write operation to + * I2C_DR register (I2C_SendData()). + * @retval None + */ +void I2C_ClearITPendingBit(I2C_TypeDef* I2Cx, uint32_t I2C_IT) +{ + uint32_t flagpos = 0; + /* Check the parameters */ + assert_param(IS_I2C_ALL_PERIPH(I2Cx)); + assert_param(IS_I2C_CLEAR_IT(I2C_IT)); + /* Get the I2C flag position */ + flagpos = I2C_IT & FLAG_Mask; + /* Clear the selected I2C flag */ + I2Cx->SR1 = (uint16_t)~flagpos; +} + +/** + * @} + */ + +/** + * @} + */ + +/** + * @} + */ + +/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ diff --git a/Libraries/STM32F10x_StdPeriph_Driver/src/stm32f10x_iwdg.c b/Libraries/STM32F10x_StdPeriph_Driver/src/stm32f10x_iwdg.c new file mode 100644 index 0000000..498d491 --- /dev/null +++ b/Libraries/STM32F10x_StdPeriph_Driver/src/stm32f10x_iwdg.c @@ -0,0 +1,196 @@ +/** + ****************************************************************************** + * @file stm32f10x_iwdg.c + * @author MCD Application Team + * @version V3.6.1 + * @date 05-March-2012 + * @brief This file provides all the IWDG firmware functions. + ****************************************************************************** + * @attention + * + *

    © COPYRIGHT 2012 STMicroelectronics

    + * + * Licensed under MCD-ST Liberty SW License Agreement V2, (the "License"); + * You may not use this file except in compliance with the License. + * You may obtain a copy of the License at: + * + * http://www.st.com/software_license_agreement_liberty_v2 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, + * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + * + ****************************************************************************** + */ + +/* Includes ------------------------------------------------------------------*/ +#include "stm32f10x_iwdg.h" + +/** @addtogroup STM32F10x_StdPeriph_Driver + * @{ + */ + +/** @defgroup IWDG + * @brief IWDG driver modules + * @{ + */ + +/** @defgroup IWDG_Private_TypesDefinitions + * @{ + */ + +/** + * @} + */ + +/** @defgroup IWDG_Private_Defines + * @{ + */ + +/* ---------------------- IWDG registers bit mask ----------------------------*/ + +/* KR register bit mask */ +#define KR_KEY_Reload ((uint16_t)0xAAAA) +#define KR_KEY_Enable ((uint16_t)0xCCCC) + +/** + * @} + */ + +/** @defgroup IWDG_Private_Macros + * @{ + */ + +/** + * @} + */ + +/** @defgroup IWDG_Private_Variables + * @{ + */ + +/** + * @} + */ + +/** @defgroup IWDG_Private_FunctionPrototypes + * @{ + */ + +/** + * @} + */ + +/** @defgroup IWDG_Private_Functions + * @{ + */ + +/** + * @brief Enables or disables write access to IWDG_PR and IWDG_RLR registers. + * @param IWDG_WriteAccess: new state of write access to IWDG_PR and IWDG_RLR registers. + * This parameter can be one of the following values: + * @arg IWDG_WriteAccess_Enable: Enable write access to IWDG_PR and IWDG_RLR registers + * @arg IWDG_WriteAccess_Disable: Disable write access to IWDG_PR and IWDG_RLR registers + * @retval None + */ +void IWDG_WriteAccessCmd(uint16_t IWDG_WriteAccess) +{ + /* Check the parameters */ + assert_param(IS_IWDG_WRITE_ACCESS(IWDG_WriteAccess)); + IWDG->KR = IWDG_WriteAccess; +} + +/** + * @brief Sets IWDG Prescaler value. + * @param IWDG_Prescaler: specifies the IWDG Prescaler value. + * This parameter can be one of the following values: + * @arg IWDG_Prescaler_4: IWDG prescaler set to 4 + * @arg IWDG_Prescaler_8: IWDG prescaler set to 8 + * @arg IWDG_Prescaler_16: IWDG prescaler set to 16 + * @arg IWDG_Prescaler_32: IWDG prescaler set to 32 + * @arg IWDG_Prescaler_64: IWDG prescaler set to 64 + * @arg IWDG_Prescaler_128: IWDG prescaler set to 128 + * @arg IWDG_Prescaler_256: IWDG prescaler set to 256 + * @retval None + */ +void IWDG_SetPrescaler(uint8_t IWDG_Prescaler) +{ + /* Check the parameters */ + assert_param(IS_IWDG_PRESCALER(IWDG_Prescaler)); + IWDG->PR = IWDG_Prescaler; +} + +/** + * @brief Sets IWDG Reload value. + * @param Reload: specifies the IWDG Reload value. + * This parameter must be a number between 0 and 0x0FFF. + * @retval None + */ +void IWDG_SetReload(uint16_t Reload) +{ + /* Check the parameters */ + assert_param(IS_IWDG_RELOAD(Reload)); + IWDG->RLR = Reload; +} + +/** + * @brief Reloads IWDG counter with value defined in the reload register + * (write access to IWDG_PR and IWDG_RLR registers disabled). + * @param None + * @retval None + */ +void IWDG_ReloadCounter(void) +{ + IWDG->KR = KR_KEY_Reload; +} + +/** + * @brief Enables IWDG (write access to IWDG_PR and IWDG_RLR registers disabled). + * @param None + * @retval None + */ +void IWDG_Enable(void) +{ + IWDG->KR = KR_KEY_Enable; +} + +/** + * @brief Checks whether the specified IWDG flag is set or not. + * @param IWDG_FLAG: specifies the flag to check. + * This parameter can be one of the following values: + * @arg IWDG_FLAG_PVU: Prescaler Value Update on going + * @arg IWDG_FLAG_RVU: Reload Value Update on going + * @retval The new state of IWDG_FLAG (SET or RESET). + */ +FlagStatus IWDG_GetFlagStatus(uint16_t IWDG_FLAG) +{ + FlagStatus bitstatus = RESET; + /* Check the parameters */ + assert_param(IS_IWDG_FLAG(IWDG_FLAG)); + if ((IWDG->SR & IWDG_FLAG) != (uint32_t)RESET) + { + bitstatus = SET; + } + else + { + bitstatus = RESET; + } + /* Return the flag status */ + return bitstatus; +} + +/** + * @} + */ + +/** + * @} + */ + +/** + * @} + */ + +/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ diff --git a/Libraries/STM32F10x_StdPeriph_Driver/src/stm32f10x_pwr.c b/Libraries/STM32F10x_StdPeriph_Driver/src/stm32f10x_pwr.c new file mode 100644 index 0000000..0987242 --- /dev/null +++ b/Libraries/STM32F10x_StdPeriph_Driver/src/stm32f10x_pwr.c @@ -0,0 +1,313 @@ +/** + ****************************************************************************** + * @file stm32f10x_pwr.c + * @author MCD Application Team + * @version V3.6.1 + * @date 05-March-2012 + * @brief This file provides all the PWR firmware functions. + ****************************************************************************** + * @attention + * + *

    © COPYRIGHT 2012 STMicroelectronics

    + * + * Licensed under MCD-ST Liberty SW License Agreement V2, (the "License"); + * You may not use this file except in compliance with the License. + * You may obtain a copy of the License at: + * + * http://www.st.com/software_license_agreement_liberty_v2 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, + * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + * + ****************************************************************************** + */ + +/* Includes ------------------------------------------------------------------*/ +#include "stm32f10x_pwr.h" +#include "stm32f10x_rcc.h" + +/** @addtogroup STM32F10x_StdPeriph_Driver + * @{ + */ + +/** @defgroup PWR + * @brief PWR driver modules + * @{ + */ + +/** @defgroup PWR_Private_TypesDefinitions + * @{ + */ + +/** + * @} + */ + +/** @defgroup PWR_Private_Defines + * @{ + */ + +/* --------- PWR registers bit address in the alias region ---------- */ +#define PWR_OFFSET (PWR_BASE - PERIPH_BASE) + +/* --- CR Register ---*/ + +/* Alias word address of DBP bit */ +#define CR_OFFSET (PWR_OFFSET + 0x00) +#define DBP_BitNumber 0x08 +#define CR_DBP_BB (PERIPH_BB_BASE + (CR_OFFSET * 32) + (DBP_BitNumber * 4)) + +/* Alias word address of PVDE bit */ +#define PVDE_BitNumber 0x04 +#define CR_PVDE_BB (PERIPH_BB_BASE + (CR_OFFSET * 32) + (PVDE_BitNumber * 4)) + +/* --- CSR Register ---*/ + +/* Alias word address of EWUP bit */ +#define CSR_OFFSET (PWR_OFFSET + 0x04) +#define EWUP_BitNumber 0x08 +#define CSR_EWUP_BB (PERIPH_BB_BASE + (CSR_OFFSET * 32) + (EWUP_BitNumber * 4)) + +/* ------------------ PWR registers bit mask ------------------------ */ + +/* CR register bit mask */ +#define CR_DS_MASK ((uint32_t)0xFFFFFFFC) +#define CR_PLS_MASK ((uint32_t)0xFFFFFF1F) + + +/** + * @} + */ + +/** @defgroup PWR_Private_Macros + * @{ + */ + +/** + * @} + */ + +/** @defgroup PWR_Private_Variables + * @{ + */ + +/** + * @} + */ + +/** @defgroup PWR_Private_FunctionPrototypes + * @{ + */ + +/** + * @} + */ + +/** @defgroup PWR_Private_Functions + * @{ + */ + +/** + * @brief Deinitializes the PWR peripheral registers to their default reset values. + * @param None + * @retval None + */ +void PWR_DeInit(void) +{ + RCC_APB1PeriphResetCmd(RCC_APB1Periph_PWR, ENABLE); + RCC_APB1PeriphResetCmd(RCC_APB1Periph_PWR, DISABLE); +} + +/** + * @brief Enables or disables access to the RTC and backup registers. + * @param NewState: new state of the access to the RTC and backup registers. + * This parameter can be: ENABLE or DISABLE. + * @retval None + */ +void PWR_BackupAccessCmd(FunctionalState NewState) +{ + /* Check the parameters */ + assert_param(IS_FUNCTIONAL_STATE(NewState)); + *(__IO uint32_t *) CR_DBP_BB = (uint32_t)NewState; +} + +/** + * @brief Enables or disables the Power Voltage Detector(PVD). + * @param NewState: new state of the PVD. + * This parameter can be: ENABLE or DISABLE. + * @retval None + */ +void PWR_PVDCmd(FunctionalState NewState) +{ + /* Check the parameters */ + assert_param(IS_FUNCTIONAL_STATE(NewState)); + *(__IO uint32_t *) CR_PVDE_BB = (uint32_t)NewState; +} + +/** + * @brief Configures the voltage threshold detected by the Power Voltage Detector(PVD). + * @param PWR_PVDLevel: specifies the PVD detection level + * This parameter can be one of the following values: + * @arg PWR_PVDLevel_2V2: PVD detection level set to 2.2V + * @arg PWR_PVDLevel_2V3: PVD detection level set to 2.3V + * @arg PWR_PVDLevel_2V4: PVD detection level set to 2.4V + * @arg PWR_PVDLevel_2V5: PVD detection level set to 2.5V + * @arg PWR_PVDLevel_2V6: PVD detection level set to 2.6V + * @arg PWR_PVDLevel_2V7: PVD detection level set to 2.7V + * @arg PWR_PVDLevel_2V8: PVD detection level set to 2.8V + * @arg PWR_PVDLevel_2V9: PVD detection level set to 2.9V + * @retval None + */ +void PWR_PVDLevelConfig(uint32_t PWR_PVDLevel) +{ + uint32_t tmpreg = 0; + /* Check the parameters */ + assert_param(IS_PWR_PVD_LEVEL(PWR_PVDLevel)); + tmpreg = PWR->CR; + /* Clear PLS[7:5] bits */ + tmpreg &= CR_PLS_MASK; + /* Set PLS[7:5] bits according to PWR_PVDLevel value */ + tmpreg |= PWR_PVDLevel; + /* Store the new value */ + PWR->CR = tmpreg; +} + +/** + * @brief Enables or disables the WakeUp Pin functionality. + * @param NewState: new state of the WakeUp Pin functionality. + * This parameter can be: ENABLE or DISABLE. + * @retval None + */ +void PWR_WakeUpPinCmd(FunctionalState NewState) +{ + /* Check the parameters */ + assert_param(IS_FUNCTIONAL_STATE(NewState)); + *(__IO uint32_t *) CSR_EWUP_BB = (uint32_t)NewState; +} + +/** + * @brief Enters STOP mode. + * @param PWR_Regulator: specifies the regulator state in STOP mode. + * This parameter can be one of the following values: + * @arg PWR_Regulator_ON: STOP mode with regulator ON + * @arg PWR_Regulator_LowPower: STOP mode with regulator in low power mode + * @param PWR_STOPEntry: specifies if STOP mode in entered with WFI or WFE instruction. + * This parameter can be one of the following values: + * @arg PWR_STOPEntry_WFI: enter STOP mode with WFI instruction + * @arg PWR_STOPEntry_WFE: enter STOP mode with WFE instruction + * @retval None + */ +void PWR_EnterSTOPMode(uint32_t PWR_Regulator, uint8_t PWR_STOPEntry) +{ + uint32_t tmpreg = 0; + /* Check the parameters */ + assert_param(IS_PWR_REGULATOR(PWR_Regulator)); + assert_param(IS_PWR_STOP_ENTRY(PWR_STOPEntry)); + + /* Select the regulator state in STOP mode ---------------------------------*/ + tmpreg = PWR->CR; + /* Clear PDDS and LPDS bits */ + tmpreg &= CR_DS_MASK; + /* Set LPDS bit according to PWR_Regulator value */ + tmpreg |= PWR_Regulator; + /* Store the new value */ + PWR->CR = tmpreg; + /* Set SLEEPDEEP bit of Cortex System Control Register */ + SCB->SCR |= SCB_SCR_SLEEPDEEP; + + /* Select STOP mode entry --------------------------------------------------*/ + if(PWR_STOPEntry == PWR_STOPEntry_WFI) + { + /* Request Wait For Interrupt */ + __WFI(); + } + else + { + /* Request Wait For Event */ + __WFE(); + } + + /* Reset SLEEPDEEP bit of Cortex System Control Register */ + SCB->SCR &= (uint32_t)~((uint32_t)SCB_SCR_SLEEPDEEP); +} + +/** + * @brief Enters STANDBY mode. + * @param None + * @retval None + */ +void PWR_EnterSTANDBYMode(void) +{ + /* Clear Wake-up flag */ + PWR->CR |= PWR_CR_CWUF; + /* Select STANDBY mode */ + PWR->CR |= PWR_CR_PDDS; + /* Set SLEEPDEEP bit of Cortex System Control Register */ + SCB->SCR |= SCB_SCR_SLEEPDEEP; +/* This option is used to ensure that store operations are completed */ +#if defined ( __CC_ARM ) + __force_stores(); +#endif + /* Request Wait For Interrupt */ + __WFI(); +} + +/** + * @brief Checks whether the specified PWR flag is set or not. + * @param PWR_FLAG: specifies the flag to check. + * This parameter can be one of the following values: + * @arg PWR_FLAG_WU: Wake Up flag + * @arg PWR_FLAG_SB: StandBy flag + * @arg PWR_FLAG_PVDO: PVD Output + * @retval The new state of PWR_FLAG (SET or RESET). + */ +FlagStatus PWR_GetFlagStatus(uint32_t PWR_FLAG) +{ + FlagStatus bitstatus = RESET; + /* Check the parameters */ + assert_param(IS_PWR_GET_FLAG(PWR_FLAG)); + + if ((PWR->CSR & PWR_FLAG) != (uint32_t)RESET) + { + bitstatus = SET; + } + else + { + bitstatus = RESET; + } + /* Return the flag status */ + return bitstatus; +} + +/** + * @brief Clears the PWR's pending flags. + * @param PWR_FLAG: specifies the flag to clear. + * This parameter can be one of the following values: + * @arg PWR_FLAG_WU: Wake Up flag + * @arg PWR_FLAG_SB: StandBy flag + * @retval None + */ +void PWR_ClearFlag(uint32_t PWR_FLAG) +{ + /* Check the parameters */ + assert_param(IS_PWR_CLEAR_FLAG(PWR_FLAG)); + + PWR->CR |= PWR_FLAG << 2; +} + +/** + * @} + */ + +/** + * @} + */ + +/** + * @} + */ + +/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ diff --git a/Libraries/STM32F10x_StdPeriph_Driver/src/stm32f10x_rcc.c b/Libraries/STM32F10x_StdPeriph_Driver/src/stm32f10x_rcc.c new file mode 100644 index 0000000..2e870f6 --- /dev/null +++ b/Libraries/STM32F10x_StdPeriph_Driver/src/stm32f10x_rcc.c @@ -0,0 +1,1476 @@ +/** + ****************************************************************************** + * @file stm32f10x_rcc.c + * @author MCD Application Team + * @version V3.6.1 + * @date 05-March-2012 + * @brief This file provides all the RCC firmware functions. + ****************************************************************************** + * @attention + * + *

    © COPYRIGHT 2012 STMicroelectronics

    + * + * Licensed under MCD-ST Liberty SW License Agreement V2, (the "License"); + * You may not use this file except in compliance with the License. + * You may obtain a copy of the License at: + * + * http://www.st.com/software_license_agreement_liberty_v2 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, + * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + * + ****************************************************************************** + */ + +/* Includes ------------------------------------------------------------------*/ +#include "stm32f10x_rcc.h" + +/** @addtogroup STM32F10x_StdPeriph_Driver + * @{ + */ + +/** @defgroup RCC + * @brief RCC driver modules + * @{ + */ + +/** @defgroup RCC_Private_TypesDefinitions + * @{ + */ + +/** + * @} + */ + +/** @defgroup RCC_Private_Defines + * @{ + */ + +/* ------------ RCC registers bit address in the alias region ----------- */ +#define RCC_OFFSET (RCC_BASE - PERIPH_BASE) + +/* --- CR Register ---*/ + +/* Alias word address of HSION bit */ +#define CR_OFFSET (RCC_OFFSET + 0x00) +#define HSION_BitNumber 0x00 +#define CR_HSION_BB (PERIPH_BB_BASE + (CR_OFFSET * 32) + (HSION_BitNumber * 4)) + +/* Alias word address of PLLON bit */ +#define PLLON_BitNumber 0x18 +#define CR_PLLON_BB (PERIPH_BB_BASE + (CR_OFFSET * 32) + (PLLON_BitNumber * 4)) + +#ifdef STM32F10X_CL + /* Alias word address of PLL2ON bit */ + #define PLL2ON_BitNumber 0x1A + #define CR_PLL2ON_BB (PERIPH_BB_BASE + (CR_OFFSET * 32) + (PLL2ON_BitNumber * 4)) + + /* Alias word address of PLL3ON bit */ + #define PLL3ON_BitNumber 0x1C + #define CR_PLL3ON_BB (PERIPH_BB_BASE + (CR_OFFSET * 32) + (PLL3ON_BitNumber * 4)) +#endif /* STM32F10X_CL */ + +/* Alias word address of CSSON bit */ +#define CSSON_BitNumber 0x13 +#define CR_CSSON_BB (PERIPH_BB_BASE + (CR_OFFSET * 32) + (CSSON_BitNumber * 4)) + +/* --- CFGR Register ---*/ + +/* Alias word address of USBPRE bit */ +#define CFGR_OFFSET (RCC_OFFSET + 0x04) + +#ifndef STM32F10X_CL + #define USBPRE_BitNumber 0x16 + #define CFGR_USBPRE_BB (PERIPH_BB_BASE + (CFGR_OFFSET * 32) + (USBPRE_BitNumber * 4)) +#else + #define OTGFSPRE_BitNumber 0x16 + #define CFGR_OTGFSPRE_BB (PERIPH_BB_BASE + (CFGR_OFFSET * 32) + (OTGFSPRE_BitNumber * 4)) +#endif /* STM32F10X_CL */ + +/* --- BDCR Register ---*/ + +/* Alias word address of RTCEN bit */ +#define BDCR_OFFSET (RCC_OFFSET + 0x20) +#define RTCEN_BitNumber 0x0F +#define BDCR_RTCEN_BB (PERIPH_BB_BASE + (BDCR_OFFSET * 32) + (RTCEN_BitNumber * 4)) + +/* Alias word address of BDRST bit */ +#define BDRST_BitNumber 0x10 +#define BDCR_BDRST_BB (PERIPH_BB_BASE + (BDCR_OFFSET * 32) + (BDRST_BitNumber * 4)) + +/* --- CSR Register ---*/ + +/* Alias word address of LSION bit */ +#define CSR_OFFSET (RCC_OFFSET + 0x24) +#define LSION_BitNumber 0x00 +#define CSR_LSION_BB (PERIPH_BB_BASE + (CSR_OFFSET * 32) + (LSION_BitNumber * 4)) + +#ifdef STM32F10X_CL +/* --- CFGR2 Register ---*/ + + /* Alias word address of I2S2SRC bit */ + #define CFGR2_OFFSET (RCC_OFFSET + 0x2C) + #define I2S2SRC_BitNumber 0x11 + #define CFGR2_I2S2SRC_BB (PERIPH_BB_BASE + (CFGR2_OFFSET * 32) + (I2S2SRC_BitNumber * 4)) + + /* Alias word address of I2S3SRC bit */ + #define I2S3SRC_BitNumber 0x12 + #define CFGR2_I2S3SRC_BB (PERIPH_BB_BASE + (CFGR2_OFFSET * 32) + (I2S3SRC_BitNumber * 4)) +#endif /* STM32F10X_CL */ + +/* ---------------------- RCC registers bit mask ------------------------ */ + +/* CR register bit mask */ +#define CR_HSEBYP_Reset ((uint32_t)0xFFFBFFFF) +#define CR_HSEBYP_Set ((uint32_t)0x00040000) +#define CR_HSEON_Reset ((uint32_t)0xFFFEFFFF) +#define CR_HSEON_Set ((uint32_t)0x00010000) +#define CR_HSITRIM_Mask ((uint32_t)0xFFFFFF07) + +/* CFGR register bit mask */ +#if defined (STM32F10X_LD_VL) || defined (STM32F10X_MD_VL) || defined (STM32F10X_HD_VL) || defined (STM32F10X_CL) + #define CFGR_PLL_Mask ((uint32_t)0xFFC2FFFF) +#else + #define CFGR_PLL_Mask ((uint32_t)0xFFC0FFFF) +#endif /* STM32F10X_CL */ + +#define CFGR_PLLMull_Mask ((uint32_t)0x003C0000) +#define CFGR_PLLSRC_Mask ((uint32_t)0x00010000) +#define CFGR_PLLXTPRE_Mask ((uint32_t)0x00020000) +#define CFGR_SWS_Mask ((uint32_t)0x0000000C) +#define CFGR_SW_Mask ((uint32_t)0xFFFFFFFC) +#define CFGR_HPRE_Reset_Mask ((uint32_t)0xFFFFFF0F) +#define CFGR_HPRE_Set_Mask ((uint32_t)0x000000F0) +#define CFGR_PPRE1_Reset_Mask ((uint32_t)0xFFFFF8FF) +#define CFGR_PPRE1_Set_Mask ((uint32_t)0x00000700) +#define CFGR_PPRE2_Reset_Mask ((uint32_t)0xFFFFC7FF) +#define CFGR_PPRE2_Set_Mask ((uint32_t)0x00003800) +#define CFGR_ADCPRE_Reset_Mask ((uint32_t)0xFFFF3FFF) +#define CFGR_ADCPRE_Set_Mask ((uint32_t)0x0000C000) + +/* CSR register bit mask */ +#define CSR_RMVF_Set ((uint32_t)0x01000000) + +#if defined (STM32F10X_LD_VL) || defined (STM32F10X_MD_VL) || defined (STM32F10X_HD_VL) || defined (STM32F10X_CL) +/* CFGR2 register bit mask */ + #define CFGR2_PREDIV1SRC ((uint32_t)0x00010000) + #define CFGR2_PREDIV1 ((uint32_t)0x0000000F) +#endif +#ifdef STM32F10X_CL + #define CFGR2_PREDIV2 ((uint32_t)0x000000F0) + #define CFGR2_PLL2MUL ((uint32_t)0x00000F00) + #define CFGR2_PLL3MUL ((uint32_t)0x0000F000) +#endif /* STM32F10X_CL */ + +/* RCC Flag Mask */ +#define FLAG_Mask ((uint8_t)0x1F) + +/* CIR register byte 2 (Bits[15:8]) base address */ +#define CIR_BYTE2_ADDRESS ((uint32_t)0x40021009) + +/* CIR register byte 3 (Bits[23:16]) base address */ +#define CIR_BYTE3_ADDRESS ((uint32_t)0x4002100A) + +/* CFGR register byte 4 (Bits[31:24]) base address */ +#define CFGR_BYTE4_ADDRESS ((uint32_t)0x40021007) + +/* BDCR register base address */ +#define BDCR_ADDRESS (PERIPH_BASE + BDCR_OFFSET) + +/** + * @} + */ + +/** @defgroup RCC_Private_Macros + * @{ + */ + +/** + * @} + */ + +/** @defgroup RCC_Private_Variables + * @{ + */ + +static __I uint8_t APBAHBPrescTable[16] = {0, 0, 0, 0, 1, 2, 3, 4, 1, 2, 3, 4, 6, 7, 8, 9}; +static __I uint8_t ADCPrescTable[4] = {2, 4, 6, 8}; + +/** + * @} + */ + +/** @defgroup RCC_Private_FunctionPrototypes + * @{ + */ + +/** + * @} + */ + +/** @defgroup RCC_Private_Functions + * @{ + */ + +/** + * @brief Resets the RCC clock configuration to the default reset state. + * @param None + * @retval None + */ +void RCC_DeInit(void) +{ + /* Set HSION bit */ + RCC->CR |= (uint32_t)0x00000001; + + /* Reset SW, HPRE, PPRE1, PPRE2, ADCPRE and MCO bits */ +#ifndef STM32F10X_CL + RCC->CFGR &= (uint32_t)0xF8FF0000; +#else + RCC->CFGR &= (uint32_t)0xF0FF0000; +#endif /* STM32F10X_CL */ + + /* Reset HSEON, CSSON and PLLON bits */ + RCC->CR &= (uint32_t)0xFEF6FFFF; + + /* Reset HSEBYP bit */ + RCC->CR &= (uint32_t)0xFFFBFFFF; + + /* Reset PLLSRC, PLLXTPRE, PLLMUL and USBPRE/OTGFSPRE bits */ + RCC->CFGR &= (uint32_t)0xFF80FFFF; + +#ifdef STM32F10X_CL + /* Reset PLL2ON and PLL3ON bits */ + RCC->CR &= (uint32_t)0xEBFFFFFF; + + /* Disable all interrupts and clear pending bits */ + RCC->CIR = 0x00FF0000; + + /* Reset CFGR2 register */ + RCC->CFGR2 = 0x00000000; +#elif defined (STM32F10X_LD_VL) || defined (STM32F10X_MD_VL) || defined (STM32F10X_HD_VL) + /* Disable all interrupts and clear pending bits */ + RCC->CIR = 0x009F0000; + + /* Reset CFGR2 register */ + RCC->CFGR2 = 0x00000000; +#else + /* Disable all interrupts and clear pending bits */ + RCC->CIR = 0x009F0000; +#endif /* STM32F10X_CL */ + +} + +/** + * @brief Configures the External High Speed oscillator (HSE). + * @note HSE can not be stopped if it is used directly or through the PLL as system clock. + * @param RCC_HSE: specifies the new state of the HSE. + * This parameter can be one of the following values: + * @arg RCC_HSE_OFF: HSE oscillator OFF + * @arg RCC_HSE_ON: HSE oscillator ON + * @arg RCC_HSE_Bypass: HSE oscillator bypassed with external clock + * @retval None + */ +void RCC_HSEConfig(uint32_t RCC_HSE) +{ + /* Check the parameters */ + assert_param(IS_RCC_HSE(RCC_HSE)); + /* Reset HSEON and HSEBYP bits before configuring the HSE ------------------*/ + /* Reset HSEON bit */ + RCC->CR &= CR_HSEON_Reset; + /* Reset HSEBYP bit */ + RCC->CR &= CR_HSEBYP_Reset; + /* Configure HSE (RCC_HSE_OFF is already covered by the code section above) */ + switch(RCC_HSE) + { + case RCC_HSE_ON: + /* Set HSEON bit */ + RCC->CR |= CR_HSEON_Set; + break; + + case RCC_HSE_Bypass: + /* Set HSEBYP and HSEON bits */ + RCC->CR |= CR_HSEBYP_Set | CR_HSEON_Set; + break; + + default: + break; + } +} + +/** + * @brief Waits for HSE start-up. + * @param None + * @retval An ErrorStatus enumuration value: + * - SUCCESS: HSE oscillator is stable and ready to use + * - ERROR: HSE oscillator not yet ready + */ +ErrorStatus RCC_WaitForHSEStartUp(void) +{ + __IO uint32_t StartUpCounter = 0; + ErrorStatus status = ERROR; + FlagStatus HSEStatus = RESET; + + /* Wait till HSE is ready and if Time out is reached exit */ + do + { + HSEStatus = RCC_GetFlagStatus(RCC_FLAG_HSERDY); + StartUpCounter++; + } while((StartUpCounter != HSE_STARTUP_TIMEOUT) && (HSEStatus == RESET)); + + if (RCC_GetFlagStatus(RCC_FLAG_HSERDY) != RESET) + { + status = SUCCESS; + } + else + { + status = ERROR; + } + return (status); +} + +/** + * @brief Adjusts the Internal High Speed oscillator (HSI) calibration value. + * @param HSICalibrationValue: specifies the calibration trimming value. + * This parameter must be a number between 0 and 0x1F. + * @retval None + */ +void RCC_AdjustHSICalibrationValue(uint8_t HSICalibrationValue) +{ + uint32_t tmpreg = 0; + /* Check the parameters */ + assert_param(IS_RCC_CALIBRATION_VALUE(HSICalibrationValue)); + tmpreg = RCC->CR; + /* Clear HSITRIM[4:0] bits */ + tmpreg &= CR_HSITRIM_Mask; + /* Set the HSITRIM[4:0] bits according to HSICalibrationValue value */ + tmpreg |= (uint32_t)HSICalibrationValue << 3; + /* Store the new value */ + RCC->CR = tmpreg; +} + +/** + * @brief Enables or disables the Internal High Speed oscillator (HSI). + * @note HSI can not be stopped if it is used directly or through the PLL as system clock. + * @param NewState: new state of the HSI. This parameter can be: ENABLE or DISABLE. + * @retval None + */ +void RCC_HSICmd(FunctionalState NewState) +{ + /* Check the parameters */ + assert_param(IS_FUNCTIONAL_STATE(NewState)); + *(__IO uint32_t *) CR_HSION_BB = (uint32_t)NewState; +} + +/** + * @brief Configures the PLL clock source and multiplication factor. + * @note This function must be used only when the PLL is disabled. + * @param RCC_PLLSource: specifies the PLL entry clock source. + * For @b STM32_Connectivity_line_devices or @b STM32_Value_line_devices, + * this parameter can be one of the following values: + * @arg RCC_PLLSource_HSI_Div2: HSI oscillator clock divided by 2 selected as PLL clock entry + * @arg RCC_PLLSource_PREDIV1: PREDIV1 clock selected as PLL clock entry + * For @b other_STM32_devices, this parameter can be one of the following values: + * @arg RCC_PLLSource_HSI_Div2: HSI oscillator clock divided by 2 selected as PLL clock entry + * @arg RCC_PLLSource_HSE_Div1: HSE oscillator clock selected as PLL clock entry + * @arg RCC_PLLSource_HSE_Div2: HSE oscillator clock divided by 2 selected as PLL clock entry + * @param RCC_PLLMul: specifies the PLL multiplication factor. + * For @b STM32_Connectivity_line_devices, this parameter can be RCC_PLLMul_x where x:{[4,9], 6_5} + * For @b other_STM32_devices, this parameter can be RCC_PLLMul_x where x:[2,16] + * @retval None + */ +void RCC_PLLConfig(uint32_t RCC_PLLSource, uint32_t RCC_PLLMul) +{ + uint32_t tmpreg = 0; + + /* Check the parameters */ + assert_param(IS_RCC_PLL_SOURCE(RCC_PLLSource)); + assert_param(IS_RCC_PLL_MUL(RCC_PLLMul)); + + tmpreg = RCC->CFGR; + /* Clear PLLSRC, PLLXTPRE and PLLMUL[3:0] bits */ + tmpreg &= CFGR_PLL_Mask; + /* Set the PLL configuration bits */ + tmpreg |= RCC_PLLSource | RCC_PLLMul; + /* Store the new value */ + RCC->CFGR = tmpreg; +} + +/** + * @brief Enables or disables the PLL. + * @note The PLL can not be disabled if it is used as system clock. + * @param NewState: new state of the PLL. This parameter can be: ENABLE or DISABLE. + * @retval None + */ +void RCC_PLLCmd(FunctionalState NewState) +{ + /* Check the parameters */ + assert_param(IS_FUNCTIONAL_STATE(NewState)); + + *(__IO uint32_t *) CR_PLLON_BB = (uint32_t)NewState; +} + +#if defined (STM32F10X_LD_VL) || defined (STM32F10X_MD_VL) || defined (STM32F10X_HD_VL) || defined (STM32F10X_CL) +/** + * @brief Configures the PREDIV1 division factor. + * @note + * - This function must be used only when the PLL is disabled. + * - This function applies only to STM32 Connectivity line and Value line + * devices. + * @param RCC_PREDIV1_Source: specifies the PREDIV1 clock source. + * This parameter can be one of the following values: + * @arg RCC_PREDIV1_Source_HSE: HSE selected as PREDIV1 clock + * @arg RCC_PREDIV1_Source_PLL2: PLL2 selected as PREDIV1 clock + * @note + * For @b STM32_Value_line_devices this parameter is always RCC_PREDIV1_Source_HSE + * @param RCC_PREDIV1_Div: specifies the PREDIV1 clock division factor. + * This parameter can be RCC_PREDIV1_Divx where x:[1,16] + * @retval None + */ +void RCC_PREDIV1Config(uint32_t RCC_PREDIV1_Source, uint32_t RCC_PREDIV1_Div) +{ + uint32_t tmpreg = 0; + + /* Check the parameters */ + assert_param(IS_RCC_PREDIV1_SOURCE(RCC_PREDIV1_Source)); + assert_param(IS_RCC_PREDIV1(RCC_PREDIV1_Div)); + + tmpreg = RCC->CFGR2; + /* Clear PREDIV1[3:0] and PREDIV1SRC bits */ + tmpreg &= ~(CFGR2_PREDIV1 | CFGR2_PREDIV1SRC); + /* Set the PREDIV1 clock source and division factor */ + tmpreg |= RCC_PREDIV1_Source | RCC_PREDIV1_Div ; + /* Store the new value */ + RCC->CFGR2 = tmpreg; +} +#endif + +#ifdef STM32F10X_CL +/** + * @brief Configures the PREDIV2 division factor. + * @note + * - This function must be used only when both PLL2 and PLL3 are disabled. + * - This function applies only to STM32 Connectivity line devices. + * @param RCC_PREDIV2_Div: specifies the PREDIV2 clock division factor. + * This parameter can be RCC_PREDIV2_Divx where x:[1,16] + * @retval None + */ +void RCC_PREDIV2Config(uint32_t RCC_PREDIV2_Div) +{ + uint32_t tmpreg = 0; + + /* Check the parameters */ + assert_param(IS_RCC_PREDIV2(RCC_PREDIV2_Div)); + + tmpreg = RCC->CFGR2; + /* Clear PREDIV2[3:0] bits */ + tmpreg &= ~CFGR2_PREDIV2; + /* Set the PREDIV2 division factor */ + tmpreg |= RCC_PREDIV2_Div; + /* Store the new value */ + RCC->CFGR2 = tmpreg; +} + +/** + * @brief Configures the PLL2 multiplication factor. + * @note + * - This function must be used only when the PLL2 is disabled. + * - This function applies only to STM32 Connectivity line devices. + * @param RCC_PLL2Mul: specifies the PLL2 multiplication factor. + * This parameter can be RCC_PLL2Mul_x where x:{[8,14], 16, 20} + * @retval None + */ +void RCC_PLL2Config(uint32_t RCC_PLL2Mul) +{ + uint32_t tmpreg = 0; + + /* Check the parameters */ + assert_param(IS_RCC_PLL2_MUL(RCC_PLL2Mul)); + + tmpreg = RCC->CFGR2; + /* Clear PLL2Mul[3:0] bits */ + tmpreg &= ~CFGR2_PLL2MUL; + /* Set the PLL2 configuration bits */ + tmpreg |= RCC_PLL2Mul; + /* Store the new value */ + RCC->CFGR2 = tmpreg; +} + + +/** + * @brief Enables or disables the PLL2. + * @note + * - The PLL2 can not be disabled if it is used indirectly as system clock + * (i.e. it is used as PLL clock entry that is used as System clock). + * - This function applies only to STM32 Connectivity line devices. + * @param NewState: new state of the PLL2. This parameter can be: ENABLE or DISABLE. + * @retval None + */ +void RCC_PLL2Cmd(FunctionalState NewState) +{ + /* Check the parameters */ + assert_param(IS_FUNCTIONAL_STATE(NewState)); + + *(__IO uint32_t *) CR_PLL2ON_BB = (uint32_t)NewState; +} + + +/** + * @brief Configures the PLL3 multiplication factor. + * @note + * - This function must be used only when the PLL3 is disabled. + * - This function applies only to STM32 Connectivity line devices. + * @param RCC_PLL3Mul: specifies the PLL3 multiplication factor. + * This parameter can be RCC_PLL3Mul_x where x:{[8,14], 16, 20} + * @retval None + */ +void RCC_PLL3Config(uint32_t RCC_PLL3Mul) +{ + uint32_t tmpreg = 0; + + /* Check the parameters */ + assert_param(IS_RCC_PLL3_MUL(RCC_PLL3Mul)); + + tmpreg = RCC->CFGR2; + /* Clear PLL3Mul[3:0] bits */ + tmpreg &= ~CFGR2_PLL3MUL; + /* Set the PLL3 configuration bits */ + tmpreg |= RCC_PLL3Mul; + /* Store the new value */ + RCC->CFGR2 = tmpreg; +} + + +/** + * @brief Enables or disables the PLL3. + * @note This function applies only to STM32 Connectivity line devices. + * @param NewState: new state of the PLL3. This parameter can be: ENABLE or DISABLE. + * @retval None + */ +void RCC_PLL3Cmd(FunctionalState NewState) +{ + /* Check the parameters */ + + assert_param(IS_FUNCTIONAL_STATE(NewState)); + *(__IO uint32_t *) CR_PLL3ON_BB = (uint32_t)NewState; +} +#endif /* STM32F10X_CL */ + +/** + * @brief Configures the system clock (SYSCLK). + * @param RCC_SYSCLKSource: specifies the clock source used as system clock. + * This parameter can be one of the following values: + * @arg RCC_SYSCLKSource_HSI: HSI selected as system clock + * @arg RCC_SYSCLKSource_HSE: HSE selected as system clock + * @arg RCC_SYSCLKSource_PLLCLK: PLL selected as system clock + * @retval None + */ +void RCC_SYSCLKConfig(uint32_t RCC_SYSCLKSource) +{ + uint32_t tmpreg = 0; + /* Check the parameters */ + assert_param(IS_RCC_SYSCLK_SOURCE(RCC_SYSCLKSource)); + tmpreg = RCC->CFGR; + /* Clear SW[1:0] bits */ + tmpreg &= CFGR_SW_Mask; + /* Set SW[1:0] bits according to RCC_SYSCLKSource value */ + tmpreg |= RCC_SYSCLKSource; + /* Store the new value */ + RCC->CFGR = tmpreg; +} + +/** + * @brief Returns the clock source used as system clock. + * @param None + * @retval The clock source used as system clock. The returned value can + * be one of the following: + * - 0x00: HSI used as system clock + * - 0x04: HSE used as system clock + * - 0x08: PLL used as system clock + */ +uint8_t RCC_GetSYSCLKSource(void) +{ + return ((uint8_t)(RCC->CFGR & CFGR_SWS_Mask)); +} + +/** + * @brief Configures the AHB clock (HCLK). + * @param RCC_SYSCLK: defines the AHB clock divider. This clock is derived from + * the system clock (SYSCLK). + * This parameter can be one of the following values: + * @arg RCC_SYSCLK_Div1: AHB clock = SYSCLK + * @arg RCC_SYSCLK_Div2: AHB clock = SYSCLK/2 + * @arg RCC_SYSCLK_Div4: AHB clock = SYSCLK/4 + * @arg RCC_SYSCLK_Div8: AHB clock = SYSCLK/8 + * @arg RCC_SYSCLK_Div16: AHB clock = SYSCLK/16 + * @arg RCC_SYSCLK_Div64: AHB clock = SYSCLK/64 + * @arg RCC_SYSCLK_Div128: AHB clock = SYSCLK/128 + * @arg RCC_SYSCLK_Div256: AHB clock = SYSCLK/256 + * @arg RCC_SYSCLK_Div512: AHB clock = SYSCLK/512 + * @retval None + */ +void RCC_HCLKConfig(uint32_t RCC_SYSCLK) +{ + uint32_t tmpreg = 0; + /* Check the parameters */ + assert_param(IS_RCC_HCLK(RCC_SYSCLK)); + tmpreg = RCC->CFGR; + /* Clear HPRE[3:0] bits */ + tmpreg &= CFGR_HPRE_Reset_Mask; + /* Set HPRE[3:0] bits according to RCC_SYSCLK value */ + tmpreg |= RCC_SYSCLK; + /* Store the new value */ + RCC->CFGR = tmpreg; +} + +/** + * @brief Configures the Low Speed APB clock (PCLK1). + * @param RCC_HCLK: defines the APB1 clock divider. This clock is derived from + * the AHB clock (HCLK). + * This parameter can be one of the following values: + * @arg RCC_HCLK_Div1: APB1 clock = HCLK + * @arg RCC_HCLK_Div2: APB1 clock = HCLK/2 + * @arg RCC_HCLK_Div4: APB1 clock = HCLK/4 + * @arg RCC_HCLK_Div8: APB1 clock = HCLK/8 + * @arg RCC_HCLK_Div16: APB1 clock = HCLK/16 + * @retval None + */ +void RCC_PCLK1Config(uint32_t RCC_HCLK) +{ + uint32_t tmpreg = 0; + /* Check the parameters */ + assert_param(IS_RCC_PCLK(RCC_HCLK)); + tmpreg = RCC->CFGR; + /* Clear PPRE1[2:0] bits */ + tmpreg &= CFGR_PPRE1_Reset_Mask; + /* Set PPRE1[2:0] bits according to RCC_HCLK value */ + tmpreg |= RCC_HCLK; + /* Store the new value */ + RCC->CFGR = tmpreg; +} + +/** + * @brief Configures the High Speed APB clock (PCLK2). + * @param RCC_HCLK: defines the APB2 clock divider. This clock is derived from + * the AHB clock (HCLK). + * This parameter can be one of the following values: + * @arg RCC_HCLK_Div1: APB2 clock = HCLK + * @arg RCC_HCLK_Div2: APB2 clock = HCLK/2 + * @arg RCC_HCLK_Div4: APB2 clock = HCLK/4 + * @arg RCC_HCLK_Div8: APB2 clock = HCLK/8 + * @arg RCC_HCLK_Div16: APB2 clock = HCLK/16 + * @retval None + */ +void RCC_PCLK2Config(uint32_t RCC_HCLK) +{ + uint32_t tmpreg = 0; + /* Check the parameters */ + assert_param(IS_RCC_PCLK(RCC_HCLK)); + tmpreg = RCC->CFGR; + /* Clear PPRE2[2:0] bits */ + tmpreg &= CFGR_PPRE2_Reset_Mask; + /* Set PPRE2[2:0] bits according to RCC_HCLK value */ + tmpreg |= RCC_HCLK << 3; + /* Store the new value */ + RCC->CFGR = tmpreg; +} + +/** + * @brief Enables or disables the specified RCC interrupts. + * @param RCC_IT: specifies the RCC interrupt sources to be enabled or disabled. + * + * For @b STM32_Connectivity_line_devices, this parameter can be any combination + * of the following values + * @arg RCC_IT_LSIRDY: LSI ready interrupt + * @arg RCC_IT_LSERDY: LSE ready interrupt + * @arg RCC_IT_HSIRDY: HSI ready interrupt + * @arg RCC_IT_HSERDY: HSE ready interrupt + * @arg RCC_IT_PLLRDY: PLL ready interrupt + * @arg RCC_IT_PLL2RDY: PLL2 ready interrupt + * @arg RCC_IT_PLL3RDY: PLL3 ready interrupt + * + * For @b other_STM32_devices, this parameter can be any combination of the + * following values + * @arg RCC_IT_LSIRDY: LSI ready interrupt + * @arg RCC_IT_LSERDY: LSE ready interrupt + * @arg RCC_IT_HSIRDY: HSI ready interrupt + * @arg RCC_IT_HSERDY: HSE ready interrupt + * @arg RCC_IT_PLLRDY: PLL ready interrupt + * + * @param NewState: new state of the specified RCC interrupts. + * This parameter can be: ENABLE or DISABLE. + * @retval None + */ +void RCC_ITConfig(uint8_t RCC_IT, FunctionalState NewState) +{ + /* Check the parameters */ + assert_param(IS_RCC_IT(RCC_IT)); + assert_param(IS_FUNCTIONAL_STATE(NewState)); + if (NewState != DISABLE) + { + /* Perform Byte access to RCC_CIR bits to enable the selected interrupts */ + *(__IO uint8_t *) CIR_BYTE2_ADDRESS |= RCC_IT; + } + else + { + /* Perform Byte access to RCC_CIR bits to disable the selected interrupts */ + *(__IO uint8_t *) CIR_BYTE2_ADDRESS &= (uint8_t)~RCC_IT; + } +} + +#ifndef STM32F10X_CL +/** + * @brief Configures the USB clock (USBCLK). + * @param RCC_USBCLKSource: specifies the USB clock source. This clock is + * derived from the PLL output. + * This parameter can be one of the following values: + * @arg RCC_USBCLKSource_PLLCLK_1Div5: PLL clock divided by 1,5 selected as USB + * clock source + * @arg RCC_USBCLKSource_PLLCLK_Div1: PLL clock selected as USB clock source + * @retval None + */ +void RCC_USBCLKConfig(uint32_t RCC_USBCLKSource) +{ + /* Check the parameters */ + assert_param(IS_RCC_USBCLK_SOURCE(RCC_USBCLKSource)); + + *(__IO uint32_t *) CFGR_USBPRE_BB = RCC_USBCLKSource; +} +#else +/** + * @brief Configures the USB OTG FS clock (OTGFSCLK). + * This function applies only to STM32 Connectivity line devices. + * @param RCC_OTGFSCLKSource: specifies the USB OTG FS clock source. + * This clock is derived from the PLL output. + * This parameter can be one of the following values: + * @arg RCC_OTGFSCLKSource_PLLVCO_Div3: PLL VCO clock divided by 2 selected as USB OTG FS clock source + * @arg RCC_OTGFSCLKSource_PLLVCO_Div2: PLL VCO clock divided by 2 selected as USB OTG FS clock source + * @retval None + */ +void RCC_OTGFSCLKConfig(uint32_t RCC_OTGFSCLKSource) +{ + /* Check the parameters */ + assert_param(IS_RCC_OTGFSCLK_SOURCE(RCC_OTGFSCLKSource)); + + *(__IO uint32_t *) CFGR_OTGFSPRE_BB = RCC_OTGFSCLKSource; +} +#endif /* STM32F10X_CL */ + +/** + * @brief Configures the ADC clock (ADCCLK). + * @param RCC_PCLK2: defines the ADC clock divider. This clock is derived from + * the APB2 clock (PCLK2). + * This parameter can be one of the following values: + * @arg RCC_PCLK2_Div2: ADC clock = PCLK2/2 + * @arg RCC_PCLK2_Div4: ADC clock = PCLK2/4 + * @arg RCC_PCLK2_Div6: ADC clock = PCLK2/6 + * @arg RCC_PCLK2_Div8: ADC clock = PCLK2/8 + * @retval None + */ +void RCC_ADCCLKConfig(uint32_t RCC_PCLK2) +{ + uint32_t tmpreg = 0; + /* Check the parameters */ + assert_param(IS_RCC_ADCCLK(RCC_PCLK2)); + tmpreg = RCC->CFGR; + /* Clear ADCPRE[1:0] bits */ + tmpreg &= CFGR_ADCPRE_Reset_Mask; + /* Set ADCPRE[1:0] bits according to RCC_PCLK2 value */ + tmpreg |= RCC_PCLK2; + /* Store the new value */ + RCC->CFGR = tmpreg; +} + +#ifdef STM32F10X_CL +/** + * @brief Configures the I2S2 clock source(I2S2CLK). + * @note + * - This function must be called before enabling I2S2 APB clock. + * - This function applies only to STM32 Connectivity line devices. + * @param RCC_I2S2CLKSource: specifies the I2S2 clock source. + * This parameter can be one of the following values: + * @arg RCC_I2S2CLKSource_SYSCLK: system clock selected as I2S2 clock entry + * @arg RCC_I2S2CLKSource_PLL3_VCO: PLL3 VCO clock selected as I2S2 clock entry + * @retval None + */ +void RCC_I2S2CLKConfig(uint32_t RCC_I2S2CLKSource) +{ + /* Check the parameters */ + assert_param(IS_RCC_I2S2CLK_SOURCE(RCC_I2S2CLKSource)); + + *(__IO uint32_t *) CFGR2_I2S2SRC_BB = RCC_I2S2CLKSource; +} + +/** + * @brief Configures the I2S3 clock source(I2S2CLK). + * @note + * - This function must be called before enabling I2S3 APB clock. + * - This function applies only to STM32 Connectivity line devices. + * @param RCC_I2S3CLKSource: specifies the I2S3 clock source. + * This parameter can be one of the following values: + * @arg RCC_I2S3CLKSource_SYSCLK: system clock selected as I2S3 clock entry + * @arg RCC_I2S3CLKSource_PLL3_VCO: PLL3 VCO clock selected as I2S3 clock entry + * @retval None + */ +void RCC_I2S3CLKConfig(uint32_t RCC_I2S3CLKSource) +{ + /* Check the parameters */ + assert_param(IS_RCC_I2S3CLK_SOURCE(RCC_I2S3CLKSource)); + + *(__IO uint32_t *) CFGR2_I2S3SRC_BB = RCC_I2S3CLKSource; +} +#endif /* STM32F10X_CL */ + +/** + * @brief Configures the External Low Speed oscillator (LSE). + * @param RCC_LSE: specifies the new state of the LSE. + * This parameter can be one of the following values: + * @arg RCC_LSE_OFF: LSE oscillator OFF + * @arg RCC_LSE_ON: LSE oscillator ON + * @arg RCC_LSE_Bypass: LSE oscillator bypassed with external clock + * @retval None + */ +void RCC_LSEConfig(uint8_t RCC_LSE) +{ + /* Check the parameters */ + assert_param(IS_RCC_LSE(RCC_LSE)); + /* Reset LSEON and LSEBYP bits before configuring the LSE ------------------*/ + /* Reset LSEON bit */ + *(__IO uint8_t *) BDCR_ADDRESS = RCC_LSE_OFF; + /* Reset LSEBYP bit */ + *(__IO uint8_t *) BDCR_ADDRESS = RCC_LSE_OFF; + /* Configure LSE (RCC_LSE_OFF is already covered by the code section above) */ + switch(RCC_LSE) + { + case RCC_LSE_ON: + /* Set LSEON bit */ + *(__IO uint8_t *) BDCR_ADDRESS = RCC_LSE_ON; + break; + + case RCC_LSE_Bypass: + /* Set LSEBYP and LSEON bits */ + *(__IO uint8_t *) BDCR_ADDRESS = RCC_LSE_Bypass | RCC_LSE_ON; + break; + + default: + break; + } +} + +/** + * @brief Enables or disables the Internal Low Speed oscillator (LSI). + * @note LSI can not be disabled if the IWDG is running. + * @param NewState: new state of the LSI. This parameter can be: ENABLE or DISABLE. + * @retval None + */ +void RCC_LSICmd(FunctionalState NewState) +{ + /* Check the parameters */ + assert_param(IS_FUNCTIONAL_STATE(NewState)); + *(__IO uint32_t *) CSR_LSION_BB = (uint32_t)NewState; +} + +/** + * @brief Configures the RTC clock (RTCCLK). + * @note Once the RTC clock is selected it can't be changed unless the Backup domain is reset. + * @param RCC_RTCCLKSource: specifies the RTC clock source. + * This parameter can be one of the following values: + * @arg RCC_RTCCLKSource_LSE: LSE selected as RTC clock + * @arg RCC_RTCCLKSource_LSI: LSI selected as RTC clock + * @arg RCC_RTCCLKSource_HSE_Div128: HSE clock divided by 128 selected as RTC clock + * @retval None + */ +void RCC_RTCCLKConfig(uint32_t RCC_RTCCLKSource) +{ + /* Check the parameters */ + assert_param(IS_RCC_RTCCLK_SOURCE(RCC_RTCCLKSource)); + /* Select the RTC clock source */ + RCC->BDCR |= RCC_RTCCLKSource; +} + +/** + * @brief Enables or disables the RTC clock. + * @note This function must be used only after the RTC clock was selected using the RCC_RTCCLKConfig function. + * @param NewState: new state of the RTC clock. This parameter can be: ENABLE or DISABLE. + * @retval None + */ +void RCC_RTCCLKCmd(FunctionalState NewState) +{ + /* Check the parameters */ + assert_param(IS_FUNCTIONAL_STATE(NewState)); + *(__IO uint32_t *) BDCR_RTCEN_BB = (uint32_t)NewState; +} + +/** + * @brief Returns the frequencies of different on chip clocks. + * @param RCC_Clocks: pointer to a RCC_ClocksTypeDef structure which will hold + * the clocks frequencies. + * @note The result of this function could be not correct when using + * fractional value for HSE crystal. + * @retval None + */ +void RCC_GetClocksFreq(RCC_ClocksTypeDef* RCC_Clocks) +{ + uint32_t tmp = 0, pllmull = 0, pllsource = 0, presc = 0; + +#ifdef STM32F10X_CL + uint32_t prediv1source = 0, prediv1factor = 0, prediv2factor = 0, pll2mull = 0; +#endif /* STM32F10X_CL */ + +#if defined (STM32F10X_LD_VL) || defined (STM32F10X_MD_VL) || defined (STM32F10X_HD_VL) + uint32_t prediv1factor = 0; +#endif + + /* Get SYSCLK source -------------------------------------------------------*/ + tmp = RCC->CFGR & CFGR_SWS_Mask; + + switch (tmp) + { + case 0x00: /* HSI used as system clock */ + RCC_Clocks->SYSCLK_Frequency = HSI_VALUE; + break; + case 0x04: /* HSE used as system clock */ + RCC_Clocks->SYSCLK_Frequency = HSE_VALUE; + break; + case 0x08: /* PLL used as system clock */ + + /* Get PLL clock source and multiplication factor ----------------------*/ + pllmull = RCC->CFGR & CFGR_PLLMull_Mask; + pllsource = RCC->CFGR & CFGR_PLLSRC_Mask; + +#ifndef STM32F10X_CL + pllmull = ( pllmull >> 18) + 2; + + if (pllsource == 0x00) + {/* HSI oscillator clock divided by 2 selected as PLL clock entry */ + RCC_Clocks->SYSCLK_Frequency = (HSI_VALUE >> 1) * pllmull; + } + else + { + #if defined (STM32F10X_LD_VL) || defined (STM32F10X_MD_VL) || defined (STM32F10X_HD_VL) + prediv1factor = (RCC->CFGR2 & CFGR2_PREDIV1) + 1; + /* HSE oscillator clock selected as PREDIV1 clock entry */ + RCC_Clocks->SYSCLK_Frequency = (HSE_VALUE / prediv1factor) * pllmull; + #else + /* HSE selected as PLL clock entry */ + if ((RCC->CFGR & CFGR_PLLXTPRE_Mask) != (uint32_t)RESET) + {/* HSE oscillator clock divided by 2 */ + RCC_Clocks->SYSCLK_Frequency = (HSE_VALUE >> 1) * pllmull; + } + else + { + RCC_Clocks->SYSCLK_Frequency = HSE_VALUE * pllmull; + } + #endif + } +#else + pllmull = pllmull >> 18; + + if (pllmull != 0x0D) + { + pllmull += 2; + } + else + { /* PLL multiplication factor = PLL input clock * 6.5 */ + pllmull = 13 / 2; + } + + if (pllsource == 0x00) + {/* HSI oscillator clock divided by 2 selected as PLL clock entry */ + RCC_Clocks->SYSCLK_Frequency = (HSI_VALUE >> 1) * pllmull; + } + else + {/* PREDIV1 selected as PLL clock entry */ + + /* Get PREDIV1 clock source and division factor */ + prediv1source = RCC->CFGR2 & CFGR2_PREDIV1SRC; + prediv1factor = (RCC->CFGR2 & CFGR2_PREDIV1) + 1; + + if (prediv1source == 0) + { /* HSE oscillator clock selected as PREDIV1 clock entry */ + RCC_Clocks->SYSCLK_Frequency = (HSE_VALUE / prediv1factor) * pllmull; + } + else + {/* PLL2 clock selected as PREDIV1 clock entry */ + + /* Get PREDIV2 division factor and PLL2 multiplication factor */ + prediv2factor = ((RCC->CFGR2 & CFGR2_PREDIV2) >> 4) + 1; + pll2mull = ((RCC->CFGR2 & CFGR2_PLL2MUL) >> 8 ) + 2; + RCC_Clocks->SYSCLK_Frequency = (((HSE_VALUE / prediv2factor) * pll2mull) / prediv1factor) * pllmull; + } + } +#endif /* STM32F10X_CL */ + break; + + default: + RCC_Clocks->SYSCLK_Frequency = HSI_VALUE; + break; + } + + /* Compute HCLK, PCLK1, PCLK2 and ADCCLK clocks frequencies ----------------*/ + /* Get HCLK prescaler */ + tmp = RCC->CFGR & CFGR_HPRE_Set_Mask; + tmp = tmp >> 4; + presc = APBAHBPrescTable[tmp]; + /* HCLK clock frequency */ + RCC_Clocks->HCLK_Frequency = RCC_Clocks->SYSCLK_Frequency >> presc; + /* Get PCLK1 prescaler */ + tmp = RCC->CFGR & CFGR_PPRE1_Set_Mask; + tmp = tmp >> 8; + presc = APBAHBPrescTable[tmp]; + /* PCLK1 clock frequency */ + RCC_Clocks->PCLK1_Frequency = RCC_Clocks->HCLK_Frequency >> presc; + /* Get PCLK2 prescaler */ + tmp = RCC->CFGR & CFGR_PPRE2_Set_Mask; + tmp = tmp >> 11; + presc = APBAHBPrescTable[tmp]; + /* PCLK2 clock frequency */ + RCC_Clocks->PCLK2_Frequency = RCC_Clocks->HCLK_Frequency >> presc; + /* Get ADCCLK prescaler */ + tmp = RCC->CFGR & CFGR_ADCPRE_Set_Mask; + tmp = tmp >> 14; + presc = ADCPrescTable[tmp]; + /* ADCCLK clock frequency */ + RCC_Clocks->ADCCLK_Frequency = RCC_Clocks->PCLK2_Frequency / presc; +} + +/** + * @brief Enables or disables the AHB peripheral clock. + * @param RCC_AHBPeriph: specifies the AHB peripheral to gates its clock. + * + * For @b STM32_Connectivity_line_devices, this parameter can be any combination + * of the following values: + * @arg RCC_AHBPeriph_DMA1 + * @arg RCC_AHBPeriph_DMA2 + * @arg RCC_AHBPeriph_SRAM + * @arg RCC_AHBPeriph_FLITF + * @arg RCC_AHBPeriph_CRC + * @arg RCC_AHBPeriph_OTG_FS + * @arg RCC_AHBPeriph_ETH_MAC + * @arg RCC_AHBPeriph_ETH_MAC_Tx + * @arg RCC_AHBPeriph_ETH_MAC_Rx + * + * For @b other_STM32_devices, this parameter can be any combination of the + * following values: + * @arg RCC_AHBPeriph_DMA1 + * @arg RCC_AHBPeriph_DMA2 + * @arg RCC_AHBPeriph_SRAM + * @arg RCC_AHBPeriph_FLITF + * @arg RCC_AHBPeriph_CRC + * @arg RCC_AHBPeriph_FSMC + * @arg RCC_AHBPeriph_SDIO + * + * @note SRAM and FLITF clock can be disabled only during sleep mode. + * @param NewState: new state of the specified peripheral clock. + * This parameter can be: ENABLE or DISABLE. + * @retval None + */ +void RCC_AHBPeriphClockCmd(uint32_t RCC_AHBPeriph, FunctionalState NewState) +{ + /* Check the parameters */ + assert_param(IS_RCC_AHB_PERIPH(RCC_AHBPeriph)); + assert_param(IS_FUNCTIONAL_STATE(NewState)); + + if (NewState != DISABLE) + { + RCC->AHBENR |= RCC_AHBPeriph; + } + else + { + RCC->AHBENR &= ~RCC_AHBPeriph; + } +} + +/** + * @brief Enables or disables the High Speed APB (APB2) peripheral clock. + * @param RCC_APB2Periph: specifies the APB2 peripheral to gates its clock. + * This parameter can be any combination of the following values: + * @arg RCC_APB2Periph_AFIO, RCC_APB2Periph_GPIOA, RCC_APB2Periph_GPIOB, + * RCC_APB2Periph_GPIOC, RCC_APB2Periph_GPIOD, RCC_APB2Periph_GPIOE, + * RCC_APB2Periph_GPIOF, RCC_APB2Periph_GPIOG, RCC_APB2Periph_ADC1, + * RCC_APB2Periph_ADC2, RCC_APB2Periph_TIM1, RCC_APB2Periph_SPI1, + * RCC_APB2Periph_TIM8, RCC_APB2Periph_USART1, RCC_APB2Periph_ADC3, + * RCC_APB2Periph_TIM15, RCC_APB2Periph_TIM16, RCC_APB2Periph_TIM17, + * RCC_APB2Periph_TIM9, RCC_APB2Periph_TIM10, RCC_APB2Periph_TIM11 + * @param NewState: new state of the specified peripheral clock. + * This parameter can be: ENABLE or DISABLE. + * @retval None + */ +void RCC_APB2PeriphClockCmd(uint32_t RCC_APB2Periph, FunctionalState NewState) +{ + /* Check the parameters */ + assert_param(IS_RCC_APB2_PERIPH(RCC_APB2Periph)); + assert_param(IS_FUNCTIONAL_STATE(NewState)); + if (NewState != DISABLE) + { + RCC->APB2ENR |= RCC_APB2Periph; + } + else + { + RCC->APB2ENR &= ~RCC_APB2Periph; + } +} + +/** + * @brief Enables or disables the Low Speed APB (APB1) peripheral clock. + * @param RCC_APB1Periph: specifies the APB1 peripheral to gates its clock. + * This parameter can be any combination of the following values: + * @arg RCC_APB1Periph_TIM2, RCC_APB1Periph_TIM3, RCC_APB1Periph_TIM4, + * RCC_APB1Periph_TIM5, RCC_APB1Periph_TIM6, RCC_APB1Periph_TIM7, + * RCC_APB1Periph_WWDG, RCC_APB1Periph_SPI2, RCC_APB1Periph_SPI3, + * RCC_APB1Periph_USART2, RCC_APB1Periph_USART3, RCC_APB1Periph_USART4, + * RCC_APB1Periph_USART5, RCC_APB1Periph_I2C1, RCC_APB1Periph_I2C2, + * RCC_APB1Periph_USB, RCC_APB1Periph_CAN1, RCC_APB1Periph_BKP, + * RCC_APB1Periph_PWR, RCC_APB1Periph_DAC, RCC_APB1Periph_CEC, + * RCC_APB1Periph_TIM12, RCC_APB1Periph_TIM13, RCC_APB1Periph_TIM14 + * @param NewState: new state of the specified peripheral clock. + * This parameter can be: ENABLE or DISABLE. + * @retval None + */ +void RCC_APB1PeriphClockCmd(uint32_t RCC_APB1Periph, FunctionalState NewState) +{ + /* Check the parameters */ + assert_param(IS_RCC_APB1_PERIPH(RCC_APB1Periph)); + assert_param(IS_FUNCTIONAL_STATE(NewState)); + if (NewState != DISABLE) + { + RCC->APB1ENR |= RCC_APB1Periph; + } + else + { + RCC->APB1ENR &= ~RCC_APB1Periph; + } +} + +#ifdef STM32F10X_CL +/** + * @brief Forces or releases AHB peripheral reset. + * @note This function applies only to STM32 Connectivity line devices. + * @param RCC_AHBPeriph: specifies the AHB peripheral to reset. + * This parameter can be any combination of the following values: + * @arg RCC_AHBPeriph_OTG_FS + * @arg RCC_AHBPeriph_ETH_MAC + * @param NewState: new state of the specified peripheral reset. + * This parameter can be: ENABLE or DISABLE. + * @retval None + */ +void RCC_AHBPeriphResetCmd(uint32_t RCC_AHBPeriph, FunctionalState NewState) +{ + /* Check the parameters */ + assert_param(IS_RCC_AHB_PERIPH_RESET(RCC_AHBPeriph)); + assert_param(IS_FUNCTIONAL_STATE(NewState)); + + if (NewState != DISABLE) + { + RCC->AHBRSTR |= RCC_AHBPeriph; + } + else + { + RCC->AHBRSTR &= ~RCC_AHBPeriph; + } +} +#endif /* STM32F10X_CL */ + +/** + * @brief Forces or releases High Speed APB (APB2) peripheral reset. + * @param RCC_APB2Periph: specifies the APB2 peripheral to reset. + * This parameter can be any combination of the following values: + * @arg RCC_APB2Periph_AFIO, RCC_APB2Periph_GPIOA, RCC_APB2Periph_GPIOB, + * RCC_APB2Periph_GPIOC, RCC_APB2Periph_GPIOD, RCC_APB2Periph_GPIOE, + * RCC_APB2Periph_GPIOF, RCC_APB2Periph_GPIOG, RCC_APB2Periph_ADC1, + * RCC_APB2Periph_ADC2, RCC_APB2Periph_TIM1, RCC_APB2Periph_SPI1, + * RCC_APB2Periph_TIM8, RCC_APB2Periph_USART1, RCC_APB2Periph_ADC3, + * RCC_APB2Periph_TIM15, RCC_APB2Periph_TIM16, RCC_APB2Periph_TIM17, + * RCC_APB2Periph_TIM9, RCC_APB2Periph_TIM10, RCC_APB2Periph_TIM11 + * @param NewState: new state of the specified peripheral reset. + * This parameter can be: ENABLE or DISABLE. + * @retval None + */ +void RCC_APB2PeriphResetCmd(uint32_t RCC_APB2Periph, FunctionalState NewState) +{ + /* Check the parameters */ + assert_param(IS_RCC_APB2_PERIPH(RCC_APB2Periph)); + assert_param(IS_FUNCTIONAL_STATE(NewState)); + if (NewState != DISABLE) + { + RCC->APB2RSTR |= RCC_APB2Periph; + } + else + { + RCC->APB2RSTR &= ~RCC_APB2Periph; + } +} + +/** + * @brief Forces or releases Low Speed APB (APB1) peripheral reset. + * @param RCC_APB1Periph: specifies the APB1 peripheral to reset. + * This parameter can be any combination of the following values: + * @arg RCC_APB1Periph_TIM2, RCC_APB1Periph_TIM3, RCC_APB1Periph_TIM4, + * RCC_APB1Periph_TIM5, RCC_APB1Periph_TIM6, RCC_APB1Periph_TIM7, + * RCC_APB1Periph_WWDG, RCC_APB1Periph_SPI2, RCC_APB1Periph_SPI3, + * RCC_APB1Periph_USART2, RCC_APB1Periph_USART3, RCC_APB1Periph_USART4, + * RCC_APB1Periph_USART5, RCC_APB1Periph_I2C1, RCC_APB1Periph_I2C2, + * RCC_APB1Periph_USB, RCC_APB1Periph_CAN1, RCC_APB1Periph_BKP, + * RCC_APB1Periph_PWR, RCC_APB1Periph_DAC, RCC_APB1Periph_CEC, + * RCC_APB1Periph_TIM12, RCC_APB1Periph_TIM13, RCC_APB1Periph_TIM14 + * @param NewState: new state of the specified peripheral clock. + * This parameter can be: ENABLE or DISABLE. + * @retval None + */ +void RCC_APB1PeriphResetCmd(uint32_t RCC_APB1Periph, FunctionalState NewState) +{ + /* Check the parameters */ + assert_param(IS_RCC_APB1_PERIPH(RCC_APB1Periph)); + assert_param(IS_FUNCTIONAL_STATE(NewState)); + if (NewState != DISABLE) + { + RCC->APB1RSTR |= RCC_APB1Periph; + } + else + { + RCC->APB1RSTR &= ~RCC_APB1Periph; + } +} + +/** + * @brief Forces or releases the Backup domain reset. + * @param NewState: new state of the Backup domain reset. + * This parameter can be: ENABLE or DISABLE. + * @retval None + */ +void RCC_BackupResetCmd(FunctionalState NewState) +{ + /* Check the parameters */ + assert_param(IS_FUNCTIONAL_STATE(NewState)); + *(__IO uint32_t *) BDCR_BDRST_BB = (uint32_t)NewState; +} + +/** + * @brief Enables or disables the Clock Security System. + * @param NewState: new state of the Clock Security System.. + * This parameter can be: ENABLE or DISABLE. + * @retval None + */ +void RCC_ClockSecuritySystemCmd(FunctionalState NewState) +{ + /* Check the parameters */ + assert_param(IS_FUNCTIONAL_STATE(NewState)); + *(__IO uint32_t *) CR_CSSON_BB = (uint32_t)NewState; +} + +/** + * @brief Selects the clock source to output on MCO pin. + * @param RCC_MCO: specifies the clock source to output. + * + * For @b STM32_Connectivity_line_devices, this parameter can be one of the + * following values: + * @arg RCC_MCO_NoClock: No clock selected + * @arg RCC_MCO_SYSCLK: System clock selected + * @arg RCC_MCO_HSI: HSI oscillator clock selected + * @arg RCC_MCO_HSE: HSE oscillator clock selected + * @arg RCC_MCO_PLLCLK_Div2: PLL clock divided by 2 selected + * @arg RCC_MCO_PLL2CLK: PLL2 clock selected + * @arg RCC_MCO_PLL3CLK_Div2: PLL3 clock divided by 2 selected + * @arg RCC_MCO_XT1: External 3-25 MHz oscillator clock selected + * @arg RCC_MCO_PLL3CLK: PLL3 clock selected + * + * For @b other_STM32_devices, this parameter can be one of the following values: + * @arg RCC_MCO_NoClock: No clock selected + * @arg RCC_MCO_SYSCLK: System clock selected + * @arg RCC_MCO_HSI: HSI oscillator clock selected + * @arg RCC_MCO_HSE: HSE oscillator clock selected + * @arg RCC_MCO_PLLCLK_Div2: PLL clock divided by 2 selected + * + * @retval None + */ +void RCC_MCOConfig(uint8_t RCC_MCO) +{ + /* Check the parameters */ + assert_param(IS_RCC_MCO(RCC_MCO)); + + /* Perform Byte access to MCO bits to select the MCO source */ + *(__IO uint8_t *) CFGR_BYTE4_ADDRESS = RCC_MCO; +} + +/** + * @brief Checks whether the specified RCC flag is set or not. + * @param RCC_FLAG: specifies the flag to check. + * + * For @b STM32_Connectivity_line_devices, this parameter can be one of the + * following values: + * @arg RCC_FLAG_HSIRDY: HSI oscillator clock ready + * @arg RCC_FLAG_HSERDY: HSE oscillator clock ready + * @arg RCC_FLAG_PLLRDY: PLL clock ready + * @arg RCC_FLAG_PLL2RDY: PLL2 clock ready + * @arg RCC_FLAG_PLL3RDY: PLL3 clock ready + * @arg RCC_FLAG_LSERDY: LSE oscillator clock ready + * @arg RCC_FLAG_LSIRDY: LSI oscillator clock ready + * @arg RCC_FLAG_PINRST: Pin reset + * @arg RCC_FLAG_PORRST: POR/PDR reset + * @arg RCC_FLAG_SFTRST: Software reset + * @arg RCC_FLAG_IWDGRST: Independent Watchdog reset + * @arg RCC_FLAG_WWDGRST: Window Watchdog reset + * @arg RCC_FLAG_LPWRRST: Low Power reset + * + * For @b other_STM32_devices, this parameter can be one of the following values: + * @arg RCC_FLAG_HSIRDY: HSI oscillator clock ready + * @arg RCC_FLAG_HSERDY: HSE oscillator clock ready + * @arg RCC_FLAG_PLLRDY: PLL clock ready + * @arg RCC_FLAG_LSERDY: LSE oscillator clock ready + * @arg RCC_FLAG_LSIRDY: LSI oscillator clock ready + * @arg RCC_FLAG_PINRST: Pin reset + * @arg RCC_FLAG_PORRST: POR/PDR reset + * @arg RCC_FLAG_SFTRST: Software reset + * @arg RCC_FLAG_IWDGRST: Independent Watchdog reset + * @arg RCC_FLAG_WWDGRST: Window Watchdog reset + * @arg RCC_FLAG_LPWRRST: Low Power reset + * + * @retval The new state of RCC_FLAG (SET or RESET). + */ +FlagStatus RCC_GetFlagStatus(uint8_t RCC_FLAG) +{ + uint32_t tmp = 0; + uint32_t statusreg = 0; + FlagStatus bitstatus = RESET; + /* Check the parameters */ + assert_param(IS_RCC_FLAG(RCC_FLAG)); + + /* Get the RCC register index */ + tmp = RCC_FLAG >> 5; + if (tmp == 1) /* The flag to check is in CR register */ + { + statusreg = RCC->CR; + } + else if (tmp == 2) /* The flag to check is in BDCR register */ + { + statusreg = RCC->BDCR; + } + else /* The flag to check is in CSR register */ + { + statusreg = RCC->CSR; + } + + /* Get the flag position */ + tmp = RCC_FLAG & FLAG_Mask; + if ((statusreg & ((uint32_t)1 << tmp)) != (uint32_t)RESET) + { + bitstatus = SET; + } + else + { + bitstatus = RESET; + } + + /* Return the flag status */ + return bitstatus; +} + +/** + * @brief Clears the RCC reset flags. + * @note The reset flags are: RCC_FLAG_PINRST, RCC_FLAG_PORRST, RCC_FLAG_SFTRST, + * RCC_FLAG_IWDGRST, RCC_FLAG_WWDGRST, RCC_FLAG_LPWRRST + * @param None + * @retval None + */ +void RCC_ClearFlag(void) +{ + /* Set RMVF bit to clear the reset flags */ + RCC->CSR |= CSR_RMVF_Set; +} + +/** + * @brief Checks whether the specified RCC interrupt has occurred or not. + * @param RCC_IT: specifies the RCC interrupt source to check. + * + * For @b STM32_Connectivity_line_devices, this parameter can be one of the + * following values: + * @arg RCC_IT_LSIRDY: LSI ready interrupt + * @arg RCC_IT_LSERDY: LSE ready interrupt + * @arg RCC_IT_HSIRDY: HSI ready interrupt + * @arg RCC_IT_HSERDY: HSE ready interrupt + * @arg RCC_IT_PLLRDY: PLL ready interrupt + * @arg RCC_IT_PLL2RDY: PLL2 ready interrupt + * @arg RCC_IT_PLL3RDY: PLL3 ready interrupt + * @arg RCC_IT_CSS: Clock Security System interrupt + * + * For @b other_STM32_devices, this parameter can be one of the following values: + * @arg RCC_IT_LSIRDY: LSI ready interrupt + * @arg RCC_IT_LSERDY: LSE ready interrupt + * @arg RCC_IT_HSIRDY: HSI ready interrupt + * @arg RCC_IT_HSERDY: HSE ready interrupt + * @arg RCC_IT_PLLRDY: PLL ready interrupt + * @arg RCC_IT_CSS: Clock Security System interrupt + * + * @retval The new state of RCC_IT (SET or RESET). + */ +ITStatus RCC_GetITStatus(uint8_t RCC_IT) +{ + ITStatus bitstatus = RESET; + /* Check the parameters */ + assert_param(IS_RCC_GET_IT(RCC_IT)); + + /* Check the status of the specified RCC interrupt */ + if ((RCC->CIR & RCC_IT) != (uint32_t)RESET) + { + bitstatus = SET; + } + else + { + bitstatus = RESET; + } + + /* Return the RCC_IT status */ + return bitstatus; +} + +/** + * @brief Clears the RCC's interrupt pending bits. + * @param RCC_IT: specifies the interrupt pending bit to clear. + * + * For @b STM32_Connectivity_line_devices, this parameter can be any combination + * of the following values: + * @arg RCC_IT_LSIRDY: LSI ready interrupt + * @arg RCC_IT_LSERDY: LSE ready interrupt + * @arg RCC_IT_HSIRDY: HSI ready interrupt + * @arg RCC_IT_HSERDY: HSE ready interrupt + * @arg RCC_IT_PLLRDY: PLL ready interrupt + * @arg RCC_IT_PLL2RDY: PLL2 ready interrupt + * @arg RCC_IT_PLL3RDY: PLL3 ready interrupt + * @arg RCC_IT_CSS: Clock Security System interrupt + * + * For @b other_STM32_devices, this parameter can be any combination of the + * following values: + * @arg RCC_IT_LSIRDY: LSI ready interrupt + * @arg RCC_IT_LSERDY: LSE ready interrupt + * @arg RCC_IT_HSIRDY: HSI ready interrupt + * @arg RCC_IT_HSERDY: HSE ready interrupt + * @arg RCC_IT_PLLRDY: PLL ready interrupt + * + * @arg RCC_IT_CSS: Clock Security System interrupt + * @retval None + */ +void RCC_ClearITPendingBit(uint8_t RCC_IT) +{ + /* Check the parameters */ + assert_param(IS_RCC_CLEAR_IT(RCC_IT)); + + /* Perform Byte access to RCC_CIR[23:16] bits to clear the selected interrupt + pending bits */ + *(__IO uint8_t *) CIR_BYTE3_ADDRESS = RCC_IT; +} + +/** + * @} + */ + +/** + * @} + */ + +/** + * @} + */ + +/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ diff --git a/Libraries/STM32F10x_StdPeriph_Driver/src/stm32f10x_rtc.c b/Libraries/STM32F10x_StdPeriph_Driver/src/stm32f10x_rtc.c new file mode 100644 index 0000000..4e31359 --- /dev/null +++ b/Libraries/STM32F10x_StdPeriph_Driver/src/stm32f10x_rtc.c @@ -0,0 +1,358 @@ +/** + ****************************************************************************** + * @file stm32f10x_rtc.c + * @author MCD Application Team + * @version V3.6.1 + * @date 05-March-2012 + * @brief This file provides all the RTC firmware functions. + ****************************************************************************** + * @attention + * + *

    © COPYRIGHT 2012 STMicroelectronics

    + * + * Licensed under MCD-ST Liberty SW License Agreement V2, (the "License"); + * You may not use this file except in compliance with the License. + * You may obtain a copy of the License at: + * + * http://www.st.com/software_license_agreement_liberty_v2 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, + * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + * + ****************************************************************************** + */ + +/* Includes ------------------------------------------------------------------*/ +#include "stm32f10x_rtc.h" + +/** @addtogroup STM32F10x_StdPeriph_Driver + * @{ + */ + +/** @defgroup RTC + * @brief RTC driver modules + * @{ + */ + +/** @defgroup RTC_Private_TypesDefinitions + * @{ + */ +/** + * @} + */ + +/** @defgroup RTC_Private_Defines + * @{ + */ +#define RTC_LSB_MASK ((uint32_t)0x0000FFFF) /*!< RTC LSB Mask */ +#define PRLH_MSB_MASK ((uint32_t)0x000F0000) /*!< RTC Prescaler MSB Mask */ + +/** + * @} + */ + +/** @defgroup RTC_Private_Macros + * @{ + */ + +/** + * @} + */ + +/** @defgroup RTC_Private_Variables + * @{ + */ + +/** + * @} + */ + +/** @defgroup RTC_Private_FunctionPrototypes + * @{ + */ + +/** + * @} + */ + +/** @defgroup RTC_Private_Functions + * @{ + */ + +/** + * @brief Enables or disables the specified RTC interrupts. + * @param RTC_IT: specifies the RTC interrupts sources to be enabled or disabled. + * This parameter can be any combination of the following values: + * @arg RTC_IT_OW: Overflow interrupt + * @arg RTC_IT_ALR: Alarm interrupt + * @arg RTC_IT_SEC: Second interrupt + * @param NewState: new state of the specified RTC interrupts. + * This parameter can be: ENABLE or DISABLE. + * @retval None + */ +void RTC_ITConfig(uint16_t RTC_IT, FunctionalState NewState) +{ + /* Check the parameters */ + assert_param(IS_RTC_IT(RTC_IT)); + assert_param(IS_FUNCTIONAL_STATE(NewState)); + + if (NewState != DISABLE) + { + RTC->CRH |= RTC_IT; + } + else + { + RTC->CRH &= (uint16_t)~RTC_IT; + } +} + +/** + * @brief Enters the RTC configuration mode. + * @param None + * @retval None + */ +void RTC_EnterConfigMode(void) +{ + /* Set the CNF flag to enter in the Configuration Mode */ + RTC->CRL |= RTC_CRL_CNF; +} + +/** + * @brief Exits from the RTC configuration mode. + * @param None + * @retval None + */ +void RTC_ExitConfigMode(void) +{ + /* Reset the CNF flag to exit from the Configuration Mode */ + RTC->CRL &= (uint16_t)~((uint16_t)RTC_CRL_CNF); +} + +/** + * @brief Gets the RTC counter value. + * @param None + * @retval RTC counter value. + */ +uint32_t RTC_GetCounter(void) +{ + uint16_t high1 = 0, high2 = 0, low = 0; + + high1 = RTC->CNTH; + low = RTC->CNTL; + high2 = RTC->CNTH; + + if (high1 != high2) + { /* In this case the counter roll over during reading of CNTL and CNTH registers, + read again CNTL register then return the counter value */ + return (((uint32_t) high2 << 16 ) | RTC->CNTL); + } + else + { /* No counter roll over during reading of CNTL and CNTH registers, counter + value is equal to first value of CNTL and CNTH */ + return (((uint32_t) high1 << 16 ) | low); + } +} + +/** + * @brief Sets the RTC counter value. + * @param CounterValue: RTC counter new value. + * @retval None + */ +void RTC_SetCounter(uint32_t CounterValue) +{ + RTC_EnterConfigMode(); + /* Set RTC COUNTER MSB word */ + RTC->CNTH = CounterValue >> 16; + /* Set RTC COUNTER LSB word */ + RTC->CNTL = (CounterValue & RTC_LSB_MASK); + RTC_ExitConfigMode(); +} + +/** + * @brief Sets the RTC prescaler value. + * @param PrescalerValue: RTC prescaler new value. + * @retval None + */ +void RTC_SetPrescaler(uint32_t PrescalerValue) +{ + /* Check the parameters */ + assert_param(IS_RTC_PRESCALER(PrescalerValue)); + + RTC_EnterConfigMode(); + /* Set RTC PRESCALER MSB word */ + RTC->PRLH = (PrescalerValue & PRLH_MSB_MASK) >> 16; + /* Set RTC PRESCALER LSB word */ + RTC->PRLL = (PrescalerValue & RTC_LSB_MASK); + RTC_ExitConfigMode(); +} + +/** + * @brief Sets the RTC alarm value. + * @param AlarmValue: RTC alarm new value. + * @retval None + */ +void RTC_SetAlarm(uint32_t AlarmValue) +{ + RTC_EnterConfigMode(); + /* Set the ALARM MSB word */ + RTC->ALRH = AlarmValue >> 16; + /* Set the ALARM LSB word */ + RTC->ALRL = (AlarmValue & RTC_LSB_MASK); + RTC_ExitConfigMode(); +} + +/** + * @brief Gets the RTC divider value. + * @param None + * @retval RTC Divider value. + */ +uint32_t RTC_GetDivider(void) +{ + uint32_t tmp = 0x00; + tmp = ((uint32_t)RTC->DIVH & (uint32_t)0x000F) << 16; + tmp |= RTC->DIVL; + return tmp; +} + +/** + * @brief Waits until last write operation on RTC registers has finished. + * @note This function must be called before any write to RTC registers. + * @param None + * @retval None + */ +void RTC_WaitForLastTask(void) +{ + /* Loop until RTOFF flag is set */ + while ((RTC->CRL & RTC_FLAG_RTOFF) == (uint16_t)RESET) + { + } +} + +/** + * @brief Waits until the RTC registers (RTC_CNT, RTC_ALR and RTC_PRL) + * are synchronized with RTC APB clock. + * @note This function must be called before any read operation after an APB reset + * or an APB clock stop. + * @param None + * @retval None + */ +void RTC_WaitForSynchro(void) +{ + /* Clear RSF flag */ + RTC->CRL &= (uint16_t)~RTC_FLAG_RSF; + /* Loop until RSF flag is set */ + while ((RTC->CRL & RTC_FLAG_RSF) == (uint16_t)RESET) + { + } +} + +/** + * @brief Checks whether the specified RTC flag is set or not. + * @param RTC_FLAG: specifies the flag to check. + * This parameter can be one the following values: + * @arg RTC_FLAG_RTOFF: RTC Operation OFF flag + * @arg RTC_FLAG_RSF: Registers Synchronized flag + * @arg RTC_FLAG_OW: Overflow flag + * @arg RTC_FLAG_ALR: Alarm flag + * @arg RTC_FLAG_SEC: Second flag + * @retval The new state of RTC_FLAG (SET or RESET). + */ +FlagStatus RTC_GetFlagStatus(uint16_t RTC_FLAG) +{ + FlagStatus bitstatus = RESET; + + /* Check the parameters */ + assert_param(IS_RTC_GET_FLAG(RTC_FLAG)); + + if ((RTC->CRL & RTC_FLAG) != (uint16_t)RESET) + { + bitstatus = SET; + } + else + { + bitstatus = RESET; + } + return bitstatus; +} + +/** + * @brief Clears the RTC's pending flags. + * @param RTC_FLAG: specifies the flag to clear. + * This parameter can be any combination of the following values: + * @arg RTC_FLAG_RSF: Registers Synchronized flag. This flag is cleared only after + * an APB reset or an APB Clock stop. + * @arg RTC_FLAG_OW: Overflow flag + * @arg RTC_FLAG_ALR: Alarm flag + * @arg RTC_FLAG_SEC: Second flag + * @retval None + */ +void RTC_ClearFlag(uint16_t RTC_FLAG) +{ + /* Check the parameters */ + assert_param(IS_RTC_CLEAR_FLAG(RTC_FLAG)); + + /* Clear the corresponding RTC flag */ + RTC->CRL &= (uint16_t)~RTC_FLAG; +} + +/** + * @brief Checks whether the specified RTC interrupt has occurred or not. + * @param RTC_IT: specifies the RTC interrupts sources to check. + * This parameter can be one of the following values: + * @arg RTC_IT_OW: Overflow interrupt + * @arg RTC_IT_ALR: Alarm interrupt + * @arg RTC_IT_SEC: Second interrupt + * @retval The new state of the RTC_IT (SET or RESET). + */ +ITStatus RTC_GetITStatus(uint16_t RTC_IT) +{ + ITStatus bitstatus = RESET; + /* Check the parameters */ + assert_param(IS_RTC_GET_IT(RTC_IT)); + + bitstatus = (ITStatus)(RTC->CRL & RTC_IT); + if (((RTC->CRH & RTC_IT) != (uint16_t)RESET) && (bitstatus != (uint16_t)RESET)) + { + bitstatus = SET; + } + else + { + bitstatus = RESET; + } + return bitstatus; +} + +/** + * @brief Clears the RTC's interrupt pending bits. + * @param RTC_IT: specifies the interrupt pending bit to clear. + * This parameter can be any combination of the following values: + * @arg RTC_IT_OW: Overflow interrupt + * @arg RTC_IT_ALR: Alarm interrupt + * @arg RTC_IT_SEC: Second interrupt + * @retval None + */ +void RTC_ClearITPendingBit(uint16_t RTC_IT) +{ + /* Check the parameters */ + assert_param(IS_RTC_IT(RTC_IT)); + + /* Clear the corresponding RTC pending bit */ + RTC->CRL &= (uint16_t)~RTC_IT; +} + +/** + * @} + */ + +/** + * @} + */ + +/** + * @} + */ + +/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ diff --git a/Libraries/STM32F10x_StdPeriph_Driver/src/stm32f10x_sdio.c b/Libraries/STM32F10x_StdPeriph_Driver/src/stm32f10x_sdio.c new file mode 100644 index 0000000..ec5bf10 --- /dev/null +++ b/Libraries/STM32F10x_StdPeriph_Driver/src/stm32f10x_sdio.c @@ -0,0 +1,804 @@ +/** + ****************************************************************************** + * @file stm32f10x_sdio.c + * @author MCD Application Team + * @version V3.6.1 + * @date 05-March-2012 + * @brief This file provides all the SDIO firmware functions. + ****************************************************************************** + * @attention + * + *

    © COPYRIGHT 2012 STMicroelectronics

    + * + * Licensed under MCD-ST Liberty SW License Agreement V2, (the "License"); + * You may not use this file except in compliance with the License. + * You may obtain a copy of the License at: + * + * http://www.st.com/software_license_agreement_liberty_v2 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, + * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + * + ****************************************************************************** + */ + +/* Includes ------------------------------------------------------------------*/ +#include "stm32f10x_sdio.h" +#include "stm32f10x_rcc.h" + +/** @addtogroup STM32F10x_StdPeriph_Driver + * @{ + */ + +/** @defgroup SDIO + * @brief SDIO driver modules + * @{ + */ + +/** @defgroup SDIO_Private_TypesDefinitions + * @{ + */ + +/* ------------ SDIO registers bit address in the alias region ----------- */ +#define SDIO_OFFSET (SDIO_BASE - PERIPH_BASE) + +/* --- CLKCR Register ---*/ + +/* Alias word address of CLKEN bit */ +#define CLKCR_OFFSET (SDIO_OFFSET + 0x04) +#define CLKEN_BitNumber 0x08 +#define CLKCR_CLKEN_BB (PERIPH_BB_BASE + (CLKCR_OFFSET * 32) + (CLKEN_BitNumber * 4)) + +/* --- CMD Register ---*/ + +/* Alias word address of SDIOSUSPEND bit */ +#define CMD_OFFSET (SDIO_OFFSET + 0x0C) +#define SDIOSUSPEND_BitNumber 0x0B +#define CMD_SDIOSUSPEND_BB (PERIPH_BB_BASE + (CMD_OFFSET * 32) + (SDIOSUSPEND_BitNumber * 4)) + +/* Alias word address of ENCMDCOMPL bit */ +#define ENCMDCOMPL_BitNumber 0x0C +#define CMD_ENCMDCOMPL_BB (PERIPH_BB_BASE + (CMD_OFFSET * 32) + (ENCMDCOMPL_BitNumber * 4)) + +/* Alias word address of NIEN bit */ +#define NIEN_BitNumber 0x0D +#define CMD_NIEN_BB (PERIPH_BB_BASE + (CMD_OFFSET * 32) + (NIEN_BitNumber * 4)) + +/* Alias word address of ATACMD bit */ +#define ATACMD_BitNumber 0x0E +#define CMD_ATACMD_BB (PERIPH_BB_BASE + (CMD_OFFSET * 32) + (ATACMD_BitNumber * 4)) + +/* --- DCTRL Register ---*/ + +/* Alias word address of DMAEN bit */ +#define DCTRL_OFFSET (SDIO_OFFSET + 0x2C) +#define DMAEN_BitNumber 0x03 +#define DCTRL_DMAEN_BB (PERIPH_BB_BASE + (DCTRL_OFFSET * 32) + (DMAEN_BitNumber * 4)) + +/* Alias word address of RWSTART bit */ +#define RWSTART_BitNumber 0x08 +#define DCTRL_RWSTART_BB (PERIPH_BB_BASE + (DCTRL_OFFSET * 32) + (RWSTART_BitNumber * 4)) + +/* Alias word address of RWSTOP bit */ +#define RWSTOP_BitNumber 0x09 +#define DCTRL_RWSTOP_BB (PERIPH_BB_BASE + (DCTRL_OFFSET * 32) + (RWSTOP_BitNumber * 4)) + +/* Alias word address of RWMOD bit */ +#define RWMOD_BitNumber 0x0A +#define DCTRL_RWMOD_BB (PERIPH_BB_BASE + (DCTRL_OFFSET * 32) + (RWMOD_BitNumber * 4)) + +/* Alias word address of SDIOEN bit */ +#define SDIOEN_BitNumber 0x0B +#define DCTRL_SDIOEN_BB (PERIPH_BB_BASE + (DCTRL_OFFSET * 32) + (SDIOEN_BitNumber * 4)) + +/* ---------------------- SDIO registers bit mask ------------------------ */ + +/* --- CLKCR Register ---*/ + +/* CLKCR register clear mask */ +#define CLKCR_CLEAR_MASK ((uint32_t)0xFFFF8100) + +/* --- PWRCTRL Register ---*/ + +/* SDIO PWRCTRL Mask */ +#define PWR_PWRCTRL_MASK ((uint32_t)0xFFFFFFFC) + +/* --- DCTRL Register ---*/ + +/* SDIO DCTRL Clear Mask */ +#define DCTRL_CLEAR_MASK ((uint32_t)0xFFFFFF08) + +/* --- CMD Register ---*/ + +/* CMD Register clear mask */ +#define CMD_CLEAR_MASK ((uint32_t)0xFFFFF800) + +/* SDIO RESP Registers Address */ +#define SDIO_RESP_ADDR ((uint32_t)(SDIO_BASE + 0x14)) + +/** + * @} + */ + +/** @defgroup SDIO_Private_Defines + * @{ + */ + +/** + * @} + */ + +/** @defgroup SDIO_Private_Macros + * @{ + */ + +/** + * @} + */ + +/** @defgroup SDIO_Private_Variables + * @{ + */ + +/** + * @} + */ + +/** @defgroup SDIO_Private_FunctionPrototypes + * @{ + */ + +/** + * @} + */ + +/** @defgroup SDIO_Private_Functions + * @{ + */ + +/** + * @brief Deinitializes the SDIO peripheral registers to their default reset values. + * @param None + * @retval None + */ +void SDIO_DeInit(void) +{ + SDIO->POWER = 0x00000000; + SDIO->CLKCR = 0x00000000; + SDIO->ARG = 0x00000000; + SDIO->CMD = 0x00000000; + SDIO->DTIMER = 0x00000000; + SDIO->DLEN = 0x00000000; + SDIO->DCTRL = 0x00000000; + SDIO->ICR = 0x00C007FF; + SDIO->MASK = 0x00000000; +} + +/** + * @brief Initializes the SDIO peripheral according to the specified + * parameters in the SDIO_InitStruct. + * @param SDIO_InitStruct : pointer to a SDIO_InitTypeDef structure + * that contains the configuration information for the SDIO peripheral. + * @retval None + */ +void SDIO_Init(SDIO_InitTypeDef* SDIO_InitStruct) +{ + uint32_t tmpreg = 0; + + /* Check the parameters */ + assert_param(IS_SDIO_CLOCK_EDGE(SDIO_InitStruct->SDIO_ClockEdge)); + assert_param(IS_SDIO_CLOCK_BYPASS(SDIO_InitStruct->SDIO_ClockBypass)); + assert_param(IS_SDIO_CLOCK_POWER_SAVE(SDIO_InitStruct->SDIO_ClockPowerSave)); + assert_param(IS_SDIO_BUS_WIDE(SDIO_InitStruct->SDIO_BusWide)); + assert_param(IS_SDIO_HARDWARE_FLOW_CONTROL(SDIO_InitStruct->SDIO_HardwareFlowControl)); + +/*---------------------------- SDIO CLKCR Configuration ------------------------*/ + /* Get the SDIO CLKCR value */ + tmpreg = SDIO->CLKCR; + + /* Clear CLKDIV, PWRSAV, BYPASS, WIDBUS, NEGEDGE, HWFC_EN bits */ + tmpreg &= CLKCR_CLEAR_MASK; + + /* Set CLKDIV bits according to SDIO_ClockDiv value */ + /* Set PWRSAV bit according to SDIO_ClockPowerSave value */ + /* Set BYPASS bit according to SDIO_ClockBypass value */ + /* Set WIDBUS bits according to SDIO_BusWide value */ + /* Set NEGEDGE bits according to SDIO_ClockEdge value */ + /* Set HWFC_EN bits according to SDIO_HardwareFlowControl value */ + tmpreg |= (SDIO_InitStruct->SDIO_ClockDiv | SDIO_InitStruct->SDIO_ClockPowerSave | + SDIO_InitStruct->SDIO_ClockBypass | SDIO_InitStruct->SDIO_BusWide | + SDIO_InitStruct->SDIO_ClockEdge | SDIO_InitStruct->SDIO_HardwareFlowControl); + + /* Write to SDIO CLKCR */ + SDIO->CLKCR = tmpreg; +} + +/** + * @brief Fills each SDIO_InitStruct member with its default value. + * @param SDIO_InitStruct: pointer to an SDIO_InitTypeDef structure which + * will be initialized. + * @retval None + */ +void SDIO_StructInit(SDIO_InitTypeDef* SDIO_InitStruct) +{ + /* SDIO_InitStruct members default value */ + SDIO_InitStruct->SDIO_ClockDiv = 0x00; + SDIO_InitStruct->SDIO_ClockEdge = SDIO_ClockEdge_Rising; + SDIO_InitStruct->SDIO_ClockBypass = SDIO_ClockBypass_Disable; + SDIO_InitStruct->SDIO_ClockPowerSave = SDIO_ClockPowerSave_Disable; + SDIO_InitStruct->SDIO_BusWide = SDIO_BusWide_1b; + SDIO_InitStruct->SDIO_HardwareFlowControl = SDIO_HardwareFlowControl_Disable; +} + +/** + * @brief Enables or disables the SDIO Clock. + * @param NewState: new state of the SDIO Clock. This parameter can be: ENABLE or DISABLE. + * @retval None + */ +void SDIO_ClockCmd(FunctionalState NewState) +{ + /* Check the parameters */ + assert_param(IS_FUNCTIONAL_STATE(NewState)); + + *(__IO uint32_t *) CLKCR_CLKEN_BB = (uint32_t)NewState; +} + +/** + * @brief Sets the power status of the controller. + * @param SDIO_PowerState: new state of the Power state. + * This parameter can be one of the following values: + * @arg SDIO_PowerState_OFF + * @arg SDIO_PowerState_ON + * @retval None + */ +void SDIO_SetPowerState(uint32_t SDIO_PowerState) +{ + /* Check the parameters */ + assert_param(IS_SDIO_POWER_STATE(SDIO_PowerState)); + + SDIO->POWER = SDIO_PowerState; +} + +/** + * @brief Gets the power status of the controller. + * @param None + * @retval Power status of the controller. The returned value can + * be one of the following: + * - 0x00: Power OFF + * - 0x02: Power UP + * - 0x03: Power ON + */ +uint32_t SDIO_GetPowerState(void) +{ + return (SDIO->POWER & (~PWR_PWRCTRL_MASK)); +} + +/** + * @brief Enables or disables the SDIO interrupts. + * @param SDIO_IT: specifies the SDIO interrupt sources to be enabled or disabled. + * This parameter can be one or a combination of the following values: + * @arg SDIO_IT_CCRCFAIL: Command response received (CRC check failed) interrupt + * @arg SDIO_IT_DCRCFAIL: Data block sent/received (CRC check failed) interrupt + * @arg SDIO_IT_CTIMEOUT: Command response timeout interrupt + * @arg SDIO_IT_DTIMEOUT: Data timeout interrupt + * @arg SDIO_IT_TXUNDERR: Transmit FIFO underrun error interrupt + * @arg SDIO_IT_RXOVERR: Received FIFO overrun error interrupt + * @arg SDIO_IT_CMDREND: Command response received (CRC check passed) interrupt + * @arg SDIO_IT_CMDSENT: Command sent (no response required) interrupt + * @arg SDIO_IT_DATAEND: Data end (data counter, SDIDCOUNT, is zero) interrupt + * @arg SDIO_IT_STBITERR: Start bit not detected on all data signals in wide + * bus mode interrupt + * @arg SDIO_IT_DBCKEND: Data block sent/received (CRC check passed) interrupt + * @arg SDIO_IT_CMDACT: Command transfer in progress interrupt + * @arg SDIO_IT_TXACT: Data transmit in progress interrupt + * @arg SDIO_IT_RXACT: Data receive in progress interrupt + * @arg SDIO_IT_TXFIFOHE: Transmit FIFO Half Empty interrupt + * @arg SDIO_IT_RXFIFOHF: Receive FIFO Half Full interrupt + * @arg SDIO_IT_TXFIFOF: Transmit FIFO full interrupt + * @arg SDIO_IT_RXFIFOF: Receive FIFO full interrupt + * @arg SDIO_IT_TXFIFOE: Transmit FIFO empty interrupt + * @arg SDIO_IT_RXFIFOE: Receive FIFO empty interrupt + * @arg SDIO_IT_TXDAVL: Data available in transmit FIFO interrupt + * @arg SDIO_IT_RXDAVL: Data available in receive FIFO interrupt + * @arg SDIO_IT_SDIOIT: SD I/O interrupt received interrupt + * @arg SDIO_IT_CEATAEND: CE-ATA command completion signal received for CMD61 interrupt + * @param NewState: new state of the specified SDIO interrupts. + * This parameter can be: ENABLE or DISABLE. + * @retval None + */ +void SDIO_ITConfig(uint32_t SDIO_IT, FunctionalState NewState) +{ + /* Check the parameters */ + assert_param(IS_SDIO_IT(SDIO_IT)); + assert_param(IS_FUNCTIONAL_STATE(NewState)); + + if (NewState != DISABLE) + { + /* Enable the SDIO interrupts */ + SDIO->MASK |= SDIO_IT; + } + else + { + /* Disable the SDIO interrupts */ + SDIO->MASK &= ~SDIO_IT; + } +} + +/** + * @brief Enables or disables the SDIO DMA request. + * @param NewState: new state of the selected SDIO DMA request. + * This parameter can be: ENABLE or DISABLE. + * @retval None + */ +void SDIO_DMACmd(FunctionalState NewState) +{ + /* Check the parameters */ + assert_param(IS_FUNCTIONAL_STATE(NewState)); + + *(__IO uint32_t *) DCTRL_DMAEN_BB = (uint32_t)NewState; +} + +/** + * @brief Initializes the SDIO Command according to the specified + * parameters in the SDIO_CmdInitStruct and send the command. + * @param SDIO_CmdInitStruct : pointer to a SDIO_CmdInitTypeDef + * structure that contains the configuration information for the SDIO command. + * @retval None + */ +void SDIO_SendCommand(SDIO_CmdInitTypeDef *SDIO_CmdInitStruct) +{ + uint32_t tmpreg = 0; + + /* Check the parameters */ + assert_param(IS_SDIO_CMD_INDEX(SDIO_CmdInitStruct->SDIO_CmdIndex)); + assert_param(IS_SDIO_RESPONSE(SDIO_CmdInitStruct->SDIO_Response)); + assert_param(IS_SDIO_WAIT(SDIO_CmdInitStruct->SDIO_Wait)); + assert_param(IS_SDIO_CPSM(SDIO_CmdInitStruct->SDIO_CPSM)); + +/*---------------------------- SDIO ARG Configuration ------------------------*/ + /* Set the SDIO Argument value */ + SDIO->ARG = SDIO_CmdInitStruct->SDIO_Argument; + +/*---------------------------- SDIO CMD Configuration ------------------------*/ + /* Get the SDIO CMD value */ + tmpreg = SDIO->CMD; + /* Clear CMDINDEX, WAITRESP, WAITINT, WAITPEND, CPSMEN bits */ + tmpreg &= CMD_CLEAR_MASK; + /* Set CMDINDEX bits according to SDIO_CmdIndex value */ + /* Set WAITRESP bits according to SDIO_Response value */ + /* Set WAITINT and WAITPEND bits according to SDIO_Wait value */ + /* Set CPSMEN bits according to SDIO_CPSM value */ + tmpreg |= (uint32_t)SDIO_CmdInitStruct->SDIO_CmdIndex | SDIO_CmdInitStruct->SDIO_Response + | SDIO_CmdInitStruct->SDIO_Wait | SDIO_CmdInitStruct->SDIO_CPSM; + + /* Write to SDIO CMD */ + SDIO->CMD = tmpreg; +} + +/** + * @brief Fills each SDIO_CmdInitStruct member with its default value. + * @param SDIO_CmdInitStruct: pointer to an SDIO_CmdInitTypeDef + * structure which will be initialized. + * @retval None + */ +void SDIO_CmdStructInit(SDIO_CmdInitTypeDef* SDIO_CmdInitStruct) +{ + /* SDIO_CmdInitStruct members default value */ + SDIO_CmdInitStruct->SDIO_Argument = 0x00; + SDIO_CmdInitStruct->SDIO_CmdIndex = 0x00; + SDIO_CmdInitStruct->SDIO_Response = SDIO_Response_No; + SDIO_CmdInitStruct->SDIO_Wait = SDIO_Wait_No; + SDIO_CmdInitStruct->SDIO_CPSM = SDIO_CPSM_Disable; +} + +/** + * @brief Returns command index of last command for which response received. + * @param None + * @retval Returns the command index of the last command response received. + */ +uint8_t SDIO_GetCommandResponse(void) +{ + return (uint8_t)(SDIO->RESPCMD); +} + +/** + * @brief Returns response received from the card for the last command. + * @param SDIO_RESP: Specifies the SDIO response register. + * This parameter can be one of the following values: + * @arg SDIO_RESP1: Response Register 1 + * @arg SDIO_RESP2: Response Register 2 + * @arg SDIO_RESP3: Response Register 3 + * @arg SDIO_RESP4: Response Register 4 + * @retval The Corresponding response register value. + */ +uint32_t SDIO_GetResponse(uint32_t SDIO_RESP) +{ + __IO uint32_t tmp = 0; + + /* Check the parameters */ + assert_param(IS_SDIO_RESP(SDIO_RESP)); + + tmp = SDIO_RESP_ADDR + SDIO_RESP; + + return (*(__IO uint32_t *) tmp); +} + +/** + * @brief Initializes the SDIO data path according to the specified + * parameters in the SDIO_DataInitStruct. + * @param SDIO_DataInitStruct : pointer to a SDIO_DataInitTypeDef structure that + * contains the configuration information for the SDIO command. + * @retval None + */ +void SDIO_DataConfig(SDIO_DataInitTypeDef* SDIO_DataInitStruct) +{ + uint32_t tmpreg = 0; + + /* Check the parameters */ + assert_param(IS_SDIO_DATA_LENGTH(SDIO_DataInitStruct->SDIO_DataLength)); + assert_param(IS_SDIO_BLOCK_SIZE(SDIO_DataInitStruct->SDIO_DataBlockSize)); + assert_param(IS_SDIO_TRANSFER_DIR(SDIO_DataInitStruct->SDIO_TransferDir)); + assert_param(IS_SDIO_TRANSFER_MODE(SDIO_DataInitStruct->SDIO_TransferMode)); + assert_param(IS_SDIO_DPSM(SDIO_DataInitStruct->SDIO_DPSM)); + +/*---------------------------- SDIO DTIMER Configuration ---------------------*/ + /* Set the SDIO Data TimeOut value */ + SDIO->DTIMER = SDIO_DataInitStruct->SDIO_DataTimeOut; + +/*---------------------------- SDIO DLEN Configuration -----------------------*/ + /* Set the SDIO DataLength value */ + SDIO->DLEN = SDIO_DataInitStruct->SDIO_DataLength; + +/*---------------------------- SDIO DCTRL Configuration ----------------------*/ + /* Get the SDIO DCTRL value */ + tmpreg = SDIO->DCTRL; + /* Clear DEN, DTMODE, DTDIR and DBCKSIZE bits */ + tmpreg &= DCTRL_CLEAR_MASK; + /* Set DEN bit according to SDIO_DPSM value */ + /* Set DTMODE bit according to SDIO_TransferMode value */ + /* Set DTDIR bit according to SDIO_TransferDir value */ + /* Set DBCKSIZE bits according to SDIO_DataBlockSize value */ + tmpreg |= (uint32_t)SDIO_DataInitStruct->SDIO_DataBlockSize | SDIO_DataInitStruct->SDIO_TransferDir + | SDIO_DataInitStruct->SDIO_TransferMode | SDIO_DataInitStruct->SDIO_DPSM; + + /* Write to SDIO DCTRL */ + SDIO->DCTRL = tmpreg; +} + +/** + * @brief Fills each SDIO_DataInitStruct member with its default value. + * @param SDIO_DataInitStruct: pointer to an SDIO_DataInitTypeDef structure which + * will be initialized. + * @retval None + */ +void SDIO_DataStructInit(SDIO_DataInitTypeDef* SDIO_DataInitStruct) +{ + /* SDIO_DataInitStruct members default value */ + SDIO_DataInitStruct->SDIO_DataTimeOut = 0xFFFFFFFF; + SDIO_DataInitStruct->SDIO_DataLength = 0x00; + SDIO_DataInitStruct->SDIO_DataBlockSize = SDIO_DataBlockSize_1b; + SDIO_DataInitStruct->SDIO_TransferDir = SDIO_TransferDir_ToCard; + SDIO_DataInitStruct->SDIO_TransferMode = SDIO_TransferMode_Block; + SDIO_DataInitStruct->SDIO_DPSM = SDIO_DPSM_Disable; +} + +/** + * @brief Returns number of remaining data bytes to be transferred. + * @param None + * @retval Number of remaining data bytes to be transferred + */ +uint32_t SDIO_GetDataCounter(void) +{ + return SDIO->DCOUNT; +} + +/** + * @brief Read one data word from Rx FIFO. + * @param None + * @retval Data received + */ +uint32_t SDIO_ReadData(void) +{ + return SDIO->FIFO; +} + +/** + * @brief Write one data word to Tx FIFO. + * @param Data: 32-bit data word to write. + * @retval None + */ +void SDIO_WriteData(uint32_t Data) +{ + SDIO->FIFO = Data; +} + +/** + * @brief Returns the number of words left to be written to or read from FIFO. + * @param None + * @retval Remaining number of words. + */ +uint32_t SDIO_GetFIFOCount(void) +{ + return SDIO->FIFOCNT; +} + +/** + * @brief Starts the SD I/O Read Wait operation. + * @param NewState: new state of the Start SDIO Read Wait operation. + * This parameter can be: ENABLE or DISABLE. + * @retval None + */ +void SDIO_StartSDIOReadWait(FunctionalState NewState) +{ + /* Check the parameters */ + assert_param(IS_FUNCTIONAL_STATE(NewState)); + + *(__IO uint32_t *) DCTRL_RWSTART_BB = (uint32_t) NewState; +} + +/** + * @brief Stops the SD I/O Read Wait operation. + * @param NewState: new state of the Stop SDIO Read Wait operation. + * This parameter can be: ENABLE or DISABLE. + * @retval None + */ +void SDIO_StopSDIOReadWait(FunctionalState NewState) +{ + /* Check the parameters */ + assert_param(IS_FUNCTIONAL_STATE(NewState)); + + *(__IO uint32_t *) DCTRL_RWSTOP_BB = (uint32_t) NewState; +} + +/** + * @brief Sets one of the two options of inserting read wait interval. + * @param SDIO_ReadWaitMode: SD I/O Read Wait operation mode. + * This parameter can be: + * @arg SDIO_ReadWaitMode_CLK: Read Wait control by stopping SDIOCLK + * @arg SDIO_ReadWaitMode_DATA2: Read Wait control using SDIO_DATA2 + * @retval None + */ +void SDIO_SetSDIOReadWaitMode(uint32_t SDIO_ReadWaitMode) +{ + /* Check the parameters */ + assert_param(IS_SDIO_READWAIT_MODE(SDIO_ReadWaitMode)); + + *(__IO uint32_t *) DCTRL_RWMOD_BB = SDIO_ReadWaitMode; +} + +/** + * @brief Enables or disables the SD I/O Mode Operation. + * @param NewState: new state of SDIO specific operation. + * This parameter can be: ENABLE or DISABLE. + * @retval None + */ +void SDIO_SetSDIOOperation(FunctionalState NewState) +{ + /* Check the parameters */ + assert_param(IS_FUNCTIONAL_STATE(NewState)); + + *(__IO uint32_t *) DCTRL_SDIOEN_BB = (uint32_t)NewState; +} + +/** + * @brief Enables or disables the SD I/O Mode suspend command sending. + * @param NewState: new state of the SD I/O Mode suspend command. + * This parameter can be: ENABLE or DISABLE. + * @retval None + */ +void SDIO_SendSDIOSuspendCmd(FunctionalState NewState) +{ + /* Check the parameters */ + assert_param(IS_FUNCTIONAL_STATE(NewState)); + + *(__IO uint32_t *) CMD_SDIOSUSPEND_BB = (uint32_t)NewState; +} + +/** + * @brief Enables or disables the command completion signal. + * @param NewState: new state of command completion signal. + * This parameter can be: ENABLE or DISABLE. + * @retval None + */ +void SDIO_CommandCompletionCmd(FunctionalState NewState) +{ + /* Check the parameters */ + assert_param(IS_FUNCTIONAL_STATE(NewState)); + + *(__IO uint32_t *) CMD_ENCMDCOMPL_BB = (uint32_t)NewState; +} + +/** + * @brief Enables or disables the CE-ATA interrupt. + * @param NewState: new state of CE-ATA interrupt. This parameter can be: ENABLE or DISABLE. + * @retval None + */ +void SDIO_CEATAITCmd(FunctionalState NewState) +{ + /* Check the parameters */ + assert_param(IS_FUNCTIONAL_STATE(NewState)); + + *(__IO uint32_t *) CMD_NIEN_BB = (uint32_t)((~((uint32_t)NewState)) & ((uint32_t)0x1)); +} + +/** + * @brief Sends CE-ATA command (CMD61). + * @param NewState: new state of CE-ATA command. This parameter can be: ENABLE or DISABLE. + * @retval None + */ +void SDIO_SendCEATACmd(FunctionalState NewState) +{ + /* Check the parameters */ + assert_param(IS_FUNCTIONAL_STATE(NewState)); + + *(__IO uint32_t *) CMD_ATACMD_BB = (uint32_t)NewState; +} + +/** + * @brief Checks whether the specified SDIO flag is set or not. + * @param SDIO_FLAG: specifies the flag to check. + * This parameter can be one of the following values: + * @arg SDIO_FLAG_CCRCFAIL: Command response received (CRC check failed) + * @arg SDIO_FLAG_DCRCFAIL: Data block sent/received (CRC check failed) + * @arg SDIO_FLAG_CTIMEOUT: Command response timeout + * @arg SDIO_FLAG_DTIMEOUT: Data timeout + * @arg SDIO_FLAG_TXUNDERR: Transmit FIFO underrun error + * @arg SDIO_FLAG_RXOVERR: Received FIFO overrun error + * @arg SDIO_FLAG_CMDREND: Command response received (CRC check passed) + * @arg SDIO_FLAG_CMDSENT: Command sent (no response required) + * @arg SDIO_FLAG_DATAEND: Data end (data counter, SDIDCOUNT, is zero) + * @arg SDIO_FLAG_STBITERR: Start bit not detected on all data signals in wide + * bus mode. + * @arg SDIO_FLAG_DBCKEND: Data block sent/received (CRC check passed) + * @arg SDIO_FLAG_CMDACT: Command transfer in progress + * @arg SDIO_FLAG_TXACT: Data transmit in progress + * @arg SDIO_FLAG_RXACT: Data receive in progress + * @arg SDIO_FLAG_TXFIFOHE: Transmit FIFO Half Empty + * @arg SDIO_FLAG_RXFIFOHF: Receive FIFO Half Full + * @arg SDIO_FLAG_TXFIFOF: Transmit FIFO full + * @arg SDIO_FLAG_RXFIFOF: Receive FIFO full + * @arg SDIO_FLAG_TXFIFOE: Transmit FIFO empty + * @arg SDIO_FLAG_RXFIFOE: Receive FIFO empty + * @arg SDIO_FLAG_TXDAVL: Data available in transmit FIFO + * @arg SDIO_FLAG_RXDAVL: Data available in receive FIFO + * @arg SDIO_FLAG_SDIOIT: SD I/O interrupt received + * @arg SDIO_FLAG_CEATAEND: CE-ATA command completion signal received for CMD61 + * @retval The new state of SDIO_FLAG (SET or RESET). + */ +FlagStatus SDIO_GetFlagStatus(uint32_t SDIO_FLAG) +{ + FlagStatus bitstatus = RESET; + + /* Check the parameters */ + assert_param(IS_SDIO_FLAG(SDIO_FLAG)); + + if ((SDIO->STA & SDIO_FLAG) != (uint32_t)RESET) + { + bitstatus = SET; + } + else + { + bitstatus = RESET; + } + return bitstatus; +} + +/** + * @brief Clears the SDIO's pending flags. + * @param SDIO_FLAG: specifies the flag to clear. + * This parameter can be one or a combination of the following values: + * @arg SDIO_FLAG_CCRCFAIL: Command response received (CRC check failed) + * @arg SDIO_FLAG_DCRCFAIL: Data block sent/received (CRC check failed) + * @arg SDIO_FLAG_CTIMEOUT: Command response timeout + * @arg SDIO_FLAG_DTIMEOUT: Data timeout + * @arg SDIO_FLAG_TXUNDERR: Transmit FIFO underrun error + * @arg SDIO_FLAG_RXOVERR: Received FIFO overrun error + * @arg SDIO_FLAG_CMDREND: Command response received (CRC check passed) + * @arg SDIO_FLAG_CMDSENT: Command sent (no response required) + * @arg SDIO_FLAG_DATAEND: Data end (data counter, SDIDCOUNT, is zero) + * @arg SDIO_FLAG_STBITERR: Start bit not detected on all data signals in wide + * bus mode + * @arg SDIO_FLAG_DBCKEND: Data block sent/received (CRC check passed) + * @arg SDIO_FLAG_SDIOIT: SD I/O interrupt received + * @arg SDIO_FLAG_CEATAEND: CE-ATA command completion signal received for CMD61 + * @retval None + */ +void SDIO_ClearFlag(uint32_t SDIO_FLAG) +{ + /* Check the parameters */ + assert_param(IS_SDIO_CLEAR_FLAG(SDIO_FLAG)); + + SDIO->ICR = SDIO_FLAG; +} + +/** + * @brief Checks whether the specified SDIO interrupt has occurred or not. + * @param SDIO_IT: specifies the SDIO interrupt source to check. + * This parameter can be one of the following values: + * @arg SDIO_IT_CCRCFAIL: Command response received (CRC check failed) interrupt + * @arg SDIO_IT_DCRCFAIL: Data block sent/received (CRC check failed) interrupt + * @arg SDIO_IT_CTIMEOUT: Command response timeout interrupt + * @arg SDIO_IT_DTIMEOUT: Data timeout interrupt + * @arg SDIO_IT_TXUNDERR: Transmit FIFO underrun error interrupt + * @arg SDIO_IT_RXOVERR: Received FIFO overrun error interrupt + * @arg SDIO_IT_CMDREND: Command response received (CRC check passed) interrupt + * @arg SDIO_IT_CMDSENT: Command sent (no response required) interrupt + * @arg SDIO_IT_DATAEND: Data end (data counter, SDIDCOUNT, is zero) interrupt + * @arg SDIO_IT_STBITERR: Start bit not detected on all data signals in wide + * bus mode interrupt + * @arg SDIO_IT_DBCKEND: Data block sent/received (CRC check passed) interrupt + * @arg SDIO_IT_CMDACT: Command transfer in progress interrupt + * @arg SDIO_IT_TXACT: Data transmit in progress interrupt + * @arg SDIO_IT_RXACT: Data receive in progress interrupt + * @arg SDIO_IT_TXFIFOHE: Transmit FIFO Half Empty interrupt + * @arg SDIO_IT_RXFIFOHF: Receive FIFO Half Full interrupt + * @arg SDIO_IT_TXFIFOF: Transmit FIFO full interrupt + * @arg SDIO_IT_RXFIFOF: Receive FIFO full interrupt + * @arg SDIO_IT_TXFIFOE: Transmit FIFO empty interrupt + * @arg SDIO_IT_RXFIFOE: Receive FIFO empty interrupt + * @arg SDIO_IT_TXDAVL: Data available in transmit FIFO interrupt + * @arg SDIO_IT_RXDAVL: Data available in receive FIFO interrupt + * @arg SDIO_IT_SDIOIT: SD I/O interrupt received interrupt + * @arg SDIO_IT_CEATAEND: CE-ATA command completion signal received for CMD61 interrupt + * @retval The new state of SDIO_IT (SET or RESET). + */ +ITStatus SDIO_GetITStatus(uint32_t SDIO_IT) +{ + ITStatus bitstatus = RESET; + + /* Check the parameters */ + assert_param(IS_SDIO_GET_IT(SDIO_IT)); + if ((SDIO->STA & SDIO_IT) != (uint32_t)RESET) + { + bitstatus = SET; + } + else + { + bitstatus = RESET; + } + return bitstatus; +} + +/** + * @brief Clears the SDIO's interrupt pending bits. + * @param SDIO_IT: specifies the interrupt pending bit to clear. + * This parameter can be one or a combination of the following values: + * @arg SDIO_IT_CCRCFAIL: Command response received (CRC check failed) interrupt + * @arg SDIO_IT_DCRCFAIL: Data block sent/received (CRC check failed) interrupt + * @arg SDIO_IT_CTIMEOUT: Command response timeout interrupt + * @arg SDIO_IT_DTIMEOUT: Data timeout interrupt + * @arg SDIO_IT_TXUNDERR: Transmit FIFO underrun error interrupt + * @arg SDIO_IT_RXOVERR: Received FIFO overrun error interrupt + * @arg SDIO_IT_CMDREND: Command response received (CRC check passed) interrupt + * @arg SDIO_IT_CMDSENT: Command sent (no response required) interrupt + * @arg SDIO_IT_DATAEND: Data end (data counter, SDIDCOUNT, is zero) interrupt + * @arg SDIO_IT_STBITERR: Start bit not detected on all data signals in wide + * bus mode interrupt + * @arg SDIO_IT_SDIOIT: SD I/O interrupt received interrupt + * @arg SDIO_IT_CEATAEND: CE-ATA command completion signal received for CMD61 + * @retval None + */ +void SDIO_ClearITPendingBit(uint32_t SDIO_IT) +{ + /* Check the parameters */ + assert_param(IS_SDIO_CLEAR_IT(SDIO_IT)); + + SDIO->ICR = SDIO_IT; +} + +/** + * @} + */ + +/** + * @} + */ + +/** + * @} + */ + +/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ diff --git a/Libraries/STM32F10x_StdPeriph_Driver/src/stm32f10x_spi.c b/Libraries/STM32F10x_StdPeriph_Driver/src/stm32f10x_spi.c new file mode 100644 index 0000000..b901d3f --- /dev/null +++ b/Libraries/STM32F10x_StdPeriph_Driver/src/stm32f10x_spi.c @@ -0,0 +1,914 @@ +/** + ****************************************************************************** + * @file stm32f10x_spi.c + * @author MCD Application Team + * @version V3.6.1 + * @date 05-March-2012 + * @brief This file provides all the SPI firmware functions. + ****************************************************************************** + * @attention + * + *

    © COPYRIGHT 2012 STMicroelectronics

    + * + * Licensed under MCD-ST Liberty SW License Agreement V2, (the "License"); + * You may not use this file except in compliance with the License. + * You may obtain a copy of the License at: + * + * http://www.st.com/software_license_agreement_liberty_v2 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, + * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + * + ****************************************************************************** + */ + +/* Includes ------------------------------------------------------------------*/ +#include "stm32f10x_spi.h" +#include "stm32f10x_rcc.h" + +/** @addtogroup STM32F10x_StdPeriph_Driver + * @{ + */ + +/** @defgroup SPI + * @brief SPI driver modules + * @{ + */ + +/** @defgroup SPI_Private_TypesDefinitions + * @{ + */ + +/** + * @} + */ + + +/** @defgroup SPI_Private_Defines + * @{ + */ + +/* SPI SPE mask */ +#define CR1_SPE_Set ((uint16_t)0x0040) +#define CR1_SPE_Reset ((uint16_t)0xFFBF) + +/* I2S I2SE mask */ +#define I2SCFGR_I2SE_Set ((uint16_t)0x0400) +#define I2SCFGR_I2SE_Reset ((uint16_t)0xFBFF) + +/* SPI CRCNext mask */ +#define CR1_CRCNext_Set ((uint16_t)0x1000) + +/* SPI CRCEN mask */ +#define CR1_CRCEN_Set ((uint16_t)0x2000) +#define CR1_CRCEN_Reset ((uint16_t)0xDFFF) + +/* SPI SSOE mask */ +#define CR2_SSOE_Set ((uint16_t)0x0004) +#define CR2_SSOE_Reset ((uint16_t)0xFFFB) + +/* SPI registers Masks */ +#define CR1_CLEAR_Mask ((uint16_t)0x3040) +#define I2SCFGR_CLEAR_Mask ((uint16_t)0xF040) + +/* SPI or I2S mode selection masks */ +#define SPI_Mode_Select ((uint16_t)0xF7FF) +#define I2S_Mode_Select ((uint16_t)0x0800) + +/* I2S clock source selection masks */ +#define I2S2_CLOCK_SRC ((uint32_t)(0x00020000)) +#define I2S3_CLOCK_SRC ((uint32_t)(0x00040000)) +#define I2S_MUL_MASK ((uint32_t)(0x0000F000)) +#define I2S_DIV_MASK ((uint32_t)(0x000000F0)) + +/** + * @} + */ + +/** @defgroup SPI_Private_Macros + * @{ + */ + +/** + * @} + */ + +/** @defgroup SPI_Private_Variables + * @{ + */ + +/** + * @} + */ + +/** @defgroup SPI_Private_FunctionPrototypes + * @{ + */ + +/** + * @} + */ + +/** @defgroup SPI_Private_Functions + * @{ + */ + +/** + * @brief Deinitializes the SPIx peripheral registers to their default + * reset values (Affects also the I2Ss). + * @param SPIx: where x can be 1, 2 or 3 to select the SPI peripheral. + * @retval None + */ +void SPI_I2S_DeInit(SPI_TypeDef* SPIx) +{ + /* Check the parameters */ + assert_param(IS_SPI_ALL_PERIPH(SPIx)); + + if (SPIx == SPI1) + { + /* Enable SPI1 reset state */ + RCC_APB2PeriphResetCmd(RCC_APB2Periph_SPI1, ENABLE); + /* Release SPI1 from reset state */ + RCC_APB2PeriphResetCmd(RCC_APB2Periph_SPI1, DISABLE); + } + else if (SPIx == SPI2) + { + /* Enable SPI2 reset state */ + RCC_APB1PeriphResetCmd(RCC_APB1Periph_SPI2, ENABLE); + /* Release SPI2 from reset state */ + RCC_APB1PeriphResetCmd(RCC_APB1Periph_SPI2, DISABLE); + } + else + { + if (SPIx == SPI3) + { + /* Enable SPI3 reset state */ + RCC_APB1PeriphResetCmd(RCC_APB1Periph_SPI3, ENABLE); + /* Release SPI3 from reset state */ + RCC_APB1PeriphResetCmd(RCC_APB1Periph_SPI3, DISABLE); + } + } +} + +/** + * @brief Initializes the SPIx peripheral according to the specified + * parameters in the SPI_InitStruct. + * @param SPIx: where x can be 1, 2 or 3 to select the SPI peripheral. + * @param SPI_InitStruct: pointer to a SPI_InitTypeDef structure that + * contains the configuration information for the specified SPI peripheral. + * @retval None + */ +void SPI_Init(SPI_TypeDef* SPIx, SPI_InitTypeDef* SPI_InitStruct) +{ + uint16_t tmpreg = 0; + + /* check the parameters */ + assert_param(IS_SPI_ALL_PERIPH(SPIx)); + + /* Check the SPI parameters */ + assert_param(IS_SPI_DIRECTION_MODE(SPI_InitStruct->SPI_Direction)); + assert_param(IS_SPI_MODE(SPI_InitStruct->SPI_Mode)); + assert_param(IS_SPI_DATASIZE(SPI_InitStruct->SPI_DataSize)); + assert_param(IS_SPI_CPOL(SPI_InitStruct->SPI_CPOL)); + assert_param(IS_SPI_CPHA(SPI_InitStruct->SPI_CPHA)); + assert_param(IS_SPI_NSS(SPI_InitStruct->SPI_NSS)); + assert_param(IS_SPI_BAUDRATE_PRESCALER(SPI_InitStruct->SPI_BaudRatePrescaler)); + assert_param(IS_SPI_FIRST_BIT(SPI_InitStruct->SPI_FirstBit)); + assert_param(IS_SPI_CRC_POLYNOMIAL(SPI_InitStruct->SPI_CRCPolynomial)); + +/*---------------------------- SPIx CR1 Configuration ------------------------*/ + /* Get the SPIx CR1 value */ + tmpreg = SPIx->CR1; + /* Clear BIDIMode, BIDIOE, RxONLY, SSM, SSI, LSBFirst, BR, MSTR, CPOL and CPHA bits */ + tmpreg &= CR1_CLEAR_Mask; + /* Configure SPIx: direction, NSS management, first transmitted bit, BaudRate prescaler + master/salve mode, CPOL and CPHA */ + /* Set BIDImode, BIDIOE and RxONLY bits according to SPI_Direction value */ + /* Set SSM, SSI and MSTR bits according to SPI_Mode and SPI_NSS values */ + /* Set LSBFirst bit according to SPI_FirstBit value */ + /* Set BR bits according to SPI_BaudRatePrescaler value */ + /* Set CPOL bit according to SPI_CPOL value */ + /* Set CPHA bit according to SPI_CPHA value */ + tmpreg |= (uint16_t)((uint32_t)SPI_InitStruct->SPI_Direction | SPI_InitStruct->SPI_Mode | + SPI_InitStruct->SPI_DataSize | SPI_InitStruct->SPI_CPOL | + SPI_InitStruct->SPI_CPHA | SPI_InitStruct->SPI_NSS | + SPI_InitStruct->SPI_BaudRatePrescaler | SPI_InitStruct->SPI_FirstBit); + /* Write to SPIx CR1 */ + SPIx->CR1 = tmpreg; + + /* Activate the SPI mode (Reset I2SMOD bit in I2SCFGR register) */ + SPIx->I2SCFGR &= SPI_Mode_Select; + +/*---------------------------- SPIx CRCPOLY Configuration --------------------*/ + /* Write to SPIx CRCPOLY */ + SPIx->CRCPR = SPI_InitStruct->SPI_CRCPolynomial; +} + +/** + * @brief Initializes the SPIx peripheral according to the specified + * parameters in the I2S_InitStruct. + * @param SPIx: where x can be 2 or 3 to select the SPI peripheral + * (configured in I2S mode). + * @param I2S_InitStruct: pointer to an I2S_InitTypeDef structure that + * contains the configuration information for the specified SPI peripheral + * configured in I2S mode. + * @note + * The function calculates the optimal prescaler needed to obtain the most + * accurate audio frequency (depending on the I2S clock source, the PLL values + * and the product configuration). But in case the prescaler value is greater + * than 511, the default value (0x02) will be configured instead. * + * @retval None + */ +void I2S_Init(SPI_TypeDef* SPIx, I2S_InitTypeDef* I2S_InitStruct) +{ + uint16_t tmpreg = 0, i2sdiv = 2, i2sodd = 0, packetlength = 1; + uint32_t tmp = 0; + RCC_ClocksTypeDef RCC_Clocks; + uint32_t sourceclock = 0; + + /* Check the I2S parameters */ + assert_param(IS_SPI_23_PERIPH(SPIx)); + assert_param(IS_I2S_MODE(I2S_InitStruct->I2S_Mode)); + assert_param(IS_I2S_STANDARD(I2S_InitStruct->I2S_Standard)); + assert_param(IS_I2S_DATA_FORMAT(I2S_InitStruct->I2S_DataFormat)); + assert_param(IS_I2S_MCLK_OUTPUT(I2S_InitStruct->I2S_MCLKOutput)); + assert_param(IS_I2S_AUDIO_FREQ(I2S_InitStruct->I2S_AudioFreq)); + assert_param(IS_I2S_CPOL(I2S_InitStruct->I2S_CPOL)); + +/*----------------------- SPIx I2SCFGR & I2SPR Configuration -----------------*/ + /* Clear I2SMOD, I2SE, I2SCFG, PCMSYNC, I2SSTD, CKPOL, DATLEN and CHLEN bits */ + SPIx->I2SCFGR &= I2SCFGR_CLEAR_Mask; + SPIx->I2SPR = 0x0002; + + /* Get the I2SCFGR register value */ + tmpreg = SPIx->I2SCFGR; + + /* If the default value has to be written, reinitialize i2sdiv and i2sodd*/ + if(I2S_InitStruct->I2S_AudioFreq == I2S_AudioFreq_Default) + { + i2sodd = (uint16_t)0; + i2sdiv = (uint16_t)2; + } + /* If the requested audio frequency is not the default, compute the prescaler */ + else + { + /* Check the frame length (For the Prescaler computing) */ + if(I2S_InitStruct->I2S_DataFormat == I2S_DataFormat_16b) + { + /* Packet length is 16 bits */ + packetlength = 1; + } + else + { + /* Packet length is 32 bits */ + packetlength = 2; + } + + /* Get the I2S clock source mask depending on the peripheral number */ + if(((uint32_t)SPIx) == SPI2_BASE) + { + /* The mask is relative to I2S2 */ + tmp = I2S2_CLOCK_SRC; + } + else + { + /* The mask is relative to I2S3 */ + tmp = I2S3_CLOCK_SRC; + } + + /* Check the I2S clock source configuration depending on the Device: + Only Connectivity line devices have the PLL3 VCO clock */ +#ifdef STM32F10X_CL + if((RCC->CFGR2 & tmp) != 0) + { + /* Get the configuration bits of RCC PLL3 multiplier */ + tmp = (uint32_t)((RCC->CFGR2 & I2S_MUL_MASK) >> 12); + + /* Get the value of the PLL3 multiplier */ + if((tmp > 5) && (tmp < 15)) + { + /* Multiplier is between 8 and 14 (value 15 is forbidden) */ + tmp += 2; + } + else + { + if (tmp == 15) + { + /* Multiplier is 20 */ + tmp = 20; + } + } + /* Get the PREDIV2 value */ + sourceclock = (uint32_t)(((RCC->CFGR2 & I2S_DIV_MASK) >> 4) + 1); + + /* Calculate the Source Clock frequency based on PLL3 and PREDIV2 values */ + sourceclock = (uint32_t) ((HSE_Value / sourceclock) * tmp * 2); + } + else + { + /* I2S Clock source is System clock: Get System Clock frequency */ + RCC_GetClocksFreq(&RCC_Clocks); + + /* Get the source clock value: based on System Clock value */ + sourceclock = RCC_Clocks.SYSCLK_Frequency; + } +#else /* STM32F10X_HD */ + /* I2S Clock source is System clock: Get System Clock frequency */ + RCC_GetClocksFreq(&RCC_Clocks); + + /* Get the source clock value: based on System Clock value */ + sourceclock = RCC_Clocks.SYSCLK_Frequency; +#endif /* STM32F10X_CL */ + + /* Compute the Real divider depending on the MCLK output state with a floating point */ + if(I2S_InitStruct->I2S_MCLKOutput == I2S_MCLKOutput_Enable) + { + /* MCLK output is enabled */ + tmp = (uint16_t)(((((sourceclock / 256) * 10) / I2S_InitStruct->I2S_AudioFreq)) + 5); + } + else + { + /* MCLK output is disabled */ + tmp = (uint16_t)(((((sourceclock / (32 * packetlength)) *10 ) / I2S_InitStruct->I2S_AudioFreq)) + 5); + } + + /* Remove the floating point */ + tmp = tmp / 10; + + /* Check the parity of the divider */ + i2sodd = (uint16_t)(tmp & (uint16_t)0x0001); + + /* Compute the i2sdiv prescaler */ + i2sdiv = (uint16_t)((tmp - i2sodd) / 2); + + /* Get the Mask for the Odd bit (SPI_I2SPR[8]) register */ + i2sodd = (uint16_t) (i2sodd << 8); + } + + /* Test if the divider is 1 or 0 or greater than 0xFF */ + if ((i2sdiv < 2) || (i2sdiv > 0xFF)) + { + /* Set the default values */ + i2sdiv = 2; + i2sodd = 0; + } + + /* Write to SPIx I2SPR register the computed value */ + SPIx->I2SPR = (uint16_t)(i2sdiv | (uint16_t)(i2sodd | (uint16_t)I2S_InitStruct->I2S_MCLKOutput)); + + /* Configure the I2S with the SPI_InitStruct values */ + tmpreg |= (uint16_t)(I2S_Mode_Select | (uint16_t)(I2S_InitStruct->I2S_Mode | \ + (uint16_t)(I2S_InitStruct->I2S_Standard | (uint16_t)(I2S_InitStruct->I2S_DataFormat | \ + (uint16_t)I2S_InitStruct->I2S_CPOL)))); + + /* Write to SPIx I2SCFGR */ + SPIx->I2SCFGR = tmpreg; +} + +/** + * @brief Fills each SPI_InitStruct member with its default value. + * @param SPI_InitStruct : pointer to a SPI_InitTypeDef structure which will be initialized. + * @retval None + */ +void SPI_StructInit(SPI_InitTypeDef* SPI_InitStruct) +{ +/*--------------- Reset SPI init structure parameters values -----------------*/ + /* Initialize the SPI_Direction member */ + SPI_InitStruct->SPI_Direction = SPI_Direction_2Lines_FullDuplex; + /* initialize the SPI_Mode member */ + SPI_InitStruct->SPI_Mode = SPI_Mode_Slave; + /* initialize the SPI_DataSize member */ + SPI_InitStruct->SPI_DataSize = SPI_DataSize_8b; + /* Initialize the SPI_CPOL member */ + SPI_InitStruct->SPI_CPOL = SPI_CPOL_Low; + /* Initialize the SPI_CPHA member */ + SPI_InitStruct->SPI_CPHA = SPI_CPHA_1Edge; + /* Initialize the SPI_NSS member */ + SPI_InitStruct->SPI_NSS = SPI_NSS_Hard; + /* Initialize the SPI_BaudRatePrescaler member */ + SPI_InitStruct->SPI_BaudRatePrescaler = SPI_BaudRatePrescaler_2; + /* Initialize the SPI_FirstBit member */ + SPI_InitStruct->SPI_FirstBit = SPI_FirstBit_MSB; + /* Initialize the SPI_CRCPolynomial member */ + SPI_InitStruct->SPI_CRCPolynomial = 7; +} + +/** + * @brief Fills each I2S_InitStruct member with its default value. + * @param I2S_InitStruct : pointer to a I2S_InitTypeDef structure which will be initialized. + * @retval None + */ +void I2S_StructInit(I2S_InitTypeDef* I2S_InitStruct) +{ +/*--------------- Reset I2S init structure parameters values -----------------*/ + /* Initialize the I2S_Mode member */ + I2S_InitStruct->I2S_Mode = I2S_Mode_SlaveTx; + + /* Initialize the I2S_Standard member */ + I2S_InitStruct->I2S_Standard = I2S_Standard_Phillips; + + /* Initialize the I2S_DataFormat member */ + I2S_InitStruct->I2S_DataFormat = I2S_DataFormat_16b; + + /* Initialize the I2S_MCLKOutput member */ + I2S_InitStruct->I2S_MCLKOutput = I2S_MCLKOutput_Disable; + + /* Initialize the I2S_AudioFreq member */ + I2S_InitStruct->I2S_AudioFreq = I2S_AudioFreq_Default; + + /* Initialize the I2S_CPOL member */ + I2S_InitStruct->I2S_CPOL = I2S_CPOL_Low; +} + +/** + * @brief Enables or disables the specified SPI peripheral. + * @param SPIx: where x can be 1, 2 or 3 to select the SPI peripheral. + * @param NewState: new state of the SPIx peripheral. + * This parameter can be: ENABLE or DISABLE. + * @retval None + */ +void SPI_Cmd(SPI_TypeDef* SPIx, FunctionalState NewState) +{ + /* Check the parameters */ + assert_param(IS_SPI_ALL_PERIPH(SPIx)); + assert_param(IS_FUNCTIONAL_STATE(NewState)); + if (NewState != DISABLE) + { + /* Enable the selected SPI peripheral */ + SPIx->CR1 |= CR1_SPE_Set; + } + else + { + /* Disable the selected SPI peripheral */ + SPIx->CR1 &= CR1_SPE_Reset; + } +} + +/** + * @brief Enables or disables the specified SPI peripheral (in I2S mode). + * @param SPIx: where x can be 2 or 3 to select the SPI peripheral. + * @param NewState: new state of the SPIx peripheral. + * This parameter can be: ENABLE or DISABLE. + * @retval None + */ +void I2S_Cmd(SPI_TypeDef* SPIx, FunctionalState NewState) +{ + /* Check the parameters */ + assert_param(IS_SPI_23_PERIPH(SPIx)); + assert_param(IS_FUNCTIONAL_STATE(NewState)); + if (NewState != DISABLE) + { + /* Enable the selected SPI peripheral (in I2S mode) */ + SPIx->I2SCFGR |= I2SCFGR_I2SE_Set; + } + else + { + /* Disable the selected SPI peripheral (in I2S mode) */ + SPIx->I2SCFGR &= I2SCFGR_I2SE_Reset; + } +} + +/** + * @brief Enables or disables the specified SPI/I2S interrupts. + * @param SPIx: where x can be + * - 1, 2 or 3 in SPI mode + * - 2 or 3 in I2S mode + * @param SPI_I2S_IT: specifies the SPI/I2S interrupt source to be enabled or disabled. + * This parameter can be one of the following values: + * @arg SPI_I2S_IT_TXE: Tx buffer empty interrupt mask + * @arg SPI_I2S_IT_RXNE: Rx buffer not empty interrupt mask + * @arg SPI_I2S_IT_ERR: Error interrupt mask + * @param NewState: new state of the specified SPI/I2S interrupt. + * This parameter can be: ENABLE or DISABLE. + * @retval None + */ +void SPI_I2S_ITConfig(SPI_TypeDef* SPIx, uint8_t SPI_I2S_IT, FunctionalState NewState) +{ + uint16_t itpos = 0, itmask = 0 ; + /* Check the parameters */ + assert_param(IS_SPI_ALL_PERIPH(SPIx)); + assert_param(IS_FUNCTIONAL_STATE(NewState)); + assert_param(IS_SPI_I2S_CONFIG_IT(SPI_I2S_IT)); + + /* Get the SPI/I2S IT index */ + itpos = SPI_I2S_IT >> 4; + + /* Set the IT mask */ + itmask = (uint16_t)1 << (uint16_t)itpos; + + if (NewState != DISABLE) + { + /* Enable the selected SPI/I2S interrupt */ + SPIx->CR2 |= itmask; + } + else + { + /* Disable the selected SPI/I2S interrupt */ + SPIx->CR2 &= (uint16_t)~itmask; + } +} + +/** + * @brief Enables or disables the SPIx/I2Sx DMA interface. + * @param SPIx: where x can be + * - 1, 2 or 3 in SPI mode + * - 2 or 3 in I2S mode + * @param SPI_I2S_DMAReq: specifies the SPI/I2S DMA transfer request to be enabled or disabled. + * This parameter can be any combination of the following values: + * @arg SPI_I2S_DMAReq_Tx: Tx buffer DMA transfer request + * @arg SPI_I2S_DMAReq_Rx: Rx buffer DMA transfer request + * @param NewState: new state of the selected SPI/I2S DMA transfer request. + * This parameter can be: ENABLE or DISABLE. + * @retval None + */ +void SPI_I2S_DMACmd(SPI_TypeDef* SPIx, uint16_t SPI_I2S_DMAReq, FunctionalState NewState) +{ + /* Check the parameters */ + assert_param(IS_SPI_ALL_PERIPH(SPIx)); + assert_param(IS_FUNCTIONAL_STATE(NewState)); + assert_param(IS_SPI_I2S_DMAREQ(SPI_I2S_DMAReq)); + if (NewState != DISABLE) + { + /* Enable the selected SPI/I2S DMA requests */ + SPIx->CR2 |= SPI_I2S_DMAReq; + } + else + { + /* Disable the selected SPI/I2S DMA requests */ + SPIx->CR2 &= (uint16_t)~SPI_I2S_DMAReq; + } +} + +/** + * @brief Transmits a Data through the SPIx/I2Sx peripheral. + * @param SPIx: where x can be + * - 1, 2 or 3 in SPI mode + * - 2 or 3 in I2S mode + * @param Data : Data to be transmitted. + * @retval None + */ +void SPI_I2S_SendData(SPI_TypeDef* SPIx, uint16_t Data) +{ + /* Check the parameters */ + assert_param(IS_SPI_ALL_PERIPH(SPIx)); + + /* Write in the DR register the data to be sent */ + SPIx->DR = Data; +} + +/** + * @brief Returns the most recent received data by the SPIx/I2Sx peripheral. + * @param SPIx: where x can be + * - 1, 2 or 3 in SPI mode + * - 2 or 3 in I2S mode + * @retval The value of the received data. + */ +uint16_t SPI_I2S_ReceiveData(SPI_TypeDef* SPIx) +{ + /* Check the parameters */ + assert_param(IS_SPI_ALL_PERIPH(SPIx)); + + /* Return the data in the DR register */ + return SPIx->DR; +} + +/** + * @brief Configures internally by software the NSS pin for the selected SPI. + * @param SPIx: where x can be 1, 2 or 3 to select the SPI peripheral. + * @param SPI_NSSInternalSoft: specifies the SPI NSS internal state. + * This parameter can be one of the following values: + * @arg SPI_NSSInternalSoft_Set: Set NSS pin internally + * @arg SPI_NSSInternalSoft_Reset: Reset NSS pin internally + * @retval None + */ +void SPI_NSSInternalSoftwareConfig(SPI_TypeDef* SPIx, uint16_t SPI_NSSInternalSoft) +{ + /* Check the parameters */ + assert_param(IS_SPI_ALL_PERIPH(SPIx)); + assert_param(IS_SPI_NSS_INTERNAL(SPI_NSSInternalSoft)); + if (SPI_NSSInternalSoft != SPI_NSSInternalSoft_Reset) + { + /* Set NSS pin internally by software */ + SPIx->CR1 |= SPI_NSSInternalSoft_Set; + } + else + { + /* Reset NSS pin internally by software */ + SPIx->CR1 &= SPI_NSSInternalSoft_Reset; + } +} + +/** + * @brief Enables or disables the SS output for the selected SPI. + * @param SPIx: where x can be 1, 2 or 3 to select the SPI peripheral. + * @param NewState: new state of the SPIx SS output. + * This parameter can be: ENABLE or DISABLE. + * @retval None + */ +void SPI_SSOutputCmd(SPI_TypeDef* SPIx, FunctionalState NewState) +{ + /* Check the parameters */ + assert_param(IS_SPI_ALL_PERIPH(SPIx)); + assert_param(IS_FUNCTIONAL_STATE(NewState)); + if (NewState != DISABLE) + { + /* Enable the selected SPI SS output */ + SPIx->CR2 |= CR2_SSOE_Set; + } + else + { + /* Disable the selected SPI SS output */ + SPIx->CR2 &= CR2_SSOE_Reset; + } +} + +/** + * @brief Configures the data size for the selected SPI. + * @param SPIx: where x can be 1, 2 or 3 to select the SPI peripheral. + * @param SPI_DataSize: specifies the SPI data size. + * This parameter can be one of the following values: + * @arg SPI_DataSize_16b: Set data frame format to 16bit + * @arg SPI_DataSize_8b: Set data frame format to 8bit + * @retval None + */ +void SPI_DataSizeConfig(SPI_TypeDef* SPIx, uint16_t SPI_DataSize) +{ + /* Check the parameters */ + assert_param(IS_SPI_ALL_PERIPH(SPIx)); + assert_param(IS_SPI_DATASIZE(SPI_DataSize)); + /* Clear DFF bit */ + SPIx->CR1 &= (uint16_t)~SPI_DataSize_16b; + /* Set new DFF bit value */ + SPIx->CR1 |= SPI_DataSize; +} + +/** + * @brief Transmit the SPIx CRC value. + * @param SPIx: where x can be 1, 2 or 3 to select the SPI peripheral. + * @retval None + */ +void SPI_TransmitCRC(SPI_TypeDef* SPIx) +{ + /* Check the parameters */ + assert_param(IS_SPI_ALL_PERIPH(SPIx)); + + /* Enable the selected SPI CRC transmission */ + SPIx->CR1 |= CR1_CRCNext_Set; +} + +/** + * @brief Enables or disables the CRC value calculation of the transferred bytes. + * @param SPIx: where x can be 1, 2 or 3 to select the SPI peripheral. + * @param NewState: new state of the SPIx CRC value calculation. + * This parameter can be: ENABLE or DISABLE. + * @retval None + */ +void SPI_CalculateCRC(SPI_TypeDef* SPIx, FunctionalState NewState) +{ + /* Check the parameters */ + assert_param(IS_SPI_ALL_PERIPH(SPIx)); + assert_param(IS_FUNCTIONAL_STATE(NewState)); + if (NewState != DISABLE) + { + /* Enable the selected SPI CRC calculation */ + SPIx->CR1 |= CR1_CRCEN_Set; + } + else + { + /* Disable the selected SPI CRC calculation */ + SPIx->CR1 &= CR1_CRCEN_Reset; + } +} + +/** + * @brief Returns the transmit or the receive CRC register value for the specified SPI. + * @param SPIx: where x can be 1, 2 or 3 to select the SPI peripheral. + * @param SPI_CRC: specifies the CRC register to be read. + * This parameter can be one of the following values: + * @arg SPI_CRC_Tx: Selects Tx CRC register + * @arg SPI_CRC_Rx: Selects Rx CRC register + * @retval The selected CRC register value.. + */ +uint16_t SPI_GetCRC(SPI_TypeDef* SPIx, uint8_t SPI_CRC) +{ + uint16_t crcreg = 0; + /* Check the parameters */ + assert_param(IS_SPI_ALL_PERIPH(SPIx)); + assert_param(IS_SPI_CRC(SPI_CRC)); + if (SPI_CRC != SPI_CRC_Rx) + { + /* Get the Tx CRC register */ + crcreg = SPIx->TXCRCR; + } + else + { + /* Get the Rx CRC register */ + crcreg = SPIx->RXCRCR; + } + /* Return the selected CRC register */ + return crcreg; +} + +/** + * @brief Returns the CRC Polynomial register value for the specified SPI. + * @param SPIx: where x can be 1, 2 or 3 to select the SPI peripheral. + * @retval The CRC Polynomial register value. + */ +uint16_t SPI_GetCRCPolynomial(SPI_TypeDef* SPIx) +{ + /* Check the parameters */ + assert_param(IS_SPI_ALL_PERIPH(SPIx)); + + /* Return the CRC polynomial register */ + return SPIx->CRCPR; +} + +/** + * @brief Selects the data transfer direction in bi-directional mode for the specified SPI. + * @param SPIx: where x can be 1, 2 or 3 to select the SPI peripheral. + * @param SPI_Direction: specifies the data transfer direction in bi-directional mode. + * This parameter can be one of the following values: + * @arg SPI_Direction_Tx: Selects Tx transmission direction + * @arg SPI_Direction_Rx: Selects Rx receive direction + * @retval None + */ +void SPI_BiDirectionalLineConfig(SPI_TypeDef* SPIx, uint16_t SPI_Direction) +{ + /* Check the parameters */ + assert_param(IS_SPI_ALL_PERIPH(SPIx)); + assert_param(IS_SPI_DIRECTION(SPI_Direction)); + if (SPI_Direction == SPI_Direction_Tx) + { + /* Set the Tx only mode */ + SPIx->CR1 |= SPI_Direction_Tx; + } + else + { + /* Set the Rx only mode */ + SPIx->CR1 &= SPI_Direction_Rx; + } +} + +/** + * @brief Checks whether the specified SPI/I2S flag is set or not. + * @param SPIx: where x can be + * - 1, 2 or 3 in SPI mode + * - 2 or 3 in I2S mode + * @param SPI_I2S_FLAG: specifies the SPI/I2S flag to check. + * This parameter can be one of the following values: + * @arg SPI_I2S_FLAG_TXE: Transmit buffer empty flag. + * @arg SPI_I2S_FLAG_RXNE: Receive buffer not empty flag. + * @arg SPI_I2S_FLAG_BSY: Busy flag. + * @arg SPI_I2S_FLAG_OVR: Overrun flag. + * @arg SPI_FLAG_MODF: Mode Fault flag. + * @arg SPI_FLAG_CRCERR: CRC Error flag. + * @arg I2S_FLAG_UDR: Underrun Error flag. + * @arg I2S_FLAG_CHSIDE: Channel Side flag. + * @retval The new state of SPI_I2S_FLAG (SET or RESET). + */ +FlagStatus SPI_I2S_GetFlagStatus(SPI_TypeDef* SPIx, uint16_t SPI_I2S_FLAG) +{ + FlagStatus bitstatus = RESET; + /* Check the parameters */ + assert_param(IS_SPI_ALL_PERIPH(SPIx)); + assert_param(IS_SPI_I2S_GET_FLAG(SPI_I2S_FLAG)); + /* Check the status of the specified SPI/I2S flag */ + if ((SPIx->SR & SPI_I2S_FLAG) != (uint16_t)RESET) + { + /* SPI_I2S_FLAG is set */ + bitstatus = SET; + } + else + { + /* SPI_I2S_FLAG is reset */ + bitstatus = RESET; + } + /* Return the SPI_I2S_FLAG status */ + return bitstatus; +} + +/** + * @brief Clears the SPIx CRC Error (CRCERR) flag. + * @param SPIx: where x can be + * - 1, 2 or 3 in SPI mode + * @param SPI_I2S_FLAG: specifies the SPI flag to clear. + * This function clears only CRCERR flag. + * @note + * - OVR (OverRun error) flag is cleared by software sequence: a read + * operation to SPI_DR register (SPI_I2S_ReceiveData()) followed by a read + * operation to SPI_SR register (SPI_I2S_GetFlagStatus()). + * - UDR (UnderRun error) flag is cleared by a read operation to + * SPI_SR register (SPI_I2S_GetFlagStatus()). + * - MODF (Mode Fault) flag is cleared by software sequence: a read/write + * operation to SPI_SR register (SPI_I2S_GetFlagStatus()) followed by a + * write operation to SPI_CR1 register (SPI_Cmd() to enable the SPI). + * @retval None + */ +void SPI_I2S_ClearFlag(SPI_TypeDef* SPIx, uint16_t SPI_I2S_FLAG) +{ + /* Check the parameters */ + assert_param(IS_SPI_ALL_PERIPH(SPIx)); + assert_param(IS_SPI_I2S_CLEAR_FLAG(SPI_I2S_FLAG)); + + /* Clear the selected SPI CRC Error (CRCERR) flag */ + SPIx->SR = (uint16_t)~SPI_I2S_FLAG; +} + +/** + * @brief Checks whether the specified SPI/I2S interrupt has occurred or not. + * @param SPIx: where x can be + * - 1, 2 or 3 in SPI mode + * - 2 or 3 in I2S mode + * @param SPI_I2S_IT: specifies the SPI/I2S interrupt source to check. + * This parameter can be one of the following values: + * @arg SPI_I2S_IT_TXE: Transmit buffer empty interrupt. + * @arg SPI_I2S_IT_RXNE: Receive buffer not empty interrupt. + * @arg SPI_I2S_IT_OVR: Overrun interrupt. + * @arg SPI_IT_MODF: Mode Fault interrupt. + * @arg SPI_IT_CRCERR: CRC Error interrupt. + * @arg I2S_IT_UDR: Underrun Error interrupt. + * @retval The new state of SPI_I2S_IT (SET or RESET). + */ +ITStatus SPI_I2S_GetITStatus(SPI_TypeDef* SPIx, uint8_t SPI_I2S_IT) +{ + ITStatus bitstatus = RESET; + uint16_t itpos = 0, itmask = 0, enablestatus = 0; + + /* Check the parameters */ + assert_param(IS_SPI_ALL_PERIPH(SPIx)); + assert_param(IS_SPI_I2S_GET_IT(SPI_I2S_IT)); + + /* Get the SPI/I2S IT index */ + itpos = 0x01 << (SPI_I2S_IT & 0x0F); + + /* Get the SPI/I2S IT mask */ + itmask = SPI_I2S_IT >> 4; + + /* Set the IT mask */ + itmask = 0x01 << itmask; + + /* Get the SPI_I2S_IT enable bit status */ + enablestatus = (SPIx->CR2 & itmask) ; + + /* Check the status of the specified SPI/I2S interrupt */ + if (((SPIx->SR & itpos) != (uint16_t)RESET) && enablestatus) + { + /* SPI_I2S_IT is set */ + bitstatus = SET; + } + else + { + /* SPI_I2S_IT is reset */ + bitstatus = RESET; + } + /* Return the SPI_I2S_IT status */ + return bitstatus; +} + +/** + * @brief Clears the SPIx CRC Error (CRCERR) interrupt pending bit. + * @param SPIx: where x can be + * - 1, 2 or 3 in SPI mode + * @param SPI_I2S_IT: specifies the SPI interrupt pending bit to clear. + * This function clears only CRCERR interrupt pending bit. + * @note + * - OVR (OverRun Error) interrupt pending bit is cleared by software + * sequence: a read operation to SPI_DR register (SPI_I2S_ReceiveData()) + * followed by a read operation to SPI_SR register (SPI_I2S_GetITStatus()). + * - UDR (UnderRun Error) interrupt pending bit is cleared by a read + * operation to SPI_SR register (SPI_I2S_GetITStatus()). + * - MODF (Mode Fault) interrupt pending bit is cleared by software sequence: + * a read/write operation to SPI_SR register (SPI_I2S_GetITStatus()) + * followed by a write operation to SPI_CR1 register (SPI_Cmd() to enable + * the SPI). + * @retval None + */ +void SPI_I2S_ClearITPendingBit(SPI_TypeDef* SPIx, uint8_t SPI_I2S_IT) +{ + uint16_t itpos = 0; + /* Check the parameters */ + assert_param(IS_SPI_ALL_PERIPH(SPIx)); + assert_param(IS_SPI_I2S_CLEAR_IT(SPI_I2S_IT)); + + /* Get the SPI IT index */ + itpos = 0x01 << (SPI_I2S_IT & 0x0F); + + /* Clear the selected SPI CRC Error (CRCERR) interrupt pending bit */ + SPIx->SR = (uint16_t)~itpos; +} +/** + * @} + */ + +/** + * @} + */ + +/** + * @} + */ + +/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ diff --git a/Libraries/STM32F10x_StdPeriph_Driver/src/stm32f10x_tim.c b/Libraries/STM32F10x_StdPeriph_Driver/src/stm32f10x_tim.c new file mode 100644 index 0000000..aa628a9 --- /dev/null +++ b/Libraries/STM32F10x_StdPeriph_Driver/src/stm32f10x_tim.c @@ -0,0 +1,2896 @@ +/** + ****************************************************************************** + * @file stm32f10x_tim.c + * @author MCD Application Team + * @version V3.6.1 + * @date 05-March-2012 + * @brief This file provides all the TIM firmware functions. + ****************************************************************************** + * @attention + * + *

    © COPYRIGHT 2012 STMicroelectronics

    + * + * Licensed under MCD-ST Liberty SW License Agreement V2, (the "License"); + * You may not use this file except in compliance with the License. + * You may obtain a copy of the License at: + * + * http://www.st.com/software_license_agreement_liberty_v2 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, + * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + * + ****************************************************************************** + */ + +/* Includes ------------------------------------------------------------------*/ +#include "stm32f10x_tim.h" +#include "stm32f10x_rcc.h" + +/** @addtogroup STM32F10x_StdPeriph_Driver + * @{ + */ + +/** @defgroup TIM + * @brief TIM driver modules + * @{ + */ + +/** @defgroup TIM_Private_TypesDefinitions + * @{ + */ + +/** + * @} + */ + +/** @defgroup TIM_Private_Defines + * @{ + */ + +/* ---------------------- TIM registers bit mask ------------------------ */ +#define SMCR_ETR_Mask ((uint16_t)0x00FF) +#define CCMR_Offset ((uint16_t)0x0018) +#define CCER_CCE_Set ((uint16_t)0x0001) +#define CCER_CCNE_Set ((uint16_t)0x0004) + +/** + * @} + */ + +/** @defgroup TIM_Private_Macros + * @{ + */ + +/** + * @} + */ + +/** @defgroup TIM_Private_Variables + * @{ + */ + +/** + * @} + */ + +/** @defgroup TIM_Private_FunctionPrototypes + * @{ + */ + +static void TI1_Config(TIM_TypeDef* TIMx, uint16_t TIM_ICPolarity, uint16_t TIM_ICSelection, + uint16_t TIM_ICFilter); +static void TI2_Config(TIM_TypeDef* TIMx, uint16_t TIM_ICPolarity, uint16_t TIM_ICSelection, + uint16_t TIM_ICFilter); +static void TI3_Config(TIM_TypeDef* TIMx, uint16_t TIM_ICPolarity, uint16_t TIM_ICSelection, + uint16_t TIM_ICFilter); +static void TI4_Config(TIM_TypeDef* TIMx, uint16_t TIM_ICPolarity, uint16_t TIM_ICSelection, + uint16_t TIM_ICFilter); +/** + * @} + */ + +/** @defgroup TIM_Private_Macros + * @{ + */ + +/** + * @} + */ + +/** @defgroup TIM_Private_Variables + * @{ + */ + +/** + * @} + */ + +/** @defgroup TIM_Private_FunctionPrototypes + * @{ + */ + +/** + * @} + */ + +/** @defgroup TIM_Private_Functions + * @{ + */ + +/** + * @brief Deinitializes the TIMx peripheral registers to their default reset values. + * @param TIMx: where x can be 1 to 17 to select the TIM peripheral. + * @retval None + */ +void TIM_DeInit(TIM_TypeDef* TIMx) +{ + /* Check the parameters */ + assert_param(IS_TIM_ALL_PERIPH(TIMx)); + + if (TIMx == TIM1) + { + RCC_APB2PeriphResetCmd(RCC_APB2Periph_TIM1, ENABLE); + RCC_APB2PeriphResetCmd(RCC_APB2Periph_TIM1, DISABLE); + } + else if (TIMx == TIM2) + { + RCC_APB1PeriphResetCmd(RCC_APB1Periph_TIM2, ENABLE); + RCC_APB1PeriphResetCmd(RCC_APB1Periph_TIM2, DISABLE); + } + else if (TIMx == TIM3) + { + RCC_APB1PeriphResetCmd(RCC_APB1Periph_TIM3, ENABLE); + RCC_APB1PeriphResetCmd(RCC_APB1Periph_TIM3, DISABLE); + } + else if (TIMx == TIM4) + { + RCC_APB1PeriphResetCmd(RCC_APB1Periph_TIM4, ENABLE); + RCC_APB1PeriphResetCmd(RCC_APB1Periph_TIM4, DISABLE); + } + else if (TIMx == TIM5) + { + RCC_APB1PeriphResetCmd(RCC_APB1Periph_TIM5, ENABLE); + RCC_APB1PeriphResetCmd(RCC_APB1Periph_TIM5, DISABLE); + } + else if (TIMx == TIM6) + { + RCC_APB1PeriphResetCmd(RCC_APB1Periph_TIM6, ENABLE); + RCC_APB1PeriphResetCmd(RCC_APB1Periph_TIM6, DISABLE); + } + else if (TIMx == TIM7) + { + RCC_APB1PeriphResetCmd(RCC_APB1Periph_TIM7, ENABLE); + RCC_APB1PeriphResetCmd(RCC_APB1Periph_TIM7, DISABLE); + } + else if (TIMx == TIM8) + { + RCC_APB2PeriphResetCmd(RCC_APB2Periph_TIM8, ENABLE); + RCC_APB2PeriphResetCmd(RCC_APB2Periph_TIM8, DISABLE); + } + else if (TIMx == TIM9) + { + RCC_APB2PeriphResetCmd(RCC_APB2Periph_TIM9, ENABLE); + RCC_APB2PeriphResetCmd(RCC_APB2Periph_TIM9, DISABLE); + } + else if (TIMx == TIM10) + { + RCC_APB2PeriphResetCmd(RCC_APB2Periph_TIM10, ENABLE); + RCC_APB2PeriphResetCmd(RCC_APB2Periph_TIM10, DISABLE); + } + else if (TIMx == TIM11) + { + RCC_APB2PeriphResetCmd(RCC_APB2Periph_TIM11, ENABLE); + RCC_APB2PeriphResetCmd(RCC_APB2Periph_TIM11, DISABLE); + } + else if (TIMx == TIM12) + { + RCC_APB1PeriphResetCmd(RCC_APB1Periph_TIM12, ENABLE); + RCC_APB1PeriphResetCmd(RCC_APB1Periph_TIM12, DISABLE); + } + else if (TIMx == TIM13) + { + RCC_APB1PeriphResetCmd(RCC_APB1Periph_TIM13, ENABLE); + RCC_APB1PeriphResetCmd(RCC_APB1Periph_TIM13, DISABLE); + } + else if (TIMx == TIM14) + { + RCC_APB1PeriphResetCmd(RCC_APB1Periph_TIM14, ENABLE); + RCC_APB1PeriphResetCmd(RCC_APB1Periph_TIM14, DISABLE); + } + else if (TIMx == TIM15) + { + RCC_APB2PeriphResetCmd(RCC_APB2Periph_TIM15, ENABLE); + RCC_APB2PeriphResetCmd(RCC_APB2Periph_TIM15, DISABLE); + } + else if (TIMx == TIM16) + { + RCC_APB2PeriphResetCmd(RCC_APB2Periph_TIM16, ENABLE); + RCC_APB2PeriphResetCmd(RCC_APB2Periph_TIM16, DISABLE); + } + else + { + if (TIMx == TIM17) + { + RCC_APB2PeriphResetCmd(RCC_APB2Periph_TIM17, ENABLE); + RCC_APB2PeriphResetCmd(RCC_APB2Periph_TIM17, DISABLE); + } + } +} + +/** + * @brief Initializes the TIMx Time Base Unit peripheral according to + * the specified parameters in the TIM_TimeBaseInitStruct. + * @param TIMx: where x can be 1 to 17 to select the TIM peripheral. + * @param TIM_TimeBaseInitStruct: pointer to a TIM_TimeBaseInitTypeDef + * structure that contains the configuration information for the + * specified TIM peripheral. + * @retval None + */ +void TIM_TimeBaseInit(TIM_TypeDef* TIMx, TIM_TimeBaseInitTypeDef* TIM_TimeBaseInitStruct) +{ + uint16_t tmpcr1 = 0; + + /* Check the parameters */ + assert_param(IS_TIM_ALL_PERIPH(TIMx)); + assert_param(IS_TIM_COUNTER_MODE(TIM_TimeBaseInitStruct->TIM_CounterMode)); + assert_param(IS_TIM_CKD_DIV(TIM_TimeBaseInitStruct->TIM_ClockDivision)); + + tmpcr1 = TIMx->CR1; + + if((TIMx == TIM1) || (TIMx == TIM8)|| (TIMx == TIM2) || (TIMx == TIM3)|| + (TIMx == TIM4) || (TIMx == TIM5)) + { + /* Select the Counter Mode */ + tmpcr1 &= (uint16_t)(~((uint16_t)(TIM_CR1_DIR | TIM_CR1_CMS))); + tmpcr1 |= (uint32_t)TIM_TimeBaseInitStruct->TIM_CounterMode; + } + + if((TIMx != TIM6) && (TIMx != TIM7)) + { + /* Set the clock division */ + tmpcr1 &= (uint16_t)(~((uint16_t)TIM_CR1_CKD)); + tmpcr1 |= (uint32_t)TIM_TimeBaseInitStruct->TIM_ClockDivision; + } + + TIMx->CR1 = tmpcr1; + + /* Set the Autoreload value */ + TIMx->ARR = TIM_TimeBaseInitStruct->TIM_Period ; + + /* Set the Prescaler value */ + TIMx->PSC = TIM_TimeBaseInitStruct->TIM_Prescaler; + + if ((TIMx == TIM1) || (TIMx == TIM8)|| (TIMx == TIM15)|| (TIMx == TIM16) || (TIMx == TIM17)) + { + /* Set the Repetition Counter value */ + TIMx->RCR = TIM_TimeBaseInitStruct->TIM_RepetitionCounter; + } + + /* Generate an update event to reload the Prescaler and the Repetition counter + values immediately */ + TIMx->EGR = TIM_PSCReloadMode_Immediate; +} + +/** + * @brief Initializes the TIMx Channel1 according to the specified + * parameters in the TIM_OCInitStruct. + * @param TIMx: where x can be 1 to 17 except 6 and 7 to select the TIM peripheral. + * @param TIM_OCInitStruct: pointer to a TIM_OCInitTypeDef structure + * that contains the configuration information for the specified TIM peripheral. + * @retval None + */ +void TIM_OC1Init(TIM_TypeDef* TIMx, TIM_OCInitTypeDef* TIM_OCInitStruct) +{ + uint16_t tmpccmrx = 0, tmpccer = 0, tmpcr2 = 0; + + /* Check the parameters */ + assert_param(IS_TIM_LIST8_PERIPH(TIMx)); + assert_param(IS_TIM_OC_MODE(TIM_OCInitStruct->TIM_OCMode)); + assert_param(IS_TIM_OUTPUT_STATE(TIM_OCInitStruct->TIM_OutputState)); + assert_param(IS_TIM_OC_POLARITY(TIM_OCInitStruct->TIM_OCPolarity)); + /* Disable the Channel 1: Reset the CC1E Bit */ + TIMx->CCER &= (uint16_t)(~(uint16_t)TIM_CCER_CC1E); + /* Get the TIMx CCER register value */ + tmpccer = TIMx->CCER; + /* Get the TIMx CR2 register value */ + tmpcr2 = TIMx->CR2; + + /* Get the TIMx CCMR1 register value */ + tmpccmrx = TIMx->CCMR1; + + /* Reset the Output Compare Mode Bits */ + tmpccmrx &= (uint16_t)(~((uint16_t)TIM_CCMR1_OC1M)); + tmpccmrx &= (uint16_t)(~((uint16_t)TIM_CCMR1_CC1S)); + + /* Select the Output Compare Mode */ + tmpccmrx |= TIM_OCInitStruct->TIM_OCMode; + + /* Reset the Output Polarity level */ + tmpccer &= (uint16_t)(~((uint16_t)TIM_CCER_CC1P)); + /* Set the Output Compare Polarity */ + tmpccer |= TIM_OCInitStruct->TIM_OCPolarity; + + /* Set the Output State */ + tmpccer |= TIM_OCInitStruct->TIM_OutputState; + + if((TIMx == TIM1) || (TIMx == TIM8)|| (TIMx == TIM15)|| + (TIMx == TIM16)|| (TIMx == TIM17)) + { + assert_param(IS_TIM_OUTPUTN_STATE(TIM_OCInitStruct->TIM_OutputNState)); + assert_param(IS_TIM_OCN_POLARITY(TIM_OCInitStruct->TIM_OCNPolarity)); + assert_param(IS_TIM_OCNIDLE_STATE(TIM_OCInitStruct->TIM_OCNIdleState)); + assert_param(IS_TIM_OCIDLE_STATE(TIM_OCInitStruct->TIM_OCIdleState)); + + /* Reset the Output N Polarity level */ + tmpccer &= (uint16_t)(~((uint16_t)TIM_CCER_CC1NP)); + /* Set the Output N Polarity */ + tmpccer |= TIM_OCInitStruct->TIM_OCNPolarity; + + /* Reset the Output N State */ + tmpccer &= (uint16_t)(~((uint16_t)TIM_CCER_CC1NE)); + /* Set the Output N State */ + tmpccer |= TIM_OCInitStruct->TIM_OutputNState; + + /* Reset the Output Compare and Output Compare N IDLE State */ + tmpcr2 &= (uint16_t)(~((uint16_t)TIM_CR2_OIS1)); + tmpcr2 &= (uint16_t)(~((uint16_t)TIM_CR2_OIS1N)); + + /* Set the Output Idle state */ + tmpcr2 |= TIM_OCInitStruct->TIM_OCIdleState; + /* Set the Output N Idle state */ + tmpcr2 |= TIM_OCInitStruct->TIM_OCNIdleState; + } + /* Write to TIMx CR2 */ + TIMx->CR2 = tmpcr2; + + /* Write to TIMx CCMR1 */ + TIMx->CCMR1 = tmpccmrx; + + /* Set the Capture Compare Register value */ + TIMx->CCR1 = TIM_OCInitStruct->TIM_Pulse; + + /* Write to TIMx CCER */ + TIMx->CCER = tmpccer; +} + +/** + * @brief Initializes the TIMx Channel2 according to the specified + * parameters in the TIM_OCInitStruct. + * @param TIMx: where x can be 1, 2, 3, 4, 5, 8, 9, 12 or 15 to select + * the TIM peripheral. + * @param TIM_OCInitStruct: pointer to a TIM_OCInitTypeDef structure + * that contains the configuration information for the specified TIM peripheral. + * @retval None + */ +void TIM_OC2Init(TIM_TypeDef* TIMx, TIM_OCInitTypeDef* TIM_OCInitStruct) +{ + uint16_t tmpccmrx = 0, tmpccer = 0, tmpcr2 = 0; + + /* Check the parameters */ + assert_param(IS_TIM_LIST6_PERIPH(TIMx)); + assert_param(IS_TIM_OC_MODE(TIM_OCInitStruct->TIM_OCMode)); + assert_param(IS_TIM_OUTPUT_STATE(TIM_OCInitStruct->TIM_OutputState)); + assert_param(IS_TIM_OC_POLARITY(TIM_OCInitStruct->TIM_OCPolarity)); + /* Disable the Channel 2: Reset the CC2E Bit */ + TIMx->CCER &= (uint16_t)(~((uint16_t)TIM_CCER_CC2E)); + + /* Get the TIMx CCER register value */ + tmpccer = TIMx->CCER; + /* Get the TIMx CR2 register value */ + tmpcr2 = TIMx->CR2; + + /* Get the TIMx CCMR1 register value */ + tmpccmrx = TIMx->CCMR1; + + /* Reset the Output Compare mode and Capture/Compare selection Bits */ + tmpccmrx &= (uint16_t)(~((uint16_t)TIM_CCMR1_OC2M)); + tmpccmrx &= (uint16_t)(~((uint16_t)TIM_CCMR1_CC2S)); + + /* Select the Output Compare Mode */ + tmpccmrx |= (uint16_t)(TIM_OCInitStruct->TIM_OCMode << 8); + + /* Reset the Output Polarity level */ + tmpccer &= (uint16_t)(~((uint16_t)TIM_CCER_CC2P)); + /* Set the Output Compare Polarity */ + tmpccer |= (uint16_t)(TIM_OCInitStruct->TIM_OCPolarity << 4); + + /* Set the Output State */ + tmpccer |= (uint16_t)(TIM_OCInitStruct->TIM_OutputState << 4); + + if((TIMx == TIM1) || (TIMx == TIM8)) + { + assert_param(IS_TIM_OUTPUTN_STATE(TIM_OCInitStruct->TIM_OutputNState)); + assert_param(IS_TIM_OCN_POLARITY(TIM_OCInitStruct->TIM_OCNPolarity)); + assert_param(IS_TIM_OCNIDLE_STATE(TIM_OCInitStruct->TIM_OCNIdleState)); + assert_param(IS_TIM_OCIDLE_STATE(TIM_OCInitStruct->TIM_OCIdleState)); + + /* Reset the Output N Polarity level */ + tmpccer &= (uint16_t)(~((uint16_t)TIM_CCER_CC2NP)); + /* Set the Output N Polarity */ + tmpccer |= (uint16_t)(TIM_OCInitStruct->TIM_OCNPolarity << 4); + + /* Reset the Output N State */ + tmpccer &= (uint16_t)(~((uint16_t)TIM_CCER_CC2NE)); + /* Set the Output N State */ + tmpccer |= (uint16_t)(TIM_OCInitStruct->TIM_OutputNState << 4); + + /* Reset the Output Compare and Output Compare N IDLE State */ + tmpcr2 &= (uint16_t)(~((uint16_t)TIM_CR2_OIS2)); + tmpcr2 &= (uint16_t)(~((uint16_t)TIM_CR2_OIS2N)); + + /* Set the Output Idle state */ + tmpcr2 |= (uint16_t)(TIM_OCInitStruct->TIM_OCIdleState << 2); + /* Set the Output N Idle state */ + tmpcr2 |= (uint16_t)(TIM_OCInitStruct->TIM_OCNIdleState << 2); + } + /* Write to TIMx CR2 */ + TIMx->CR2 = tmpcr2; + + /* Write to TIMx CCMR1 */ + TIMx->CCMR1 = tmpccmrx; + + /* Set the Capture Compare Register value */ + TIMx->CCR2 = TIM_OCInitStruct->TIM_Pulse; + + /* Write to TIMx CCER */ + TIMx->CCER = tmpccer; +} + +/** + * @brief Initializes the TIMx Channel3 according to the specified + * parameters in the TIM_OCInitStruct. + * @param TIMx: where x can be 1, 2, 3, 4, 5 or 8 to select the TIM peripheral. + * @param TIM_OCInitStruct: pointer to a TIM_OCInitTypeDef structure + * that contains the configuration information for the specified TIM peripheral. + * @retval None + */ +void TIM_OC3Init(TIM_TypeDef* TIMx, TIM_OCInitTypeDef* TIM_OCInitStruct) +{ + uint16_t tmpccmrx = 0, tmpccer = 0, tmpcr2 = 0; + + /* Check the parameters */ + assert_param(IS_TIM_LIST3_PERIPH(TIMx)); + assert_param(IS_TIM_OC_MODE(TIM_OCInitStruct->TIM_OCMode)); + assert_param(IS_TIM_OUTPUT_STATE(TIM_OCInitStruct->TIM_OutputState)); + assert_param(IS_TIM_OC_POLARITY(TIM_OCInitStruct->TIM_OCPolarity)); + /* Disable the Channel 2: Reset the CC2E Bit */ + TIMx->CCER &= (uint16_t)(~((uint16_t)TIM_CCER_CC3E)); + + /* Get the TIMx CCER register value */ + tmpccer = TIMx->CCER; + /* Get the TIMx CR2 register value */ + tmpcr2 = TIMx->CR2; + + /* Get the TIMx CCMR2 register value */ + tmpccmrx = TIMx->CCMR2; + + /* Reset the Output Compare mode and Capture/Compare selection Bits */ + tmpccmrx &= (uint16_t)(~((uint16_t)TIM_CCMR2_OC3M)); + tmpccmrx &= (uint16_t)(~((uint16_t)TIM_CCMR2_CC3S)); + /* Select the Output Compare Mode */ + tmpccmrx |= TIM_OCInitStruct->TIM_OCMode; + + /* Reset the Output Polarity level */ + tmpccer &= (uint16_t)(~((uint16_t)TIM_CCER_CC3P)); + /* Set the Output Compare Polarity */ + tmpccer |= (uint16_t)(TIM_OCInitStruct->TIM_OCPolarity << 8); + + /* Set the Output State */ + tmpccer |= (uint16_t)(TIM_OCInitStruct->TIM_OutputState << 8); + + if((TIMx == TIM1) || (TIMx == TIM8)) + { + assert_param(IS_TIM_OUTPUTN_STATE(TIM_OCInitStruct->TIM_OutputNState)); + assert_param(IS_TIM_OCN_POLARITY(TIM_OCInitStruct->TIM_OCNPolarity)); + assert_param(IS_TIM_OCNIDLE_STATE(TIM_OCInitStruct->TIM_OCNIdleState)); + assert_param(IS_TIM_OCIDLE_STATE(TIM_OCInitStruct->TIM_OCIdleState)); + + /* Reset the Output N Polarity level */ + tmpccer &= (uint16_t)(~((uint16_t)TIM_CCER_CC3NP)); + /* Set the Output N Polarity */ + tmpccer |= (uint16_t)(TIM_OCInitStruct->TIM_OCNPolarity << 8); + /* Reset the Output N State */ + tmpccer &= (uint16_t)(~((uint16_t)TIM_CCER_CC3NE)); + + /* Set the Output N State */ + tmpccer |= (uint16_t)(TIM_OCInitStruct->TIM_OutputNState << 8); + /* Reset the Output Compare and Output Compare N IDLE State */ + tmpcr2 &= (uint16_t)(~((uint16_t)TIM_CR2_OIS3)); + tmpcr2 &= (uint16_t)(~((uint16_t)TIM_CR2_OIS3N)); + /* Set the Output Idle state */ + tmpcr2 |= (uint16_t)(TIM_OCInitStruct->TIM_OCIdleState << 4); + /* Set the Output N Idle state */ + tmpcr2 |= (uint16_t)(TIM_OCInitStruct->TIM_OCNIdleState << 4); + } + /* Write to TIMx CR2 */ + TIMx->CR2 = tmpcr2; + + /* Write to TIMx CCMR2 */ + TIMx->CCMR2 = tmpccmrx; + + /* Set the Capture Compare Register value */ + TIMx->CCR3 = TIM_OCInitStruct->TIM_Pulse; + + /* Write to TIMx CCER */ + TIMx->CCER = tmpccer; +} + +/** + * @brief Initializes the TIMx Channel4 according to the specified + * parameters in the TIM_OCInitStruct. + * @param TIMx: where x can be 1, 2, 3, 4, 5 or 8 to select the TIM peripheral. + * @param TIM_OCInitStruct: pointer to a TIM_OCInitTypeDef structure + * that contains the configuration information for the specified TIM peripheral. + * @retval None + */ +void TIM_OC4Init(TIM_TypeDef* TIMx, TIM_OCInitTypeDef* TIM_OCInitStruct) +{ + uint16_t tmpccmrx = 0, tmpccer = 0, tmpcr2 = 0; + + /* Check the parameters */ + assert_param(IS_TIM_LIST3_PERIPH(TIMx)); + assert_param(IS_TIM_OC_MODE(TIM_OCInitStruct->TIM_OCMode)); + assert_param(IS_TIM_OUTPUT_STATE(TIM_OCInitStruct->TIM_OutputState)); + assert_param(IS_TIM_OC_POLARITY(TIM_OCInitStruct->TIM_OCPolarity)); + /* Disable the Channel 2: Reset the CC4E Bit */ + TIMx->CCER &= (uint16_t)(~((uint16_t)TIM_CCER_CC4E)); + + /* Get the TIMx CCER register value */ + tmpccer = TIMx->CCER; + /* Get the TIMx CR2 register value */ + tmpcr2 = TIMx->CR2; + + /* Get the TIMx CCMR2 register value */ + tmpccmrx = TIMx->CCMR2; + + /* Reset the Output Compare mode and Capture/Compare selection Bits */ + tmpccmrx &= (uint16_t)(~((uint16_t)TIM_CCMR2_OC4M)); + tmpccmrx &= (uint16_t)(~((uint16_t)TIM_CCMR2_CC4S)); + + /* Select the Output Compare Mode */ + tmpccmrx |= (uint16_t)(TIM_OCInitStruct->TIM_OCMode << 8); + + /* Reset the Output Polarity level */ + tmpccer &= (uint16_t)(~((uint16_t)TIM_CCER_CC4P)); + /* Set the Output Compare Polarity */ + tmpccer |= (uint16_t)(TIM_OCInitStruct->TIM_OCPolarity << 12); + + /* Set the Output State */ + tmpccer |= (uint16_t)(TIM_OCInitStruct->TIM_OutputState << 12); + + if((TIMx == TIM1) || (TIMx == TIM8)) + { + assert_param(IS_TIM_OCIDLE_STATE(TIM_OCInitStruct->TIM_OCIdleState)); + /* Reset the Output Compare IDLE State */ + tmpcr2 &= (uint16_t)(~((uint16_t)TIM_CR2_OIS4)); + /* Set the Output Idle state */ + tmpcr2 |= (uint16_t)(TIM_OCInitStruct->TIM_OCIdleState << 6); + } + /* Write to TIMx CR2 */ + TIMx->CR2 = tmpcr2; + + /* Write to TIMx CCMR2 */ + TIMx->CCMR2 = tmpccmrx; + + /* Set the Capture Compare Register value */ + TIMx->CCR4 = TIM_OCInitStruct->TIM_Pulse; + + /* Write to TIMx CCER */ + TIMx->CCER = tmpccer; +} + +/** + * @brief Initializes the TIM peripheral according to the specified + * parameters in the TIM_ICInitStruct. + * @param TIMx: where x can be 1 to 17 except 6 and 7 to select the TIM peripheral. + * @param TIM_ICInitStruct: pointer to a TIM_ICInitTypeDef structure + * that contains the configuration information for the specified TIM peripheral. + * @retval None + */ +void TIM_ICInit(TIM_TypeDef* TIMx, TIM_ICInitTypeDef* TIM_ICInitStruct) +{ + /* Check the parameters */ + assert_param(IS_TIM_CHANNEL(TIM_ICInitStruct->TIM_Channel)); + assert_param(IS_TIM_IC_SELECTION(TIM_ICInitStruct->TIM_ICSelection)); + assert_param(IS_TIM_IC_PRESCALER(TIM_ICInitStruct->TIM_ICPrescaler)); + assert_param(IS_TIM_IC_FILTER(TIM_ICInitStruct->TIM_ICFilter)); + + if((TIMx == TIM1) || (TIMx == TIM8) || (TIMx == TIM2) || (TIMx == TIM3) || + (TIMx == TIM4) ||(TIMx == TIM5)) + { + assert_param(IS_TIM_IC_POLARITY(TIM_ICInitStruct->TIM_ICPolarity)); + } + else + { + assert_param(IS_TIM_IC_POLARITY_LITE(TIM_ICInitStruct->TIM_ICPolarity)); + } + if (TIM_ICInitStruct->TIM_Channel == TIM_Channel_1) + { + assert_param(IS_TIM_LIST8_PERIPH(TIMx)); + /* TI1 Configuration */ + TI1_Config(TIMx, TIM_ICInitStruct->TIM_ICPolarity, + TIM_ICInitStruct->TIM_ICSelection, + TIM_ICInitStruct->TIM_ICFilter); + /* Set the Input Capture Prescaler value */ + TIM_SetIC1Prescaler(TIMx, TIM_ICInitStruct->TIM_ICPrescaler); + } + else if (TIM_ICInitStruct->TIM_Channel == TIM_Channel_2) + { + assert_param(IS_TIM_LIST6_PERIPH(TIMx)); + /* TI2 Configuration */ + TI2_Config(TIMx, TIM_ICInitStruct->TIM_ICPolarity, + TIM_ICInitStruct->TIM_ICSelection, + TIM_ICInitStruct->TIM_ICFilter); + /* Set the Input Capture Prescaler value */ + TIM_SetIC2Prescaler(TIMx, TIM_ICInitStruct->TIM_ICPrescaler); + } + else if (TIM_ICInitStruct->TIM_Channel == TIM_Channel_3) + { + assert_param(IS_TIM_LIST3_PERIPH(TIMx)); + /* TI3 Configuration */ + TI3_Config(TIMx, TIM_ICInitStruct->TIM_ICPolarity, + TIM_ICInitStruct->TIM_ICSelection, + TIM_ICInitStruct->TIM_ICFilter); + /* Set the Input Capture Prescaler value */ + TIM_SetIC3Prescaler(TIMx, TIM_ICInitStruct->TIM_ICPrescaler); + } + else + { + assert_param(IS_TIM_LIST3_PERIPH(TIMx)); + /* TI4 Configuration */ + TI4_Config(TIMx, TIM_ICInitStruct->TIM_ICPolarity, + TIM_ICInitStruct->TIM_ICSelection, + TIM_ICInitStruct->TIM_ICFilter); + /* Set the Input Capture Prescaler value */ + TIM_SetIC4Prescaler(TIMx, TIM_ICInitStruct->TIM_ICPrescaler); + } +} + +/** + * @brief Configures the TIM peripheral according to the specified + * parameters in the TIM_ICInitStruct to measure an external PWM signal. + * @param TIMx: where x can be 1, 2, 3, 4, 5, 8, 9, 12 or 15 to select the TIM peripheral. + * @param TIM_ICInitStruct: pointer to a TIM_ICInitTypeDef structure + * that contains the configuration information for the specified TIM peripheral. + * @retval None + */ +void TIM_PWMIConfig(TIM_TypeDef* TIMx, TIM_ICInitTypeDef* TIM_ICInitStruct) +{ + uint16_t icoppositepolarity = TIM_ICPolarity_Rising; + uint16_t icoppositeselection = TIM_ICSelection_DirectTI; + /* Check the parameters */ + assert_param(IS_TIM_LIST6_PERIPH(TIMx)); + /* Select the Opposite Input Polarity */ + if (TIM_ICInitStruct->TIM_ICPolarity == TIM_ICPolarity_Rising) + { + icoppositepolarity = TIM_ICPolarity_Falling; + } + else + { + icoppositepolarity = TIM_ICPolarity_Rising; + } + /* Select the Opposite Input */ + if (TIM_ICInitStruct->TIM_ICSelection == TIM_ICSelection_DirectTI) + { + icoppositeselection = TIM_ICSelection_IndirectTI; + } + else + { + icoppositeselection = TIM_ICSelection_DirectTI; + } + if (TIM_ICInitStruct->TIM_Channel == TIM_Channel_1) + { + /* TI1 Configuration */ + TI1_Config(TIMx, TIM_ICInitStruct->TIM_ICPolarity, TIM_ICInitStruct->TIM_ICSelection, + TIM_ICInitStruct->TIM_ICFilter); + /* Set the Input Capture Prescaler value */ + TIM_SetIC1Prescaler(TIMx, TIM_ICInitStruct->TIM_ICPrescaler); + /* TI2 Configuration */ + TI2_Config(TIMx, icoppositepolarity, icoppositeselection, TIM_ICInitStruct->TIM_ICFilter); + /* Set the Input Capture Prescaler value */ + TIM_SetIC2Prescaler(TIMx, TIM_ICInitStruct->TIM_ICPrescaler); + } + else + { + /* TI2 Configuration */ + TI2_Config(TIMx, TIM_ICInitStruct->TIM_ICPolarity, TIM_ICInitStruct->TIM_ICSelection, + TIM_ICInitStruct->TIM_ICFilter); + /* Set the Input Capture Prescaler value */ + TIM_SetIC2Prescaler(TIMx, TIM_ICInitStruct->TIM_ICPrescaler); + /* TI1 Configuration */ + TI1_Config(TIMx, icoppositepolarity, icoppositeselection, TIM_ICInitStruct->TIM_ICFilter); + /* Set the Input Capture Prescaler value */ + TIM_SetIC1Prescaler(TIMx, TIM_ICInitStruct->TIM_ICPrescaler); + } +} + +/** + * @brief Configures the: Break feature, dead time, Lock level, the OSSI, + * the OSSR State and the AOE(automatic output enable). + * @param TIMx: where x can be 1 or 8 to select the TIM + * @param TIM_BDTRInitStruct: pointer to a TIM_BDTRInitTypeDef structure that + * contains the BDTR Register configuration information for the TIM peripheral. + * @retval None + */ +void TIM_BDTRConfig(TIM_TypeDef* TIMx, TIM_BDTRInitTypeDef *TIM_BDTRInitStruct) +{ + /* Check the parameters */ + assert_param(IS_TIM_LIST2_PERIPH(TIMx)); + assert_param(IS_TIM_OSSR_STATE(TIM_BDTRInitStruct->TIM_OSSRState)); + assert_param(IS_TIM_OSSI_STATE(TIM_BDTRInitStruct->TIM_OSSIState)); + assert_param(IS_TIM_LOCK_LEVEL(TIM_BDTRInitStruct->TIM_LOCKLevel)); + assert_param(IS_TIM_BREAK_STATE(TIM_BDTRInitStruct->TIM_Break)); + assert_param(IS_TIM_BREAK_POLARITY(TIM_BDTRInitStruct->TIM_BreakPolarity)); + assert_param(IS_TIM_AUTOMATIC_OUTPUT_STATE(TIM_BDTRInitStruct->TIM_AutomaticOutput)); + /* Set the Lock level, the Break enable Bit and the Ploarity, the OSSR State, + the OSSI State, the dead time value and the Automatic Output Enable Bit */ + TIMx->BDTR = (uint32_t)TIM_BDTRInitStruct->TIM_OSSRState | TIM_BDTRInitStruct->TIM_OSSIState | + TIM_BDTRInitStruct->TIM_LOCKLevel | TIM_BDTRInitStruct->TIM_DeadTime | + TIM_BDTRInitStruct->TIM_Break | TIM_BDTRInitStruct->TIM_BreakPolarity | + TIM_BDTRInitStruct->TIM_AutomaticOutput; +} + +/** + * @brief Fills each TIM_TimeBaseInitStruct member with its default value. + * @param TIM_TimeBaseInitStruct : pointer to a TIM_TimeBaseInitTypeDef + * structure which will be initialized. + * @retval None + */ +void TIM_TimeBaseStructInit(TIM_TimeBaseInitTypeDef* TIM_TimeBaseInitStruct) +{ + /* Set the default configuration */ + TIM_TimeBaseInitStruct->TIM_Period = 0xFFFF; + TIM_TimeBaseInitStruct->TIM_Prescaler = 0x0000; + TIM_TimeBaseInitStruct->TIM_ClockDivision = TIM_CKD_DIV1; + TIM_TimeBaseInitStruct->TIM_CounterMode = TIM_CounterMode_Up; + TIM_TimeBaseInitStruct->TIM_RepetitionCounter = 0x0000; +} + +/** + * @brief Fills each TIM_OCInitStruct member with its default value. + * @param TIM_OCInitStruct : pointer to a TIM_OCInitTypeDef structure which will + * be initialized. + * @retval None + */ +void TIM_OCStructInit(TIM_OCInitTypeDef* TIM_OCInitStruct) +{ + /* Set the default configuration */ + TIM_OCInitStruct->TIM_OCMode = TIM_OCMode_Timing; + TIM_OCInitStruct->TIM_OutputState = TIM_OutputState_Disable; + TIM_OCInitStruct->TIM_OutputNState = TIM_OutputNState_Disable; + TIM_OCInitStruct->TIM_Pulse = 0x0000; + TIM_OCInitStruct->TIM_OCPolarity = TIM_OCPolarity_High; + TIM_OCInitStruct->TIM_OCNPolarity = TIM_OCPolarity_High; + TIM_OCInitStruct->TIM_OCIdleState = TIM_OCIdleState_Reset; + TIM_OCInitStruct->TIM_OCNIdleState = TIM_OCNIdleState_Reset; +} + +/** + * @brief Fills each TIM_ICInitStruct member with its default value. + * @param TIM_ICInitStruct: pointer to a TIM_ICInitTypeDef structure which will + * be initialized. + * @retval None + */ +void TIM_ICStructInit(TIM_ICInitTypeDef* TIM_ICInitStruct) +{ + /* Set the default configuration */ + TIM_ICInitStruct->TIM_Channel = TIM_Channel_1; + TIM_ICInitStruct->TIM_ICPolarity = TIM_ICPolarity_Rising; + TIM_ICInitStruct->TIM_ICSelection = TIM_ICSelection_DirectTI; + TIM_ICInitStruct->TIM_ICPrescaler = TIM_ICPSC_DIV1; + TIM_ICInitStruct->TIM_ICFilter = 0x00; +} + +/** + * @brief Fills each TIM_BDTRInitStruct member with its default value. + * @param TIM_BDTRInitStruct: pointer to a TIM_BDTRInitTypeDef structure which + * will be initialized. + * @retval None + */ +void TIM_BDTRStructInit(TIM_BDTRInitTypeDef* TIM_BDTRInitStruct) +{ + /* Set the default configuration */ + TIM_BDTRInitStruct->TIM_OSSRState = TIM_OSSRState_Disable; + TIM_BDTRInitStruct->TIM_OSSIState = TIM_OSSIState_Disable; + TIM_BDTRInitStruct->TIM_LOCKLevel = TIM_LOCKLevel_OFF; + TIM_BDTRInitStruct->TIM_DeadTime = 0x00; + TIM_BDTRInitStruct->TIM_Break = TIM_Break_Disable; + TIM_BDTRInitStruct->TIM_BreakPolarity = TIM_BreakPolarity_Low; + TIM_BDTRInitStruct->TIM_AutomaticOutput = TIM_AutomaticOutput_Disable; +} + +/** + * @brief Enables or disables the specified TIM peripheral. + * @param TIMx: where x can be 1 to 17 to select the TIMx peripheral. + * @param NewState: new state of the TIMx peripheral. + * This parameter can be: ENABLE or DISABLE. + * @retval None + */ +void TIM_Cmd(TIM_TypeDef* TIMx, FunctionalState NewState) +{ + /* Check the parameters */ + assert_param(IS_TIM_ALL_PERIPH(TIMx)); + assert_param(IS_FUNCTIONAL_STATE(NewState)); + + if (NewState != DISABLE) + { + /* Enable the TIM Counter */ + TIMx->CR1 |= TIM_CR1_CEN; + } + else + { + /* Disable the TIM Counter */ + TIMx->CR1 &= (uint16_t)(~((uint16_t)TIM_CR1_CEN)); + } +} + +/** + * @brief Enables or disables the TIM peripheral Main Outputs. + * @param TIMx: where x can be 1, 8, 15, 16 or 17 to select the TIMx peripheral. + * @param NewState: new state of the TIM peripheral Main Outputs. + * This parameter can be: ENABLE or DISABLE. + * @retval None + */ +void TIM_CtrlPWMOutputs(TIM_TypeDef* TIMx, FunctionalState NewState) +{ + /* Check the parameters */ + assert_param(IS_TIM_LIST2_PERIPH(TIMx)); + assert_param(IS_FUNCTIONAL_STATE(NewState)); + if (NewState != DISABLE) + { + /* Enable the TIM Main Output */ + TIMx->BDTR |= TIM_BDTR_MOE; + } + else + { + /* Disable the TIM Main Output */ + TIMx->BDTR &= (uint16_t)(~((uint16_t)TIM_BDTR_MOE)); + } +} + +/** + * @brief Enables or disables the specified TIM interrupts. + * @param TIMx: where x can be 1 to 17 to select the TIMx peripheral. + * @param TIM_IT: specifies the TIM interrupts sources to be enabled or disabled. + * This parameter can be any combination of the following values: + * @arg TIM_IT_Update: TIM update Interrupt source + * @arg TIM_IT_CC1: TIM Capture Compare 1 Interrupt source + * @arg TIM_IT_CC2: TIM Capture Compare 2 Interrupt source + * @arg TIM_IT_CC3: TIM Capture Compare 3 Interrupt source + * @arg TIM_IT_CC4: TIM Capture Compare 4 Interrupt source + * @arg TIM_IT_COM: TIM Commutation Interrupt source + * @arg TIM_IT_Trigger: TIM Trigger Interrupt source + * @arg TIM_IT_Break: TIM Break Interrupt source + * @note + * - TIM6 and TIM7 can only generate an update interrupt. + * - TIM9, TIM12 and TIM15 can have only TIM_IT_Update, TIM_IT_CC1, + * TIM_IT_CC2 or TIM_IT_Trigger. + * - TIM10, TIM11, TIM13, TIM14, TIM16 and TIM17 can have TIM_IT_Update or TIM_IT_CC1. + * - TIM_IT_Break is used only with TIM1, TIM8 and TIM15. + * - TIM_IT_COM is used only with TIM1, TIM8, TIM15, TIM16 and TIM17. + * @param NewState: new state of the TIM interrupts. + * This parameter can be: ENABLE or DISABLE. + * @retval None + */ +void TIM_ITConfig(TIM_TypeDef* TIMx, uint16_t TIM_IT, FunctionalState NewState) +{ + /* Check the parameters */ + assert_param(IS_TIM_ALL_PERIPH(TIMx)); + assert_param(IS_TIM_IT(TIM_IT)); + assert_param(IS_FUNCTIONAL_STATE(NewState)); + + if (NewState != DISABLE) + { + /* Enable the Interrupt sources */ + TIMx->DIER |= TIM_IT; + } + else + { + /* Disable the Interrupt sources */ + TIMx->DIER &= (uint16_t)~TIM_IT; + } +} + +/** + * @brief Configures the TIMx event to be generate by software. + * @param TIMx: where x can be 1 to 17 to select the TIM peripheral. + * @param TIM_EventSource: specifies the event source. + * This parameter can be one or more of the following values: + * @arg TIM_EventSource_Update: Timer update Event source + * @arg TIM_EventSource_CC1: Timer Capture Compare 1 Event source + * @arg TIM_EventSource_CC2: Timer Capture Compare 2 Event source + * @arg TIM_EventSource_CC3: Timer Capture Compare 3 Event source + * @arg TIM_EventSource_CC4: Timer Capture Compare 4 Event source + * @arg TIM_EventSource_COM: Timer COM event source + * @arg TIM_EventSource_Trigger: Timer Trigger Event source + * @arg TIM_EventSource_Break: Timer Break event source + * @note + * - TIM6 and TIM7 can only generate an update event. + * - TIM_EventSource_COM and TIM_EventSource_Break are used only with TIM1 and TIM8. + * @retval None + */ +void TIM_GenerateEvent(TIM_TypeDef* TIMx, uint16_t TIM_EventSource) +{ + /* Check the parameters */ + assert_param(IS_TIM_ALL_PERIPH(TIMx)); + assert_param(IS_TIM_EVENT_SOURCE(TIM_EventSource)); + + /* Set the event sources */ + TIMx->EGR = TIM_EventSource; +} + +/** + * @brief Configures the TIMx's DMA interface. + * @param TIMx: where x can be 1, 2, 3, 4, 5, 8, 15, 16 or 17 to select + * the TIM peripheral. + * @param TIM_DMABase: DMA Base address. + * This parameter can be one of the following values: + * @arg TIM_DMABase_CR, TIM_DMABase_CR2, TIM_DMABase_SMCR, + * TIM_DMABase_DIER, TIM1_DMABase_SR, TIM_DMABase_EGR, + * TIM_DMABase_CCMR1, TIM_DMABase_CCMR2, TIM_DMABase_CCER, + * TIM_DMABase_CNT, TIM_DMABase_PSC, TIM_DMABase_ARR, + * TIM_DMABase_RCR, TIM_DMABase_CCR1, TIM_DMABase_CCR2, + * TIM_DMABase_CCR3, TIM_DMABase_CCR4, TIM_DMABase_BDTR, + * TIM_DMABase_DCR. + * @param TIM_DMABurstLength: DMA Burst length. + * This parameter can be one value between: + * TIM_DMABurstLength_1Transfer and TIM_DMABurstLength_18Transfers. + * @retval None + */ +void TIM_DMAConfig(TIM_TypeDef* TIMx, uint16_t TIM_DMABase, uint16_t TIM_DMABurstLength) +{ + /* Check the parameters */ + assert_param(IS_TIM_LIST4_PERIPH(TIMx)); + assert_param(IS_TIM_DMA_BASE(TIM_DMABase)); + assert_param(IS_TIM_DMA_LENGTH(TIM_DMABurstLength)); + /* Set the DMA Base and the DMA Burst Length */ + TIMx->DCR = TIM_DMABase | TIM_DMABurstLength; +} + +/** + * @brief Enables or disables the TIMx's DMA Requests. + * @param TIMx: where x can be 1, 2, 3, 4, 5, 6, 7, 8, 15, 16 or 17 + * to select the TIM peripheral. + * @param TIM_DMASource: specifies the DMA Request sources. + * This parameter can be any combination of the following values: + * @arg TIM_DMA_Update: TIM update Interrupt source + * @arg TIM_DMA_CC1: TIM Capture Compare 1 DMA source + * @arg TIM_DMA_CC2: TIM Capture Compare 2 DMA source + * @arg TIM_DMA_CC3: TIM Capture Compare 3 DMA source + * @arg TIM_DMA_CC4: TIM Capture Compare 4 DMA source + * @arg TIM_DMA_COM: TIM Commutation DMA source + * @arg TIM_DMA_Trigger: TIM Trigger DMA source + * @param NewState: new state of the DMA Request sources. + * This parameter can be: ENABLE or DISABLE. + * @retval None + */ +void TIM_DMACmd(TIM_TypeDef* TIMx, uint16_t TIM_DMASource, FunctionalState NewState) +{ + /* Check the parameters */ + assert_param(IS_TIM_LIST9_PERIPH(TIMx)); + assert_param(IS_TIM_DMA_SOURCE(TIM_DMASource)); + assert_param(IS_FUNCTIONAL_STATE(NewState)); + + if (NewState != DISABLE) + { + /* Enable the DMA sources */ + TIMx->DIER |= TIM_DMASource; + } + else + { + /* Disable the DMA sources */ + TIMx->DIER &= (uint16_t)~TIM_DMASource; + } +} + +/** + * @brief Configures the TIMx internal Clock + * @param TIMx: where x can be 1, 2, 3, 4, 5, 8, 9, 12 or 15 + * to select the TIM peripheral. + * @retval None + */ +void TIM_InternalClockConfig(TIM_TypeDef* TIMx) +{ + /* Check the parameters */ + assert_param(IS_TIM_LIST6_PERIPH(TIMx)); + /* Disable slave mode to clock the prescaler directly with the internal clock */ + TIMx->SMCR &= (uint16_t)(~((uint16_t)TIM_SMCR_SMS)); +} + +/** + * @brief Configures the TIMx Internal Trigger as External Clock + * @param TIMx: where x can be 1, 2, 3, 4, 5, 9, 12 or 15 to select the TIM peripheral. + * @param TIM_ITRSource: Trigger source. + * This parameter can be one of the following values: + * @param TIM_TS_ITR0: Internal Trigger 0 + * @param TIM_TS_ITR1: Internal Trigger 1 + * @param TIM_TS_ITR2: Internal Trigger 2 + * @param TIM_TS_ITR3: Internal Trigger 3 + * @retval None + */ +void TIM_ITRxExternalClockConfig(TIM_TypeDef* TIMx, uint16_t TIM_InputTriggerSource) +{ + /* Check the parameters */ + assert_param(IS_TIM_LIST6_PERIPH(TIMx)); + assert_param(IS_TIM_INTERNAL_TRIGGER_SELECTION(TIM_InputTriggerSource)); + /* Select the Internal Trigger */ + TIM_SelectInputTrigger(TIMx, TIM_InputTriggerSource); + /* Select the External clock mode1 */ + TIMx->SMCR |= TIM_SlaveMode_External1; +} + +/** + * @brief Configures the TIMx Trigger as External Clock + * @param TIMx: where x can be 1, 2, 3, 4, 5, 9, 12 or 15 to select the TIM peripheral. + * @param TIM_TIxExternalCLKSource: Trigger source. + * This parameter can be one of the following values: + * @arg TIM_TIxExternalCLK1Source_TI1ED: TI1 Edge Detector + * @arg TIM_TIxExternalCLK1Source_TI1: Filtered Timer Input 1 + * @arg TIM_TIxExternalCLK1Source_TI2: Filtered Timer Input 2 + * @param TIM_ICPolarity: specifies the TIx Polarity. + * This parameter can be one of the following values: + * @arg TIM_ICPolarity_Rising + * @arg TIM_ICPolarity_Falling + * @param ICFilter : specifies the filter value. + * This parameter must be a value between 0x0 and 0xF. + * @retval None + */ +void TIM_TIxExternalClockConfig(TIM_TypeDef* TIMx, uint16_t TIM_TIxExternalCLKSource, + uint16_t TIM_ICPolarity, uint16_t ICFilter) +{ + /* Check the parameters */ + assert_param(IS_TIM_LIST6_PERIPH(TIMx)); + assert_param(IS_TIM_TIXCLK_SOURCE(TIM_TIxExternalCLKSource)); + assert_param(IS_TIM_IC_POLARITY(TIM_ICPolarity)); + assert_param(IS_TIM_IC_FILTER(ICFilter)); + /* Configure the Timer Input Clock Source */ + if (TIM_TIxExternalCLKSource == TIM_TIxExternalCLK1Source_TI2) + { + TI2_Config(TIMx, TIM_ICPolarity, TIM_ICSelection_DirectTI, ICFilter); + } + else + { + TI1_Config(TIMx, TIM_ICPolarity, TIM_ICSelection_DirectTI, ICFilter); + } + /* Select the Trigger source */ + TIM_SelectInputTrigger(TIMx, TIM_TIxExternalCLKSource); + /* Select the External clock mode1 */ + TIMx->SMCR |= TIM_SlaveMode_External1; +} + +/** + * @brief Configures the External clock Mode1 + * @param TIMx: where x can be 1, 2, 3, 4, 5 or 8 to select the TIM peripheral. + * @param TIM_ExtTRGPrescaler: The external Trigger Prescaler. + * This parameter can be one of the following values: + * @arg TIM_ExtTRGPSC_OFF: ETRP Prescaler OFF. + * @arg TIM_ExtTRGPSC_DIV2: ETRP frequency divided by 2. + * @arg TIM_ExtTRGPSC_DIV4: ETRP frequency divided by 4. + * @arg TIM_ExtTRGPSC_DIV8: ETRP frequency divided by 8. + * @param TIM_ExtTRGPolarity: The external Trigger Polarity. + * This parameter can be one of the following values: + * @arg TIM_ExtTRGPolarity_Inverted: active low or falling edge active. + * @arg TIM_ExtTRGPolarity_NonInverted: active high or rising edge active. + * @param ExtTRGFilter: External Trigger Filter. + * This parameter must be a value between 0x00 and 0x0F + * @retval None + */ +void TIM_ETRClockMode1Config(TIM_TypeDef* TIMx, uint16_t TIM_ExtTRGPrescaler, uint16_t TIM_ExtTRGPolarity, + uint16_t ExtTRGFilter) +{ + uint16_t tmpsmcr = 0; + /* Check the parameters */ + assert_param(IS_TIM_LIST3_PERIPH(TIMx)); + assert_param(IS_TIM_EXT_PRESCALER(TIM_ExtTRGPrescaler)); + assert_param(IS_TIM_EXT_POLARITY(TIM_ExtTRGPolarity)); + assert_param(IS_TIM_EXT_FILTER(ExtTRGFilter)); + /* Configure the ETR Clock source */ + TIM_ETRConfig(TIMx, TIM_ExtTRGPrescaler, TIM_ExtTRGPolarity, ExtTRGFilter); + + /* Get the TIMx SMCR register value */ + tmpsmcr = TIMx->SMCR; + /* Reset the SMS Bits */ + tmpsmcr &= (uint16_t)(~((uint16_t)TIM_SMCR_SMS)); + /* Select the External clock mode1 */ + tmpsmcr |= TIM_SlaveMode_External1; + /* Select the Trigger selection : ETRF */ + tmpsmcr &= (uint16_t)(~((uint16_t)TIM_SMCR_TS)); + tmpsmcr |= TIM_TS_ETRF; + /* Write to TIMx SMCR */ + TIMx->SMCR = tmpsmcr; +} + +/** + * @brief Configures the External clock Mode2 + * @param TIMx: where x can be 1, 2, 3, 4, 5 or 8 to select the TIM peripheral. + * @param TIM_ExtTRGPrescaler: The external Trigger Prescaler. + * This parameter can be one of the following values: + * @arg TIM_ExtTRGPSC_OFF: ETRP Prescaler OFF. + * @arg TIM_ExtTRGPSC_DIV2: ETRP frequency divided by 2. + * @arg TIM_ExtTRGPSC_DIV4: ETRP frequency divided by 4. + * @arg TIM_ExtTRGPSC_DIV8: ETRP frequency divided by 8. + * @param TIM_ExtTRGPolarity: The external Trigger Polarity. + * This parameter can be one of the following values: + * @arg TIM_ExtTRGPolarity_Inverted: active low or falling edge active. + * @arg TIM_ExtTRGPolarity_NonInverted: active high or rising edge active. + * @param ExtTRGFilter: External Trigger Filter. + * This parameter must be a value between 0x00 and 0x0F + * @retval None + */ +void TIM_ETRClockMode2Config(TIM_TypeDef* TIMx, uint16_t TIM_ExtTRGPrescaler, + uint16_t TIM_ExtTRGPolarity, uint16_t ExtTRGFilter) +{ + /* Check the parameters */ + assert_param(IS_TIM_LIST3_PERIPH(TIMx)); + assert_param(IS_TIM_EXT_PRESCALER(TIM_ExtTRGPrescaler)); + assert_param(IS_TIM_EXT_POLARITY(TIM_ExtTRGPolarity)); + assert_param(IS_TIM_EXT_FILTER(ExtTRGFilter)); + /* Configure the ETR Clock source */ + TIM_ETRConfig(TIMx, TIM_ExtTRGPrescaler, TIM_ExtTRGPolarity, ExtTRGFilter); + /* Enable the External clock mode2 */ + TIMx->SMCR |= TIM_SMCR_ECE; +} + +/** + * @brief Configures the TIMx External Trigger (ETR). + * @param TIMx: where x can be 1, 2, 3, 4, 5 or 8 to select the TIM peripheral. + * @param TIM_ExtTRGPrescaler: The external Trigger Prescaler. + * This parameter can be one of the following values: + * @arg TIM_ExtTRGPSC_OFF: ETRP Prescaler OFF. + * @arg TIM_ExtTRGPSC_DIV2: ETRP frequency divided by 2. + * @arg TIM_ExtTRGPSC_DIV4: ETRP frequency divided by 4. + * @arg TIM_ExtTRGPSC_DIV8: ETRP frequency divided by 8. + * @param TIM_ExtTRGPolarity: The external Trigger Polarity. + * This parameter can be one of the following values: + * @arg TIM_ExtTRGPolarity_Inverted: active low or falling edge active. + * @arg TIM_ExtTRGPolarity_NonInverted: active high or rising edge active. + * @param ExtTRGFilter: External Trigger Filter. + * This parameter must be a value between 0x00 and 0x0F + * @retval None + */ +void TIM_ETRConfig(TIM_TypeDef* TIMx, uint16_t TIM_ExtTRGPrescaler, uint16_t TIM_ExtTRGPolarity, + uint16_t ExtTRGFilter) +{ + uint16_t tmpsmcr = 0; + /* Check the parameters */ + assert_param(IS_TIM_LIST3_PERIPH(TIMx)); + assert_param(IS_TIM_EXT_PRESCALER(TIM_ExtTRGPrescaler)); + assert_param(IS_TIM_EXT_POLARITY(TIM_ExtTRGPolarity)); + assert_param(IS_TIM_EXT_FILTER(ExtTRGFilter)); + tmpsmcr = TIMx->SMCR; + /* Reset the ETR Bits */ + tmpsmcr &= SMCR_ETR_Mask; + /* Set the Prescaler, the Filter value and the Polarity */ + tmpsmcr |= (uint16_t)(TIM_ExtTRGPrescaler | (uint16_t)(TIM_ExtTRGPolarity | (uint16_t)(ExtTRGFilter << (uint16_t)8))); + /* Write to TIMx SMCR */ + TIMx->SMCR = tmpsmcr; +} + +/** + * @brief Configures the TIMx Prescaler. + * @param TIMx: where x can be 1 to 17 to select the TIM peripheral. + * @param Prescaler: specifies the Prescaler Register value + * @param TIM_PSCReloadMode: specifies the TIM Prescaler Reload mode + * This parameter can be one of the following values: + * @arg TIM_PSCReloadMode_Update: The Prescaler is loaded at the update event. + * @arg TIM_PSCReloadMode_Immediate: The Prescaler is loaded immediately. + * @retval None + */ +void TIM_PrescalerConfig(TIM_TypeDef* TIMx, uint16_t Prescaler, uint16_t TIM_PSCReloadMode) +{ + /* Check the parameters */ + assert_param(IS_TIM_ALL_PERIPH(TIMx)); + assert_param(IS_TIM_PRESCALER_RELOAD(TIM_PSCReloadMode)); + /* Set the Prescaler value */ + TIMx->PSC = Prescaler; + /* Set or reset the UG Bit */ + TIMx->EGR = TIM_PSCReloadMode; +} + +/** + * @brief Specifies the TIMx Counter Mode to be used. + * @param TIMx: where x can be 1, 2, 3, 4, 5 or 8 to select the TIM peripheral. + * @param TIM_CounterMode: specifies the Counter Mode to be used + * This parameter can be one of the following values: + * @arg TIM_CounterMode_Up: TIM Up Counting Mode + * @arg TIM_CounterMode_Down: TIM Down Counting Mode + * @arg TIM_CounterMode_CenterAligned1: TIM Center Aligned Mode1 + * @arg TIM_CounterMode_CenterAligned2: TIM Center Aligned Mode2 + * @arg TIM_CounterMode_CenterAligned3: TIM Center Aligned Mode3 + * @retval None + */ +void TIM_CounterModeConfig(TIM_TypeDef* TIMx, uint16_t TIM_CounterMode) +{ + uint16_t tmpcr1 = 0; + /* Check the parameters */ + assert_param(IS_TIM_LIST3_PERIPH(TIMx)); + assert_param(IS_TIM_COUNTER_MODE(TIM_CounterMode)); + tmpcr1 = TIMx->CR1; + /* Reset the CMS and DIR Bits */ + tmpcr1 &= (uint16_t)(~((uint16_t)(TIM_CR1_DIR | TIM_CR1_CMS))); + /* Set the Counter Mode */ + tmpcr1 |= TIM_CounterMode; + /* Write to TIMx CR1 register */ + TIMx->CR1 = tmpcr1; +} + +/** + * @brief Selects the Input Trigger source + * @param TIMx: where x can be 1, 2, 3, 4, 5, 8, 9, 12 or 15 to select the TIM peripheral. + * @param TIM_InputTriggerSource: The Input Trigger source. + * This parameter can be one of the following values: + * @arg TIM_TS_ITR0: Internal Trigger 0 + * @arg TIM_TS_ITR1: Internal Trigger 1 + * @arg TIM_TS_ITR2: Internal Trigger 2 + * @arg TIM_TS_ITR3: Internal Trigger 3 + * @arg TIM_TS_TI1F_ED: TI1 Edge Detector + * @arg TIM_TS_TI1FP1: Filtered Timer Input 1 + * @arg TIM_TS_TI2FP2: Filtered Timer Input 2 + * @arg TIM_TS_ETRF: External Trigger input + * @retval None + */ +void TIM_SelectInputTrigger(TIM_TypeDef* TIMx, uint16_t TIM_InputTriggerSource) +{ + uint16_t tmpsmcr = 0; + /* Check the parameters */ + assert_param(IS_TIM_LIST6_PERIPH(TIMx)); + assert_param(IS_TIM_TRIGGER_SELECTION(TIM_InputTriggerSource)); + /* Get the TIMx SMCR register value */ + tmpsmcr = TIMx->SMCR; + /* Reset the TS Bits */ + tmpsmcr &= (uint16_t)(~((uint16_t)TIM_SMCR_TS)); + /* Set the Input Trigger source */ + tmpsmcr |= TIM_InputTriggerSource; + /* Write to TIMx SMCR */ + TIMx->SMCR = tmpsmcr; +} + +/** + * @brief Configures the TIMx Encoder Interface. + * @param TIMx: where x can be 1, 2, 3, 4, 5 or 8 to select the TIM peripheral. + * @param TIM_EncoderMode: specifies the TIMx Encoder Mode. + * This parameter can be one of the following values: + * @arg TIM_EncoderMode_TI1: Counter counts on TI1FP1 edge depending on TI2FP2 level. + * @arg TIM_EncoderMode_TI2: Counter counts on TI2FP2 edge depending on TI1FP1 level. + * @arg TIM_EncoderMode_TI12: Counter counts on both TI1FP1 and TI2FP2 edges depending + * on the level of the other input. + * @param TIM_IC1Polarity: specifies the IC1 Polarity + * This parameter can be one of the following values: + * @arg TIM_ICPolarity_Falling: IC Falling edge. + * @arg TIM_ICPolarity_Rising: IC Rising edge. + * @param TIM_IC2Polarity: specifies the IC2 Polarity + * This parameter can be one of the following values: + * @arg TIM_ICPolarity_Falling: IC Falling edge. + * @arg TIM_ICPolarity_Rising: IC Rising edge. + * @retval None + */ +void TIM_EncoderInterfaceConfig(TIM_TypeDef* TIMx, uint16_t TIM_EncoderMode, + uint16_t TIM_IC1Polarity, uint16_t TIM_IC2Polarity) +{ + uint16_t tmpsmcr = 0; + uint16_t tmpccmr1 = 0; + uint16_t tmpccer = 0; + + /* Check the parameters */ + assert_param(IS_TIM_LIST5_PERIPH(TIMx)); + assert_param(IS_TIM_ENCODER_MODE(TIM_EncoderMode)); + assert_param(IS_TIM_IC_POLARITY(TIM_IC1Polarity)); + assert_param(IS_TIM_IC_POLARITY(TIM_IC2Polarity)); + + /* Get the TIMx SMCR register value */ + tmpsmcr = TIMx->SMCR; + + /* Get the TIMx CCMR1 register value */ + tmpccmr1 = TIMx->CCMR1; + + /* Get the TIMx CCER register value */ + tmpccer = TIMx->CCER; + + /* Set the encoder Mode */ + tmpsmcr &= (uint16_t)(~((uint16_t)TIM_SMCR_SMS)); + tmpsmcr |= TIM_EncoderMode; + + /* Select the Capture Compare 1 and the Capture Compare 2 as input */ + tmpccmr1 &= (uint16_t)(((uint16_t)~((uint16_t)TIM_CCMR1_CC1S)) & (uint16_t)(~((uint16_t)TIM_CCMR1_CC2S))); + tmpccmr1 |= TIM_CCMR1_CC1S_0 | TIM_CCMR1_CC2S_0; + + /* Set the TI1 and the TI2 Polarities */ + tmpccer &= (uint16_t)(((uint16_t)~((uint16_t)TIM_CCER_CC1P)) & ((uint16_t)~((uint16_t)TIM_CCER_CC2P))); + tmpccer |= (uint16_t)(TIM_IC1Polarity | (uint16_t)(TIM_IC2Polarity << (uint16_t)4)); + + /* Write to TIMx SMCR */ + TIMx->SMCR = tmpsmcr; + /* Write to TIMx CCMR1 */ + TIMx->CCMR1 = tmpccmr1; + /* Write to TIMx CCER */ + TIMx->CCER = tmpccer; +} + +/** + * @brief Forces the TIMx output 1 waveform to active or inactive level. + * @param TIMx: where x can be 1 to 17 except 6 and 7 to select the TIM peripheral. + * @param TIM_ForcedAction: specifies the forced Action to be set to the output waveform. + * This parameter can be one of the following values: + * @arg TIM_ForcedAction_Active: Force active level on OC1REF + * @arg TIM_ForcedAction_InActive: Force inactive level on OC1REF. + * @retval None + */ +void TIM_ForcedOC1Config(TIM_TypeDef* TIMx, uint16_t TIM_ForcedAction) +{ + uint16_t tmpccmr1 = 0; + /* Check the parameters */ + assert_param(IS_TIM_LIST8_PERIPH(TIMx)); + assert_param(IS_TIM_FORCED_ACTION(TIM_ForcedAction)); + tmpccmr1 = TIMx->CCMR1; + /* Reset the OC1M Bits */ + tmpccmr1 &= (uint16_t)~((uint16_t)TIM_CCMR1_OC1M); + /* Configure The Forced output Mode */ + tmpccmr1 |= TIM_ForcedAction; + /* Write to TIMx CCMR1 register */ + TIMx->CCMR1 = tmpccmr1; +} + +/** + * @brief Forces the TIMx output 2 waveform to active or inactive level. + * @param TIMx: where x can be 1, 2, 3, 4, 5, 8, 9, 12 or 15 to select the TIM peripheral. + * @param TIM_ForcedAction: specifies the forced Action to be set to the output waveform. + * This parameter can be one of the following values: + * @arg TIM_ForcedAction_Active: Force active level on OC2REF + * @arg TIM_ForcedAction_InActive: Force inactive level on OC2REF. + * @retval None + */ +void TIM_ForcedOC2Config(TIM_TypeDef* TIMx, uint16_t TIM_ForcedAction) +{ + uint16_t tmpccmr1 = 0; + /* Check the parameters */ + assert_param(IS_TIM_LIST6_PERIPH(TIMx)); + assert_param(IS_TIM_FORCED_ACTION(TIM_ForcedAction)); + tmpccmr1 = TIMx->CCMR1; + /* Reset the OC2M Bits */ + tmpccmr1 &= (uint16_t)~((uint16_t)TIM_CCMR1_OC2M); + /* Configure The Forced output Mode */ + tmpccmr1 |= (uint16_t)(TIM_ForcedAction << 8); + /* Write to TIMx CCMR1 register */ + TIMx->CCMR1 = tmpccmr1; +} + +/** + * @brief Forces the TIMx output 3 waveform to active or inactive level. + * @param TIMx: where x can be 1, 2, 3, 4, 5 or 8 to select the TIM peripheral. + * @param TIM_ForcedAction: specifies the forced Action to be set to the output waveform. + * This parameter can be one of the following values: + * @arg TIM_ForcedAction_Active: Force active level on OC3REF + * @arg TIM_ForcedAction_InActive: Force inactive level on OC3REF. + * @retval None + */ +void TIM_ForcedOC3Config(TIM_TypeDef* TIMx, uint16_t TIM_ForcedAction) +{ + uint16_t tmpccmr2 = 0; + /* Check the parameters */ + assert_param(IS_TIM_LIST3_PERIPH(TIMx)); + assert_param(IS_TIM_FORCED_ACTION(TIM_ForcedAction)); + tmpccmr2 = TIMx->CCMR2; + /* Reset the OC1M Bits */ + tmpccmr2 &= (uint16_t)~((uint16_t)TIM_CCMR2_OC3M); + /* Configure The Forced output Mode */ + tmpccmr2 |= TIM_ForcedAction; + /* Write to TIMx CCMR2 register */ + TIMx->CCMR2 = tmpccmr2; +} + +/** + * @brief Forces the TIMx output 4 waveform to active or inactive level. + * @param TIMx: where x can be 1, 2, 3, 4, 5 or 8 to select the TIM peripheral. + * @param TIM_ForcedAction: specifies the forced Action to be set to the output waveform. + * This parameter can be one of the following values: + * @arg TIM_ForcedAction_Active: Force active level on OC4REF + * @arg TIM_ForcedAction_InActive: Force inactive level on OC4REF. + * @retval None + */ +void TIM_ForcedOC4Config(TIM_TypeDef* TIMx, uint16_t TIM_ForcedAction) +{ + uint16_t tmpccmr2 = 0; + /* Check the parameters */ + assert_param(IS_TIM_LIST3_PERIPH(TIMx)); + assert_param(IS_TIM_FORCED_ACTION(TIM_ForcedAction)); + tmpccmr2 = TIMx->CCMR2; + /* Reset the OC2M Bits */ + tmpccmr2 &= (uint16_t)~((uint16_t)TIM_CCMR2_OC4M); + /* Configure The Forced output Mode */ + tmpccmr2 |= (uint16_t)(TIM_ForcedAction << 8); + /* Write to TIMx CCMR2 register */ + TIMx->CCMR2 = tmpccmr2; +} + +/** + * @brief Enables or disables TIMx peripheral Preload register on ARR. + * @param TIMx: where x can be 1 to 17 to select the TIM peripheral. + * @param NewState: new state of the TIMx peripheral Preload register + * This parameter can be: ENABLE or DISABLE. + * @retval None + */ +void TIM_ARRPreloadConfig(TIM_TypeDef* TIMx, FunctionalState NewState) +{ + /* Check the parameters */ + assert_param(IS_TIM_ALL_PERIPH(TIMx)); + assert_param(IS_FUNCTIONAL_STATE(NewState)); + if (NewState != DISABLE) + { + /* Set the ARR Preload Bit */ + TIMx->CR1 |= TIM_CR1_ARPE; + } + else + { + /* Reset the ARR Preload Bit */ + TIMx->CR1 &= (uint16_t)~((uint16_t)TIM_CR1_ARPE); + } +} + +/** + * @brief Selects the TIM peripheral Commutation event. + * @param TIMx: where x can be 1, 8, 15, 16 or 17 to select the TIMx peripheral + * @param NewState: new state of the Commutation event. + * This parameter can be: ENABLE or DISABLE. + * @retval None + */ +void TIM_SelectCOM(TIM_TypeDef* TIMx, FunctionalState NewState) +{ + /* Check the parameters */ + assert_param(IS_TIM_LIST2_PERIPH(TIMx)); + assert_param(IS_FUNCTIONAL_STATE(NewState)); + if (NewState != DISABLE) + { + /* Set the COM Bit */ + TIMx->CR2 |= TIM_CR2_CCUS; + } + else + { + /* Reset the COM Bit */ + TIMx->CR2 &= (uint16_t)~((uint16_t)TIM_CR2_CCUS); + } +} + +/** + * @brief Selects the TIMx peripheral Capture Compare DMA source. + * @param TIMx: where x can be 1, 2, 3, 4, 5, 8, 15, 16 or 17 to select + * the TIM peripheral. + * @param NewState: new state of the Capture Compare DMA source + * This parameter can be: ENABLE or DISABLE. + * @retval None + */ +void TIM_SelectCCDMA(TIM_TypeDef* TIMx, FunctionalState NewState) +{ + /* Check the parameters */ + assert_param(IS_TIM_LIST4_PERIPH(TIMx)); + assert_param(IS_FUNCTIONAL_STATE(NewState)); + if (NewState != DISABLE) + { + /* Set the CCDS Bit */ + TIMx->CR2 |= TIM_CR2_CCDS; + } + else + { + /* Reset the CCDS Bit */ + TIMx->CR2 &= (uint16_t)~((uint16_t)TIM_CR2_CCDS); + } +} + +/** + * @brief Sets or Resets the TIM peripheral Capture Compare Preload Control bit. + * @param TIMx: where x can be 1, 2, 3, 4, 5, 8 or 15 + * to select the TIMx peripheral + * @param NewState: new state of the Capture Compare Preload Control bit + * This parameter can be: ENABLE or DISABLE. + * @retval None + */ +void TIM_CCPreloadControl(TIM_TypeDef* TIMx, FunctionalState NewState) +{ + /* Check the parameters */ + assert_param(IS_TIM_LIST5_PERIPH(TIMx)); + assert_param(IS_FUNCTIONAL_STATE(NewState)); + if (NewState != DISABLE) + { + /* Set the CCPC Bit */ + TIMx->CR2 |= TIM_CR2_CCPC; + } + else + { + /* Reset the CCPC Bit */ + TIMx->CR2 &= (uint16_t)~((uint16_t)TIM_CR2_CCPC); + } +} + +/** + * @brief Enables or disables the TIMx peripheral Preload register on CCR1. + * @param TIMx: where x can be 1 to 17 except 6 and 7 to select the TIM peripheral. + * @param TIM_OCPreload: new state of the TIMx peripheral Preload register + * This parameter can be one of the following values: + * @arg TIM_OCPreload_Enable + * @arg TIM_OCPreload_Disable + * @retval None + */ +void TIM_OC1PreloadConfig(TIM_TypeDef* TIMx, uint16_t TIM_OCPreload) +{ + uint16_t tmpccmr1 = 0; + /* Check the parameters */ + assert_param(IS_TIM_LIST8_PERIPH(TIMx)); + assert_param(IS_TIM_OCPRELOAD_STATE(TIM_OCPreload)); + tmpccmr1 = TIMx->CCMR1; + /* Reset the OC1PE Bit */ + tmpccmr1 &= (uint16_t)~((uint16_t)TIM_CCMR1_OC1PE); + /* Enable or Disable the Output Compare Preload feature */ + tmpccmr1 |= TIM_OCPreload; + /* Write to TIMx CCMR1 register */ + TIMx->CCMR1 = tmpccmr1; +} + +/** + * @brief Enables or disables the TIMx peripheral Preload register on CCR2. + * @param TIMx: where x can be 1, 2, 3, 4, 5, 8, 9, 12 or 15 to select + * the TIM peripheral. + * @param TIM_OCPreload: new state of the TIMx peripheral Preload register + * This parameter can be one of the following values: + * @arg TIM_OCPreload_Enable + * @arg TIM_OCPreload_Disable + * @retval None + */ +void TIM_OC2PreloadConfig(TIM_TypeDef* TIMx, uint16_t TIM_OCPreload) +{ + uint16_t tmpccmr1 = 0; + /* Check the parameters */ + assert_param(IS_TIM_LIST6_PERIPH(TIMx)); + assert_param(IS_TIM_OCPRELOAD_STATE(TIM_OCPreload)); + tmpccmr1 = TIMx->CCMR1; + /* Reset the OC2PE Bit */ + tmpccmr1 &= (uint16_t)~((uint16_t)TIM_CCMR1_OC2PE); + /* Enable or Disable the Output Compare Preload feature */ + tmpccmr1 |= (uint16_t)(TIM_OCPreload << 8); + /* Write to TIMx CCMR1 register */ + TIMx->CCMR1 = tmpccmr1; +} + +/** + * @brief Enables or disables the TIMx peripheral Preload register on CCR3. + * @param TIMx: where x can be 1, 2, 3, 4, 5 or 8 to select the TIM peripheral. + * @param TIM_OCPreload: new state of the TIMx peripheral Preload register + * This parameter can be one of the following values: + * @arg TIM_OCPreload_Enable + * @arg TIM_OCPreload_Disable + * @retval None + */ +void TIM_OC3PreloadConfig(TIM_TypeDef* TIMx, uint16_t TIM_OCPreload) +{ + uint16_t tmpccmr2 = 0; + /* Check the parameters */ + assert_param(IS_TIM_LIST3_PERIPH(TIMx)); + assert_param(IS_TIM_OCPRELOAD_STATE(TIM_OCPreload)); + tmpccmr2 = TIMx->CCMR2; + /* Reset the OC3PE Bit */ + tmpccmr2 &= (uint16_t)~((uint16_t)TIM_CCMR2_OC3PE); + /* Enable or Disable the Output Compare Preload feature */ + tmpccmr2 |= TIM_OCPreload; + /* Write to TIMx CCMR2 register */ + TIMx->CCMR2 = tmpccmr2; +} + +/** + * @brief Enables or disables the TIMx peripheral Preload register on CCR4. + * @param TIMx: where x can be 1, 2, 3, 4, 5 or 8 to select the TIM peripheral. + * @param TIM_OCPreload: new state of the TIMx peripheral Preload register + * This parameter can be one of the following values: + * @arg TIM_OCPreload_Enable + * @arg TIM_OCPreload_Disable + * @retval None + */ +void TIM_OC4PreloadConfig(TIM_TypeDef* TIMx, uint16_t TIM_OCPreload) +{ + uint16_t tmpccmr2 = 0; + /* Check the parameters */ + assert_param(IS_TIM_LIST3_PERIPH(TIMx)); + assert_param(IS_TIM_OCPRELOAD_STATE(TIM_OCPreload)); + tmpccmr2 = TIMx->CCMR2; + /* Reset the OC4PE Bit */ + tmpccmr2 &= (uint16_t)~((uint16_t)TIM_CCMR2_OC4PE); + /* Enable or Disable the Output Compare Preload feature */ + tmpccmr2 |= (uint16_t)(TIM_OCPreload << 8); + /* Write to TIMx CCMR2 register */ + TIMx->CCMR2 = tmpccmr2; +} + +/** + * @brief Configures the TIMx Output Compare 1 Fast feature. + * @param TIMx: where x can be 1 to 17 except 6 and 7 to select the TIM peripheral. + * @param TIM_OCFast: new state of the Output Compare Fast Enable Bit. + * This parameter can be one of the following values: + * @arg TIM_OCFast_Enable: TIM output compare fast enable + * @arg TIM_OCFast_Disable: TIM output compare fast disable + * @retval None + */ +void TIM_OC1FastConfig(TIM_TypeDef* TIMx, uint16_t TIM_OCFast) +{ + uint16_t tmpccmr1 = 0; + /* Check the parameters */ + assert_param(IS_TIM_LIST8_PERIPH(TIMx)); + assert_param(IS_TIM_OCFAST_STATE(TIM_OCFast)); + /* Get the TIMx CCMR1 register value */ + tmpccmr1 = TIMx->CCMR1; + /* Reset the OC1FE Bit */ + tmpccmr1 &= (uint16_t)~((uint16_t)TIM_CCMR1_OC1FE); + /* Enable or Disable the Output Compare Fast Bit */ + tmpccmr1 |= TIM_OCFast; + /* Write to TIMx CCMR1 */ + TIMx->CCMR1 = tmpccmr1; +} + +/** + * @brief Configures the TIMx Output Compare 2 Fast feature. + * @param TIMx: where x can be 1, 2, 3, 4, 5, 8, 9, 12 or 15 to select + * the TIM peripheral. + * @param TIM_OCFast: new state of the Output Compare Fast Enable Bit. + * This parameter can be one of the following values: + * @arg TIM_OCFast_Enable: TIM output compare fast enable + * @arg TIM_OCFast_Disable: TIM output compare fast disable + * @retval None + */ +void TIM_OC2FastConfig(TIM_TypeDef* TIMx, uint16_t TIM_OCFast) +{ + uint16_t tmpccmr1 = 0; + /* Check the parameters */ + assert_param(IS_TIM_LIST6_PERIPH(TIMx)); + assert_param(IS_TIM_OCFAST_STATE(TIM_OCFast)); + /* Get the TIMx CCMR1 register value */ + tmpccmr1 = TIMx->CCMR1; + /* Reset the OC2FE Bit */ + tmpccmr1 &= (uint16_t)~((uint16_t)TIM_CCMR1_OC2FE); + /* Enable or Disable the Output Compare Fast Bit */ + tmpccmr1 |= (uint16_t)(TIM_OCFast << 8); + /* Write to TIMx CCMR1 */ + TIMx->CCMR1 = tmpccmr1; +} + +/** + * @brief Configures the TIMx Output Compare 3 Fast feature. + * @param TIMx: where x can be 1, 2, 3, 4, 5 or 8 to select the TIM peripheral. + * @param TIM_OCFast: new state of the Output Compare Fast Enable Bit. + * This parameter can be one of the following values: + * @arg TIM_OCFast_Enable: TIM output compare fast enable + * @arg TIM_OCFast_Disable: TIM output compare fast disable + * @retval None + */ +void TIM_OC3FastConfig(TIM_TypeDef* TIMx, uint16_t TIM_OCFast) +{ + uint16_t tmpccmr2 = 0; + /* Check the parameters */ + assert_param(IS_TIM_LIST3_PERIPH(TIMx)); + assert_param(IS_TIM_OCFAST_STATE(TIM_OCFast)); + /* Get the TIMx CCMR2 register value */ + tmpccmr2 = TIMx->CCMR2; + /* Reset the OC3FE Bit */ + tmpccmr2 &= (uint16_t)~((uint16_t)TIM_CCMR2_OC3FE); + /* Enable or Disable the Output Compare Fast Bit */ + tmpccmr2 |= TIM_OCFast; + /* Write to TIMx CCMR2 */ + TIMx->CCMR2 = tmpccmr2; +} + +/** + * @brief Configures the TIMx Output Compare 4 Fast feature. + * @param TIMx: where x can be 1, 2, 3, 4, 5 or 8 to select the TIM peripheral. + * @param TIM_OCFast: new state of the Output Compare Fast Enable Bit. + * This parameter can be one of the following values: + * @arg TIM_OCFast_Enable: TIM output compare fast enable + * @arg TIM_OCFast_Disable: TIM output compare fast disable + * @retval None + */ +void TIM_OC4FastConfig(TIM_TypeDef* TIMx, uint16_t TIM_OCFast) +{ + uint16_t tmpccmr2 = 0; + /* Check the parameters */ + assert_param(IS_TIM_LIST3_PERIPH(TIMx)); + assert_param(IS_TIM_OCFAST_STATE(TIM_OCFast)); + /* Get the TIMx CCMR2 register value */ + tmpccmr2 = TIMx->CCMR2; + /* Reset the OC4FE Bit */ + tmpccmr2 &= (uint16_t)~((uint16_t)TIM_CCMR2_OC4FE); + /* Enable or Disable the Output Compare Fast Bit */ + tmpccmr2 |= (uint16_t)(TIM_OCFast << 8); + /* Write to TIMx CCMR2 */ + TIMx->CCMR2 = tmpccmr2; +} + +/** + * @brief Clears or safeguards the OCREF1 signal on an external event + * @param TIMx: where x can be 1, 2, 3, 4, 5 or 8 to select the TIM peripheral. + * @param TIM_OCClear: new state of the Output Compare Clear Enable Bit. + * This parameter can be one of the following values: + * @arg TIM_OCClear_Enable: TIM Output clear enable + * @arg TIM_OCClear_Disable: TIM Output clear disable + * @retval None + */ +void TIM_ClearOC1Ref(TIM_TypeDef* TIMx, uint16_t TIM_OCClear) +{ + uint16_t tmpccmr1 = 0; + /* Check the parameters */ + assert_param(IS_TIM_LIST3_PERIPH(TIMx)); + assert_param(IS_TIM_OCCLEAR_STATE(TIM_OCClear)); + + tmpccmr1 = TIMx->CCMR1; + + /* Reset the OC1CE Bit */ + tmpccmr1 &= (uint16_t)~((uint16_t)TIM_CCMR1_OC1CE); + /* Enable or Disable the Output Compare Clear Bit */ + tmpccmr1 |= TIM_OCClear; + /* Write to TIMx CCMR1 register */ + TIMx->CCMR1 = tmpccmr1; +} + +/** + * @brief Clears or safeguards the OCREF2 signal on an external event + * @param TIMx: where x can be 1, 2, 3, 4, 5 or 8 to select the TIM peripheral. + * @param TIM_OCClear: new state of the Output Compare Clear Enable Bit. + * This parameter can be one of the following values: + * @arg TIM_OCClear_Enable: TIM Output clear enable + * @arg TIM_OCClear_Disable: TIM Output clear disable + * @retval None + */ +void TIM_ClearOC2Ref(TIM_TypeDef* TIMx, uint16_t TIM_OCClear) +{ + uint16_t tmpccmr1 = 0; + /* Check the parameters */ + assert_param(IS_TIM_LIST3_PERIPH(TIMx)); + assert_param(IS_TIM_OCCLEAR_STATE(TIM_OCClear)); + tmpccmr1 = TIMx->CCMR1; + /* Reset the OC2CE Bit */ + tmpccmr1 &= (uint16_t)~((uint16_t)TIM_CCMR1_OC2CE); + /* Enable or Disable the Output Compare Clear Bit */ + tmpccmr1 |= (uint16_t)(TIM_OCClear << 8); + /* Write to TIMx CCMR1 register */ + TIMx->CCMR1 = tmpccmr1; +} + +/** + * @brief Clears or safeguards the OCREF3 signal on an external event + * @param TIMx: where x can be 1, 2, 3, 4, 5 or 8 to select the TIM peripheral. + * @param TIM_OCClear: new state of the Output Compare Clear Enable Bit. + * This parameter can be one of the following values: + * @arg TIM_OCClear_Enable: TIM Output clear enable + * @arg TIM_OCClear_Disable: TIM Output clear disable + * @retval None + */ +void TIM_ClearOC3Ref(TIM_TypeDef* TIMx, uint16_t TIM_OCClear) +{ + uint16_t tmpccmr2 = 0; + /* Check the parameters */ + assert_param(IS_TIM_LIST3_PERIPH(TIMx)); + assert_param(IS_TIM_OCCLEAR_STATE(TIM_OCClear)); + tmpccmr2 = TIMx->CCMR2; + /* Reset the OC3CE Bit */ + tmpccmr2 &= (uint16_t)~((uint16_t)TIM_CCMR2_OC3CE); + /* Enable or Disable the Output Compare Clear Bit */ + tmpccmr2 |= TIM_OCClear; + /* Write to TIMx CCMR2 register */ + TIMx->CCMR2 = tmpccmr2; +} + +/** + * @brief Clears or safeguards the OCREF4 signal on an external event + * @param TIMx: where x can be 1, 2, 3, 4, 5 or 8 to select the TIM peripheral. + * @param TIM_OCClear: new state of the Output Compare Clear Enable Bit. + * This parameter can be one of the following values: + * @arg TIM_OCClear_Enable: TIM Output clear enable + * @arg TIM_OCClear_Disable: TIM Output clear disable + * @retval None + */ +void TIM_ClearOC4Ref(TIM_TypeDef* TIMx, uint16_t TIM_OCClear) +{ + uint16_t tmpccmr2 = 0; + /* Check the parameters */ + assert_param(IS_TIM_LIST3_PERIPH(TIMx)); + assert_param(IS_TIM_OCCLEAR_STATE(TIM_OCClear)); + tmpccmr2 = TIMx->CCMR2; + /* Reset the OC4CE Bit */ + tmpccmr2 &= (uint16_t)~((uint16_t)TIM_CCMR2_OC4CE); + /* Enable or Disable the Output Compare Clear Bit */ + tmpccmr2 |= (uint16_t)(TIM_OCClear << 8); + /* Write to TIMx CCMR2 register */ + TIMx->CCMR2 = tmpccmr2; +} + +/** + * @brief Configures the TIMx channel 1 polarity. + * @param TIMx: where x can be 1 to 17 except 6 and 7 to select the TIM peripheral. + * @param TIM_OCPolarity: specifies the OC1 Polarity + * This parameter can be one of the following values: + * @arg TIM_OCPolarity_High: Output Compare active high + * @arg TIM_OCPolarity_Low: Output Compare active low + * @retval None + */ +void TIM_OC1PolarityConfig(TIM_TypeDef* TIMx, uint16_t TIM_OCPolarity) +{ + uint16_t tmpccer = 0; + /* Check the parameters */ + assert_param(IS_TIM_LIST8_PERIPH(TIMx)); + assert_param(IS_TIM_OC_POLARITY(TIM_OCPolarity)); + tmpccer = TIMx->CCER; + /* Set or Reset the CC1P Bit */ + tmpccer &= (uint16_t)~((uint16_t)TIM_CCER_CC1P); + tmpccer |= TIM_OCPolarity; + /* Write to TIMx CCER register */ + TIMx->CCER = tmpccer; +} + +/** + * @brief Configures the TIMx Channel 1N polarity. + * @param TIMx: where x can be 1, 8, 15, 16 or 17 to select the TIM peripheral. + * @param TIM_OCNPolarity: specifies the OC1N Polarity + * This parameter can be one of the following values: + * @arg TIM_OCNPolarity_High: Output Compare active high + * @arg TIM_OCNPolarity_Low: Output Compare active low + * @retval None + */ +void TIM_OC1NPolarityConfig(TIM_TypeDef* TIMx, uint16_t TIM_OCNPolarity) +{ + uint16_t tmpccer = 0; + /* Check the parameters */ + assert_param(IS_TIM_LIST2_PERIPH(TIMx)); + assert_param(IS_TIM_OCN_POLARITY(TIM_OCNPolarity)); + + tmpccer = TIMx->CCER; + /* Set or Reset the CC1NP Bit */ + tmpccer &= (uint16_t)~((uint16_t)TIM_CCER_CC1NP); + tmpccer |= TIM_OCNPolarity; + /* Write to TIMx CCER register */ + TIMx->CCER = tmpccer; +} + +/** + * @brief Configures the TIMx channel 2 polarity. + * @param TIMx: where x can be 1, 2, 3, 4, 5, 8, 9, 12 or 15 to select the TIM peripheral. + * @param TIM_OCPolarity: specifies the OC2 Polarity + * This parameter can be one of the following values: + * @arg TIM_OCPolarity_High: Output Compare active high + * @arg TIM_OCPolarity_Low: Output Compare active low + * @retval None + */ +void TIM_OC2PolarityConfig(TIM_TypeDef* TIMx, uint16_t TIM_OCPolarity) +{ + uint16_t tmpccer = 0; + /* Check the parameters */ + assert_param(IS_TIM_LIST6_PERIPH(TIMx)); + assert_param(IS_TIM_OC_POLARITY(TIM_OCPolarity)); + tmpccer = TIMx->CCER; + /* Set or Reset the CC2P Bit */ + tmpccer &= (uint16_t)~((uint16_t)TIM_CCER_CC2P); + tmpccer |= (uint16_t)(TIM_OCPolarity << 4); + /* Write to TIMx CCER register */ + TIMx->CCER = tmpccer; +} + +/** + * @brief Configures the TIMx Channel 2N polarity. + * @param TIMx: where x can be 1 or 8 to select the TIM peripheral. + * @param TIM_OCNPolarity: specifies the OC2N Polarity + * This parameter can be one of the following values: + * @arg TIM_OCNPolarity_High: Output Compare active high + * @arg TIM_OCNPolarity_Low: Output Compare active low + * @retval None + */ +void TIM_OC2NPolarityConfig(TIM_TypeDef* TIMx, uint16_t TIM_OCNPolarity) +{ + uint16_t tmpccer = 0; + /* Check the parameters */ + assert_param(IS_TIM_LIST1_PERIPH(TIMx)); + assert_param(IS_TIM_OCN_POLARITY(TIM_OCNPolarity)); + + tmpccer = TIMx->CCER; + /* Set or Reset the CC2NP Bit */ + tmpccer &= (uint16_t)~((uint16_t)TIM_CCER_CC2NP); + tmpccer |= (uint16_t)(TIM_OCNPolarity << 4); + /* Write to TIMx CCER register */ + TIMx->CCER = tmpccer; +} + +/** + * @brief Configures the TIMx channel 3 polarity. + * @param TIMx: where x can be 1, 2, 3, 4, 5 or 8 to select the TIM peripheral. + * @param TIM_OCPolarity: specifies the OC3 Polarity + * This parameter can be one of the following values: + * @arg TIM_OCPolarity_High: Output Compare active high + * @arg TIM_OCPolarity_Low: Output Compare active low + * @retval None + */ +void TIM_OC3PolarityConfig(TIM_TypeDef* TIMx, uint16_t TIM_OCPolarity) +{ + uint16_t tmpccer = 0; + /* Check the parameters */ + assert_param(IS_TIM_LIST3_PERIPH(TIMx)); + assert_param(IS_TIM_OC_POLARITY(TIM_OCPolarity)); + tmpccer = TIMx->CCER; + /* Set or Reset the CC3P Bit */ + tmpccer &= (uint16_t)~((uint16_t)TIM_CCER_CC3P); + tmpccer |= (uint16_t)(TIM_OCPolarity << 8); + /* Write to TIMx CCER register */ + TIMx->CCER = tmpccer; +} + +/** + * @brief Configures the TIMx Channel 3N polarity. + * @param TIMx: where x can be 1 or 8 to select the TIM peripheral. + * @param TIM_OCNPolarity: specifies the OC3N Polarity + * This parameter can be one of the following values: + * @arg TIM_OCNPolarity_High: Output Compare active high + * @arg TIM_OCNPolarity_Low: Output Compare active low + * @retval None + */ +void TIM_OC3NPolarityConfig(TIM_TypeDef* TIMx, uint16_t TIM_OCNPolarity) +{ + uint16_t tmpccer = 0; + + /* Check the parameters */ + assert_param(IS_TIM_LIST1_PERIPH(TIMx)); + assert_param(IS_TIM_OCN_POLARITY(TIM_OCNPolarity)); + + tmpccer = TIMx->CCER; + /* Set or Reset the CC3NP Bit */ + tmpccer &= (uint16_t)~((uint16_t)TIM_CCER_CC3NP); + tmpccer |= (uint16_t)(TIM_OCNPolarity << 8); + /* Write to TIMx CCER register */ + TIMx->CCER = tmpccer; +} + +/** + * @brief Configures the TIMx channel 4 polarity. + * @param TIMx: where x can be 1, 2, 3, 4, 5 or 8 to select the TIM peripheral. + * @param TIM_OCPolarity: specifies the OC4 Polarity + * This parameter can be one of the following values: + * @arg TIM_OCPolarity_High: Output Compare active high + * @arg TIM_OCPolarity_Low: Output Compare active low + * @retval None + */ +void TIM_OC4PolarityConfig(TIM_TypeDef* TIMx, uint16_t TIM_OCPolarity) +{ + uint16_t tmpccer = 0; + /* Check the parameters */ + assert_param(IS_TIM_LIST3_PERIPH(TIMx)); + assert_param(IS_TIM_OC_POLARITY(TIM_OCPolarity)); + tmpccer = TIMx->CCER; + /* Set or Reset the CC4P Bit */ + tmpccer &= (uint16_t)~((uint16_t)TIM_CCER_CC4P); + tmpccer |= (uint16_t)(TIM_OCPolarity << 12); + /* Write to TIMx CCER register */ + TIMx->CCER = tmpccer; +} + +/** + * @brief Enables or disables the TIM Capture Compare Channel x. + * @param TIMx: where x can be 1 to 17 except 6 and 7 to select the TIM peripheral. + * @param TIM_Channel: specifies the TIM Channel + * This parameter can be one of the following values: + * @arg TIM_Channel_1: TIM Channel 1 + * @arg TIM_Channel_2: TIM Channel 2 + * @arg TIM_Channel_3: TIM Channel 3 + * @arg TIM_Channel_4: TIM Channel 4 + * @param TIM_CCx: specifies the TIM Channel CCxE bit new state. + * This parameter can be: TIM_CCx_Enable or TIM_CCx_Disable. + * @retval None + */ +void TIM_CCxCmd(TIM_TypeDef* TIMx, uint16_t TIM_Channel, uint16_t TIM_CCx) +{ + uint16_t tmp = 0; + + /* Check the parameters */ + assert_param(IS_TIM_LIST8_PERIPH(TIMx)); + assert_param(IS_TIM_CHANNEL(TIM_Channel)); + assert_param(IS_TIM_CCX(TIM_CCx)); + + tmp = CCER_CCE_Set << TIM_Channel; + + /* Reset the CCxE Bit */ + TIMx->CCER &= (uint16_t)~ tmp; + + /* Set or reset the CCxE Bit */ + TIMx->CCER |= (uint16_t)(TIM_CCx << TIM_Channel); +} + +/** + * @brief Enables or disables the TIM Capture Compare Channel xN. + * @param TIMx: where x can be 1, 8, 15, 16 or 17 to select the TIM peripheral. + * @param TIM_Channel: specifies the TIM Channel + * This parameter can be one of the following values: + * @arg TIM_Channel_1: TIM Channel 1 + * @arg TIM_Channel_2: TIM Channel 2 + * @arg TIM_Channel_3: TIM Channel 3 + * @param TIM_CCxN: specifies the TIM Channel CCxNE bit new state. + * This parameter can be: TIM_CCxN_Enable or TIM_CCxN_Disable. + * @retval None + */ +void TIM_CCxNCmd(TIM_TypeDef* TIMx, uint16_t TIM_Channel, uint16_t TIM_CCxN) +{ + uint16_t tmp = 0; + + /* Check the parameters */ + assert_param(IS_TIM_LIST2_PERIPH(TIMx)); + assert_param(IS_TIM_COMPLEMENTARY_CHANNEL(TIM_Channel)); + assert_param(IS_TIM_CCXN(TIM_CCxN)); + + tmp = CCER_CCNE_Set << TIM_Channel; + + /* Reset the CCxNE Bit */ + TIMx->CCER &= (uint16_t) ~tmp; + + /* Set or reset the CCxNE Bit */ + TIMx->CCER |= (uint16_t)(TIM_CCxN << TIM_Channel); +} + +/** + * @brief Selects the TIM Output Compare Mode. + * @note This function disables the selected channel before changing the Output + * Compare Mode. + * User has to enable this channel using TIM_CCxCmd and TIM_CCxNCmd functions. + * @param TIMx: where x can be 1 to 17 except 6 and 7 to select the TIM peripheral. + * @param TIM_Channel: specifies the TIM Channel + * This parameter can be one of the following values: + * @arg TIM_Channel_1: TIM Channel 1 + * @arg TIM_Channel_2: TIM Channel 2 + * @arg TIM_Channel_3: TIM Channel 3 + * @arg TIM_Channel_4: TIM Channel 4 + * @param TIM_OCMode: specifies the TIM Output Compare Mode. + * This parameter can be one of the following values: + * @arg TIM_OCMode_Timing + * @arg TIM_OCMode_Active + * @arg TIM_OCMode_Toggle + * @arg TIM_OCMode_PWM1 + * @arg TIM_OCMode_PWM2 + * @arg TIM_ForcedAction_Active + * @arg TIM_ForcedAction_InActive + * @retval None + */ +void TIM_SelectOCxM(TIM_TypeDef* TIMx, uint16_t TIM_Channel, uint16_t TIM_OCMode) +{ + uint32_t tmp = 0; + uint16_t tmp1 = 0; + + /* Check the parameters */ + assert_param(IS_TIM_LIST8_PERIPH(TIMx)); + assert_param(IS_TIM_CHANNEL(TIM_Channel)); + assert_param(IS_TIM_OCM(TIM_OCMode)); + + tmp = (uint32_t) TIMx; + tmp += CCMR_Offset; + + tmp1 = CCER_CCE_Set << (uint16_t)TIM_Channel; + + /* Disable the Channel: Reset the CCxE Bit */ + TIMx->CCER &= (uint16_t) ~tmp1; + + if((TIM_Channel == TIM_Channel_1) ||(TIM_Channel == TIM_Channel_3)) + { + tmp += (TIM_Channel>>1); + + /* Reset the OCxM bits in the CCMRx register */ + *(__IO uint32_t *) tmp &= (uint32_t)~((uint32_t)TIM_CCMR1_OC1M); + + /* Configure the OCxM bits in the CCMRx register */ + *(__IO uint32_t *) tmp |= TIM_OCMode; + } + else + { + tmp += (uint16_t)(TIM_Channel - (uint16_t)4)>> (uint16_t)1; + + /* Reset the OCxM bits in the CCMRx register */ + *(__IO uint32_t *) tmp &= (uint32_t)~((uint32_t)TIM_CCMR1_OC2M); + + /* Configure the OCxM bits in the CCMRx register */ + *(__IO uint32_t *) tmp |= (uint16_t)(TIM_OCMode << 8); + } +} + +/** + * @brief Enables or Disables the TIMx Update event. + * @param TIMx: where x can be 1 to 17 to select the TIM peripheral. + * @param NewState: new state of the TIMx UDIS bit + * This parameter can be: ENABLE or DISABLE. + * @retval None + */ +void TIM_UpdateDisableConfig(TIM_TypeDef* TIMx, FunctionalState NewState) +{ + /* Check the parameters */ + assert_param(IS_TIM_ALL_PERIPH(TIMx)); + assert_param(IS_FUNCTIONAL_STATE(NewState)); + if (NewState != DISABLE) + { + /* Set the Update Disable Bit */ + TIMx->CR1 |= TIM_CR1_UDIS; + } + else + { + /* Reset the Update Disable Bit */ + TIMx->CR1 &= (uint16_t)~((uint16_t)TIM_CR1_UDIS); + } +} + +/** + * @brief Configures the TIMx Update Request Interrupt source. + * @param TIMx: where x can be 1 to 17 to select the TIM peripheral. + * @param TIM_UpdateSource: specifies the Update source. + * This parameter can be one of the following values: + * @arg TIM_UpdateSource_Global: Source of update is the counter overflow/underflow + or the setting of UG bit, or an update generation + through the slave mode controller. + * @arg TIM_UpdateSource_Regular: Source of update is counter overflow/underflow. + * @retval None + */ +void TIM_UpdateRequestConfig(TIM_TypeDef* TIMx, uint16_t TIM_UpdateSource) +{ + /* Check the parameters */ + assert_param(IS_TIM_ALL_PERIPH(TIMx)); + assert_param(IS_TIM_UPDATE_SOURCE(TIM_UpdateSource)); + if (TIM_UpdateSource != TIM_UpdateSource_Global) + { + /* Set the URS Bit */ + TIMx->CR1 |= TIM_CR1_URS; + } + else + { + /* Reset the URS Bit */ + TIMx->CR1 &= (uint16_t)~((uint16_t)TIM_CR1_URS); + } +} + +/** + * @brief Enables or disables the TIMx's Hall sensor interface. + * @param TIMx: where x can be 1, 2, 3, 4, 5 or 8 to select the TIM peripheral. + * @param NewState: new state of the TIMx Hall sensor interface. + * This parameter can be: ENABLE or DISABLE. + * @retval None + */ +void TIM_SelectHallSensor(TIM_TypeDef* TIMx, FunctionalState NewState) +{ + /* Check the parameters */ + assert_param(IS_TIM_LIST6_PERIPH(TIMx)); + assert_param(IS_FUNCTIONAL_STATE(NewState)); + if (NewState != DISABLE) + { + /* Set the TI1S Bit */ + TIMx->CR2 |= TIM_CR2_TI1S; + } + else + { + /* Reset the TI1S Bit */ + TIMx->CR2 &= (uint16_t)~((uint16_t)TIM_CR2_TI1S); + } +} + +/** + * @brief Selects the TIMx's One Pulse Mode. + * @param TIMx: where x can be 1 to 17 to select the TIM peripheral. + * @param TIM_OPMode: specifies the OPM Mode to be used. + * This parameter can be one of the following values: + * @arg TIM_OPMode_Single + * @arg TIM_OPMode_Repetitive + * @retval None + */ +void TIM_SelectOnePulseMode(TIM_TypeDef* TIMx, uint16_t TIM_OPMode) +{ + /* Check the parameters */ + assert_param(IS_TIM_ALL_PERIPH(TIMx)); + assert_param(IS_TIM_OPM_MODE(TIM_OPMode)); + /* Reset the OPM Bit */ + TIMx->CR1 &= (uint16_t)~((uint16_t)TIM_CR1_OPM); + /* Configure the OPM Mode */ + TIMx->CR1 |= TIM_OPMode; +} + +/** + * @brief Selects the TIMx Trigger Output Mode. + * @param TIMx: where x can be 1, 2, 3, 4, 5, 6, 7, 8, 9, 12 or 15 to select the TIM peripheral. + * @param TIM_TRGOSource: specifies the Trigger Output source. + * This paramter can be one of the following values: + * + * - For all TIMx + * @arg TIM_TRGOSource_Reset: The UG bit in the TIM_EGR register is used as the trigger output (TRGO). + * @arg TIM_TRGOSource_Enable: The Counter Enable CEN is used as the trigger output (TRGO). + * @arg TIM_TRGOSource_Update: The update event is selected as the trigger output (TRGO). + * + * - For all TIMx except TIM6 and TIM7 + * @arg TIM_TRGOSource_OC1: The trigger output sends a positive pulse when the CC1IF flag + * is to be set, as soon as a capture or compare match occurs (TRGO). + * @arg TIM_TRGOSource_OC1Ref: OC1REF signal is used as the trigger output (TRGO). + * @arg TIM_TRGOSource_OC2Ref: OC2REF signal is used as the trigger output (TRGO). + * @arg TIM_TRGOSource_OC3Ref: OC3REF signal is used as the trigger output (TRGO). + * @arg TIM_TRGOSource_OC4Ref: OC4REF signal is used as the trigger output (TRGO). + * + * @retval None + */ +void TIM_SelectOutputTrigger(TIM_TypeDef* TIMx, uint16_t TIM_TRGOSource) +{ + /* Check the parameters */ + assert_param(IS_TIM_LIST7_PERIPH(TIMx)); + assert_param(IS_TIM_TRGO_SOURCE(TIM_TRGOSource)); + /* Reset the MMS Bits */ + TIMx->CR2 &= (uint16_t)~((uint16_t)TIM_CR2_MMS); + /* Select the TRGO source */ + TIMx->CR2 |= TIM_TRGOSource; +} + +/** + * @brief Selects the TIMx Slave Mode. + * @param TIMx: where x can be 1, 2, 3, 4, 5, 8, 9, 12 or 15 to select the TIM peripheral. + * @param TIM_SlaveMode: specifies the Timer Slave Mode. + * This parameter can be one of the following values: + * @arg TIM_SlaveMode_Reset: Rising edge of the selected trigger signal (TRGI) re-initializes + * the counter and triggers an update of the registers. + * @arg TIM_SlaveMode_Gated: The counter clock is enabled when the trigger signal (TRGI) is high. + * @arg TIM_SlaveMode_Trigger: The counter starts at a rising edge of the trigger TRGI. + * @arg TIM_SlaveMode_External1: Rising edges of the selected trigger (TRGI) clock the counter. + * @retval None + */ +void TIM_SelectSlaveMode(TIM_TypeDef* TIMx, uint16_t TIM_SlaveMode) +{ + /* Check the parameters */ + assert_param(IS_TIM_LIST6_PERIPH(TIMx)); + assert_param(IS_TIM_SLAVE_MODE(TIM_SlaveMode)); + /* Reset the SMS Bits */ + TIMx->SMCR &= (uint16_t)~((uint16_t)TIM_SMCR_SMS); + /* Select the Slave Mode */ + TIMx->SMCR |= TIM_SlaveMode; +} + +/** + * @brief Sets or Resets the TIMx Master/Slave Mode. + * @param TIMx: where x can be 1, 2, 3, 4, 5, 8, 9, 12 or 15 to select the TIM peripheral. + * @param TIM_MasterSlaveMode: specifies the Timer Master Slave Mode. + * This parameter can be one of the following values: + * @arg TIM_MasterSlaveMode_Enable: synchronization between the current timer + * and its slaves (through TRGO). + * @arg TIM_MasterSlaveMode_Disable: No action + * @retval None + */ +void TIM_SelectMasterSlaveMode(TIM_TypeDef* TIMx, uint16_t TIM_MasterSlaveMode) +{ + /* Check the parameters */ + assert_param(IS_TIM_LIST6_PERIPH(TIMx)); + assert_param(IS_TIM_MSM_STATE(TIM_MasterSlaveMode)); + /* Reset the MSM Bit */ + TIMx->SMCR &= (uint16_t)~((uint16_t)TIM_SMCR_MSM); + + /* Set or Reset the MSM Bit */ + TIMx->SMCR |= TIM_MasterSlaveMode; +} + +/** + * @brief Sets the TIMx Counter Register value + * @param TIMx: where x can be 1 to 17 to select the TIM peripheral. + * @param Counter: specifies the Counter register new value. + * @retval None + */ +void TIM_SetCounter(TIM_TypeDef* TIMx, uint16_t Counter) +{ + /* Check the parameters */ + assert_param(IS_TIM_ALL_PERIPH(TIMx)); + /* Set the Counter Register value */ + TIMx->CNT = Counter; +} + +/** + * @brief Sets the TIMx Autoreload Register value + * @param TIMx: where x can be 1 to 17 to select the TIM peripheral. + * @param Autoreload: specifies the Autoreload register new value. + * @retval None + */ +void TIM_SetAutoreload(TIM_TypeDef* TIMx, uint16_t Autoreload) +{ + /* Check the parameters */ + assert_param(IS_TIM_ALL_PERIPH(TIMx)); + /* Set the Autoreload Register value */ + TIMx->ARR = Autoreload; +} + +/** + * @brief Sets the TIMx Capture Compare1 Register value + * @param TIMx: where x can be 1 to 17 except 6 and 7 to select the TIM peripheral. + * @param Compare1: specifies the Capture Compare1 register new value. + * @retval None + */ +void TIM_SetCompare1(TIM_TypeDef* TIMx, uint16_t Compare1) +{ + /* Check the parameters */ + assert_param(IS_TIM_LIST8_PERIPH(TIMx)); + /* Set the Capture Compare1 Register value */ + TIMx->CCR1 = Compare1; +} + +/** + * @brief Sets the TIMx Capture Compare2 Register value + * @param TIMx: where x can be 1, 2, 3, 4, 5, 8, 9, 12 or 15 to select the TIM peripheral. + * @param Compare2: specifies the Capture Compare2 register new value. + * @retval None + */ +void TIM_SetCompare2(TIM_TypeDef* TIMx, uint16_t Compare2) +{ + /* Check the parameters */ + assert_param(IS_TIM_LIST6_PERIPH(TIMx)); + /* Set the Capture Compare2 Register value */ + TIMx->CCR2 = Compare2; +} + +/** + * @brief Sets the TIMx Capture Compare3 Register value + * @param TIMx: where x can be 1, 2, 3, 4, 5 or 8 to select the TIM peripheral. + * @param Compare3: specifies the Capture Compare3 register new value. + * @retval None + */ +void TIM_SetCompare3(TIM_TypeDef* TIMx, uint16_t Compare3) +{ + /* Check the parameters */ + assert_param(IS_TIM_LIST3_PERIPH(TIMx)); + /* Set the Capture Compare3 Register value */ + TIMx->CCR3 = Compare3; +} + +/** + * @brief Sets the TIMx Capture Compare4 Register value + * @param TIMx: where x can be 1, 2, 3, 4, 5 or 8 to select the TIM peripheral. + * @param Compare4: specifies the Capture Compare4 register new value. + * @retval None + */ +void TIM_SetCompare4(TIM_TypeDef* TIMx, uint16_t Compare4) +{ + /* Check the parameters */ + assert_param(IS_TIM_LIST3_PERIPH(TIMx)); + /* Set the Capture Compare4 Register value */ + TIMx->CCR4 = Compare4; +} + +/** + * @brief Sets the TIMx Input Capture 1 prescaler. + * @param TIMx: where x can be 1 to 17 except 6 and 7 to select the TIM peripheral. + * @param TIM_ICPSC: specifies the Input Capture1 prescaler new value. + * This parameter can be one of the following values: + * @arg TIM_ICPSC_DIV1: no prescaler + * @arg TIM_ICPSC_DIV2: capture is done once every 2 events + * @arg TIM_ICPSC_DIV4: capture is done once every 4 events + * @arg TIM_ICPSC_DIV8: capture is done once every 8 events + * @retval None + */ +void TIM_SetIC1Prescaler(TIM_TypeDef* TIMx, uint16_t TIM_ICPSC) +{ + /* Check the parameters */ + assert_param(IS_TIM_LIST8_PERIPH(TIMx)); + assert_param(IS_TIM_IC_PRESCALER(TIM_ICPSC)); + /* Reset the IC1PSC Bits */ + TIMx->CCMR1 &= (uint16_t)~((uint16_t)TIM_CCMR1_IC1PSC); + /* Set the IC1PSC value */ + TIMx->CCMR1 |= TIM_ICPSC; +} + +/** + * @brief Sets the TIMx Input Capture 2 prescaler. + * @param TIMx: where x can be 1, 2, 3, 4, 5, 8, 9, 12 or 15 to select the TIM peripheral. + * @param TIM_ICPSC: specifies the Input Capture2 prescaler new value. + * This parameter can be one of the following values: + * @arg TIM_ICPSC_DIV1: no prescaler + * @arg TIM_ICPSC_DIV2: capture is done once every 2 events + * @arg TIM_ICPSC_DIV4: capture is done once every 4 events + * @arg TIM_ICPSC_DIV8: capture is done once every 8 events + * @retval None + */ +void TIM_SetIC2Prescaler(TIM_TypeDef* TIMx, uint16_t TIM_ICPSC) +{ + /* Check the parameters */ + assert_param(IS_TIM_LIST6_PERIPH(TIMx)); + assert_param(IS_TIM_IC_PRESCALER(TIM_ICPSC)); + /* Reset the IC2PSC Bits */ + TIMx->CCMR1 &= (uint16_t)~((uint16_t)TIM_CCMR1_IC2PSC); + /* Set the IC2PSC value */ + TIMx->CCMR1 |= (uint16_t)(TIM_ICPSC << 8); +} + +/** + * @brief Sets the TIMx Input Capture 3 prescaler. + * @param TIMx: where x can be 1, 2, 3, 4, 5 or 8 to select the TIM peripheral. + * @param TIM_ICPSC: specifies the Input Capture3 prescaler new value. + * This parameter can be one of the following values: + * @arg TIM_ICPSC_DIV1: no prescaler + * @arg TIM_ICPSC_DIV2: capture is done once every 2 events + * @arg TIM_ICPSC_DIV4: capture is done once every 4 events + * @arg TIM_ICPSC_DIV8: capture is done once every 8 events + * @retval None + */ +void TIM_SetIC3Prescaler(TIM_TypeDef* TIMx, uint16_t TIM_ICPSC) +{ + /* Check the parameters */ + assert_param(IS_TIM_LIST3_PERIPH(TIMx)); + assert_param(IS_TIM_IC_PRESCALER(TIM_ICPSC)); + /* Reset the IC3PSC Bits */ + TIMx->CCMR2 &= (uint16_t)~((uint16_t)TIM_CCMR2_IC3PSC); + /* Set the IC3PSC value */ + TIMx->CCMR2 |= TIM_ICPSC; +} + +/** + * @brief Sets the TIMx Input Capture 4 prescaler. + * @param TIMx: where x can be 1, 2, 3, 4, 5 or 8 to select the TIM peripheral. + * @param TIM_ICPSC: specifies the Input Capture4 prescaler new value. + * This parameter can be one of the following values: + * @arg TIM_ICPSC_DIV1: no prescaler + * @arg TIM_ICPSC_DIV2: capture is done once every 2 events + * @arg TIM_ICPSC_DIV4: capture is done once every 4 events + * @arg TIM_ICPSC_DIV8: capture is done once every 8 events + * @retval None + */ +void TIM_SetIC4Prescaler(TIM_TypeDef* TIMx, uint16_t TIM_ICPSC) +{ + /* Check the parameters */ + assert_param(IS_TIM_LIST3_PERIPH(TIMx)); + assert_param(IS_TIM_IC_PRESCALER(TIM_ICPSC)); + /* Reset the IC4PSC Bits */ + TIMx->CCMR2 &= (uint16_t)~((uint16_t)TIM_CCMR2_IC4PSC); + /* Set the IC4PSC value */ + TIMx->CCMR2 |= (uint16_t)(TIM_ICPSC << 8); +} + +/** + * @brief Sets the TIMx Clock Division value. + * @param TIMx: where x can be 1 to 17 except 6 and 7 to select + * the TIM peripheral. + * @param TIM_CKD: specifies the clock division value. + * This parameter can be one of the following value: + * @arg TIM_CKD_DIV1: TDTS = Tck_tim + * @arg TIM_CKD_DIV2: TDTS = 2*Tck_tim + * @arg TIM_CKD_DIV4: TDTS = 4*Tck_tim + * @retval None + */ +void TIM_SetClockDivision(TIM_TypeDef* TIMx, uint16_t TIM_CKD) +{ + /* Check the parameters */ + assert_param(IS_TIM_LIST8_PERIPH(TIMx)); + assert_param(IS_TIM_CKD_DIV(TIM_CKD)); + /* Reset the CKD Bits */ + TIMx->CR1 &= (uint16_t)~((uint16_t)TIM_CR1_CKD); + /* Set the CKD value */ + TIMx->CR1 |= TIM_CKD; +} + +/** + * @brief Gets the TIMx Input Capture 1 value. + * @param TIMx: where x can be 1 to 17 except 6 and 7 to select the TIM peripheral. + * @retval Capture Compare 1 Register value. + */ +uint16_t TIM_GetCapture1(TIM_TypeDef* TIMx) +{ + /* Check the parameters */ + assert_param(IS_TIM_LIST8_PERIPH(TIMx)); + /* Get the Capture 1 Register value */ + return TIMx->CCR1; +} + +/** + * @brief Gets the TIMx Input Capture 2 value. + * @param TIMx: where x can be 1, 2, 3, 4, 5, 8, 9, 12 or 15 to select the TIM peripheral. + * @retval Capture Compare 2 Register value. + */ +uint16_t TIM_GetCapture2(TIM_TypeDef* TIMx) +{ + /* Check the parameters */ + assert_param(IS_TIM_LIST6_PERIPH(TIMx)); + /* Get the Capture 2 Register value */ + return TIMx->CCR2; +} + +/** + * @brief Gets the TIMx Input Capture 3 value. + * @param TIMx: where x can be 1, 2, 3, 4, 5 or 8 to select the TIM peripheral. + * @retval Capture Compare 3 Register value. + */ +uint16_t TIM_GetCapture3(TIM_TypeDef* TIMx) +{ + /* Check the parameters */ + assert_param(IS_TIM_LIST3_PERIPH(TIMx)); + /* Get the Capture 3 Register value */ + return TIMx->CCR3; +} + +/** + * @brief Gets the TIMx Input Capture 4 value. + * @param TIMx: where x can be 1, 2, 3, 4, 5 or 8 to select the TIM peripheral. + * @retval Capture Compare 4 Register value. + */ +uint16_t TIM_GetCapture4(TIM_TypeDef* TIMx) +{ + /* Check the parameters */ + assert_param(IS_TIM_LIST3_PERIPH(TIMx)); + /* Get the Capture 4 Register value */ + return TIMx->CCR4; +} + +/** + * @brief Gets the TIMx Counter value. + * @param TIMx: where x can be 1 to 17 to select the TIM peripheral. + * @retval Counter Register value. + */ +uint16_t TIM_GetCounter(TIM_TypeDef* TIMx) +{ + /* Check the parameters */ + assert_param(IS_TIM_ALL_PERIPH(TIMx)); + /* Get the Counter Register value */ + return TIMx->CNT; +} + +/** + * @brief Gets the TIMx Prescaler value. + * @param TIMx: where x can be 1 to 17 to select the TIM peripheral. + * @retval Prescaler Register value. + */ +uint16_t TIM_GetPrescaler(TIM_TypeDef* TIMx) +{ + /* Check the parameters */ + assert_param(IS_TIM_ALL_PERIPH(TIMx)); + /* Get the Prescaler Register value */ + return TIMx->PSC; +} + +/** + * @brief Checks whether the specified TIM flag is set or not. + * @param TIMx: where x can be 1 to 17 to select the TIM peripheral. + * @param TIM_FLAG: specifies the flag to check. + * This parameter can be one of the following values: + * @arg TIM_FLAG_Update: TIM update Flag + * @arg TIM_FLAG_CC1: TIM Capture Compare 1 Flag + * @arg TIM_FLAG_CC2: TIM Capture Compare 2 Flag + * @arg TIM_FLAG_CC3: TIM Capture Compare 3 Flag + * @arg TIM_FLAG_CC4: TIM Capture Compare 4 Flag + * @arg TIM_FLAG_COM: TIM Commutation Flag + * @arg TIM_FLAG_Trigger: TIM Trigger Flag + * @arg TIM_FLAG_Break: TIM Break Flag + * @arg TIM_FLAG_CC1OF: TIM Capture Compare 1 overcapture Flag + * @arg TIM_FLAG_CC2OF: TIM Capture Compare 2 overcapture Flag + * @arg TIM_FLAG_CC3OF: TIM Capture Compare 3 overcapture Flag + * @arg TIM_FLAG_CC4OF: TIM Capture Compare 4 overcapture Flag + * @note + * - TIM6 and TIM7 can have only one update flag. + * - TIM9, TIM12 and TIM15 can have only TIM_FLAG_Update, TIM_FLAG_CC1, + * TIM_FLAG_CC2 or TIM_FLAG_Trigger. + * - TIM10, TIM11, TIM13, TIM14, TIM16 and TIM17 can have TIM_FLAG_Update or TIM_FLAG_CC1. + * - TIM_FLAG_Break is used only with TIM1, TIM8 and TIM15. + * - TIM_FLAG_COM is used only with TIM1, TIM8, TIM15, TIM16 and TIM17. + * @retval The new state of TIM_FLAG (SET or RESET). + */ +FlagStatus TIM_GetFlagStatus(TIM_TypeDef* TIMx, uint16_t TIM_FLAG) +{ + ITStatus bitstatus = RESET; + /* Check the parameters */ + assert_param(IS_TIM_ALL_PERIPH(TIMx)); + assert_param(IS_TIM_GET_FLAG(TIM_FLAG)); + + if ((TIMx->SR & TIM_FLAG) != (uint16_t)RESET) + { + bitstatus = SET; + } + else + { + bitstatus = RESET; + } + return bitstatus; +} + +/** + * @brief Clears the TIMx's pending flags. + * @param TIMx: where x can be 1 to 17 to select the TIM peripheral. + * @param TIM_FLAG: specifies the flag bit to clear. + * This parameter can be any combination of the following values: + * @arg TIM_FLAG_Update: TIM update Flag + * @arg TIM_FLAG_CC1: TIM Capture Compare 1 Flag + * @arg TIM_FLAG_CC2: TIM Capture Compare 2 Flag + * @arg TIM_FLAG_CC3: TIM Capture Compare 3 Flag + * @arg TIM_FLAG_CC4: TIM Capture Compare 4 Flag + * @arg TIM_FLAG_COM: TIM Commutation Flag + * @arg TIM_FLAG_Trigger: TIM Trigger Flag + * @arg TIM_FLAG_Break: TIM Break Flag + * @arg TIM_FLAG_CC1OF: TIM Capture Compare 1 overcapture Flag + * @arg TIM_FLAG_CC2OF: TIM Capture Compare 2 overcapture Flag + * @arg TIM_FLAG_CC3OF: TIM Capture Compare 3 overcapture Flag + * @arg TIM_FLAG_CC4OF: TIM Capture Compare 4 overcapture Flag + * @note + * - TIM6 and TIM7 can have only one update flag. + * - TIM9, TIM12 and TIM15 can have only TIM_FLAG_Update, TIM_FLAG_CC1, + * TIM_FLAG_CC2 or TIM_FLAG_Trigger. + * - TIM10, TIM11, TIM13, TIM14, TIM16 and TIM17 can have TIM_FLAG_Update or TIM_FLAG_CC1. + * - TIM_FLAG_Break is used only with TIM1, TIM8 and TIM15. + * - TIM_FLAG_COM is used only with TIM1, TIM8, TIM15, TIM16 and TIM17. + * @retval None + */ +void TIM_ClearFlag(TIM_TypeDef* TIMx, uint16_t TIM_FLAG) +{ + /* Check the parameters */ + assert_param(IS_TIM_ALL_PERIPH(TIMx)); + assert_param(IS_TIM_CLEAR_FLAG(TIM_FLAG)); + + /* Clear the flags */ + TIMx->SR = (uint16_t)~TIM_FLAG; +} + +/** + * @brief Checks whether the TIM interrupt has occurred or not. + * @param TIMx: where x can be 1 to 17 to select the TIM peripheral. + * @param TIM_IT: specifies the TIM interrupt source to check. + * This parameter can be one of the following values: + * @arg TIM_IT_Update: TIM update Interrupt source + * @arg TIM_IT_CC1: TIM Capture Compare 1 Interrupt source + * @arg TIM_IT_CC2: TIM Capture Compare 2 Interrupt source + * @arg TIM_IT_CC3: TIM Capture Compare 3 Interrupt source + * @arg TIM_IT_CC4: TIM Capture Compare 4 Interrupt source + * @arg TIM_IT_COM: TIM Commutation Interrupt source + * @arg TIM_IT_Trigger: TIM Trigger Interrupt source + * @arg TIM_IT_Break: TIM Break Interrupt source + * @note + * - TIM6 and TIM7 can generate only an update interrupt. + * - TIM9, TIM12 and TIM15 can have only TIM_IT_Update, TIM_IT_CC1, + * TIM_IT_CC2 or TIM_IT_Trigger. + * - TIM10, TIM11, TIM13, TIM14, TIM16 and TIM17 can have TIM_IT_Update or TIM_IT_CC1. + * - TIM_IT_Break is used only with TIM1, TIM8 and TIM15. + * - TIM_IT_COM is used only with TIM1, TIM8, TIM15, TIM16 and TIM17. + * @retval The new state of the TIM_IT(SET or RESET). + */ +ITStatus TIM_GetITStatus(TIM_TypeDef* TIMx, uint16_t TIM_IT) +{ + ITStatus bitstatus = RESET; + uint16_t itstatus = 0x0, itenable = 0x0; + /* Check the parameters */ + assert_param(IS_TIM_ALL_PERIPH(TIMx)); + assert_param(IS_TIM_GET_IT(TIM_IT)); + + itstatus = TIMx->SR & TIM_IT; + + itenable = TIMx->DIER & TIM_IT; + if ((itstatus != (uint16_t)RESET) && (itenable != (uint16_t)RESET)) + { + bitstatus = SET; + } + else + { + bitstatus = RESET; + } + return bitstatus; +} + +/** + * @brief Clears the TIMx's interrupt pending bits. + * @param TIMx: where x can be 1 to 17 to select the TIM peripheral. + * @param TIM_IT: specifies the pending bit to clear. + * This parameter can be any combination of the following values: + * @arg TIM_IT_Update: TIM1 update Interrupt source + * @arg TIM_IT_CC1: TIM Capture Compare 1 Interrupt source + * @arg TIM_IT_CC2: TIM Capture Compare 2 Interrupt source + * @arg TIM_IT_CC3: TIM Capture Compare 3 Interrupt source + * @arg TIM_IT_CC4: TIM Capture Compare 4 Interrupt source + * @arg TIM_IT_COM: TIM Commutation Interrupt source + * @arg TIM_IT_Trigger: TIM Trigger Interrupt source + * @arg TIM_IT_Break: TIM Break Interrupt source + * @note + * - TIM6 and TIM7 can generate only an update interrupt. + * - TIM9, TIM12 and TIM15 can have only TIM_IT_Update, TIM_IT_CC1, + * TIM_IT_CC2 or TIM_IT_Trigger. + * - TIM10, TIM11, TIM13, TIM14, TIM16 and TIM17 can have TIM_IT_Update or TIM_IT_CC1. + * - TIM_IT_Break is used only with TIM1, TIM8 and TIM15. + * - TIM_IT_COM is used only with TIM1, TIM8, TIM15, TIM16 and TIM17. + * @retval None + */ +void TIM_ClearITPendingBit(TIM_TypeDef* TIMx, uint16_t TIM_IT) +{ + /* Check the parameters */ + assert_param(IS_TIM_ALL_PERIPH(TIMx)); + assert_param(IS_TIM_IT(TIM_IT)); + /* Clear the IT pending Bit */ + TIMx->SR = (uint16_t)~TIM_IT; +} + +/** + * @brief Configure the TI1 as Input. + * @param TIMx: where x can be 1 to 17 except 6 and 7 to select the TIM peripheral. + * @param TIM_ICPolarity : The Input Polarity. + * This parameter can be one of the following values: + * @arg TIM_ICPolarity_Rising + * @arg TIM_ICPolarity_Falling + * @param TIM_ICSelection: specifies the input to be used. + * This parameter can be one of the following values: + * @arg TIM_ICSelection_DirectTI: TIM Input 1 is selected to be connected to IC1. + * @arg TIM_ICSelection_IndirectTI: TIM Input 1 is selected to be connected to IC2. + * @arg TIM_ICSelection_TRC: TIM Input 1 is selected to be connected to TRC. + * @param TIM_ICFilter: Specifies the Input Capture Filter. + * This parameter must be a value between 0x00 and 0x0F. + * @retval None + */ +static void TI1_Config(TIM_TypeDef* TIMx, uint16_t TIM_ICPolarity, uint16_t TIM_ICSelection, + uint16_t TIM_ICFilter) +{ + uint16_t tmpccmr1 = 0, tmpccer = 0; + /* Disable the Channel 1: Reset the CC1E Bit */ + TIMx->CCER &= (uint16_t)~((uint16_t)TIM_CCER_CC1E); + tmpccmr1 = TIMx->CCMR1; + tmpccer = TIMx->CCER; + /* Select the Input and set the filter */ + tmpccmr1 &= (uint16_t)(((uint16_t)~((uint16_t)TIM_CCMR1_CC1S)) & ((uint16_t)~((uint16_t)TIM_CCMR1_IC1F))); + tmpccmr1 |= (uint16_t)(TIM_ICSelection | (uint16_t)(TIM_ICFilter << (uint16_t)4)); + + if((TIMx == TIM1) || (TIMx == TIM8) || (TIMx == TIM2) || (TIMx == TIM3) || + (TIMx == TIM4) ||(TIMx == TIM5)) + { + /* Select the Polarity and set the CC1E Bit */ + tmpccer &= (uint16_t)~((uint16_t)(TIM_CCER_CC1P)); + tmpccer |= (uint16_t)(TIM_ICPolarity | (uint16_t)TIM_CCER_CC1E); + } + else + { + /* Select the Polarity and set the CC1E Bit */ + tmpccer &= (uint16_t)~((uint16_t)(TIM_CCER_CC1P | TIM_CCER_CC1NP)); + tmpccer |= (uint16_t)(TIM_ICPolarity | (uint16_t)TIM_CCER_CC1E); + } + + /* Write to TIMx CCMR1 and CCER registers */ + TIMx->CCMR1 = tmpccmr1; + TIMx->CCER = tmpccer; +} + +/** + * @brief Configure the TI2 as Input. + * @param TIMx: where x can be 1, 2, 3, 4, 5, 8, 9, 12 or 15 to select the TIM peripheral. + * @param TIM_ICPolarity : The Input Polarity. + * This parameter can be one of the following values: + * @arg TIM_ICPolarity_Rising + * @arg TIM_ICPolarity_Falling + * @param TIM_ICSelection: specifies the input to be used. + * This parameter can be one of the following values: + * @arg TIM_ICSelection_DirectTI: TIM Input 2 is selected to be connected to IC2. + * @arg TIM_ICSelection_IndirectTI: TIM Input 2 is selected to be connected to IC1. + * @arg TIM_ICSelection_TRC: TIM Input 2 is selected to be connected to TRC. + * @param TIM_ICFilter: Specifies the Input Capture Filter. + * This parameter must be a value between 0x00 and 0x0F. + * @retval None + */ +static void TI2_Config(TIM_TypeDef* TIMx, uint16_t TIM_ICPolarity, uint16_t TIM_ICSelection, + uint16_t TIM_ICFilter) +{ + uint16_t tmpccmr1 = 0, tmpccer = 0, tmp = 0; + /* Disable the Channel 2: Reset the CC2E Bit */ + TIMx->CCER &= (uint16_t)~((uint16_t)TIM_CCER_CC2E); + tmpccmr1 = TIMx->CCMR1; + tmpccer = TIMx->CCER; + tmp = (uint16_t)(TIM_ICPolarity << 4); + /* Select the Input and set the filter */ + tmpccmr1 &= (uint16_t)(((uint16_t)~((uint16_t)TIM_CCMR1_CC2S)) & ((uint16_t)~((uint16_t)TIM_CCMR1_IC2F))); + tmpccmr1 |= (uint16_t)(TIM_ICFilter << 12); + tmpccmr1 |= (uint16_t)(TIM_ICSelection << 8); + + if((TIMx == TIM1) || (TIMx == TIM8) || (TIMx == TIM2) || (TIMx == TIM3) || + (TIMx == TIM4) ||(TIMx == TIM5)) + { + /* Select the Polarity and set the CC2E Bit */ + tmpccer &= (uint16_t)~((uint16_t)(TIM_CCER_CC2P)); + tmpccer |= (uint16_t)(tmp | (uint16_t)TIM_CCER_CC2E); + } + else + { + /* Select the Polarity and set the CC2E Bit */ + tmpccer &= (uint16_t)~((uint16_t)(TIM_CCER_CC2P | TIM_CCER_CC2NP)); + tmpccer |= (uint16_t)(TIM_ICPolarity | (uint16_t)TIM_CCER_CC2E); + } + + /* Write to TIMx CCMR1 and CCER registers */ + TIMx->CCMR1 = tmpccmr1 ; + TIMx->CCER = tmpccer; +} + +/** + * @brief Configure the TI3 as Input. + * @param TIMx: where x can be 1, 2, 3, 4, 5 or 8 to select the TIM peripheral. + * @param TIM_ICPolarity : The Input Polarity. + * This parameter can be one of the following values: + * @arg TIM_ICPolarity_Rising + * @arg TIM_ICPolarity_Falling + * @param TIM_ICSelection: specifies the input to be used. + * This parameter can be one of the following values: + * @arg TIM_ICSelection_DirectTI: TIM Input 3 is selected to be connected to IC3. + * @arg TIM_ICSelection_IndirectTI: TIM Input 3 is selected to be connected to IC4. + * @arg TIM_ICSelection_TRC: TIM Input 3 is selected to be connected to TRC. + * @param TIM_ICFilter: Specifies the Input Capture Filter. + * This parameter must be a value between 0x00 and 0x0F. + * @retval None + */ +static void TI3_Config(TIM_TypeDef* TIMx, uint16_t TIM_ICPolarity, uint16_t TIM_ICSelection, + uint16_t TIM_ICFilter) +{ + uint16_t tmpccmr2 = 0, tmpccer = 0, tmp = 0; + /* Disable the Channel 3: Reset the CC3E Bit */ + TIMx->CCER &= (uint16_t)~((uint16_t)TIM_CCER_CC3E); + tmpccmr2 = TIMx->CCMR2; + tmpccer = TIMx->CCER; + tmp = (uint16_t)(TIM_ICPolarity << 8); + /* Select the Input and set the filter */ + tmpccmr2 &= (uint16_t)(((uint16_t)~((uint16_t)TIM_CCMR2_CC3S)) & ((uint16_t)~((uint16_t)TIM_CCMR2_IC3F))); + tmpccmr2 |= (uint16_t)(TIM_ICSelection | (uint16_t)(TIM_ICFilter << (uint16_t)4)); + + if((TIMx == TIM1) || (TIMx == TIM8) || (TIMx == TIM2) || (TIMx == TIM3) || + (TIMx == TIM4) ||(TIMx == TIM5)) + { + /* Select the Polarity and set the CC3E Bit */ + tmpccer &= (uint16_t)~((uint16_t)(TIM_CCER_CC3P)); + tmpccer |= (uint16_t)(tmp | (uint16_t)TIM_CCER_CC3E); + } + else + { + /* Select the Polarity and set the CC3E Bit */ + tmpccer &= (uint16_t)~((uint16_t)(TIM_CCER_CC3P | TIM_CCER_CC3NP)); + tmpccer |= (uint16_t)(TIM_ICPolarity | (uint16_t)TIM_CCER_CC3E); + } + + /* Write to TIMx CCMR2 and CCER registers */ + TIMx->CCMR2 = tmpccmr2; + TIMx->CCER = tmpccer; +} + +/** + * @brief Configure the TI4 as Input. + * @param TIMx: where x can be 1, 2, 3, 4, 5 or 8 to select the TIM peripheral. + * @param TIM_ICPolarity : The Input Polarity. + * This parameter can be one of the following values: + * @arg TIM_ICPolarity_Rising + * @arg TIM_ICPolarity_Falling + * @param TIM_ICSelection: specifies the input to be used. + * This parameter can be one of the following values: + * @arg TIM_ICSelection_DirectTI: TIM Input 4 is selected to be connected to IC4. + * @arg TIM_ICSelection_IndirectTI: TIM Input 4 is selected to be connected to IC3. + * @arg TIM_ICSelection_TRC: TIM Input 4 is selected to be connected to TRC. + * @param TIM_ICFilter: Specifies the Input Capture Filter. + * This parameter must be a value between 0x00 and 0x0F. + * @retval None + */ +static void TI4_Config(TIM_TypeDef* TIMx, uint16_t TIM_ICPolarity, uint16_t TIM_ICSelection, + uint16_t TIM_ICFilter) +{ + uint16_t tmpccmr2 = 0, tmpccer = 0, tmp = 0; + + /* Disable the Channel 4: Reset the CC4E Bit */ + TIMx->CCER &= (uint16_t)~((uint16_t)TIM_CCER_CC4E); + tmpccmr2 = TIMx->CCMR2; + tmpccer = TIMx->CCER; + tmp = (uint16_t)(TIM_ICPolarity << 12); + /* Select the Input and set the filter */ + tmpccmr2 &= (uint16_t)((uint16_t)(~(uint16_t)TIM_CCMR2_CC4S) & ((uint16_t)~((uint16_t)TIM_CCMR2_IC4F))); + tmpccmr2 |= (uint16_t)(TIM_ICSelection << 8); + tmpccmr2 |= (uint16_t)(TIM_ICFilter << 12); + + if((TIMx == TIM1) || (TIMx == TIM8) || (TIMx == TIM2) || (TIMx == TIM3) || + (TIMx == TIM4) ||(TIMx == TIM5)) + { + /* Select the Polarity and set the CC4E Bit */ + tmpccer &= (uint16_t)~((uint16_t)(TIM_CCER_CC4P)); + tmpccer |= (uint16_t)(tmp | (uint16_t)TIM_CCER_CC4E); + } + else + { + /* Select the Polarity and set the CC4E Bit */ + tmpccer &= (uint16_t)~((uint16_t)(TIM_CCER_CC3P | TIM_CCER_CC4NP)); + tmpccer |= (uint16_t)(TIM_ICPolarity | (uint16_t)TIM_CCER_CC4E); + } + /* Write to TIMx CCMR2 and CCER registers */ + TIMx->CCMR2 = tmpccmr2; + TIMx->CCER = tmpccer; +} + +/** + * @} + */ + +/** + * @} + */ + +/** + * @} + */ + +/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ diff --git a/Libraries/STM32F10x_StdPeriph_Driver/src/stm32f10x_usart.c b/Libraries/STM32F10x_StdPeriph_Driver/src/stm32f10x_usart.c new file mode 100644 index 0000000..7f01f12 --- /dev/null +++ b/Libraries/STM32F10x_StdPeriph_Driver/src/stm32f10x_usart.c @@ -0,0 +1,1065 @@ +/** + ****************************************************************************** + * @file stm32f10x_usart.c + * @author MCD Application Team + * @version V3.6.1 + * @date 05-March-2012 + * @brief This file provides all the USART firmware functions. + ****************************************************************************** + * @attention + * + *

    © COPYRIGHT 2012 STMicroelectronics

    + * + * Licensed under MCD-ST Liberty SW License Agreement V2, (the "License"); + * You may not use this file except in compliance with the License. + * You may obtain a copy of the License at: + * + * http://www.st.com/software_license_agreement_liberty_v2 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, + * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + * + ****************************************************************************** + */ + +/* Includes ------------------------------------------------------------------*/ +#include "stm32f10x_usart.h" +#include "stm32f10x_rcc.h" + +/** @addtogroup STM32F10x_StdPeriph_Driver + * @{ + */ + +/** @defgroup USART + * @brief USART driver modules + * @{ + */ + +/** @defgroup USART_Private_TypesDefinitions + * @{ + */ + +/** + * @} + */ + +/** @defgroup USART_Private_Defines + * @{ + */ + +#define CR1_UE_Set ((uint16_t)0x2000) /*!< USART Enable Mask */ +#define CR1_UE_Reset ((uint16_t)0xDFFF) /*!< USART Disable Mask */ + +#define CR1_WAKE_Mask ((uint16_t)0xF7FF) /*!< USART WakeUp Method Mask */ + +#define CR1_RWU_Set ((uint16_t)0x0002) /*!< USART mute mode Enable Mask */ +#define CR1_RWU_Reset ((uint16_t)0xFFFD) /*!< USART mute mode Enable Mask */ +#define CR1_SBK_Set ((uint16_t)0x0001) /*!< USART Break Character send Mask */ +#define CR1_CLEAR_Mask ((uint16_t)0xE9F3) /*!< USART CR1 Mask */ +#define CR2_Address_Mask ((uint16_t)0xFFF0) /*!< USART address Mask */ + +#define CR2_LINEN_Set ((uint16_t)0x4000) /*!< USART LIN Enable Mask */ +#define CR2_LINEN_Reset ((uint16_t)0xBFFF) /*!< USART LIN Disable Mask */ + +#define CR2_LBDL_Mask ((uint16_t)0xFFDF) /*!< USART LIN Break detection Mask */ +#define CR2_STOP_CLEAR_Mask ((uint16_t)0xCFFF) /*!< USART CR2 STOP Bits Mask */ +#define CR2_CLOCK_CLEAR_Mask ((uint16_t)0xF0FF) /*!< USART CR2 Clock Mask */ + +#define CR3_SCEN_Set ((uint16_t)0x0020) /*!< USART SC Enable Mask */ +#define CR3_SCEN_Reset ((uint16_t)0xFFDF) /*!< USART SC Disable Mask */ + +#define CR3_NACK_Set ((uint16_t)0x0010) /*!< USART SC NACK Enable Mask */ +#define CR3_NACK_Reset ((uint16_t)0xFFEF) /*!< USART SC NACK Disable Mask */ + +#define CR3_HDSEL_Set ((uint16_t)0x0008) /*!< USART Half-Duplex Enable Mask */ +#define CR3_HDSEL_Reset ((uint16_t)0xFFF7) /*!< USART Half-Duplex Disable Mask */ + +#define CR3_IRLP_Mask ((uint16_t)0xFFFB) /*!< USART IrDA LowPower mode Mask */ +#define CR3_CLEAR_Mask ((uint16_t)0xFCFF) /*!< USART CR3 Mask */ + +#define CR3_IREN_Set ((uint16_t)0x0002) /*!< USART IrDA Enable Mask */ +#define CR3_IREN_Reset ((uint16_t)0xFFFD) /*!< USART IrDA Disable Mask */ +#define GTPR_LSB_Mask ((uint16_t)0x00FF) /*!< Guard Time Register LSB Mask */ +#define GTPR_MSB_Mask ((uint16_t)0xFF00) /*!< Guard Time Register MSB Mask */ +#define IT_Mask ((uint16_t)0x001F) /*!< USART Interrupt Mask */ + +/* USART OverSampling-8 Mask */ +#define CR1_OVER8_Set ((u16)0x8000) /* USART OVER8 mode Enable Mask */ +#define CR1_OVER8_Reset ((u16)0x7FFF) /* USART OVER8 mode Disable Mask */ + +/* USART One Bit Sampling Mask */ +#define CR3_ONEBITE_Set ((u16)0x0800) /* USART ONEBITE mode Enable Mask */ +#define CR3_ONEBITE_Reset ((u16)0xF7FF) /* USART ONEBITE mode Disable Mask */ + +/** + * @} + */ + +/** @defgroup USART_Private_Macros + * @{ + */ + +/** + * @} + */ + +/** @defgroup USART_Private_Variables + * @{ + */ + +/** + * @} + */ + +/** @defgroup USART_Private_FunctionPrototypes + * @{ + */ + +/** + * @} + */ + +/** @defgroup USART_Private_Functions + * @{ + */ + +/** + * @brief Deinitializes the USARTx peripheral registers to their default reset values. + * @param USARTx: Select the USART or the UART peripheral. + * This parameter can be one of the following values: + * USART1, USART2, USART3, UART4 or UART5. + * @retval None + */ +void USART_DeInit(USART_TypeDef* USARTx) +{ + /* Check the parameters */ + assert_param(IS_USART_ALL_PERIPH(USARTx)); + + if (USARTx == USART1) + { + RCC_APB2PeriphResetCmd(RCC_APB2Periph_USART1, ENABLE); + RCC_APB2PeriphResetCmd(RCC_APB2Periph_USART1, DISABLE); + } + else if (USARTx == USART2) + { + RCC_APB1PeriphResetCmd(RCC_APB1Periph_USART2, ENABLE); + RCC_APB1PeriphResetCmd(RCC_APB1Periph_USART2, DISABLE); + } + else if (USARTx == USART3) + { + RCC_APB1PeriphResetCmd(RCC_APB1Periph_USART3, ENABLE); + RCC_APB1PeriphResetCmd(RCC_APB1Periph_USART3, DISABLE); + } + else if (USARTx == UART4) + { + RCC_APB1PeriphResetCmd(RCC_APB1Periph_UART4, ENABLE); + RCC_APB1PeriphResetCmd(RCC_APB1Periph_UART4, DISABLE); + } + else + { + if (USARTx == UART5) + { + RCC_APB1PeriphResetCmd(RCC_APB1Periph_UART5, ENABLE); + RCC_APB1PeriphResetCmd(RCC_APB1Periph_UART5, DISABLE); + } + } +} + +/** + * @brief Initializes the USARTx peripheral according to the specified + * parameters in the USART_InitStruct . + * @param USARTx: Select the USART or the UART peripheral. + * This parameter can be one of the following values: + * USART1, USART2, USART3, UART4 or UART5. + * @param USART_InitStruct: pointer to a USART_InitTypeDef structure + * that contains the configuration information for the specified USART + * peripheral. + * @retval None + */ +void USART_Init(USART_TypeDef* USARTx, USART_InitTypeDef* USART_InitStruct) +{ + uint32_t tmpreg = 0x00, apbclock = 0x00; + uint32_t integerdivider = 0x00; + uint32_t fractionaldivider = 0x00; + uint32_t usartxbase = 0; + RCC_ClocksTypeDef RCC_ClocksStatus; + /* Check the parameters */ + assert_param(IS_USART_ALL_PERIPH(USARTx)); + assert_param(IS_USART_BAUDRATE(USART_InitStruct->USART_BaudRate)); + assert_param(IS_USART_WORD_LENGTH(USART_InitStruct->USART_WordLength)); + assert_param(IS_USART_STOPBITS(USART_InitStruct->USART_StopBits)); + assert_param(IS_USART_PARITY(USART_InitStruct->USART_Parity)); + assert_param(IS_USART_MODE(USART_InitStruct->USART_Mode)); + assert_param(IS_USART_HARDWARE_FLOW_CONTROL(USART_InitStruct->USART_HardwareFlowControl)); + /* The hardware flow control is available only for USART1, USART2 and USART3 */ + if (USART_InitStruct->USART_HardwareFlowControl != USART_HardwareFlowControl_None) + { + assert_param(IS_USART_123_PERIPH(USARTx)); + } + + usartxbase = (uint32_t)USARTx; + +/*---------------------------- USART CR2 Configuration -----------------------*/ + tmpreg = USARTx->CR2; + /* Clear STOP[13:12] bits */ + tmpreg &= CR2_STOP_CLEAR_Mask; + /* Configure the USART Stop Bits, Clock, CPOL, CPHA and LastBit ------------*/ + /* Set STOP[13:12] bits according to USART_StopBits value */ + tmpreg |= (uint32_t)USART_InitStruct->USART_StopBits; + + /* Write to USART CR2 */ + USARTx->CR2 = (uint16_t)tmpreg; + +/*---------------------------- USART CR1 Configuration -----------------------*/ + tmpreg = USARTx->CR1; + /* Clear M, PCE, PS, TE and RE bits */ + tmpreg &= CR1_CLEAR_Mask; + /* Configure the USART Word Length, Parity and mode ----------------------- */ + /* Set the M bits according to USART_WordLength value */ + /* Set PCE and PS bits according to USART_Parity value */ + /* Set TE and RE bits according to USART_Mode value */ + tmpreg |= (uint32_t)USART_InitStruct->USART_WordLength | USART_InitStruct->USART_Parity | + USART_InitStruct->USART_Mode; + /* Write to USART CR1 */ + USARTx->CR1 = (uint16_t)tmpreg; + +/*---------------------------- USART CR3 Configuration -----------------------*/ + tmpreg = USARTx->CR3; + /* Clear CTSE and RTSE bits */ + tmpreg &= CR3_CLEAR_Mask; + /* Configure the USART HFC -------------------------------------------------*/ + /* Set CTSE and RTSE bits according to USART_HardwareFlowControl value */ + tmpreg |= USART_InitStruct->USART_HardwareFlowControl; + /* Write to USART CR3 */ + USARTx->CR3 = (uint16_t)tmpreg; + +/*---------------------------- USART BRR Configuration -----------------------*/ + /* Configure the USART Baud Rate -------------------------------------------*/ + RCC_GetClocksFreq(&RCC_ClocksStatus); + if (usartxbase == USART1_BASE) + { + apbclock = RCC_ClocksStatus.PCLK2_Frequency; + } + else + { + apbclock = RCC_ClocksStatus.PCLK1_Frequency; + } + + /* Determine the integer part */ + if ((USARTx->CR1 & CR1_OVER8_Set) != 0) + { + /* Integer part computing in case Oversampling mode is 8 Samples */ + integerdivider = ((25 * apbclock) / (2 * (USART_InitStruct->USART_BaudRate))); + } + else /* if ((USARTx->CR1 & CR1_OVER8_Set) == 0) */ + { + /* Integer part computing in case Oversampling mode is 16 Samples */ + integerdivider = ((25 * apbclock) / (4 * (USART_InitStruct->USART_BaudRate))); + } + tmpreg = (integerdivider / 100) << 4; + + /* Determine the fractional part */ + fractionaldivider = integerdivider - (100 * (tmpreg >> 4)); + + /* Implement the fractional part in the register */ + if ((USARTx->CR1 & CR1_OVER8_Set) != 0) + { + tmpreg |= ((((fractionaldivider * 8) + 50) / 100)) & ((uint8_t)0x07); + } + else /* if ((USARTx->CR1 & CR1_OVER8_Set) == 0) */ + { + tmpreg |= ((((fractionaldivider * 16) + 50) / 100)) & ((uint8_t)0x0F); + } + + /* Write to USART BRR */ + USARTx->BRR = (uint16_t)tmpreg; +} + +/** + * @brief Fills each USART_InitStruct member with its default value. + * @param USART_InitStruct: pointer to a USART_InitTypeDef structure + * which will be initialized. + * @retval None + */ +void USART_StructInit(USART_InitTypeDef* USART_InitStruct) +{ + /* USART_InitStruct members default value */ + USART_InitStruct->USART_BaudRate = 9600; + USART_InitStruct->USART_WordLength = USART_WordLength_8b; + USART_InitStruct->USART_StopBits = USART_StopBits_1; + USART_InitStruct->USART_Parity = USART_Parity_No ; + USART_InitStruct->USART_Mode = USART_Mode_Rx | USART_Mode_Tx; + USART_InitStruct->USART_HardwareFlowControl = USART_HardwareFlowControl_None; +} + +/** + * @brief Initializes the USARTx peripheral Clock according to the + * specified parameters in the USART_ClockInitStruct . + * @param USARTx: where x can be 1, 2, 3 to select the USART peripheral. + * @param USART_ClockInitStruct: pointer to a USART_ClockInitTypeDef + * structure that contains the configuration information for the specified + * USART peripheral. + * @note The Smart Card and Synchronous modes are not available for UART4 and UART5. + * @retval None + */ +void USART_ClockInit(USART_TypeDef* USARTx, USART_ClockInitTypeDef* USART_ClockInitStruct) +{ + uint32_t tmpreg = 0x00; + /* Check the parameters */ + assert_param(IS_USART_123_PERIPH(USARTx)); + assert_param(IS_USART_CLOCK(USART_ClockInitStruct->USART_Clock)); + assert_param(IS_USART_CPOL(USART_ClockInitStruct->USART_CPOL)); + assert_param(IS_USART_CPHA(USART_ClockInitStruct->USART_CPHA)); + assert_param(IS_USART_LASTBIT(USART_ClockInitStruct->USART_LastBit)); + +/*---------------------------- USART CR2 Configuration -----------------------*/ + tmpreg = USARTx->CR2; + /* Clear CLKEN, CPOL, CPHA and LBCL bits */ + tmpreg &= CR2_CLOCK_CLEAR_Mask; + /* Configure the USART Clock, CPOL, CPHA and LastBit ------------*/ + /* Set CLKEN bit according to USART_Clock value */ + /* Set CPOL bit according to USART_CPOL value */ + /* Set CPHA bit according to USART_CPHA value */ + /* Set LBCL bit according to USART_LastBit value */ + tmpreg |= (uint32_t)USART_ClockInitStruct->USART_Clock | USART_ClockInitStruct->USART_CPOL | + USART_ClockInitStruct->USART_CPHA | USART_ClockInitStruct->USART_LastBit; + /* Write to USART CR2 */ + USARTx->CR2 = (uint16_t)tmpreg; +} + +/** + * @brief Fills each USART_ClockInitStruct member with its default value. + * @param USART_ClockInitStruct: pointer to a USART_ClockInitTypeDef + * structure which will be initialized. + * @retval None + */ +void USART_ClockStructInit(USART_ClockInitTypeDef* USART_ClockInitStruct) +{ + /* USART_ClockInitStruct members default value */ + USART_ClockInitStruct->USART_Clock = USART_Clock_Disable; + USART_ClockInitStruct->USART_CPOL = USART_CPOL_Low; + USART_ClockInitStruct->USART_CPHA = USART_CPHA_1Edge; + USART_ClockInitStruct->USART_LastBit = USART_LastBit_Disable; +} + +/** + * @brief Enables or disables the specified USART peripheral. + * @param USARTx: Select the USART or the UART peripheral. + * This parameter can be one of the following values: + * USART1, USART2, USART3, UART4 or UART5. + * @param NewState: new state of the USARTx peripheral. + * This parameter can be: ENABLE or DISABLE. + * @retval None + */ +void USART_Cmd(USART_TypeDef* USARTx, FunctionalState NewState) +{ + /* Check the parameters */ + assert_param(IS_USART_ALL_PERIPH(USARTx)); + assert_param(IS_FUNCTIONAL_STATE(NewState)); + + if (NewState != DISABLE) + { + /* Enable the selected USART by setting the UE bit in the CR1 register */ + USARTx->CR1 |= CR1_UE_Set; + } + else + { + /* Disable the selected USART by clearing the UE bit in the CR1 register */ + USARTx->CR1 &= CR1_UE_Reset; + } +} + +/** + * @brief Enables or disables the specified USART interrupts. + * @param USARTx: Select the USART or the UART peripheral. + * This parameter can be one of the following values: + * USART1, USART2, USART3, UART4 or UART5. + * @param USART_IT: specifies the USART interrupt sources to be enabled or disabled. + * This parameter can be one of the following values: + * @arg USART_IT_CTS: CTS change interrupt (not available for UART4 and UART5) + * @arg USART_IT_LBD: LIN Break detection interrupt + * @arg USART_IT_TXE: Transmit Data Register empty interrupt + * @arg USART_IT_TC: Transmission complete interrupt + * @arg USART_IT_RXNE: Receive Data register not empty interrupt + * @arg USART_IT_IDLE: Idle line detection interrupt + * @arg USART_IT_PE: Parity Error interrupt + * @arg USART_IT_ERR: Error interrupt(Frame error, noise error, overrun error) + * @param NewState: new state of the specified USARTx interrupts. + * This parameter can be: ENABLE or DISABLE. + * @retval None + */ +void USART_ITConfig(USART_TypeDef* USARTx, uint16_t USART_IT, FunctionalState NewState) +{ + uint32_t usartreg = 0x00, itpos = 0x00, itmask = 0x00; + uint32_t usartxbase = 0x00; + /* Check the parameters */ + assert_param(IS_USART_ALL_PERIPH(USARTx)); + assert_param(IS_USART_CONFIG_IT(USART_IT)); + assert_param(IS_FUNCTIONAL_STATE(NewState)); + /* The CTS interrupt is not available for UART4 and UART5 */ + if (USART_IT == USART_IT_CTS) + { + assert_param(IS_USART_123_PERIPH(USARTx)); + } + + usartxbase = (uint32_t)USARTx; + + /* Get the USART register index */ + usartreg = (((uint8_t)USART_IT) >> 0x05); + + /* Get the interrupt position */ + itpos = USART_IT & IT_Mask; + itmask = (((uint32_t)0x01) << itpos); + + if (usartreg == 0x01) /* The IT is in CR1 register */ + { + usartxbase += 0x0C; + } + else if (usartreg == 0x02) /* The IT is in CR2 register */ + { + usartxbase += 0x10; + } + else /* The IT is in CR3 register */ + { + usartxbase += 0x14; + } + if (NewState != DISABLE) + { + *(__IO uint32_t*)usartxbase |= itmask; + } + else + { + *(__IO uint32_t*)usartxbase &= ~itmask; + } +} + +/** + * @brief Enables or disables the USARTs DMA interface. + * @param USARTx: Select the USART or the UART peripheral. + * This parameter can be one of the following values: + * USART1, USART2, USART3, UART4 or UART5. + * @param USART_DMAReq: specifies the DMA request. + * This parameter can be any combination of the following values: + * @arg USART_DMAReq_Tx: USART DMA transmit request + * @arg USART_DMAReq_Rx: USART DMA receive request + * @param NewState: new state of the DMA Request sources. + * This parameter can be: ENABLE or DISABLE. + * @note The DMA mode is not available for UART5 except in the STM32 + * High density value line devices(STM32F10X_HD_VL). + * @retval None + */ +void USART_DMACmd(USART_TypeDef* USARTx, uint16_t USART_DMAReq, FunctionalState NewState) +{ + /* Check the parameters */ + assert_param(IS_USART_ALL_PERIPH(USARTx)); + assert_param(IS_USART_DMAREQ(USART_DMAReq)); + assert_param(IS_FUNCTIONAL_STATE(NewState)); + if (NewState != DISABLE) + { + /* Enable the DMA transfer for selected requests by setting the DMAT and/or + DMAR bits in the USART CR3 register */ + USARTx->CR3 |= USART_DMAReq; + } + else + { + /* Disable the DMA transfer for selected requests by clearing the DMAT and/or + DMAR bits in the USART CR3 register */ + USARTx->CR3 &= (uint16_t)~USART_DMAReq; + } +} + +/** + * @brief Sets the address of the USART node. + * @param USARTx: Select the USART or the UART peripheral. + * This parameter can be one of the following values: + * USART1, USART2, USART3, UART4 or UART5. + * @param USART_Address: Indicates the address of the USART node. + * @retval None + */ +void USART_SetAddress(USART_TypeDef* USARTx, uint8_t USART_Address) +{ + /* Check the parameters */ + assert_param(IS_USART_ALL_PERIPH(USARTx)); + assert_param(IS_USART_ADDRESS(USART_Address)); + + /* Clear the USART address */ + USARTx->CR2 &= CR2_Address_Mask; + /* Set the USART address node */ + USARTx->CR2 |= USART_Address; +} + +/** + * @brief Selects the USART WakeUp method. + * @param USARTx: Select the USART or the UART peripheral. + * This parameter can be one of the following values: + * USART1, USART2, USART3, UART4 or UART5. + * @param USART_WakeUp: specifies the USART wakeup method. + * This parameter can be one of the following values: + * @arg USART_WakeUp_IdleLine: WakeUp by an idle line detection + * @arg USART_WakeUp_AddressMark: WakeUp by an address mark + * @retval None + */ +void USART_WakeUpConfig(USART_TypeDef* USARTx, uint16_t USART_WakeUp) +{ + /* Check the parameters */ + assert_param(IS_USART_ALL_PERIPH(USARTx)); + assert_param(IS_USART_WAKEUP(USART_WakeUp)); + + USARTx->CR1 &= CR1_WAKE_Mask; + USARTx->CR1 |= USART_WakeUp; +} + +/** + * @brief Determines if the USART is in mute mode or not. + * @param USARTx: Select the USART or the UART peripheral. + * This parameter can be one of the following values: + * USART1, USART2, USART3, UART4 or UART5. + * @param NewState: new state of the USART mute mode. + * This parameter can be: ENABLE or DISABLE. + * @retval None + */ +void USART_ReceiverWakeUpCmd(USART_TypeDef* USARTx, FunctionalState NewState) +{ + /* Check the parameters */ + assert_param(IS_USART_ALL_PERIPH(USARTx)); + assert_param(IS_FUNCTIONAL_STATE(NewState)); + + if (NewState != DISABLE) + { + /* Enable the USART mute mode by setting the RWU bit in the CR1 register */ + USARTx->CR1 |= CR1_RWU_Set; + } + else + { + /* Disable the USART mute mode by clearing the RWU bit in the CR1 register */ + USARTx->CR1 &= CR1_RWU_Reset; + } +} + +/** + * @brief Sets the USART LIN Break detection length. + * @param USARTx: Select the USART or the UART peripheral. + * This parameter can be one of the following values: + * USART1, USART2, USART3, UART4 or UART5. + * @param USART_LINBreakDetectLength: specifies the LIN break detection length. + * This parameter can be one of the following values: + * @arg USART_LINBreakDetectLength_10b: 10-bit break detection + * @arg USART_LINBreakDetectLength_11b: 11-bit break detection + * @retval None + */ +void USART_LINBreakDetectLengthConfig(USART_TypeDef* USARTx, uint16_t USART_LINBreakDetectLength) +{ + /* Check the parameters */ + assert_param(IS_USART_ALL_PERIPH(USARTx)); + assert_param(IS_USART_LIN_BREAK_DETECT_LENGTH(USART_LINBreakDetectLength)); + + USARTx->CR2 &= CR2_LBDL_Mask; + USARTx->CR2 |= USART_LINBreakDetectLength; +} + +/** + * @brief Enables or disables the USARTs LIN mode. + * @param USARTx: Select the USART or the UART peripheral. + * This parameter can be one of the following values: + * USART1, USART2, USART3, UART4 or UART5. + * @param NewState: new state of the USART LIN mode. + * This parameter can be: ENABLE or DISABLE. + * @retval None + */ +void USART_LINCmd(USART_TypeDef* USARTx, FunctionalState NewState) +{ + /* Check the parameters */ + assert_param(IS_USART_ALL_PERIPH(USARTx)); + assert_param(IS_FUNCTIONAL_STATE(NewState)); + + if (NewState != DISABLE) + { + /* Enable the LIN mode by setting the LINEN bit in the CR2 register */ + USARTx->CR2 |= CR2_LINEN_Set; + } + else + { + /* Disable the LIN mode by clearing the LINEN bit in the CR2 register */ + USARTx->CR2 &= CR2_LINEN_Reset; + } +} + +/** + * @brief Transmits single data through the USARTx peripheral. + * @param USARTx: Select the USART or the UART peripheral. + * This parameter can be one of the following values: + * USART1, USART2, USART3, UART4 or UART5. + * @param Data: the data to transmit. + * @retval None + */ +void USART_SendData(USART_TypeDef* USARTx, uint16_t Data) +{ + /* Check the parameters */ + assert_param(IS_USART_ALL_PERIPH(USARTx)); + assert_param(IS_USART_DATA(Data)); + + /* Transmit Data */ + USARTx->DR = (Data & (uint16_t)0x01FF); +} + +/** + * @brief Returns the most recent received data by the USARTx peripheral. + * @param USARTx: Select the USART or the UART peripheral. + * This parameter can be one of the following values: + * USART1, USART2, USART3, UART4 or UART5. + * @retval The received data. + */ +uint16_t USART_ReceiveData(USART_TypeDef* USARTx) +{ + /* Check the parameters */ + assert_param(IS_USART_ALL_PERIPH(USARTx)); + + /* Receive Data */ + return (uint16_t)(USARTx->DR & (uint16_t)0x01FF); +} + +/** + * @brief Transmits break characters. + * @param USARTx: Select the USART or the UART peripheral. + * This parameter can be one of the following values: + * USART1, USART2, USART3, UART4 or UART5. + * @retval None + */ +void USART_SendBreak(USART_TypeDef* USARTx) +{ + /* Check the parameters */ + assert_param(IS_USART_ALL_PERIPH(USARTx)); + + /* Send break characters */ + USARTx->CR1 |= CR1_SBK_Set; +} + +/** + * @brief Sets the specified USART guard time. + * @param USARTx: where x can be 1, 2 or 3 to select the USART peripheral. + * @param USART_GuardTime: specifies the guard time. + * @note The guard time bits are not available for UART4 and UART5. + * @retval None + */ +void USART_SetGuardTime(USART_TypeDef* USARTx, uint8_t USART_GuardTime) +{ + /* Check the parameters */ + assert_param(IS_USART_123_PERIPH(USARTx)); + + /* Clear the USART Guard time */ + USARTx->GTPR &= GTPR_LSB_Mask; + /* Set the USART guard time */ + USARTx->GTPR |= (uint16_t)((uint16_t)USART_GuardTime << 0x08); +} + +/** + * @brief Sets the system clock prescaler. + * @param USARTx: Select the USART or the UART peripheral. + * This parameter can be one of the following values: + * USART1, USART2, USART3, UART4 or UART5. + * @param USART_Prescaler: specifies the prescaler clock. + * @note The function is used for IrDA mode with UART4 and UART5. + * @retval None + */ +void USART_SetPrescaler(USART_TypeDef* USARTx, uint8_t USART_Prescaler) +{ + /* Check the parameters */ + assert_param(IS_USART_ALL_PERIPH(USARTx)); + + /* Clear the USART prescaler */ + USARTx->GTPR &= GTPR_MSB_Mask; + /* Set the USART prescaler */ + USARTx->GTPR |= USART_Prescaler; +} + +/** + * @brief Enables or disables the USARTs Smart Card mode. + * @param USARTx: where x can be 1, 2 or 3 to select the USART peripheral. + * @param NewState: new state of the Smart Card mode. + * This parameter can be: ENABLE or DISABLE. + * @note The Smart Card mode is not available for UART4 and UART5. + * @retval None + */ +void USART_SmartCardCmd(USART_TypeDef* USARTx, FunctionalState NewState) +{ + /* Check the parameters */ + assert_param(IS_USART_123_PERIPH(USARTx)); + assert_param(IS_FUNCTIONAL_STATE(NewState)); + if (NewState != DISABLE) + { + /* Enable the SC mode by setting the SCEN bit in the CR3 register */ + USARTx->CR3 |= CR3_SCEN_Set; + } + else + { + /* Disable the SC mode by clearing the SCEN bit in the CR3 register */ + USARTx->CR3 &= CR3_SCEN_Reset; + } +} + +/** + * @brief Enables or disables NACK transmission. + * @param USARTx: where x can be 1, 2 or 3 to select the USART peripheral. + * @param NewState: new state of the NACK transmission. + * This parameter can be: ENABLE or DISABLE. + * @note The Smart Card mode is not available for UART4 and UART5. + * @retval None + */ +void USART_SmartCardNACKCmd(USART_TypeDef* USARTx, FunctionalState NewState) +{ + /* Check the parameters */ + assert_param(IS_USART_123_PERIPH(USARTx)); + assert_param(IS_FUNCTIONAL_STATE(NewState)); + if (NewState != DISABLE) + { + /* Enable the NACK transmission by setting the NACK bit in the CR3 register */ + USARTx->CR3 |= CR3_NACK_Set; + } + else + { + /* Disable the NACK transmission by clearing the NACK bit in the CR3 register */ + USARTx->CR3 &= CR3_NACK_Reset; + } +} + +/** + * @brief Enables or disables the USARTs Half Duplex communication. + * @param USARTx: Select the USART or the UART peripheral. + * This parameter can be one of the following values: + * USART1, USART2, USART3, UART4 or UART5. + * @param NewState: new state of the USART Communication. + * This parameter can be: ENABLE or DISABLE. + * @retval None + */ +void USART_HalfDuplexCmd(USART_TypeDef* USARTx, FunctionalState NewState) +{ + /* Check the parameters */ + assert_param(IS_USART_ALL_PERIPH(USARTx)); + assert_param(IS_FUNCTIONAL_STATE(NewState)); + + if (NewState != DISABLE) + { + /* Enable the Half-Duplex mode by setting the HDSEL bit in the CR3 register */ + USARTx->CR3 |= CR3_HDSEL_Set; + } + else + { + /* Disable the Half-Duplex mode by clearing the HDSEL bit in the CR3 register */ + USARTx->CR3 &= CR3_HDSEL_Reset; + } +} + + +/** + * @brief Enables or disables the USART's 8x oversampling mode. + * @param USARTx: Select the USART or the UART peripheral. + * This parameter can be one of the following values: + * USART1, USART2, USART3, UART4 or UART5. + * @param NewState: new state of the USART one bit sampling method. + * This parameter can be: ENABLE or DISABLE. + * @note + * This function has to be called before calling USART_Init() + * function in order to have correct baudrate Divider value. + * @retval None + */ +void USART_OverSampling8Cmd(USART_TypeDef* USARTx, FunctionalState NewState) +{ + /* Check the parameters */ + assert_param(IS_USART_ALL_PERIPH(USARTx)); + assert_param(IS_FUNCTIONAL_STATE(NewState)); + + if (NewState != DISABLE) + { + /* Enable the 8x Oversampling mode by setting the OVER8 bit in the CR1 register */ + USARTx->CR1 |= CR1_OVER8_Set; + } + else + { + /* Disable the 8x Oversampling mode by clearing the OVER8 bit in the CR1 register */ + USARTx->CR1 &= CR1_OVER8_Reset; + } +} + +/** + * @brief Enables or disables the USART's one bit sampling method. + * @param USARTx: Select the USART or the UART peripheral. + * This parameter can be one of the following values: + * USART1, USART2, USART3, UART4 or UART5. + * @param NewState: new state of the USART one bit sampling method. + * This parameter can be: ENABLE or DISABLE. + * @retval None + */ +void USART_OneBitMethodCmd(USART_TypeDef* USARTx, FunctionalState NewState) +{ + /* Check the parameters */ + assert_param(IS_USART_ALL_PERIPH(USARTx)); + assert_param(IS_FUNCTIONAL_STATE(NewState)); + + if (NewState != DISABLE) + { + /* Enable the one bit method by setting the ONEBITE bit in the CR3 register */ + USARTx->CR3 |= CR3_ONEBITE_Set; + } + else + { + /* Disable tthe one bit method by clearing the ONEBITE bit in the CR3 register */ + USARTx->CR3 &= CR3_ONEBITE_Reset; + } +} + +/** + * @brief Configures the USART's IrDA interface. + * @param USARTx: Select the USART or the UART peripheral. + * This parameter can be one of the following values: + * USART1, USART2, USART3, UART4 or UART5. + * @param USART_IrDAMode: specifies the IrDA mode. + * This parameter can be one of the following values: + * @arg USART_IrDAMode_LowPower + * @arg USART_IrDAMode_Normal + * @retval None + */ +void USART_IrDAConfig(USART_TypeDef* USARTx, uint16_t USART_IrDAMode) +{ + /* Check the parameters */ + assert_param(IS_USART_ALL_PERIPH(USARTx)); + assert_param(IS_USART_IRDA_MODE(USART_IrDAMode)); + + USARTx->CR3 &= CR3_IRLP_Mask; + USARTx->CR3 |= USART_IrDAMode; +} + +/** + * @brief Enables or disables the USART's IrDA interface. + * @param USARTx: Select the USART or the UART peripheral. + * This parameter can be one of the following values: + * USART1, USART2, USART3, UART4 or UART5. + * @param NewState: new state of the IrDA mode. + * This parameter can be: ENABLE or DISABLE. + * @retval None + */ +void USART_IrDACmd(USART_TypeDef* USARTx, FunctionalState NewState) +{ + /* Check the parameters */ + assert_param(IS_USART_ALL_PERIPH(USARTx)); + assert_param(IS_FUNCTIONAL_STATE(NewState)); + + if (NewState != DISABLE) + { + /* Enable the IrDA mode by setting the IREN bit in the CR3 register */ + USARTx->CR3 |= CR3_IREN_Set; + } + else + { + /* Disable the IrDA mode by clearing the IREN bit in the CR3 register */ + USARTx->CR3 &= CR3_IREN_Reset; + } +} + +/** + * @brief Checks whether the specified USART flag is set or not. + * @param USARTx: Select the USART or the UART peripheral. + * This parameter can be one of the following values: + * USART1, USART2, USART3, UART4 or UART5. + * @param USART_FLAG: specifies the flag to check. + * This parameter can be one of the following values: + * @arg USART_FLAG_CTS: CTS Change flag (not available for UART4 and UART5) + * @arg USART_FLAG_LBD: LIN Break detection flag + * @arg USART_FLAG_TXE: Transmit data register empty flag + * @arg USART_FLAG_TC: Transmission Complete flag + * @arg USART_FLAG_RXNE: Receive data register not empty flag + * @arg USART_FLAG_IDLE: Idle Line detection flag + * @arg USART_FLAG_ORE: OverRun Error flag + * @arg USART_FLAG_NE: Noise Error flag + * @arg USART_FLAG_FE: Framing Error flag + * @arg USART_FLAG_PE: Parity Error flag + * @retval The new state of USART_FLAG (SET or RESET). + */ +FlagStatus USART_GetFlagStatus(USART_TypeDef* USARTx, uint16_t USART_FLAG) +{ + FlagStatus bitstatus = RESET; + /* Check the parameters */ + assert_param(IS_USART_ALL_PERIPH(USARTx)); + assert_param(IS_USART_FLAG(USART_FLAG)); + /* The CTS flag is not available for UART4 and UART5 */ + if (USART_FLAG == USART_FLAG_CTS) + { + assert_param(IS_USART_123_PERIPH(USARTx)); + } + + if ((USARTx->SR & USART_FLAG) != (uint16_t)RESET) + { + bitstatus = SET; + } + else + { + bitstatus = RESET; + } + return bitstatus; +} + +/** + * @brief Clears the USARTx's pending flags. + * @param USARTx: Select the USART or the UART peripheral. + * This parameter can be one of the following values: + * USART1, USART2, USART3, UART4 or UART5. + * @param USART_FLAG: specifies the flag to clear. + * This parameter can be any combination of the following values: + * @arg USART_FLAG_CTS: CTS Change flag (not available for UART4 and UART5). + * @arg USART_FLAG_LBD: LIN Break detection flag. + * @arg USART_FLAG_TC: Transmission Complete flag. + * @arg USART_FLAG_RXNE: Receive data register not empty flag. + * + * @note + * - PE (Parity error), FE (Framing error), NE (Noise error), ORE (OverRun + * error) and IDLE (Idle line detected) flags are cleared by software + * sequence: a read operation to USART_SR register (USART_GetFlagStatus()) + * followed by a read operation to USART_DR register (USART_ReceiveData()). + * - RXNE flag can be also cleared by a read to the USART_DR register + * (USART_ReceiveData()). + * - TC flag can be also cleared by software sequence: a read operation to + * USART_SR register (USART_GetFlagStatus()) followed by a write operation + * to USART_DR register (USART_SendData()). + * - TXE flag is cleared only by a write to the USART_DR register + * (USART_SendData()). + * @retval None + */ +void USART_ClearFlag(USART_TypeDef* USARTx, uint16_t USART_FLAG) +{ + /* Check the parameters */ + assert_param(IS_USART_ALL_PERIPH(USARTx)); + assert_param(IS_USART_CLEAR_FLAG(USART_FLAG)); + /* The CTS flag is not available for UART4 and UART5 */ + if ((USART_FLAG & USART_FLAG_CTS) == USART_FLAG_CTS) + { + assert_param(IS_USART_123_PERIPH(USARTx)); + } + + USARTx->SR = (uint16_t)~USART_FLAG; +} + +/** + * @brief Checks whether the specified USART interrupt has occurred or not. + * @param USARTx: Select the USART or the UART peripheral. + * This parameter can be one of the following values: + * USART1, USART2, USART3, UART4 or UART5. + * @param USART_IT: specifies the USART interrupt source to check. + * This parameter can be one of the following values: + * @arg USART_IT_CTS: CTS change interrupt (not available for UART4 and UART5) + * @arg USART_IT_LBD: LIN Break detection interrupt + * @arg USART_IT_TXE: Tansmit Data Register empty interrupt + * @arg USART_IT_TC: Transmission complete interrupt + * @arg USART_IT_RXNE: Receive Data register not empty interrupt + * @arg USART_IT_IDLE: Idle line detection interrupt + * @arg USART_IT_ORE_RX : OverRun Error interrupt if the RXNEIE bit is set + * @arg USART_IT_ORE_ER : OverRun Error interrupt if the EIE bit is set + * @arg USART_IT_NE: Noise Error interrupt + * @arg USART_IT_FE: Framing Error interrupt + * @arg USART_IT_PE: Parity Error interrupt + * @retval The new state of USART_IT (SET or RESET). + */ +ITStatus USART_GetITStatus(USART_TypeDef* USARTx, uint16_t USART_IT) +{ + uint32_t bitpos = 0x00, itmask = 0x00, usartreg = 0x00; + ITStatus bitstatus = RESET; + /* Check the parameters */ + assert_param(IS_USART_ALL_PERIPH(USARTx)); + assert_param(IS_USART_GET_IT(USART_IT)); + /* The CTS interrupt is not available for UART4 and UART5 */ + if (USART_IT == USART_IT_CTS) + { + assert_param(IS_USART_123_PERIPH(USARTx)); + } + + /* Get the USART register index */ + usartreg = (((uint8_t)USART_IT) >> 0x05); + /* Get the interrupt position */ + itmask = USART_IT & IT_Mask; + itmask = (uint32_t)0x01 << itmask; + + if (usartreg == 0x01) /* The IT is in CR1 register */ + { + itmask &= USARTx->CR1; + } + else if (usartreg == 0x02) /* The IT is in CR2 register */ + { + itmask &= USARTx->CR2; + } + else /* The IT is in CR3 register */ + { + itmask &= USARTx->CR3; + } + + bitpos = USART_IT >> 0x08; + bitpos = (uint32_t)0x01 << bitpos; + bitpos &= USARTx->SR; + if ((itmask != (uint16_t)RESET)&&(bitpos != (uint16_t)RESET)) + { + bitstatus = SET; + } + else + { + bitstatus = RESET; + } + + return bitstatus; +} + +/** + * @brief Clears the USARTx's interrupt pending bits. + * @param USARTx: Select the USART or the UART peripheral. + * This parameter can be one of the following values: + * USART1, USART2, USART3, UART4 or UART5. + * @param USART_IT: specifies the interrupt pending bit to clear. + * This parameter can be one of the following values: + * @arg USART_IT_CTS: CTS change interrupt (not available for UART4 and UART5) + * @arg USART_IT_LBD: LIN Break detection interrupt + * @arg USART_IT_TC: Transmission complete interrupt. + * @arg USART_IT_RXNE: Receive Data register not empty interrupt. + * + * @note + * - PE (Parity error), FE (Framing error), NE (Noise error), ORE (OverRun + * error) and IDLE (Idle line detected) pending bits are cleared by + * software sequence: a read operation to USART_SR register + * (USART_GetITStatus()) followed by a read operation to USART_DR register + * (USART_ReceiveData()). + * - RXNE pending bit can be also cleared by a read to the USART_DR register + * (USART_ReceiveData()). + * - TC pending bit can be also cleared by software sequence: a read + * operation to USART_SR register (USART_GetITStatus()) followed by a write + * operation to USART_DR register (USART_SendData()). + * - TXE pending bit is cleared only by a write to the USART_DR register + * (USART_SendData()). + * @retval None + */ +void USART_ClearITPendingBit(USART_TypeDef* USARTx, uint16_t USART_IT) +{ + uint16_t bitpos = 0x00, itmask = 0x00; + /* Check the parameters */ + assert_param(IS_USART_ALL_PERIPH(USARTx)); + assert_param(IS_USART_CLEAR_IT(USART_IT)); + /* The CTS interrupt is not available for UART4 and UART5 */ + if (USART_IT == USART_IT_CTS) + { + assert_param(IS_USART_123_PERIPH(USARTx)); + } + + bitpos = USART_IT >> 0x08; + itmask = ((uint16_t)0x01 << (uint16_t)bitpos); + USARTx->SR = (uint16_t)~itmask; +} +/** + * @} + */ + +/** + * @} + */ + +/** + * @} + */ + +/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ diff --git a/Libraries/STM32F10x_StdPeriph_Driver/src/stm32f10x_wwdg.c b/Libraries/STM32F10x_StdPeriph_Driver/src/stm32f10x_wwdg.c new file mode 100644 index 0000000..0115b24 --- /dev/null +++ b/Libraries/STM32F10x_StdPeriph_Driver/src/stm32f10x_wwdg.c @@ -0,0 +1,230 @@ +/** + ****************************************************************************** + * @file stm32f10x_wwdg.c + * @author MCD Application Team + * @version V3.6.1 + * @date 05-March-2012 + * @brief This file provides all the WWDG firmware functions. + ****************************************************************************** + * @attention + * + *

    © COPYRIGHT 2012 STMicroelectronics

    + * + * Licensed under MCD-ST Liberty SW License Agreement V2, (the "License"); + * You may not use this file except in compliance with the License. + * You may obtain a copy of the License at: + * + * http://www.st.com/software_license_agreement_liberty_v2 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, + * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + * + ****************************************************************************** + */ + +/* Includes ------------------------------------------------------------------*/ +#include "stm32f10x_wwdg.h" +#include "stm32f10x_rcc.h" + +/** @addtogroup STM32F10x_StdPeriph_Driver + * @{ + */ + +/** @defgroup WWDG + * @brief WWDG driver modules + * @{ + */ + +/** @defgroup WWDG_Private_TypesDefinitions + * @{ + */ + +/** + * @} + */ + +/** @defgroup WWDG_Private_Defines + * @{ + */ + +/* ----------- WWDG registers bit address in the alias region ----------- */ +#define WWDG_OFFSET (WWDG_BASE - PERIPH_BASE) + +/* Alias word address of EWI bit */ +#define CFR_OFFSET (WWDG_OFFSET + 0x04) +#define EWI_BitNumber 0x09 +#define CFR_EWI_BB (PERIPH_BB_BASE + (CFR_OFFSET * 32) + (EWI_BitNumber * 4)) + +/* --------------------- WWDG registers bit mask ------------------------ */ + +/* CR register bit mask */ +#define CR_WDGA_Set ((uint32_t)0x00000080) + +/* CFR register bit mask */ +#define CFR_WDGTB_Mask ((uint32_t)0xFFFFFE7F) +#define CFR_W_Mask ((uint32_t)0xFFFFFF80) +#define BIT_Mask ((uint8_t)0x7F) + +/** + * @} + */ + +/** @defgroup WWDG_Private_Macros + * @{ + */ + +/** + * @} + */ + +/** @defgroup WWDG_Private_Variables + * @{ + */ + +/** + * @} + */ + +/** @defgroup WWDG_Private_FunctionPrototypes + * @{ + */ + +/** + * @} + */ + +/** @defgroup WWDG_Private_Functions + * @{ + */ + +/** + * @brief Deinitializes the WWDG peripheral registers to their default reset values. + * @param None + * @retval None + */ +void WWDG_DeInit(void) +{ + RCC_APB1PeriphResetCmd(RCC_APB1Periph_WWDG, ENABLE); + RCC_APB1PeriphResetCmd(RCC_APB1Periph_WWDG, DISABLE); +} + +/** + * @brief Sets the WWDG Prescaler. + * @param WWDG_Prescaler: specifies the WWDG Prescaler. + * This parameter can be one of the following values: + * @arg WWDG_Prescaler_1: WWDG counter clock = (PCLK1/4096)/1 + * @arg WWDG_Prescaler_2: WWDG counter clock = (PCLK1/4096)/2 + * @arg WWDG_Prescaler_4: WWDG counter clock = (PCLK1/4096)/4 + * @arg WWDG_Prescaler_8: WWDG counter clock = (PCLK1/4096)/8 + * @retval None + */ +void WWDG_SetPrescaler(uint32_t WWDG_Prescaler) +{ + uint32_t tmpreg = 0; + /* Check the parameters */ + assert_param(IS_WWDG_PRESCALER(WWDG_Prescaler)); + /* Clear WDGTB[1:0] bits */ + tmpreg = WWDG->CFR & CFR_WDGTB_Mask; + /* Set WDGTB[1:0] bits according to WWDG_Prescaler value */ + tmpreg |= WWDG_Prescaler; + /* Store the new value */ + WWDG->CFR = tmpreg; +} + +/** + * @brief Sets the WWDG window value. + * @param WindowValue: specifies the window value to be compared to the downcounter. + * This parameter value must be lower than 0x80. + * @retval None + */ +void WWDG_SetWindowValue(uint8_t WindowValue) +{ + __IO uint32_t tmpreg = 0; + + /* Check the parameters */ + assert_param(IS_WWDG_WINDOW_VALUE(WindowValue)); + /* Clear W[6:0] bits */ + + tmpreg = WWDG->CFR & CFR_W_Mask; + + /* Set W[6:0] bits according to WindowValue value */ + tmpreg |= WindowValue & (uint32_t) BIT_Mask; + + /* Store the new value */ + WWDG->CFR = tmpreg; +} + +/** + * @brief Enables the WWDG Early Wakeup interrupt(EWI). + * @param None + * @retval None + */ +void WWDG_EnableIT(void) +{ + *(__IO uint32_t *) CFR_EWI_BB = (uint32_t)ENABLE; +} + +/** + * @brief Sets the WWDG counter value. + * @param Counter: specifies the watchdog counter value. + * This parameter must be a number between 0x40 and 0x7F. + * @retval None + */ +void WWDG_SetCounter(uint8_t Counter) +{ + /* Check the parameters */ + assert_param(IS_WWDG_COUNTER(Counter)); + /* Write to T[6:0] bits to configure the counter value, no need to do + a read-modify-write; writing a 0 to WDGA bit does nothing */ + WWDG->CR = Counter & BIT_Mask; +} + +/** + * @brief Enables WWDG and load the counter value. + * @param Counter: specifies the watchdog counter value. + * This parameter must be a number between 0x40 and 0x7F. + * @retval None + */ +void WWDG_Enable(uint8_t Counter) +{ + /* Check the parameters */ + assert_param(IS_WWDG_COUNTER(Counter)); + WWDG->CR = CR_WDGA_Set | Counter; +} + +/** + * @brief Checks whether the Early Wakeup interrupt flag is set or not. + * @param None + * @retval The new state of the Early Wakeup interrupt flag (SET or RESET) + */ +FlagStatus WWDG_GetFlagStatus(void) +{ + return (FlagStatus)(WWDG->SR); +} + +/** + * @brief Clears Early Wakeup interrupt flag. + * @param None + * @retval None + */ +void WWDG_ClearFlag(void) +{ + WWDG->SR = (uint32_t)RESET; +} + +/** + * @} + */ + +/** + * @} + */ + +/** + * @} + */ + +/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ diff --git a/Libraries/STM32_USB-FS-Device_Driver/Release_Notes.html b/Libraries/STM32_USB-FS-Device_Driver/Release_Notes.html new file mode 100644 index 0000000..cfaab7d --- /dev/null +++ b/Libraries/STM32_USB-FS-Device_Driver/Release_Notes.html @@ -0,0 +1,871 @@ + + + + + + Release Notes for STM32F10x, STM32L1xx and STM32F3xx USB-FS-Device Driver + + + + + + + + +
    +

    + +   + + +

    +
    + + + + + + +
    + + + + + + + + + +
    +

    + + Back to Release page + + + + + +

    +

    + Release Notes for +

    +

    +  STM32F10x, STM32L1xx and STM32F3xx USB-FS-Device Driver + + + + +

    +

    + Copyright 2012 STMicroelectronics + + + + + + + +

    +

    + + + + + + + +

    +

    + +   + + +

    + + + + + + +
    +

    + Contents + + +

    +
      +
    1. + + Update History + + +
      2. +
    2. + + License + + +
      3. +
    +

    + Update History


    +

    V4.0.0 / 28-August-2012

    + + +

    Main +Changes

    + + + +
      +
    • Remove support of the USB OTG Full speed in device (peripheral) mode embedded in the STM32F105x/7x devices
      • +
        +
      • All source files starting with prefix otgd_fs (ex. otgd_fs_pcd.c/.h) were removed
        • +
      • There is no change on the API dealing with the USB FS Device  peripheral, full compatibility is maintained vs. V3.4.0
        +
        • +
      • The  STM32F105x/7x devices are supported by the STM32F105/7xx, STM32F2xx and STM32F4xx USB On-The-Go Host and Device Library
        +
        • +
      +
    • usb_type.h: remove Types definition (available in stm32xxx.h file, ex. stm32f10x.h)
      +
      • +
    +

    V3.4.0 / 12-March-2012

    +

    Main +Changes

    + +
    • All source files: license disclaimer text update and add link to the License file on ST Internet.
    +

    + V3.3.0 / 21-March-2011 +

    +

    + + Main Changes + + + +

    +
      +
    • + Update library driver to support + + + STM32L15x Medium-Density Low-Power + + + devices (add STM32L1xx defines). +
      • +
    • + Minor fixes: +
      • +
        +
      • + otgd_fs_cal.c: correction of iteration number in OTGD_FS_CoreInitDev() function. +
        • +
      +
        +
      • + usb_core.c: update the remote wakeup checking condition in NoData_Setup0() function. +
        • +
      +
        +
      • + otgd_fs_int.c: update the data count in case of 0 packet length in OTGD_FS_Handle_RxStatusQueueLevel_ISR() function. +
        • +
      +
    + + + + + +

    + + License + + +

    Licensed under MCD-ST Liberty SW License Agreement V2, (the "License"); You may not use this package except in compliance with the License. You may obtain a copy of the License at:


    Unless +required by applicable law or agreed to in writing, software +distributed under the License is distributed on an "AS IS" BASIS,
    WITHOUT +WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See +the License for the specific language governing permissions and +limitations under the License.     +
    +     +
    +

    + For + complete documentation on STM32 + Microcontrollers visit www.st.com/STM32 + + + +

    +

    + + + + +

    +
    +

    +   + +

    +
    + \ No newline at end of file diff --git a/Libraries/STM32_USB-FS-Device_Driver/inc/usb_core.h b/Libraries/STM32_USB-FS-Device_Driver/inc/usb_core.h new file mode 100644 index 0000000..bf303f7 --- /dev/null +++ b/Libraries/STM32_USB-FS-Device_Driver/inc/usb_core.h @@ -0,0 +1,259 @@ +/** + ****************************************************************************** + * @file usb_core.h + * @author MCD Application Team + * @version V4.0.0 + * @date 28-August-2012 + * @brief Standard protocol processing functions prototypes + ****************************************************************************** + * @attention + * + *

    © COPYRIGHT 2012 STMicroelectronics

    + * + * Licensed under MCD-ST Liberty SW License Agreement V2, (the "License"); + * You may not use this file except in compliance with the License. + * You may obtain a copy of the License at: + * + * http://www.st.com/software_license_agreement_liberty_v2 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, + * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + * + ****************************************************************************** + */ + + +/* Define to prevent recursive inclusion -------------------------------------*/ +#ifndef __USB_CORE_H +#define __USB_CORE_H + +/* Includes ------------------------------------------------------------------*/ +/* Exported types ------------------------------------------------------------*/ +typedef enum _CONTROL_STATE +{ + WAIT_SETUP, /* 0 */ + SETTING_UP, /* 1 */ + IN_DATA, /* 2 */ + OUT_DATA, /* 3 */ + LAST_IN_DATA, /* 4 */ + LAST_OUT_DATA, /* 5 */ + WAIT_STATUS_IN, /* 7 */ + WAIT_STATUS_OUT, /* 8 */ + STALLED, /* 9 */ + PAUSE /* 10 */ +} CONTROL_STATE; /* The state machine states of a control pipe */ + +typedef struct OneDescriptor +{ + uint8_t *Descriptor; + uint16_t Descriptor_Size; +} +ONE_DESCRIPTOR, *PONE_DESCRIPTOR; +/* All the request process routines return a value of this type + If the return value is not SUCCESS or NOT_READY, + the software will STALL the correspond endpoint */ +typedef enum _RESULT +{ + USB_SUCCESS = 0, /* Process successfully */ + USB_ERROR, + USB_UNSUPPORT, + USB_NOT_READY /* The process has not been finished, endpoint will be + NAK to further request */ +} RESULT; + + +/*-*-*-*-*-*-*-*-*-*-* Definitions for endpoint level -*-*-*-*-*-*-*-*-*-*-*-*/ +typedef struct _ENDPOINT_INFO +{ + /* When send data out of the device, + CopyData() is used to get data buffer 'Length' bytes data + if Length is 0, + CopyData() returns the total length of the data + if the request is not supported, returns 0 + (NEW Feature ) + if CopyData() returns -1, the calling routine should not proceed + further and will resume the SETUP process by the class device + if Length is not 0, + CopyData() returns a pointer to indicate the data location + Usb_wLength is the data remain to be sent, + Usb_wOffset is the Offset of original data + When receive data from the host, + CopyData() is used to get user data buffer which is capable + of Length bytes data to copy data from the endpoint buffer. + if Length is 0, + CopyData() returns the available data length, + if Length is not 0, + CopyData() returns user buffer address + Usb_rLength is the data remain to be received, + Usb_rPointer is the Offset of data buffer + */ + uint16_t Usb_wLength; + uint16_t Usb_wOffset; + uint16_t PacketSize; + uint8_t *(*CopyData)(uint16_t Length); +}ENDPOINT_INFO; + +/*-*-*-*-*-*-*-*-*-*-*-* Definitions for device level -*-*-*-*-*-*-*-*-*-*-*-*/ + +typedef struct _DEVICE +{ + uint8_t Total_Endpoint; /* Number of endpoints that are used */ + uint8_t Total_Configuration;/* Number of configuration available */ +} +DEVICE; + +typedef union +{ + uint16_t w; + struct BW + { + uint8_t bb1; + uint8_t bb0; + } + bw; +} uint16_t_uint8_t; + +typedef struct _DEVICE_INFO +{ + uint8_t USBbmRequestType; /* bmRequestType */ + uint8_t USBbRequest; /* bRequest */ + uint16_t_uint8_t USBwValues; /* wValue */ + uint16_t_uint8_t USBwIndexs; /* wIndex */ + uint16_t_uint8_t USBwLengths; /* wLength */ + + uint8_t ControlState; /* of type CONTROL_STATE */ + uint8_t Current_Feature; + uint8_t Current_Configuration; /* Selected configuration */ + uint8_t Current_Interface; /* Selected interface of current configuration */ + uint8_t Current_AlternateSetting;/* Selected Alternate Setting of current + interface*/ + + ENDPOINT_INFO Ctrl_Info; +}DEVICE_INFO; + +typedef struct _DEVICE_PROP +{ + void (*Init)(void); /* Initialize the device */ + void (*Reset)(void); /* Reset routine of this device */ + + /* Device dependent process after the status stage */ + void (*Process_Status_IN)(void); + void (*Process_Status_OUT)(void); + + /* Procedure of process on setup stage of a class specified request with data stage */ + /* All class specified requests with data stage are processed in Class_Data_Setup + Class_Data_Setup() + responses to check all special requests and fills ENDPOINT_INFO + according to the request + If IN tokens are expected, then wLength & wOffset will be filled + with the total transferring bytes and the starting position + If OUT tokens are expected, then rLength & rOffset will be filled + with the total expected bytes and the starting position in the buffer + + If the request is valid, Class_Data_Setup returns SUCCESS, else UNSUPPORT + + CAUTION: + Since GET_CONFIGURATION & GET_INTERFACE are highly related to + the individual classes, they will be checked and processed here. + */ + RESULT (*Class_Data_Setup)(uint8_t RequestNo); + + /* Procedure of process on setup stage of a class specified request without data stage */ + /* All class specified requests without data stage are processed in Class_NoData_Setup + Class_NoData_Setup + responses to check all special requests and perform the request + + CAUTION: + Since SET_CONFIGURATION & SET_INTERFACE are highly related to + the individual classes, they will be checked and processed here. + */ + RESULT (*Class_NoData_Setup)(uint8_t RequestNo); + + /*Class_Get_Interface_Setting + This function is used by the file usb_core.c to test if the selected Interface + and Alternate Setting (uint8_t Interface, uint8_t AlternateSetting) are supported by + the application. + This function is writing by user. It should return "SUCCESS" if the Interface + and Alternate Setting are supported by the application or "UNSUPPORT" if they + are not supported. */ + + RESULT (*Class_Get_Interface_Setting)(uint8_t Interface, uint8_t AlternateSetting); + + uint8_t* (*GetDeviceDescriptor)(uint16_t Length); + uint8_t* (*GetConfigDescriptor)(uint16_t Length); + uint8_t* (*GetStringDescriptor)(uint16_t Length); + + /* This field is not used in current library version. It is kept only for + compatibility with previous versions */ + void* RxEP_buffer; + + uint8_t MaxPacketSize; + +}DEVICE_PROP; + +typedef struct _USER_STANDARD_REQUESTS +{ + void (*User_GetConfiguration)(void); /* Get Configuration */ + void (*User_SetConfiguration)(void); /* Set Configuration */ + void (*User_GetInterface)(void); /* Get Interface */ + void (*User_SetInterface)(void); /* Set Interface */ + void (*User_GetStatus)(void); /* Get Status */ + void (*User_ClearFeature)(void); /* Clear Feature */ + void (*User_SetEndPointFeature)(void); /* Set Endpoint Feature */ + void (*User_SetDeviceFeature)(void); /* Set Device Feature */ + void (*User_SetDeviceAddress)(void); /* Set Device Address */ +} +USER_STANDARD_REQUESTS; + +/* Exported constants --------------------------------------------------------*/ +#define Type_Recipient (pInformation->USBbmRequestType & (REQUEST_TYPE | RECIPIENT)) + +#define Usb_rLength Usb_wLength +#define Usb_rOffset Usb_wOffset + +#define USBwValue USBwValues.w +#define USBwValue0 USBwValues.bw.bb0 +#define USBwValue1 USBwValues.bw.bb1 +#define USBwIndex USBwIndexs.w +#define USBwIndex0 USBwIndexs.bw.bb0 +#define USBwIndex1 USBwIndexs.bw.bb1 +#define USBwLength USBwLengths.w +#define USBwLength0 USBwLengths.bw.bb0 +#define USBwLength1 USBwLengths.bw.bb1 + +/* Exported macro ------------------------------------------------------------*/ +/* Exported functions ------------------------------------------------------- */ +uint8_t Setup0_Process(void); +uint8_t Post0_Process(void); +uint8_t Out0_Process(void); +uint8_t In0_Process(void); + +RESULT Standard_SetEndPointFeature(void); +RESULT Standard_SetDeviceFeature(void); + +uint8_t *Standard_GetConfiguration(uint16_t Length); +RESULT Standard_SetConfiguration(void); +uint8_t *Standard_GetInterface(uint16_t Length); +RESULT Standard_SetInterface(void); +uint8_t *Standard_GetDescriptorData(uint16_t Length, PONE_DESCRIPTOR pDesc); + +uint8_t *Standard_GetStatus(uint16_t Length); +RESULT Standard_ClearFeature(void); +void SetDeviceAddress(uint8_t); +void NOP_Process(void); + +extern DEVICE_PROP Device_Property; +extern USER_STANDARD_REQUESTS User_Standard_Requests; +extern DEVICE Device_Table; +extern DEVICE_INFO Device_Info; + +/* cells saving status during interrupt servicing */ +extern __IO uint16_t SaveRState; +extern __IO uint16_t SaveTState; + +#endif /* __USB_CORE_H */ + +/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ diff --git a/Libraries/STM32_USB-FS-Device_Driver/inc/usb_def.h b/Libraries/STM32_USB-FS-Device_Driver/inc/usb_def.h new file mode 100644 index 0000000..7f6e1b5 --- /dev/null +++ b/Libraries/STM32_USB-FS-Device_Driver/inc/usb_def.h @@ -0,0 +1,92 @@ +/** + ****************************************************************************** + * @file usb_def.h + * @author MCD Application Team + * @version V4.0.0 + * @date 28-August-2012 + * @brief Definitions related to USB Core + ****************************************************************************** + * @attention + * + *

    © COPYRIGHT 2012 STMicroelectronics

    + * + * Licensed under MCD-ST Liberty SW License Agreement V2, (the "License"); + * You may not use this file except in compliance with the License. + * You may obtain a copy of the License at: + * + * http://www.st.com/software_license_agreement_liberty_v2 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, + * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + * + ****************************************************************************** + */ + +/* Define to prevent recursive inclusion -------------------------------------*/ +#ifndef __USB_DEF_H +#define __USB_DEF_H + +/* Includes ------------------------------------------------------------------*/ +/* Exported types ------------------------------------------------------------*/ +typedef enum _RECIPIENT_TYPE +{ + DEVICE_RECIPIENT, /* Recipient device */ + INTERFACE_RECIPIENT, /* Recipient interface */ + ENDPOINT_RECIPIENT, /* Recipient endpoint */ + OTHER_RECIPIENT +} RECIPIENT_TYPE; + + +typedef enum _STANDARD_REQUESTS +{ + GET_STATUS = 0, + CLEAR_FEATURE, + RESERVED1, + SET_FEATURE, + RESERVED2, + SET_ADDRESS, + GET_DESCRIPTOR, + SET_DESCRIPTOR, + GET_CONFIGURATION, + SET_CONFIGURATION, + GET_INTERFACE, + SET_INTERFACE, + TOTAL_sREQUEST, /* Total number of Standard request */ + SYNCH_FRAME = 12 +} STANDARD_REQUESTS; + +/* Definition of "USBwValue" */ +typedef enum _DESCRIPTOR_TYPE +{ + DEVICE_DESCRIPTOR = 1, + CONFIG_DESCRIPTOR, + STRING_DESCRIPTOR, + INTERFACE_DESCRIPTOR, + ENDPOINT_DESCRIPTOR +} DESCRIPTOR_TYPE; + +/* Feature selector of a SET_FEATURE or CLEAR_FEATURE */ +typedef enum _FEATURE_SELECTOR +{ + ENDPOINT_STALL, + DEVICE_REMOTE_WAKEUP +} FEATURE_SELECTOR; + +/* Exported constants --------------------------------------------------------*/ +/* Definition of "USBbmRequestType" */ +#define REQUEST_TYPE 0x60 /* Mask to get request type */ +#define STANDARD_REQUEST 0x00 /* Standard request */ +#define CLASS_REQUEST 0x20 /* Class request */ +#define VENDOR_REQUEST 0x40 /* Vendor request */ + +#define RECIPIENT 0x1F /* Mask to get recipient */ + +/* Exported macro ------------------------------------------------------------*/ +/* Exported functions ------------------------------------------------------- */ + +#endif /* __USB_DEF_H */ + +/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ diff --git a/Libraries/STM32_USB-FS-Device_Driver/inc/usb_init.h b/Libraries/STM32_USB-FS-Device_Driver/inc/usb_init.h new file mode 100644 index 0000000..44b528c --- /dev/null +++ b/Libraries/STM32_USB-FS-Device_Driver/inc/usb_init.h @@ -0,0 +1,62 @@ +/** + ****************************************************************************** + * @file usb_init.h + * @author MCD Application Team + * @version V4.0.0 + * @date 28-August-2012 + * @brief Initialization routines & global variables + ****************************************************************************** + * @attention + * + *

    © COPYRIGHT 2012 STMicroelectronics

    + * + * Licensed under MCD-ST Liberty SW License Agreement V2, (the "License"); + * You may not use this file except in compliance with the License. + * You may obtain a copy of the License at: + * + * http://www.st.com/software_license_agreement_liberty_v2 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, + * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + * + ****************************************************************************** + */ + + +/* Define to prevent recursive inclusion -------------------------------------*/ +#ifndef __USB_INIT_H +#define __USB_INIT_H + +/* Includes ------------------------------------------------------------------*/ +/* Exported types ------------------------------------------------------------*/ +/* Exported constants --------------------------------------------------------*/ +/* Exported macro ------------------------------------------------------------*/ +/* Exported functions ------------------------------------------------------- */ +void USB_Init(void); + +/* External variables --------------------------------------------------------*/ +/* The number of current endpoint, it will be used to specify an endpoint */ +extern uint8_t EPindex; +/* The number of current device, it is an index to the Device_Table */ +/*extern uint8_t Device_no; */ +/* Points to the DEVICE_INFO structure of current device */ +/* The purpose of this register is to speed up the execution */ +extern DEVICE_INFO* pInformation; +/* Points to the DEVICE_PROP structure of current device */ +/* The purpose of this register is to speed up the execution */ +extern DEVICE_PROP* pProperty; +/* Temporary save the state of Rx & Tx status. */ +/* Whenever the Rx or Tx state is changed, its value is saved */ +/* in this variable first and will be set to the EPRB or EPRA */ +/* at the end of interrupt process */ +extern USER_STANDARD_REQUESTS *pUser_Standard_Requests; + +extern uint16_t SaveState ; +extern uint16_t wInterrupt_Mask; + +#endif /* __USB_INIT_H */ + +/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ diff --git a/Libraries/STM32_USB-FS-Device_Driver/inc/usb_int.h b/Libraries/STM32_USB-FS-Device_Driver/inc/usb_int.h new file mode 100644 index 0000000..307ab14 --- /dev/null +++ b/Libraries/STM32_USB-FS-Device_Driver/inc/usb_int.h @@ -0,0 +1,45 @@ +/** + ****************************************************************************** + * @file usb_int.h + * @author MCD Application Team + * @version V4.0.0 + * @date 28-August-2012 + * @brief Endpoint CTR (Low and High) interrupt's service routines prototypes + ****************************************************************************** + * @attention + * + *

    © COPYRIGHT 2012 STMicroelectronics

    + * + * Licensed under MCD-ST Liberty SW License Agreement V2, (the "License"); + * You may not use this file except in compliance with the License. + * You may obtain a copy of the License at: + * + * http://www.st.com/software_license_agreement_liberty_v2 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, + * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + * + ****************************************************************************** + */ + + +/* Define to prevent recursive inclusion -------------------------------------*/ +#ifndef __USB_INT_H +#define __USB_INT_H + +/* Includes ------------------------------------------------------------------*/ +/* Exported types ------------------------------------------------------------*/ +/* Exported constants --------------------------------------------------------*/ +/* Exported macro ------------------------------------------------------------*/ +/* Exported functions ------------------------------------------------------- */ +void CTR_LP(void); +void CTR_HP(void); + +/* External variables --------------------------------------------------------*/ + +#endif /* __USB_INT_H */ + +/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ diff --git a/Libraries/STM32_USB-FS-Device_Driver/inc/usb_lib.h b/Libraries/STM32_USB-FS-Device_Driver/inc/usb_lib.h new file mode 100644 index 0000000..510478f --- /dev/null +++ b/Libraries/STM32_USB-FS-Device_Driver/inc/usb_lib.h @@ -0,0 +1,53 @@ +/** + ****************************************************************************** + * @file usb_lib.h + * @author MCD Application Team + * @version V4.0.0 + * @date 28-August-2012 + * @brief USB library include files + ****************************************************************************** + * @attention + * + *

    © COPYRIGHT 2012 STMicroelectronics

    + * + * Licensed under MCD-ST Liberty SW License Agreement V2, (the "License"); + * You may not use this file except in compliance with the License. + * You may obtain a copy of the License at: + * + * http://www.st.com/software_license_agreement_liberty_v2 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, + * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + * + ****************************************************************************** + */ + + +/* Define to prevent recursive inclusion -------------------------------------*/ +#ifndef __USB_LIB_H +#define __USB_LIB_H + +/* Includes ------------------------------------------------------------------*/ +//#include "hw_config.h" +#include "usb_hw.h" +#include "usb_type.h" +#include "usb_regs.h" +#include "usb_def.h" +#include "usb_core.h" +#include "usb_init.h" +#include "usb_sil.h" +#include "usb_mem.h" +#include "usb_int.h" + +/* Exported types ------------------------------------------------------------*/ +/* Exported constants --------------------------------------------------------*/ +/* Exported macro ------------------------------------------------------------*/ +/* Exported functions ------------------------------------------------------- */ +/* External variables --------------------------------------------------------*/ + +#endif /* __USB_LIB_H */ + +/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ diff --git a/Libraries/STM32_USB-FS-Device_Driver/inc/usb_mem.h b/Libraries/STM32_USB-FS-Device_Driver/inc/usb_mem.h new file mode 100644 index 0000000..0b29100 --- /dev/null +++ b/Libraries/STM32_USB-FS-Device_Driver/inc/usb_mem.h @@ -0,0 +1,45 @@ +/** + ****************************************************************************** + * @file usb_mem.h + * @author MCD Application Team + * @version V4.0.0 + * @date 28-August-2012 + * @brief Utility prototypes functions for memory/PMA transfers + ****************************************************************************** + * @attention + * + *

    © COPYRIGHT 2012 STMicroelectronics

    + * + * Licensed under MCD-ST Liberty SW License Agreement V2, (the "License"); + * You may not use this file except in compliance with the License. + * You may obtain a copy of the License at: + * + * http://www.st.com/software_license_agreement_liberty_v2 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, + * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + * + ****************************************************************************** + */ + + +/* Define to prevent recursive inclusion -------------------------------------*/ +#ifndef __USB_MEM_H +#define __USB_MEM_H + +/* Includes ------------------------------------------------------------------*/ +/* Exported types ------------------------------------------------------------*/ +/* Exported constants --------------------------------------------------------*/ +/* Exported macro ------------------------------------------------------------*/ +/* Exported functions ------------------------------------------------------- */ +void UserToPMABufferCopy(uint8_t *pbUsrBuf, uint16_t wPMABufAddr, uint16_t wNBytes); +void PMAToUserBufferCopy(uint8_t *pbUsrBuf, uint16_t wPMABufAddr, uint16_t wNBytes); + +/* External variables --------------------------------------------------------*/ + +#endif /*__USB_MEM_H*/ + +/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ diff --git a/Libraries/STM32_USB-FS-Device_Driver/inc/usb_regs.h b/Libraries/STM32_USB-FS-Device_Driver/inc/usb_regs.h new file mode 100644 index 0000000..87e0a00 --- /dev/null +++ b/Libraries/STM32_USB-FS-Device_Driver/inc/usb_regs.h @@ -0,0 +1,680 @@ +/** + ****************************************************************************** + * @file usb_regs.h + * @author MCD Application Team + * @version V4.0.0 + * @date 28-August-2012 + * @brief Interface prototype functions to USB cell registers + ****************************************************************************** + * @attention + * + *

    © COPYRIGHT 2012 STMicroelectronics

    + * + * Licensed under MCD-ST Liberty SW License Agreement V2, (the "License"); + * You may not use this file except in compliance with the License. + * You may obtain a copy of the License at: + * + * http://www.st.com/software_license_agreement_liberty_v2 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, + * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + * + ****************************************************************************** + */ + + +/* Define to prevent recursive inclusion -------------------------------------*/ +#ifndef __USB_REGS_H +#define __USB_REGS_H + +/* Includes ------------------------------------------------------------------*/ +/* Exported types ------------------------------------------------------------*/ +typedef enum _EP_DBUF_DIR +{ + /* double buffered endpoint direction */ + EP_DBUF_ERR, + EP_DBUF_OUT, + EP_DBUF_IN +}EP_DBUF_DIR; + +/* endpoint buffer number */ +enum EP_BUF_NUM +{ + EP_NOBUF, + EP_BUF0, + EP_BUF1 +}; + +/* Exported constants --------------------------------------------------------*/ +#define RegBase (0x40005C00L) /* USB_IP Peripheral Registers base address */ +#define PMAAddr (0x40006000L) /* USB_IP Packet Memory Area base address */ + +/******************************************************************************/ +/* General registers */ +/******************************************************************************/ + +/* Control register */ +#define CNTR ((__IO unsigned *)(RegBase + 0x40)) +/* Interrupt status register */ +#define ISTR ((__IO unsigned *)(RegBase + 0x44)) +/* Frame number register */ +#define FNR ((__IO unsigned *)(RegBase + 0x48)) +/* Device address register */ +#define DADDR ((__IO unsigned *)(RegBase + 0x4C)) +/* Buffer Table address register */ +#define BTABLE ((__IO unsigned *)(RegBase + 0x50)) +/******************************************************************************/ +/* Endpoint registers */ +/******************************************************************************/ +#define EP0REG ((__IO unsigned *)(RegBase)) /* endpoint 0 register address */ + +/* Endpoint Addresses (w/direction) */ +#define EP0_OUT ((uint8_t)0x00) +#define EP0_IN ((uint8_t)0x80) +#define EP1_OUT ((uint8_t)0x01) +#define EP1_IN ((uint8_t)0x81) +#define EP2_OUT ((uint8_t)0x02) +#define EP2_IN ((uint8_t)0x82) +#define EP3_OUT ((uint8_t)0x03) +#define EP3_IN ((uint8_t)0x83) +#define EP4_OUT ((uint8_t)0x04) +#define EP4_IN ((uint8_t)0x84) +#define EP5_OUT ((uint8_t)0x05) +#define EP5_IN ((uint8_t)0x85) +#define EP6_OUT ((uint8_t)0x06) +#define EP6_IN ((uint8_t)0x86) +#define EP7_OUT ((uint8_t)0x07) +#define EP7_IN ((uint8_t)0x87) + +/* endpoints enumeration */ +#define ENDP0 ((uint8_t)0) +#define ENDP1 ((uint8_t)1) +#define ENDP2 ((uint8_t)2) +#define ENDP3 ((uint8_t)3) +#define ENDP4 ((uint8_t)4) +#define ENDP5 ((uint8_t)5) +#define ENDP6 ((uint8_t)6) +#define ENDP7 ((uint8_t)7) + +/******************************************************************************/ +/* ISTR interrupt events */ +/******************************************************************************/ +#define ISTR_CTR (0x8000) /* Correct TRansfer (clear-only bit) */ +#define ISTR_DOVR (0x4000) /* DMA OVeR/underrun (clear-only bit) */ +#define ISTR_ERR (0x2000) /* ERRor (clear-only bit) */ +#define ISTR_WKUP (0x1000) /* WaKe UP (clear-only bit) */ +#define ISTR_SUSP (0x0800) /* SUSPend (clear-only bit) */ +#define ISTR_RESET (0x0400) /* RESET (clear-only bit) */ +#define ISTR_SOF (0x0200) /* Start Of Frame (clear-only bit) */ +#define ISTR_ESOF (0x0100) /* Expected Start Of Frame (clear-only bit) */ + + +#define ISTR_DIR (0x0010) /* DIRection of transaction (read-only bit) */ +#define ISTR_EP_ID (0x000F) /* EndPoint IDentifier (read-only bit) */ + +#define CLR_CTR (~ISTR_CTR) /* clear Correct TRansfer bit */ +#define CLR_DOVR (~ISTR_DOVR) /* clear DMA OVeR/underrun bit*/ +#define CLR_ERR (~ISTR_ERR) /* clear ERRor bit */ +#define CLR_WKUP (~ISTR_WKUP) /* clear WaKe UP bit */ +#define CLR_SUSP (~ISTR_SUSP) /* clear SUSPend bit */ +#define CLR_RESET (~ISTR_RESET) /* clear RESET bit */ +#define CLR_SOF (~ISTR_SOF) /* clear Start Of Frame bit */ +#define CLR_ESOF (~ISTR_ESOF) /* clear Expected Start Of Frame bit */ + +/******************************************************************************/ +/* CNTR control register bits definitions */ +/******************************************************************************/ +#define CNTR_CTRM (0x8000) /* Correct TRansfer Mask */ +#define CNTR_DOVRM (0x4000) /* DMA OVeR/underrun Mask */ +#define CNTR_ERRM (0x2000) /* ERRor Mask */ +#define CNTR_WKUPM (0x1000) /* WaKe UP Mask */ +#define CNTR_SUSPM (0x0800) /* SUSPend Mask */ +#define CNTR_RESETM (0x0400) /* RESET Mask */ +#define CNTR_SOFM (0x0200) /* Start Of Frame Mask */ +#define CNTR_ESOFM (0x0100) /* Expected Start Of Frame Mask */ + + +#define CNTR_RESUME (0x0010) /* RESUME request */ +#define CNTR_FSUSP (0x0008) /* Force SUSPend */ +#define CNTR_LPMODE (0x0004) /* Low-power MODE */ +#define CNTR_PDWN (0x0002) /* Power DoWN */ +#define CNTR_FRES (0x0001) /* Force USB RESet */ + +/******************************************************************************/ +/* FNR Frame Number Register bit definitions */ +/******************************************************************************/ +#define FNR_RXDP (0x8000) /* status of D+ data line */ +#define FNR_RXDM (0x4000) /* status of D- data line */ +#define FNR_LCK (0x2000) /* LoCKed */ +#define FNR_LSOF (0x1800) /* Lost SOF */ +#define FNR_FN (0x07FF) /* Frame Number */ +/******************************************************************************/ +/* DADDR Device ADDRess bit definitions */ +/******************************************************************************/ +#define DADDR_EF (0x80) +#define DADDR_ADD (0x7F) +/******************************************************************************/ +/* Endpoint register */ +/******************************************************************************/ +/* bit positions */ +#define EP_CTR_RX (0x8000) /* EndPoint Correct TRansfer RX */ +#define EP_DTOG_RX (0x4000) /* EndPoint Data TOGGLE RX */ +#define EPRX_STAT (0x3000) /* EndPoint RX STATus bit field */ +#define EP_SETUP (0x0800) /* EndPoint SETUP */ +#define EP_T_FIELD (0x0600) /* EndPoint TYPE */ +#define EP_KIND (0x0100) /* EndPoint KIND */ +#define EP_CTR_TX (0x0080) /* EndPoint Correct TRansfer TX */ +#define EP_DTOG_TX (0x0040) /* EndPoint Data TOGGLE TX */ +#define EPTX_STAT (0x0030) /* EndPoint TX STATus bit field */ +#define EPADDR_FIELD (0x000F) /* EndPoint ADDRess FIELD */ + +/* EndPoint REGister MASK (no toggle fields) */ +#define EPREG_MASK (EP_CTR_RX|EP_SETUP|EP_T_FIELD|EP_KIND|EP_CTR_TX|EPADDR_FIELD) + +/* EP_TYPE[1:0] EndPoint TYPE */ +#define EP_TYPE_MASK (0x0600) /* EndPoint TYPE Mask */ +#define EP_BULK (0x0000) /* EndPoint BULK */ +#define EP_CONTROL (0x0200) /* EndPoint CONTROL */ +#define EP_ISOCHRONOUS (0x0400) /* EndPoint ISOCHRONOUS */ +#define EP_INTERRUPT (0x0600) /* EndPoint INTERRUPT */ +#define EP_T_MASK (~EP_T_FIELD & EPREG_MASK) + + +/* EP_KIND EndPoint KIND */ +#define EPKIND_MASK (~EP_KIND & EPREG_MASK) + +/* STAT_TX[1:0] STATus for TX transfer */ +#define EP_TX_DIS (0x0000) /* EndPoint TX DISabled */ +#define EP_TX_STALL (0x0010) /* EndPoint TX STALLed */ +#define EP_TX_NAK (0x0020) /* EndPoint TX NAKed */ +#define EP_TX_VALID (0x0030) /* EndPoint TX VALID */ +#define EPTX_DTOG1 (0x0010) /* EndPoint TX Data TOGgle bit1 */ +#define EPTX_DTOG2 (0x0020) /* EndPoint TX Data TOGgle bit2 */ +#define EPTX_DTOGMASK (EPTX_STAT|EPREG_MASK) + +/* STAT_RX[1:0] STATus for RX transfer */ +#define EP_RX_DIS (0x0000) /* EndPoint RX DISabled */ +#define EP_RX_STALL (0x1000) /* EndPoint RX STALLed */ +#define EP_RX_NAK (0x2000) /* EndPoint RX NAKed */ +#define EP_RX_VALID (0x3000) /* EndPoint RX VALID */ +#define EPRX_DTOG1 (0x1000) /* EndPoint RX Data TOGgle bit1 */ +#define EPRX_DTOG2 (0x2000) /* EndPoint RX Data TOGgle bit1 */ +#define EPRX_DTOGMASK (EPRX_STAT|EPREG_MASK) +/* Exported macro ------------------------------------------------------------*/ +/* SetCNTR */ +#define _SetCNTR(wRegValue) (*CNTR = (uint16_t)wRegValue) + +/* SetISTR */ +#define _SetISTR(wRegValue) (*ISTR = (uint16_t)wRegValue) + +/* SetDADDR */ +#define _SetDADDR(wRegValue) (*DADDR = (uint16_t)wRegValue) + +/* SetBTABLE */ +#define _SetBTABLE(wRegValue)(*BTABLE = (uint16_t)(wRegValue & 0xFFF8)) + +/* GetCNTR */ +#define _GetCNTR() ((uint16_t) *CNTR) + +/* GetISTR */ +#define _GetISTR() ((uint16_t) *ISTR) + +/* GetFNR */ +#define _GetFNR() ((uint16_t) *FNR) + +/* GetDADDR */ +#define _GetDADDR() ((uint16_t) *DADDR) + +/* GetBTABLE */ +#define _GetBTABLE() ((uint16_t) *BTABLE) + +/* SetENDPOINT */ +#define _SetENDPOINT(bEpNum,wRegValue) (*(EP0REG + bEpNum)= \ + (uint16_t)wRegValue) + +/* GetENDPOINT */ +#define _GetENDPOINT(bEpNum) ((uint16_t)(*(EP0REG + bEpNum))) + +/******************************************************************************* +* Macro Name : SetEPType +* Description : sets the type in the endpoint register(bits EP_TYPE[1:0]) +* Input : bEpNum: Endpoint Number. +* wType +* Output : None. +* Return : None. +*******************************************************************************/ +#define _SetEPType(bEpNum,wType) (_SetENDPOINT(bEpNum,\ + ((_GetENDPOINT(bEpNum) & EP_T_MASK) | wType ))) + +/******************************************************************************* +* Macro Name : GetEPType +* Description : gets the type in the endpoint register(bits EP_TYPE[1:0]) +* Input : bEpNum: Endpoint Number. +* Output : None. +* Return : Endpoint Type +*******************************************************************************/ +#define _GetEPType(bEpNum) (_GetENDPOINT(bEpNum) & EP_T_FIELD) + +/******************************************************************************* +* Macro Name : SetEPTxStatus +* Description : sets the status for tx transfer (bits STAT_TX[1:0]). +* Input : bEpNum: Endpoint Number. +* wState: new state +* Output : None. +* Return : None. +*******************************************************************************/ +#define _SetEPTxStatus(bEpNum,wState) {\ + register uint16_t _wRegVal; \ + _wRegVal = _GetENDPOINT(bEpNum) & EPTX_DTOGMASK;\ + /* toggle first bit ? */ \ + if((EPTX_DTOG1 & wState)!= 0) \ + _wRegVal ^= EPTX_DTOG1; \ + /* toggle second bit ? */ \ + if((EPTX_DTOG2 & wState)!= 0) \ + _wRegVal ^= EPTX_DTOG2; \ + _SetENDPOINT(bEpNum, (_wRegVal | EP_CTR_RX|EP_CTR_TX)); \ + } /* _SetEPTxStatus */ + +/******************************************************************************* +* Macro Name : SetEPRxStatus +* Description : sets the status for rx transfer (bits STAT_TX[1:0]) +* Input : bEpNum: Endpoint Number. +* wState: new state. +* Output : None. +* Return : None. +*******************************************************************************/ +#define _SetEPRxStatus(bEpNum,wState) {\ + register uint16_t _wRegVal; \ + \ + _wRegVal = _GetENDPOINT(bEpNum) & EPRX_DTOGMASK;\ + /* toggle first bit ? */ \ + if((EPRX_DTOG1 & wState)!= 0) \ + _wRegVal ^= EPRX_DTOG1; \ + /* toggle second bit ? */ \ + if((EPRX_DTOG2 & wState)!= 0) \ + _wRegVal ^= EPRX_DTOG2; \ + _SetENDPOINT(bEpNum, (_wRegVal | EP_CTR_RX|EP_CTR_TX)); \ + } /* _SetEPRxStatus */ + +/******************************************************************************* +* Macro Name : SetEPRxTxStatus +* Description : sets the status for rx & tx (bits STAT_TX[1:0] & STAT_RX[1:0]) +* Input : bEpNum: Endpoint Number. +* wStaterx: new state. +* wStatetx: new state. +* Output : None. +* Return : None. +*******************************************************************************/ +#define _SetEPRxTxStatus(bEpNum,wStaterx,wStatetx) {\ + register uint32_t _wRegVal; \ + \ + _wRegVal = _GetENDPOINT(bEpNum) & (EPRX_DTOGMASK |EPTX_STAT) ;\ + /* toggle first bit ? */ \ + if((EPRX_DTOG1 & wStaterx)!= 0) \ + _wRegVal ^= EPRX_DTOG1; \ + /* toggle second bit ? */ \ + if((EPRX_DTOG2 & wStaterx)!= 0) \ + _wRegVal ^= EPRX_DTOG2; \ + /* toggle first bit ? */ \ + if((EPTX_DTOG1 & wStatetx)!= 0) \ + _wRegVal ^= EPTX_DTOG1; \ + /* toggle second bit ? */ \ + if((EPTX_DTOG2 & wStatetx)!= 0) \ + _wRegVal ^= EPTX_DTOG2; \ + _SetENDPOINT(bEpNum, _wRegVal | EP_CTR_RX|EP_CTR_TX); \ + } /* _SetEPRxTxStatus */ +/******************************************************************************* +* Macro Name : GetEPTxStatus / GetEPRxStatus +* Description : gets the status for tx/rx transfer (bits STAT_TX[1:0] +* /STAT_RX[1:0]) +* Input : bEpNum: Endpoint Number. +* Output : None. +* Return : status . +*******************************************************************************/ +#define _GetEPTxStatus(bEpNum) ((uint16_t)_GetENDPOINT(bEpNum) & EPTX_STAT) + +#define _GetEPRxStatus(bEpNum) ((uint16_t)_GetENDPOINT(bEpNum) & EPRX_STAT) + +/******************************************************************************* +* Macro Name : SetEPTxValid / SetEPRxValid +* Description : sets directly the VALID tx/rx-status into the enpoint register +* Input : bEpNum: Endpoint Number. +* Output : None. +* Return : None. +*******************************************************************************/ +#define _SetEPTxValid(bEpNum) (_SetEPTxStatus(bEpNum, EP_TX_VALID)) + +#define _SetEPRxValid(bEpNum) (_SetEPRxStatus(bEpNum, EP_RX_VALID)) + +/******************************************************************************* +* Macro Name : GetTxStallStatus / GetRxStallStatus. +* Description : checks stall condition in an endpoint. +* Input : bEpNum: Endpoint Number. +* Output : None. +* Return : TRUE = endpoint in stall condition. +*******************************************************************************/ +#define _GetTxStallStatus(bEpNum) (_GetEPTxStatus(bEpNum) \ + == EP_TX_STALL) +#define _GetRxStallStatus(bEpNum) (_GetEPRxStatus(bEpNum) \ + == EP_RX_STALL) + +/******************************************************************************* +* Macro Name : SetEP_KIND / ClearEP_KIND. +* Description : set & clear EP_KIND bit. +* Input : bEpNum: Endpoint Number. +* Output : None. +* Return : None. +*******************************************************************************/ +#define _SetEP_KIND(bEpNum) (_SetENDPOINT(bEpNum, \ + (EP_CTR_RX|EP_CTR_TX|((_GetENDPOINT(bEpNum) | EP_KIND) & EPREG_MASK)))) +#define _ClearEP_KIND(bEpNum) (_SetENDPOINT(bEpNum, \ + (EP_CTR_RX|EP_CTR_TX|(_GetENDPOINT(bEpNum) & EPKIND_MASK)))) + +/******************************************************************************* +* Macro Name : Set_Status_Out / Clear_Status_Out. +* Description : Sets/clears directly STATUS_OUT bit in the endpoint register. +* Input : bEpNum: Endpoint Number. +* Output : None. +* Return : None. +*******************************************************************************/ +#define _Set_Status_Out(bEpNum) _SetEP_KIND(bEpNum) +#define _Clear_Status_Out(bEpNum) _ClearEP_KIND(bEpNum) + +/******************************************************************************* +* Macro Name : SetEPDoubleBuff / ClearEPDoubleBuff. +* Description : Sets/clears directly EP_KIND bit in the endpoint register. +* Input : bEpNum: Endpoint Number. +* Output : None. +* Return : None. +*******************************************************************************/ +#define _SetEPDoubleBuff(bEpNum) _SetEP_KIND(bEpNum) +#define _ClearEPDoubleBuff(bEpNum) _ClearEP_KIND(bEpNum) + +/******************************************************************************* +* Macro Name : ClearEP_CTR_RX / ClearEP_CTR_TX. +* Description : Clears bit CTR_RX / CTR_TX in the endpoint register. +* Input : bEpNum: Endpoint Number. +* Output : None. +* Return : None. +*******************************************************************************/ +#define _ClearEP_CTR_RX(bEpNum) (_SetENDPOINT(bEpNum,\ + _GetENDPOINT(bEpNum) & 0x7FFF & EPREG_MASK)) +#define _ClearEP_CTR_TX(bEpNum) (_SetENDPOINT(bEpNum,\ + _GetENDPOINT(bEpNum) & 0xFF7F & EPREG_MASK)) + +/******************************************************************************* +* Macro Name : ToggleDTOG_RX / ToggleDTOG_TX . +* Description : Toggles DTOG_RX / DTOG_TX bit in the endpoint register. +* Input : bEpNum: Endpoint Number. +* Output : None. +* Return : None. +*******************************************************************************/ +#define _ToggleDTOG_RX(bEpNum) (_SetENDPOINT(bEpNum, \ + EP_CTR_RX|EP_CTR_TX|EP_DTOG_RX | (_GetENDPOINT(bEpNum) & EPREG_MASK))) +#define _ToggleDTOG_TX(bEpNum) (_SetENDPOINT(bEpNum, \ + EP_CTR_RX|EP_CTR_TX|EP_DTOG_TX | (_GetENDPOINT(bEpNum) & EPREG_MASK))) + +/******************************************************************************* +* Macro Name : ClearDTOG_RX / ClearDTOG_TX. +* Description : Clears DTOG_RX / DTOG_TX bit in the endpoint register. +* Input : bEpNum: Endpoint Number. +* Output : None. +* Return : None. +*******************************************************************************/ +#define _ClearDTOG_RX(bEpNum) if((_GetENDPOINT(bEpNum) & EP_DTOG_RX) != 0)\ + _ToggleDTOG_RX(bEpNum) +#define _ClearDTOG_TX(bEpNum) if((_GetENDPOINT(bEpNum) & EP_DTOG_TX) != 0)\ + _ToggleDTOG_TX(bEpNum) +/******************************************************************************* +* Macro Name : SetEPAddress. +* Description : Sets address in an endpoint register. +* Input : bEpNum: Endpoint Number. +* bAddr: Address. +* Output : None. +* Return : None. +*******************************************************************************/ +#define _SetEPAddress(bEpNum,bAddr) _SetENDPOINT(bEpNum,\ + EP_CTR_RX|EP_CTR_TX|(_GetENDPOINT(bEpNum) & EPREG_MASK) | bAddr) + +/******************************************************************************* +* Macro Name : GetEPAddress. +* Description : Gets address in an endpoint register. +* Input : bEpNum: Endpoint Number. +* Output : None. +* Return : None. +*******************************************************************************/ +#define _GetEPAddress(bEpNum) ((uint8_t)(_GetENDPOINT(bEpNum) & EPADDR_FIELD)) + +#define _pEPTxAddr(bEpNum) ((uint32_t *)((_GetBTABLE()+bEpNum*8 )*2 + PMAAddr)) +#define _pEPTxCount(bEpNum) ((uint32_t *)((_GetBTABLE()+bEpNum*8+2)*2 + PMAAddr)) +#define _pEPRxAddr(bEpNum) ((uint32_t *)((_GetBTABLE()+bEpNum*8+4)*2 + PMAAddr)) +#define _pEPRxCount(bEpNum) ((uint32_t *)((_GetBTABLE()+bEpNum*8+6)*2 + PMAAddr)) + +/******************************************************************************* +* Macro Name : SetEPTxAddr / SetEPRxAddr. +* Description : sets address of the tx/rx buffer. +* Input : bEpNum: Endpoint Number. +* wAddr: address to be set (must be word aligned). +* Output : None. +* Return : None. +*******************************************************************************/ +#define _SetEPTxAddr(bEpNum,wAddr) (*_pEPTxAddr(bEpNum) = ((wAddr >> 1) << 1)) +#define _SetEPRxAddr(bEpNum,wAddr) (*_pEPRxAddr(bEpNum) = ((wAddr >> 1) << 1)) + +/******************************************************************************* +* Macro Name : GetEPTxAddr / GetEPRxAddr. +* Description : Gets address of the tx/rx buffer. +* Input : bEpNum: Endpoint Number. +* Output : None. +* Return : address of the buffer. +*******************************************************************************/ +#define _GetEPTxAddr(bEpNum) ((uint16_t)*_pEPTxAddr(bEpNum)) +#define _GetEPRxAddr(bEpNum) ((uint16_t)*_pEPRxAddr(bEpNum)) + +/******************************************************************************* +* Macro Name : SetEPCountRxReg. +* Description : Sets counter of rx buffer with no. of blocks. +* Input : pdwReg: pointer to counter. +* wCount: Counter. +* Output : None. +* Return : None. +*******************************************************************************/ +#define _BlocksOf32(dwReg,wCount,wNBlocks) {\ + wNBlocks = wCount >> 5;\ + if((wCount & 0x1f) == 0)\ + wNBlocks--;\ + *pdwReg = (uint32_t)((wNBlocks << 10) | 0x8000);\ + }/* _BlocksOf32 */ + +#define _BlocksOf2(dwReg,wCount,wNBlocks) {\ + wNBlocks = wCount >> 1;\ + if((wCount & 0x1) != 0)\ + wNBlocks++;\ + *pdwReg = (uint32_t)(wNBlocks << 10);\ + }/* _BlocksOf2 */ + +#define _SetEPCountRxReg(dwReg,wCount) {\ + uint16_t wNBlocks;\ + if(wCount > 62){_BlocksOf32(dwReg,wCount,wNBlocks);}\ + else {_BlocksOf2(dwReg,wCount,wNBlocks);}\ + }/* _SetEPCountRxReg */ + + + +#define _SetEPRxDblBuf0Count(bEpNum,wCount) {\ + uint32_t *pdwReg = _pEPTxCount(bEpNum); \ + _SetEPCountRxReg(pdwReg, wCount);\ + } +/******************************************************************************* +* Macro Name : SetEPTxCount / SetEPRxCount. +* Description : sets counter for the tx/rx buffer. +* Input : bEpNum: endpoint number. +* wCount: Counter value. +* Output : None. +* Return : None. +*******************************************************************************/ +#define _SetEPTxCount(bEpNum,wCount) (*_pEPTxCount(bEpNum) = wCount) +#define _SetEPRxCount(bEpNum,wCount) {\ + uint32_t *pdwReg = _pEPRxCount(bEpNum); \ + _SetEPCountRxReg(pdwReg, wCount);\ + } +/******************************************************************************* +* Macro Name : GetEPTxCount / GetEPRxCount. +* Description : gets counter of the tx buffer. +* Input : bEpNum: endpoint number. +* Output : None. +* Return : Counter value. +*******************************************************************************/ +#define _GetEPTxCount(bEpNum)((uint16_t)(*_pEPTxCount(bEpNum)) & 0x3ff) +#define _GetEPRxCount(bEpNum)((uint16_t)(*_pEPRxCount(bEpNum)) & 0x3ff) + +/******************************************************************************* +* Macro Name : SetEPDblBuf0Addr / SetEPDblBuf1Addr. +* Description : Sets buffer 0/1 address in a double buffer endpoint. +* Input : bEpNum: endpoint number. +* : wBuf0Addr: buffer 0 address. +* Output : None. +* Return : None. +*******************************************************************************/ +#define _SetEPDblBuf0Addr(bEpNum,wBuf0Addr) {_SetEPTxAddr(bEpNum, wBuf0Addr);} +#define _SetEPDblBuf1Addr(bEpNum,wBuf1Addr) {_SetEPRxAddr(bEpNum, wBuf1Addr);} + +/******************************************************************************* +* Macro Name : SetEPDblBuffAddr. +* Description : Sets addresses in a double buffer endpoint. +* Input : bEpNum: endpoint number. +* : wBuf0Addr: buffer 0 address. +* : wBuf1Addr = buffer 1 address. +* Output : None. +* Return : None. +*******************************************************************************/ +#define _SetEPDblBuffAddr(bEpNum,wBuf0Addr,wBuf1Addr) { \ + _SetEPDblBuf0Addr(bEpNum, wBuf0Addr);\ + _SetEPDblBuf1Addr(bEpNum, wBuf1Addr);\ + } /* _SetEPDblBuffAddr */ + +/******************************************************************************* +* Macro Name : GetEPDblBuf0Addr / GetEPDblBuf1Addr. +* Description : Gets buffer 0/1 address of a double buffer endpoint. +* Input : bEpNum: endpoint number. +* Output : None. +* Return : None. +*******************************************************************************/ +#define _GetEPDblBuf0Addr(bEpNum) (_GetEPTxAddr(bEpNum)) +#define _GetEPDblBuf1Addr(bEpNum) (_GetEPRxAddr(bEpNum)) + +/******************************************************************************* +* Macro Name : SetEPDblBuffCount / SetEPDblBuf0Count / SetEPDblBuf1Count. +* Description : Gets buffer 0/1 address of a double buffer endpoint. +* Input : bEpNum: endpoint number. +* : bDir: endpoint dir EP_DBUF_OUT = OUT +* EP_DBUF_IN = IN +* : wCount: Counter value +* Output : None. +* Return : None. +*******************************************************************************/ +#define _SetEPDblBuf0Count(bEpNum, bDir, wCount) { \ + if(bDir == EP_DBUF_OUT)\ + /* OUT endpoint */ \ + {_SetEPRxDblBuf0Count(bEpNum,wCount);} \ + else if(bDir == EP_DBUF_IN)\ + /* IN endpoint */ \ + *_pEPTxCount(bEpNum) = (uint32_t)wCount; \ + } /* SetEPDblBuf0Count*/ + +#define _SetEPDblBuf1Count(bEpNum, bDir, wCount) { \ + if(bDir == EP_DBUF_OUT)\ + /* OUT endpoint */ \ + {_SetEPRxCount(bEpNum,wCount);}\ + else if(bDir == EP_DBUF_IN)\ + /* IN endpoint */\ + *_pEPRxCount(bEpNum) = (uint32_t)wCount; \ + } /* SetEPDblBuf1Count */ + +#define _SetEPDblBuffCount(bEpNum, bDir, wCount) {\ + _SetEPDblBuf0Count(bEpNum, bDir, wCount); \ + _SetEPDblBuf1Count(bEpNum, bDir, wCount); \ + } /* _SetEPDblBuffCount */ + +/******************************************************************************* +* Macro Name : GetEPDblBuf0Count / GetEPDblBuf1Count. +* Description : Gets buffer 0/1 rx/tx counter for double buffering. +* Input : bEpNum: endpoint number. +* Output : None. +* Return : None. +*******************************************************************************/ +#define _GetEPDblBuf0Count(bEpNum) (_GetEPTxCount(bEpNum)) +#define _GetEPDblBuf1Count(bEpNum) (_GetEPRxCount(bEpNum)) + + +/* External variables --------------------------------------------------------*/ +extern __IO uint16_t wIstr; /* ISTR register last read value */ + +/* Exported functions ------------------------------------------------------- */ +void SetCNTR(uint16_t /*wRegValue*/); +void SetISTR(uint16_t /*wRegValue*/); +void SetDADDR(uint16_t /*wRegValue*/); +void SetBTABLE(uint16_t /*wRegValue*/); +void SetBTABLE(uint16_t /*wRegValue*/); +uint16_t GetCNTR(void); +uint16_t GetISTR(void); +uint16_t GetFNR(void); +uint16_t GetDADDR(void); +uint16_t GetBTABLE(void); +void SetENDPOINT(uint8_t /*bEpNum*/, uint16_t /*wRegValue*/); +uint16_t GetENDPOINT(uint8_t /*bEpNum*/); +void SetEPType(uint8_t /*bEpNum*/, uint16_t /*wType*/); +uint16_t GetEPType(uint8_t /*bEpNum*/); +void SetEPTxStatus(uint8_t /*bEpNum*/, uint16_t /*wState*/); +void SetEPRxStatus(uint8_t /*bEpNum*/, uint16_t /*wState*/); +void SetDouBleBuffEPStall(uint8_t /*bEpNum*/, uint8_t bDir); +uint16_t GetEPTxStatus(uint8_t /*bEpNum*/); +uint16_t GetEPRxStatus(uint8_t /*bEpNum*/); +void SetEPTxValid(uint8_t /*bEpNum*/); +void SetEPRxValid(uint8_t /*bEpNum*/); +uint16_t GetTxStallStatus(uint8_t /*bEpNum*/); +uint16_t GetRxStallStatus(uint8_t /*bEpNum*/); +void SetEP_KIND(uint8_t /*bEpNum*/); +void ClearEP_KIND(uint8_t /*bEpNum*/); +void Set_Status_Out(uint8_t /*bEpNum*/); +void Clear_Status_Out(uint8_t /*bEpNum*/); +void SetEPDoubleBuff(uint8_t /*bEpNum*/); +void ClearEPDoubleBuff(uint8_t /*bEpNum*/); +void ClearEP_CTR_RX(uint8_t /*bEpNum*/); +void ClearEP_CTR_TX(uint8_t /*bEpNum*/); +void ToggleDTOG_RX(uint8_t /*bEpNum*/); +void ToggleDTOG_TX(uint8_t /*bEpNum*/); +void ClearDTOG_RX(uint8_t /*bEpNum*/); +void ClearDTOG_TX(uint8_t /*bEpNum*/); +void SetEPAddress(uint8_t /*bEpNum*/, uint8_t /*bAddr*/); +uint8_t GetEPAddress(uint8_t /*bEpNum*/); +void SetEPTxAddr(uint8_t /*bEpNum*/, uint16_t /*wAddr*/); +void SetEPRxAddr(uint8_t /*bEpNum*/, uint16_t /*wAddr*/); +uint16_t GetEPTxAddr(uint8_t /*bEpNum*/); +uint16_t GetEPRxAddr(uint8_t /*bEpNum*/); +void SetEPCountRxReg(uint32_t * /*pdwReg*/, uint16_t /*wCount*/); +void SetEPTxCount(uint8_t /*bEpNum*/, uint16_t /*wCount*/); +void SetEPRxCount(uint8_t /*bEpNum*/, uint16_t /*wCount*/); +uint16_t GetEPTxCount(uint8_t /*bEpNum*/); +uint16_t GetEPRxCount(uint8_t /*bEpNum*/); +void SetEPDblBuf0Addr(uint8_t /*bEpNum*/, uint16_t /*wBuf0Addr*/); +void SetEPDblBuf1Addr(uint8_t /*bEpNum*/, uint16_t /*wBuf1Addr*/); +void SetEPDblBuffAddr(uint8_t /*bEpNum*/, uint16_t /*wBuf0Addr*/, uint16_t /*wBuf1Addr*/); +uint16_t GetEPDblBuf0Addr(uint8_t /*bEpNum*/); +uint16_t GetEPDblBuf1Addr(uint8_t /*bEpNum*/); +void SetEPDblBuffCount(uint8_t /*bEpNum*/, uint8_t /*bDir*/, uint16_t /*wCount*/); +void SetEPDblBuf0Count(uint8_t /*bEpNum*/, uint8_t /*bDir*/, uint16_t /*wCount*/); +void SetEPDblBuf1Count(uint8_t /*bEpNum*/, uint8_t /*bDir*/, uint16_t /*wCount*/); +uint16_t GetEPDblBuf0Count(uint8_t /*bEpNum*/); +uint16_t GetEPDblBuf1Count(uint8_t /*bEpNum*/); +EP_DBUF_DIR GetEPDblBufDir(uint8_t /*bEpNum*/); +void FreeUserBuffer(uint8_t bEpNum/*bEpNum*/, uint8_t bDir); +uint16_t ToWord(uint8_t, uint8_t); +uint16_t ByteSwap(uint16_t); + +#endif /* __USB_REGS_H */ + +/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ diff --git a/Libraries/STM32_USB-FS-Device_Driver/inc/usb_sil.h b/Libraries/STM32_USB-FS-Device_Driver/inc/usb_sil.h new file mode 100644 index 0000000..5548175 --- /dev/null +++ b/Libraries/STM32_USB-FS-Device_Driver/inc/usb_sil.h @@ -0,0 +1,47 @@ +/** + ****************************************************************************** + * @file usb_sil.h + * @author MCD Application Team + * @version V4.0.0 + * @date 28-August-2012 + * @brief Simplified Interface Layer function prototypes. + ****************************************************************************** + * @attention + * + *

    © COPYRIGHT 2012 STMicroelectronics

    + * + * Licensed under MCD-ST Liberty SW License Agreement V2, (the "License"); + * You may not use this file except in compliance with the License. + * You may obtain a copy of the License at: + * + * http://www.st.com/software_license_agreement_liberty_v2 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, + * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + * + ****************************************************************************** + */ + + +/* Define to prevent recursive inclusion -------------------------------------*/ +#ifndef __USB_SIL_H +#define __USB_SIL_H + +/* Includes ------------------------------------------------------------------*/ +/* Exported types ------------------------------------------------------------*/ +/* Exported constants --------------------------------------------------------*/ +/* Exported macro ------------------------------------------------------------*/ +/* Exported functions ------------------------------------------------------- */ + +uint32_t USB_SIL_Init(void); +uint32_t USB_SIL_Write(uint8_t bEpAddr, uint8_t* pBufferPointer, uint32_t wBufferSize); +uint32_t USB_SIL_Read(uint8_t bEpAddr, uint8_t* pBufferPointer); + +/* External variables --------------------------------------------------------*/ + +#endif /* __USB_SIL_H */ + +/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ diff --git a/Libraries/STM32_USB-FS-Device_Driver/inc/usb_type.h b/Libraries/STM32_USB-FS-Device_Driver/inc/usb_type.h new file mode 100644 index 0000000..21e1670 --- /dev/null +++ b/Libraries/STM32_USB-FS-Device_Driver/inc/usb_type.h @@ -0,0 +1,54 @@ +/** + ****************************************************************************** + * @file usb_type.h + * @author MCD Application Team + * @version V4.0.0 + * @date 28-August-2012 + * @brief Type definitions used by the USB Library + ****************************************************************************** + * @attention + * + *

    © COPYRIGHT 2012 STMicroelectronics

    + * + * Licensed under MCD-ST Liberty SW License Agreement V2, (the "License"); + * You may not use this file except in compliance with the License. + * You may obtain a copy of the License at: + * + * http://www.st.com/software_license_agreement_liberty_v2 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, + * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + * + ****************************************************************************** + */ + + +/* Define to prevent recursive inclusion -------------------------------------*/ +#ifndef __USB_TYPE_H +#define __USB_TYPE_H + +/* Includes ------------------------------------------------------------------*/ +#include "usb_conf.h" + +/* Exported types ------------------------------------------------------------*/ +/* Exported constants --------------------------------------------------------*/ +#ifndef NULL +#define NULL ((void *)0) +#endif + +typedef enum +{ + FALSE = 0, TRUE = !FALSE +} +bool; + +/* Exported macro ------------------------------------------------------------*/ +/* Exported functions ------------------------------------------------------- */ +/* External variables --------------------------------------------------------*/ + +#endif /* __USB_TYPE_H */ + +/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ diff --git a/Libraries/STM32_USB-FS-Device_Driver/src/usb_core.c b/Libraries/STM32_USB-FS-Device_Driver/src/usb_core.c new file mode 100644 index 0000000..3231a96 --- /dev/null +++ b/Libraries/STM32_USB-FS-Device_Driver/src/usb_core.c @@ -0,0 +1,1033 @@ +/** + ****************************************************************************** + * @file usb_core.c + * @author MCD Application Team + * @version V4.0.0 + * @date 28-August-2012 + * @brief Standard protocol processing (USB v2.0) + ****************************************************************************** + * @attention + * + *

    © COPYRIGHT 2012 STMicroelectronics

    + * + * Licensed under MCD-ST Liberty SW License Agreement V2, (the "License"); + * You may not use this file except in compliance with the License. + * You may obtain a copy of the License at: + * + * http://www.st.com/software_license_agreement_liberty_v2 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, + * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + * + ****************************************************************************** + */ + + +/* Includes ------------------------------------------------------------------*/ +#include "usb_lib.h" +/* Private typedef -----------------------------------------------------------*/ +/* Private define ------------------------------------------------------------*/ +#define ValBit(VAR,Place) (VAR & (1 << Place)) +#define SetBit(VAR,Place) (VAR |= (1 << Place)) +#define ClrBit(VAR,Place) (VAR &= ((1 << Place) ^ 255)) +#define Send0LengthData() { _SetEPTxCount(ENDP0, 0); \ + vSetEPTxStatus(EP_TX_VALID); \ + } + +#define vSetEPRxStatus(st) (SaveRState = st) +#define vSetEPTxStatus(st) (SaveTState = st) + +#define USB_StatusIn() Send0LengthData() +#define USB_StatusOut() vSetEPRxStatus(EP_RX_VALID) + +#define StatusInfo0 StatusInfo.bw.bb1 /* Reverse bb0 & bb1 */ +#define StatusInfo1 StatusInfo.bw.bb0 + +/* Private macro -------------------------------------------------------------*/ +/* Private variables ---------------------------------------------------------*/ +uint16_t_uint8_t StatusInfo; + +bool Data_Mul_MaxPacketSize = FALSE; +/* Private function prototypes -----------------------------------------------*/ +static void DataStageOut(void); +static void DataStageIn(void); +static void NoData_Setup0(void); +static void Data_Setup0(void); +/* Private functions ---------------------------------------------------------*/ + +/******************************************************************************* +* Function Name : Standard_GetConfiguration. +* Description : Return the current configuration variable address. +* Input : Length - How many bytes are needed. +* Output : None. +* Return : Return 1 , if the request is invalid when "Length" is 0. +* Return "Buffer" if the "Length" is not 0. +*******************************************************************************/ +uint8_t *Standard_GetConfiguration(uint16_t Length) +{ + if (Length == 0) + { + pInformation->Ctrl_Info.Usb_wLength = + sizeof(pInformation->Current_Configuration); + return 0; + } + pUser_Standard_Requests->User_GetConfiguration(); + return (uint8_t *)&pInformation->Current_Configuration; +} + +/******************************************************************************* +* Function Name : Standard_SetConfiguration. +* Description : This routine is called to set the configuration value +* Then each class should configure device itself. +* Input : None. +* Output : None. +* Return : Return USB_SUCCESS, if the request is performed. +* Return USB_UNSUPPORT, if the request is invalid. +*******************************************************************************/ +RESULT Standard_SetConfiguration(void) +{ + + if ((pInformation->USBwValue0 <= + Device_Table.Total_Configuration) && (pInformation->USBwValue1 == 0) + && (pInformation->USBwIndex == 0)) /*call Back usb spec 2.0*/ + { + pInformation->Current_Configuration = pInformation->USBwValue0; + pUser_Standard_Requests->User_SetConfiguration(); + return USB_SUCCESS; + } + else + { + return USB_UNSUPPORT; + } +} + +/******************************************************************************* +* Function Name : Standard_GetInterface. +* Description : Return the Alternate Setting of the current interface. +* Input : Length - How many bytes are needed. +* Output : None. +* Return : Return 0, if the request is invalid when "Length" is 0. +* Return "Buffer" if the "Length" is not 0. +*******************************************************************************/ +uint8_t *Standard_GetInterface(uint16_t Length) +{ + if (Length == 0) + { + pInformation->Ctrl_Info.Usb_wLength = + sizeof(pInformation->Current_AlternateSetting); + return 0; + } + pUser_Standard_Requests->User_GetInterface(); + return (uint8_t *)&pInformation->Current_AlternateSetting; +} + +/******************************************************************************* +* Function Name : Standard_SetInterface. +* Description : This routine is called to set the interface. +* Then each class should configure the interface them self. +* Input : None. +* Output : None. +* Return : - Return USB_SUCCESS, if the request is performed. +* - Return USB_UNSUPPORT, if the request is invalid. +*******************************************************************************/ +RESULT Standard_SetInterface(void) +{ + RESULT Re; + /*Test if the specified Interface and Alternate Setting are supported by + the application Firmware*/ + Re = (*pProperty->Class_Get_Interface_Setting)(pInformation->USBwIndex0, pInformation->USBwValue0); + + if (pInformation->Current_Configuration != 0) + { + if ((Re != USB_SUCCESS) || (pInformation->USBwIndex1 != 0) + || (pInformation->USBwValue1 != 0)) + { + return USB_UNSUPPORT; + } + else if (Re == USB_SUCCESS) + { + pUser_Standard_Requests->User_SetInterface(); + pInformation->Current_Interface = pInformation->USBwIndex0; + pInformation->Current_AlternateSetting = pInformation->USBwValue0; + return USB_SUCCESS; + } + + } + + return USB_UNSUPPORT; +} + +/******************************************************************************* +* Function Name : Standard_GetStatus. +* Description : Copy the device request data to "StatusInfo buffer". +* Input : - Length - How many bytes are needed. +* Output : None. +* Return : Return 0, if the request is at end of data block, +* or is invalid when "Length" is 0. +*******************************************************************************/ +uint8_t *Standard_GetStatus(uint16_t Length) +{ + if (Length == 0) + { + pInformation->Ctrl_Info.Usb_wLength = 2; + return 0; + } + + /* Reset Status Information */ + StatusInfo.w = 0; + + if (Type_Recipient == (STANDARD_REQUEST | DEVICE_RECIPIENT)) + { + /*Get Device Status */ + uint8_t Feature = pInformation->Current_Feature; + + /* Remote Wakeup enabled */ + if (ValBit(Feature, 5)) + { + SetBit(StatusInfo0, 1); + } + else + { + ClrBit(StatusInfo0, 1); + } + + /* Bus-powered */ + if (ValBit(Feature, 6)) + { + SetBit(StatusInfo0, 0); + } + else /* Self-powered */ + { + ClrBit(StatusInfo0, 0); + } + } + /*Interface Status*/ + else if (Type_Recipient == (STANDARD_REQUEST | INTERFACE_RECIPIENT)) + { + return (uint8_t *)&StatusInfo; + } + /*Get EndPoint Status*/ + else if (Type_Recipient == (STANDARD_REQUEST | ENDPOINT_RECIPIENT)) + { + uint8_t Related_Endpoint; + uint8_t wIndex0 = pInformation->USBwIndex0; + + Related_Endpoint = (wIndex0 & 0x0f); + if (ValBit(wIndex0, 7)) + { + /* IN endpoint */ + if (_GetTxStallStatus(Related_Endpoint)) + { + SetBit(StatusInfo0, 0); /* IN Endpoint stalled */ + } + } + else + { + /* OUT endpoint */ + if (_GetRxStallStatus(Related_Endpoint)) + { + SetBit(StatusInfo0, 0); /* OUT Endpoint stalled */ + } + } + + } + else + { + return NULL; + } + pUser_Standard_Requests->User_GetStatus(); + return (uint8_t *)&StatusInfo; +} + +/******************************************************************************* +* Function Name : Standard_ClearFeature. +* Description : Clear or disable a specific feature. +* Input : None. +* Output : None. +* Return : - Return USB_SUCCESS, if the request is performed. +* - Return USB_UNSUPPORT, if the request is invalid. +*******************************************************************************/ +RESULT Standard_ClearFeature(void) +{ + uint32_t Type_Rec = Type_Recipient; + uint32_t Status; + + + if (Type_Rec == (STANDARD_REQUEST | DEVICE_RECIPIENT)) + {/*Device Clear Feature*/ + ClrBit(pInformation->Current_Feature, 5); + return USB_SUCCESS; + } + else if (Type_Rec == (STANDARD_REQUEST | ENDPOINT_RECIPIENT)) + {/*EndPoint Clear Feature*/ + DEVICE* pDev; + uint32_t Related_Endpoint; + uint32_t wIndex0; + uint32_t rEP; + + if ((pInformation->USBwValue != ENDPOINT_STALL) + || (pInformation->USBwIndex1 != 0)) + { + return USB_UNSUPPORT; + } + + pDev = &Device_Table; + wIndex0 = pInformation->USBwIndex0; + rEP = wIndex0 & ~0x80; + Related_Endpoint = ENDP0 + rEP; + + if (ValBit(pInformation->USBwIndex0, 7)) + { + /*Get Status of endpoint & stall the request if the related_ENdpoint + is Disabled*/ + Status = _GetEPTxStatus(Related_Endpoint); + } + else + { + Status = _GetEPRxStatus(Related_Endpoint); + } + + if ((rEP >= pDev->Total_Endpoint) || (Status == 0) + || (pInformation->Current_Configuration == 0)) + { + return USB_UNSUPPORT; + } + + + if (wIndex0 & 0x80) + { + /* IN endpoint */ + if (_GetTxStallStatus(Related_Endpoint )) + { + ClearDTOG_TX(Related_Endpoint); + SetEPTxStatus(Related_Endpoint, EP_TX_VALID); + } + } + else + { + /* OUT endpoint */ + if (_GetRxStallStatus(Related_Endpoint)) + { + if (Related_Endpoint == ENDP0) + { + /* After clear the STALL, enable the default endpoint receiver */ + SetEPRxCount(Related_Endpoint, Device_Property.MaxPacketSize); + _SetEPRxStatus(Related_Endpoint, EP_RX_VALID); + } + else + { + ClearDTOG_RX(Related_Endpoint); + _SetEPRxStatus(Related_Endpoint, EP_RX_VALID); + } + } + } + pUser_Standard_Requests->User_ClearFeature(); + return USB_SUCCESS; + } + + return USB_UNSUPPORT; +} + +/******************************************************************************* +* Function Name : Standard_SetEndPointFeature +* Description : Set or enable a specific feature of EndPoint +* Input : None. +* Output : None. +* Return : - Return USB_SUCCESS, if the request is performed. +* - Return USB_UNSUPPORT, if the request is invalid. +*******************************************************************************/ +RESULT Standard_SetEndPointFeature(void) +{ + uint32_t wIndex0; + uint32_t Related_Endpoint; + uint32_t rEP; + uint32_t Status; + + wIndex0 = pInformation->USBwIndex0; + rEP = wIndex0 & ~0x80; + Related_Endpoint = ENDP0 + rEP; + + if (ValBit(pInformation->USBwIndex0, 7)) + { + /* get Status of endpoint & stall the request if the related_ENdpoint + is Disabled*/ + Status = _GetEPTxStatus(Related_Endpoint); + } + else + { + Status = _GetEPRxStatus(Related_Endpoint); + } + + if (Related_Endpoint >= Device_Table.Total_Endpoint + || pInformation->USBwValue != 0 || Status == 0 + || pInformation->Current_Configuration == 0) + { + return USB_UNSUPPORT; + } + else + { + if (wIndex0 & 0x80) + { + /* IN endpoint */ + _SetEPTxStatus(Related_Endpoint, EP_TX_STALL); + } + + else + { + /* OUT endpoint */ + _SetEPRxStatus(Related_Endpoint, EP_RX_STALL); + } + } + pUser_Standard_Requests->User_SetEndPointFeature(); + return USB_SUCCESS; +} + +/******************************************************************************* +* Function Name : Standard_SetDeviceFeature. +* Description : Set or enable a specific feature of Device. +* Input : None. +* Output : None. +* Return : - Return USB_SUCCESS, if the request is performed. +* - Return USB_UNSUPPORT, if the request is invalid. +*******************************************************************************/ +RESULT Standard_SetDeviceFeature(void) +{ + SetBit(pInformation->Current_Feature, 5); + pUser_Standard_Requests->User_SetDeviceFeature(); + return USB_SUCCESS; +} + +/******************************************************************************* +* Function Name : Standard_GetDescriptorData. +* Description : Standard_GetDescriptorData is used for descriptors transfer. +* : This routine is used for the descriptors resident in Flash +* or RAM +* pDesc can be in either Flash or RAM +* The purpose of this routine is to have a versatile way to +* response descriptors request. It allows user to generate +* certain descriptors with software or read descriptors from +* external storage part by part. +* Input : - Length - Length of the data in this transfer. +* - pDesc - A pointer points to descriptor struct. +* The structure gives the initial address of the descriptor and +* its original size. +* Output : None. +* Return : Address of a part of the descriptor pointed by the Usb_ +* wOffset The buffer pointed by this address contains at least +* Length bytes. +*******************************************************************************/ +uint8_t *Standard_GetDescriptorData(uint16_t Length, ONE_DESCRIPTOR *pDesc) +{ + uint32_t wOffset; + + wOffset = pInformation->Ctrl_Info.Usb_wOffset; + if (Length == 0) + { + pInformation->Ctrl_Info.Usb_wLength = pDesc->Descriptor_Size - wOffset; + return 0; + } + + return pDesc->Descriptor + wOffset; +} + +/******************************************************************************* +* Function Name : DataStageOut. +* Description : Data stage of a Control Write Transfer. +* Input : None. +* Output : None. +* Return : None. +*******************************************************************************/ +void DataStageOut(void) +{ + ENDPOINT_INFO *pEPinfo = &pInformation->Ctrl_Info; + uint32_t save_rLength; + + save_rLength = pEPinfo->Usb_rLength; + + if (pEPinfo->CopyData && save_rLength) + { + uint8_t *Buffer; + uint32_t Length; + + Length = pEPinfo->PacketSize; + if (Length > save_rLength) + { + Length = save_rLength; + } + + Buffer = (*pEPinfo->CopyData)(Length); + pEPinfo->Usb_rLength -= Length; + pEPinfo->Usb_rOffset += Length; + PMAToUserBufferCopy(Buffer, GetEPRxAddr(ENDP0), Length); + + } + + if (pEPinfo->Usb_rLength != 0) + { + vSetEPRxStatus(EP_RX_VALID);/* re-enable for next data reception */ + SetEPTxCount(ENDP0, 0); + vSetEPTxStatus(EP_TX_VALID);/* Expect the host to abort the data OUT stage */ + } + /* Set the next State*/ + if (pEPinfo->Usb_rLength >= pEPinfo->PacketSize) + { + pInformation->ControlState = OUT_DATA; + } + else + { + if (pEPinfo->Usb_rLength > 0) + { + pInformation->ControlState = LAST_OUT_DATA; + } + else if (pEPinfo->Usb_rLength == 0) + { + pInformation->ControlState = WAIT_STATUS_IN; + USB_StatusIn(); + } + } +} + +/******************************************************************************* +* Function Name : DataStageIn. +* Description : Data stage of a Control Read Transfer. +* Input : None. +* Output : None. +* Return : None. +*******************************************************************************/ +void DataStageIn(void) +{ + ENDPOINT_INFO *pEPinfo = &pInformation->Ctrl_Info; + uint32_t save_wLength = pEPinfo->Usb_wLength; + uint32_t ControlState = pInformation->ControlState; + + uint8_t *DataBuffer; + uint32_t Length; + + if ((save_wLength == 0) && (ControlState == LAST_IN_DATA)) + { + if(Data_Mul_MaxPacketSize == TRUE) + { + /* No more data to send and empty packet */ + Send0LengthData(); + ControlState = LAST_IN_DATA; + Data_Mul_MaxPacketSize = FALSE; + } + else + { + /* No more data to send so STALL the TX Status*/ + ControlState = WAIT_STATUS_OUT; + vSetEPTxStatus(EP_TX_STALL); + + } + + goto Expect_Status_Out; + } + + Length = pEPinfo->PacketSize; + ControlState = (save_wLength <= Length) ? LAST_IN_DATA : IN_DATA; + + if (Length > save_wLength) + { + Length = save_wLength; + } + + DataBuffer = (*pEPinfo->CopyData)(Length); + + UserToPMABufferCopy(DataBuffer, GetEPTxAddr(ENDP0), Length); + + SetEPTxCount(ENDP0, Length); + + pEPinfo->Usb_wLength -= Length; + pEPinfo->Usb_wOffset += Length; + vSetEPTxStatus(EP_TX_VALID); + + USB_StatusOut();/* Expect the host to abort the data IN stage */ + +Expect_Status_Out: + pInformation->ControlState = ControlState; +} + +/******************************************************************************* +* Function Name : NoData_Setup0. +* Description : Proceed the processing of setup request without data stage. +* Input : None. +* Output : None. +* Return : None. +*******************************************************************************/ +void NoData_Setup0(void) +{ + RESULT Result = USB_UNSUPPORT; + uint32_t RequestNo = pInformation->USBbRequest; + uint32_t ControlState; + + if (Type_Recipient == (STANDARD_REQUEST | DEVICE_RECIPIENT)) + { + /* Device Request*/ + /* SET_CONFIGURATION*/ + if (RequestNo == SET_CONFIGURATION) + { + Result = Standard_SetConfiguration(); + } + + /*SET ADDRESS*/ + else if (RequestNo == SET_ADDRESS) + { + if ((pInformation->USBwValue0 > 127) || (pInformation->USBwValue1 != 0) + || (pInformation->USBwIndex != 0) + || (pInformation->Current_Configuration != 0)) + /* Device Address should be 127 or less*/ + { + ControlState = STALLED; + goto exit_NoData_Setup0; + } + else + { + Result = USB_SUCCESS; + } + } + /*SET FEATURE for Device*/ + else if (RequestNo == SET_FEATURE) + { + if ((pInformation->USBwValue0 == DEVICE_REMOTE_WAKEUP) \ + && (pInformation->USBwIndex == 0)) + { + Result = Standard_SetDeviceFeature(); + } + else + { + Result = USB_UNSUPPORT; + } + } + /*Clear FEATURE for Device */ + else if (RequestNo == CLEAR_FEATURE) + { + if (pInformation->USBwValue0 == DEVICE_REMOTE_WAKEUP + && pInformation->USBwIndex == 0 + && ValBit(pInformation->Current_Feature, 5)) + { + Result = Standard_ClearFeature(); + } + else + { + Result = USB_UNSUPPORT; + } + } + + } + + /* Interface Request*/ + else if (Type_Recipient == (STANDARD_REQUEST | INTERFACE_RECIPIENT)) + { + /*SET INTERFACE*/ + if (RequestNo == SET_INTERFACE) + { + Result = Standard_SetInterface(); + } + } + + /* EndPoint Request*/ + else if (Type_Recipient == (STANDARD_REQUEST | ENDPOINT_RECIPIENT)) + { + /*CLEAR FEATURE for EndPoint*/ + if (RequestNo == CLEAR_FEATURE) + { + Result = Standard_ClearFeature(); + } + /* SET FEATURE for EndPoint*/ + else if (RequestNo == SET_FEATURE) + { + Result = Standard_SetEndPointFeature(); + } + } + else + { + Result = USB_UNSUPPORT; + } + + + if (Result != USB_SUCCESS) + { + Result = (*pProperty->Class_NoData_Setup)(RequestNo); + if (Result == USB_NOT_READY) + { + ControlState = PAUSE; + goto exit_NoData_Setup0; + } + } + + if (Result != USB_SUCCESS) + { + ControlState = STALLED; + goto exit_NoData_Setup0; + } + + ControlState = WAIT_STATUS_IN;/* After no data stage SETUP */ + + USB_StatusIn(); + +exit_NoData_Setup0: + pInformation->ControlState = ControlState; + return; +} + +/******************************************************************************* +* Function Name : Data_Setup0. +* Description : Proceed the processing of setup request with data stage. +* Input : None. +* Output : None. +* Return : None. +*******************************************************************************/ +void Data_Setup0(void) +{ + uint8_t *(*CopyRoutine)(uint16_t); + RESULT Result; + uint32_t Request_No = pInformation->USBbRequest; + + uint32_t Related_Endpoint, Reserved; + uint32_t wOffset, Status; + + + + CopyRoutine = NULL; + wOffset = 0; + + /*GET DESCRIPTOR*/ + if (Request_No == GET_DESCRIPTOR) + { + if (Type_Recipient == (STANDARD_REQUEST | DEVICE_RECIPIENT)) + { + uint8_t wValue1 = pInformation->USBwValue1; + if (wValue1 == DEVICE_DESCRIPTOR) + { + CopyRoutine = pProperty->GetDeviceDescriptor; + } + else if (wValue1 == CONFIG_DESCRIPTOR) + { + CopyRoutine = pProperty->GetConfigDescriptor; + } + else if (wValue1 == STRING_DESCRIPTOR) + { + CopyRoutine = pProperty->GetStringDescriptor; + } /* End of GET_DESCRIPTOR */ + } + } + + /*GET STATUS*/ + else if ((Request_No == GET_STATUS) && (pInformation->USBwValue == 0) + && (pInformation->USBwLength == 0x0002) + && (pInformation->USBwIndex1 == 0)) + { + /* GET STATUS for Device*/ + if ((Type_Recipient == (STANDARD_REQUEST | DEVICE_RECIPIENT)) + && (pInformation->USBwIndex == 0)) + { + CopyRoutine = Standard_GetStatus; + } + + /* GET STATUS for Interface*/ + else if (Type_Recipient == (STANDARD_REQUEST | INTERFACE_RECIPIENT)) + { + if (((*pProperty->Class_Get_Interface_Setting)(pInformation->USBwIndex0, 0) == USB_SUCCESS) + && (pInformation->Current_Configuration != 0)) + { + CopyRoutine = Standard_GetStatus; + } + } + + /* GET STATUS for EndPoint*/ + else if (Type_Recipient == (STANDARD_REQUEST | ENDPOINT_RECIPIENT)) + { + Related_Endpoint = (pInformation->USBwIndex0 & 0x0f); + Reserved = pInformation->USBwIndex0 & 0x70; + + if (ValBit(pInformation->USBwIndex0, 7)) + { + /*Get Status of endpoint & stall the request if the related_ENdpoint + is Disabled*/ + Status = _GetEPTxStatus(Related_Endpoint); + } + else + { + Status = _GetEPRxStatus(Related_Endpoint); + } + + if ((Related_Endpoint < Device_Table.Total_Endpoint) && (Reserved == 0) + && (Status != 0)) + { + CopyRoutine = Standard_GetStatus; + } + } + + } + + /*GET CONFIGURATION*/ + else if (Request_No == GET_CONFIGURATION) + { + if (Type_Recipient == (STANDARD_REQUEST | DEVICE_RECIPIENT)) + { + CopyRoutine = Standard_GetConfiguration; + } + } + /*GET INTERFACE*/ + else if (Request_No == GET_INTERFACE) + { + if ((Type_Recipient == (STANDARD_REQUEST | INTERFACE_RECIPIENT)) + && (pInformation->Current_Configuration != 0) && (pInformation->USBwValue == 0) + && (pInformation->USBwIndex1 == 0) && (pInformation->USBwLength == 0x0001) + && ((*pProperty->Class_Get_Interface_Setting)(pInformation->USBwIndex0, 0) == USB_SUCCESS)) + { + CopyRoutine = Standard_GetInterface; + } + + } + + if (CopyRoutine) + { + pInformation->Ctrl_Info.Usb_wOffset = wOffset; + pInformation->Ctrl_Info.CopyData = CopyRoutine; + /* sb in the original the cast to word was directly */ + /* now the cast is made step by step */ + (*CopyRoutine)(0); + Result = USB_SUCCESS; + } + else + { + Result = (*pProperty->Class_Data_Setup)(pInformation->USBbRequest); + if (Result == USB_NOT_READY) + { + pInformation->ControlState = PAUSE; + return; + } + } + + if (pInformation->Ctrl_Info.Usb_wLength == 0xFFFF) + { + /* Data is not ready, wait it */ + pInformation->ControlState = PAUSE; + return; + } + if ((Result == USB_UNSUPPORT) || (pInformation->Ctrl_Info.Usb_wLength == 0)) + { + /* Unsupported request */ + pInformation->ControlState = STALLED; + return; + } + + + if (ValBit(pInformation->USBbmRequestType, 7)) + { + /* Device ==> Host */ + __IO uint32_t wLength = pInformation->USBwLength; + + /* Restrict the data length to be the one host asks for */ + if (pInformation->Ctrl_Info.Usb_wLength > wLength) + { + pInformation->Ctrl_Info.Usb_wLength = wLength; + } + + else if (pInformation->Ctrl_Info.Usb_wLength < pInformation->USBwLength) + { + if (pInformation->Ctrl_Info.Usb_wLength < pProperty->MaxPacketSize) + { + Data_Mul_MaxPacketSize = FALSE; + } + else if ((pInformation->Ctrl_Info.Usb_wLength % pProperty->MaxPacketSize) == 0) + { + Data_Mul_MaxPacketSize = TRUE; + } + } + + pInformation->Ctrl_Info.PacketSize = pProperty->MaxPacketSize; + DataStageIn(); + } + else + { + pInformation->ControlState = OUT_DATA; + vSetEPRxStatus(EP_RX_VALID); /* enable for next data reception */ + } + + return; +} + +/******************************************************************************* +* Function Name : Setup0_Process +* Description : Get the device request data and dispatch to individual process. +* Input : None. +* Output : None. +* Return : Post0_Process. +*******************************************************************************/ +uint8_t Setup0_Process(void) +{ + + union + { + uint8_t* b; + uint16_t* w; + } pBuf; + uint16_t offset = 1; + + pBuf.b = PMAAddr + (uint8_t *)(_GetEPRxAddr(ENDP0) * 2); /* *2 for 32 bits addr */ + + if (pInformation->ControlState != PAUSE) + { + pInformation->USBbmRequestType = *pBuf.b++; /* bmRequestType */ + pInformation->USBbRequest = *pBuf.b++; /* bRequest */ + pBuf.w += offset; /* word not accessed because of 32 bits addressing */ + pInformation->USBwValue = ByteSwap(*pBuf.w++); /* wValue */ + pBuf.w += offset; /* word not accessed because of 32 bits addressing */ + pInformation->USBwIndex = ByteSwap(*pBuf.w++); /* wIndex */ + pBuf.w += offset; /* word not accessed because of 32 bits addressing */ + pInformation->USBwLength = *pBuf.w; /* wLength */ + } + + pInformation->ControlState = SETTING_UP; + if (pInformation->USBwLength == 0) + { + /* Setup with no data stage */ + NoData_Setup0(); + } + else + { + /* Setup with data stage */ + Data_Setup0(); + } + return Post0_Process(); +} + +/******************************************************************************* +* Function Name : In0_Process +* Description : Process the IN token on all default endpoint. +* Input : None. +* Output : None. +* Return : Post0_Process. +*******************************************************************************/ +uint8_t In0_Process(void) +{ + uint32_t ControlState = pInformation->ControlState; + + if ((ControlState == IN_DATA) || (ControlState == LAST_IN_DATA)) + { + DataStageIn(); + /* ControlState may be changed outside the function */ + ControlState = pInformation->ControlState; + } + + else if (ControlState == WAIT_STATUS_IN) + { + if ((pInformation->USBbRequest == SET_ADDRESS) && + (Type_Recipient == (STANDARD_REQUEST | DEVICE_RECIPIENT))) + { + SetDeviceAddress(pInformation->USBwValue0); + pUser_Standard_Requests->User_SetDeviceAddress(); + } + (*pProperty->Process_Status_IN)(); + ControlState = STALLED; + } + + else + { + ControlState = STALLED; + } + + pInformation->ControlState = ControlState; + + return Post0_Process(); +} + +/******************************************************************************* +* Function Name : Out0_Process +* Description : Process the OUT token on all default endpoint. +* Input : None. +* Output : None. +* Return : Post0_Process. +*******************************************************************************/ +uint8_t Out0_Process(void) +{ + uint32_t ControlState = pInformation->ControlState; + + if ((ControlState == IN_DATA) || (ControlState == LAST_IN_DATA)) + { + /* host aborts the transfer before finish */ + ControlState = STALLED; + } + else if ((ControlState == OUT_DATA) || (ControlState == LAST_OUT_DATA)) + { + DataStageOut(); + ControlState = pInformation->ControlState; /* may be changed outside the function */ + } + + else if (ControlState == WAIT_STATUS_OUT) + { + (*pProperty->Process_Status_OUT)(); + ControlState = STALLED; + } + + + /* Unexpect state, STALL the endpoint */ + else + { + ControlState = STALLED; + } + + pInformation->ControlState = ControlState; + + return Post0_Process(); +} + +/******************************************************************************* +* Function Name : Post0_Process +* Description : Stall the Endpoint 0 in case of error. +* Input : None. +* Output : None. +* Return : - 0 if the control State is in PAUSE +* - 1 if not. +*******************************************************************************/ +uint8_t Post0_Process(void) +{ + + SetEPRxCount(ENDP0, Device_Property.MaxPacketSize); + + if (pInformation->ControlState == STALLED) + { + vSetEPRxStatus(EP_RX_STALL); + vSetEPTxStatus(EP_TX_STALL); + } + + return (pInformation->ControlState == PAUSE); +} + +/******************************************************************************* +* Function Name : SetDeviceAddress. +* Description : Set the device and all the used Endpoints addresses. +* Input : - Val: device address. +* Output : None. +* Return : None. +*******************************************************************************/ +void SetDeviceAddress(uint8_t Val) +{ + uint32_t i; + uint32_t nEP = Device_Table.Total_Endpoint; + + /* set address in every used endpoint */ + for (i = 0; i < nEP; i++) + { + _SetEPAddress((uint8_t)i, (uint8_t)i); + } /* for */ + _SetDADDR(Val | DADDR_EF); /* set device address and enable function */ +} + +/******************************************************************************* +* Function Name : NOP_Process +* Description : No operation function. +* Input : None. +* Output : None. +* Return : None. +*******************************************************************************/ +void NOP_Process(void) +{ +} + +/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ diff --git a/Libraries/STM32_USB-FS-Device_Driver/src/usb_init.c b/Libraries/STM32_USB-FS-Device_Driver/src/usb_init.c new file mode 100644 index 0000000..0949620 --- /dev/null +++ b/Libraries/STM32_USB-FS-Device_Driver/src/usb_init.c @@ -0,0 +1,76 @@ +/** + ****************************************************************************** + * @file usb_init.c + * @author MCD Application Team + * @version V4.0.0 + * @date 28-August-2012 + * @brief Initialization routines & global variables + ****************************************************************************** + * @attention + * + *

    © COPYRIGHT 2012 STMicroelectronics

    + * + * Licensed under MCD-ST Liberty SW License Agreement V2, (the "License"); + * You may not use this file except in compliance with the License. + * You may obtain a copy of the License at: + * + * http://www.st.com/software_license_agreement_liberty_v2 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, + * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + * + ****************************************************************************** + */ + + +/* Includes ------------------------------------------------------------------*/ +#include "usb_lib.h" + +/* Private typedef -----------------------------------------------------------*/ +/* Private define ------------------------------------------------------------*/ +/* Private macro -------------------------------------------------------------*/ +/* Private variables ---------------------------------------------------------*/ +/* The number of current endpoint, it will be used to specify an endpoint */ + uint8_t EPindex; +/* The number of current device, it is an index to the Device_Table */ +/* uint8_t Device_no; */ +/* Points to the DEVICE_INFO structure of current device */ +/* The purpose of this register is to speed up the execution */ +DEVICE_INFO *pInformation; +/* Points to the DEVICE_PROP structure of current device */ +/* The purpose of this register is to speed up the execution */ +DEVICE_PROP *pProperty; +/* Temporary save the state of Rx & Tx status. */ +/* Whenever the Rx or Tx state is changed, its value is saved */ +/* in this variable first and will be set to the EPRB or EPRA */ +/* at the end of interrupt process */ +uint16_t SaveState ; +uint16_t wInterrupt_Mask; +DEVICE_INFO Device_Info; +USER_STANDARD_REQUESTS *pUser_Standard_Requests; + +/* Extern variables ----------------------------------------------------------*/ +/* Private function prototypes -----------------------------------------------*/ +/* Private functions ---------------------------------------------------------*/ + +/******************************************************************************* +* Function Name : USB_Init +* Description : USB system initialization +* Input : None. +* Output : None. +* Return : None. +*******************************************************************************/ +void USB_Init(void) +{ + pInformation = &Device_Info; + pInformation->ControlState = 2; + pProperty = &Device_Property; + pUser_Standard_Requests = &User_Standard_Requests; + /* Initialize devices one by one */ + pProperty->Init(); +} + +/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ diff --git a/Libraries/STM32_USB-FS-Device_Driver/src/usb_int.c b/Libraries/STM32_USB-FS-Device_Driver/src/usb_int.c new file mode 100644 index 0000000..dbaa331 --- /dev/null +++ b/Libraries/STM32_USB-FS-Device_Driver/src/usb_int.c @@ -0,0 +1,195 @@ +/** + ****************************************************************************** + * @file usb_int.c + * @author MCD Application Team + * @version V4.0.0 + * @date 28-August-2012 + * @brief Endpoint CTR (Low and High) interrupt's service routines + ****************************************************************************** + * @attention + * + *

    © COPYRIGHT 2012 STMicroelectronics

    + * + * Licensed under MCD-ST Liberty SW License Agreement V2, (the "License"); + * You may not use this file except in compliance with the License. + * You may obtain a copy of the License at: + * + * http://www.st.com/software_license_agreement_liberty_v2 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, + * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + * + ****************************************************************************** + */ + +/* Includes ------------------------------------------------------------------*/ +#include "usb_lib.h" + +/* Private typedef -----------------------------------------------------------*/ +/* Private define ------------------------------------------------------------*/ +/* Private macro -------------------------------------------------------------*/ +/* Private variables ---------------------------------------------------------*/ +__IO uint16_t SaveRState; +__IO uint16_t SaveTState; + +/* Extern variables ----------------------------------------------------------*/ +extern void (*pEpInt_IN[7])(void); /* Handles IN interrupts */ +extern void (*pEpInt_OUT[7])(void); /* Handles OUT interrupts */ + +/* Private function prototypes -----------------------------------------------*/ +/* Private functions ---------------------------------------------------------*/ + +/******************************************************************************* +* Function Name : CTR_LP. +* Description : Low priority Endpoint Correct Transfer interrupt's service +* routine. +* Input : None. +* Output : None. +* Return : None. +*******************************************************************************/ +void CTR_LP(void) +{ + __IO uint16_t wEPVal = 0; + /* stay in loop while pending interrupts */ + while (((wIstr = _GetISTR()) & ISTR_CTR) != 0) + { + /* extract highest priority endpoint number */ + EPindex = (uint8_t)(wIstr & ISTR_EP_ID); + if (EPindex == 0) + { + /* Decode and service control endpoint interrupt */ + /* calling related service routine */ + /* (Setup0_Process, In0_Process, Out0_Process) */ + + /* save RX & TX status */ + /* and set both to NAK */ + + SaveRState = _GetENDPOINT(ENDP0); + SaveTState = SaveRState & EPTX_STAT; + SaveRState &= EPRX_STAT; + + _SetEPRxTxStatus(ENDP0,EP_RX_NAK,EP_TX_NAK); + + /* DIR bit = origin of the interrupt */ + + if ((wIstr & ISTR_DIR) == 0) + { + /* DIR = 0 */ + + /* DIR = 0 => IN int */ + /* DIR = 0 implies that (EP_CTR_TX = 1) always */ + + _ClearEP_CTR_TX(ENDP0); + In0_Process(); + + /* before terminate set Tx & Rx status */ + + _SetEPRxTxStatus(ENDP0,SaveRState,SaveTState); + return; + } + else + { + /* DIR = 1 */ + + /* DIR = 1 & CTR_RX => SETUP or OUT int */ + /* DIR = 1 & (CTR_TX | CTR_RX) => 2 int pending */ + + wEPVal = _GetENDPOINT(ENDP0); + + if ((wEPVal &EP_SETUP) != 0) + { + _ClearEP_CTR_RX(ENDP0); /* SETUP bit kept frozen while CTR_RX = 1 */ + Setup0_Process(); + /* before terminate set Tx & Rx status */ + + _SetEPRxTxStatus(ENDP0,SaveRState,SaveTState); + return; + } + + else if ((wEPVal & EP_CTR_RX) != 0) + { + _ClearEP_CTR_RX(ENDP0); + Out0_Process(); + /* before terminate set Tx & Rx status */ + + _SetEPRxTxStatus(ENDP0,SaveRState,SaveTState); + return; + } + } + }/* if(EPindex == 0) */ + else + { + /* Decode and service non control endpoints interrupt */ + + /* process related endpoint register */ + wEPVal = _GetENDPOINT(EPindex); + if ((wEPVal & EP_CTR_RX) != 0) + { + /* clear int flag */ + _ClearEP_CTR_RX(EPindex); + + /* call OUT service function */ + (*pEpInt_OUT[EPindex-1])(); + + } /* if((wEPVal & EP_CTR_RX) */ + + if ((wEPVal & EP_CTR_TX) != 0) + { + /* clear int flag */ + _ClearEP_CTR_TX(EPindex); + + /* call IN service function */ + (*pEpInt_IN[EPindex-1])(); + } /* if((wEPVal & EP_CTR_TX) != 0) */ + + }/* if(EPindex == 0) else */ + + }/* while(...) */ +} + +/******************************************************************************* +* Function Name : CTR_HP. +* Description : High Priority Endpoint Correct Transfer interrupt's service +* routine. +* Input : None. +* Output : None. +* Return : None. +*******************************************************************************/ +void CTR_HP(void) +{ + uint32_t wEPVal = 0; + + while (((wIstr = _GetISTR()) & ISTR_CTR) != 0) + { + _SetISTR((uint16_t)CLR_CTR); /* clear CTR flag */ + /* extract highest priority endpoint number */ + EPindex = (uint8_t)(wIstr & ISTR_EP_ID); + /* process related endpoint register */ + wEPVal = _GetENDPOINT(EPindex); + if ((wEPVal & EP_CTR_RX) != 0) + { + /* clear int flag */ + _ClearEP_CTR_RX(EPindex); + + /* call OUT service function */ + (*pEpInt_OUT[EPindex-1])(); + + } /* if((wEPVal & EP_CTR_RX) */ + else if ((wEPVal & EP_CTR_TX) != 0) + { + /* clear int flag */ + _ClearEP_CTR_TX(EPindex); + + /* call IN service function */ + (*pEpInt_IN[EPindex-1])(); + + + } /* if((wEPVal & EP_CTR_TX) != 0) */ + + }/* while(...) */ +} + +/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ diff --git a/Libraries/STM32_USB-FS-Device_Driver/src/usb_mem.c b/Libraries/STM32_USB-FS-Device_Driver/src/usb_mem.c new file mode 100644 index 0000000..4e0748a --- /dev/null +++ b/Libraries/STM32_USB-FS-Device_Driver/src/usb_mem.c @@ -0,0 +1,87 @@ +/** + ****************************************************************************** + * @file usb_mem.c + * @author MCD Application Team + * @version V4.0.0 + * @date 28-August-2012 + * @brief Utility functions for memory transfers to/from PMA + ****************************************************************************** + * @attention + * + *

    © COPYRIGHT 2012 STMicroelectronics

    + * + * Licensed under MCD-ST Liberty SW License Agreement V2, (the "License"); + * You may not use this file except in compliance with the License. + * You may obtain a copy of the License at: + * + * http://www.st.com/software_license_agreement_liberty_v2 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, + * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + * + ****************************************************************************** + */ + +/* Includes ------------------------------------------------------------------*/ +#include "usb_lib.h" + +/* Private typedef -----------------------------------------------------------*/ +/* Private define ------------------------------------------------------------*/ +/* Private macro -------------------------------------------------------------*/ +/* Private variables ---------------------------------------------------------*/ +/* Extern variables ----------------------------------------------------------*/ +/* Private function prototypes -----------------------------------------------*/ +/* Private functions ---------------------------------------------------------*/ + +/******************************************************************************* +* Function Name : UserToPMABufferCopy +* Description : Copy a buffer from user memory area to packet memory area (PMA) +* Input : - pbUsrBuf: pointer to user memory area. +* - wPMABufAddr: address into PMA. +* - wNBytes: no. of bytes to be copied. +* Output : None. +* Return : None . +*******************************************************************************/ +void UserToPMABufferCopy(uint8_t *pbUsrBuf, uint16_t wPMABufAddr, uint16_t wNBytes) +{ + uint32_t n = (wNBytes + 1) >> 1; /* n = (wNBytes + 1) / 2 */ + uint32_t i, temp1, temp2; + uint16_t *pdwVal; + pdwVal = (uint16_t *)(wPMABufAddr * 2 + PMAAddr); + for (i = n; i != 0; i--) + { + temp1 = (uint16_t) * pbUsrBuf; + pbUsrBuf++; + temp2 = temp1 | (uint16_t) * pbUsrBuf << 8; + *pdwVal++ = temp2; + pdwVal++; + pbUsrBuf++; + } +} + +/******************************************************************************* +* Function Name : PMAToUserBufferCopy +* Description : Copy a buffer from user memory area to packet memory area (PMA) +* Input : - pbUsrBuf = pointer to user memory area. +* - wPMABufAddr = address into PMA. +* - wNBytes = no. of bytes to be copied. +* Output : None. +* Return : None. +*******************************************************************************/ +void PMAToUserBufferCopy(uint8_t *pbUsrBuf, uint16_t wPMABufAddr, uint16_t wNBytes) +{ + uint32_t n = (wNBytes + 1) >> 1;/* /2*/ + uint32_t i; + uint32_t *pdwVal; + pdwVal = (uint32_t *)(wPMABufAddr * 2 + PMAAddr); + for (i = n; i != 0; i--) + { + *(uint16_t*)pbUsrBuf++ = *pdwVal++; + pbUsrBuf++; + } +} + +/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ diff --git a/Libraries/STM32_USB-FS-Device_Driver/src/usb_regs.c b/Libraries/STM32_USB-FS-Device_Driver/src/usb_regs.c new file mode 100644 index 0000000..b1e22fe --- /dev/null +++ b/Libraries/STM32_USB-FS-Device_Driver/src/usb_regs.c @@ -0,0 +1,760 @@ +/** + ****************************************************************************** + * @file usb_regs.c + * @author MCD Application Team + * @version V4.0.0 + * @date 28-August-2012 + * @brief Interface functions to USB cell registers + ****************************************************************************** + * @attention + * + *

    © COPYRIGHT 2012 STMicroelectronics

    + * + * Licensed under MCD-ST Liberty SW License Agreement V2, (the "License"); + * You may not use this file except in compliance with the License. + * You may obtain a copy of the License at: + * + * http://www.st.com/software_license_agreement_liberty_v2 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, + * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + * + ****************************************************************************** + */ + +/* Includes ------------------------------------------------------------------*/ +#include "usb_lib.h" + +/* Private typedef -----------------------------------------------------------*/ +/* Private define ------------------------------------------------------------*/ +/* Private macro -------------------------------------------------------------*/ +/* Private variables ---------------------------------------------------------*/ +/* Extern variables ----------------------------------------------------------*/ +/* Private function prototypes -----------------------------------------------*/ +/* Private functions ---------------------------------------------------------*/ + +/******************************************************************************* +* Function Name : SetCNTR. +* Description : Set the CNTR register value. +* Input : wRegValue: new register value. +* Output : None. +* Return : None. +*******************************************************************************/ +void SetCNTR(uint16_t wRegValue) +{ + _SetCNTR(wRegValue); +} + +/******************************************************************************* +* Function Name : GetCNTR. +* Description : returns the CNTR register value. +* Input : None. +* Output : None. +* Return : CNTR register Value. +*******************************************************************************/ +uint16_t GetCNTR(void) +{ + return(_GetCNTR()); +} + +/******************************************************************************* +* Function Name : SetISTR. +* Description : Set the ISTR register value. +* Input : wRegValue: new register value. +* Output : None. +* Return : None. +*******************************************************************************/ +void SetISTR(uint16_t wRegValue) +{ + _SetISTR(wRegValue); +} + +/******************************************************************************* +* Function Name : GetISTR +* Description : Returns the ISTR register value. +* Input : None. +* Output : None. +* Return : ISTR register Value +*******************************************************************************/ +uint16_t GetISTR(void) +{ + return(_GetISTR()); +} + +/******************************************************************************* +* Function Name : GetFNR +* Description : Returns the FNR register value. +* Input : None. +* Output : None. +* Return : FNR register Value +*******************************************************************************/ +uint16_t GetFNR(void) +{ + return(_GetFNR()); +} + +/******************************************************************************* +* Function Name : SetDADDR +* Description : Set the DADDR register value. +* Input : wRegValue: new register value. +* Output : None. +* Return : None. +*******************************************************************************/ +void SetDADDR(uint16_t wRegValue) +{ + _SetDADDR(wRegValue); +} + +/******************************************************************************* +* Function Name : GetDADDR +* Description : Returns the DADDR register value. +* Input : None. +* Output : None. +* Return : DADDR register Value +*******************************************************************************/ +uint16_t GetDADDR(void) +{ + return(_GetDADDR()); +} + +/******************************************************************************* +* Function Name : SetBTABLE +* Description : Set the BTABLE. +* Input : wRegValue: New register value. +* Output : None. +* Return : None. +*******************************************************************************/ +void SetBTABLE(uint16_t wRegValue) +{ + _SetBTABLE(wRegValue); +} + +/******************************************************************************* +* Function Name : GetBTABLE. +* Description : Returns the BTABLE register value. +* Input : None. +* Output : None. +* Return : BTABLE address. +*******************************************************************************/ +uint16_t GetBTABLE(void) +{ + return(_GetBTABLE()); +} + +/******************************************************************************* +* Function Name : SetENDPOINT +* Description : Set the Endpoint register value. +* Input : bEpNum: Endpoint Number. +* wRegValue. +* Output : None. +* Return : None. +*******************************************************************************/ +void SetENDPOINT(uint8_t bEpNum, uint16_t wRegValue) +{ + _SetENDPOINT(bEpNum, wRegValue); +} + +/******************************************************************************* +* Function Name : GetENDPOINT +* Description : Return the Endpoint register value. +* Input : bEpNum: Endpoint Number. +* Output : None. +* Return : Endpoint register value. +*******************************************************************************/ +uint16_t GetENDPOINT(uint8_t bEpNum) +{ + return(_GetENDPOINT(bEpNum)); +} + +/******************************************************************************* +* Function Name : SetEPType +* Description : sets the type in the endpoint register. +* Input : bEpNum: Endpoint Number. +* wType: type definition. +* Output : None. +* Return : None. +*******************************************************************************/ +void SetEPType(uint8_t bEpNum, uint16_t wType) +{ + _SetEPType(bEpNum, wType); +} + +/******************************************************************************* +* Function Name : GetEPType +* Description : Returns the endpoint type. +* Input : bEpNum: Endpoint Number. +* Output : None. +* Return : Endpoint Type +*******************************************************************************/ +uint16_t GetEPType(uint8_t bEpNum) +{ + return(_GetEPType(bEpNum)); +} + +/******************************************************************************* +* Function Name : SetEPTxStatus +* Description : Set the status of Tx endpoint. +* Input : bEpNum: Endpoint Number. +* wState: new state. +* Output : None. +* Return : None. +*******************************************************************************/ +void SetEPTxStatus(uint8_t bEpNum, uint16_t wState) +{ + _SetEPTxStatus(bEpNum, wState); +} + +/******************************************************************************* +* Function Name : SetEPRxStatus +* Description : Set the status of Rx endpoint. +* Input : bEpNum: Endpoint Number. +* wState: new state. +* Output : None. +* Return : None. +*******************************************************************************/ +void SetEPRxStatus(uint8_t bEpNum, uint16_t wState) +{ + _SetEPRxStatus(bEpNum, wState); +} + +/******************************************************************************* +* Function Name : SetDouBleBuffEPStall +* Description : sets the status for Double Buffer Endpoint to STALL +* Input : bEpNum: Endpoint Number. +* bDir: Endpoint direction. +* Output : None. +* Return : None. +*******************************************************************************/ +void SetDouBleBuffEPStall(uint8_t bEpNum, uint8_t bDir) +{ + uint16_t Endpoint_DTOG_Status; + Endpoint_DTOG_Status = GetENDPOINT(bEpNum); + if (bDir == EP_DBUF_OUT) + { /* OUT double buffered endpoint */ + _SetENDPOINT(bEpNum, Endpoint_DTOG_Status & ~EPRX_DTOG1); + } + else if (bDir == EP_DBUF_IN) + { /* IN double buffered endpoint */ + _SetENDPOINT(bEpNum, Endpoint_DTOG_Status & ~EPTX_DTOG1); + } +} + +/******************************************************************************* +* Function Name : GetEPTxStatus +* Description : Returns the endpoint Tx status. +* Input : bEpNum: Endpoint Number. +* Output : None. +* Return : Endpoint TX Status +*******************************************************************************/ +uint16_t GetEPTxStatus(uint8_t bEpNum) +{ + return(_GetEPTxStatus(bEpNum)); +} + +/******************************************************************************* +* Function Name : GetEPRxStatus +* Description : Returns the endpoint Rx status. +* Input : bEpNum: Endpoint Number. +* Output : None. +* Return : Endpoint RX Status +*******************************************************************************/ +uint16_t GetEPRxStatus(uint8_t bEpNum) +{ + return(_GetEPRxStatus(bEpNum)); +} + +/******************************************************************************* +* Function Name : SetEPTxValid +* Description : Valid the endpoint Tx Status. +* Input : bEpNum: Endpoint Number. +* Output : None. +* Return : None. +*******************************************************************************/ +void SetEPTxValid(uint8_t bEpNum) +{ + _SetEPTxStatus(bEpNum, EP_TX_VALID); +} + +/******************************************************************************* +* Function Name : SetEPRxValid +* Description : Valid the endpoint Rx Status. +* Input : bEpNum: Endpoint Number. +* Output : None. +* Return : None. +*******************************************************************************/ +void SetEPRxValid(uint8_t bEpNum) +{ + _SetEPRxStatus(bEpNum, EP_RX_VALID); +} + +/******************************************************************************* +* Function Name : SetEP_KIND +* Description : Clear the EP_KIND bit. +* Input : bEpNum: Endpoint Number. +* Output : None. +* Return : None. +*******************************************************************************/ +void SetEP_KIND(uint8_t bEpNum) +{ + _SetEP_KIND(bEpNum); +} + +/******************************************************************************* +* Function Name : ClearEP_KIND +* Description : set the EP_KIND bit. +* Input : bEpNum: Endpoint Number. +* Output : None. +* Return : None. +*******************************************************************************/ +void ClearEP_KIND(uint8_t bEpNum) +{ + _ClearEP_KIND(bEpNum); +} +/******************************************************************************* +* Function Name : Clear_Status_Out +* Description : Clear the Status Out of the related Endpoint +* Input : bEpNum: Endpoint Number. +* Output : None. +* Return : None. +*******************************************************************************/ +void Clear_Status_Out(uint8_t bEpNum) +{ + _ClearEP_KIND(bEpNum); +} +/******************************************************************************* +* Function Name : Set_Status_Out +* Description : Set the Status Out of the related Endpoint +* Input : bEpNum: Endpoint Number. +* Output : None. +* Return : None. +*******************************************************************************/ +void Set_Status_Out(uint8_t bEpNum) +{ + _SetEP_KIND(bEpNum); +} +/******************************************************************************* +* Function Name : SetEPDoubleBuff +* Description : Enable the double buffer feature for the endpoint. +* Input : bEpNum: Endpoint Number. +* Output : None. +* Return : None. +*******************************************************************************/ +void SetEPDoubleBuff(uint8_t bEpNum) +{ + _SetEP_KIND(bEpNum); +} +/******************************************************************************* +* Function Name : ClearEPDoubleBuff +* Description : Disable the double buffer feature for the endpoint. +* Input : bEpNum: Endpoint Number. +* Output : None. +* Return : None. +*******************************************************************************/ +void ClearEPDoubleBuff(uint8_t bEpNum) +{ + _ClearEP_KIND(bEpNum); +} +/******************************************************************************* +* Function Name : GetTxStallStatus +* Description : Returns the Stall status of the Tx endpoint. +* Input : bEpNum: Endpoint Number. +* Output : None. +* Return : Tx Stall status. +*******************************************************************************/ +uint16_t GetTxStallStatus(uint8_t bEpNum) +{ + return(_GetTxStallStatus(bEpNum)); +} +/******************************************************************************* +* Function Name : GetRxStallStatus +* Description : Returns the Stall status of the Rx endpoint. +* Input : bEpNum: Endpoint Number. +* Output : None. +* Return : Rx Stall status. +*******************************************************************************/ +uint16_t GetRxStallStatus(uint8_t bEpNum) +{ + return(_GetRxStallStatus(bEpNum)); +} +/******************************************************************************* +* Function Name : ClearEP_CTR_RX +* Description : Clear the CTR_RX bit. +* Input : bEpNum: Endpoint Number. +* Output : None. +* Return : None. +*******************************************************************************/ +void ClearEP_CTR_RX(uint8_t bEpNum) +{ + _ClearEP_CTR_RX(bEpNum); +} +/******************************************************************************* +* Function Name : ClearEP_CTR_TX +* Description : Clear the CTR_TX bit. +* Input : bEpNum: Endpoint Number. +* Output : None. +* Return : None. +*******************************************************************************/ +void ClearEP_CTR_TX(uint8_t bEpNum) +{ + _ClearEP_CTR_TX(bEpNum); +} +/******************************************************************************* +* Function Name : ToggleDTOG_RX +* Description : Toggle the DTOG_RX bit. +* Input : bEpNum: Endpoint Number. +* Output : None. +* Return : None. +*******************************************************************************/ +void ToggleDTOG_RX(uint8_t bEpNum) +{ + _ToggleDTOG_RX(bEpNum); +} +/******************************************************************************* +* Function Name : ToggleDTOG_TX +* Description : Toggle the DTOG_TX bit. +* Input : bEpNum: Endpoint Number. +* Output : None. +* Return : None. +*******************************************************************************/ +void ToggleDTOG_TX(uint8_t bEpNum) +{ + _ToggleDTOG_TX(bEpNum); +} +/******************************************************************************* +* Function Name : ClearDTOG_RX. +* Description : Clear the DTOG_RX bit. +* Input : bEpNum: Endpoint Number. +* Output : None. +* Return : None. +*******************************************************************************/ +void ClearDTOG_RX(uint8_t bEpNum) +{ + _ClearDTOG_RX(bEpNum); +} +/******************************************************************************* +* Function Name : ClearDTOG_TX. +* Description : Clear the DTOG_TX bit. +* Input : bEpNum: Endpoint Number. +* Output : None. +* Return : None. +*******************************************************************************/ +void ClearDTOG_TX(uint8_t bEpNum) +{ + _ClearDTOG_TX(bEpNum); +} +/******************************************************************************* +* Function Name : SetEPAddress +* Description : Set the endpoint address. +* Input : bEpNum: Endpoint Number. +* bAddr: New endpoint address. +* Output : None. +* Return : None. +*******************************************************************************/ +void SetEPAddress(uint8_t bEpNum, uint8_t bAddr) +{ + _SetEPAddress(bEpNum, bAddr); +} +/******************************************************************************* +* Function Name : GetEPAddress +* Description : Get the endpoint address. +* Input : bEpNum: Endpoint Number. +* Output : None. +* Return : Endpoint address. +*******************************************************************************/ +uint8_t GetEPAddress(uint8_t bEpNum) +{ + return(_GetEPAddress(bEpNum)); +} +/******************************************************************************* +* Function Name : SetEPTxAddr +* Description : Set the endpoint Tx buffer address. +* Input : bEpNum: Endpoint Number. +* wAddr: new address. +* Output : None. +* Return : None. +*******************************************************************************/ +void SetEPTxAddr(uint8_t bEpNum, uint16_t wAddr) +{ + _SetEPTxAddr(bEpNum, wAddr); +} +/******************************************************************************* +* Function Name : SetEPRxAddr +* Description : Set the endpoint Rx buffer address. +* Input : bEpNum: Endpoint Number. +* wAddr: new address. +* Output : None. +* Return : None. +*******************************************************************************/ +void SetEPRxAddr(uint8_t bEpNum, uint16_t wAddr) +{ + _SetEPRxAddr(bEpNum, wAddr); +} +/******************************************************************************* +* Function Name : GetEPTxAddr +* Description : Returns the endpoint Tx buffer address. +* Input : bEpNum: Endpoint Number. +* Output : None. +* Return : Rx buffer address. +*******************************************************************************/ +uint16_t GetEPTxAddr(uint8_t bEpNum) +{ + return(_GetEPTxAddr(bEpNum)); +} +/******************************************************************************* +* Function Name : GetEPRxAddr. +* Description : Returns the endpoint Rx buffer address. +* Input : bEpNum: Endpoint Number. +* Output : None. +* Return : Rx buffer address. +*******************************************************************************/ +uint16_t GetEPRxAddr(uint8_t bEpNum) +{ + return(_GetEPRxAddr(bEpNum)); +} +/******************************************************************************* +* Function Name : SetEPTxCount. +* Description : Set the Tx count. +* Input : bEpNum: Endpoint Number. +* wCount: new count value. +* Output : None. +* Return : None. +*******************************************************************************/ +void SetEPTxCount(uint8_t bEpNum, uint16_t wCount) +{ + _SetEPTxCount(bEpNum, wCount); +} +/******************************************************************************* +* Function Name : SetEPCountRxReg. +* Description : Set the Count Rx Register value. +* Input : *pdwReg: point to the register. +* wCount: the new register value. +* Output : None. +* Return : None. +*******************************************************************************/ +void SetEPCountRxReg(uint32_t *pdwReg, uint16_t wCount) +{ + _SetEPCountRxReg(dwReg, wCount); +} +/******************************************************************************* +* Function Name : SetEPRxCount +* Description : Set the Rx count. +* Input : bEpNum: Endpoint Number. +* wCount: the new count value. +* Output : None. +* Return : None. +*******************************************************************************/ +void SetEPRxCount(uint8_t bEpNum, uint16_t wCount) +{ + _SetEPRxCount(bEpNum, wCount); +} +/******************************************************************************* +* Function Name : GetEPTxCount +* Description : Get the Tx count. +* Input : bEpNum: Endpoint Number. +* Output : None +* Return : Tx count value. +*******************************************************************************/ +uint16_t GetEPTxCount(uint8_t bEpNum) +{ + return(_GetEPTxCount(bEpNum)); +} +/******************************************************************************* +* Function Name : GetEPRxCount +* Description : Get the Rx count. +* Input : bEpNum: Endpoint Number. +* Output : None. +* Return : Rx count value. +*******************************************************************************/ +uint16_t GetEPRxCount(uint8_t bEpNum) +{ + return(_GetEPRxCount(bEpNum)); +} +/******************************************************************************* +* Function Name : SetEPDblBuffAddr +* Description : Set the addresses of the buffer 0 and 1. +* Input : bEpNum: Endpoint Number. +* wBuf0Addr: new address of buffer 0. +* wBuf1Addr: new address of buffer 1. +* Output : None. +* Return : None. +*******************************************************************************/ +void SetEPDblBuffAddr(uint8_t bEpNum, uint16_t wBuf0Addr, uint16_t wBuf1Addr) +{ + _SetEPDblBuffAddr(bEpNum, wBuf0Addr, wBuf1Addr); +} +/******************************************************************************* +* Function Name : SetEPDblBuf0Addr +* Description : Set the Buffer 1 address. +* Input : bEpNum: Endpoint Number +* wBuf0Addr: new address. +* Output : None. +* Return : None. +*******************************************************************************/ +void SetEPDblBuf0Addr(uint8_t bEpNum, uint16_t wBuf0Addr) +{ + _SetEPDblBuf0Addr(bEpNum, wBuf0Addr); +} +/******************************************************************************* +* Function Name : SetEPDblBuf1Addr +* Description : Set the Buffer 1 address. +* Input : bEpNum: Endpoint Number +* wBuf1Addr: new address. +* Output : None. +* Return : None. +*******************************************************************************/ +void SetEPDblBuf1Addr(uint8_t bEpNum, uint16_t wBuf1Addr) +{ + _SetEPDblBuf1Addr(bEpNum, wBuf1Addr); +} +/******************************************************************************* +* Function Name : GetEPDblBuf0Addr +* Description : Returns the address of the Buffer 0. +* Input : bEpNum: Endpoint Number. +* Output : None. +* Return : None. +*******************************************************************************/ +uint16_t GetEPDblBuf0Addr(uint8_t bEpNum) +{ + return(_GetEPDblBuf0Addr(bEpNum)); +} +/******************************************************************************* +* Function Name : GetEPDblBuf1Addr +* Description : Returns the address of the Buffer 1. +* Input : bEpNum: Endpoint Number. +* Output : None. +* Return : Address of the Buffer 1. +*******************************************************************************/ +uint16_t GetEPDblBuf1Addr(uint8_t bEpNum) +{ + return(_GetEPDblBuf1Addr(bEpNum)); +} +/******************************************************************************* +* Function Name : SetEPDblBuffCount +* Description : Set the number of bytes for a double Buffer +* endpoint. +* Input : bEpNum,bDir, wCount +* Output : None. +* Return : None. +*******************************************************************************/ +void SetEPDblBuffCount(uint8_t bEpNum, uint8_t bDir, uint16_t wCount) +{ + _SetEPDblBuffCount(bEpNum, bDir, wCount); +} +/******************************************************************************* +* Function Name : SetEPDblBuf0Count +* Description : Set the number of bytes in the buffer 0 of a double Buffer +* endpoint. +* Input : bEpNum, bDir, wCount +* Output : None. +* Return : None. +*******************************************************************************/ +void SetEPDblBuf0Count(uint8_t bEpNum, uint8_t bDir, uint16_t wCount) +{ + _SetEPDblBuf0Count(bEpNum, bDir, wCount); +} +/******************************************************************************* +* Function Name : SetEPDblBuf1Count +* Description : Set the number of bytes in the buffer 0 of a double Buffer +* endpoint. +* Input : bEpNum, bDir, wCount +* Output : None. +* Return : None. +*******************************************************************************/ +void SetEPDblBuf1Count(uint8_t bEpNum, uint8_t bDir, uint16_t wCount) +{ + _SetEPDblBuf1Count(bEpNum, bDir, wCount); +} +/******************************************************************************* +* Function Name : GetEPDblBuf0Count +* Description : Returns the number of byte received in the buffer 0 of a double +* Buffer endpoint. +* Input : bEpNum: Endpoint Number. +* Output : None. +* Return : Endpoint Buffer 0 count +*******************************************************************************/ +uint16_t GetEPDblBuf0Count(uint8_t bEpNum) +{ + return(_GetEPDblBuf0Count(bEpNum)); +} +/******************************************************************************* +* Function Name : GetEPDblBuf1Count +* Description : Returns the number of data received in the buffer 1 of a double +* Buffer endpoint. +* Input : bEpNum: Endpoint Number. +* Output : None. +* Return : Endpoint Buffer 1 count. +*******************************************************************************/ +uint16_t GetEPDblBuf1Count(uint8_t bEpNum) +{ + return(_GetEPDblBuf1Count(bEpNum)); +} +/******************************************************************************* +* Function Name : GetEPDblBufDir +* Description : gets direction of the double buffered endpoint +* Input : bEpNum: Endpoint Number. +* Output : None. +* Return : EP_DBUF_OUT, EP_DBUF_IN, +* EP_DBUF_ERR if the endpoint counter not yet programmed. +*******************************************************************************/ +EP_DBUF_DIR GetEPDblBufDir(uint8_t bEpNum) +{ + if ((uint16_t)(*_pEPRxCount(bEpNum) & 0xFC00) != 0) + return(EP_DBUF_OUT); + else if (((uint16_t)(*_pEPTxCount(bEpNum)) & 0x03FF) != 0) + return(EP_DBUF_IN); + else + return(EP_DBUF_ERR); +} +/******************************************************************************* +* Function Name : FreeUserBuffer +* Description : free buffer used from the application realizing it to the line + toggles bit SW_BUF in the double buffered endpoint register +* Input : bEpNum, bDir +* Output : None. +* Return : None. +*******************************************************************************/ +void FreeUserBuffer(uint8_t bEpNum, uint8_t bDir) +{ + if (bDir == EP_DBUF_OUT) + { /* OUT double buffered endpoint */ + _ToggleDTOG_TX(bEpNum); + } + else if (bDir == EP_DBUF_IN) + { /* IN double buffered endpoint */ + _ToggleDTOG_RX(bEpNum); + } +} + +/******************************************************************************* +* Function Name : ToWord +* Description : merge two byte in a word. +* Input : bh: byte high, bl: bytes low. +* Output : None. +* Return : resulted word. +*******************************************************************************/ +uint16_t ToWord(uint8_t bh, uint8_t bl) +{ + uint16_t wRet; + wRet = (uint16_t)bl | ((uint16_t)bh << 8); + return(wRet); +} +/******************************************************************************* +* Function Name : ByteSwap +* Description : Swap two byte in a word. +* Input : wSwW: word to Swap. +* Output : None. +* Return : resulted word. +*******************************************************************************/ +uint16_t ByteSwap(uint16_t wSwW) +{ + uint8_t bTemp; + uint16_t wRet; + bTemp = (uint8_t)(wSwW & 0xff); + wRet = (wSwW >> 8) | ((uint16_t)bTemp << 8); + return(wRet); +} + +/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ diff --git a/Libraries/STM32_USB-FS-Device_Driver/src/usb_sil.c b/Libraries/STM32_USB-FS-Device_Driver/src/usb_sil.c new file mode 100644 index 0000000..5f2e4db --- /dev/null +++ b/Libraries/STM32_USB-FS-Device_Driver/src/usb_sil.c @@ -0,0 +1,103 @@ +/** + ****************************************************************************** + * @file usb_sil.c + * @author MCD Application Team + * @version V4.0.0 + * @date 28-August-2012 + * @brief Simplified Interface Layer for Global Initialization and Endpoint + * Rea/Write operations. + ****************************************************************************** + * @attention + * + *

    © COPYRIGHT 2012 STMicroelectronics

    + * + * Licensed under MCD-ST Liberty SW License Agreement V2, (the "License"); + * You may not use this file except in compliance with the License. + * You may obtain a copy of the License at: + * + * http://www.st.com/software_license_agreement_liberty_v2 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, + * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + * + ****************************************************************************** + */ + + +/* Includes ------------------------------------------------------------------*/ +#include "usb_lib.h" + +/* Private typedef -----------------------------------------------------------*/ +/* Private define ------------------------------------------------------------*/ +/* Private macro -------------------------------------------------------------*/ +/* Private variables ---------------------------------------------------------*/ +/* Extern variables ----------------------------------------------------------*/ +/* Private function prototypes -----------------------------------------------*/ +/* Private functions ---------------------------------------------------------*/ + +/******************************************************************************* +* Function Name : USB_SIL_Init +* Description : Initialize the USB Device IP and the Endpoint 0. +* Input : None. +* Output : None. +* Return : Status. +*******************************************************************************/ +uint32_t USB_SIL_Init(void) +{ + /* USB interrupts initialization */ + /* clear pending interrupts */ + _SetISTR(0); + wInterrupt_Mask = IMR_MSK; + /* set interrupts mask */ + _SetCNTR(wInterrupt_Mask); + return 0; +} + +/******************************************************************************* +* Function Name : USB_SIL_Write +* Description : Write a buffer of data to a selected endpoint. +* Input : - bEpAddr: The address of the non control endpoint. +* - pBufferPointer: The pointer to the buffer of data to be written +* to the endpoint. +* - wBufferSize: Number of data to be written (in bytes). +* Output : None. +* Return : Status. +*******************************************************************************/ +uint32_t USB_SIL_Write(uint8_t bEpAddr, uint8_t* pBufferPointer, uint32_t wBufferSize) +{ + /* Use the memory interface function to write to the selected endpoint */ + UserToPMABufferCopy(pBufferPointer, GetEPTxAddr(bEpAddr & 0x7F), wBufferSize); + + /* Update the data length in the control register */ + SetEPTxCount((bEpAddr & 0x7F), wBufferSize); + + return 0; +} + +/******************************************************************************* +* Function Name : USB_SIL_Read +* Description : Write a buffer of data to a selected endpoint. +* Input : - bEpAddr: The address of the non control endpoint. +* - pBufferPointer: The pointer to which will be saved the +* received data buffer. +* Output : None. +* Return : Number of received data (in Bytes). +*******************************************************************************/ +uint32_t USB_SIL_Read(uint8_t bEpAddr, uint8_t* pBufferPointer) +{ + uint32_t DataLength = 0; + + /* Get the number of received data on the selected Endpoint */ + DataLength = GetEPRxCount(bEpAddr & 0x7F); + + /* Use the memory interface function to write to the selected endpoint */ + PMAToUserBufferCopy(pBufferPointer, GetEPRxAddr(bEpAddr & 0x7F), DataLength); + + /* Return the number of received data */ + return DataLength; +} + +/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ diff --git a/Project/MDK-ARM/.vscode/c_cpp_properties.json b/Project/MDK-ARM/.vscode/c_cpp_properties.json new file mode 100644 index 0000000..ce73ca1 --- /dev/null +++ b/Project/MDK-ARM/.vscode/c_cpp_properties.json @@ -0,0 +1,207 @@ +{ + "configurations": [ + { + "name": "Flash", + "includePath": [ + "d:\\Project\\MFT\\Motor\\Libraries\\CMSIS\\Device\\ST\\STM32F10x\\Include", + "d:\\Project\\MFT\\Motor\\Libraries\\STM32F10x_StdPeriph_Driver\\inc", + "d:\\Project\\MFT\\Motor\\Libraries\\STM32_USB-FS-Device_Driver\\inc", + "d:\\Project\\MFT\\Motor\\Libraries\\CMSIS\\Include", + "d:\\Project\\MFT\\Motor\\User\\bsp", + "d:\\Project\\MFT\\Motor\\User\\bsp\\inc", + "d:\\Project\\MFT\\Motor\\User\\app\\inc", + "d:\\Project\\MFT\\Motor\\User", + "C:\\Keil_v5\\ARM\\ARMCC\\include", + "C:\\Keil_v5\\ARM\\ARMCC\\include\\rw", + "d:\\Project\\MFT\\Motor\\User\\app\\src", + "d:\\Project\\MFT\\Motor\\User\\bsp\\src", + "d:\\Project\\MFT\\Motor\\Libraries\\CMSIS\\Device\\ST\\STM32F10x\\Source\\Templates\\arm", + "d:\\Project\\MFT\\Motor\\Libraries\\STM32F10x_StdPeriph_Driver\\src", + "d:\\Project\\MFT\\Motor\\Doc" + ], + "defines": [ + "USE_STDPERIPH_DRIVER", + "STM32F10X_HD", + "__CC_ARM", + "__arm__", + "__align(x)=", + "__ALIGNOF__(x)=", + "__alignof__(x)=", + "__asm(x)=", + "__forceinline=", + "__restrict=", + "__global_reg(n)=", + "__inline=", + "__int64=long long", + "__INTADDR__(expr)=0", + "__irq=", + "__packed=", + "__pure=", + "__smc(n)=", + "__svc(n)=", + "__svc_indirect(n)=", + "__svc_indirect_r7(n)=", + "__value_in_regs=", + "__weak=", + "__writeonly=", + "__declspec(x)=", + "__attribute__(x)=", + "__nonnull__(x)=", + "__register=", + "__breakpoint(x)=", + "__cdp(x,y,z)=", + "__clrex()=", + "__clz(x)=0U", + "__current_pc()=0U", + "__current_sp()=0U", + "__disable_fiq()=", + "__disable_irq()=", + "__dmb(x)=", + "__dsb(x)=", + "__enable_fiq()=", + "__enable_irq()=", + "__fabs(x)=0.0", + "__fabsf(x)=0.0f", + "__force_loads()=", + "__force_stores()=", + "__isb(x)=", + "__ldrex(x)=0U", + "__ldrexd(x)=0U", + "__ldrt(x)=0U", + "__memory_changed()=", + "__nop()=", + "__pld(...)=", + "__pli(...)=", + "__qadd(x,y)=0", + "__qdbl(x)=0", + "__qsub(x,y)=0", + "__rbit(x)=0U", + "__rev(x)=0U", + "__return_address()=0U", + "__ror(x,y)=0U", + "__schedule_barrier()=", + "__semihost(x,y)=0", + "__sev()=", + "__sqrt(x)=0.0", + "__sqrtf(x)=0.0f", + "__ssat(x,y)=0", + "__strex(x,y)=0U", + "__strexd(x,y)=0", + "__strt(x,y)=", + "__swp(x,y)=0U", + "__usat(x,y)=0U", + "__wfe()=", + "__wfi()=", + "__yield()=", + "__vfp_status(x,y)=0" + ], + "intelliSenseMode": "${default}" + }, + { + "name": "CpuRAM", + "includePath": [ + "d:\\Project\\MFT\\Motor\\Libraries\\CMSIS\\Device\\ST\\STM32F10x\\Include", + "d:\\Project\\MFT\\Motor\\Libraries\\STM32F10x_StdPeriph_Driver\\inc", + "d:\\Project\\MFT\\Motor\\Libraries\\STM32_USB-FS-Device_Driver\\inc", + "d:\\Project\\MFT\\Motor\\Libraries\\CMSIS\\Include", + "d:\\Project\\MFT\\Motor\\User\\bsp", + "d:\\Project\\MFT\\Motor\\User\\bsp\\inc", + "d:\\Project\\MFT\\Motor\\User\\app\\inc", + "d:\\Project\\MFT\\Motor\\User\\fonts", + "d:\\Project\\MFT\\Motor\\User\\images", + "d:\\Project\\MFT\\Motor\\User\\uIP\\uip", + "d:\\Project\\MFT\\Motor\\User\\uIP\\http", + "d:\\Project\\MFT\\Motor\\User\\uIP\\dm9000", + "d:\\Project\\MFT\\Motor\\User\\FatFS\\src", + "d:\\Project\\MFT\\Motor\\User\\usb_mass", + "d:\\Project\\MFT\\Motor\\User\\CH376\\inc", + "C:\\Keil_v5\\ARM\\ARMCC\\include", + "C:\\Keil_v5\\ARM\\ARMCC\\include\\rw", + "d:\\Project\\MFT\\Motor\\User\\app\\src", + "d:\\Project\\MFT\\Motor\\User\\bsp\\src", + "d:\\Project\\MFT\\Motor\\Libraries\\CMSIS\\Device\\ST\\STM32F10x\\Source\\Templates\\arm", + "d:\\Project\\MFT\\Motor\\Libraries\\STM32F10x_StdPeriph_Driver\\src", + "d:\\Project\\MFT\\Motor\\Doc" + ], + "defines": [ + "USE_STDPERIPH_DRIVER", + "STM32F10X_HD", + "VECT_TAB_SRAM", + "__CC_ARM", + "__arm__", + "__align(x)=", + "__ALIGNOF__(x)=", + "__alignof__(x)=", + "__asm(x)=", + "__forceinline=", + "__restrict=", + "__global_reg(n)=", + "__inline=", + "__int64=long long", + "__INTADDR__(expr)=0", + "__irq=", + "__packed=", + "__pure=", + "__smc(n)=", + "__svc(n)=", + "__svc_indirect(n)=", + "__svc_indirect_r7(n)=", + "__value_in_regs=", + "__weak=", + "__writeonly=", + "__declspec(x)=", + "__attribute__(x)=", + "__nonnull__(x)=", + "__register=", + "__breakpoint(x)=", + "__cdp(x,y,z)=", + "__clrex()=", + "__clz(x)=0U", + "__current_pc()=0U", + "__current_sp()=0U", + "__disable_fiq()=", + "__disable_irq()=", + "__dmb(x)=", + "__dsb(x)=", + "__enable_fiq()=", + "__enable_irq()=", + "__fabs(x)=0.0", + "__fabsf(x)=0.0f", + "__force_loads()=", + "__force_stores()=", + "__isb(x)=", + "__ldrex(x)=0U", + "__ldrexd(x)=0U", + "__ldrt(x)=0U", + "__memory_changed()=", + "__nop()=", + "__pld(...)=", + "__pli(...)=", + "__qadd(x,y)=0", + "__qdbl(x)=0", + "__qsub(x,y)=0", + "__rbit(x)=0U", + "__rev(x)=0U", + "__return_address()=0U", + "__ror(x,y)=0U", + "__schedule_barrier()=", + "__semihost(x,y)=0", + "__sev()=", + "__sqrt(x)=0.0", + "__sqrtf(x)=0.0f", + "__ssat(x,y)=0", + "__strex(x,y)=0U", + "__strexd(x,y)=0", + "__strt(x,y)=", + "__swp(x,y)=0U", + "__usat(x,y)=0U", + "__wfe()=", + "__wfi()=", + "__yield()=", + "__vfp_status(x,y)=0" + ], + "intelliSenseMode": "${default}" + } + ], + "version": 4 +} \ No newline at end of file diff --git a/Project/MDK-ARM/.vscode/keil-assistant.log b/Project/MDK-ARM/.vscode/keil-assistant.log new file mode 100644 index 0000000..c7632b2 --- /dev/null +++ b/Project/MDK-ARM/.vscode/keil-assistant.log @@ -0,0 +1,18 @@ +[info] Log at : 2025/7/17|16:20:31|GMT+0800 + +[info] Log at : 2025/7/17|16:20:38|GMT+0800 + +[info] Log at : 2025/7/17|16:31:17|GMT+0800 + +[info] Log at : 2025/7/17|16:32:14|GMT+0800 + +[info] Log at : 2025/7/17|16:32:17|GMT+0800 + +[info] Log at : 2026/4/15|18:36:04|GMT+0800 + +[info] Log at : 2026/4/15|18:36:07|GMT+0800 + +[info] Log at : 2026/4/16|09:06:52|GMT+0800 + +[info] Log at : 2026/4/16|16:26:04|GMT+0800 + diff --git a/Project/MDK-ARM/.vscode/settings.json b/Project/MDK-ARM/.vscode/settings.json new file mode 100644 index 0000000..069281d --- /dev/null +++ b/Project/MDK-ARM/.vscode/settings.json @@ -0,0 +1,9 @@ +{ + "files.associations": { + "*.bin": "plaintext", + "bsp.h": "c", + "string.h": "c", + "math.h": "c", + "stdint.h": "c" + } +} \ No newline at end of file diff --git a/Project/MDK-ARM/.vscode/uv4.log b/Project/MDK-ARM/.vscode/uv4.log new file mode 100644 index 0000000..d892970 --- /dev/null +++ b/Project/MDK-ARM/.vscode/uv4.log @@ -0,0 +1,3 @@ +Load "d:\\Project\\MFT\\Motor\\Project\\MDK-ARM\\Flash\\Obj\\output.axf" +Erase Done.Programming Done.Verify OK.Application running ... +Flash Load finished at 16:27:27 diff --git a/Project/MDK-ARM/.vscode/uv4.log.lock b/Project/MDK-ARM/.vscode/uv4.log.lock new file mode 100644 index 0000000..1a026df --- /dev/null +++ b/Project/MDK-ARM/.vscode/uv4.log.lock @@ -0,0 +1 @@ +2026/4/16 16:27:27 \ No newline at end of file diff --git a/Project/MDK-ARM/CpuRAM.ini b/Project/MDK-ARM/CpuRAM.ini new file mode 100644 index 0000000..f457b7a --- /dev/null +++ b/Project/MDK-ARM/CpuRAM.ini @@ -0,0 +1,31 @@ +/* +********************************************************************************************************* + ڰSTM32F103ZE-EKϵͨ + QQ: 1295744630, armfly, Email: armfly@qq.com + + ļ CpuRAM.ini + + CPUڲRAMԽűʼLoadʱIDEƷִνű + + űɵĹ + (1) װĿCPUڲRAM + (2) öջָSP + (3) ޸PCָ + + ű﷨ + μMDKHELP, ؼ uv3 Library Routines Կuv3ֵ֧Ľű + + Copyright (C), 2013-2014, www.armfly.com + +********************************************************************************************************* +*/ + +FUNC void Setup (void) { + SP = _RDWORD(0x20000000); // öջָ + PC = _RDWORD(0x20000004); // PCָ + _WDWORD(0xE000ED08, 0x20000000); // жַ +} + +LOAD CpuRAM\obj\output.axf INCREMENTAL // װش뵽CPUڲRAM (ѡоͲҪѡLoad Application ar Startup) +Setup(); // ٵSetup޸ĶջPCָ(ΪSPֵҪĿжȡ) +g, main // еmain() diff --git a/Project/MDK-ARM/EventRecorderStub.scvd b/Project/MDK-ARM/EventRecorderStub.scvd new file mode 100644 index 0000000..2956b29 --- /dev/null +++ b/Project/MDK-ARM/EventRecorderStub.scvd @@ -0,0 +1,9 @@ + + + + + + + + + diff --git a/Project/MDK-ARM/Flash/List/bsp.txt b/Project/MDK-ARM/Flash/List/bsp.txt new file mode 100644 index 0000000..87c1ab0 --- /dev/null +++ b/Project/MDK-ARM/Flash/List/bsp.txt @@ -0,0 +1,149 @@ +; generated by Component: ARM Compiler 5.06 update 7 (build 960) Tool: ArmCC [4d365d] +; commandline ArmCC [--list --split_sections --debug -c --asm --interleave -o.\flash\obj\bsp.o --asm_dir=.\Flash\List\ --list_dir=.\Flash\List\ --depend=.\flash\obj\bsp.d --cpu=Cortex-M3 --apcs=interwork -O0 --diag_suppress=9931,870 -I..\..\Libraries\CMSIS\Device\ST\STM32F10x\Include -I..\..\Libraries\STM32F10x_StdPeriph_Driver\inc -I..\..\Libraries\STM32_USB-FS-Device_Driver\inc -I..\..\Libraries\CMSIS\Include -I..\..\User\bsp -I..\..\User\bsp\inc -I..\..\User\app\inc -I..\..\User -IC:\Users\w1619\AppData\Local\Arm\Packs\Keil\STM32F1xx_DFP\2.4.1\Device\Include -D__MICROLIB -D__UVISION_VERSION=538 -DSTM32F10X_HD -DUSE_STDPERIPH_DRIVER -DSTM32F10X_HD --omf_browse=.\flash\obj\bsp.crf ..\..\User\bsp\bsp.c] + THUMB + + AREA ||i.bsp_Idle||, CODE, READONLY, ALIGN=1 + + bsp_Idle PROC +;;;104 */ +;;;105 void bsp_Idle(void) +000000 4770 BX lr +;;;106 { +;;;107 /* --- 喂狗 */ +;;;108 +;;;109 /* --- 让CPU进入休眠，由Systick定时中断唤醒或者其他中断唤醒 */ +;;;110 +;;;111 /* 例如 emWin 图形库，可以插入图形库需要的轮询函数 */ +;;;112 // GUI_Exec(); +;;;113 +;;;114 /* 例如 uIP 协议，可以插入uip轮询函数 */ +;;;115 } +;;;116 + ENDP + + + AREA ||i.bsp_Init||, CODE, READONLY, ALIGN=2 + + bsp_Init PROC +;;;32 */ +;;;33 void bsp_Init(void) +000000 b510 PUSH {r4,lr} +;;;34 { +;;;35 /* +;;;36 由于ST固件库的启动文件已经执行了CPU系统时钟的初始化，所以不必再次重复配置系统时钟。 +;;;37 启动文件配置了CPU主时钟频率、内部Flash访问速度和可选的外部SRAM FSMC初始化。 +;;;38 +;;;39 系统时钟缺省配置为72MHz，如果需要更改，可以修改 system_stm32f103.c 文件 +;;;40 */ +;;;41 +;;;42 /* 优先级分组设置为4 */ +;;;43 NVIC_PriorityGroupConfig(NVIC_PriorityGroup_4); +000002 f44f7040 MOV r0,#0x300 +000006 f7fffffe BL NVIC_PriorityGroupConfig +;;;44 +;;;45 bsp_InitKey(); /* 初始化按键 */ +00000a f7fffffe BL bsp_InitKey +;;;46 +;;;47 bsp_InitTimer(); /* 初始化系统滴答定时器 (此函数会开中断) */ +00000e f7fffffe BL bsp_InitTimer +;;;48 +;;;49 /* 初始化串口驱动 */ +;;;50 USART_Config(); +000012 f7fffffe BL USART_Config +;;;51 /* 配置使用DMA模式 */ +;;;52 USARTx_DMA_Config(); +000016 f7fffffe BL USARTx_DMA_Config +;;;53 USART_DMACmd(DEBUG_USARTx, USART_DMAReq_Rx, ENABLE); +00001a 2201 MOVS r2,#1 +00001c 2140 MOVS r1,#0x40 +00001e 4807 LDR r0,|L2.60| +000020 f7fffffe BL USART_DMACmd +;;;54 +;;;55 BEEP_InitHard(); /* 配置蜂鸣器GPIO */ +000024 f7fffffe BL BEEP_InitHard +;;;56 +;;;57 bsp_InitI2C(); /* 配置I2C总线 */ +000028 f7fffffe BL bsp_InitI2C +;;;58 bsp_InitDigitalTube(); // 初始化数码管控制端口 +00002c f7fffffe BL bsp_InitDigitalTube +;;;59 +;;;60 bsp_Init_Drv8880_Hard(); +000030 f7fffffe BL bsp_Init_Drv8880_Hard +;;;61 bsp_InitStepMoto(); +000034 f7fffffe BL bsp_InitStepMoto +;;;62 } +000038 bd10 POP {r4,pc} +;;;63 + ENDP + +00003a 0000 DCW 0x0000 + |L2.60| + DCD 0x40013800 + + AREA ||i.bsp_RunPer10ms||, CODE, READONLY, ALIGN=1 + + bsp_RunPer10ms PROC +;;;72 */ +;;;73 void bsp_RunPer10ms(void) +000000 b510 PUSH {r4,lr} +;;;74 { +;;;75 bsp_KeyScan(); /* 每10ms扫描按键一次 */ +000002 f7fffffe BL bsp_KeyScan +;;;76 +;;;77 BEEP_Pro(); /* 蜂鸣器定时处理 */ +000006 f7fffffe BL BEEP_Pro +;;;78 +;;;79 // bsp_FpgaPowerMainLoop(30); // 给FPAGA延迟供电，延迟时间位30*10ms +;;;80 } +00000a bd10 POP {r4,pc} +;;;81 + ENDP + + + AREA ||i.bsp_RunPer1ms||, CODE, READONLY, ALIGN=1 + + bsp_RunPer1ms PROC +;;;90 */ +;;;91 void bsp_RunPer1ms(void) +000000 b510 PUSH {r4,lr} +;;;92 { +;;;93 bsp_DigitalTubeMainLoop(); +000002 f7fffffe BL bsp_DigitalTubeMainLoop +;;;94 } +000006 bd10 POP {r4,pc} +;;;95 + ENDP + + + AREA ||.data||, DATA, ALIGN=2 + + RxCount + DCD 0x00000000 + TxCount + DCD 0x00000000 + +;*** Start embedded assembler *** + +#line 1 "..\\..\\User\\bsp\\bsp.c" + AREA ||.rev16_text||, CODE + THUMB + EXPORT |__asm___5_bsp_c_RxCount____REV16| +#line 114 "..\\..\\Libraries\\CMSIS\\Include\\core_cmInstr.h" +|__asm___5_bsp_c_RxCount____REV16| PROC +#line 115 + + rev16 r0, r0 + bx lr + ENDP + AREA ||.revsh_text||, CODE + THUMB + EXPORT |__asm___5_bsp_c_RxCount____REVSH| +#line 128 +|__asm___5_bsp_c_RxCount____REVSH| PROC +#line 129 + + revsh r0, r0 + bx lr + ENDP + +;*** End embedded assembler *** diff --git a/Project/MDK-ARM/Flash/List/bsp_adc.txt b/Project/MDK-ARM/Flash/List/bsp_adc.txt new file mode 100644 index 0000000..e69de29 diff --git a/Project/MDK-ARM/Flash/List/bsp_beep.txt b/Project/MDK-ARM/Flash/List/bsp_beep.txt new file mode 100644 index 0000000..953dfbd --- /dev/null +++ b/Project/MDK-ARM/Flash/List/bsp_beep.txt @@ -0,0 +1,323 @@ +; generated by Component: ARM Compiler 5.06 update 7 (build 960) Tool: ArmCC [4d365d] +; commandline ArmCC [--list --split_sections --debug -c --asm --interleave -o.\flash\obj\bsp_beep.o --asm_dir=.\Flash\List\ --list_dir=.\Flash\List\ --depend=.\flash\obj\bsp_beep.d --cpu=Cortex-M3 --apcs=interwork -O0 --diag_suppress=9931,870 -I..\..\Libraries\CMSIS\Device\ST\STM32F10x\Include -I..\..\Libraries\STM32F10x_StdPeriph_Driver\inc -I..\..\Libraries\STM32_USB-FS-Device_Driver\inc -I..\..\Libraries\CMSIS\Include -I..\..\User\bsp -I..\..\User\bsp\inc -I..\..\User\app\inc -I..\..\User -IC:\Users\w1619\AppData\Local\Arm\Packs\Keil\STM32F1xx_DFP\2.4.1\Device\Include -D__MICROLIB -D__UVISION_VERSION=538 -DSTM32F10X_HD -DUSE_STDPERIPH_DRIVER -DSTM32F10X_HD --omf_browse=.\flash\obj\bsp_beep.crf ..\..\User\bsp\src\bsp_beep.c] + THUMB + + AREA ||i.BEEP_InitHard||, CODE, READONLY, ALIGN=2 + + BEEP_InitHard PROC +;;;51 */ +;;;52 void BEEP_InitHard(void) +000000 b508 PUSH {r3,lr} +;;;53 { +;;;54 #ifdef BEEP_HAVE_POWER /* 有源蜂鸣器 */ +;;;55 GPIO_InitTypeDef GPIO_InitStructure; +;;;56 +;;;57 /* 打开GPIO的时钟 */ +;;;58 RCC_APB2PeriphClockCmd(GPIO_RCC_BEEP, ENABLE); +000002 2101 MOVS r1,#1 +000004 2008 MOVS r0,#8 +000006 f7fffffe BL RCC_APB2PeriphClockCmd +;;;59 +;;;60 BEEP_DISABLE(); +00000a f44f7080 MOV r0,#0x100 +00000e 4908 LDR r1,|L1.48| +000010 6008 STR r0,[r1,#0] +;;;61 +;;;62 GPIO_InitStructure.GPIO_Speed = GPIO_Speed_50MHz; +000012 2003 MOVS r0,#3 +000014 f88d0002 STRB r0,[sp,#2] +;;;63 GPIO_InitStructure.GPIO_Mode = GPIO_Mode_Out_PP; /* 推挽输出模式 */ +000018 2010 MOVS r0,#0x10 +00001a f88d0003 STRB r0,[sp,#3] +;;;64 GPIO_InitStructure.GPIO_Pin = GPIO_PIN_BEEP; +00001e 0100 LSLS r0,r0,#4 +000020 f8ad0000 STRH r0,[sp,#0] +;;;65 GPIO_Init(GPIO_PORT_BEEP, &GPIO_InitStructure); +000024 4669 MOV r1,sp +000026 4802 LDR r0,|L1.48| +000028 3814 SUBS r0,r0,#0x14 +00002a f7fffffe BL GPIO_Init +;;;66 #else +;;;67 ; /* 无源蜂鸣器 */ +;;;68 +;;;69 #endif +;;;70 } +00002e bd08 POP {r3,pc} +;;;71 + ENDP + + |L1.48| + DCD 0x40010c14 + + AREA ||i.BEEP_KeyTone||, CODE, READONLY, ALIGN=1 + + BEEP_KeyTone PROC +;;;124 */ +;;;125 void BEEP_KeyTone(void) +000000 b500 PUSH {lr} +;;;126 { +;;;127 BEEP_Start(4300, 4, 1, 1); +000002 2301 MOVS r3,#1 +000004 461a MOV r2,r3 +000006 2104 MOVS r1,#4 +000008 f24100cc MOV r0,#0x10cc +00000c f7fffffe BL BEEP_Start +;;;128 } +000010 bd00 POP {pc} +;;;129 + ENDP + + + AREA ||i.BEEP_Pro||, CODE, READONLY, ALIGN=2 + + BEEP_Pro PROC +;;;137 */ +;;;138 void BEEP_Pro(void) +000000 4827 LDR r0,|L3.160| +;;;139 { +;;;140 if ((g_tBeep.ucEnalbe == 0) || (g_tBeep.usStopTime == 0)) +000002 7800 LDRB r0,[r0,#0] ; g_tBeep +000004 b110 CBZ r0,|L3.12| +000006 4826 LDR r0,|L3.160| +000008 8880 LDRH r0,[r0,#4] ; g_tBeep +00000a b900 CBNZ r0,|L3.14| + |L3.12| +;;;141 { +;;;142 return; +;;;143 } +;;;144 +;;;145 if (g_tBeep.ucState == 0) +;;;146 { +;;;147 if (g_tBeep.usStopTime > 0) /* 间断发声 */ +;;;148 { +;;;149 if (++g_tBeep.usCount >= g_tBeep.usBeepTime) +;;;150 { +;;;151 BEEP_DISABLE(); /* 停止发声 */ +;;;152 g_tBeep.usCount = 0; +;;;153 g_tBeep.ucState = 1; +;;;154 } +;;;155 } +;;;156 else +;;;157 { +;;;158 ; /* 不做任何处理，连续发声 */ +;;;159 } +;;;160 } +;;;161 else if (g_tBeep.ucState == 1) +;;;162 { +;;;163 if (++g_tBeep.usCount >= g_tBeep.usStopTime) +;;;164 { +;;;165 /* 连续发声时，直到调用stop停止为止 */ +;;;166 if (g_tBeep.usCycle > 0) +;;;167 { +;;;168 if (++g_tBeep.usCycleCount >= g_tBeep.usCycle) +;;;169 { +;;;170 /* 循环次数到，停止发声 */ +;;;171 g_tBeep.ucEnalbe = 0; +;;;172 } +;;;173 +;;;174 if (g_tBeep.ucEnalbe == 0) +;;;175 { +;;;176 g_tBeep.usStopTime = 0; +;;;177 return; +;;;178 } +;;;179 } +;;;180 +;;;181 g_tBeep.usCount = 0; +;;;182 g_tBeep.ucState = 0; +;;;183 +;;;184 BEEP_ENABLE(); /* 开始发声 */ +;;;185 } +;;;186 } +;;;187 } +00000c 4770 BX lr + |L3.14| +00000e 4824 LDR r0,|L3.160| +000010 7840 LDRB r0,[r0,#1] ;145 ; g_tBeep +000012 b9b0 CBNZ r0,|L3.66| +000014 4822 LDR r0,|L3.160| +000016 8880 LDRH r0,[r0,#4] ;147 ; g_tBeep +000018 2800 CMP r0,#0 ;147 +00001a dd3f BLE |L3.156| +00001c 4820 LDR r0,|L3.160| +00001e 8900 LDRH r0,[r0,#8] ;149 ; g_tBeep +000020 1c40 ADDS r0,r0,#1 ;149 +000022 b280 UXTH r0,r0 ;149 +000024 491e LDR r1,|L3.160| +000026 8108 STRH r0,[r1,#8] ;149 +000028 8849 LDRH r1,[r1,#2] ;149 ; g_tBeep +00002a 4288 CMP r0,r1 ;149 +00002c db36 BLT |L3.156| +00002e f44f7080 MOV r0,#0x100 ;151 +000032 491c LDR r1,|L3.164| +000034 6008 STR r0,[r1,#0] ;151 +000036 2000 MOVS r0,#0 ;152 +000038 4919 LDR r1,|L3.160| +00003a 8108 STRH r0,[r1,#8] ;152 +00003c 2001 MOVS r0,#1 ;153 +00003e 7048 STRB r0,[r1,#1] ;153 +000040 e02c B |L3.156| + |L3.66| +000042 4817 LDR r0,|L3.160| +000044 7840 LDRB r0,[r0,#1] ;161 ; g_tBeep +000046 2801 CMP r0,#1 ;161 +000048 d128 BNE |L3.156| +00004a 4815 LDR r0,|L3.160| +00004c 8900 LDRH r0,[r0,#8] ;163 ; g_tBeep +00004e 1c40 ADDS r0,r0,#1 ;163 +000050 b280 UXTH r0,r0 ;163 +000052 4913 LDR r1,|L3.160| +000054 8108 STRH r0,[r1,#8] ;163 +000056 8889 LDRH r1,[r1,#4] ;163 ; g_tBeep +000058 4288 CMP r0,r1 ;163 +00005a db1f BLT |L3.156| +00005c 4810 LDR r0,|L3.160| +00005e 88c0 LDRH r0,[r0,#6] ;166 ; g_tBeep +000060 2800 CMP r0,#0 ;166 +000062 dd12 BLE |L3.138| +000064 480e LDR r0,|L3.160| +000066 8940 LDRH r0,[r0,#0xa] ;168 ; g_tBeep +000068 1c40 ADDS r0,r0,#1 ;168 +00006a b280 UXTH r0,r0 ;168 +00006c 490c LDR r1,|L3.160| +00006e 8148 STRH r0,[r1,#0xa] ;168 +000070 88c9 LDRH r1,[r1,#6] ;168 ; g_tBeep +000072 4288 CMP r0,r1 ;168 +000074 db02 BLT |L3.124| +000076 2000 MOVS r0,#0 ;171 +000078 4909 LDR r1,|L3.160| +00007a 7008 STRB r0,[r1,#0] ;171 + |L3.124| +00007c 4808 LDR r0,|L3.160| +00007e 7800 LDRB r0,[r0,#0] ;174 ; g_tBeep +000080 b918 CBNZ r0,|L3.138| +000082 2000 MOVS r0,#0 ;176 +000084 4906 LDR r1,|L3.160| +000086 8088 STRH r0,[r1,#4] ;176 +000088 e7c0 B |L3.12| + |L3.138| +00008a 2000 MOVS r0,#0 ;181 +00008c 4904 LDR r1,|L3.160| +00008e 8108 STRH r0,[r1,#8] ;181 +000090 7048 STRB r0,[r1,#1] ;182 +000092 f44f7080 MOV r0,#0x100 ;184 +000096 4903 LDR r1,|L3.164| +000098 1f09 SUBS r1,r1,#4 ;184 +00009a 6008 STR r0,[r1,#0] ;184 + |L3.156| +00009c bf00 NOP +00009e e7b5 B |L3.12| +;;;188 + ENDP + + |L3.160| + DCD g_tBeep + |L3.164| + DCD 0x40010c14 + + AREA ||i.BEEP_Start||, CODE, READONLY, ALIGN=2 + + BEEP_Start PROC +;;;82 */ +;;;83 void BEEP_Start(uint32_t _uiFreq, uint16_t _usBeepTime, uint16_t _usStopTime, uint16_t _usCycle) +000000 b530 PUSH {r4,r5,lr} +;;;84 { +;;;85 if (_usBeepTime == 0) +000002 b901 CBNZ r1,|L4.6| + |L4.4| +;;;86 { +;;;87 return; +;;;88 } +;;;89 +;;;90 g_tBeep.uiFreq = _uiFreq; +;;;91 g_tBeep.usBeepTime = _usBeepTime; +;;;92 g_tBeep.usStopTime = _usStopTime; +;;;93 g_tBeep.usCycle = _usCycle; +;;;94 g_tBeep.usCount = 0; +;;;95 g_tBeep.usCycleCount = 0; +;;;96 g_tBeep.ucState = 0; +;;;97 g_tBeep.ucEnalbe = 1; /* 设置完全局参数后再使能发声标志 */ +;;;98 +;;;99 BEEP_ENABLE(); /* 开始发声 */ +;;;100 } +000004 bd30 POP {r4,r5,pc} + |L4.6| +000006 4c08 LDR r4,|L4.40| +000008 60e0 STR r0,[r4,#0xc] ;90 ; g_tBeep +00000a 8061 STRH r1,[r4,#2] ;91 +00000c 80a2 STRH r2,[r4,#4] ;92 +00000e 80e3 STRH r3,[r4,#6] ;93 +000010 2400 MOVS r4,#0 ;94 +000012 4d05 LDR r5,|L4.40| +000014 812c STRH r4,[r5,#8] ;94 +000016 816c STRH r4,[r5,#0xa] ;95 +000018 706c STRB r4,[r5,#1] ;96 +00001a 2401 MOVS r4,#1 ;97 +00001c 702c STRB r4,[r5,#0] ;97 +00001e 0224 LSLS r4,r4,#8 ;99 +000020 4d02 LDR r5,|L4.44| +000022 602c STR r4,[r5,#0] ;99 +000024 bf00 NOP +000026 e7ed B |L4.4| +;;;101 + ENDP + + |L4.40| + DCD g_tBeep + |L4.44| + DCD 0x40010c10 + + AREA ||i.BEEP_Stop||, CODE, READONLY, ALIGN=2 + + BEEP_Stop PROC +;;;109 */ +;;;110 void BEEP_Stop(void) +000000 2000 MOVS r0,#0 +;;;111 { +;;;112 g_tBeep.ucEnalbe = 0; +000002 4903 LDR r1,|L5.16| +000004 7008 STRB r0,[r1,#0] +;;;113 +;;;114 BEEP_DISABLE(); /* 必须在清控制标志后再停止发声，避免停止后在中断中又开启 */ +000006 f44f7080 MOV r0,#0x100 +00000a 4902 LDR r1,|L5.20| +00000c 6008 STR r0,[r1,#0] +;;;115 } +00000e 4770 BX lr +;;;116 + ENDP + + |L5.16| + DCD g_tBeep + |L5.20| + DCD 0x40010c14 + + AREA ||.bss||, DATA, NOINIT, ALIGN=2 + + g_tBeep + % 16 + +;*** Start embedded assembler *** + +#line 1 "..\\..\\User\\bsp\\src\\bsp_beep.c" + AREA ||.rev16_text||, CODE + THUMB + EXPORT |__asm___10_bsp_beep_c_471486d3____REV16| +#line 114 "..\\..\\Libraries\\CMSIS\\Include\\core_cmInstr.h" +|__asm___10_bsp_beep_c_471486d3____REV16| PROC +#line 115 + + rev16 r0, r0 + bx lr + ENDP + AREA ||.revsh_text||, CODE + THUMB + EXPORT |__asm___10_bsp_beep_c_471486d3____REVSH| +#line 128 +|__asm___10_bsp_beep_c_471486d3____REVSH| PROC +#line 129 + + revsh r0, r0 + bx lr + ENDP + +;*** End embedded assembler *** diff --git a/Project/MDK-ARM/Flash/List/bsp_channel_realy.txt b/Project/MDK-ARM/Flash/List/bsp_channel_realy.txt new file mode 100644 index 0000000..a55cab9 --- /dev/null +++ b/Project/MDK-ARM/Flash/List/bsp_channel_realy.txt @@ -0,0 +1,238 @@ +; generated by Component: ARM Compiler 5.05 update 1 (build 106) Tool: ArmCC [4d0efa] +; commandline ArmCC [--list --split_sections --debug -c --asm --interleave -o.\flash\obj\bsp_channel_realy.o --asm_dir=.\Flash\List\ --list_dir=.\Flash\List\ --depend=.\flash\obj\bsp_channel_realy.d --cpu=Cortex-M3 --apcs=interwork -O0 --diag_suppress=9931,870 -I..\..\Libraries\CMSIS\Device\ST\STM32F10x\Include -I..\..\Libraries\STM32F10x_StdPeriph_Driver\inc -I..\..\Libraries\STM32_USB-FS-Device_Driver\inc -I..\..\Libraries\CMSIS\Include -I..\..\User\bsp -I..\..\User\bsp\inc -I..\..\User\app\inc -IC:\Keil_v5\ARM\RV31\INC -IC:\Keil_v5\ARM\CMSIS\Include -IC:\Keil_v5\ARM\Inc\ST\STM32F10x -D__MICROLIB -D__UVISION_VERSION=514 -DUSE_STDPERIPH_DRIVER -DSTM32F10X_HD --omf_browse=.\flash\obj\bsp_channel_realy.crf ..\..\User\bsp\src\bsp_channel_realy.c] + THUMB + + AREA ||i.bsp_InitChannelRelay||, CODE, READONLY, ALIGN=2 + + bsp_InitChannelRelay PROC +;;;39 +;;;40 void bsp_InitChannelRelay(void) +000000 b508 PUSH {r3,lr} +;;;41 { +;;;42 GPIO_InitTypeDef GPIO_InitStructure; +;;;43 +;;;44 // GPIOʱ +;;;45 RCC_APB2PeriphClockCmd(RCC_ALL_RELAY, ENABLE); +000002 2101 MOVS r1,#1 +000004 2048 MOVS r0,#0x48 +000006 f7fffffe BL RCC_APB2PeriphClockCmd +;;;46 +;;;47 GPIO_InitStructure.GPIO_Speed = GPIO_Speed_50MHz; +00000a 2003 MOVS r0,#3 +00000c f88d0002 STRB r0,[sp,#2] +;;;48 GPIO_InitStructure.GPIO_Mode = GPIO_Mode_Out_PP; /* ģʽ */ +000010 2010 MOVS r0,#0x10 +000012 f88d0003 STRB r0,[sp,#3] +;;;49 +;;;50 GPIO_InitStructure.GPIO_Pin = GPIO_PIN_RELAY1; +000016 2008 MOVS r0,#8 +000018 f8ad0000 STRH r0,[sp,#0] +;;;51 GPIO_Init(GPIO_PORT_RELAY1, &GPIO_InitStructure); +00001c 4669 MOV r1,sp +00001e 4814 LDR r0,|L1.112| +000020 f7fffffe BL GPIO_Init +;;;52 +;;;53 GPIO_InitStructure.GPIO_Pin = GPIO_PIN_RELAY2; +000024 f44f7080 MOV r0,#0x100 +000028 f8ad0000 STRH r0,[sp,#0] +;;;54 GPIO_Init(GPIO_PORT_RELAY2, &GPIO_InitStructure); +00002c 4669 MOV r1,sp +00002e 4811 LDR r0,|L1.116| +000030 f7fffffe BL GPIO_Init +;;;55 +;;;56 GPIO_InitStructure.GPIO_Pin = GPIO_PIN_RELAY3; +000034 2004 MOVS r0,#4 +000036 f8ad0000 STRH r0,[sp,#0] +;;;57 GPIO_Init(GPIO_PORT_RELAY3, &GPIO_InitStructure); +00003a 4669 MOV r1,sp +00003c 480c LDR r0,|L1.112| +00003e f7fffffe BL GPIO_Init +;;;58 +;;;59 GPIO_InitStructure.GPIO_Pin = GPIO_PIN_RELAY4; +000042 f44f7000 MOV r0,#0x200 +000046 f8ad0000 STRH r0,[sp,#0] +;;;60 GPIO_Init(GPIO_PORT_RELAY4, &GPIO_InitStructure); +00004a 4669 MOV r1,sp +00004c 4809 LDR r0,|L1.116| +00004e f7fffffe BL GPIO_Init +;;;61 +;;;62 GPIO_InitStructure.GPIO_Pin = GPIO_PIN_RELAY5; +000052 2002 MOVS r0,#2 +000054 f8ad0000 STRH r0,[sp,#0] +;;;63 GPIO_Init(GPIO_PORT_RELAY5, &GPIO_InitStructure); +000058 4669 MOV r1,sp +00005a 4805 LDR r0,|L1.112| +00005c f7fffffe BL GPIO_Init +;;;64 +;;;65 GPIO_InitStructure.GPIO_Pin = GPIO_PIN_RELAY6; +000060 2001 MOVS r0,#1 +000062 f8ad0000 STRH r0,[sp,#0] +;;;66 GPIO_Init(GPIO_PORT_RELAY6, &GPIO_InitStructure); +000066 4669 MOV r1,sp +000068 4801 LDR r0,|L1.112| +00006a f7fffffe BL GPIO_Init +;;;67 +;;;68 } +00006e bd08 POP {r3,pc} +;;;69 + ENDP + + |L1.112| + DCD 0x40011800 + |L1.116| + DCD 0x40010c00 + + AREA ||i.bsp_RealyAllOff||, CODE, READONLY, ALIGN=2 + + bsp_RealyAllOff PROC +;;;69 +;;;70 void bsp_RealyAllOff(void) +000000 2008 MOVS r0,#8 +;;;71 { +;;;72 GPIO_PORT_RELAY1->BRR = GPIO_PIN_RELAY1; +000002 4908 LDR r1,|L2.36| +000004 6008 STR r0,[r1,#0] +;;;73 GPIO_PORT_RELAY2->BRR = GPIO_PIN_RELAY2; +000006 0140 LSLS r0,r0,#5 +000008 4907 LDR r1,|L2.40| +00000a 6008 STR r0,[r1,#0] +;;;74 GPIO_PORT_RELAY3->BRR = GPIO_PIN_RELAY3; +00000c 2004 MOVS r0,#4 +00000e 4905 LDR r1,|L2.36| +000010 6008 STR r0,[r1,#0] +;;;75 GPIO_PORT_RELAY4->BRR = GPIO_PIN_RELAY4; +000012 01c0 LSLS r0,r0,#7 +000014 4904 LDR r1,|L2.40| +000016 6008 STR r0,[r1,#0] +;;;76 GPIO_PORT_RELAY5->BRR = GPIO_PIN_RELAY5; +000018 2002 MOVS r0,#2 +00001a 4902 LDR r1,|L2.36| +00001c 6008 STR r0,[r1,#0] +;;;77 GPIO_PORT_RELAY6->BRR = GPIO_PIN_RELAY6; +00001e 2001 MOVS r0,#1 +000020 6008 STR r0,[r1,#0] +;;;78 } +000022 4770 BX lr +;;;79 + ENDP + + |L2.36| + DCD 0x40011814 + |L2.40| + DCD 0x40010c14 + + AREA ||i.bsp_RelayOn||, CODE, READONLY, ALIGN=2 + + bsp_RelayOn PROC +;;;85 //------------------------------------------------------------------------------ +;;;86 void bsp_RelayOn(uint8_t _ch) +000000 2108 MOVS r1,#8 +;;;87 { +;;;88 GPIO_PORT_RELAY1->BRR = GPIO_PIN_RELAY1; +000002 4a1d LDR r2,|L3.120| +000004 6011 STR r1,[r2,#0] +;;;89 GPIO_PORT_RELAY2->BRR = GPIO_PIN_RELAY2; +000006 0149 LSLS r1,r1,#5 +000008 4a1c LDR r2,|L3.124| +00000a 6011 STR r1,[r2,#0] +;;;90 GPIO_PORT_RELAY3->BRR = GPIO_PIN_RELAY3; +00000c 2104 MOVS r1,#4 +00000e 4a1a LDR r2,|L3.120| +000010 6011 STR r1,[r2,#0] +;;;91 GPIO_PORT_RELAY4->BRR = GPIO_PIN_RELAY4; +000012 01c9 LSLS r1,r1,#7 +000014 4a19 LDR r2,|L3.124| +000016 6011 STR r1,[r2,#0] +;;;92 GPIO_PORT_RELAY5->BRR = GPIO_PIN_RELAY5; +000018 2102 MOVS r1,#2 +00001a 4a17 LDR r2,|L3.120| +00001c 6011 STR r1,[r2,#0] +;;;93 GPIO_PORT_RELAY6->BRR = GPIO_PIN_RELAY6; +00001e 2101 MOVS r1,#1 +000020 6011 STR r1,[r2,#0] +;;;94 +;;;95 switch(_ch) +000022 2807 CMP r0,#7 +000024 d225 BCS |L3.114| +000026 e8dff000 TBB [pc,r0] +00002a 2404 DCB 0x24,0x04 +00002c 090f141a DCB 0x09,0x0f,0x14,0x1a +000030 1f00 DCB 0x1f,0x00 +;;;96 { +;;;97 case 1: GPIO_PORT_RELAY1->BSRR = GPIO_PIN_RELAY1; break; +000032 2108 MOVS r1,#8 +000034 4a10 LDR r2,|L3.120| +000036 1f12 SUBS r2,r2,#4 +000038 6011 STR r1,[r2,#0] +00003a e01b B |L3.116| +;;;98 case 2: GPIO_PORT_RELAY2->BSRR = GPIO_PIN_RELAY2; break; +00003c f44f7180 MOV r1,#0x100 +000040 4a0e LDR r2,|L3.124| +000042 1f12 SUBS r2,r2,#4 +000044 6011 STR r1,[r2,#0] +000046 e015 B |L3.116| +;;;99 case 3: GPIO_PORT_RELAY3->BSRR = GPIO_PIN_RELAY3; break; +000048 2104 MOVS r1,#4 +00004a 4a0b LDR r2,|L3.120| +00004c 1f12 SUBS r2,r2,#4 +00004e 6011 STR r1,[r2,#0] +000050 e010 B |L3.116| +;;;100 case 4: GPIO_PORT_RELAY4->BSRR = GPIO_PIN_RELAY4; break; +000052 f44f7100 MOV r1,#0x200 +000056 4a09 LDR r2,|L3.124| +000058 1f12 SUBS r2,r2,#4 +00005a 6011 STR r1,[r2,#0] +00005c e00a B |L3.116| +;;;101 case 5: GPIO_PORT_RELAY5->BSRR = GPIO_PIN_RELAY5; break; +00005e 2102 MOVS r1,#2 +000060 4a05 LDR r2,|L3.120| +000062 1f12 SUBS r2,r2,#4 +000064 6011 STR r1,[r2,#0] +000066 e005 B |L3.116| +;;;102 case 6: GPIO_PORT_RELAY6->BSRR = GPIO_PIN_RELAY6; break; +000068 2101 MOVS r1,#1 +00006a 4a03 LDR r2,|L3.120| +00006c 1f12 SUBS r2,r2,#4 +00006e 6011 STR r1,[r2,#0] +000070 e000 B |L3.116| + |L3.114| +;;;103 default: break; +000072 bf00 NOP + |L3.116| +000074 bf00 NOP ;97 +;;;104 } +;;;105 } +000076 4770 BX lr +;;;106 + ENDP + + |L3.120| + DCD 0x40011814 + |L3.124| + DCD 0x40010c14 + +;*** Start embedded assembler *** + +#line 1 "..\\..\\User\\bsp\\src\\bsp_channel_realy.c" + AREA ||.rev16_text||, CODE + THUMB + EXPORT |__asm___19_bsp_channel_realy_c_4e9aa111____REV16| +#line 114 "..\\..\\Libraries\\CMSIS\\Include\\core_cmInstr.h" +|__asm___19_bsp_channel_realy_c_4e9aa111____REV16| PROC +#line 115 + + rev16 r0, r0 + bx lr + ENDP + AREA ||.revsh_text||, CODE + THUMB + EXPORT |__asm___19_bsp_channel_realy_c_4e9aa111____REVSH| +#line 128 +|__asm___19_bsp_channel_realy_c_4e9aa111____REVSH| PROC +#line 129 + + revsh r0, r0 + bx lr + ENDP + +;*** End embedded assembler *** diff --git a/Project/MDK-ARM/Flash/List/bsp_digital_tube.txt b/Project/MDK-ARM/Flash/List/bsp_digital_tube.txt new file mode 100644 index 0000000..b9d5a6b --- /dev/null +++ b/Project/MDK-ARM/Flash/List/bsp_digital_tube.txt @@ -0,0 +1,1168 @@ +; generated by Component: ARM Compiler 5.06 update 7 (build 960) Tool: ArmCC [4d365d] +; commandline ArmCC [--list --split_sections --debug -c --asm --interleave -o.\flash\obj\bsp_digital_tube.o --asm_dir=.\Flash\List\ --list_dir=.\Flash\List\ --depend=.\flash\obj\bsp_digital_tube.d --cpu=Cortex-M3 --apcs=interwork -O0 --diag_suppress=9931,870 -I..\..\Libraries\CMSIS\Device\ST\STM32F10x\Include -I..\..\Libraries\STM32F10x_StdPeriph_Driver\inc -I..\..\Libraries\STM32_USB-FS-Device_Driver\inc -I..\..\Libraries\CMSIS\Include -I..\..\User\bsp -I..\..\User\bsp\inc -I..\..\User\app\inc -I..\..\User -IC:\Users\w1619\AppData\Local\Arm\Packs\Keil\STM32F1xx_DFP\2.4.1\Device\Include -D__MICROLIB -D__UVISION_VERSION=538 -DSTM32F10X_HD -DUSE_STDPERIPH_DRIVER -DSTM32F10X_HD --omf_browse=.\flash\obj\bsp_digital_tube.crf ..\..\User\bsp\src\bsp_digital_tube.c] + THUMB + + AREA ||i.bsp_Angle2Buf||, CODE, READONLY, ALIGN=2 + + REQUIRE _printf_pre_padding + REQUIRE _printf_percent + REQUIRE _printf_widthprec + REQUIRE _printf_d + REQUIRE _printf_int_dec + bsp_Angle2Buf PROC +;;;317 } +;;;318 void bsp_Angle2Buf(void) +000000 e92d41f0 PUSH {r4-r8,lr} +;;;319 { +;;;320 uint8_t i = 0; +000004 2400 MOVS r4,#0 +;;;321 float angle = (((g_tTube.pulse % STEP_PER_LAP) + STEP_PER_LAP) % STEP_PER_LAP) * 360.0f / (STEP_PER_LAP / 100.0f); +000006 4838 LDR r0,|L1.232| +000008 6900 LDR r0,[r0,#0x10] ; g_tTube +00000a f242110d MOV r1,#0x210d +00000e fb90f2f1 SDIV r2,r0,r1 +000012 fb010012 MLS r0,r1,r2,r0 +000016 4408 ADD r0,r0,r1 +000018 fb90f2f1 SDIV r2,r0,r1 +00001c fb010812 MLS r8,r1,r2,r0 +000020 4640 MOV r0,r8 +000022 f7fffffe BL __aeabi_i2f +000026 4607 MOV r7,r0 +000028 4930 LDR r1,|L1.236| +00002a f7fffffe BL __aeabi_fmul +00002e 4606 MOV r6,r0 +000030 492f LDR r1,|L1.240| +000032 f7fffffe BL __aeabi_fdiv +000036 4605 MOV r5,r0 +;;;322 // printf("angle = %f\r\n", angle); +;;;323 if (angle < 0) +000038 2100 MOVS r1,#0 +00003a 4628 MOV r0,r5 +00003c f7fffffe BL __aeabi_cfcmple +000040 d20b BCS |L1.90| +;;;324 { +;;;325 angle -= 0.5f; // 负数向下取整 +000042 f04f517c MOV r1,#0x3f000000 +000046 4628 MOV r0,r5 +000048 f7fffffe BL __aeabi_fsub +00004c 4605 MOV r5,r0 +;;;326 angle += 360.0f; // 转换成整角度 +00004e 4927 LDR r1,|L1.236| +000050 4628 MOV r0,r5 +000052 f7fffffe BL __aeabi_fadd +000056 4605 MOV r5,r0 +000058 e005 B |L1.102| + |L1.90| +;;;327 } +;;;328 else +;;;329 angle += 0.5f; // 正数向上取整 +00005a f04f517c MOV r1,#0x3f000000 +00005e 4628 MOV r0,r5 +000060 f7fffffe BL __aeabi_fadd +000064 4605 MOV r5,r0 + |L1.102| +;;;330 +;;;331 // printf("angle = %f\r\n", angle); +;;;332 +;;;333 memset(g_tTube.buf, 0, 8); +000066 4820 LDR r0,|L1.232| +000068 2100 MOVS r1,#0 +00006a 6001 STR r1,[r0,#0] ; g_tTube +00006c 6041 STR r1,[r0,#4] ; g_tTube +;;;334 g_tTube.angle = angle; +00006e 4628 MOV r0,r5 +000070 f7fffffe BL __aeabi_f2iz +000074 491c LDR r1,|L1.232| +000076 6188 STR r0,[r1,#0x18] ; g_tTube +;;;335 snprintf(g_tTube.buf, 9, "%8d", g_tTube.angle); +000078 4608 MOV r0,r1 +00007a a21e ADR r2,|L1.244| +00007c 2109 MOVS r1,#9 +00007e 6983 LDR r3,[r0,#0x18] ; g_tTube +000080 f7fffffe BL __2snprintf +;;;336 for (i = 0; i < 8; i++) +000084 2400 MOVS r4,#0 +000086 e02a B |L1.222| + |L1.136| +;;;337 { +;;;338 if (g_tTube.buf[i] == ' ') +000088 4817 LDR r0,|L1.232| +00008a 5d00 LDRB r0,[r0,r4] +00008c 2820 CMP r0,#0x20 +00008e d107 BNE |L1.160| +;;;339 { +;;;340 g_tTube.buf[i] = NO_NULL; +000090 200b MOVS r0,#0xb +000092 4915 LDR r1,|L1.232| +000094 5508 STRB r0,[r1,r4] +;;;341 if (i >= 5) +000096 2c05 CMP r4,#5 +000098 db1f BLT |L1.218| +;;;342 { +;;;343 g_tTube.buf[i] = NO_0; +00009a 2000 MOVS r0,#0 +00009c 5508 STRB r0,[r1,r4] +00009e e01c B |L1.218| + |L1.160| +;;;344 } +;;;345 } +;;;346 else if (g_tTube.buf[i] == '-') +0000a0 4811 LDR r0,|L1.232| +0000a2 5d00 LDRB r0,[r0,r4] +0000a4 282d CMP r0,#0x2d +0000a6 d10b BNE |L1.192| +;;;347 { +;;;348 if (i >= 5) +0000a8 2c05 CMP r4,#5 +0000aa db05 BLT |L1.184| +;;;349 { +;;;350 g_tTube.buf[4] = NO__; +0000ac 200a MOVS r0,#0xa +0000ae 490e LDR r1,|L1.232| +0000b0 7108 STRB r0,[r1,#4] +;;;351 g_tTube.buf[i] = NO_0; +0000b2 2000 MOVS r0,#0 +0000b4 5508 STRB r0,[r1,r4] +0000b6 e010 B |L1.218| + |L1.184| +;;;352 } +;;;353 else +;;;354 { +;;;355 g_tTube.buf[i] = NO__; +0000b8 200a MOVS r0,#0xa +0000ba 490b LDR r1,|L1.232| +0000bc 5508 STRB r0,[r1,r4] +0000be e00c B |L1.218| + |L1.192| +;;;356 } +;;;357 } +;;;358 else if (isdigit(g_tTube.buf[i])) +0000c0 f7fffffe BL __rt_ctype_table +0000c4 6800 LDR r0,[r0,#0] +0000c6 4908 LDR r1,|L1.232| +0000c8 5d09 LDRB r1,[r1,r4] +0000ca 5c40 LDRB r0,[r0,r1] +0000cc 2820 CMP r0,#0x20 +0000ce d104 BNE |L1.218| +;;;359 { +;;;360 g_tTube.buf[i] = g_tTube.buf[i] - '0'; +0000d0 4805 LDR r0,|L1.232| +0000d2 5d00 LDRB r0,[r0,r4] +0000d4 3830 SUBS r0,r0,#0x30 +0000d6 4904 LDR r1,|L1.232| +0000d8 5508 STRB r0,[r1,r4] + |L1.218| +0000da 1c60 ADDS r0,r4,#1 ;336 +0000dc b2c4 UXTB r4,r0 ;336 + |L1.222| +0000de 2c08 CMP r4,#8 ;336 +0000e0 dbd2 BLT |L1.136| +;;;361 } +;;;362 } +;;;363 } +0000e2 e8bd81f0 POP {r4-r8,pc} +;;;364 + ENDP + +0000e6 0000 DCW 0x0000 + |L1.232| + DCD g_tTube + |L1.236| + DCD 0x43b40000 + |L1.240| + DCD 0x42a93852 + |L1.244| +0000f4 25386400 DCB "%8d",0 + + AREA ||i.bsp_DigitalTubeMainLoop||, CODE, READONLY, ALIGN=2 + + bsp_DigitalTubeMainLoop PROC +;;;364 +;;;365 void bsp_DigitalTubeMainLoop(void) +000000 b510 PUSH {r4,lr} +;;;366 { +;;;367 static uint8_t i = 0; +;;;368 if (++i >= 50) // 该函数每1ms调用一次，每50ms刷新一次脉冲或角度值 +000002 4816 LDR r0,|L2.92| +000004 7800 LDRB r0,[r0,#0] ; i +000006 1c40 ADDS r0,r0,#1 +000008 b2c0 UXTB r0,r0 +00000a 4914 LDR r1,|L2.92| +00000c 7008 STRB r0,[r1,#0] +00000e 2832 CMP r0,#0x32 +000010 db10 BLT |L2.52| +;;;369 { +;;;370 i = 0; +000012 2000 MOVS r0,#0 +000014 7008 STRB r0,[r1,#0] +;;;371 if (g_tTube.dir == DIR_CCW) +000016 4812 LDR r0,|L2.96| +000018 7b00 LDRB r0,[r0,#0xc] ; g_tTube +00001a 2801 CMP r0,#1 +00001c d104 BNE |L2.40| +;;;372 { +;;;373 g_tTube.pulse = g_tMoto.pv_pulse; +00001e 4811 LDR r0,|L2.100| +000020 6a00 LDR r0,[r0,#0x20] ; g_tMoto +000022 490f LDR r1,|L2.96| +000024 6108 STR r0,[r1,#0x10] ; g_tTube +000026 e003 B |L2.48| + |L2.40| +;;;374 } +;;;375 else +;;;376 { +;;;377 g_tTube.pulse = g_tMoto.pv_pulse; +000028 480e LDR r0,|L2.100| +00002a 6a00 LDR r0,[r0,#0x20] ; g_tMoto +00002c 490c LDR r1,|L2.96| +00002e 6108 STR r0,[r1,#0x10] ; g_tTube + |L2.48| +;;;378 } +;;;379 bsp_UpdateDisplayBuf(); +000030 f7fffffe BL bsp_UpdateDisplayBuf + |L2.52| +;;;380 } +;;;381 bsp_TubeTest(g_tTube.cnt, g_tTube.buf[g_tTube.cnt]); +000034 4a0a LDR r2,|L2.96| +000036 7a92 LDRB r2,[r2,#0xa] ; g_tTube +000038 4b09 LDR r3,|L2.96| +00003a 5c99 LDRB r1,[r3,r2] +00003c 461a MOV r2,r3 +00003e 7a90 LDRB r0,[r2,#0xa] ; g_tTube +000040 f7fffffe BL bsp_TubeTest +;;;382 if (++g_tTube.cnt >= 8) +000044 4806 LDR r0,|L2.96| +000046 7a80 LDRB r0,[r0,#0xa] ; g_tTube +000048 1c40 ADDS r0,r0,#1 +00004a b2c0 UXTB r0,r0 +00004c 4904 LDR r1,|L2.96| +00004e 7288 STRB r0,[r1,#0xa] +000050 2808 CMP r0,#8 +000052 db01 BLT |L2.88| +;;;383 g_tTube.cnt = 0; +000054 2000 MOVS r0,#0 +000056 7288 STRB r0,[r1,#0xa] + |L2.88| +;;;384 } +000058 bd10 POP {r4,pc} +;;;385 + ENDP + +00005a 0000 DCW 0x0000 + |L2.92| + DCD i + |L2.96| + DCD g_tTube + |L2.100| + DCD g_tMoto + + AREA ||i.bsp_InitDigitalTube||, CODE, READONLY, ALIGN=2 + + bsp_InitDigitalTube PROC +;;;391 //------------------------------------------------------------------------------ +;;;392 void bsp_InitDigitalTube(void) +000000 b508 PUSH {r3,lr} +;;;393 { +;;;394 GPIO_InitTypeDef GPIO_InitStructure; +;;;395 // 打开数码管GPIO时钟 +;;;396 RCC_APB2PeriphClockCmd(RCC_ALL_TUBE, ENABLE); +000002 2101 MOVS r1,#1 +000004 2030 MOVS r0,#0x30 +000006 f7fffffe BL RCC_APB2PeriphClockCmd +;;;397 GPIO_InitStructure.GPIO_Speed = GPIO_Speed_50MHz; +00000a 2003 MOVS r0,#3 +00000c f88d0002 STRB r0,[sp,#2] +;;;398 GPIO_InitStructure.GPIO_Mode = GPIO_Mode_Out_PP; // 推挽输出模式 +000010 2010 MOVS r0,#0x10 +000012 f88d0003 STRB r0,[sp,#3] +;;;399 +;;;400 GPIO_InitStructure.GPIO_Pin = GPIO_PIN_A; // 位 a +000016 2001 MOVS r0,#1 +000018 f8ad0000 STRH r0,[sp,#0] +;;;401 GPIO_Init(GPIO_PORT_A, &GPIO_InitStructure); +00001c 4669 MOV r1,sp +00001e 483d LDR r0,|L3.276| +000020 f7fffffe BL GPIO_Init +;;;402 GPIO_InitStructure.GPIO_Pin = GPIO_PIN_B; // 位 b +000024 2002 MOVS r0,#2 +000026 f8ad0000 STRH r0,[sp,#0] +;;;403 GPIO_Init(GPIO_PORT_B, &GPIO_InitStructure); +00002a 4669 MOV r1,sp +00002c 4839 LDR r0,|L3.276| +00002e f7fffffe BL GPIO_Init +;;;404 GPIO_InitStructure.GPIO_Pin = GPIO_PIN_C; // 位 c +000032 2004 MOVS r0,#4 +000034 f8ad0000 STRH r0,[sp,#0] +;;;405 GPIO_Init(GPIO_PORT_C, &GPIO_InitStructure); +000038 4669 MOV r1,sp +00003a 4836 LDR r0,|L3.276| +00003c f7fffffe BL GPIO_Init +;;;406 GPIO_InitStructure.GPIO_Pin = GPIO_PIN_D; // 位 d +000040 2008 MOVS r0,#8 +000042 f8ad0000 STRH r0,[sp,#0] +;;;407 GPIO_Init(GPIO_PORT_D, &GPIO_InitStructure); +000046 4669 MOV r1,sp +000048 4832 LDR r0,|L3.276| +00004a f7fffffe BL GPIO_Init +;;;408 GPIO_InitStructure.GPIO_Pin = GPIO_PIN_E; // 位 e +00004e 2010 MOVS r0,#0x10 +000050 f8ad0000 STRH r0,[sp,#0] +;;;409 GPIO_Init(GPIO_PORT_E, &GPIO_InitStructure); +000054 4669 MOV r1,sp +000056 482f LDR r0,|L3.276| +000058 f7fffffe BL GPIO_Init +;;;410 GPIO_InitStructure.GPIO_Pin = GPIO_PIN_F; // 位 f +00005c 2020 MOVS r0,#0x20 +00005e f8ad0000 STRH r0,[sp,#0] +;;;411 GPIO_Init(GPIO_PORT_F, &GPIO_InitStructure); +000062 4669 MOV r1,sp +000064 482b LDR r0,|L3.276| +000066 f7fffffe BL GPIO_Init +;;;412 GPIO_InitStructure.GPIO_Pin = GPIO_PIN_G; // 位 g +00006a 2040 MOVS r0,#0x40 +00006c f8ad0000 STRH r0,[sp,#0] +;;;413 GPIO_Init(GPIO_PORT_G, &GPIO_InitStructure); +000070 4669 MOV r1,sp +000072 4828 LDR r0,|L3.276| +000074 f7fffffe BL GPIO_Init +;;;414 GPIO_InitStructure.GPIO_Pin = GPIO_PIN_H; // 位 h +000078 2080 MOVS r0,#0x80 +00007a f8ad0000 STRH r0,[sp,#0] +;;;415 GPIO_Init(GPIO_PORT_H, &GPIO_InitStructure); +00007e 4669 MOV r1,sp +000080 4824 LDR r0,|L3.276| +000082 f7fffffe BL GPIO_Init +;;;416 +;;;417 GPIO_InitStructure.GPIO_Pin = GPIO_PIN_DS1; // 段 1 +000086 f44f7000 MOV r0,#0x200 +00008a f8ad0000 STRH r0,[sp,#0] +;;;418 GPIO_Init(GPIO_PORT_DS1, &GPIO_InitStructure); +00008e 4669 MOV r1,sp +000090 4821 LDR r0,|L3.280| +000092 f7fffffe BL GPIO_Init +;;;419 GPIO_InitStructure.GPIO_Pin = GPIO_PIN_DS2; // 段 2 +000096 f44f7080 MOV r0,#0x100 +00009a f8ad0000 STRH r0,[sp,#0] +;;;420 GPIO_Init(GPIO_PORT_DS2, &GPIO_InitStructure); +00009e 4669 MOV r1,sp +0000a0 481d LDR r0,|L3.280| +0000a2 f7fffffe BL GPIO_Init +;;;421 GPIO_InitStructure.GPIO_Pin = GPIO_PIN_DS3; // 段 3 +0000a6 f44f6080 MOV r0,#0x400 +0000aa f8ad0000 STRH r0,[sp,#0] +;;;422 GPIO_Init(GPIO_PORT_DS3, &GPIO_InitStructure); +0000ae 4669 MOV r1,sp +0000b0 4819 LDR r0,|L3.280| +0000b2 f7fffffe BL GPIO_Init +;;;423 GPIO_InitStructure.GPIO_Pin = GPIO_PIN_DS4; // 段 4 +0000b6 2040 MOVS r0,#0x40 +0000b8 f8ad0000 STRH r0,[sp,#0] +;;;424 GPIO_Init(GPIO_PORT_DS4, &GPIO_InitStructure); +0000bc 4669 MOV r1,sp +0000be 4816 LDR r0,|L3.280| +0000c0 f7fffffe BL GPIO_Init +;;;425 GPIO_InitStructure.GPIO_Pin = GPIO_PIN_DS5; // 段 5 +0000c4 f44f6000 MOV r0,#0x800 +0000c8 f8ad0000 STRH r0,[sp,#0] +;;;426 GPIO_Init(GPIO_PORT_DS5, &GPIO_InitStructure); +0000cc 4669 MOV r1,sp +0000ce 4811 LDR r0,|L3.276| +0000d0 f7fffffe BL GPIO_Init +;;;427 GPIO_InitStructure.GPIO_Pin = GPIO_PIN_DS6; // 段 6 +0000d4 f44f6080 MOV r0,#0x400 +0000d8 f8ad0000 STRH r0,[sp,#0] +;;;428 GPIO_Init(GPIO_PORT_DS6, &GPIO_InitStructure); +0000dc 4669 MOV r1,sp +0000de 480d LDR r0,|L3.276| +0000e0 f7fffffe BL GPIO_Init +;;;429 GPIO_InitStructure.GPIO_Pin = GPIO_PIN_DS7; // 段 7 +0000e4 f44f7000 MOV r0,#0x200 +0000e8 f8ad0000 STRH r0,[sp,#0] +;;;430 GPIO_Init(GPIO_PORT_DS7, &GPIO_InitStructure); +0000ec 4669 MOV r1,sp +0000ee 4809 LDR r0,|L3.276| +0000f0 f7fffffe BL GPIO_Init +;;;431 GPIO_InitStructure.GPIO_Pin = GPIO_PIN_DS8; // 段 8 +0000f4 f44f7080 MOV r0,#0x100 +0000f8 f8ad0000 STRH r0,[sp,#0] +;;;432 GPIO_Init(GPIO_PORT_DS8, &GPIO_InitStructure); +0000fc 4669 MOV r1,sp +0000fe 4805 LDR r0,|L3.276| +000100 f7fffffe BL GPIO_Init +;;;433 +;;;434 bsp_InitTubeVar(); +000104 f7fffffe BL bsp_InitTubeVar +;;;435 bsp_ReadDatFromEEPROM(); +000108 f7fffffe BL bsp_ReadDatFromEEPROM +;;;436 bsp_UpdateDisplayBuf(); +00010c f7fffffe BL bsp_UpdateDisplayBuf +;;;437 } +000110 bd08 POP {r3,pc} +;;;438 + ENDP + +000112 0000 DCW 0x0000 + |L3.276| + DCD 0x40011400 + |L3.280| + DCD 0x40011000 + + AREA ||i.bsp_InitTubeVar||, CODE, READONLY, ALIGN=2 + + bsp_InitTubeVar PROC +;;;126 +;;;127 void bsp_InitTubeVar(void) +000000 2000 MOVS r0,#0 +;;;128 { +;;;129 uint8_t i = 0; +;;;130 +;;;131 for (i = 0; i < 8; i++) +000002 bf00 NOP +000004 e004 B |L4.16| + |L4.6| +;;;132 { +;;;133 g_tTube.buf[i] = NO_NULL; +000006 210b MOVS r1,#0xb +000008 4a07 LDR r2,|L4.40| +00000a 5411 STRB r1,[r2,r0] +00000c 1c41 ADDS r1,r0,#1 ;131 +00000e b2c8 UXTB r0,r1 ;131 + |L4.16| +000010 2808 CMP r0,#8 ;131 +000012 dbf8 BLT |L4.6| +;;;134 } +;;;135 g_tTube.disp_mode = MODE_PULSE; +000014 2100 MOVS r1,#0 +000016 4a04 LDR r2,|L4.40| +000018 7251 STRB r1,[r2,#9] +;;;136 g_tTube.cnt = 0; +00001a 7291 STRB r1,[r2,#0xa] +;;;137 g_tTube.state = IDLE; +00001c 72d1 STRB r1,[r2,#0xb] +;;;138 // g_tTube.state = WORK; +;;;139 g_tTube.dir = DIR_CW; +00001e 7311 STRB r1,[r2,#0xc] +;;;140 g_tTube.pulse = 0; +000020 6111 STR r1,[r2,#0x10] ; g_tTube +;;;141 g_tTube.tim_pulse_cnt = 0; +000022 6151 STR r1,[r2,#0x14] ; g_tTube +;;;142 g_tTube.angle = 0; +000024 6191 STR r1,[r2,#0x18] ; g_tTube +;;;143 } +000026 4770 BX lr +;;;144 + ENDP + + |L4.40| + DCD g_tTube + + AREA ||i.bsp_Pulse2Buf||, CODE, READONLY, ALIGN=2 + + REQUIRE _printf_pre_padding + REQUIRE _printf_percent + REQUIRE _printf_widthprec + REQUIRE _printf_d + REQUIRE _printf_int_dec + bsp_Pulse2Buf PROC +;;;295 } +;;;296 void bsp_Pulse2Buf(void) +000000 b510 PUSH {r4,lr} +;;;297 { +;;;298 uint8_t i = 0; +000002 2400 MOVS r4,#0 +;;;299 +;;;300 memset(g_tTube.buf, 0, 8); +000004 4816 LDR r0,|L5.96| +000006 2100 MOVS r1,#0 +000008 6001 STR r1,[r0,#0] ; g_tTube +00000a 6041 STR r1,[r0,#4] ; g_tTube +;;;301 snprintf(g_tTube.buf, 9, "%8d", g_tTube.pulse); +00000c a215 ADR r2,|L5.100| +00000e 2109 MOVS r1,#9 +000010 6903 LDR r3,[r0,#0x10] ; g_tTube +000012 f7fffffe BL __2snprintf +;;;302 for (i = 0; i < 8; i++) +000016 bf00 NOP +000018 e01e B |L5.88| + |L5.26| +;;;303 { +;;;304 if (g_tTube.buf[i] == ' ') +00001a 4811 LDR r0,|L5.96| +00001c 5d00 LDRB r0,[r0,r4] +00001e 2820 CMP r0,#0x20 +000020 d103 BNE |L5.42| +;;;305 { +;;;306 g_tTube.buf[i] = NO_NULL; +000022 200b MOVS r0,#0xb +000024 490e LDR r1,|L5.96| +000026 5508 STRB r0,[r1,r4] +000028 e014 B |L5.84| + |L5.42| +;;;307 } +;;;308 else if (g_tTube.buf[i] == '-') +00002a 480d LDR r0,|L5.96| +00002c 5d00 LDRB r0,[r0,r4] +00002e 282d CMP r0,#0x2d +000030 d103 BNE |L5.58| +;;;309 { +;;;310 g_tTube.buf[i] = NO__; +000032 200a MOVS r0,#0xa +000034 490a LDR r1,|L5.96| +000036 5508 STRB r0,[r1,r4] +000038 e00c B |L5.84| + |L5.58| +;;;311 } +;;;312 else if (isdigit(g_tTube.buf[i])) +00003a f7fffffe BL __rt_ctype_table +00003e 6800 LDR r0,[r0,#0] +000040 4907 LDR r1,|L5.96| +000042 5d09 LDRB r1,[r1,r4] +000044 5c40 LDRB r0,[r0,r1] +000046 2820 CMP r0,#0x20 +000048 d104 BNE |L5.84| +;;;313 { +;;;314 g_tTube.buf[i] = g_tTube.buf[i] - '0'; +00004a 4805 LDR r0,|L5.96| +00004c 5d00 LDRB r0,[r0,r4] +00004e 3830 SUBS r0,r0,#0x30 +000050 4903 LDR r1,|L5.96| +000052 5508 STRB r0,[r1,r4] + |L5.84| +000054 1c60 ADDS r0,r4,#1 ;302 +000056 b2c4 UXTB r4,r0 ;302 + |L5.88| +000058 2c08 CMP r4,#8 ;302 +00005a dbde BLT |L5.26| +;;;315 } +;;;316 } +;;;317 } +00005c bd10 POP {r4,pc} +;;;318 void bsp_Angle2Buf(void) + ENDP + +00005e 0000 DCW 0x0000 + |L5.96| + DCD g_tTube + |L5.100| +000064 25386400 DCB "%8d",0 + + AREA ||i.bsp_ReadDatFromEEPROM||, CODE, READONLY, ALIGN=2 + + bsp_ReadDatFromEEPROM PROC +;;;438 +;;;439 static void bsp_ReadDatFromEEPROM(void) +000000 b51c PUSH {r2-r4,lr} +;;;440 { +;;;441 uint8_t buf[5]; // PULSE: 55AA00FF; ANGLE: FF00AA55 +;;;442 +;;;443 ee_ReadBytes((uint8_t *)buf, 0, 4); +000002 2204 MOVS r2,#4 +000004 2100 MOVS r1,#0 +000006 4668 MOV r0,sp +000008 f7fffffe BL ee_ReadBytes +;;;444 if ((buf[0] == 0X55) && (buf[1] == 0XAA) && (buf[2] == 0X00) && (buf[3] == 0XFF)) +00000c f89d0000 LDRB r0,[sp,#0] +000010 2855 CMP r0,#0x55 +000012 d10e BNE |L6.50| +000014 f89d0001 LDRB r0,[sp,#1] +000018 28aa CMP r0,#0xaa +00001a d10a BNE |L6.50| +00001c f89d0002 LDRB r0,[sp,#2] +000020 b938 CBNZ r0,|L6.50| +000022 f89d0003 LDRB r0,[sp,#3] +000026 28ff CMP r0,#0xff +000028 d103 BNE |L6.50| +;;;445 { +;;;446 g_tTube.disp_mode = MODE_PULSE; +00002a 2000 MOVS r0,#0 +00002c 490a LDR r1,|L6.88| +00002e 7248 STRB r0,[r1,#9] +000030 e011 B |L6.86| + |L6.50| +;;;447 } +;;;448 else if ((buf[0] == 0XFF) && (buf[1] == 0X00) && (buf[2] == 0XAA) && (buf[3] == 0X55)) +000032 f89d0000 LDRB r0,[sp,#0] +000036 28ff CMP r0,#0xff +000038 d10d BNE |L6.86| +00003a f89d0001 LDRB r0,[sp,#1] +00003e b950 CBNZ r0,|L6.86| +000040 f89d0002 LDRB r0,[sp,#2] +000044 28aa CMP r0,#0xaa +000046 d106 BNE |L6.86| +000048 f89d0003 LDRB r0,[sp,#3] +00004c 2855 CMP r0,#0x55 +00004e d102 BNE |L6.86| +;;;449 { +;;;450 g_tTube.disp_mode = MODE_ANGLE; +000050 2001 MOVS r0,#1 +000052 4901 LDR r1,|L6.88| +000054 7248 STRB r0,[r1,#9] + |L6.86| +;;;451 } +;;;452 } +000056 bd1c POP {r2-r4,pc} +;;;453 + ENDP + + |L6.88| + DCD g_tTube + + AREA ||i.bsp_ToogleDispMode||, CODE, READONLY, ALIGN=2 + + bsp_ToogleDispMode PROC +;;;217 } +;;;218 void bsp_ToogleDispMode(void) +000000 b51c PUSH {r2-r4,lr} +;;;219 { +;;;220 uint8_t buf[5]; // PULSE: 55AA00FF; ANGLE: FF00AA55 +;;;221 +;;;222 switch (g_tTube.disp_mode) +000002 481e LDR r0,|L7.124| +000004 7a40 LDRB r0,[r0,#9] ; g_tTube +000006 b110 CBZ r0,|L7.14| +000008 2801 CMP r0,#1 +00000a d108 BNE |L7.30| +00000c e003 B |L7.22| + |L7.14| +;;;223 { +;;;224 case MODE_PULSE: +;;;225 g_tTube.disp_mode = MODE_ANGLE; +00000e 2001 MOVS r0,#1 +000010 491a LDR r1,|L7.124| +000012 7248 STRB r0,[r1,#9] +;;;226 break; +000014 e004 B |L7.32| + |L7.22| +;;;227 case MODE_ANGLE: +;;;228 g_tTube.disp_mode = MODE_PULSE; +000016 2000 MOVS r0,#0 +000018 4918 LDR r1,|L7.124| +00001a 7248 STRB r0,[r1,#9] +;;;229 break; +00001c e000 B |L7.32| + |L7.30| +;;;230 default: +;;;231 break; +00001e bf00 NOP + |L7.32| +000020 bf00 NOP ;226 +;;;232 } +;;;233 +;;;234 if (g_tTube.disp_mode == MODE_ANGLE) +000022 4816 LDR r0,|L7.124| +000024 7a40 LDRB r0,[r0,#9] ; g_tTube +000026 2801 CMP r0,#1 +000028 d111 BNE |L7.78| +;;;235 { +;;;236 buf[0] = 0xFF; +00002a 20ff MOVS r0,#0xff +00002c f88d0000 STRB r0,[sp,#0] +;;;237 buf[1] = 0x00; +000030 2000 MOVS r0,#0 +000032 f88d0001 STRB r0,[sp,#1] +;;;238 buf[2] = 0xAA; +000036 20aa MOVS r0,#0xaa +000038 f88d0002 STRB r0,[sp,#2] +;;;239 buf[3] = 0x55; +00003c 2055 MOVS r0,#0x55 +00003e f88d0003 STRB r0,[sp,#3] +;;;240 ee_WriteBytes(buf, 0, 4); +000042 2204 MOVS r2,#4 +000044 2100 MOVS r1,#0 +000046 4668 MOV r0,sp +000048 f7fffffe BL ee_WriteBytes +00004c e013 B |L7.118| + |L7.78| +;;;241 } +;;;242 else if (g_tTube.disp_mode == MODE_PULSE) +00004e 480b LDR r0,|L7.124| +000050 7a40 LDRB r0,[r0,#9] ; g_tTube +000052 b980 CBNZ r0,|L7.118| +;;;243 { +;;;244 buf[0] = 0x55; +000054 2055 MOVS r0,#0x55 +000056 f88d0000 STRB r0,[sp,#0] +;;;245 buf[1] = 0xAA; +00005a 20aa MOVS r0,#0xaa +00005c f88d0001 STRB r0,[sp,#1] +;;;246 buf[2] = 0x00; +000060 2000 MOVS r0,#0 +000062 f88d0002 STRB r0,[sp,#2] +;;;247 buf[3] = 0xFF; +000066 20ff MOVS r0,#0xff +000068 f88d0003 STRB r0,[sp,#3] +;;;248 ee_WriteBytes(buf, 0, 4); +00006c 2204 MOVS r2,#4 +00006e 2100 MOVS r1,#0 +000070 4668 MOV r0,sp +000072 f7fffffe BL ee_WriteBytes + |L7.118| +;;;249 } +;;;250 +;;;251 bsp_UpdateDisplayBuf(); +000076 f7fffffe BL bsp_UpdateDisplayBuf +;;;252 } +00007a bd1c POP {r2-r4,pc} +;;;253 void bsp_ToogleStateMode(void) + ENDP + + |L7.124| + DCD g_tTube + + AREA ||i.bsp_ToogleStateMode||, CODE, READONLY, ALIGN=2 + + bsp_ToogleStateMode PROC +;;;252 } +;;;253 void bsp_ToogleStateMode(void) +000000 b510 PUSH {r4,lr} +;;;254 { +;;;255 switch (g_tTube.state) +000002 4809 LDR r0,|L8.40| +000004 7ac0 LDRB r0,[r0,#0xb] ; g_tTube +000006 b110 CBZ r0,|L8.14| +000008 2801 CMP r0,#1 +00000a d108 BNE |L8.30| +00000c e003 B |L8.22| + |L8.14| +;;;256 { +;;;257 case IDLE: +;;;258 g_tTube.state = WORK; +00000e 2001 MOVS r0,#1 +000010 4905 LDR r1,|L8.40| +000012 72c8 STRB r0,[r1,#0xb] +;;;259 break; +000014 e004 B |L8.32| + |L8.22| +;;;260 case WORK: +;;;261 g_tTube.state = IDLE; +000016 2000 MOVS r0,#0 +000018 4903 LDR r1,|L8.40| +00001a 72c8 STRB r0,[r1,#0xb] +;;;262 break; +00001c e000 B |L8.32| + |L8.30| +;;;263 default: +;;;264 break; +00001e bf00 NOP + |L8.32| +000020 bf00 NOP ;259 +;;;265 } +;;;266 bsp_UpdateDisplayBuf(); +000022 f7fffffe BL bsp_UpdateDisplayBuf +;;;267 } +000026 bd10 POP {r4,pc} +;;;268 + ENDP + + |L8.40| + DCD g_tTube + + AREA ||i.bsp_TubeTest||, CODE, READONLY, ALIGN=2 + + bsp_TubeTest PROC +;;;144 +;;;145 void bsp_TubeTest(uint8_t _com, uint8_t _seg) +000000 2920 CMP r1,#0x20 +;;;146 { +;;;147 if (_seg == ' ') +000002 d100 BNE |L9.6| +;;;148 _seg = NO_NULL; +000004 210b MOVS r1,#0xb + |L9.6| +;;;149 if (_seg >= 12) +000006 290c CMP r1,#0xc +000008 db00 BLT |L9.12| + |L9.10| +;;;150 return; +;;;151 +;;;152 CLOSE_ALL_TUBE_COM; +;;;153 CLOSE_ALL_TUBE_SEG; +;;;154 +;;;155 if (g_tube_table[_seg][0]) +;;;156 { +;;;157 GPIO_PORT_A->BSRR = GPIO_PIN_A; +;;;158 }; +;;;159 if (g_tube_table[_seg][1]) +;;;160 { +;;;161 GPIO_PORT_B->BSRR = GPIO_PIN_B; +;;;162 }; +;;;163 if (g_tube_table[_seg][2]) +;;;164 { +;;;165 GPIO_PORT_C->BSRR = GPIO_PIN_C; +;;;166 }; +;;;167 if (g_tube_table[_seg][3]) +;;;168 { +;;;169 GPIO_PORT_D->BSRR = GPIO_PIN_D; +;;;170 }; +;;;171 if (g_tube_table[_seg][4]) +;;;172 { +;;;173 GPIO_PORT_E->BSRR = GPIO_PIN_E; +;;;174 }; +;;;175 if (g_tube_table[_seg][5]) +;;;176 { +;;;177 GPIO_PORT_F->BSRR = GPIO_PIN_F; +;;;178 }; +;;;179 if (g_tube_table[_seg][6]) +;;;180 { +;;;181 GPIO_PORT_G->BSRR = GPIO_PIN_G; +;;;182 }; +;;;183 if ((_com == 5) && (g_tTube.disp_mode == MODE_ANGLE)) +;;;184 { +;;;185 GPIO_PORT_H->BSRR = GPIO_PIN_H; +;;;186 } +;;;187 +;;;188 switch (_com) +;;;189 { +;;;190 case 0: +;;;191 GPIO_PORT_DS1->BSRR = GPIO_PIN_DS1; +;;;192 break; +;;;193 case 1: +;;;194 GPIO_PORT_DS2->BSRR = GPIO_PIN_DS2; +;;;195 break; +;;;196 case 2: +;;;197 GPIO_PORT_DS3->BSRR = GPIO_PIN_DS3; +;;;198 break; +;;;199 case 3: +;;;200 GPIO_PORT_DS4->BSRR = GPIO_PIN_DS4; +;;;201 break; +;;;202 case 4: +;;;203 GPIO_PORT_DS5->BSRR = GPIO_PIN_DS5; +;;;204 break; +;;;205 case 5: +;;;206 GPIO_PORT_DS6->BSRR = GPIO_PIN_DS6; +;;;207 break; +;;;208 case 6: +;;;209 GPIO_PORT_DS7->BSRR = GPIO_PIN_DS7; +;;;210 break; +;;;211 case 7: +;;;212 GPIO_PORT_DS8->BSRR = GPIO_PIN_DS8; +;;;213 break; +;;;214 default: +;;;215 break; +;;;216 } +;;;217 } +00000a 4770 BX lr + |L9.12| +00000c bf00 NOP ;152 +00000e f44f7200 MOV r2,#0x200 ;152 +000012 4b55 LDR r3,|L9.360| +000014 615a STR r2,[r3,#0x14] ;152 +000016 1052 ASRS r2,r2,#1 ;152 +000018 615a STR r2,[r3,#0x14] ;152 +00001a 0092 LSLS r2,r2,#2 ;152 +00001c 615a STR r2,[r3,#0x14] ;152 +00001e 2240 MOVS r2,#0x40 ;152 +000020 615a STR r2,[r3,#0x14] ;152 +000022 0152 LSLS r2,r2,#5 ;152 +000024 4b51 LDR r3,|L9.364| +000026 601a STR r2,[r3,#0] ;152 +000028 1052 ASRS r2,r2,#1 ;152 +00002a 601a STR r2,[r3,#0] ;152 +00002c 1052 ASRS r2,r2,#1 ;152 +00002e 601a STR r2,[r3,#0] ;152 +000030 1052 ASRS r2,r2,#1 ;152 +000032 601a STR r2,[r3,#0] ;152 +000034 bf00 NOP ;152 +000036 bf00 NOP ;153 +000038 2201 MOVS r2,#1 ;153 +00003a 601a STR r2,[r3,#0] ;153 +00003c 2202 MOVS r2,#2 ;153 +00003e 601a STR r2,[r3,#0] ;153 +000040 2204 MOVS r2,#4 ;153 +000042 601a STR r2,[r3,#0] ;153 +000044 2208 MOVS r2,#8 ;153 +000046 601a STR r2,[r3,#0] ;153 +000048 2210 MOVS r2,#0x10 ;153 +00004a 601a STR r2,[r3,#0] ;153 +00004c 2220 MOVS r2,#0x20 ;153 +00004e 601a STR r2,[r3,#0] ;153 +000050 2240 MOVS r2,#0x40 ;153 +000052 601a STR r2,[r3,#0] ;153 +000054 2280 MOVS r2,#0x80 ;153 +000056 601a STR r2,[r3,#0] ;153 +000058 bf00 NOP ;153 +00005a ebc102c1 RSB r2,r1,r1,LSL #3 ;155 +00005e 4b44 LDR r3,|L9.368| +000060 5c9a LDRB r2,[r3,r2] ;155 +000062 b11a CBZ r2,|L9.108| +000064 2201 MOVS r2,#1 ;157 +000066 4b41 LDR r3,|L9.364| +000068 1f1b SUBS r3,r3,#4 ;157 +00006a 601a STR r2,[r3,#0] ;157 + |L9.108| +00006c ebc102c1 RSB r2,r1,r1,LSL #3 ;159 +000070 4b3f LDR r3,|L9.368| +000072 441a ADD r2,r2,r3 ;159 +000074 7852 LDRB r2,[r2,#1] ;159 +000076 b11a CBZ r2,|L9.128| +000078 2202 MOVS r2,#2 ;161 +00007a 4b3c LDR r3,|L9.364| +00007c 1f1b SUBS r3,r3,#4 ;161 +00007e 601a STR r2,[r3,#0] ;161 + |L9.128| +000080 ebc102c1 RSB r2,r1,r1,LSL #3 ;163 +000084 4b3a LDR r3,|L9.368| +000086 441a ADD r2,r2,r3 ;163 +000088 7892 LDRB r2,[r2,#2] ;163 +00008a b11a CBZ r2,|L9.148| +00008c 2204 MOVS r2,#4 ;165 +00008e 4b37 LDR r3,|L9.364| +000090 1f1b SUBS r3,r3,#4 ;165 +000092 601a STR r2,[r3,#0] ;165 + |L9.148| +000094 ebc102c1 RSB r2,r1,r1,LSL #3 ;167 +000098 4b35 LDR r3,|L9.368| +00009a 441a ADD r2,r2,r3 ;167 +00009c 78d2 LDRB r2,[r2,#3] ;167 +00009e b11a CBZ r2,|L9.168| +0000a0 2208 MOVS r2,#8 ;169 +0000a2 4b32 LDR r3,|L9.364| +0000a4 1f1b SUBS r3,r3,#4 ;169 +0000a6 601a STR r2,[r3,#0] ;169 + |L9.168| +0000a8 ebc102c1 RSB r2,r1,r1,LSL #3 ;171 +0000ac 4b30 LDR r3,|L9.368| +0000ae 441a ADD r2,r2,r3 ;171 +0000b0 7912 LDRB r2,[r2,#4] ;171 +0000b2 b11a CBZ r2,|L9.188| +0000b4 2210 MOVS r2,#0x10 ;173 +0000b6 4b2d LDR r3,|L9.364| +0000b8 1f1b SUBS r3,r3,#4 ;173 +0000ba 601a STR r2,[r3,#0] ;173 + |L9.188| +0000bc ebc102c1 RSB r2,r1,r1,LSL #3 ;175 +0000c0 4b2b LDR r3,|L9.368| +0000c2 441a ADD r2,r2,r3 ;175 +0000c4 7952 LDRB r2,[r2,#5] ;175 +0000c6 b11a CBZ r2,|L9.208| +0000c8 2220 MOVS r2,#0x20 ;177 +0000ca 4b28 LDR r3,|L9.364| +0000cc 1f1b SUBS r3,r3,#4 ;177 +0000ce 601a STR r2,[r3,#0] ;177 + |L9.208| +0000d0 ebc102c1 RSB r2,r1,r1,LSL #3 ;179 +0000d4 4b26 LDR r3,|L9.368| +0000d6 441a ADD r2,r2,r3 ;179 +0000d8 7992 LDRB r2,[r2,#6] ;179 +0000da b11a CBZ r2,|L9.228| +0000dc 2240 MOVS r2,#0x40 ;181 +0000de 4b23 LDR r3,|L9.364| +0000e0 1f1b SUBS r3,r3,#4 ;181 +0000e2 601a STR r2,[r3,#0] ;181 + |L9.228| +0000e4 2805 CMP r0,#5 ;183 +0000e6 d107 BNE |L9.248| +0000e8 4a22 LDR r2,|L9.372| +0000ea 7a52 LDRB r2,[r2,#9] ;183 ; g_tTube +0000ec 2a01 CMP r2,#1 ;183 +0000ee d103 BNE |L9.248| +0000f0 2280 MOVS r2,#0x80 ;185 +0000f2 4b1e LDR r3,|L9.364| +0000f4 1f1b SUBS r3,r3,#4 ;185 +0000f6 601a STR r2,[r3,#0] ;185 + |L9.248| +0000f8 2808 CMP r0,#8 ;188 +0000fa d230 BCS |L9.350| +0000fc e8dff000 TBB [pc,r0] ;188 +000100 04090e13 DCB 0x04,0x09,0x0e,0x13 +000104 171d2329 DCB 0x17,0x1d,0x23,0x29 +000108 f44f7200 MOV r2,#0x200 ;191 +00010c 4b16 LDR r3,|L9.360| +00010e 611a STR r2,[r3,#0x10] ;191 +000110 e026 B |L9.352| +000112 f44f7280 MOV r2,#0x100 ;194 +000116 4b14 LDR r3,|L9.360| +000118 611a STR r2,[r3,#0x10] ;194 +00011a e021 B |L9.352| +00011c f44f6280 MOV r2,#0x400 ;197 +000120 4b11 LDR r3,|L9.360| +000122 611a STR r2,[r3,#0x10] ;197 +000124 e01c B |L9.352| +000126 2240 MOVS r2,#0x40 ;200 +000128 4b0f LDR r3,|L9.360| +00012a 611a STR r2,[r3,#0x10] ;200 +00012c e018 B |L9.352| +00012e f44f6200 MOV r2,#0x800 ;203 +000132 4b0e LDR r3,|L9.364| +000134 1f1b SUBS r3,r3,#4 ;203 +000136 601a STR r2,[r3,#0] ;203 +000138 e012 B |L9.352| +00013a f44f6280 MOV r2,#0x400 ;206 +00013e 4b0b LDR r3,|L9.364| +000140 1f1b SUBS r3,r3,#4 ;206 +000142 601a STR r2,[r3,#0] ;206 +000144 e00c B |L9.352| +000146 f44f7200 MOV r2,#0x200 ;209 +00014a 4b08 LDR r3,|L9.364| +00014c 1f1b SUBS r3,r3,#4 ;209 +00014e 601a STR r2,[r3,#0] ;209 +000150 e006 B |L9.352| +000152 f44f7280 MOV r2,#0x100 ;212 +000156 4b05 LDR r3,|L9.364| +000158 1f1b SUBS r3,r3,#4 ;212 +00015a 601a STR r2,[r3,#0] ;212 +00015c e000 B |L9.352| + |L9.350| +00015e bf00 NOP ;215 + |L9.352| +000160 bf00 NOP ;192 +000162 bf00 NOP +000164 e751 B |L9.10| +;;;218 void bsp_ToogleDispMode(void) + ENDP + +000166 0000 DCW 0x0000 + |L9.360| + DCD 0x40011000 + |L9.364| + DCD 0x40011414 + |L9.368| + DCD g_tube_table + |L9.372| + DCD g_tTube + + AREA ||i.bsp_UpdateDisplayBuf||, CODE, READONLY, ALIGN=2 + + bsp_UpdateDisplayBuf PROC +;;;268 +;;;269 void bsp_UpdateDisplayBuf(void) +000000 b510 PUSH {r4,lr} +;;;270 { +;;;271 uint8_t i = 0; +000002 2400 MOVS r4,#0 +;;;272 +;;;273 // 开机或执行了搜索命令但未找到零点时的数码管显示状态 +;;;274 if ((g_tTube.state == IDLE) || (g_tTube.state == SEARCH)) +000004 4814 LDR r0,|L10.88| +000006 7ac0 LDRB r0,[r0,#0xb] ; g_tTube +000008 b118 CBZ r0,|L10.18| +00000a 4813 LDR r0,|L10.88| +00000c 7ac0 LDRB r0,[r0,#0xb] ; g_tTube +00000e 2802 CMP r0,#2 +000010 d11b BNE |L10.74| + |L10.18| +;;;275 { +;;;276 if (g_tTube.disp_mode == MODE_PULSE) // 数码管显示[--------] +000012 4811 LDR r0,|L10.88| +000014 7a40 LDRB r0,[r0,#9] ; g_tTube +000016 b928 CBNZ r0,|L10.36| +;;;277 { +;;;278 memset(g_tTube.buf, NO__, 8); +000018 220a MOVS r2,#0xa +00001a 2108 MOVS r1,#8 +00001c 480e LDR r0,|L10.88| +00001e f7fffffe BL __aeabi_memset +000022 e018 B |L10.86| + |L10.36| +;;;279 } +;;;280 else if (g_tTube.disp_mode == MODE_ANGLE) // 数码管显示[ -.--] +000024 480c LDR r0,|L10.88| +000026 7a40 LDRB r0,[r0,#9] ; g_tTube +000028 2801 CMP r0,#1 +00002a d114 BNE |L10.86| +;;;281 { +;;;282 for (i = 0; i < 5; i++) +00002c 2400 MOVS r4,#0 +00002e e004 B |L10.58| + |L10.48| +;;;283 { +;;;284 g_tTube.buf[i] = NO_NULL; +000030 200b MOVS r0,#0xb +000032 4909 LDR r1,|L10.88| +000034 5508 STRB r0,[r1,r4] +000036 1c60 ADDS r0,r4,#1 ;282 +000038 b2c4 UXTB r4,r0 ;282 + |L10.58| +00003a 2c05 CMP r4,#5 ;282 +00003c dbf8 BLT |L10.48| +;;;285 } +;;;286 g_tTube.buf[5] = NO__; +00003e 200a MOVS r0,#0xa +000040 4905 LDR r1,|L10.88| +000042 7148 STRB r0,[r1,#5] +;;;287 g_tTube.buf[6] = NO__; +000044 7188 STRB r0,[r1,#6] +;;;288 g_tTube.buf[7] = NO__; +000046 71c8 STRB r0,[r1,#7] +000048 e005 B |L10.86| + |L10.74| +;;;289 } +;;;290 } +;;;291 else if (g_tTube.state == WORK) // 已经找到零点后数码管的显示状态 +00004a 4803 LDR r0,|L10.88| +00004c 7ac0 LDRB r0,[r0,#0xb] ; g_tTube +00004e 2801 CMP r0,#1 +000050 d101 BNE |L10.86| +;;;292 { +;;;293 bsp_Angle2Buf(); // 数码管显示，例如[-1234567] +000052 f7fffffe BL bsp_Angle2Buf + |L10.86| +;;;294 } +;;;295 } +000056 bd10 POP {r4,pc} +;;;296 void bsp_Pulse2Buf(void) + ENDP + + |L10.88| + DCD g_tTube + + AREA ||.bss||, DATA, NOINIT, ALIGN=2 + + g_tTube + % 28 + + AREA ||.constdata||, DATA, READONLY, ALIGN=0 + + g_tube_table +000000 01010101 DCB 0x01,0x01,0x01,0x01 +000004 01010000 DCB 0x01,0x01,0x00,0x00 +000008 01010000 DCB 0x01,0x01,0x00,0x00 +00000c 00000101 DCB 0x00,0x00,0x01,0x01 +000010 00010100 DCB 0x00,0x01,0x01,0x00 +000014 01010101 DCB 0x01,0x01,0x01,0x01 +000018 01000001 DCB 0x01,0x00,0x00,0x01 +00001c 00010100 DCB 0x00,0x01,0x01,0x00 +000020 00010101 DCB 0x00,0x01,0x01,0x01 +000024 00010100 DCB 0x00,0x01,0x01,0x00 +000028 01010100 DCB 0x01,0x01,0x01,0x00 +00002c 01010101 DCB 0x01,0x01,0x01,0x01 +000030 01010101 DCB 0x01,0x01,0x01,0x01 +000034 00000000 DCB 0x00,0x00,0x00,0x00 +000038 01010101 DCB 0x01,0x01,0x01,0x01 +00003c 01010101 DCB 0x01,0x01,0x01,0x01 +000040 01010100 DCB 0x01,0x01,0x01,0x00 +000044 01010000 DCB 0x01,0x01,0x00,0x00 +000048 00000000 DCB 0x00,0x00,0x00,0x00 +00004c 01000000 DCB 0x01,0x00,0x00,0x00 +000050 00000000 DCB 0x00,0x00,0x00,0x00 + + AREA ||.data||, DATA, ALIGN=0 + + i +000000 00 DCB 0x00 + +;*** Start embedded assembler *** + +#line 1 "..\\..\\User\\bsp\\src\\bsp_digital_tube.c" + AREA ||.rev16_text||, CODE + THUMB + EXPORT |__asm___18_bsp_digital_tube_c_0f5ccf8f____REV16| +#line 114 "..\\..\\Libraries\\CMSIS\\Include\\core_cmInstr.h" +|__asm___18_bsp_digital_tube_c_0f5ccf8f____REV16| PROC +#line 115 + + rev16 r0, r0 + bx lr + ENDP + AREA ||.revsh_text||, CODE + THUMB + EXPORT |__asm___18_bsp_digital_tube_c_0f5ccf8f____REVSH| +#line 128 +|__asm___18_bsp_digital_tube_c_0f5ccf8f____REVSH| PROC +#line 129 + + revsh r0, r0 + bx lr + ENDP + +;*** End embedded assembler *** diff --git a/Project/MDK-ARM/Flash/List/bsp_drv8880.txt b/Project/MDK-ARM/Flash/List/bsp_drv8880.txt new file mode 100644 index 0000000..d6f9b38 --- /dev/null +++ b/Project/MDK-ARM/Flash/List/bsp_drv8880.txt @@ -0,0 +1,565 @@ +; generated by Component: ARM Compiler 5.06 update 7 (build 960) Tool: ArmCC [4d365d] +; commandline ArmCC [--list --split_sections --debug -c --asm --interleave -o.\flash\obj\bsp_drv8880.o --asm_dir=.\Flash\List\ --list_dir=.\Flash\List\ --depend=.\flash\obj\bsp_drv8880.d --cpu=Cortex-M3 --apcs=interwork -O0 --diag_suppress=9931,870 -I..\..\Libraries\CMSIS\Device\ST\STM32F10x\Include -I..\..\Libraries\STM32F10x_StdPeriph_Driver\inc -I..\..\Libraries\STM32_USB-FS-Device_Driver\inc -I..\..\Libraries\CMSIS\Include -I..\..\User\bsp -I..\..\User\bsp\inc -I..\..\User\app\inc -I..\..\User -IC:\Users\w1619\AppData\Local\Arm\Packs\Keil\STM32F1xx_DFP\2.4.1\Device\Include -D__MICROLIB -D__UVISION_VERSION=538 -DSTM32F10X_HD -DUSE_STDPERIPH_DRIVER -DSTM32F10X_HD --omf_browse=.\flash\obj\bsp_drv8880.crf ..\..\User\bsp\src\bsp_drv8880.c] + THUMB + + AREA ||i.bsp_Init_Drv8880_Hard||, CODE, READONLY, ALIGN=2 + + bsp_Init_Drv8880_Hard PROC +;;;191 +;;;192 void bsp_Init_Drv8880_Hard(void) +000000 b508 PUSH {r3,lr} +;;;193 { +;;;194 GPIO_InitTypeDef GPIO_InitStructure; +;;;195 +;;;196 RCC_APB2PeriphClockCmd(RCC_ALL_MOTO, ENABLE); +000002 2101 MOVS r1,#1 +000004 f44f70ac MOV r0,#0x158 +000008 f7fffffe BL RCC_APB2PeriphClockCmd +;;;197 +;;;198 GPIO_InitStructure.GPIO_Speed = GPIO_Speed_50MHz; +00000c 2003 MOVS r0,#3 +00000e f88d0002 STRB r0,[sp,#2] +;;;199 GPIO_InitStructure.GPIO_Mode = GPIO_Mode_Out_PP; +000012 2010 MOVS r0,#0x10 +000014 f88d0003 STRB r0,[sp,#3] +;;;200 +;;;201 // 配置自动整定引脚为高电平，设置为自动整定模式 +;;;202 GPIO_PORT_ATE->BSRR = GPIO_PIN_ATE; +000018 02c0 LSLS r0,r0,#11 +00001a 4940 LDR r1,|L1.284| +00001c 6008 STR r0,[r1,#0] +;;;203 GPIO_InitStructure.GPIO_Pin = GPIO_PIN_ATE; +00001e f8ad0000 STRH r0,[sp,#0] +;;;204 GPIO_Init(GPIO_PORT_ATE, &GPIO_InitStructure); +000022 4669 MOV r1,sp +000024 483d LDR r0,|L1.284| +000026 3810 SUBS r0,r0,#0x10 +000028 f7fffffe BL GPIO_Init +;;;205 +;;;206 // 配置脉冲输入引脚，设置为默认低电平 +;;;207 GPIO_InitStructure.GPIO_Pin = GPIO_PIN_STEP; +00002c 2080 MOVS r0,#0x80 +00002e f8ad0000 STRH r0,[sp,#0] +;;;208 GPIO_Init(GPIO_PORT_STEP, &GPIO_InitStructure); +000032 4669 MOV r1,sp +000034 483a LDR r0,|L1.288| +000036 f7fffffe BL GPIO_Init +;;;209 +;;;210 // 配置方向引脚，设置默认为低电平 +;;;211 GPIO_InitStructure.GPIO_Pin = GPIO_PIN_DIR; +00003a f44f6080 MOV r0,#0x400 +00003e f8ad0000 STRH r0,[sp,#0] +;;;212 GPIO_Init(GPIO_PORT_DIR, &GPIO_InitStructure); +000042 4669 MOV r1,sp +000044 4835 LDR r0,|L1.284| +000046 3810 SUBS r0,r0,#0x10 +000048 f7fffffe BL GPIO_Init +;;;213 +;;;214 // 配置使能引脚，设置默认为低电平，不使能 +;;;215 GPIO_InitStructure.GPIO_Pin = GPIO_PIN_ENABLE; +00004c f44f6000 MOV r0,#0x800 +000050 f8ad0000 STRH r0,[sp,#0] +;;;216 GPIO_Init(GPIO_PORT_ENABLE, &GPIO_InitStructure); +000054 4669 MOV r1,sp +000056 4831 LDR r0,|L1.284| +000058 3810 SUBS r0,r0,#0x10 +00005a f7fffffe BL GPIO_Init +;;;217 +;;;218 // 配置睡眠引脚，设置默认为低电平，处于睡眠状态 +;;;219 GPIO_InitStructure.GPIO_Pin = GPIO_PIN_SLEEP; +00005e f44f6000 MOV r0,#0x800 +000062 f8ad0000 STRH r0,[sp,#0] +;;;220 GPIO_Init(GPIO_PORT_SLEEP, &GPIO_InitStructure); +000066 4669 MOV r1,sp +000068 482e LDR r0,|L1.292| +00006a f7fffffe BL GPIO_Init +;;;221 +;;;222 // 配置细分引脚，设置默认为低电平，不细分 +;;;223 GPIO_InitStructure.GPIO_Pin = GPIO_PIN_M1; +00006e f44f7080 MOV r0,#0x100 +000072 f8ad0000 STRH r0,[sp,#0] +;;;224 GPIO_Init(GPIO_PORT_M1, &GPIO_InitStructure); +000076 4669 MOV r1,sp +000078 4828 LDR r0,|L1.284| +00007a 3810 SUBS r0,r0,#0x10 +00007c f7fffffe BL GPIO_Init +;;;225 GPIO_InitStructure.GPIO_Pin = GPIO_PIN_M0; +000080 2080 MOVS r0,#0x80 +000082 f8ad0000 STRH r0,[sp,#0] +;;;226 GPIO_Init(GPIO_PORT_M0, &GPIO_InitStructure); +000086 4669 MOV r1,sp +000088 4824 LDR r0,|L1.284| +00008a 3810 SUBS r0,r0,#0x10 +00008c f7fffffe BL GPIO_Init +;;;227 +;;;228 // 配置力矩引脚，设置默认为低电平，100%力矩 +;;;229 GPIO_InitStructure.GPIO_Pin = GPIO_PIN_TRQ1; +000090 2002 MOVS r0,#2 +000092 f8ad0000 STRH r0,[sp,#0] +;;;230 GPIO_Init(GPIO_PORT_TRQ1, &GPIO_InitStructure); +000096 4669 MOV r1,sp +000098 4823 LDR r0,|L1.296| +00009a f7fffffe BL GPIO_Init +;;;231 GPIO_InitStructure.GPIO_Pin = GPIO_PIN_TRQ0; +00009e 2001 MOVS r0,#1 +0000a0 f8ad0000 STRH r0,[sp,#0] +;;;232 GPIO_Init(GPIO_PORT_TRQ0, &GPIO_InitStructure); +0000a4 4669 MOV r1,sp +0000a6 4820 LDR r0,|L1.296| +0000a8 f7fffffe BL GPIO_Init +;;;233 +;;;234 // 设置衰减模式，设置默认为低电平，为slow decay模式 +;;;235 GPIO_InitStructure.GPIO_Pin = GPIO_PIN_DECAY1; +0000ac f44f5000 MOV r0,#0x2000 +0000b0 f8ad0000 STRH r0,[sp,#0] +;;;236 GPIO_Init(GPIO_PORT_DECAY1, &GPIO_InitStructure); +0000b4 4669 MOV r1,sp +0000b6 4819 LDR r0,|L1.284| +0000b8 3810 SUBS r0,r0,#0x10 +0000ba f7fffffe BL GPIO_Init +;;;237 GPIO_InitStructure.GPIO_Pin = GPIO_PIN_DECAY0; +0000be f44f5080 MOV r0,#0x1000 +0000c2 f8ad0000 STRH r0,[sp,#0] +;;;238 GPIO_Init(GPIO_PORT_DECAY0, &GPIO_InitStructure); +0000c6 4669 MOV r1,sp +0000c8 4814 LDR r0,|L1.284| +0000ca 3810 SUBS r0,r0,#0x10 +0000cc f7fffffe BL GPIO_Init +;;;239 +;;;240 // 设置fixed-off-time，设置默认为低电平，为20us +;;;241 GPIO_InitStructure.GPIO_Pin = GPIO_PIN_TOFF; +0000d0 f44f6080 MOV r0,#0x400 +0000d4 f8ad0000 STRH r0,[sp,#0] +;;;242 GPIO_Init(GPIO_PORT_TOFF, &GPIO_InitStructure); +0000d8 4669 MOV r1,sp +0000da 4812 LDR r0,|L1.292| +0000dc f7fffffe BL GPIO_Init +;;;243 +;;;244 // 设置报警输出引脚，设置为输入浮空模式 +;;;245 GPIO_InitStructure.GPIO_Mode = GPIO_Mode_IN_FLOATING; +0000e0 2004 MOVS r0,#4 +0000e2 f88d0003 STRB r0,[sp,#3] +;;;246 GPIO_InitStructure.GPIO_Pin = GPIO_PIN_FAULT; +0000e6 0300 LSLS r0,r0,#12 +0000e8 f8ad0000 STRH r0,[sp,#0] +;;;247 GPIO_Init(GPIO_PORT_FAULT, &GPIO_InitStructure); +0000ec 4669 MOV r1,sp +0000ee 480b LDR r0,|L1.284| +0000f0 3810 SUBS r0,r0,#0x10 +0000f2 f7fffffe BL GPIO_Init +;;;248 +;;;249 // 设置细分 +;;;250 bsp_drv8880_microstep_config(STEP_1_16); +0000f6 2005 MOVS r0,#5 +0000f8 f7fffffe BL bsp_drv8880_microstep_config +;;;251 +;;;252 // 方向设置 +;;;253 bsp_drv8880_config_dir(DIR_CCW); +0000fc 2001 MOVS r0,#1 +0000fe f7fffffe BL bsp_drv8880_config_dir +;;;254 +;;;255 // DA输出，步进电机电流设置 0.495V +;;;256 +;;;257 // 设置DA输出的电压为0.495V +;;;258 bsp_dev8880_vref_init_hard(1500); +000102 f24050dc MOV r0,#0x5dc +000106 f7fffffe BL bsp_dev8880_vref_init_hard +;;;259 +;;;260 // 退出睡眠模式 +;;;261 GPIO_PORT_SLEEP->BSRR = GPIO_PIN_SLEEP; +00010a f44f6000 MOV r0,#0x800 +00010e 4905 LDR r1,|L1.292| +000110 3110 ADDS r1,r1,#0x10 +000112 6008 STR r0,[r1,#0] +;;;262 +;;;263 // 暂时不使能，等待零点所搜命令 +;;;264 // bsp_drv8880_enable_config(DISABLE); +;;;265 bsp_drv8880_enable_config(ENABLE); +000114 2001 MOVS r0,#1 +000116 f7fffffe BL bsp_drv8880_enable_config +;;;266 } +00011a bd08 POP {r3,pc} +;;;267 + ENDP + + |L1.284| + DCD 0x40011810 + |L1.288| + DCD 0x40011000 + |L1.292| + DCD 0x40010c00 + |L1.296| + DCD 0x40012000 + + AREA ||i.bsp_dev8880_vref_init_hard||, CODE, READONLY, ALIGN=2 + + bsp_dev8880_vref_init_hard PROC +;;;160 // vol:0~3300,代表0~3.3V +;;;161 static void bsp_dev8880_vref_init_hard(uint16_t vol) +000000 e92d47f0 PUSH {r4-r10,lr} +;;;162 { +000004 b086 SUB sp,sp,#0x18 +000006 4604 MOV r4,r0 +;;;163 float temp = vol; +000008 4620 MOV r0,r4 +00000a f7fffffe BL __aeabi_ui2f +00000e 4681 MOV r9,r0 +;;;164 +;;;165 GPIO_InitTypeDef GPIO_InitStructure; +;;;166 DAC_InitTypeDef DAC_InitType; +;;;167 +;;;168 RCC_APB2PeriphClockCmd(RCC_APB2Periph_GPIOA, ENABLE); // 使能PORTA通道时钟 +000010 2101 MOVS r1,#1 +000012 2004 MOVS r0,#4 +000014 f7fffffe BL RCC_APB2PeriphClockCmd +;;;169 RCC_APB1PeriphClockCmd(RCC_APB1Periph_DAC, ENABLE); // 使能DAC通道时钟 +000018 2101 MOVS r1,#1 +00001a 0748 LSLS r0,r1,#29 +00001c f7fffffe BL RCC_APB1PeriphClockCmd +;;;170 +;;;171 GPIO_InitStructure.GPIO_Pin = GPIO_Pin_4; // 端口配置 +000020 2010 MOVS r0,#0x10 +000022 f8ad0014 STRH r0,[sp,#0x14] +;;;172 GPIO_InitStructure.GPIO_Mode = GPIO_Mode_AIN; // 模拟输入 +000026 2000 MOVS r0,#0 +000028 f88d0017 STRB r0,[sp,#0x17] +;;;173 GPIO_InitStructure.GPIO_Speed = GPIO_Speed_50MHz; +00002c 2003 MOVS r0,#3 +00002e f88d0016 STRB r0,[sp,#0x16] +;;;174 GPIO_Init(GPIOA, &GPIO_InitStructure); +000032 a905 ADD r1,sp,#0x14 +000034 481d LDR r0,|L2.172| +000036 f7fffffe BL GPIO_Init +;;;175 GPIO_SetBits(GPIOA, GPIO_Pin_4); // PA.4 输出高 +00003a 2110 MOVS r1,#0x10 +00003c 481b LDR r0,|L2.172| +00003e f7fffffe BL GPIO_SetBits +;;;176 +;;;177 DAC_InitType.DAC_Trigger = DAC_Trigger_None; // 不使用触发功能 TEN1=0 +000042 2000 MOVS r0,#0 +000044 9001 STR r0,[sp,#4] +;;;178 DAC_InitType.DAC_WaveGeneration = DAC_WaveGeneration_None; // 不使用波形发生 +000046 9002 STR r0,[sp,#8] +;;;179 DAC_InitType.DAC_LFSRUnmask_TriangleAmplitude = DAC_LFSRUnmask_Bit0; // 屏蔽、幅值设置 +000048 9003 STR r0,[sp,#0xc] +;;;180 DAC_InitType.DAC_OutputBuffer = DAC_OutputBuffer_Disable; // DAC1输出缓存关闭 BOFF1=1 +00004a 2002 MOVS r0,#2 +00004c 9004 STR r0,[sp,#0x10] +;;;181 DAC_Init(DAC_Channel_1, &DAC_InitType); // 初始化DAC通道1 +00004e a901 ADD r1,sp,#4 +000050 2000 MOVS r0,#0 +000052 f7fffffe BL DAC_Init +;;;182 +;;;183 DAC_Cmd(DAC_Channel_1, ENABLE); // 使能DAC1 +000056 2101 MOVS r1,#1 +000058 2000 MOVS r0,#0 +00005a f7fffffe BL DAC_Cmd +;;;184 +;;;185 DAC_SetChannel1Data(DAC_Align_12b_R, 0); // 12位右对齐数据格式设置DAC值 +00005e 2100 MOVS r1,#0 +000060 4608 MOV r0,r1 +000062 f7fffffe BL DAC_SetChannel1Data +;;;186 +;;;187 temp /= 1000; +000066 4912 LDR r1,|L2.176| +000068 4648 MOV r0,r9 +00006a f7fffffe BL __aeabi_fdiv +00006e 4681 MOV r9,r0 +;;;188 temp = temp * 4096 / 3.3; +000070 f04f418b MOV r1,#0x45800000 +000074 4648 MOV r0,r9 +000076 f7fffffe BL __aeabi_fmul +00007a 4682 MOV r10,r0 +00007c f7fffffe BL __aeabi_f2d +000080 4607 MOV r7,r0 +000082 f04f3266 MOV r2,#0x66666666 +000086 4b0b LDR r3,|L2.180| +000088 f7fffffe BL __aeabi_ddiv +00008c 4605 MOV r5,r0 +00008e f7fffffe BL __aeabi_d2f +000092 4681 MOV r9,r0 +;;;189 DAC_SetChannel1Data(DAC_Align_12b_R, temp); // 12位右对齐数据格式设置DAC值 +000094 4648 MOV r0,r9 +000096 f7fffffe BL __aeabi_f2uiz +00009a b285 UXTH r5,r0 +00009c 4629 MOV r1,r5 +00009e 2000 MOVS r0,#0 +0000a0 f7fffffe BL DAC_SetChannel1Data +;;;190 } +0000a4 b006 ADD sp,sp,#0x18 +0000a6 e8bd87f0 POP {r4-r10,pc} +;;;191 + ENDP + +0000aa 0000 DCW 0x0000 + |L2.172| + DCD 0x40010800 + |L2.176| + DCD 0x447a0000 + |L2.180| + DCD 0x400a6666 + + AREA ||i.bsp_drv8880_config_dir||, CODE, READONLY, ALIGN=2 + + bsp_drv8880_config_dir PROC +;;;131 } +;;;132 void bsp_drv8880_config_dir(DIR_E dir) +000000 b110 CBZ r0,|L3.8| +;;;133 { +;;;134 switch (dir) +000002 2801 CMP r0,#1 +000004 d111 BNE |L3.42| +000006 e007 B |L3.24| + |L3.8| +;;;135 { +;;;136 case DIR_CW: +;;;137 DRV8880_CW; +000008 f44f6180 MOV r1,#0x400 +00000c 4a08 LDR r2,|L3.48| +00000e 6011 STR r1,[r2,#0] +;;;138 g_tTube.dir = DIR_CW; +000010 2100 MOVS r1,#0 +000012 4a08 LDR r2,|L3.52| +000014 7311 STRB r1,[r2,#0xc] +;;;139 break; +000016 e009 B |L3.44| + |L3.24| +;;;140 case DIR_CCW: +;;;141 DRV8880_CCW; +000018 f44f6180 MOV r1,#0x400 +00001c 4a04 LDR r2,|L3.48| +00001e 1f12 SUBS r2,r2,#4 +000020 6011 STR r1,[r2,#0] +;;;142 g_tTube.dir = DIR_CCW; +000022 2101 MOVS r1,#1 +000024 4a03 LDR r2,|L3.52| +000026 7311 STRB r1,[r2,#0xc] +;;;143 break; +000028 e000 B |L3.44| + |L3.42| +;;;144 default: +;;;145 break; +00002a bf00 NOP + |L3.44| +00002c bf00 NOP ;139 +;;;146 } +;;;147 } +00002e 4770 BX lr +;;;148 void bsp_drv8880_enable_config(FunctionalState en) + ENDP + + |L3.48| + DCD 0x40011814 + |L3.52| + DCD g_tTube + + AREA ||i.bsp_drv8880_enable_config||, CODE, READONLY, ALIGN=2 + + bsp_drv8880_enable_config PROC +;;;147 } +;;;148 void bsp_drv8880_enable_config(FunctionalState en) +000000 b920 CBNZ r0,|L4.12| +;;;149 { +;;;150 if (en == DISABLE) +;;;151 { +;;;152 DRV8880_DISABLE; +000002 f44f6100 MOV r1,#0x800 +000006 4a04 LDR r2,|L4.24| +000008 6011 STR r1,[r2,#0] +00000a e004 B |L4.22| + |L4.12| +;;;153 } +;;;154 else +;;;155 { +;;;156 DRV8880_ENABLE; +00000c f44f6100 MOV r1,#0x800 +000010 4a01 LDR r2,|L4.24| +000012 1f12 SUBS r2,r2,#4 +000014 6011 STR r1,[r2,#0] + |L4.22| +;;;157 } +;;;158 } +000016 4770 BX lr +;;;159 + ENDP + + |L4.24| + DCD 0x40011814 + + AREA ||i.bsp_drv8880_microstep_config||, CODE, READONLY, ALIGN=2 + + bsp_drv8880_microstep_config PROC +;;;95 +;;;96 void bsp_drv8880_microstep_config(MICRO_STEPPING_E step) +000000 2806 CMP r0,#6 +;;;97 { +;;;98 switch (step) +000002 d26f BCS |L5.228| +000004 e8dff000 TBB [pc,r0] +000008 0315283b DCB 0x03,0x15,0x28,0x3b +00000c 4d5d DCB 0x4d,0x5d +;;;99 { +;;;100 case STEP_FULL: // M1M0: 00 +;;;101 M0_SET_AS_OUTPUT(); +00000e 4937 LDR r1,|L5.236| +000010 6809 LDR r1,[r1,#0] +000012 f0214170 BIC r1,r1,#0xf0000000 +000016 4a35 LDR r2,|L5.236| +000018 6011 STR r1,[r2,#0] +00001a 4611 MOV r1,r2 +00001c 6809 LDR r1,[r1,#0] +00001e f0415140 ORR r1,r1,#0x30000000 +000022 6011 STR r1,[r2,#0] +;;;102 M1_DISABLE; +000024 1591 ASRS r1,r2,#22 +000026 4a31 LDR r2,|L5.236| +000028 3214 ADDS r2,r2,#0x14 +00002a 6011 STR r1,[r2,#0] +;;;103 M0_DISABLE; +00002c 2180 MOVS r1,#0x80 +00002e 6011 STR r1,[r2,#0] +;;;104 break; +000030 e059 B |L5.230| +;;;105 case STEP_1_2_NC: // M1M0: 01 +;;;106 M0_SET_AS_OUTPUT(); +000032 492e LDR r1,|L5.236| +000034 6809 LDR r1,[r1,#0] +000036 f0214170 BIC r1,r1,#0xf0000000 +00003a 4a2c LDR r2,|L5.236| +00003c 6011 STR r1,[r2,#0] +00003e 4611 MOV r1,r2 +000040 6809 LDR r1,[r1,#0] +000042 f0415140 ORR r1,r1,#0x30000000 +000046 6011 STR r1,[r2,#0] +;;;107 M1_DISABLE; +000048 1591 ASRS r1,r2,#22 +00004a 4a28 LDR r2,|L5.236| +00004c 3214 ADDS r2,r2,#0x14 +00004e 6011 STR r1,[r2,#0] +;;;108 M0_ENABLE; +000050 2180 MOVS r1,#0x80 +000052 1f12 SUBS r2,r2,#4 +000054 6011 STR r1,[r2,#0] +;;;109 break; +000056 e046 B |L5.230| +;;;110 case STEP_1_2: // M1M0: 10 +;;;111 M0_SET_AS_OUTPUT(); +000058 4924 LDR r1,|L5.236| +00005a 6809 LDR r1,[r1,#0] +00005c f0214170 BIC r1,r1,#0xf0000000 +000060 4a22 LDR r2,|L5.236| +000062 6011 STR r1,[r2,#0] +000064 4611 MOV r1,r2 +000066 6809 LDR r1,[r1,#0] +000068 f0415140 ORR r1,r1,#0x30000000 +00006c 6011 STR r1,[r2,#0] +;;;112 M1_ENABLE; +00006e 1591 ASRS r1,r2,#22 +000070 4a1e LDR r2,|L5.236| +000072 3210 ADDS r2,r2,#0x10 +000074 6011 STR r1,[r2,#0] +;;;113 M0_DISABLE; +000076 2180 MOVS r1,#0x80 +000078 1d12 ADDS r2,r2,#4 +00007a 6011 STR r1,[r2,#0] +;;;114 break; +00007c e033 B |L5.230| +;;;115 case STEP_1_4: // M1M0: 11 +;;;116 M0_SET_AS_OUTPUT(); +00007e 491b LDR r1,|L5.236| +000080 6809 LDR r1,[r1,#0] +000082 f0214170 BIC r1,r1,#0xf0000000 +000086 4a19 LDR r2,|L5.236| +000088 6011 STR r1,[r2,#0] +00008a 4611 MOV r1,r2 +00008c 6809 LDR r1,[r1,#0] +00008e f0415140 ORR r1,r1,#0x30000000 +000092 6011 STR r1,[r2,#0] +;;;117 M1_ENABLE; +000094 1591 ASRS r1,r2,#22 +000096 4a15 LDR r2,|L5.236| +000098 3210 ADDS r2,r2,#0x10 +00009a 6011 STR r1,[r2,#0] +;;;118 M0_ENABLE; +00009c 2180 MOVS r1,#0x80 +00009e 6011 STR r1,[r2,#0] +;;;119 break; +0000a0 e021 B |L5.230| +;;;120 case STEP_1_8: // M1M0: 0Z +;;;121 M0_SET_AS_INPUT(); +0000a2 4912 LDR r1,|L5.236| +0000a4 6809 LDR r1,[r1,#0] +0000a6 f0214170 BIC r1,r1,#0xf0000000 +0000aa 4a10 LDR r2,|L5.236| +0000ac 6011 STR r1,[r2,#0] +0000ae 4611 MOV r1,r2 +0000b0 6809 LDR r1,[r1,#0] +0000b2 f0414180 ORR r1,r1,#0x40000000 +0000b6 6011 STR r1,[r2,#0] +;;;122 M1_DISABLE; +0000b8 1591 ASRS r1,r2,#22 +0000ba 4a0c LDR r2,|L5.236| +0000bc 3214 ADDS r2,r2,#0x14 +0000be 6011 STR r1,[r2,#0] +;;;123 break; +0000c0 e011 B |L5.230| +;;;124 case STEP_1_16: // M1M0: 1Z +;;;125 M0_SET_AS_INPUT(); +0000c2 490a LDR r1,|L5.236| +0000c4 6809 LDR r1,[r1,#0] +0000c6 f0214170 BIC r1,r1,#0xf0000000 +0000ca 4a08 LDR r2,|L5.236| +0000cc 6011 STR r1,[r2,#0] +0000ce 4611 MOV r1,r2 +0000d0 6809 LDR r1,[r1,#0] +0000d2 f0414180 ORR r1,r1,#0x40000000 +0000d6 6011 STR r1,[r2,#0] +;;;126 M1_ENABLE; +0000d8 1591 ASRS r1,r2,#22 +0000da 4a04 LDR r2,|L5.236| +0000dc 3210 ADDS r2,r2,#0x10 +0000de 6011 STR r1,[r2,#0] +;;;127 break; +0000e0 e001 B |L5.230| +0000e2 e7ff B |L5.228| + |L5.228| +;;;128 default: +;;;129 break; +0000e4 bf00 NOP + |L5.230| +0000e6 bf00 NOP ;104 +;;;130 } +;;;131 } +0000e8 4770 BX lr +;;;132 void bsp_drv8880_config_dir(DIR_E dir) + ENDP + +0000ea 0000 DCW 0x0000 + |L5.236| + DCD 0x40011800 + +;*** Start embedded assembler *** + +#line 1 "..\\..\\User\\bsp\\src\\bsp_drv8880.c" + AREA ||.rev16_text||, CODE + THUMB + EXPORT |__asm___13_bsp_drv8880_c_b3f300ed____REV16| +#line 114 "..\\..\\Libraries\\CMSIS\\Include\\core_cmInstr.h" +|__asm___13_bsp_drv8880_c_b3f300ed____REV16| PROC +#line 115 + + rev16 r0, r0 + bx lr + ENDP + AREA ||.revsh_text||, CODE + THUMB + EXPORT |__asm___13_bsp_drv8880_c_b3f300ed____REVSH| +#line 128 +|__asm___13_bsp_drv8880_c_b3f300ed____REVSH| PROC +#line 129 + + revsh r0, r0 + bx lr + ENDP + +;*** End embedded assembler *** diff --git a/Project/MDK-ARM/Flash/List/bsp_eeprom_24xx.txt b/Project/MDK-ARM/Flash/List/bsp_eeprom_24xx.txt new file mode 100644 index 0000000..c184eda --- /dev/null +++ b/Project/MDK-ARM/Flash/List/bsp_eeprom_24xx.txt @@ -0,0 +1,367 @@ +; generated by Component: ARM Compiler 5.06 update 7 (build 960) Tool: ArmCC [4d365d] +; commandline ArmCC [--list --split_sections --debug -c --asm --interleave -o.\flash\obj\bsp_eeprom_24xx.o --asm_dir=.\Flash\List\ --list_dir=.\Flash\List\ --depend=.\flash\obj\bsp_eeprom_24xx.d --cpu=Cortex-M3 --apcs=interwork -O0 --diag_suppress=9931,870 -I..\..\Libraries\CMSIS\Device\ST\STM32F10x\Include -I..\..\Libraries\STM32F10x_StdPeriph_Driver\inc -I..\..\Libraries\STM32_USB-FS-Device_Driver\inc -I..\..\Libraries\CMSIS\Include -I..\..\User\bsp -I..\..\User\bsp\inc -I..\..\User\app\inc -I..\..\User -IC:\Users\w1619\AppData\Local\Arm\Packs\Keil\STM32F1xx_DFP\2.4.1\Device\Include -D__MICROLIB -D__UVISION_VERSION=538 -DSTM32F10X_HD -DUSE_STDPERIPH_DRIVER -DSTM32F10X_HD --omf_browse=.\flash\obj\bsp_eeprom_24xx.crf ..\..\User\bsp\src\bsp_eeprom_24xx.c] + THUMB + + AREA ||i.ee_CheckOk||, CODE, READONLY, ALIGN=1 + + ee_CheckOk PROC +;;;32 */ +;;;33 uint8_t ee_CheckOk(void) +000000 b510 PUSH {r4,lr} +;;;34 { +;;;35 if (i2c_CheckDevice(EE_DEV_ADDR) == 0) +000002 20a0 MOVS r0,#0xa0 +000004 f7fffffe BL i2c_CheckDevice +000008 b908 CBNZ r0,|L1.14| +;;;36 { +;;;37 return 1; +00000a 2001 MOVS r0,#1 + |L1.12| +;;;38 } +;;;39 else +;;;40 { +;;;41 /* 失败后，切记发送I2C总线停止信号 */ +;;;42 i2c_Stop(); +;;;43 return 0; +;;;44 } +;;;45 } +00000c bd10 POP {r4,pc} + |L1.14| +00000e f7fffffe BL i2c_Stop +000012 2000 MOVS r0,#0 ;43 +000014 e7fa B |L1.12| +;;;46 + ENDP + + + AREA ||i.ee_ReadBytes||, CODE, READONLY, ALIGN=1 + + ee_ReadBytes PROC +;;;56 */ +;;;57 uint8_t ee_ReadBytes(uint8_t *_pReadBuf, uint16_t _usAddress, uint16_t _usSize) +000000 e92d41f0 PUSH {r4-r8,lr} +;;;58 { +000004 4607 MOV r7,r0 +000006 460d MOV r5,r1 +000008 4616 MOV r6,r2 +;;;59 uint16_t i; +;;;60 +;;;61 /* 采用串行EEPROM随即读取指令序列，连续读取若干字节 */ +;;;62 +;;;63 /* 第1步：发起I2C总线启动信号 */ +;;;64 i2c_Start(); +00000a f7fffffe BL i2c_Start +;;;65 +;;;66 /* 第2步：发起控制字节，高7bit是地址，bit0是读写控制位，0表示写，1表示读 */ +;;;67 i2c_SendByte(EE_DEV_ADDR | I2C_WR); /* 此处是写指令 */ +00000e 20a0 MOVS r0,#0xa0 +000010 f7fffffe BL i2c_SendByte +;;;68 +;;;69 /* 第3步：发送ACK */ +;;;70 if (i2c_WaitAck() != 0) +000014 f7fffffe BL i2c_WaitAck +000018 b100 CBZ r0,|L2.28| +;;;71 { +;;;72 goto cmd_fail; /* EEPROM器件无应答 */ +00001a e02c B |L2.118| + |L2.28| +;;;73 } +;;;74 +;;;75 /* 第4步：发送字节地址，24C02只有256字节，因此1个字节就够了，如果是24C04以上，那么此处需要连发多个地址 */ +;;;76 if (EE_ADDR_BYTES == 1) +;;;77 { +;;;78 i2c_SendByte((uint8_t)_usAddress); +;;;79 if (i2c_WaitAck() != 0) +;;;80 { +;;;81 goto cmd_fail; /* EEPROM器件无应答 */ +;;;82 } +;;;83 } +;;;84 else +;;;85 { +;;;86 i2c_SendByte(_usAddress >> 8); +00001c 1228 ASRS r0,r5,#8 +00001e f7fffffe BL i2c_SendByte +;;;87 if (i2c_WaitAck() != 0) +000022 f7fffffe BL i2c_WaitAck +000026 b100 CBZ r0,|L2.42| +;;;88 { +;;;89 goto cmd_fail; /* EEPROM器件无应答 */ +000028 e025 B |L2.118| + |L2.42| +;;;90 } +;;;91 +;;;92 i2c_SendByte(_usAddress); +00002a b2e8 UXTB r0,r5 +00002c f7fffffe BL i2c_SendByte +;;;93 if (i2c_WaitAck() != 0) +000030 f7fffffe BL i2c_WaitAck +000034 b100 CBZ r0,|L2.56| +;;;94 { +;;;95 goto cmd_fail; /* EEPROM器件无应答 */ +000036 e01e B |L2.118| + |L2.56| +;;;96 } +;;;97 } +;;;98 +;;;99 /* 第6步：重新启动I2C总线。下面开始读取数据 */ +;;;100 i2c_Start(); +000038 f7fffffe BL i2c_Start +;;;101 +;;;102 /* 第7步：发起控制字节，高7bit是地址，bit0是读写控制位，0表示写，1表示读 */ +;;;103 i2c_SendByte(EE_DEV_ADDR | I2C_RD); /* 此处是读指令 */ +00003c 20a1 MOVS r0,#0xa1 +00003e f7fffffe BL i2c_SendByte +;;;104 +;;;105 /* 第8步：发送ACK */ +;;;106 if (i2c_WaitAck() != 0) +000042 f7fffffe BL i2c_WaitAck +000046 b100 CBZ r0,|L2.74| +;;;107 { +;;;108 goto cmd_fail; /* EEPROM器件无应答 */ +000048 e015 B |L2.118| + |L2.74| +;;;109 } +;;;110 +;;;111 /* 第9步：循环读取数据 */ +;;;112 for (i = 0; i < _usSize; i++) +00004a 2400 MOVS r4,#0 +00004c e00c B |L2.104| + |L2.78| +;;;113 { +;;;114 _pReadBuf[i] = i2c_ReadByte(); /* 读1个字节 */ +00004e f7fffffe BL i2c_ReadByte +000052 5538 STRB r0,[r7,r4] +;;;115 +;;;116 /* 每读完1个字节后，需要发送Ack， 最后一个字节不需要Ack，发Nack */ +;;;117 if (i != _usSize - 1) +000054 1e70 SUBS r0,r6,#1 +000056 42a0 CMP r0,r4 +000058 d002 BEQ |L2.96| +;;;118 { +;;;119 i2c_Ack(); /* 中间字节读完后，CPU产生ACK信号(驱动SDA = 0) */ +00005a f7fffffe BL i2c_Ack +00005e e001 B |L2.100| + |L2.96| +;;;120 } +;;;121 else +;;;122 { +;;;123 i2c_NAck(); /* 最后1个字节读完后，CPU产生NACK信号(驱动SDA = 1) */ +000060 f7fffffe BL i2c_NAck + |L2.100| +000064 1c60 ADDS r0,r4,#1 ;112 +000066 b284 UXTH r4,r0 ;112 + |L2.104| +000068 42b4 CMP r4,r6 ;112 +00006a dbf0 BLT |L2.78| +;;;124 } +;;;125 } +;;;126 /* 发送I2C总线停止信号 */ +;;;127 i2c_Stop(); +00006c f7fffffe BL i2c_Stop +;;;128 return 1; /* 执行成功 */ +000070 2001 MOVS r0,#1 + |L2.114| +;;;129 +;;;130 cmd_fail: /* 命令执行失败后，切记发送停止信号，避免影响I2C总线上其他设备 */ +;;;131 /* 发送I2C总线停止信号 */ +;;;132 i2c_Stop(); +;;;133 return 0; +;;;134 } +000072 e8bd81f0 POP {r4-r8,pc} + |L2.118| +000076 f7fffffe BL i2c_Stop +00007a 2000 MOVS r0,#0 ;133 +00007c e7f9 B |L2.114| +;;;135 + ENDP + + + AREA ||i.ee_WriteBytes||, CODE, READONLY, ALIGN=1 + + ee_WriteBytes PROC +;;;145 */ +;;;146 uint8_t ee_WriteBytes(uint8_t *_pWriteBuf, uint16_t _usAddress, uint16_t _usSize) +000000 e92d47f0 PUSH {r4-r10,lr} +;;;147 { +000004 4607 MOV r7,r0 +000006 4688 MOV r8,r1 +000008 4691 MOV r9,r2 +;;;148 uint16_t i, m; +;;;149 uint16_t usAddr; +;;;150 +;;;151 /* +;;;152 写串行EEPROM不像读操作可以连续读取很多字节，每次写操作只能在同一个page。 +;;;153 对于24xx02，page size = 8 +;;;154 简单的处理方法为：按字节写操作模式，每写1个字节，都发送地址 +;;;155 为了提高连续写的效率: 本函数采用page wirte操作。 +;;;156 */ +;;;157 +;;;158 usAddr = _usAddress; +00000a 4645 MOV r5,r8 +;;;159 for (i = 0; i < _usSize; i++) +00000c 2400 MOVS r4,#0 +00000e e033 B |L3.120| + |L3.16| +;;;160 { +;;;161 /* 当发送第1个字节或是页面首地址时，需要重新发起启动信号和地址 */ +;;;162 if ((i == 0) || (usAddr & (EE_PAGE_SIZE - 1)) == 0) +000010 b114 CBZ r4,|L3.24| +000012 f005003f AND r0,r5,#0x3f +000016 bb20 CBNZ r0,|L3.98| + |L3.24| +;;;163 { +;;;164 /*　第０步：发停止信号，启动内部写操作　*/ +;;;165 i2c_Stop(); +000018 f7fffffe BL i2c_Stop +;;;166 +;;;167 /* 通过检查器件应答的方式，判断内部写操作是否完成, 一般小于 10ms +;;;168 CLK频率为200KHz时，查询次数为30次左右 +;;;169 */ +;;;170 for (m = 0; m < 1000; m++) +00001c 2600 MOVS r6,#0 +00001e e00a B |L3.54| + |L3.32| +;;;171 { +;;;172 /* 第1步：发起I2C总线启动信号 */ +;;;173 i2c_Start(); +000020 f7fffffe BL i2c_Start +;;;174 +;;;175 /* 第2步：发起控制字节，高7bit是地址，bit0是读写控制位，0表示写，1表示读 */ +;;;176 i2c_SendByte(EE_DEV_ADDR | I2C_WR); /* 此处是写指令 */ +000024 20a0 MOVS r0,#0xa0 +000026 f7fffffe BL i2c_SendByte +;;;177 +;;;178 /* 第3步：发送一个时钟，判断器件是否正确应答 */ +;;;179 if (i2c_WaitAck() == 0) +00002a f7fffffe BL i2c_WaitAck +00002e b900 CBNZ r0,|L3.50| +;;;180 { +;;;181 break; +000030 e004 B |L3.60| + |L3.50| +000032 1c70 ADDS r0,r6,#1 ;170 +000034 b286 UXTH r6,r0 ;170 + |L3.54| +000036 f5b67f7a CMP r6,#0x3e8 ;170 +00003a dbf1 BLT |L3.32| + |L3.60| +00003c bf00 NOP +;;;182 } +;;;183 } +;;;184 if (m == 1000) +00003e f5b67f7a CMP r6,#0x3e8 +000042 d100 BNE |L3.70| +;;;185 { +;;;186 goto cmd_fail; /* EEPROM器件写超时 */ +000044 e01f B |L3.134| + |L3.70| +;;;187 } +;;;188 +;;;189 /* 第4步：发送字节地址，24C02只有256字节，因此1个字节就够了，如果是24C04以上，那么此处需要连发多个地址 */ +;;;190 if (EE_ADDR_BYTES == 1) +;;;191 { +;;;192 i2c_SendByte((uint8_t)usAddr); +;;;193 if (i2c_WaitAck() != 0) +;;;194 { +;;;195 goto cmd_fail; /* EEPROM器件无应答 */ +;;;196 } +;;;197 } +;;;198 else +;;;199 { +;;;200 i2c_SendByte(usAddr >> 8); +000046 1228 ASRS r0,r5,#8 +000048 f7fffffe BL i2c_SendByte +;;;201 if (i2c_WaitAck() != 0) +00004c f7fffffe BL i2c_WaitAck +000050 b100 CBZ r0,|L3.84| +;;;202 { +;;;203 goto cmd_fail; /* EEPROM器件无应答 */ +000052 e018 B |L3.134| + |L3.84| +;;;204 } +;;;205 +;;;206 i2c_SendByte(usAddr); +000054 b2e8 UXTB r0,r5 +000056 f7fffffe BL i2c_SendByte +;;;207 if (i2c_WaitAck() != 0) +00005a f7fffffe BL i2c_WaitAck +00005e b100 CBZ r0,|L3.98| +;;;208 { +;;;209 goto cmd_fail; /* EEPROM器件无应答 */ +000060 e011 B |L3.134| + |L3.98| +;;;210 } +;;;211 } +;;;212 } +;;;213 +;;;214 /* 第6步：开始写入数据 */ +;;;215 i2c_SendByte(_pWriteBuf[i]); +000062 5d38 LDRB r0,[r7,r4] +000064 f7fffffe BL i2c_SendByte +;;;216 +;;;217 /* 第7步：发送ACK */ +;;;218 if (i2c_WaitAck() != 0) +000068 f7fffffe BL i2c_WaitAck +00006c b100 CBZ r0,|L3.112| +;;;219 { +;;;220 goto cmd_fail; /* EEPROM器件无应答 */ +00006e e00a B |L3.134| + |L3.112| +;;;221 } +;;;222 +;;;223 usAddr++; /* 地址增1 */ +000070 1c68 ADDS r0,r5,#1 +000072 b285 UXTH r5,r0 +000074 1c60 ADDS r0,r4,#1 ;159 +000076 b284 UXTH r4,r0 ;159 + |L3.120| +000078 454c CMP r4,r9 ;159 +00007a dbc9 BLT |L3.16| +;;;224 } +;;;225 +;;;226 /* 命令执行成功，发送I2C总线停止信号 */ +;;;227 i2c_Stop(); +00007c f7fffffe BL i2c_Stop +;;;228 return 1; +000080 2001 MOVS r0,#1 + |L3.130| +;;;229 +;;;230 cmd_fail: /* 命令执行失败后，切记发送停止信号，避免影响I2C总线上其他设备 */ +;;;231 /* 发送I2C总线停止信号 */ +;;;232 i2c_Stop(); +;;;233 return 0; +;;;234 } +000082 e8bd87f0 POP {r4-r10,pc} + |L3.134| +000086 f7fffffe BL i2c_Stop +00008a 2000 MOVS r0,#0 ;233 +00008c e7f9 B |L3.130| +;;;235 + ENDP + + +;*** Start embedded assembler *** + +#line 1 "..\\..\\User\\bsp\\src\\bsp_eeprom_24xx.c" + AREA ||.rev16_text||, CODE + THUMB + EXPORT |__asm___17_bsp_eeprom_24xx_c_4eb00f1b____REV16| +#line 114 "..\\..\\Libraries\\CMSIS\\Include\\core_cmInstr.h" +|__asm___17_bsp_eeprom_24xx_c_4eb00f1b____REV16| PROC +#line 115 + + rev16 r0, r0 + bx lr + ENDP + AREA ||.revsh_text||, CODE + THUMB + EXPORT |__asm___17_bsp_eeprom_24xx_c_4eb00f1b____REVSH| +#line 128 +|__asm___17_bsp_eeprom_24xx_c_4eb00f1b____REVSH| PROC +#line 129 + + revsh r0, r0 + bx lr + ENDP + +;*** End embedded assembler *** diff --git a/Project/MDK-ARM/Flash/List/bsp_fpga_power.txt b/Project/MDK-ARM/Flash/List/bsp_fpga_power.txt new file mode 100644 index 0000000..0b35c8e --- /dev/null +++ b/Project/MDK-ARM/Flash/List/bsp_fpga_power.txt @@ -0,0 +1,158 @@ +; generated by Component: ARM Compiler 5.05 update 1 (build 106) Tool: ArmCC [4d0efa] +; commandline ArmCC [--list --split_sections --debug -c --asm --interleave -o.\flash\obj\bsp_fpga_power.o --asm_dir=.\Flash\List\ --list_dir=.\Flash\List\ --depend=.\flash\obj\bsp_fpga_power.d --cpu=Cortex-M3 --apcs=interwork -O0 --diag_suppress=9931,870 -I..\..\Libraries\CMSIS\Device\ST\STM32F10x\Include -I..\..\Libraries\STM32F10x_StdPeriph_Driver\inc -I..\..\Libraries\STM32_USB-FS-Device_Driver\inc -I..\..\Libraries\CMSIS\Include -I..\..\User\bsp -I..\..\User\bsp\inc -I..\..\User\app\inc -IC:\Keil_v5\ARM\RV31\INC -IC:\Keil_v5\ARM\CMSIS\Include -IC:\Keil_v5\ARM\Inc\ST\STM32F10x -D__MICROLIB -D__UVISION_VERSION=514 -DUSE_STDPERIPH_DRIVER -DSTM32F10X_HD --omf_browse=.\flash\obj\bsp_fpga_power.crf ..\..\User\bsp\src\bsp_fpga_power.c] + THUMB + + AREA ||i.bsp_FpgaPowerCmd||, CODE, READONLY, ALIGN=2 + + bsp_FpgaPowerCmd PROC +;;;53 //------------------------------------------------------------------------------ +;;;54 void bsp_FpgaPowerCmd(FunctionalState _NewState) +000000 2801 CMP r0,#1 +;;;55 { +;;;56 if(_NewState==ENABLE) +000002 d103 BNE |L1.12| +;;;57 { +;;;58 GPIO_PORT_PWR->BSRR = GPIO_PIN_PWR; +000004 0381 LSLS r1,r0,#14 +000006 4a05 LDR r2,|L1.28| +000008 6011 STR r1,[r2,#0] +00000a e005 B |L1.24| + |L1.12| +;;;59 } +;;;60 else if(_NewState==DISABLE) +00000c b920 CBNZ r0,|L1.24| +;;;61 { +;;;62 GPIO_PORT_PWR->BRR = GPIO_PIN_PWR; +00000e f44f4180 MOV r1,#0x4000 +000012 4a02 LDR r2,|L1.28| +000014 1d12 ADDS r2,r2,#4 +000016 6011 STR r1,[r2,#0] + |L1.24| +;;;63 } +;;;64 } +000018 4770 BX lr +;;;65 + ENDP + +00001a 0000 DCW 0x0000 + |L1.28| + DCD 0x40011810 + + AREA ||i.bsp_FpgaPowerMainLoop||, CODE, READONLY, ALIGN=2 + + bsp_FpgaPowerMainLoop PROC +;;;71 //------------------------------------------------------------------------------ +;;;72 void bsp_FpgaPowerMainLoop(uint16_t _delay_n_10ms) +000000 b500 PUSH {lr} +;;;73 { +000002 4603 MOV r3,r0 +;;;74 static uint16_t cnt=0; +;;;75 if(!s_gucStartOk) +000004 4809 LDR r0,|L2.44| +000006 7800 LDRB r0,[r0,#0] ; s_gucStartOk +000008 b970 CBNZ r0,|L2.40| +;;;76 { +;;;77 if(++cnt>=_delay_n_10ms) +00000a 4809 LDR r0,|L2.48| +00000c 8800 LDRH r0,[r0,#0] ; cnt +00000e 1c40 ADDS r0,r0,#1 +000010 b280 UXTH r0,r0 +000012 4907 LDR r1,|L2.48| +000014 8008 STRH r0,[r1,#0] +000016 4298 CMP r0,r3 +000018 db06 BLT |L2.40| +;;;78 { +;;;79 cnt = 0; +00001a 2000 MOVS r0,#0 +00001c 8008 STRH r0,[r1,#0] +;;;80 s_gucStartOk = 1; +00001e 2001 MOVS r0,#1 +000020 4902 LDR r1,|L2.44| +000022 7008 STRB r0,[r1,#0] +;;;81 bsp_FpgaPowerCmd(ENABLE); +000024 f7fffffe BL bsp_FpgaPowerCmd + |L2.40| +;;;82 } +;;;83 } +;;;84 } +000028 bd00 POP {pc} +;;;85 + ENDP + +00002a 0000 DCW 0x0000 + |L2.44| + DCD s_gucStartOk + |L2.48| + DCD ||cnt|| + + AREA ||i.bsp_InitFpgaPower||, CODE, READONLY, ALIGN=2 + + bsp_InitFpgaPower PROC +;;;32 //------------------------------------------------------------------------------ +;;;33 void bsp_InitFpgaPower(void) +000000 b508 PUSH {r3,lr} +;;;34 { +;;;35 +;;;36 GPIO_InitTypeDef GPIO_InitStructure; +;;;37 +;;;38 // GPIOʱ +;;;39 RCC_APB2PeriphClockCmd(RCC_ALL_FPGA_POWER, ENABLE); +000002 2101 MOVS r1,#1 +000004 2040 MOVS r0,#0x40 +000006 f7fffffe BL RCC_APB2PeriphClockCmd +;;;40 +;;;41 GPIO_InitStructure.GPIO_Speed = GPIO_Speed_50MHz; +00000a 2003 MOVS r0,#3 +00000c f88d0002 STRB r0,[sp,#2] +;;;42 GPIO_InitStructure.GPIO_Mode = GPIO_Mode_Out_PP; // ģʽ +000010 2010 MOVS r0,#0x10 +000012 f88d0003 STRB r0,[sp,#3] +;;;43 +;;;44 GPIO_InitStructure.GPIO_Pin = GPIO_PIN_PWR; +000016 0280 LSLS r0,r0,#10 +000018 f8ad0000 STRH r0,[sp,#0] +;;;45 GPIO_Init(GPIO_PORT_PWR, &GPIO_InitStructure); +00001c 4669 MOV r1,sp +00001e 4802 LDR r0,|L3.40| +000020 f7fffffe BL GPIO_Init +;;;46 } +000024 bd08 POP {r3,pc} +;;;47 + ENDP + +000026 0000 DCW 0x0000 + |L3.40| + DCD 0x40011800 + + AREA ||.data||, DATA, ALIGN=1 + + s_gucStartOk +000000 0000 DCB 0x00,0x00 + ||cnt|| +000002 0000 DCW 0x0000 + +;*** Start embedded assembler *** + +#line 1 "..\\..\\User\\bsp\\src\\bsp_fpga_power.c" + AREA ||.rev16_text||, CODE + THUMB + EXPORT |__asm___16_bsp_fpga_power_c_e013a162____REV16| +#line 114 "..\\..\\Libraries\\CMSIS\\Include\\core_cmInstr.h" +|__asm___16_bsp_fpga_power_c_e013a162____REV16| PROC +#line 115 + + rev16 r0, r0 + bx lr + ENDP + AREA ||.revsh_text||, CODE + THUMB + EXPORT |__asm___16_bsp_fpga_power_c_e013a162____REVSH| +#line 128 +|__asm___16_bsp_fpga_power_c_e013a162____REVSH| PROC +#line 129 + + revsh r0, r0 + bx lr + ENDP + +;*** End embedded assembler *** diff --git a/Project/MDK-ARM/Flash/List/bsp_i2c_gpio.txt b/Project/MDK-ARM/Flash/List/bsp_i2c_gpio.txt new file mode 100644 index 0000000..772f22b --- /dev/null +++ b/Project/MDK-ARM/Flash/List/bsp_i2c_gpio.txt @@ -0,0 +1,505 @@ +; generated by Component: ARM Compiler 5.06 update 7 (build 960) Tool: ArmCC [4d365d] +; commandline ArmCC [--list --split_sections --debug -c --asm --interleave -o.\flash\obj\bsp_i2c_gpio.o --asm_dir=.\Flash\List\ --list_dir=.\Flash\List\ --depend=.\flash\obj\bsp_i2c_gpio.d --cpu=Cortex-M3 --apcs=interwork -O0 --diag_suppress=9931,870 -I..\..\Libraries\CMSIS\Device\ST\STM32F10x\Include -I..\..\Libraries\STM32F10x_StdPeriph_Driver\inc -I..\..\Libraries\STM32_USB-FS-Device_Driver\inc -I..\..\Libraries\CMSIS\Include -I..\..\User\bsp -I..\..\User\bsp\inc -I..\..\User\app\inc -I..\..\User -IC:\Users\w1619\AppData\Local\Arm\Packs\Keil\STM32F1xx_DFP\2.4.1\Device\Include -D__MICROLIB -D__UVISION_VERSION=538 -DSTM32F10X_HD -DUSE_STDPERIPH_DRIVER -DSTM32F10X_HD --omf_browse=.\flash\obj\bsp_i2c_gpio.crf ..\..\User\bsp\src\bsp_i2c_gpio.c] + THUMB + + AREA ||i.bsp_InitI2C||, CODE, READONLY, ALIGN=2 + + bsp_InitI2C PROC +;;;61 */ +;;;62 void bsp_InitI2C(void) +000000 b508 PUSH {r3,lr} +;;;63 { +;;;64 GPIO_InitTypeDef GPIO_InitStructure; +;;;65 +;;;66 RCC_APB2PeriphClockCmd(RCC_I2C_PORT, ENABLE); /* 打开GPIO时钟 */ +000002 2101 MOVS r1,#1 +000004 2008 MOVS r0,#8 +000006 f7fffffe BL RCC_APB2PeriphClockCmd +;;;67 +;;;68 GPIO_InitStructure.GPIO_Speed = GPIO_Speed_50MHz; +00000a 2003 MOVS r0,#3 +00000c f88d0002 STRB r0,[sp,#2] +;;;69 GPIO_InitStructure.GPIO_Mode = GPIO_Mode_Out_OD; /* 开漏输出模式 */ +000010 2014 MOVS r0,#0x14 +000012 f88d0003 STRB r0,[sp,#3] +;;;70 +;;;71 GPIO_InitStructure.GPIO_Pin = PIN_I2C_SCL; +000016 2040 MOVS r0,#0x40 +000018 f8ad0000 STRH r0,[sp,#0] +;;;72 GPIO_Init(PORT_I2C_SCL, &GPIO_InitStructure); +00001c 4669 MOV r1,sp +00001e 4806 LDR r0,|L1.56| +000020 f7fffffe BL GPIO_Init +;;;73 +;;;74 GPIO_InitStructure.GPIO_Pin = PIN_I2C_SDA; +000024 2080 MOVS r0,#0x80 +000026 f8ad0000 STRH r0,[sp,#0] +;;;75 GPIO_Init(PORT_I2C_SDA, &GPIO_InitStructure); +00002a 4669 MOV r1,sp +00002c 4802 LDR r0,|L1.56| +00002e f7fffffe BL GPIO_Init +;;;76 +;;;77 /* 给一个停止信号, 复位I2C总线上的所有设备到待机模式 */ +;;;78 i2c_Stop(); +000032 f7fffffe BL i2c_Stop +;;;79 } +000036 bd08 POP {r3,pc} +;;;80 + ENDP + + |L1.56| + DCD 0x40010c00 + + AREA ||i.i2c_Ack||, CODE, READONLY, ALIGN=2 + + i2c_Ack PROC +;;;248 */ +;;;249 void i2c_Ack(void) +000000 b510 PUSH {r4,lr} +;;;250 { +;;;251 I2C_SDA_0(); /* CPU驱动SDA = 0 */ +000002 2080 MOVS r0,#0x80 +000004 4909 LDR r1,|L2.44| +000006 6008 STR r0,[r1,#0] +;;;252 i2c_Delay(); +000008 f7fffffe BL i2c_Delay +;;;253 I2C_SCL_1(); /* CPU产生1个时钟 */ +00000c 2040 MOVS r0,#0x40 +00000e 4907 LDR r1,|L2.44| +000010 1f09 SUBS r1,r1,#4 +000012 6008 STR r0,[r1,#0] +;;;254 i2c_Delay(); +000014 f7fffffe BL i2c_Delay +;;;255 I2C_SCL_0(); +000018 2040 MOVS r0,#0x40 +00001a 4904 LDR r1,|L2.44| +00001c 6008 STR r0,[r1,#0] +;;;256 i2c_Delay(); +00001e f7fffffe BL i2c_Delay +;;;257 I2C_SDA_1(); /* CPU释放SDA总线 */ +000022 2080 MOVS r0,#0x80 +000024 4901 LDR r1,|L2.44| +000026 1f09 SUBS r1,r1,#4 +000028 6008 STR r0,[r1,#0] +;;;258 } +00002a bd10 POP {r4,pc} +;;;259 + ENDP + + |L2.44| + DCD 0x40010c14 + + AREA ||i.i2c_CheckDevice||, CODE, READONLY, ALIGN=2 + + i2c_CheckDevice PROC +;;;285 */ +;;;286 uint8_t i2c_CheckDevice(uint8_t _Address) +000000 b570 PUSH {r4-r6,lr} +;;;287 { +000002 4604 MOV r4,r0 +;;;288 uint8_t ucAck; +;;;289 +;;;290 if (I2C_SDA_READ() && I2C_SCL_READ()) +000004 480b LDR r0,|L3.52| +000006 6800 LDR r0,[r0,#0] +000008 f0000080 AND r0,r0,#0x80 +00000c b180 CBZ r0,|L3.48| +00000e 4809 LDR r0,|L3.52| +000010 6800 LDR r0,[r0,#0] +000012 f0000040 AND r0,r0,#0x40 +000016 b158 CBZ r0,|L3.48| +;;;291 { +;;;292 i2c_Start(); /* 发送启动信号 */ +000018 f7fffffe BL i2c_Start +;;;293 +;;;294 /* 发送设备地址+读写控制bit（0 = w， 1 = r) bit7 先传 */ +;;;295 i2c_SendByte(_Address | I2C_WR); +00001c 4620 MOV r0,r4 +00001e f7fffffe BL i2c_SendByte +;;;296 ucAck = i2c_WaitAck(); /* 检测设备的ACK应答 */ +000022 f7fffffe BL i2c_WaitAck +000026 4605 MOV r5,r0 +;;;297 +;;;298 i2c_Stop(); /* 发送停止信号 */ +000028 f7fffffe BL i2c_Stop +;;;299 +;;;300 return ucAck; +00002c 4628 MOV r0,r5 + |L3.46| +;;;301 } +;;;302 return 1; /* I2C总线异常 */ +;;;303 } +00002e bd70 POP {r4-r6,pc} + |L3.48| +000030 2001 MOVS r0,#1 ;302 +000032 e7fc B |L3.46| +;;;304 + ENDP + + |L3.52| + DCD 0x40010c08 + + AREA ||i.i2c_Delay||, CODE, READONLY, ALIGN=1 + + i2c_Delay PROC +;;;88 */ +;;;89 static void i2c_Delay(void) +000000 2000 MOVS r0,#0 +;;;90 { +;;;91 uint8_t i; +;;;92 +;;;93 /*　 +;;;94 CPU主频168MHz时，在内部Flash运行, MDK工程不优化。用台式示波器观测波形。 +;;;95 循环次数为5时，SCL频率 = 1.78MHz (读耗时: 92ms, 读写正常，但是用示波器探头碰上就读写失败。时序接近临界) +;;;96 循环次数为10时，SCL频率 = 1.1MHz (读耗时: 138ms, 读速度: 118724B/s) +;;;97 循环次数为30时，SCL频率 = 440KHz， SCL高电平时间1.0us，SCL低电平时间1.2us +;;;98 +;;;99 上拉电阻选择2.2K欧时，SCL上升沿时间约0.5us，如果选4.7K欧，则上升沿约1us +;;;100 +;;;101 实际应用选择400KHz左右的速率即可 +;;;102 */ +;;;103 for (i = 0; i < 30; i++) +000002 e001 B |L4.8| + |L4.4| +000004 1c41 ADDS r1,r0,#1 +000006 b2c8 UXTB r0,r1 + |L4.8| +000008 281e CMP r0,#0x1e +00000a dbfb BLT |L4.4| +;;;104 ; +;;;105 } +00000c 4770 BX lr +;;;106 + ENDP + + + AREA ||i.i2c_NAck||, CODE, READONLY, ALIGN=2 + + i2c_NAck PROC +;;;267 */ +;;;268 void i2c_NAck(void) +000000 b510 PUSH {r4,lr} +;;;269 { +;;;270 I2C_SDA_1(); /* CPU驱动SDA = 1 */ +000002 2080 MOVS r0,#0x80 +000004 4907 LDR r1,|L5.36| +000006 6008 STR r0,[r1,#0] +;;;271 i2c_Delay(); +000008 f7fffffe BL i2c_Delay +;;;272 I2C_SCL_1(); /* CPU产生1个时钟 */ +00000c 2040 MOVS r0,#0x40 +00000e 4905 LDR r1,|L5.36| +000010 6008 STR r0,[r1,#0] +;;;273 i2c_Delay(); +000012 f7fffffe BL i2c_Delay +;;;274 I2C_SCL_0(); +000016 2040 MOVS r0,#0x40 +000018 4902 LDR r1,|L5.36| +00001a 1d09 ADDS r1,r1,#4 +00001c 6008 STR r0,[r1,#0] +;;;275 i2c_Delay(); +00001e f7fffffe BL i2c_Delay +;;;276 } +000022 bd10 POP {r4,pc} +;;;277 + ENDP + + |L5.36| + DCD 0x40010c10 + + AREA ||i.i2c_ReadByte||, CODE, READONLY, ALIGN=2 + + i2c_ReadByte PROC +;;;189 */ +;;;190 uint8_t i2c_ReadByte(void) +000000 b570 PUSH {r4-r6,lr} +;;;191 { +;;;192 uint8_t i; +;;;193 uint8_t value; +;;;194 +;;;195 /* 读到第1个bit为数据的bit7 */ +;;;196 value = 0; +000002 2400 MOVS r4,#0 +;;;197 for (i = 0; i < 8; i++) +000004 2500 MOVS r5,#0 +000006 e016 B |L6.54| + |L6.8| +;;;198 { +;;;199 value <<= 1; +000008 0660 LSLS r0,r4,#25 +00000a 0e04 LSRS r4,r0,#24 +;;;200 I2C_SCL_1(); +00000c 2040 MOVS r0,#0x40 +00000e 490c LDR r1,|L6.64| +000010 6008 STR r0,[r1,#0] +;;;201 i2c_Delay(); +000012 f7fffffe BL i2c_Delay +;;;202 if (I2C_SDA_READ()) +000016 480a LDR r0,|L6.64| +000018 3808 SUBS r0,r0,#8 +00001a 6800 LDR r0,[r0,#0] +00001c f0000080 AND r0,r0,#0x80 +000020 b108 CBZ r0,|L6.38| +;;;203 { +;;;204 value++; +000022 1c60 ADDS r0,r4,#1 +000024 b2c4 UXTB r4,r0 + |L6.38| +;;;205 } +;;;206 I2C_SCL_0(); +000026 2040 MOVS r0,#0x40 +000028 4905 LDR r1,|L6.64| +00002a 1d09 ADDS r1,r1,#4 +00002c 6008 STR r0,[r1,#0] +;;;207 i2c_Delay(); +00002e f7fffffe BL i2c_Delay +000032 1c68 ADDS r0,r5,#1 ;197 +000034 b2c5 UXTB r5,r0 ;197 + |L6.54| +000036 2d08 CMP r5,#8 ;197 +000038 dbe6 BLT |L6.8| +;;;208 } +;;;209 return value; +00003a 4620 MOV r0,r4 +;;;210 } +00003c bd70 POP {r4-r6,pc} +;;;211 + ENDP + +00003e 0000 DCW 0x0000 + |L6.64| + DCD 0x40010c10 + + AREA ||i.i2c_SendByte||, CODE, READONLY, ALIGN=2 + + i2c_SendByte PROC +;;;153 */ +;;;154 void i2c_SendByte(uint8_t _ucByte) +000000 b570 PUSH {r4-r6,lr} +;;;155 { +000002 4604 MOV r4,r0 +;;;156 uint8_t i; +;;;157 +;;;158 /* 先发送字节的高位bit7 */ +;;;159 for (i = 0; i < 8; i++) +000004 2500 MOVS r5,#0 +000006 e020 B |L7.74| + |L7.8| +;;;160 { +;;;161 if (_ucByte & 0x80) +000008 f0040080 AND r0,r4,#0x80 +00000c b118 CBZ r0,|L7.22| +;;;162 { +;;;163 I2C_SDA_1(); +00000e 2080 MOVS r0,#0x80 +000010 490f LDR r1,|L7.80| +000012 6008 STR r0,[r1,#0] +000014 e003 B |L7.30| + |L7.22| +;;;164 } +;;;165 else +;;;166 { +;;;167 I2C_SDA_0(); +000016 2080 MOVS r0,#0x80 +000018 490d LDR r1,|L7.80| +00001a 1d09 ADDS r1,r1,#4 +00001c 6008 STR r0,[r1,#0] + |L7.30| +;;;168 } +;;;169 i2c_Delay(); +00001e f7fffffe BL i2c_Delay +;;;170 I2C_SCL_1(); +000022 2040 MOVS r0,#0x40 +000024 490a LDR r1,|L7.80| +000026 6008 STR r0,[r1,#0] +;;;171 i2c_Delay(); +000028 f7fffffe BL i2c_Delay +;;;172 I2C_SCL_0(); +00002c 2040 MOVS r0,#0x40 +00002e 4908 LDR r1,|L7.80| +000030 1d09 ADDS r1,r1,#4 +000032 6008 STR r0,[r1,#0] +;;;173 if (i == 7) +000034 2d07 CMP r5,#7 +000036 d102 BNE |L7.62| +;;;174 { +;;;175 I2C_SDA_1(); // 释放总线 +000038 2080 MOVS r0,#0x80 +00003a 1f09 SUBS r1,r1,#4 +00003c 6008 STR r0,[r1,#0] + |L7.62| +;;;176 } +;;;177 _ucByte <<= 1; /* 左移一个bit */ +00003e 0660 LSLS r0,r4,#25 +000040 0e04 LSRS r4,r0,#24 +;;;178 i2c_Delay(); +000042 f7fffffe BL i2c_Delay +000046 1c68 ADDS r0,r5,#1 ;159 +000048 b2c5 UXTB r5,r0 ;159 + |L7.74| +00004a 2d08 CMP r5,#8 ;159 +00004c dbdc BLT |L7.8| +;;;179 } +;;;180 } +00004e bd70 POP {r4-r6,pc} +;;;181 + ENDP + + |L7.80| + DCD 0x40010c10 + + AREA ||i.i2c_Start||, CODE, READONLY, ALIGN=2 + + i2c_Start PROC +;;;114 */ +;;;115 void i2c_Start(void) +000000 b510 PUSH {r4,lr} +;;;116 { +;;;117 /* 当SCL高电平时，SDA出现一个下跳沿表示I2C总线启动信号 */ +;;;118 I2C_SDA_1(); +000002 2080 MOVS r0,#0x80 +000004 4909 LDR r1,|L8.44| +000006 6008 STR r0,[r1,#0] +;;;119 I2C_SCL_1(); +000008 2040 MOVS r0,#0x40 +00000a 6008 STR r0,[r1,#0] +;;;120 i2c_Delay(); +00000c f7fffffe BL i2c_Delay +;;;121 I2C_SDA_0(); +000010 2080 MOVS r0,#0x80 +000012 4906 LDR r1,|L8.44| +000014 1d09 ADDS r1,r1,#4 +000016 6008 STR r0,[r1,#0] +;;;122 i2c_Delay(); +000018 f7fffffe BL i2c_Delay +;;;123 +;;;124 I2C_SCL_0(); +00001c 2040 MOVS r0,#0x40 +00001e 4903 LDR r1,|L8.44| +000020 1d09 ADDS r1,r1,#4 +000022 6008 STR r0,[r1,#0] +;;;125 i2c_Delay(); +000024 f7fffffe BL i2c_Delay +;;;126 } +000028 bd10 POP {r4,pc} +;;;127 + ENDP + +00002a 0000 DCW 0x0000 + |L8.44| + DCD 0x40010c10 + + AREA ||i.i2c_Stop||, CODE, READONLY, ALIGN=2 + + i2c_Stop PROC +;;;135 */ +;;;136 void i2c_Stop(void) +000000 b510 PUSH {r4,lr} +;;;137 { +;;;138 /* 当SCL高电平时，SDA出现一个上跳沿表示I2C总线停止信号 */ +;;;139 I2C_SDA_0(); +000002 2080 MOVS r0,#0x80 +000004 4906 LDR r1,|L9.32| +000006 6008 STR r0,[r1,#0] +;;;140 I2C_SCL_1(); +000008 2040 MOVS r0,#0x40 +00000a 1f09 SUBS r1,r1,#4 +00000c 6008 STR r0,[r1,#0] +;;;141 i2c_Delay(); +00000e f7fffffe BL i2c_Delay +;;;142 I2C_SDA_1(); +000012 2080 MOVS r0,#0x80 +000014 4902 LDR r1,|L9.32| +000016 1f09 SUBS r1,r1,#4 +000018 6008 STR r0,[r1,#0] +;;;143 i2c_Delay(); +00001a f7fffffe BL i2c_Delay +;;;144 } +00001e bd10 POP {r4,pc} +;;;145 + ENDP + + |L9.32| + DCD 0x40010c14 + + AREA ||i.i2c_WaitAck||, CODE, READONLY, ALIGN=2 + + i2c_WaitAck PROC +;;;219 */ +;;;220 uint8_t i2c_WaitAck(void) +000000 b510 PUSH {r4,lr} +;;;221 { +;;;222 uint8_t re; +;;;223 +;;;224 I2C_SDA_1(); /* CPU释放SDA总线 */ +000002 2080 MOVS r0,#0x80 +000004 490c LDR r1,|L10.56| +000006 6008 STR r0,[r1,#0] +;;;225 i2c_Delay(); +000008 f7fffffe BL i2c_Delay +;;;226 I2C_SCL_1(); /* CPU驱动SCL = 1, 此时器件会返回ACK应答 */ +00000c 2040 MOVS r0,#0x40 +00000e 490a LDR r1,|L10.56| +000010 6008 STR r0,[r1,#0] +;;;227 i2c_Delay(); +000012 f7fffffe BL i2c_Delay +;;;228 if (I2C_SDA_READ()) /* CPU读取SDA口线状态 */ +000016 4808 LDR r0,|L10.56| +000018 3808 SUBS r0,r0,#8 +00001a 6800 LDR r0,[r0,#0] +00001c f0000080 AND r0,r0,#0x80 +000020 b108 CBZ r0,|L10.38| +;;;229 { +;;;230 re = 1; +000022 2401 MOVS r4,#1 +000024 e000 B |L10.40| + |L10.38| +;;;231 } +;;;232 else +;;;233 { +;;;234 re = 0; +000026 2400 MOVS r4,#0 + |L10.40| +;;;235 } +;;;236 I2C_SCL_0(); +000028 2040 MOVS r0,#0x40 +00002a 4903 LDR r1,|L10.56| +00002c 1d09 ADDS r1,r1,#4 +00002e 6008 STR r0,[r1,#0] +;;;237 i2c_Delay(); +000030 f7fffffe BL i2c_Delay +;;;238 return re; +000034 4620 MOV r0,r4 +;;;239 } +000036 bd10 POP {r4,pc} +;;;240 + ENDP + + |L10.56| + DCD 0x40010c10 + +;*** Start embedded assembler *** + +#line 1 "..\\..\\User\\bsp\\src\\bsp_i2c_gpio.c" + AREA ||.rev16_text||, CODE + THUMB + EXPORT |__asm___14_bsp_i2c_gpio_c_ec180c52____REV16| +#line 114 "..\\..\\Libraries\\CMSIS\\Include\\core_cmInstr.h" +|__asm___14_bsp_i2c_gpio_c_ec180c52____REV16| PROC +#line 115 + + rev16 r0, r0 + bx lr + ENDP + AREA ||.revsh_text||, CODE + THUMB + EXPORT |__asm___14_bsp_i2c_gpio_c_ec180c52____REVSH| +#line 128 +|__asm___14_bsp_i2c_gpio_c_ec180c52____REVSH| PROC +#line 129 + + revsh r0, r0 + bx lr + ENDP + +;*** End embedded assembler *** diff --git a/Project/MDK-ARM/Flash/List/bsp_key.txt b/Project/MDK-ARM/Flash/List/bsp_key.txt new file mode 100644 index 0000000..926cfa5 --- /dev/null +++ b/Project/MDK-ARM/Flash/List/bsp_key.txt @@ -0,0 +1,748 @@ +; generated by Component: ARM Compiler 5.06 update 7 (build 960) Tool: ArmCC [4d365d] +; commandline ArmCC [--list --split_sections --debug -c --asm --interleave -o.\flash\obj\bsp_key.o --asm_dir=.\Flash\List\ --list_dir=.\Flash\List\ --depend=.\flash\obj\bsp_key.d --cpu=Cortex-M3 --apcs=interwork -O0 --diag_suppress=9931,870 -I..\..\Libraries\CMSIS\Device\ST\STM32F10x\Include -I..\..\Libraries\STM32F10x_StdPeriph_Driver\inc -I..\..\Libraries\STM32_USB-FS-Device_Driver\inc -I..\..\Libraries\CMSIS\Include -I..\..\User\bsp -I..\..\User\bsp\inc -I..\..\User\app\inc -I..\..\User -IC:\Users\w1619\AppData\Local\Arm\Packs\Keil\STM32F1xx_DFP\2.4.1\Device\Include -D__MICROLIB -D__UVISION_VERSION=538 -DSTM32F10X_HD -DUSE_STDPERIPH_DRIVER -DSTM32F10X_HD --omf_browse=.\flash\obj\bsp_key.crf ..\..\User\bsp\src\bsp_key.c] + THUMB + + AREA ||i.IsKeyDown1||, CODE, READONLY, ALIGN=2 + + IsKeyDown1 PROC +;;;118 #else +;;;119 uint8_t IsKeyDown1(void) +000000 4804 LDR r0,|L1.20| +;;;120 { +;;;121 if ((GPIO_PORT_K6->IDR & GPIO_PIN_K6) == 0) +000002 6800 LDR r0,[r0,#0] +000004 f0000008 AND r0,r0,#8 +000008 b908 CBNZ r0,|L1.14| +;;;122 return 1; +00000a 2001 MOVS r0,#1 + |L1.12| +;;;123 else +;;;124 return 0; +;;;125 } // 复位键 +00000c 4770 BX lr + |L1.14| +00000e 2000 MOVS r0,#0 ;124 +000010 e7fc B |L1.12| +;;;126 // 被main函数调用 + ENDP + +000012 0000 DCW 0x0000 + |L1.20| + DCD 0x40010808 + + AREA ||i.IsKeyDown2||, CODE, READONLY, ALIGN=2 + + IsKeyDown2 PROC +;;;126 // 被main函数调用 +;;;127 uint8_t IsKeyDown2(void) +000000 4804 LDR r0,|L2.20| +;;;128 { +;;;129 if ((GPIO_PORT_K1->IDR & GPIO_PIN_K1) == 0) +000002 6800 LDR r0,[r0,#0] +000004 f0000004 AND r0,r0,#4 +000008 b908 CBNZ r0,|L2.14| +;;;130 return 1; +00000a 2001 MOVS r0,#1 + |L2.12| +;;;131 else +;;;132 return 0; +;;;133 } // 模式切换键 +00000c 4770 BX lr + |L2.14| +00000e 2000 MOVS r0,#0 ;132 +000010 e7fc B |L2.12| +;;;134 uint8_t IsKeyDown3(void) + ENDP + +000012 0000 DCW 0x0000 + |L2.20| + DCD 0x40011808 + + AREA ||i.IsKeyDown3||, CODE, READONLY, ALIGN=2 + + IsKeyDown3 PROC +;;;133 } // 模式切换键 +;;;134 uint8_t IsKeyDown3(void) +000000 4804 LDR r0,|L3.20| +;;;135 { +;;;136 if ((GPIO_PORT_K2->IDR & GPIO_PIN_K2) == 0) +000002 6800 LDR r0,[r0,#0] +000004 f0000008 AND r0,r0,#8 +000008 b908 CBNZ r0,|L3.14| +;;;137 return 1; +00000a 2001 MOVS r0,#1 + |L3.12| +;;;138 else +;;;139 return 0; +;;;140 } // 模式切换键 +00000c 4770 BX lr + |L3.14| +00000e 2000 MOVS r0,#0 ;139 +000010 e7fc B |L3.12| +;;;141 // static uint8_t IsKeyDown3(void) {if ((GPIO_PORT_K3->IDR & GPIO_PIN_K3) == 0) return 1;else return 0;} + ENDP + +000012 0000 DCW 0x0000 + |L3.20| + DCD 0x40011808 + + AREA ||i.bsp_ClearKey||, CODE, READONLY, ALIGN=2 + + bsp_ClearKey PROC +;;;279 */ +;;;280 void bsp_ClearKey(void) +000000 4802 LDR r0,|L4.12| +;;;281 { +;;;282 s_tKey.Read = s_tKey.Write; +000002 7ac0 LDRB r0,[r0,#0xb] ; s_tKey +000004 4901 LDR r1,|L4.12| +000006 7288 STRB r0,[r1,#0xa] +;;;283 } +000008 4770 BX lr +;;;284 + ENDP + +00000a 0000 DCW 0x0000 + |L4.12| + DCD s_tKey + + AREA ||i.bsp_DetectKey||, CODE, READONLY, ALIGN=2 + + bsp_DetectKey PROC +;;;392 */ +;;;393 static void bsp_DetectKey(uint8_t i) +000000 b570 PUSH {r4-r6,lr} +;;;394 { +000002 4605 MOV r5,r0 +;;;395 KEY_T *pBtn; +;;;396 +;;;397 /* +;;;398 如果没有初始化按键函数，则报错 +;;;399 if (s_tBtn[i].IsKeyDownFunc == 0) +;;;400 { +;;;401 printf("Fault : DetectButton(), s_tBtn[i].IsKeyDownFunc undefine"); +;;;402 } +;;;403 */ +;;;404 +;;;405 pBtn = &s_tBtn[i]; +000004 4830 LDR r0,|L5.200| +000006 eb001405 ADD r4,r0,r5,LSL #4 +;;;406 if (pBtn->IsKeyDownFunc()) +00000a 6820 LDR r0,[r4,#0] +00000c 4780 BLX r0 +00000e 2800 CMP r0,#0 +000010 d03e BEQ |L5.144| +;;;407 { +;;;408 if (pBtn->Count < KEY_FILTER_TIME) +000012 7920 LDRB r0,[r4,#4] +000014 2801 CMP r0,#1 +000016 da02 BGE |L5.30| +;;;409 { +;;;410 pBtn->Count = KEY_FILTER_TIME; +000018 2001 MOVS r0,#1 +00001a 7120 STRB r0,[r4,#4] +00001c e052 B |L5.196| + |L5.30| +;;;411 } +;;;412 else if (pBtn->Count < 2 * KEY_FILTER_TIME) +00001e 7920 LDRB r0,[r4,#4] +000020 2802 CMP r0,#2 +000022 da03 BGE |L5.44| +;;;413 { +;;;414 pBtn->Count++; +000024 7920 LDRB r0,[r4,#4] +000026 1c40 ADDS r0,r0,#1 +000028 7120 STRB r0,[r4,#4] +00002a e04b B |L5.196| + |L5.44| +;;;415 } +;;;416 else +;;;417 { +;;;418 if (pBtn->State == 0) +00002c 7aa0 LDRB r0,[r4,#0xa] +00002e b938 CBNZ r0,|L5.64| +;;;419 { +;;;420 pBtn->State = 1; +000030 2001 MOVS r0,#1 +000032 72a0 STRB r0,[r4,#0xa] +;;;421 +;;;422 /* 发送按钮按下的消息 */ +;;;423 bsp_PutKey((uint8_t)(3 * i + 1)); +000034 eb050145 ADD r1,r5,r5,LSL #1 +000038 1c49 ADDS r1,r1,#1 +00003a b2c8 UXTB r0,r1 +00003c f7fffffe BL bsp_PutKey + |L5.64| +;;;424 } +;;;425 +;;;426 if (pBtn->LongTime > 0) +000040 8920 LDRH r0,[r4,#8] +000042 2800 CMP r0,#0 +000044 dd3e BLE |L5.196| +;;;427 { +;;;428 if (pBtn->LongCount < pBtn->LongTime) +000046 88e0 LDRH r0,[r4,#6] +000048 8921 LDRH r1,[r4,#8] +00004a 4288 CMP r0,r1 +00004c da0d BGE |L5.106| +;;;429 { +;;;430 /* 发送按钮持续按下的消息 */ +;;;431 if (++pBtn->LongCount == pBtn->LongTime) +00004e 88e0 LDRH r0,[r4,#6] +000050 1c40 ADDS r0,r0,#1 +000052 b280 UXTH r0,r0 +000054 80e0 STRH r0,[r4,#6] +000056 8921 LDRH r1,[r4,#8] +000058 4288 CMP r0,r1 +00005a d133 BNE |L5.196| +;;;432 { +;;;433 /* 键值放入按键FIFO */ +;;;434 bsp_PutKey((uint8_t)(3 * i + 3)); +00005c eb050145 ADD r1,r5,r5,LSL #1 +000060 1cc9 ADDS r1,r1,#3 +000062 b2c8 UXTB r0,r1 +000064 f7fffffe BL bsp_PutKey +000068 e02c B |L5.196| + |L5.106| +;;;435 } +;;;436 } +;;;437 else +;;;438 { +;;;439 if (pBtn->RepeatSpeed > 0) +00006a 7ae0 LDRB r0,[r4,#0xb] +00006c 2800 CMP r0,#0 +00006e dd29 BLE |L5.196| +;;;440 { +;;;441 if (++pBtn->RepeatCount >= pBtn->RepeatSpeed) +000070 7b20 LDRB r0,[r4,#0xc] +000072 1c40 ADDS r0,r0,#1 +000074 b2c0 UXTB r0,r0 +000076 7320 STRB r0,[r4,#0xc] +000078 7ae1 LDRB r1,[r4,#0xb] +00007a 4288 CMP r0,r1 +00007c db22 BLT |L5.196| +;;;442 { +;;;443 pBtn->RepeatCount = 0; +00007e 2000 MOVS r0,#0 +000080 7320 STRB r0,[r4,#0xc] +;;;444 /* 常按键后，每隔10ms发送1个按键 */ +;;;445 bsp_PutKey((uint8_t)(3 * i + 1)); +000082 eb050145 ADD r1,r5,r5,LSL #1 +000086 1c49 ADDS r1,r1,#1 +000088 b2c8 UXTB r0,r1 +00008a f7fffffe BL bsp_PutKey +00008e e019 B |L5.196| + |L5.144| +;;;446 } +;;;447 } +;;;448 } +;;;449 } +;;;450 } +;;;451 } +;;;452 else +;;;453 { +;;;454 if (pBtn->Count > KEY_FILTER_TIME) +000090 7920 LDRB r0,[r4,#4] +000092 2801 CMP r0,#1 +000094 dd02 BLE |L5.156| +;;;455 { +;;;456 pBtn->Count = KEY_FILTER_TIME; +000096 2001 MOVS r0,#1 +000098 7120 STRB r0,[r4,#4] +00009a e010 B |L5.190| + |L5.156| +;;;457 } +;;;458 else if (pBtn->Count != 0) +00009c 7920 LDRB r0,[r4,#4] +00009e b118 CBZ r0,|L5.168| +;;;459 { +;;;460 pBtn->Count--; +0000a0 7920 LDRB r0,[r4,#4] +0000a2 1e40 SUBS r0,r0,#1 +0000a4 7120 STRB r0,[r4,#4] +0000a6 e00a B |L5.190| + |L5.168| +;;;461 } +;;;462 else +;;;463 { +;;;464 if (pBtn->State == 1) +0000a8 7aa0 LDRB r0,[r4,#0xa] +0000aa 2801 CMP r0,#1 +0000ac d107 BNE |L5.190| +;;;465 { +;;;466 pBtn->State = 0; +0000ae 2000 MOVS r0,#0 +0000b0 72a0 STRB r0,[r4,#0xa] +;;;467 +;;;468 /* 发送按钮弹起的消息 */ +;;;469 bsp_PutKey((uint8_t)(3 * i + 2)); +0000b2 eb050145 ADD r1,r5,r5,LSL #1 +0000b6 1c89 ADDS r1,r1,#2 +0000b8 b2c8 UXTB r0,r1 +0000ba f7fffffe BL bsp_PutKey + |L5.190| +;;;470 } +;;;471 } +;;;472 +;;;473 pBtn->LongCount = 0; +0000be 2000 MOVS r0,#0 +0000c0 80e0 STRH r0,[r4,#6] +;;;474 pBtn->RepeatCount = 0; +0000c2 7320 STRB r0,[r4,#0xc] + |L5.196| +;;;475 } +;;;476 } +0000c4 bd70 POP {r4-r6,pc} +;;;477 + ENDP + +0000c6 0000 DCW 0x0000 + |L5.200| + DCD s_tBtn + + AREA ||i.bsp_GetKey||, CODE, READONLY, ALIGN=2 + + bsp_GetKey PROC +;;;193 */ +;;;194 uint8_t bsp_GetKey(void) +000000 480b LDR r0,|L6.48| +;;;195 { +;;;196 uint8_t ret; +;;;197 +;;;198 if (s_tKey.Read == s_tKey.Write) +000002 7a80 LDRB r0,[r0,#0xa] ; s_tKey +000004 4a0a LDR r2,|L6.48| +000006 7ad2 LDRB r2,[r2,#0xb] ; s_tKey +000008 4290 CMP r0,r2 +00000a d101 BNE |L6.16| +;;;199 { +;;;200 return KEY_NONE; +00000c 2000 MOVS r0,#0 + |L6.14| +;;;201 } +;;;202 else +;;;203 { +;;;204 ret = s_tKey.Buf[s_tKey.Read]; +;;;205 +;;;206 if (++s_tKey.Read >= KEY_FIFO_SIZE) +;;;207 { +;;;208 s_tKey.Read = 0; +;;;209 } +;;;210 return ret; +;;;211 } +;;;212 } +00000e 4770 BX lr + |L6.16| +000010 4807 LDR r0,|L6.48| +000012 7a80 LDRB r0,[r0,#0xa] ;204 ; s_tKey +000014 4a06 LDR r2,|L6.48| +000016 5c11 LDRB r1,[r2,r0] ;204 +000018 4610 MOV r0,r2 ;206 +00001a 7a80 LDRB r0,[r0,#0xa] ;206 ; s_tKey +00001c 1c40 ADDS r0,r0,#1 ;206 +00001e b2c0 UXTB r0,r0 ;206 +000020 7290 STRB r0,[r2,#0xa] ;206 +000022 280a CMP r0,#0xa ;206 +000024 db01 BLT |L6.42| +000026 2000 MOVS r0,#0 ;208 +000028 7290 STRB r0,[r2,#0xa] ;208 + |L6.42| +00002a 4608 MOV r0,r1 ;210 +00002c e7ef B |L6.14| +;;;213 + ENDP + +00002e 0000 DCW 0x0000 + |L6.48| + DCD s_tKey + + AREA ||i.bsp_GetKey2||, CODE, READONLY, ALIGN=2 + + bsp_GetKey2 PROC +;;;221 */ +;;;222 uint8_t bsp_GetKey2(void) +000000 480b LDR r0,|L7.48| +;;;223 { +;;;224 uint8_t ret; +;;;225 +;;;226 if (s_tKey.Read2 == s_tKey.Write) +000002 7b00 LDRB r0,[r0,#0xc] ; s_tKey +000004 4a0a LDR r2,|L7.48| +000006 7ad2 LDRB r2,[r2,#0xb] ; s_tKey +000008 4290 CMP r0,r2 +00000a d101 BNE |L7.16| +;;;227 { +;;;228 return KEY_NONE; +00000c 2000 MOVS r0,#0 + |L7.14| +;;;229 } +;;;230 else +;;;231 { +;;;232 ret = s_tKey.Buf[s_tKey.Read2]; +;;;233 +;;;234 if (++s_tKey.Read2 >= KEY_FIFO_SIZE) +;;;235 { +;;;236 s_tKey.Read2 = 0; +;;;237 } +;;;238 return ret; +;;;239 } +;;;240 } +00000e 4770 BX lr + |L7.16| +000010 4807 LDR r0,|L7.48| +000012 7b00 LDRB r0,[r0,#0xc] ;232 ; s_tKey +000014 4a06 LDR r2,|L7.48| +000016 5c11 LDRB r1,[r2,r0] ;232 +000018 4610 MOV r0,r2 ;234 +00001a 7b00 LDRB r0,[r0,#0xc] ;234 ; s_tKey +00001c 1c40 ADDS r0,r0,#1 ;234 +00001e b2c0 UXTB r0,r0 ;234 +000020 7310 STRB r0,[r2,#0xc] ;234 +000022 280a CMP r0,#0xa ;234 +000024 db01 BLT |L7.42| +000026 2000 MOVS r0,#0 ;236 +000028 7310 STRB r0,[r2,#0xc] ;236 + |L7.42| +00002a 4608 MOV r0,r1 ;238 +00002c e7ef B |L7.14| +;;;241 + ENDP + +00002e 0000 DCW 0x0000 + |L7.48| + DCD s_tKey + + AREA ||i.bsp_GetKeyState||, CODE, READONLY, ALIGN=2 + + bsp_GetKeyState PROC +;;;249 */ +;;;250 uint8_t bsp_GetKeyState(KEY_ID_E _ucKeyID) +000000 4601 MOV r1,r0 +;;;251 { +;;;252 return s_tBtn[_ucKeyID].State; +000002 4802 LDR r0,|L8.12| +000004 eb001001 ADD r0,r0,r1,LSL #4 +000008 7a80 LDRB r0,[r0,#0xa] +;;;253 } +00000a 4770 BX lr +;;;254 + ENDP + + |L8.12| + DCD s_tBtn + + AREA ||i.bsp_InitKey||, CODE, READONLY, ALIGN=1 + + bsp_InitKey PROC +;;;161 */ +;;;162 void bsp_InitKey(void) +000000 b510 PUSH {r4,lr} +;;;163 { +;;;164 bsp_InitKeyVar(); /* 初始化按键变量 */ +000002 f7fffffe BL bsp_InitKeyVar +;;;165 bsp_InitKeyHard(); /* 初始化按键硬件 */ +000006 f7fffffe BL bsp_InitKeyHard +;;;166 } +00000a bd10 POP {r4,pc} +;;;167 + ENDP + + + AREA ||i.bsp_InitKeyHard||, CODE, READONLY, ALIGN=2 + + bsp_InitKeyHard PROC +;;;292 */ +;;;293 static void bsp_InitKeyHard(void) +000000 b508 PUSH {r3,lr} +;;;294 { +;;;295 GPIO_InitTypeDef GPIO_InitStructure; +;;;296 +;;;297 /* 第1步：打开GPIO时钟 */ +;;;298 RCC_APB2PeriphClockCmd(RCC_ALL_KEY | RCC_ALL_KEY1, ENABLE); +000002 2101 MOVS r1,#1 +000004 2044 MOVS r0,#0x44 +000006 f7fffffe BL RCC_APB2PeriphClockCmd +;;;299 +;;;300 /* 第2步：配置所有的按键GPIO为浮动输入模式(实际上CPU复位后就是输入状态) */ +;;;301 GPIO_InitStructure.GPIO_Speed = GPIO_Speed_50MHz; +00000a 2003 MOVS r0,#3 +00000c f88d0002 STRB r0,[sp,#2] +;;;302 GPIO_InitStructure.GPIO_Mode = GPIO_Mode_IN_FLOATING; /* 输入浮空模式 */ +000010 2004 MOVS r0,#4 +000012 f88d0003 STRB r0,[sp,#3] +;;;303 +;;;304 GPIO_InitStructure.GPIO_Pin = GPIO_PIN_K1; +000016 f8ad0000 STRH r0,[sp,#0] +;;;305 GPIO_Init(GPIO_PORT_K1, &GPIO_InitStructure); +00001a 4669 MOV r1,sp +00001c 4808 LDR r0,|L10.64| +00001e f7fffffe BL GPIO_Init +;;;306 +;;;307 GPIO_InitStructure.GPIO_Pin = GPIO_PIN_K2; +000022 2008 MOVS r0,#8 +000024 f8ad0000 STRH r0,[sp,#0] +;;;308 GPIO_Init(GPIO_PORT_K2, &GPIO_InitStructure); +000028 4669 MOV r1,sp +00002a 4805 LDR r0,|L10.64| +00002c f7fffffe BL GPIO_Init +;;;309 +;;;310 GPIO_InitStructure.GPIO_Pin = GPIO_PIN_K6; +000030 2008 MOVS r0,#8 +000032 f8ad0000 STRH r0,[sp,#0] +;;;311 GPIO_Init(GPIO_PORT_K6, &GPIO_InitStructure); +000036 4669 MOV r1,sp +000038 4802 LDR r0,|L10.68| +00003a f7fffffe BL GPIO_Init +;;;312 +;;;313 // GPIO_InitStructure.GPIO_Pin = GPIO_PIN_K3; +;;;314 // GPIO_Init(GPIO_PORT_K3, &GPIO_InitStructure); +;;;315 // +;;;316 // GPIO_InitStructure.GPIO_Pin = GPIO_PIN_K4; +;;;317 // GPIO_Init(GPIO_PORT_K4, &GPIO_InitStructure); +;;;318 // +;;;319 // GPIO_InitStructure.GPIO_Pin = GPIO_PIN_K5; +;;;320 // GPIO_Init(GPIO_PORT_K5, &GPIO_InitStructure); +;;;321 // +;;;322 // GPIO_InitStructure.GPIO_Pin = GPIO_PIN_K6; +;;;323 // GPIO_Init(GPIO_PORT_K6, &GPIO_InitStructure); +;;;324 // +;;;325 // GPIO_InitStructure.GPIO_Pin = GPIO_PIN_K7; +;;;326 // GPIO_Init(GPIO_PORT_K7, &GPIO_InitStructure); +;;;327 // +;;;328 // GPIO_InitStructure.GPIO_Pin = GPIO_PIN_K8; +;;;329 // GPIO_Init(GPIO_PORT_K8, &GPIO_InitStructure); +;;;330 } +00003e bd08 POP {r3,pc} +;;;331 + ENDP + + |L10.64| + DCD 0x40011800 + |L10.68| + DCD 0x40010800 + + AREA ||i.bsp_InitKeyVar||, CODE, READONLY, ALIGN=2 + + bsp_InitKeyVar PROC +;;;339 */ +;;;340 static void bsp_InitKeyVar(void) +000000 2100 MOVS r1,#0 +;;;341 { +;;;342 uint8_t i; +;;;343 +;;;344 /* 对按键FIFO读写指针清零 */ +;;;345 s_tKey.Read = 0; +000002 4a14 LDR r2,|L11.84| +000004 7291 STRB r1,[r2,#0xa] +;;;346 s_tKey.Write = 0; +000006 72d1 STRB r1,[r2,#0xb] +;;;347 s_tKey.Read2 = 0; +000008 7311 STRB r1,[r2,#0xc] +;;;348 +;;;349 /* 给每个按键结构体成员变量赋一组缺省值 */ +;;;350 for (i = 0; i < KEY_COUNT; i++) +00000a 2000 MOVS r0,#0 +00000c e017 B |L11.62| + |L11.14| +;;;351 { +;;;352 s_tBtn[i].LongTime = KEY_LONG_TIME; /* 长按时间 0 表示不检测长按键事件 */ +00000e 2164 MOVS r1,#0x64 +000010 4a11 LDR r2,|L11.88| +000012 eb021200 ADD r2,r2,r0,LSL #4 +000016 8111 STRH r1,[r2,#8] +;;;353 s_tBtn[i].Count = KEY_FILTER_TIME / 2; /* 计数器设置为滤波时间的一半 */ +000018 2100 MOVS r1,#0 +00001a 4a0f LDR r2,|L11.88| +00001c eb021200 ADD r2,r2,r0,LSL #4 +000020 7111 STRB r1,[r2,#4] +;;;354 s_tBtn[i].State = 0; /* 按键缺省状态，0为未按下 */ +000022 4a0d LDR r2,|L11.88| +000024 eb021200 ADD r2,r2,r0,LSL #4 +000028 7291 STRB r1,[r2,#0xa] +;;;355 // s_tBtn[i].KeyCodeDown = 3 * i + 1; /* 按键按下的键值代码 */ +;;;356 // s_tBtn[i].KeyCodeUp = 3 * i + 2; /* 按键弹起的键值代码 */ +;;;357 // s_tBtn[i].KeyCodeLong = 3 * i + 3; /* 按键被持续按下的键值代码 */ +;;;358 s_tBtn[i].RepeatSpeed = 0; /* 按键连发的速度，0表示不支持连发 */ +00002a 4a0b LDR r2,|L11.88| +00002c eb021200 ADD r2,r2,r0,LSL #4 +000030 72d1 STRB r1,[r2,#0xb] +;;;359 s_tBtn[i].RepeatCount = 0; /* 连发计数器 */ +000032 4a09 LDR r2,|L11.88| +000034 eb021200 ADD r2,r2,r0,LSL #4 +000038 7311 STRB r1,[r2,#0xc] +00003a 1c41 ADDS r1,r0,#1 ;350 +00003c b2c8 UXTB r0,r1 ;350 + |L11.62| +00003e 2803 CMP r0,#3 ;350 +000040 dbe5 BLT |L11.14| +;;;360 } +;;;361 +;;;362 /* 如果需要单独更改某个按键的参数，可以在此单独重新赋值 */ +;;;363 /* 比如，我们希望按键1按下超过1秒后，自动重发相同键值 */ +;;;364 // s_tBtn[KID_K7].LongTime = 40; +;;;365 // s_tBtn[KID_K7].RepeatSpeed = 5; /* 每隔50ms自动发送键值 */ +;;;366 // +;;;367 // s_tBtn[KID_K8].LongTime = 40; +;;;368 // s_tBtn[KID_K8].RepeatSpeed = 5; /* 每隔50ms自动发送键值 */ +;;;369 +;;;370 /* 判断按键按下的函数 */ +;;;371 s_tBtn[0].IsKeyDownFunc = IsKeyDown1; +000042 4906 LDR r1,|L11.92| +000044 4a04 LDR r2,|L11.88| +000046 6011 STR r1,[r2,#0] ; s_tBtn +;;;372 s_tBtn[1].IsKeyDownFunc = IsKeyDown2; +000048 4905 LDR r1,|L11.96| +00004a 6111 STR r1,[r2,#0x10] ; s_tBtn +;;;373 s_tBtn[2].IsKeyDownFunc = IsKeyDown3; +00004c 4905 LDR r1,|L11.100| +00004e 6211 STR r1,[r2,#0x20] ; s_tBtn +;;;374 // s_tBtn[3].IsKeyDownFunc = IsKeyDown4; +;;;375 // s_tBtn[4].IsKeyDownFunc = IsKeyDown5; +;;;376 // s_tBtn[5].IsKeyDownFunc = IsKeyDown6; +;;;377 // s_tBtn[6].IsKeyDownFunc = IsKeyDown7;// shen 0809 +;;;378 // s_tBtn[7].IsKeyDownFunc = IsKeyDown8; +;;;379 +;;;380 /* 组合键 */ +;;;381 // s_tBtn[8].IsKeyDownFunc = IsKeyDown9; +;;;382 // s_tBtn[9].IsKeyDownFunc = IsKeyDown10; +;;;383 } +000050 4770 BX lr +;;;384 + ENDP + +000052 0000 DCW 0x0000 + |L11.84| + DCD s_tKey + |L11.88| + DCD s_tBtn + |L11.92| + DCD IsKeyDown1 + |L11.96| + DCD IsKeyDown2 + |L11.100| + DCD IsKeyDown3 + + AREA ||i.bsp_KeyScan||, CODE, READONLY, ALIGN=1 + + bsp_KeyScan PROC +;;;485 */ +;;;486 void bsp_KeyScan(void) +000000 b510 PUSH {r4,lr} +;;;487 { +;;;488 uint8_t i; +;;;489 +;;;490 for (i = 0; i < KEY_COUNT; i++) +000002 2400 MOVS r4,#0 +000004 e004 B |L12.16| + |L12.6| +;;;491 { +;;;492 bsp_DetectKey(i); +000006 4620 MOV r0,r4 +000008 f7fffffe BL bsp_DetectKey +00000c 1c60 ADDS r0,r4,#1 ;490 +00000e b2c4 UXTB r4,r0 ;490 + |L12.16| +000010 2c03 CMP r4,#3 ;490 +000012 dbf8 BLT |L12.6| +;;;493 } +;;;494 } +000014 bd10 POP {r4,pc} +;;;495 + ENDP + + + AREA ||i.bsp_PutKey||, CODE, READONLY, ALIGN=2 + + bsp_PutKey PROC +;;;175 */ +;;;176 void bsp_PutKey(uint8_t _KeyCode) +000000 4906 LDR r1,|L13.28| +;;;177 { +;;;178 s_tKey.Buf[s_tKey.Write] = _KeyCode; +000002 7ac9 LDRB r1,[r1,#0xb] ; s_tKey +000004 4a05 LDR r2,|L13.28| +000006 5450 STRB r0,[r2,r1] +;;;179 +;;;180 if (++s_tKey.Write >= KEY_FIFO_SIZE) +000008 4611 MOV r1,r2 +00000a 7ac9 LDRB r1,[r1,#0xb] ; s_tKey +00000c 1c49 ADDS r1,r1,#1 +00000e b2c9 UXTB r1,r1 +000010 72d1 STRB r1,[r2,#0xb] +000012 290a CMP r1,#0xa +000014 db01 BLT |L13.26| +;;;181 { +;;;182 s_tKey.Write = 0; +000016 2100 MOVS r1,#0 +000018 72d1 STRB r1,[r2,#0xb] + |L13.26| +;;;183 } +;;;184 } +00001a 4770 BX lr +;;;185 + ENDP + + |L13.28| + DCD s_tKey + + AREA ||i.bsp_SetKeyParam||, CODE, READONLY, ALIGN=2 + + bsp_SetKeyParam PROC +;;;264 */ +;;;265 void bsp_SetKeyParam(uint8_t _ucKeyID, uint16_t _LongTime, uint8_t _RepeatSpeed) +000000 b510 PUSH {r4,lr} +;;;266 { +;;;267 s_tBtn[_ucKeyID].LongTime = _LongTime; /* 长按时间 0 表示不检测长按键事件 */ +000002 4b07 LDR r3,|L14.32| +000004 eb031300 ADD r3,r3,r0,LSL #4 +000008 8119 STRH r1,[r3,#8] +;;;268 s_tBtn[_ucKeyID].RepeatSpeed = _RepeatSpeed; /* 按键连发的速度，0表示不支持连发 */ +00000a 4b05 LDR r3,|L14.32| +00000c eb031300 ADD r3,r3,r0,LSL #4 +000010 72da STRB r2,[r3,#0xb] +;;;269 s_tBtn[_ucKeyID].RepeatCount = 0; /* 连发计数器 */ +000012 2300 MOVS r3,#0 +000014 4c02 LDR r4,|L14.32| +000016 eb041400 ADD r4,r4,r0,LSL #4 +00001a 7323 STRB r3,[r4,#0xc] +;;;270 } +00001c bd10 POP {r4,pc} +;;;271 + ENDP + +00001e 0000 DCW 0x0000 + |L14.32| + DCD s_tBtn + + AREA ||.bss||, DATA, NOINIT, ALIGN=2 + + s_tBtn + % 48 + s_tKey + % 13 + +;*** Start embedded assembler *** + +#line 1 "..\\..\\User\\bsp\\src\\bsp_key.c" + AREA ||.rev16_text||, CODE + THUMB + EXPORT |__asm___9_bsp_key_c_fc777be6____REV16| +#line 114 "..\\..\\Libraries\\CMSIS\\Include\\core_cmInstr.h" +|__asm___9_bsp_key_c_fc777be6____REV16| PROC +#line 115 + + rev16 r0, r0 + bx lr + ENDP + AREA ||.revsh_text||, CODE + THUMB + EXPORT |__asm___9_bsp_key_c_fc777be6____REVSH| +#line 128 +|__asm___9_bsp_key_c_fc777be6____REVSH| PROC +#line 129 + + revsh r0, r0 + bx lr + ENDP + +;*** End embedded assembler *** diff --git a/Project/MDK-ARM/Flash/List/bsp_led.txt b/Project/MDK-ARM/Flash/List/bsp_led.txt new file mode 100644 index 0000000..557cd03 --- /dev/null +++ b/Project/MDK-ARM/Flash/List/bsp_led.txt @@ -0,0 +1,969 @@ +; generated by Component: ARM Compiler 5.05 update 1 (build 106) Tool: ArmCC [4d0efa] +; commandline ArmCC [--list --split_sections --debug -c --asm --interleave -o.\flash\obj\bsp_led.o --asm_dir=.\Flash\List\ --list_dir=.\Flash\List\ --depend=.\flash\obj\bsp_led.d --cpu=Cortex-M3 --apcs=interwork -O0 --diag_suppress=9931,870 -I..\..\Libraries\CMSIS\Device\ST\STM32F10x\Include -I..\..\Libraries\STM32F10x_StdPeriph_Driver\inc -I..\..\Libraries\STM32_USB-FS-Device_Driver\inc -I..\..\Libraries\CMSIS\Include -I..\..\User\bsp -I..\..\User\bsp\inc -I..\..\User\app\inc -IC:\Keil_v5\ARM\RV31\INC -IC:\Keil_v5\ARM\CMSIS\Include -IC:\Keil_v5\ARM\Inc\ST\STM32F10x -D__MICROLIB -D__UVISION_VERSION=514 -DUSE_STDPERIPH_DRIVER -DSTM32F10X_HD --omf_browse=.\flash\obj\bsp_led.crf ..\..\User\bsp\src\bsp_led.c] + THUMB + + AREA ||i.ChannelLedAllOff||, CODE, READONLY, ALIGN=1 + + ChannelLedAllOff PROC +;;;391 +;;;392 static void ChannelLedAllOff(void) +000000 b500 PUSH {lr} +;;;393 { +;;;394 bsp_LedOff(1); +000002 2001 MOVS r0,#1 +000004 f7fffffe BL bsp_LedOff +;;;395 bsp_LedOff(2); +000008 2002 MOVS r0,#2 +00000a f7fffffe BL bsp_LedOff +;;;396 bsp_LedOff(3); +00000e 2003 MOVS r0,#3 +000010 f7fffffe BL bsp_LedOff +;;;397 bsp_LedOff(4); +000014 2004 MOVS r0,#4 +000016 f7fffffe BL bsp_LedOff +;;;398 bsp_LedOff(5); +00001a 2005 MOVS r0,#5 +00001c f7fffffe BL bsp_LedOff +;;;399 bsp_LedOff(6); +000020 2006 MOVS r0,#6 +000022 f7fffffe BL bsp_LedOff +;;;400 } +000026 bd00 POP {pc} +;;;401 + ENDP + + + AREA ||i.ResLedAllOff||, CODE, READONLY, ALIGN=1 + + ResLedAllOff PROC +;;;401 +;;;402 static void ResLedAllOff(void) +000000 b500 PUSH {lr} +;;;403 { +;;;404 bsp_LedOff(7); +000002 2007 MOVS r0,#7 +000004 f7fffffe BL bsp_LedOff +;;;405 bsp_LedOff(8); +000008 2008 MOVS r0,#8 +00000a f7fffffe BL bsp_LedOff +;;;406 bsp_LedOff(9); +00000e 2009 MOVS r0,#9 +000010 f7fffffe BL bsp_LedOff +;;;407 bsp_LedOff(10); +000014 200a MOVS r0,#0xa +000016 f7fffffe BL bsp_LedOff +;;;408 bsp_LedOff(11); +00001a 200b MOVS r0,#0xb +00001c f7fffffe BL bsp_LedOff +;;;409 bsp_LedOff(12); +000020 200c MOVS r0,#0xc +000022 f7fffffe BL bsp_LedOff +;;;410 bsp_LedOff(13); +000026 200d MOVS r0,#0xd +000028 f7fffffe BL bsp_LedOff +;;;411 bsp_LedOff(14); +00002c 200e MOVS r0,#0xe +00002e f7fffffe BL bsp_LedOff +;;;412 } +000032 bd00 POP {pc} +;;;413 + ENDP + + + AREA ||i.bsp_ChannelSelect||, CODE, READONLY, ALIGN=2 + + bsp_ChannelSelect PROC +;;;416 //--------------------------------------- +;;;417 void bsp_ChannelSelect(uint8_t _ch) +000000 b510 PUSH {r4,lr} +;;;418 { +000002 4604 MOV r4,r0 +;;;419 static uint8_t s_ucOldCh=255; +;;;420 +;;;421 if(_ch==s_ucOldCh) +000004 480b LDR r0,|L3.52| +000006 7800 LDRB r0,[r0,#0] ; s_ucOldCh +000008 4284 CMP r4,r0 +00000a d107 BNE |L3.28| +;;;422 { +;;;423 ChannelLedAllOff(); +00000c f7fffffe BL ChannelLedAllOff +;;;424 bsp_RealyAllOff(); +000010 f7fffffe BL bsp_RealyAllOff +;;;425 s_ucOldCh=255; +000014 20ff MOVS r0,#0xff +000016 4907 LDR r1,|L3.52| +000018 7008 STRB r0,[r1,#0] +00001a e009 B |L3.48| + |L3.28| +;;;426 } +;;;427 else +;;;428 { +;;;429 s_ucOldCh = _ch; +00001c 4805 LDR r0,|L3.52| +00001e 7004 STRB r4,[r0,#0] +;;;430 ChannelLedAllOff(); +000020 f7fffffe BL ChannelLedAllOff +;;;431 bsp_LedOn(_ch); +000024 4620 MOV r0,r4 +000026 f7fffffe BL bsp_LedOn +;;;432 bsp_RelayOn(_ch); +00002a 4620 MOV r0,r4 +00002c f7fffffe BL bsp_RelayOn + |L3.48| +;;;433 } +;;;434 +;;;435 } +000030 bd10 POP {r4,pc} +;;;436 + ENDP + +000032 0000 DCW 0x0000 + |L3.52| + DCD s_ucOldCh + + AREA ||i.bsp_InitLed||, CODE, READONLY, ALIGN=2 + + bsp_InitLed PROC +;;;81 */ +;;;82 void bsp_InitLed(void) +000000 b508 PUSH {r3,lr} +;;;83 { +;;;84 GPIO_InitTypeDef GPIO_InitStructure; +;;;85 +;;;86 /* GPIOʱ */ +;;;87 RCC_APB2PeriphClockCmd(RCC_ALL_LED, ENABLE); +000002 2101 MOVS r1,#1 +000004 20f4 MOVS r0,#0xf4 +000006 f7fffffe BL RCC_APB2PeriphClockCmd +;;;88 +;;;89 /* +;;;90 еLEDָʾGPIOΪģʽ +;;;91 ڽGPIOΪʱGPIOĴֵȱʡ0˻LED. +;;;92 ҲϣģڸıGPIOΪǰȹرLEDָʾ +;;;93 */ +;;;94 bsp_LedOff(1); +00000a 2001 MOVS r0,#1 +00000c f7fffffe BL bsp_LedOff +;;;95 bsp_LedOff(2); +000010 2002 MOVS r0,#2 +000012 f7fffffe BL bsp_LedOff +;;;96 bsp_LedOff(3); +000016 2003 MOVS r0,#3 +000018 f7fffffe BL bsp_LedOff +;;;97 bsp_LedOff(4); +00001c 2004 MOVS r0,#4 +00001e f7fffffe BL bsp_LedOff +;;;98 bsp_LedOff(5); +000022 2005 MOVS r0,#5 +000024 f7fffffe BL bsp_LedOff +;;;99 bsp_LedOff(6); +000028 2006 MOVS r0,#6 +00002a f7fffffe BL bsp_LedOff +;;;100 bsp_LedOn(7); +00002e 2007 MOVS r0,#7 +000030 f7fffffe BL bsp_LedOn +;;;101 bsp_LedOff(8); +000034 2008 MOVS r0,#8 +000036 f7fffffe BL bsp_LedOff +;;;102 bsp_LedOff(9); +00003a 2009 MOVS r0,#9 +00003c f7fffffe BL bsp_LedOff +;;;103 bsp_LedOff(10); +000040 200a MOVS r0,#0xa +000042 f7fffffe BL bsp_LedOff +;;;104 bsp_LedOff(11); +000046 200b MOVS r0,#0xb +000048 f7fffffe BL bsp_LedOff +;;;105 bsp_LedOff(12); +00004c 200c MOVS r0,#0xc +00004e f7fffffe BL bsp_LedOff +;;;106 bsp_LedOff(13); +000052 200d MOVS r0,#0xd +000054 f7fffffe BL bsp_LedOff +;;;107 bsp_LedOff(14); +000058 200e MOVS r0,#0xe +00005a f7fffffe BL bsp_LedOff +;;;108 +;;;109 GPIO_InitStructure.GPIO_Speed = GPIO_Speed_50MHz; +00005e 2003 MOVS r0,#3 +000060 f88d0002 STRB r0,[sp,#2] +;;;110 GPIO_InitStructure.GPIO_Mode = GPIO_Mode_Out_PP; /* ģʽ */ +000064 2010 MOVS r0,#0x10 +000066 f88d0003 STRB r0,[sp,#3] +;;;111 +;;;112 RCC_APB2PeriphClockCmd(RCC_APB2Periph_GPIOA|RCC_APB2Periph_AFIO, ENABLE); +00006a 2101 MOVS r1,#1 +00006c 2005 MOVS r0,#5 +00006e f7fffffe BL RCC_APB2PeriphClockCmd +;;;113 GPIO_PinRemapConfig(GPIO_Remap_SWJ_JTAGDisable, ENABLE); +000072 2101 MOVS r1,#1 +000074 4834 LDR r0,|L4.328| +000076 f7fffffe BL GPIO_PinRemapConfig +;;;114 +;;;115 GPIO_InitStructure.GPIO_Pin = GPIO_PIN_LED1; +00007a f44f4000 MOV r0,#0x8000 +00007e f8ad0000 STRH r0,[sp,#0] +;;;116 GPIO_Init(GPIO_PORT_LED1, &GPIO_InitStructure); +000082 4669 MOV r1,sp +000084 4831 LDR r0,|L4.332| +000086 f7fffffe BL GPIO_Init +;;;117 +;;;118 GPIO_InitStructure.GPIO_Pin = GPIO_PIN_LED2; +00008a f44f6080 MOV r0,#0x400 +00008e f8ad0000 STRH r0,[sp,#0] +;;;119 GPIO_Init(GPIO_PORT_LED2, &GPIO_InitStructure); +000092 4669 MOV r1,sp +000094 482e LDR r0,|L4.336| +000096 f7fffffe BL GPIO_Init +;;;120 +;;;121 GPIO_InitStructure.GPIO_Pin = GPIO_PIN_LED3; +00009a f44f6000 MOV r0,#0x800 +00009e f8ad0000 STRH r0,[sp,#0] +;;;122 GPIO_Init(GPIO_PORT_LED3, &GPIO_InitStructure); +0000a2 4669 MOV r1,sp +0000a4 482a LDR r0,|L4.336| +0000a6 f7fffffe BL GPIO_Init +;;;123 +;;;124 GPIO_InitStructure.GPIO_Pin = GPIO_PIN_LED4; +0000aa f44f5080 MOV r0,#0x1000 +0000ae f8ad0000 STRH r0,[sp,#0] +;;;125 GPIO_Init(GPIO_PORT_LED4, &GPIO_InitStructure); +0000b2 4669 MOV r1,sp +0000b4 4826 LDR r0,|L4.336| +0000b6 f7fffffe BL GPIO_Init +;;;126 +;;;127 GPIO_InitStructure.GPIO_Pin = GPIO_PIN_LED5; +0000ba 2001 MOVS r0,#1 +0000bc f8ad0000 STRH r0,[sp,#0] +;;;128 GPIO_Init(GPIO_PORT_LED5, &GPIO_InitStructure); +0000c0 4669 MOV r1,sp +0000c2 4824 LDR r0,|L4.340| +0000c4 f7fffffe BL GPIO_Init +;;;129 +;;;130 GPIO_InitStructure.GPIO_Pin = GPIO_PIN_LED6; +0000c8 2002 MOVS r0,#2 +0000ca f8ad0000 STRH r0,[sp,#0] +;;;131 GPIO_Init(GPIO_PORT_LED6, &GPIO_InitStructure); +0000ce 4669 MOV r1,sp +0000d0 4820 LDR r0,|L4.340| +0000d2 f7fffffe BL GPIO_Init +;;;132 +;;;133 GPIO_InitStructure.GPIO_Pin = GPIO_PIN_LED7; +0000d6 2020 MOVS r0,#0x20 +0000d8 f8ad0000 STRH r0,[sp,#0] +;;;134 GPIO_Init(GPIO_PORT_LED7, &GPIO_InitStructure); +0000dc 4669 MOV r1,sp +0000de 481e LDR r0,|L4.344| +0000e0 f7fffffe BL GPIO_Init +;;;135 +;;;136 GPIO_InitStructure.GPIO_Pin = GPIO_PIN_LED8; +0000e4 2010 MOVS r0,#0x10 +0000e6 f8ad0000 STRH r0,[sp,#0] +;;;137 GPIO_Init(GPIO_PORT_LED8, &GPIO_InitStructure); +0000ea 4669 MOV r1,sp +0000ec 481a LDR r0,|L4.344| +0000ee f7fffffe BL GPIO_Init +;;;138 +;;;139 GPIO_InitStructure.GPIO_Pin = GPIO_PIN_LED9; +0000f2 2008 MOVS r0,#8 +0000f4 f8ad0000 STRH r0,[sp,#0] +;;;140 GPIO_Init(GPIO_PORT_LED9, &GPIO_InitStructure); +0000f8 4669 MOV r1,sp +0000fa 4817 LDR r0,|L4.344| +0000fc f7fffffe BL GPIO_Init +;;;141 +;;;142 GPIO_InitStructure.GPIO_Pin = GPIO_PIN_LED10; +000100 2004 MOVS r0,#4 +000102 f8ad0000 STRH r0,[sp,#0] +;;;143 GPIO_Init(GPIO_PORT_LED10, &GPIO_InitStructure); +000106 4669 MOV r1,sp +000108 4813 LDR r0,|L4.344| +00010a f7fffffe BL GPIO_Init +;;;144 +;;;145 GPIO_InitStructure.GPIO_Pin = GPIO_PIN_LED11; +00010e 2002 MOVS r0,#2 +000110 f8ad0000 STRH r0,[sp,#0] +;;;146 GPIO_Init(GPIO_PORT_LED11, &GPIO_InitStructure); +000114 4669 MOV r1,sp +000116 4810 LDR r0,|L4.344| +000118 f7fffffe BL GPIO_Init +;;;147 +;;;148 GPIO_InitStructure.GPIO_Pin = GPIO_PIN_LED12; +00011c 2001 MOVS r0,#1 +00011e f8ad0000 STRH r0,[sp,#0] +;;;149 GPIO_Init(GPIO_PORT_LED12, &GPIO_InitStructure); +000122 4669 MOV r1,sp +000124 480c LDR r0,|L4.344| +000126 f7fffffe BL GPIO_Init +;;;150 +;;;151 GPIO_InitStructure.GPIO_Pin = GPIO_PIN_LED13; +00012a 2020 MOVS r0,#0x20 +00012c f8ad0000 STRH r0,[sp,#0] +;;;152 GPIO_Init(GPIO_PORT_LED13, &GPIO_InitStructure); +000130 4669 MOV r1,sp +000132 480a LDR r0,|L4.348| +000134 f7fffffe BL GPIO_Init +;;;153 +;;;154 GPIO_InitStructure.GPIO_Pin = GPIO_PIN_LED14; +000138 2010 MOVS r0,#0x10 +00013a f8ad0000 STRH r0,[sp,#0] +;;;155 GPIO_Init(GPIO_PORT_LED14, &GPIO_InitStructure); +00013e 4669 MOV r1,sp +000140 4806 LDR r0,|L4.348| +000142 f7fffffe BL GPIO_Init +;;;156 +;;;157 } +000146 bd08 POP {r3,pc} +;;;158 + ENDP + + |L4.328| + DCD 0x00300200 + |L4.332| + DCD 0x40010800 + |L4.336| + DCD 0x40011000 + |L4.340| + DCD 0x40011400 + |L4.344| + DCD 0x40011c00 + |L4.348| + DCD 0x40011800 + + AREA ||i.bsp_IsLedOn||, CODE, READONLY, ALIGN=2 + + bsp_IsLedOn PROC +;;;335 */ +;;;336 uint8_t bsp_IsLedOn(uint8_t _no) +000000 4601 MOV r1,r0 +;;;337 { +;;;338 if (_no == 1) +000002 2901 CMP r1,#1 +000004 d108 BNE |L5.24| +;;;339 { +;;;340 if ((GPIO_PORT_LED1->ODR & GPIO_PIN_LED1) == 0) +000006 4816 LDR r0,|L5.96| +000008 6800 LDR r0,[r0,#0] +00000a f4004000 AND r0,r0,#0x8000 +00000e b908 CBNZ r0,|L5.20| +;;;341 { +;;;342 return 1; +000010 2001 MOVS r0,#1 + |L5.18| +;;;343 } +;;;344 return 0; +;;;345 } +;;;346 else if (_no == 2) +;;;347 { +;;;348 if ((GPIO_PORT_LED2->ODR & GPIO_PIN_LED2) == 0) +;;;349 { +;;;350 return 1; +;;;351 } +;;;352 return 0; +;;;353 } +;;;354 else if (_no == 3) +;;;355 { +;;;356 if ((GPIO_PORT_LED3->ODR & GPIO_PIN_LED3) == 0) +;;;357 { +;;;358 return 1; +;;;359 } +;;;360 return 0; +;;;361 } +;;;362 else if (_no == 4) +;;;363 { +;;;364 if ((GPIO_PORT_LED4->ODR & GPIO_PIN_LED4) == 0) +;;;365 { +;;;366 return 1; +;;;367 } +;;;368 return 0; +;;;369 } +;;;370 +;;;371 return 0; +;;;372 } +000012 4770 BX lr + |L5.20| +000014 2000 MOVS r0,#0 ;344 +000016 e7fc B |L5.18| + |L5.24| +000018 2902 CMP r1,#2 ;346 +00001a d108 BNE |L5.46| +00001c 4811 LDR r0,|L5.100| +00001e 68c0 LDR r0,[r0,#0xc] ;348 +000020 f4006080 AND r0,r0,#0x400 ;348 +000024 b908 CBNZ r0,|L5.42| +000026 2001 MOVS r0,#1 ;350 +000028 e7f3 B |L5.18| + |L5.42| +00002a 2000 MOVS r0,#0 ;352 +00002c e7f1 B |L5.18| + |L5.46| +00002e 2903 CMP r1,#3 ;354 +000030 d108 BNE |L5.68| +000032 480c LDR r0,|L5.100| +000034 68c0 LDR r0,[r0,#0xc] ;356 +000036 f4006000 AND r0,r0,#0x800 ;356 +00003a b908 CBNZ r0,|L5.64| +00003c 2001 MOVS r0,#1 ;358 +00003e e7e8 B |L5.18| + |L5.64| +000040 2000 MOVS r0,#0 ;360 +000042 e7e6 B |L5.18| + |L5.68| +000044 2904 CMP r1,#4 ;362 +000046 d108 BNE |L5.90| +000048 4806 LDR r0,|L5.100| +00004a 68c0 LDR r0,[r0,#0xc] ;364 +00004c f4005080 AND r0,r0,#0x1000 ;364 +000050 b908 CBNZ r0,|L5.86| +000052 2001 MOVS r0,#1 ;366 +000054 e7dd B |L5.18| + |L5.86| +000056 2000 MOVS r0,#0 ;368 +000058 e7db B |L5.18| + |L5.90| +00005a 2000 MOVS r0,#0 ;371 +00005c e7d9 B |L5.18| +;;;373 + ENDP + +00005e 0000 DCW 0x0000 + |L5.96| + DCD 0x4001080c + |L5.100| + DCD 0x40011000 + + AREA ||i.bsp_LedAllOff||, CODE, READONLY, ALIGN=1 + + bsp_LedAllOff PROC +;;;373 +;;;374 void bsp_LedAllOff(void) +000000 b500 PUSH {lr} +;;;375 { +;;;376 bsp_LedOff(1); +000002 2001 MOVS r0,#1 +000004 f7fffffe BL bsp_LedOff +;;;377 bsp_LedOff(2); +000008 2002 MOVS r0,#2 +00000a f7fffffe BL bsp_LedOff +;;;378 bsp_LedOff(3); +00000e 2003 MOVS r0,#3 +000010 f7fffffe BL bsp_LedOff +;;;379 bsp_LedOff(4); +000014 2004 MOVS r0,#4 +000016 f7fffffe BL bsp_LedOff +;;;380 bsp_LedOff(5); +00001a 2005 MOVS r0,#5 +00001c f7fffffe BL bsp_LedOff +;;;381 bsp_LedOff(6); +000020 2006 MOVS r0,#6 +000022 f7fffffe BL bsp_LedOff +;;;382 bsp_LedOff(7); +000026 2007 MOVS r0,#7 +000028 f7fffffe BL bsp_LedOff +;;;383 bsp_LedOff(8); +00002c 2008 MOVS r0,#8 +00002e f7fffffe BL bsp_LedOff +;;;384 bsp_LedOff(9); +000032 2009 MOVS r0,#9 +000034 f7fffffe BL bsp_LedOff +;;;385 bsp_LedOff(10); +000038 200a MOVS r0,#0xa +00003a f7fffffe BL bsp_LedOff +;;;386 bsp_LedOff(11); +00003e 200b MOVS r0,#0xb +000040 f7fffffe BL bsp_LedOff +;;;387 bsp_LedOff(12); +000044 200c MOVS r0,#0xc +000046 f7fffffe BL bsp_LedOff +;;;388 bsp_LedOff(13); +00004a 200d MOVS r0,#0xd +00004c f7fffffe BL bsp_LedOff +;;;389 bsp_LedOff(14); +000050 200e MOVS r0,#0xe +000052 f7fffffe BL bsp_LedOff +;;;390 } +000056 bd00 POP {pc} +;;;391 + ENDP + + + AREA ||i.bsp_LedOff||, CODE, READONLY, ALIGN=2 + + bsp_LedOff PROC +;;;166 */ +;;;167 void bsp_LedOff(uint8_t _no) +000000 1e41 SUBS r1,r0,#1 +;;;168 { +;;;169 _no--; +000002 b2c8 UXTB r0,r1 +;;;170 +;;;171 if (_no == 0) +000004 b920 CBNZ r0,|L7.16| +;;;172 { +;;;173 GPIO_PORT_LED1->BRR = GPIO_PIN_LED1; +000006 f44f4100 MOV r1,#0x8000 +00000a 4a29 LDR r2,|L7.176| +00000c 6011 STR r1,[r2,#0] +00000e e04d B |L7.172| + |L7.16| +;;;174 } +;;;175 else if (_no == 1) +000010 2801 CMP r0,#1 +000012 d103 BNE |L7.28| +;;;176 { +;;;177 GPIO_PORT_LED2->BRR = GPIO_PIN_LED2; +000014 0281 LSLS r1,r0,#10 +000016 4a27 LDR r2,|L7.180| +000018 6151 STR r1,[r2,#0x14] +00001a e047 B |L7.172| + |L7.28| +;;;178 } +;;;179 else if (_no == 2) +00001c 2802 CMP r0,#2 +00001e d103 BNE |L7.40| +;;;180 { +;;;181 GPIO_PORT_LED3->BRR = GPIO_PIN_LED3; +000020 0281 LSLS r1,r0,#10 +000022 4a24 LDR r2,|L7.180| +000024 6151 STR r1,[r2,#0x14] +000026 e041 B |L7.172| + |L7.40| +;;;182 } +;;;183 else if (_no == 3) +000028 2803 CMP r0,#3 +00002a d104 BNE |L7.54| +;;;184 { +;;;185 GPIO_PORT_LED4->BRR = GPIO_PIN_LED4; +00002c f44f5180 MOV r1,#0x1000 +000030 4a20 LDR r2,|L7.180| +000032 6151 STR r1,[r2,#0x14] +000034 e03a B |L7.172| + |L7.54| +;;;186 } +;;;187 else if (_no == 4) +000036 2804 CMP r0,#4 +000038 d103 BNE |L7.66| +;;;188 { +;;;189 GPIO_PORT_LED5->BRR = GPIO_PIN_LED5; +00003a 2101 MOVS r1,#1 +00003c 4a1e LDR r2,|L7.184| +00003e 6011 STR r1,[r2,#0] +000040 e034 B |L7.172| + |L7.66| +;;;190 } +;;;191 else if (_no == 5) +000042 2805 CMP r0,#5 +000044 d103 BNE |L7.78| +;;;192 { +;;;193 GPIO_PORT_LED6->BRR = GPIO_PIN_LED6; +000046 2102 MOVS r1,#2 +000048 4a1b LDR r2,|L7.184| +00004a 6011 STR r1,[r2,#0] +00004c e02e B |L7.172| + |L7.78| +;;;194 } +;;;195 else if (_no == 6) +00004e 2806 CMP r0,#6 +000050 d103 BNE |L7.90| +;;;196 { +;;;197 GPIO_PORT_LED7->BRR = GPIO_PIN_LED7; +000052 2120 MOVS r1,#0x20 +000054 4a19 LDR r2,|L7.188| +000056 6011 STR r1,[r2,#0] +000058 e028 B |L7.172| + |L7.90| +;;;198 } +;;;199 else if (_no == 7) +00005a 2807 CMP r0,#7 +00005c d103 BNE |L7.102| +;;;200 { +;;;201 GPIO_PORT_LED8->BRR = GPIO_PIN_LED8; +00005e 2110 MOVS r1,#0x10 +000060 4a16 LDR r2,|L7.188| +000062 6011 STR r1,[r2,#0] +000064 e022 B |L7.172| + |L7.102| +;;;202 } +;;;203 else if (_no == 8) +000066 2808 CMP r0,#8 +000068 d103 BNE |L7.114| +;;;204 { +;;;205 GPIO_PORT_LED9->BRR = GPIO_PIN_LED9; +00006a 2108 MOVS r1,#8 +00006c 4a13 LDR r2,|L7.188| +00006e 6011 STR r1,[r2,#0] +000070 e01c B |L7.172| + |L7.114| +;;;206 } +;;;207 else if (_no == 9) +000072 2809 CMP r0,#9 +000074 d103 BNE |L7.126| +;;;208 { +;;;209 GPIO_PORT_LED10->BRR = GPIO_PIN_LED10; +000076 2104 MOVS r1,#4 +000078 4a10 LDR r2,|L7.188| +00007a 6011 STR r1,[r2,#0] +00007c e016 B |L7.172| + |L7.126| +;;;210 } +;;;211 else if (_no == 10) +00007e 280a CMP r0,#0xa +000080 d103 BNE |L7.138| +;;;212 { +;;;213 GPIO_PORT_LED11->BRR = GPIO_PIN_LED11; +000082 2102 MOVS r1,#2 +000084 4a0d LDR r2,|L7.188| +000086 6011 STR r1,[r2,#0] +000088 e010 B |L7.172| + |L7.138| +;;;214 } +;;;215 else if (_no == 11) +00008a 280b CMP r0,#0xb +00008c d103 BNE |L7.150| +;;;216 { +;;;217 GPIO_PORT_LED12->BRR = GPIO_PIN_LED12; +00008e 2101 MOVS r1,#1 +000090 4a0a LDR r2,|L7.188| +000092 6011 STR r1,[r2,#0] +000094 e00a B |L7.172| + |L7.150| +;;;218 } +;;;219 else if (_no == 12) +000096 280c CMP r0,#0xc +000098 d103 BNE |L7.162| +;;;220 { +;;;221 GPIO_PORT_LED13->BRR = GPIO_PIN_LED13; +00009a 2120 MOVS r1,#0x20 +00009c 4a08 LDR r2,|L7.192| +00009e 6011 STR r1,[r2,#0] +0000a0 e004 B |L7.172| + |L7.162| +;;;222 } +;;;223 else if (_no == 13) +0000a2 280d CMP r0,#0xd +0000a4 d102 BNE |L7.172| +;;;224 { +;;;225 GPIO_PORT_LED14->BRR = GPIO_PIN_LED14; +0000a6 2110 MOVS r1,#0x10 +0000a8 4a05 LDR r2,|L7.192| +0000aa 6011 STR r1,[r2,#0] + |L7.172| +;;;226 } +;;;227 } +0000ac 4770 BX lr +;;;228 + ENDP + +0000ae 0000 DCW 0x0000 + |L7.176| + DCD 0x40010814 + |L7.180| + DCD 0x40011000 + |L7.184| + DCD 0x40011414 + |L7.188| + DCD 0x40011c14 + |L7.192| + DCD 0x40011814 + + AREA ||i.bsp_LedOn||, CODE, READONLY, ALIGN=2 + + bsp_LedOn PROC +;;;236 */ +;;;237 void bsp_LedOn(uint8_t _no) +000000 1e41 SUBS r1,r0,#1 +;;;238 { +;;;239 _no--; +000002 b2c8 UXTB r0,r1 +;;;240 +;;;241 if (_no == 0) +000004 b920 CBNZ r0,|L8.16| +;;;242 { +;;;243 GPIO_PORT_LED1->BSRR = GPIO_PIN_LED1; +000006 f44f4100 MOV r1,#0x8000 +00000a 4a29 LDR r2,|L8.176| +00000c 6011 STR r1,[r2,#0] +00000e e04d B |L8.172| + |L8.16| +;;;244 } +;;;245 else if (_no == 1) +000010 2801 CMP r0,#1 +000012 d103 BNE |L8.28| +;;;246 { +;;;247 GPIO_PORT_LED2->BSRR = GPIO_PIN_LED2; +000014 0281 LSLS r1,r0,#10 +000016 4a27 LDR r2,|L8.180| +000018 6111 STR r1,[r2,#0x10] +00001a e047 B |L8.172| + |L8.28| +;;;248 } +;;;249 else if (_no == 2) +00001c 2802 CMP r0,#2 +00001e d103 BNE |L8.40| +;;;250 { +;;;251 GPIO_PORT_LED3->BSRR = GPIO_PIN_LED3; +000020 0281 LSLS r1,r0,#10 +000022 4a24 LDR r2,|L8.180| +000024 6111 STR r1,[r2,#0x10] +000026 e041 B |L8.172| + |L8.40| +;;;252 } +;;;253 else if (_no == 3) +000028 2803 CMP r0,#3 +00002a d104 BNE |L8.54| +;;;254 { +;;;255 GPIO_PORT_LED4->BSRR = GPIO_PIN_LED4; +00002c f44f5180 MOV r1,#0x1000 +000030 4a20 LDR r2,|L8.180| +000032 6111 STR r1,[r2,#0x10] +000034 e03a B |L8.172| + |L8.54| +;;;256 } +;;;257 else if (_no == 4) +000036 2804 CMP r0,#4 +000038 d103 BNE |L8.66| +;;;258 { +;;;259 GPIO_PORT_LED5->BSRR = GPIO_PIN_LED5; +00003a 2101 MOVS r1,#1 +00003c 4a1e LDR r2,|L8.184| +00003e 6011 STR r1,[r2,#0] +000040 e034 B |L8.172| + |L8.66| +;;;260 } +;;;261 else if (_no == 5) +000042 2805 CMP r0,#5 +000044 d103 BNE |L8.78| +;;;262 { +;;;263 GPIO_PORT_LED6->BSRR = GPIO_PIN_LED6; +000046 2102 MOVS r1,#2 +000048 4a1b LDR r2,|L8.184| +00004a 6011 STR r1,[r2,#0] +00004c e02e B |L8.172| + |L8.78| +;;;264 } +;;;265 else if (_no == 6) +00004e 2806 CMP r0,#6 +000050 d103 BNE |L8.90| +;;;266 { +;;;267 GPIO_PORT_LED7->BSRR = GPIO_PIN_LED7; +000052 2120 MOVS r1,#0x20 +000054 4a19 LDR r2,|L8.188| +000056 6011 STR r1,[r2,#0] +000058 e028 B |L8.172| + |L8.90| +;;;268 } +;;;269 else if (_no == 7) +00005a 2807 CMP r0,#7 +00005c d103 BNE |L8.102| +;;;270 { +;;;271 GPIO_PORT_LED8->BSRR = GPIO_PIN_LED8; +00005e 2110 MOVS r1,#0x10 +000060 4a16 LDR r2,|L8.188| +000062 6011 STR r1,[r2,#0] +000064 e022 B |L8.172| + |L8.102| +;;;272 } +;;;273 else if (_no == 8) +000066 2808 CMP r0,#8 +000068 d103 BNE |L8.114| +;;;274 { +;;;275 GPIO_PORT_LED9->BSRR = GPIO_PIN_LED9; +00006a 2108 MOVS r1,#8 +00006c 4a13 LDR r2,|L8.188| +00006e 6011 STR r1,[r2,#0] +000070 e01c B |L8.172| + |L8.114| +;;;276 } +;;;277 else if (_no == 9) +000072 2809 CMP r0,#9 +000074 d103 BNE |L8.126| +;;;278 { +;;;279 GPIO_PORT_LED10->BSRR = GPIO_PIN_LED10; +000076 2104 MOVS r1,#4 +000078 4a10 LDR r2,|L8.188| +00007a 6011 STR r1,[r2,#0] +00007c e016 B |L8.172| + |L8.126| +;;;280 } +;;;281 else if (_no == 10) +00007e 280a CMP r0,#0xa +000080 d103 BNE |L8.138| +;;;282 { +;;;283 GPIO_PORT_LED11->BSRR = GPIO_PIN_LED11; +000082 2102 MOVS r1,#2 +000084 4a0d LDR r2,|L8.188| +000086 6011 STR r1,[r2,#0] +000088 e010 B |L8.172| + |L8.138| +;;;284 } +;;;285 else if (_no == 11) +00008a 280b CMP r0,#0xb +00008c d103 BNE |L8.150| +;;;286 { +;;;287 GPIO_PORT_LED12->BSRR = GPIO_PIN_LED12; +00008e 2101 MOVS r1,#1 +000090 4a0a LDR r2,|L8.188| +000092 6011 STR r1,[r2,#0] +000094 e00a B |L8.172| + |L8.150| +;;;288 } +;;;289 else if (_no == 12) +000096 280c CMP r0,#0xc +000098 d103 BNE |L8.162| +;;;290 { +;;;291 GPIO_PORT_LED13->BSRR = GPIO_PIN_LED13; +00009a 2120 MOVS r1,#0x20 +00009c 4a08 LDR r2,|L8.192| +00009e 6011 STR r1,[r2,#0] +0000a0 e004 B |L8.172| + |L8.162| +;;;292 } +;;;293 else if (_no == 13) +0000a2 280d CMP r0,#0xd +0000a4 d102 BNE |L8.172| +;;;294 { +;;;295 GPIO_PORT_LED14->BSRR = GPIO_PIN_LED14; +0000a6 2110 MOVS r1,#0x10 +0000a8 4a05 LDR r2,|L8.192| +0000aa 6011 STR r1,[r2,#0] + |L8.172| +;;;296 } +;;;297 +;;;298 } +0000ac 4770 BX lr +;;;299 + ENDP + +0000ae 0000 DCW 0x0000 + |L8.176| + DCD 0x40010810 + |L8.180| + DCD 0x40011000 + |L8.184| + DCD 0x40011410 + |L8.188| + DCD 0x40011c10 + |L8.192| + DCD 0x40011810 + + AREA ||i.bsp_LedToggle||, CODE, READONLY, ALIGN=2 + + bsp_LedToggle PROC +;;;307 */ +;;;308 void bsp_LedToggle(uint8_t _no) +000000 2801 CMP r0,#1 +;;;309 { +;;;310 if (_no == 1) +000002 d106 BNE |L9.18| +;;;311 { +;;;312 GPIO_PORT_LED1->ODR ^= GPIO_PIN_LED1; +000004 4910 LDR r1,|L9.72| +000006 6809 LDR r1,[r1,#0] +000008 f4814100 EOR r1,r1,#0x8000 +00000c 4a0e LDR r2,|L9.72| +00000e 6011 STR r1,[r2,#0] +000010 e019 B |L9.70| + |L9.18| +;;;313 } +;;;314 else if (_no == 2) +000012 2802 CMP r0,#2 +000014 d106 BNE |L9.36| +;;;315 { +;;;316 GPIO_PORT_LED2->ODR ^= GPIO_PIN_LED2; +000016 490d LDR r1,|L9.76| +000018 68c9 LDR r1,[r1,#0xc] +00001a f4816180 EOR r1,r1,#0x400 +00001e 4a0b LDR r2,|L9.76| +000020 60d1 STR r1,[r2,#0xc] +000022 e010 B |L9.70| + |L9.36| +;;;317 } +;;;318 else if (_no == 3) +000024 2803 CMP r0,#3 +000026 d106 BNE |L9.54| +;;;319 { +;;;320 GPIO_PORT_LED3->ODR ^= GPIO_PIN_LED3; +000028 4908 LDR r1,|L9.76| +00002a 68c9 LDR r1,[r1,#0xc] +00002c f4816100 EOR r1,r1,#0x800 +000030 4a06 LDR r2,|L9.76| +000032 60d1 STR r1,[r2,#0xc] +000034 e007 B |L9.70| + |L9.54| +;;;321 } +;;;322 else if (_no == 4) +000036 2804 CMP r0,#4 +000038 d105 BNE |L9.70| +;;;323 { +;;;324 GPIO_PORT_LED4->ODR ^= GPIO_PIN_LED4; +00003a 4904 LDR r1,|L9.76| +00003c 68c9 LDR r1,[r1,#0xc] +00003e f4815180 EOR r1,r1,#0x1000 +000042 4a02 LDR r2,|L9.76| +000044 60d1 STR r1,[r2,#0xc] + |L9.70| +;;;325 } +;;;326 } +000046 4770 BX lr +;;;327 + ENDP + + |L9.72| + DCD 0x4001080c + |L9.76| + DCD 0x40011000 + + AREA ||i.bsp_ResSelect||, CODE, READONLY, ALIGN=1 + + bsp_ResSelect PROC +;;;436 +;;;437 void bsp_ResSelect(uint8_t _res) +000000 b510 PUSH {r4,lr} +;;;438 { +000002 4604 MOV r4,r0 +;;;439 ResLedAllOff(); +000004 f7fffffe BL ResLedAllOff +;;;440 //printf("_res:%d\r\n",_res); +;;;441 bsp_LedOn(_res); +000008 4620 MOV r0,r4 +00000a f7fffffe BL bsp_LedOn +;;;442 bsp_SelectRes(_res); +00000e 4620 MOV r0,r4 +000010 f7fffffe BL bsp_SelectRes +;;;443 } +000014 bd10 POP {r4,pc} +;;;444 + ENDP + + + AREA ||.data||, DATA, ALIGN=0 + + s_ucOldCh +000000 ff DCB 0xff + +;*** Start embedded assembler *** + +#line 1 "..\\..\\User\\bsp\\src\\bsp_led.c" + AREA ||.rev16_text||, CODE + THUMB + EXPORT |__asm___9_bsp_led_c_ba23b041____REV16| +#line 114 "..\\..\\Libraries\\CMSIS\\Include\\core_cmInstr.h" +|__asm___9_bsp_led_c_ba23b041____REV16| PROC +#line 115 + + rev16 r0, r0 + bx lr + ENDP + AREA ||.revsh_text||, CODE + THUMB + EXPORT |__asm___9_bsp_led_c_ba23b041____REVSH| +#line 128 +|__asm___9_bsp_led_c_ba23b041____REVSH| PROC +#line 129 + + revsh r0, r0 + bx lr + ENDP + +;*** End embedded assembler *** diff --git a/Project/MDK-ARM/Flash/List/bsp_res.txt b/Project/MDK-ARM/Flash/List/bsp_res.txt new file mode 100644 index 0000000..3b3b230 --- /dev/null +++ b/Project/MDK-ARM/Flash/List/bsp_res.txt @@ -0,0 +1,349 @@ +; generated by Component: ARM Compiler 5.05 update 1 (build 106) Tool: ArmCC [4d0efa] +; commandline ArmCC [--list --split_sections --debug -c --asm --interleave -o.\flash\obj\bsp_res.o --asm_dir=.\Flash\List\ --list_dir=.\Flash\List\ --depend=.\flash\obj\bsp_res.d --cpu=Cortex-M3 --apcs=interwork -O0 --diag_suppress=9931,870 -I..\..\Libraries\CMSIS\Device\ST\STM32F10x\Include -I..\..\Libraries\STM32F10x_StdPeriph_Driver\inc -I..\..\Libraries\STM32_USB-FS-Device_Driver\inc -I..\..\Libraries\CMSIS\Include -I..\..\User\bsp -I..\..\User\bsp\inc -I..\..\User\app\inc -IC:\Keil_v5\ARM\RV31\INC -IC:\Keil_v5\ARM\CMSIS\Include -IC:\Keil_v5\ARM\Inc\ST\STM32F10x -D__MICROLIB -D__UVISION_VERSION=514 -DUSE_STDPERIPH_DRIVER -DSTM32F10X_HD --omf_browse=.\flash\obj\bsp_res.crf ..\..\User\bsp\src\bsp_res.c] + THUMB + + AREA ||i.bsp_InitRes||, CODE, READONLY, ALIGN=2 + + bsp_InitRes PROC +;;;39 //------------------------------------------------------------------------------ +;;;40 void bsp_InitRes(void) +000000 b508 PUSH {r3,lr} +;;;41 { +;;;42 GPIO_InitTypeDef GPIO_InitStructure; +;;;43 +;;;44 // GPIOʱ +;;;45 RCC_APB2PeriphClockCmd(RCC_ALL_RES, ENABLE); +000002 2101 MOVS r1,#1 +000004 2018 MOVS r0,#0x18 +000006 f7fffffe BL RCC_APB2PeriphClockCmd +;;;46 +;;;47 GPIO_InitStructure.GPIO_Speed = GPIO_Speed_50MHz; +00000a 2003 MOVS r0,#3 +00000c f88d0002 STRB r0,[sp,#2] +;;;48 GPIO_InitStructure.GPIO_Mode = GPIO_Mode_Out_PP; /* ģʽ */ +000010 2010 MOVS r0,#0x10 +000012 f88d0003 STRB r0,[sp,#3] +;;;49 +;;;50 GPIO_InitStructure.GPIO_Pin = GPIO_PIN_RES10; +000016 f8ad0000 STRH r0,[sp,#0] +;;;51 GPIO_Init(GPIO_PORT_RES10, &GPIO_InitStructure); +00001a 4669 MOV r1,sp +00001c 480c LDR r0,|L1.80| +00001e f7fffffe BL GPIO_Init +;;;52 +;;;53 GPIO_InitStructure.GPIO_Pin = GPIO_PIN_RES51_1; +000022 2020 MOVS r0,#0x20 +000024 f8ad0000 STRH r0,[sp,#0] +;;;54 GPIO_Init(GPIO_PORT_RES51_1, &GPIO_InitStructure); +000028 4669 MOV r1,sp +00002a 4809 LDR r0,|L1.80| +00002c f7fffffe BL GPIO_Init +;;;55 +;;;56 GPIO_InitStructure.GPIO_Pin = GPIO_PIN_RES51_2; +000030 2001 MOVS r0,#1 +000032 f8ad0000 STRH r0,[sp,#0] +;;;57 GPIO_Init(GPIO_PORT_RES51_2, &GPIO_InitStructure); +000036 4669 MOV r1,sp +000038 4806 LDR r0,|L1.84| +00003a f7fffffe BL GPIO_Init +;;;58 +;;;59 GPIO_InitStructure.GPIO_Pin = GPIO_PIN_RES100; +00003e 2002 MOVS r0,#2 +000040 f8ad0000 STRH r0,[sp,#0] +;;;60 GPIO_Init(GPIO_PORT_RES100, &GPIO_InitStructure); +000044 4669 MOV r1,sp +000046 4803 LDR r0,|L1.84| +000048 f7fffffe BL GPIO_Init +;;;61 } +00004c bd08 POP {r3,pc} +;;;62 + ENDP + +00004e 0000 DCW 0x0000 + |L1.80| + DCD 0x40011000 + |L1.84| + DCD 0x40010c00 + + AREA ||i.bsp_Port100_Output||, CODE, READONLY, ALIGN=2 + + bsp_Port100_Output PROC +;;;119 //------------------------------------------------------------------------------ +;;;120 void bsp_Port100_Output(uint8_t _status) +000000 b918 CBNZ r0,|L2.10| +;;;121 { +;;;122 if(_status==0) +;;;123 { +;;;124 GPIO_PORT_RES100->BRR = GPIO_PIN_RES100; +000002 2102 MOVS r1,#2 +000004 4a04 LDR r2,|L2.24| +000006 6011 STR r1,[r2,#0] +000008 e005 B |L2.22| + |L2.10| +;;;125 } +;;;126 else if(_status==1) +00000a 2801 CMP r0,#1 +00000c d103 BNE |L2.22| +;;;127 { +;;;128 GPIO_PORT_RES100->BSRR = GPIO_PIN_RES100; +00000e 2102 MOVS r1,#2 +000010 4a01 LDR r2,|L2.24| +000012 1f12 SUBS r2,r2,#4 +000014 6011 STR r1,[r2,#0] + |L2.22| +;;;129 } +;;;130 } +000016 4770 BX lr +;;;131 + ENDP + + |L2.24| + DCD 0x40010c14 + + AREA ||i.bsp_Port10_Output||, CODE, READONLY, ALIGN=2 + + bsp_Port10_Output PROC +;;;68 //------------------------------------------------------------------------------ +;;;69 void bsp_Port10_Output(uint8_t _status) +000000 b918 CBNZ r0,|L3.10| +;;;70 { +;;;71 if(_status==0) +;;;72 { +;;;73 GPIO_PORT_RES10->BRR = GPIO_PIN_RES10; +000002 2110 MOVS r1,#0x10 +000004 4a04 LDR r2,|L3.24| +000006 6151 STR r1,[r2,#0x14] +000008 e004 B |L3.20| + |L3.10| +;;;74 } +;;;75 else if(_status==1) +00000a 2801 CMP r0,#1 +00000c d102 BNE |L3.20| +;;;76 { +;;;77 GPIO_PORT_RES10->BSRR = GPIO_PIN_RES10; +00000e 2110 MOVS r1,#0x10 +000010 4a01 LDR r2,|L3.24| +000012 6111 STR r1,[r2,#0x10] + |L3.20| +;;;78 } +;;;79 } +000014 4770 BX lr +;;;80 //------------------------------------------------------------------------------ + ENDP + +000016 0000 DCW 0x0000 + |L3.24| + DCD 0x40011000 + + AREA ||i.bsp_Port51_1_Output||, CODE, READONLY, ALIGN=2 + + bsp_Port51_1_Output PROC +;;;85 //------------------------------------------------------------------------------ +;;;86 void bsp_Port51_1_Output(uint8_t _status) +000000 b918 CBNZ r0,|L4.10| +;;;87 { +;;;88 if(_status==0) +;;;89 { +;;;90 GPIO_PORT_RES51_1->BRR = GPIO_PIN_RES51_1; +000002 2120 MOVS r1,#0x20 +000004 4a04 LDR r2,|L4.24| +000006 6151 STR r1,[r2,#0x14] +000008 e004 B |L4.20| + |L4.10| +;;;91 } +;;;92 else if(_status==1) +00000a 2801 CMP r0,#1 +00000c d102 BNE |L4.20| +;;;93 { +;;;94 GPIO_PORT_RES51_1->BSRR = GPIO_PIN_RES51_1; +00000e 2120 MOVS r1,#0x20 +000010 4a01 LDR r2,|L4.24| +000012 6111 STR r1,[r2,#0x10] + |L4.20| +;;;95 } +;;;96 } +000014 4770 BX lr +;;;97 //------------------------------------------------------------------------------ + ENDP + +000016 0000 DCW 0x0000 + |L4.24| + DCD 0x40011000 + + AREA ||i.bsp_Port51_2_Output||, CODE, READONLY, ALIGN=2 + + bsp_Port51_2_Output PROC +;;;102 //------------------------------------------------------------------------------ +;;;103 void bsp_Port51_2_Output(uint8_t _status) +000000 b918 CBNZ r0,|L5.10| +;;;104 { +;;;105 if(_status==0) +;;;106 { +;;;107 GPIO_PORT_RES51_2->BRR = GPIO_PIN_RES51_2; +000002 2101 MOVS r1,#1 +000004 4a04 LDR r2,|L5.24| +000006 6011 STR r1,[r2,#0] +000008 e005 B |L5.22| + |L5.10| +;;;108 } +;;;109 else if(_status==1) +00000a 2801 CMP r0,#1 +00000c d103 BNE |L5.22| +;;;110 { +;;;111 GPIO_PORT_RES51_2->BSRR = GPIO_PIN_RES51_2; +00000e 2101 MOVS r1,#1 +000010 4a01 LDR r2,|L5.24| +000012 1f12 SUBS r2,r2,#4 +000014 6011 STR r1,[r2,#0] + |L5.22| +;;;112 } +;;;113 } +000016 4770 BX lr +;;;114 //------------------------------------------------------------------------------ + ENDP + + |L5.24| + DCD 0x40010c14 + + AREA ||i.bsp_SelectRes||, CODE, READONLY, ALIGN=1 + + bsp_SelectRes PROC +;;;137 //------------------------------------------------------------------------------ +;;;138 void bsp_SelectRes(uint8_t _res) +000000 b500 PUSH {lr} +;;;139 { +000002 4603 MOV r3,r0 +;;;140 switch(_res) +000004 1fd8 SUBS r0,r3,#7 +000006 2808 CMP r0,#8 +000008 d26d BCS |L6.230| +00000a e8dff000 TBB [pc,r0] +00000e 0411 DCB 0x04,0x11 +000010 1e2b3845 DCB 0x1e,0x2b,0x38,0x45 +000014 525f DCB 0x52,0x5f +;;;141 { +;;;142 case RES_0: +;;;143 bsp_Port10_Output(0);bsp_Port51_1_Output(0);bsp_Port51_2_Output(0);bsp_Port100_Output(0); break; +000016 2000 MOVS r0,#0 +000018 f7fffffe BL bsp_Port10_Output +00001c 2000 MOVS r0,#0 +00001e f7fffffe BL bsp_Port51_1_Output +000022 2000 MOVS r0,#0 +000024 f7fffffe BL bsp_Port51_2_Output +000028 2000 MOVS r0,#0 +00002a f7fffffe BL bsp_Port100_Output +00002e e05b B |L6.232| +;;;144 case RES_10: +;;;145 bsp_Port10_Output(1);bsp_Port51_1_Output(0);bsp_Port51_2_Output(0);bsp_Port100_Output(0); break; +000030 2001 MOVS r0,#1 +000032 f7fffffe BL bsp_Port10_Output +000036 2000 MOVS r0,#0 +000038 f7fffffe BL bsp_Port51_1_Output +00003c 2000 MOVS r0,#0 +00003e f7fffffe BL bsp_Port51_2_Output +000042 2000 MOVS r0,#0 +000044 f7fffffe BL bsp_Port100_Output +000048 e04e B |L6.232| +;;;146 case RES_61: +;;;147 bsp_Port10_Output(1);bsp_Port51_1_Output(1);bsp_Port51_2_Output(0);bsp_Port100_Output(0); break; +00004a 2001 MOVS r0,#1 +00004c f7fffffe BL bsp_Port10_Output +000050 2001 MOVS r0,#1 +000052 f7fffffe BL bsp_Port51_1_Output +000056 2000 MOVS r0,#0 +000058 f7fffffe BL bsp_Port51_2_Output +00005c 2000 MOVS r0,#0 +00005e f7fffffe BL bsp_Port100_Output +000062 e041 B |L6.232| +;;;148 case RES_100: +;;;149 bsp_Port10_Output(0);bsp_Port51_1_Output(0);bsp_Port51_2_Output(0);bsp_Port100_Output(1); break; +000064 2000 MOVS r0,#0 +000066 f7fffffe BL bsp_Port10_Output +00006a 2000 MOVS r0,#0 +00006c f7fffffe BL bsp_Port51_1_Output +000070 2000 MOVS r0,#0 +000072 f7fffffe BL bsp_Port51_2_Output +000076 2001 MOVS r0,#1 +000078 f7fffffe BL bsp_Port100_Output +00007c e034 B |L6.232| +;;;150 case RES_110: +;;;151 bsp_Port10_Output(1);bsp_Port51_1_Output(0);bsp_Port51_2_Output(0);bsp_Port100_Output(1); break; +00007e 2001 MOVS r0,#1 +000080 f7fffffe BL bsp_Port10_Output +000084 2000 MOVS r0,#0 +000086 f7fffffe BL bsp_Port51_1_Output +00008a 2000 MOVS r0,#0 +00008c f7fffffe BL bsp_Port51_2_Output +000090 2001 MOVS r0,#1 +000092 f7fffffe BL bsp_Port100_Output +000096 e027 B |L6.232| +;;;152 case RES_151: +;;;153 bsp_Port10_Output(0);bsp_Port51_1_Output(1);bsp_Port51_2_Output(0);bsp_Port100_Output(1); break; +000098 2000 MOVS r0,#0 +00009a f7fffffe BL bsp_Port10_Output +00009e 2001 MOVS r0,#1 +0000a0 f7fffffe BL bsp_Port51_1_Output +0000a4 2000 MOVS r0,#0 +0000a6 f7fffffe BL bsp_Port51_2_Output +0000aa 2001 MOVS r0,#1 +0000ac f7fffffe BL bsp_Port100_Output +0000b0 e01a B |L6.232| +;;;154 case RES_202: +;;;155 bsp_Port10_Output(0);bsp_Port51_1_Output(1);bsp_Port51_2_Output(1);bsp_Port100_Output(1); break; +0000b2 2000 MOVS r0,#0 +0000b4 f7fffffe BL bsp_Port10_Output +0000b8 2001 MOVS r0,#1 +0000ba f7fffffe BL bsp_Port51_1_Output +0000be 2001 MOVS r0,#1 +0000c0 f7fffffe BL bsp_Port51_2_Output +0000c4 2001 MOVS r0,#1 +0000c6 f7fffffe BL bsp_Port100_Output +0000ca e00d B |L6.232| +;;;156 case RES_212: +;;;157 bsp_Port10_Output(1);bsp_Port51_1_Output(1);bsp_Port51_2_Output(1);bsp_Port100_Output(1); break; +0000cc 2001 MOVS r0,#1 +0000ce f7fffffe BL bsp_Port10_Output +0000d2 2001 MOVS r0,#1 +0000d4 f7fffffe BL bsp_Port51_1_Output +0000d8 2001 MOVS r0,#1 +0000da f7fffffe BL bsp_Port51_2_Output +0000de 2001 MOVS r0,#1 +0000e0 f7fffffe BL bsp_Port100_Output +0000e4 e000 B |L6.232| + |L6.230| +;;;158 default: break; +0000e6 bf00 NOP + |L6.232| +0000e8 bf00 NOP ;143 +;;;159 } +;;;160 } +0000ea bd00 POP {pc} +;;;161 + ENDP + + +;*** Start embedded assembler *** + +#line 1 "..\\..\\User\\bsp\\src\\bsp_res.c" + AREA ||.rev16_text||, CODE + THUMB + EXPORT |__asm___9_bsp_res_c_2f48bbfc____REV16| +#line 114 "..\\..\\Libraries\\CMSIS\\Include\\core_cmInstr.h" +|__asm___9_bsp_res_c_2f48bbfc____REV16| PROC +#line 115 + + rev16 r0, r0 + bx lr + ENDP + AREA ||.revsh_text||, CODE + THUMB + EXPORT |__asm___9_bsp_res_c_2f48bbfc____REVSH| +#line 128 +|__asm___9_bsp_res_c_2f48bbfc____REVSH| PROC +#line 129 + + revsh r0, r0 + bx lr + ENDP + +;*** End embedded assembler *** diff --git a/Project/MDK-ARM/Flash/List/bsp_step_moto.txt b/Project/MDK-ARM/Flash/List/bsp_step_moto.txt new file mode 100644 index 0000000..d0b68c4 --- /dev/null +++ b/Project/MDK-ARM/Flash/List/bsp_step_moto.txt @@ -0,0 +1,562 @@ +; generated by Component: ARM Compiler 5.06 update 7 (build 960) Tool: ArmCC [4d365d] +; commandline ArmCC [--list --split_sections --debug -c --asm --interleave -o.\flash\obj\bsp_step_moto.o --asm_dir=.\Flash\List\ --list_dir=.\Flash\List\ --depend=.\flash\obj\bsp_step_moto.d --cpu=Cortex-M3 --apcs=interwork -O0 --diag_suppress=9931,870 -I..\..\Libraries\CMSIS\Device\ST\STM32F10x\Include -I..\..\Libraries\STM32F10x_StdPeriph_Driver\inc -I..\..\Libraries\STM32_USB-FS-Device_Driver\inc -I..\..\Libraries\CMSIS\Include -I..\..\User\bsp -I..\..\User\bsp\inc -I..\..\User\app\inc -I..\..\User -IC:\Users\w1619\AppData\Local\Arm\Packs\Keil\STM32F1xx_DFP\2.4.1\Device\Include -D__MICROLIB -D__UVISION_VERSION=538 -DSTM32F10X_HD -DUSE_STDPERIPH_DRIVER -DSTM32F10X_HD --omf_browse=.\flash\obj\bsp_step_moto.crf ..\..\User\bsp\src\bsp_step_moto.c] + THUMB + + AREA ||i.MOTO_ISR||, CODE, READONLY, ALIGN=2 + + MOTO_ISR PROC +;;;182 //------------------------------------------------------------------------------ +;;;183 void MOTO_ISR(void) +000000 e92d41f0 PUSH {r4-r8,lr} +;;;184 { +;;;185 if (g_tMoto.Running == 0) +000004 483c LDR r0,|L1.248| +000006 7e00 LDRB r0,[r0,#0x18] ; g_tMoto +000008 b908 CBNZ r0,|L1.14| + |L1.10| +;;;186 { +;;;187 return; +;;;188 } +;;;189 // BEEP_KeyTone(); +;;;190 +;;;191 // g_tMoto.Pos = 0; +;;;192 switch (g_tMoto.Pos) +;;;193 { +;;;194 case 0: +;;;195 { +;;;196 g_tMoto.Pos = 1; +;;;197 MOTO_STEP_1(); +;;;198 g_tMoto.prev_pv_pulse = g_tMoto.pv_pulse; +;;;199 if (g_tMoto.pv_pulse < g_tMoto.sv_pulse) +;;;200 { +;;;201 g_tMoto.pv_pulse++; +;;;202 } +;;;203 else if (g_tMoto.pv_pulse > g_tMoto.sv_pulse) +;;;204 { +;;;205 g_tMoto.pv_pulse--; +;;;206 } +;;;207 // 检测过零点：pv_pulse 每跨越一个 STEP_PER_LAP（即每转一圈）翻转PA6 +;;;208 if ((g_tMoto.prev_pv_pulse / STEP_PER_LAP) != (g_tMoto.pv_pulse / STEP_PER_LAP)) +;;;209 { +;;;210 ZERO_SIG_TOGGLE(); +;;;211 } +;;;212 break; +;;;213 } +;;;214 +;;;215 case 1: +;;;216 { +;;;217 g_tMoto.Pos = 0; +;;;218 MOTO_STEP_0(); +;;;219 g_tMoto.CurrentStep++; +;;;220 if (g_tMoto.pv_pulse == g_tMoto.sv_pulse) +;;;221 { +;;;222 MOTO_Stop(); +;;;223 TIM_ClearITPendingBit(TIM6, TIM_IT_Update); /* 清除中断标志位 */ +;;;224 } +;;;225 break; +;;;226 } +;;;227 default: +;;;228 break; +;;;229 } +;;;230 } +00000a e8bd81f0 POP {r4-r8,pc} + |L1.14| +00000e 483a LDR r0,|L1.248| +000010 7e40 LDRB r0,[r0,#0x19] ;192 ; g_tMoto +000012 b110 CBZ r0,|L1.26| +000014 2801 CMP r0,#1 ;192 +000016 d16b BNE |L1.240| +000018 e04e B |L1.184| + |L1.26| +00001a 2001 MOVS r0,#1 ;196 +00001c 4936 LDR r1,|L1.248| +00001e 7648 STRB r0,[r1,#0x19] ;196 +000020 2080 MOVS r0,#0x80 ;197 +000022 4936 LDR r1,|L1.252| +000024 6108 STR r0,[r1,#0x10] ;197 +000026 4834 LDR r0,|L1.248| +000028 e9d01008 LDRD r1,r0,[r0,#0x20] ;198 +00002c 4a32 LDR r2,|L1.248| +00002e e9c2100c STRD r1,r0,[r2,#0x30] ;198 +000032 4610 MOV r0,r2 ;199 +000034 e9d03008 LDRD r3,r0,[r0,#0x20] ;199 +000038 e9d2120a LDRD r1,r2,[r2,#0x28] ;199 +00003c 1a59 SUBS r1,r3,r1 ;199 +00003e 4190 SBCS r0,r0,r2 ;199 +000040 da09 BGE |L1.86| +000042 482d LDR r0,|L1.248| +000044 e9d01008 LDRD r1,r0,[r0,#0x20] ;201 +000048 1c49 ADDS r1,r1,#1 ;201 +00004a f1400000 ADC r0,r0,#0 ;201 +00004e 4a2a LDR r2,|L1.248| +000050 e9c21008 STRD r1,r0,[r2,#0x20] ;201 +000054 e011 B |L1.122| + |L1.86| +000056 4828 LDR r0,|L1.248| +000058 e9d0200a LDRD r2,r0,[r0,#0x28] ;203 +00005c 4926 LDR r1,|L1.248| +00005e e9d13108 LDRD r3,r1,[r1,#0x20] ;203 +000062 1ad2 SUBS r2,r2,r3 ;203 +000064 4188 SBCS r0,r0,r1 ;203 +000066 da08 BGE |L1.122| +000068 4823 LDR r0,|L1.248| +00006a e9d01008 LDRD r1,r0,[r0,#0x20] ;205 +00006e 1e49 SUBS r1,r1,#1 ;205 +000070 f1600000 SBC r0,r0,#0 ;205 +000074 4a20 LDR r2,|L1.248| +000076 e9c21008 STRD r1,r0,[r2,#0x20] ;205 + |L1.122| +00007a 481f LDR r0,|L1.248| +00007c f242120d MOV r2,#0x210d ;208 +000080 2300 MOVS r3,#0 ;208 +000082 e9d0410c LDRD r4,r1,[r0,#0x30] ;208 +000086 4620 MOV r0,r4 ;208 +000088 f7fffffe BL __aeabi_ldivmod +00008c 4606 MOV r6,r0 ;208 +00008e 460f MOV r7,r1 ;208 +000090 4819 LDR r0,|L1.248| +000092 f242120d MOV r2,#0x210d ;208 +000096 2300 MOVS r3,#0 ;208 +000098 e9d04108 LDRD r4,r1,[r0,#0x20] ;208 +00009c 4620 MOV r0,r4 ;208 +00009e f7fffffe BL __aeabi_ldivmod +0000a2 4046 EORS r6,r6,r0 ;208 +0000a4 404f EORS r7,r7,r1 ;208 +0000a6 433e ORRS r6,r6,r7 ;208 +0000a8 d005 BEQ |L1.182| +0000aa 4815 LDR r0,|L1.256| +0000ac 6800 LDR r0,[r0,#0] ;210 +0000ae f0800040 EOR r0,r0,#0x40 ;210 +0000b2 4913 LDR r1,|L1.256| +0000b4 6008 STR r0,[r1,#0] ;210 + |L1.182| +0000b6 e01c B |L1.242| + |L1.184| +0000b8 2000 MOVS r0,#0 ;217 +0000ba 490f LDR r1,|L1.248| +0000bc 7648 STRB r0,[r1,#0x19] ;217 +0000be 2080 MOVS r0,#0x80 ;218 +0000c0 490e LDR r1,|L1.252| +0000c2 6148 STR r0,[r1,#0x14] ;218 +0000c4 480c LDR r0,|L1.248| +0000c6 6900 LDR r0,[r0,#0x10] ;219 ; g_tMoto +0000c8 1c40 ADDS r0,r0,#1 ;219 +0000ca 490b LDR r1,|L1.248| +0000cc 6108 STR r0,[r1,#0x10] ;219 ; g_tMoto +0000ce 4608 MOV r0,r1 ;220 +0000d0 e9d01008 LDRD r1,r0,[r0,#0x20] ;220 +0000d4 4a08 LDR r2,|L1.248| +0000d6 e9d2320a LDRD r3,r2,[r2,#0x28] ;220 +0000da 4059 EORS r1,r1,r3 ;220 +0000dc 4050 EORS r0,r0,r2 ;220 +0000de 4301 ORRS r1,r1,r0 ;220 +0000e0 d105 BNE |L1.238| +0000e2 f7fffffe BL MOTO_Stop +0000e6 2101 MOVS r1,#1 ;223 +0000e8 4806 LDR r0,|L1.260| +0000ea f7fffffe BL TIM_ClearITPendingBit + |L1.238| +0000ee e000 B |L1.242| + |L1.240| +0000f0 bf00 NOP ;228 + |L1.242| +0000f2 bf00 NOP ;212 +0000f4 bf00 NOP +0000f6 e788 B |L1.10| +;;;231 + ENDP + + |L1.248| + DCD g_tMoto + |L1.252| + DCD 0x40011000 + |L1.256| + DCD 0x4001080c + |L1.260| + DCD 0x40001000 + + AREA ||i.MOTO_Pause||, CODE, READONLY, ALIGN=2 + + MOTO_Pause PROC +;;;148 //------------------------------------------------------------------------------ +;;;149 void MOTO_Pause(void) +000000 b510 PUSH {r4,lr} +;;;150 { +;;;151 // void bsp_SetTIMforInt(TIM_TypeDef* TIMx, uint32_t _ulFreq, uint8_t _PreemptionPriority, uint8_t _SubPriority) +;;;152 bsp_SetTIMforInt(TIM6, 0, 0, 0); +000002 2300 MOVS r3,#0 +000004 461a MOV r2,r3 +000006 4619 MOV r1,r3 +000008 4804 LDR r0,|L2.28| +00000a f7fffffe BL bsp_SetTIMforInt +;;;153 g_tMoto.Running = 0; +00000e 2000 MOVS r0,#0 +000010 4903 LDR r1,|L2.32| +000012 7608 STRB r0,[r1,#0x18] +;;;154 MOTO_STEP_0(); +000014 2080 MOVS r0,#0x80 +000016 4903 LDR r1,|L2.36| +000018 6148 STR r0,[r1,#0x14] +;;;155 // bsp_drv8880_enable_config(DISABLE); +;;;156 } +00001a bd10 POP {r4,pc} +;;;157 + ENDP + + |L2.28| + DCD 0x40001000 + |L2.32| + DCD g_tMoto + |L2.36| + DCD 0x40011000 + + AREA ||i.MOTO_RoudToStep||, CODE, READONLY, ALIGN=1 + + MOTO_RoudToStep PROC +;;;163 //------------------------------------------------------------------------------ +;;;164 uint32_t MOTO_RoudToStep(void) +000000 f44f6080 MOV r0,#0x400 +;;;165 { +;;;166 uint32_t steps; +;;;167 +;;;168 /* 28BYJ48 电机步距角度 = 5.625/64度. +;;;169 一圈 360度； +;;;170 step = 360 / (5.625 / 64) +;;;171 */ +;;;172 steps = (360 * 64 * 1000 / 4) / 5625; // 4096步 +;;;173 +;;;174 return steps; +;;;175 } +000004 4770 BX lr +;;;176 + ENDP + + + AREA ||i.MOTO_ShangeSpeed||, CODE, READONLY, ALIGN=2 + + MOTO_ShangeSpeed PROC +;;;101 //------------------------------------------------------------------------------ +;;;102 void MOTO_ShangeSpeed(uint32_t _speed) +000000 b510 PUSH {r4,lr} +;;;103 { +000002 4604 MOV r4,r0 +;;;104 g_tMoto.StepFreq = _speed; +000004 4805 LDR r0,|L4.28| +000006 6044 STR r4,[r0,#4] ; g_tMoto +;;;105 +;;;106 if (g_tMoto.Running == 1) +000008 7e00 LDRB r0,[r0,#0x18] ; g_tMoto +00000a 2801 CMP r0,#1 +00000c d105 BNE |L4.26| +;;;107 { +;;;108 // void bsp_SetTIMforInt(TIM_TypeDef* TIMx, uint32_t _ulFreq, uint8_t _PreemptionPriority, uint8_t _SubPriority) +;;;109 bsp_SetTIMforInt(TIM6, _speed, 2, 2); +00000e 2302 MOVS r3,#2 +000010 461a MOV r2,r3 +000012 4621 MOV r1,r4 +000014 4802 LDR r0,|L4.32| +000016 f7fffffe BL bsp_SetTIMforInt + |L4.26| +;;;110 } +;;;111 } +00001a bd10 POP {r4,pc} +;;;112 + ENDP + + |L4.28| + DCD g_tMoto + |L4.32| + DCD 0x40001000 + + AREA ||i.MOTO_Start||, CODE, READONLY, ALIGN=2 + + MOTO_Start PROC +;;;67 //------------------------------------------------------------------------------ +;;;68 void MOTO_Start(uint32_t _speed, uint8_t _dir, int32_t _stpes) +000000 b570 PUSH {r4-r6,lr} +;;;69 { +000002 4604 MOV r4,r0 +000004 460d MOV r5,r1 +000006 4616 MOV r6,r2 +;;;70 bsp_drv8880_enable_config(ENABLE); +000008 2001 MOVS r0,#1 +00000a f7fffffe BL bsp_drv8880_enable_config +;;;71 g_tMoto.Dir = _dir; +00000e 480f LDR r0,|L5.76| +000010 7005 STRB r5,[r0,#0] +;;;72 g_tMoto.StepFreq = _speed; +000012 6044 STR r4,[r0,#4] ; g_tMoto +;;;73 g_tMoto.StepCount = _stpes; +000014 6086 STR r6,[r0,#8] ; g_tMoto +;;;74 g_tMoto.AllStep = _stpes; +000016 60c6 STR r6,[r0,#0xc] ; g_tMoto +;;;75 g_tMoto.CurrentStep = 0; +000018 2000 MOVS r0,#0 +00001a 490c LDR r1,|L5.76| +00001c 6108 STR r0,[r1,#0x10] ; g_tMoto +;;;76 g_tMoto.Running = 1; +00001e 2001 MOVS r0,#1 +000020 7608 STRB r0,[r1,#0x18] +;;;77 +;;;78 // void bsp_SetTIMforInt(TIM_TypeDef* TIMx, uint32_t _ulFreq, uint8_t _PreemptionPriority, uint8_t _SubPriority) +;;;79 // bsp_SetTIMforInt(TIM6, _speed*2, 2, 2); +;;;80 switch (_dir) +000022 b12d CBZ r5,|L5.48| +000024 2d01 CMP r5,#1 +000026 d107 BNE |L5.56| +;;;81 { +;;;82 case 1: +;;;83 bsp_drv8880_config_dir(DIR_CW); +000028 2000 MOVS r0,#0 +00002a f7fffffe BL bsp_drv8880_config_dir +;;;84 break; +00002e e004 B |L5.58| + |L5.48| +;;;85 case 0: +;;;86 bsp_drv8880_config_dir(DIR_CCW); +000030 2001 MOVS r0,#1 +000032 f7fffffe BL bsp_drv8880_config_dir +;;;87 break; +000036 e000 B |L5.58| + |L5.56| +;;;88 default: +;;;89 break; +000038 bf00 NOP + |L5.58| +00003a bf00 NOP ;84 +;;;90 } +;;;91 bsp_SetTIMforInt(TIM6, _speed * 2, 0, 0); +00003c 0061 LSLS r1,r4,#1 +00003e 2300 MOVS r3,#0 +000040 461a MOV r2,r3 +000042 4803 LDR r0,|L5.80| +000044 f7fffffe BL bsp_SetTIMforInt +;;;92 } +000048 bd70 POP {r4-r6,pc} +;;;93 + ENDP + +00004a 0000 DCW 0x0000 + |L5.76| + DCD g_tMoto + |L5.80| + DCD 0x40001000 + + AREA ||i.MOTO_Stop||, CODE, READONLY, ALIGN=2 + + MOTO_Stop PROC +;;;128 //------------------------------------------------------------------------------ +;;;129 void MOTO_Stop(void) +000000 b510 PUSH {r4,lr} +;;;130 { +;;;131 // void bsp_SetTIMforInt(TIM_TypeDef* TIMx, uint32_t _ulFreq, uint8_t _PreemptionPriority, uint8_t _SubPriority) +;;;132 bsp_SetTIMforInt(TIM6, 0, 0, 0); +000002 2300 MOVS r3,#0 +000004 461a MOV r2,r3 +000006 4619 MOV r1,r3 +000008 4808 LDR r0,|L6.44| +00000a f7fffffe BL bsp_SetTIMforInt +;;;133 g_tMoto.Running = 0; +00000e 2000 MOVS r0,#0 +000010 4907 LDR r1,|L6.48| +000012 7608 STRB r0,[r1,#0x18] +;;;134 +;;;135 MOTO_STEP_0(); +000014 2080 MOVS r0,#0x80 +000016 4907 LDR r1,|L6.52| +000018 6148 STR r0,[r1,#0x14] +;;;136 // bsp_drv8880_enable_config(DISABLE); +;;;137 if (g_tTube.state == SEARCH) +00001a 4807 LDR r0,|L6.56| +00001c 7ac0 LDRB r0,[r0,#0xb] ; g_tTube +00001e 2802 CMP r0,#2 +000020 d102 BNE |L6.40| +;;;138 { +;;;139 g_tTube.state = IDLE; +000022 2000 MOVS r0,#0 +000024 4904 LDR r1,|L6.56| +000026 72c8 STRB r0,[r1,#0xb] + |L6.40| +;;;140 } +;;;141 } +000028 bd10 POP {r4,pc} +;;;142 + ENDP + +00002a 0000 DCW 0x0000 + |L6.44| + DCD 0x40001000 + |L6.48| + DCD g_tMoto + |L6.52| + DCD 0x40011000 + |L6.56| + DCD g_tTube + + AREA ||i.MOTO_ZorePos||, CODE, READONLY, ALIGN=2 + + MOTO_ZorePos PROC +;;;112 +;;;113 void MOTO_ZorePos(void) +000000 b510 PUSH {r4,lr} +;;;114 { +;;;115 MOTO_Stop(); +000002 f7fffffe BL MOTO_Stop +;;;116 g_tMoto.sv_pulse = 0; +000006 2100 MOVS r1,#0 +000008 4a08 LDR r2,|L7.44| +00000a 6291 STR r1,[r2,#0x28] ; g_tMoto +00000c 62d1 STR r1,[r2,#0x2c] ; g_tMoto +;;;117 g_tMoto.pv_pulse = 0; +00000e 6211 STR r1,[r2,#0x20] ; g_tMoto +000010 6251 STR r1,[r2,#0x24] ; g_tMoto +;;;118 g_tMoto.prev_pv_pulse = 0; +000012 6311 STR r1,[r2,#0x30] ; g_tMoto +000014 6351 STR r1,[r2,#0x34] ; g_tMoto +;;;119 GPIO_PORT_ZERO_SIG->BRR = GPIO_PIN_ZERO_SIG; // 归零时 PA6 输出低 +000016 2040 MOVS r0,#0x40 +000018 4905 LDR r1,|L7.48| +00001a 6008 STR r0,[r1,#0] +;;;120 BEEP_Start(1500, 5, 5, 3); +00001c 2303 MOVS r3,#3 +00001e 2205 MOVS r2,#5 +000020 4611 MOV r1,r2 +000022 f24050dc MOV r0,#0x5dc +000026 f7fffffe BL BEEP_Start +;;;121 } +00002a bd10 POP {r4,pc} +;;;122 + ENDP + + |L7.44| + DCD g_tMoto + |L7.48| + DCD 0x40010814 + + AREA ||i.TIM6_IRQHandler||, CODE, READONLY, ALIGN=2 + + TIM6_IRQHandler PROC +;;;238 #ifndef TIM6_ISR_MOVE_OUT /* bsp.h 中定义此行，表示本函数移到 stam32fxxx_it.c。 避免重复定义 */ +;;;239 void TIM6_IRQHandler(void) +000000 b510 PUSH {r4,lr} +;;;240 { +;;;241 if (TIM_GetITStatus(TIM6, TIM_IT_Update) != RESET) +000002 2101 MOVS r1,#1 +000004 4805 LDR r0,|L8.28| +000006 f7fffffe BL TIM_GetITStatus +00000a b128 CBZ r0,|L8.24| +;;;242 { +;;;243 MOTO_ISR(); /* 中断服务程序 */ +00000c f7fffffe BL MOTO_ISR +;;;244 +;;;245 TIM_ClearITPendingBit(TIM6, TIM_IT_Update); /* 清除中断标志位 */ +000010 2101 MOVS r1,#1 +000012 4802 LDR r0,|L8.28| +000014 f7fffffe BL TIM_ClearITPendingBit + |L8.24| +;;;246 } +;;;247 } +000018 bd10 POP {r4,pc} +;;;248 #endif + ENDP + +00001a 0000 DCW 0x0000 + |L8.28| + DCD 0x40001000 + + AREA ||i.bsp_InitStepMoto||, CODE, READONLY, ALIGN=2 + + bsp_InitStepMoto PROC +;;;37 //------------------------------------------------------------------------------ +;;;38 void bsp_InitStepMoto(void) +000000 b508 PUSH {r3,lr} +;;;39 { +;;;40 GPIO_InitTypeDef GPIO_InitStructure; +;;;41 +;;;42 // 初始化 PA6 为零位信号输出引脚 +;;;43 RCC_APB2PeriphClockCmd(RCC_APB2Periph_GPIOA, ENABLE); +000002 2101 MOVS r1,#1 +000004 2004 MOVS r0,#4 +000006 f7fffffe BL RCC_APB2PeriphClockCmd +;;;44 GPIO_InitStructure.GPIO_Pin = GPIO_PIN_ZERO_SIG; +00000a 2040 MOVS r0,#0x40 +00000c f8ad0000 STRH r0,[sp,#0] +;;;45 GPIO_InitStructure.GPIO_Mode = GPIO_Mode_Out_PP; +000010 2010 MOVS r0,#0x10 +000012 f88d0003 STRB r0,[sp,#3] +;;;46 GPIO_InitStructure.GPIO_Speed = GPIO_Speed_50MHz; +000016 2003 MOVS r0,#3 +000018 f88d0002 STRB r0,[sp,#2] +;;;47 GPIO_Init(GPIO_PORT_ZERO_SIG, &GPIO_InitStructure); +00001c 4669 MOV r1,sp +00001e 480b LDR r0,|L9.76| +000020 f7fffffe BL GPIO_Init +;;;48 GPIO_PORT_ZERO_SIG->BRR = GPIO_PIN_ZERO_SIG; // 默认输出低电平 +000024 2040 MOVS r0,#0x40 +000026 4909 LDR r1,|L9.76| +000028 3114 ADDS r1,r1,#0x14 +00002a 6008 STR r0,[r1,#0] +;;;49 +;;;50 g_tMoto.Dir = 0; +00002c 2000 MOVS r0,#0 +00002e 4908 LDR r1,|L9.80| +000030 7008 STRB r0,[r1,#0] +;;;51 g_tMoto.StepFreq = 0; +000032 6048 STR r0,[r1,#4] ; g_tMoto +;;;52 g_tMoto.StepCount = 0; +000034 6088 STR r0,[r1,#8] ; g_tMoto +;;;53 g_tMoto.Running = 0; +000036 7608 STRB r0,[r1,#0x18] +;;;54 g_tMoto.Pos = 0; +000038 7648 STRB r0,[r1,#0x19] +;;;55 g_tMoto.pv_pulse = 0; +00003a 2100 MOVS r1,#0 +00003c 4a04 LDR r2,|L9.80| +00003e 6211 STR r1,[r2,#0x20] ; g_tMoto +000040 6251 STR r1,[r2,#0x24] ; g_tMoto +;;;56 g_tMoto.sv_pulse = 0; +000042 6291 STR r1,[r2,#0x28] ; g_tMoto +000044 62d1 STR r1,[r2,#0x2c] ; g_tMoto +;;;57 g_tMoto.prev_pv_pulse = 0; +000046 6311 STR r1,[r2,#0x30] ; g_tMoto +000048 6351 STR r1,[r2,#0x34] ; g_tMoto +;;;58 } +00004a bd08 POP {r3,pc} +;;;59 + ENDP + + |L9.76| + DCD 0x40010800 + |L9.80| + DCD g_tMoto + + AREA ||.bss||, DATA, NOINIT, ALIGN=3 + + g_tMoto + % 56 + +;*** Start embedded assembler *** + +#line 1 "..\\..\\User\\bsp\\src\\bsp_step_moto.c" + AREA ||.rev16_text||, CODE + THUMB + EXPORT |__asm___15_bsp_step_moto_c_70f53da4____REV16| +#line 114 "..\\..\\Libraries\\CMSIS\\Include\\core_cmInstr.h" +|__asm___15_bsp_step_moto_c_70f53da4____REV16| PROC +#line 115 + + rev16 r0, r0 + bx lr + ENDP + AREA ||.revsh_text||, CODE + THUMB + EXPORT |__asm___15_bsp_step_moto_c_70f53da4____REVSH| +#line 128 +|__asm___15_bsp_step_moto_c_70f53da4____REVSH| PROC +#line 129 + + revsh r0, r0 + bx lr + ENDP + +;*** End embedded assembler *** diff --git a/Project/MDK-ARM/Flash/List/bsp_tim_pwm.txt b/Project/MDK-ARM/Flash/List/bsp_tim_pwm.txt new file mode 100644 index 0000000..dd9be1d --- /dev/null +++ b/Project/MDK-ARM/Flash/List/bsp_tim_pwm.txt @@ -0,0 +1,1447 @@ +; generated by Component: ARM Compiler 5.06 update 7 (build 960) Tool: ArmCC [4d365d] +; commandline ArmCC [--list --split_sections --debug -c --asm --interleave -o.\flash\obj\bsp_tim_pwm.o --asm_dir=.\Flash\List\ --list_dir=.\Flash\List\ --depend=.\flash\obj\bsp_tim_pwm.d --cpu=Cortex-M3 --apcs=interwork -O0 --diag_suppress=9931,870 -I..\..\Libraries\CMSIS\Device\ST\STM32F10x\Include -I..\..\Libraries\STM32F10x_StdPeriph_Driver\inc -I..\..\Libraries\STM32_USB-FS-Device_Driver\inc -I..\..\Libraries\CMSIS\Include -I..\..\User\bsp -I..\..\User\bsp\inc -I..\..\User\app\inc -I..\..\User -IC:\Users\w1619\AppData\Local\Arm\Packs\Keil\STM32F1xx_DFP\2.4.1\Device\Include -D__MICROLIB -D__UVISION_VERSION=538 -DSTM32F10X_HD -DUSE_STDPERIPH_DRIVER -DSTM32F10X_HD --omf_browse=.\flash\obj\bsp_tim_pwm.crf ..\..\User\bsp\src\bsp_tim_pwm.c] + THUMB + + AREA ||i.bsp_ConfigGpioOut||, CODE, READONLY, ALIGN=1 + + bsp_ConfigGpioOut PROC +;;;242 */ +;;;243 void bsp_ConfigGpioOut(GPIO_TypeDef *GPIOx, uint16_t GPIO_PinX) +000000 b5f8 PUSH {r3-r7,lr} +;;;244 { +000002 4605 MOV r5,r0 +000004 460c MOV r4,r1 +;;;245 GPIO_InitTypeDef GPIO_InitStructure; +;;;246 +;;;247 /* 使能GPIO时钟 */ +;;;248 RCC_APB2PeriphClockCmd(bsp_GetRCCofGPIO(GPIOx), ENABLE); +000006 4628 MOV r0,r5 +000008 f7fffffe BL bsp_GetRCCofGPIO +00000c 4606 MOV r6,r0 +00000e 2101 MOVS r1,#1 +000010 f7fffffe BL RCC_APB2PeriphClockCmd +;;;249 +;;;250 /* 配置GPIO */ +;;;251 GPIO_InitStructure.GPIO_Pin = GPIO_PinX; /* 带入的形参 */ +000014 f8ad4000 STRH r4,[sp,#0] +;;;252 GPIO_InitStructure.GPIO_Mode = GPIO_Mode_Out_PP; /* 输出 */ +000018 2010 MOVS r0,#0x10 +00001a f88d0003 STRB r0,[sp,#3] +;;;253 GPIO_InitStructure.GPIO_Speed = GPIO_Speed_50MHz; +00001e 2003 MOVS r0,#3 +000020 f88d0002 STRB r0,[sp,#2] +;;;254 GPIO_Init(GPIOx, &GPIO_InitStructure); +000024 4669 MOV r1,sp +000026 4628 MOV r0,r5 +000028 f7fffffe BL GPIO_Init +;;;255 } +00002c bdf8 POP {r3-r7,pc} +;;;256 + ENDP + + + AREA ||i.bsp_ConfigTimGpio||, CODE, READONLY, ALIGN=2 + + bsp_ConfigTimGpio PROC +;;;209 */ +;;;210 void bsp_ConfigTimGpio(GPIO_TypeDef *GPIOx, uint16_t GPIO_PinX, TIM_TypeDef *TIMx, uint8_t _ucChannel) +000000 e92d43f8 PUSH {r3-r9,lr} +;;;211 { +000004 4606 MOV r6,r0 +000006 460d MOV r5,r1 +000008 4614 MOV r4,r2 +00000a 4698 MOV r8,r3 +;;;212 GPIO_InitTypeDef GPIO_InitStructure; +;;;213 +;;;214 /* 使能GPIO时钟 */ +;;;215 RCC_APB2PeriphClockCmd(bsp_GetRCCofGPIO(GPIOx), ENABLE); +00000c 4630 MOV r0,r6 +00000e f7fffffe BL bsp_GetRCCofGPIO +000012 4607 MOV r7,r0 +000014 2101 MOVS r1,#1 +000016 f7fffffe BL RCC_APB2PeriphClockCmd +;;;216 +;;;217 /* 使能TIM时钟 */ +;;;218 if ((TIMx == TIM1) || (TIMx == TIM8)) +00001a 4811 LDR r0,|L2.96| +00001c 4284 CMP r4,r0 +00001e d002 BEQ |L2.38| +000020 4810 LDR r0,|L2.100| +000022 4284 CMP r4,r0 +000024 d107 BNE |L2.54| + |L2.38| +;;;219 { +;;;220 RCC_APB2PeriphClockCmd(bsp_GetRCCofTIM(TIMx), ENABLE); +000026 4620 MOV r0,r4 +000028 f7fffffe BL bsp_GetRCCofTIM +00002c 4607 MOV r7,r0 +00002e 2101 MOVS r1,#1 +000030 f7fffffe BL RCC_APB2PeriphClockCmd +000034 e006 B |L2.68| + |L2.54| +;;;221 } +;;;222 else +;;;223 { +;;;224 RCC_APB1PeriphClockCmd(bsp_GetRCCofTIM(TIMx), ENABLE); +000036 4620 MOV r0,r4 +000038 f7fffffe BL bsp_GetRCCofTIM +00003c 4607 MOV r7,r0 +00003e 2101 MOVS r1,#1 +000040 f7fffffe BL RCC_APB1PeriphClockCmd + |L2.68| +;;;225 } +;;;226 +;;;227 /* 配置GPIO */ +;;;228 GPIO_InitStructure.GPIO_Pin = GPIO_PinX; +000044 f8ad5000 STRH r5,[sp,#0] +;;;229 GPIO_InitStructure.GPIO_Mode = GPIO_Mode_AF_PP; /* 复用功能 */ +000048 2018 MOVS r0,#0x18 +00004a f88d0003 STRB r0,[sp,#3] +;;;230 GPIO_InitStructure.GPIO_Speed = GPIO_Speed_50MHz; +00004e 2003 MOVS r0,#3 +000050 f88d0002 STRB r0,[sp,#2] +;;;231 GPIO_Init(GPIOx, &GPIO_InitStructure); +000054 4669 MOV r1,sp +000056 4630 MOV r0,r6 +000058 f7fffffe BL GPIO_Init +;;;232 } +00005c e8bd83f8 POP {r3-r9,pc} +;;;233 + ENDP + + |L2.96| + DCD 0x40012c00 + |L2.100| + DCD 0x40013400 + + AREA ||i.bsp_GetRCCofGPIO||, CODE, READONLY, ALIGN=2 + + bsp_GetRCCofGPIO PROC +;;;85 */ +;;;86 uint32_t bsp_GetRCCofGPIO(GPIO_TypeDef *GPIOx) +000000 4601 MOV r1,r0 +;;;87 { +;;;88 uint32_t rcc = 0; +000002 2000 MOVS r0,#0 +;;;89 +;;;90 if (GPIOx == GPIOA) +000004 4a11 LDR r2,|L3.76| +000006 4291 CMP r1,r2 +000008 d101 BNE |L3.14| +;;;91 { +;;;92 rcc = RCC_APB2Periph_GPIOA; +00000a 2004 MOVS r0,#4 +00000c e01c B |L3.72| + |L3.14| +;;;93 } +;;;94 else if (GPIOx == GPIOB) +00000e 4a10 LDR r2,|L3.80| +000010 4291 CMP r1,r2 +000012 d101 BNE |L3.24| +;;;95 { +;;;96 rcc = RCC_APB2Periph_GPIOB; +000014 2008 MOVS r0,#8 +000016 e017 B |L3.72| + |L3.24| +;;;97 } +;;;98 else if (GPIOx == GPIOC) +000018 4a0e LDR r2,|L3.84| +00001a 4291 CMP r1,r2 +00001c d101 BNE |L3.34| +;;;99 { +;;;100 rcc = RCC_APB2Periph_GPIOC; +00001e 2010 MOVS r0,#0x10 +000020 e012 B |L3.72| + |L3.34| +;;;101 } +;;;102 else if (GPIOx == GPIOD) +000022 4a0d LDR r2,|L3.88| +000024 4291 CMP r1,r2 +000026 d101 BNE |L3.44| +;;;103 { +;;;104 rcc = RCC_APB2Periph_GPIOD; +000028 2020 MOVS r0,#0x20 +00002a e00d B |L3.72| + |L3.44| +;;;105 } +;;;106 else if (GPIOx == GPIOE) +00002c 4a0b LDR r2,|L3.92| +00002e 4291 CMP r1,r2 +000030 d101 BNE |L3.54| +;;;107 { +;;;108 rcc = RCC_APB2Periph_GPIOE; +000032 2040 MOVS r0,#0x40 +000034 e008 B |L3.72| + |L3.54| +;;;109 } +;;;110 else if (GPIOx == GPIOF) +000036 4a0a LDR r2,|L3.96| +000038 4291 CMP r1,r2 +00003a d101 BNE |L3.64| +;;;111 { +;;;112 rcc = RCC_APB2Periph_GPIOF; +00003c 2080 MOVS r0,#0x80 +00003e e003 B |L3.72| + |L3.64| +;;;113 } +;;;114 else if (GPIOx == GPIOG) +000040 4a08 LDR r2,|L3.100| +000042 4291 CMP r1,r2 +000044 d100 BNE |L3.72| +;;;115 { +;;;116 rcc = RCC_APB2Periph_GPIOG; +000046 1588 ASRS r0,r1,#22 + |L3.72| +;;;117 } +;;;118 +;;;119 return rcc; +;;;120 } +000048 4770 BX lr +;;;121 + ENDP + +00004a 0000 DCW 0x0000 + |L3.76| + DCD 0x40010800 + |L3.80| + DCD 0x40010c00 + |L3.84| + DCD 0x40011000 + |L3.88| + DCD 0x40011400 + |L3.92| + DCD 0x40011800 + |L3.96| + DCD 0x40011c00 + |L3.100| + DCD 0x40012000 + + AREA ||i.bsp_GetRCCofTIM||, CODE, READONLY, ALIGN=2 + + bsp_GetRCCofTIM PROC +;;;129 */ +;;;130 uint32_t bsp_GetRCCofTIM(TIM_TypeDef *TIMx) +000000 4601 MOV r1,r0 +;;;131 { +;;;132 uint32_t rcc = 0; +000002 2000 MOVS r0,#0 +;;;133 +;;;134 /* +;;;135 APB1 定时器有 TIM2, TIM3 ,TIM4, TIM5, TIM6, TIM7, TIM12, TIM13, TIM14 +;;;136 APB2 定时器有 TIM1, TIM8 ,TIM9, TIM10, TIM11 +;;;137 */ +;;;138 if (TIMx == TIM1) +000004 4a24 LDR r2,|L4.152| +000006 4291 CMP r1,r2 +000008 d101 BNE |L4.14| +;;;139 { +;;;140 rcc = RCC_APB2Periph_TIM1; +00000a 14c8 ASRS r0,r1,#19 +00000c e042 B |L4.148| + |L4.14| +;;;141 } +;;;142 else if (TIMx == TIM8) +00000e 4a23 LDR r2,|L4.156| +000010 4291 CMP r1,r2 +000012 d101 BNE |L4.24| +;;;143 { +;;;144 rcc = RCC_APB2Periph_TIM8; +000014 1448 ASRS r0,r1,#17 +000016 e03d B |L4.148| + |L4.24| +;;;145 } +;;;146 else if (TIMx == TIM9) +000018 4a21 LDR r2,|L4.160| +00001a 4291 CMP r1,r2 +00001c d102 BNE |L4.36| +;;;147 { +;;;148 rcc = RCC_APB2Periph_TIM9; +00001e f44f2000 MOV r0,#0x80000 +000022 e037 B |L4.148| + |L4.36| +;;;149 } +;;;150 else if (TIMx == TIM10) +000024 4a1f LDR r2,|L4.164| +000026 4291 CMP r1,r2 +000028 d102 BNE |L4.48| +;;;151 { +;;;152 rcc = RCC_APB2Periph_TIM10; +00002a f44f1080 MOV r0,#0x100000 +00002e e031 B |L4.148| + |L4.48| +;;;153 } +;;;154 else if (TIMx == TIM11) +000030 4a1d LDR r2,|L4.168| +000032 4291 CMP r1,r2 +000034 d102 BNE |L4.60| +;;;155 { +;;;156 rcc = RCC_APB2Periph_TIM11; +000036 f44f1000 MOV r0,#0x200000 +00003a e02b B |L4.148| + |L4.60| +;;;157 } +;;;158 /* 下面是 APB1时钟 */ +;;;159 else if (TIMx == TIM2) +00003c f1b14f80 CMP r1,#0x40000000 +000040 d101 BNE |L4.70| +;;;160 { +;;;161 rcc = RCC_APB1Periph_TIM2; +000042 2001 MOVS r0,#1 +000044 e026 B |L4.148| + |L4.70| +;;;162 } +;;;163 else if (TIMx == TIM3) +000046 4a19 LDR r2,|L4.172| +000048 4291 CMP r1,r2 +00004a d101 BNE |L4.80| +;;;164 { +;;;165 rcc = RCC_APB1Periph_TIM3; +00004c 2002 MOVS r0,#2 +00004e e021 B |L4.148| + |L4.80| +;;;166 } +;;;167 else if (TIMx == TIM4) +000050 4a17 LDR r2,|L4.176| +000052 4291 CMP r1,r2 +000054 d101 BNE |L4.90| +;;;168 { +;;;169 rcc = RCC_APB1Periph_TIM4; +000056 2004 MOVS r0,#4 +000058 e01c B |L4.148| + |L4.90| +;;;170 } +;;;171 else if (TIMx == TIM5) +00005a 4a16 LDR r2,|L4.180| +00005c 4291 CMP r1,r2 +00005e d101 BNE |L4.100| +;;;172 { +;;;173 rcc = RCC_APB1Periph_TIM5; +000060 2008 MOVS r0,#8 +000062 e017 B |L4.148| + |L4.100| +;;;174 } +;;;175 else if (TIMx == TIM6) +000064 4a14 LDR r2,|L4.184| +000066 4291 CMP r1,r2 +000068 d101 BNE |L4.110| +;;;176 { +;;;177 rcc = RCC_APB1Periph_TIM6; +00006a 2010 MOVS r0,#0x10 +00006c e012 B |L4.148| + |L4.110| +;;;178 } +;;;179 else if (TIMx == TIM7) +00006e 4a13 LDR r2,|L4.188| +000070 4291 CMP r1,r2 +000072 d101 BNE |L4.120| +;;;180 { +;;;181 rcc = RCC_APB1Periph_TIM7; +000074 2020 MOVS r0,#0x20 +000076 e00d B |L4.148| + |L4.120| +;;;182 } +;;;183 else if (TIMx == TIM12) +000078 4a11 LDR r2,|L4.192| +00007a 4291 CMP r1,r2 +00007c d101 BNE |L4.130| +;;;184 { +;;;185 rcc = RCC_APB1Periph_TIM12; +00007e 2040 MOVS r0,#0x40 +000080 e008 B |L4.148| + |L4.130| +;;;186 } +;;;187 else if (TIMx == TIM13) +000082 4a10 LDR r2,|L4.196| +000084 4291 CMP r1,r2 +000086 d101 BNE |L4.140| +;;;188 { +;;;189 rcc = RCC_APB1Periph_TIM13; +000088 2080 MOVS r0,#0x80 +00008a e003 B |L4.148| + |L4.140| +;;;190 } +;;;191 else if (TIMx == TIM14) +00008c 4a0e LDR r2,|L4.200| +00008e 4291 CMP r1,r2 +000090 d100 BNE |L4.148| +;;;192 { +;;;193 rcc = RCC_APB1Periph_TIM14; +000092 1588 ASRS r0,r1,#22 + |L4.148| +;;;194 } +;;;195 +;;;196 return rcc; +;;;197 } +000094 4770 BX lr +;;;198 + ENDP + +000096 0000 DCW 0x0000 + |L4.152| + DCD 0x40012c00 + |L4.156| + DCD 0x40013400 + |L4.160| + DCD 0x40014c00 + |L4.164| + DCD 0x40015000 + |L4.168| + DCD 0x40015400 + |L4.172| + DCD 0x40000400 + |L4.176| + DCD 0x40000800 + |L4.180| + DCD 0x40000c00 + |L4.184| + DCD 0x40001000 + |L4.188| + DCD 0x40001400 + |L4.192| + DCD 0x40001800 + |L4.196| + DCD 0x40001c00 + |L4.200| + DCD 0x40002000 + + AREA ||i.bsp_SetTIMOutPWM||, CODE, READONLY, ALIGN=2 + + bsp_SetTIMOutPWM PROC +;;;266 */ +;;;267 void bsp_SetTIMOutPWM(GPIO_TypeDef *GPIOx, uint16_t GPIO_Pin, TIM_TypeDef *TIMx, uint8_t _ucChannel, +000000 e92d4fff PUSH {r0-r11,lr} +;;;268 uint32_t _ulFreq, uint32_t _ulDutyCycle) +;;;269 { +000004 b087 SUB sp,sp,#0x1c +000006 4683 MOV r11,r0 +000008 4614 MOV r4,r2 +00000a 461d MOV r5,r3 +00000c e9dd6a14 LDRD r6,r10,[sp,#0x50] +;;;270 TIM_TimeBaseInitTypeDef TIM_TimeBaseStructure; +;;;271 TIM_OCInitTypeDef TIM_OCInitStructure; +;;;272 uint16_t usPeriod; +;;;273 uint16_t usPrescaler; +;;;274 uint32_t uiTIMxCLK; +;;;275 +;;;276 if (_ulDutyCycle == 0) +000010 f1ba0f00 CMP r10,#0 +000014 d10f BNE |L5.54| +;;;277 { +;;;278 TIM_Cmd(TIMx, DISABLE); /* 关闭PWM输出 */ +000016 2100 MOVS r1,#0 +000018 4620 MOV r0,r4 +00001a f7fffffe BL TIM_Cmd +;;;279 bsp_ConfigGpioOut(GPIOx, GPIO_Pin); /* 配置GPIO为推挽输出 */ +00001e 4658 MOV r0,r11 +000020 9908 LDR r1,[sp,#0x20] +000022 f7fffffe BL bsp_ConfigGpioOut +;;;280 GPIO_WriteBit(GPIOx, GPIO_Pin, Bit_RESET); /* PWM = 0 */ +000026 2200 MOVS r2,#0 +000028 4658 MOV r0,r11 +00002a 9908 LDR r1,[sp,#0x20] +00002c f7fffffe BL GPIO_WriteBit + |L5.48| +;;;281 return; +;;;282 } +;;;283 else if (_ulDutyCycle == 10000) +;;;284 { +;;;285 TIM_Cmd(TIMx, DISABLE); /* 关闭PWM输出 */ +;;;286 +;;;287 bsp_ConfigGpioOut(GPIOx, GPIO_Pin); /* 配置GPIO为推挽输出 */ +;;;288 GPIO_WriteBit(GPIOx, GPIO_Pin, Bit_SET); /* PWM = 1 */ +;;;289 return; +;;;290 } +;;;291 +;;;292 bsp_ConfigTimGpio(GPIOx, GPIO_Pin, TIMx, _ucChannel); /* 使能GPIO和TIM时钟，并连接TIM通道到GPIO */ +;;;293 +;;;294 /*----------------------------------------------------------------------- +;;;295 system_stm32f4xx.c 文件中 void SetSysClock(void) 函数对时钟的配置如下： +;;;296 +;;;297 HCLK = SYSCLK / 1 (AHB1Periph) +;;;298 PCLK2 = HCLK / 2 (APB2Periph) +;;;299 PCLK1 = HCLK / 4 (APB1Periph) +;;;300 +;;;301 因为APB1 prescaler != 1, 所以 APB1上的TIMxCLK = PCLK1 x 2 = SystemCoreClock / 2; +;;;302 因为APB2 prescaler != 1, 所以 APB2上的TIMxCLK = PCLK2 x 2 = SystemCoreClock; +;;;303 +;;;304 APB1 定时器有 TIM2, TIM3 ,TIM4, TIM5, TIM6, TIM6, TIM12, TIM13,TIM14 +;;;305 APB2 定时器有 TIM1, TIM8 ,TIM9, TIM10, TIM11 +;;;306 +;;;307 ----------------------------------------------------------------------- */ +;;;308 if ((TIMx == TIM1) || (TIMx == TIM8) || (TIMx == TIM9) || (TIMx == TIM10) || (TIMx == TIM11)) +;;;309 { +;;;310 /* APB2 定时器 */ +;;;311 uiTIMxCLK = SystemCoreClock; +;;;312 } +;;;313 else /* APB1 定时器 */ +;;;314 { +;;;315 uiTIMxCLK = SystemCoreClock; // SystemCoreClock / 2; +;;;316 } +;;;317 +;;;318 if (_ulFreq < 100) +;;;319 { +;;;320 usPrescaler = 10000 - 1; /* 分频比 = 10000 */ +;;;321 usPeriod = (uiTIMxCLK / 10000) / _ulFreq - 1; /* 自动重装的值 */ +;;;322 } +;;;323 else if (_ulFreq < 3000) +;;;324 { +;;;325 usPrescaler = 100 - 1; /* 分频比 = 100 */ +;;;326 usPeriod = (uiTIMxCLK / 100) / _ulFreq - 1; /* 自动重装的值 */ +;;;327 } +;;;328 else /* 大于4K的频率，无需分频 */ +;;;329 { +;;;330 usPrescaler = 0; /* 分频比 = 1 */ +;;;331 usPeriod = uiTIMxCLK / _ulFreq - 1; /* 自动重装的值 */ +;;;332 } +;;;333 +;;;334 /* Time base configuration */ +;;;335 TIM_TimeBaseStructure.TIM_Period = usPeriod; +;;;336 TIM_TimeBaseStructure.TIM_Prescaler = usPrescaler; +;;;337 TIM_TimeBaseStructure.TIM_ClockDivision = 0; +;;;338 TIM_TimeBaseStructure.TIM_CounterMode = TIM_CounterMode_Up; +;;;339 TIM_TimeBaseStructure.TIM_RepetitionCounter = 0; +;;;340 TIM_TimeBaseInit(TIMx, &TIM_TimeBaseStructure); +;;;341 +;;;342 /* PWM1 Mode configuration: Channel1 */ +;;;343 TIM_OCStructInit(&TIM_OCInitStructure); /* 初始化结构体成员 */ +;;;344 +;;;345 TIM_OCInitStructure.TIM_OCMode = TIM_OCMode_PWM1; +;;;346 TIM_OCInitStructure.TIM_OutputState = TIM_OutputState_Enable; +;;;347 TIM_OCInitStructure.TIM_Pulse = (_ulDutyCycle * usPeriod) / 10000; +;;;348 TIM_OCInitStructure.TIM_OCPolarity = TIM_OCPolarity_High; +;;;349 +;;;350 TIM_OCInitStructure.TIM_OutputNState = TIM_OutputNState_Disable; /* only for TIM1 and TIM8. */ +;;;351 TIM_OCInitStructure.TIM_OCNPolarity = TIM_OCNPolarity_High; /* only for TIM1 and TIM8. */ +;;;352 TIM_OCInitStructure.TIM_OCIdleState = TIM_OCIdleState_Reset; /* only for TIM1 and TIM8. */ +;;;353 TIM_OCInitStructure.TIM_OCNIdleState = TIM_OCNIdleState_Reset; /* only for TIM1 and TIM8. */ +;;;354 +;;;355 if (_ucChannel == 1) +;;;356 { +;;;357 TIM_OC1Init(TIMx, &TIM_OCInitStructure); +;;;358 TIM_OC1PreloadConfig(TIMx, TIM_OCPreload_Enable); +;;;359 } +;;;360 else if (_ucChannel == 2) +;;;361 { +;;;362 TIM_OC2Init(TIMx, &TIM_OCInitStructure); +;;;363 TIM_OC2PreloadConfig(TIMx, TIM_OCPreload_Enable); +;;;364 } +;;;365 else if (_ucChannel == 3) +;;;366 { +;;;367 TIM_OC3Init(TIMx, &TIM_OCInitStructure); +;;;368 TIM_OC3PreloadConfig(TIMx, TIM_OCPreload_Enable); +;;;369 } +;;;370 else if (_ucChannel == 4) +;;;371 { +;;;372 TIM_OC4Init(TIMx, &TIM_OCInitStructure); +;;;373 TIM_OC4PreloadConfig(TIMx, TIM_OCPreload_Enable); +;;;374 } +;;;375 +;;;376 TIM_ARRPreloadConfig(TIMx, ENABLE); +;;;377 +;;;378 /* TIMx enable counter */ +;;;379 TIM_Cmd(TIMx, ENABLE); +;;;380 +;;;381 /* 下面这句话对于TIM1和TIM8是必须的，对于TIM2-TIM6则不必要 */ +;;;382 if ((TIMx == TIM1) || (TIMx == TIM8)) +;;;383 { +;;;384 TIM_CtrlPWMOutputs(TIMx, ENABLE); +;;;385 } +;;;386 } +000030 b00b ADD sp,sp,#0x2c +000032 e8bd8ff0 POP {r4-r11,pc} + |L5.54| +000036 f2427010 MOV r0,#0x2710 ;283 +00003a 4582 CMP r10,r0 ;283 +00003c d10d BNE |L5.90| +00003e 2100 MOVS r1,#0 ;285 +000040 4620 MOV r0,r4 ;285 +000042 f7fffffe BL TIM_Cmd +000046 4658 MOV r0,r11 ;287 +000048 9908 LDR r1,[sp,#0x20] ;287 +00004a f7fffffe BL bsp_ConfigGpioOut +00004e 2201 MOVS r2,#1 ;288 +000050 4658 MOV r0,r11 ;288 +000052 9908 LDR r1,[sp,#0x20] ;288 +000054 f7fffffe BL GPIO_WriteBit +000058 e7ea B |L5.48| + |L5.90| +00005a 462b MOV r3,r5 ;292 +00005c 4622 MOV r2,r4 ;292 +00005e 4658 MOV r0,r11 ;292 +000060 9908 LDR r1,[sp,#0x20] ;292 +000062 f7fffffe BL bsp_ConfigTimGpio +000066 4851 LDR r0,|L5.428| +000068 4284 CMP r4,r0 ;308 +00006a d00b BEQ |L5.132| +00006c 4850 LDR r0,|L5.432| +00006e 4284 CMP r4,r0 ;308 +000070 d008 BEQ |L5.132| +000072 4850 LDR r0,|L5.436| +000074 4284 CMP r4,r0 ;308 +000076 d005 BEQ |L5.132| +000078 484f LDR r0,|L5.440| +00007a 4284 CMP r4,r0 ;308 +00007c d002 BEQ |L5.132| +00007e 484f LDR r0,|L5.444| +000080 4284 CMP r4,r0 ;308 +000082 d103 BNE |L5.140| + |L5.132| +000084 484e LDR r0,|L5.448| +000086 f8d08000 LDR r8,[r0,#0] ;311 ; SystemCoreClock +00008a e002 B |L5.146| + |L5.140| +00008c 484c LDR r0,|L5.448| +00008e f8d08000 LDR r8,[r0,#0] ;315 ; SystemCoreClock + |L5.146| +000092 2e64 CMP r6,#0x64 ;318 +000094 d20a BCS |L5.172| +000096 f242790f MOV r9,#0x270f ;320 +00009a f2427010 MOV r0,#0x2710 ;321 +00009e fbb8f0f0 UDIV r0,r8,r0 ;321 +0000a2 fbb0f0f6 UDIV r0,r0,r6 ;321 +0000a6 1e40 SUBS r0,r0,#1 ;321 +0000a8 b287 UXTH r7,r0 ;321 +0000aa e013 B |L5.212| + |L5.172| +0000ac f64030b8 MOV r0,#0xbb8 ;323 +0000b0 4286 CMP r6,r0 ;323 +0000b2 d209 BCS |L5.200| +0000b4 f04f0963 MOV r9,#0x63 ;325 +0000b8 2064 MOVS r0,#0x64 ;326 +0000ba fbb8f0f0 UDIV r0,r8,r0 ;326 +0000be fbb0f0f6 UDIV r0,r0,r6 ;326 +0000c2 1e40 SUBS r0,r0,#1 ;326 +0000c4 b287 UXTH r7,r0 ;326 +0000c6 e005 B |L5.212| + |L5.200| +0000c8 f04f0900 MOV r9,#0 ;330 +0000cc fbb8f0f6 UDIV r0,r8,r6 ;331 +0000d0 1e40 SUBS r0,r0,#1 ;331 +0000d2 b287 UXTH r7,r0 ;331 + |L5.212| +0000d4 f8ad7014 STRH r7,[sp,#0x14] ;335 +0000d8 f8ad9010 STRH r9,[sp,#0x10] ;336 +0000dc 2000 MOVS r0,#0 ;337 +0000de f8ad0016 STRH r0,[sp,#0x16] ;337 +0000e2 f8ad0012 STRH r0,[sp,#0x12] ;338 +0000e6 f88d0018 STRB r0,[sp,#0x18] ;339 +0000ea a904 ADD r1,sp,#0x10 ;340 +0000ec 4620 MOV r0,r4 ;340 +0000ee f7fffffe BL TIM_TimeBaseInit +0000f2 4668 MOV r0,sp ;343 +0000f4 f7fffffe BL TIM_OCStructInit +0000f8 2060 MOVS r0,#0x60 ;345 +0000fa f8ad0000 STRH r0,[sp,#0] ;345 +0000fe 2001 MOVS r0,#1 ;346 +000100 f8ad0002 STRH r0,[sp,#2] ;346 +000104 fb0af007 MUL r0,r10,r7 ;347 +000108 f2427110 MOV r1,#0x2710 ;347 +00010c fbb0f0f1 UDIV r0,r0,r1 ;347 +000110 b280 UXTH r0,r0 ;347 +000112 f8ad0006 STRH r0,[sp,#6] ;347 +000116 2000 MOVS r0,#0 ;348 +000118 f8ad0008 STRH r0,[sp,#8] ;348 +00011c f8ad0004 STRH r0,[sp,#4] ;350 +000120 f8ad000a STRH r0,[sp,#0xa] ;351 +000124 f8ad000c STRH r0,[sp,#0xc] ;352 +000128 f8ad000e STRH r0,[sp,#0xe] ;353 +00012c 2d01 CMP r5,#1 ;355 +00012e d108 BNE |L5.322| +000130 4669 MOV r1,sp ;357 +000132 4620 MOV r0,r4 ;357 +000134 f7fffffe BL TIM_OC1Init +000138 2108 MOVS r1,#8 ;358 +00013a 4620 MOV r0,r4 ;358 +00013c f7fffffe BL TIM_OC1PreloadConfig +000140 e01f B |L5.386| + |L5.322| +000142 2d02 CMP r5,#2 ;360 +000144 d108 BNE |L5.344| +000146 4669 MOV r1,sp ;362 +000148 4620 MOV r0,r4 ;362 +00014a f7fffffe BL TIM_OC2Init +00014e 2108 MOVS r1,#8 ;363 +000150 4620 MOV r0,r4 ;363 +000152 f7fffffe BL TIM_OC2PreloadConfig +000156 e014 B |L5.386| + |L5.344| +000158 2d03 CMP r5,#3 ;365 +00015a d108 BNE |L5.366| +00015c 4669 MOV r1,sp ;367 +00015e 4620 MOV r0,r4 ;367 +000160 f7fffffe BL TIM_OC3Init +000164 2108 MOVS r1,#8 ;368 +000166 4620 MOV r0,r4 ;368 +000168 f7fffffe BL TIM_OC3PreloadConfig +00016c e009 B |L5.386| + |L5.366| +00016e 2d04 CMP r5,#4 ;370 +000170 d107 BNE |L5.386| +000172 4669 MOV r1,sp ;372 +000174 4620 MOV r0,r4 ;372 +000176 f7fffffe BL TIM_OC4Init +00017a 2108 MOVS r1,#8 ;373 +00017c 4620 MOV r0,r4 ;373 +00017e f7fffffe BL TIM_OC4PreloadConfig + |L5.386| +000182 2101 MOVS r1,#1 ;376 +000184 4620 MOV r0,r4 ;376 +000186 f7fffffe BL TIM_ARRPreloadConfig +00018a 2101 MOVS r1,#1 ;379 +00018c 4620 MOV r0,r4 ;379 +00018e f7fffffe BL TIM_Cmd +000192 4806 LDR r0,|L5.428| +000194 4284 CMP r4,r0 ;382 +000196 d002 BEQ |L5.414| +000198 4805 LDR r0,|L5.432| +00019a 4284 CMP r4,r0 ;382 +00019c d103 BNE |L5.422| + |L5.414| +00019e 2101 MOVS r1,#1 ;384 +0001a0 4620 MOV r0,r4 ;384 +0001a2 f7fffffe BL TIM_CtrlPWMOutputs + |L5.422| +0001a6 bf00 NOP +0001a8 e742 B |L5.48| +;;;387 + ENDP + +0001aa 0000 DCW 0x0000 + |L5.428| + DCD 0x40012c00 + |L5.432| + DCD 0x40013400 + |L5.436| + DCD 0x40014c00 + |L5.440| + DCD 0x40015000 + |L5.444| + DCD 0x40015400 + |L5.448| + DCD SystemCoreClock + + AREA ||i.bsp_SetTIMOutPWM_N||, CODE, READONLY, ALIGN=2 + + bsp_SetTIMOutPWM_N PROC +;;;397 */ +;;;398 void bsp_SetTIMOutPWM_N(GPIO_TypeDef *GPIOx, uint16_t GPIO_Pin, TIM_TypeDef *TIMx, uint8_t _ucChannel, +000000 e92d4fff PUSH {r0-r11,lr} +;;;399 uint32_t _ulFreq, uint32_t _ulDutyCycle) +;;;400 { +000004 b087 SUB sp,sp,#0x1c +000006 4683 MOV r11,r0 +000008 4614 MOV r4,r2 +00000a 461d MOV r5,r3 +00000c e9dd6a14 LDRD r6,r10,[sp,#0x50] +;;;401 TIM_TimeBaseInitTypeDef TIM_TimeBaseStructure; +;;;402 TIM_OCInitTypeDef TIM_OCInitStructure; +;;;403 uint16_t usPeriod; +;;;404 uint16_t usPrescaler; +;;;405 uint32_t uiTIMxCLK; +;;;406 +;;;407 if (_ulDutyCycle == 0) +000010 f1ba0f00 CMP r10,#0 +000014 d10f BNE |L6.54| +;;;408 { +;;;409 TIM_Cmd(TIMx, DISABLE); /* 关闭PWM输出 */ +000016 2100 MOVS r1,#0 +000018 4620 MOV r0,r4 +00001a f7fffffe BL TIM_Cmd +;;;410 bsp_ConfigGpioOut(GPIOx, GPIO_Pin); /* 配置GPIO为推挽输出 */ +00001e 4658 MOV r0,r11 +000020 9908 LDR r1,[sp,#0x20] +000022 f7fffffe BL bsp_ConfigGpioOut +;;;411 GPIO_WriteBit(GPIOx, GPIO_Pin, Bit_RESET); /* PWM = 0 */ +000026 2200 MOVS r2,#0 +000028 4658 MOV r0,r11 +00002a 9908 LDR r1,[sp,#0x20] +00002c f7fffffe BL GPIO_WriteBit + |L6.48| +;;;412 return; +;;;413 } +;;;414 else if (_ulDutyCycle == 10000) +;;;415 { +;;;416 TIM_Cmd(TIMx, DISABLE); /* 关闭PWM输出 */ +;;;417 +;;;418 bsp_ConfigGpioOut(GPIOx, GPIO_Pin); /* 配置GPIO为推挽输出 */ +;;;419 GPIO_WriteBit(GPIOx, GPIO_Pin, Bit_SET); /* PWM = 1 */ +;;;420 return; +;;;421 } +;;;422 +;;;423 bsp_ConfigTimGpio(GPIOx, GPIO_Pin, TIMx, _ucChannel); /* 使能GPIO和TIM时钟，并连接TIM通道到GPIO */ +;;;424 +;;;425 /*----------------------------------------------------------------------- +;;;426 system_stm32f4xx.c 文件中 void SetSysClock(void) 函数对时钟的配置如下： +;;;427 +;;;428 HCLK = SYSCLK / 1 (AHB1Periph) +;;;429 PCLK2 = HCLK / 2 (APB2Periph) +;;;430 PCLK1 = HCLK / 4 (APB1Periph) +;;;431 +;;;432 因为APB1 prescaler != 1, 所以 APB1上的TIMxCLK = PCLK1 x 2 = SystemCoreClock / 2; +;;;433 因为APB2 prescaler != 1, 所以 APB2上的TIMxCLK = PCLK2 x 2 = SystemCoreClock; +;;;434 +;;;435 APB1 定时器有 TIM2, TIM3 ,TIM4, TIM5, TIM6, TIM6, TIM12, TIM13,TIM14 +;;;436 APB2 定时器有 TIM1, TIM8 ,TIM9, TIM10, TIM11 +;;;437 +;;;438 ----------------------------------------------------------------------- */ +;;;439 if ((TIMx == TIM1) || (TIMx == TIM8) || (TIMx == TIM9) || (TIMx == TIM10) || (TIMx == TIM11)) +;;;440 { +;;;441 /* APB2 定时器 */ +;;;442 uiTIMxCLK = SystemCoreClock; +;;;443 } +;;;444 else /* APB1 定时器 */ +;;;445 { +;;;446 uiTIMxCLK = SystemCoreClock; // SystemCoreClock / 2; +;;;447 } +;;;448 +;;;449 if (_ulFreq < 100) +;;;450 { +;;;451 usPrescaler = 10000 - 1; /* 分频比 = 10000 */ +;;;452 usPeriod = (uiTIMxCLK / 10000) / _ulFreq - 1; /* 自动重装的值 */ +;;;453 } +;;;454 else if (_ulFreq < 3000) +;;;455 { +;;;456 usPrescaler = 100 - 1; /* 分频比 = 100 */ +;;;457 usPeriod = (uiTIMxCLK / 100) / _ulFreq - 1; /* 自动重装的值 */ +;;;458 } +;;;459 else /* 大于4K的频率，无需分频 */ +;;;460 { +;;;461 usPrescaler = 0; /* 分频比 = 1 */ +;;;462 usPeriod = uiTIMxCLK / _ulFreq - 1; /* 自动重装的值 */ +;;;463 } +;;;464 +;;;465 /* Time base configuration */ +;;;466 TIM_TimeBaseStructure.TIM_Period = usPeriod; +;;;467 TIM_TimeBaseStructure.TIM_Prescaler = usPrescaler; +;;;468 TIM_TimeBaseStructure.TIM_ClockDivision = 0; +;;;469 TIM_TimeBaseStructure.TIM_CounterMode = TIM_CounterMode_Up; +;;;470 TIM_TimeBaseStructure.TIM_RepetitionCounter = 0; +;;;471 TIM_TimeBaseInit(TIMx, &TIM_TimeBaseStructure); +;;;472 +;;;473 /* PWM1 Mode configuration: Channel1 */ +;;;474 TIM_OCStructInit(&TIM_OCInitStructure); /* 初始化结构体成员 */ +;;;475 +;;;476 TIM_OCInitStructure.TIM_OCMode = TIM_OCMode_PWM1; +;;;477 TIM_OCInitStructure.TIM_OutputState = TIM_OutputState_Disable; /* 和 bsp_SetTIMOutPWM_N() 不同 */ +;;;478 TIM_OCInitStructure.TIM_Pulse = (_ulDutyCycle * usPeriod) / 10000; +;;;479 TIM_OCInitStructure.TIM_OCPolarity = TIM_OCPolarity_High; +;;;480 +;;;481 TIM_OCInitStructure.TIM_OutputNState = TIM_OutputNState_Enable; /* only for TIM1 and TIM8. */ +;;;482 TIM_OCInitStructure.TIM_OCNPolarity = TIM_OCNPolarity_High; /* only for TIM1 and TIM8. */ +;;;483 TIM_OCInitStructure.TIM_OCIdleState = TIM_OCIdleState_Reset; /* only for TIM1 and TIM8. */ +;;;484 TIM_OCInitStructure.TIM_OCNIdleState = TIM_OCNIdleState_Reset; /* only for TIM1 and TIM8. */ +;;;485 +;;;486 if (_ucChannel == 1) +;;;487 { +;;;488 TIM_OC1Init(TIMx, &TIM_OCInitStructure); +;;;489 TIM_OC1PreloadConfig(TIMx, TIM_OCPreload_Enable); +;;;490 } +;;;491 else if (_ucChannel == 2) +;;;492 { +;;;493 TIM_OC2Init(TIMx, &TIM_OCInitStructure); +;;;494 TIM_OC2PreloadConfig(TIMx, TIM_OCPreload_Enable); +;;;495 } +;;;496 else if (_ucChannel == 3) +;;;497 { +;;;498 TIM_OC3Init(TIMx, &TIM_OCInitStructure); +;;;499 TIM_OC3PreloadConfig(TIMx, TIM_OCPreload_Enable); +;;;500 } +;;;501 else if (_ucChannel == 4) +;;;502 { +;;;503 TIM_OC4Init(TIMx, &TIM_OCInitStructure); +;;;504 TIM_OC4PreloadConfig(TIMx, TIM_OCPreload_Enable); +;;;505 } +;;;506 +;;;507 TIM_ARRPreloadConfig(TIMx, ENABLE); +;;;508 +;;;509 /* TIMx enable counter */ +;;;510 TIM_Cmd(TIMx, ENABLE); +;;;511 +;;;512 /* 下面这句话对于TIM1和TIM8是必须的，对于TIM2-TIM6则不必要 */ +;;;513 if ((TIMx == TIM1) || (TIMx == TIM8)) +;;;514 { +;;;515 TIM_CtrlPWMOutputs(TIMx, ENABLE); +;;;516 } +;;;517 } +000030 b00b ADD sp,sp,#0x2c +000032 e8bd8ff0 POP {r4-r11,pc} + |L6.54| +000036 f2427010 MOV r0,#0x2710 ;414 +00003a 4582 CMP r10,r0 ;414 +00003c d10d BNE |L6.90| +00003e 2100 MOVS r1,#0 ;416 +000040 4620 MOV r0,r4 ;416 +000042 f7fffffe BL TIM_Cmd +000046 4658 MOV r0,r11 ;418 +000048 9908 LDR r1,[sp,#0x20] ;418 +00004a f7fffffe BL bsp_ConfigGpioOut +00004e 2201 MOVS r2,#1 ;419 +000050 4658 MOV r0,r11 ;419 +000052 9908 LDR r1,[sp,#0x20] ;419 +000054 f7fffffe BL GPIO_WriteBit +000058 e7ea B |L6.48| + |L6.90| +00005a 462b MOV r3,r5 ;423 +00005c 4622 MOV r2,r4 ;423 +00005e 4658 MOV r0,r11 ;423 +000060 9908 LDR r1,[sp,#0x20] ;423 +000062 f7fffffe BL bsp_ConfigTimGpio +000066 4852 LDR r0,|L6.432| +000068 4284 CMP r4,r0 ;439 +00006a d00b BEQ |L6.132| +00006c 4851 LDR r0,|L6.436| +00006e 4284 CMP r4,r0 ;439 +000070 d008 BEQ |L6.132| +000072 4851 LDR r0,|L6.440| +000074 4284 CMP r4,r0 ;439 +000076 d005 BEQ |L6.132| +000078 4850 LDR r0,|L6.444| +00007a 4284 CMP r4,r0 ;439 +00007c d002 BEQ |L6.132| +00007e 4850 LDR r0,|L6.448| +000080 4284 CMP r4,r0 ;439 +000082 d103 BNE |L6.140| + |L6.132| +000084 484f LDR r0,|L6.452| +000086 f8d08000 LDR r8,[r0,#0] ;442 ; SystemCoreClock +00008a e002 B |L6.146| + |L6.140| +00008c 484d LDR r0,|L6.452| +00008e f8d08000 LDR r8,[r0,#0] ;446 ; SystemCoreClock + |L6.146| +000092 2e64 CMP r6,#0x64 ;449 +000094 d20a BCS |L6.172| +000096 f242790f MOV r9,#0x270f ;451 +00009a f2427010 MOV r0,#0x2710 ;452 +00009e fbb8f0f0 UDIV r0,r8,r0 ;452 +0000a2 fbb0f0f6 UDIV r0,r0,r6 ;452 +0000a6 1e40 SUBS r0,r0,#1 ;452 +0000a8 b287 UXTH r7,r0 ;452 +0000aa e013 B |L6.212| + |L6.172| +0000ac f64030b8 MOV r0,#0xbb8 ;454 +0000b0 4286 CMP r6,r0 ;454 +0000b2 d209 BCS |L6.200| +0000b4 f04f0963 MOV r9,#0x63 ;456 +0000b8 2064 MOVS r0,#0x64 ;457 +0000ba fbb8f0f0 UDIV r0,r8,r0 ;457 +0000be fbb0f0f6 UDIV r0,r0,r6 ;457 +0000c2 1e40 SUBS r0,r0,#1 ;457 +0000c4 b287 UXTH r7,r0 ;457 +0000c6 e005 B |L6.212| + |L6.200| +0000c8 f04f0900 MOV r9,#0 ;461 +0000cc fbb8f0f6 UDIV r0,r8,r6 ;462 +0000d0 1e40 SUBS r0,r0,#1 ;462 +0000d2 b287 UXTH r7,r0 ;462 + |L6.212| +0000d4 f8ad7014 STRH r7,[sp,#0x14] ;466 +0000d8 f8ad9010 STRH r9,[sp,#0x10] ;467 +0000dc 2000 MOVS r0,#0 ;468 +0000de f8ad0016 STRH r0,[sp,#0x16] ;468 +0000e2 f8ad0012 STRH r0,[sp,#0x12] ;469 +0000e6 f88d0018 STRB r0,[sp,#0x18] ;470 +0000ea a904 ADD r1,sp,#0x10 ;471 +0000ec 4620 MOV r0,r4 ;471 +0000ee f7fffffe BL TIM_TimeBaseInit +0000f2 4668 MOV r0,sp ;474 +0000f4 f7fffffe BL TIM_OCStructInit +0000f8 2060 MOVS r0,#0x60 ;476 +0000fa f8ad0000 STRH r0,[sp,#0] ;476 +0000fe 2000 MOVS r0,#0 ;477 +000100 f8ad0002 STRH r0,[sp,#2] ;477 +000104 fb0af007 MUL r0,r10,r7 ;478 +000108 f2427110 MOV r1,#0x2710 ;478 +00010c fbb0f0f1 UDIV r0,r0,r1 ;478 +000110 b280 UXTH r0,r0 ;478 +000112 f8ad0006 STRH r0,[sp,#6] ;478 +000116 2000 MOVS r0,#0 ;479 +000118 f8ad0008 STRH r0,[sp,#8] ;479 +00011c 2004 MOVS r0,#4 ;481 +00011e f8ad0004 STRH r0,[sp,#4] ;481 +000122 2000 MOVS r0,#0 ;482 +000124 f8ad000a STRH r0,[sp,#0xa] ;482 +000128 f8ad000c STRH r0,[sp,#0xc] ;483 +00012c f8ad000e STRH r0,[sp,#0xe] ;484 +000130 2d01 CMP r5,#1 ;486 +000132 d108 BNE |L6.326| +000134 4669 MOV r1,sp ;488 +000136 4620 MOV r0,r4 ;488 +000138 f7fffffe BL TIM_OC1Init +00013c 2108 MOVS r1,#8 ;489 +00013e 4620 MOV r0,r4 ;489 +000140 f7fffffe BL TIM_OC1PreloadConfig +000144 e01f B |L6.390| + |L6.326| +000146 2d02 CMP r5,#2 ;491 +000148 d108 BNE |L6.348| +00014a 4669 MOV r1,sp ;493 +00014c 4620 MOV r0,r4 ;493 +00014e f7fffffe BL TIM_OC2Init +000152 2108 MOVS r1,#8 ;494 +000154 4620 MOV r0,r4 ;494 +000156 f7fffffe BL TIM_OC2PreloadConfig +00015a e014 B |L6.390| + |L6.348| +00015c 2d03 CMP r5,#3 ;496 +00015e d108 BNE |L6.370| +000160 4669 MOV r1,sp ;498 +000162 4620 MOV r0,r4 ;498 +000164 f7fffffe BL TIM_OC3Init +000168 2108 MOVS r1,#8 ;499 +00016a 4620 MOV r0,r4 ;499 +00016c f7fffffe BL TIM_OC3PreloadConfig +000170 e009 B |L6.390| + |L6.370| +000172 2d04 CMP r5,#4 ;501 +000174 d107 BNE |L6.390| +000176 4669 MOV r1,sp ;503 +000178 4620 MOV r0,r4 ;503 +00017a f7fffffe BL TIM_OC4Init +00017e 2108 MOVS r1,#8 ;504 +000180 4620 MOV r0,r4 ;504 +000182 f7fffffe BL TIM_OC4PreloadConfig + |L6.390| +000186 2101 MOVS r1,#1 ;507 +000188 4620 MOV r0,r4 ;507 +00018a f7fffffe BL TIM_ARRPreloadConfig +00018e 2101 MOVS r1,#1 ;510 +000190 4620 MOV r0,r4 ;510 +000192 f7fffffe BL TIM_Cmd +000196 4806 LDR r0,|L6.432| +000198 4284 CMP r4,r0 ;513 +00019a d002 BEQ |L6.418| +00019c 4805 LDR r0,|L6.436| +00019e 4284 CMP r4,r0 ;513 +0001a0 d103 BNE |L6.426| + |L6.418| +0001a2 2101 MOVS r1,#1 ;515 +0001a4 4620 MOV r0,r4 ;515 +0001a6 f7fffffe BL TIM_CtrlPWMOutputs + |L6.426| +0001aa bf00 NOP +0001ac e740 B |L6.48| +;;;518 + ENDP + +0001ae 0000 DCW 0x0000 + |L6.432| + DCD 0x40012c00 + |L6.436| + DCD 0x40013400 + |L6.440| + DCD 0x40014c00 + |L6.444| + DCD 0x40015000 + |L6.448| + DCD 0x40015400 + |L6.452| + DCD SystemCoreClock + + AREA ||i.bsp_SetTIMforInt||, CODE, READONLY, ALIGN=2 + + bsp_SetTIMforInt PROC +;;;529 */ +;;;530 void bsp_SetTIMforInt(TIM_TypeDef *TIMx, uint32_t _ulFreq, uint8_t _PreemptionPriority, uint8_t _SubPriority) +000000 e92d5fff PUSH {r0-r12,lr} +;;;531 { +000004 4604 MOV r4,r0 +000006 460d MOV r5,r1 +000008 4691 MOV r9,r2 +00000a 469a MOV r10,r3 +;;;532 TIM_TimeBaseInitTypeDef TIM_TimeBaseStructure; +;;;533 uint16_t usPeriod; +;;;534 uint16_t usPrescaler; +;;;535 uint32_t uiTIMxCLK; +;;;536 +;;;537 /* 使能TIM时钟 */ +;;;538 if ((TIMx == TIM1) || (TIMx == TIM8)) +00000c 4874 LDR r0,|L7.480| +00000e 4284 CMP r4,r0 +000010 d002 BEQ |L7.24| +000012 4874 LDR r0,|L7.484| +000014 4284 CMP r4,r0 +000016 d107 BNE |L7.40| + |L7.24| +;;;539 { +;;;540 RCC_APB2PeriphClockCmd(bsp_GetRCCofTIM(TIMx), ENABLE); +000018 4620 MOV r0,r4 +00001a f7fffffe BL bsp_GetRCCofTIM +00001e 4683 MOV r11,r0 +000020 2101 MOVS r1,#1 +000022 f7fffffe BL RCC_APB2PeriphClockCmd +000026 e006 B |L7.54| + |L7.40| +;;;541 } +;;;542 else +;;;543 { +;;;544 RCC_APB1PeriphClockCmd(bsp_GetRCCofTIM(TIMx), ENABLE); +000028 4620 MOV r0,r4 +00002a f7fffffe BL bsp_GetRCCofTIM +00002e 4683 MOV r11,r0 +000030 2101 MOVS r1,#1 +000032 f7fffffe BL RCC_APB1PeriphClockCmd + |L7.54| +;;;545 } +;;;546 +;;;547 if (_ulFreq == 0) +000036 2d00 CMP r5,#0 +000038 d141 BNE |L7.190| +;;;548 { +;;;549 TIM_Cmd(TIMx, DISABLE); /* 关闭定时输出 */ +00003a 2100 MOVS r1,#0 +00003c 4620 MOV r0,r4 +00003e f7fffffe BL TIM_Cmd +;;;550 +;;;551 /* 关闭TIM定时更新中断 (Update) */ +;;;552 { +;;;553 NVIC_InitTypeDef NVIC_InitStructure; /* 中断结构体在 misc.h 中定义 */ +;;;554 uint8_t irq = 0; /* 中断号, 定义在 stm32f4xx.h */ +000042 46ab MOV r11,r5 +;;;555 +;;;556 if (TIMx == TIM1) +000044 4866 LDR r0,|L7.480| +000046 4284 CMP r4,r0 +000048 d102 BNE |L7.80| +;;;557 irq = TIM1_UP_IRQn; +00004a f04f0b19 MOV r11,#0x19 +00004e e028 B |L7.162| + |L7.80| +;;;558 else if (TIMx == TIM2) +000050 f1b44f80 CMP r4,#0x40000000 +000054 d102 BNE |L7.92| +;;;559 irq = TIM2_IRQn; +000056 f04f0b1c MOV r11,#0x1c +00005a e022 B |L7.162| + |L7.92| +;;;560 else if (TIMx == TIM3) +00005c 4862 LDR r0,|L7.488| +00005e 4284 CMP r4,r0 +000060 d102 BNE |L7.104| +;;;561 irq = TIM3_IRQn; +000062 f04f0b1d MOV r11,#0x1d +000066 e01c B |L7.162| + |L7.104| +;;;562 else if (TIMx == TIM4) +000068 4860 LDR r0,|L7.492| +00006a 4284 CMP r4,r0 +00006c d102 BNE |L7.116| +;;;563 irq = TIM4_IRQn; +00006e f04f0b1e MOV r11,#0x1e +000072 e016 B |L7.162| + |L7.116| +;;;564 else if (TIMx == TIM5) +000074 485e LDR r0,|L7.496| +000076 4284 CMP r4,r0 +000078 d102 BNE |L7.128| +;;;565 irq = TIM5_IRQn; +00007a f04f0b32 MOV r11,#0x32 +00007e e010 B |L7.162| + |L7.128| +;;;566 else if (TIMx == TIM6) +000080 485c LDR r0,|L7.500| +000082 4284 CMP r4,r0 +000084 d102 BNE |L7.140| +;;;567 irq = TIM6_IRQn; +000086 f04f0b36 MOV r11,#0x36 +00008a e00a B |L7.162| + |L7.140| +;;;568 else if (TIMx == TIM7) +00008c 485a LDR r0,|L7.504| +00008e 4284 CMP r4,r0 +000090 d102 BNE |L7.152| +;;;569 irq = TIM7_IRQn; +000092 f04f0b37 MOV r11,#0x37 +000096 e004 B |L7.162| + |L7.152| +;;;570 else if (TIMx == TIM8) +000098 4852 LDR r0,|L7.484| +00009a 4284 CMP r4,r0 +00009c d101 BNE |L7.162| +;;;571 irq = TIM8_UP_IRQn; +00009e f04f0b2c MOV r11,#0x2c + |L7.162| +;;;572 +;;;573 NVIC_InitStructure.NVIC_IRQChannel = irq; +0000a2 f88db000 STRB r11,[sp,#0] +;;;574 NVIC_InitStructure.NVIC_IRQChannelPreemptionPriority = _PreemptionPriority; +0000a6 f88d9001 STRB r9,[sp,#1] +;;;575 NVIC_InitStructure.NVIC_IRQChannelSubPriority = _SubPriority; +0000aa f88da002 STRB r10,[sp,#2] +;;;576 NVIC_InitStructure.NVIC_IRQChannelCmd = DISABLE; +0000ae 2000 MOVS r0,#0 +0000b0 f88d0003 STRB r0,[sp,#3] +;;;577 NVIC_Init(&NVIC_InitStructure); +0000b4 4668 MOV r0,sp +0000b6 f7fffffe BL NVIC_Init + |L7.186| +;;;578 } +;;;579 return; +;;;580 } +;;;581 +;;;582 /*----------------------------------------------------------------------- +;;;583 system_stm32f4xx.c 文件中 static void SetSysClockToHSE(void) 函数对时钟的配置如下： +;;;584 +;;;585 //HCLK = SYSCLK +;;;586 RCC->CFGR |= (uint32_t)RCC_CFGR_HPRE_DIV1; +;;;587 +;;;588 //PCLK2 = HCLK +;;;589 RCC->CFGR |= (uint32_t)RCC_CFGR_PPRE2_DIV1; +;;;590 +;;;591 //PCLK1 = HCLK +;;;592 RCC->CFGR |= (uint32_t)RCC_CFGR_PPRE1_DIV1; +;;;593 +;;;594 APB1 定时器有 TIM2, TIM3 ,TIM4, TIM5, TIM6, TIM7, TIM12, TIM13,TIM14 +;;;595 APB2 定时器有 TIM1, TIM8 ,TIM9, TIM10, TIM11 +;;;596 +;;;597 ----------------------------------------------------------------------- */ +;;;598 if ((TIMx == TIM1) || (TIMx == TIM8) || (TIMx == TIM9) || (TIMx == TIM10) || (TIMx == TIM11)) +;;;599 { +;;;600 /* APB2 定时器 */ +;;;601 uiTIMxCLK = SystemCoreClock; +;;;602 } +;;;603 else /* APB1 定时器 . */ +;;;604 { +;;;605 uiTIMxCLK = SystemCoreClock; // SystemCoreClock / 2; +;;;606 } +;;;607 +;;;608 if (_ulFreq < 100) +;;;609 { +;;;610 usPrescaler = 10000 - 1; /* 分频比 = 1000 */ +;;;611 usPeriod = (uiTIMxCLK / 10000) / _ulFreq - 1; /* 自动重装的值 */ +;;;612 } +;;;613 else if (_ulFreq < 3000) +;;;614 { +;;;615 usPrescaler = 100 - 1; /* 分频比 = 100 */ +;;;616 usPeriod = (uiTIMxCLK / 100) / _ulFreq - 1; /* 自动重装的值 */ +;;;617 } +;;;618 else /* 大于4K的频率，无需分频 */ +;;;619 { +;;;620 usPrescaler = 0; /* 分频比 = 1 */ +;;;621 usPeriod = uiTIMxCLK / _ulFreq - 1; /* 自动重装的值 */ +;;;622 } +;;;623 +;;;624 /* Time base configuration */ +;;;625 TIM_TimeBaseStructure.TIM_Period = usPeriod; +;;;626 TIM_TimeBaseStructure.TIM_Prescaler = usPrescaler; +;;;627 TIM_TimeBaseStructure.TIM_ClockDivision = 0; +;;;628 TIM_TimeBaseStructure.TIM_CounterMode = TIM_CounterMode_Up; +;;;629 TIM_TimeBaseStructure.TIM_RepetitionCounter = 0; +;;;630 +;;;631 TIM_TimeBaseInit(TIMx, &TIM_TimeBaseStructure); +;;;632 +;;;633 TIM_ARRPreloadConfig(TIMx, ENABLE); +;;;634 +;;;635 /* TIM Interrupts enable */ +;;;636 TIM_ITConfig(TIMx, TIM_IT_Update, ENABLE); +;;;637 +;;;638 /* TIMx enable counter */ +;;;639 TIM_Cmd(TIMx, ENABLE); +;;;640 +;;;641 /* 配置TIM定时更新中断 (Update) */ +;;;642 { +;;;643 NVIC_InitTypeDef NVIC_InitStructure; /* 中断结构体在 misc.h 中定义 */ +;;;644 uint8_t irq = 0; /* 中断号, 定义在 stm32f4xx.h */ +;;;645 +;;;646 if (TIMx == TIM1) +;;;647 irq = TIM1_UP_IRQn; +;;;648 else if (TIMx == TIM2) +;;;649 irq = TIM2_IRQn; +;;;650 else if (TIMx == TIM3) +;;;651 irq = TIM3_IRQn; +;;;652 else if (TIMx == TIM4) +;;;653 irq = TIM4_IRQn; +;;;654 else if (TIMx == TIM5) +;;;655 irq = TIM5_IRQn; +;;;656 else if (TIMx == TIM6) +;;;657 irq = TIM6_IRQn; +;;;658 else if (TIMx == TIM7) +;;;659 irq = TIM7_IRQn; +;;;660 else if (TIMx == TIM8) +;;;661 irq = TIM8_UP_IRQn; +;;;662 +;;;663 NVIC_InitStructure.NVIC_IRQChannel = irq; +;;;664 NVIC_InitStructure.NVIC_IRQChannelPreemptionPriority = _PreemptionPriority; +;;;665 NVIC_InitStructure.NVIC_IRQChannelSubPriority = _SubPriority; +;;;666 NVIC_InitStructure.NVIC_IRQChannelCmd = ENABLE; +;;;667 NVIC_Init(&NVIC_InitStructure); +;;;668 } +;;;669 } +0000ba e8bd9fff POP {r0-r12,pc} + |L7.190| +0000be 4848 LDR r0,|L7.480| +0000c0 4284 CMP r4,r0 ;598 +0000c2 d00b BEQ |L7.220| +0000c4 4847 LDR r0,|L7.484| +0000c6 4284 CMP r4,r0 ;598 +0000c8 d008 BEQ |L7.220| +0000ca 484c LDR r0,|L7.508| +0000cc 4284 CMP r4,r0 ;598 +0000ce d005 BEQ |L7.220| +0000d0 484b LDR r0,|L7.512| +0000d2 4284 CMP r4,r0 ;598 +0000d4 d002 BEQ |L7.220| +0000d6 484b LDR r0,|L7.516| +0000d8 4284 CMP r4,r0 ;598 +0000da d102 BNE |L7.226| + |L7.220| +0000dc 484a LDR r0,|L7.520| +0000de 6806 LDR r6,[r0,#0] ;601 ; SystemCoreClock +0000e0 e001 B |L7.230| + |L7.226| +0000e2 4849 LDR r0,|L7.520| +0000e4 6806 LDR r6,[r0,#0] ;605 ; SystemCoreClock + |L7.230| +0000e6 2d64 CMP r5,#0x64 ;608 +0000e8 d20a BCS |L7.256| +0000ea f242780f MOV r8,#0x270f ;610 +0000ee f2427010 MOV r0,#0x2710 ;611 +0000f2 fbb6f0f0 UDIV r0,r6,r0 ;611 +0000f6 fbb0f0f5 UDIV r0,r0,r5 ;611 +0000fa 1e40 SUBS r0,r0,#1 ;611 +0000fc b287 UXTH r7,r0 ;611 +0000fe e013 B |L7.296| + |L7.256| +000100 f64030b8 MOV r0,#0xbb8 ;613 +000104 4285 CMP r5,r0 ;613 +000106 d209 BCS |L7.284| +000108 f04f0863 MOV r8,#0x63 ;615 +00010c 2064 MOVS r0,#0x64 ;616 +00010e fbb6f0f0 UDIV r0,r6,r0 ;616 +000112 fbb0f0f5 UDIV r0,r0,r5 ;616 +000116 1e40 SUBS r0,r0,#1 ;616 +000118 b287 UXTH r7,r0 ;616 +00011a e005 B |L7.296| + |L7.284| +00011c f04f0800 MOV r8,#0 ;620 +000120 fbb6f0f5 UDIV r0,r6,r5 ;621 +000124 1e40 SUBS r0,r0,#1 ;621 +000126 b287 UXTH r7,r0 ;621 + |L7.296| +000128 f8ad7008 STRH r7,[sp,#8] ;625 +00012c f8ad8004 STRH r8,[sp,#4] ;626 +000130 2000 MOVS r0,#0 ;627 +000132 f8ad000a STRH r0,[sp,#0xa] ;627 +000136 f8ad0006 STRH r0,[sp,#6] ;628 +00013a f88d000c STRB r0,[sp,#0xc] ;629 +00013e a901 ADD r1,sp,#4 ;631 +000140 4620 MOV r0,r4 ;631 +000142 f7fffffe BL TIM_TimeBaseInit +000146 2101 MOVS r1,#1 ;633 +000148 4620 MOV r0,r4 ;633 +00014a f7fffffe BL TIM_ARRPreloadConfig +00014e 2201 MOVS r2,#1 ;636 +000150 4611 MOV r1,r2 ;636 +000152 4620 MOV r0,r4 ;636 +000154 f7fffffe BL TIM_ITConfig +000158 2101 MOVS r1,#1 ;639 +00015a 4620 MOV r0,r4 ;639 +00015c f7fffffe BL TIM_Cmd +000160 f04f0b00 MOV r11,#0 ;644 +000164 481e LDR r0,|L7.480| +000166 4284 CMP r4,r0 ;646 +000168 d102 BNE |L7.368| +00016a f04f0b19 MOV r11,#0x19 ;647 +00016e e028 B |L7.450| + |L7.368| +000170 f1b44f80 CMP r4,#0x40000000 ;648 +000174 d102 BNE |L7.380| +000176 f04f0b1c MOV r11,#0x1c ;649 +00017a e022 B |L7.450| + |L7.380| +00017c 481a LDR r0,|L7.488| +00017e 4284 CMP r4,r0 ;650 +000180 d102 BNE |L7.392| +000182 f04f0b1d MOV r11,#0x1d ;651 +000186 e01c B |L7.450| + |L7.392| +000188 4818 LDR r0,|L7.492| +00018a 4284 CMP r4,r0 ;652 +00018c d102 BNE |L7.404| +00018e f04f0b1e MOV r11,#0x1e ;653 +000192 e016 B |L7.450| + |L7.404| +000194 4816 LDR r0,|L7.496| +000196 4284 CMP r4,r0 ;654 +000198 d102 BNE |L7.416| +00019a f04f0b32 MOV r11,#0x32 ;655 +00019e e010 B |L7.450| + |L7.416| +0001a0 4814 LDR r0,|L7.500| +0001a2 4284 CMP r4,r0 ;656 +0001a4 d102 BNE |L7.428| +0001a6 f04f0b36 MOV r11,#0x36 ;657 +0001aa e00a B |L7.450| + |L7.428| +0001ac 4812 LDR r0,|L7.504| +0001ae 4284 CMP r4,r0 ;658 +0001b0 d102 BNE |L7.440| +0001b2 f04f0b37 MOV r11,#0x37 ;659 +0001b6 e004 B |L7.450| + |L7.440| +0001b8 480a LDR r0,|L7.484| +0001ba 4284 CMP r4,r0 ;660 +0001bc d101 BNE |L7.450| +0001be f04f0b2c MOV r11,#0x2c ;661 + |L7.450| +0001c2 f88db000 STRB r11,[sp,#0] ;663 +0001c6 f88d9001 STRB r9,[sp,#1] ;664 +0001ca f88da002 STRB r10,[sp,#2] ;665 +0001ce 2001 MOVS r0,#1 ;666 +0001d0 f88d0003 STRB r0,[sp,#3] ;666 +0001d4 4668 MOV r0,sp ;667 +0001d6 f7fffffe BL NVIC_Init +0001da bf00 NOP +0001dc e76d B |L7.186| +;;;670 + ENDP + +0001de 0000 DCW 0x0000 + |L7.480| + DCD 0x40012c00 + |L7.484| + DCD 0x40013400 + |L7.488| + DCD 0x40000400 + |L7.492| + DCD 0x40000800 + |L7.496| + DCD 0x40000c00 + |L7.500| + DCD 0x40001000 + |L7.504| + DCD 0x40001400 + |L7.508| + DCD 0x40014c00 + |L7.512| + DCD 0x40015000 + |L7.516| + DCD 0x40015400 + |L7.520| + DCD SystemCoreClock + +;*** Start embedded assembler *** + +#line 1 "..\\..\\User\\bsp\\src\\bsp_tim_pwm.c" + AREA ||.rev16_text||, CODE + THUMB + EXPORT |__asm___13_bsp_tim_pwm_c_d7165983____REV16| +#line 114 "..\\..\\Libraries\\CMSIS\\Include\\core_cmInstr.h" +|__asm___13_bsp_tim_pwm_c_d7165983____REV16| PROC +#line 115 + + rev16 r0, r0 + bx lr + ENDP + AREA ||.revsh_text||, CODE + THUMB + EXPORT |__asm___13_bsp_tim_pwm_c_d7165983____REVSH| +#line 128 +|__asm___13_bsp_tim_pwm_c_d7165983____REVSH| PROC +#line 129 + + revsh r0, r0 + bx lr + ENDP + +;*** End embedded assembler *** diff --git a/Project/MDK-ARM/Flash/List/bsp_timer.txt b/Project/MDK-ARM/Flash/List/bsp_timer.txt new file mode 100644 index 0000000..e7f417c --- /dev/null +++ b/Project/MDK-ARM/Flash/List/bsp_timer.txt @@ -0,0 +1,1323 @@ +; generated by Component: ARM Compiler 5.06 update 7 (build 960) Tool: ArmCC [4d365d] +; commandline ArmCC [--list --split_sections --debug -c --asm --interleave -o.\flash\obj\bsp_timer.o --asm_dir=.\Flash\List\ --list_dir=.\Flash\List\ --depend=.\flash\obj\bsp_timer.d --cpu=Cortex-M3 --apcs=interwork -O0 --diag_suppress=9931,870 -I..\..\Libraries\CMSIS\Device\ST\STM32F10x\Include -I..\..\Libraries\STM32F10x_StdPeriph_Driver\inc -I..\..\Libraries\STM32_USB-FS-Device_Driver\inc -I..\..\Libraries\CMSIS\Include -I..\..\User\bsp -I..\..\User\bsp\inc -I..\..\User\app\inc -I..\..\User -IC:\Users\w1619\AppData\Local\Arm\Packs\Keil\STM32F1xx_DFP\2.4.1\Device\Include -D__MICROLIB -D__UVISION_VERSION=538 -DSTM32F10X_HD -DUSE_STDPERIPH_DRIVER -DSTM32F10X_HD --omf_browse=.\flash\obj\bsp_timer.crf ..\..\User\bsp\src\bsp_timer.c] + THUMB + + AREA ||i.SysTick_Handler||, CODE, READONLY, ALIGN=1 + + SysTick_Handler PROC +;;;463 */ +;;;464 void SysTick_Handler(void) +000000 b510 PUSH {r4,lr} +;;;465 { +;;;466 SysTick_ISR(); +000002 f7fffffe BL SysTick_ISR +;;;467 } +000006 bd10 POP {r4,pc} +;;;468 + ENDP + + + AREA ||i.SysTick_ISR||, CODE, READONLY, ALIGN=2 + + SysTick_ISR PROC +;;;132 extern void bsp_RunPer10ms(void); +;;;133 void SysTick_ISR(void) +000000 b510 PUSH {r4,lr} +;;;134 { +;;;135 static uint8_t s_count = 0; +;;;136 uint8_t i; +;;;137 +;;;138 /* 每隔1ms进来1次 （仅用于 bsp_DelayMS） */ +;;;139 if (s_uiDelayCount > 0) +000002 4822 LDR r0,|L2.140| +000004 6800 LDR r0,[r0,#0] ; s_uiDelayCount +000006 b140 CBZ r0,|L2.26| +;;;140 { +;;;141 if (--s_uiDelayCount == 0) +000008 4820 LDR r0,|L2.140| +00000a 6800 LDR r0,[r0,#0] ; s_uiDelayCount +00000c 1e40 SUBS r0,r0,#1 +00000e 491f LDR r1,|L2.140| +000010 6008 STR r0,[r1,#0] ; s_uiDelayCount +000012 b910 CBNZ r0,|L2.26| +;;;142 { +;;;143 s_ucTimeOutFlag = 1; +000014 2001 MOVS r0,#1 +000016 491e LDR r1,|L2.144| +000018 7008 STRB r0,[r1,#0] + |L2.26| +;;;144 } +;;;145 } +;;;146 +;;;147 /* 每隔1ms，对软件定时器的计数器进行减一操作 */ +;;;148 for (i = 0; i < TMR_COUNT; i++) +00001a 2400 MOVS r4,#0 +00001c e008 B |L2.48| + |L2.30| +;;;149 { +;;;150 bsp_SoftTimerDec(&s_tTmr[i]); +00001e eb040144 ADD r1,r4,r4,LSL #1 +000022 4a1c LDR r2,|L2.148| +000024 eb020081 ADD r0,r2,r1,LSL #2 +000028 f7fffffe BL bsp_SoftTimerDec +00002c 1c60 ADDS r0,r4,#1 ;148 +00002e b2c4 UXTB r4,r0 ;148 + |L2.48| +000030 2c04 CMP r4,#4 ;148 +000032 dbf4 BLT |L2.30| +;;;151 } +;;;152 +;;;153 /* 全局运行时间每1ms增1 */ +;;;154 g_iRunTime++; +000034 4818 LDR r0,|L2.152| +000036 6800 LDR r0,[r0,#0] ; g_iRunTime +000038 1c40 ADDS r0,r0,#1 +00003a 4917 LDR r1,|L2.152| +00003c 6008 STR r0,[r1,#0] ; g_iRunTime +;;;155 init_100ms++; +00003e 4817 LDR r0,|L2.156| +000040 8800 LDRH r0,[r0,#0] ; init_100ms +000042 1c40 ADDS r0,r0,#1 +000044 4915 LDR r1,|L2.156| +000046 8008 STRH r0,[r1,#0] +;;;156 if (init_100ms > 100) // 100m's +000048 4608 MOV r0,r1 +00004a 8800 LDRH r0,[r0,#0] ; init_100ms +00004c 2864 CMP r0,#0x64 +00004e dd04 BLE |L2.90| +;;;157 { +;;;158 init_100ms = 0; +000050 2000 MOVS r0,#0 +000052 8008 STRH r0,[r1,#0] +;;;159 Flag_100ms = 1; +000054 2001 MOVS r0,#1 +000056 4912 LDR r1,|L2.160| +000058 7008 STRB r0,[r1,#0] + |L2.90| +;;;160 } +;;;161 +;;;162 if (g_iRunTime == 0x7FFFFFFF) /* 这个变量是 int32_t 类型，最大数为 0x7FFFFFFF */ +00005a 480f LDR r0,|L2.152| +00005c 6800 LDR r0,[r0,#0] ; g_iRunTime +00005e f06f4100 MVN r1,#0x80000000 +000062 4288 CMP r0,r1 +000064 d102 BNE |L2.108| +;;;163 { +;;;164 g_iRunTime = 0; +000066 2000 MOVS r0,#0 +000068 490b LDR r1,|L2.152| +00006a 6008 STR r0,[r1,#0] ; g_iRunTime + |L2.108| +;;;165 } +;;;166 +;;;167 bsp_RunPer1ms(); /* 每隔1ms调用一次此函数，此函数在 bsp.c */ +00006c f7fffffe BL bsp_RunPer1ms +;;;168 +;;;169 if (++s_count >= 10) +000070 480c LDR r0,|L2.164| +000072 7800 LDRB r0,[r0,#0] ; s_count +000074 1c40 ADDS r0,r0,#1 +000076 b2c0 UXTB r0,r0 +000078 490a LDR r1,|L2.164| +00007a 7008 STRB r0,[r1,#0] +00007c 280a CMP r0,#0xa +00007e db03 BLT |L2.136| +;;;170 { +;;;171 s_count = 0; +000080 2000 MOVS r0,#0 +000082 7008 STRB r0,[r1,#0] +;;;172 +;;;173 bsp_RunPer10ms(); /* 每隔10ms调用一次此函数，此函数在 bsp.c */ +000084 f7fffffe BL bsp_RunPer10ms + |L2.136| +;;;174 } +;;;175 } +000088 bd10 POP {r4,pc} +;;;176 + ENDP + +00008a 0000 DCW 0x0000 + |L2.140| + DCD s_uiDelayCount + |L2.144| + DCD s_ucTimeOutFlag + |L2.148| + DCD s_tTmr + |L2.152| + DCD g_iRunTime + |L2.156| + DCD init_100ms + |L2.160| + DCD Flag_100ms + |L2.164| + DCD s_count + + AREA ||i.TIM2_IRQHandler||, CODE, READONLY, ALIGN=2 + + TIM2_IRQHandler PROC +;;;620 #ifdef USE_TIM2 +;;;621 void TIM2_IRQHandler(void) +000000 b510 PUSH {r4,lr} +;;;622 #endif +;;;623 +;;;624 #ifdef USE_TIM3 +;;;625 void TIM3_IRQHandler(void) +;;;626 #endif +;;;627 +;;;628 #ifdef USE_TIM4 +;;;629 void TIM4_IRQHandler(void) +;;;630 #endif +;;;631 +;;;632 #ifdef USE_TIM5 +;;;633 void TIM5_IRQHandler(void) +;;;634 #endif +;;;635 { +;;;636 if (TIM_GetITStatus(TIM_HARD, TIM_IT_CC1)) +000002 2102 MOVS r1,#2 +000004 0748 LSLS r0,r1,#29 +000006 f7fffffe BL TIM_GetITStatus +00000a b158 CBZ r0,|L3.36| +;;;637 { +;;;638 TIM_ClearITPendingBit(TIM_HARD, TIM_IT_CC1); +00000c 2102 MOVS r1,#2 +00000e 0748 LSLS r0,r1,#29 +000010 f7fffffe BL TIM_ClearITPendingBit +;;;639 TIM_ITConfig(TIM_HARD, TIM_IT_CC1, DISABLE); /* 禁能CC1中断 */ +000014 2200 MOVS r2,#0 +000016 2102 MOVS r1,#2 +000018 0748 LSLS r0,r1,#29 +00001a f7fffffe BL TIM_ITConfig +;;;640 +;;;641 /* 先关闭中断，再执行回调函数。因为回调函数可能需要重启定时器 */ +;;;642 s_TIM_CallBack1(); +00001e 481b LDR r0,|L3.140| +000020 6800 LDR r0,[r0,#0] ; s_TIM_CallBack1 +000022 4780 BLX r0 + |L3.36| +;;;643 } +;;;644 +;;;645 if (TIM_GetITStatus(TIM_HARD, TIM_IT_CC2)) +000024 2104 MOVS r1,#4 +000026 0708 LSLS r0,r1,#28 +000028 f7fffffe BL TIM_GetITStatus +00002c b158 CBZ r0,|L3.70| +;;;646 { +;;;647 TIM_ClearITPendingBit(TIM_HARD, TIM_IT_CC2); +00002e 2104 MOVS r1,#4 +000030 0708 LSLS r0,r1,#28 +000032 f7fffffe BL TIM_ClearITPendingBit +;;;648 TIM_ITConfig(TIM_HARD, TIM_IT_CC2, DISABLE); /* 禁能CC2中断 */ +000036 2200 MOVS r2,#0 +000038 2104 MOVS r1,#4 +00003a 0708 LSLS r0,r1,#28 +00003c f7fffffe BL TIM_ITConfig +;;;649 +;;;650 /* 先关闭中断，再执行回调函数。因为回调函数可能需要重启定时器 */ +;;;651 s_TIM_CallBack2(); +000040 4813 LDR r0,|L3.144| +000042 6800 LDR r0,[r0,#0] ; s_TIM_CallBack2 +000044 4780 BLX r0 + |L3.70| +;;;652 } +;;;653 +;;;654 if (TIM_GetITStatus(TIM_HARD, TIM_IT_CC3)) +000046 2108 MOVS r1,#8 +000048 06c8 LSLS r0,r1,#27 +00004a f7fffffe BL TIM_GetITStatus +00004e b158 CBZ r0,|L3.104| +;;;655 { +;;;656 TIM_ClearITPendingBit(TIM_HARD, TIM_IT_CC3); +000050 2108 MOVS r1,#8 +000052 06c8 LSLS r0,r1,#27 +000054 f7fffffe BL TIM_ClearITPendingBit +;;;657 TIM_ITConfig(TIM_HARD, TIM_IT_CC3, DISABLE); /* 禁能CC3中断 */ +000058 2200 MOVS r2,#0 +00005a 2108 MOVS r1,#8 +00005c 06c8 LSLS r0,r1,#27 +00005e f7fffffe BL TIM_ITConfig +;;;658 +;;;659 /* 先关闭中断，再执行回调函数。因为回调函数可能需要重启定时器 */ +;;;660 s_TIM_CallBack3(); +000062 480c LDR r0,|L3.148| +000064 6800 LDR r0,[r0,#0] ; s_TIM_CallBack3 +000066 4780 BLX r0 + |L3.104| +;;;661 } +;;;662 +;;;663 if (TIM_GetITStatus(TIM_HARD, TIM_IT_CC4)) +000068 2110 MOVS r1,#0x10 +00006a 0688 LSLS r0,r1,#26 +00006c f7fffffe BL TIM_GetITStatus +000070 b158 CBZ r0,|L3.138| +;;;664 { +;;;665 TIM_ClearITPendingBit(TIM_HARD, TIM_IT_CC4); +000072 2110 MOVS r1,#0x10 +000074 0688 LSLS r0,r1,#26 +000076 f7fffffe BL TIM_ClearITPendingBit +;;;666 TIM_ITConfig(TIM_HARD, TIM_IT_CC4, DISABLE); /* 禁能CC4中断 */ +00007a 2200 MOVS r2,#0 +00007c 2110 MOVS r1,#0x10 +00007e 0688 LSLS r0,r1,#26 +000080 f7fffffe BL TIM_ITConfig +;;;667 +;;;668 /* 先关闭中断，再执行回调函数。因为回调函数可能需要重启定时器 */ +;;;669 s_TIM_CallBack4(); +000084 4804 LDR r0,|L3.152| +000086 6800 LDR r0,[r0,#0] ; s_TIM_CallBack4 +000088 4780 BLX r0 + |L3.138| +;;;670 } +;;;671 } +00008a bd10 POP {r4,pc} +;;;672 + ENDP + + |L3.140| + DCD s_TIM_CallBack1 + |L3.144| + DCD s_TIM_CallBack2 + |L3.148| + DCD s_TIM_CallBack3 + |L3.152| + DCD s_TIM_CallBack4 + + AREA ||i.__set_PRIMASK||, CODE, READONLY, ALIGN=1 + + __set_PRIMASK PROC +;;;179 */ +;;;180 __STATIC_INLINE void __set_PRIMASK(uint32_t priMask) +000000 f3808810 MSR PRIMASK,r0 +;;;181 { +;;;182 register uint32_t __regPriMask __ASM("primask"); +;;;183 __regPriMask = (priMask); +;;;184 } +000004 4770 BX lr +;;;185 + ENDP + + + AREA ||i.bsp_CheckRunTime||, CODE, READONLY, ALIGN=2 + + bsp_CheckRunTime PROC +;;;432 */ +;;;433 int32_t bsp_CheckRunTime(int32_t _LastTime) +000000 b570 PUSH {r4-r6,lr} +;;;434 { +000002 4604 MOV r4,r0 +;;;435 int32_t now_time; +;;;436 int32_t time_diff; +;;;437 +;;;438 DISABLE_INT(); /* 关中断 */ +000004 2001 MOVS r0,#1 +000006 f7fffffe BL __set_PRIMASK +;;;439 +;;;440 now_time = g_iRunTime; /* 这个变量在Systick中断中被改写，因此需要关中断进行保护 */ +00000a 4807 LDR r0,|L5.40| +00000c 6806 LDR r6,[r0,#0] ; g_iRunTime +;;;441 +;;;442 ENABLE_INT(); /* 开中断 */ +00000e 2000 MOVS r0,#0 +000010 f7fffffe BL __set_PRIMASK +;;;443 +;;;444 if (now_time >= _LastTime) +000014 42a6 CMP r6,r4 +000016 db01 BLT |L5.28| +;;;445 { +;;;446 time_diff = now_time - _LastTime; +000018 1b35 SUBS r5,r6,r4 +00001a e003 B |L5.36| + |L5.28| +;;;447 } +;;;448 else +;;;449 { +;;;450 time_diff = 0x7FFFFFFF - _LastTime + now_time; +00001c f06f4000 MVN r0,#0x80000000 +000020 1b00 SUBS r0,r0,r4 +000022 1985 ADDS r5,r0,r6 + |L5.36| +;;;451 } +;;;452 +;;;453 return time_diff; +000024 4628 MOV r0,r5 +;;;454 } +000026 bd70 POP {r4-r6,pc} +;;;455 + ENDP + + |L5.40| + DCD g_iRunTime + + AREA ||i.bsp_CheckTimer||, CODE, READONLY, ALIGN=2 + + bsp_CheckTimer PROC +;;;385 */ +;;;386 uint8_t bsp_CheckTimer(uint8_t _id) +000000 4601 MOV r1,r0 +;;;387 { +;;;388 if (_id >= TMR_COUNT) +000002 2904 CMP r1,#4 +000004 db01 BLT |L6.10| +;;;389 { +;;;390 return 0; +000006 2000 MOVS r0,#0 + |L6.8| +;;;391 } +;;;392 +;;;393 if (s_tTmr[_id].Flag == 1) +;;;394 { +;;;395 s_tTmr[_id].Flag = 0; +;;;396 return 1; +;;;397 } +;;;398 else +;;;399 { +;;;400 return 0; +;;;401 } +;;;402 } +000008 4770 BX lr + |L6.10| +00000a eb010041 ADD r0,r1,r1,LSL #1 ;393 +00000e 4a08 LDR r2,|L6.48| +000010 eb020080 ADD r0,r2,r0,LSL #2 ;393 +000014 7840 LDRB r0,[r0,#1] ;393 +000016 2801 CMP r0,#1 ;393 +000018 d108 BNE |L6.44| +00001a 2000 MOVS r0,#0 ;395 +00001c eb010241 ADD r2,r1,r1,LSL #1 ;395 +000020 4b03 LDR r3,|L6.48| +000022 eb030282 ADD r2,r3,r2,LSL #2 ;395 +000026 7050 STRB r0,[r2,#1] ;395 +000028 2001 MOVS r0,#1 ;396 +00002a e7ed B |L6.8| + |L6.44| +00002c 2000 MOVS r0,#0 ;400 +00002e e7eb B |L6.8| +;;;403 + ENDP + + |L6.48| + DCD s_tTmr + + AREA ||i.bsp_DelayMS||, CODE, READONLY, ALIGN=2 + + bsp_DelayMS PROC +;;;210 */ +;;;211 void bsp_DelayMS(uint32_t n) +000000 b510 PUSH {r4,lr} +;;;212 { +000002 4604 MOV r4,r0 +;;;213 if (n == 0) +000004 b904 CBNZ r4,|L7.8| + |L7.6| +;;;214 { +;;;215 return; +;;;216 } +;;;217 else if (n == 1) +;;;218 { +;;;219 n = 2; +;;;220 } +;;;221 +;;;222 DISABLE_INT(); /* 关中断 */ +;;;223 +;;;224 s_uiDelayCount = n; +;;;225 s_ucTimeOutFlag = 0; +;;;226 +;;;227 ENABLE_INT(); /* 开中断 */ +;;;228 +;;;229 while (1) +;;;230 { +;;;231 bsp_Idle(); /* CPU空闲执行的操作， 见 bsp.c 和 bsp.h 文件 */ +;;;232 +;;;233 /* +;;;234 等待延迟时间到 +;;;235 注意：编译器认为 s_ucTimeOutFlag = 0，所以可能优化错误，因此 s_ucTimeOutFlag 变量必须申明为 volatile +;;;236 */ +;;;237 if (s_ucTimeOutFlag == 1) +;;;238 { +;;;239 break; +;;;240 } +;;;241 } +;;;242 } +000006 bd10 POP {r4,pc} + |L7.8| +000008 2c01 CMP r4,#1 ;217 +00000a d100 BNE |L7.14| +00000c 2402 MOVS r4,#2 ;219 + |L7.14| +00000e 2001 MOVS r0,#1 ;222 +000010 f7fffffe BL __set_PRIMASK +000014 4809 LDR r0,|L7.60| +000016 6004 STR r4,[r0,#0] ;224 ; s_uiDelayCount +000018 2000 MOVS r0,#0 ;225 +00001a 4909 LDR r1,|L7.64| +00001c 7008 STRB r0,[r1,#0] ;225 +00001e f7fffffe BL __set_PRIMASK +000022 e006 B |L7.50| + |L7.36| +000024 f7fffffe BL bsp_Idle +000028 4805 LDR r0,|L7.64| +00002a 7800 LDRB r0,[r0,#0] ;237 ; s_ucTimeOutFlag +00002c 2801 CMP r0,#1 ;237 +00002e d100 BNE |L7.50| +000030 e000 B |L7.52| + |L7.50| +000032 e7f7 B |L7.36| + |L7.52| +000034 bf00 NOP ;239 +000036 bf00 NOP +000038 e7e5 B |L7.6| +;;;243 + ENDP + +00003a 0000 DCW 0x0000 + |L7.60| + DCD s_uiDelayCount + |L7.64| + DCD s_ucTimeOutFlag + + AREA ||i.bsp_DelayUS||, CODE, READONLY, ALIGN=2 + + bsp_DelayUS PROC +;;;251 */ +;;;252 void bsp_DelayUS(uint32_t n) +000000 b5f0 PUSH {r4-r7,lr} +;;;253 { +000002 4603 MOV r3,r0 +;;;254 uint32_t ticks; +;;;255 uint32_t told; +;;;256 uint32_t tnow; +;;;257 uint32_t tcnt = 0; +000004 2200 MOVS r2,#0 +;;;258 uint32_t reload; +;;;259 +;;;260 reload = SysTick->LOAD; +000006 f04f26e0 MOV r6,#0xe000e000 +00000a 6975 LDR r5,[r6,#0x14] +;;;261 ticks = n * (SystemCoreClock / 1000000); /* 需要的节拍数 */ +00000c 4e0f LDR r6,|L8.76| +00000e 6836 LDR r6,[r6,#0] ; SystemCoreClock +000010 4f0f LDR r7,|L8.80| +000012 fbb6f6f7 UDIV r6,r6,r7 +000016 fb06f403 MUL r4,r6,r3 +;;;262 +;;;263 tcnt = 0; +00001a bf00 NOP +;;;264 told = SysTick->VAL; /* 刚进入时的计数器值 */ +00001c f04f26e0 MOV r6,#0xe000e000 +000020 69b1 LDR r1,[r6,#0x18] +;;;265 +;;;266 while (1) +000022 e010 B |L8.70| + |L8.36| +;;;267 { +;;;268 tnow = SysTick->VAL; +000024 f04f26e0 MOV r6,#0xe000e000 +000028 69b0 LDR r0,[r6,#0x18] +;;;269 if (tnow != told) +00002a 4288 CMP r0,r1 +00002c d00b BEQ |L8.70| +;;;270 { +;;;271 /* SYSTICK是一个递减的计数器 */ +;;;272 if (tnow < told) +00002e 4288 CMP r0,r1 +000030 d202 BCS |L8.56| +;;;273 { +;;;274 tcnt += told - tnow; +000032 1a0e SUBS r6,r1,r0 +000034 4432 ADD r2,r2,r6 +000036 e002 B |L8.62| + |L8.56| +;;;275 } +;;;276 /* 重新装载递减 */ +;;;277 else +;;;278 { +;;;279 tcnt += reload - tnow + told; +000038 1a2e SUBS r6,r5,r0 +00003a 440e ADD r6,r6,r1 +00003c 4432 ADD r2,r2,r6 + |L8.62| +;;;280 } +;;;281 told = tnow; +00003e 4601 MOV r1,r0 +;;;282 +;;;283 /* 时间超过/等于要延迟的时间,则退出 */ +;;;284 if (tcnt >= ticks) +000040 42a2 CMP r2,r4 +000042 d300 BCC |L8.70| +;;;285 { +;;;286 break; +000044 e000 B |L8.72| + |L8.70| +000046 e7ed B |L8.36| + |L8.72| +000048 bf00 NOP +;;;287 } +;;;288 } +;;;289 } +;;;290 } +00004a bdf0 POP {r4-r7,pc} +;;;291 + ENDP + + |L8.76| + DCD SystemCoreClock + |L8.80| + DCD 0x000f4240 + + AREA ||i.bsp_GetRunTime||, CODE, READONLY, ALIGN=2 + + bsp_GetRunTime PROC +;;;411 */ +;;;412 int32_t bsp_GetRunTime(void) +000000 b510 PUSH {r4,lr} +;;;413 { +;;;414 int32_t runtime; +;;;415 +;;;416 DISABLE_INT(); /* 关中断 */ +000002 2001 MOVS r0,#1 +000004 f7fffffe BL __set_PRIMASK +;;;417 +;;;418 runtime = g_iRunTime; /* 这个变量在Systick中断中被改写，因此需要关中断进行保护 */ +000008 4803 LDR r0,|L9.24| +00000a 6804 LDR r4,[r0,#0] ; g_iRunTime +;;;419 +;;;420 ENABLE_INT(); /* 开中断 */ +00000c 2000 MOVS r0,#0 +00000e f7fffffe BL __set_PRIMASK +;;;421 +;;;422 return runtime; +000012 4620 MOV r0,r4 +;;;423 } +000014 bd10 POP {r4,pc} +;;;424 + ENDP + +000016 0000 DCW 0x0000 + |L9.24| + DCD g_iRunTime + + AREA ||i.bsp_InitHardTimer||, CODE, READONLY, ALIGN=2 + + bsp_InitHardTimer PROC +;;;478 #if defined(USE_TIM2) || defined(USE_TIM3) || defined(USE_TIM4) || defined(USE_TIM5) +;;;479 void bsp_InitHardTimer(void) +000000 b57f PUSH {r0-r6,lr} +;;;480 { +;;;481 TIM_TimeBaseInitTypeDef TIM_TimeBaseStructure; +;;;482 uint32_t usPeriod; +;;;483 uint16_t usPrescaler; +;;;484 uint32_t uiTIMxCLK; +;;;485 +;;;486 /* 使能TIM时钟 */ +;;;487 RCC_APB1PeriphClockCmd(TIM_HARD_RCC, ENABLE); +000002 2101 MOVS r1,#1 +000004 4608 MOV r0,r1 +000006 f7fffffe BL RCC_APB1PeriphClockCmd +;;;488 +;;;489 /*----------------------------------------------------------------------- +;;;490 system_stm32f4xx.c 文件中 void SetSysClock(void) 函数对时钟的配置如下： +;;;491 +;;;492 HCLK = SYSCLK / 1 (AHB1Periph) +;;;493 PCLK2 = HCLK / 2 (APB2Periph) +;;;494 PCLK1 = HCLK / 4 (APB1Periph) +;;;495 +;;;496 因为APB1 prescaler != 1, 所以 APB1上的TIMxCLK = PCLK1 x 2 = SystemCoreClock / 2; +;;;497 因为APB2 prescaler != 1, 所以 APB2上的TIMxCLK = PCLK2 x 2 = SystemCoreClock; +;;;498 +;;;499 APB1 定时器有 TIM2, TIM3 ,TIM4, TIM5, TIM6, TIM7, TIM12, TIM13,TIM14 +;;;500 APB2 定时器有 TIM1, TIM8 ,TIM9, TIM10, TIM11 +;;;501 +;;;502 ----------------------------------------------------------------------- */ +;;;503 uiTIMxCLK = SystemCoreClock / 2; +00000a 4815 LDR r0,|L10.96| +00000c 6800 LDR r0,[r0,#0] ; SystemCoreClock +00000e 0846 LSRS r6,r0,#1 +;;;504 +;;;505 usPrescaler = uiTIMxCLK / 1000000; /* 分频到周期 1us */ +000010 4814 LDR r0,|L10.100| +000012 fbb6f0f0 UDIV r0,r6,r0 +000016 b285 UXTH r5,r0 +;;;506 +;;;507 #if defined(USE_TIM2) || defined(USE_TIM5) +;;;508 // usPeriod = 0xFFFFFFFF; /* 407支持32位定时器 */ +;;;509 usPeriod = 0xFFFF; /* 103支持16位 */ +000018 f64f74ff MOV r4,#0xffff +;;;510 #else +;;;511 usPeriod = 0xFFFF; +;;;512 #endif +;;;513 /* Time base configuration */ +;;;514 TIM_TimeBaseStructure.TIM_Period = usPeriod; +00001c f8ad4008 STRH r4,[sp,#8] +;;;515 TIM_TimeBaseStructure.TIM_Prescaler = usPrescaler; +000020 f8ad5004 STRH r5,[sp,#4] +;;;516 TIM_TimeBaseStructure.TIM_ClockDivision = 0; +000024 2000 MOVS r0,#0 +000026 f8ad000a STRH r0,[sp,#0xa] +;;;517 TIM_TimeBaseStructure.TIM_CounterMode = TIM_CounterMode_Up; +00002a f8ad0006 STRH r0,[sp,#6] +;;;518 +;;;519 TIM_TimeBaseInit(TIM_HARD, &TIM_TimeBaseStructure); +00002e a901 ADD r1,sp,#4 +000030 f04f4080 MOV r0,#0x40000000 +000034 f7fffffe BL TIM_TimeBaseInit +;;;520 +;;;521 // TIM_ARRPreloadConfig(TIMx, ENABLE); +;;;522 +;;;523 /* TIMx enable counter */ +;;;524 TIM_Cmd(TIM_HARD, ENABLE); +000038 2101 MOVS r1,#1 +00003a 0788 LSLS r0,r1,#30 +00003c f7fffffe BL TIM_Cmd +;;;525 +;;;526 /* 配置TIM定时中断 (Update) */ +;;;527 { +;;;528 NVIC_InitTypeDef NVIC_InitStructure; /* 中断结构体在 misc.h 中定义 */ +;;;529 +;;;530 NVIC_InitStructure.NVIC_IRQChannel = TIM_HARD_IRQn; +000040 201c MOVS r0,#0x1c +000042 f88d0000 STRB r0,[sp,#0] +;;;531 +;;;532 NVIC_InitStructure.NVIC_IRQChannelPreemptionPriority = 4; /* 比串口优先级低 */ +000046 2004 MOVS r0,#4 +000048 f88d0001 STRB r0,[sp,#1] +;;;533 NVIC_InitStructure.NVIC_IRQChannelSubPriority = 0; +00004c 2000 MOVS r0,#0 +00004e f88d0002 STRB r0,[sp,#2] +;;;534 NVIC_InitStructure.NVIC_IRQChannelCmd = ENABLE; +000052 2001 MOVS r0,#1 +000054 f88d0003 STRB r0,[sp,#3] +;;;535 NVIC_Init(&NVIC_InitStructure); +000058 4668 MOV r0,sp +00005a f7fffffe BL NVIC_Init +;;;536 } +;;;537 } +00005e bd7f POP {r0-r6,pc} +;;;538 + ENDP + + |L10.96| + DCD SystemCoreClock + |L10.100| + DCD 0x000f4240 + + AREA ||i.bsp_InitTimer||, CODE, READONLY, ALIGN=2 + + bsp_InitTimer PROC +;;;90 */ +;;;91 void bsp_InitTimer(void) +000000 b570 PUSH {r4-r6,lr} +;;;92 { +;;;93 uint8_t i; +;;;94 +;;;95 /* 清零所有的软件定时器 */ +;;;96 for (i = 0; i < TMR_COUNT; i++) +000002 2400 MOVS r4,#0 +000004 e016 B |L11.52| + |L11.6| +;;;97 { +;;;98 s_tTmr[i].Count = 0; +000006 2000 MOVS r0,#0 +000008 eb040144 ADD r1,r4,r4,LSL #1 +00000c 4a20 LDR r2,|L11.144| +00000e eb020181 ADD r1,r2,r1,LSL #2 +000012 6048 STR r0,[r1,#4] +;;;99 s_tTmr[i].PreLoad = 0; +000014 eb040144 ADD r1,r4,r4,LSL #1 +000018 eb020181 ADD r1,r2,r1,LSL #2 +00001c 6088 STR r0,[r1,#8] +;;;100 s_tTmr[i].Flag = 0; +00001e eb040144 ADD r1,r4,r4,LSL #1 +000022 eb020181 ADD r1,r2,r1,LSL #2 +000026 7048 STRB r0,[r1,#1] +;;;101 s_tTmr[i].Mode = TMR_ONCE_MODE; /* 缺省是1次性工作模式 */ +000028 eb040144 ADD r1,r4,r4,LSL #1 +00002c f8020021 STRB r0,[r2,r1,LSL #2] +000030 1c60 ADDS r0,r4,#1 ;96 +000032 b2c4 UXTB r4,r0 ;96 + |L11.52| +000034 2c04 CMP r4,#4 ;96 +000036 dbe6 BLT |L11.6| +;;;102 } +;;;103 +;;;104 /* +;;;105 配置systic中断周期为1ms，并启动systick中断。 +;;;106 +;;;107 SystemCoreClock 是固件中定义的系统内核时钟，对于STM32F4XX,一般为 168MHz +;;;108 +;;;109 SysTick_Config() 函数的形参表示内核时钟多少个周期后触发一次Systick定时中断. +;;;110 -- SystemCoreClock / 1000 表示定时频率为 1000Hz， 也就是定时周期为 1ms +;;;111 -- SystemCoreClock / 500 表示定时频率为 500Hz， 也就是定时周期为 2ms +;;;112 -- SystemCoreClock / 2000 表示定时频率为 2000Hz， 也就是定时周期为 500us +;;;113 +;;;114 对于常规的应用，我们一般取定时周期1ms。对于低速CPU或者低功耗应用，可以设置定时周期为 10ms +;;;115 */ +;;;116 SysTick_Config(SystemCoreClock / 1000); +000038 4816 LDR r0,|L11.148| +00003a 6800 LDR r0,[r0,#0] ; SystemCoreClock +00003c f44f727a MOV r2,#0x3e8 +000040 fbb0f1f2 UDIV r1,r0,r2 +000044 f1b17f80 CMP r1,#0x1000000 +000048 d300 BCC |L11.76| +00004a e01d B |L11.136| + |L11.76| +00004c f021407f BIC r0,r1,#0xff000000 +000050 1e40 SUBS r0,r0,#1 +000052 f04f22e0 MOV r2,#0xe000e000 +000056 6150 STR r0,[r2,#0x14] +000058 1750 ASRS r0,r2,#29 +00005a 220f MOVS r2,#0xf +00005c 2800 CMP r0,#0 +00005e da07 BGE |L11.112| +000060 0713 LSLS r3,r2,#28 +000062 0e1e LSRS r6,r3,#24 +000064 4b0c LDR r3,|L11.152| +000066 f000050f AND r5,r0,#0xf +00006a 1f2d SUBS r5,r5,#4 +00006c 555e STRB r6,[r3,r5] +00006e e003 B |L11.120| + |L11.112| +000070 0713 LSLS r3,r2,#28 +000072 0e1d LSRS r5,r3,#24 +000074 4b09 LDR r3,|L11.156| +000076 541d STRB r5,[r3,r0] + |L11.120| +000078 bf00 NOP +00007a 2000 MOVS r0,#0 +00007c f04f22e0 MOV r2,#0xe000e000 +000080 6190 STR r0,[r2,#0x18] +000082 2007 MOVS r0,#7 +000084 6110 STR r0,[r2,#0x10] +000086 bf00 NOP + |L11.136| +;;;117 +;;;118 #if defined(USE_TIM2) || defined(USE_TIM3) || defined(USE_TIM4) || defined(USE_TIM5) +;;;119 bsp_InitHardTimer(); +000088 f7fffffe BL bsp_InitHardTimer +;;;120 #endif +;;;121 } +00008c bd70 POP {r4-r6,pc} +;;;122 + ENDP + +00008e 0000 DCW 0x0000 + |L11.144| + DCD s_tTmr + |L11.148| + DCD SystemCoreClock + |L11.152| + DCD 0xe000ed18 + |L11.156| + DCD 0xe000e400 + + AREA ||i.bsp_SoftTimerDec||, CODE, READONLY, ALIGN=1 + + bsp_SoftTimerDec PROC +;;;184 */ +;;;185 static void bsp_SoftTimerDec(SOFT_TMR *_tmr) +000000 6841 LDR r1,[r0,#4] +;;;186 { +;;;187 if (_tmr->Count > 0) +000002 b151 CBZ r1,|L12.26| +;;;188 { +;;;189 /* 如果定时器变量减到1则设置定时器到达标志 */ +;;;190 if (--_tmr->Count == 0) +000004 6841 LDR r1,[r0,#4] +000006 1e49 SUBS r1,r1,#1 +000008 6041 STR r1,[r0,#4] +00000a b931 CBNZ r1,|L12.26| +;;;191 { +;;;192 _tmr->Flag = 1; +00000c 2101 MOVS r1,#1 +00000e 7041 STRB r1,[r0,#1] +;;;193 +;;;194 /* 如果是自动模式，则自动重装计数器 */ +;;;195 if (_tmr->Mode == TMR_AUTO_MODE) +000010 7801 LDRB r1,[r0,#0] +000012 2901 CMP r1,#1 +000014 d101 BNE |L12.26| +;;;196 { +;;;197 _tmr->Count = _tmr->PreLoad; +000016 6881 LDR r1,[r0,#8] +000018 6041 STR r1,[r0,#4] + |L12.26| +;;;198 } +;;;199 } +;;;200 } +;;;201 } +00001a 4770 BX lr +;;;202 + ENDP + + + AREA ||i.bsp_StartAutoTimer||, CODE, READONLY, ALIGN=2 + + REQUIRE _printf_percent + REQUIRE _printf_s + REQUIRE _printf_str + bsp_StartAutoTimer PROC +;;;329 */ +;;;330 void bsp_StartAutoTimer(uint8_t _id, uint32_t _period) +000000 b570 PUSH {r4-r6,lr} +;;;331 { +000002 4604 MOV r4,r0 +000004 460d MOV r5,r1 +;;;332 if (_id >= TMR_COUNT) +000006 2c04 CMP r4,#4 +000008 db06 BLT |L13.24| +;;;333 { +;;;334 /* 打印出错的源代码文件名、函数名称 */ +;;;335 BSP_Printf("Error: file %s, function %s()\r\n", __FILE__, __FUNCTION__); +00000a 4a12 LDR r2,|L13.84| +00000c a112 ADR r1,|L13.88| +00000e a01a ADR r0,|L13.120| +000010 f7fffffe BL __2printf +;;;336 while (1) +000014 bf00 NOP + |L13.22| +000016 e7fe B |L13.22| + |L13.24| +;;;337 ; /* 参数异常，死机等待看门狗复位 */ +;;;338 } +;;;339 +;;;340 DISABLE_INT(); /* 关中断 */ +000018 2001 MOVS r0,#1 +00001a f7fffffe BL __set_PRIMASK +;;;341 +;;;342 s_tTmr[_id].Count = _period; /* 实时计数器初值 */ +00001e eb040044 ADD r0,r4,r4,LSL #1 +000022 491d LDR r1,|L13.152| +000024 eb010080 ADD r0,r1,r0,LSL #2 +000028 6045 STR r5,[r0,#4] +;;;343 s_tTmr[_id].PreLoad = _period; /* 计数器自动重装值，仅自动模式起作用 */ +00002a eb040044 ADD r0,r4,r4,LSL #1 +00002e eb010080 ADD r0,r1,r0,LSL #2 +000032 6085 STR r5,[r0,#8] +;;;344 s_tTmr[_id].Flag = 0; /* 定时时间到标志 */ +000034 2000 MOVS r0,#0 +000036 eb040144 ADD r1,r4,r4,LSL #1 +00003a 4a17 LDR r2,|L13.152| +00003c eb020181 ADD r1,r2,r1,LSL #2 +000040 7048 STRB r0,[r1,#1] +;;;345 s_tTmr[_id].Mode = TMR_AUTO_MODE; /* 自动工作模式 */ +000042 2001 MOVS r0,#1 +000044 eb040144 ADD r1,r4,r4,LSL #1 +000048 f8020021 STRB r0,[r2,r1,LSL #2] +;;;346 +;;;347 ENABLE_INT(); /* 开中断 */ +00004c 2000 MOVS r0,#0 +00004e f7fffffe BL __set_PRIMASK +;;;348 } +000052 bd70 POP {r4-r6,pc} +;;;349 + ENDP + + |L13.84| + DCD |symbol_number.53| + |L13.88| +000058 2e2e5c2e DCB "..\\..\\User\\bsp\\src\\bsp_timer.c",0 +00005c 2e5c5573 +000060 65725c62 +000064 73705c73 +000068 72635c62 +00006c 73705f74 +000070 696d6572 +000074 2e6300 +000077 00 DCB 0 + |L13.120| +000078 4572726f DCB "Error: file %s, function %s()\r\n",0 +00007c 723a2066 +000080 696c6520 +000084 25732c20 +000088 66756e63 +00008c 74696f6e +000090 20257328 +000094 290d0a00 + |L13.152| + DCD s_tTmr + + AREA ||i.bsp_StartHardTimer||, CODE, READONLY, ALIGN=2 + + bsp_StartHardTimer PROC +;;;551 */ +;;;552 void bsp_StartHardTimer(uint8_t _CC, uint32_t _uiTimeOut, void *_pCallBack) +000000 e92d41f0 PUSH {r4-r8,lr} +;;;553 { +000004 4604 MOV r4,r0 +000006 460f MOV r7,r1 +000008 4615 MOV r5,r2 +;;;554 uint32_t cnt_now; +;;;555 uint32_t cnt_tar; +;;;556 +;;;557 /* +;;;558 执行下面这个语句，时长 = 18us (通过逻辑分析仪测量IO翻转) +;;;559 bsp_StartTimer2(3, 500, (void *)test1); +;;;560 */ +;;;561 if (_uiTimeOut < 5) +00000a 2f05 CMP r7,#5 +00000c d300 BCC |L14.16| +;;;562 { +;;;563 ; +;;;564 } +;;;565 else +;;;566 { +;;;567 _uiTimeOut -= 5; +00000e 1f7f SUBS r7,r7,#5 + |L14.16| +;;;568 } +;;;569 +;;;570 cnt_now = TIM_GetCounter(TIM_HARD); /* 读取当前的计数器值 */ +000010 f04f4080 MOV r0,#0x40000000 +000014 f7fffffe BL TIM_GetCounter +000018 4680 MOV r8,r0 +;;;571 cnt_tar = cnt_now + _uiTimeOut; /* 计算捕获的计数器值 */ +00001a eb080607 ADD r6,r8,r7 +;;;572 if (_CC == 1) +00001e 2c01 CMP r4,#1 +000020 d10f BNE |L14.66| +;;;573 { +;;;574 s_TIM_CallBack1 = (void (*)(void))_pCallBack; +000022 4825 LDR r0,|L14.184| +000024 6005 STR r5,[r0,#0] ; s_TIM_CallBack1 +;;;575 +;;;576 TIM_SetCompare1(TIM_HARD, cnt_tar); /* 设置捕获比较计数器CC1 */ +000026 b2b1 UXTH r1,r6 +000028 07a0 LSLS r0,r4,#30 +00002a f7fffffe BL TIM_SetCompare1 +;;;577 TIM_ClearITPendingBit(TIM_HARD, TIM_IT_CC1); +00002e 2102 MOVS r1,#2 +000030 0748 LSLS r0,r1,#29 +000032 f7fffffe BL TIM_ClearITPendingBit +;;;578 TIM_ITConfig(TIM_HARD, TIM_IT_CC1, ENABLE); /* 使能CC1中断 */ +000036 2201 MOVS r2,#1 +000038 2102 MOVS r1,#2 +00003a 0748 LSLS r0,r1,#29 +00003c f7fffffe BL TIM_ITConfig +000040 e038 B |L14.180| + |L14.66| +;;;579 } +;;;580 else if (_CC == 2) +000042 2c02 CMP r4,#2 +000044 d10f BNE |L14.102| +;;;581 { +;;;582 s_TIM_CallBack2 = (void (*)(void))_pCallBack; +000046 481d LDR r0,|L14.188| +000048 6005 STR r5,[r0,#0] ; s_TIM_CallBack2 +;;;583 +;;;584 TIM_SetCompare2(TIM_HARD, cnt_tar); /* 设置捕获比较计数器CC2 */ +00004a b2b1 UXTH r1,r6 +00004c 0760 LSLS r0,r4,#29 +00004e f7fffffe BL TIM_SetCompare2 +;;;585 TIM_ClearITPendingBit(TIM_HARD, TIM_IT_CC2); +000052 2104 MOVS r1,#4 +000054 0708 LSLS r0,r1,#28 +000056 f7fffffe BL TIM_ClearITPendingBit +;;;586 TIM_ITConfig(TIM_HARD, TIM_IT_CC2, ENABLE); /* 使能CC2中断 */ +00005a 2201 MOVS r2,#1 +00005c 2104 MOVS r1,#4 +00005e 0708 LSLS r0,r1,#28 +000060 f7fffffe BL TIM_ITConfig +000064 e026 B |L14.180| + |L14.102| +;;;587 } +;;;588 else if (_CC == 3) +000066 2c03 CMP r4,#3 +000068 d110 BNE |L14.140| +;;;589 { +;;;590 s_TIM_CallBack3 = (void (*)(void))_pCallBack; +00006a 4815 LDR r0,|L14.192| +00006c 6005 STR r5,[r0,#0] ; s_TIM_CallBack3 +;;;591 +;;;592 TIM_SetCompare3(TIM_HARD, cnt_tar); /* 设置捕获比较计数器CC3 */ +00006e b2b1 UXTH r1,r6 +000070 f04f4080 MOV r0,#0x40000000 +000074 f7fffffe BL TIM_SetCompare3 +;;;593 TIM_ClearITPendingBit(TIM_HARD, TIM_IT_CC3); +000078 2108 MOVS r1,#8 +00007a 06c8 LSLS r0,r1,#27 +00007c f7fffffe BL TIM_ClearITPendingBit +;;;594 TIM_ITConfig(TIM_HARD, TIM_IT_CC3, ENABLE); /* 使能CC3中断 */ +000080 2201 MOVS r2,#1 +000082 2108 MOVS r1,#8 +000084 06c8 LSLS r0,r1,#27 +000086 f7fffffe BL TIM_ITConfig +00008a e013 B |L14.180| + |L14.140| +;;;595 } +;;;596 else if (_CC == 4) +00008c 2c04 CMP r4,#4 +00008e d10f BNE |L14.176| +;;;597 { +;;;598 s_TIM_CallBack4 = (void (*)(void))_pCallBack; +000090 480c LDR r0,|L14.196| +000092 6005 STR r5,[r0,#0] ; s_TIM_CallBack4 +;;;599 +;;;600 TIM_SetCompare4(TIM_HARD, cnt_tar); /* 设置捕获比较计数器CC4 */ +000094 b2b1 UXTH r1,r6 +000096 0720 LSLS r0,r4,#28 +000098 f7fffffe BL TIM_SetCompare4 +;;;601 TIM_ClearITPendingBit(TIM_HARD, TIM_IT_CC4); +00009c 2110 MOVS r1,#0x10 +00009e 0688 LSLS r0,r1,#26 +0000a0 f7fffffe BL TIM_ClearITPendingBit +;;;602 TIM_ITConfig(TIM_HARD, TIM_IT_CC4, ENABLE); /* 使能CC4中断 */ +0000a4 2201 MOVS r2,#1 +0000a6 2110 MOVS r1,#0x10 +0000a8 0688 LSLS r0,r1,#26 +0000aa f7fffffe BL TIM_ITConfig +0000ae e001 B |L14.180| + |L14.176| +;;;603 } +;;;604 else +;;;605 { +;;;606 return; +;;;607 } +;;;608 } +0000b0 e8bd81f0 POP {r4-r8,pc} + |L14.180| +0000b4 bf00 NOP +0000b6 e7fb B |L14.176| +;;;609 #endif + ENDP + + |L14.184| + DCD s_TIM_CallBack1 + |L14.188| + DCD s_TIM_CallBack2 + |L14.192| + DCD s_TIM_CallBack3 + |L14.196| + DCD s_TIM_CallBack4 + + AREA ||i.bsp_StartTimer||, CODE, READONLY, ALIGN=2 + + REQUIRE _printf_percent + REQUIRE _printf_s + REQUIRE _printf_str + bsp_StartTimer PROC +;;;300 */ +;;;301 void bsp_StartTimer(uint8_t _id, uint32_t _period) +000000 b570 PUSH {r4-r6,lr} +;;;302 { +000002 4604 MOV r4,r0 +000004 460d MOV r5,r1 +;;;303 if (_id >= TMR_COUNT) +000006 2c04 CMP r4,#4 +000008 db06 BLT |L15.24| +;;;304 { +;;;305 /* 打印出错的源代码文件名、函数名称 */ +;;;306 BSP_Printf("Error: file %s, function %s()\r\n", __FILE__, __FUNCTION__); +00000a 4a11 LDR r2,|L15.80| +00000c a111 ADR r1,|L15.84| +00000e a019 ADR r0,|L15.116| +000010 f7fffffe BL __2printf +;;;307 while (1) +000014 bf00 NOP + |L15.22| +000016 e7fe B |L15.22| + |L15.24| +;;;308 ; /* 参数异常，死机等待看门狗复位 */ +;;;309 } +;;;310 +;;;311 DISABLE_INT(); /* 关中断 */ +000018 2001 MOVS r0,#1 +00001a f7fffffe BL __set_PRIMASK +;;;312 +;;;313 s_tTmr[_id].Count = _period; /* 实时计数器初值 */ +00001e eb040044 ADD r0,r4,r4,LSL #1 +000022 491c LDR r1,|L15.148| +000024 eb010080 ADD r0,r1,r0,LSL #2 +000028 6045 STR r5,[r0,#4] +;;;314 s_tTmr[_id].PreLoad = _period; /* 计数器自动重装值，仅自动模式起作用 */ +00002a eb040044 ADD r0,r4,r4,LSL #1 +00002e eb010080 ADD r0,r1,r0,LSL #2 +000032 6085 STR r5,[r0,#8] +;;;315 s_tTmr[_id].Flag = 0; /* 定时时间到标志 */ +000034 2000 MOVS r0,#0 +000036 eb040144 ADD r1,r4,r4,LSL #1 +00003a 4a16 LDR r2,|L15.148| +00003c eb020181 ADD r1,r2,r1,LSL #2 +000040 7048 STRB r0,[r1,#1] +;;;316 s_tTmr[_id].Mode = TMR_ONCE_MODE; /* 1次性工作模式 */ +000042 eb040144 ADD r1,r4,r4,LSL #1 +000046 f8020021 STRB r0,[r2,r1,LSL #2] +;;;317 +;;;318 ENABLE_INT(); /* 开中断 */ +00004a f7fffffe BL __set_PRIMASK +;;;319 } +00004e bd70 POP {r4-r6,pc} +;;;320 + ENDP + + |L15.80| + DCD __FUNCTION__ + |L15.84| +000054 2e2e5c2e DCB "..\\..\\User\\bsp\\src\\bsp_timer.c",0 +000058 2e5c5573 +00005c 65725c62 +000060 73705c73 +000064 72635c62 +000068 73705f74 +00006c 696d6572 +000070 2e6300 +000073 00 DCB 0 + |L15.116| +000074 4572726f DCB "Error: file %s, function %s()\r\n",0 +000078 723a2066 +00007c 696c6520 +000080 25732c20 +000084 66756e63 +000088 74696f6e +00008c 20257328 +000090 290d0a00 + |L15.148| + DCD s_tTmr + + AREA ||i.bsp_StopTimer||, CODE, READONLY, ALIGN=2 + + REQUIRE _printf_percent + REQUIRE _printf_s + REQUIRE _printf_str + bsp_StopTimer PROC +;;;357 */ +;;;358 void bsp_StopTimer(uint8_t _id) +000000 b510 PUSH {r4,lr} +;;;359 { +000002 4604 MOV r4,r0 +;;;360 if (_id >= TMR_COUNT) +000004 2c04 CMP r4,#4 +000006 db06 BLT |L16.22| +;;;361 { +;;;362 /* 打印出错的源代码文件名、函数名称 */ +;;;363 BSP_Printf("Error: file %s, function %s()\r\n", __FILE__, __FUNCTION__); +000008 4a0e LDR r2,|L16.68| +00000a a10f ADR r1,|L16.72| +00000c a016 ADR r0,|L16.104| +00000e f7fffffe BL __2printf +;;;364 while (1) +000012 bf00 NOP + |L16.20| +000014 e7fe B |L16.20| + |L16.22| +;;;365 ; /* 参数异常，死机等待看门狗复位 */ +;;;366 } +;;;367 +;;;368 DISABLE_INT(); /* 关中断 */ +000016 2001 MOVS r0,#1 +000018 f7fffffe BL __set_PRIMASK +;;;369 +;;;370 s_tTmr[_id].Count = 0; /* 实时计数器初值 */ +00001c 2000 MOVS r0,#0 +00001e eb040144 ADD r1,r4,r4,LSL #1 +000022 4a19 LDR r2,|L16.136| +000024 eb020181 ADD r1,r2,r1,LSL #2 +000028 6048 STR r0,[r1,#4] +;;;371 s_tTmr[_id].Flag = 0; /* 定时时间到标志 */ +00002a eb040144 ADD r1,r4,r4,LSL #1 +00002e eb020181 ADD r1,r2,r1,LSL #2 +000032 7048 STRB r0,[r1,#1] +;;;372 s_tTmr[_id].Mode = TMR_ONCE_MODE; /* 自动工作模式 */ +000034 eb040144 ADD r1,r4,r4,LSL #1 +000038 f8020021 STRB r0,[r2,r1,LSL #2] +;;;373 +;;;374 ENABLE_INT(); /* 开中断 */ +00003c f7fffffe BL __set_PRIMASK +;;;375 } +000040 bd10 POP {r4,pc} +;;;376 + ENDP + +000042 0000 DCW 0x0000 + |L16.68| + DCD |symbol_number.54| + |L16.72| +000048 2e2e5c2e DCB "..\\..\\User\\bsp\\src\\bsp_timer.c",0 +00004c 2e5c5573 +000050 65725c62 +000054 73705c73 +000058 72635c62 +00005c 73705f74 +000060 696d6572 +000064 2e6300 +000067 00 DCB 0 + |L16.104| +000068 4572726f DCB "Error: file %s, function %s()\r\n",0 +00006c 723a2066 +000070 696c6520 +000074 25732c20 +000078 66756e63 +00007c 74696f6e +000080 20257328 +000084 290d0a00 + |L16.136| + DCD s_tTmr + + AREA ||.bss||, DATA, NOINIT, ALIGN=2 + + s_tTmr + % 48 + + AREA ||.constdata||, DATA, READONLY, ALIGN=0 + + __FUNCTION__ +000000 6273705f DCB 0x62,0x73,0x70,0x5f +000004 53746172 DCB 0x53,0x74,0x61,0x72 +000008 7454696d DCB 0x74,0x54,0x69,0x6d +00000c 657200 DCB 0x65,0x72,0x00 + |symbol_number.53| +00000f 62 DCB 0x62 +000010 73705f53 DCB 0x73,0x70,0x5f,0x53 +000014 74617274 DCB 0x74,0x61,0x72,0x74 +000018 4175746f DCB 0x41,0x75,0x74,0x6f +00001c 54696d65 DCB 0x54,0x69,0x6d,0x65 +000020 7200 DCB 0x72,0x00 + |symbol_number.54| +000022 6273 DCB 0x62,0x73 +000024 705f5374 DCB 0x70,0x5f,0x53,0x74 +000028 6f705469 DCB 0x6f,0x70,0x54,0x69 +00002c 6d657200 DCB 0x6d,0x65,0x72,0x00 + + AREA ||.data||, DATA, ALIGN=2 + + s_uiDelayCount + DCD 0x00000000 + s_ucTimeOutFlag +000004 00000000 DCB 0x00,0x00,0x00,0x00 + g_iRunTime + DCD 0x00000000 + init_100ms +00000c 00000000 DCB 0x00,0x00,0x00,0x00 + s_TIM_CallBack1 + DCD 0x00000000 + s_TIM_CallBack2 + DCD 0x00000000 + s_TIM_CallBack3 + DCD 0x00000000 + s_TIM_CallBack4 + DCD 0x00000000 + s_count +000020 00 DCB 0x00 + +;*** Start embedded assembler *** + +#line 1 "..\\..\\User\\bsp\\src\\bsp_timer.c" + AREA ||.rev16_text||, CODE + THUMB + EXPORT |__asm___11_bsp_timer_c_95bb07ef____REV16| +#line 114 "..\\..\\Libraries\\CMSIS\\Include\\core_cmInstr.h" +|__asm___11_bsp_timer_c_95bb07ef____REV16| PROC +#line 115 + + rev16 r0, r0 + bx lr + ENDP + AREA ||.revsh_text||, CODE + THUMB + EXPORT |__asm___11_bsp_timer_c_95bb07ef____REVSH| +#line 128 +|__asm___11_bsp_timer_c_95bb07ef____REVSH| PROC +#line 129 + + revsh r0, r0 + bx lr + ENDP + +;*** End embedded assembler *** diff --git a/Project/MDK-ARM/Flash/List/bsp_uart_fifo.txt b/Project/MDK-ARM/Flash/List/bsp_uart_fifo.txt new file mode 100644 index 0000000..a700920 --- /dev/null +++ b/Project/MDK-ARM/Flash/List/bsp_uart_fifo.txt @@ -0,0 +1,1587 @@ +; generated by Component: ARM Compiler 5.06 update 7 (build 960) Tool: ArmCC [4d365d] +; commandline ArmCC [--list --split_sections --debug -c --asm --interleave -o.\flash\obj\bsp_uart_fifo.o --asm_dir=.\Flash\List\ --list_dir=.\Flash\List\ --depend=.\flash\obj\bsp_uart_fifo.d --cpu=Cortex-M3 --apcs=interwork -O1 --diag_suppress=9931,870 -I..\..\Libraries\CMSIS\Device\ST\STM32F10x\Include -I..\..\Libraries\STM32F10x_StdPeriph_Driver\inc -I..\..\Libraries\STM32_USB-FS-Device_Driver\inc -I..\..\Libraries\CMSIS\Include -I..\..\User\bsp -I..\..\User\bsp\inc -I..\..\User\app\inc -I..\..\User -ID:\Arm\Packs\Keil\STM32F1xx_DFP\2.4.1\Device\Include -D__MICROLIB -D__UVISION_VERSION=536 -DSTM32F10X_HD -DUSE_STDPERIPH_DRIVER -DSTM32F10X_HD --omf_browse=.\flash\obj\bsp_uart_fifo.crf ..\..\User\bsp\src\bsp_uart_fifo.c] + THUMB + + AREA ||i.ComToUart||, CODE, READONLY, ALIGN=2 + + ComToUart PROC +;;;92 */ +;;;93 UART_T *ComToUart(COM_PORT_E _ucPort) +000000 2800 CMP r0,#0 +;;;94 { +000002 d009 BEQ |L1.24| +;;;95 if (_ucPort == COM1) +;;;96 { +;;;97 #if UART1_FIFO_EN == 1 +;;;98 return &g_tUart1; +;;;99 #else +;;;100 return 0; +;;;101 #endif +;;;102 } +;;;103 else if (_ucPort == COM2) +000004 2801 CMP r0,#1 +000006 d009 BEQ |L1.28| +;;;104 { +;;;105 #if UART2_FIFO_EN == 1 +;;;106 return &g_tUart2; +;;;107 #else +;;;108 return 0; +;;;109 #endif +;;;110 } +;;;111 else if (_ucPort == COM3) +000008 2802 CMP r0,#2 +00000a d009 BEQ |L1.32| +;;;112 { +;;;113 #if UART3_FIFO_EN == 1 +;;;114 return &g_tUart3; +;;;115 #else +;;;116 return 0; +;;;117 #endif +;;;118 } +;;;119 else if (_ucPort == COM4) +00000c 2803 CMP r0,#3 +00000e d009 BEQ |L1.36| +;;;120 { +;;;121 #if UART4_FIFO_EN == 1 +;;;122 return &g_tUart4; +;;;123 #else +;;;124 return 0; +;;;125 #endif +;;;126 } +;;;127 else if (_ucPort == COM5) +000010 2804 CMP r0,#4 +000012 d009 BEQ |L1.40| +;;;128 { +;;;129 #if UART5_FIFO_EN == 1 +;;;130 return &g_tUart5; +;;;131 #else +;;;132 return 0; +;;;133 #endif +;;;134 } +;;;135 else +;;;136 { +;;;137 /* κδ */ +;;;138 return 0; +000014 2000 MOVS r0,#0 +;;;139 } +;;;140 } +000016 4770 BX lr + |L1.24| +000018 4804 LDR r0,|L1.44| +00001a 4770 BX lr + |L1.28| +00001c 2000 MOVS r0,#0 ;108 +00001e 4770 BX lr + |L1.32| +000020 2000 MOVS r0,#0 ;116 +000022 4770 BX lr + |L1.36| +000024 2000 MOVS r0,#0 ;124 +000026 4770 BX lr + |L1.40| +000028 2000 MOVS r0,#0 ;132 +00002a 4770 BX lr +;;;141 + ENDP + + |L1.44| + DCD ||.bss||+0x20 + + AREA ||i.ConfigUartNVIC||, CODE, READONLY, ALIGN=1 + + ConfigUartNVIC PROC +;;;774 */ +;;;775 static void ConfigUartNVIC(void) +000000 b508 PUSH {r3,lr} +;;;776 { +;;;777 NVIC_InitTypeDef NVIC_InitStructure; +;;;778 +;;;779 /* Configure the NVIC Preemption Priority Bits */ +;;;780 /* NVIC_PriorityGroupConfig(NVIC_PriorityGroup_0); --- bsp.c bsp_Init() жȼ */ +;;;781 +;;;782 #if UART1_FIFO_EN == 1 +;;;783 /* ʹܴ1ж */ +;;;784 NVIC_InitStructure.NVIC_IRQChannel = USART1_IRQn; +000002 2025 MOVS r0,#0x25 +000004 f88d0000 STRB r0,[sp,#0] +;;;785 NVIC_InitStructure.NVIC_IRQChannelSubPriority = 0; +000008 2000 MOVS r0,#0 +00000a f88d0002 STRB r0,[sp,#2] +;;;786 NVIC_InitStructure.NVIC_IRQChannelCmd = ENABLE; +00000e 2001 MOVS r0,#1 +000010 f88d0003 STRB r0,[sp,#3] +;;;787 NVIC_Init(&NVIC_InitStructure); +000014 4668 MOV r0,sp +000016 f7fffffe BL NVIC_Init +;;;788 #endif +;;;789 +;;;790 #if UART2_FIFO_EN == 1 +;;;791 /* ʹܴ2ж */ +;;;792 NVIC_InitStructure.NVIC_IRQChannel = USART2_IRQn; +;;;793 NVIC_InitStructure.NVIC_IRQChannelSubPriority = 1; +;;;794 NVIC_InitStructure.NVIC_IRQChannelCmd = ENABLE; +;;;795 NVIC_Init(&NVIC_InitStructure); +;;;796 #endif +;;;797 +;;;798 #if UART3_FIFO_EN == 1 +;;;799 /* ʹܴ3жt */ +;;;800 NVIC_InitStructure.NVIC_IRQChannel = USART3_IRQn; +;;;801 NVIC_InitStructure.NVIC_IRQChannelSubPriority = 2; +;;;802 NVIC_InitStructure.NVIC_IRQChannelCmd = ENABLE; +;;;803 NVIC_Init(&NVIC_InitStructure); +;;;804 #endif +;;;805 +;;;806 #if UART4_FIFO_EN == 1 +;;;807 /* ʹܴ4жt */ +;;;808 NVIC_InitStructure.NVIC_IRQChannel = UART4_IRQn; +;;;809 NVIC_InitStructure.NVIC_IRQChannelSubPriority = 3; +;;;810 NVIC_InitStructure.NVIC_IRQChannelCmd = ENABLE; +;;;811 NVIC_Init(&NVIC_InitStructure); +;;;812 #endif +;;;813 +;;;814 #if UART5_FIFO_EN == 1 +;;;815 /* ʹܴ5жt */ +;;;816 NVIC_InitStructure.NVIC_IRQChannel = UART5_IRQn; +;;;817 NVIC_InitStructure.NVIC_IRQChannelSubPriority = 4; +;;;818 NVIC_InitStructure.NVIC_IRQChannelCmd = ENABLE; +;;;819 NVIC_Init(&NVIC_InitStructure); +;;;820 #endif +;;;821 +;;;822 #if UART6_FIFO_EN == 1 +;;;823 /* ʹܴ6жt */ +;;;824 NVIC_InitStructure.NVIC_IRQChannel = USART6_IRQn; +;;;825 NVIC_InitStructure.NVIC_IRQChannelSubPriority = 5; +;;;826 NVIC_InitStructure.NVIC_IRQChannelCmd = ENABLE; +;;;827 NVIC_Init(&NVIC_InitStructure); +;;;828 #endif +;;;829 } +00001a bd08 POP {r3,pc} +;;;830 + ENDP + + + AREA ||i.InitHardUart||, CODE, READONLY, ALIGN=2 + + InitHardUart PROC +;;;534 */ +;;;535 static void InitHardUart(void) +000000 b510 PUSH {r4,lr} +;;;536 { +000002 b086 SUB sp,sp,#0x18 +;;;537 GPIO_InitTypeDef GPIO_InitStructure; +;;;538 USART_InitTypeDef USART_InitStructure; +;;;539 +;;;540 #if UART1_FIFO_EN == 1 /* 1 TX = PA9 RX = PA10 TX = PB6 RX = PB7*/ +;;;541 +;;;542 /* 1GPIOUSARTʱ */ +;;;543 RCC_APB2PeriphClockCmd(RCC_APB2Periph_GPIOA | RCC_APB2Periph_AFIO, ENABLE); +000004 2101 MOVS r1,#1 +000006 2005 MOVS r0,#5 +000008 f7fffffe BL RCC_APB2PeriphClockCmd +;;;544 RCC_APB2PeriphClockCmd(RCC_APB2Periph_USART1, ENABLE); +00000c 2101 MOVS r1,#1 +00000e 0388 LSLS r0,r1,#14 +000010 f7fffffe BL RCC_APB2PeriphClockCmd +;;;545 +;;;546 /* 2USART TxGPIOΪ츴ģʽ */ +;;;547 GPIO_InitStructure.GPIO_Pin = GPIO_Pin_9; +000014 f44f7000 MOV r0,#0x200 +000018 f8ad0014 STRH r0,[sp,#0x14] +;;;548 GPIO_InitStructure.GPIO_Mode = GPIO_Mode_AF_PP; +00001c 2018 MOVS r0,#0x18 +00001e f88d0017 STRB r0,[sp,#0x17] +;;;549 GPIO_InitStructure.GPIO_Speed = GPIO_Speed_50MHz; +000022 2003 MOVS r0,#3 +000024 f88d0016 STRB r0,[sp,#0x16] +;;;550 GPIO_Init(GPIOA, &GPIO_InitStructure); +000028 4c19 LDR r4,|L3.144| +00002a a905 ADD r1,sp,#0x14 +00002c 4620 MOV r0,r4 +00002e f7fffffe BL GPIO_Init +;;;551 +;;;552 /* 3USART RxGPIOΪģʽ +;;;553 CPUλGPIOȱʡǸģʽ費DZ +;;;554 ǣһǽϱĶҷֹط޸ߵò +;;;555 */ +;;;556 GPIO_InitStructure.GPIO_Pin = GPIO_Pin_10; +000032 1521 ASRS r1,r4,#20 +000034 f8ad1014 STRH r1,[sp,#0x14] +;;;557 GPIO_InitStructure.GPIO_Mode = GPIO_Mode_IN_FLOATING; +000038 2104 MOVS r1,#4 +00003a f88d1017 STRB r1,[sp,#0x17] +;;;558 GPIO_Init(GPIOA, &GPIO_InitStructure); +00003e a905 ADD r1,sp,#0x14 +000040 4620 MOV r0,r4 +000042 f7fffffe BL GPIO_Init +;;;559 +;;;560 /* 4 ôӲ */ +;;;561 USART_InitStructure.USART_BaudRate = UART1_BAUD; /* */ +000046 f44f30e1 MOV r0,#0x1c200 +00004a 9001 STR r0,[sp,#4] +;;;562 USART_InitStructure.USART_WordLength = USART_WordLength_8b; +00004c 2000 MOVS r0,#0 +00004e f8ad0008 STRH r0,[sp,#8] +;;;563 USART_InitStructure.USART_StopBits = USART_StopBits_1; +000052 f8ad000a STRH r0,[sp,#0xa] +;;;564 USART_InitStructure.USART_Parity = USART_Parity_No ; +000056 f8ad000c STRH r0,[sp,#0xc] +;;;565 USART_InitStructure.USART_HardwareFlowControl = USART_HardwareFlowControl_None; +00005a f8ad0010 STRH r0,[sp,#0x10] +;;;566 USART_InitStructure.USART_Mode = USART_Mode_Rx | USART_Mode_Tx; +00005e 200c MOVS r0,#0xc +000060 f8ad000e STRH r0,[sp,#0xe] +;;;567 USART_Init(USART1, &USART_InitStructure); +000064 4c0b LDR r4,|L3.148| +000066 a901 ADD r1,sp,#4 +000068 4620 MOV r0,r4 +00006a f7fffffe BL USART_Init +;;;568 +;;;569 USART_ITConfig(USART1, USART_IT_RXNE, ENABLE); /* ʹܽж */ +00006e 2201 MOVS r2,#1 +000070 f2405125 MOV r1,#0x525 +000074 4620 MOV r0,r4 +000076 f7fffffe BL USART_ITConfig +;;;570 /* +;;;571 USART_ITConfig(USART1, USART_IT_TXE, ENABLE); +;;;572 ע: Ҫڴ˴򿪷ж +;;;573 жʹSendUart() +;;;574 */ +;;;575 USART_Cmd(USART1, ENABLE); /* ʹܴ */ +00007a 2101 MOVS r1,#1 +00007c 4620 MOV r0,r4 +00007e f7fffffe BL USART_Cmd +;;;576 +;;;577 /* CPUСȱݣúãֱSend1ֽڷͲȥ +;;;578 1ֽ޷ȷͳȥ */ +;;;579 USART_ClearFlag(USART1, USART_FLAG_TC); /* 巢ɱ־Transmission Complete flag */ +000082 2140 MOVS r1,#0x40 +000084 4620 MOV r0,r4 +000086 f7fffffe BL USART_ClearFlag +;;;580 #endif +;;;581 +;;;582 #if UART2_FIFO_EN == 1 /* 2 TX = PA2 RX = PA3 */ +;;;583 /* 1GPIOUSARTʱ */ +;;;584 RCC_APB2PeriphClockCmd(RCC_APB2Periph_GPIOA | RCC_APB2Periph_AFIO, ENABLE); +;;;585 RCC_APB1PeriphClockCmd(RCC_APB1Periph_USART2, ENABLE); +;;;586 +;;;587 /* 2USART TxGPIOΪ츴ģʽ */ +;;;588 GPIO_InitStructure.GPIO_Pin = GPIO_Pin_2; +;;;589 GPIO_InitStructure.GPIO_Mode = GPIO_Mode_AF_PP; +;;;590 GPIO_InitStructure.GPIO_Speed = GPIO_Speed_50MHz; +;;;591 GPIO_Init(GPIOA, &GPIO_InitStructure); +;;;592 +;;;593 /* 3USART RxGPIOΪģʽ +;;;594 CPUλGPIOȱʡǸģʽ費DZ +;;;595 ǣһǽϱĶҷֹط޸ߵò +;;;596 */ +;;;597 GPIO_InitStructure.GPIO_Pin = GPIO_Pin_3; +;;;598 GPIO_InitStructure.GPIO_Mode = GPIO_Mode_IN_FLOATING; +;;;599 GPIO_Init(GPIOA, &GPIO_InitStructure); +;;;600 /* 3ѾˣⲽԲ +;;;601 GPIO_InitStructure.GPIO_Speed = GPIO_Speed_50MHz; +;;;602 */ +;;;603 GPIO_Init(GPIOA, &GPIO_InitStructure); +;;;604 +;;;605 /* 4 ôӲ */ +;;;606 USART_InitStructure.USART_BaudRate = UART2_BAUD; /* */ +;;;607 USART_InitStructure.USART_WordLength = USART_WordLength_8b; +;;;608 USART_InitStructure.USART_StopBits = USART_StopBits_1; +;;;609 USART_InitStructure.USART_Parity = USART_Parity_No ; +;;;610 USART_InitStructure.USART_HardwareFlowControl = USART_HardwareFlowControl_None; +;;;611 USART_InitStructure.USART_Mode = USART_Mode_Tx | USART_Mode_Rx; /* ѡģʽ */ +;;;612 USART_Init(USART2, &USART_InitStructure); +;;;613 +;;;614 USART_ITConfig(USART2, USART_IT_RXNE, ENABLE); /* ʹܽж */ +;;;615 /* +;;;616 USART_ITConfig(USART1, USART_IT_TXE, ENABLE); +;;;617 ע: Ҫڴ˴򿪷ж +;;;618 жʹSendUart() +;;;619 */ +;;;620 USART_Cmd(USART2, ENABLE); /* ʹܴ */ +;;;621 +;;;622 /* CPUСȱݣúãֱSend1ֽڷͲȥ +;;;623 1ֽ޷ȷͳȥ */ +;;;624 USART_ClearFlag(USART2, USART_FLAG_TC); /* 巢ɱ־Transmission Complete flag */ +;;;625 #endif +;;;626 +;;;627 #if UART3_FIFO_EN == 1 /* 3 TX = PB10 RX = PB11 */ +;;;628 +;;;629 /* PB2Ϊл RS485оƬշ״̬ */ +;;;630 { +;;;631 RCC_APB2PeriphClockCmd(RCC_RS485_TXEN, ENABLE); +;;;632 +;;;633 GPIO_InitStructure.GPIO_Mode = GPIO_Mode_Out_PP; +;;;634 GPIO_InitStructure.GPIO_Speed = GPIO_Speed_50MHz; +;;;635 GPIO_InitStructure.GPIO_Pin = PIN_RS485_TXEN; +;;;636 GPIO_Init(PORT_RS485_TXEN, &GPIO_InitStructure); +;;;637 } +;;;638 +;;;639 /* 1 GPIOUARTʱ */ +;;;640 RCC_APB2PeriphClockCmd(RCC_APB2Periph_GPIOB | RCC_APB2Periph_AFIO, ENABLE); +;;;641 RCC_APB1PeriphClockCmd(RCC_APB1Periph_USART3, ENABLE); +;;;642 +;;;643 /* 2USART TxGPIOΪ츴ģʽ */ +;;;644 GPIO_InitStructure.GPIO_Pin = GPIO_Pin_10; +;;;645 GPIO_InitStructure.GPIO_Mode = GPIO_Mode_AF_PP; +;;;646 GPIO_InitStructure.GPIO_Speed = GPIO_Speed_50MHz; +;;;647 GPIO_Init(GPIOB, &GPIO_InitStructure); +;;;648 +;;;649 /* 3USART RxGPIOΪģʽ +;;;650 CPUλGPIOȱʡǸģʽ費DZ +;;;651 ǣһǽϱĶҷֹط޸ߵò +;;;652 */ +;;;653 GPIO_InitStructure.GPIO_Pin = GPIO_Pin_11; +;;;654 GPIO_InitStructure.GPIO_Mode = GPIO_Mode_IN_FLOATING; +;;;655 GPIO_Init(GPIOB, &GPIO_InitStructure); +;;;656 /* 3ѾˣⲽԲ +;;;657 GPIO_InitStructure.GPIO_Speed = GPIO_Speed_50MHz; +;;;658 */ +;;;659 GPIO_Init(GPIOB, &GPIO_InitStructure); +;;;660 +;;;661 /* 4 ôӲ */ +;;;662 USART_InitStructure.USART_BaudRate = UART3_BAUD; /* */ +;;;663 USART_InitStructure.USART_WordLength = USART_WordLength_8b; +;;;664 USART_InitStructure.USART_StopBits = USART_StopBits_1; +;;;665 USART_InitStructure.USART_Parity = USART_Parity_No ; +;;;666 USART_InitStructure.USART_HardwareFlowControl = USART_HardwareFlowControl_None; +;;;667 USART_InitStructure.USART_Mode = USART_Mode_Rx | USART_Mode_Tx; +;;;668 USART_Init(USART3, &USART_InitStructure); +;;;669 +;;;670 USART_ITConfig(USART3, USART_IT_RXNE, ENABLE); /* ʹܽж */ +;;;671 /* +;;;672 USART_ITConfig(USART1, USART_IT_TXE, ENABLE); +;;;673 ע: Ҫڴ˴򿪷ж +;;;674 жʹSendUart() +;;;675 */ +;;;676 USART_Cmd(USART3, ENABLE); /* ʹܴ */ +;;;677 +;;;678 /* CPUСȱݣúãֱSend1ֽڷͲȥ +;;;679 1ֽ޷ȷͳȥ */ +;;;680 USART_ClearFlag(USART3, USART_FLAG_TC); /* 巢ɱ־Transmission Complete flag */ +;;;681 #endif +;;;682 +;;;683 #if UART4_FIFO_EN == 1 /* 4 TX = PC10 RX = PC11 */ +;;;684 /* 1 GPIOUARTʱ */ +;;;685 RCC_APB2PeriphClockCmd(RCC_APB2Periph_GPIOC | RCC_APB2Periph_AFIO, ENABLE); +;;;686 RCC_APB1PeriphClockCmd(RCC_APB1Periph_UART4, ENABLE); +;;;687 +;;;688 /* 2USART TxGPIOΪ츴ģʽ */ +;;;689 GPIO_InitStructure.GPIO_Pin = GPIO_Pin_10; +;;;690 GPIO_InitStructure.GPIO_Mode = GPIO_Mode_AF_PP; +;;;691 GPIO_InitStructure.GPIO_Speed = GPIO_Speed_50MHz; +;;;692 GPIO_Init(GPIOC, &GPIO_InitStructure); +;;;693 +;;;694 /* 3USART RxGPIOΪģʽ +;;;695 CPUλGPIOȱʡǸģʽ費DZ +;;;696 ǣһǽϱĶҷֹط޸ߵò +;;;697 */ +;;;698 GPIO_InitStructure.GPIO_Pin = GPIO_Pin_11; +;;;699 GPIO_InitStructure.GPIO_Mode = GPIO_Mode_IN_FLOATING; +;;;700 GPIO_Init(GPIOC, &GPIO_InitStructure); +;;;701 +;;;702 /* 4 ôӲ */ +;;;703 USART_InitStructure.USART_BaudRate = UART4_BAUD; /* */ +;;;704 USART_InitStructure.USART_WordLength = USART_WordLength_8b; +;;;705 USART_InitStructure.USART_StopBits = USART_StopBits_1; +;;;706 USART_InitStructure.USART_Parity = USART_Parity_No ; +;;;707 USART_InitStructure.USART_HardwareFlowControl = USART_HardwareFlowControl_None; +;;;708 USART_InitStructure.USART_Mode = USART_Mode_Rx | USART_Mode_Tx; +;;;709 USART_Init(UART4, &USART_InitStructure); +;;;710 +;;;711 USART_ITConfig(UART4, USART_IT_RXNE, ENABLE); /* ʹܽж */ +;;;712 /* +;;;713 USART_ITConfig(USART1, USART_IT_TXE, ENABLE); +;;;714 ע: Ҫڴ˴򿪷ж +;;;715 жʹSendUart() +;;;716 */ +;;;717 USART_Cmd(UART4, ENABLE); /* ʹܴ */ +;;;718 +;;;719 /* CPUСȱݣúãֱSend1ֽڷͲȥ +;;;720 1ֽ޷ȷͳȥ */ +;;;721 USART_ClearFlag(UART4, USART_FLAG_TC); /* 巢ɱ־Transmission Complete flag */ +;;;722 #endif +;;;723 +;;;724 #if UART5_FIFO_EN == 1 /* 5 TX = PC12 RX = PD2 */ +;;;725 /* 1 GPIOUARTʱ */ +;;;726 RCC_APB2PeriphClockCmd(RCC_APB2Periph_GPIOC | RCC_APB2Periph_GPIOD | RCC_APB2Periph_AFIO, ENABLE); +;;;727 RCC_APB1PeriphClockCmd(RCC_APB1Periph_UART5, ENABLE); +;;;728 +;;;729 /* 2USART TxGPIOΪ츴ģʽ */ +;;;730 GPIO_InitStructure.GPIO_Pin = GPIO_Pin_12; +;;;731 GPIO_InitStructure.GPIO_Mode = GPIO_Mode_AF_PP; +;;;732 GPIO_InitStructure.GPIO_Speed = GPIO_Speed_50MHz; +;;;733 GPIO_Init(GPIOC, &GPIO_InitStructure); +;;;734 +;;;735 /* 3USART RxGPIOΪģʽ +;;;736 CPUλGPIOȱʡǸģʽ費DZ +;;;737 ǣһǽϱĶҷֹط޸ߵò +;;;738 */ +;;;739 GPIO_InitStructure.GPIO_Pin = GPIO_Pin_2; +;;;740 GPIO_InitStructure.GPIO_Mode = GPIO_Mode_IN_FLOATING; +;;;741 GPIO_Init(GPIOD, &GPIO_InitStructure); +;;;742 +;;;743 +;;;744 /* 4 ôӲ */ +;;;745 USART_InitStructure.USART_BaudRate = UART5_BAUD; /* */ +;;;746 USART_InitStructure.USART_WordLength = USART_WordLength_8b; +;;;747 USART_InitStructure.USART_StopBits = USART_StopBits_1; +;;;748 USART_InitStructure.USART_Parity = USART_Parity_No ; +;;;749 USART_InitStructure.USART_HardwareFlowControl = USART_HardwareFlowControl_None; +;;;750 USART_InitStructure.USART_Mode = USART_Mode_Rx | USART_Mode_Tx; +;;;751 USART_Init(UART5, &USART_InitStructure); +;;;752 +;;;753 USART_ITConfig(UART5, USART_IT_RXNE, ENABLE); /* ʹܽж */ +;;;754 /* +;;;755 USART_ITConfig(USART1, USART_IT_TXE, ENABLE); +;;;756 ע: Ҫڴ˴򿪷ж +;;;757 жʹSendUart() +;;;758 */ +;;;759 USART_Cmd(UART5, ENABLE); /* ʹܴ */ +;;;760 +;;;761 /* CPUСȱݣúãֱSend1ֽڷͲȥ +;;;762 1ֽ޷ȷͳȥ */ +;;;763 USART_ClearFlag(UART5, USART_FLAG_TC); /* 巢ɱ־Transmission Complete flag */ +;;;764 #endif +;;;765 } +00008a b006 ADD sp,sp,#0x18 +00008c bd10 POP {r4,pc} +;;;766 + ENDP + +00008e 0000 DCW 0x0000 + |L3.144| + DCD 0x40010800 + |L3.148| + DCD 0x40013800 + + AREA ||i.RS485_InitTXE||, CODE, READONLY, ALIGN=2 + + RS485_InitTXE PROC +;;;307 */ +;;;308 void RS485_InitTXE(void) +000000 b508 PUSH {r3,lr} +;;;309 { +;;;310 GPIO_InitTypeDef GPIO_InitStructure; +;;;311 +;;;312 RCC_APB2PeriphClockCmd(RCC_RS485_TXEN, ENABLE); /* GPIOʱ */ +000002 2101 MOVS r1,#1 +000004 2008 MOVS r0,#8 +000006 f7fffffe BL RCC_APB2PeriphClockCmd +;;;313 +;;;314 GPIO_InitStructure.GPIO_Speed = GPIO_Speed_50MHz; +00000a 2003 MOVS r0,#3 +00000c f88d0002 STRB r0,[sp,#2] +;;;315 GPIO_InitStructure.GPIO_Mode = GPIO_Mode_Out_PP; /* ģʽ */ +000010 2010 MOVS r0,#0x10 +000012 f88d0003 STRB r0,[sp,#3] +;;;316 GPIO_InitStructure.GPIO_Pin = PIN_RS485_TXEN; +000016 2004 MOVS r0,#4 +000018 f8ad0000 STRH r0,[sp,#0] +;;;317 GPIO_Init(PORT_RS485_TXEN, &GPIO_InitStructure); +00001c 4669 MOV r1,sp +00001e 4802 LDR r0,|L4.40| +000020 f7fffffe BL GPIO_Init +;;;318 } +000024 bd08 POP {r3,pc} +;;;319 + ENDP + +000026 0000 DCW 0x0000 + |L4.40| + DCD 0x40010c00 + + AREA ||i.RS485_ReciveNew||, CODE, READONLY, ALIGN=1 + + RS485_ReciveNew PROC +;;;407 extern void MODBUS_ReciveNew(uint8_t _byte); +;;;408 void RS485_ReciveNew(uint8_t _byte) +000000 4770 BX lr +;;;409 { +;;;410 //MODBUS_ReciveNew(_byte); +;;;411 } +;;;412 + ENDP + + + AREA ||i.RS485_SendBefor||, CODE, READONLY, ALIGN=2 + + RS485_SendBefor PROC +;;;350 */ +;;;351 void RS485_SendBefor(void) +000000 4901 LDR r1,|L6.8| +;;;352 { +;;;353 RS485_TX_EN(); /* лRS485շоƬΪģʽ */ +000002 2004 MOVS r0,#4 +000004 6008 STR r0,[r1,#0] +;;;354 } +000006 4770 BX lr +;;;355 + ENDP + + |L6.8| + DCD 0x40010c10 + + AREA ||i.RS485_SendBuf||, CODE, READONLY, ALIGN=1 + + RS485_SendBuf PROC +;;;378 */ +;;;379 void RS485_SendBuf(uint8_t *_ucaBuf, uint16_t _usLen) +000000 460a MOV r2,r1 +;;;380 { +;;;381 comSendBuf(COM3, _ucaBuf, _usLen); +000002 4601 MOV r1,r0 +000004 2002 MOVS r0,#2 +000006 f7ffbffe B.W comSendBuf +;;;382 } +;;;383 + ENDP + + + AREA ||i.RS485_SendOver||, CODE, READONLY, ALIGN=2 + + RS485_SendOver PROC +;;;364 */ +;;;365 void RS485_SendOver(void) +000000 4901 LDR r1,|L8.8| +;;;366 { +;;;367 RS485_RX_EN(); /* лRS485շоƬΪģʽ */ +000002 2004 MOVS r0,#4 +000004 6008 STR r0,[r1,#0] +;;;368 } +000006 4770 BX lr +;;;369 + ENDP + + |L8.8| + DCD 0x40010c14 + + AREA ||i.RS485_SendStr||, CODE, READONLY, ALIGN=1 + + RS485_SendStr PROC +;;;393 */ +;;;394 void RS485_SendStr(char *_pBuf) +000000 b510 PUSH {r4,lr} +;;;395 { +000002 4604 MOV r4,r0 +;;;396 RS485_SendBuf((uint8_t *)_pBuf, strlen(_pBuf)); +000004 4620 MOV r0,r4 +000006 f7fffffe BL strlen +00000a b281 UXTH r1,r0 +00000c 4620 MOV r0,r4 +00000e e8bd4010 POP {r4,lr} +000012 f7ffbffe B.W RS485_SendBuf +;;;397 } +;;;398 + ENDP + + + AREA ||i.USART1_IRQHandler||, CODE, READONLY, ALIGN=2 + + USART1_IRQHandler PROC +;;;1096 #if UART1_FIFO_EN == 1 +;;;1097 void USART1_IRQHandler(void) +000000 4801 LDR r0,|L10.8| +;;;1098 { +;;;1099 UartIRQ(&g_tUart1); +000002 f7ffbffe B.W UartIRQ +;;;1100 } +;;;1101 #endif + ENDP + +000006 0000 DCW 0x0000 + |L10.8| + DCD ||.bss||+0x20 + + AREA ||i.UartGetChar||, CODE, READONLY, ALIGN=1 + + UartGetChar PROC +;;;910 */ +;;;911 static uint8_t UartGetChar(UART_T *_pUart, uint8_t *_pByte) +000000 2201 MOVS r2,#1 +000002 f3828810 MSR PRIMASK,r2 +;;;912 { +;;;913 uint16_t usCount; +;;;914 +;;;915 /* usRxWrite жϺбдȡñʱٽ */ +;;;916 DISABLE_INT(); +;;;917 usCount = _pUart->usRxCount; +000006 8b42 LDRH r2,[r0,#0x1a] +;;;918 ENABLE_INT(); +000008 2300 MOVS r3,#0 +00000a f3838810 MSR PRIMASK,r3 +;;;919 +;;;920 /* дͬ򷵻0 */ +;;;921 //if (_pUart->usRxRead == usRxWrite) +;;;922 if (usCount == 0) /* Ѿû */ +00000e 2a00 CMP r2,#0 +000010 d017 BEQ |L11.66| +;;;923 { +;;;924 return 0; +;;;925 } +;;;926 else +;;;927 { +;;;928 *_pByte = _pUart->pRxBuf[_pUart->usRxRead]; /* ӴڽFIFOȡ1 */ +000012 8b03 LDRH r3,[r0,#0x18] +000014 6882 LDR r2,[r0,#8] +000016 5cd2 LDRB r2,[r2,r3] +000018 700a STRB r2,[r1,#0] +;;;929 +;;;930 /* дFIFO */ +;;;931 DISABLE_INT(); +00001a 2101 MOVS r1,#1 +00001c f3818810 MSR PRIMASK,r1 +;;;932 if (++_pUart->usRxRead >= _pUart->usRxBufSize) +000020 8b01 LDRH r1,[r0,#0x18] +000022 1c49 ADDS r1,r1,#1 +000024 b289 UXTH r1,r1 +000026 8301 STRH r1,[r0,#0x18] +000028 89c2 LDRH r2,[r0,#0xe] +00002a 4291 CMP r1,r2 +00002c d301 BCC |L11.50| +;;;933 { +;;;934 _pUart->usRxRead = 0; +00002e 2100 MOVS r1,#0 +000030 8301 STRH r1,[r0,#0x18] + |L11.50| +;;;935 } +;;;936 _pUart->usRxCount--; +000032 8b41 LDRH r1,[r0,#0x1a] +000034 1e49 SUBS r1,r1,#1 +000036 8341 STRH r1,[r0,#0x1a] +;;;937 ENABLE_INT(); +000038 2000 MOVS r0,#0 +00003a f3808810 MSR PRIMASK,r0 +;;;938 return 1; +00003e 2001 MOVS r0,#1 +;;;939 } +;;;940 } +000040 4770 BX lr + |L11.66| +000042 2000 MOVS r0,#0 ;924 +000044 4770 BX lr +;;;941 + ENDP + + + AREA ||i.UartIRQ||, CODE, READONLY, ALIGN=2 + + UartIRQ PROC +;;;956 */ +;;;957 static void UartIRQ(UART_T *_pUart) +000000 e92d41f0 PUSH {r4-r8,lr} +;;;958 { +000004 4604 MOV r4,r0 +;;;959 static UART_RX_STATE_E rx_state=RX_IDEL; +;;;960 +;;;961 /* ж */ +;;;962 if (USART_GetITStatus(_pUart->uart, USART_IT_RXNE) != RESET) +000006 f2405125 MOV r1,#0x525 +00000a 6820 LDR r0,[r4,#0] +00000c f7fffffe BL USART_GetITStatus +000010 2500 MOVS r5,#0 +000012 b300 CBZ r0,|L12.86| +;;;963 { +;;;964 /* ӴڽݼĴȡݴŵFIFO */ +;;;965 uint8_t ch; +;;;966 +;;;967 ch = USART_ReceiveData(_pUart->uart); +000014 6820 LDR r0,[r4,#0] +000016 f7fffffe BL USART_ReceiveData +00001a b2c0 UXTB r0,r0 +;;;968 +;;;969 //-------add by J.C---------------- +;;;970 switch(rx_state) +00001c 4b3a LDR r3,|L12.264| +;;;971 { +;;;972 case RX_IDEL: +;;;973 { +;;;974 if(ch=='[') +;;;975 { +;;;976 rx_state = RX_WORK; +;;;977 pt = 0; +;;;978 g_RxBuf[pt] = ch; +00001e 4e3b LDR r6,|L12.268| +000020 2701 MOVS r7,#1 ;970 +000022 7899 LDRB r1,[r3,#2] ;970 ; rx_state +000024 b111 CBZ r1,|L12.44| +000026 2901 CMP r1,#1 ;970 +000028 d115 BNE |L12.86| +00002a e005 B |L12.56| + |L12.44| +00002c 285b CMP r0,#0x5b ;974 +00002e d112 BNE |L12.86| +000030 709f STRB r7,[r3,#2] ;976 +000032 7030 STRB r0,[r6,#0] +;;;979 pt++; +000034 701f STRB r7,[r3,#0] +000036 e00e B |L12.86| + |L12.56| +;;;980 } +;;;981 break; +;;;982 } +;;;983 case RX_WORK: +;;;984 { +;;;985 if(ch=='[') +000038 285b CMP r0,#0x5b +00003a d004 BEQ |L12.70| +;;;986 { +;;;987 pt = 0; +;;;988 g_RxBuf[pt++] = ch; +;;;989 } +;;;990 else +;;;991 { +;;;992 if(pt >= 25) +00003c 7819 LDRB r1,[r3,#0] ; pt +00003e 2919 CMP r1,#0x19 +000040 d304 BCC |L12.76| +;;;993 { +;;;994 rx_state = RX_IDEL; +000042 709d STRB r5,[r3,#2] +000044 e007 B |L12.86| + |L12.70| +000046 701f STRB r7,[r3,#0] ;988 +000048 7030 STRB r0,[r6,#0] ;988 +00004a e004 B |L12.86| + |L12.76| +;;;995 } +;;;996 else if(ch==']') +00004c 285d CMP r0,#0x5d +00004e d020 BEQ |L12.146| +;;;997 { +;;;998 rx_state = RX_IDEL; +;;;999 g_RxBuf[pt++] = ch; +;;;1000 g_RxBuf[pt++] = 0; +;;;1001 g_ucRxRcvNewFlag = 1; +;;;1002 /* ص,֪ͨӦóյ,һǷ1Ϣһ */ +;;;1003 //if (_pUart->usRxWrite == _pUart->usRxRead) +;;;1004 //if (_pUart->usRxCount == 1) +;;;1005 //{ +;;;1006 // if (_pUart->ReciveNew) +;;;1007 // { +;;;1008 // _pUart->ReciveNew(ch); +;;;1009 // } +;;;1010 //} +;;;1011 } +;;;1012 else +;;;1013 { +;;;1014 g_RxBuf[pt++] = ch; +000050 1c4a ADDS r2,r1,#1 +000052 701a STRB r2,[r3,#0] +000054 5470 STRB r0,[r6,r1] + |L12.86| +;;;1015 } +;;;1016 } +;;;1017 break; +;;;1018 } +;;;1019 default: break; +;;;1020 } +;;;1021 +;;;1022 //-------add by J.C----------end--- +;;;1023 // if (++_pUart->usRxWrite >= _pUart->usRxBufSize) +;;;1024 // { +;;;1025 // _pUart->usRxWrite = 0; +;;;1026 // } +;;;1027 // if (_pUart->usRxCount < _pUart->usRxBufSize) +;;;1028 // { +;;;1029 // _pUart->usRxCount++; +;;;1030 // } +;;;1031 +;;;1032 } +;;;1033 +;;;1034 /* ͻж */ +;;;1035 if (USART_GetITStatus(_pUart->uart, USART_IT_TXE) != RESET) +000056 f2407727 MOV r7,#0x727 +00005a 4639 MOV r1,r7 +00005c 6820 LDR r0,[r4,#0] +00005e f7fffffe BL USART_GetITStatus +;;;1036 { +;;;1037 //if (_pUart->usTxRead == _pUart->usTxWrite) +;;;1038 if (_pUart->usTxCount == 0) +;;;1039 { +;;;1040 /* ͻȡʱ ֹͻж ע⣺ʱ1ݻδϣ*/ +;;;1041 USART_ITConfig(_pUart->uart, USART_IT_TXE, DISABLE); +;;;1042 +;;;1043 /* ʹݷж */ +;;;1044 USART_ITConfig(_pUart->uart, USART_IT_TC, ENABLE); +000062 f2406626 MOV r6,#0x626 +000066 b348 CBZ r0,|L12.188| +000068 8aa0 LDRH r0,[r4,#0x14] ;1038 +00006a b1d8 CBZ r0,|L12.164| +;;;1045 } +;;;1046 else +;;;1047 { +;;;1048 /* ӷFIFOȡ1ֽд봮ڷݼĴ */ +;;;1049 USART_SendData(_pUart->uart, _pUart->pTxBuf[_pUart->usTxRead]); +00006c 8a61 LDRH r1,[r4,#0x12] +00006e 6860 LDR r0,[r4,#4] +000070 5c41 LDRB r1,[r0,r1] +000072 6820 LDR r0,[r4,#0] +000074 f7fffffe BL USART_SendData +;;;1050 if (++_pUart->usTxRead >= _pUart->usTxBufSize) +000078 8a60 LDRH r0,[r4,#0x12] +00007a 1c40 ADDS r0,r0,#1 +00007c b280 UXTH r0,r0 +00007e 8260 STRH r0,[r4,#0x12] +000080 89a1 LDRH r1,[r4,#0xc] +000082 4288 CMP r0,r1 +000084 d300 BCC |L12.136| +;;;1051 { +;;;1052 _pUart->usTxRead = 0; +000086 8265 STRH r5,[r4,#0x12] + |L12.136| +;;;1053 } +;;;1054 _pUart->usTxCount--; +000088 8aa0 LDRH r0,[r4,#0x14] +00008a 1e40 SUBS r0,r0,#1 +00008c 82a0 STRH r0,[r4,#0x14] + |L12.142| +;;;1055 } +;;;1056 +;;;1057 } +;;;1058 /* bitλȫϵж */ +;;;1059 else if (USART_GetITStatus(_pUart->uart, USART_IT_TC) != RESET) +;;;1060 { +;;;1061 //if (_pUart->usTxRead == _pUart->usTxWrite) +;;;1062 if (_pUart->usTxCount == 0) +;;;1063 { +;;;1064 /* FIFOȫϣֹݷж */ +;;;1065 USART_ITConfig(_pUart->uart, USART_IT_TC, DISABLE); +;;;1066 +;;;1067 /* ص, һRS485ͨţRS485оƬΪģʽռ */ +;;;1068 if (_pUart->SendOver) +;;;1069 { +;;;1070 _pUart->SendOver(); +;;;1071 } +;;;1072 } +;;;1073 else +;;;1074 { +;;;1075 /* £˷֧ */ +;;;1076 +;;;1077 /* FIFOݻδϣӷFIFOȡ1д뷢ݼĴ */ +;;;1078 USART_SendData(_pUart->uart, _pUart->pTxBuf[_pUart->usTxRead]); +;;;1079 if (++_pUart->usTxRead >= _pUart->usTxBufSize) +;;;1080 { +;;;1081 _pUart->usTxRead = 0; +;;;1082 } +;;;1083 _pUart->usTxCount--; +;;;1084 } +;;;1085 } +;;;1086 } +00008e e8bd81f0 POP {r4-r8,pc} + |L12.146| +000092 709d STRB r5,[r3,#2] ;998 +000094 1c4a ADDS r2,r1,#1 ;999 +000096 b2d2 UXTB r2,r2 ;999 +000098 5470 STRB r0,[r6,r1] ;999 +00009a 1c50 ADDS r0,r2,#1 ;1000 +00009c 7018 STRB r0,[r3,#0] ;1000 +00009e 54b5 STRB r5,[r6,r2] ;1000 +0000a0 705f STRB r7,[r3,#1] ;1001 +0000a2 e7d8 B |L12.86| + |L12.164| +0000a4 2200 MOVS r2,#0 ;1041 +0000a6 4639 MOV r1,r7 ;1041 +0000a8 6820 LDR r0,[r4,#0] ;1041 +0000aa f7fffffe BL USART_ITConfig +0000ae 4631 MOV r1,r6 ;1044 +0000b0 6820 LDR r0,[r4,#0] ;1044 +0000b2 e8bd41f0 POP {r4-r8,lr} ;1044 +0000b6 2201 MOVS r2,#1 ;1044 +0000b8 f7ffbffe B.W USART_ITConfig + |L12.188| +0000bc 4631 MOV r1,r6 ;1059 +0000be 6820 LDR r0,[r4,#0] ;1059 +0000c0 f7fffffe BL USART_GetITStatus +0000c4 2800 CMP r0,#0 ;1059 +0000c6 d0e2 BEQ |L12.142| +0000c8 8aa0 LDRH r0,[r4,#0x14] ;1062 +0000ca b188 CBZ r0,|L12.240| +0000cc 8a61 LDRH r1,[r4,#0x12] ;1078 +0000ce 6860 LDR r0,[r4,#4] ;1078 +0000d0 5c41 LDRB r1,[r0,r1] ;1078 +0000d2 6820 LDR r0,[r4,#0] ;1078 +0000d4 f7fffffe BL USART_SendData +0000d8 8a60 LDRH r0,[r4,#0x12] ;1079 +0000da 1c40 ADDS r0,r0,#1 ;1079 +0000dc b280 UXTH r0,r0 ;1079 +0000de 8260 STRH r0,[r4,#0x12] ;1079 +0000e0 89a1 LDRH r1,[r4,#0xc] ;1079 +0000e2 4288 CMP r0,r1 ;1079 +0000e4 d300 BCC |L12.232| +0000e6 8265 STRH r5,[r4,#0x12] ;1081 + |L12.232| +0000e8 8aa0 LDRH r0,[r4,#0x14] ;1083 +0000ea 1e40 SUBS r0,r0,#1 ;1083 +0000ec 82a0 STRH r0,[r4,#0x14] ;1083 +0000ee e7ce B |L12.142| + |L12.240| +0000f0 2200 MOVS r2,#0 ;1065 +0000f2 4631 MOV r1,r6 ;1065 +0000f4 6820 LDR r0,[r4,#0] ;1065 +0000f6 f7fffffe BL USART_ITConfig +0000fa 6a20 LDR r0,[r4,#0x20] ;1068 +0000fc 2800 CMP r0,#0 ;1068 +0000fe d0c6 BEQ |L12.142| +000100 e8bd41f0 POP {r4-r8,lr} ;1070 +000104 4700 BX r0 ;1070 +;;;1087 + ENDP + +000106 0000 DCW 0x0000 + |L12.264| + DCD ||.data|| + |L12.268| + DCD ||.bss|| + + AREA ||i.UartSend||, CODE, READONLY, ALIGN=1 + + UartSend PROC +;;;838 */ +;;;839 static void UartSend(UART_T *_pUart, uint8_t *_ucaBuf, uint16_t _usLen) +000000 b478 PUSH {r3-r6} +;;;840 { +;;;841 uint16_t i; +;;;842 +;;;843 for (i = 0; i < _usLen; i++) +000002 2300 MOVS r3,#0 +000004 e024 B |L13.80| + |L13.6| +;;;844 { +;;;845 /* ͻѾˣȴ */ +;;;846 #if 0 +;;;847 /* +;;;848 ڵGPRSʱĴwhile ѭ +;;;849 ԭ ͵1ֽʱ _pUart->usTxWrite = 1_pUart->usTxRead = 0; +;;;850 while(1) ޷˳ +;;;851 */ +;;;852 while (1) +;;;853 { +;;;854 uint16_t usRead; +;;;855 +;;;856 DISABLE_INT(); +;;;857 usRead = _pUart->usTxRead; +;;;858 ENABLE_INT(); +;;;859 +;;;860 if (++usRead >= _pUart->usTxBufSize) +;;;861 { +;;;862 usRead = 0; +;;;863 } +;;;864 +;;;865 if (usRead != _pUart->usTxWrite) +;;;866 { +;;;867 break; +;;;868 } +;;;869 } +;;;870 #else +;;;871 /* _pUart->usTxBufSize == 1 ʱ, ĺ() */ +;;;872 while (1) +;;;873 { +;;;874 __IO uint16_t usCount; +;;;875 +;;;876 DISABLE_INT(); +;;;877 usCount = _pUart->usTxCount; +;;;878 ENABLE_INT(); +;;;879 +;;;880 if (usCount < _pUart->usTxBufSize) +;;;881 { +;;;882 break; +;;;883 } +;;;884 } +;;;885 #endif +;;;886 +;;;887 /* 뷢ͻ */ +;;;888 _pUart->pTxBuf[_pUart->usTxWrite] = _ucaBuf[i]; +;;;889 +;;;890 DISABLE_INT(); +;;;891 if (++_pUart->usTxWrite >= _pUart->usTxBufSize) +000006 8985 LDRH r5,[r0,#0xc] + |L13.8| +000008 2401 MOVS r4,#1 ;876 +00000a f3848810 MSR PRIMASK,r4 ;876 +00000e 8a84 LDRH r4,[r0,#0x14] ;877 +000010 9400 STR r4,[sp,#0] ;877 +000012 2400 MOVS r4,#0 ;878 +000014 f3848810 MSR PRIMASK,r4 ;878 +000018 f8bd4000 LDRH r4,[sp,#0] ;880 +00001c 42a5 CMP r5,r4 ;880 +00001e d9f3 BLS |L13.8| +000020 5ccc LDRB r4,[r1,r3] ;888 +000022 8a06 LDRH r6,[r0,#0x10] ;888 +000024 6845 LDR r5,[r0,#4] ;888 +000026 55ac STRB r4,[r5,r6] ;888 +000028 2401 MOVS r4,#1 ;890 +00002a f3848810 MSR PRIMASK,r4 ;890 +00002e 8a04 LDRH r4,[r0,#0x10] +000030 1c64 ADDS r4,r4,#1 +000032 b2a4 UXTH r4,r4 +000034 8204 STRH r4,[r0,#0x10] +000036 8985 LDRH r5,[r0,#0xc] +000038 42ac CMP r4,r5 +00003a d301 BCC |L13.64| +;;;892 { +;;;893 _pUart->usTxWrite = 0; +00003c 2400 MOVS r4,#0 +00003e 8204 STRH r4,[r0,#0x10] + |L13.64| +;;;894 } +;;;895 _pUart->usTxCount++; +000040 8a84 LDRH r4,[r0,#0x14] +000042 1c64 ADDS r4,r4,#1 +000044 8284 STRH r4,[r0,#0x14] +;;;896 ENABLE_INT(); +000046 2400 MOVS r4,#0 +000048 f3848810 MSR PRIMASK,r4 +00004c 1c5b ADDS r3,r3,#1 ;843 +00004e b29b UXTH r3,r3 ;843 + |L13.80| +000050 4293 CMP r3,r2 ;843 +000052 d3d8 BCC |L13.6| +;;;897 } +;;;898 +;;;899 USART_ITConfig(_pUart->uart, USART_IT_TXE, ENABLE); +000054 6800 LDR r0,[r0,#0] +000056 bc78 POP {r3-r6} +000058 2201 MOVS r2,#1 +00005a f2407127 MOV r1,#0x727 +00005e f7ffbffe B.W USART_ITConfig +;;;900 } +;;;901 + ENDP + + + AREA ||i.UartVarInit||, CODE, READONLY, ALIGN=2 + + UartVarInit PROC +;;;420 */ +;;;421 static void UartVarInit(void) +000000 480c LDR r0,|L14.52| +;;;422 { +;;;423 #if UART1_FIFO_EN == 1 +;;;424 g_tUart1.uart = USART1; /* STM32 豸 */ +000002 490b LDR r1,|L14.48| +000004 6001 STR r1,[r0,#0] ; g_tUart1 +;;;425 g_tUart1.pTxBuf = g_TxBuf1; /* ͻָ */ +000006 f1000128 ADD r1,r0,#0x28 +00000a 6041 STR r1,[r0,#4] ; g_tUart1 +;;;426 g_tUart1.pRxBuf = g_RxBuf1; /* ջָ */ +00000c f5006185 ADD r1,r0,#0x428 +000010 6081 STR r1,[r0,#8] ; g_tUart1 +;;;427 g_tUart1.usTxBufSize = UART1_TX_BUF_SIZE; /* ͻС */ +000012 f44f6180 MOV r1,#0x400 +000016 8181 STRH r1,[r0,#0xc] +;;;428 g_tUart1.usRxBufSize = UART1_RX_BUF_SIZE; /* ջС */ +000018 81c1 STRH r1,[r0,#0xe] +;;;429 g_tUart1.usTxWrite = 0; /* FIFOд */ +00001a 2100 MOVS r1,#0 +00001c 8201 STRH r1,[r0,#0x10] +;;;430 g_tUart1.usTxRead = 0; /* FIFO */ +00001e 8241 STRH r1,[r0,#0x12] +;;;431 g_tUart1.usRxWrite = 0; /* FIFOд */ +000020 82c1 STRH r1,[r0,#0x16] +;;;432 g_tUart1.usRxRead = 0; /* FIFO */ +000022 8301 STRH r1,[r0,#0x18] +;;;433 g_tUart1.usRxCount = 0; /* յݸ */ +000024 8341 STRH r1,[r0,#0x1a] +;;;434 g_tUart1.usTxCount = 0; /* ͵ݸ */ +000026 8281 STRH r1,[r0,#0x14] +;;;435 g_tUart1.SendBefor = 0; /* ǰĻص */ +000028 61c1 STR r1,[r0,#0x1c] ; g_tUart1 +;;;436 g_tUart1.SendOver = 0; /* ϺĻص */ +00002a 6201 STR r1,[r0,#0x20] ; g_tUart1 +;;;437 g_tUart1.ReciveNew = 0; /* յݺĻص */ +00002c 6241 STR r1,[r0,#0x24] ; g_tUart1 +;;;438 #endif +;;;439 +;;;440 #if UART2_FIFO_EN == 1 +;;;441 g_tUart2.uart = USART2; /* STM32 豸 */ +;;;442 g_tUart2.pTxBuf = g_TxBuf2; /* ͻָ */ +;;;443 g_tUart2.pRxBuf = g_RxBuf2; /* ջָ */ +;;;444 g_tUart2.usTxBufSize = UART2_TX_BUF_SIZE; /* ͻС */ +;;;445 g_tUart2.usRxBufSize = UART2_RX_BUF_SIZE; /* ջС */ +;;;446 g_tUart2.usTxWrite = 0; /* FIFOд */ +;;;447 g_tUart2.usTxRead = 0; /* FIFO */ +;;;448 g_tUart2.usRxWrite = 0; /* FIFOд */ +;;;449 g_tUart2.usRxRead = 0; /* FIFO */ +;;;450 g_tUart2.usRxCount = 0; /* յݸ */ +;;;451 g_tUart2.usTxCount = 0; /* ͵ݸ */ +;;;452 g_tUart2.SendBefor = 0; /* ǰĻص */ +;;;453 g_tUart2.SendOver = 0; /* ϺĻص */ +;;;454 g_tUart2.ReciveNew = 0; /* յݺĻص */ +;;;455 #endif +;;;456 +;;;457 #if UART3_FIFO_EN == 1 +;;;458 g_tUart3.uart = USART3; /* STM32 豸 */ +;;;459 g_tUart3.pTxBuf = g_TxBuf3; /* ͻָ */ +;;;460 g_tUart3.pRxBuf = g_RxBuf3; /* ջָ */ +;;;461 g_tUart3.usTxBufSize = UART3_TX_BUF_SIZE; /* ͻС */ +;;;462 g_tUart3.usRxBufSize = UART3_RX_BUF_SIZE; /* ջС */ +;;;463 g_tUart3.usTxWrite = 0; /* FIFOд */ +;;;464 g_tUart3.usTxRead = 0; /* FIFO */ +;;;465 g_tUart3.usRxWrite = 0; /* FIFOд */ +;;;466 g_tUart3.usRxRead = 0; /* FIFO */ +;;;467 g_tUart3.usRxCount = 0; /* յݸ */ +;;;468 g_tUart3.usTxCount = 0; /* ͵ݸ */ +;;;469 g_tUart3.SendBefor = RS485_SendBefor; /* ǰĻص */ +;;;470 g_tUart3.SendOver = RS485_SendOver; /* ϺĻص */ +;;;471 g_tUart3.ReciveNew = RS485_ReciveNew; /* յݺĻص */ +;;;472 #endif +;;;473 +;;;474 #if UART4_FIFO_EN == 1 +;;;475 g_tUart4.uart = UART4; /* STM32 豸 */ +;;;476 g_tUart4.pTxBuf = g_TxBuf4; /* ͻָ */ +;;;477 g_tUart4.pRxBuf = g_RxBuf4; /* ջָ */ +;;;478 g_tUart4.usTxBufSize = UART4_TX_BUF_SIZE; /* ͻС */ +;;;479 g_tUart4.usRxBufSize = UART4_RX_BUF_SIZE; /* ջС */ +;;;480 g_tUart4.usTxWrite = 0; /* FIFOд */ +;;;481 g_tUart4.usTxRead = 0; /* FIFO */ +;;;482 g_tUart4.usRxWrite = 0; /* FIFOд */ +;;;483 g_tUart4.usRxRead = 0; /* FIFO */ +;;;484 g_tUart4.usRxCount = 0; /* յݸ */ +;;;485 g_tUart4.usTxCount = 0; /* ͵ݸ */ +;;;486 g_tUart4.SendBefor = 0; /* ǰĻص */ +;;;487 g_tUart4.SendOver = 0; /* ϺĻص */ +;;;488 g_tUart4.ReciveNew = 0; /* յݺĻص */ +;;;489 #endif +;;;490 +;;;491 #if UART5_FIFO_EN == 1 +;;;492 g_tUart5.uart = UART5; /* STM32 豸 */ +;;;493 g_tUart5.pTxBuf = g_TxBuf5; /* ͻָ */ +;;;494 g_tUart5.pRxBuf = g_RxBuf5; /* ջָ */ +;;;495 g_tUart5.usTxBufSize = UART5_TX_BUF_SIZE; /* ͻС */ +;;;496 g_tUart5.usRxBufSize = UART5_RX_BUF_SIZE; /* ջС */ +;;;497 g_tUart5.usTxWrite = 0; /* FIFOд */ +;;;498 g_tUart5.usTxRead = 0; /* FIFO */ +;;;499 g_tUart5.usRxWrite = 0; /* FIFOд */ +;;;500 g_tUart5.usRxRead = 0; /* FIFO */ +;;;501 g_tUart5.usRxCount = 0; /* յݸ */ +;;;502 g_tUart5.usTxCount = 0; /* ͵ݸ */ +;;;503 g_tUart5.SendBefor = 0; /* ǰĻص */ +;;;504 g_tUart5.SendOver = 0; /* ϺĻص */ +;;;505 g_tUart5.ReciveNew = 0; /* յݺĻص */ +;;;506 #endif +;;;507 +;;;508 +;;;509 #if UART6_FIFO_EN == 1 +;;;510 g_tUart6.uart = USART6; /* STM32 豸 */ +;;;511 g_tUart6.pTxBuf = g_TxBuf6; /* ͻָ */ +;;;512 g_tUart6.pRxBuf = g_RxBuf6; /* ջָ */ +;;;513 g_tUart6.usTxBufSize = UART6_TX_BUF_SIZE; /* ͻС */ +;;;514 g_tUart6.usRxBufSize = UART6_RX_BUF_SIZE; /* ջС */ +;;;515 g_tUart6.usTxWrite = 0; /* FIFOд */ +;;;516 g_tUart6.usTxRead = 0; /* FIFO */ +;;;517 g_tUart6.usRxWrite = 0; /* FIFOд */ +;;;518 g_tUart6.usRxRead = 0; /* FIFO */ +;;;519 g_tUart6.usRxCount = 0; /* յݸ */ +;;;520 g_tUart6.usTxCount = 0; /* ͵ݸ */ +;;;521 g_tUart6.SendBefor = 0; /* ǰĻص */ +;;;522 g_tUart6.SendOver = 0; /* ϺĻص */ +;;;523 g_tUart6.ReciveNew = 0; /* յݺĻص */ +;;;524 #endif +;;;525 } +00002e 4770 BX lr +;;;526 + ENDP + + |L14.48| + DCD 0x40013800 + |L14.52| + DCD ||.bss||+0x20 + + AREA ||i.bsp_InitUart||, CODE, READONLY, ALIGN=1 + + bsp_InitUart PROC +;;;73 */ +;;;74 void bsp_InitUart(void) +000000 b510 PUSH {r4,lr} +;;;75 { +;;;76 UartVarInit(); /* ȳʼȫֱ,Ӳ */ +000002 f7fffffe BL UartVarInit +;;;77 +;;;78 InitHardUart(); /* ôڵӲ(ʵ) */ +000006 f7fffffe BL InitHardUart +;;;79 +;;;80 RS485_InitTXE(); /* RS485оƬķʹӲΪ */ +00000a f7fffffe BL RS485_InitTXE +;;;81 +;;;82 ConfigUartNVIC(); /* ôж */ +00000e e8bd4010 POP {r4,lr} +000012 f7ffbffe B.W ConfigUartNVIC +;;;83 } +;;;84 + ENDP + + + AREA ||i.bsp_Set485Baud||, CODE, READONLY, ALIGN=2 + + bsp_Set485Baud PROC +;;;327 */ +;;;328 void bsp_Set485Baud(uint32_t _baud) +000000 b51f PUSH {r0-r4,lr} +;;;329 { +;;;330 USART_InitTypeDef USART_InitStructure; +;;;331 +;;;332 /* 2 ôӲ */ +;;;333 USART_InitStructure.USART_BaudRate = _baud; /* */ +000002 9000 STR r0,[sp,#0] +;;;334 USART_InitStructure.USART_WordLength = USART_WordLength_8b; +000004 2000 MOVS r0,#0 +000006 f8ad0004 STRH r0,[sp,#4] +;;;335 USART_InitStructure.USART_StopBits = USART_StopBits_1; +00000a f8ad0006 STRH r0,[sp,#6] +;;;336 USART_InitStructure.USART_Parity = USART_Parity_No ; +00000e f8ad0008 STRH r0,[sp,#8] +;;;337 USART_InitStructure.USART_HardwareFlowControl = USART_HardwareFlowControl_None; +000012 f8ad000c STRH r0,[sp,#0xc] +;;;338 USART_InitStructure.USART_Mode = USART_Mode_Rx | USART_Mode_Tx; +000016 200c MOVS r0,#0xc +000018 f8ad000a STRH r0,[sp,#0xa] +;;;339 USART_Init(USART3, &USART_InitStructure); +00001c 4669 MOV r1,sp +00001e 4802 LDR r0,|L16.40| +000020 f7fffffe BL USART_Init +;;;340 } +000024 bd1f POP {r0-r4,pc} +;;;341 + ENDP + +000026 0000 DCW 0x0000 + |L16.40| + DCD 0x40004800 + + AREA ||i.bsp_SetUart1Baud||, CODE, READONLY, ALIGN=2 + + bsp_SetUart1Baud PROC +;;;259 */ +;;;260 void bsp_SetUart1Baud(uint32_t _baud) +000000 b51f PUSH {r0-r4,lr} +;;;261 { +;;;262 USART_InitTypeDef USART_InitStructure; +;;;263 +;;;264 /* 2 ôӲ */ +;;;265 USART_InitStructure.USART_BaudRate = _baud; /* */ +000002 9000 STR r0,[sp,#0] +;;;266 USART_InitStructure.USART_WordLength = USART_WordLength_8b; +000004 2000 MOVS r0,#0 +000006 f8ad0004 STRH r0,[sp,#4] +;;;267 USART_InitStructure.USART_StopBits = USART_StopBits_1; +00000a f8ad0006 STRH r0,[sp,#6] +;;;268 USART_InitStructure.USART_Parity = USART_Parity_No ; +00000e f8ad0008 STRH r0,[sp,#8] +;;;269 USART_InitStructure.USART_HardwareFlowControl = USART_HardwareFlowControl_None; +000012 f8ad000c STRH r0,[sp,#0xc] +;;;270 USART_InitStructure.USART_Mode = USART_Mode_Rx | USART_Mode_Tx; +000016 200c MOVS r0,#0xc +000018 f8ad000a STRH r0,[sp,#0xa] +;;;271 //USART_Init(USART2, &USART_InitStructure); +;;;272 USART_Init(USART1, &USART_InitStructure); // 2018.08.25 13:28 ޸ by J.C +00001c 4669 MOV r1,sp +00001e 4802 LDR r0,|L17.40| +000020 f7fffffe BL USART_Init +;;;273 } +000024 bd1f POP {r0-r4,pc} +;;;274 + ENDP + +000026 0000 DCW 0x0000 + |L17.40| + DCD 0x40013800 + + AREA ||i.bsp_SetUart2Baud||, CODE, READONLY, ALIGN=2 + + bsp_SetUart2Baud PROC +;;;282 */ +;;;283 void bsp_SetUart2Baud(uint32_t _baud) +000000 b51f PUSH {r0-r4,lr} +;;;284 { +;;;285 USART_InitTypeDef USART_InitStructure; +;;;286 +;;;287 /* 2 ôӲ */ +;;;288 USART_InitStructure.USART_BaudRate = _baud; /* */ +000002 9000 STR r0,[sp,#0] +;;;289 USART_InitStructure.USART_WordLength = USART_WordLength_8b; +000004 2000 MOVS r0,#0 +000006 f8ad0004 STRH r0,[sp,#4] +;;;290 USART_InitStructure.USART_StopBits = USART_StopBits_1; +00000a f8ad0006 STRH r0,[sp,#6] +;;;291 USART_InitStructure.USART_Parity = USART_Parity_No ; +00000e f8ad0008 STRH r0,[sp,#8] +;;;292 USART_InitStructure.USART_HardwareFlowControl = USART_HardwareFlowControl_None; +000012 f8ad000c STRH r0,[sp,#0xc] +;;;293 USART_InitStructure.USART_Mode = USART_Mode_Rx | USART_Mode_Tx; +000016 200c MOVS r0,#0xc +000018 f8ad000a STRH r0,[sp,#0xa] +;;;294 USART_Init(USART2, &USART_InitStructure); +00001c 4669 MOV r1,sp +00001e 4802 LDR r0,|L18.40| +000020 f7fffffe BL USART_Init +;;;295 } +000024 bd1f POP {r0-r4,pc} +;;;296 + ENDP + +000026 0000 DCW 0x0000 + |L18.40| + DCD 0x40004400 + + AREA ||i.comClearRxFifo||, CODE, READONLY, ALIGN=1 + + comClearRxFifo PROC +;;;236 */ +;;;237 void comClearRxFifo(COM_PORT_E _ucPort) +000000 b500 PUSH {lr} +;;;238 { +;;;239 UART_T *pUart; +;;;240 +;;;241 pUart = ComToUart(_ucPort); +000002 f7fffffe BL ComToUart +;;;242 if (pUart == 0) +000006 2800 CMP r0,#0 +000008 d003 BEQ |L19.18| +;;;243 { +;;;244 return; +;;;245 } +;;;246 +;;;247 pUart->usRxWrite = 0; +00000a 2100 MOVS r1,#0 +00000c 82c1 STRH r1,[r0,#0x16] +;;;248 pUart->usRxRead = 0; +00000e 8301 STRH r1,[r0,#0x18] +;;;249 pUart->usRxCount = 0; +000010 8341 STRH r1,[r0,#0x1a] + |L19.18| +;;;250 } +000012 bd00 POP {pc} +;;;251 + ENDP + + + AREA ||i.comClearTxFifo||, CODE, READONLY, ALIGN=1 + + comClearTxFifo PROC +;;;213 */ +;;;214 void comClearTxFifo(COM_PORT_E _ucPort) +000000 b500 PUSH {lr} +;;;215 { +;;;216 UART_T *pUart; +;;;217 +;;;218 pUart = ComToUart(_ucPort); +000002 f7fffffe BL ComToUart +;;;219 if (pUart == 0) +000006 2800 CMP r0,#0 +000008 d003 BEQ |L20.18| +;;;220 { +;;;221 return; +;;;222 } +;;;223 +;;;224 pUart->usTxWrite = 0; +00000a 2100 MOVS r1,#0 +00000c 8201 STRH r1,[r0,#0x10] +;;;225 pUart->usTxRead = 0; +00000e 8241 STRH r1,[r0,#0x12] +;;;226 pUart->usTxCount = 0; +000010 8281 STRH r1,[r0,#0x14] + |L20.18| +;;;227 } +000012 bd00 POP {pc} +;;;228 + ENDP + + + AREA ||i.comGetChar||, CODE, READONLY, ALIGN=1 + + comGetChar PROC +;;;192 */ +;;;193 uint8_t comGetChar(COM_PORT_E _ucPort, uint8_t *_pByte) +000000 b510 PUSH {r4,lr} +;;;194 { +;;;195 UART_T *pUart; +;;;196 +;;;197 pUart = ComToUart(_ucPort); +000002 f7fffffe BL ComToUart +;;;198 if (pUart == 0) +000006 b118 CBZ r0,|L21.16| +;;;199 { +;;;200 return 0; +;;;201 } +;;;202 +;;;203 return UartGetChar(pUart, _pByte); +000008 e8bd4010 POP {r4,lr} +00000c f7ffbffe B.W UartGetChar + |L21.16| +000010 2000 MOVS r0,#0 ;200 +;;;204 } +000012 bd10 POP {r4,pc} +;;;205 + ENDP + + + AREA ||i.comSendBuf||, CODE, READONLY, ALIGN=1 + + comSendBuf PROC +;;;151 */ +;;;152 void comSendBuf(COM_PORT_E _ucPort, uint8_t *_ucaBuf, uint16_t _usLen) +000000 b570 PUSH {r4-r6,lr} +;;;153 { +000002 460d MOV r5,r1 +000004 4616 MOV r6,r2 +;;;154 UART_T *pUart; +;;;155 +;;;156 pUart = ComToUart(_ucPort); +000006 f7fffffe BL ComToUart +00000a 4604 MOV r4,r0 +;;;157 if (pUart == 0) +00000c 2c00 CMP r4,#0 +00000e d009 BEQ |L22.36| +;;;158 { +;;;159 return; +;;;160 } +;;;161 +;;;162 if (pUart->SendBefor != 0) +000010 69e0 LDR r0,[r4,#0x1c] +000012 b100 CBZ r0,|L22.22| +;;;163 { +;;;164 pUart->SendBefor(); /* RS485ͨţнRS485Ϊģʽ */ +000014 4780 BLX r0 + |L22.22| +;;;165 } +;;;166 +;;;167 UartSend(pUart, _ucaBuf, _usLen); +000016 4632 MOV r2,r6 +000018 4629 MOV r1,r5 +00001a 4620 MOV r0,r4 +00001c e8bd4070 POP {r4-r6,lr} +000020 f7ffbffe B.W UartSend + |L22.36| +;;;168 } +000024 bd70 POP {r4-r6,pc} +;;;169 + ENDP + + + AREA ||i.comSendChar||, CODE, READONLY, ALIGN=1 + + comSendChar PROC +;;;178 */ +;;;179 void comSendChar(COM_PORT_E _ucPort, uint8_t _ucByte) +000000 b513 PUSH {r0,r1,r4,lr} +;;;180 { +;;;181 comSendBuf(_ucPort, &_ucByte, 1); +000002 2201 MOVS r2,#1 +000004 a901 ADD r1,sp,#4 +000006 f7fffffe BL comSendBuf +;;;182 } +00000a bd1c POP {r2-r4,pc} +;;;183 + ENDP + + + AREA ||i.fgetc||, CODE, READONLY, ALIGN=1 + + fgetc PROC +;;;1171 */ +;;;1172 int fgetc(FILE *f) +000000 b508 PUSH {r3,lr} + |L24.2| +;;;1173 { +;;;1174 +;;;1175 #if 1 /* ӴڽFIFOȡ1, ֻȡݲŷ */ +;;;1176 uint8_t ucData; +;;;1177 +;;;1178 while(comGetChar(COM1, &ucData) == 0); +000002 4669 MOV r1,sp +000004 2000 MOVS r0,#0 +000006 f7fffffe BL comGetChar +00000a 2800 CMP r0,#0 +00000c d0f9 BEQ |L24.2| +;;;1179 +;;;1180 return ucData; +00000e f89d0000 LDRB r0,[sp,#0] +;;;1181 #else +;;;1182 /* ȴ1 */ +;;;1183 while (USART_GetFlagStatus(USART1, USART_FLAG_RXNE) == RESET); +;;;1184 +;;;1185 return (int)USART_ReceiveData(USART1); +;;;1186 #endif +;;;1187 } +000012 bd08 POP {r3,pc} +;;;1188 + ENDP + + + AREA ||i.fputc||, CODE, READONLY, ALIGN=1 + + fputc PROC +;;;1145 */ +;;;1146 int fputc(int ch, FILE *f) +000000 b510 PUSH {r4,lr} +;;;1147 { +000002 4604 MOV r4,r0 +;;;1148 #if 1 /* ҪprintfַͨжFIFOͳȥprintf */ +;;;1149 comSendChar(COM1, ch); +000004 b2e1 UXTB r1,r4 +000006 2000 MOVS r0,#0 +000008 f7fffffe BL comSendChar +;;;1150 +;;;1151 return ch; +00000c 4620 MOV r0,r4 +;;;1152 #else /* ʽÿַ,ȴݷ */ +;;;1153 /* дһֽڵUSART1 */ +;;;1154 USART_SendData(USART1, (uint8_t) ch); +;;;1155 +;;;1156 /* ȴͽ */ +;;;1157 while (USART_GetFlagStatus(USART1, USART_FLAG_TC) == RESET) +;;;1158 {} +;;;1159 +;;;1160 return ch; +;;;1161 #endif +;;;1162 } +00000e bd10 POP {r4,pc} +;;;1163 + ENDP + + + AREA ||.bss||, DATA, NOINIT, ALIGN=2 + + g_RxBuf + % 32 + g_tUart1 + % 40 + g_TxBuf1 + % 1024 + g_RxBuf1 + % 1024 + + AREA ||.data||, DATA, ALIGN=0 + + ||pt|| +000000 00 DCB 0x00 + g_ucRxRcvNewFlag +000001 00 DCB 0x00 + rx_state +000002 00 DCB 0x00 + +;*** Start embedded assembler *** + +#line 1 "..\\..\\User\\bsp\\src\\bsp_uart_fifo.c" + AREA ||.rev16_text||, CODE + THUMB + EXPORT |__asm___15_bsp_uart_fifo_c_pt____REV16| +#line 114 "..\\..\\Libraries\\CMSIS\\Include\\core_cmInstr.h" +|__asm___15_bsp_uart_fifo_c_pt____REV16| PROC +#line 115 + + rev16 r0, r0 + bx lr + ENDP + AREA ||.revsh_text||, CODE + THUMB + EXPORT |__asm___15_bsp_uart_fifo_c_pt____REVSH| +#line 128 +|__asm___15_bsp_uart_fifo_c_pt____REVSH| PROC +#line 129 + + revsh r0, r0 + bx lr + ENDP + +;*** End embedded assembler *** diff --git a/Project/MDK-ARM/Flash/List/bsp_usart_dma.txt b/Project/MDK-ARM/Flash/List/bsp_usart_dma.txt new file mode 100644 index 0000000..20771a6 --- /dev/null +++ b/Project/MDK-ARM/Flash/List/bsp_usart_dma.txt @@ -0,0 +1,555 @@ +; generated by Component: ARM Compiler 5.06 update 7 (build 960) Tool: ArmCC [4d365d] +; commandline ArmCC [--list --split_sections --debug -c --asm --interleave -o.\flash\obj\bsp_usart_dma.o --asm_dir=.\Flash\List\ --list_dir=.\Flash\List\ --depend=.\flash\obj\bsp_usart_dma.d --cpu=Cortex-M3 --apcs=interwork -O0 --diag_suppress=9931,870 -I..\..\Libraries\CMSIS\Device\ST\STM32F10x\Include -I..\..\Libraries\STM32F10x_StdPeriph_Driver\inc -I..\..\Libraries\STM32_USB-FS-Device_Driver\inc -I..\..\Libraries\CMSIS\Include -I..\..\User\bsp -I..\..\User\bsp\inc -I..\..\User\app\inc -I..\..\User -IC:\Users\w1619\AppData\Local\Arm\Packs\Keil\STM32F1xx_DFP\2.4.1\Device\Include -D__MICROLIB -D__UVISION_VERSION=538 -DSTM32F10X_HD -DUSE_STDPERIPH_DRIVER -DSTM32F10X_HD --omf_browse=.\flash\obj\bsp_usart_dma.crf ..\..\User\bsp\src\bsp_usart_dma.c] + THUMB + + AREA ||i.USART1_IRQHandler||, CODE, READONLY, ALIGN=2 + + USART1_IRQHandler PROC +;;;194 */ +;;;195 void DEBUG_USART_IRQHandler(void) +000000 b510 PUSH {r4,lr} +;;;196 { +;;;197 uint16_t t; +;;;198 if (USART_GetITStatus(DEBUG_USARTx, USART_IT_IDLE) == SET) // 检查中断是否发生 +000002 f2404124 MOV r1,#0x424 +000006 4817 LDR r0,|L1.100| +000008 f7fffffe BL USART_GetITStatus +00000c 2801 CMP r0,#1 +00000e d127 BNE |L1.96| +;;;199 { +;;;200 DMA_Cmd(USART_RX_DMA_CHANNEL, DISABLE); // 关闭DMA传输 +000010 2100 MOVS r1,#0 +000012 4815 LDR r0,|L1.104| +000014 f7fffffe BL DMA_Cmd +;;;201 +;;;202 t = DMA_GetCurrDataCounter(USART_RX_DMA_CHANNEL); // 获取剩余的数据数量 +000018 4813 LDR r0,|L1.104| +00001a f7fffffe BL DMA_GetCurrDataCounter +00001e 4604 MOV r4,r0 +;;;203 memset(g_RxBuf, 0, sizeof g_RxBuf); +000020 2140 MOVS r1,#0x40 +000022 4812 LDR r0,|L1.108| +000024 f7fffffe BL __aeabi_memclr +;;;204 memcpy(g_RxBuf, ReceiveBuff, RECEIVEBUFF_SIZE - t); +000028 f1c40240 RSB r2,r4,#0x40 +00002c 4910 LDR r1,|L1.112| +00002e 480f LDR r0,|L1.108| +000030 f7fffffe BL __aeabi_memcpy +;;;205 memset(ReceiveBuff, 0, sizeof ReceiveBuff); +000034 2140 MOVS r1,#0x40 +000036 480e LDR r0,|L1.112| +000038 f7fffffe BL __aeabi_memclr +;;;206 g_ucRxRcvNewFlag = 1; +00003c 2001 MOVS r0,#1 +00003e 490d LDR r1,|L1.116| +000040 7008 STRB r0,[r1,#0] +;;;207 +;;;208 DMA_SetCurrDataCounter(USART_RX_DMA_CHANNEL, RECEIVEBUFF_SIZE); // 重新设置传输的数据数量 +000042 2140 MOVS r1,#0x40 +000044 4808 LDR r0,|L1.104| +000046 f7fffffe BL DMA_SetCurrDataCounter +;;;209 DMA_Cmd(USART_RX_DMA_CHANNEL, ENABLE); // 开启DMA传输 +00004a 2101 MOVS r1,#1 +00004c 4806 LDR r0,|L1.104| +00004e f7fffffe BL DMA_Cmd +;;;210 +;;;211 USART_ReceiveData(DEBUG_USARTx); // 读取一次数据，不然会一直进中断 +000052 4804 LDR r0,|L1.100| +000054 f7fffffe BL USART_ReceiveData +;;;212 USART_ClearFlag(DEBUG_USARTx, USART_FLAG_IDLE); // 清除串口空闲中断标志位 +000058 2110 MOVS r1,#0x10 +00005a 4802 LDR r0,|L1.100| +00005c f7fffffe BL USART_ClearFlag + |L1.96| +;;;213 } +;;;214 } +000060 bd10 POP {r4,pc} + ENDP + +000062 0000 DCW 0x0000 + |L1.100| + DCD 0x40013800 + |L1.104| + DCD 0x40020058 + |L1.108| + DCD g_RxBuf + |L1.112| + DCD ReceiveBuff + |L1.116| + DCD g_ucRxRcvNewFlag + + AREA ||i.USART_Config||, CODE, READONLY, ALIGN=2 + + USART_Config PROC +;;;13 */ +;;;14 void USART_Config(void) +000000 b500 PUSH {lr} +;;;15 { +000002 b087 SUB sp,sp,#0x1c +;;;16 GPIO_InitTypeDef GPIO_InitStructure; +;;;17 USART_InitTypeDef USART_InitStructure; +;;;18 NVIC_InitTypeDef NVIC_InitStruct; +;;;19 // 打开串口GPIO的时钟 +;;;20 DEBUG_USART_GPIO_APBxClkCmd(DEBUG_USART_GPIO_CLK, ENABLE); +000004 2101 MOVS r1,#1 +000006 2004 MOVS r0,#4 +000008 f7fffffe BL RCC_APB2PeriphClockCmd +;;;21 +;;;22 // 打开串口外设的时钟 +;;;23 DEBUG_USART_APBxClkCmd(DEBUG_USART_CLK, ENABLE); +00000c 2101 MOVS r1,#1 +00000e 0388 LSLS r0,r1,#14 +000010 f7fffffe BL RCC_APB2PeriphClockCmd +;;;24 +;;;25 NVIC_PriorityGroupConfig(NVIC_PriorityGroup_2); +000014 f44f60a0 MOV r0,#0x500 +000018 f7fffffe BL NVIC_PriorityGroupConfig +;;;26 NVIC_InitStruct.NVIC_IRQChannel = DEBUG_USART_IRQ; +00001c 2025 MOVS r0,#0x25 +00001e f88d0004 STRB r0,[sp,#4] +;;;27 NVIC_InitStruct.NVIC_IRQChannelCmd = ENABLE; +000022 2001 MOVS r0,#1 +000024 f88d0007 STRB r0,[sp,#7] +;;;28 NVIC_InitStruct.NVIC_IRQChannelPreemptionPriority = 1; +000028 f88d0005 STRB r0,[sp,#5] +;;;29 NVIC_InitStruct.NVIC_IRQChannelSubPriority = 3; +00002c 2003 MOVS r0,#3 +00002e f88d0006 STRB r0,[sp,#6] +;;;30 NVIC_Init(&NVIC_InitStruct); +000032 a801 ADD r0,sp,#4 +000034 f7fffffe BL NVIC_Init +;;;31 +;;;32 // 将USART Tx的GPIO配置为推挽复用模式 +;;;33 GPIO_InitStructure.GPIO_Pin = DEBUG_USART_TX_GPIO_PIN; +000038 f44f7000 MOV r0,#0x200 +00003c f8ad0018 STRH r0,[sp,#0x18] +;;;34 GPIO_InitStructure.GPIO_Mode = GPIO_Mode_AF_PP; +000040 2018 MOVS r0,#0x18 +000042 f88d001b STRB r0,[sp,#0x1b] +;;;35 GPIO_InitStructure.GPIO_Speed = GPIO_Speed_50MHz; +000046 2003 MOVS r0,#3 +000048 f88d001a STRB r0,[sp,#0x1a] +;;;36 GPIO_Init(DEBUG_USART_TX_GPIO_PORT, &GPIO_InitStructure); +00004c a906 ADD r1,sp,#0x18 +00004e 4816 LDR r0,|L2.168| +000050 f7fffffe BL GPIO_Init +;;;37 +;;;38 // 将USART Rx的GPIO配置为浮空输入模式 +;;;39 GPIO_InitStructure.GPIO_Pin = DEBUG_USART_RX_GPIO_PIN; +000054 f44f6080 MOV r0,#0x400 +000058 f8ad0018 STRH r0,[sp,#0x18] +;;;40 GPIO_InitStructure.GPIO_Mode = GPIO_Mode_IN_FLOATING; +00005c 2004 MOVS r0,#4 +00005e f88d001b STRB r0,[sp,#0x1b] +;;;41 GPIO_Init(DEBUG_USART_RX_GPIO_PORT, &GPIO_InitStructure); +000062 a906 ADD r1,sp,#0x18 +000064 4810 LDR r0,|L2.168| +000066 f7fffffe BL GPIO_Init +;;;42 +;;;43 // 配置串口的工作参数 +;;;44 // 配置波特率 +;;;45 USART_InitStructure.USART_BaudRate = DEBUG_USART_BAUDRATE; +00006a f44f30e1 MOV r0,#0x1c200 +00006e 9002 STR r0,[sp,#8] +;;;46 // 配置 针数据字长 +;;;47 USART_InitStructure.USART_WordLength = USART_WordLength_8b; +000070 2000 MOVS r0,#0 +000072 f8ad000c STRH r0,[sp,#0xc] +;;;48 // 配置停止位 +;;;49 USART_InitStructure.USART_StopBits = USART_StopBits_1; +000076 f8ad000e STRH r0,[sp,#0xe] +;;;50 // 配置校验位 +;;;51 USART_InitStructure.USART_Parity = USART_Parity_No; +00007a f8ad0010 STRH r0,[sp,#0x10] +;;;52 // 配置硬件流控制 +;;;53 USART_InitStructure.USART_HardwareFlowControl = USART_HardwareFlowControl_None; +00007e f8ad0014 STRH r0,[sp,#0x14] +;;;54 // 配置工作模式，收发一起 +;;;55 USART_InitStructure.USART_Mode = USART_Mode_Rx | USART_Mode_Tx; +000082 200c MOVS r0,#0xc +000084 f8ad0012 STRH r0,[sp,#0x12] +;;;56 // 完成串口的初始化配置 +;;;57 USART_Init(DEBUG_USARTx, &USART_InitStructure); +000088 a902 ADD r1,sp,#8 +00008a 4808 LDR r0,|L2.172| +00008c f7fffffe BL USART_Init +;;;58 // 使能空闲中断 +;;;59 USART_ITConfig(DEBUG_USARTx, USART_IT_IDLE, ENABLE); +000090 2201 MOVS r2,#1 +000092 f2404124 MOV r1,#0x424 +000096 4805 LDR r0,|L2.172| +000098 f7fffffe BL USART_ITConfig +;;;60 // 使能串口 +;;;61 USART_Cmd(DEBUG_USARTx, ENABLE); +00009c 2101 MOVS r1,#1 +00009e 4803 LDR r0,|L2.172| +0000a0 f7fffffe BL USART_Cmd +;;;62 } +0000a4 b007 ADD sp,sp,#0x1c +0000a6 bd00 POP {pc} +;;;63 + ENDP + + |L2.168| + DCD 0x40010800 + |L2.172| + DCD 0x40013800 + + AREA ||i.USARTx_DMA_Config||, CODE, READONLY, ALIGN=2 + + USARTx_DMA_Config PROC +;;;154 */ +;;;155 void USARTx_DMA_Config(void) +000000 b500 PUSH {lr} +;;;156 { +000002 b08b SUB sp,sp,#0x2c +;;;157 DMA_InitTypeDef DMA_InitStructure; +;;;158 // 开启DMA时钟 +;;;159 RCC_AHBPeriphClockCmd(RCC_AHBPeriph_DMA1, ENABLE); +000004 2101 MOVS r1,#1 +000006 4608 MOV r0,r1 +000008 f7fffffe BL RCC_AHBPeriphClockCmd +;;;160 +;;;161 // 设置DMA源地址：串口数据寄存器地址*/ +;;;162 DMA_InitStructure.DMA_PeripheralBaseAddr = USART_DR_ADDRESS; +00000c 480f LDR r0,|L3.76| +00000e 9000 STR r0,[sp,#0] +;;;163 // 内存地址(要传输的变量的指针) +;;;164 DMA_InitStructure.DMA_MemoryBaseAddr = (u32)ReceiveBuff; +000010 480f LDR r0,|L3.80| +000012 9001 STR r0,[sp,#4] +;;;165 // 方向：从外设到内存 +;;;166 DMA_InitStructure.DMA_DIR = DMA_DIR_PeripheralSRC; +000014 2000 MOVS r0,#0 +000016 9002 STR r0,[sp,#8] +;;;167 // 传输大小 +;;;168 DMA_InitStructure.DMA_BufferSize = RECEIVEBUFF_SIZE; +000018 2040 MOVS r0,#0x40 +00001a 9003 STR r0,[sp,#0xc] +;;;169 // 外设地址不增 +;;;170 DMA_InitStructure.DMA_PeripheralInc = DMA_PeripheralInc_Disable; +00001c 2000 MOVS r0,#0 +00001e 9004 STR r0,[sp,#0x10] +;;;171 // 内存地址自增 +;;;172 DMA_InitStructure.DMA_MemoryInc = DMA_MemoryInc_Enable; +000020 2080 MOVS r0,#0x80 +000022 9005 STR r0,[sp,#0x14] +;;;173 // 外设数据单位 +;;;174 DMA_InitStructure.DMA_PeripheralDataSize = DMA_PeripheralDataSize_Byte; +000024 2000 MOVS r0,#0 +000026 9006 STR r0,[sp,#0x18] +;;;175 // 内存数据单位 +;;;176 DMA_InitStructure.DMA_MemoryDataSize = DMA_MemoryDataSize_Byte; +000028 9007 STR r0,[sp,#0x1c] +;;;177 // DMA模式，一次或者循环模式 +;;;178 // DMA_InitStructure.DMA_Mode = DMA_Mode_Normal ; +;;;179 DMA_InitStructure.DMA_Mode = DMA_Mode_Circular; +00002a 2020 MOVS r0,#0x20 +00002c 9008 STR r0,[sp,#0x20] +;;;180 // 优先级：中 +;;;181 DMA_InitStructure.DMA_Priority = DMA_Priority_Medium; +00002e 01c0 LSLS r0,r0,#7 +000030 9009 STR r0,[sp,#0x24] +;;;182 // 禁止内存到内存的传输 +;;;183 DMA_InitStructure.DMA_M2M = DMA_M2M_Disable; +000032 2000 MOVS r0,#0 +000034 900a STR r0,[sp,#0x28] +;;;184 // 配置DMA通道 +;;;185 DMA_Init(USART_RX_DMA_CHANNEL, &DMA_InitStructure); +000036 4669 MOV r1,sp +000038 4806 LDR r0,|L3.84| +00003a f7fffffe BL DMA_Init +;;;186 // 使能DMA +;;;187 DMA_Cmd(USART_RX_DMA_CHANNEL, ENABLE); +00003e 2101 MOVS r1,#1 +000040 4804 LDR r0,|L3.84| +000042 f7fffffe BL DMA_Cmd +;;;188 } +000046 b00b ADD sp,sp,#0x2c +000048 bd00 POP {pc} +;;;189 + ENDP + +00004a 0000 DCW 0x0000 + |L3.76| + DCD 0x40013804 + |L3.80| + DCD ReceiveBuff + |L3.84| + DCD 0x40020058 + + AREA ||i.Usart_SendArray||, CODE, READONLY, ALIGN=1 + + Usart_SendArray PROC +;;;75 /****************** 发送8位的数组 ************************/ +;;;76 void Usart_SendArray(USART_TypeDef *pUSARTx, uint8_t *array, uint16_t num) +000000 e92d41f0 PUSH {r4-r8,lr} +;;;77 { +000004 4607 MOV r7,r0 +000006 460d MOV r5,r1 +000008 4616 MOV r6,r2 +;;;78 uint8_t i; +;;;79 +;;;80 for (i = 0; i < num; i++) +00000a 2400 MOVS r4,#0 +00000c e005 B |L4.26| + |L4.14| +;;;81 { +;;;82 /* 发送一个字节数据到USART */ +;;;83 Usart_SendByte(pUSARTx, array[i]); +00000e 5d29 LDRB r1,[r5,r4] +000010 4638 MOV r0,r7 +000012 f7fffffe BL Usart_SendByte +000016 1c60 ADDS r0,r4,#1 ;80 +000018 b2c4 UXTB r4,r0 ;80 + |L4.26| +00001a 42b4 CMP r4,r6 ;80 +00001c dbf7 BLT |L4.14| +;;;84 } +;;;85 /* 等待发送完成 */ +;;;86 while (USART_GetFlagStatus(pUSARTx, USART_FLAG_TC) == RESET) +00001e bf00 NOP + |L4.32| +000020 2140 MOVS r1,#0x40 +000022 4638 MOV r0,r7 +000024 f7fffffe BL USART_GetFlagStatus +000028 2800 CMP r0,#0 +00002a d0f9 BEQ |L4.32| +;;;87 ; +;;;88 } +00002c e8bd81f0 POP {r4-r8,pc} +;;;89 + ENDP + + + AREA ||i.Usart_SendByte||, CODE, READONLY, ALIGN=1 + + Usart_SendByte PROC +;;;64 /***************** 发送一个字节 **********************/ +;;;65 void Usart_SendByte(USART_TypeDef *pUSARTx, uint8_t ch) +000000 b570 PUSH {r4-r6,lr} +;;;66 { +000002 4604 MOV r4,r0 +000004 460d MOV r5,r1 +;;;67 /* 发送一个字节数据到USART */ +;;;68 USART_SendData(pUSARTx, ch); +000006 4629 MOV r1,r5 +000008 4620 MOV r0,r4 +00000a f7fffffe BL USART_SendData +;;;69 +;;;70 /* 等待发送数据寄存器为空 */ +;;;71 while (USART_GetFlagStatus(pUSARTx, USART_FLAG_TXE) == RESET) +00000e bf00 NOP + |L5.16| +000010 2180 MOVS r1,#0x80 +000012 4620 MOV r0,r4 +000014 f7fffffe BL USART_GetFlagStatus +000018 2800 CMP r0,#0 +00001a d0f9 BEQ |L5.16| +;;;72 ; +;;;73 } +00001c bd70 POP {r4-r6,pc} +;;;74 + ENDP + + + AREA ||i.Usart_SendHalfWord||, CODE, READONLY, ALIGN=1 + + Usart_SendHalfWord PROC +;;;106 /***************** 发送一个16位数 **********************/ +;;;107 void Usart_SendHalfWord(USART_TypeDef *pUSARTx, uint16_t ch) +000000 e92d41f0 PUSH {r4-r8,lr} +;;;108 { +000004 4605 MOV r5,r0 +000006 460c MOV r4,r1 +;;;109 uint8_t temp_h, temp_l; +;;;110 +;;;111 /* 取出高八位 */ +;;;112 temp_h = (ch & 0XFF00) >> 8; +000008 0a26 LSRS r6,r4,#8 +;;;113 /* 取出低八位 */ +;;;114 temp_l = ch & 0XFF; +00000a b2e7 UXTB r7,r4 +;;;115 +;;;116 /* 发送高八位 */ +;;;117 USART_SendData(pUSARTx, temp_h); +00000c 4631 MOV r1,r6 +00000e 4628 MOV r0,r5 +000010 f7fffffe BL USART_SendData +;;;118 while (USART_GetFlagStatus(pUSARTx, USART_FLAG_TXE) == RESET) +000014 bf00 NOP + |L6.22| +000016 2180 MOVS r1,#0x80 +000018 4628 MOV r0,r5 +00001a f7fffffe BL USART_GetFlagStatus +00001e 2800 CMP r0,#0 +000020 d0f9 BEQ |L6.22| +;;;119 ; +;;;120 +;;;121 /* 发送低八位 */ +;;;122 USART_SendData(pUSARTx, temp_l); +000022 4639 MOV r1,r7 +000024 4628 MOV r0,r5 +000026 f7fffffe BL USART_SendData +;;;123 while (USART_GetFlagStatus(pUSARTx, USART_FLAG_TXE) == RESET) +00002a bf00 NOP + |L6.44| +00002c 2180 MOVS r1,#0x80 +00002e 4628 MOV r0,r5 +000030 f7fffffe BL USART_GetFlagStatus +000034 2800 CMP r0,#0 +000036 d0f9 BEQ |L6.44| +;;;124 ; +;;;125 } +000038 e8bd81f0 POP {r4-r8,pc} +;;;126 + ENDP + + + AREA ||i.Usart_SendString||, CODE, READONLY, ALIGN=1 + + Usart_SendString PROC +;;;90 /***************** 发送字符串 **********************/ +;;;91 void Usart_SendString(USART_TypeDef *pUSARTx, char *str) +000000 b570 PUSH {r4-r6,lr} +;;;92 { +000002 4606 MOV r6,r0 +000004 460c MOV r4,r1 +;;;93 unsigned int k = 0; +000006 2500 MOVS r5,#0 +;;;94 do +000008 bf00 NOP + |L7.10| +;;;95 { +;;;96 Usart_SendByte(pUSARTx, *(str + k)); +00000a 5d61 LDRB r1,[r4,r5] +00000c 4630 MOV r0,r6 +00000e f7fffffe BL Usart_SendByte +;;;97 k++; +000012 1c6d ADDS r5,r5,#1 +;;;98 } while (*(str + k) != '\0'); +000014 5d60 LDRB r0,[r4,r5] +000016 2800 CMP r0,#0 +000018 d1f7 BNE |L7.10| +;;;99 +;;;100 /* 等待发送完成 */ +;;;101 while (USART_GetFlagStatus(pUSARTx, USART_FLAG_TC) == RESET) +00001a bf00 NOP + |L7.28| +00001c 2140 MOVS r1,#0x40 +00001e 4630 MOV r0,r6 +000020 f7fffffe BL USART_GetFlagStatus +000024 2800 CMP r0,#0 +000026 d0f9 BEQ |L7.28| +;;;102 { +;;;103 } +;;;104 } +000028 bd70 POP {r4-r6,pc} +;;;105 + ENDP + + + AREA ||i.fgetc||, CODE, READONLY, ALIGN=2 + + fgetc PROC +;;;140 /// 重定向c库函数scanf到串口，重写向后可使用scanf、getchar等函数 +;;;141 int fgetc(FILE *f) +000000 b510 PUSH {r4,lr} +;;;142 { +000002 4604 MOV r4,r0 +;;;143 /* 等待串口输入数据 */ +;;;144 while (USART_GetFlagStatus(DEBUG_USARTx, USART_FLAG_RXNE) == RESET) +000004 bf00 NOP + |L8.6| +000006 2120 MOVS r1,#0x20 +000008 4804 LDR r0,|L8.28| +00000a f7fffffe BL USART_GetFlagStatus +00000e 2800 CMP r0,#0 +000010 d0f9 BEQ |L8.6| +;;;145 ; +;;;146 +;;;147 return (int)USART_ReceiveData(DEBUG_USARTx); +000012 4802 LDR r0,|L8.28| +000014 f7fffffe BL USART_ReceiveData +;;;148 } +000018 bd10 POP {r4,pc} +;;;149 + ENDP + +00001a 0000 DCW 0x0000 + |L8.28| + DCD 0x40013800 + + AREA ||i.fputc||, CODE, READONLY, ALIGN=2 + + fputc PROC +;;;127 /// 重定向c库函数printf到串口，重定向后可使用printf函数 +;;;128 int fputc(int ch, FILE *f) +000000 b570 PUSH {r4-r6,lr} +;;;129 { +000002 4604 MOV r4,r0 +000004 460d MOV r5,r1 +;;;130 /* 发送一个字节数据到串口 */ +;;;131 USART_SendData(DEBUG_USARTx, (uint8_t)ch); +000006 b2e1 UXTB r1,r4 +000008 4805 LDR r0,|L9.32| +00000a f7fffffe BL USART_SendData +;;;132 +;;;133 /* 等待发送完毕 */ +;;;134 while (USART_GetFlagStatus(DEBUG_USARTx, USART_FLAG_TXE) == RESET) +00000e bf00 NOP + |L9.16| +000010 2180 MOVS r1,#0x80 +000012 4803 LDR r0,|L9.32| +000014 f7fffffe BL USART_GetFlagStatus +000018 2800 CMP r0,#0 +00001a d0f9 BEQ |L9.16| +;;;135 ; +;;;136 +;;;137 return (ch); +00001c 4620 MOV r0,r4 +;;;138 } +00001e bd70 POP {r4-r6,pc} +;;;139 + ENDP + + |L9.32| + DCD 0x40013800 + + AREA ||.bss||, DATA, NOINIT, ALIGN=0 + + ReceiveBuff + % 64 + g_RxBuf + % 64 + + AREA ||.data||, DATA, ALIGN=0 + + g_ucRxRcvNewFlag +000000 00 DCB 0x00 + +;*** Start embedded assembler *** + +#line 1 "..\\..\\User\\bsp\\src\\bsp_usart_dma.c" + AREA ||.rev16_text||, CODE + THUMB + EXPORT |__asm___15_bsp_usart_dma_c_7598bab3____REV16| +#line 114 "..\\..\\Libraries\\CMSIS\\Include\\core_cmInstr.h" +|__asm___15_bsp_usart_dma_c_7598bab3____REV16| PROC +#line 115 + + rev16 r0, r0 + bx lr + ENDP + AREA ||.revsh_text||, CODE + THUMB + EXPORT |__asm___15_bsp_usart_dma_c_7598bab3____REVSH| +#line 128 +|__asm___15_bsp_usart_dma_c_7598bab3____REVSH| PROC +#line 129 + + revsh r0, r0 + bx lr + ENDP + +;*** End embedded assembler *** diff --git a/Project/MDK-ARM/Flash/List/demo_i2c_eeprom.txt b/Project/MDK-ARM/Flash/List/demo_i2c_eeprom.txt new file mode 100644 index 0000000..4157a17 --- /dev/null +++ b/Project/MDK-ARM/Flash/List/demo_i2c_eeprom.txt @@ -0,0 +1,640 @@ +; generated by Component: ARM Compiler 5.05 update 1 (build 106) Tool: ArmCC [4d0efa] +; commandline ArmCC [--list --split_sections --debug -c --asm --interleave -o.\flash\obj\demo_i2c_eeprom.o --asm_dir=.\Flash\List\ --list_dir=.\Flash\List\ --depend=.\flash\obj\demo_i2c_eeprom.d --cpu=Cortex-M3 --apcs=interwork -O0 --diag_suppress=9931,870 -I..\..\Libraries\CMSIS\Device\ST\STM32F10x\Include -I..\..\Libraries\STM32F10x_StdPeriph_Driver\inc -I..\..\Libraries\STM32_USB-FS-Device_Driver\inc -I..\..\Libraries\CMSIS\Include -I..\..\User\bsp -I..\..\User\bsp\inc -I..\..\User\app\inc -IC:\Keil_v5\ARM\RV31\INC -IC:\Keil_v5\ARM\CMSIS\Include -IC:\Keil_v5\ARM\Inc\ST\STM32F10x -D__MICROLIB -D__UVISION_VERSION=514 -DUSE_STDPERIPH_DRIVER -DSTM32F10X_HD --omf_browse=.\flash\obj\demo_i2c_eeprom.crf ..\..\User\app\src\demo_i2c_eeprom.c] + THUMB + + AREA ||i.DemoEEPROM||, CODE, READONLY, ALIGN=2 + + REQUIRE _printf_percent + REQUIRE _printf_d + REQUIRE _printf_s + REQUIRE _printf_int_dec + REQUIRE _printf_str + DemoEEPROM PROC +;;;36 */ +;;;37 void DemoEEPROM(void) +000000 b508 PUSH {r3,lr} +;;;38 { +;;;39 uint8_t cmd; +;;;40 +;;;41 if (ee_CheckOk() == 0) +000002 f7fffffe BL ee_CheckOk +000006 b920 CBNZ r0,|L1.18| +;;;42 { +;;;43 /* ûм⵽EEPROM */ +;;;44 printf("ûм⵽EEPROM!\r\n"); +000008 a01c ADR r0,|L1.124| +00000a f7fffffe BL __2printf +;;;45 +;;;46 while (1); /* ͣ */ +00000e bf00 NOP + |L1.16| +000010 e7fe B |L1.16| + |L1.18| +;;;47 } +;;;48 +;;;49 printf("Ѿ⵽EEPROM : \r\n"); +000012 a020 ADR r0,|L1.148| +000014 f7fffffe BL __2printf +;;;50 printf("ͺ: %s, = %d ֽ, ҳС = %d\r\n", EE_MODEL_NAME, EE_SIZE, EE_PAGE_SIZE); +000018 2340 MOVS r3,#0x40 +00001a 021a LSLS r2,r3,#8 +00001c a124 ADR r1,|L1.176| +00001e a027 ADR r0,|L1.188| +000020 f7fffffe BL __2printf +;;;51 +;;;52 ee_DispMenu(); /* ӡʾ */ +000024 f7fffffe BL ee_DispMenu +;;;53 while(1) +000028 e026 B |L1.120| + |L1.42| +;;;54 { +;;;55 bsp_Idle(); /* bsp.cļû޸ʵCPUߺι */ +00002a f7fffffe BL bsp_Idle +;;;56 +;;;57 //cmd = getchar(); /* Ӵڶһַ (ʽ) */ +;;;58 if (comGetChar(COM1, &cmd)) /* Ӵڶһַ(ʽ) */ +00002e 4669 MOV r1,sp +000030 2000 MOVS r0,#0 +000032 f7fffffe BL comGetChar +000036 2800 CMP r0,#0 +000038 d01e BEQ |L1.120| +;;;59 { +;;;60 switch (cmd) +00003a f89d0000 LDRB r0,[sp,#0] +00003e 2831 CMP r0,#0x31 +000040 d004 BEQ |L1.76| +000042 2832 CMP r0,#0x32 +000044 d008 BEQ |L1.88| +000046 2833 CMP r0,#0x33 +000048 d112 BNE |L1.112| +00004a e00b B |L1.100| + |L1.76| +;;;61 { +;;;62 case '1': +;;;63 printf("\r\n1 - EEPROM ԡ\r\n"); +00004c a026 ADR r0,|L1.232| +00004e f7fffffe BL __2printf +;;;64 ee_ReadTest(); /* EEPROMݣӡ */ +000052 f7fffffe BL ee_ReadTest +;;;65 break; +000056 e00e B |L1.118| + |L1.88| +;;;66 +;;;67 case '2': +;;;68 printf("\r\n2 - д EEPROM ԡ\r\n"); +000058 a02a ADR r0,|L1.260| +00005a f7fffffe BL __2printf +;;;69 ee_WriteTest(); /* дEEPROMݣӡдٶ */ +00005e f7fffffe BL ee_WriteTest +;;;70 break; +000062 e008 B |L1.118| + |L1.100| +;;;71 +;;;72 case '3': +;;;73 printf("\r\n3 - EEPROM\r\n"); +000064 a02e ADR r0,|L1.288| +000066 f7fffffe BL __2printf +;;;74 ee_Erase(); /* EEPROMݣʵϾдȫ0xFF */ +00006a f7fffffe BL ee_Erase +;;;75 break; +00006e e002 B |L1.118| + |L1.112| +;;;76 +;;;77 default: +;;;78 ee_DispMenu(); /* Ч´ӡʾ */ +000070 f7fffffe BL ee_DispMenu +;;;79 break; +000074 bf00 NOP + |L1.118| +000076 bf00 NOP ;65 + |L1.120| +000078 e7d7 B |L1.42| +;;;80 +;;;81 } +;;;82 } +;;;83 } +;;;84 } +;;;85 + ENDP + +00007a 0000 DCW 0x0000 + |L1.124| +00007c c3bbd3d0 DCB 195,187,211,208,188,236,178,226,181,189,180,174,208,208,"E" +000080 bcecb2e2 +000084 b5bdb4ae +000088 d0d045 +00008b 4550524f DCB "EPROM!\r\n",0 +00008f 4d210d0a +000093 00 + |L1.148| +000094 d2d1bead DCB 210,209,190,173,188,236,178,226,181,189,180,174,208,208,"E" +000098 bcecb2e2 +00009c b5bdb4ae +0000a0 d0d045 +0000a3 4550524f DCB "EPROM : \r\n",0 +0000a7 4d203a20 +0000ab 0d0a00 +0000ae 00 DCB 0 +0000af 00 DCB 0 + |L1.176| +0000b0 41543234 DCB "AT24C128",0 +0000b4 43313238 +0000b8 00 +0000b9 00 DCB 0 +0000ba 00 DCB 0 +0000bb 00 DCB 0 + |L1.188| +0000bc d0cdbac5 DCB 208,205,186,197,": %s, ",200,221,193,191," = %d ",215,214 +0000c0 3a202573 +0000c4 2c20c8dd +0000c8 c1bf203d +0000cc 20256420 +0000d0 d7d6 +0000d2 bdda2c20 DCB 189,218,", ",210,179,195,230,180,243,208,161," = %d\r\n",0 +0000d6 d2b3c3e6 +0000da b4f3d0a1 +0000de 203d2025 +0000e2 640d0a00 +0000e6 00 DCB 0 +0000e7 00 DCB 0 + |L1.232| +0000e8 0d0aa1be DCB "\r\n",161,190,"1 - ",182,193," EEPROM ",178,226,202,212 +0000ec 31202d20 +0000f0 b6c12045 +0000f4 4550524f +0000f8 4d20b2e2 +0000fc cad4 +0000fe a1bf0d0a DCB 161,191,"\r\n",0 +000102 00 +000103 00 DCB 0 + |L1.260| +000104 0d0aa1be DCB "\r\n",161,190,"2 - ",208,180," EEPROM ",178,226,202,212 +000108 32202d20 +00010c d0b42045 +000110 4550524f +000114 4d20b2e2 +000118 cad4 +00011a a1bf0d0a DCB 161,191,"\r\n",0 +00011e 00 +00011f 00 DCB 0 + |L1.288| +000120 0d0aa1be DCB "\r\n",161,190,"3 - ",178,193,179,253," EEPROM",161,191,"\r" +000124 33202d20 +000128 b2c1b3fd +00012c 20454550 +000130 524f4da1 +000134 bf0d +000136 0a00 DCB "\n",0 + + AREA ||i.ee_DispMenu||, CODE, READONLY, ALIGN=2 + + REQUIRE _printf_percent + REQUIRE _printf_d + REQUIRE _printf_int_dec + ee_DispMenu PROC +;;;204 */ +;;;205 static void ee_DispMenu(void) +000000 b510 PUSH {r4,lr} +;;;206 { +;;;207 printf("\r\n------------------------------------------------\r\n"); +000002 a00b ADR r0,|L2.48| +000004 f7fffffe BL __2printf +;;;208 printf("ѡ:\r\n"); +000008 a017 ADR r0,|L2.104| +00000a f7fffffe BL __2printf +;;;209 printf("1 - EEPROM (%d ֽ)\r\n", EE_SIZE); +00000e f44f4180 MOV r1,#0x4000 +000012 a01a ADR r0,|L2.124| +000014 f7fffffe BL __2printf +;;;210 printf("2 - дEEPROM (%d ֽ,0x00-0xFF)\r\n", EE_SIZE); +000018 f44f4180 MOV r1,#0x4000 +00001c a01e ADR r0,|L2.152| +00001e f7fffffe BL __2printf +;;;211 printf("3 - EEPROM\r\n"); +000022 a026 ADR r0,|L2.188| +000024 f7fffffe BL __2printf +;;;212 printf("4 - ʾʾ\r\n"); +000028 a029 ADR r0,|L2.208| +00002a f7fffffe BL __2printf +;;;213 } +00002e bd10 POP {r4,pc} +;;;214 + ENDP + + |L2.48| +000030 0d0a2d2d DCB "\r\n------------------------------------------------\r\n" +000034 2d2d2d2d +000038 2d2d2d2d +00003c 2d2d2d2d +000040 2d2d2d2d +000044 2d2d2d2d +000048 2d2d2d2d +00004c 2d2d2d2d +000050 2d2d2d2d +000054 2d2d2d2d +000058 2d2d2d2d +00005c 2d2d2d2d +000060 2d2d0d0a +000064 00 DCB 0 +000065 00 DCB 0 +000066 00 DCB 0 +000067 00 DCB 0 + |L2.104| +000068 c7ebd1a1 DCB 199,235,209,161,212,241,178,217,215,247,195,252,193,238,":" +00006c d4f1b2d9 +000070 d7f7c3fc +000074 c1ee3a +000077 0d0a00 DCB "\r\n",0 +00007a 00 DCB 0 +00007b 00 DCB 0 + |L2.124| +00007c 31202d20 DCB "1 - ",182,193,"EEPROM (%d ",215,214,189,218,")\r\n",0 +000080 b6c14545 +000084 50524f4d +000088 20282564 +00008c 20d7d6bd +000090 da290d0a +000094 00 +000095 00 DCB 0 +000096 00 DCB 0 +000097 00 DCB 0 + |L2.152| +000098 32202d20 DCB "2 - ",208,180,"EEPROM (%d ",215,214,189,218,",0x00-0xFF" +00009c d0b44545 +0000a0 50524f4d +0000a4 20282564 +0000a8 20d7d6bd +0000ac da2c3078 +0000b0 30302d30 +0000b4 784646 +0000b7 290d0a00 DCB ")\r\n",0 +0000bb 00 DCB 0 + |L2.188| +0000bc 33202d20 DCB "3 - ",178,193,179,253,"EEPROM\r\n",0 +0000c0 b2c1b3fd +0000c4 45455052 +0000c8 4f4d0d0a +0000cc 00 +0000cd 00 DCB 0 +0000ce 00 DCB 0 +0000cf 00 DCB 0 + |L2.208| +0000d0 34202d20 DCB "4 - ",207,212,202,190,195,252,193,238,204,225,202,190,"\r" +0000d4 cfd4cabe +0000d8 c3fcc1ee +0000dc cce1cabe +0000e0 0d +0000e1 0a00 DCB "\n",0 +0000e3 00 DCB 0 + + AREA ||i.ee_Erase||, CODE, READONLY, ALIGN=2 + + ee_Erase PROC +;;;174 */ +;;;175 static void ee_Erase(void) +000000 b510 PUSH {r4,lr} +;;;176 { +;;;177 uint16_t i; +;;;178 +;;;179 /* 仺 */ +;;;180 for (i = 0; i < EE_SIZE; i++) +000002 2400 MOVS r4,#0 +000004 e004 B |L3.16| + |L3.6| +;;;181 { +;;;182 buf[i] = 0xFF; +000006 20ff MOVS r0,#0xff +000008 490b LDR r1,|L3.56| +00000a 5508 STRB r0,[r1,r4] +00000c 1c60 ADDS r0,r4,#1 ;180 +00000e b284 UXTH r4,r0 ;180 + |L3.16| +000010 f5b44f80 CMP r4,#0x4000 ;180 +000014 dbf7 BLT |L3.6| +;;;183 } +;;;184 +;;;185 /* дEEPROM, ʼַ = 0ݳΪ 256 */ +;;;186 if (ee_WriteBytes(buf, 0, EE_SIZE) == 0) +000016 f44f4280 MOV r2,#0x4000 +00001a 2100 MOVS r1,#0 +00001c 4806 LDR r0,|L3.56| +00001e f7fffffe BL ee_WriteBytes +000022 b918 CBNZ r0,|L3.44| +;;;187 { +;;;188 printf("eeprom\r\n"); +000024 a005 ADR r0,|L3.60| +000026 f7fffffe BL __2printf + |L3.42| +;;;189 return; +;;;190 } +;;;191 else +;;;192 { +;;;193 printf("eepromɹ\r\n"); +;;;194 } +;;;195 } +00002a bd10 POP {r4,pc} + |L3.44| +00002c a008 ADR r0,|L3.80| +00002e f7fffffe BL __2printf +000032 bf00 NOP +000034 e7f9 B |L3.42| +;;;196 + ENDP + +000036 0000 DCW 0x0000 + |L3.56| + DCD buf + |L3.60| +00003c b2c1b3fd DCB 178,193,179,253,"eeprom",179,246,180,237,163,161,"\r\n",0 +000040 65657072 +000044 6f6db3f6 +000048 b4eda3a1 +00004c 0d0a00 +00004f 00 DCB 0 + |L3.80| +000050 b2c1b3fd DCB 178,193,179,253,"eeprom",179,201,185,166,163,161,"\r\n",0 +000054 65657072 +000058 6f6db3c9 +00005c b9a6a3a1 +000060 0d0a00 +000063 00 DCB 0 + + AREA ||i.ee_ReadTest||, CODE, READONLY, ALIGN=2 + + REQUIRE _printf_pre_padding + REQUIRE _printf_percent + REQUIRE _printf_flags + REQUIRE _printf_widthprec + REQUIRE _printf_x + REQUIRE _printf_longlong_hex + REQUIRE _printf_d + REQUIRE _printf_int_dec + ee_ReadTest PROC +;;;93 */ +;;;94 static void ee_ReadTest(void) +000000 e92d41f0 PUSH {r4-r8,lr} +;;;95 { +;;;96 uint16_t i; +;;;97 int32_t iTime1, iTime2; +;;;98 +;;;99 /* EEPROM, ʼַ = 0 ݳΪ 256 */ +;;;100 iTime1 = bsp_GetRunTime(); /* ¿ʼʱ */ +000004 f7fffffe BL bsp_GetRunTime +000008 4606 MOV r6,r0 +;;;101 if (ee_ReadBytes((uint8_t *)buf, 0, EE_SIZE) == 0) +00000a f44f4280 MOV r2,#0x4000 +00000e 2100 MOVS r1,#0 +000010 481a LDR r0,|L4.124| +000012 f7fffffe BL ee_ReadBytes +000016 b920 CBNZ r0,|L4.34| +;;;102 { +;;;103 printf("eeprom\r\n"); +000018 a019 ADR r0,|L4.128| +00001a f7fffffe BL __2printf + |L4.30| +;;;104 return; +;;;105 } +;;;106 else +;;;107 { +;;;108 iTime2 = bsp_GetRunTime(); /* ½ʱ */ +;;;109 printf("eepromɹ£\r\n"); +;;;110 } +;;;111 +;;;112 /* ӡ */ +;;;113 for (i = 0; i < EE_SIZE; i++) +;;;114 { +;;;115 printf(" %02X", buf[i]); +;;;116 +;;;117 if ((i & 31) == 31) +;;;118 { +;;;119 printf("\r\n"); /* ÿʾ16ֽ */ +;;;120 } +;;;121 else if ((i & 31) == 15) +;;;122 { +;;;123 printf(" - "); +;;;124 } +;;;125 } +;;;126 +;;;127 /* ӡٶ */ +;;;128 printf("ʱ: %dms, ٶ: %dB/s\r\n", iTime2 - iTime1, (EE_SIZE * 1000) / (iTime2 - iTime1)); +;;;129 } +00001e e8bd81f0 POP {r4-r8,pc} + |L4.34| +000022 f7fffffe BL bsp_GetRunTime +000026 4605 MOV r5,r0 ;108 +000028 a01a ADR r0,|L4.148| +00002a f7fffffe BL __2printf +00002e 2400 MOVS r4,#0 ;113 +000030 e015 B |L4.94| + |L4.50| +000032 4812 LDR r0,|L4.124| +000034 5d01 LDRB r1,[r0,r4] ;115 +000036 a01e ADR r0,|L4.176| +000038 f7fffffe BL __2printf +00003c f004001f AND r0,r4,#0x1f ;117 +000040 281f CMP r0,#0x1f ;117 +000042 d103 BNE |L4.76| +000044 a019 ADR r0,|L4.172| +000046 f7fffffe BL __2printf +00004a e006 B |L4.90| + |L4.76| +00004c f004001f AND r0,r4,#0x1f ;121 +000050 280f CMP r0,#0xf ;121 +000052 d102 BNE |L4.90| +000054 a018 ADR r0,|L4.184| +000056 f7fffffe BL __2printf + |L4.90| +00005a 1c60 ADDS r0,r4,#1 ;113 +00005c b284 UXTH r4,r0 ;113 + |L4.94| +00005e f5b44f80 CMP r4,#0x4000 ;113 +000062 dbe6 BLT |L4.50| +000064 1ba8 SUBS r0,r5,r6 ;128 +000066 f44f017a MOV r1,#0xfa0000 ;128 +00006a fb91f7f0 SDIV r7,r1,r0 ;128 +00006e 1ba9 SUBS r1,r5,r6 ;128 +000070 463a MOV r2,r7 ;128 +000072 a012 ADR r0,|L4.188| +000074 f7fffffe BL __2printf +000078 bf00 NOP +00007a e7d0 B |L4.30| +;;;130 /* + ENDP + + |L4.124| + DCD buf + |L4.128| +000080 b6c16565 DCB 182,193,"eeprom",179,246,180,237,163,161,"\r\n",0 +000084 70726f6d +000088 b3f6b4ed +00008c a3a10d0a +000090 00 +000091 00 DCB 0 +000092 00 DCB 0 +000093 00 DCB 0 + |L4.148| +000094 b6c16565 DCB 182,193,"eeprom",179,201,185,166,163,172,202,253,190,221 +000098 70726f6d +00009c b3c9b9a6 +0000a0 a3accafd +0000a4 bedd +0000a6 c8e7cfc2 DCB 200,231,207,194,163,186 +0000aa a3ba + |L4.172| +0000ac 0d0a00 DCB "\r\n",0 +0000af 00 DCB 0 + |L4.176| +0000b0 20253032 DCB " %02X",0 +0000b4 5800 +0000b6 00 DCB 0 +0000b7 00 DCB 0 + |L4.184| +0000b8 202d2000 DCB " - ",0 + |L4.188| +0000bc b6c1bac4 DCB 182,193,186,196,202,177,": %dms, ",182,193,203,217,182,200 +0000c0 cab13a20 +0000c4 25646d73 +0000c8 2c20b6c1 +0000cc cbd9b6c8 +0000d0 3a202564 DCB ": %dB/s\r\n",0 +0000d4 422f730d +0000d8 0a00 +0000da 00 DCB 0 +0000db 00 DCB 0 + + AREA ||i.ee_WriteTest||, CODE, READONLY, ALIGN=2 + + REQUIRE _printf_percent + REQUIRE _printf_d + REQUIRE _printf_int_dec + ee_WriteTest PROC +;;;137 */ +;;;138 static void ee_WriteTest(void) +000000 e92d41f0 PUSH {r4-r8,lr} +;;;139 { +;;;140 uint16_t i; +;;;141 int32_t iTime1, iTime2; +;;;142 +;;;143 /* Ի */ +;;;144 for (i = 0; i < EE_SIZE; i++) +000004 2400 MOVS r4,#0 +000006 e003 B |L5.16| + |L5.8| +;;;145 { +;;;146 buf[i] = i; +000008 4913 LDR r1,|L5.88| +00000a 550c STRB r4,[r1,r4] +00000c 1c60 ADDS r0,r4,#1 ;144 +00000e b284 UXTH r4,r0 ;144 + |L5.16| +000010 f5b44f80 CMP r4,#0x4000 ;144 +000014 dbf8 BLT |L5.8| +;;;147 } +;;;148 +;;;149 /* дEEPROM, ʼַ = 0ݳΪ 256 */ +;;;150 iTime1 = bsp_GetRunTime(); /* ¿ʼʱ */ +000016 f7fffffe BL bsp_GetRunTime +00001a 4605 MOV r5,r0 +;;;151 if (ee_WriteBytes(buf, 0, EE_SIZE) == 0) +00001c f44f4280 MOV r2,#0x4000 +000020 2100 MOVS r1,#0 +000022 480d LDR r0,|L5.88| +000024 f7fffffe BL ee_WriteBytes +000028 b920 CBNZ r0,|L5.52| +;;;152 { +;;;153 printf("дeeprom\r\n"); +00002a a00c ADR r0,|L5.92| +00002c f7fffffe BL __2printf + |L5.48| +;;;154 return; +;;;155 } +;;;156 else +;;;157 { +;;;158 iTime2 = bsp_GetRunTime(); /* ½ʱ */ +;;;159 printf("дeepromɹ\r\n"); +;;;160 } +;;;161 +;;;162 +;;;163 /* ӡٶ */ +;;;164 printf("дʱ: %dms, дٶ: %dB/s\r\n", iTime2 - iTime1, (EE_SIZE * 1000) / (iTime2 - iTime1)); +;;;165 } +000030 e8bd81f0 POP {r4-r8,pc} + |L5.52| +000034 f7fffffe BL bsp_GetRunTime +000038 4606 MOV r6,r0 ;158 +00003a a00d ADR r0,|L5.112| +00003c f7fffffe BL __2printf +000040 1b70 SUBS r0,r6,r5 ;164 +000042 f44f017a MOV r1,#0xfa0000 ;164 +000046 fb91f7f0 SDIV r7,r1,r0 ;164 +00004a 1b71 SUBS r1,r6,r5 ;164 +00004c 463a MOV r2,r7 ;164 +00004e a00d ADR r0,|L5.132| +000050 f7fffffe BL __2printf +000054 bf00 NOP +000056 e7eb B |L5.48| +;;;166 + ENDP + + |L5.88| + DCD buf + |L5.92| +00005c d0b46565 DCB 208,180,"eeprom",179,246,180,237,163,161,"\r\n",0 +000060 70726f6d +000064 b3f6b4ed +000068 a3a10d0a +00006c 00 +00006d 00 DCB 0 +00006e 00 DCB 0 +00006f 00 DCB 0 + |L5.112| +000070 d0b46565 DCB 208,180,"eeprom",179,201,185,166,163,161,"\r\n",0 +000074 70726f6d +000078 b3c9b9a6 +00007c a3a10d0a +000080 00 +000081 00 DCB 0 +000082 00 DCB 0 +000083 00 DCB 0 + |L5.132| +000084 d0b4bac4 DCB 208,180,186,196,202,177,": %dms, ",208,180,203,217,182,200 +000088 cab13a20 +00008c 25646d73 +000090 2c20d0b4 +000094 cbd9b6c8 +000098 3a202564 DCB ": %dB/s\r\n",0 +00009c 422f730d +0000a0 0a00 +0000a2 00 DCB 0 +0000a3 00 DCB 0 + + AREA ||.bss||, DATA, NOINIT, ALIGN=0 + + buf + % 16384 + +;*** Start embedded assembler *** + +#line 1 "..\\..\\User\\app\\src\\demo_i2c_eeprom.c" + AREA ||.rev16_text||, CODE + THUMB + EXPORT |__asm___17_demo_i2c_eeprom_c_4000555c____REV16| +#line 114 "..\\..\\Libraries\\CMSIS\\Include\\core_cmInstr.h" +|__asm___17_demo_i2c_eeprom_c_4000555c____REV16| PROC +#line 115 + + rev16 r0, r0 + bx lr + ENDP + AREA ||.revsh_text||, CODE + THUMB + EXPORT |__asm___17_demo_i2c_eeprom_c_4000555c____REVSH| +#line 128 +|__asm___17_demo_i2c_eeprom_c_4000555c____REVSH| PROC +#line 129 + + revsh r0, r0 + bx lr + ENDP + +;*** End embedded assembler *** diff --git a/Project/MDK-ARM/Flash/List/main.txt b/Project/MDK-ARM/Flash/List/main.txt new file mode 100644 index 0000000..af457b9 --- /dev/null +++ b/Project/MDK-ARM/Flash/List/main.txt @@ -0,0 +1,1673 @@ +; generated by Component: ARM Compiler 5.06 update 7 (build 960) Tool: ArmCC [4d365d] +; commandline ArmCC [--list --split_sections --debug -c --asm --interleave -o.\flash\obj\main.o --asm_dir=.\Flash\List\ --list_dir=.\Flash\List\ --depend=.\flash\obj\main.d --cpu=Cortex-M3 --apcs=interwork -O0 --diag_suppress=9931,870 -I..\..\Libraries\CMSIS\Device\ST\STM32F10x\Include -I..\..\Libraries\STM32F10x_StdPeriph_Driver\inc -I..\..\Libraries\STM32_USB-FS-Device_Driver\inc -I..\..\Libraries\CMSIS\Include -I..\..\User\bsp -I..\..\User\bsp\inc -I..\..\User\app\inc -I..\..\User -IC:\Users\w1619\AppData\Local\Arm\Packs\Keil\STM32F1xx_DFP\2.4.1\Device\Include -D__MICROLIB -D__UVISION_VERSION=538 -DSTM32F10X_HD -DUSE_STDPERIPH_DRIVER -DSTM32F10X_HD --omf_browse=.\flash\obj\main.crf ..\..\User\app\src\main.c] + THUMB + + AREA ||i.Adc_Init||, CODE, READONLY, ALIGN=2 + + Adc_Init PROC +;;;53 // 我们默认将开启通道0~3 +;;;54 void Adc_Init(void) +000000 b500 PUSH {lr} +;;;55 { +000002 b087 SUB sp,sp,#0x1c +;;;56 ADC_InitTypeDef ADC_InitStructure; +;;;57 GPIO_InitTypeDef GPIO_InitStructure; +;;;58 +;;;59 RCC_APB2PeriphClockCmd(RCC_APB2Periph_GPIOA | RCC_APB2Periph_ADC1, ENABLE); // 使能ADC1通道时钟 +000004 2101 MOVS r1,#1 +000006 f44f7001 MOV r0,#0x204 +00000a f7fffffe BL RCC_APB2PeriphClockCmd +;;;60 +;;;61 RCC_ADCCLKConfig(RCC_PCLK2_Div6); // 设置ADC分频因子6 72M/6=12,ADC最大时间不能超过14M +00000e f44f4000 MOV r0,#0x8000 +000012 f7fffffe BL RCC_ADCCLKConfig +;;;62 +;;;63 // PA1 作为模拟通道输入引脚 +;;;64 GPIO_InitStructure.GPIO_Pin = GPIO_Pin_1 | GPIO_Pin_2; +000016 2006 MOVS r0,#6 +000018 f8ad0004 STRH r0,[sp,#4] +;;;65 GPIO_InitStructure.GPIO_Mode = GPIO_Mode_AIN; // 模拟输入引脚 +00001c 2000 MOVS r0,#0 +00001e f88d0007 STRB r0,[sp,#7] +;;;66 GPIO_Init(GPIOA, &GPIO_InitStructure); +000022 a901 ADD r1,sp,#4 +000024 4817 LDR r0,|L1.132| +000026 f7fffffe BL GPIO_Init +;;;67 +;;;68 ADC_DeInit(ADC1); // 复位ADC1,将外设 ADC1 的全部寄存器重设为缺省值 +00002a 4817 LDR r0,|L1.136| +00002c f7fffffe BL ADC_DeInit +;;;69 +;;;70 ADC_InitStructure.ADC_Mode = ADC_Mode_Independent; // ADC工作模式:ADC1和ADC2工作在独立模式 +000030 2000 MOVS r0,#0 +000032 9002 STR r0,[sp,#8] +;;;71 ADC_InitStructure.ADC_ScanConvMode = DISABLE; // 模数转换工作在单通道模式 +000034 f88d000c STRB r0,[sp,#0xc] +;;;72 ADC_InitStructure.ADC_ContinuousConvMode = DISABLE; // 模数转换工作在单次转换模式 +000038 f88d000d STRB r0,[sp,#0xd] +;;;73 ADC_InitStructure.ADC_ExternalTrigConv = ADC_ExternalTrigConv_None; // 转换由软件而不是外部触发启动 +00003c f44f2060 MOV r0,#0xe0000 +000040 9004 STR r0,[sp,#0x10] +;;;74 ADC_InitStructure.ADC_DataAlign = ADC_DataAlign_Right; // ADC数据右对齐 +000042 2000 MOVS r0,#0 +000044 9005 STR r0,[sp,#0x14] +;;;75 ADC_InitStructure.ADC_NbrOfChannel = 1; // 顺序进行规则转换的ADC通道的数目 +000046 2001 MOVS r0,#1 +000048 f88d0018 STRB r0,[sp,#0x18] +;;;76 ADC_Init(ADC1, &ADC_InitStructure); // 根据ADC_InitStruct中指定的参数初始化外设ADCx的寄存器 +00004c a902 ADD r1,sp,#8 +00004e 480e LDR r0,|L1.136| +000050 f7fffffe BL ADC_Init +;;;77 +;;;78 ADC_Cmd(ADC1, ENABLE); // 使能指定的ADC1 +000054 2101 MOVS r1,#1 +000056 480c LDR r0,|L1.136| +000058 f7fffffe BL ADC_Cmd +;;;79 +;;;80 ADC_ResetCalibration(ADC1); // 使能复位校准 +00005c 480a LDR r0,|L1.136| +00005e f7fffffe BL ADC_ResetCalibration +;;;81 +;;;82 while (ADC_GetResetCalibrationStatus(ADC1)) +000062 bf00 NOP + |L1.100| +000064 4808 LDR r0,|L1.136| +000066 f7fffffe BL ADC_GetResetCalibrationStatus +00006a 2800 CMP r0,#0 +00006c d1fa BNE |L1.100| +;;;83 ; // 等待复位校准结束 +;;;84 +;;;85 ADC_StartCalibration(ADC1); // 开启AD校准 +00006e 4806 LDR r0,|L1.136| +000070 f7fffffe BL ADC_StartCalibration +;;;86 +;;;87 while (ADC_GetCalibrationStatus(ADC1)) +000074 bf00 NOP + |L1.118| +000076 4804 LDR r0,|L1.136| +000078 f7fffffe BL ADC_GetCalibrationStatus +00007c 2800 CMP r0,#0 +00007e d1fa BNE |L1.118| +;;;88 ; // 等待校准结束 +;;;89 +;;;90 // ADC_SoftwareStartConvCmd(ADC1, ENABLE); //使能指定的ADC1的软件转换启动功能 +;;;91 } +000080 b007 ADD sp,sp,#0x1c +000082 bd00 POP {pc} +;;;92 // 获得ADC值 + ENDP + + |L1.132| + DCD 0x40010800 + |L1.136| + DCD 0x40012400 + + AREA ||i.Delay_ms||, CODE, READONLY, ALIGN=1 + + Delay_ms PROC +;;;27 #define IS_MF_VALID (g_RxBuf[1] == 'M' && g_RxBuf[2] == 'F') +;;;28 static void Delay_ms(uint16_t us) +000000 2100 MOVS r1,#0 +;;;29 { +;;;30 uint16_t i; +;;;31 +;;;32 /*　 +;;;33 CPU主频168MHz时，在内部Flash运行, MDK工程不优化。用台式示波器观测波形。 +;;;34 循环次数为5时，SCL频率 = 1.78MHz (读耗时: 92ms, 读写正常，但是用示波器探头碰上就读写失败。时序接近临界) +;;;35 循环次数为10时，SCL频率 = 1.1MHz (读耗时: 138ms, 读速度: 118724B/s) +;;;36 循环次数为30时，SCL频率 = 440KHz， SCL高电平时间1.0us，SCL低电平时间1.2us +;;;37 +;;;38 上拉电阻选择2.2K欧时，SCL上升沿时间约0.5us，如果选4.7K欧，则上升沿约1us +;;;39 +;;;40 实际应用选择400KHz左右的速率即可 +;;;41 */ +;;;42 for (i = 0; i < (300 * us); i++) +000002 e001 B |L2.8| + |L2.4| +000004 1c4a ADDS r2,r1,#1 +000006 b291 UXTH r1,r2 + |L2.8| +000008 f44f7296 MOV r2,#0x12c +00000c 4342 MULS r2,r0,r2 +00000e 428a CMP r2,r1 +000010 dcf8 BGT |L2.4| +;;;43 ; +;;;44 } +000012 4770 BX lr +;;;45 void key1_task(void); + ENDP + + + AREA ||i.Get_Adc||, CODE, READONLY, ALIGN=2 + + Get_Adc PROC +;;;93 // ch:通道值 0~3 ADC_Channel_1 +;;;94 u16 Get_Adc(u8 ch) +000000 b510 PUSH {r4,lr} +;;;95 { +000002 4604 MOV r4,r0 +;;;96 // 设置指定ADC的规则组通道，一个序列，采样时间 +;;;97 ADC_RegularChannelConfig(ADC1, ch, 1, ADC_SampleTime_239Cycles5); // ADC1,ADC通道,采样时间为239.5周期 +000004 2307 MOVS r3,#7 +000006 2201 MOVS r2,#1 +000008 4621 MOV r1,r4 +00000a 4809 LDR r0,|L3.48| +00000c f7fffffe BL ADC_RegularChannelConfig +;;;98 +;;;99 ADC_SoftwareStartConvCmd(ADC1, ENABLE); // 使能指定的ADC1的软件转换启动功能 +000010 2101 MOVS r1,#1 +000012 4807 LDR r0,|L3.48| +000014 f7fffffe BL ADC_SoftwareStartConvCmd +;;;100 +;;;101 while (!ADC_GetFlagStatus(ADC1, ADC_FLAG_EOC)) +000018 bf00 NOP + |L3.26| +00001a 2102 MOVS r1,#2 +00001c 4804 LDR r0,|L3.48| +00001e f7fffffe BL ADC_GetFlagStatus +000022 2800 CMP r0,#0 +000024 d0f9 BEQ |L3.26| +;;;102 ; // 等待转换结束 +;;;103 +;;;104 return ADC_GetConversionValue(ADC1); // 返回最近一次ADC1规则组的转换结果 +000026 4802 LDR r0,|L3.48| +000028 f7fffffe BL ADC_GetConversionValue +;;;105 } +00002c bd10 POP {r4,pc} +;;;106 + ENDP + +00002e 0000 DCW 0x0000 + |L3.48| + DCD 0x40012400 + + AREA ||i.Get_Adc_Average||, CODE, READONLY, ALIGN=1 + + Get_Adc_Average PROC +;;;106 +;;;107 u16 Get_Adc_Average(u8 ch, u8 times) +000000 e92d41f0 PUSH {r4-r8,lr} +;;;108 { +000004 4607 MOV r7,r0 +000006 460c MOV r4,r1 +;;;109 u32 temp_val = 0; +000008 2500 MOVS r5,#0 +;;;110 u8 t; +;;;111 for (t = 0; t < times; t++) +00000a 2600 MOVS r6,#0 +00000c e008 B |L4.32| + |L4.14| +;;;112 { +;;;113 temp_val += Get_Adc(ch); +00000e 4638 MOV r0,r7 +000010 f7fffffe BL Get_Adc +000014 4405 ADD r5,r5,r0 +;;;114 Delay_ms(5); +000016 2005 MOVS r0,#5 +000018 f7fffffe BL Delay_ms +00001c 1c70 ADDS r0,r6,#1 ;111 +00001e b2c6 UXTB r6,r0 ;111 + |L4.32| +000020 42a6 CMP r6,r4 ;111 +000022 dbf4 BLT |L4.14| +;;;115 } +;;;116 return temp_val / times; +000024 fbb5f0f4 UDIV r0,r5,r4 +000028 b280 UXTH r0,r0 +;;;117 } +00002a e8bd81f0 POP {r4-r8,pc} +;;;118 + ENDP + + + AREA ||i.get_key4_adc||, CODE, READONLY, ALIGN=1 + + get_key4_adc PROC +;;;118 +;;;119 u16 get_key4_adc(void) +000000 b570 PUSH {r4-r6,lr} +;;;120 { +;;;121 u16 key4_adc = 0; +000002 2400 MOVS r4,#0 +;;;122 u16 ad_value; +;;;123 +;;;124 ad_value = Get_Adc_Average(ADC_Channel_1, 10); +000004 210a MOVS r1,#0xa +000006 2001 MOVS r0,#1 +000008 f7fffffe BL Get_Adc_Average +00000c 4605 MOV r5,r0 +;;;125 +;;;126 key4_adc = ad_value; +00000e 462c MOV r4,r5 +;;;127 if (key4_adc > 3000) +000010 f64030b8 MOV r0,#0xbb8 +000014 4284 CMP r4,r0 +000016 dd01 BLE |L5.28| +;;;128 { +;;;129 key4_adc = 2; // 前进 +000018 2402 MOVS r4,#2 +00001a e00c B |L5.54| + |L5.28| +;;;130 } +;;;131 else if (key4_adc <= 1200) +00001c f5b46f96 CMP r4,#0x4b0 +000020 dc01 BGT |L5.38| +;;;132 { +;;;133 key4_adc = 1; // 后退 +000022 2401 MOVS r4,#1 +000024 e007 B |L5.54| + |L5.38| +;;;134 } +;;;135 else if ((key4_adc > 1200) && (key4_adc <= 3000)) +000026 f5b46f96 CMP r4,#0x4b0 +00002a dd04 BLE |L5.54| +00002c f64030b8 MOV r0,#0xbb8 +000030 4284 CMP r4,r0 +000032 dc00 BGT |L5.54| +;;;136 { +;;;137 key4_adc = 0; // 后退 +000034 2400 MOVS r4,#0 + |L5.54| +;;;138 } +;;;139 return key4_adc; +000036 4620 MOV r0,r4 +;;;140 } +000038 bd70 POP {r4-r6,pc} +;;;141 u16 get_key5_adc(void) + ENDP + + + AREA ||i.get_key5_adc||, CODE, READONLY, ALIGN=2 + + get_key5_adc PROC +;;;140 } +;;;141 u16 get_key5_adc(void) +000000 e92d5ff0 PUSH {r4-r12,lr} +;;;142 { +;;;143 u16 key5_adc = 0; +000004 f04f0a00 MOV r10,#0 +;;;144 u16 ad_value; +;;;145 +;;;146 ad_value = Get_Adc_Average(ADC_Channel_2, 10); +000008 210a MOVS r1,#0xa +00000a 2002 MOVS r0,#2 +00000c f7fffffe BL Get_Adc_Average +000010 4683 MOV r11,r0 +;;;147 +;;;148 // electric_quantity_percent = ((ad_value*3.3/4096.0)-1.846)*100/0.52; +;;;149 key5_adc = (ad_value * 3.3 / 4096.0); +000012 4658 MOV r0,r11 +000014 f7fffffe BL __aeabi_ui2d +000018 4680 MOV r8,r0 +00001a f04f3266 MOV r2,#0x66666666 +00001e 4b13 LDR r3,|L6.108| +000020 f7fffffe BL __aeabi_dmul +000024 4606 MOV r6,r0 +000026 2200 MOVS r2,#0 +000028 4b11 LDR r3,|L6.112| +00002a f7fffffe BL __aeabi_ddiv +00002e 4604 MOV r4,r0 +000030 f7fffffe BL __aeabi_d2uiz +000034 fa1ffa80 UXTH r10,r0 +;;;150 +;;;151 if (key5_adc >= 3000) +000038 f64030b8 MOV r0,#0xbb8 +00003c 4582 CMP r10,r0 +00003e db02 BLT |L6.70| +;;;152 { +;;;153 key5_adc = 1; // 前进 +000040 f04f0a01 MOV r10,#1 +000044 e00e B |L6.100| + |L6.70| +;;;154 } +;;;155 else if (key5_adc <= 1200) +000046 f5ba6f96 CMP r10,#0x4b0 +00004a dc02 BGT |L6.82| +;;;156 { +;;;157 key5_adc = 2; // 后退 +00004c f04f0a02 MOV r10,#2 +000050 e008 B |L6.100| + |L6.82| +;;;158 } +;;;159 else if ((key5_adc > 1200) && (key5_adc < 3000)) +000052 f5ba6f96 CMP r10,#0x4b0 +000056 dd05 BLE |L6.100| +000058 f64030b8 MOV r0,#0xbb8 +00005c 4582 CMP r10,r0 +00005e da01 BGE |L6.100| +;;;160 { +;;;161 key5_adc = 0; // 后退 +000060 f04f0a00 MOV r10,#0 + |L6.100| +;;;162 } +;;;163 return key5_adc; +000064 4650 MOV r0,r10 +;;;164 } +000066 e8bd9ff0 POP {r4-r12,pc} +;;;165 + ENDP + +00006a 0000 DCW 0x0000 + |L6.108| + DCD 0x400a6666 + |L6.112| + DCD 0x40b00000 + + AREA ||i.main||, CODE, READONLY, ALIGN=2 + + REQUIRE _printf_percent + REQUIRE _printf_u + REQUIRE _printf_int_dec + REQUIRE _printf_sizespec + REQUIRE _printf_pre_padding + REQUIRE _printf_flags + REQUIRE _printf_widthprec + REQUIRE _printf_x + REQUIRE _printf_longlong_hex + main PROC +;;;209 } +;;;210 int main(void) +000000 b508 PUSH {r3,lr} +;;;211 { +;;;212 uint8_t ucKeyCode; +;;;213 uint32_t freq = 1500; +000002 f24058dc MOV r8,#0x5dc +;;;214 uint16_t motor_move1 = 0; +000006 2700 MOVS r7,#0 +;;;215 uint32_t g_sysclk_src = 0, g_pll_mul = 0; +000008 2500 MOVS r5,#0 +00000a 2600 MOVS r6,#0 +;;;216 // uint16_t motor_move2 = 0; +;;;217 +;;;218 SCB->VTOR = 0x08008000; +00000c 484a LDR r0,|L7.312| +00000e 494b LDR r1,|L7.316| +000010 6008 STR r0,[r1,#0] +;;;219 +;;;220 /* === MCO 测试: PA8 输出 PLLCLK/2，示波器测量 PA8 === */ +;;;221 { +;;;222 GPIO_InitTypeDef GPIO_InitStruct; +;;;223 RCC_APB2PeriphClockCmd(RCC_APB2Periph_GPIOA, ENABLE); +000012 2101 MOVS r1,#1 +000014 2004 MOVS r0,#4 +000016 f7fffffe BL RCC_APB2PeriphClockCmd +;;;224 GPIO_InitStruct.GPIO_Pin = GPIO_Pin_8; +00001a f44f7080 MOV r0,#0x100 +00001e f8ad0000 STRH r0,[sp,#0] +;;;225 GPIO_InitStruct.GPIO_Mode = GPIO_Mode_AF_PP; +000022 2018 MOVS r0,#0x18 +000024 f88d0003 STRB r0,[sp,#3] +;;;226 GPIO_InitStruct.GPIO_Speed = GPIO_Speed_50MHz; +000028 2003 MOVS r0,#3 +00002a f88d0002 STRB r0,[sp,#2] +;;;227 GPIO_Init(GPIOA, &GPIO_InitStruct); +00002e 4669 MOV r1,sp +000030 4843 LDR r0,|L7.320| +000032 f7fffffe BL GPIO_Init +;;;228 RCC->CFGR = (RCC->CFGR & ~RCC_CFGR_MCO) | RCC_CFGR_MCO_PLL; +000036 4843 LDR r0,|L7.324| +000038 6840 LDR r0,[r0,#4] +00003a f04060e0 ORR r0,r0,#0x7000000 +00003e 4941 LDR r1,|L7.324| +000040 6048 STR r0,[r1,#4] +;;;229 /* MCO 输出 PLL/2：72MHz 系统 = 36MHz, 48MHz 系统 = 24MHz */ +;;;230 } +;;;231 +;;;232 /* 运行时检测实际系统时钟 */ +;;;233 { +;;;234 g_sysclk_src = RCC->CFGR & RCC_CFGR_SWS; +000042 4608 MOV r0,r1 +000044 6840 LDR r0,[r0,#4] +000046 f000050c AND r5,r0,#0xc +;;;235 if (g_sysclk_src == 0x08) +00004a 2d08 CMP r5,#8 +00004c d104 BNE |L7.88| +;;;236 { +;;;237 g_pll_mul = (RCC->CFGR & RCC_CFGR_PLLMULL) >> 18; +00004e 4608 MOV r0,r1 +000050 6840 LDR r0,[r0,#4] +000052 f3c04683 UBFX r6,r0,#18,#4 +;;;238 g_pll_mul = g_pll_mul + 2; +000056 1cb6 ADDS r6,r6,#2 + |L7.88| +;;;239 } +;;;240 } +;;;241 +;;;242 bsp_Init(); /* 硬件初始化 */ +000058 f7fffffe BL bsp_Init +;;;243 +;;;244 /* 打印调试信息（需在串口初始化后） */ +;;;245 { +;;;246 if (g_sysclk_src == 0x00) +00005c b91d CBNZ r5,|L7.102| +;;;247 printf("SYSCLK = HSI 8MHz\r\n"); +00005e a03a ADR r0,|L7.328| +000060 f7fffffe BL __2printf +000064 e00d B |L7.130| + |L7.102| +;;;248 else if (g_sysclk_src == 0x04) +000066 2d04 CMP r5,#4 +000068 d103 BNE |L7.114| +;;;249 printf("SYSCLK = HSE\r\n"); +00006a a03c ADR r0,|L7.348| +00006c f7fffffe BL __2printf +000070 e007 B |L7.130| + |L7.114| +;;;250 else if (g_sysclk_src == 0x08) +000072 2d08 CMP r5,#8 +000074 d105 BNE |L7.130| +;;;251 { +;;;252 printf("PLL MUL = %u, PLL = 8MHz * %u = %uMHz\r\n", g_pll_mul, g_pll_mul, 8 * g_pll_mul); +000076 00f3 LSLS r3,r6,#3 +000078 4632 MOV r2,r6 +00007a 4631 MOV r1,r6 +00007c a03b ADR r0,|L7.364| +00007e f7fffffe BL __2printf + |L7.130| +;;;253 } +;;;254 printf("SystemCoreClock var = %lu\r\n", SystemCoreClock); +000082 4844 LDR r0,|L7.404| +000084 6801 LDR r1,[r0,#0] ; SystemCoreClock +000086 a044 ADR r0,|L7.408| +000088 f7fffffe BL __2printf +;;;255 printf("RCC->CFGR = 0x%08lX, PPRE1=%lu\r\n", RCC->CFGR, (RCC->CFGR >> 8) & 0x7); +00008c 482d LDR r0,|L7.324| +00008e 6840 LDR r0,[r0,#4] +000090 f3c02202 UBFX r2,r0,#8,#3 +000094 482b LDR r0,|L7.324| +000096 6841 LDR r1,[r0,#4] +000098 a046 ADR r0,|L7.436| +00009a f7fffffe BL __2printf +;;;256 printf("TIM6 PSC = %u, ARR = %u\r\n", TIM6->PSC, TIM6->ARR); +00009e 484e LDR r0,|L7.472| +0000a0 8d82 LDRH r2,[r0,#0x2c] +0000a2 8d01 LDRH r1,[r0,#0x28] +0000a4 a04d ADR r0,|L7.476| +0000a6 f7fffffe BL __2printf +;;;257 } +;;;258 +;;;259 Adc_Init(); // ADC初始化 +0000aa f7fffffe BL Adc_Init +;;;260 BEEP_Start(freq, 20, 1, 1); +0000ae 2301 MOVS r3,#1 +0000b0 461a MOV r2,r3 +0000b2 2114 MOVS r1,#0x14 +0000b4 4640 MOV r0,r8 +0000b6 f7fffffe BL BEEP_Start +;;;261 +;;;262 g_tTube.state = WORK; +0000ba 2001 MOVS r0,#1 +0000bc 494e LDR r1,|L7.504| +0000be 72c8 STRB r0,[r1,#0xb] +;;;263 MOTO_Stop(); +0000c0 f7fffffe BL MOTO_Stop +;;;264 +;;;265 /* 主程序大循环 */ +;;;266 while (1) +0000c4 e036 B |L7.308| + |L7.198| +;;;267 { +;;;268 bsp_Idle(); /* CPU空闲时执行的函数，在 bsp.c */ +0000c6 f7fffffe BL bsp_Idle +;;;269 uart_msg_idle(); +0000ca f7fffffe BL uart_msg_idle +;;;270 if (Flag_100ms == 1) +0000ce 484b LDR r0,|L7.508| +0000d0 7800 LDRB r0,[r0,#0] ; Flag_100ms +0000d2 2801 CMP r0,#1 +0000d4 d11a BNE |L7.268| +;;;271 { +;;;272 Flag_100ms = 0; +0000d6 2000 MOVS r0,#0 +0000d8 4948 LDR r1,|L7.508| +0000da 7008 STRB r0,[r1,#0] +;;;273 motor_move1 = get_key4_adc(); +0000dc f7fffffe BL get_key4_adc +0000e0 4607 MOV r7,r0 +;;;274 // motor_move2 = get_key5_adc(); +;;;275 if (motor_move1 == 1) // key4 +0000e2 2f01 CMP r7,#1 +0000e4 d108 BNE |L7.248| +;;;276 { +;;;277 motor_move1 = 0; +0000e6 2700 MOVS r7,#0 +;;;278 // 前进 +;;;279 motor_dir(1500, 0, 3000); +0000e8 f64032b8 MOV r2,#0xbb8 +0000ec 2300 MOVS r3,#0 +0000ee 4619 MOV r1,r3 +0000f0 1050 ASRS r0,r2,#1 +0000f2 f7fffffe BL motor_dir +0000f6 e009 B |L7.268| + |L7.248| +;;;280 } +;;;281 else if (motor_move1 == 2) +0000f8 2f02 CMP r7,#2 +0000fa d107 BNE |L7.268| +;;;282 { +;;;283 motor_move1 = 0; +0000fc 2700 MOVS r7,#0 +;;;284 // 后退 +;;;285 motor_dir(1500, 1, 3000); +0000fe f64032b8 MOV r2,#0xbb8 +000102 2300 MOVS r3,#0 +000104 2101 MOVS r1,#1 +000106 1050 ASRS r0,r2,#1 +000108 f7fffffe BL motor_dir + |L7.268| +;;;286 } +;;;287 } +;;;288 /* 处理按键事件 */ +;;;289 ucKeyCode = bsp_GetKey(); +00010c f7fffffe BL bsp_GetKey +000110 4604 MOV r4,r0 +;;;290 +;;;291 if (ucKeyCode > 0) +000112 2c00 CMP r4,#0 +000114 dd0e BLE |L7.308| +;;;292 { +;;;293 /* 有键按下 */ +;;;294 switch (ucKeyCode) // key6 +000116 2c01 CMP r4,#1 +000118 d002 BEQ |L7.288| +00011a 2c04 CMP r4,#4 +00011c d108 BNE |L7.304| +00011e e002 B |L7.294| + |L7.288| +;;;295 { +;;;296 case KEY_DOWN_K6: // key6 短按 +;;;297 { +;;;298 MOTO_ZorePos(); +000120 f7fffffe BL MOTO_ZorePos +;;;299 break; +000124 e005 B |L7.306| + |L7.294| +;;;300 } +;;;301 +;;;302 case KEY_DOWN_K1: // Key1 短按 +;;;303 { +;;;304 BEEP_KeyTone(); // 按键提示音 +000126 f7fffffe BL BEEP_KeyTone +;;;305 bsp_ToogleDispMode(); +00012a f7fffffe BL bsp_ToogleDispMode +;;;306 break; +00012e e000 B |L7.306| + |L7.304| +;;;307 } +;;;308 +;;;309 default: +;;;310 break; +000130 bf00 NOP + |L7.306| +000132 bf00 NOP ;299 + |L7.308| +000134 e7c7 B |L7.198| +;;;311 } +;;;312 } +;;;313 } +;;;314 } +;;;315 + ENDP + +000136 0000 DCW 0x0000 + |L7.312| + DCD 0x08008000 + |L7.316| + DCD 0xe000ed08 + |L7.320| + DCD 0x40010800 + |L7.324| + DCD 0x40021000 + |L7.328| +000148 53595343 DCB "SYSCLK = HSI 8MHz\r\n",0 +00014c 4c4b203d +000150 20485349 +000154 20384d48 +000158 7a0d0a00 + |L7.348| +00015c 53595343 DCB "SYSCLK = HSE\r\n",0 +000160 4c4b203d +000164 20485345 +000168 0d0a00 +00016b 00 DCB 0 + |L7.364| +00016c 504c4c20 DCB "PLL MUL = %u, PLL = 8MHz * %u = %uMHz\r\n",0 +000170 4d554c20 +000174 3d202575 +000178 2c20504c +00017c 4c203d20 +000180 384d487a +000184 202a2025 +000188 75203d20 +00018c 25754d48 +000190 7a0d0a00 + |L7.404| + DCD SystemCoreClock + |L7.408| +000198 53797374 DCB "SystemCoreClock var = %lu\r\n",0 +00019c 656d436f +0001a0 7265436c +0001a4 6f636b20 +0001a8 76617220 +0001ac 3d20256c +0001b0 750d0a00 + |L7.436| +0001b4 5243432d DCB "RCC->CFGR = 0x%08lX, PPRE1=%lu\r\n",0 +0001b8 3e434647 +0001bc 52203d20 +0001c0 30782530 +0001c4 386c582c +0001c8 20505052 +0001cc 45313d25 +0001d0 6c750d0a +0001d4 00 +0001d5 00 DCB 0 +0001d6 00 DCB 0 +0001d7 00 DCB 0 + |L7.472| + DCD 0x40001000 + |L7.476| +0001dc 54494d36 DCB "TIM6 PSC = %u, ARR = %u\r\n",0 +0001e0 20505343 +0001e4 203d2025 +0001e8 752c2041 +0001ec 5252203d +0001f0 2025750d +0001f4 0a00 +0001f6 00 DCB 0 +0001f7 00 DCB 0 + |L7.504| + DCD g_tTube + |L7.508| + DCD Flag_100ms + + AREA ||i.motor_dir||, CODE, READONLY, ALIGN=2 + + motor_dir PROC +;;;165 +;;;166 void motor_dir(uint32_t freq, uint8_t _dir, int64_t _stpes) +000000 e92d41f0 PUSH {r4-r8,lr} +;;;167 { +000004 4607 MOV r7,r0 +000006 460c MOV r4,r1 +000008 4615 MOV r5,r2 +00000a 461e MOV r6,r3 +;;;168 // [r,1,1500,108288] +;;;169 +;;;170 if (g_tTube.state == WORK) +00000c 482b LDR r0,|L8.188| +00000e 7ac0 LDRB r0,[r0,#0xb] ; g_tTube +000010 2801 CMP r0,#1 +000012 d150 BNE |L8.182| +;;;171 { +;;;172 if (_dir == 1) +000014 2c01 CMP r4,#1 +000016 d117 BNE |L8.72| +;;;173 { +;;;174 _dir = 1; +000018 bf00 NOP +;;;175 if (g_tMoto.sv_pulse + 100 < INT64_MAX) +00001a 4929 LDR r1,|L8.192| +00001c e9d1010a LDRD r0,r1,[r1,#0x28] +000020 3064 ADDS r0,r0,#0x64 +000022 f1410100 ADC r1,r1,#0 +000026 f06f4200 MVN r2,#0x80000000 +00002a 4051 EORS r1,r1,r2 +00002c ea710000 ORNS r0,r1,r0 +000030 d020 BEQ |L8.116| +;;;176 g_tMoto.sv_pulse = g_tMoto.sv_pulse + 100; +000032 4823 LDR r0,|L8.192| +000034 e9d0300a LDRD r3,r0,[r0,#0x28] +000038 2264 MOVS r2,#0x64 +00003a 189a ADDS r2,r3,r2 +00003c f1400000 ADC r0,r0,#0 +000040 491f LDR r1,|L8.192| +000042 e9c1200a STRD r2,r0,[r1,#0x28] +000046 e015 B |L8.116| + |L8.72| +;;;177 } +;;;178 else if (_dir == 0) +000048 b9a4 CBNZ r4,|L8.116| +;;;179 { +;;;180 _dir = 0; +00004a 2400 MOVS r4,#0 +;;;181 if (g_tMoto.sv_pulse - 100 > INT64_MIN) +00004c 491c LDR r1,|L8.192| +00004e e9d1010a LDRD r0,r1,[r1,#0x28] +000052 3864 SUBS r0,r0,#0x64 +000054 f1610100 SBC r1,r1,#0 +000058 f04f4200 MOV r2,#0x80000000 +00005c 4051 EORS r1,r1,r2 +00005e 4308 ORRS r0,r0,r1 +000060 d008 BEQ |L8.116| +;;;182 g_tMoto.sv_pulse = g_tMoto.sv_pulse - 100; +000062 4817 LDR r0,|L8.192| +000064 e9d0200a LDRD r2,r0,[r0,#0x28] +000068 3a64 SUBS r2,r2,#0x64 +00006a f1600000 SBC r0,r0,#0 +00006e 4914 LDR r1,|L8.192| +000070 e9c1200a STRD r2,r0,[r1,#0x28] + |L8.116| +;;;183 } +;;;184 +;;;185 if (g_tMoto.pv_pulse < g_tMoto.sv_pulse) +000074 4812 LDR r0,|L8.192| +000076 e9d01008 LDRD r1,r0,[r0,#0x20] +00007a 4a11 LDR r2,|L8.192| +00007c e9d2320a LDRD r3,r2,[r2,#0x28] +000080 1ac9 SUBS r1,r1,r3 +000082 4190 SBCS r0,r0,r2 +000084 da07 BGE |L8.150| +;;;186 { +;;;187 +;;;188 if (g_tMoto.sv_pulse > INT64_MAX) +000086 bf00 NOP +;;;189 { +;;;190 g_tMoto.sv_pulse = INT64_MAX; +;;;191 } +;;;192 else if (g_tMoto.sv_pulse <= INT64_MAX) +;;;193 { +;;;194 MOTO_Start(1500, 0, 100); +000088 2264 MOVS r2,#0x64 +00008a 2100 MOVS r1,#0 +00008c f24050dc MOV r0,#0x5dc +000090 f7fffffe BL MOTO_Start +000094 e00f B |L8.182| + |L8.150| +;;;195 } +;;;196 } +;;;197 else if (g_tMoto.pv_pulse > g_tMoto.sv_pulse) +000096 480a LDR r0,|L8.192| +000098 e9d0200a LDRD r2,r0,[r0,#0x28] +00009c 4908 LDR r1,|L8.192| +00009e e9d13108 LDRD r3,r1,[r1,#0x20] +0000a2 1ad2 SUBS r2,r2,r3 +0000a4 4188 SBCS r0,r0,r1 +0000a6 da06 BGE |L8.182| +;;;198 { +;;;199 if (g_tMoto.sv_pulse < INT64_MIN) +0000a8 bf00 NOP +;;;200 { +;;;201 g_tMoto.sv_pulse = INT64_MIN; +;;;202 } +;;;203 else if (g_tMoto.sv_pulse >= INT64_MIN) +;;;204 { +;;;205 MOTO_Start(1500, 1, 100); +0000aa 2264 MOVS r2,#0x64 +0000ac 2101 MOVS r1,#1 +0000ae f24050dc MOV r0,#0x5dc +0000b2 f7fffffe BL MOTO_Start + |L8.182| +;;;206 } +;;;207 } +;;;208 } +;;;209 } +0000b6 e8bd81f0 POP {r4-r8,pc} +;;;210 int main(void) + ENDP + +0000ba 0000 DCW 0x0000 + |L8.188| + DCD g_tTube + |L8.192| + DCD g_tMoto + + AREA ||i.print_sys_info||, CODE, READONLY, ALIGN=2 + + REQUIRE _printf_percent + REQUIRE _printf_s + REQUIRE _printf_str + REQUIRE _printf_str + print_sys_info PROC +;;;321 +;;;322 void print_sys_info(void) +000000 b510 PUSH {r4,lr} +;;;323 { +;;;324 printf("\r\n"); +000002 a019 ADR r0,|L9.104| +000004 f7fffffe BL __2printf +;;;325 printf("----------------------------->\r\n"); +000008 a018 ADR r0,|L9.108| +00000a f7fffffe BL __2printf +;;;326 printf("-> 设备名称：无限旋转控制器\r\n"); +00000e a020 ADR r0,|L9.144| +000010 f7fffffe BL __2printf +;;;327 printf("-> software verson: V1.0\r\n"); +000014 a029 ADR r0,|L9.188| +000016 f7fffffe BL __2printf +;;;328 printf("-> compile time: %s\r\n", __TIME__); +00001a a12f ADR r1,|L9.216| +00001c a031 ADR r0,|L9.228| +00001e f7fffffe BL __2printf +;;;329 printf("-> compile date: %s\r\n", __DATE__); +000022 a136 ADR r1,|L9.252| +000024 a038 ADR r0,|L9.264| +000026 f7fffffe BL __2printf +;;;330 printf("-> [多场低温科技有限公司]\r\n"); +00002a a03d ADR r0,|L9.288| +00002c f7fffffe BL __2printf +;;;331 printf("------------------------------\r\n"); +000030 a045 ADR r0,|L9.328| +000032 f7fffffe BL __2printf +;;;332 printf("->可用命令：\r\n"); +000036 a04d ADR r0,|L9.364| +000038 f7fffffe BL __2printf +;;;333 printf("1. [s] // 停止电机转动\r\n"); +00003c a051 ADR r0,|L9.388| +00003e f7fffffe BL __2printf +;;;334 printf("2. [?] // 读取当前位置角度\r\n"); +000042 a058 ADR r0,|L9.420| +000044 f7fffffe BL __2printf +;;;335 printf("3. [z] // 设置当前位置为零点\r\n"); +000048 a060 ADR r0,|L9.460| +00004a f7fffffe BL __2printf +;;;336 printf("4. [MF] // 打印系统信息\r\n"); +00004e a06a ADR r0,|L9.504| +000050 f7fffffe BL __2printf +;;;337 printf("5. [r:10:360] // 转动命令，10为转动角速度，360为目标角度\r\n"); +000054 4870 LDR r0,|L9.536| +000056 f7fffffe BL __2printf +;;;338 printf("6. [rr:10:20] // 转动命令，10为转动角速度，20为相对转动角度\r\n"); +00005a 4870 LDR r0,|L9.540| +00005c f7fffffe BL __2printf +;;;339 printf("<-----------------------------\r\n"); +000060 a06f ADR r0,|L9.544| +000062 f7fffffe BL __2printf +;;;340 } +000066 bd10 POP {r4,pc} +;;;341 + ENDP + + |L9.104| +000068 0d0a00 DCB "\r\n",0 +00006b 00 DCB 0 + |L9.108| +00006c 2d2d2d2d DCB "----------------------------->\r\n",0 +000070 2d2d2d2d +000074 2d2d2d2d +000078 2d2d2d2d +00007c 2d2d2d2d +000080 2d2d2d2d +000084 2d2d2d2d +000088 2d3e0d0a +00008c 00 +00008d 00 DCB 0 +00008e 00 DCB 0 +00008f 00 DCB 0 + |L9.144| +000090 2d3e20e8 DCB "-> ",232,174,190,229,164,135,229,144,141,231,167,176,239 +000094 aebee5a4 +000098 87e5908d +00009c e7a7b0ef +0000a0 bc9ae697 DCB 188,154,230,151,160,233,153,144,230,151,139,232,189,172,230 +0000a4 a0e99990 +0000a8 e6978be8 +0000ac bdace6 +0000af 8ea7e588 DCB 142,167,229,136,182,229,153,168,"\r\n",0 +0000b3 b6e599a8 +0000b7 0d0a00 +0000ba 00 DCB 0 +0000bb 00 DCB 0 + |L9.188| +0000bc 2d3e2073 DCB "-> software verson: V1.0\r\n",0 +0000c0 6f667477 +0000c4 61726520 +0000c8 76657273 +0000cc 6f6e3a20 +0000d0 56312e30 +0000d4 0d0a00 +0000d7 00 DCB 0 + |L9.216| +0000d8 31363a32 DCB "16:27:16",0 +0000dc 373a3136 +0000e0 00 +0000e1 00 DCB 0 +0000e2 00 DCB 0 +0000e3 00 DCB 0 + |L9.228| +0000e4 2d3e2063 DCB "-> compile time: %s\r\n",0 +0000e8 6f6d7069 +0000ec 6c652074 +0000f0 696d653a +0000f4 2025730d +0000f8 0a00 +0000fa 00 DCB 0 +0000fb 00 DCB 0 + |L9.252| +0000fc 41707220 DCB "Apr 16 2026",0 +000100 31362032 +000104 30323600 + |L9.264| +000108 2d3e2063 DCB "-> compile date: %s\r\n",0 +00010c 6f6d7069 +000110 6c652064 +000114 6174653a +000118 2025730d +00011c 0a00 +00011e 00 DCB 0 +00011f 00 DCB 0 + |L9.288| +000120 2d3e205b DCB "-> [",229,164,154,229,156,186,228,189,142,230,184,169,231 +000124 e5a49ae5 +000128 9cbae4bd +00012c 8ee6b8a9 +000130 e7 +000131 a791e68a DCB 167,145,230,138,128,230,156,137,233,153,144,229,133,172,229 +000135 80e69c89 +000139 e99990e5 +00013d 85ace5 +000140 8fb85d0d DCB 143,184,"]\r\n",0 +000144 0a00 +000146 00 DCB 0 +000147 00 DCB 0 + |L9.328| +000148 2d2d2d2d DCB "------------------------------\r\n",0 +00014c 2d2d2d2d +000150 2d2d2d2d +000154 2d2d2d2d +000158 2d2d2d2d +00015c 2d2d2d2d +000160 2d2d2d2d +000164 2d2d0d0a +000168 00 +000169 00 DCB 0 +00016a 00 DCB 0 +00016b 00 DCB 0 + |L9.364| +00016c 2d3ee58f DCB "->",229,143,175,231,148,168,229,145,189,228,187,164,239 +000170 afe794a8 +000174 e591bde4 +000178 bba4ef +00017b bc9a5c72 DCB 188,154,"\\r\n",0 +00017f 0a00 +000181 00 DCB 0 +000182 00 DCB 0 +000183 00 DCB 0 + |L9.388| +000184 312e205b DCB "1. [s] // ",229,129,156,230,173,162,231,148,181,230,156 +000188 735d2020 +00018c 2f2f20e5 +000190 819ce6ad +000194 a2e794b5 +000198 e69c +00019a bae8bdac DCB 186,232,189,172,229,138,168,"\r\n",0 +00019e e58aa80d +0001a2 0a00 + |L9.420| +0001a4 322e205b DCB "2. [?] // ",232,175,187,229,143,150,229,189,147,229,137 +0001a8 3f5d2020 +0001ac 2f2f20e8 +0001b0 afbbe58f +0001b4 96e5bd93 +0001b8 e589 +0001ba 8de4bd8d DCB 141,228,189,141,231,189,174,232,167,146,229,186,166,"\r\n" +0001be e7bdaee8 +0001c2 a792e5ba +0001c6 a60d0a +0001c9 00 DCB 0 +0001ca 00 DCB 0 +0001cb 00 DCB 0 + |L9.460| +0001cc 332e205b DCB "3. [z] // ",232,174,190,231,189,174,229,189,147,229,137 +0001d0 7a5d2020 +0001d4 2f2f20e8 +0001d8 aebee7bd +0001dc aee5bd93 +0001e0 e589 +0001e2 8de4bd8d DCB 141,228,189,141,231,189,174,228,184,186,233,155,182,231,130 +0001e6 e7bdaee4 +0001ea b8bae99b +0001ee b6e782 +0001f1 b95c720a DCB 185,"\\r\n",0 +0001f5 00 +0001f6 00 DCB 0 +0001f7 00 DCB 0 + |L9.504| +0001f8 342e205b DCB "4. [MF] // ",230,137,147,229,141,176,231,179,187,231,187 +0001fc 4d465d20 +000200 2f2f20e6 +000204 8993e58d +000208 b0e7b3bb +00020c e7bb +00020e 9fe4bfa1 DCB 159,228,191,161,230,129,175,"\r\n",0 +000212 e681af0d +000216 0a00 + |L9.536| + DCD ||.conststring|| + |L9.540| + DCD ||.conststring||+0x50 + |L9.544| +000220 3c2d2d2d DCB "<-----------------------------\r\n",0 +000224 2d2d2d2d +000228 2d2d2d2d +00022c 2d2d2d2d +000230 2d2d2d2d +000234 2d2d2d2d +000238 2d2d2d2d +00023c 2d2d0d0a +000240 00 +000241 00 DCB 0 +000242 00 DCB 0 +000243 00 DCB 0 + + AREA ||i.send_sv_2_uart||, CODE, READONLY, ALIGN=2 + + REQUIRE _printf_percent + REQUIRE _printf_widthprec + REQUIRE _printf_f + REQUIRE _printf_fp_dec + send_sv_2_uart PROC +;;;315 +;;;316 void send_sv_2_uart(void) +000000 b570 PUSH {r4-r6,lr} +;;;317 { +;;;318 float angle = g_tTube.pulse * 360.0f / STEP_PER_LAP; // 22 * 16 * 24 +000002 490b LDR r1,|L10.48| +000004 6908 LDR r0,[r1,#0x10] ; g_tTube +000006 f7fffffe BL __aeabi_i2f +00000a 4606 MOV r6,r0 +00000c 4909 LDR r1,|L10.52| +00000e f7fffffe BL __aeabi_fmul +000012 4605 MOV r5,r0 +000014 4908 LDR r1,|L10.56| +000016 f7fffffe BL __aeabi_fdiv +00001a 4604 MOV r4,r0 +;;;319 printf("[w,%.2f]\r\n", angle); +00001c 4620 MOV r0,r4 +00001e f7fffffe BL __aeabi_f2d +000022 4605 MOV r5,r0 +000024 462a MOV r2,r5 +000026 460b MOV r3,r1 +000028 a004 ADR r0,|L10.60| +00002a f7fffffe BL __2printf +;;;320 } +00002e bd70 POP {r4-r6,pc} +;;;321 + ENDP + + |L10.48| + DCD g_tTube + |L10.52| + DCD 0x43b40000 + |L10.56| + DCD 0x46043400 + |L10.60| +00003c 5b772c25 DCB "[w,%.2f]\r\n",0 +000040 2e32665d +000044 0d0a00 +000047 00 DCB 0 + + AREA ||i.uart_msg_idle||, CODE, READONLY, ALIGN=2 + + REQUIRE _scanf_real + REQUIRE _printf_sizespec + REQUIRE _printf_percent + REQUIRE _printf_d + REQUIRE _printf_u + REQUIRE _printf_lld + REQUIRE _printf_f + REQUIRE _printf_int_dec + REQUIRE _printf_longlong_dec + REQUIRE _printf_fp_dec + uart_msg_idle PROC +;;;341 +;;;342 void uart_msg_idle(void) +000000 e92d43f0 PUSH {r4-r9,lr} +;;;343 { +000004 b087 SUB sp,sp,#0x1c +;;;344 uint8_t n = 0; +000006 2400 MOVS r4,#0 +;;;345 float freq = 0; +000008 2000 MOVS r0,#0 +00000a 9006 STR r0,[sp,#0x18] +;;;346 float pulse = 0; +00000c 2500 MOVS r5,#0 +;;;347 float angle = 0; +00000e 9005 STR r0,[sp,#0x14] +;;;348 +;;;349 if (g_ucRxRcvNewFlag) +000010 48a1 LDR r0,|L11.664| +000012 7800 LDRB r0,[r0,#0] ; g_ucRxRcvNewFlag +000014 2800 CMP r0,#0 +000016 d01b BEQ |L11.80| +;;;350 { +;;;351 g_ucRxRcvNewFlag = 0; +000018 2000 MOVS r0,#0 +00001a 499f LDR r1,|L11.664| +00001c 7008 STRB r0,[r1,#0] +;;;352 +;;;353 n = strlen((char *)g_RxBuf); +00001e 489f LDR r0,|L11.668| +000020 f7fffffe BL strlen +000024 b2c4 UXTB r4,r0 +;;;354 if (n == 3) +000026 2c03 CMP r4,#3 +000028 d113 BNE |L11.82| +;;;355 { +;;;356 switch (g_RxBuf[1]) +00002a 489c LDR r0,|L11.668| +00002c 7840 LDRB r0,[r0,#1] ; g_RxBuf +00002e 283f CMP r0,#0x3f +000030 d004 BEQ |L11.60| +000032 2873 CMP r0,#0x73 +000034 d005 BEQ |L11.66| +000036 287a CMP r0,#0x7a +000038 d109 BNE |L11.78| +00003a e005 B |L11.72| + |L11.60| +;;;357 { +;;;358 case '?': +;;;359 send_sv_2_uart(); +00003c f7fffffe BL send_sv_2_uart +;;;360 break; +000040 e006 B |L11.80| + |L11.66| +;;;361 case 's': +;;;362 MOTO_Stop(); +000042 f7fffffe BL MOTO_Stop +;;;363 break; +000046 e003 B |L11.80| + |L11.72| +;;;364 case 'z': +;;;365 MOTO_ZorePos(); +000048 f7fffffe BL MOTO_ZorePos +;;;366 break; +00004c e000 B |L11.80| + |L11.78| +;;;367 default: +;;;368 break; +00004e bf00 NOP + |L11.80| +000050 e11e B |L11.656| + |L11.82| +;;;369 } +;;;370 } +;;;371 else if (n == 4) +000052 2c04 CMP r4,#4 +000054 d10a BNE |L11.108| +;;;372 { +;;;373 if (IS_MF_VALID) +000056 4891 LDR r0,|L11.668| +000058 7840 LDRB r0,[r0,#1] ; g_RxBuf +00005a 284d CMP r0,#0x4d +00005c d1f8 BNE |L11.80| +00005e 488f LDR r0,|L11.668| +000060 7880 LDRB r0,[r0,#2] ; g_RxBuf +000062 2846 CMP r0,#0x46 +000064 d1f4 BNE |L11.80| +;;;374 { +;;;375 print_sys_info(); +000066 f7fffffe BL print_sys_info +00006a e111 B |L11.656| + |L11.108| +;;;376 } +;;;377 } +;;;378 else if (g_RxBuf[1] == 'r') +00006c 488b LDR r0,|L11.668| +00006e 7840 LDRB r0,[r0,#1] ; g_RxBuf +000070 2872 CMP r0,#0x72 +000072 d178 BNE |L11.358| +;;;379 { +;;;380 // [r,10,100] // 10°/s 转到100° +;;;381 if (sscanf((char *)g_RxBuf, "[r:%f:%f]", &freq, &angle) == 2) +000074 ab05 ADD r3,sp,#0x14 +000076 aa06 ADD r2,sp,#0x18 +000078 a189 ADR r1,|L11.672| +00007a 4888 LDR r0,|L11.668| +00007c f7fffffe BL __0sscanf +000080 2802 CMP r0,#2 +000082 d176 BNE |L11.370| +;;;382 { +;;;383 if (freq < 0.01f) +000084 4989 LDR r1,|L11.684| +000086 9806 LDR r0,[sp,#0x18] +000088 f7fffffe BL __aeabi_cfcmple +00008c d202 BCS |L11.148| +;;;384 freq = 0.01f; +00008e 4887 LDR r0,|L11.684| +000090 9006 STR r0,[sp,#0x18] +000092 e006 B |L11.162| + |L11.148| +;;;385 else if (freq > MAX_SPEED) +000094 4986 LDR r1,|L11.688| +000096 9806 LDR r0,[sp,#0x18] +000098 f7fffffe BL __aeabi_cfrcmple +00009c d201 BCS |L11.162| +;;;386 freq = MAX_SPEED; +00009e 4884 LDR r0,|L11.688| +0000a0 9006 STR r0,[sp,#0x18] + |L11.162| +;;;387 pulse = (angle / 360) * STEP_PER_LAP; // angle所有需要的脉冲 +0000a2 4984 LDR r1,|L11.692| +0000a4 9805 LDR r0,[sp,#0x14] +0000a6 f7fffffe BL __aeabi_fdiv +0000aa 4606 MOV r6,r0 +0000ac 4982 LDR r1,|L11.696| +0000ae f7fffffe BL __aeabi_fmul +0000b2 4605 MOV r5,r0 +;;;388 freq = freq * (STEP_PER_LAP / 360.0f); // 角速度所需要的脉冲频率 +0000b4 4981 LDR r1,|L11.700| +0000b6 9806 LDR r0,[sp,#0x18] +0000b8 f7fffffe BL __aeabi_fmul +0000bc 9006 STR r0,[sp,#0x18] +;;;389 g_tMoto.sv_pulse = (int64_t)pulse; +0000be 4628 MOV r0,r5 +0000c0 f7fffffe BL __aeabi_f2lz +0000c4 4a7e LDR r2,|L11.704| +0000c6 e9c2010a STRD r0,r1,[r2,#0x28] +;;;390 +;;;391 printf("[r] freq=%lu, angle=%f, pulse=%ld, sv_pulse=%lld\r\n", (unsigned long)freq, angle, (long)pulse, g_tMoto.sv_pulse); +0000ca 4628 MOV r0,r5 +0000cc f7fffffe BL __aeabi_f2iz +0000d0 4606 MOV r6,r0 +0000d2 9805 LDR r0,[sp,#0x14] +0000d4 f7fffffe BL __aeabi_f2d +0000d8 4607 MOV r7,r0 +0000da 4688 MOV r8,r1 +0000dc 9806 LDR r0,[sp,#0x18] +0000de f7fffffe BL __aeabi_f2uiz +0000e2 4681 MOV r9,r0 +0000e4 4876 LDR r0,|L11.704| +0000e6 6ac1 LDR r1,[r0,#0x2c] ; g_tMoto +0000e8 6a80 LDR r0,[r0,#0x28] ; g_tMoto +0000ea 463a MOV r2,r7 +0000ec 4643 MOV r3,r8 +0000ee 9600 STR r6,[sp,#0] +0000f0 e9cd0102 STRD r0,r1,[sp,#8] +0000f4 4649 MOV r1,r9 +0000f6 a073 ADR r0,|L11.708| +0000f8 f7fffffe BL __2printf +;;;392 printf("TIM6 before start: PSC=%u, ARR=%u\r\n", TIM6->PSC, TIM6->ARR); +0000fc 487e LDR r0,|L11.760| +0000fe 8d82 LDRH r2,[r0,#0x2c] +000100 8d01 LDRH r1,[r0,#0x28] +000102 a07e ADR r0,|L11.764| +000104 f7fffffe BL __2printf +;;;393 +;;;394 if (g_tMoto.pv_pulse < g_tMoto.sv_pulse) +000108 486d LDR r0,|L11.704| +00010a e9d03008 LDRD r3,r0,[r0,#0x20] +00010e 4a6c LDR r2,|L11.704| +000110 e9d2120a LDRD r1,r2,[r2,#0x28] +000114 1a59 SUBS r1,r3,r1 +000116 4190 SBCS r0,r0,r2 +000118 da08 BGE |L11.300| +;;;395 { +;;;396 MOTO_Start(freq, 0, 123); +00011a 9806 LDR r0,[sp,#0x18] +00011c f7fffffe BL __aeabi_f2uiz +000120 4606 MOV r6,r0 +000122 227b MOVS r2,#0x7b +000124 2100 MOVS r1,#0 +000126 f7fffffe BL MOTO_Start +00012a e018 B |L11.350| + |L11.300| +;;;397 } +;;;398 else if (g_tMoto.pv_pulse > g_tMoto.sv_pulse) +00012c 4864 LDR r0,|L11.704| +00012e e9d0100a LDRD r1,r0,[r0,#0x28] +000132 4b63 LDR r3,|L11.704| +000134 e9d32308 LDRD r2,r3,[r3,#0x20] +000138 1a89 SUBS r1,r1,r2 +00013a 4198 SBCS r0,r0,r3 +00013c da08 BGE |L11.336| +;;;399 { +;;;400 MOTO_Start(freq, 1, 123); +00013e 9806 LDR r0,[sp,#0x18] +000140 f7fffffe BL __aeabi_f2uiz +000144 4606 MOV r6,r0 +000146 227b MOVS r2,#0x7b +000148 2101 MOVS r1,#1 +00014a f7fffffe BL MOTO_Start +00014e e006 B |L11.350| + |L11.336| +;;;401 } +;;;402 else +;;;403 { +;;;404 BEEP_Start(1500, 5, 5, 3); +000150 2303 MOVS r3,#3 +000152 2205 MOVS r2,#5 +000154 4611 MOV r1,r2 +000156 f24050dc MOV r0,#0x5dc +00015a f7fffffe BL BEEP_Start + |L11.350| +;;;405 } +;;;406 printf("TIM6 after start: PSC=%u, ARR=%u\r\n", TIM6->PSC, TIM6->ARR); +00015e 4866 LDR r0,|L11.760| +000160 8d82 LDRH r2,[r0,#0x2c] +000162 8d01 LDRH r1,[r0,#0x28] +000164 e001 B |L11.362| + |L11.358| +000166 e08c B |L11.642| +000168 e003 B |L11.370| + |L11.362| +00016a a06d ADR r0,|L11.800| +00016c f7fffffe BL __2printf +000170 e08e B |L11.656| + |L11.370| +;;;407 } +;;;408 else if (sscanf((char *)g_RxBuf, "[rr:%f:%f]", &freq, &angle) == 2) +000172 ab05 ADD r3,sp,#0x14 +000174 aa06 ADD r2,sp,#0x18 +000176 a173 ADR r1,|L11.836| +000178 4848 LDR r0,|L11.668| +00017a f7fffffe BL __0sscanf +00017e 2802 CMP r0,#2 +000180 d177 BNE |L11.626| +;;;409 { +;;;410 if (pulse < 0.01f) +000182 494a LDR r1,|L11.684| +000184 4628 MOV r0,r5 +000186 f7fffffe BL __aeabi_cfcmple +00018a d201 BCS |L11.400| +;;;411 pulse = 0.01f; +00018c 4d47 LDR r5,|L11.684| +00018e e005 B |L11.412| + |L11.400| +;;;412 else if (pulse > MAX_SPEED) +000190 4947 LDR r1,|L11.688| +000192 4628 MOV r0,r5 +000194 f7fffffe BL __aeabi_cfrcmple +000198 d200 BCS |L11.412| +;;;413 pulse = MAX_SPEED; +00019a 4d45 LDR r5,|L11.688| + |L11.412| +;;;414 pulse = (angle / 360) * STEP_PER_LAP; // angle所有需要的脉冲 +00019c 4945 LDR r1,|L11.692| +00019e 9805 LDR r0,[sp,#0x14] +0001a0 f7fffffe BL __aeabi_fdiv +0001a4 4606 MOV r6,r0 +0001a6 4944 LDR r1,|L11.696| +0001a8 f7fffffe BL __aeabi_fmul +0001ac 4605 MOV r5,r0 +;;;415 freq = freq * (STEP_PER_LAP / 360.0f); // 角速度所需要的脉冲频率 +0001ae 4943 LDR r1,|L11.700| +0001b0 9806 LDR r0,[sp,#0x18] +0001b2 f7fffffe BL __aeabi_fmul +0001b6 9006 STR r0,[sp,#0x18] +;;;416 g_tMoto.sv_pulse += (int64_t)pulse; +0001b8 4628 MOV r0,r5 +0001ba f7fffffe BL __aeabi_f2lz +0001be 4a40 LDR r2,|L11.704| +0001c0 e9d2320a LDRD r3,r2,[r2,#0x28] +0001c4 18c0 ADDS r0,r0,r3 +0001c6 4151 ADCS r1,r1,r2 +0001c8 4a3d LDR r2,|L11.704| +0001ca e9c2010a STRD r0,r1,[r2,#0x28] +;;;417 +;;;418 printf("[rr] freq=%lu, angle=%f, pulse=%ld, sv_pulse=%lld\r\n", (unsigned long)freq, angle, (long)pulse, g_tMoto.sv_pulse); +0001ce 4628 MOV r0,r5 +0001d0 f7fffffe BL __aeabi_f2iz +0001d4 4606 MOV r6,r0 +0001d6 9805 LDR r0,[sp,#0x14] +0001d8 f7fffffe BL __aeabi_f2d +0001dc 4607 MOV r7,r0 +0001de 4688 MOV r8,r1 +0001e0 9806 LDR r0,[sp,#0x18] +0001e2 f7fffffe BL __aeabi_f2uiz +0001e6 4681 MOV r9,r0 +0001e8 4835 LDR r0,|L11.704| +0001ea 6ac1 LDR r1,[r0,#0x2c] ; g_tMoto +0001ec 6a80 LDR r0,[r0,#0x28] ; g_tMoto +0001ee 463a MOV r2,r7 +0001f0 4643 MOV r3,r8 +0001f2 9600 STR r6,[sp,#0] +0001f4 e9cd0102 STRD r0,r1,[sp,#8] +0001f8 4649 MOV r1,r9 +0001fa a055 ADR r0,|L11.848| +0001fc f7fffffe BL __2printf +;;;419 printf("TIM6 before start: PSC=%u, ARR=%u\r\n", TIM6->PSC, TIM6->ARR); +000200 483d LDR r0,|L11.760| +000202 8d82 LDRH r2,[r0,#0x2c] +000204 8d01 LDRH r1,[r0,#0x28] +000206 a03d ADR r0,|L11.764| +000208 f7fffffe BL __2printf +;;;420 +;;;421 if (g_tMoto.pv_pulse < g_tMoto.sv_pulse) +00020c 482c LDR r0,|L11.704| +00020e e9d01008 LDRD r1,r0,[r0,#0x20] +000212 4a2b LDR r2,|L11.704| +000214 e9d2320a LDRD r3,r2,[r2,#0x28] +000218 1ac9 SUBS r1,r1,r3 +00021a 4190 SBCS r0,r0,r2 +00021c da08 BGE |L11.560| +;;;422 { +;;;423 MOTO_Start(freq, 0, 123); +00021e 9806 LDR r0,[sp,#0x18] +000220 f7fffffe BL __aeabi_f2uiz +000224 4606 MOV r6,r0 +000226 227b MOVS r2,#0x7b +000228 2100 MOVS r1,#0 +00022a f7fffffe BL MOTO_Start +00022e e018 B |L11.610| + |L11.560| +;;;424 } +;;;425 else if (g_tMoto.pv_pulse > g_tMoto.sv_pulse) +000230 4823 LDR r0,|L11.704| +000232 e9d0100a LDRD r1,r0,[r0,#0x28] +000236 4a22 LDR r2,|L11.704| +000238 e9d23208 LDRD r3,r2,[r2,#0x20] +00023c 1ac9 SUBS r1,r1,r3 +00023e 4190 SBCS r0,r0,r2 +000240 da08 BGE |L11.596| +;;;426 { +;;;427 MOTO_Start(freq, 1, 123); +000242 9806 LDR r0,[sp,#0x18] +000244 f7fffffe BL __aeabi_f2uiz +000248 4606 MOV r6,r0 +00024a 227b MOVS r2,#0x7b +00024c 2101 MOVS r1,#1 +00024e f7fffffe BL MOTO_Start +000252 e006 B |L11.610| + |L11.596| +;;;428 } +;;;429 else +;;;430 { +;;;431 BEEP_Start(1500, 5, 5, 3); +000254 2303 MOVS r3,#3 +000256 2205 MOVS r2,#5 +000258 4611 MOV r1,r2 +00025a f24050dc MOV r0,#0x5dc +00025e f7fffffe BL BEEP_Start + |L11.610| +;;;432 } +;;;433 printf("TIM6 after start: PSC=%u, ARR=%u\r\n", TIM6->PSC, TIM6->ARR); +000262 4825 LDR r0,|L11.760| +000264 8d82 LDRH r2,[r0,#0x2c] +000266 8d01 LDRH r1,[r0,#0x28] +000268 a02d ADR r0,|L11.800| +00026a f7fffffe BL __2printf +00026e e00f B |L11.656| +000270 e7ff B |L11.626| + |L11.626| +;;;434 } +;;;435 else +;;;436 { +;;;437 BEEP_Start(1500, 5, 5, 3); +000272 2303 MOVS r3,#3 +000274 2205 MOVS r2,#5 +000276 4611 MOV r1,r2 +000278 f24050dc MOV r0,#0x5dc +00027c f7fffffe BL BEEP_Start +000280 e006 B |L11.656| + |L11.642| +;;;438 } +;;;439 } +;;;440 else +;;;441 { +;;;442 BEEP_Start(1500, 5, 5, 3); +000282 2303 MOVS r3,#3 +000284 2205 MOVS r2,#5 +000286 4611 MOV r1,r2 +000288 f24050dc MOV r0,#0x5dc +00028c f7fffffe BL BEEP_Start + |L11.656| +;;;443 } +;;;444 } +;;;445 } +000290 b007 ADD sp,sp,#0x1c +000292 e8bd83f0 POP {r4-r9,pc} +;;;446 + ENDP + +000296 0000 DCW 0x0000 + |L11.664| + DCD g_ucRxRcvNewFlag + |L11.668| + DCD g_RxBuf + |L11.672| +0002a0 5b723a25 DCB "[r:%f:%f]",0 +0002a4 663a2566 +0002a8 5d00 +0002aa 00 DCB 0 +0002ab 00 DCB 0 + |L11.684| + DCD 0x3c23d70a + |L11.688| + DCD 0x43c80000 + |L11.692| + DCD 0x43b40000 + |L11.696| + DCD 0x46043400 + |L11.700| + DCD 0x41bc05b0 + |L11.704| + DCD g_tMoto + |L11.708| +0002c4 5b725d20 DCB "[r] freq=%lu, angle=%f, pulse=%ld, sv_pulse=%lld\r\n",0 +0002c8 66726571 +0002cc 3d256c75 +0002d0 2c20616e +0002d4 676c653d +0002d8 25662c20 +0002dc 70756c73 +0002e0 653d256c +0002e4 642c2073 +0002e8 765f7075 +0002ec 6c73653d +0002f0 256c6c64 +0002f4 0d0a00 +0002f7 00 DCB 0 + |L11.760| + DCD 0x40001000 + |L11.764| +0002fc 54494d36 DCB "TIM6 before start: PSC=%u, ARR=%u\r\n",0 +000300 20626566 +000304 6f726520 +000308 73746172 +00030c 743a2050 +000310 53433d25 +000314 752c2041 +000318 52523d25 +00031c 750d0a00 + |L11.800| +000320 54494d36 DCB "TIM6 after start: PSC=%u, ARR=%u\r\n",0 +000324 20616674 +000328 65722073 +00032c 74617274 +000330 3a205053 +000334 433d2575 +000338 2c204152 +00033c 523d2575 +000340 0d0a00 +000343 00 DCB 0 + |L11.836| +000344 5b72723a DCB "[rr:%f:%f]",0 +000348 25663a25 +00034c 665d00 +00034f 00 DCB 0 + |L11.848| +000350 5b72725d DCB "[rr] freq=%lu, angle=%f, pulse=%ld, sv_pulse=%lld\r\n",0 +000354 20667265 +000358 713d256c +00035c 752c2061 +000360 6e676c65 +000364 3d25662c +000368 2070756c +00036c 73653d25 +000370 6c642c20 +000374 73765f70 +000378 756c7365 +00037c 3d256c6c +000380 640d0a00 + + AREA ||.conststring||, DATA, READONLY, MERGE=1, STRINGS, ALIGN=2 + +000000 352e205b DCB "5. [r:10:360] // ",232,189,172,229,138,168,229,145,189,228 +000004 723a3130 +000008 3a333630 +00000c 5d202f2f +000010 20e8bdac +000014 e58aa8e5 +000018 91bde4 +00001b bba4efbc DCB 187,164,239,188,140,"10",228,184,186,232,189,172,229,138 +00001f 8c3130e4 +000023 b8bae8bd +000027 ace58a +00002a a8e8a792 DCB 168,232,167,146,233,128,159,229,186,166,239,188,140,"360" +00002e e9809fe5 +000032 baa6efbc +000036 8c333630 +00003a e4b8bae7 DCB 228,184,186,231,155,174,230,160,135,232,167,146,229,186,166 +00003e 9baee6a0 +000042 87e8a792 +000046 e5baa6 +000049 5c720a00 DCB "\\r\n",0 +00004d 00 DCB 0 +00004e 00 DCB 0 +00004f 00 DCB 0 +000050 362e205b DCB "6. [rr:10:20] // ",232,189,172,229,138,168,229,145,189,228 +000054 72723a31 +000058 303a3230 +00005c 5d202f2f +000060 20e8bdac +000064 e58aa8e5 +000068 91bde4 +00006b bba4efbc DCB 187,164,239,188,140,"10",228,184,186,232,189,172,229,138 +00006f 8c3130e4 +000073 b8bae8bd +000077 ace58a +00007a a8e8a792 DCB 168,232,167,146,233,128,159,229,186,166,239,188,140,"20",228 +00007e e9809fe5 +000082 baa6efbc +000086 8c3230e4 +00008a b8bae79b DCB 184,186,231,155,184,229,175,185,232,189,172,229,138,168,232 +00008e b8e5afb9 +000092 e8bdace5 +000096 8aa8e8 +000099 a792e5ba DCB 167,146,229,186,166,"\\r\n",0 +00009d a65c720a +0000a1 00 + + AREA ||.data||, DATA, ALIGN=0 + + Flag_100ms +000000 00 DCB 0x00 + +;*** Start embedded assembler *** + +#line 1 "..\\..\\User\\app\\src\\main.c" + AREA ||.rev16_text||, CODE + THUMB + EXPORT |__asm___6_main_c_34afbc26____REV16| +#line 114 "..\\..\\Libraries\\CMSIS\\Include\\core_cmInstr.h" +|__asm___6_main_c_34afbc26____REV16| PROC +#line 115 + + rev16 r0, r0 + bx lr + ENDP + AREA ||.revsh_text||, CODE + THUMB + EXPORT |__asm___6_main_c_34afbc26____REVSH| +#line 128 +|__asm___6_main_c_34afbc26____REVSH| PROC +#line 129 + + revsh r0, r0 + bx lr + ENDP + +;*** End embedded assembler *** + + __ARM_use_no_argv EQU 0 diff --git a/Project/MDK-ARM/Flash/List/misc.txt b/Project/MDK-ARM/Flash/List/misc.txt new file mode 100644 index 0000000..92f8026 --- /dev/null +++ b/Project/MDK-ARM/Flash/List/misc.txt @@ -0,0 +1,249 @@ +; generated by Component: ARM Compiler 5.06 update 7 (build 960) Tool: ArmCC [4d365d] +; commandline ArmCC [--list --split_sections --debug -c --asm --interleave -o.\flash\obj\misc.o --asm_dir=.\Flash\List\ --list_dir=.\Flash\List\ --depend=.\flash\obj\misc.d --cpu=Cortex-M3 --apcs=interwork -O0 --diag_suppress=9931,870 -I..\..\Libraries\CMSIS\Device\ST\STM32F10x\Include -I..\..\Libraries\STM32F10x_StdPeriph_Driver\inc -I..\..\Libraries\STM32_USB-FS-Device_Driver\inc -I..\..\Libraries\CMSIS\Include -I..\..\User\bsp -I..\..\User\bsp\inc -I..\..\User\app\inc -I..\..\User -IC:\Users\w1619\AppData\Local\Arm\Packs\Keil\STM32F1xx_DFP\2.4.1\Device\Include -D__MICROLIB -D__UVISION_VERSION=538 -DSTM32F10X_HD -DUSE_STDPERIPH_DRIVER -DSTM32F10X_HD --omf_browse=.\flash\obj\misc.crf ..\..\Libraries\STM32F10x_StdPeriph_Driver\src\misc.c] + THUMB + + AREA ||i.NVIC_Init||, CODE, READONLY, ALIGN=2 + + NVIC_Init PROC +;;;117 */ +;;;118 void NVIC_Init(NVIC_InitTypeDef* NVIC_InitStruct) +000000 b570 PUSH {r4-r6,lr} +;;;119 { +;;;120 uint32_t tmppriority = 0x00, tmppre = 0x00, tmpsub = 0x0F; +000002 2100 MOVS r1,#0 +000004 2300 MOVS r3,#0 +000006 220f MOVS r2,#0xf +;;;121 +;;;122 /* Check the parameters */ +;;;123 assert_param(IS_FUNCTIONAL_STATE(NVIC_InitStruct->NVIC_IRQChannelCmd)); +;;;124 assert_param(IS_NVIC_PREEMPTION_PRIORITY(NVIC_InitStruct->NVIC_IRQChannelPreemptionPriority)); +;;;125 assert_param(IS_NVIC_SUB_PRIORITY(NVIC_InitStruct->NVIC_IRQChannelSubPriority)); +;;;126 +;;;127 if (NVIC_InitStruct->NVIC_IRQChannelCmd != DISABLE) +000008 78c4 LDRB r4,[r0,#3] +00000a b304 CBZ r4,|L1.78| +;;;128 { +;;;129 /* Compute the Corresponding IRQ Priority --------------------------------*/ +;;;130 tmppriority = (0x700 - ((SCB->AIRCR) & (uint32_t)0x700))>> 0x08; +00000c 4c15 LDR r4,|L1.100| +00000e 6824 LDR r4,[r4,#0] +000010 f40464e0 AND r4,r4,#0x700 +000014 f5c464e0 RSB r4,r4,#0x700 +000018 0a21 LSRS r1,r4,#8 +;;;131 tmppre = (0x4 - tmppriority); +00001a f1c10304 RSB r3,r1,#4 +;;;132 tmpsub = tmpsub >> tmppriority; +00001e 40ca LSRS r2,r2,r1 +;;;133 +;;;134 tmppriority = (uint32_t)NVIC_InitStruct->NVIC_IRQChannelPreemptionPriority << tmppre; +000020 7844 LDRB r4,[r0,#1] +000022 fa04f103 LSL r1,r4,r3 +;;;135 tmppriority |= NVIC_InitStruct->NVIC_IRQChannelSubPriority & tmpsub; +000026 7884 LDRB r4,[r0,#2] +000028 4014 ANDS r4,r4,r2 +00002a 4321 ORRS r1,r1,r4 +;;;136 tmppriority = tmppriority << 0x04; +00002c 0109 LSLS r1,r1,#4 +;;;137 +;;;138 NVIC->IP[NVIC_InitStruct->NVIC_IRQChannel] = tmppriority; +00002e 4c0e LDR r4,|L1.104| +000030 7806 LDRB r6,[r0,#0] +000032 55a1 STRB r1,[r4,r6] +;;;139 +;;;140 /* Enable the Selected IRQ Channels --------------------------------------*/ +;;;141 NVIC->ISER[NVIC_InitStruct->NVIC_IRQChannel >> 0x05] = +000034 7804 LDRB r4,[r0,#0] +000036 f004051f AND r5,r4,#0x1f +00003a 2401 MOVS r4,#1 +00003c 40ac LSLS r4,r4,r5 +00003e 7805 LDRB r5,[r0,#0] +000040 116d ASRS r5,r5,#5 +000042 00ad LSLS r5,r5,#2 +000044 f10525e0 ADD r5,r5,#0xe000e000 +000048 f8c54100 STR r4,[r5,#0x100] +00004c e009 B |L1.98| + |L1.78| +;;;142 (uint32_t)0x01 << (NVIC_InitStruct->NVIC_IRQChannel & (uint8_t)0x1F); +;;;143 } +;;;144 else +;;;145 { +;;;146 /* Disable the Selected IRQ Channels -------------------------------------*/ +;;;147 NVIC->ICER[NVIC_InitStruct->NVIC_IRQChannel >> 0x05] = +00004e 7804 LDRB r4,[r0,#0] +000050 f004051f AND r5,r4,#0x1f +000054 2401 MOVS r4,#1 +000056 40ac LSLS r4,r4,r5 +000058 4d04 LDR r5,|L1.108| +00005a 7806 LDRB r6,[r0,#0] +00005c 1176 ASRS r6,r6,#5 +00005e f8454026 STR r4,[r5,r6,LSL #2] + |L1.98| +;;;148 (uint32_t)0x01 << (NVIC_InitStruct->NVIC_IRQChannel & (uint8_t)0x1F); +;;;149 } +;;;150 } +000062 bd70 POP {r4-r6,pc} +;;;151 + ENDP + + |L1.100| + DCD 0xe000ed0c + |L1.104| + DCD 0xe000e400 + |L1.108| + DCD 0xe000e180 + + AREA ||i.NVIC_PriorityGroupConfig||, CODE, READONLY, ALIGN=2 + + NVIC_PriorityGroupConfig PROC +;;;101 */ +;;;102 void NVIC_PriorityGroupConfig(uint32_t NVIC_PriorityGroup) +000000 4902 LDR r1,|L2.12| +;;;103 { +;;;104 /* Check the parameters */ +;;;105 assert_param(IS_NVIC_PRIORITY_GROUP(NVIC_PriorityGroup)); +;;;106 +;;;107 /* Set the PRIGROUP[10:8] bits according to NVIC_PriorityGroup value */ +;;;108 SCB->AIRCR = AIRCR_VECTKEY_MASK | NVIC_PriorityGroup; +000002 4301 ORRS r1,r1,r0 +000004 4a02 LDR r2,|L2.16| +000006 6011 STR r1,[r2,#0] +;;;109 } +000008 4770 BX lr +;;;110 + ENDP + +00000a 0000 DCW 0x0000 + |L2.12| + DCD 0x05fa0000 + |L2.16| + DCD 0xe000ed0c + + AREA ||i.NVIC_SetVectorTable||, CODE, READONLY, ALIGN=2 + + NVIC_SetVectorTable PROC +;;;161 */ +;;;162 void NVIC_SetVectorTable(uint32_t NVIC_VectTab, uint32_t Offset) +000000 4a02 LDR r2,|L3.12| +;;;163 { +;;;164 /* Check the parameters */ +;;;165 assert_param(IS_NVIC_VECTTAB(NVIC_VectTab)); +;;;166 assert_param(IS_NVIC_OFFSET(Offset)); +;;;167 +;;;168 SCB->VTOR = NVIC_VectTab | (Offset & (uint32_t)0x1FFFFF80); +000002 400a ANDS r2,r2,r1 +000004 4302 ORRS r2,r2,r0 +000006 4b02 LDR r3,|L3.16| +000008 601a STR r2,[r3,#0] +;;;169 } +00000a 4770 BX lr +;;;170 + ENDP + + |L3.12| + DCD 0x1fffff80 + |L3.16| + DCD 0xe000ed08 + + AREA ||i.NVIC_SystemLPConfig||, CODE, READONLY, ALIGN=2 + + NVIC_SystemLPConfig PROC +;;;180 */ +;;;181 void NVIC_SystemLPConfig(uint8_t LowPowerMode, FunctionalState NewState) +000000 b129 CBZ r1,|L4.14| +;;;182 { +;;;183 /* Check the parameters */ +;;;184 assert_param(IS_NVIC_LP(LowPowerMode)); +;;;185 assert_param(IS_FUNCTIONAL_STATE(NewState)); +;;;186 +;;;187 if (NewState != DISABLE) +;;;188 { +;;;189 SCB->SCR |= LowPowerMode; +000002 4a06 LDR r2,|L4.28| +000004 6812 LDR r2,[r2,#0] +000006 4302 ORRS r2,r2,r0 +000008 4b04 LDR r3,|L4.28| +00000a 601a STR r2,[r3,#0] +00000c e004 B |L4.24| + |L4.14| +;;;190 } +;;;191 else +;;;192 { +;;;193 SCB->SCR &= (uint32_t)(~(uint32_t)LowPowerMode); +00000e 4a03 LDR r2,|L4.28| +000010 6812 LDR r2,[r2,#0] +000012 4382 BICS r2,r2,r0 +000014 4b01 LDR r3,|L4.28| +000016 601a STR r2,[r3,#0] + |L4.24| +;;;194 } +;;;195 } +000018 4770 BX lr +;;;196 + ENDP + +00001a 0000 DCW 0x0000 + |L4.28| + DCD 0xe000ed10 + + AREA ||i.SysTick_CLKSourceConfig||, CODE, READONLY, ALIGN=1 + + SysTick_CLKSourceConfig PROC +;;;204 */ +;;;205 void SysTick_CLKSourceConfig(uint32_t SysTick_CLKSource) +000000 2804 CMP r0,#4 +;;;206 { +;;;207 /* Check the parameters */ +;;;208 assert_param(IS_SYSTICK_CLK_SOURCE(SysTick_CLKSource)); +;;;209 if (SysTick_CLKSource == SysTick_CLKSource_HCLK) +000002 d108 BNE |L5.22| +;;;210 { +;;;211 SysTick->CTRL |= SysTick_CLKSource_HCLK; +000004 f04f21e0 MOV r1,#0xe000e000 +000008 6909 LDR r1,[r1,#0x10] +00000a f0410104 ORR r1,r1,#4 +00000e f04f22e0 MOV r2,#0xe000e000 +000012 6111 STR r1,[r2,#0x10] +000014 e007 B |L5.38| + |L5.22| +;;;212 } +;;;213 else +;;;214 { +;;;215 SysTick->CTRL &= SysTick_CLKSource_HCLK_Div8; +000016 f04f21e0 MOV r1,#0xe000e000 +00001a 6909 LDR r1,[r1,#0x10] +00001c f0210104 BIC r1,r1,#4 +000020 f04f22e0 MOV r2,#0xe000e000 +000024 6111 STR r1,[r2,#0x10] + |L5.38| +;;;216 } +;;;217 } +000026 4770 BX lr +;;;218 + ENDP + + +;*** Start embedded assembler *** + +#line 1 "..\\..\\Libraries\\STM32F10x_StdPeriph_Driver\\src\\misc.c" + AREA ||.rev16_text||, CODE + THUMB + EXPORT |__asm___6_misc_c_d0fc1254____REV16| +#line 114 "..\\..\\Libraries\\CMSIS\\Include\\core_cmInstr.h" +|__asm___6_misc_c_d0fc1254____REV16| PROC +#line 115 + + rev16 r0, r0 + bx lr + ENDP + AREA ||.revsh_text||, CODE + THUMB + EXPORT |__asm___6_misc_c_d0fc1254____REVSH| +#line 128 +|__asm___6_misc_c_d0fc1254____REVSH| PROC +#line 129 + + revsh r0, r0 + bx lr + ENDP + +;*** End embedded assembler *** diff --git a/Project/MDK-ARM/Flash/List/stm32f10x_adc.txt b/Project/MDK-ARM/Flash/List/stm32f10x_adc.txt new file mode 100644 index 0000000..0bd3f97 --- /dev/null +++ b/Project/MDK-ARM/Flash/List/stm32f10x_adc.txt @@ -0,0 +1,1535 @@ +; generated by Component: ARM Compiler 5.06 update 7 (build 960) Tool: ArmCC [4d365d] +; commandline ArmCC [--list --split_sections --debug -c --asm --interleave -o.\flash\obj\stm32f10x_adc.o --asm_dir=.\Flash\List\ --list_dir=.\Flash\List\ --depend=.\flash\obj\stm32f10x_adc.d --cpu=Cortex-M3 --apcs=interwork -O0 --diag_suppress=9931,870 -I..\..\Libraries\CMSIS\Device\ST\STM32F10x\Include -I..\..\Libraries\STM32F10x_StdPeriph_Driver\inc -I..\..\Libraries\STM32_USB-FS-Device_Driver\inc -I..\..\Libraries\CMSIS\Include -I..\..\User\bsp -I..\..\User\bsp\inc -I..\..\User\app\inc -I..\..\User -IC:\Users\w1619\AppData\Local\Arm\Packs\Keil\STM32F1xx_DFP\2.4.1\Device\Include -D__MICROLIB -D__UVISION_VERSION=538 -DSTM32F10X_HD -DUSE_STDPERIPH_DRIVER -DSTM32F10X_HD --omf_browse=.\flash\obj\stm32f10x_adc.crf ..\..\Libraries\STM32F10x_StdPeriph_Driver\src\stm32f10x_adc.c] + THUMB + + AREA ||i.ADC_AnalogWatchdogCmd||, CODE, READONLY, ALIGN=2 + + ADC_AnalogWatchdogCmd PROC +;;;1087 */ +;;;1088 void ADC_AnalogWatchdogCmd(ADC_TypeDef* ADCx, uint32_t ADC_AnalogWatchdog) +000000 460a MOV r2,r1 +;;;1089 { +;;;1090 uint32_t tmpreg = 0; +000002 2100 MOVS r1,#0 +;;;1091 /* Check the parameters */ +;;;1092 assert_param(IS_ADC_ALL_PERIPH(ADCx)); +;;;1093 assert_param(IS_ADC_ANALOG_WATCHDOG(ADC_AnalogWatchdog)); +;;;1094 /* Get the old register value */ +;;;1095 tmpreg = ADCx->CR1; +000004 6841 LDR r1,[r0,#4] +;;;1096 /* Clear AWDEN, AWDENJ and AWDSGL bits */ +;;;1097 tmpreg &= CR1_AWDMode_Reset; +000006 4b02 LDR r3,|L1.16| +000008 4019 ANDS r1,r1,r3 +;;;1098 /* Set the analog watchdog enable mode */ +;;;1099 tmpreg |= ADC_AnalogWatchdog; +00000a 4311 ORRS r1,r1,r2 +;;;1100 /* Store the new register value */ +;;;1101 ADCx->CR1 = tmpreg; +00000c 6041 STR r1,[r0,#4] +;;;1102 } +00000e 4770 BX lr +;;;1103 + ENDP + + |L1.16| + DCD 0xff3ffdff + + AREA ||i.ADC_AnalogWatchdogSingleChannelConfig||, CODE, READONLY, ALIGN=1 + + ADC_AnalogWatchdogSingleChannelConfig PROC +;;;1150 */ +;;;1151 void ADC_AnalogWatchdogSingleChannelConfig(ADC_TypeDef* ADCx, uint8_t ADC_Channel) +000000 460a MOV r2,r1 +;;;1152 { +;;;1153 uint32_t tmpreg = 0; +000002 2100 MOVS r1,#0 +;;;1154 /* Check the parameters */ +;;;1155 assert_param(IS_ADC_ALL_PERIPH(ADCx)); +;;;1156 assert_param(IS_ADC_CHANNEL(ADC_Channel)); +;;;1157 /* Get the old register value */ +;;;1158 tmpreg = ADCx->CR1; +000004 6841 LDR r1,[r0,#4] +;;;1159 /* Clear the Analog watchdog channel select bits */ +;;;1160 tmpreg &= CR1_AWDCH_Reset; +000006 f021011f BIC r1,r1,#0x1f +;;;1161 /* Set the Analog watchdog channel */ +;;;1162 tmpreg |= ADC_Channel; +00000a 4311 ORRS r1,r1,r2 +;;;1163 /* Store the new register value */ +;;;1164 ADCx->CR1 = tmpreg; +00000c 6041 STR r1,[r0,#4] +;;;1165 } +00000e 4770 BX lr +;;;1166 + ENDP + + + AREA ||i.ADC_AnalogWatchdogThresholdsConfig||, CODE, READONLY, ALIGN=1 + + ADC_AnalogWatchdogThresholdsConfig PROC +;;;1112 */ +;;;1113 void ADC_AnalogWatchdogThresholdsConfig(ADC_TypeDef* ADCx, uint16_t HighThreshold, +000000 6241 STR r1,[r0,#0x24] +;;;1114 uint16_t LowThreshold) +;;;1115 { +;;;1116 /* Check the parameters */ +;;;1117 assert_param(IS_ADC_ALL_PERIPH(ADCx)); +;;;1118 assert_param(IS_ADC_THRESHOLD(HighThreshold)); +;;;1119 assert_param(IS_ADC_THRESHOLD(LowThreshold)); +;;;1120 /* Set the ADCx high threshold */ +;;;1121 ADCx->HTR = HighThreshold; +;;;1122 /* Set the ADCx low threshold */ +;;;1123 ADCx->LTR = LowThreshold; +000002 6282 STR r2,[r0,#0x28] +;;;1124 } +000004 4770 BX lr +;;;1125 + ENDP + + + AREA ||i.ADC_AutoInjectedConvCmd||, CODE, READONLY, ALIGN=1 + + ADC_AutoInjectedConvCmd PROC +;;;739 */ +;;;740 void ADC_AutoInjectedConvCmd(ADC_TypeDef* ADCx, FunctionalState NewState) +000000 b121 CBZ r1,|L4.12| +;;;741 { +;;;742 /* Check the parameters */ +;;;743 assert_param(IS_ADC_ALL_PERIPH(ADCx)); +;;;744 assert_param(IS_FUNCTIONAL_STATE(NewState)); +;;;745 if (NewState != DISABLE) +;;;746 { +;;;747 /* Enable the selected ADC automatic injected group conversion */ +;;;748 ADCx->CR1 |= CR1_JAUTO_Set; +000002 6842 LDR r2,[r0,#4] +000004 f4426280 ORR r2,r2,#0x400 +000008 6042 STR r2,[r0,#4] +00000a e003 B |L4.20| + |L4.12| +;;;749 } +;;;750 else +;;;751 { +;;;752 /* Disable the selected ADC automatic injected group conversion */ +;;;753 ADCx->CR1 &= CR1_JAUTO_Reset; +00000c 6842 LDR r2,[r0,#4] +00000e f4226280 BIC r2,r2,#0x400 +000012 6042 STR r2,[r0,#4] + |L4.20| +;;;754 } +;;;755 } +000014 4770 BX lr +;;;756 + ENDP + + + AREA ||i.ADC_ClearFlag||, CODE, READONLY, ALIGN=1 + + ADC_ClearFlag PROC +;;;1233 */ +;;;1234 void ADC_ClearFlag(ADC_TypeDef* ADCx, uint8_t ADC_FLAG) +000000 43ca MVNS r2,r1 +;;;1235 { +;;;1236 /* Check the parameters */ +;;;1237 assert_param(IS_ADC_ALL_PERIPH(ADCx)); +;;;1238 assert_param(IS_ADC_CLEAR_FLAG(ADC_FLAG)); +;;;1239 /* Clear the selected ADC flags */ +;;;1240 ADCx->SR = ~(uint32_t)ADC_FLAG; +000002 6002 STR r2,[r0,#0] +;;;1241 } +000004 4770 BX lr +;;;1242 + ENDP + + + AREA ||i.ADC_ClearITPendingBit||, CODE, READONLY, ALIGN=1 + + ADC_ClearITPendingBit PROC +;;;1288 */ +;;;1289 void ADC_ClearITPendingBit(ADC_TypeDef* ADCx, uint16_t ADC_IT) +000000 2200 MOVS r2,#0 +;;;1290 { +;;;1291 uint8_t itmask = 0; +;;;1292 /* Check the parameters */ +;;;1293 assert_param(IS_ADC_ALL_PERIPH(ADCx)); +;;;1294 assert_param(IS_ADC_IT(ADC_IT)); +;;;1295 /* Get the ADC IT index */ +;;;1296 itmask = (uint8_t)(ADC_IT >> 8); +000002 120a ASRS r2,r1,#8 +;;;1297 /* Clear the selected ADC interrupt pending bits */ +;;;1298 ADCx->SR = ~(uint32_t)itmask; +000004 43d3 MVNS r3,r2 +000006 6003 STR r3,[r0,#0] +;;;1299 } +000008 4770 BX lr +;;;1300 + ENDP + + + AREA ||i.ADC_Cmd||, CODE, READONLY, ALIGN=1 + + ADC_Cmd PROC +;;;304 */ +;;;305 void ADC_Cmd(ADC_TypeDef* ADCx, FunctionalState NewState) +000000 b121 CBZ r1,|L7.12| +;;;306 { +;;;307 /* Check the parameters */ +;;;308 assert_param(IS_ADC_ALL_PERIPH(ADCx)); +;;;309 assert_param(IS_FUNCTIONAL_STATE(NewState)); +;;;310 if (NewState != DISABLE) +;;;311 { +;;;312 /* Set the ADON bit to wake up the ADC from power down mode */ +;;;313 ADCx->CR2 |= CR2_ADON_Set; +000002 6882 LDR r2,[r0,#8] +000004 f0420201 ORR r2,r2,#1 +000008 6082 STR r2,[r0,#8] +00000a e003 B |L7.20| + |L7.12| +;;;314 } +;;;315 else +;;;316 { +;;;317 /* Disable the selected ADC peripheral */ +;;;318 ADCx->CR2 &= CR2_ADON_Reset; +00000c 6882 LDR r2,[r0,#8] +00000e f0220201 BIC r2,r2,#1 +000012 6082 STR r2,[r0,#8] + |L7.20| +;;;319 } +;;;320 } +000014 4770 BX lr +;;;321 + ENDP + + + AREA ||i.ADC_DMACmd||, CODE, READONLY, ALIGN=1 + + ADC_DMACmd PROC +;;;329 */ +;;;330 void ADC_DMACmd(ADC_TypeDef* ADCx, FunctionalState NewState) +000000 b121 CBZ r1,|L8.12| +;;;331 { +;;;332 /* Check the parameters */ +;;;333 assert_param(IS_ADC_DMA_PERIPH(ADCx)); +;;;334 assert_param(IS_FUNCTIONAL_STATE(NewState)); +;;;335 if (NewState != DISABLE) +;;;336 { +;;;337 /* Enable the selected ADC DMA request */ +;;;338 ADCx->CR2 |= CR2_DMA_Set; +000002 6882 LDR r2,[r0,#8] +000004 f4427280 ORR r2,r2,#0x100 +000008 6082 STR r2,[r0,#8] +00000a e003 B |L8.20| + |L8.12| +;;;339 } +;;;340 else +;;;341 { +;;;342 /* Disable the selected ADC DMA request */ +;;;343 ADCx->CR2 &= CR2_DMA_Reset; +00000c 6882 LDR r2,[r0,#8] +00000e f4227280 BIC r2,r2,#0x100 +000012 6082 STR r2,[r0,#8] + |L8.20| +;;;344 } +;;;345 } +000014 4770 BX lr +;;;346 + ENDP + + + AREA ||i.ADC_DeInit||, CODE, READONLY, ALIGN=2 + + ADC_DeInit PROC +;;;184 */ +;;;185 void ADC_DeInit(ADC_TypeDef* ADCx) +000000 b510 PUSH {r4,lr} +;;;186 { +000002 4604 MOV r4,r0 +;;;187 /* Check the parameters */ +;;;188 assert_param(IS_ADC_ALL_PERIPH(ADCx)); +;;;189 +;;;190 if (ADCx == ADC1) +000004 4812 LDR r0,|L9.80| +000006 4284 CMP r4,r0 +000008 d108 BNE |L9.28| +;;;191 { +;;;192 /* Enable ADC1 reset state */ +;;;193 RCC_APB2PeriphResetCmd(RCC_APB2Periph_ADC1, ENABLE); +00000a 2101 MOVS r1,#1 +00000c 1540 ASRS r0,r0,#21 +00000e f7fffffe BL RCC_APB2PeriphResetCmd +;;;194 /* Release ADC1 from reset state */ +;;;195 RCC_APB2PeriphResetCmd(RCC_APB2Periph_ADC1, DISABLE); +000012 2100 MOVS r1,#0 +000014 1560 ASRS r0,r4,#21 +000016 f7fffffe BL RCC_APB2PeriphResetCmd +00001a e017 B |L9.76| + |L9.28| +;;;196 } +;;;197 else if (ADCx == ADC2) +00001c 480d LDR r0,|L9.84| +00001e 4284 CMP r4,r0 +000020 d108 BNE |L9.52| +;;;198 { +;;;199 /* Enable ADC2 reset state */ +;;;200 RCC_APB2PeriphResetCmd(RCC_APB2Periph_ADC2, ENABLE); +000022 2101 MOVS r1,#1 +000024 1500 ASRS r0,r0,#20 +000026 f7fffffe BL RCC_APB2PeriphResetCmd +;;;201 /* Release ADC2 from reset state */ +;;;202 RCC_APB2PeriphResetCmd(RCC_APB2Periph_ADC2, DISABLE); +00002a 2100 MOVS r1,#0 +00002c 1520 ASRS r0,r4,#20 +00002e f7fffffe BL RCC_APB2PeriphResetCmd +000032 e00b B |L9.76| + |L9.52| +;;;203 } +;;;204 else +;;;205 { +;;;206 if (ADCx == ADC3) +000034 4808 LDR r0,|L9.88| +000036 4284 CMP r4,r0 +000038 d108 BNE |L9.76| +;;;207 { +;;;208 /* Enable ADC3 reset state */ +;;;209 RCC_APB2PeriphResetCmd(RCC_APB2Periph_ADC3, ENABLE); +00003a 2101 MOVS r1,#1 +00003c 03c8 LSLS r0,r1,#15 +00003e f7fffffe BL RCC_APB2PeriphResetCmd +;;;210 /* Release ADC3 from reset state */ +;;;211 RCC_APB2PeriphResetCmd(RCC_APB2Periph_ADC3, DISABLE); +000042 2100 MOVS r1,#0 +000044 f44f4000 MOV r0,#0x8000 +000048 f7fffffe BL RCC_APB2PeriphResetCmd + |L9.76| +;;;212 } +;;;213 } +;;;214 } +00004c bd10 POP {r4,pc} +;;;215 + ENDP + +00004e 0000 DCW 0x0000 + |L9.80| + DCD 0x40012400 + |L9.84| + DCD 0x40012800 + |L9.88| + DCD 0x40013c00 + + AREA ||i.ADC_DiscModeChannelCountConfig||, CODE, READONLY, ALIGN=1 + + ADC_DiscModeChannelCountConfig PROC +;;;514 */ +;;;515 void ADC_DiscModeChannelCountConfig(ADC_TypeDef* ADCx, uint8_t Number) +000000 b510 PUSH {r4,lr} +;;;516 { +000002 460a MOV r2,r1 +;;;517 uint32_t tmpreg1 = 0; +000004 2100 MOVS r1,#0 +;;;518 uint32_t tmpreg2 = 0; +000006 2300 MOVS r3,#0 +;;;519 /* Check the parameters */ +;;;520 assert_param(IS_ADC_ALL_PERIPH(ADCx)); +;;;521 assert_param(IS_ADC_REGULAR_DISC_NUMBER(Number)); +;;;522 /* Get the old register value */ +;;;523 tmpreg1 = ADCx->CR1; +000008 6841 LDR r1,[r0,#4] +;;;524 /* Clear the old discontinuous mode channel count */ +;;;525 tmpreg1 &= CR1_DISCNUM_Reset; +00000a f4214160 BIC r1,r1,#0xe000 +;;;526 /* Set the discontinuous mode channel count */ +;;;527 tmpreg2 = Number - 1; +00000e 1e53 SUBS r3,r2,#1 +;;;528 tmpreg1 |= tmpreg2 << 13; +000010 ea413143 ORR r1,r1,r3,LSL #13 +;;;529 /* Store the new register value */ +;;;530 ADCx->CR1 = tmpreg1; +000014 6041 STR r1,[r0,#4] +;;;531 } +000016 bd10 POP {r4,pc} +;;;532 + ENDP + + + AREA ||i.ADC_DiscModeCmd||, CODE, READONLY, ALIGN=1 + + ADC_DiscModeCmd PROC +;;;541 */ +;;;542 void ADC_DiscModeCmd(ADC_TypeDef* ADCx, FunctionalState NewState) +000000 b121 CBZ r1,|L11.12| +;;;543 { +;;;544 /* Check the parameters */ +;;;545 assert_param(IS_ADC_ALL_PERIPH(ADCx)); +;;;546 assert_param(IS_FUNCTIONAL_STATE(NewState)); +;;;547 if (NewState != DISABLE) +;;;548 { +;;;549 /* Enable the selected ADC regular discontinuous mode */ +;;;550 ADCx->CR1 |= CR1_DISCEN_Set; +000002 6842 LDR r2,[r0,#4] +000004 f4426200 ORR r2,r2,#0x800 +000008 6042 STR r2,[r0,#4] +00000a e003 B |L11.20| + |L11.12| +;;;551 } +;;;552 else +;;;553 { +;;;554 /* Disable the selected ADC regular discontinuous mode */ +;;;555 ADCx->CR1 &= CR1_DISCEN_Reset; +00000c 6842 LDR r2,[r0,#4] +00000e f4226200 BIC r2,r2,#0x800 +000012 6042 STR r2,[r0,#4] + |L11.20| +;;;556 } +;;;557 } +000014 4770 BX lr +;;;558 + ENDP + + + AREA ||i.ADC_ExternalTrigConvCmd||, CODE, READONLY, ALIGN=1 + + ADC_ExternalTrigConvCmd PROC +;;;691 */ +;;;692 void ADC_ExternalTrigConvCmd(ADC_TypeDef* ADCx, FunctionalState NewState) +000000 b121 CBZ r1,|L12.12| +;;;693 { +;;;694 /* Check the parameters */ +;;;695 assert_param(IS_ADC_ALL_PERIPH(ADCx)); +;;;696 assert_param(IS_FUNCTIONAL_STATE(NewState)); +;;;697 if (NewState != DISABLE) +;;;698 { +;;;699 /* Enable the selected ADC conversion on external event */ +;;;700 ADCx->CR2 |= CR2_EXTTRIG_Set; +000002 6882 LDR r2,[r0,#8] +000004 f4421280 ORR r2,r2,#0x100000 +000008 6082 STR r2,[r0,#8] +00000a e003 B |L12.20| + |L12.12| +;;;701 } +;;;702 else +;;;703 { +;;;704 /* Disable the selected ADC conversion on external event */ +;;;705 ADCx->CR2 &= CR2_EXTTRIG_Reset; +00000c 6882 LDR r2,[r0,#8] +00000e f4221280 BIC r2,r2,#0x100000 +000012 6082 STR r2,[r0,#8] + |L12.20| +;;;706 } +;;;707 } +000014 4770 BX lr +;;;708 + ENDP + + + AREA ||i.ADC_ExternalTrigInjectedConvCmd||, CODE, READONLY, ALIGN=1 + + ADC_ExternalTrigInjectedConvCmd PROC +;;;829 */ +;;;830 void ADC_ExternalTrigInjectedConvCmd(ADC_TypeDef* ADCx, FunctionalState NewState) +000000 b121 CBZ r1,|L13.12| +;;;831 { +;;;832 /* Check the parameters */ +;;;833 assert_param(IS_ADC_ALL_PERIPH(ADCx)); +;;;834 assert_param(IS_FUNCTIONAL_STATE(NewState)); +;;;835 if (NewState != DISABLE) +;;;836 { +;;;837 /* Enable the selected ADC external event selection for injected group */ +;;;838 ADCx->CR2 |= CR2_JEXTTRIG_Set; +000002 6882 LDR r2,[r0,#8] +000004 f4424200 ORR r2,r2,#0x8000 +000008 6082 STR r2,[r0,#8] +00000a e003 B |L13.20| + |L13.12| +;;;839 } +;;;840 else +;;;841 { +;;;842 /* Disable the selected ADC external event selection for injected group */ +;;;843 ADCx->CR2 &= CR2_JEXTTRIG_Reset; +00000c 6882 LDR r2,[r0,#8] +00000e f4224200 BIC r2,r2,#0x8000 +000012 6082 STR r2,[r0,#8] + |L13.20| +;;;844 } +;;;845 } +000014 4770 BX lr +;;;846 + ENDP + + + AREA ||i.ADC_ExternalTrigInjectedConvConfig||, CODE, READONLY, ALIGN=1 + + ADC_ExternalTrigInjectedConvConfig PROC +;;;804 */ +;;;805 void ADC_ExternalTrigInjectedConvConfig(ADC_TypeDef* ADCx, uint32_t ADC_ExternalTrigInjecConv) +000000 460a MOV r2,r1 +;;;806 { +;;;807 uint32_t tmpreg = 0; +000002 2100 MOVS r1,#0 +;;;808 /* Check the parameters */ +;;;809 assert_param(IS_ADC_ALL_PERIPH(ADCx)); +;;;810 assert_param(IS_ADC_EXT_INJEC_TRIG(ADC_ExternalTrigInjecConv)); +;;;811 /* Get the old register value */ +;;;812 tmpreg = ADCx->CR2; +000004 6881 LDR r1,[r0,#8] +;;;813 /* Clear the old external event selection for injected group */ +;;;814 tmpreg &= CR2_JEXTSEL_Reset; +000006 f42141e0 BIC r1,r1,#0x7000 +;;;815 /* Set the external event selection for injected group */ +;;;816 tmpreg |= ADC_ExternalTrigInjecConv; +00000a 4311 ORRS r1,r1,r2 +;;;817 /* Store the new register value */ +;;;818 ADCx->CR2 = tmpreg; +00000c 6081 STR r1,[r0,#8] +;;;819 } +00000e 4770 BX lr +;;;820 + ENDP + + + AREA ||i.ADC_GetCalibrationStatus||, CODE, READONLY, ALIGN=1 + + ADC_GetCalibrationStatus PROC +;;;435 */ +;;;436 FlagStatus ADC_GetCalibrationStatus(ADC_TypeDef* ADCx) +000000 4601 MOV r1,r0 +;;;437 { +;;;438 FlagStatus bitstatus = RESET; +000002 2000 MOVS r0,#0 +;;;439 /* Check the parameters */ +;;;440 assert_param(IS_ADC_ALL_PERIPH(ADCx)); +;;;441 /* Check the status of CAL bit */ +;;;442 if ((ADCx->CR2 & CR2_CAL_Set) != (uint32_t)RESET) +000004 688a LDR r2,[r1,#8] +000006 f0020204 AND r2,r2,#4 +00000a b10a CBZ r2,|L15.16| +;;;443 { +;;;444 /* CAL bit is set: calibration on going */ +;;;445 bitstatus = SET; +00000c 2001 MOVS r0,#1 +00000e e000 B |L15.18| + |L15.16| +;;;446 } +;;;447 else +;;;448 { +;;;449 /* CAL bit is reset: end of calibration */ +;;;450 bitstatus = RESET; +000010 2000 MOVS r0,#0 + |L15.18| +;;;451 } +;;;452 /* Return the CAL bit status */ +;;;453 return bitstatus; +;;;454 } +000012 4770 BX lr +;;;455 + ENDP + + + AREA ||i.ADC_GetConversionValue||, CODE, READONLY, ALIGN=1 + + ADC_GetConversionValue PROC +;;;713 */ +;;;714 uint16_t ADC_GetConversionValue(ADC_TypeDef* ADCx) +000000 4601 MOV r1,r0 +;;;715 { +;;;716 /* Check the parameters */ +;;;717 assert_param(IS_ADC_ALL_PERIPH(ADCx)); +;;;718 /* Return the selected ADC conversion value */ +;;;719 return (uint16_t) ADCx->DR; +000002 6cc8 LDR r0,[r1,#0x4c] +000004 b280 UXTH r0,r0 +;;;720 } +000006 4770 BX lr +;;;721 + ENDP + + + AREA ||i.ADC_GetDualModeConversionValue||, CODE, READONLY, ALIGN=2 + + ADC_GetDualModeConversionValue PROC +;;;725 */ +;;;726 uint32_t ADC_GetDualModeConversionValue(void) +000000 4801 LDR r0,|L17.8| +;;;727 { +;;;728 /* Return the dual mode conversion value */ +;;;729 return (*(__IO uint32_t *) DR_ADDRESS); +000002 6800 LDR r0,[r0,#0] +;;;730 } +000004 4770 BX lr +;;;731 + ENDP + +000006 0000 DCW 0x0000 + |L17.8| + DCD 0x4001244c + + AREA ||i.ADC_GetFlagStatus||, CODE, READONLY, ALIGN=1 + + ADC_GetFlagStatus PROC +;;;1200 */ +;;;1201 FlagStatus ADC_GetFlagStatus(ADC_TypeDef* ADCx, uint8_t ADC_FLAG) +000000 4602 MOV r2,r0 +;;;1202 { +;;;1203 FlagStatus bitstatus = RESET; +000002 2000 MOVS r0,#0 +;;;1204 /* Check the parameters */ +;;;1205 assert_param(IS_ADC_ALL_PERIPH(ADCx)); +;;;1206 assert_param(IS_ADC_GET_FLAG(ADC_FLAG)); +;;;1207 /* Check the status of the specified ADC flag */ +;;;1208 if ((ADCx->SR & ADC_FLAG) != (uint8_t)RESET) +000004 6813 LDR r3,[r2,#0] +000006 400b ANDS r3,r3,r1 +000008 b10b CBZ r3,|L18.14| +;;;1209 { +;;;1210 /* ADC_FLAG is set */ +;;;1211 bitstatus = SET; +00000a 2001 MOVS r0,#1 +00000c e000 B |L18.16| + |L18.14| +;;;1212 } +;;;1213 else +;;;1214 { +;;;1215 /* ADC_FLAG is reset */ +;;;1216 bitstatus = RESET; +00000e 2000 MOVS r0,#0 + |L18.16| +;;;1217 } +;;;1218 /* Return the ADC_FLAG status */ +;;;1219 return bitstatus; +;;;1220 } +000010 4770 BX lr +;;;1221 + ENDP + + + AREA ||i.ADC_GetITStatus||, CODE, READONLY, ALIGN=1 + + ADC_GetITStatus PROC +;;;1252 */ +;;;1253 ITStatus ADC_GetITStatus(ADC_TypeDef* ADCx, uint16_t ADC_IT) +000000 b570 PUSH {r4-r6,lr} +;;;1254 { +000002 4602 MOV r2,r0 +;;;1255 ITStatus bitstatus = RESET; +000004 2000 MOVS r0,#0 +;;;1256 uint32_t itmask = 0, enablestatus = 0; +000006 2300 MOVS r3,#0 +000008 2400 MOVS r4,#0 +;;;1257 /* Check the parameters */ +;;;1258 assert_param(IS_ADC_ALL_PERIPH(ADCx)); +;;;1259 assert_param(IS_ADC_GET_IT(ADC_IT)); +;;;1260 /* Get the ADC IT index */ +;;;1261 itmask = ADC_IT >> 8; +00000a 120b ASRS r3,r1,#8 +;;;1262 /* Get the ADC_IT enable bit status */ +;;;1263 enablestatus = (ADCx->CR1 & (uint8_t)ADC_IT) ; +00000c 6855 LDR r5,[r2,#4] +00000e b2ce UXTB r6,r1 +000010 ea050406 AND r4,r5,r6 +;;;1264 /* Check the status of the specified ADC interrupt */ +;;;1265 if (((ADCx->SR & itmask) != (uint32_t)RESET) && enablestatus) +000014 6815 LDR r5,[r2,#0] +000016 401d ANDS r5,r5,r3 +000018 b115 CBZ r5,|L19.32| +00001a b10c CBZ r4,|L19.32| +;;;1266 { +;;;1267 /* ADC_IT is set */ +;;;1268 bitstatus = SET; +00001c 2001 MOVS r0,#1 +00001e e000 B |L19.34| + |L19.32| +;;;1269 } +;;;1270 else +;;;1271 { +;;;1272 /* ADC_IT is reset */ +;;;1273 bitstatus = RESET; +000020 2000 MOVS r0,#0 + |L19.34| +;;;1274 } +;;;1275 /* Return the ADC_IT status */ +;;;1276 return bitstatus; +;;;1277 } +000022 bd70 POP {r4-r6,pc} +;;;1278 + ENDP + + + AREA ||i.ADC_GetInjectedConversionValue||, CODE, READONLY, ALIGN=1 + + ADC_GetInjectedConversionValue PROC +;;;1057 */ +;;;1058 uint16_t ADC_GetInjectedConversionValue(ADC_TypeDef* ADCx, uint8_t ADC_InjectedChannel) +000000 b508 PUSH {r3,lr} +;;;1059 { +000002 4602 MOV r2,r0 +;;;1060 __IO uint32_t tmp = 0; +000004 2000 MOVS r0,#0 +000006 9000 STR r0,[sp,#0] +;;;1061 +;;;1062 /* Check the parameters */ +;;;1063 assert_param(IS_ADC_ALL_PERIPH(ADCx)); +;;;1064 assert_param(IS_ADC_INJECTED_CHANNEL(ADC_InjectedChannel)); +;;;1065 +;;;1066 tmp = (uint32_t)ADCx; +000008 9200 STR r2,[sp,#0] +;;;1067 tmp += ADC_InjectedChannel + JDR_Offset; +00000a f1010028 ADD r0,r1,#0x28 +00000e 9b00 LDR r3,[sp,#0] +000010 4418 ADD r0,r0,r3 +000012 9000 STR r0,[sp,#0] +;;;1068 +;;;1069 /* Returns the selected injected channel conversion data value */ +;;;1070 return (uint16_t) (*(__IO uint32_t*) tmp); +000014 9800 LDR r0,[sp,#0] +000016 6800 LDR r0,[r0,#0] +000018 b280 UXTH r0,r0 +;;;1071 } +00001a bd08 POP {r3,pc} +;;;1072 + ENDP + + + AREA ||i.ADC_GetResetCalibrationStatus||, CODE, READONLY, ALIGN=1 + + ADC_GetResetCalibrationStatus PROC +;;;397 */ +;;;398 FlagStatus ADC_GetResetCalibrationStatus(ADC_TypeDef* ADCx) +000000 4601 MOV r1,r0 +;;;399 { +;;;400 FlagStatus bitstatus = RESET; +000002 2000 MOVS r0,#0 +;;;401 /* Check the parameters */ +;;;402 assert_param(IS_ADC_ALL_PERIPH(ADCx)); +;;;403 /* Check the status of RSTCAL bit */ +;;;404 if ((ADCx->CR2 & CR2_RSTCAL_Set) != (uint32_t)RESET) +000004 688a LDR r2,[r1,#8] +000006 f0020208 AND r2,r2,#8 +00000a b10a CBZ r2,|L21.16| +;;;405 { +;;;406 /* RSTCAL bit is set */ +;;;407 bitstatus = SET; +00000c 2001 MOVS r0,#1 +00000e e000 B |L21.18| + |L21.16| +;;;408 } +;;;409 else +;;;410 { +;;;411 /* RSTCAL bit is reset */ +;;;412 bitstatus = RESET; +000010 2000 MOVS r0,#0 + |L21.18| +;;;413 } +;;;414 /* Return the RSTCAL bit status */ +;;;415 return bitstatus; +;;;416 } +000012 4770 BX lr +;;;417 + ENDP + + + AREA ||i.ADC_GetSoftwareStartConvStatus||, CODE, READONLY, ALIGN=1 + + ADC_GetSoftwareStartConvStatus PROC +;;;486 */ +;;;487 FlagStatus ADC_GetSoftwareStartConvStatus(ADC_TypeDef* ADCx) +000000 4601 MOV r1,r0 +;;;488 { +;;;489 FlagStatus bitstatus = RESET; +000002 2000 MOVS r0,#0 +;;;490 /* Check the parameters */ +;;;491 assert_param(IS_ADC_ALL_PERIPH(ADCx)); +;;;492 /* Check the status of SWSTART bit */ +;;;493 if ((ADCx->CR2 & CR2_SWSTART_Set) != (uint32_t)RESET) +000004 688a LDR r2,[r1,#8] +000006 f4020280 AND r2,r2,#0x400000 +00000a b10a CBZ r2,|L22.16| +;;;494 { +;;;495 /* SWSTART bit is set */ +;;;496 bitstatus = SET; +00000c 2001 MOVS r0,#1 +00000e e000 B |L22.18| + |L22.16| +;;;497 } +;;;498 else +;;;499 { +;;;500 /* SWSTART bit is reset */ +;;;501 bitstatus = RESET; +000010 2000 MOVS r0,#0 + |L22.18| +;;;502 } +;;;503 /* Return the SWSTART bit status */ +;;;504 return bitstatus; +;;;505 } +000012 4770 BX lr +;;;506 + ENDP + + + AREA ||i.ADC_GetSoftwareStartInjectedConvCmdStatus||, CODE, READONLY, ALIGN=1 + + ADC_GetSoftwareStartInjectedConvCmdStatus PROC +;;;878 */ +;;;879 FlagStatus ADC_GetSoftwareStartInjectedConvCmdStatus(ADC_TypeDef* ADCx) +000000 4601 MOV r1,r0 +;;;880 { +;;;881 FlagStatus bitstatus = RESET; +000002 2000 MOVS r0,#0 +;;;882 /* Check the parameters */ +;;;883 assert_param(IS_ADC_ALL_PERIPH(ADCx)); +;;;884 /* Check the status of JSWSTART bit */ +;;;885 if ((ADCx->CR2 & CR2_JSWSTART_Set) != (uint32_t)RESET) +000004 688a LDR r2,[r1,#8] +000006 f4021200 AND r2,r2,#0x200000 +00000a b10a CBZ r2,|L23.16| +;;;886 { +;;;887 /* JSWSTART bit is set */ +;;;888 bitstatus = SET; +00000c 2001 MOVS r0,#1 +00000e e000 B |L23.18| + |L23.16| +;;;889 } +;;;890 else +;;;891 { +;;;892 /* JSWSTART bit is reset */ +;;;893 bitstatus = RESET; +000010 2000 MOVS r0,#0 + |L23.18| +;;;894 } +;;;895 /* Return the JSWSTART bit status */ +;;;896 return bitstatus; +;;;897 } +000012 4770 BX lr +;;;898 + ENDP + + + AREA ||i.ADC_ITConfig||, CODE, READONLY, ALIGN=1 + + ADC_ITConfig PROC +;;;358 */ +;;;359 void ADC_ITConfig(ADC_TypeDef* ADCx, uint16_t ADC_IT, FunctionalState NewState) +000000 b510 PUSH {r4,lr} +;;;360 { +;;;361 uint8_t itmask = 0; +000002 2300 MOVS r3,#0 +;;;362 /* Check the parameters */ +;;;363 assert_param(IS_ADC_ALL_PERIPH(ADCx)); +;;;364 assert_param(IS_FUNCTIONAL_STATE(NewState)); +;;;365 assert_param(IS_ADC_IT(ADC_IT)); +;;;366 /* Get the ADC IT index */ +;;;367 itmask = (uint8_t)ADC_IT; +000004 b2cb UXTB r3,r1 +;;;368 if (NewState != DISABLE) +000006 b11a CBZ r2,|L24.16| +;;;369 { +;;;370 /* Enable the selected ADC interrupts */ +;;;371 ADCx->CR1 |= itmask; +000008 6844 LDR r4,[r0,#4] +00000a 431c ORRS r4,r4,r3 +00000c 6044 STR r4,[r0,#4] +00000e e002 B |L24.22| + |L24.16| +;;;372 } +;;;373 else +;;;374 { +;;;375 /* Disable the selected ADC interrupts */ +;;;376 ADCx->CR1 &= (~(uint32_t)itmask); +000010 6844 LDR r4,[r0,#4] +000012 439c BICS r4,r4,r3 +000014 6044 STR r4,[r0,#4] + |L24.22| +;;;377 } +;;;378 } +000016 bd10 POP {r4,pc} +;;;379 + ENDP + + + AREA ||i.ADC_Init||, CODE, READONLY, ALIGN=2 + + ADC_Init PROC +;;;223 */ +;;;224 void ADC_Init(ADC_TypeDef* ADCx, ADC_InitTypeDef* ADC_InitStruct) +000000 b530 PUSH {r4,r5,lr} +;;;225 { +000002 4602 MOV r2,r0 +;;;226 uint32_t tmpreg1 = 0; +000004 2000 MOVS r0,#0 +;;;227 uint8_t tmpreg2 = 0; +000006 2300 MOVS r3,#0 +;;;228 /* Check the parameters */ +;;;229 assert_param(IS_ADC_ALL_PERIPH(ADCx)); +;;;230 assert_param(IS_ADC_MODE(ADC_InitStruct->ADC_Mode)); +;;;231 assert_param(IS_FUNCTIONAL_STATE(ADC_InitStruct->ADC_ScanConvMode)); +;;;232 assert_param(IS_FUNCTIONAL_STATE(ADC_InitStruct->ADC_ContinuousConvMode)); +;;;233 assert_param(IS_ADC_EXT_TRIG(ADC_InitStruct->ADC_ExternalTrigConv)); +;;;234 assert_param(IS_ADC_DATA_ALIGN(ADC_InitStruct->ADC_DataAlign)); +;;;235 assert_param(IS_ADC_REGULAR_LENGTH(ADC_InitStruct->ADC_NbrOfChannel)); +;;;236 +;;;237 /*---------------------------- ADCx CR1 Configuration -----------------*/ +;;;238 /* Get the ADCx CR1 value */ +;;;239 tmpreg1 = ADCx->CR1; +000008 6850 LDR r0,[r2,#4] +;;;240 /* Clear DUALMOD and SCAN bits */ +;;;241 tmpreg1 &= CR1_CLEAR_Mask; +00000a 4c0f LDR r4,|L25.72| +00000c 4020 ANDS r0,r0,r4 +;;;242 /* Configure ADCx: Dual mode and scan conversion mode */ +;;;243 /* Set DUALMOD bits according to ADC_Mode value */ +;;;244 /* Set SCAN bit according to ADC_ScanConvMode value */ +;;;245 tmpreg1 |= (uint32_t)(ADC_InitStruct->ADC_Mode | ((uint32_t)ADC_InitStruct->ADC_ScanConvMode << 8)); +00000e 790d LDRB r5,[r1,#4] +000010 680c LDR r4,[r1,#0] +000012 ea442405 ORR r4,r4,r5,LSL #8 +000016 4320 ORRS r0,r0,r4 +;;;246 /* Write to ADCx CR1 */ +;;;247 ADCx->CR1 = tmpreg1; +000018 6050 STR r0,[r2,#4] +;;;248 +;;;249 /*---------------------------- ADCx CR2 Configuration -----------------*/ +;;;250 /* Get the ADCx CR2 value */ +;;;251 tmpreg1 = ADCx->CR2; +00001a 6890 LDR r0,[r2,#8] +;;;252 /* Clear CONT, ALIGN and EXTSEL bits */ +;;;253 tmpreg1 &= CR2_CLEAR_Mask; +00001c 4c0b LDR r4,|L25.76| +00001e 4020 ANDS r0,r0,r4 +;;;254 /* Configure ADCx: external trigger event and continuous conversion mode */ +;;;255 /* Set ALIGN bit according to ADC_DataAlign value */ +;;;256 /* Set EXTSEL bits according to ADC_ExternalTrigConv value */ +;;;257 /* Set CONT bit according to ADC_ContinuousConvMode value */ +;;;258 tmpreg1 |= (uint32_t)(ADC_InitStruct->ADC_DataAlign | ADC_InitStruct->ADC_ExternalTrigConv | +000020 e9d15402 LDRD r5,r4,[r1,#8] +000024 432c ORRS r4,r4,r5 +000026 794d LDRB r5,[r1,#5] +000028 ea440445 ORR r4,r4,r5,LSL #1 +00002c 4320 ORRS r0,r0,r4 +;;;259 ((uint32_t)ADC_InitStruct->ADC_ContinuousConvMode << 1)); +;;;260 /* Write to ADCx CR2 */ +;;;261 ADCx->CR2 = tmpreg1; +00002e 6090 STR r0,[r2,#8] +;;;262 +;;;263 /*---------------------------- ADCx SQR1 Configuration -----------------*/ +;;;264 /* Get the ADCx SQR1 value */ +;;;265 tmpreg1 = ADCx->SQR1; +000030 6ad0 LDR r0,[r2,#0x2c] +;;;266 /* Clear L bits */ +;;;267 tmpreg1 &= SQR1_CLEAR_Mask; +000032 f4200070 BIC r0,r0,#0xf00000 +;;;268 /* Configure ADCx: regular channel sequence length */ +;;;269 /* Set L bits according to ADC_NbrOfChannel value */ +;;;270 tmpreg2 |= (uint8_t) (ADC_InitStruct->ADC_NbrOfChannel - (uint8_t)1); +000036 7c0c LDRB r4,[r1,#0x10] +000038 1e64 SUBS r4,r4,#1 +00003a b2e4 UXTB r4,r4 +00003c 4323 ORRS r3,r3,r4 +;;;271 tmpreg1 |= (uint32_t)tmpreg2 << 20; +00003e ea405003 ORR r0,r0,r3,LSL #20 +;;;272 /* Write to ADCx SQR1 */ +;;;273 ADCx->SQR1 = tmpreg1; +000042 62d0 STR r0,[r2,#0x2c] +;;;274 } +000044 bd30 POP {r4,r5,pc} +;;;275 + ENDP + +000046 0000 DCW 0x0000 + |L25.72| + DCD 0xfff0feff + |L25.76| + DCD 0xfff1f7fd + + AREA ||i.ADC_InjectedChannelConfig||, CODE, READONLY, ALIGN=1 + + ADC_InjectedChannelConfig PROC +;;;935 */ +;;;936 void ADC_InjectedChannelConfig(ADC_TypeDef* ADCx, uint8_t ADC_Channel, uint8_t Rank, uint8_t ADC_SampleTime) +000000 b5f0 PUSH {r4-r7,lr} +;;;937 { +000002 4604 MOV r4,r0 +000004 4615 MOV r5,r2 +;;;938 uint32_t tmpreg1 = 0, tmpreg2 = 0, tmpreg3 = 0; +000006 2000 MOVS r0,#0 +000008 2200 MOVS r2,#0 +00000a 2600 MOVS r6,#0 +;;;939 /* Check the parameters */ +;;;940 assert_param(IS_ADC_ALL_PERIPH(ADCx)); +;;;941 assert_param(IS_ADC_CHANNEL(ADC_Channel)); +;;;942 assert_param(IS_ADC_INJECTED_RANK(Rank)); +;;;943 assert_param(IS_ADC_SAMPLE_TIME(ADC_SampleTime)); +;;;944 /* if ADC_Channel_10 ... ADC_Channel_17 is selected */ +;;;945 if (ADC_Channel > ADC_Channel_9) +00000c 2909 CMP r1,#9 +00000e dd11 BLE |L26.52| +;;;946 { +;;;947 /* Get the old register value */ +;;;948 tmpreg1 = ADCx->SMPR1; +000010 68e0 LDR r0,[r4,#0xc] +;;;949 /* Calculate the mask to clear */ +;;;950 tmpreg2 = SMPR1_SMP_Set << (3*(ADC_Channel - 10)); +000012 f1a1070a SUB r7,r1,#0xa +000016 eb070c47 ADD r12,r7,r7,LSL #1 +00001a 2707 MOVS r7,#7 +00001c fa07f20c LSL r2,r7,r12 +;;;951 /* Clear the old channel sample time */ +;;;952 tmpreg1 &= ~tmpreg2; +000020 4390 BICS r0,r0,r2 +;;;953 /* Calculate the mask to set */ +;;;954 tmpreg2 = (uint32_t)ADC_SampleTime << (3*(ADC_Channel - 10)); +000022 f1a1070a SUB r7,r1,#0xa +000026 eb070747 ADD r7,r7,r7,LSL #1 +00002a fa03f207 LSL r2,r3,r7 +;;;955 /* Set the new channel sample time */ +;;;956 tmpreg1 |= tmpreg2; +00002e 4310 ORRS r0,r0,r2 +;;;957 /* Store the new register value */ +;;;958 ADCx->SMPR1 = tmpreg1; +000030 60e0 STR r0,[r4,#0xc] +000032 e00c B |L26.78| + |L26.52| +;;;959 } +;;;960 else /* ADC_Channel include in ADC_Channel_[0..9] */ +;;;961 { +;;;962 /* Get the old register value */ +;;;963 tmpreg1 = ADCx->SMPR2; +000034 6920 LDR r0,[r4,#0x10] +;;;964 /* Calculate the mask to clear */ +;;;965 tmpreg2 = SMPR2_SMP_Set << (3 * ADC_Channel); +000036 eb010c41 ADD r12,r1,r1,LSL #1 +00003a 2707 MOVS r7,#7 +00003c fa07f20c LSL r2,r7,r12 +;;;966 /* Clear the old channel sample time */ +;;;967 tmpreg1 &= ~tmpreg2; +000040 4390 BICS r0,r0,r2 +;;;968 /* Calculate the mask to set */ +;;;969 tmpreg2 = (uint32_t)ADC_SampleTime << (3 * ADC_Channel); +000042 eb010741 ADD r7,r1,r1,LSL #1 +000046 fa03f207 LSL r2,r3,r7 +;;;970 /* Set the new channel sample time */ +;;;971 tmpreg1 |= tmpreg2; +00004a 4310 ORRS r0,r0,r2 +;;;972 /* Store the new register value */ +;;;973 ADCx->SMPR2 = tmpreg1; +00004c 6120 STR r0,[r4,#0x10] + |L26.78| +;;;974 } +;;;975 /* Rank configuration */ +;;;976 /* Get the old register value */ +;;;977 tmpreg1 = ADCx->JSQR; +00004e 6ba0 LDR r0,[r4,#0x38] +;;;978 /* Get JL value: Number = JL+1 */ +;;;979 tmpreg3 = (tmpreg1 & JSQR_JL_Set)>> 20; +000050 f3c05601 UBFX r6,r0,#20,#2 +;;;980 /* Calculate the mask to clear: ((Rank-1)+(4-JL-1)) */ +;;;981 tmpreg2 = JSQR_JSQ_Set << (5 * (uint8_t)((Rank + 3) - (tmpreg3 + 1))); +000054 1cef ADDS r7,r5,#3 +000056 f1060c01 ADD r12,r6,#1 +00005a eba7070c SUB r7,r7,r12 +00005e eb070c87 ADD r12,r7,r7,LSL #2 +000062 271f MOVS r7,#0x1f +000064 fa07f20c LSL r2,r7,r12 +;;;982 /* Clear the old JSQx bits for the selected rank */ +;;;983 tmpreg1 &= ~tmpreg2; +000068 4390 BICS r0,r0,r2 +;;;984 /* Calculate the mask to set: ((Rank-1)+(4-JL-1)) */ +;;;985 tmpreg2 = (uint32_t)ADC_Channel << (5 * (uint8_t)((Rank + 3) - (tmpreg3 + 1))); +00006a 1cef ADDS r7,r5,#3 +00006c f1060c01 ADD r12,r6,#1 +000070 eba7070c SUB r7,r7,r12 +000074 eb070787 ADD r7,r7,r7,LSL #2 +000078 fa01f207 LSL r2,r1,r7 +;;;986 /* Set the JSQx bits for the selected rank */ +;;;987 tmpreg1 |= tmpreg2; +00007c 4310 ORRS r0,r0,r2 +;;;988 /* Store the new register value */ +;;;989 ADCx->JSQR = tmpreg1; +00007e 63a0 STR r0,[r4,#0x38] +;;;990 } +000080 bdf0 POP {r4-r7,pc} +;;;991 + ENDP + + + AREA ||i.ADC_InjectedDiscModeCmd||, CODE, READONLY, ALIGN=1 + + ADC_InjectedDiscModeCmd PROC +;;;765 */ +;;;766 void ADC_InjectedDiscModeCmd(ADC_TypeDef* ADCx, FunctionalState NewState) +000000 b121 CBZ r1,|L27.12| +;;;767 { +;;;768 /* Check the parameters */ +;;;769 assert_param(IS_ADC_ALL_PERIPH(ADCx)); +;;;770 assert_param(IS_FUNCTIONAL_STATE(NewState)); +;;;771 if (NewState != DISABLE) +;;;772 { +;;;773 /* Enable the selected ADC injected discontinuous mode */ +;;;774 ADCx->CR1 |= CR1_JDISCEN_Set; +000002 6842 LDR r2,[r0,#4] +000004 f4425280 ORR r2,r2,#0x1000 +000008 6042 STR r2,[r0,#4] +00000a e003 B |L27.20| + |L27.12| +;;;775 } +;;;776 else +;;;777 { +;;;778 /* Disable the selected ADC injected discontinuous mode */ +;;;779 ADCx->CR1 &= CR1_JDISCEN_Reset; +00000c 6842 LDR r2,[r0,#4] +00000e f4225280 BIC r2,r2,#0x1000 +000012 6042 STR r2,[r0,#4] + |L27.20| +;;;780 } +;;;781 } +000014 4770 BX lr +;;;782 + ENDP + + + AREA ||i.ADC_InjectedSequencerLengthConfig||, CODE, READONLY, ALIGN=1 + + ADC_InjectedSequencerLengthConfig PROC +;;;998 */ +;;;999 void ADC_InjectedSequencerLengthConfig(ADC_TypeDef* ADCx, uint8_t Length) +000000 b510 PUSH {r4,lr} +;;;1000 { +000002 460a MOV r2,r1 +;;;1001 uint32_t tmpreg1 = 0; +000004 2100 MOVS r1,#0 +;;;1002 uint32_t tmpreg2 = 0; +000006 2300 MOVS r3,#0 +;;;1003 /* Check the parameters */ +;;;1004 assert_param(IS_ADC_ALL_PERIPH(ADCx)); +;;;1005 assert_param(IS_ADC_INJECTED_LENGTH(Length)); +;;;1006 +;;;1007 /* Get the old register value */ +;;;1008 tmpreg1 = ADCx->JSQR; +000008 6b81 LDR r1,[r0,#0x38] +;;;1009 /* Clear the old injected sequnence lenght JL bits */ +;;;1010 tmpreg1 &= JSQR_JL_Reset; +00000a f4211140 BIC r1,r1,#0x300000 +;;;1011 /* Set the injected sequnence lenght JL bits */ +;;;1012 tmpreg2 = Length - 1; +00000e 1e53 SUBS r3,r2,#1 +;;;1013 tmpreg1 |= tmpreg2 << 20; +000010 ea415103 ORR r1,r1,r3,LSL #20 +;;;1014 /* Store the new register value */ +;;;1015 ADCx->JSQR = tmpreg1; +000014 6381 STR r1,[r0,#0x38] +;;;1016 } +000016 bd10 POP {r4,pc} +;;;1017 + ENDP + + + AREA ||i.ADC_RegularChannelConfig||, CODE, READONLY, ALIGN=1 + + ADC_RegularChannelConfig PROC +;;;595 */ +;;;596 void ADC_RegularChannelConfig(ADC_TypeDef* ADCx, uint8_t ADC_Channel, uint8_t Rank, uint8_t ADC_SampleTime) +000000 b5f0 PUSH {r4-r7,lr} +;;;597 { +000002 4604 MOV r4,r0 +000004 460d MOV r5,r1 +;;;598 uint32_t tmpreg1 = 0, tmpreg2 = 0; +000006 2000 MOVS r0,#0 +000008 2100 MOVS r1,#0 +;;;599 /* Check the parameters */ +;;;600 assert_param(IS_ADC_ALL_PERIPH(ADCx)); +;;;601 assert_param(IS_ADC_CHANNEL(ADC_Channel)); +;;;602 assert_param(IS_ADC_REGULAR_RANK(Rank)); +;;;603 assert_param(IS_ADC_SAMPLE_TIME(ADC_SampleTime)); +;;;604 /* if ADC_Channel_10 ... ADC_Channel_17 is selected */ +;;;605 if (ADC_Channel > ADC_Channel_9) +00000a 2d09 CMP r5,#9 +00000c dd11 BLE |L29.50| +;;;606 { +;;;607 /* Get the old register value */ +;;;608 tmpreg1 = ADCx->SMPR1; +00000e 68e0 LDR r0,[r4,#0xc] +;;;609 /* Calculate the mask to clear */ +;;;610 tmpreg2 = SMPR1_SMP_Set << (3 * (ADC_Channel - 10)); +000010 f1a5060a SUB r6,r5,#0xa +000014 eb060746 ADD r7,r6,r6,LSL #1 +000018 2607 MOVS r6,#7 +00001a fa06f107 LSL r1,r6,r7 +;;;611 /* Clear the old channel sample time */ +;;;612 tmpreg1 &= ~tmpreg2; +00001e 4388 BICS r0,r0,r1 +;;;613 /* Calculate the mask to set */ +;;;614 tmpreg2 = (uint32_t)ADC_SampleTime << (3 * (ADC_Channel - 10)); +000020 f1a5060a SUB r6,r5,#0xa +000024 eb060646 ADD r6,r6,r6,LSL #1 +000028 fa03f106 LSL r1,r3,r6 +;;;615 /* Set the new channel sample time */ +;;;616 tmpreg1 |= tmpreg2; +00002c 4308 ORRS r0,r0,r1 +;;;617 /* Store the new register value */ +;;;618 ADCx->SMPR1 = tmpreg1; +00002e 60e0 STR r0,[r4,#0xc] +000030 e00c B |L29.76| + |L29.50| +;;;619 } +;;;620 else /* ADC_Channel include in ADC_Channel_[0..9] */ +;;;621 { +;;;622 /* Get the old register value */ +;;;623 tmpreg1 = ADCx->SMPR2; +000032 6920 LDR r0,[r4,#0x10] +;;;624 /* Calculate the mask to clear */ +;;;625 tmpreg2 = SMPR2_SMP_Set << (3 * ADC_Channel); +000034 eb050745 ADD r7,r5,r5,LSL #1 +000038 2607 MOVS r6,#7 +00003a fa06f107 LSL r1,r6,r7 +;;;626 /* Clear the old channel sample time */ +;;;627 tmpreg1 &= ~tmpreg2; +00003e 4388 BICS r0,r0,r1 +;;;628 /* Calculate the mask to set */ +;;;629 tmpreg2 = (uint32_t)ADC_SampleTime << (3 * ADC_Channel); +000040 eb050645 ADD r6,r5,r5,LSL #1 +000044 fa03f106 LSL r1,r3,r6 +;;;630 /* Set the new channel sample time */ +;;;631 tmpreg1 |= tmpreg2; +000048 4308 ORRS r0,r0,r1 +;;;632 /* Store the new register value */ +;;;633 ADCx->SMPR2 = tmpreg1; +00004a 6120 STR r0,[r4,#0x10] + |L29.76| +;;;634 } +;;;635 /* For Rank 1 to 6 */ +;;;636 if (Rank < 7) +00004c 2a07 CMP r2,#7 +00004e da0f BGE |L29.112| +;;;637 { +;;;638 /* Get the old register value */ +;;;639 tmpreg1 = ADCx->SQR3; +000050 6b60 LDR r0,[r4,#0x34] +;;;640 /* Calculate the mask to clear */ +;;;641 tmpreg2 = SQR3_SQ_Set << (5 * (Rank - 1)); +000052 1e56 SUBS r6,r2,#1 +000054 eb060786 ADD r7,r6,r6,LSL #2 +000058 261f MOVS r6,#0x1f +00005a fa06f107 LSL r1,r6,r7 +;;;642 /* Clear the old SQx bits for the selected rank */ +;;;643 tmpreg1 &= ~tmpreg2; +00005e 4388 BICS r0,r0,r1 +;;;644 /* Calculate the mask to set */ +;;;645 tmpreg2 = (uint32_t)ADC_Channel << (5 * (Rank - 1)); +000060 1e56 SUBS r6,r2,#1 +000062 eb060686 ADD r6,r6,r6,LSL #2 +000066 fa05f106 LSL r1,r5,r6 +;;;646 /* Set the SQx bits for the selected rank */ +;;;647 tmpreg1 |= tmpreg2; +00006a 4308 ORRS r0,r0,r1 +;;;648 /* Store the new register value */ +;;;649 ADCx->SQR3 = tmpreg1; +00006c 6360 STR r0,[r4,#0x34] +00006e e022 B |L29.182| + |L29.112| +;;;650 } +;;;651 /* For Rank 7 to 12 */ +;;;652 else if (Rank < 13) +000070 2a0d CMP r2,#0xd +000072 da0f BGE |L29.148| +;;;653 { +;;;654 /* Get the old register value */ +;;;655 tmpreg1 = ADCx->SQR2; +000074 6b20 LDR r0,[r4,#0x30] +;;;656 /* Calculate the mask to clear */ +;;;657 tmpreg2 = SQR2_SQ_Set << (5 * (Rank - 7)); +000076 1fd6 SUBS r6,r2,#7 +000078 eb060786 ADD r7,r6,r6,LSL #2 +00007c 261f MOVS r6,#0x1f +00007e fa06f107 LSL r1,r6,r7 +;;;658 /* Clear the old SQx bits for the selected rank */ +;;;659 tmpreg1 &= ~tmpreg2; +000082 4388 BICS r0,r0,r1 +;;;660 /* Calculate the mask to set */ +;;;661 tmpreg2 = (uint32_t)ADC_Channel << (5 * (Rank - 7)); +000084 1fd6 SUBS r6,r2,#7 +000086 eb060686 ADD r6,r6,r6,LSL #2 +00008a fa05f106 LSL r1,r5,r6 +;;;662 /* Set the SQx bits for the selected rank */ +;;;663 tmpreg1 |= tmpreg2; +00008e 4308 ORRS r0,r0,r1 +;;;664 /* Store the new register value */ +;;;665 ADCx->SQR2 = tmpreg1; +000090 6320 STR r0,[r4,#0x30] +000092 e010 B |L29.182| + |L29.148| +;;;666 } +;;;667 /* For Rank 13 to 16 */ +;;;668 else +;;;669 { +;;;670 /* Get the old register value */ +;;;671 tmpreg1 = ADCx->SQR1; +000094 6ae0 LDR r0,[r4,#0x2c] +;;;672 /* Calculate the mask to clear */ +;;;673 tmpreg2 = SQR1_SQ_Set << (5 * (Rank - 13)); +000096 f1a2060d SUB r6,r2,#0xd +00009a eb060786 ADD r7,r6,r6,LSL #2 +00009e 261f MOVS r6,#0x1f +0000a0 fa06f107 LSL r1,r6,r7 +;;;674 /* Clear the old SQx bits for the selected rank */ +;;;675 tmpreg1 &= ~tmpreg2; +0000a4 4388 BICS r0,r0,r1 +;;;676 /* Calculate the mask to set */ +;;;677 tmpreg2 = (uint32_t)ADC_Channel << (5 * (Rank - 13)); +0000a6 f1a2060d SUB r6,r2,#0xd +0000aa eb060686 ADD r6,r6,r6,LSL #2 +0000ae fa05f106 LSL r1,r5,r6 +;;;678 /* Set the SQx bits for the selected rank */ +;;;679 tmpreg1 |= tmpreg2; +0000b2 4308 ORRS r0,r0,r1 +;;;680 /* Store the new register value */ +;;;681 ADCx->SQR1 = tmpreg1; +0000b4 62e0 STR r0,[r4,#0x2c] + |L29.182| +;;;682 } +;;;683 } +0000b6 bdf0 POP {r4-r7,pc} +;;;684 + ENDP + + + AREA ||i.ADC_ResetCalibration||, CODE, READONLY, ALIGN=1 + + ADC_ResetCalibration PROC +;;;384 */ +;;;385 void ADC_ResetCalibration(ADC_TypeDef* ADCx) +000000 6881 LDR r1,[r0,#8] +;;;386 { +;;;387 /* Check the parameters */ +;;;388 assert_param(IS_ADC_ALL_PERIPH(ADCx)); +;;;389 /* Resets the selected ADC calibration registers */ +;;;390 ADCx->CR2 |= CR2_RSTCAL_Set; +000002 f0410108 ORR r1,r1,#8 +000006 6081 STR r1,[r0,#8] +;;;391 } +000008 4770 BX lr +;;;392 + ENDP + + + AREA ||i.ADC_SetInjectedOffset||, CODE, READONLY, ALIGN=1 + + ADC_SetInjectedOffset PROC +;;;1030 */ +;;;1031 void ADC_SetInjectedOffset(ADC_TypeDef* ADCx, uint8_t ADC_InjectedChannel, uint16_t Offset) +000000 b508 PUSH {r3,lr} +;;;1032 { +;;;1033 __IO uint32_t tmp = 0; +000002 2300 MOVS r3,#0 +000004 9300 STR r3,[sp,#0] +;;;1034 +;;;1035 /* Check the parameters */ +;;;1036 assert_param(IS_ADC_ALL_PERIPH(ADCx)); +;;;1037 assert_param(IS_ADC_INJECTED_CHANNEL(ADC_InjectedChannel)); +;;;1038 assert_param(IS_ADC_OFFSET(Offset)); +;;;1039 +;;;1040 tmp = (uint32_t)ADCx; +000006 9000 STR r0,[sp,#0] +;;;1041 tmp += ADC_InjectedChannel; +000008 9b00 LDR r3,[sp,#0] +00000a 440b ADD r3,r3,r1 +00000c 9300 STR r3,[sp,#0] +;;;1042 +;;;1043 /* Set the selected injected channel data offset */ +;;;1044 *(__IO uint32_t *) tmp = (uint32_t)Offset; +00000e 9b00 LDR r3,[sp,#0] +000010 601a STR r2,[r3,#0] +;;;1045 } +000012 bd08 POP {r3,pc} +;;;1046 + ENDP + + + AREA ||i.ADC_SoftwareStartConvCmd||, CODE, READONLY, ALIGN=1 + + ADC_SoftwareStartConvCmd PROC +;;;462 */ +;;;463 void ADC_SoftwareStartConvCmd(ADC_TypeDef* ADCx, FunctionalState NewState) +000000 b121 CBZ r1,|L32.12| +;;;464 { +;;;465 /* Check the parameters */ +;;;466 assert_param(IS_ADC_ALL_PERIPH(ADCx)); +;;;467 assert_param(IS_FUNCTIONAL_STATE(NewState)); +;;;468 if (NewState != DISABLE) +;;;469 { +;;;470 /* Enable the selected ADC conversion on external event and start the selected +;;;471 ADC conversion */ +;;;472 ADCx->CR2 |= CR2_EXTTRIG_SWSTART_Set; +000002 6882 LDR r2,[r0,#8] +000004 f44202a0 ORR r2,r2,#0x500000 +000008 6082 STR r2,[r0,#8] +00000a e003 B |L32.20| + |L32.12| +;;;473 } +;;;474 else +;;;475 { +;;;476 /* Disable the selected ADC conversion on external event and stop the selected +;;;477 ADC conversion */ +;;;478 ADCx->CR2 &= CR2_EXTTRIG_SWSTART_Reset; +00000c 6882 LDR r2,[r0,#8] +00000e f42202a0 BIC r2,r2,#0x500000 +000012 6082 STR r2,[r0,#8] + |L32.20| +;;;479 } +;;;480 } +000014 4770 BX lr +;;;481 + ENDP + + + AREA ||i.ADC_SoftwareStartInjectedConvCmd||, CODE, READONLY, ALIGN=1 + + ADC_SoftwareStartInjectedConvCmd PROC +;;;854 */ +;;;855 void ADC_SoftwareStartInjectedConvCmd(ADC_TypeDef* ADCx, FunctionalState NewState) +000000 b121 CBZ r1,|L33.12| +;;;856 { +;;;857 /* Check the parameters */ +;;;858 assert_param(IS_ADC_ALL_PERIPH(ADCx)); +;;;859 assert_param(IS_FUNCTIONAL_STATE(NewState)); +;;;860 if (NewState != DISABLE) +;;;861 { +;;;862 /* Enable the selected ADC conversion for injected group on external event and start the selected +;;;863 ADC injected conversion */ +;;;864 ADCx->CR2 |= CR2_JEXTTRIG_JSWSTART_Set; +000002 6882 LDR r2,[r0,#8] +000004 f4421202 ORR r2,r2,#0x208000 +000008 6082 STR r2,[r0,#8] +00000a e003 B |L33.20| + |L33.12| +;;;865 } +;;;866 else +;;;867 { +;;;868 /* Disable the selected ADC conversion on external event for injected group and stop the selected +;;;869 ADC injected conversion */ +;;;870 ADCx->CR2 &= CR2_JEXTTRIG_JSWSTART_Reset; +00000c 6882 LDR r2,[r0,#8] +00000e f4221202 BIC r2,r2,#0x208000 +000012 6082 STR r2,[r0,#8] + |L33.20| +;;;871 } +;;;872 } +000014 4770 BX lr +;;;873 + ENDP + + + AREA ||i.ADC_StartCalibration||, CODE, READONLY, ALIGN=1 + + ADC_StartCalibration PROC +;;;422 */ +;;;423 void ADC_StartCalibration(ADC_TypeDef* ADCx) +000000 6881 LDR r1,[r0,#8] +;;;424 { +;;;425 /* Check the parameters */ +;;;426 assert_param(IS_ADC_ALL_PERIPH(ADCx)); +;;;427 /* Enable the selected ADC calibration process */ +;;;428 ADCx->CR2 |= CR2_CAL_Set; +000002 f0410104 ORR r1,r1,#4 +000006 6081 STR r1,[r0,#8] +;;;429 } +000008 4770 BX lr +;;;430 + ENDP + + + AREA ||i.ADC_StructInit||, CODE, READONLY, ALIGN=1 + + ADC_StructInit PROC +;;;280 */ +;;;281 void ADC_StructInit(ADC_InitTypeDef* ADC_InitStruct) +000000 2100 MOVS r1,#0 +;;;282 { +;;;283 /* Reset ADC init structure parameters values */ +;;;284 /* Initialize the ADC_Mode member */ +;;;285 ADC_InitStruct->ADC_Mode = ADC_Mode_Independent; +000002 6001 STR r1,[r0,#0] +;;;286 /* initialize the ADC_ScanConvMode member */ +;;;287 ADC_InitStruct->ADC_ScanConvMode = DISABLE; +000004 7101 STRB r1,[r0,#4] +;;;288 /* Initialize the ADC_ContinuousConvMode member */ +;;;289 ADC_InitStruct->ADC_ContinuousConvMode = DISABLE; +000006 7141 STRB r1,[r0,#5] +;;;290 /* Initialize the ADC_ExternalTrigConv member */ +;;;291 ADC_InitStruct->ADC_ExternalTrigConv = ADC_ExternalTrigConv_T1_CC1; +000008 6081 STR r1,[r0,#8] +;;;292 /* Initialize the ADC_DataAlign member */ +;;;293 ADC_InitStruct->ADC_DataAlign = ADC_DataAlign_Right; +00000a 60c1 STR r1,[r0,#0xc] +;;;294 /* Initialize the ADC_NbrOfChannel member */ +;;;295 ADC_InitStruct->ADC_NbrOfChannel = 1; +00000c 2101 MOVS r1,#1 +00000e 7401 STRB r1,[r0,#0x10] +;;;296 } +000010 4770 BX lr +;;;297 + ENDP + + + AREA ||i.ADC_TempSensorVrefintCmd||, CODE, READONLY, ALIGN=2 + + ADC_TempSensorVrefintCmd PROC +;;;1172 */ +;;;1173 void ADC_TempSensorVrefintCmd(FunctionalState NewState) +000000 b130 CBZ r0,|L36.16| +;;;1174 { +;;;1175 /* Check the parameters */ +;;;1176 assert_param(IS_FUNCTIONAL_STATE(NewState)); +;;;1177 if (NewState != DISABLE) +;;;1178 { +;;;1179 /* Enable the temperature sensor and Vrefint channel*/ +;;;1180 ADC1->CR2 |= CR2_TSVREFE_Set; +000002 4907 LDR r1,|L36.32| +000004 6809 LDR r1,[r1,#0] +000006 f4410100 ORR r1,r1,#0x800000 +00000a 4a05 LDR r2,|L36.32| +00000c 6011 STR r1,[r2,#0] +00000e e005 B |L36.28| + |L36.16| +;;;1181 } +;;;1182 else +;;;1183 { +;;;1184 /* Disable the temperature sensor and Vrefint channel*/ +;;;1185 ADC1->CR2 &= CR2_TSVREFE_Reset; +000010 4903 LDR r1,|L36.32| +000012 6809 LDR r1,[r1,#0] +000014 f4210100 BIC r1,r1,#0x800000 +000018 4a01 LDR r2,|L36.32| +00001a 6011 STR r1,[r2,#0] + |L36.28| +;;;1186 } +;;;1187 } +00001c 4770 BX lr +;;;1188 + ENDP + +00001e 0000 DCW 0x0000 + |L36.32| + DCD 0x40012408 + +;*** Start embedded assembler *** + +#line 1 "..\\..\\Libraries\\STM32F10x_StdPeriph_Driver\\src\\stm32f10x_adc.c" + AREA ||.rev16_text||, CODE + THUMB + EXPORT |__asm___15_stm32f10x_adc_c_e11a2ea2____REV16| +#line 114 "..\\..\\Libraries\\CMSIS\\Include\\core_cmInstr.h" +|__asm___15_stm32f10x_adc_c_e11a2ea2____REV16| PROC +#line 115 + + rev16 r0, r0 + bx lr + ENDP + AREA ||.revsh_text||, CODE + THUMB + EXPORT |__asm___15_stm32f10x_adc_c_e11a2ea2____REVSH| +#line 128 +|__asm___15_stm32f10x_adc_c_e11a2ea2____REVSH| PROC +#line 129 + + revsh r0, r0 + bx lr + ENDP + +;*** End embedded assembler *** diff --git a/Project/MDK-ARM/Flash/List/stm32f10x_assert.txt b/Project/MDK-ARM/Flash/List/stm32f10x_assert.txt new file mode 100644 index 0000000..3c39cc0 --- /dev/null +++ b/Project/MDK-ARM/Flash/List/stm32f10x_assert.txt @@ -0,0 +1,29 @@ +; generated by Component: ARM Compiler 5.06 update 7 (build 960) Tool: ArmCC [4d365d] +; commandline ArmCC [--list --split_sections --debug -c --asm --interleave -o.\flash\obj\stm32f10x_assert.o --asm_dir=.\Flash\List\ --list_dir=.\Flash\List\ --depend=.\flash\obj\stm32f10x_assert.d --cpu=Cortex-M3 --apcs=interwork -O0 --diag_suppress=9931,870 -I..\..\Libraries\CMSIS\Device\ST\STM32F10x\Include -I..\..\Libraries\STM32F10x_StdPeriph_Driver\inc -I..\..\Libraries\STM32_USB-FS-Device_Driver\inc -I..\..\Libraries\CMSIS\Include -I..\..\User\bsp -I..\..\User\bsp\inc -I..\..\User\app\inc -I..\..\User -IC:\Users\w1619\AppData\Local\Arm\Packs\Keil\STM32F1xx_DFP\2.4.1\Device\Include -D__MICROLIB -D__UVISION_VERSION=538 -DSTM32F10X_HD -DUSE_STDPERIPH_DRIVER -DSTM32F10X_HD --omf_browse=.\flash\obj\stm32f10x_assert.crf ..\..\User\bsp\stm32f10x_assert.c] + THUMB + +;*** Start embedded assembler *** + +#line 1 "..\\..\\User\\bsp\\stm32f10x_assert.c" + AREA ||.rev16_text||, CODE + THUMB + EXPORT |__asm___18_stm32f10x_assert_c____REV16| +#line 114 "..\\..\\Libraries\\CMSIS\\Include\\core_cmInstr.h" +|__asm___18_stm32f10x_assert_c____REV16| PROC +#line 115 + + rev16 r0, r0 + bx lr + ENDP + AREA ||.revsh_text||, CODE + THUMB + EXPORT |__asm___18_stm32f10x_assert_c____REVSH| +#line 128 +|__asm___18_stm32f10x_assert_c____REVSH| PROC +#line 129 + + revsh r0, r0 + bx lr + ENDP + +;*** End embedded assembler *** diff --git a/Project/MDK-ARM/Flash/List/stm32f10x_dac.txt b/Project/MDK-ARM/Flash/List/stm32f10x_dac.txt new file mode 100644 index 0000000..f86cf9d --- /dev/null +++ b/Project/MDK-ARM/Flash/List/stm32f10x_dac.txt @@ -0,0 +1,522 @@ +; generated by Component: ARM Compiler 5.06 update 7 (build 960) Tool: ArmCC [4d365d] +; commandline ArmCC [--list --split_sections --debug -c --asm --interleave -o.\flash\obj\stm32f10x_dac.o --asm_dir=.\Flash\List\ --list_dir=.\Flash\List\ --depend=.\flash\obj\stm32f10x_dac.d --cpu=Cortex-M3 --apcs=interwork -O0 --diag_suppress=9931,870 -I..\..\Libraries\CMSIS\Device\ST\STM32F10x\Include -I..\..\Libraries\STM32F10x_StdPeriph_Driver\inc -I..\..\Libraries\STM32_USB-FS-Device_Driver\inc -I..\..\Libraries\CMSIS\Include -I..\..\User\bsp -I..\..\User\bsp\inc -I..\..\User\app\inc -I..\..\User -IC:\Users\w1619\AppData\Local\Arm\Packs\Keil\STM32F1xx_DFP\2.4.1\Device\Include -D__MICROLIB -D__UVISION_VERSION=538 -DSTM32F10X_HD -DUSE_STDPERIPH_DRIVER -DSTM32F10X_HD --omf_browse=.\flash\obj\stm32f10x_dac.crf ..\..\Libraries\STM32F10x_StdPeriph_Driver\src\stm32f10x_dac.c] + THUMB + + AREA ||i.DAC_Cmd||, CODE, READONLY, ALIGN=2 + + DAC_Cmd PROC +;;;178 */ +;;;179 void DAC_Cmd(uint32_t DAC_Channel, FunctionalState NewState) +000000 b139 CBZ r1,|L1.18| +;;;180 { +;;;181 /* Check the parameters */ +;;;182 assert_param(IS_DAC_CHANNEL(DAC_Channel)); +;;;183 assert_param(IS_FUNCTIONAL_STATE(NewState)); +;;;184 if (NewState != DISABLE) +;;;185 { +;;;186 /* Enable the selected DAC channel */ +;;;187 DAC->CR |= (DAC_CR_EN1 << DAC_Channel); +000002 4a08 LDR r2,|L1.36| +000004 6812 LDR r2,[r2,#0] +000006 2301 MOVS r3,#1 +000008 4083 LSLS r3,r3,r0 +00000a 431a ORRS r2,r2,r3 +00000c 4b05 LDR r3,|L1.36| +00000e 601a STR r2,[r3,#0] +000010 e006 B |L1.32| + |L1.18| +;;;188 } +;;;189 else +;;;190 { +;;;191 /* Disable the selected DAC channel */ +;;;192 DAC->CR &= ~(DAC_CR_EN1 << DAC_Channel); +000012 4a04 LDR r2,|L1.36| +000014 6812 LDR r2,[r2,#0] +000016 2301 MOVS r3,#1 +000018 4083 LSLS r3,r3,r0 +00001a 439a BICS r2,r2,r3 +00001c 4b01 LDR r3,|L1.36| +00001e 601a STR r2,[r3,#0] + |L1.32| +;;;193 } +;;;194 } +000020 4770 BX lr +;;;195 #if defined (STM32F10X_LD_VL) || defined (STM32F10X_MD_VL) || defined (STM32F10X_HD_VL) + ENDP + +000022 0000 DCW 0x0000 + |L1.36| + DCD 0x40007400 + + AREA ||i.DAC_DMACmd||, CODE, READONLY, ALIGN=2 + + DAC_DMACmd PROC +;;;238 */ +;;;239 void DAC_DMACmd(uint32_t DAC_Channel, FunctionalState NewState) +000000 b141 CBZ r1,|L2.20| +;;;240 { +;;;241 /* Check the parameters */ +;;;242 assert_param(IS_DAC_CHANNEL(DAC_Channel)); +;;;243 assert_param(IS_FUNCTIONAL_STATE(NewState)); +;;;244 if (NewState != DISABLE) +;;;245 { +;;;246 /* Enable the selected DAC channel DMA request */ +;;;247 DAC->CR |= (DAC_CR_DMAEN1 << DAC_Channel); +000002 4a09 LDR r2,|L2.40| +000004 6812 LDR r2,[r2,#0] +000006 f44f5380 MOV r3,#0x1000 +00000a 4083 LSLS r3,r3,r0 +00000c 431a ORRS r2,r2,r3 +00000e 4b06 LDR r3,|L2.40| +000010 601a STR r2,[r3,#0] +000012 e007 B |L2.36| + |L2.20| +;;;248 } +;;;249 else +;;;250 { +;;;251 /* Disable the selected DAC channel DMA request */ +;;;252 DAC->CR &= ~(DAC_CR_DMAEN1 << DAC_Channel); +000014 4a04 LDR r2,|L2.40| +000016 6812 LDR r2,[r2,#0] +000018 f44f5380 MOV r3,#0x1000 +00001c 4083 LSLS r3,r3,r0 +00001e 439a BICS r2,r2,r3 +000020 4b01 LDR r3,|L2.40| +000022 601a STR r2,[r3,#0] + |L2.36| +;;;253 } +;;;254 } +000024 4770 BX lr +;;;255 + ENDP + +000026 0000 DCW 0x0000 + |L2.40| + DCD 0x40007400 + + AREA ||i.DAC_DeInit||, CODE, READONLY, ALIGN=1 + + DAC_DeInit PROC +;;;103 */ +;;;104 void DAC_DeInit(void) +000000 b510 PUSH {r4,lr} +;;;105 { +;;;106 /* Enable DAC reset state */ +;;;107 RCC_APB1PeriphResetCmd(RCC_APB1Periph_DAC, ENABLE); +000002 2101 MOVS r1,#1 +000004 0748 LSLS r0,r1,#29 +000006 f7fffffe BL RCC_APB1PeriphResetCmd +;;;108 /* Release DAC from reset state */ +;;;109 RCC_APB1PeriphResetCmd(RCC_APB1Periph_DAC, DISABLE); +00000a 2100 MOVS r1,#0 +00000c f04f5000 MOV r0,#0x20000000 +000010 f7fffffe BL RCC_APB1PeriphResetCmd +;;;110 } +000014 bd10 POP {r4,pc} +;;;111 + ENDP + + + AREA ||i.DAC_DualSoftwareTriggerCmd||, CODE, READONLY, ALIGN=2 + + DAC_DualSoftwareTriggerCmd PROC +;;;289 */ +;;;290 void DAC_DualSoftwareTriggerCmd(FunctionalState NewState) +000000 b130 CBZ r0,|L4.16| +;;;291 { +;;;292 /* Check the parameters */ +;;;293 assert_param(IS_FUNCTIONAL_STATE(NewState)); +;;;294 if (NewState != DISABLE) +;;;295 { +;;;296 /* Enable software trigger for both DAC channels */ +;;;297 DAC->SWTRIGR |= DUAL_SWTRIG_SET ; +000002 4907 LDR r1,|L4.32| +000004 6809 LDR r1,[r1,#0] +000006 f0410103 ORR r1,r1,#3 +00000a 4a05 LDR r2,|L4.32| +00000c 6011 STR r1,[r2,#0] +00000e e005 B |L4.28| + |L4.16| +;;;298 } +;;;299 else +;;;300 { +;;;301 /* Disable software trigger for both DAC channels */ +;;;302 DAC->SWTRIGR &= DUAL_SWTRIG_RESET; +000010 4903 LDR r1,|L4.32| +000012 6809 LDR r1,[r1,#0] +000014 f0210103 BIC r1,r1,#3 +000018 4a01 LDR r2,|L4.32| +00001a 6011 STR r1,[r2,#0] + |L4.28| +;;;303 } +;;;304 } +00001c 4770 BX lr +;;;305 + ENDP + +00001e 0000 DCW 0x0000 + |L4.32| + DCD 0x40007404 + + AREA ||i.DAC_GetDataOutputValue||, CODE, READONLY, ALIGN=2 + + DAC_GetDataOutputValue PROC +;;;435 */ +;;;436 uint16_t DAC_GetDataOutputValue(uint32_t DAC_Channel) +000000 b508 PUSH {r3,lr} +;;;437 { +000002 4601 MOV r1,r0 +;;;438 __IO uint32_t tmp = 0; +000004 2000 MOVS r0,#0 +000006 9000 STR r0,[sp,#0] +;;;439 +;;;440 /* Check the parameters */ +;;;441 assert_param(IS_DAC_CHANNEL(DAC_Channel)); +;;;442 +;;;443 tmp = (uint32_t) DAC_BASE ; +000008 4805 LDR r0,|L5.32| +00000a 9000 STR r0,[sp,#0] +;;;444 tmp += DOR_OFFSET + ((uint32_t)DAC_Channel >> 2); +00000c 202c MOVS r0,#0x2c +00000e eb000091 ADD r0,r0,r1,LSR #2 +000012 9a00 LDR r2,[sp,#0] +000014 4410 ADD r0,r0,r2 +000016 9000 STR r0,[sp,#0] +;;;445 +;;;446 /* Returns the DAC channel data output register value */ +;;;447 return (uint16_t) (*(__IO uint32_t*) tmp); +000018 9800 LDR r0,[sp,#0] +00001a 6800 LDR r0,[r0,#0] +00001c b280 UXTH r0,r0 +;;;448 } +00001e bd08 POP {r3,pc} +;;;449 + ENDP + + |L5.32| + DCD 0x40007400 + + AREA ||i.DAC_Init||, CODE, READONLY, ALIGN=2 + + DAC_Init PROC +;;;122 */ +;;;123 void DAC_Init(uint32_t DAC_Channel, DAC_InitTypeDef* DAC_InitStruct) +000000 b530 PUSH {r4,r5,lr} +;;;124 { +;;;125 uint32_t tmpreg1 = 0, tmpreg2 = 0; +000002 2200 MOVS r2,#0 +000004 2300 MOVS r3,#0 +;;;126 /* Check the DAC parameters */ +;;;127 assert_param(IS_DAC_TRIGGER(DAC_InitStruct->DAC_Trigger)); +;;;128 assert_param(IS_DAC_GENERATE_WAVE(DAC_InitStruct->DAC_WaveGeneration)); +;;;129 assert_param(IS_DAC_LFSR_UNMASK_TRIANGLE_AMPLITUDE(DAC_InitStruct->DAC_LFSRUnmask_TriangleAmplitude)); +;;;130 assert_param(IS_DAC_OUTPUT_BUFFER_STATE(DAC_InitStruct->DAC_OutputBuffer)); +;;;131 /*---------------------------- DAC CR Configuration --------------------------*/ +;;;132 /* Get the DAC CR value */ +;;;133 tmpreg1 = DAC->CR; +000006 4c0a LDR r4,|L6.48| +000008 6822 LDR r2,[r4,#0] +;;;134 /* Clear BOFFx, TENx, TSELx, WAVEx and MAMPx bits */ +;;;135 tmpreg1 &= ~(CR_CLEAR_MASK << DAC_Channel); +00000a f64074fe MOV r4,#0xffe +00000e 4084 LSLS r4,r4,r0 +000010 43a2 BICS r2,r2,r4 +;;;136 /* Configure for the selected DAC channel: buffer output, trigger, wave generation, +;;;137 mask/amplitude for wave generation */ +;;;138 /* Set TSELx and TENx bits according to DAC_Trigger value */ +;;;139 /* Set WAVEx bits according to DAC_WaveGeneration value */ +;;;140 /* Set MAMPx bits according to DAC_LFSRUnmask_TriangleAmplitude value */ +;;;141 /* Set BOFFx bit according to DAC_OutputBuffer value */ +;;;142 tmpreg2 = (DAC_InitStruct->DAC_Trigger | DAC_InitStruct->DAC_WaveGeneration | +000012 e9d14500 LDRD r4,r5,[r1,#0] +000016 432c ORRS r4,r4,r5 +000018 688d LDR r5,[r1,#8] +00001a 432c ORRS r4,r4,r5 +00001c 68cd LDR r5,[r1,#0xc] +00001e ea440305 ORR r3,r4,r5 +;;;143 DAC_InitStruct->DAC_LFSRUnmask_TriangleAmplitude | DAC_InitStruct->DAC_OutputBuffer); +;;;144 /* Calculate CR register value depending on DAC_Channel */ +;;;145 tmpreg1 |= tmpreg2 << DAC_Channel; +000022 fa03f400 LSL r4,r3,r0 +000026 4322 ORRS r2,r2,r4 +;;;146 /* Write to DAC CR */ +;;;147 DAC->CR = tmpreg1; +000028 4c01 LDR r4,|L6.48| +00002a 6022 STR r2,[r4,#0] +;;;148 } +00002c bd30 POP {r4,r5,pc} +;;;149 + ENDP + +00002e 0000 DCW 0x0000 + |L6.48| + DCD 0x40007400 + + AREA ||i.DAC_SetChannel1Data||, CODE, READONLY, ALIGN=2 + + DAC_SetChannel1Data PROC +;;;347 */ +;;;348 void DAC_SetChannel1Data(uint32_t DAC_Align, uint16_t Data) +000000 b508 PUSH {r3,lr} +;;;349 { +;;;350 __IO uint32_t tmp = 0; +000002 2200 MOVS r2,#0 +000004 9200 STR r2,[sp,#0] +;;;351 +;;;352 /* Check the parameters */ +;;;353 assert_param(IS_DAC_ALIGN(DAC_Align)); +;;;354 assert_param(IS_DAC_DATA(Data)); +;;;355 +;;;356 tmp = (uint32_t)DAC_BASE; +000006 4a05 LDR r2,|L7.28| +000008 9200 STR r2,[sp,#0] +;;;357 tmp += DHR12R1_OFFSET + DAC_Align; +00000a f1000208 ADD r2,r0,#8 +00000e 9b00 LDR r3,[sp,#0] +000010 441a ADD r2,r2,r3 +000012 9200 STR r2,[sp,#0] +;;;358 +;;;359 /* Set the DAC channel1 selected data holding register */ +;;;360 *(__IO uint32_t *) tmp = Data; +000014 9a00 LDR r2,[sp,#0] +000016 6011 STR r1,[r2,#0] +;;;361 } +000018 bd08 POP {r3,pc} +;;;362 + ENDP + +00001a 0000 DCW 0x0000 + |L7.28| + DCD 0x40007400 + + AREA ||i.DAC_SetChannel2Data||, CODE, READONLY, ALIGN=2 + + DAC_SetChannel2Data PROC +;;;372 */ +;;;373 void DAC_SetChannel2Data(uint32_t DAC_Align, uint16_t Data) +000000 b508 PUSH {r3,lr} +;;;374 { +;;;375 __IO uint32_t tmp = 0; +000002 2200 MOVS r2,#0 +000004 9200 STR r2,[sp,#0] +;;;376 +;;;377 /* Check the parameters */ +;;;378 assert_param(IS_DAC_ALIGN(DAC_Align)); +;;;379 assert_param(IS_DAC_DATA(Data)); +;;;380 +;;;381 tmp = (uint32_t)DAC_BASE; +000006 4a05 LDR r2,|L8.28| +000008 9200 STR r2,[sp,#0] +;;;382 tmp += DHR12R2_OFFSET + DAC_Align; +00000a f1000214 ADD r2,r0,#0x14 +00000e 9b00 LDR r3,[sp,#0] +000010 441a ADD r2,r2,r3 +000012 9200 STR r2,[sp,#0] +;;;383 +;;;384 /* Set the DAC channel2 selected data holding register */ +;;;385 *(__IO uint32_t *)tmp = Data; +000014 9a00 LDR r2,[sp,#0] +000016 6011 STR r1,[r2,#0] +;;;386 } +000018 bd08 POP {r3,pc} +;;;387 + ENDP + +00001a 0000 DCW 0x0000 + |L8.28| + DCD 0x40007400 + + AREA ||i.DAC_SetDualChannelData||, CODE, READONLY, ALIGN=2 + + DAC_SetDualChannelData PROC +;;;401 */ +;;;402 void DAC_SetDualChannelData(uint32_t DAC_Align, uint16_t Data2, uint16_t Data1) +000000 b530 PUSH {r4,r5,lr} +;;;403 { +;;;404 uint32_t data = 0, tmp = 0; +000002 2400 MOVS r4,#0 +000004 2300 MOVS r3,#0 +;;;405 +;;;406 /* Check the parameters */ +;;;407 assert_param(IS_DAC_ALIGN(DAC_Align)); +;;;408 assert_param(IS_DAC_DATA(Data1)); +;;;409 assert_param(IS_DAC_DATA(Data2)); +;;;410 +;;;411 /* Calculate and set dual DAC data holding register value */ +;;;412 if (DAC_Align == DAC_Align_8b_R) +000006 2808 CMP r0,#8 +000008 d102 BNE |L9.16| +;;;413 { +;;;414 data = ((uint32_t)Data2 << 8) | Data1; +00000a ea422401 ORR r4,r2,r1,LSL #8 +00000e e001 B |L9.20| + |L9.16| +;;;415 } +;;;416 else +;;;417 { +;;;418 data = ((uint32_t)Data2 << 16) | Data1; +000010 ea424401 ORR r4,r2,r1,LSL #16 + |L9.20| +;;;419 } +;;;420 +;;;421 tmp = (uint32_t)DAC_BASE; +000014 4b02 LDR r3,|L9.32| +;;;422 tmp += DHR12RD_OFFSET + DAC_Align; +000016 f1000520 ADD r5,r0,#0x20 +00001a 442b ADD r3,r3,r5 +;;;423 +;;;424 /* Set the dual DAC selected data holding register */ +;;;425 *(__IO uint32_t *)tmp = data; +00001c 601c STR r4,[r3,#0] +;;;426 } +00001e bd30 POP {r4,r5,pc} +;;;427 + ENDP + + |L9.32| + DCD 0x40007400 + + AREA ||i.DAC_SoftwareTriggerCmd||, CODE, READONLY, ALIGN=2 + + DAC_SoftwareTriggerCmd PROC +;;;265 */ +;;;266 void DAC_SoftwareTriggerCmd(uint32_t DAC_Channel, FunctionalState NewState) +000000 b510 PUSH {r4,lr} +;;;267 { +;;;268 /* Check the parameters */ +;;;269 assert_param(IS_DAC_CHANNEL(DAC_Channel)); +;;;270 assert_param(IS_FUNCTIONAL_STATE(NewState)); +;;;271 if (NewState != DISABLE) +000002 b141 CBZ r1,|L10.22| +;;;272 { +;;;273 /* Enable software trigger for the selected DAC channel */ +;;;274 DAC->SWTRIGR |= (uint32_t)DAC_SWTRIGR_SWTRIG1 << (DAC_Channel >> 4); +000004 4a08 LDR r2,|L10.40| +000006 6812 LDR r2,[r2,#0] +000008 0904 LSRS r4,r0,#4 +00000a 2301 MOVS r3,#1 +00000c 40a3 LSLS r3,r3,r4 +00000e 431a ORRS r2,r2,r3 +000010 4b05 LDR r3,|L10.40| +000012 601a STR r2,[r3,#0] +000014 e007 B |L10.38| + |L10.22| +;;;275 } +;;;276 else +;;;277 { +;;;278 /* Disable software trigger for the selected DAC channel */ +;;;279 DAC->SWTRIGR &= ~((uint32_t)DAC_SWTRIGR_SWTRIG1 << (DAC_Channel >> 4)); +000016 4a04 LDR r2,|L10.40| +000018 6812 LDR r2,[r2,#0] +00001a 0904 LSRS r4,r0,#4 +00001c 2301 MOVS r3,#1 +00001e 40a3 LSLS r3,r3,r4 +000020 439a BICS r2,r2,r3 +000022 4b01 LDR r3,|L10.40| +000024 601a STR r2,[r3,#0] + |L10.38| +;;;280 } +;;;281 } +000026 bd10 POP {r4,pc} +;;;282 + ENDP + + |L10.40| + DCD 0x40007404 + + AREA ||i.DAC_StructInit||, CODE, READONLY, ALIGN=1 + + DAC_StructInit PROC +;;;155 */ +;;;156 void DAC_StructInit(DAC_InitTypeDef* DAC_InitStruct) +000000 2100 MOVS r1,#0 +;;;157 { +;;;158 /*--------------- Reset DAC init structure parameters values -----------------*/ +;;;159 /* Initialize the DAC_Trigger member */ +;;;160 DAC_InitStruct->DAC_Trigger = DAC_Trigger_None; +000002 6001 STR r1,[r0,#0] +;;;161 /* Initialize the DAC_WaveGeneration member */ +;;;162 DAC_InitStruct->DAC_WaveGeneration = DAC_WaveGeneration_None; +000004 6041 STR r1,[r0,#4] +;;;163 /* Initialize the DAC_LFSRUnmask_TriangleAmplitude member */ +;;;164 DAC_InitStruct->DAC_LFSRUnmask_TriangleAmplitude = DAC_LFSRUnmask_Bit0; +000006 6081 STR r1,[r0,#8] +;;;165 /* Initialize the DAC_OutputBuffer member */ +;;;166 DAC_InitStruct->DAC_OutputBuffer = DAC_OutputBuffer_Enable; +000008 60c1 STR r1,[r0,#0xc] +;;;167 } +00000a 4770 BX lr +;;;168 + ENDP + + + AREA ||i.DAC_WaveGenerationCmd||, CODE, READONLY, ALIGN=2 + + DAC_WaveGenerationCmd PROC +;;;319 */ +;;;320 void DAC_WaveGenerationCmd(uint32_t DAC_Channel, uint32_t DAC_Wave, FunctionalState NewState) +000000 b510 PUSH {r4,lr} +;;;321 { +;;;322 /* Check the parameters */ +;;;323 assert_param(IS_DAC_CHANNEL(DAC_Channel)); +;;;324 assert_param(IS_DAC_WAVE(DAC_Wave)); +;;;325 assert_param(IS_FUNCTIONAL_STATE(NewState)); +;;;326 if (NewState != DISABLE) +000002 b13a CBZ r2,|L12.20| +;;;327 { +;;;328 /* Enable the selected wave generation for the selected DAC channel */ +;;;329 DAC->CR |= DAC_Wave << DAC_Channel; +000004 4b07 LDR r3,|L12.36| +000006 681b LDR r3,[r3,#0] +000008 fa01f400 LSL r4,r1,r0 +00000c 4323 ORRS r3,r3,r4 +00000e 4c05 LDR r4,|L12.36| +000010 6023 STR r3,[r4,#0] +000012 e006 B |L12.34| + |L12.20| +;;;330 } +;;;331 else +;;;332 { +;;;333 /* Disable the selected wave generation for the selected DAC channel */ +;;;334 DAC->CR &= ~(DAC_Wave << DAC_Channel); +000014 4b03 LDR r3,|L12.36| +000016 681b LDR r3,[r3,#0] +000018 fa01f400 LSL r4,r1,r0 +00001c 43a3 BICS r3,r3,r4 +00001e 4c01 LDR r4,|L12.36| +000020 6023 STR r3,[r4,#0] + |L12.34| +;;;335 } +;;;336 } +000022 bd10 POP {r4,pc} +;;;337 + ENDP + + |L12.36| + DCD 0x40007400 + +;*** Start embedded assembler *** + +#line 1 "..\\..\\Libraries\\STM32F10x_StdPeriph_Driver\\src\\stm32f10x_dac.c" + AREA ||.rev16_text||, CODE + THUMB + EXPORT |__asm___15_stm32f10x_dac_c_4da4a0a9____REV16| +#line 114 "..\\..\\Libraries\\CMSIS\\Include\\core_cmInstr.h" +|__asm___15_stm32f10x_dac_c_4da4a0a9____REV16| PROC +#line 115 + + rev16 r0, r0 + bx lr + ENDP + AREA ||.revsh_text||, CODE + THUMB + EXPORT |__asm___15_stm32f10x_dac_c_4da4a0a9____REVSH| +#line 128 +|__asm___15_stm32f10x_dac_c_4da4a0a9____REVSH| PROC +#line 129 + + revsh r0, r0 + bx lr + ENDP + +;*** End embedded assembler *** diff --git a/Project/MDK-ARM/Flash/List/stm32f10x_dma.txt b/Project/MDK-ARM/Flash/List/stm32f10x_dma.txt new file mode 100644 index 0000000..33ced8a --- /dev/null +++ b/Project/MDK-ARM/Flash/List/stm32f10x_dma.txt @@ -0,0 +1,744 @@ +; generated by Component: ARM Compiler 5.06 update 7 (build 960) Tool: ArmCC [4d365d] +; commandline ArmCC [--list --split_sections --debug -c --asm --interleave -o.\flash\obj\stm32f10x_dma.o --asm_dir=.\Flash\List\ --list_dir=.\Flash\List\ --depend=.\flash\obj\stm32f10x_dma.d --cpu=Cortex-M3 --apcs=interwork -O0 --diag_suppress=9931,870 -I..\..\Libraries\CMSIS\Device\ST\STM32F10x\Include -I..\..\Libraries\STM32F10x_StdPeriph_Driver\inc -I..\..\Libraries\STM32_USB-FS-Device_Driver\inc -I..\..\Libraries\CMSIS\Include -I..\..\User\bsp -I..\..\User\bsp\inc -I..\..\User\app\inc -I..\..\User -IC:\Users\w1619\AppData\Local\Arm\Packs\Keil\STM32F1xx_DFP\2.4.1\Device\Include -D__MICROLIB -D__UVISION_VERSION=538 -DSTM32F10X_HD -DUSE_STDPERIPH_DRIVER -DSTM32F10X_HD --omf_browse=.\flash\obj\stm32f10x_dma.crf ..\..\Libraries\STM32F10x_StdPeriph_Driver\src\stm32f10x_dma.c] + THUMB + + AREA ||i.DMA_ClearFlag||, CODE, READONLY, ALIGN=2 + + DMA_ClearFlag PROC +;;;528 */ +;;;529 void DMA_ClearFlag(uint32_t DMAy_FLAG) +000000 f0005180 AND r1,r0,#0x10000000 +;;;530 { +;;;531 /* Check the parameters */ +;;;532 assert_param(IS_DMA_CLEAR_FLAG(DMAy_FLAG)); +;;;533 +;;;534 /* Calculate the used DMAy */ +;;;535 if ((DMAy_FLAG & FLAG_Mask) != (uint32_t)RESET) +000004 b111 CBZ r1,|L1.12| +;;;536 { +;;;537 /* Clear the selected DMAy flags */ +;;;538 DMA2->IFCR = DMAy_FLAG; +000006 4903 LDR r1,|L1.20| +000008 6008 STR r0,[r1,#0] +00000a e001 B |L1.16| + |L1.12| +;;;539 } +;;;540 else +;;;541 { +;;;542 /* Clear the selected DMAy flags */ +;;;543 DMA1->IFCR = DMAy_FLAG; +00000c 4902 LDR r1,|L1.24| +00000e 6048 STR r0,[r1,#4] + |L1.16| +;;;544 } +;;;545 } +000010 4770 BX lr +;;;546 + ENDP + +000012 0000 DCW 0x0000 + |L1.20| + DCD 0x40020404 + |L1.24| + DCD 0x40020000 + + AREA ||i.DMA_ClearITPendingBit||, CODE, READONLY, ALIGN=2 + + DMA_ClearITPendingBit PROC +;;;689 */ +;;;690 void DMA_ClearITPendingBit(uint32_t DMAy_IT) +000000 f0005180 AND r1,r0,#0x10000000 +;;;691 { +;;;692 /* Check the parameters */ +;;;693 assert_param(IS_DMA_CLEAR_IT(DMAy_IT)); +;;;694 +;;;695 /* Calculate the used DMAy */ +;;;696 if ((DMAy_IT & FLAG_Mask) != (uint32_t)RESET) +000004 b111 CBZ r1,|L2.12| +;;;697 { +;;;698 /* Clear the selected DMAy interrupt pending bits */ +;;;699 DMA2->IFCR = DMAy_IT; +000006 4903 LDR r1,|L2.20| +000008 6008 STR r0,[r1,#0] +00000a e001 B |L2.16| + |L2.12| +;;;700 } +;;;701 else +;;;702 { +;;;703 /* Clear the selected DMAy interrupt pending bits */ +;;;704 DMA1->IFCR = DMAy_IT; +00000c 4902 LDR r1,|L2.24| +00000e 6048 STR r0,[r1,#4] + |L2.16| +;;;705 } +;;;706 } +000010 4770 BX lr +;;;707 + ENDP + +000012 0000 DCW 0x0000 + |L2.20| + DCD 0x40020404 + |L2.24| + DCD 0x40020000 + + AREA ||i.DMA_Cmd||, CODE, READONLY, ALIGN=1 + + DMA_Cmd PROC +;;;299 */ +;;;300 void DMA_Cmd(DMA_Channel_TypeDef* DMAy_Channelx, FunctionalState NewState) +000000 b121 CBZ r1,|L3.12| +;;;301 { +;;;302 /* Check the parameters */ +;;;303 assert_param(IS_DMA_ALL_PERIPH(DMAy_Channelx)); +;;;304 assert_param(IS_FUNCTIONAL_STATE(NewState)); +;;;305 +;;;306 if (NewState != DISABLE) +;;;307 { +;;;308 /* Enable the selected DMAy Channelx */ +;;;309 DMAy_Channelx->CCR |= DMA_CCR1_EN; +000002 6802 LDR r2,[r0,#0] +000004 f0420201 ORR r2,r2,#1 +000008 6002 STR r2,[r0,#0] +00000a e004 B |L3.22| + |L3.12| +;;;310 } +;;;311 else +;;;312 { +;;;313 /* Disable the selected DMAy Channelx */ +;;;314 DMAy_Channelx->CCR &= (uint16_t)(~DMA_CCR1_EN); +00000c 6802 LDR r2,[r0,#0] +00000e f64f73fe MOV r3,#0xfffe +000012 401a ANDS r2,r2,r3 +000014 6002 STR r2,[r0,#0] + |L3.22| +;;;315 } +;;;316 } +000016 4770 BX lr +;;;317 + ENDP + + + AREA ||i.DMA_DeInit||, CODE, READONLY, ALIGN=2 + + DMA_DeInit PROC +;;;113 */ +;;;114 void DMA_DeInit(DMA_Channel_TypeDef* DMAy_Channelx) +000000 6801 LDR r1,[r0,#0] +;;;115 { +;;;116 /* Check the parameters */ +;;;117 assert_param(IS_DMA_ALL_PERIPH(DMAy_Channelx)); +;;;118 +;;;119 /* Disable the selected DMAy Channelx */ +;;;120 DMAy_Channelx->CCR &= (uint16_t)(~DMA_CCR1_EN); +000002 f64f72fe MOV r2,#0xfffe +000006 4011 ANDS r1,r1,r2 +000008 6001 STR r1,[r0,#0] +;;;121 +;;;122 /* Reset DMAy Channelx control register */ +;;;123 DMAy_Channelx->CCR = 0; +00000a 2100 MOVS r1,#0 +00000c 6001 STR r1,[r0,#0] +;;;124 +;;;125 /* Reset DMAy Channelx remaining bytes register */ +;;;126 DMAy_Channelx->CNDTR = 0; +00000e 6041 STR r1,[r0,#4] +;;;127 +;;;128 /* Reset DMAy Channelx peripheral address register */ +;;;129 DMAy_Channelx->CPAR = 0; +000010 6081 STR r1,[r0,#8] +;;;130 +;;;131 /* Reset DMAy Channelx memory address register */ +;;;132 DMAy_Channelx->CMAR = 0; +000012 60c1 STR r1,[r0,#0xc] +;;;133 +;;;134 if (DMAy_Channelx == DMA1_Channel1) +000014 494b LDR r1,|L4.324| +000016 4288 CMP r0,r1 +000018 d108 BNE |L4.44| +;;;135 { +;;;136 /* Reset interrupt pending bits for DMA1 Channel1 */ +;;;137 DMA1->IFCR |= DMA1_Channel1_IT_Mask; +00001a 494a LDR r1,|L4.324| +00001c 3908 SUBS r1,r1,#8 +00001e 6849 LDR r1,[r1,#4] +000020 f041010f ORR r1,r1,#0xf +000024 4a47 LDR r2,|L4.324| +000026 3a08 SUBS r2,r2,#8 +000028 6051 STR r1,[r2,#4] +00002a e08a B |L4.322| + |L4.44| +;;;138 } +;;;139 else if (DMAy_Channelx == DMA1_Channel2) +00002c 4945 LDR r1,|L4.324| +00002e 3114 ADDS r1,r1,#0x14 +000030 4288 CMP r0,r1 +000032 d108 BNE |L4.70| +;;;140 { +;;;141 /* Reset interrupt pending bits for DMA1 Channel2 */ +;;;142 DMA1->IFCR |= DMA1_Channel2_IT_Mask; +000034 4943 LDR r1,|L4.324| +000036 3908 SUBS r1,r1,#8 +000038 6849 LDR r1,[r1,#4] +00003a f04101f0 ORR r1,r1,#0xf0 +00003e 4a41 LDR r2,|L4.324| +000040 3a08 SUBS r2,r2,#8 +000042 6051 STR r1,[r2,#4] +000044 e07d B |L4.322| + |L4.70| +;;;143 } +;;;144 else if (DMAy_Channelx == DMA1_Channel3) +000046 493f LDR r1,|L4.324| +000048 3128 ADDS r1,r1,#0x28 +00004a 4288 CMP r0,r1 +00004c d108 BNE |L4.96| +;;;145 { +;;;146 /* Reset interrupt pending bits for DMA1 Channel3 */ +;;;147 DMA1->IFCR |= DMA1_Channel3_IT_Mask; +00004e 493d LDR r1,|L4.324| +000050 3908 SUBS r1,r1,#8 +000052 6849 LDR r1,[r1,#4] +000054 f4416170 ORR r1,r1,#0xf00 +000058 4a3a LDR r2,|L4.324| +00005a 3a08 SUBS r2,r2,#8 +00005c 6051 STR r1,[r2,#4] +00005e e070 B |L4.322| + |L4.96| +;;;148 } +;;;149 else if (DMAy_Channelx == DMA1_Channel4) +000060 4938 LDR r1,|L4.324| +000062 313c ADDS r1,r1,#0x3c +000064 4288 CMP r0,r1 +000066 d108 BNE |L4.122| +;;;150 { +;;;151 /* Reset interrupt pending bits for DMA1 Channel4 */ +;;;152 DMA1->IFCR |= DMA1_Channel4_IT_Mask; +000068 4936 LDR r1,|L4.324| +00006a 3908 SUBS r1,r1,#8 +00006c 6849 LDR r1,[r1,#4] +00006e f4414170 ORR r1,r1,#0xf000 +000072 4a34 LDR r2,|L4.324| +000074 3a08 SUBS r2,r2,#8 +000076 6051 STR r1,[r2,#4] +000078 e063 B |L4.322| + |L4.122| +;;;153 } +;;;154 else if (DMAy_Channelx == DMA1_Channel5) +00007a 4932 LDR r1,|L4.324| +00007c 3150 ADDS r1,r1,#0x50 +00007e 4288 CMP r0,r1 +000080 d108 BNE |L4.148| +;;;155 { +;;;156 /* Reset interrupt pending bits for DMA1 Channel5 */ +;;;157 DMA1->IFCR |= DMA1_Channel5_IT_Mask; +000082 4930 LDR r1,|L4.324| +000084 3908 SUBS r1,r1,#8 +000086 6849 LDR r1,[r1,#4] +000088 f4412170 ORR r1,r1,#0xf0000 +00008c 4a2d LDR r2,|L4.324| +00008e 3a08 SUBS r2,r2,#8 +000090 6051 STR r1,[r2,#4] +000092 e056 B |L4.322| + |L4.148| +;;;158 } +;;;159 else if (DMAy_Channelx == DMA1_Channel6) +000094 492b LDR r1,|L4.324| +000096 3164 ADDS r1,r1,#0x64 +000098 4288 CMP r0,r1 +00009a d108 BNE |L4.174| +;;;160 { +;;;161 /* Reset interrupt pending bits for DMA1 Channel6 */ +;;;162 DMA1->IFCR |= DMA1_Channel6_IT_Mask; +00009c 4929 LDR r1,|L4.324| +00009e 3908 SUBS r1,r1,#8 +0000a0 6849 LDR r1,[r1,#4] +0000a2 f4410170 ORR r1,r1,#0xf00000 +0000a6 4a27 LDR r2,|L4.324| +0000a8 3a08 SUBS r2,r2,#8 +0000aa 6051 STR r1,[r2,#4] +0000ac e049 B |L4.322| + |L4.174| +;;;163 } +;;;164 else if (DMAy_Channelx == DMA1_Channel7) +0000ae 4925 LDR r1,|L4.324| +0000b0 3178 ADDS r1,r1,#0x78 +0000b2 4288 CMP r0,r1 +0000b4 d108 BNE |L4.200| +;;;165 { +;;;166 /* Reset interrupt pending bits for DMA1 Channel7 */ +;;;167 DMA1->IFCR |= DMA1_Channel7_IT_Mask; +0000b6 4923 LDR r1,|L4.324| +0000b8 3908 SUBS r1,r1,#8 +0000ba 6849 LDR r1,[r1,#4] +0000bc f0416170 ORR r1,r1,#0xf000000 +0000c0 4a20 LDR r2,|L4.324| +0000c2 3a08 SUBS r2,r2,#8 +0000c4 6051 STR r1,[r2,#4] +0000c6 e03c B |L4.322| + |L4.200| +;;;168 } +;;;169 else if (DMAy_Channelx == DMA2_Channel1) +0000c8 491f LDR r1,|L4.328| +0000ca 4288 CMP r0,r1 +0000cc d106 BNE |L4.220| +;;;170 { +;;;171 /* Reset interrupt pending bits for DMA2 Channel1 */ +;;;172 DMA2->IFCR |= DMA2_Channel1_IT_Mask; +0000ce 1f01 SUBS r1,r0,#4 +0000d0 6809 LDR r1,[r1,#0] +0000d2 f041010f ORR r1,r1,#0xf +0000d6 1f02 SUBS r2,r0,#4 +0000d8 6011 STR r1,[r2,#0] +0000da e032 B |L4.322| + |L4.220| +;;;173 } +;;;174 else if (DMAy_Channelx == DMA2_Channel2) +0000dc 491a LDR r1,|L4.328| +0000de 3114 ADDS r1,r1,#0x14 +0000e0 4288 CMP r0,r1 +0000e2 d108 BNE |L4.246| +;;;175 { +;;;176 /* Reset interrupt pending bits for DMA2 Channel2 */ +;;;177 DMA2->IFCR |= DMA2_Channel2_IT_Mask; +0000e4 4918 LDR r1,|L4.328| +0000e6 1f09 SUBS r1,r1,#4 +0000e8 6809 LDR r1,[r1,#0] +0000ea f04101f0 ORR r1,r1,#0xf0 +0000ee 4a16 LDR r2,|L4.328| +0000f0 1f12 SUBS r2,r2,#4 +0000f2 6011 STR r1,[r2,#0] +0000f4 e025 B |L4.322| + |L4.246| +;;;178 } +;;;179 else if (DMAy_Channelx == DMA2_Channel3) +0000f6 4914 LDR r1,|L4.328| +0000f8 3128 ADDS r1,r1,#0x28 +0000fa 4288 CMP r0,r1 +0000fc d108 BNE |L4.272| +;;;180 { +;;;181 /* Reset interrupt pending bits for DMA2 Channel3 */ +;;;182 DMA2->IFCR |= DMA2_Channel3_IT_Mask; +0000fe 4912 LDR r1,|L4.328| +000100 1f09 SUBS r1,r1,#4 +000102 6809 LDR r1,[r1,#0] +000104 f4416170 ORR r1,r1,#0xf00 +000108 4a0f LDR r2,|L4.328| +00010a 1f12 SUBS r2,r2,#4 +00010c 6011 STR r1,[r2,#0] +00010e e018 B |L4.322| + |L4.272| +;;;183 } +;;;184 else if (DMAy_Channelx == DMA2_Channel4) +000110 490d LDR r1,|L4.328| +000112 313c ADDS r1,r1,#0x3c +000114 4288 CMP r0,r1 +000116 d108 BNE |L4.298| +;;;185 { +;;;186 /* Reset interrupt pending bits for DMA2 Channel4 */ +;;;187 DMA2->IFCR |= DMA2_Channel4_IT_Mask; +000118 490b LDR r1,|L4.328| +00011a 1f09 SUBS r1,r1,#4 +00011c 6809 LDR r1,[r1,#0] +00011e f4414170 ORR r1,r1,#0xf000 +000122 4a09 LDR r2,|L4.328| +000124 1f12 SUBS r2,r2,#4 +000126 6011 STR r1,[r2,#0] +000128 e00b B |L4.322| + |L4.298| +;;;188 } +;;;189 else +;;;190 { +;;;191 if (DMAy_Channelx == DMA2_Channel5) +00012a 4907 LDR r1,|L4.328| +00012c 3150 ADDS r1,r1,#0x50 +00012e 4288 CMP r0,r1 +000130 d107 BNE |L4.322| +;;;192 { +;;;193 /* Reset interrupt pending bits for DMA2 Channel5 */ +;;;194 DMA2->IFCR |= DMA2_Channel5_IT_Mask; +000132 4905 LDR r1,|L4.328| +000134 1f09 SUBS r1,r1,#4 +000136 6809 LDR r1,[r1,#0] +000138 f4412170 ORR r1,r1,#0xf0000 +00013c 4a02 LDR r2,|L4.328| +00013e 1f12 SUBS r2,r2,#4 +000140 6011 STR r1,[r2,#0] + |L4.322| +;;;195 } +;;;196 } +;;;197 } +000142 4770 BX lr +;;;198 + ENDP + + |L4.324| + DCD 0x40020008 + |L4.328| + DCD 0x40020408 + + AREA ||i.DMA_GetCurrDataCounter||, CODE, READONLY, ALIGN=1 + + DMA_GetCurrDataCounter PROC +;;;376 */ +;;;377 uint16_t DMA_GetCurrDataCounter(DMA_Channel_TypeDef* DMAy_Channelx) +000000 4601 MOV r1,r0 +;;;378 { +;;;379 /* Check the parameters */ +;;;380 assert_param(IS_DMA_ALL_PERIPH(DMAy_Channelx)); +;;;381 /* Return the number of remaining data units for DMAy Channelx */ +;;;382 return ((uint16_t)(DMAy_Channelx->CNDTR)); +000002 6848 LDR r0,[r1,#4] +000004 b280 UXTH r0,r0 +;;;383 } +000006 4770 BX lr +;;;384 + ENDP + + + AREA ||i.DMA_GetFlagStatus||, CODE, READONLY, ALIGN=2 + + DMA_GetFlagStatus PROC +;;;438 */ +;;;439 FlagStatus DMA_GetFlagStatus(uint32_t DMAy_FLAG) +000000 4601 MOV r1,r0 +;;;440 { +;;;441 FlagStatus bitstatus = RESET; +000002 2000 MOVS r0,#0 +;;;442 uint32_t tmpreg = 0; +000004 2200 MOVS r2,#0 +;;;443 +;;;444 /* Check the parameters */ +;;;445 assert_param(IS_DMA_GET_FLAG(DMAy_FLAG)); +;;;446 +;;;447 /* Calculate the used DMAy */ +;;;448 if ((DMAy_FLAG & FLAG_Mask) != (uint32_t)RESET) +000006 f0015380 AND r3,r1,#0x10000000 +00000a b113 CBZ r3,|L6.18| +;;;449 { +;;;450 /* Get DMA2 ISR register value */ +;;;451 tmpreg = DMA2->ISR ; +00000c 4b05 LDR r3,|L6.36| +00000e 681a LDR r2,[r3,#0] +000010 e001 B |L6.22| + |L6.18| +;;;452 } +;;;453 else +;;;454 { +;;;455 /* Get DMA1 ISR register value */ +;;;456 tmpreg = DMA1->ISR ; +000012 4b05 LDR r3,|L6.40| +000014 681a LDR r2,[r3,#0] + |L6.22| +;;;457 } +;;;458 +;;;459 /* Check the status of the specified DMAy flag */ +;;;460 if ((tmpreg & DMAy_FLAG) != (uint32_t)RESET) +000016 ea020301 AND r3,r2,r1 +00001a b10b CBZ r3,|L6.32| +;;;461 { +;;;462 /* DMAy_FLAG is set */ +;;;463 bitstatus = SET; +00001c 2001 MOVS r0,#1 +00001e e000 B |L6.34| + |L6.32| +;;;464 } +;;;465 else +;;;466 { +;;;467 /* DMAy_FLAG is reset */ +;;;468 bitstatus = RESET; +000020 2000 MOVS r0,#0 + |L6.34| +;;;469 } +;;;470 +;;;471 /* Return the DMAy_FLAG status */ +;;;472 return bitstatus; +;;;473 } +000022 4770 BX lr +;;;474 + ENDP + + |L6.36| + DCD 0x40020400 + |L6.40| + DCD 0x40020000 + + AREA ||i.DMA_GetITStatus||, CODE, READONLY, ALIGN=2 + + DMA_GetITStatus PROC +;;;600 */ +;;;601 ITStatus DMA_GetITStatus(uint32_t DMAy_IT) +000000 4601 MOV r1,r0 +;;;602 { +;;;603 ITStatus bitstatus = RESET; +000002 2000 MOVS r0,#0 +;;;604 uint32_t tmpreg = 0; +000004 2200 MOVS r2,#0 +;;;605 +;;;606 /* Check the parameters */ +;;;607 assert_param(IS_DMA_GET_IT(DMAy_IT)); +;;;608 +;;;609 /* Calculate the used DMA */ +;;;610 if ((DMAy_IT & FLAG_Mask) != (uint32_t)RESET) +000006 f0015380 AND r3,r1,#0x10000000 +00000a b113 CBZ r3,|L7.18| +;;;611 { +;;;612 /* Get DMA2 ISR register value */ +;;;613 tmpreg = DMA2->ISR; +00000c 4b05 LDR r3,|L7.36| +00000e 681a LDR r2,[r3,#0] +000010 e001 B |L7.22| + |L7.18| +;;;614 } +;;;615 else +;;;616 { +;;;617 /* Get DMA1 ISR register value */ +;;;618 tmpreg = DMA1->ISR; +000012 4b05 LDR r3,|L7.40| +000014 681a LDR r2,[r3,#0] + |L7.22| +;;;619 } +;;;620 +;;;621 /* Check the status of the specified DMAy interrupt */ +;;;622 if ((tmpreg & DMAy_IT) != (uint32_t)RESET) +000016 ea020301 AND r3,r2,r1 +00001a b10b CBZ r3,|L7.32| +;;;623 { +;;;624 /* DMAy_IT is set */ +;;;625 bitstatus = SET; +00001c 2001 MOVS r0,#1 +00001e e000 B |L7.34| + |L7.32| +;;;626 } +;;;627 else +;;;628 { +;;;629 /* DMAy_IT is reset */ +;;;630 bitstatus = RESET; +000020 2000 MOVS r0,#0 + |L7.34| +;;;631 } +;;;632 /* Return the DMA_IT status */ +;;;633 return bitstatus; +;;;634 } +000022 4770 BX lr +;;;635 + ENDP + + |L7.36| + DCD 0x40020400 + |L7.40| + DCD 0x40020000 + + AREA ||i.DMA_ITConfig||, CODE, READONLY, ALIGN=1 + + DMA_ITConfig PROC +;;;331 */ +;;;332 void DMA_ITConfig(DMA_Channel_TypeDef* DMAy_Channelx, uint32_t DMA_IT, FunctionalState NewState) +000000 b11a CBZ r2,|L8.10| +;;;333 { +;;;334 /* Check the parameters */ +;;;335 assert_param(IS_DMA_ALL_PERIPH(DMAy_Channelx)); +;;;336 assert_param(IS_DMA_CONFIG_IT(DMA_IT)); +;;;337 assert_param(IS_FUNCTIONAL_STATE(NewState)); +;;;338 if (NewState != DISABLE) +;;;339 { +;;;340 /* Enable the selected DMA interrupts */ +;;;341 DMAy_Channelx->CCR |= DMA_IT; +000002 6803 LDR r3,[r0,#0] +000004 430b ORRS r3,r3,r1 +000006 6003 STR r3,[r0,#0] +000008 e002 B |L8.16| + |L8.10| +;;;342 } +;;;343 else +;;;344 { +;;;345 /* Disable the selected DMA interrupts */ +;;;346 DMAy_Channelx->CCR &= ~DMA_IT; +00000a 6803 LDR r3,[r0,#0] +00000c 438b BICS r3,r3,r1 +00000e 6003 STR r3,[r0,#0] + |L8.16| +;;;347 } +;;;348 } +000010 4770 BX lr +;;;349 + ENDP + + + AREA ||i.DMA_Init||, CODE, READONLY, ALIGN=1 + + DMA_Init PROC +;;;207 */ +;;;208 void DMA_Init(DMA_Channel_TypeDef* DMAy_Channelx, DMA_InitTypeDef* DMA_InitStruct) +000000 b510 PUSH {r4,lr} +;;;209 { +;;;210 uint32_t tmpreg = 0; +000002 2200 MOVS r2,#0 +;;;211 +;;;212 /* Check the parameters */ +;;;213 assert_param(IS_DMA_ALL_PERIPH(DMAy_Channelx)); +;;;214 assert_param(IS_DMA_DIR(DMA_InitStruct->DMA_DIR)); +;;;215 assert_param(IS_DMA_BUFFER_SIZE(DMA_InitStruct->DMA_BufferSize)); +;;;216 assert_param(IS_DMA_PERIPHERAL_INC_STATE(DMA_InitStruct->DMA_PeripheralInc)); +;;;217 assert_param(IS_DMA_MEMORY_INC_STATE(DMA_InitStruct->DMA_MemoryInc)); +;;;218 assert_param(IS_DMA_PERIPHERAL_DATA_SIZE(DMA_InitStruct->DMA_PeripheralDataSize)); +;;;219 assert_param(IS_DMA_MEMORY_DATA_SIZE(DMA_InitStruct->DMA_MemoryDataSize)); +;;;220 assert_param(IS_DMA_MODE(DMA_InitStruct->DMA_Mode)); +;;;221 assert_param(IS_DMA_PRIORITY(DMA_InitStruct->DMA_Priority)); +;;;222 assert_param(IS_DMA_M2M_STATE(DMA_InitStruct->DMA_M2M)); +;;;223 +;;;224 /*--------------------------- DMAy Channelx CCR Configuration -----------------*/ +;;;225 /* Get the DMAy_Channelx CCR value */ +;;;226 tmpreg = DMAy_Channelx->CCR; +000004 6802 LDR r2,[r0,#0] +;;;227 /* Clear MEM2MEM, PL, MSIZE, PSIZE, MINC, PINC, CIRC and DIR bits */ +;;;228 tmpreg &= CCR_CLEAR_Mask; +000006 f64773f0 MOV r3,#0x7ff0 +00000a 439a BICS r2,r2,r3 +;;;229 /* Configure DMAy Channelx: data transfer, data size, priority level and mode */ +;;;230 /* Set DIR bit according to DMA_DIR value */ +;;;231 /* Set CIRC bit according to DMA_Mode value */ +;;;232 /* Set PINC bit according to DMA_PeripheralInc value */ +;;;233 /* Set MINC bit according to DMA_MemoryInc value */ +;;;234 /* Set PSIZE bits according to DMA_PeripheralDataSize value */ +;;;235 /* Set MSIZE bits according to DMA_MemoryDataSize value */ +;;;236 /* Set PL bits according to DMA_Priority value */ +;;;237 /* Set the MEM2MEM bit according to DMA_M2M value */ +;;;238 tmpreg |= DMA_InitStruct->DMA_DIR | DMA_InitStruct->DMA_Mode | +00000c 6a0c LDR r4,[r1,#0x20] +00000e 688b LDR r3,[r1,#8] +000010 4323 ORRS r3,r3,r4 +000012 690c LDR r4,[r1,#0x10] +000014 4323 ORRS r3,r3,r4 +000016 694c LDR r4,[r1,#0x14] +000018 4323 ORRS r3,r3,r4 +00001a 698c LDR r4,[r1,#0x18] +00001c 4323 ORRS r3,r3,r4 +00001e 69cc LDR r4,[r1,#0x1c] +000020 4323 ORRS r3,r3,r4 +000022 6a4c LDR r4,[r1,#0x24] +000024 4323 ORRS r3,r3,r4 +000026 6a8c LDR r4,[r1,#0x28] +000028 4323 ORRS r3,r3,r4 +00002a 431a ORRS r2,r2,r3 +;;;239 DMA_InitStruct->DMA_PeripheralInc | DMA_InitStruct->DMA_MemoryInc | +;;;240 DMA_InitStruct->DMA_PeripheralDataSize | DMA_InitStruct->DMA_MemoryDataSize | +;;;241 DMA_InitStruct->DMA_Priority | DMA_InitStruct->DMA_M2M; +;;;242 +;;;243 /* Write to DMAy Channelx CCR */ +;;;244 DMAy_Channelx->CCR = tmpreg; +00002c 6002 STR r2,[r0,#0] +;;;245 +;;;246 /*--------------------------- DMAy Channelx CNDTR Configuration ---------------*/ +;;;247 /* Write to DMAy Channelx CNDTR */ +;;;248 DMAy_Channelx->CNDTR = DMA_InitStruct->DMA_BufferSize; +00002e 68cb LDR r3,[r1,#0xc] +000030 6043 STR r3,[r0,#4] +;;;249 +;;;250 /*--------------------------- DMAy Channelx CPAR Configuration ----------------*/ +;;;251 /* Write to DMAy Channelx CPAR */ +;;;252 DMAy_Channelx->CPAR = DMA_InitStruct->DMA_PeripheralBaseAddr; +000032 680b LDR r3,[r1,#0] +000034 6083 STR r3,[r0,#8] +;;;253 +;;;254 /*--------------------------- DMAy Channelx CMAR Configuration ----------------*/ +;;;255 /* Write to DMAy Channelx CMAR */ +;;;256 DMAy_Channelx->CMAR = DMA_InitStruct->DMA_MemoryBaseAddr; +000036 684b LDR r3,[r1,#4] +000038 60c3 STR r3,[r0,#0xc] +;;;257 } +00003a bd10 POP {r4,pc} +;;;258 + ENDP + + + AREA ||i.DMA_SetCurrDataCounter||, CODE, READONLY, ALIGN=1 + + DMA_SetCurrDataCounter PROC +;;;358 */ +;;;359 void DMA_SetCurrDataCounter(DMA_Channel_TypeDef* DMAy_Channelx, uint16_t DataNumber) +000000 6041 STR r1,[r0,#4] +;;;360 { +;;;361 /* Check the parameters */ +;;;362 assert_param(IS_DMA_ALL_PERIPH(DMAy_Channelx)); +;;;363 +;;;364 /*--------------------------- DMAy Channelx CNDTR Configuration ---------------*/ +;;;365 /* Write to DMAy Channelx CNDTR */ +;;;366 DMAy_Channelx->CNDTR = DataNumber; +;;;367 } +000002 4770 BX lr +;;;368 + ENDP + + + AREA ||i.DMA_StructInit||, CODE, READONLY, ALIGN=1 + + DMA_StructInit PROC +;;;264 */ +;;;265 void DMA_StructInit(DMA_InitTypeDef* DMA_InitStruct) +000000 2100 MOVS r1,#0 +;;;266 { +;;;267 /*-------------- Reset DMA init structure parameters values ------------------*/ +;;;268 /* Initialize the DMA_PeripheralBaseAddr member */ +;;;269 DMA_InitStruct->DMA_PeripheralBaseAddr = 0; +000002 6001 STR r1,[r0,#0] +;;;270 /* Initialize the DMA_MemoryBaseAddr member */ +;;;271 DMA_InitStruct->DMA_MemoryBaseAddr = 0; +000004 6041 STR r1,[r0,#4] +;;;272 /* Initialize the DMA_DIR member */ +;;;273 DMA_InitStruct->DMA_DIR = DMA_DIR_PeripheralSRC; +000006 6081 STR r1,[r0,#8] +;;;274 /* Initialize the DMA_BufferSize member */ +;;;275 DMA_InitStruct->DMA_BufferSize = 0; +000008 60c1 STR r1,[r0,#0xc] +;;;276 /* Initialize the DMA_PeripheralInc member */ +;;;277 DMA_InitStruct->DMA_PeripheralInc = DMA_PeripheralInc_Disable; +00000a 6101 STR r1,[r0,#0x10] +;;;278 /* Initialize the DMA_MemoryInc member */ +;;;279 DMA_InitStruct->DMA_MemoryInc = DMA_MemoryInc_Disable; +00000c 6141 STR r1,[r0,#0x14] +;;;280 /* Initialize the DMA_PeripheralDataSize member */ +;;;281 DMA_InitStruct->DMA_PeripheralDataSize = DMA_PeripheralDataSize_Byte; +00000e 6181 STR r1,[r0,#0x18] +;;;282 /* Initialize the DMA_MemoryDataSize member */ +;;;283 DMA_InitStruct->DMA_MemoryDataSize = DMA_MemoryDataSize_Byte; +000010 61c1 STR r1,[r0,#0x1c] +;;;284 /* Initialize the DMA_Mode member */ +;;;285 DMA_InitStruct->DMA_Mode = DMA_Mode_Normal; +000012 6201 STR r1,[r0,#0x20] +;;;286 /* Initialize the DMA_Priority member */ +;;;287 DMA_InitStruct->DMA_Priority = DMA_Priority_Low; +000014 6241 STR r1,[r0,#0x24] +;;;288 /* Initialize the DMA_M2M member */ +;;;289 DMA_InitStruct->DMA_M2M = DMA_M2M_Disable; +000016 6281 STR r1,[r0,#0x28] +;;;290 } +000018 4770 BX lr +;;;291 + ENDP + + +;*** Start embedded assembler *** + +#line 1 "..\\..\\Libraries\\STM32F10x_StdPeriph_Driver\\src\\stm32f10x_dma.c" + AREA ||.rev16_text||, CODE + THUMB + EXPORT |__asm___15_stm32f10x_dma_c_e9b554c0____REV16| +#line 114 "..\\..\\Libraries\\CMSIS\\Include\\core_cmInstr.h" +|__asm___15_stm32f10x_dma_c_e9b554c0____REV16| PROC +#line 115 + + rev16 r0, r0 + bx lr + ENDP + AREA ||.revsh_text||, CODE + THUMB + EXPORT |__asm___15_stm32f10x_dma_c_e9b554c0____REVSH| +#line 128 +|__asm___15_stm32f10x_dma_c_e9b554c0____REVSH| PROC +#line 129 + + revsh r0, r0 + bx lr + ENDP + +;*** End embedded assembler *** diff --git a/Project/MDK-ARM/Flash/List/stm32f10x_gpio.txt b/Project/MDK-ARM/Flash/List/stm32f10x_gpio.txt new file mode 100644 index 0000000..7737fc9 --- /dev/null +++ b/Project/MDK-ARM/Flash/List/stm32f10x_gpio.txt @@ -0,0 +1,887 @@ +; generated by Component: ARM Compiler 5.06 update 7 (build 960) Tool: ArmCC [4d365d] +; commandline ArmCC [--list --split_sections --debug -c --asm --interleave -o.\flash\obj\stm32f10x_gpio.o --asm_dir=.\Flash\List\ --list_dir=.\Flash\List\ --depend=.\flash\obj\stm32f10x_gpio.d --cpu=Cortex-M3 --apcs=interwork -O0 --diag_suppress=9931,870 -I..\..\Libraries\CMSIS\Device\ST\STM32F10x\Include -I..\..\Libraries\STM32F10x_StdPeriph_Driver\inc -I..\..\Libraries\STM32_USB-FS-Device_Driver\inc -I..\..\Libraries\CMSIS\Include -I..\..\User\bsp -I..\..\User\bsp\inc -I..\..\User\app\inc -I..\..\User -IC:\Users\w1619\AppData\Local\Arm\Packs\Keil\STM32F1xx_DFP\2.4.1\Device\Include -D__MICROLIB -D__UVISION_VERSION=538 -DSTM32F10X_HD -DUSE_STDPERIPH_DRIVER -DSTM32F10X_HD --omf_browse=.\flash\obj\stm32f10x_gpio.crf ..\..\Libraries\STM32F10x_StdPeriph_Driver\src\stm32f10x_gpio.c] + THUMB + + AREA ||i.GPIO_AFIODeInit||, CODE, READONLY, ALIGN=1 + + GPIO_AFIODeInit PROC +;;;162 */ +;;;163 void GPIO_AFIODeInit(void) +000000 b510 PUSH {r4,lr} +;;;164 { +;;;165 RCC_APB2PeriphResetCmd(RCC_APB2Periph_AFIO, ENABLE); +000002 2101 MOVS r1,#1 +000004 4608 MOV r0,r1 +000006 f7fffffe BL RCC_APB2PeriphResetCmd +;;;166 RCC_APB2PeriphResetCmd(RCC_APB2Periph_AFIO, DISABLE); +00000a 2100 MOVS r1,#0 +00000c 2001 MOVS r0,#1 +00000e f7fffffe BL RCC_APB2PeriphResetCmd +;;;167 } +000012 bd10 POP {r4,pc} +;;;168 + ENDP + + + AREA ||i.GPIO_DeInit||, CODE, READONLY, ALIGN=2 + + GPIO_DeInit PROC +;;;111 */ +;;;112 void GPIO_DeInit(GPIO_TypeDef *GPIOx) +000000 b510 PUSH {r4,lr} +;;;113 { +000002 4604 MOV r4,r0 +;;;114 /* Check the parameters */ +;;;115 assert_param(IS_GPIO_ALL_PERIPH(GPIOx)); +;;;116 +;;;117 if (GPIOx == GPIOA) +000004 4829 LDR r0,|L2.172| +000006 4284 CMP r4,r0 +000008 d108 BNE |L2.28| +;;;118 { +;;;119 RCC_APB2PeriphResetCmd(RCC_APB2Periph_GPIOA, ENABLE); +00000a 2101 MOVS r1,#1 +00000c 2004 MOVS r0,#4 +00000e f7fffffe BL RCC_APB2PeriphResetCmd +;;;120 RCC_APB2PeriphResetCmd(RCC_APB2Periph_GPIOA, DISABLE); +000012 2100 MOVS r1,#0 +000014 2004 MOVS r0,#4 +000016 f7fffffe BL RCC_APB2PeriphResetCmd +00001a e046 B |L2.170| + |L2.28| +;;;121 } +;;;122 else if (GPIOx == GPIOB) +00001c 4824 LDR r0,|L2.176| +00001e 4284 CMP r4,r0 +000020 d108 BNE |L2.52| +;;;123 { +;;;124 RCC_APB2PeriphResetCmd(RCC_APB2Periph_GPIOB, ENABLE); +000022 2101 MOVS r1,#1 +000024 2008 MOVS r0,#8 +000026 f7fffffe BL RCC_APB2PeriphResetCmd +;;;125 RCC_APB2PeriphResetCmd(RCC_APB2Periph_GPIOB, DISABLE); +00002a 2100 MOVS r1,#0 +00002c 2008 MOVS r0,#8 +00002e f7fffffe BL RCC_APB2PeriphResetCmd +000032 e03a B |L2.170| + |L2.52| +;;;126 } +;;;127 else if (GPIOx == GPIOC) +000034 481f LDR r0,|L2.180| +000036 4284 CMP r4,r0 +000038 d108 BNE |L2.76| +;;;128 { +;;;129 RCC_APB2PeriphResetCmd(RCC_APB2Periph_GPIOC, ENABLE); +00003a 2101 MOVS r1,#1 +00003c 2010 MOVS r0,#0x10 +00003e f7fffffe BL RCC_APB2PeriphResetCmd +;;;130 RCC_APB2PeriphResetCmd(RCC_APB2Periph_GPIOC, DISABLE); +000042 2100 MOVS r1,#0 +000044 2010 MOVS r0,#0x10 +000046 f7fffffe BL RCC_APB2PeriphResetCmd +00004a e02e B |L2.170| + |L2.76| +;;;131 } +;;;132 else if (GPIOx == GPIOD) +00004c 481a LDR r0,|L2.184| +00004e 4284 CMP r4,r0 +000050 d108 BNE |L2.100| +;;;133 { +;;;134 RCC_APB2PeriphResetCmd(RCC_APB2Periph_GPIOD, ENABLE); +000052 2101 MOVS r1,#1 +000054 2020 MOVS r0,#0x20 +000056 f7fffffe BL RCC_APB2PeriphResetCmd +;;;135 RCC_APB2PeriphResetCmd(RCC_APB2Periph_GPIOD, DISABLE); +00005a 2100 MOVS r1,#0 +00005c 2020 MOVS r0,#0x20 +00005e f7fffffe BL RCC_APB2PeriphResetCmd +000062 e022 B |L2.170| + |L2.100| +;;;136 } +;;;137 else if (GPIOx == GPIOE) +000064 4815 LDR r0,|L2.188| +000066 4284 CMP r4,r0 +000068 d108 BNE |L2.124| +;;;138 { +;;;139 RCC_APB2PeriphResetCmd(RCC_APB2Periph_GPIOE, ENABLE); +00006a 2101 MOVS r1,#1 +00006c 2040 MOVS r0,#0x40 +00006e f7fffffe BL RCC_APB2PeriphResetCmd +;;;140 RCC_APB2PeriphResetCmd(RCC_APB2Periph_GPIOE, DISABLE); +000072 2100 MOVS r1,#0 +000074 2040 MOVS r0,#0x40 +000076 f7fffffe BL RCC_APB2PeriphResetCmd +00007a e016 B |L2.170| + |L2.124| +;;;141 } +;;;142 else if (GPIOx == GPIOF) +00007c 4810 LDR r0,|L2.192| +00007e 4284 CMP r4,r0 +000080 d108 BNE |L2.148| +;;;143 { +;;;144 RCC_APB2PeriphResetCmd(RCC_APB2Periph_GPIOF, ENABLE); +000082 2101 MOVS r1,#1 +000084 2080 MOVS r0,#0x80 +000086 f7fffffe BL RCC_APB2PeriphResetCmd +;;;145 RCC_APB2PeriphResetCmd(RCC_APB2Periph_GPIOF, DISABLE); +00008a 2100 MOVS r1,#0 +00008c 2080 MOVS r0,#0x80 +00008e f7fffffe BL RCC_APB2PeriphResetCmd +000092 e00a B |L2.170| + |L2.148| +;;;146 } +;;;147 else +;;;148 { +;;;149 if (GPIOx == GPIOG) +000094 480b LDR r0,|L2.196| +000096 4284 CMP r4,r0 +000098 d107 BNE |L2.170| +;;;150 { +;;;151 RCC_APB2PeriphResetCmd(RCC_APB2Periph_GPIOG, ENABLE); +00009a 2101 MOVS r1,#1 +00009c 1580 ASRS r0,r0,#22 +00009e f7fffffe BL RCC_APB2PeriphResetCmd +;;;152 RCC_APB2PeriphResetCmd(RCC_APB2Periph_GPIOG, DISABLE); +0000a2 2100 MOVS r1,#0 +0000a4 15a0 ASRS r0,r4,#22 +0000a6 f7fffffe BL RCC_APB2PeriphResetCmd + |L2.170| +;;;153 } +;;;154 } +;;;155 } +0000aa bd10 POP {r4,pc} +;;;156 + ENDP + + |L2.172| + DCD 0x40010800 + |L2.176| + DCD 0x40010c00 + |L2.180| + DCD 0x40011000 + |L2.184| + DCD 0x40011400 + |L2.188| + DCD 0x40011800 + |L2.192| + DCD 0x40011c00 + |L2.196| + DCD 0x40012000 + + AREA ||i.GPIO_ETH_MediaInterfaceConfig||, CODE, READONLY, ALIGN=2 + + GPIO_ETH_MediaInterfaceConfig PROC +;;;633 */ +;;;634 void GPIO_ETH_MediaInterfaceConfig(uint32_t GPIO_ETH_MediaInterface) +000000 4901 LDR r1,|L3.8| +;;;635 { +;;;636 assert_param(IS_GPIO_ETH_MEDIA_INTERFACE(GPIO_ETH_MediaInterface)); +;;;637 +;;;638 /* Configure MII_RMII selection bit */ +;;;639 *(__IO uint32_t *)MAPR_MII_RMII_SEL_BB = GPIO_ETH_MediaInterface; +000002 6008 STR r0,[r1,#0] +;;;640 } +000004 4770 BX lr +;;;641 + ENDP + +000006 0000 DCW 0x0000 + |L3.8| + DCD 0x422000dc + + AREA ||i.GPIO_EXTILineConfig||, CODE, READONLY, ALIGN=2 + + GPIO_EXTILineConfig PROC +;;;612 */ +;;;613 void GPIO_EXTILineConfig(uint8_t GPIO_PortSource, uint8_t GPIO_PinSource) +000000 b530 PUSH {r4,r5,lr} +;;;614 { +;;;615 uint32_t tmp = 0x00; +000002 2200 MOVS r2,#0 +;;;616 /* Check the parameters */ +;;;617 assert_param(IS_GPIO_EXTI_PORT_SOURCE(GPIO_PortSource)); +;;;618 assert_param(IS_GPIO_PIN_SOURCE(GPIO_PinSource)); +;;;619 +;;;620 tmp = ((uint32_t)0x0F) << (0x04 * (GPIO_PinSource & (uint8_t)0x03)); +000004 078b LSLS r3,r1,#30 +000006 0f1c LSRS r4,r3,#28 +000008 230f MOVS r3,#0xf +00000a fa03f204 LSL r2,r3,r4 +;;;621 AFIO->EXTICR[GPIO_PinSource >> 0x02] &= ~tmp; +00000e 4b0b LDR r3,|L4.60| +000010 108c ASRS r4,r1,#2 +000012 f8533024 LDR r3,[r3,r4,LSL #2] +000016 4393 BICS r3,r3,r2 +000018 4c08 LDR r4,|L4.60| +00001a 108d ASRS r5,r1,#2 +00001c f8443025 STR r3,[r4,r5,LSL #2] +;;;622 AFIO->EXTICR[GPIO_PinSource >> 0x02] |= (((uint32_t)GPIO_PortSource) << (0x04 * (GPIO_PinSource & (uint8_t)0x03))); +000020 4623 MOV r3,r4 +000022 108c ASRS r4,r1,#2 +000024 f8533024 LDR r3,[r3,r4,LSL #2] +000028 078c LSLS r4,r1,#30 +00002a 0f24 LSRS r4,r4,#28 +00002c fa00f404 LSL r4,r0,r4 +000030 4323 ORRS r3,r3,r4 +000032 4c02 LDR r4,|L4.60| +000034 108d ASRS r5,r1,#2 +000036 f8443025 STR r3,[r4,r5,LSL #2] +;;;623 } +00003a bd30 POP {r4,r5,pc} +;;;624 + ENDP + + |L4.60| + DCD 0x40010008 + + AREA ||i.GPIO_EventOutputCmd||, CODE, READONLY, ALIGN=2 + + GPIO_EventOutputCmd PROC +;;;486 */ +;;;487 void GPIO_EventOutputCmd(FunctionalState NewState) +000000 4901 LDR r1,|L5.8| +;;;488 { +;;;489 /* Check the parameters */ +;;;490 assert_param(IS_FUNCTIONAL_STATE(NewState)); +;;;491 +;;;492 *(__IO uint32_t *)EVCR_EVOE_BB = (uint32_t)NewState; +000002 61c8 STR r0,[r1,#0x1c] +;;;493 } +000004 4770 BX lr +;;;494 + ENDP + +000006 0000 DCW 0x0000 + |L5.8| + DCD 0x42200000 + + AREA ||i.GPIO_EventOutputConfig||, CODE, READONLY, ALIGN=2 + + GPIO_EventOutputConfig PROC +;;;465 */ +;;;466 void GPIO_EventOutputConfig(uint8_t GPIO_PortSource, uint8_t GPIO_PinSource) +000000 4602 MOV r2,r0 +;;;467 { +;;;468 uint32_t tmpreg = 0x00; +000002 2000 MOVS r0,#0 +;;;469 /* Check the parameters */ +;;;470 assert_param(IS_GPIO_EVENTOUT_PORT_SOURCE(GPIO_PortSource)); +;;;471 assert_param(IS_GPIO_PIN_SOURCE(GPIO_PinSource)); +;;;472 +;;;473 tmpreg = AFIO->EVCR; +000004 4b05 LDR r3,|L6.28| +000006 6818 LDR r0,[r3,#0] +;;;474 /* Clear the PORT[6:4] and PIN[3:0] bits */ +;;;475 tmpreg &= EVCR_PORTPINCONFIG_MASK; +000008 f64f7380 MOV r3,#0xff80 +00000c 4018 ANDS r0,r0,r3 +;;;476 tmpreg |= (uint32_t)GPIO_PortSource << 0x04; +00000e ea401002 ORR r0,r0,r2,LSL #4 +;;;477 tmpreg |= GPIO_PinSource; +000012 4308 ORRS r0,r0,r1 +;;;478 AFIO->EVCR = tmpreg; +000014 4b01 LDR r3,|L6.28| +000016 6018 STR r0,[r3,#0] +;;;479 } +000018 4770 BX lr +;;;480 + ENDP + +00001a 0000 DCW 0x0000 + |L6.28| + DCD 0x40010000 + + AREA ||i.GPIO_Init||, CODE, READONLY, ALIGN=1 + + GPIO_Init PROC +;;;176 */ +;;;177 void GPIO_Init(GPIO_TypeDef *GPIOx, GPIO_InitTypeDef *GPIO_InitStruct) +000000 e92d41f0 PUSH {r4-r8,lr} +;;;178 { +000004 4602 MOV r2,r0 +;;;179 uint32_t currentmode = 0x00, currentpin = 0x00, pinpos = 0x00, pos = 0x00; +000006 2500 MOVS r5,#0 +000008 2600 MOVS r6,#0 +00000a 2000 MOVS r0,#0 +00000c 2300 MOVS r3,#0 +;;;180 uint32_t tmpreg = 0x00, pinmask = 0x00; +00000e 2400 MOVS r4,#0 +000010 2700 MOVS r7,#0 +;;;181 /* Check the parameters */ +;;;182 assert_param(IS_GPIO_ALL_PERIPH(GPIOx)); +;;;183 assert_param(IS_GPIO_MODE(GPIO_InitStruct->GPIO_Mode)); +;;;184 assert_param(IS_GPIO_PIN(GPIO_InitStruct->GPIO_Pin)); +;;;185 +;;;186 /*---------------------------- GPIO Mode Configuration -----------------------*/ +;;;187 currentmode = ((uint32_t)GPIO_InitStruct->GPIO_Mode) & ((uint32_t)0x0F); +000012 f891c003 LDRB r12,[r1,#3] +000016 f00c050f AND r5,r12,#0xf +;;;188 if ((((uint32_t)GPIO_InitStruct->GPIO_Mode) & ((uint32_t)0x10)) != 0x00) +00001a f891c003 LDRB r12,[r1,#3] +00001e f00c0c10 AND r12,r12,#0x10 +000022 f1bc0f00 CMP r12,#0 +000026 d003 BEQ |L7.48| +;;;189 { +;;;190 /* Check the parameters */ +;;;191 assert_param(IS_GPIO_SPEED(GPIO_InitStruct->GPIO_Speed)); +;;;192 /* Output mode */ +;;;193 currentmode |= (uint32_t)GPIO_InitStruct->GPIO_Speed; +000028 f891c002 LDRB r12,[r1,#2] +00002c ea4c0505 ORR r5,r12,r5 + |L7.48| +;;;194 } +;;;195 /*---------------------------- GPIO CRL Configuration ------------------------*/ +;;;196 /* Configure the eight low port pins */ +;;;197 if (((uint32_t)GPIO_InitStruct->GPIO_Pin & ((uint32_t)0x00FF)) != 0x00) +000030 f891c000 LDRB r12,[r1,#0] +000034 f1bc0f00 CMP r12,#0 +000038 d031 BEQ |L7.158| +;;;198 { +;;;199 tmpreg = GPIOx->CRL; +00003a 6814 LDR r4,[r2,#0] +;;;200 for (pinpos = 0x00; pinpos < 0x08; pinpos++) +00003c 2000 MOVS r0,#0 +00003e e02b B |L7.152| + |L7.64| +;;;201 { +;;;202 pos = ((uint32_t)0x01) << pinpos; +000040 f04f0c01 MOV r12,#1 +000044 fa0cf300 LSL r3,r12,r0 +;;;203 /* Get the port pins position */ +;;;204 currentpin = (GPIO_InitStruct->GPIO_Pin) & pos; +000048 f8b1c000 LDRH r12,[r1,#0] +00004c ea0c0603 AND r6,r12,r3 +;;;205 if (currentpin == pos) +000050 429e CMP r6,r3 +000052 d120 BNE |L7.150| +;;;206 { +;;;207 pos = pinpos << 2; +000054 0083 LSLS r3,r0,#2 +;;;208 /* Clear the corresponding low control register bits */ +;;;209 pinmask = ((uint32_t)0x0F) << pos; +000056 f04f0c0f MOV r12,#0xf +00005a fa0cf703 LSL r7,r12,r3 +;;;210 tmpreg &= ~pinmask; +00005e 43bc BICS r4,r4,r7 +;;;211 /* Write the mode configuration in the corresponding bits */ +;;;212 tmpreg |= (currentmode << pos); +000060 fa05fc03 LSL r12,r5,r3 +000064 ea4c0404 ORR r4,r12,r4 +;;;213 /* Reset the corresponding ODR bit */ +;;;214 if (GPIO_InitStruct->GPIO_Mode == GPIO_Mode_IPD) +000068 f891c003 LDRB r12,[r1,#3] +00006c f1bc0f28 CMP r12,#0x28 +000070 d106 BNE |L7.128| +;;;215 { +;;;216 GPIOx->BRR = (((uint32_t)0x01) << pinpos); +000072 f04f0c01 MOV r12,#1 +000076 fa0cfc00 LSL r12,r12,r0 +00007a f8c2c014 STR r12,[r2,#0x14] +00007e e00a B |L7.150| + |L7.128| +;;;217 } +;;;218 else +;;;219 { +;;;220 /* Set the corresponding ODR bit */ +;;;221 if (GPIO_InitStruct->GPIO_Mode == GPIO_Mode_IPU) +000080 f891c003 LDRB r12,[r1,#3] +000084 f1bc0f48 CMP r12,#0x48 +000088 d105 BNE |L7.150| +;;;222 { +;;;223 GPIOx->BSRR = (((uint32_t)0x01) << pinpos); +00008a f04f0c01 MOV r12,#1 +00008e fa0cfc00 LSL r12,r12,r0 +000092 f8c2c010 STR r12,[r2,#0x10] + |L7.150| +000096 1c40 ADDS r0,r0,#1 ;200 + |L7.152| +000098 2808 CMP r0,#8 ;200 +00009a d3d1 BCC |L7.64| +;;;224 } +;;;225 } +;;;226 } +;;;227 } +;;;228 GPIOx->CRL = tmpreg; +00009c 6014 STR r4,[r2,#0] + |L7.158| +;;;229 } +;;;230 /*---------------------------- GPIO CRH Configuration ------------------------*/ +;;;231 /* Configure the eight high port pins */ +;;;232 if (GPIO_InitStruct->GPIO_Pin > 0x00FF) +00009e f8b1c000 LDRH r12,[r1,#0] +0000a2 f1bc0fff CMP r12,#0xff +0000a6 dd34 BLE |L7.274| +;;;233 { +;;;234 tmpreg = GPIOx->CRH; +0000a8 6854 LDR r4,[r2,#4] +;;;235 for (pinpos = 0x00; pinpos < 0x08; pinpos++) +0000aa 2000 MOVS r0,#0 +0000ac e02e B |L7.268| + |L7.174| +;;;236 { +;;;237 pos = (((uint32_t)0x01) << (pinpos + 0x08)); +0000ae f1000c08 ADD r12,r0,#8 +0000b2 f04f0801 MOV r8,#1 +0000b6 fa08f30c LSL r3,r8,r12 +;;;238 /* Get the port pins position */ +;;;239 currentpin = ((GPIO_InitStruct->GPIO_Pin) & pos); +0000ba f8b1c000 LDRH r12,[r1,#0] +0000be ea0c0603 AND r6,r12,r3 +;;;240 if (currentpin == pos) +0000c2 429e CMP r6,r3 +0000c4 d121 BNE |L7.266| +;;;241 { +;;;242 pos = pinpos << 2; +0000c6 0083 LSLS r3,r0,#2 +;;;243 /* Clear the corresponding high control register bits */ +;;;244 pinmask = ((uint32_t)0x0F) << pos; +0000c8 f04f0c0f MOV r12,#0xf +0000cc fa0cf703 LSL r7,r12,r3 +;;;245 tmpreg &= ~pinmask; +0000d0 43bc BICS r4,r4,r7 +;;;246 /* Write the mode configuration in the corresponding bits */ +;;;247 tmpreg |= (currentmode << pos); +0000d2 fa05fc03 LSL r12,r5,r3 +0000d6 ea4c0404 ORR r4,r12,r4 +;;;248 /* Reset the corresponding ODR bit */ +;;;249 if (GPIO_InitStruct->GPIO_Mode == GPIO_Mode_IPD) +0000da f891c003 LDRB r12,[r1,#3] +0000de f1bc0f28 CMP r12,#0x28 +0000e2 d105 BNE |L7.240| +;;;250 { +;;;251 GPIOx->BRR = (((uint32_t)0x01) << (pinpos + 0x08)); +0000e4 f1000c08 ADD r12,r0,#8 +0000e8 fa08f80c LSL r8,r8,r12 +0000ec f8c28014 STR r8,[r2,#0x14] + |L7.240| +;;;252 } +;;;253 /* Set the corresponding ODR bit */ +;;;254 if (GPIO_InitStruct->GPIO_Mode == GPIO_Mode_IPU) +0000f0 f891c003 LDRB r12,[r1,#3] +0000f4 f1bc0f48 CMP r12,#0x48 +0000f8 d107 BNE |L7.266| +;;;255 { +;;;256 GPIOx->BSRR = (((uint32_t)0x01) << (pinpos + 0x08)); +0000fa f1000c08 ADD r12,r0,#8 +0000fe f04f0801 MOV r8,#1 +000102 fa08f80c LSL r8,r8,r12 +000106 f8c28010 STR r8,[r2,#0x10] + |L7.266| +00010a 1c40 ADDS r0,r0,#1 ;235 + |L7.268| +00010c 2808 CMP r0,#8 ;235 +00010e d3ce BCC |L7.174| +;;;257 } +;;;258 } +;;;259 } +;;;260 GPIOx->CRH = tmpreg; +000110 6054 STR r4,[r2,#4] + |L7.274| +;;;261 } +;;;262 } +000112 e8bd81f0 POP {r4-r8,pc} +;;;263 + ENDP + + + AREA ||i.GPIO_PinLockConfig||, CODE, READONLY, ALIGN=1 + + GPIO_PinLockConfig PROC +;;;435 */ +;;;436 void GPIO_PinLockConfig(GPIO_TypeDef *GPIOx, uint16_t GPIO_Pin) +000000 f44f3280 MOV r2,#0x10000 +;;;437 { +;;;438 uint32_t tmp = 0x00010000; +;;;439 +;;;440 /* Check the parameters */ +;;;441 assert_param(IS_GPIO_ALL_PERIPH(GPIOx)); +;;;442 assert_param(IS_GPIO_PIN(GPIO_Pin)); +;;;443 +;;;444 tmp |= GPIO_Pin; +000004 430a ORRS r2,r2,r1 +;;;445 /* Set LCKK bit */ +;;;446 GPIOx->LCKR = tmp; +000006 6182 STR r2,[r0,#0x18] +;;;447 /* Reset LCKK bit */ +;;;448 GPIOx->LCKR = GPIO_Pin; +000008 6181 STR r1,[r0,#0x18] +;;;449 /* Set LCKK bit */ +;;;450 GPIOx->LCKR = tmp; +00000a 6182 STR r2,[r0,#0x18] +;;;451 /* Read LCKK bit*/ +;;;452 tmp = GPIOx->LCKR; +00000c 6982 LDR r2,[r0,#0x18] +;;;453 /* Read LCKK bit*/ +;;;454 tmp = GPIOx->LCKR; +00000e 6982 LDR r2,[r0,#0x18] +;;;455 } +000010 4770 BX lr +;;;456 + ENDP + + + AREA ||i.GPIO_PinRemapConfig||, CODE, READONLY, ALIGN=2 + + GPIO_PinRemapConfig PROC +;;;552 */ +;;;553 void GPIO_PinRemapConfig(uint32_t GPIO_Remap, FunctionalState NewState) +000000 b5f0 PUSH {r4-r7,lr} +;;;554 { +000002 460a MOV r2,r1 +;;;555 uint32_t tmp = 0x00, tmp1 = 0x00, tmpreg = 0x00, tmpmask = 0x00; +000004 2300 MOVS r3,#0 +000006 2400 MOVS r4,#0 +000008 2100 MOVS r1,#0 +00000a 2500 MOVS r5,#0 +;;;556 +;;;557 /* Check the parameters */ +;;;558 assert_param(IS_GPIO_REMAP(GPIO_Remap)); +;;;559 assert_param(IS_FUNCTIONAL_STATE(NewState)); +;;;560 +;;;561 if ((GPIO_Remap & 0x80000000) == 0x80000000) +00000c f0004600 AND r6,r0,#0x80000000 +000010 f1b64f00 CMP r6,#0x80000000 +000014 d102 BNE |L9.28| +;;;562 { +;;;563 tmpreg = AFIO->MAPR2; +000016 4e1d LDR r6,|L9.140| +000018 69f1 LDR r1,[r6,#0x1c] +00001a e001 B |L9.32| + |L9.28| +;;;564 } +;;;565 else +;;;566 { +;;;567 tmpreg = AFIO->MAPR; +00001c 4e1b LDR r6,|L9.140| +00001e 6871 LDR r1,[r6,#4] + |L9.32| +;;;568 } +;;;569 +;;;570 tmpmask = (GPIO_Remap & DBGAFR_POSITION_MASK) >> 0x10; +000020 f3c04503 UBFX r5,r0,#16,#4 +;;;571 tmp = GPIO_Remap & LSB_MASK; +000024 b283 UXTH r3,r0 +;;;572 +;;;573 if ((GPIO_Remap & (DBGAFR_LOCATION_MASK | DBGAFR_NUMBITS_MASK)) == (DBGAFR_LOCATION_MASK | DBGAFR_NUMBITS_MASK)) +000026 f4001640 AND r6,r0,#0x300000 +00002a f5b61f40 CMP r6,#0x300000 +00002e d108 BNE |L9.66| +;;;574 { +;;;575 tmpreg &= DBGAFR_SWJCFG_MASK; +000030 f0216170 BIC r1,r1,#0xf000000 +;;;576 AFIO->MAPR &= DBGAFR_SWJCFG_MASK; +000034 4e15 LDR r6,|L9.140| +000036 6876 LDR r6,[r6,#4] +000038 f0266670 BIC r6,r6,#0xf000000 +00003c 4f13 LDR r7,|L9.140| +00003e 607e STR r6,[r7,#4] +000040 e012 B |L9.104| + |L9.66| +;;;577 } +;;;578 else if ((GPIO_Remap & DBGAFR_NUMBITS_MASK) == DBGAFR_NUMBITS_MASK) +000042 f4001680 AND r6,r0,#0x100000 +000046 f5b61f80 CMP r6,#0x100000 +00004a d106 BNE |L9.90| +;;;579 { +;;;580 tmp1 = ((uint32_t)0x03) << tmpmask; +00004c 2603 MOVS r6,#3 +00004e fa06f405 LSL r4,r6,r5 +;;;581 tmpreg &= ~tmp1; +000052 43a1 BICS r1,r1,r4 +;;;582 tmpreg |= ~DBGAFR_SWJCFG_MASK; +000054 f0416170 ORR r1,r1,#0xf000000 +000058 e006 B |L9.104| + |L9.90| +;;;583 } +;;;584 else +;;;585 { +;;;586 tmpreg &= ~(tmp << ((GPIO_Remap >> 0x15) * 0x10)); +00005a 0d46 LSRS r6,r0,#21 +00005c 0136 LSLS r6,r6,#4 +00005e fa03f606 LSL r6,r3,r6 +000062 43b1 BICS r1,r1,r6 +;;;587 tmpreg |= ~DBGAFR_SWJCFG_MASK; +000064 f0416170 ORR r1,r1,#0xf000000 + |L9.104| +;;;588 } +;;;589 +;;;590 if (NewState != DISABLE) +000068 b122 CBZ r2,|L9.116| +;;;591 { +;;;592 tmpreg |= (tmp << ((GPIO_Remap >> 0x15) * 0x10)); +00006a 0d46 LSRS r6,r0,#21 +00006c 0136 LSLS r6,r6,#4 +00006e fa03f606 LSL r6,r3,r6 +000072 4331 ORRS r1,r1,r6 + |L9.116| +;;;593 } +;;;594 +;;;595 if ((GPIO_Remap & 0x80000000) == 0x80000000) +000074 f0004600 AND r6,r0,#0x80000000 +000078 f1b64f00 CMP r6,#0x80000000 +00007c d102 BNE |L9.132| +;;;596 { +;;;597 AFIO->MAPR2 = tmpreg; +00007e 4e03 LDR r6,|L9.140| +000080 61f1 STR r1,[r6,#0x1c] +000082 e001 B |L9.136| + |L9.132| +;;;598 } +;;;599 else +;;;600 { +;;;601 AFIO->MAPR = tmpreg; +000084 4e01 LDR r6,|L9.140| +000086 6071 STR r1,[r6,#4] + |L9.136| +;;;602 } +;;;603 } +000088 bdf0 POP {r4-r7,pc} +;;;604 + ENDP + +00008a 0000 DCW 0x0000 + |L9.140| + DCD 0x40010000 + + AREA ||i.GPIO_ReadInputData||, CODE, READONLY, ALIGN=1 + + GPIO_ReadInputData PROC +;;;308 */ +;;;309 uint16_t GPIO_ReadInputData(GPIO_TypeDef *GPIOx) +000000 4601 MOV r1,r0 +;;;310 { +;;;311 /* Check the parameters */ +;;;312 assert_param(IS_GPIO_ALL_PERIPH(GPIOx)); +;;;313 +;;;314 return ((uint16_t)GPIOx->IDR); +000002 6888 LDR r0,[r1,#8] +000004 b280 UXTH r0,r0 +;;;315 } +000006 4770 BX lr +;;;316 + ENDP + + + AREA ||i.GPIO_ReadInputDataBit||, CODE, READONLY, ALIGN=1 + + GPIO_ReadInputDataBit PROC +;;;284 */ +;;;285 uint8_t GPIO_ReadInputDataBit(GPIO_TypeDef *GPIOx, uint16_t GPIO_Pin) +000000 4602 MOV r2,r0 +;;;286 { +;;;287 uint8_t bitstatus = 0x00; +000002 2000 MOVS r0,#0 +;;;288 +;;;289 /* Check the parameters */ +;;;290 assert_param(IS_GPIO_ALL_PERIPH(GPIOx)); +;;;291 assert_param(IS_GET_GPIO_PIN(GPIO_Pin)); +;;;292 +;;;293 if ((GPIOx->IDR & GPIO_Pin) != (uint32_t)Bit_RESET) +000004 6893 LDR r3,[r2,#8] +000006 400b ANDS r3,r3,r1 +000008 b10b CBZ r3,|L11.14| +;;;294 { +;;;295 bitstatus = (uint8_t)Bit_SET; +00000a 2001 MOVS r0,#1 +00000c e000 B |L11.16| + |L11.14| +;;;296 } +;;;297 else +;;;298 { +;;;299 bitstatus = (uint8_t)Bit_RESET; +00000e 2000 MOVS r0,#0 + |L11.16| +;;;300 } +;;;301 return bitstatus; +;;;302 } +000010 4770 BX lr +;;;303 + ENDP + + + AREA ||i.GPIO_ReadOutputData||, CODE, READONLY, ALIGN=1 + + GPIO_ReadOutputData PROC +;;;346 */ +;;;347 uint16_t GPIO_ReadOutputData(GPIO_TypeDef *GPIOx) +000000 4601 MOV r1,r0 +;;;348 { +;;;349 /* Check the parameters */ +;;;350 assert_param(IS_GPIO_ALL_PERIPH(GPIOx)); +;;;351 +;;;352 return ((uint16_t)GPIOx->ODR); +000002 68c8 LDR r0,[r1,#0xc] +000004 b280 UXTH r0,r0 +;;;353 } +000006 4770 BX lr +;;;354 + ENDP + + + AREA ||i.GPIO_ReadOutputDataBit||, CODE, READONLY, ALIGN=1 + + GPIO_ReadOutputDataBit PROC +;;;323 */ +;;;324 uint8_t GPIO_ReadOutputDataBit(GPIO_TypeDef *GPIOx, uint16_t GPIO_Pin) +000000 4602 MOV r2,r0 +;;;325 { +;;;326 uint8_t bitstatus = 0x00; +000002 2000 MOVS r0,#0 +;;;327 /* Check the parameters */ +;;;328 assert_param(IS_GPIO_ALL_PERIPH(GPIOx)); +;;;329 assert_param(IS_GET_GPIO_PIN(GPIO_Pin)); +;;;330 +;;;331 if ((GPIOx->ODR & GPIO_Pin) != (uint32_t)Bit_RESET) +000004 68d3 LDR r3,[r2,#0xc] +000006 400b ANDS r3,r3,r1 +000008 b10b CBZ r3,|L13.14| +;;;332 { +;;;333 bitstatus = (uint8_t)Bit_SET; +00000a 2001 MOVS r0,#1 +00000c e000 B |L13.16| + |L13.14| +;;;334 } +;;;335 else +;;;336 { +;;;337 bitstatus = (uint8_t)Bit_RESET; +00000e 2000 MOVS r0,#0 + |L13.16| +;;;338 } +;;;339 return bitstatus; +;;;340 } +000010 4770 BX lr +;;;341 + ENDP + + + AREA ||i.GPIO_ResetBits||, CODE, READONLY, ALIGN=1 + + GPIO_ResetBits PROC +;;;377 */ +;;;378 void GPIO_ResetBits(GPIO_TypeDef *GPIOx, uint16_t GPIO_Pin) +000000 6141 STR r1,[r0,#0x14] +;;;379 { +;;;380 /* Check the parameters */ +;;;381 assert_param(IS_GPIO_ALL_PERIPH(GPIOx)); +;;;382 assert_param(IS_GPIO_PIN(GPIO_Pin)); +;;;383 +;;;384 GPIOx->BRR = GPIO_Pin; +;;;385 } +000002 4770 BX lr +;;;386 + ENDP + + + AREA ||i.GPIO_SetBits||, CODE, READONLY, ALIGN=1 + + GPIO_SetBits PROC +;;;361 */ +;;;362 void GPIO_SetBits(GPIO_TypeDef *GPIOx, uint16_t GPIO_Pin) +000000 6101 STR r1,[r0,#0x10] +;;;363 { +;;;364 /* Check the parameters */ +;;;365 assert_param(IS_GPIO_ALL_PERIPH(GPIOx)); +;;;366 assert_param(IS_GPIO_PIN(GPIO_Pin)); +;;;367 +;;;368 GPIOx->BSRR = GPIO_Pin; +;;;369 } +000002 4770 BX lr +;;;370 + ENDP + + + AREA ||i.GPIO_StructInit||, CODE, READONLY, ALIGN=1 + + GPIO_StructInit PROC +;;;269 */ +;;;270 void GPIO_StructInit(GPIO_InitTypeDef *GPIO_InitStruct) +000000 f64f71ff MOV r1,#0xffff +;;;271 { +;;;272 /* Reset GPIO init structure parameters values */ +;;;273 GPIO_InitStruct->GPIO_Pin = GPIO_Pin_All; +000004 8001 STRH r1,[r0,#0] +;;;274 GPIO_InitStruct->GPIO_Speed = GPIO_Speed_2MHz; +000006 2102 MOVS r1,#2 +000008 7081 STRB r1,[r0,#2] +;;;275 GPIO_InitStruct->GPIO_Mode = GPIO_Mode_IN_FLOATING; +00000a 2104 MOVS r1,#4 +00000c 70c1 STRB r1,[r0,#3] +;;;276 } +00000e 4770 BX lr +;;;277 + ENDP + + + AREA ||i.GPIO_Write||, CODE, READONLY, ALIGN=1 + + GPIO_Write PROC +;;;420 */ +;;;421 void GPIO_Write(GPIO_TypeDef *GPIOx, uint16_t PortVal) +000000 60c1 STR r1,[r0,#0xc] +;;;422 { +;;;423 /* Check the parameters */ +;;;424 assert_param(IS_GPIO_ALL_PERIPH(GPIOx)); +;;;425 +;;;426 GPIOx->ODR = PortVal; +;;;427 } +000002 4770 BX lr +;;;428 + ENDP + + + AREA ||i.GPIO_WriteBit||, CODE, READONLY, ALIGN=1 + + GPIO_WriteBit PROC +;;;397 */ +;;;398 void GPIO_WriteBit(GPIO_TypeDef *GPIOx, uint16_t GPIO_Pin, BitAction BitVal) +000000 b10a CBZ r2,|L18.6| +;;;399 { +;;;400 /* Check the parameters */ +;;;401 assert_param(IS_GPIO_ALL_PERIPH(GPIOx)); +;;;402 assert_param(IS_GET_GPIO_PIN(GPIO_Pin)); +;;;403 assert_param(IS_GPIO_BIT_ACTION(BitVal)); +;;;404 +;;;405 if (BitVal != Bit_RESET) +;;;406 { +;;;407 GPIOx->BSRR = GPIO_Pin; +000002 6101 STR r1,[r0,#0x10] +000004 e000 B |L18.8| + |L18.6| +;;;408 } +;;;409 else +;;;410 { +;;;411 GPIOx->BRR = GPIO_Pin; +000006 6141 STR r1,[r0,#0x14] + |L18.8| +;;;412 } +;;;413 } +000008 4770 BX lr +;;;414 + ENDP + + +;*** Start embedded assembler *** + +#line 1 "..\\..\\Libraries\\STM32F10x_StdPeriph_Driver\\src\\stm32f10x_gpio.c" + AREA ||.rev16_text||, CODE + THUMB + EXPORT |__asm___16_stm32f10x_gpio_c_f8e8e39a____REV16| +#line 114 "..\\..\\Libraries\\CMSIS\\Include\\core_cmInstr.h" +|__asm___16_stm32f10x_gpio_c_f8e8e39a____REV16| PROC +#line 115 + + rev16 r0, r0 + bx lr + ENDP + AREA ||.revsh_text||, CODE + THUMB + EXPORT |__asm___16_stm32f10x_gpio_c_f8e8e39a____REVSH| +#line 128 +|__asm___16_stm32f10x_gpio_c_f8e8e39a____REVSH| PROC +#line 129 + + revsh r0, r0 + bx lr + ENDP + +;*** End embedded assembler *** diff --git a/Project/MDK-ARM/Flash/List/stm32f10x_it.txt b/Project/MDK-ARM/Flash/List/stm32f10x_it.txt new file mode 100644 index 0000000..8fb6edd --- /dev/null +++ b/Project/MDK-ARM/Flash/List/stm32f10x_it.txt @@ -0,0 +1,197 @@ +; generated by Component: ARM Compiler 5.06 update 7 (build 960) Tool: ArmCC [4d365d] +; commandline ArmCC [--list --split_sections --debug -c --asm --interleave -o.\flash\obj\stm32f10x_it.o --asm_dir=.\Flash\List\ --list_dir=.\Flash\List\ --depend=.\flash\obj\stm32f10x_it.d --cpu=Cortex-M3 --apcs=interwork -O0 --diag_suppress=9931,870 -I..\..\Libraries\CMSIS\Device\ST\STM32F10x\Include -I..\..\Libraries\STM32F10x_StdPeriph_Driver\inc -I..\..\Libraries\STM32_USB-FS-Device_Driver\inc -I..\..\Libraries\CMSIS\Include -I..\..\User\bsp -I..\..\User\bsp\inc -I..\..\User\app\inc -I..\..\User -IC:\Users\w1619\AppData\Local\Arm\Packs\Keil\STM32F1xx_DFP\2.4.1\Device\Include -D__MICROLIB -D__UVISION_VERSION=538 -DSTM32F10X_HD -DUSE_STDPERIPH_DRIVER -DSTM32F10X_HD --omf_browse=.\flash\obj\stm32f10x_it.crf ..\..\User\bsp\stm32f10x_it.c] + THUMB + + AREA ||i.BusFault_Handler||, CODE, READONLY, ALIGN=1 + + BusFault_Handler PROC +;;;114 */ +;;;115 void BusFault_Handler(void) +000000 bf00 NOP + |L1.2| +;;;116 { +;;;117 /* 当总线异常时进入死循环 */ +;;;118 while (1) +000002 e7fe B |L1.2| +;;;119 { +;;;120 } +;;;121 } +;;;122 + ENDP + + + AREA ||i.DebugMon_Handler||, CODE, READONLY, ALIGN=1 + + DebugMon_Handler PROC +;;;158 */ +;;;159 void DebugMon_Handler(void) +000000 4770 BX lr +;;;160 { +;;;161 } +;;;162 + ENDP + + + AREA ||i.HardFault_Handler||, CODE, READONLY, ALIGN=1 + + HardFault_Handler PROC +;;;58 */ +;;;59 void HardFault_Handler(void) +000000 bf00 NOP + |L3.2| +;;;60 { +;;;61 #if 0 +;;;62 const char *pError = ERR_INFO; +;;;63 uint8_t i; +;;;64 +;;;65 for (i = 0; i < sizeof(ERR_INFO); i++) +;;;66 { +;;;67 USART1->DR = pError[i]; +;;;68 /* 等待发送结束 */ +;;;69 while ((USART1->SR & USART_FLAG_TC) == (uint16_t)RESET); +;;;70 } +;;;71 #endif +;;;72 +;;;73 #if 0 /* 出现异常时，驱动蜂鸣器发声 */ +;;;74 while(1) +;;;75 { +;;;76 uint16_t m; +;;;77 +;;;78 GPIOA->ODR ^= GPIO_Pin_8; +;;;79 +;;;80 for (m = 0; m < 10000; m++); +;;;81 } +;;;82 #else +;;;83 +;;;84 /* 当硬件失效异常发生时进入死循环 */ +;;;85 while (1) +000002 e7fe B |L3.2| +;;;86 { +;;;87 } +;;;88 #endif +;;;89 } +;;;90 + ENDP + + + AREA ||i.MemManage_Handler||, CODE, READONLY, ALIGN=1 + + MemManage_Handler PROC +;;;98 */ +;;;99 void MemManage_Handler(void) +000000 bf00 NOP + |L4.2| +;;;100 { +;;;101 /* 当内存管理异常发生时进入死循环 */ +;;;102 while (1) +000002 e7fe B |L4.2| +;;;103 { +;;;104 } +;;;105 } +;;;106 + ENDP + + + AREA ||i.NMI_Handler||, CODE, READONLY, ALIGN=1 + + NMI_Handler PROC +;;;46 */ +;;;47 void NMI_Handler(void) +000000 4770 BX lr +;;;48 { +;;;49 } +;;;50 + ENDP + + + AREA ||i.PendSV_Handler||, CODE, READONLY, ALIGN=1 + + PendSV_Handler PROC +;;;170 */ +;;;171 void PendSV_Handler(void) +000000 4770 BX lr +;;;172 { +;;;173 } +;;;174 + ENDP + + + AREA ||i.SVC_Handler||, CODE, READONLY, ALIGN=1 + + SVC_Handler PROC +;;;146 */ +;;;147 void SVC_Handler(void) +000000 4770 BX lr +;;;148 { +;;;149 } +;;;150 + ENDP + + + AREA ||i.USB_LP_CAN1_RX0_IRQHandler||, CODE, READONLY, ALIGN=2 + + USB_LP_CAN1_RX0_IRQHandler PROC +;;;205 extern void USB_Istr(void); +;;;206 void USB_LP_CAN1_RX0_IRQHandler(void) +000000 4801 LDR r0,|L8.8| +;;;207 { +;;;208 /* 判断CAN1的时钟是否打开 */ +;;;209 if (RCC->APB1ENR & RCC_APB1Periph_CAN1) +000002 69c0 LDR r0,[r0,#0x1c] +;;;210 { +;;;211 } +;;;212 else +;;;213 { +;;;214 } +;;;215 } +000004 4770 BX lr +;;;216 + ENDP + +000006 0000 DCW 0x0000 + |L8.8| + DCD 0x40021000 + + AREA ||i.UsageFault_Handler||, CODE, READONLY, ALIGN=1 + + UsageFault_Handler PROC +;;;130 */ +;;;131 void UsageFault_Handler(void) +000000 bf00 NOP + |L9.2| +;;;132 { +;;;133 /* 当用法异常时进入死循环 */ +;;;134 while (1) +000002 e7fe B |L9.2| +;;;135 { +;;;136 } +;;;137 } +;;;138 + ENDP + + +;*** Start embedded assembler *** + +#line 1 "..\\..\\User\\bsp\\stm32f10x_it.c" + AREA ||.rev16_text||, CODE + THUMB + EXPORT |__asm___14_stm32f10x_it_c_bb8ca80c____REV16| +#line 114 "..\\..\\Libraries\\CMSIS\\Include\\core_cmInstr.h" +|__asm___14_stm32f10x_it_c_bb8ca80c____REV16| PROC +#line 115 + + rev16 r0, r0 + bx lr + ENDP + AREA ||.revsh_text||, CODE + THUMB + EXPORT |__asm___14_stm32f10x_it_c_bb8ca80c____REVSH| +#line 128 +|__asm___14_stm32f10x_it_c_bb8ca80c____REVSH| PROC +#line 129 + + revsh r0, r0 + bx lr + ENDP + +;*** End embedded assembler *** diff --git a/Project/MDK-ARM/Flash/List/stm32f10x_rcc.txt b/Project/MDK-ARM/Flash/List/stm32f10x_rcc.txt new file mode 100644 index 0000000..afcbb49 --- /dev/null +++ b/Project/MDK-ARM/Flash/List/stm32f10x_rcc.txt @@ -0,0 +1,1392 @@ +; generated by Component: ARM Compiler 5.06 update 7 (build 960) Tool: ArmCC [4d365d] +; commandline ArmCC [--list --split_sections --debug -c --asm --interleave -o.\flash\obj\stm32f10x_rcc.o --asm_dir=.\Flash\List\ --list_dir=.\Flash\List\ --depend=.\flash\obj\stm32f10x_rcc.d --cpu=Cortex-M3 --apcs=interwork -O0 --diag_suppress=9931,870 -I..\..\Libraries\CMSIS\Device\ST\STM32F10x\Include -I..\..\Libraries\STM32F10x_StdPeriph_Driver\inc -I..\..\Libraries\STM32_USB-FS-Device_Driver\inc -I..\..\Libraries\CMSIS\Include -I..\..\User\bsp -I..\..\User\bsp\inc -I..\..\User\app\inc -I..\..\User -IC:\Users\w1619\AppData\Local\Arm\Packs\Keil\STM32F1xx_DFP\2.4.1\Device\Include -D__MICROLIB -D__UVISION_VERSION=538 -DSTM32F10X_HD -DUSE_STDPERIPH_DRIVER -DSTM32F10X_HD --omf_browse=.\flash\obj\stm32f10x_rcc.crf ..\..\Libraries\STM32F10x_StdPeriph_Driver\src\stm32f10x_rcc.c] + THUMB + + AREA ||i.RCC_ADCCLKConfig||, CODE, READONLY, ALIGN=2 + + RCC_ADCCLKConfig PROC +;;;771 */ +;;;772 void RCC_ADCCLKConfig(uint32_t RCC_PCLK2) +000000 4601 MOV r1,r0 +;;;773 { +;;;774 uint32_t tmpreg = 0; +000002 2000 MOVS r0,#0 +;;;775 /* Check the parameters */ +;;;776 assert_param(IS_RCC_ADCCLK(RCC_PCLK2)); +;;;777 tmpreg = RCC->CFGR; +000004 4a03 LDR r2,|L1.20| +000006 6850 LDR r0,[r2,#4] +;;;778 /* Clear ADCPRE[1:0] bits */ +;;;779 tmpreg &= CFGR_ADCPRE_Reset_Mask; +000008 f4204040 BIC r0,r0,#0xc000 +;;;780 /* Set ADCPRE[1:0] bits according to RCC_PCLK2 value */ +;;;781 tmpreg |= RCC_PCLK2; +00000c 4308 ORRS r0,r0,r1 +;;;782 /* Store the new value */ +;;;783 RCC->CFGR = tmpreg; +00000e 6050 STR r0,[r2,#4] +;;;784 } +000010 4770 BX lr +;;;785 + ENDP + +000012 0000 DCW 0x0000 + |L1.20| + DCD 0x40021000 + + AREA ||i.RCC_AHBPeriphClockCmd||, CODE, READONLY, ALIGN=2 + + RCC_AHBPeriphClockCmd PROC +;;;1069 */ +;;;1070 void RCC_AHBPeriphClockCmd(uint32_t RCC_AHBPeriph, FunctionalState NewState) +000000 b129 CBZ r1,|L2.14| +;;;1071 { +;;;1072 /* Check the parameters */ +;;;1073 assert_param(IS_RCC_AHB_PERIPH(RCC_AHBPeriph)); +;;;1074 assert_param(IS_FUNCTIONAL_STATE(NewState)); +;;;1075 +;;;1076 if (NewState != DISABLE) +;;;1077 { +;;;1078 RCC->AHBENR |= RCC_AHBPeriph; +000002 4a06 LDR r2,|L2.28| +000004 6952 LDR r2,[r2,#0x14] +000006 4302 ORRS r2,r2,r0 +000008 4b04 LDR r3,|L2.28| +00000a 615a STR r2,[r3,#0x14] +00000c e004 B |L2.24| + |L2.14| +;;;1079 } +;;;1080 else +;;;1081 { +;;;1082 RCC->AHBENR &= ~RCC_AHBPeriph; +00000e 4a03 LDR r2,|L2.28| +000010 6952 LDR r2,[r2,#0x14] +000012 4382 BICS r2,r2,r0 +000014 4b01 LDR r3,|L2.28| +000016 615a STR r2,[r3,#0x14] + |L2.24| +;;;1083 } +;;;1084 } +000018 4770 BX lr +;;;1085 + ENDP + +00001a 0000 DCW 0x0000 + |L2.28| + DCD 0x40021000 + + AREA ||i.RCC_APB1PeriphClockCmd||, CODE, READONLY, ALIGN=2 + + RCC_APB1PeriphClockCmd PROC +;;;1131 */ +;;;1132 void RCC_APB1PeriphClockCmd(uint32_t RCC_APB1Periph, FunctionalState NewState) +000000 b129 CBZ r1,|L3.14| +;;;1133 { +;;;1134 /* Check the parameters */ +;;;1135 assert_param(IS_RCC_APB1_PERIPH(RCC_APB1Periph)); +;;;1136 assert_param(IS_FUNCTIONAL_STATE(NewState)); +;;;1137 if (NewState != DISABLE) +;;;1138 { +;;;1139 RCC->APB1ENR |= RCC_APB1Periph; +000002 4a06 LDR r2,|L3.28| +000004 69d2 LDR r2,[r2,#0x1c] +000006 4302 ORRS r2,r2,r0 +000008 4b04 LDR r3,|L3.28| +00000a 61da STR r2,[r3,#0x1c] +00000c e004 B |L3.24| + |L3.14| +;;;1140 } +;;;1141 else +;;;1142 { +;;;1143 RCC->APB1ENR &= ~RCC_APB1Periph; +00000e 4a03 LDR r2,|L3.28| +000010 69d2 LDR r2,[r2,#0x1c] +000012 4382 BICS r2,r2,r0 +000014 4b01 LDR r3,|L3.28| +000016 61da STR r2,[r3,#0x1c] + |L3.24| +;;;1144 } +;;;1145 } +000018 4770 BX lr +;;;1146 + ENDP + +00001a 0000 DCW 0x0000 + |L3.28| + DCD 0x40021000 + + AREA ||i.RCC_APB1PeriphResetCmd||, CODE, READONLY, ALIGN=2 + + RCC_APB1PeriphResetCmd PROC +;;;1221 */ +;;;1222 void RCC_APB1PeriphResetCmd(uint32_t RCC_APB1Periph, FunctionalState NewState) +000000 b129 CBZ r1,|L4.14| +;;;1223 { +;;;1224 /* Check the parameters */ +;;;1225 assert_param(IS_RCC_APB1_PERIPH(RCC_APB1Periph)); +;;;1226 assert_param(IS_FUNCTIONAL_STATE(NewState)); +;;;1227 if (NewState != DISABLE) +;;;1228 { +;;;1229 RCC->APB1RSTR |= RCC_APB1Periph; +000002 4a06 LDR r2,|L4.28| +000004 6912 LDR r2,[r2,#0x10] +000006 4302 ORRS r2,r2,r0 +000008 4b04 LDR r3,|L4.28| +00000a 611a STR r2,[r3,#0x10] +00000c e004 B |L4.24| + |L4.14| +;;;1230 } +;;;1231 else +;;;1232 { +;;;1233 RCC->APB1RSTR &= ~RCC_APB1Periph; +00000e 4a03 LDR r2,|L4.28| +000010 6912 LDR r2,[r2,#0x10] +000012 4382 BICS r2,r2,r0 +000014 4b01 LDR r3,|L4.28| +000016 611a STR r2,[r3,#0x10] + |L4.24| +;;;1234 } +;;;1235 } +000018 4770 BX lr +;;;1236 + ENDP + +00001a 0000 DCW 0x0000 + |L4.28| + DCD 0x40021000 + + AREA ||i.RCC_APB2PeriphClockCmd||, CODE, READONLY, ALIGN=2 + + RCC_APB2PeriphClockCmd PROC +;;;1100 */ +;;;1101 void RCC_APB2PeriphClockCmd(uint32_t RCC_APB2Periph, FunctionalState NewState) +000000 b129 CBZ r1,|L5.14| +;;;1102 { +;;;1103 /* Check the parameters */ +;;;1104 assert_param(IS_RCC_APB2_PERIPH(RCC_APB2Periph)); +;;;1105 assert_param(IS_FUNCTIONAL_STATE(NewState)); +;;;1106 if (NewState != DISABLE) +;;;1107 { +;;;1108 RCC->APB2ENR |= RCC_APB2Periph; +000002 4a06 LDR r2,|L5.28| +000004 6992 LDR r2,[r2,#0x18] +000006 4302 ORRS r2,r2,r0 +000008 4b04 LDR r3,|L5.28| +00000a 619a STR r2,[r3,#0x18] +00000c e004 B |L5.24| + |L5.14| +;;;1109 } +;;;1110 else +;;;1111 { +;;;1112 RCC->APB2ENR &= ~RCC_APB2Periph; +00000e 4a03 LDR r2,|L5.28| +000010 6992 LDR r2,[r2,#0x18] +000012 4382 BICS r2,r2,r0 +000014 4b01 LDR r3,|L5.28| +000016 619a STR r2,[r3,#0x18] + |L5.24| +;;;1113 } +;;;1114 } +000018 4770 BX lr +;;;1115 + ENDP + +00001a 0000 DCW 0x0000 + |L5.28| + DCD 0x40021000 + + AREA ||i.RCC_APB2PeriphResetCmd||, CODE, READONLY, ALIGN=2 + + RCC_APB2PeriphResetCmd PROC +;;;1190 */ +;;;1191 void RCC_APB2PeriphResetCmd(uint32_t RCC_APB2Periph, FunctionalState NewState) +000000 b129 CBZ r1,|L6.14| +;;;1192 { +;;;1193 /* Check the parameters */ +;;;1194 assert_param(IS_RCC_APB2_PERIPH(RCC_APB2Periph)); +;;;1195 assert_param(IS_FUNCTIONAL_STATE(NewState)); +;;;1196 if (NewState != DISABLE) +;;;1197 { +;;;1198 RCC->APB2RSTR |= RCC_APB2Periph; +000002 4a06 LDR r2,|L6.28| +000004 68d2 LDR r2,[r2,#0xc] +000006 4302 ORRS r2,r2,r0 +000008 4b04 LDR r3,|L6.28| +00000a 60da STR r2,[r3,#0xc] +00000c e004 B |L6.24| + |L6.14| +;;;1199 } +;;;1200 else +;;;1201 { +;;;1202 RCC->APB2RSTR &= ~RCC_APB2Periph; +00000e 4a03 LDR r2,|L6.28| +000010 68d2 LDR r2,[r2,#0xc] +000012 4382 BICS r2,r2,r0 +000014 4b01 LDR r3,|L6.28| +000016 60da STR r2,[r3,#0xc] + |L6.24| +;;;1203 } +;;;1204 } +000018 4770 BX lr +;;;1205 + ENDP + +00001a 0000 DCW 0x0000 + |L6.28| + DCD 0x40021000 + + AREA ||i.RCC_AdjustHSICalibrationValue||, CODE, READONLY, ALIGN=2 + + RCC_AdjustHSICalibrationValue PROC +;;;339 */ +;;;340 void RCC_AdjustHSICalibrationValue(uint8_t HSICalibrationValue) +000000 4601 MOV r1,r0 +;;;341 { +;;;342 uint32_t tmpreg = 0; +000002 2000 MOVS r0,#0 +;;;343 /* Check the parameters */ +;;;344 assert_param(IS_RCC_CALIBRATION_VALUE(HSICalibrationValue)); +;;;345 tmpreg = RCC->CR; +000004 4a03 LDR r2,|L7.20| +000006 6810 LDR r0,[r2,#0] +;;;346 /* Clear HSITRIM[4:0] bits */ +;;;347 tmpreg &= CR_HSITRIM_Mask; +000008 f02000f8 BIC r0,r0,#0xf8 +;;;348 /* Set the HSITRIM[4:0] bits according to HSICalibrationValue value */ +;;;349 tmpreg |= (uint32_t)HSICalibrationValue << 3; +00000c ea4000c1 ORR r0,r0,r1,LSL #3 +;;;350 /* Store the new value */ +;;;351 RCC->CR = tmpreg; +000010 6010 STR r0,[r2,#0] +;;;352 } +000012 4770 BX lr +;;;353 + ENDP + + |L7.20| + DCD 0x40021000 + + AREA ||i.RCC_BackupResetCmd||, CODE, READONLY, ALIGN=2 + + RCC_BackupResetCmd PROC +;;;1242 */ +;;;1243 void RCC_BackupResetCmd(FunctionalState NewState) +000000 4901 LDR r1,|L8.8| +;;;1244 { +;;;1245 /* Check the parameters */ +;;;1246 assert_param(IS_FUNCTIONAL_STATE(NewState)); +;;;1247 *(__IO uint32_t *) BDCR_BDRST_BB = (uint32_t)NewState; +000002 6008 STR r0,[r1,#0] +;;;1248 } +000004 4770 BX lr +;;;1249 + ENDP + +000006 0000 DCW 0x0000 + |L8.8| + DCD 0x42420440 + + AREA ||i.RCC_ClearFlag||, CODE, READONLY, ALIGN=2 + + RCC_ClearFlag PROC +;;;1376 */ +;;;1377 void RCC_ClearFlag(void) +000000 4803 LDR r0,|L9.16| +;;;1378 { +;;;1379 /* Set RMVF bit to clear the reset flags */ +;;;1380 RCC->CSR |= CSR_RMVF_Set; +000002 6a40 LDR r0,[r0,#0x24] +000004 f0407080 ORR r0,r0,#0x1000000 +000008 4901 LDR r1,|L9.16| +00000a 6248 STR r0,[r1,#0x24] +;;;1381 } +00000c 4770 BX lr +;;;1382 + ENDP + +00000e 0000 DCW 0x0000 + |L9.16| + DCD 0x40021000 + + AREA ||i.RCC_ClearITPendingBit||, CODE, READONLY, ALIGN=2 + + RCC_ClearITPendingBit PROC +;;;1453 */ +;;;1454 void RCC_ClearITPendingBit(uint8_t RCC_IT) +000000 4901 LDR r1,|L10.8| +;;;1455 { +;;;1456 /* Check the parameters */ +;;;1457 assert_param(IS_RCC_CLEAR_IT(RCC_IT)); +;;;1458 +;;;1459 /* Perform Byte access to RCC_CIR[23:16] bits to clear the selected interrupt +;;;1460 pending bits */ +;;;1461 *(__IO uint8_t *) CIR_BYTE3_ADDRESS = RCC_IT; +000002 7288 STRB r0,[r1,#0xa] +;;;1462 } +000004 4770 BX lr +;;;1463 + ENDP + +000006 0000 DCW 0x0000 + |L10.8| + DCD 0x40021000 + + AREA ||i.RCC_ClockSecuritySystemCmd||, CODE, READONLY, ALIGN=2 + + RCC_ClockSecuritySystemCmd PROC +;;;1255 */ +;;;1256 void RCC_ClockSecuritySystemCmd(FunctionalState NewState) +000000 4901 LDR r1,|L11.8| +;;;1257 { +;;;1258 /* Check the parameters */ +;;;1259 assert_param(IS_FUNCTIONAL_STATE(NewState)); +;;;1260 *(__IO uint32_t *) CR_CSSON_BB = (uint32_t)NewState; +000002 64c8 STR r0,[r1,#0x4c] +;;;1261 } +000004 4770 BX lr +;;;1262 + ENDP + +000006 0000 DCW 0x0000 + |L11.8| + DCD 0x42420000 + + AREA ||i.RCC_DeInit||, CODE, READONLY, ALIGN=2 + + RCC_DeInit PROC +;;;222 */ +;;;223 void RCC_DeInit(void) +000000 480f LDR r0,|L12.64| +;;;224 { +;;;225 /* Set HSION bit */ +;;;226 RCC->CR |= (uint32_t)0x00000001; +000002 6800 LDR r0,[r0,#0] +000004 f0400001 ORR r0,r0,#1 +000008 490d LDR r1,|L12.64| +00000a 6008 STR r0,[r1,#0] +;;;227 +;;;228 /* Reset SW, HPRE, PPRE1, PPRE2, ADCPRE and MCO bits */ +;;;229 #ifndef STM32F10X_CL +;;;230 RCC->CFGR &= (uint32_t)0xF8FF0000; +00000c 4608 MOV r0,r1 +00000e 6840 LDR r0,[r0,#4] +000010 490c LDR r1,|L12.68| +000012 4008 ANDS r0,r0,r1 +000014 490a LDR r1,|L12.64| +000016 6048 STR r0,[r1,#4] +;;;231 #else +;;;232 RCC->CFGR &= (uint32_t)0xF0FF0000; +;;;233 #endif /* STM32F10X_CL */ +;;;234 +;;;235 /* Reset HSEON, CSSON and PLLON bits */ +;;;236 RCC->CR &= (uint32_t)0xFEF6FFFF; +000018 4608 MOV r0,r1 +00001a 6800 LDR r0,[r0,#0] +00001c 490a LDR r1,|L12.72| +00001e 4008 ANDS r0,r0,r1 +000020 4907 LDR r1,|L12.64| +000022 6008 STR r0,[r1,#0] +;;;237 +;;;238 /* Reset HSEBYP bit */ +;;;239 RCC->CR &= (uint32_t)0xFFFBFFFF; +000024 4608 MOV r0,r1 +000026 6800 LDR r0,[r0,#0] +000028 f4202080 BIC r0,r0,#0x40000 +00002c 6008 STR r0,[r1,#0] +;;;240 +;;;241 /* Reset PLLSRC, PLLXTPRE, PLLMUL and USBPRE/OTGFSPRE bits */ +;;;242 RCC->CFGR &= (uint32_t)0xFF80FFFF; +00002e 4608 MOV r0,r1 +000030 6840 LDR r0,[r0,#4] +000032 f42000fe BIC r0,r0,#0x7f0000 +000036 6048 STR r0,[r1,#4] +;;;243 +;;;244 #ifdef STM32F10X_CL +;;;245 /* Reset PLL2ON and PLL3ON bits */ +;;;246 RCC->CR &= (uint32_t)0xEBFFFFFF; +;;;247 +;;;248 /* Disable all interrupts and clear pending bits */ +;;;249 RCC->CIR = 0x00FF0000; +;;;250 +;;;251 /* Reset CFGR2 register */ +;;;252 RCC->CFGR2 = 0x00000000; +;;;253 #elif defined (STM32F10X_LD_VL) || defined (STM32F10X_MD_VL) || defined (STM32F10X_HD_VL) +;;;254 /* Disable all interrupts and clear pending bits */ +;;;255 RCC->CIR = 0x009F0000; +;;;256 +;;;257 /* Reset CFGR2 register */ +;;;258 RCC->CFGR2 = 0x00000000; +;;;259 #else +;;;260 /* Disable all interrupts and clear pending bits */ +;;;261 RCC->CIR = 0x009F0000; +000038 f44f001f MOV r0,#0x9f0000 +00003c 6088 STR r0,[r1,#8] +;;;262 #endif /* STM32F10X_CL */ +;;;263 +;;;264 } +00003e 4770 BX lr +;;;265 + ENDP + + |L12.64| + DCD 0x40021000 + |L12.68| + DCD 0xf8ff0000 + |L12.72| + DCD 0xfef6ffff + + AREA ||i.RCC_GetClocksFreq||, CODE, READONLY, ALIGN=2 + + RCC_GetClocksFreq PROC +;;;913 */ +;;;914 void RCC_GetClocksFreq(RCC_ClocksTypeDef* RCC_Clocks) +000000 b530 PUSH {r4,r5,lr} +;;;915 { +;;;916 uint32_t tmp = 0, pllmull = 0, pllsource = 0, presc = 0; +000002 2100 MOVS r1,#0 +000004 2200 MOVS r2,#0 +000006 2400 MOVS r4,#0 +000008 2300 MOVS r3,#0 +;;;917 +;;;918 #ifdef STM32F10X_CL +;;;919 uint32_t prediv1source = 0, prediv1factor = 0, prediv2factor = 0, pll2mull = 0; +;;;920 #endif /* STM32F10X_CL */ +;;;921 +;;;922 #if defined (STM32F10X_LD_VL) || defined (STM32F10X_MD_VL) || defined (STM32F10X_HD_VL) +;;;923 uint32_t prediv1factor = 0; +;;;924 #endif +;;;925 +;;;926 /* Get SYSCLK source -------------------------------------------------------*/ +;;;927 tmp = RCC->CFGR & CFGR_SWS_Mask; +00000a 4d2d LDR r5,|L13.192| +00000c 686d LDR r5,[r5,#4] +00000e f005010c AND r1,r5,#0xc +;;;928 +;;;929 switch (tmp) +000012 b121 CBZ r1,|L13.30| +000014 2904 CMP r1,#4 +000016 d005 BEQ |L13.36| +000018 2908 CMP r1,#8 +00001a d123 BNE |L13.100| +00001c e005 B |L13.42| + |L13.30| +;;;930 { +;;;931 case 0x00: /* HSI used as system clock */ +;;;932 RCC_Clocks->SYSCLK_Frequency = HSI_VALUE; +00001e 4d29 LDR r5,|L13.196| +000020 6005 STR r5,[r0,#0] +;;;933 break; +000022 e022 B |L13.106| + |L13.36| +;;;934 case 0x04: /* HSE used as system clock */ +;;;935 RCC_Clocks->SYSCLK_Frequency = HSE_VALUE; +000024 4d27 LDR r5,|L13.196| +000026 6005 STR r5,[r0,#0] +;;;936 break; +000028 e01f B |L13.106| + |L13.42| +;;;937 case 0x08: /* PLL used as system clock */ +;;;938 +;;;939 /* Get PLL clock source and multiplication factor ----------------------*/ +;;;940 pllmull = RCC->CFGR & CFGR_PLLMull_Mask; +00002a 4d25 LDR r5,|L13.192| +00002c 686d LDR r5,[r5,#4] +00002e f4051270 AND r2,r5,#0x3c0000 +;;;941 pllsource = RCC->CFGR & CFGR_PLLSRC_Mask; +000032 4d23 LDR r5,|L13.192| +000034 686d LDR r5,[r5,#4] +000036 f4053480 AND r4,r5,#0x10000 +;;;942 +;;;943 #ifndef STM32F10X_CL +;;;944 pllmull = ( pllmull >> 18) + 2; +00003a 2502 MOVS r5,#2 +00003c eb054292 ADD r2,r5,r2,LSR #18 +;;;945 +;;;946 if (pllsource == 0x00) +000040 b91c CBNZ r4,|L13.74| +;;;947 {/* HSI oscillator clock divided by 2 selected as PLL clock entry */ +;;;948 RCC_Clocks->SYSCLK_Frequency = (HSI_VALUE >> 1) * pllmull; +000042 4d21 LDR r5,|L13.200| +000044 4355 MULS r5,r2,r5 +000046 6005 STR r5,[r0,#0] +000048 e00b B |L13.98| + |L13.74| +;;;949 } +;;;950 else +;;;951 { +;;;952 #if defined (STM32F10X_LD_VL) || defined (STM32F10X_MD_VL) || defined (STM32F10X_HD_VL) +;;;953 prediv1factor = (RCC->CFGR2 & CFGR2_PREDIV1) + 1; +;;;954 /* HSE oscillator clock selected as PREDIV1 clock entry */ +;;;955 RCC_Clocks->SYSCLK_Frequency = (HSE_VALUE / prediv1factor) * pllmull; +;;;956 #else +;;;957 /* HSE selected as PLL clock entry */ +;;;958 if ((RCC->CFGR & CFGR_PLLXTPRE_Mask) != (uint32_t)RESET) +00004a 4d1d LDR r5,|L13.192| +00004c 686d LDR r5,[r5,#4] +00004e f4053500 AND r5,r5,#0x20000 +000052 b11d CBZ r5,|L13.92| +;;;959 {/* HSE oscillator clock divided by 2 */ +;;;960 RCC_Clocks->SYSCLK_Frequency = (HSE_VALUE >> 1) * pllmull; +000054 4d1c LDR r5,|L13.200| +000056 4355 MULS r5,r2,r5 +000058 6005 STR r5,[r0,#0] +00005a e002 B |L13.98| + |L13.92| +;;;961 } +;;;962 else +;;;963 { +;;;964 RCC_Clocks->SYSCLK_Frequency = HSE_VALUE * pllmull; +00005c 4d19 LDR r5,|L13.196| +00005e 4355 MULS r5,r2,r5 +000060 6005 STR r5,[r0,#0] + |L13.98| +;;;965 } +;;;966 #endif +;;;967 } +;;;968 #else +;;;969 pllmull = pllmull >> 18; +;;;970 +;;;971 if (pllmull != 0x0D) +;;;972 { +;;;973 pllmull += 2; +;;;974 } +;;;975 else +;;;976 { /* PLL multiplication factor = PLL input clock * 6.5 */ +;;;977 pllmull = 13 / 2; +;;;978 } +;;;979 +;;;980 if (pllsource == 0x00) +;;;981 {/* HSI oscillator clock divided by 2 selected as PLL clock entry */ +;;;982 RCC_Clocks->SYSCLK_Frequency = (HSI_VALUE >> 1) * pllmull; +;;;983 } +;;;984 else +;;;985 {/* PREDIV1 selected as PLL clock entry */ +;;;986 +;;;987 /* Get PREDIV1 clock source and division factor */ +;;;988 prediv1source = RCC->CFGR2 & CFGR2_PREDIV1SRC; +;;;989 prediv1factor = (RCC->CFGR2 & CFGR2_PREDIV1) + 1; +;;;990 +;;;991 if (prediv1source == 0) +;;;992 { /* HSE oscillator clock selected as PREDIV1 clock entry */ +;;;993 RCC_Clocks->SYSCLK_Frequency = (HSE_VALUE / prediv1factor) * pllmull; +;;;994 } +;;;995 else +;;;996 {/* PLL2 clock selected as PREDIV1 clock entry */ +;;;997 +;;;998 /* Get PREDIV2 division factor and PLL2 multiplication factor */ +;;;999 prediv2factor = ((RCC->CFGR2 & CFGR2_PREDIV2) >> 4) + 1; +;;;1000 pll2mull = ((RCC->CFGR2 & CFGR2_PLL2MUL) >> 8 ) + 2; +;;;1001 RCC_Clocks->SYSCLK_Frequency = (((HSE_VALUE / prediv2factor) * pll2mull) / prediv1factor) * pllmull; +;;;1002 } +;;;1003 } +;;;1004 #endif /* STM32F10X_CL */ +;;;1005 break; +000062 e002 B |L13.106| + |L13.100| +;;;1006 +;;;1007 default: +;;;1008 RCC_Clocks->SYSCLK_Frequency = HSI_VALUE; +000064 4d17 LDR r5,|L13.196| +000066 6005 STR r5,[r0,#0] +;;;1009 break; +000068 bf00 NOP + |L13.106| +00006a bf00 NOP ;933 +;;;1010 } +;;;1011 +;;;1012 /* Compute HCLK, PCLK1, PCLK2 and ADCCLK clocks frequencies ----------------*/ +;;;1013 /* Get HCLK prescaler */ +;;;1014 tmp = RCC->CFGR & CFGR_HPRE_Set_Mask; +00006c 4d14 LDR r5,|L13.192| +00006e 686d LDR r5,[r5,#4] +000070 f00501f0 AND r1,r5,#0xf0 +;;;1015 tmp = tmp >> 4; +000074 0909 LSRS r1,r1,#4 +;;;1016 presc = APBAHBPrescTable[tmp]; +000076 4d15 LDR r5,|L13.204| +000078 5c6b LDRB r3,[r5,r1] +;;;1017 /* HCLK clock frequency */ +;;;1018 RCC_Clocks->HCLK_Frequency = RCC_Clocks->SYSCLK_Frequency >> presc; +00007a 6805 LDR r5,[r0,#0] +00007c 40dd LSRS r5,r5,r3 +00007e 6045 STR r5,[r0,#4] +;;;1019 /* Get PCLK1 prescaler */ +;;;1020 tmp = RCC->CFGR & CFGR_PPRE1_Set_Mask; +000080 4d0f LDR r5,|L13.192| +000082 686d LDR r5,[r5,#4] +000084 f40561e0 AND r1,r5,#0x700 +;;;1021 tmp = tmp >> 8; +000088 0a09 LSRS r1,r1,#8 +;;;1022 presc = APBAHBPrescTable[tmp]; +00008a 4d10 LDR r5,|L13.204| +00008c 5c6b LDRB r3,[r5,r1] +;;;1023 /* PCLK1 clock frequency */ +;;;1024 RCC_Clocks->PCLK1_Frequency = RCC_Clocks->HCLK_Frequency >> presc; +00008e 6845 LDR r5,[r0,#4] +000090 40dd LSRS r5,r5,r3 +000092 6085 STR r5,[r0,#8] +;;;1025 /* Get PCLK2 prescaler */ +;;;1026 tmp = RCC->CFGR & CFGR_PPRE2_Set_Mask; +000094 4d0a LDR r5,|L13.192| +000096 686d LDR r5,[r5,#4] +000098 f4055160 AND r1,r5,#0x3800 +;;;1027 tmp = tmp >> 11; +00009c 0ac9 LSRS r1,r1,#11 +;;;1028 presc = APBAHBPrescTable[tmp]; +00009e 4d0b LDR r5,|L13.204| +0000a0 5c6b LDRB r3,[r5,r1] +;;;1029 /* PCLK2 clock frequency */ +;;;1030 RCC_Clocks->PCLK2_Frequency = RCC_Clocks->HCLK_Frequency >> presc; +0000a2 6845 LDR r5,[r0,#4] +0000a4 40dd LSRS r5,r5,r3 +0000a6 60c5 STR r5,[r0,#0xc] +;;;1031 /* Get ADCCLK prescaler */ +;;;1032 tmp = RCC->CFGR & CFGR_ADCPRE_Set_Mask; +0000a8 4d05 LDR r5,|L13.192| +0000aa 686d LDR r5,[r5,#4] +0000ac f4054140 AND r1,r5,#0xc000 +;;;1033 tmp = tmp >> 14; +0000b0 0b89 LSRS r1,r1,#14 +;;;1034 presc = ADCPrescTable[tmp]; +0000b2 4d07 LDR r5,|L13.208| +0000b4 5c6b LDRB r3,[r5,r1] +;;;1035 /* ADCCLK clock frequency */ +;;;1036 RCC_Clocks->ADCCLK_Frequency = RCC_Clocks->PCLK2_Frequency / presc; +0000b6 68c5 LDR r5,[r0,#0xc] +0000b8 fbb5f5f3 UDIV r5,r5,r3 +0000bc 6105 STR r5,[r0,#0x10] +;;;1037 } +0000be bd30 POP {r4,r5,pc} +;;;1038 + ENDP + + |L13.192| + DCD 0x40021000 + |L13.196| + DCD 0x007a1200 + |L13.200| + DCD 0x003d0900 + |L13.204| + DCD APBAHBPrescTable + |L13.208| + DCD ADCPrescTable + + AREA ||i.RCC_GetFlagStatus||, CODE, READONLY, ALIGN=2 + + RCC_GetFlagStatus PROC +;;;1331 */ +;;;1332 FlagStatus RCC_GetFlagStatus(uint8_t RCC_FLAG) +000000 b510 PUSH {r4,lr} +;;;1333 { +000002 4601 MOV r1,r0 +;;;1334 uint32_t tmp = 0; +000004 2200 MOVS r2,#0 +;;;1335 uint32_t statusreg = 0; +000006 2300 MOVS r3,#0 +;;;1336 FlagStatus bitstatus = RESET; +000008 2000 MOVS r0,#0 +;;;1337 /* Check the parameters */ +;;;1338 assert_param(IS_RCC_FLAG(RCC_FLAG)); +;;;1339 +;;;1340 /* Get the RCC register index */ +;;;1341 tmp = RCC_FLAG >> 5; +00000a 114a ASRS r2,r1,#5 +;;;1342 if (tmp == 1) /* The flag to check is in CR register */ +00000c 2a01 CMP r2,#1 +00000e d102 BNE |L14.22| +;;;1343 { +;;;1344 statusreg = RCC->CR; +000010 4c09 LDR r4,|L14.56| +000012 6823 LDR r3,[r4,#0] +000014 e006 B |L14.36| + |L14.22| +;;;1345 } +;;;1346 else if (tmp == 2) /* The flag to check is in BDCR register */ +000016 2a02 CMP r2,#2 +000018 d102 BNE |L14.32| +;;;1347 { +;;;1348 statusreg = RCC->BDCR; +00001a 4c07 LDR r4,|L14.56| +00001c 6a23 LDR r3,[r4,#0x20] +00001e e001 B |L14.36| + |L14.32| +;;;1349 } +;;;1350 else /* The flag to check is in CSR register */ +;;;1351 { +;;;1352 statusreg = RCC->CSR; +000020 4c05 LDR r4,|L14.56| +000022 6a63 LDR r3,[r4,#0x24] + |L14.36| +;;;1353 } +;;;1354 +;;;1355 /* Get the flag position */ +;;;1356 tmp = RCC_FLAG & FLAG_Mask; +000024 f001021f AND r2,r1,#0x1f +;;;1357 if ((statusreg & ((uint32_t)1 << tmp)) != (uint32_t)RESET) +000028 2401 MOVS r4,#1 +00002a 4094 LSLS r4,r4,r2 +00002c 401c ANDS r4,r4,r3 +00002e b10c CBZ r4,|L14.52| +;;;1358 { +;;;1359 bitstatus = SET; +000030 2001 MOVS r0,#1 +000032 e000 B |L14.54| + |L14.52| +;;;1360 } +;;;1361 else +;;;1362 { +;;;1363 bitstatus = RESET; +000034 2000 MOVS r0,#0 + |L14.54| +;;;1364 } +;;;1365 +;;;1366 /* Return the flag status */ +;;;1367 return bitstatus; +;;;1368 } +000036 bd10 POP {r4,pc} +;;;1369 + ENDP + + |L14.56| + DCD 0x40021000 + + AREA ||i.RCC_GetITStatus||, CODE, READONLY, ALIGN=2 + + RCC_GetITStatus PROC +;;;1407 */ +;;;1408 ITStatus RCC_GetITStatus(uint8_t RCC_IT) +000000 4601 MOV r1,r0 +;;;1409 { +;;;1410 ITStatus bitstatus = RESET; +000002 2000 MOVS r0,#0 +;;;1411 /* Check the parameters */ +;;;1412 assert_param(IS_RCC_GET_IT(RCC_IT)); +;;;1413 +;;;1414 /* Check the status of the specified RCC interrupt */ +;;;1415 if ((RCC->CIR & RCC_IT) != (uint32_t)RESET) +000004 4a03 LDR r2,|L15.20| +000006 6892 LDR r2,[r2,#8] +000008 400a ANDS r2,r2,r1 +00000a b10a CBZ r2,|L15.16| +;;;1416 { +;;;1417 bitstatus = SET; +00000c 2001 MOVS r0,#1 +00000e e000 B |L15.18| + |L15.16| +;;;1418 } +;;;1419 else +;;;1420 { +;;;1421 bitstatus = RESET; +000010 2000 MOVS r0,#0 + |L15.18| +;;;1422 } +;;;1423 +;;;1424 /* Return the RCC_IT status */ +;;;1425 return bitstatus; +;;;1426 } +000012 4770 BX lr +;;;1427 + ENDP + + |L15.20| + DCD 0x40021000 + + AREA ||i.RCC_GetSYSCLKSource||, CODE, READONLY, ALIGN=2 + + RCC_GetSYSCLKSource PROC +;;;592 */ +;;;593 uint8_t RCC_GetSYSCLKSource(void) +000000 4802 LDR r0,|L16.12| +;;;594 { +;;;595 return ((uint8_t)(RCC->CFGR & CFGR_SWS_Mask)); +000002 6840 LDR r0,[r0,#4] +000004 f000000c AND r0,r0,#0xc +;;;596 } +000008 4770 BX lr +;;;597 + ENDP + +00000a 0000 DCW 0x0000 + |L16.12| + DCD 0x40021000 + + AREA ||i.RCC_HCLKConfig||, CODE, READONLY, ALIGN=2 + + RCC_HCLKConfig PROC +;;;613 */ +;;;614 void RCC_HCLKConfig(uint32_t RCC_SYSCLK) +000000 4601 MOV r1,r0 +;;;615 { +;;;616 uint32_t tmpreg = 0; +000002 2000 MOVS r0,#0 +;;;617 /* Check the parameters */ +;;;618 assert_param(IS_RCC_HCLK(RCC_SYSCLK)); +;;;619 tmpreg = RCC->CFGR; +000004 4a03 LDR r2,|L17.20| +000006 6850 LDR r0,[r2,#4] +;;;620 /* Clear HPRE[3:0] bits */ +;;;621 tmpreg &= CFGR_HPRE_Reset_Mask; +000008 f02000f0 BIC r0,r0,#0xf0 +;;;622 /* Set HPRE[3:0] bits according to RCC_SYSCLK value */ +;;;623 tmpreg |= RCC_SYSCLK; +00000c 4308 ORRS r0,r0,r1 +;;;624 /* Store the new value */ +;;;625 RCC->CFGR = tmpreg; +00000e 6050 STR r0,[r2,#4] +;;;626 } +000010 4770 BX lr +;;;627 + ENDP + +000012 0000 DCW 0x0000 + |L17.20| + DCD 0x40021000 + + AREA ||i.RCC_HSEConfig||, CODE, READONLY, ALIGN=2 + + RCC_HSEConfig PROC +;;;275 */ +;;;276 void RCC_HSEConfig(uint32_t RCC_HSE) +000000 4911 LDR r1,|L18.72| +;;;277 { +;;;278 /* Check the parameters */ +;;;279 assert_param(IS_RCC_HSE(RCC_HSE)); +;;;280 /* Reset HSEON and HSEBYP bits before configuring the HSE ------------------*/ +;;;281 /* Reset HSEON bit */ +;;;282 RCC->CR &= CR_HSEON_Reset; +000002 6809 LDR r1,[r1,#0] +000004 f4213180 BIC r1,r1,#0x10000 +000008 4a0f LDR r2,|L18.72| +00000a 6011 STR r1,[r2,#0] +;;;283 /* Reset HSEBYP bit */ +;;;284 RCC->CR &= CR_HSEBYP_Reset; +00000c 4611 MOV r1,r2 +00000e 6809 LDR r1,[r1,#0] +000010 f4212180 BIC r1,r1,#0x40000 +000014 6011 STR r1,[r2,#0] +;;;285 /* Configure HSE (RCC_HSE_OFF is already covered by the code section above) */ +;;;286 switch(RCC_HSE) +000016 f5b03f80 CMP r0,#0x10000 +00001a d003 BEQ |L18.36| +00001c f5b02f80 CMP r0,#0x40000 +000020 d10e BNE |L18.64| +000022 e006 B |L18.50| + |L18.36| +;;;287 { +;;;288 case RCC_HSE_ON: +;;;289 /* Set HSEON bit */ +;;;290 RCC->CR |= CR_HSEON_Set; +000024 4908 LDR r1,|L18.72| +000026 6809 LDR r1,[r1,#0] +000028 f4413180 ORR r1,r1,#0x10000 +00002c 4a06 LDR r2,|L18.72| +00002e 6011 STR r1,[r2,#0] +;;;291 break; +000030 e007 B |L18.66| + |L18.50| +;;;292 +;;;293 case RCC_HSE_Bypass: +;;;294 /* Set HSEBYP and HSEON bits */ +;;;295 RCC->CR |= CR_HSEBYP_Set | CR_HSEON_Set; +000032 4905 LDR r1,|L18.72| +000034 6809 LDR r1,[r1,#0] +000036 f44121a0 ORR r1,r1,#0x50000 +00003a 4a03 LDR r2,|L18.72| +00003c 6011 STR r1,[r2,#0] +;;;296 break; +00003e e000 B |L18.66| + |L18.64| +;;;297 +;;;298 default: +;;;299 break; +000040 bf00 NOP + |L18.66| +000042 bf00 NOP ;291 +;;;300 } +;;;301 } +000044 4770 BX lr +;;;302 + ENDP + +000046 0000 DCW 0x0000 + |L18.72| + DCD 0x40021000 + + AREA ||i.RCC_HSICmd||, CODE, READONLY, ALIGN=2 + + RCC_HSICmd PROC +;;;359 */ +;;;360 void RCC_HSICmd(FunctionalState NewState) +000000 4901 LDR r1,|L19.8| +;;;361 { +;;;362 /* Check the parameters */ +;;;363 assert_param(IS_FUNCTIONAL_STATE(NewState)); +;;;364 *(__IO uint32_t *) CR_HSION_BB = (uint32_t)NewState; +000002 6008 STR r0,[r1,#0] +;;;365 } +000004 4770 BX lr +;;;366 + ENDP + +000006 0000 DCW 0x0000 + |L19.8| + DCD 0x42420000 + + AREA ||i.RCC_ITConfig||, CODE, READONLY, ALIGN=2 + + RCC_ITConfig PROC +;;;705 */ +;;;706 void RCC_ITConfig(uint8_t RCC_IT, FunctionalState NewState) +000000 b129 CBZ r1,|L20.14| +;;;707 { +;;;708 /* Check the parameters */ +;;;709 assert_param(IS_RCC_IT(RCC_IT)); +;;;710 assert_param(IS_FUNCTIONAL_STATE(NewState)); +;;;711 if (NewState != DISABLE) +;;;712 { +;;;713 /* Perform Byte access to RCC_CIR bits to enable the selected interrupts */ +;;;714 *(__IO uint8_t *) CIR_BYTE2_ADDRESS |= RCC_IT; +000002 4a06 LDR r2,|L20.28| +000004 7a52 LDRB r2,[r2,#9] +000006 4302 ORRS r2,r2,r0 +000008 4b04 LDR r3,|L20.28| +00000a 725a STRB r2,[r3,#9] +00000c e004 B |L20.24| + |L20.14| +;;;715 } +;;;716 else +;;;717 { +;;;718 /* Perform Byte access to RCC_CIR bits to disable the selected interrupts */ +;;;719 *(__IO uint8_t *) CIR_BYTE2_ADDRESS &= (uint8_t)~RCC_IT; +00000e 4a03 LDR r2,|L20.28| +000010 7a52 LDRB r2,[r2,#9] +000012 4382 BICS r2,r2,r0 +000014 4b01 LDR r3,|L20.28| +000016 725a STRB r2,[r3,#9] + |L20.24| +;;;720 } +;;;721 } +000018 4770 BX lr +;;;722 + ENDP + +00001a 0000 DCW 0x0000 + |L20.28| + DCD 0x40021000 + + AREA ||i.RCC_LSEConfig||, CODE, READONLY, ALIGN=2 + + RCC_LSEConfig PROC +;;;834 */ +;;;835 void RCC_LSEConfig(uint8_t RCC_LSE) +000000 2100 MOVS r1,#0 +;;;836 { +;;;837 /* Check the parameters */ +;;;838 assert_param(IS_RCC_LSE(RCC_LSE)); +;;;839 /* Reset LSEON and LSEBYP bits before configuring the LSE ------------------*/ +;;;840 /* Reset LSEON bit */ +;;;841 *(__IO uint8_t *) BDCR_ADDRESS = RCC_LSE_OFF; +000002 4a0b LDR r2,|L21.48| +000004 7011 STRB r1,[r2,#0] +;;;842 /* Reset LSEBYP bit */ +;;;843 *(__IO uint8_t *) BDCR_ADDRESS = RCC_LSE_OFF; +000006 4a0a LDR r2,|L21.48| +000008 3a20 SUBS r2,r2,#0x20 +00000a f8821020 STRB r1,[r2,#0x20] +;;;844 /* Configure LSE (RCC_LSE_OFF is already covered by the code section above) */ +;;;845 switch(RCC_LSE) +00000e 2801 CMP r0,#1 +000010 d002 BEQ |L21.24| +000012 2804 CMP r0,#4 +000014 d108 BNE |L21.40| +000016 e003 B |L21.32| + |L21.24| +;;;846 { +;;;847 case RCC_LSE_ON: +;;;848 /* Set LSEON bit */ +;;;849 *(__IO uint8_t *) BDCR_ADDRESS = RCC_LSE_ON; +000018 2101 MOVS r1,#1 +00001a 4a05 LDR r2,|L21.48| +00001c 7011 STRB r1,[r2,#0] +;;;850 break; +00001e e004 B |L21.42| + |L21.32| +;;;851 +;;;852 case RCC_LSE_Bypass: +;;;853 /* Set LSEBYP and LSEON bits */ +;;;854 *(__IO uint8_t *) BDCR_ADDRESS = RCC_LSE_Bypass | RCC_LSE_ON; +000020 2105 MOVS r1,#5 +000022 4a03 LDR r2,|L21.48| +000024 7011 STRB r1,[r2,#0] +;;;855 break; +000026 e000 B |L21.42| + |L21.40| +;;;856 +;;;857 default: +;;;858 break; +000028 bf00 NOP + |L21.42| +00002a bf00 NOP ;850 +;;;859 } +;;;860 } +00002c 4770 BX lr +;;;861 + ENDP + +00002e 0000 DCW 0x0000 + |L21.48| + DCD 0x40021020 + + AREA ||i.RCC_LSICmd||, CODE, READONLY, ALIGN=2 + + RCC_LSICmd PROC +;;;867 */ +;;;868 void RCC_LSICmd(FunctionalState NewState) +000000 4901 LDR r1,|L22.8| +;;;869 { +;;;870 /* Check the parameters */ +;;;871 assert_param(IS_FUNCTIONAL_STATE(NewState)); +;;;872 *(__IO uint32_t *) CSR_LSION_BB = (uint32_t)NewState; +000002 6008 STR r0,[r1,#0] +;;;873 } +000004 4770 BX lr +;;;874 + ENDP + +000006 0000 DCW 0x0000 + |L22.8| + DCD 0x42420480 + + AREA ||i.RCC_MCOConfig||, CODE, READONLY, ALIGN=2 + + RCC_MCOConfig PROC +;;;1287 */ +;;;1288 void RCC_MCOConfig(uint8_t RCC_MCO) +000000 4901 LDR r1,|L23.8| +;;;1289 { +;;;1290 /* Check the parameters */ +;;;1291 assert_param(IS_RCC_MCO(RCC_MCO)); +;;;1292 +;;;1293 /* Perform Byte access to MCO bits to select the MCO source */ +;;;1294 *(__IO uint8_t *) CFGR_BYTE4_ADDRESS = RCC_MCO; +000002 71c8 STRB r0,[r1,#7] +;;;1295 } +000004 4770 BX lr +;;;1296 + ENDP + +000006 0000 DCW 0x0000 + |L23.8| + DCD 0x40021000 + + AREA ||i.RCC_PCLK1Config||, CODE, READONLY, ALIGN=2 + + RCC_PCLK1Config PROC +;;;639 */ +;;;640 void RCC_PCLK1Config(uint32_t RCC_HCLK) +000000 4601 MOV r1,r0 +;;;641 { +;;;642 uint32_t tmpreg = 0; +000002 2000 MOVS r0,#0 +;;;643 /* Check the parameters */ +;;;644 assert_param(IS_RCC_PCLK(RCC_HCLK)); +;;;645 tmpreg = RCC->CFGR; +000004 4a03 LDR r2,|L24.20| +000006 6850 LDR r0,[r2,#4] +;;;646 /* Clear PPRE1[2:0] bits */ +;;;647 tmpreg &= CFGR_PPRE1_Reset_Mask; +000008 f42060e0 BIC r0,r0,#0x700 +;;;648 /* Set PPRE1[2:0] bits according to RCC_HCLK value */ +;;;649 tmpreg |= RCC_HCLK; +00000c 4308 ORRS r0,r0,r1 +;;;650 /* Store the new value */ +;;;651 RCC->CFGR = tmpreg; +00000e 6050 STR r0,[r2,#4] +;;;652 } +000010 4770 BX lr +;;;653 + ENDP + +000012 0000 DCW 0x0000 + |L24.20| + DCD 0x40021000 + + AREA ||i.RCC_PCLK2Config||, CODE, READONLY, ALIGN=2 + + RCC_PCLK2Config PROC +;;;665 */ +;;;666 void RCC_PCLK2Config(uint32_t RCC_HCLK) +000000 4601 MOV r1,r0 +;;;667 { +;;;668 uint32_t tmpreg = 0; +000002 2000 MOVS r0,#0 +;;;669 /* Check the parameters */ +;;;670 assert_param(IS_RCC_PCLK(RCC_HCLK)); +;;;671 tmpreg = RCC->CFGR; +000004 4a03 LDR r2,|L25.20| +000006 6850 LDR r0,[r2,#4] +;;;672 /* Clear PPRE2[2:0] bits */ +;;;673 tmpreg &= CFGR_PPRE2_Reset_Mask; +000008 f4205060 BIC r0,r0,#0x3800 +;;;674 /* Set PPRE2[2:0] bits according to RCC_HCLK value */ +;;;675 tmpreg |= RCC_HCLK << 3; +00000c ea4000c1 ORR r0,r0,r1,LSL #3 +;;;676 /* Store the new value */ +;;;677 RCC->CFGR = tmpreg; +000010 6050 STR r0,[r2,#4] +;;;678 } +000012 4770 BX lr +;;;679 + ENDP + + |L25.20| + DCD 0x40021000 + + AREA ||i.RCC_PLLCmd||, CODE, READONLY, ALIGN=2 + + RCC_PLLCmd PROC +;;;406 */ +;;;407 void RCC_PLLCmd(FunctionalState NewState) +000000 4901 LDR r1,|L26.8| +;;;408 { +;;;409 /* Check the parameters */ +;;;410 assert_param(IS_FUNCTIONAL_STATE(NewState)); +;;;411 +;;;412 *(__IO uint32_t *) CR_PLLON_BB = (uint32_t)NewState; +000002 6608 STR r0,[r1,#0x60] +;;;413 } +000004 4770 BX lr +;;;414 + ENDP + +000006 0000 DCW 0x0000 + |L26.8| + DCD 0x42420000 + + AREA ||i.RCC_PLLConfig||, CODE, READONLY, ALIGN=2 + + RCC_PLLConfig PROC +;;;383 */ +;;;384 void RCC_PLLConfig(uint32_t RCC_PLLSource, uint32_t RCC_PLLMul) +000000 4602 MOV r2,r0 +;;;385 { +;;;386 uint32_t tmpreg = 0; +000002 2000 MOVS r0,#0 +;;;387 +;;;388 /* Check the parameters */ +;;;389 assert_param(IS_RCC_PLL_SOURCE(RCC_PLLSource)); +;;;390 assert_param(IS_RCC_PLL_MUL(RCC_PLLMul)); +;;;391 +;;;392 tmpreg = RCC->CFGR; +000004 4b04 LDR r3,|L27.24| +000006 6858 LDR r0,[r3,#4] +;;;393 /* Clear PLLSRC, PLLXTPRE and PLLMUL[3:0] bits */ +;;;394 tmpreg &= CFGR_PLL_Mask; +000008 f420107c BIC r0,r0,#0x3f0000 +;;;395 /* Set the PLL configuration bits */ +;;;396 tmpreg |= RCC_PLLSource | RCC_PLLMul; +00000c ea420301 ORR r3,r2,r1 +000010 4318 ORRS r0,r0,r3 +;;;397 /* Store the new value */ +;;;398 RCC->CFGR = tmpreg; +000012 4b01 LDR r3,|L27.24| +000014 6058 STR r0,[r3,#4] +;;;399 } +000016 4770 BX lr +;;;400 + ENDP + + |L27.24| + DCD 0x40021000 + + AREA ||i.RCC_RTCCLKCmd||, CODE, READONLY, ALIGN=2 + + RCC_RTCCLKCmd PROC +;;;898 */ +;;;899 void RCC_RTCCLKCmd(FunctionalState NewState) +000000 4901 LDR r1,|L28.8| +;;;900 { +;;;901 /* Check the parameters */ +;;;902 assert_param(IS_FUNCTIONAL_STATE(NewState)); +;;;903 *(__IO uint32_t *) BDCR_RTCEN_BB = (uint32_t)NewState; +000002 6008 STR r0,[r1,#0] +;;;904 } +000004 4770 BX lr +;;;905 + ENDP + +000006 0000 DCW 0x0000 + |L28.8| + DCD 0x4242043c + + AREA ||i.RCC_RTCCLKConfig||, CODE, READONLY, ALIGN=2 + + RCC_RTCCLKConfig PROC +;;;884 */ +;;;885 void RCC_RTCCLKConfig(uint32_t RCC_RTCCLKSource) +000000 4902 LDR r1,|L29.12| +;;;886 { +;;;887 /* Check the parameters */ +;;;888 assert_param(IS_RCC_RTCCLK_SOURCE(RCC_RTCCLKSource)); +;;;889 /* Select the RTC clock source */ +;;;890 RCC->BDCR |= RCC_RTCCLKSource; +000002 6a09 LDR r1,[r1,#0x20] +000004 4301 ORRS r1,r1,r0 +000006 4a01 LDR r2,|L29.12| +000008 6211 STR r1,[r2,#0x20] +;;;891 } +00000a 4770 BX lr +;;;892 + ENDP + + |L29.12| + DCD 0x40021000 + + AREA ||i.RCC_SYSCLKConfig||, CODE, READONLY, ALIGN=2 + + RCC_SYSCLKConfig PROC +;;;569 */ +;;;570 void RCC_SYSCLKConfig(uint32_t RCC_SYSCLKSource) +000000 4601 MOV r1,r0 +;;;571 { +;;;572 uint32_t tmpreg = 0; +000002 2000 MOVS r0,#0 +;;;573 /* Check the parameters */ +;;;574 assert_param(IS_RCC_SYSCLK_SOURCE(RCC_SYSCLKSource)); +;;;575 tmpreg = RCC->CFGR; +000004 4a03 LDR r2,|L30.20| +000006 6850 LDR r0,[r2,#4] +;;;576 /* Clear SW[1:0] bits */ +;;;577 tmpreg &= CFGR_SW_Mask; +000008 f0200003 BIC r0,r0,#3 +;;;578 /* Set SW[1:0] bits according to RCC_SYSCLKSource value */ +;;;579 tmpreg |= RCC_SYSCLKSource; +00000c 4308 ORRS r0,r0,r1 +;;;580 /* Store the new value */ +;;;581 RCC->CFGR = tmpreg; +00000e 6050 STR r0,[r2,#4] +;;;582 } +000010 4770 BX lr +;;;583 + ENDP + +000012 0000 DCW 0x0000 + |L30.20| + DCD 0x40021000 + + AREA ||i.RCC_USBCLKConfig||, CODE, READONLY, ALIGN=2 + + RCC_USBCLKConfig PROC +;;;733 */ +;;;734 void RCC_USBCLKConfig(uint32_t RCC_USBCLKSource) +000000 4901 LDR r1,|L31.8| +;;;735 { +;;;736 /* Check the parameters */ +;;;737 assert_param(IS_RCC_USBCLK_SOURCE(RCC_USBCLKSource)); +;;;738 +;;;739 *(__IO uint32_t *) CFGR_USBPRE_BB = RCC_USBCLKSource; +000002 6008 STR r0,[r1,#0] +;;;740 } +000004 4770 BX lr +;;;741 #else + ENDP + +000006 0000 DCW 0x0000 + |L31.8| + DCD 0x424200d8 + + AREA ||i.RCC_WaitForHSEStartUp||, CODE, READONLY, ALIGN=1 + + RCC_WaitForHSEStartUp PROC +;;;309 */ +;;;310 ErrorStatus RCC_WaitForHSEStartUp(void) +000000 b538 PUSH {r3-r5,lr} +;;;311 { +;;;312 __IO uint32_t StartUpCounter = 0; +000002 2000 MOVS r0,#0 +000004 9000 STR r0,[sp,#0] +;;;313 ErrorStatus status = ERROR; +000006 2400 MOVS r4,#0 +;;;314 FlagStatus HSEStatus = RESET; +000008 2500 MOVS r5,#0 +;;;315 +;;;316 /* Wait till HSE is ready and if Time out is reached exit */ +;;;317 do +00000a bf00 NOP + |L32.12| +;;;318 { +;;;319 HSEStatus = RCC_GetFlagStatus(RCC_FLAG_HSERDY); +00000c 2031 MOVS r0,#0x31 +00000e f7fffffe BL RCC_GetFlagStatus +000012 4605 MOV r5,r0 +;;;320 StartUpCounter++; +000014 9800 LDR r0,[sp,#0] +000016 1c40 ADDS r0,r0,#1 +000018 9000 STR r0,[sp,#0] +;;;321 } while((StartUpCounter != HSE_STARTUP_TIMEOUT) && (HSEStatus == RESET)); +00001a 9800 LDR r0,[sp,#0] +00001c f5b06fa0 CMP r0,#0x500 +000020 d001 BEQ |L32.38| +000022 2d00 CMP r5,#0 +000024 d0f2 BEQ |L32.12| + |L32.38| +;;;322 +;;;323 if (RCC_GetFlagStatus(RCC_FLAG_HSERDY) != RESET) +000026 2031 MOVS r0,#0x31 +000028 f7fffffe BL RCC_GetFlagStatus +00002c b108 CBZ r0,|L32.50| +;;;324 { +;;;325 status = SUCCESS; +00002e 2401 MOVS r4,#1 +000030 e000 B |L32.52| + |L32.50| +;;;326 } +;;;327 else +;;;328 { +;;;329 status = ERROR; +000032 2400 MOVS r4,#0 + |L32.52| +;;;330 } +;;;331 return (status); +000034 4620 MOV r0,r4 +;;;332 } +000036 bd38 POP {r3-r5,pc} +;;;333 + ENDP + + + AREA ||.data||, DATA, ALIGN=0 + + APBAHBPrescTable +000000 00000000 DCB 0x00,0x00,0x00,0x00 +000004 01020304 DCB 0x01,0x02,0x03,0x04 +000008 01020304 DCB 0x01,0x02,0x03,0x04 +00000c 06070809 DCB 0x06,0x07,0x08,0x09 + ADCPrescTable +000010 02040608 DCB 0x02,0x04,0x06,0x08 + +;*** Start embedded assembler *** + +#line 1 "..\\..\\Libraries\\STM32F10x_StdPeriph_Driver\\src\\stm32f10x_rcc.c" + AREA ||.rev16_text||, CODE + THUMB + EXPORT |__asm___15_stm32f10x_rcc_c_49e27980____REV16| +#line 114 "..\\..\\Libraries\\CMSIS\\Include\\core_cmInstr.h" +|__asm___15_stm32f10x_rcc_c_49e27980____REV16| PROC +#line 115 + + rev16 r0, r0 + bx lr + ENDP + AREA ||.revsh_text||, CODE + THUMB + EXPORT |__asm___15_stm32f10x_rcc_c_49e27980____REVSH| +#line 128 +|__asm___15_stm32f10x_rcc_c_49e27980____REVSH| PROC +#line 129 + + revsh r0, r0 + bx lr + ENDP + +;*** End embedded assembler *** diff --git a/Project/MDK-ARM/Flash/List/stm32f10x_tim.txt b/Project/MDK-ARM/Flash/List/stm32f10x_tim.txt new file mode 100644 index 0000000..44e1771 --- /dev/null +++ b/Project/MDK-ARM/Flash/List/stm32f10x_tim.txt @@ -0,0 +1,4144 @@ +; generated by Component: ARM Compiler 5.06 update 7 (build 960) Tool: ArmCC [4d365d] +; commandline ArmCC [--list --split_sections --debug -c --asm --interleave -o.\flash\obj\stm32f10x_tim.o --asm_dir=.\Flash\List\ --list_dir=.\Flash\List\ --depend=.\flash\obj\stm32f10x_tim.d --cpu=Cortex-M3 --apcs=interwork -O0 --diag_suppress=9931,870 -I..\..\Libraries\CMSIS\Device\ST\STM32F10x\Include -I..\..\Libraries\STM32F10x_StdPeriph_Driver\inc -I..\..\Libraries\STM32_USB-FS-Device_Driver\inc -I..\..\Libraries\CMSIS\Include -I..\..\User\bsp -I..\..\User\bsp\inc -I..\..\User\app\inc -I..\..\User -IC:\Users\w1619\AppData\Local\Arm\Packs\Keil\STM32F1xx_DFP\2.4.1\Device\Include -D__MICROLIB -D__UVISION_VERSION=538 -DSTM32F10X_HD -DUSE_STDPERIPH_DRIVER -DSTM32F10X_HD --omf_browse=.\flash\obj\stm32f10x_tim.crf ..\..\Libraries\STM32F10x_StdPeriph_Driver\src\stm32f10x_tim.c] + THUMB + + AREA ||i.TI1_Config||, CODE, READONLY, ALIGN=2 + + TI1_Config PROC +;;;2706 */ +;;;2707 static void TI1_Config(TIM_TypeDef* TIMx, uint16_t TIM_ICPolarity, uint16_t TIM_ICSelection, +000000 b5f0 PUSH {r4-r7,lr} +;;;2708 uint16_t TIM_ICFilter) +;;;2709 { +000002 460c MOV r4,r1 +000004 4615 MOV r5,r2 +;;;2710 uint16_t tmpccmr1 = 0, tmpccer = 0; +000006 2200 MOVS r2,#0 +000008 2100 MOVS r1,#0 +;;;2711 /* Disable the Channel 1: Reset the CC1E Bit */ +;;;2712 TIMx->CCER &= (uint16_t)~((uint16_t)TIM_CCER_CC1E); +00000a 8c06 LDRH r6,[r0,#0x20] +00000c f64f77fe MOV r7,#0xfffe +000010 403e ANDS r6,r6,r7 +000012 8406 STRH r6,[r0,#0x20] +;;;2713 tmpccmr1 = TIMx->CCMR1; +000014 8b02 LDRH r2,[r0,#0x18] +;;;2714 tmpccer = TIMx->CCER; +000016 8c01 LDRH r1,[r0,#0x20] +;;;2715 /* Select the Input and set the filter */ +;;;2716 tmpccmr1 &= (uint16_t)(((uint16_t)~((uint16_t)TIM_CCMR1_CC1S)) & ((uint16_t)~((uint16_t)TIM_CCMR1_IC1F))); +000018 f64f760c MOV r6,#0xff0c +00001c 4032 ANDS r2,r2,r6 +;;;2717 tmpccmr1 |= (uint16_t)(TIM_ICSelection | (uint16_t)(TIM_ICFilter << (uint16_t)4)); +00001e 1c7e ADDS r6,r7,#1 +000020 ea061603 AND r6,r6,r3,LSL #4 +000024 432e ORRS r6,r6,r5 +000026 4332 ORRS r2,r2,r6 +;;;2718 +;;;2719 if((TIMx == TIM1) || (TIMx == TIM8) || (TIMx == TIM2) || (TIMx == TIM3) || +000028 4e10 LDR r6,|L1.108| +00002a 42b0 CMP r0,r6 +00002c d00e BEQ |L1.76| +00002e 4e10 LDR r6,|L1.112| +000030 42b0 CMP r0,r6 +000032 d00b BEQ |L1.76| +000034 f1b04f80 CMP r0,#0x40000000 +000038 d008 BEQ |L1.76| +00003a 4e0e LDR r6,|L1.116| +00003c 42b0 CMP r0,r6 +00003e d005 BEQ |L1.76| +;;;2720 (TIMx == TIM4) ||(TIMx == TIM5)) +000040 4e0d LDR r6,|L1.120| +000042 42b0 CMP r0,r6 +000044 d002 BEQ |L1.76| +000046 4e0d LDR r6,|L1.124| +000048 42b0 CMP r0,r6 +00004a d106 BNE |L1.90| + |L1.76| +;;;2721 { +;;;2722 /* Select the Polarity and set the CC1E Bit */ +;;;2723 tmpccer &= (uint16_t)~((uint16_t)(TIM_CCER_CC1P)); +00004c f64f76fd MOV r6,#0xfffd +000050 4031 ANDS r1,r1,r6 +;;;2724 tmpccer |= (uint16_t)(TIM_ICPolarity | (uint16_t)TIM_CCER_CC1E); +000052 f0440601 ORR r6,r4,#1 +000056 4331 ORRS r1,r1,r6 +000058 e005 B |L1.102| + |L1.90| +;;;2725 } +;;;2726 else +;;;2727 { +;;;2728 /* Select the Polarity and set the CC1E Bit */ +;;;2729 tmpccer &= (uint16_t)~((uint16_t)(TIM_CCER_CC1P | TIM_CCER_CC1NP)); +00005a f64f76f5 MOV r6,#0xfff5 +00005e 4031 ANDS r1,r1,r6 +;;;2730 tmpccer |= (uint16_t)(TIM_ICPolarity | (uint16_t)TIM_CCER_CC1E); +000060 f0440601 ORR r6,r4,#1 +000064 4331 ORRS r1,r1,r6 + |L1.102| +;;;2731 } +;;;2732 +;;;2733 /* Write to TIMx CCMR1 and CCER registers */ +;;;2734 TIMx->CCMR1 = tmpccmr1; +000066 8302 STRH r2,[r0,#0x18] +;;;2735 TIMx->CCER = tmpccer; +000068 8401 STRH r1,[r0,#0x20] +;;;2736 } +00006a bdf0 POP {r4-r7,pc} +;;;2737 + ENDP + + |L1.108| + DCD 0x40012c00 + |L1.112| + DCD 0x40013400 + |L1.116| + DCD 0x40000400 + |L1.120| + DCD 0x40000800 + |L1.124| + DCD 0x40000c00 + + AREA ||i.TI2_Config||, CODE, READONLY, ALIGN=2 + + TI2_Config PROC +;;;2753 */ +;;;2754 static void TI2_Config(TIM_TypeDef* TIMx, uint16_t TIM_ICPolarity, uint16_t TIM_ICSelection, +000000 b5f0 PUSH {r4-r7,lr} +;;;2755 uint16_t TIM_ICFilter) +;;;2756 { +000002 460c MOV r4,r1 +000004 4615 MOV r5,r2 +;;;2757 uint16_t tmpccmr1 = 0, tmpccer = 0, tmp = 0; +000006 2200 MOVS r2,#0 +000008 2100 MOVS r1,#0 +00000a 2600 MOVS r6,#0 +;;;2758 /* Disable the Channel 2: Reset the CC2E Bit */ +;;;2759 TIMx->CCER &= (uint16_t)~((uint16_t)TIM_CCER_CC2E); +00000c 8c07 LDRH r7,[r0,#0x20] +00000e f64f7cef MOV r12,#0xffef +000012 ea07070c AND r7,r7,r12 +000016 8407 STRH r7,[r0,#0x20] +;;;2760 tmpccmr1 = TIMx->CCMR1; +000018 8b02 LDRH r2,[r0,#0x18] +;;;2761 tmpccer = TIMx->CCER; +00001a 8c01 LDRH r1,[r0,#0x20] +;;;2762 tmp = (uint16_t)(TIM_ICPolarity << 4); +00001c f64f77ff MOV r7,#0xffff +000020 ea071604 AND r6,r7,r4,LSL #4 +;;;2763 /* Select the Input and set the filter */ +;;;2764 tmpccmr1 &= (uint16_t)(((uint16_t)~((uint16_t)TIM_CCMR1_CC2S)) & ((uint16_t)~((uint16_t)TIM_CCMR1_IC2F))); +000024 f64047ff MOV r7,#0xcff +000028 403a ANDS r2,r2,r7 +;;;2765 tmpccmr1 |= (uint16_t)(TIM_ICFilter << 12); +00002a f64f77ff MOV r7,#0xffff +00002e ea073703 AND r7,r7,r3,LSL #12 +000032 433a ORRS r2,r2,r7 +;;;2766 tmpccmr1 |= (uint16_t)(TIM_ICSelection << 8); +000034 f64f77ff MOV r7,#0xffff +000038 ea072705 AND r7,r7,r5,LSL #8 +00003c 433a ORRS r2,r2,r7 +;;;2767 +;;;2768 if((TIMx == TIM1) || (TIMx == TIM8) || (TIMx == TIM2) || (TIMx == TIM3) || +00003e 4f11 LDR r7,|L2.132| +000040 42b8 CMP r0,r7 +000042 d00e BEQ |L2.98| +000044 4f10 LDR r7,|L2.136| +000046 42b8 CMP r0,r7 +000048 d00b BEQ |L2.98| +00004a f1b04f80 CMP r0,#0x40000000 +00004e d008 BEQ |L2.98| +000050 4f0e LDR r7,|L2.140| +000052 42b8 CMP r0,r7 +000054 d005 BEQ |L2.98| +;;;2769 (TIMx == TIM4) ||(TIMx == TIM5)) +000056 4f0e LDR r7,|L2.144| +000058 42b8 CMP r0,r7 +00005a d002 BEQ |L2.98| +00005c 4f0d LDR r7,|L2.148| +00005e 42b8 CMP r0,r7 +000060 d106 BNE |L2.112| + |L2.98| +;;;2770 { +;;;2771 /* Select the Polarity and set the CC2E Bit */ +;;;2772 tmpccer &= (uint16_t)~((uint16_t)(TIM_CCER_CC2P)); +000062 f64f77df MOV r7,#0xffdf +000066 4039 ANDS r1,r1,r7 +;;;2773 tmpccer |= (uint16_t)(tmp | (uint16_t)TIM_CCER_CC2E); +000068 f0460710 ORR r7,r6,#0x10 +00006c 4339 ORRS r1,r1,r7 +00006e e005 B |L2.124| + |L2.112| +;;;2774 } +;;;2775 else +;;;2776 { +;;;2777 /* Select the Polarity and set the CC2E Bit */ +;;;2778 tmpccer &= (uint16_t)~((uint16_t)(TIM_CCER_CC2P | TIM_CCER_CC2NP)); +000070 f64f775f MOV r7,#0xff5f +000074 4039 ANDS r1,r1,r7 +;;;2779 tmpccer |= (uint16_t)(TIM_ICPolarity | (uint16_t)TIM_CCER_CC2E); +000076 f0440710 ORR r7,r4,#0x10 +00007a 4339 ORRS r1,r1,r7 + |L2.124| +;;;2780 } +;;;2781 +;;;2782 /* Write to TIMx CCMR1 and CCER registers */ +;;;2783 TIMx->CCMR1 = tmpccmr1 ; +00007c 8302 STRH r2,[r0,#0x18] +;;;2784 TIMx->CCER = tmpccer; +00007e 8401 STRH r1,[r0,#0x20] +;;;2785 } +000080 bdf0 POP {r4-r7,pc} +;;;2786 + ENDP + +000082 0000 DCW 0x0000 + |L2.132| + DCD 0x40012c00 + |L2.136| + DCD 0x40013400 + |L2.140| + DCD 0x40000400 + |L2.144| + DCD 0x40000800 + |L2.148| + DCD 0x40000c00 + + AREA ||i.TI3_Config||, CODE, READONLY, ALIGN=2 + + TI3_Config PROC +;;;2802 */ +;;;2803 static void TI3_Config(TIM_TypeDef* TIMx, uint16_t TIM_ICPolarity, uint16_t TIM_ICSelection, +000000 b5f0 PUSH {r4-r7,lr} +;;;2804 uint16_t TIM_ICFilter) +;;;2805 { +000002 460c MOV r4,r1 +000004 4615 MOV r5,r2 +;;;2806 uint16_t tmpccmr2 = 0, tmpccer = 0, tmp = 0; +000006 2200 MOVS r2,#0 +000008 2100 MOVS r1,#0 +00000a 2600 MOVS r6,#0 +;;;2807 /* Disable the Channel 3: Reset the CC3E Bit */ +;;;2808 TIMx->CCER &= (uint16_t)~((uint16_t)TIM_CCER_CC3E); +00000c 8c07 LDRH r7,[r0,#0x20] +00000e f64f6cff MOV r12,#0xfeff +000012 ea07070c AND r7,r7,r12 +000016 8407 STRH r7,[r0,#0x20] +;;;2809 tmpccmr2 = TIMx->CCMR2; +000018 8b82 LDRH r2,[r0,#0x1c] +;;;2810 tmpccer = TIMx->CCER; +00001a 8c01 LDRH r1,[r0,#0x20] +;;;2811 tmp = (uint16_t)(TIM_ICPolarity << 8); +00001c f64f77ff MOV r7,#0xffff +000020 ea072604 AND r6,r7,r4,LSL #8 +;;;2812 /* Select the Input and set the filter */ +;;;2813 tmpccmr2 &= (uint16_t)(((uint16_t)~((uint16_t)TIM_CCMR2_CC3S)) & ((uint16_t)~((uint16_t)TIM_CCMR2_IC3F))); +000024 f64f770c MOV r7,#0xff0c +000028 403a ANDS r2,r2,r7 +;;;2814 tmpccmr2 |= (uint16_t)(TIM_ICSelection | (uint16_t)(TIM_ICFilter << (uint16_t)4)); +00002a f64f77ff MOV r7,#0xffff +00002e ea071703 AND r7,r7,r3,LSL #4 +000032 432f ORRS r7,r7,r5 +000034 433a ORRS r2,r2,r7 +;;;2815 +;;;2816 if((TIMx == TIM1) || (TIMx == TIM8) || (TIMx == TIM2) || (TIMx == TIM3) || +000036 4f11 LDR r7,|L3.124| +000038 42b8 CMP r0,r7 +00003a d00e BEQ |L3.90| +00003c 4f10 LDR r7,|L3.128| +00003e 42b8 CMP r0,r7 +000040 d00b BEQ |L3.90| +000042 f1b04f80 CMP r0,#0x40000000 +000046 d008 BEQ |L3.90| +000048 4f0e LDR r7,|L3.132| +00004a 42b8 CMP r0,r7 +00004c d005 BEQ |L3.90| +;;;2817 (TIMx == TIM4) ||(TIMx == TIM5)) +00004e 4f0e LDR r7,|L3.136| +000050 42b8 CMP r0,r7 +000052 d002 BEQ |L3.90| +000054 4f0d LDR r7,|L3.140| +000056 42b8 CMP r0,r7 +000058 d106 BNE |L3.104| + |L3.90| +;;;2818 { +;;;2819 /* Select the Polarity and set the CC3E Bit */ +;;;2820 tmpccer &= (uint16_t)~((uint16_t)(TIM_CCER_CC3P)); +00005a f64f57ff MOV r7,#0xfdff +00005e 4039 ANDS r1,r1,r7 +;;;2821 tmpccer |= (uint16_t)(tmp | (uint16_t)TIM_CCER_CC3E); +000060 f4467780 ORR r7,r6,#0x100 +000064 4339 ORRS r1,r1,r7 +000066 e005 B |L3.116| + |L3.104| +;;;2822 } +;;;2823 else +;;;2824 { +;;;2825 /* Select the Polarity and set the CC3E Bit */ +;;;2826 tmpccer &= (uint16_t)~((uint16_t)(TIM_CCER_CC3P | TIM_CCER_CC3NP)); +000068 f24f57ff MOV r7,#0xf5ff +00006c 4039 ANDS r1,r1,r7 +;;;2827 tmpccer |= (uint16_t)(TIM_ICPolarity | (uint16_t)TIM_CCER_CC3E); +00006e f4447780 ORR r7,r4,#0x100 +000072 4339 ORRS r1,r1,r7 + |L3.116| +;;;2828 } +;;;2829 +;;;2830 /* Write to TIMx CCMR2 and CCER registers */ +;;;2831 TIMx->CCMR2 = tmpccmr2; +000074 8382 STRH r2,[r0,#0x1c] +;;;2832 TIMx->CCER = tmpccer; +000076 8401 STRH r1,[r0,#0x20] +;;;2833 } +000078 bdf0 POP {r4-r7,pc} +;;;2834 + ENDP + +00007a 0000 DCW 0x0000 + |L3.124| + DCD 0x40012c00 + |L3.128| + DCD 0x40013400 + |L3.132| + DCD 0x40000400 + |L3.136| + DCD 0x40000800 + |L3.140| + DCD 0x40000c00 + + AREA ||i.TI4_Config||, CODE, READONLY, ALIGN=2 + + TI4_Config PROC +;;;2850 */ +;;;2851 static void TI4_Config(TIM_TypeDef* TIMx, uint16_t TIM_ICPolarity, uint16_t TIM_ICSelection, +000000 b5f0 PUSH {r4-r7,lr} +;;;2852 uint16_t TIM_ICFilter) +;;;2853 { +000002 460c MOV r4,r1 +000004 4615 MOV r5,r2 +;;;2854 uint16_t tmpccmr2 = 0, tmpccer = 0, tmp = 0; +000006 2200 MOVS r2,#0 +000008 2100 MOVS r1,#0 +00000a 2600 MOVS r6,#0 +;;;2855 +;;;2856 /* Disable the Channel 4: Reset the CC4E Bit */ +;;;2857 TIMx->CCER &= (uint16_t)~((uint16_t)TIM_CCER_CC4E); +00000c 8c07 LDRH r7,[r0,#0x20] +00000e f64e7cff MOV r12,#0xefff +000012 ea07070c AND r7,r7,r12 +000016 8407 STRH r7,[r0,#0x20] +;;;2858 tmpccmr2 = TIMx->CCMR2; +000018 8b82 LDRH r2,[r0,#0x1c] +;;;2859 tmpccer = TIMx->CCER; +00001a 8c01 LDRH r1,[r0,#0x20] +;;;2860 tmp = (uint16_t)(TIM_ICPolarity << 12); +00001c f64f77ff MOV r7,#0xffff +000020 ea073604 AND r6,r7,r4,LSL #12 +;;;2861 /* Select the Input and set the filter */ +;;;2862 tmpccmr2 &= (uint16_t)((uint16_t)(~(uint16_t)TIM_CCMR2_CC4S) & ((uint16_t)~((uint16_t)TIM_CCMR2_IC4F))); +000024 f64047ff MOV r7,#0xcff +000028 403a ANDS r2,r2,r7 +;;;2863 tmpccmr2 |= (uint16_t)(TIM_ICSelection << 8); +00002a f64f77ff MOV r7,#0xffff +00002e ea072705 AND r7,r7,r5,LSL #8 +000032 433a ORRS r2,r2,r7 +;;;2864 tmpccmr2 |= (uint16_t)(TIM_ICFilter << 12); +000034 f64f77ff MOV r7,#0xffff +000038 ea073703 AND r7,r7,r3,LSL #12 +00003c 433a ORRS r2,r2,r7 +;;;2865 +;;;2866 if((TIMx == TIM1) || (TIMx == TIM8) || (TIMx == TIM2) || (TIMx == TIM3) || +00003e 4f11 LDR r7,|L4.132| +000040 42b8 CMP r0,r7 +000042 d00e BEQ |L4.98| +000044 4f10 LDR r7,|L4.136| +000046 42b8 CMP r0,r7 +000048 d00b BEQ |L4.98| +00004a f1b04f80 CMP r0,#0x40000000 +00004e d008 BEQ |L4.98| +000050 4f0e LDR r7,|L4.140| +000052 42b8 CMP r0,r7 +000054 d005 BEQ |L4.98| +;;;2867 (TIMx == TIM4) ||(TIMx == TIM5)) +000056 4f0e LDR r7,|L4.144| +000058 42b8 CMP r0,r7 +00005a d002 BEQ |L4.98| +00005c 4f0d LDR r7,|L4.148| +00005e 42b8 CMP r0,r7 +000060 d106 BNE |L4.112| + |L4.98| +;;;2868 { +;;;2869 /* Select the Polarity and set the CC4E Bit */ +;;;2870 tmpccer &= (uint16_t)~((uint16_t)(TIM_CCER_CC4P)); +000062 f64d77ff MOV r7,#0xdfff +000066 4039 ANDS r1,r1,r7 +;;;2871 tmpccer |= (uint16_t)(tmp | (uint16_t)TIM_CCER_CC4E); +000068 f4465780 ORR r7,r6,#0x1000 +00006c 4339 ORRS r1,r1,r7 +00006e e005 B |L4.124| + |L4.112| +;;;2872 } +;;;2873 else +;;;2874 { +;;;2875 /* Select the Polarity and set the CC4E Bit */ +;;;2876 tmpccer &= (uint16_t)~((uint16_t)(TIM_CCER_CC3P | TIM_CCER_CC4NP)); +000070 f64757ff MOV r7,#0x7dff +000074 4039 ANDS r1,r1,r7 +;;;2877 tmpccer |= (uint16_t)(TIM_ICPolarity | (uint16_t)TIM_CCER_CC4E); +000076 f4445780 ORR r7,r4,#0x1000 +00007a 4339 ORRS r1,r1,r7 + |L4.124| +;;;2878 } +;;;2879 /* Write to TIMx CCMR2 and CCER registers */ +;;;2880 TIMx->CCMR2 = tmpccmr2; +00007c 8382 STRH r2,[r0,#0x1c] +;;;2881 TIMx->CCER = tmpccer; +00007e 8401 STRH r1,[r0,#0x20] +;;;2882 } +000080 bdf0 POP {r4-r7,pc} +;;;2883 + ENDP + +000082 0000 DCW 0x0000 + |L4.132| + DCD 0x40012c00 + |L4.136| + DCD 0x40013400 + |L4.140| + DCD 0x40000400 + |L4.144| + DCD 0x40000800 + |L4.148| + DCD 0x40000c00 + + AREA ||i.TIM_ARRPreloadConfig||, CODE, READONLY, ALIGN=1 + + TIM_ARRPreloadConfig PROC +;;;1414 */ +;;;1415 void TIM_ARRPreloadConfig(TIM_TypeDef* TIMx, FunctionalState NewState) +000000 b121 CBZ r1,|L5.12| +;;;1416 { +;;;1417 /* Check the parameters */ +;;;1418 assert_param(IS_TIM_ALL_PERIPH(TIMx)); +;;;1419 assert_param(IS_FUNCTIONAL_STATE(NewState)); +;;;1420 if (NewState != DISABLE) +;;;1421 { +;;;1422 /* Set the ARR Preload Bit */ +;;;1423 TIMx->CR1 |= TIM_CR1_ARPE; +000002 8802 LDRH r2,[r0,#0] +000004 f0420280 ORR r2,r2,#0x80 +000008 8002 STRH r2,[r0,#0] +00000a e004 B |L5.22| + |L5.12| +;;;1424 } +;;;1425 else +;;;1426 { +;;;1427 /* Reset the ARR Preload Bit */ +;;;1428 TIMx->CR1 &= (uint16_t)~((uint16_t)TIM_CR1_ARPE); +00000c 8802 LDRH r2,[r0,#0] +00000e f64f737f MOV r3,#0xff7f +000012 401a ANDS r2,r2,r3 +000014 8002 STRH r2,[r0,#0] + |L5.22| +;;;1429 } +;;;1430 } +000016 4770 BX lr +;;;1431 + ENDP + + + AREA ||i.TIM_BDTRConfig||, CODE, READONLY, ALIGN=1 + + TIM_BDTRConfig PROC +;;;717 */ +;;;718 void TIM_BDTRConfig(TIM_TypeDef* TIMx, TIM_BDTRInitTypeDef *TIM_BDTRInitStruct) +000000 880a LDRH r2,[r1,#0] +;;;719 { +;;;720 /* Check the parameters */ +;;;721 assert_param(IS_TIM_LIST2_PERIPH(TIMx)); +;;;722 assert_param(IS_TIM_OSSR_STATE(TIM_BDTRInitStruct->TIM_OSSRState)); +;;;723 assert_param(IS_TIM_OSSI_STATE(TIM_BDTRInitStruct->TIM_OSSIState)); +;;;724 assert_param(IS_TIM_LOCK_LEVEL(TIM_BDTRInitStruct->TIM_LOCKLevel)); +;;;725 assert_param(IS_TIM_BREAK_STATE(TIM_BDTRInitStruct->TIM_Break)); +;;;726 assert_param(IS_TIM_BREAK_POLARITY(TIM_BDTRInitStruct->TIM_BreakPolarity)); +;;;727 assert_param(IS_TIM_AUTOMATIC_OUTPUT_STATE(TIM_BDTRInitStruct->TIM_AutomaticOutput)); +;;;728 /* Set the Lock level, the Break enable Bit and the Ploarity, the OSSR State, +;;;729 the OSSI State, the dead time value and the Automatic Output Enable Bit */ +;;;730 TIMx->BDTR = (uint32_t)TIM_BDTRInitStruct->TIM_OSSRState | TIM_BDTRInitStruct->TIM_OSSIState | +000002 884b LDRH r3,[r1,#2] +000004 431a ORRS r2,r2,r3 +000006 888b LDRH r3,[r1,#4] +000008 431a ORRS r2,r2,r3 +00000a 88cb LDRH r3,[r1,#6] +00000c 431a ORRS r2,r2,r3 +00000e 890b LDRH r3,[r1,#8] +000010 431a ORRS r2,r2,r3 +000012 894b LDRH r3,[r1,#0xa] +000014 431a ORRS r2,r2,r3 +000016 898b LDRH r3,[r1,#0xc] +000018 431a ORRS r2,r2,r3 +00001a f8a02044 STRH r2,[r0,#0x44] +;;;731 TIM_BDTRInitStruct->TIM_LOCKLevel | TIM_BDTRInitStruct->TIM_DeadTime | +;;;732 TIM_BDTRInitStruct->TIM_Break | TIM_BDTRInitStruct->TIM_BreakPolarity | +;;;733 TIM_BDTRInitStruct->TIM_AutomaticOutput; +;;;734 } +00001e 4770 BX lr +;;;735 + ENDP + + + AREA ||i.TIM_BDTRStructInit||, CODE, READONLY, ALIGN=1 + + TIM_BDTRStructInit PROC +;;;792 */ +;;;793 void TIM_BDTRStructInit(TIM_BDTRInitTypeDef* TIM_BDTRInitStruct) +000000 2100 MOVS r1,#0 +;;;794 { +;;;795 /* Set the default configuration */ +;;;796 TIM_BDTRInitStruct->TIM_OSSRState = TIM_OSSRState_Disable; +000002 8001 STRH r1,[r0,#0] +;;;797 TIM_BDTRInitStruct->TIM_OSSIState = TIM_OSSIState_Disable; +000004 8041 STRH r1,[r0,#2] +;;;798 TIM_BDTRInitStruct->TIM_LOCKLevel = TIM_LOCKLevel_OFF; +000006 8081 STRH r1,[r0,#4] +;;;799 TIM_BDTRInitStruct->TIM_DeadTime = 0x00; +000008 80c1 STRH r1,[r0,#6] +;;;800 TIM_BDTRInitStruct->TIM_Break = TIM_Break_Disable; +00000a 8101 STRH r1,[r0,#8] +;;;801 TIM_BDTRInitStruct->TIM_BreakPolarity = TIM_BreakPolarity_Low; +00000c 8141 STRH r1,[r0,#0xa] +;;;802 TIM_BDTRInitStruct->TIM_AutomaticOutput = TIM_AutomaticOutput_Disable; +00000e 8181 STRH r1,[r0,#0xc] +;;;803 } +000010 4770 BX lr +;;;804 + ENDP + + + AREA ||i.TIM_CCPreloadControl||, CODE, READONLY, ALIGN=1 + + TIM_CCPreloadControl PROC +;;;1488 */ +;;;1489 void TIM_CCPreloadControl(TIM_TypeDef* TIMx, FunctionalState NewState) +000000 b121 CBZ r1,|L8.12| +;;;1490 { +;;;1491 /* Check the parameters */ +;;;1492 assert_param(IS_TIM_LIST5_PERIPH(TIMx)); +;;;1493 assert_param(IS_FUNCTIONAL_STATE(NewState)); +;;;1494 if (NewState != DISABLE) +;;;1495 { +;;;1496 /* Set the CCPC Bit */ +;;;1497 TIMx->CR2 |= TIM_CR2_CCPC; +000002 8882 LDRH r2,[r0,#4] +000004 f0420201 ORR r2,r2,#1 +000008 8082 STRH r2,[r0,#4] +00000a e004 B |L8.22| + |L8.12| +;;;1498 } +;;;1499 else +;;;1500 { +;;;1501 /* Reset the CCPC Bit */ +;;;1502 TIMx->CR2 &= (uint16_t)~((uint16_t)TIM_CR2_CCPC); +00000c 8882 LDRH r2,[r0,#4] +00000e f64f73fe MOV r3,#0xfffe +000012 401a ANDS r2,r2,r3 +000014 8082 STRH r2,[r0,#4] + |L8.22| +;;;1503 } +;;;1504 } +000016 4770 BX lr +;;;1505 + ENDP + + + AREA ||i.TIM_CCxCmd||, CODE, READONLY, ALIGN=1 + + TIM_CCxCmd PROC +;;;1979 */ +;;;1980 void TIM_CCxCmd(TIM_TypeDef* TIMx, uint16_t TIM_Channel, uint16_t TIM_CCx) +000000 b530 PUSH {r4,r5,lr} +;;;1981 { +;;;1982 uint16_t tmp = 0; +000002 2300 MOVS r3,#0 +;;;1983 +;;;1984 /* Check the parameters */ +;;;1985 assert_param(IS_TIM_LIST8_PERIPH(TIMx)); +;;;1986 assert_param(IS_TIM_CHANNEL(TIM_Channel)); +;;;1987 assert_param(IS_TIM_CCX(TIM_CCx)); +;;;1988 +;;;1989 tmp = CCER_CCE_Set << TIM_Channel; +000004 2401 MOVS r4,#1 +000006 408c LSLS r4,r4,r1 +000008 b2a3 UXTH r3,r4 +;;;1990 +;;;1991 /* Reset the CCxE Bit */ +;;;1992 TIMx->CCER &= (uint16_t)~ tmp; +00000a 8c04 LDRH r4,[r0,#0x20] +00000c 439c BICS r4,r4,r3 +00000e 8404 STRH r4,[r0,#0x20] +;;;1993 +;;;1994 /* Set or reset the CCxE Bit */ +;;;1995 TIMx->CCER |= (uint16_t)(TIM_CCx << TIM_Channel); +000010 8c04 LDRH r4,[r0,#0x20] +000012 fa02f501 LSL r5,r2,r1 +000016 b2ad UXTH r5,r5 +000018 432c ORRS r4,r4,r5 +00001a 8404 STRH r4,[r0,#0x20] +;;;1996 } +00001c bd30 POP {r4,r5,pc} +;;;1997 + ENDP + + + AREA ||i.TIM_CCxNCmd||, CODE, READONLY, ALIGN=1 + + TIM_CCxNCmd PROC +;;;2009 */ +;;;2010 void TIM_CCxNCmd(TIM_TypeDef* TIMx, uint16_t TIM_Channel, uint16_t TIM_CCxN) +000000 b530 PUSH {r4,r5,lr} +;;;2011 { +;;;2012 uint16_t tmp = 0; +000002 2300 MOVS r3,#0 +;;;2013 +;;;2014 /* Check the parameters */ +;;;2015 assert_param(IS_TIM_LIST2_PERIPH(TIMx)); +;;;2016 assert_param(IS_TIM_COMPLEMENTARY_CHANNEL(TIM_Channel)); +;;;2017 assert_param(IS_TIM_CCXN(TIM_CCxN)); +;;;2018 +;;;2019 tmp = CCER_CCNE_Set << TIM_Channel; +000004 2404 MOVS r4,#4 +000006 408c LSLS r4,r4,r1 +000008 b2a3 UXTH r3,r4 +;;;2020 +;;;2021 /* Reset the CCxNE Bit */ +;;;2022 TIMx->CCER &= (uint16_t) ~tmp; +00000a 8c04 LDRH r4,[r0,#0x20] +00000c 439c BICS r4,r4,r3 +00000e 8404 STRH r4,[r0,#0x20] +;;;2023 +;;;2024 /* Set or reset the CCxNE Bit */ +;;;2025 TIMx->CCER |= (uint16_t)(TIM_CCxN << TIM_Channel); +000010 8c04 LDRH r4,[r0,#0x20] +000012 fa02f501 LSL r5,r2,r1 +000016 b2ad UXTH r5,r5 +000018 432c ORRS r4,r4,r5 +00001a 8404 STRH r4,[r0,#0x20] +;;;2026 } +00001c bd30 POP {r4,r5,pc} +;;;2027 + ENDP + + + AREA ||i.TIM_ClearFlag||, CODE, READONLY, ALIGN=1 + + TIM_ClearFlag PROC +;;;2605 */ +;;;2606 void TIM_ClearFlag(TIM_TypeDef* TIMx, uint16_t TIM_FLAG) +000000 43ca MVNS r2,r1 +;;;2607 { +;;;2608 /* Check the parameters */ +;;;2609 assert_param(IS_TIM_ALL_PERIPH(TIMx)); +;;;2610 assert_param(IS_TIM_CLEAR_FLAG(TIM_FLAG)); +;;;2611 +;;;2612 /* Clear the flags */ +;;;2613 TIMx->SR = (uint16_t)~TIM_FLAG; +000002 8202 STRH r2,[r0,#0x10] +;;;2614 } +000004 4770 BX lr +;;;2615 + ENDP + + + AREA ||i.TIM_ClearITPendingBit||, CODE, READONLY, ALIGN=1 + + TIM_ClearITPendingBit PROC +;;;2681 */ +;;;2682 void TIM_ClearITPendingBit(TIM_TypeDef* TIMx, uint16_t TIM_IT) +000000 43ca MVNS r2,r1 +;;;2683 { +;;;2684 /* Check the parameters */ +;;;2685 assert_param(IS_TIM_ALL_PERIPH(TIMx)); +;;;2686 assert_param(IS_TIM_IT(TIM_IT)); +;;;2687 /* Clear the IT pending Bit */ +;;;2688 TIMx->SR = (uint16_t)~TIM_IT; +000002 8202 STRH r2,[r0,#0x10] +;;;2689 } +000004 4770 BX lr +;;;2690 + ENDP + + + AREA ||i.TIM_ClearOC1Ref||, CODE, READONLY, ALIGN=1 + + TIM_ClearOC1Ref PROC +;;;1712 */ +;;;1713 void TIM_ClearOC1Ref(TIM_TypeDef* TIMx, uint16_t TIM_OCClear) +000000 460a MOV r2,r1 +;;;1714 { +;;;1715 uint16_t tmpccmr1 = 0; +000002 2100 MOVS r1,#0 +;;;1716 /* Check the parameters */ +;;;1717 assert_param(IS_TIM_LIST3_PERIPH(TIMx)); +;;;1718 assert_param(IS_TIM_OCCLEAR_STATE(TIM_OCClear)); +;;;1719 +;;;1720 tmpccmr1 = TIMx->CCMR1; +000004 8b01 LDRH r1,[r0,#0x18] +;;;1721 +;;;1722 /* Reset the OC1CE Bit */ +;;;1723 tmpccmr1 &= (uint16_t)~((uint16_t)TIM_CCMR1_OC1CE); +000006 f64f737f MOV r3,#0xff7f +00000a 4019 ANDS r1,r1,r3 +;;;1724 /* Enable or Disable the Output Compare Clear Bit */ +;;;1725 tmpccmr1 |= TIM_OCClear; +00000c 4311 ORRS r1,r1,r2 +;;;1726 /* Write to TIMx CCMR1 register */ +;;;1727 TIMx->CCMR1 = tmpccmr1; +00000e 8301 STRH r1,[r0,#0x18] +;;;1728 } +000010 4770 BX lr +;;;1729 + ENDP + + + AREA ||i.TIM_ClearOC2Ref||, CODE, READONLY, ALIGN=1 + + TIM_ClearOC2Ref PROC +;;;1738 */ +;;;1739 void TIM_ClearOC2Ref(TIM_TypeDef* TIMx, uint16_t TIM_OCClear) +000000 460a MOV r2,r1 +;;;1740 { +;;;1741 uint16_t tmpccmr1 = 0; +000002 2100 MOVS r1,#0 +;;;1742 /* Check the parameters */ +;;;1743 assert_param(IS_TIM_LIST3_PERIPH(TIMx)); +;;;1744 assert_param(IS_TIM_OCCLEAR_STATE(TIM_OCClear)); +;;;1745 tmpccmr1 = TIMx->CCMR1; +000004 8b01 LDRH r1,[r0,#0x18] +;;;1746 /* Reset the OC2CE Bit */ +;;;1747 tmpccmr1 &= (uint16_t)~((uint16_t)TIM_CCMR1_OC2CE); +000006 f3c1010e UBFX r1,r1,#0,#15 +;;;1748 /* Enable or Disable the Output Compare Clear Bit */ +;;;1749 tmpccmr1 |= (uint16_t)(TIM_OCClear << 8); +00000a f64f73ff MOV r3,#0xffff +00000e ea032302 AND r3,r3,r2,LSL #8 +000012 4319 ORRS r1,r1,r3 +;;;1750 /* Write to TIMx CCMR1 register */ +;;;1751 TIMx->CCMR1 = tmpccmr1; +000014 8301 STRH r1,[r0,#0x18] +;;;1752 } +000016 4770 BX lr +;;;1753 + ENDP + + + AREA ||i.TIM_ClearOC3Ref||, CODE, READONLY, ALIGN=1 + + TIM_ClearOC3Ref PROC +;;;1762 */ +;;;1763 void TIM_ClearOC3Ref(TIM_TypeDef* TIMx, uint16_t TIM_OCClear) +000000 460a MOV r2,r1 +;;;1764 { +;;;1765 uint16_t tmpccmr2 = 0; +000002 2100 MOVS r1,#0 +;;;1766 /* Check the parameters */ +;;;1767 assert_param(IS_TIM_LIST3_PERIPH(TIMx)); +;;;1768 assert_param(IS_TIM_OCCLEAR_STATE(TIM_OCClear)); +;;;1769 tmpccmr2 = TIMx->CCMR2; +000004 8b81 LDRH r1,[r0,#0x1c] +;;;1770 /* Reset the OC3CE Bit */ +;;;1771 tmpccmr2 &= (uint16_t)~((uint16_t)TIM_CCMR2_OC3CE); +000006 f64f737f MOV r3,#0xff7f +00000a 4019 ANDS r1,r1,r3 +;;;1772 /* Enable or Disable the Output Compare Clear Bit */ +;;;1773 tmpccmr2 |= TIM_OCClear; +00000c 4311 ORRS r1,r1,r2 +;;;1774 /* Write to TIMx CCMR2 register */ +;;;1775 TIMx->CCMR2 = tmpccmr2; +00000e 8381 STRH r1,[r0,#0x1c] +;;;1776 } +000010 4770 BX lr +;;;1777 + ENDP + + + AREA ||i.TIM_ClearOC4Ref||, CODE, READONLY, ALIGN=1 + + TIM_ClearOC4Ref PROC +;;;1786 */ +;;;1787 void TIM_ClearOC4Ref(TIM_TypeDef* TIMx, uint16_t TIM_OCClear) +000000 460a MOV r2,r1 +;;;1788 { +;;;1789 uint16_t tmpccmr2 = 0; +000002 2100 MOVS r1,#0 +;;;1790 /* Check the parameters */ +;;;1791 assert_param(IS_TIM_LIST3_PERIPH(TIMx)); +;;;1792 assert_param(IS_TIM_OCCLEAR_STATE(TIM_OCClear)); +;;;1793 tmpccmr2 = TIMx->CCMR2; +000004 8b81 LDRH r1,[r0,#0x1c] +;;;1794 /* Reset the OC4CE Bit */ +;;;1795 tmpccmr2 &= (uint16_t)~((uint16_t)TIM_CCMR2_OC4CE); +000006 f3c1010e UBFX r1,r1,#0,#15 +;;;1796 /* Enable or Disable the Output Compare Clear Bit */ +;;;1797 tmpccmr2 |= (uint16_t)(TIM_OCClear << 8); +00000a f64f73ff MOV r3,#0xffff +00000e ea032302 AND r3,r3,r2,LSL #8 +000012 4319 ORRS r1,r1,r3 +;;;1798 /* Write to TIMx CCMR2 register */ +;;;1799 TIMx->CCMR2 = tmpccmr2; +000014 8381 STRH r1,[r0,#0x1c] +;;;1800 } +000016 4770 BX lr +;;;1801 + ENDP + + + AREA ||i.TIM_Cmd||, CODE, READONLY, ALIGN=1 + + TIM_Cmd PROC +;;;811 */ +;;;812 void TIM_Cmd(TIM_TypeDef* TIMx, FunctionalState NewState) +000000 b121 CBZ r1,|L17.12| +;;;813 { +;;;814 /* Check the parameters */ +;;;815 assert_param(IS_TIM_ALL_PERIPH(TIMx)); +;;;816 assert_param(IS_FUNCTIONAL_STATE(NewState)); +;;;817 +;;;818 if (NewState != DISABLE) +;;;819 { +;;;820 /* Enable the TIM Counter */ +;;;821 TIMx->CR1 |= TIM_CR1_CEN; +000002 8802 LDRH r2,[r0,#0] +000004 f0420201 ORR r2,r2,#1 +000008 8002 STRH r2,[r0,#0] +00000a e004 B |L17.22| + |L17.12| +;;;822 } +;;;823 else +;;;824 { +;;;825 /* Disable the TIM Counter */ +;;;826 TIMx->CR1 &= (uint16_t)(~((uint16_t)TIM_CR1_CEN)); +00000c 8802 LDRH r2,[r0,#0] +00000e f64f73fe MOV r3,#0xfffe +000012 401a ANDS r2,r2,r3 +000014 8002 STRH r2,[r0,#0] + |L17.22| +;;;827 } +;;;828 } +000016 4770 BX lr +;;;829 + ENDP + + + AREA ||i.TIM_CounterModeConfig||, CODE, READONLY, ALIGN=1 + + TIM_CounterModeConfig PROC +;;;1204 */ +;;;1205 void TIM_CounterModeConfig(TIM_TypeDef* TIMx, uint16_t TIM_CounterMode) +000000 460a MOV r2,r1 +;;;1206 { +;;;1207 uint16_t tmpcr1 = 0; +000002 2100 MOVS r1,#0 +;;;1208 /* Check the parameters */ +;;;1209 assert_param(IS_TIM_LIST3_PERIPH(TIMx)); +;;;1210 assert_param(IS_TIM_COUNTER_MODE(TIM_CounterMode)); +;;;1211 tmpcr1 = TIMx->CR1; +000004 8801 LDRH r1,[r0,#0] +;;;1212 /* Reset the CMS and DIR Bits */ +;;;1213 tmpcr1 &= (uint16_t)(~((uint16_t)(TIM_CR1_DIR | TIM_CR1_CMS))); +000006 f64f738f MOV r3,#0xff8f +00000a 4019 ANDS r1,r1,r3 +;;;1214 /* Set the Counter Mode */ +;;;1215 tmpcr1 |= TIM_CounterMode; +00000c 4311 ORRS r1,r1,r2 +;;;1216 /* Write to TIMx CR1 register */ +;;;1217 TIMx->CR1 = tmpcr1; +00000e 8001 STRH r1,[r0,#0] +;;;1218 } +000010 4770 BX lr +;;;1219 + ENDP + + + AREA ||i.TIM_CtrlPWMOutputs||, CODE, READONLY, ALIGN=1 + + TIM_CtrlPWMOutputs PROC +;;;836 */ +;;;837 void TIM_CtrlPWMOutputs(TIM_TypeDef* TIMx, FunctionalState NewState) +000000 b131 CBZ r1,|L19.16| +;;;838 { +;;;839 /* Check the parameters */ +;;;840 assert_param(IS_TIM_LIST2_PERIPH(TIMx)); +;;;841 assert_param(IS_FUNCTIONAL_STATE(NewState)); +;;;842 if (NewState != DISABLE) +;;;843 { +;;;844 /* Enable the TIM Main Output */ +;;;845 TIMx->BDTR |= TIM_BDTR_MOE; +000002 f8b02044 LDRH r2,[r0,#0x44] +000006 f4424200 ORR r2,r2,#0x8000 +00000a f8a02044 STRH r2,[r0,#0x44] +00000e e005 B |L19.28| + |L19.16| +;;;846 } +;;;847 else +;;;848 { +;;;849 /* Disable the TIM Main Output */ +;;;850 TIMx->BDTR &= (uint16_t)(~((uint16_t)TIM_BDTR_MOE)); +000010 f8b02044 LDRH r2,[r0,#0x44] +000014 f3c2020e UBFX r2,r2,#0,#15 +000018 f8a02044 STRH r2,[r0,#0x44] + |L19.28| +;;;851 } +;;;852 } +00001c 4770 BX lr +;;;853 + ENDP + + + AREA ||i.TIM_DMACmd||, CODE, READONLY, ALIGN=1 + + TIM_DMACmd PROC +;;;969 */ +;;;970 void TIM_DMACmd(TIM_TypeDef* TIMx, uint16_t TIM_DMASource, FunctionalState NewState) +000000 b11a CBZ r2,|L20.10| +;;;971 { +;;;972 /* Check the parameters */ +;;;973 assert_param(IS_TIM_LIST9_PERIPH(TIMx)); +;;;974 assert_param(IS_TIM_DMA_SOURCE(TIM_DMASource)); +;;;975 assert_param(IS_FUNCTIONAL_STATE(NewState)); +;;;976 +;;;977 if (NewState != DISABLE) +;;;978 { +;;;979 /* Enable the DMA sources */ +;;;980 TIMx->DIER |= TIM_DMASource; +000002 8983 LDRH r3,[r0,#0xc] +000004 430b ORRS r3,r3,r1 +000006 8183 STRH r3,[r0,#0xc] +000008 e002 B |L20.16| + |L20.10| +;;;981 } +;;;982 else +;;;983 { +;;;984 /* Disable the DMA sources */ +;;;985 TIMx->DIER &= (uint16_t)~TIM_DMASource; +00000a 8983 LDRH r3,[r0,#0xc] +00000c 438b BICS r3,r3,r1 +00000e 8183 STRH r3,[r0,#0xc] + |L20.16| +;;;986 } +;;;987 } +000010 4770 BX lr +;;;988 + ENDP + + + AREA ||i.TIM_DMAConfig||, CODE, READONLY, ALIGN=1 + + TIM_DMAConfig PROC +;;;942 */ +;;;943 void TIM_DMAConfig(TIM_TypeDef* TIMx, uint16_t TIM_DMABase, uint16_t TIM_DMABurstLength) +000000 ea410302 ORR r3,r1,r2 +;;;944 { +;;;945 /* Check the parameters */ +;;;946 assert_param(IS_TIM_LIST4_PERIPH(TIMx)); +;;;947 assert_param(IS_TIM_DMA_BASE(TIM_DMABase)); +;;;948 assert_param(IS_TIM_DMA_LENGTH(TIM_DMABurstLength)); +;;;949 /* Set the DMA Base and the DMA Burst Length */ +;;;950 TIMx->DCR = TIM_DMABase | TIM_DMABurstLength; +000004 f8a03048 STRH r3,[r0,#0x48] +;;;951 } +000008 4770 BX lr +;;;952 + ENDP + + + AREA ||i.TIM_DeInit||, CODE, READONLY, ALIGN=2 + + TIM_DeInit PROC +;;;127 */ +;;;128 void TIM_DeInit(TIM_TypeDef* TIMx) +000000 b510 PUSH {r4,lr} +;;;129 { +000002 4604 MOV r4,r0 +;;;130 /* Check the parameters */ +;;;131 assert_param(IS_TIM_ALL_PERIPH(TIMx)); +;;;132 +;;;133 if (TIMx == TIM1) +000004 4868 LDR r0,|L22.424| +000006 4284 CMP r4,r0 +000008 d108 BNE |L22.28| +;;;134 { +;;;135 RCC_APB2PeriphResetCmd(RCC_APB2Periph_TIM1, ENABLE); +00000a 2101 MOVS r1,#1 +00000c 14c0 ASRS r0,r0,#19 +00000e f7fffffe BL RCC_APB2PeriphResetCmd +;;;136 RCC_APB2PeriphResetCmd(RCC_APB2Periph_TIM1, DISABLE); +000012 2100 MOVS r1,#0 +000014 14e0 ASRS r0,r4,#19 +000016 f7fffffe BL RCC_APB2PeriphResetCmd +00001a e0c4 B |L22.422| + |L22.28| +;;;137 } +;;;138 else if (TIMx == TIM2) +00001c f1b44f80 CMP r4,#0x40000000 +000020 d108 BNE |L22.52| +;;;139 { +;;;140 RCC_APB1PeriphResetCmd(RCC_APB1Periph_TIM2, ENABLE); +000022 2101 MOVS r1,#1 +000024 4608 MOV r0,r1 +000026 f7fffffe BL RCC_APB1PeriphResetCmd +;;;141 RCC_APB1PeriphResetCmd(RCC_APB1Periph_TIM2, DISABLE); +00002a 2100 MOVS r1,#0 +00002c 2001 MOVS r0,#1 +00002e f7fffffe BL RCC_APB1PeriphResetCmd +000032 e0b8 B |L22.422| + |L22.52| +;;;142 } +;;;143 else if (TIMx == TIM3) +000034 485d LDR r0,|L22.428| +000036 4284 CMP r4,r0 +000038 d108 BNE |L22.76| +;;;144 { +;;;145 RCC_APB1PeriphResetCmd(RCC_APB1Periph_TIM3, ENABLE); +00003a 2101 MOVS r1,#1 +00003c 2002 MOVS r0,#2 +00003e f7fffffe BL RCC_APB1PeriphResetCmd +;;;146 RCC_APB1PeriphResetCmd(RCC_APB1Periph_TIM3, DISABLE); +000042 2100 MOVS r1,#0 +000044 2002 MOVS r0,#2 +000046 f7fffffe BL RCC_APB1PeriphResetCmd +00004a e0ac B |L22.422| + |L22.76| +;;;147 } +;;;148 else if (TIMx == TIM4) +00004c 4858 LDR r0,|L22.432| +00004e 4284 CMP r4,r0 +000050 d108 BNE |L22.100| +;;;149 { +;;;150 RCC_APB1PeriphResetCmd(RCC_APB1Periph_TIM4, ENABLE); +000052 2101 MOVS r1,#1 +000054 2004 MOVS r0,#4 +000056 f7fffffe BL RCC_APB1PeriphResetCmd +;;;151 RCC_APB1PeriphResetCmd(RCC_APB1Periph_TIM4, DISABLE); +00005a 2100 MOVS r1,#0 +00005c 2004 MOVS r0,#4 +00005e f7fffffe BL RCC_APB1PeriphResetCmd +000062 e0a0 B |L22.422| + |L22.100| +;;;152 } +;;;153 else if (TIMx == TIM5) +000064 4853 LDR r0,|L22.436| +000066 4284 CMP r4,r0 +000068 d108 BNE |L22.124| +;;;154 { +;;;155 RCC_APB1PeriphResetCmd(RCC_APB1Periph_TIM5, ENABLE); +00006a 2101 MOVS r1,#1 +00006c 2008 MOVS r0,#8 +00006e f7fffffe BL RCC_APB1PeriphResetCmd +;;;156 RCC_APB1PeriphResetCmd(RCC_APB1Periph_TIM5, DISABLE); +000072 2100 MOVS r1,#0 +000074 2008 MOVS r0,#8 +000076 f7fffffe BL RCC_APB1PeriphResetCmd +00007a e094 B |L22.422| + |L22.124| +;;;157 } +;;;158 else if (TIMx == TIM6) +00007c 484e LDR r0,|L22.440| +00007e 4284 CMP r4,r0 +000080 d108 BNE |L22.148| +;;;159 { +;;;160 RCC_APB1PeriphResetCmd(RCC_APB1Periph_TIM6, ENABLE); +000082 2101 MOVS r1,#1 +000084 2010 MOVS r0,#0x10 +000086 f7fffffe BL RCC_APB1PeriphResetCmd +;;;161 RCC_APB1PeriphResetCmd(RCC_APB1Periph_TIM6, DISABLE); +00008a 2100 MOVS r1,#0 +00008c 2010 MOVS r0,#0x10 +00008e f7fffffe BL RCC_APB1PeriphResetCmd +000092 e088 B |L22.422| + |L22.148| +;;;162 } +;;;163 else if (TIMx == TIM7) +000094 4849 LDR r0,|L22.444| +000096 4284 CMP r4,r0 +000098 d108 BNE |L22.172| +;;;164 { +;;;165 RCC_APB1PeriphResetCmd(RCC_APB1Periph_TIM7, ENABLE); +00009a 2101 MOVS r1,#1 +00009c 2020 MOVS r0,#0x20 +00009e f7fffffe BL RCC_APB1PeriphResetCmd +;;;166 RCC_APB1PeriphResetCmd(RCC_APB1Periph_TIM7, DISABLE); +0000a2 2100 MOVS r1,#0 +0000a4 2020 MOVS r0,#0x20 +0000a6 f7fffffe BL RCC_APB1PeriphResetCmd +0000aa e07c B |L22.422| + |L22.172| +;;;167 } +;;;168 else if (TIMx == TIM8) +0000ac 4844 LDR r0,|L22.448| +0000ae 4284 CMP r4,r0 +0000b0 d108 BNE |L22.196| +;;;169 { +;;;170 RCC_APB2PeriphResetCmd(RCC_APB2Periph_TIM8, ENABLE); +0000b2 2101 MOVS r1,#1 +0000b4 1440 ASRS r0,r0,#17 +0000b6 f7fffffe BL RCC_APB2PeriphResetCmd +;;;171 RCC_APB2PeriphResetCmd(RCC_APB2Periph_TIM8, DISABLE); +0000ba 2100 MOVS r1,#0 +0000bc 1460 ASRS r0,r4,#17 +0000be f7fffffe BL RCC_APB2PeriphResetCmd +0000c2 e070 B |L22.422| + |L22.196| +;;;172 } +;;;173 else if (TIMx == TIM9) +0000c4 483f LDR r0,|L22.452| +0000c6 4284 CMP r4,r0 +0000c8 d109 BNE |L22.222| +;;;174 { +;;;175 RCC_APB2PeriphResetCmd(RCC_APB2Periph_TIM9, ENABLE); +0000ca 2101 MOVS r1,#1 +0000cc 04c8 LSLS r0,r1,#19 +0000ce f7fffffe BL RCC_APB2PeriphResetCmd +;;;176 RCC_APB2PeriphResetCmd(RCC_APB2Periph_TIM9, DISABLE); +0000d2 2100 MOVS r1,#0 +0000d4 f44f2000 MOV r0,#0x80000 +0000d8 f7fffffe BL RCC_APB2PeriphResetCmd +0000dc e063 B |L22.422| + |L22.222| +;;;177 } +;;;178 else if (TIMx == TIM10) +0000de 483a LDR r0,|L22.456| +0000e0 4284 CMP r4,r0 +0000e2 d109 BNE |L22.248| +;;;179 { +;;;180 RCC_APB2PeriphResetCmd(RCC_APB2Periph_TIM10, ENABLE); +0000e4 2101 MOVS r1,#1 +0000e6 0508 LSLS r0,r1,#20 +0000e8 f7fffffe BL RCC_APB2PeriphResetCmd +;;;181 RCC_APB2PeriphResetCmd(RCC_APB2Periph_TIM10, DISABLE); +0000ec 2100 MOVS r1,#0 +0000ee f44f1080 MOV r0,#0x100000 +0000f2 f7fffffe BL RCC_APB2PeriphResetCmd +0000f6 e056 B |L22.422| + |L22.248| +;;;182 } +;;;183 else if (TIMx == TIM11) +0000f8 4834 LDR r0,|L22.460| +0000fa 4284 CMP r4,r0 +0000fc d109 BNE |L22.274| +;;;184 { +;;;185 RCC_APB2PeriphResetCmd(RCC_APB2Periph_TIM11, ENABLE); +0000fe 2101 MOVS r1,#1 +000100 0548 LSLS r0,r1,#21 +000102 f7fffffe BL RCC_APB2PeriphResetCmd +;;;186 RCC_APB2PeriphResetCmd(RCC_APB2Periph_TIM11, DISABLE); +000106 2100 MOVS r1,#0 +000108 f44f1000 MOV r0,#0x200000 +00010c f7fffffe BL RCC_APB2PeriphResetCmd +000110 e049 B |L22.422| + |L22.274| +;;;187 } +;;;188 else if (TIMx == TIM12) +000112 482f LDR r0,|L22.464| +000114 4284 CMP r4,r0 +000116 d108 BNE |L22.298| +;;;189 { +;;;190 RCC_APB1PeriphResetCmd(RCC_APB1Periph_TIM12, ENABLE); +000118 2101 MOVS r1,#1 +00011a 2040 MOVS r0,#0x40 +00011c f7fffffe BL RCC_APB1PeriphResetCmd +;;;191 RCC_APB1PeriphResetCmd(RCC_APB1Periph_TIM12, DISABLE); +000120 2100 MOVS r1,#0 +000122 2040 MOVS r0,#0x40 +000124 f7fffffe BL RCC_APB1PeriphResetCmd +000128 e03d B |L22.422| + |L22.298| +;;;192 } +;;;193 else if (TIMx == TIM13) +00012a 482a LDR r0,|L22.468| +00012c 4284 CMP r4,r0 +00012e d108 BNE |L22.322| +;;;194 { +;;;195 RCC_APB1PeriphResetCmd(RCC_APB1Periph_TIM13, ENABLE); +000130 2101 MOVS r1,#1 +000132 2080 MOVS r0,#0x80 +000134 f7fffffe BL RCC_APB1PeriphResetCmd +;;;196 RCC_APB1PeriphResetCmd(RCC_APB1Periph_TIM13, DISABLE); +000138 2100 MOVS r1,#0 +00013a 2080 MOVS r0,#0x80 +00013c f7fffffe BL RCC_APB1PeriphResetCmd +000140 e031 B |L22.422| + |L22.322| +;;;197 } +;;;198 else if (TIMx == TIM14) +000142 4825 LDR r0,|L22.472| +000144 4284 CMP r4,r0 +000146 d108 BNE |L22.346| +;;;199 { +;;;200 RCC_APB1PeriphResetCmd(RCC_APB1Periph_TIM14, ENABLE); +000148 2101 MOVS r1,#1 +00014a 1580 ASRS r0,r0,#22 +00014c f7fffffe BL RCC_APB1PeriphResetCmd +;;;201 RCC_APB1PeriphResetCmd(RCC_APB1Periph_TIM14, DISABLE); +000150 2100 MOVS r1,#0 +000152 15a0 ASRS r0,r4,#22 +000154 f7fffffe BL RCC_APB1PeriphResetCmd +000158 e025 B |L22.422| + |L22.346| +;;;202 } +;;;203 else if (TIMx == TIM15) +00015a 4820 LDR r0,|L22.476| +00015c 4284 CMP r4,r0 +00015e d109 BNE |L22.372| +;;;204 { +;;;205 RCC_APB2PeriphResetCmd(RCC_APB2Periph_TIM15, ENABLE); +000160 2101 MOVS r1,#1 +000162 0408 LSLS r0,r1,#16 +000164 f7fffffe BL RCC_APB2PeriphResetCmd +;;;206 RCC_APB2PeriphResetCmd(RCC_APB2Periph_TIM15, DISABLE); +000168 2100 MOVS r1,#0 +00016a f44f3080 MOV r0,#0x10000 +00016e f7fffffe BL RCC_APB2PeriphResetCmd +000172 e018 B |L22.422| + |L22.372| +;;;207 } +;;;208 else if (TIMx == TIM16) +000174 481a LDR r0,|L22.480| +000176 4284 CMP r4,r0 +000178 d109 BNE |L22.398| +;;;209 { +;;;210 RCC_APB2PeriphResetCmd(RCC_APB2Periph_TIM16, ENABLE); +00017a 2101 MOVS r1,#1 +00017c 0448 LSLS r0,r1,#17 +00017e f7fffffe BL RCC_APB2PeriphResetCmd +;;;211 RCC_APB2PeriphResetCmd(RCC_APB2Periph_TIM16, DISABLE); +000182 2100 MOVS r1,#0 +000184 f44f3000 MOV r0,#0x20000 +000188 f7fffffe BL RCC_APB2PeriphResetCmd +00018c e00b B |L22.422| + |L22.398| +;;;212 } +;;;213 else +;;;214 { +;;;215 if (TIMx == TIM17) +00018e 4815 LDR r0,|L22.484| +000190 4284 CMP r4,r0 +000192 d108 BNE |L22.422| +;;;216 { +;;;217 RCC_APB2PeriphResetCmd(RCC_APB2Periph_TIM17, ENABLE); +000194 2101 MOVS r1,#1 +000196 0488 LSLS r0,r1,#18 +000198 f7fffffe BL RCC_APB2PeriphResetCmd +;;;218 RCC_APB2PeriphResetCmd(RCC_APB2Periph_TIM17, DISABLE); +00019c 2100 MOVS r1,#0 +00019e f44f2080 MOV r0,#0x40000 +0001a2 f7fffffe BL RCC_APB2PeriphResetCmd + |L22.422| +;;;219 } +;;;220 } +;;;221 } +0001a6 bd10 POP {r4,pc} +;;;222 + ENDP + + |L22.424| + DCD 0x40012c00 + |L22.428| + DCD 0x40000400 + |L22.432| + DCD 0x40000800 + |L22.436| + DCD 0x40000c00 + |L22.440| + DCD 0x40001000 + |L22.444| + DCD 0x40001400 + |L22.448| + DCD 0x40013400 + |L22.452| + DCD 0x40014c00 + |L22.456| + DCD 0x40015000 + |L22.460| + DCD 0x40015400 + |L22.464| + DCD 0x40001800 + |L22.468| + DCD 0x40001c00 + |L22.472| + DCD 0x40002000 + |L22.476| + DCD 0x40014000 + |L22.480| + DCD 0x40014400 + |L22.484| + DCD 0x40014800 + + AREA ||i.TIM_ETRClockMode1Config||, CODE, READONLY, ALIGN=1 + + TIM_ETRClockMode1Config PROC +;;;1080 */ +;;;1081 void TIM_ETRClockMode1Config(TIM_TypeDef* TIMx, uint16_t TIM_ExtTRGPrescaler, uint16_t TIM_ExtTRGPolarity, +000000 e92d41f0 PUSH {r4-r8,lr} +;;;1082 uint16_t ExtTRGFilter) +;;;1083 { +000004 4605 MOV r5,r0 +000006 460e MOV r6,r1 +000008 4617 MOV r7,r2 +00000a 4698 MOV r8,r3 +;;;1084 uint16_t tmpsmcr = 0; +00000c 2400 MOVS r4,#0 +;;;1085 /* Check the parameters */ +;;;1086 assert_param(IS_TIM_LIST3_PERIPH(TIMx)); +;;;1087 assert_param(IS_TIM_EXT_PRESCALER(TIM_ExtTRGPrescaler)); +;;;1088 assert_param(IS_TIM_EXT_POLARITY(TIM_ExtTRGPolarity)); +;;;1089 assert_param(IS_TIM_EXT_FILTER(ExtTRGFilter)); +;;;1090 /* Configure the ETR Clock source */ +;;;1091 TIM_ETRConfig(TIMx, TIM_ExtTRGPrescaler, TIM_ExtTRGPolarity, ExtTRGFilter); +00000e 4643 MOV r3,r8 +000010 463a MOV r2,r7 +000012 4631 MOV r1,r6 +000014 4628 MOV r0,r5 +000016 f7fffffe BL TIM_ETRConfig +;;;1092 +;;;1093 /* Get the TIMx SMCR register value */ +;;;1094 tmpsmcr = TIMx->SMCR; +00001a 892c LDRH r4,[r5,#8] +;;;1095 /* Reset the SMS Bits */ +;;;1096 tmpsmcr &= (uint16_t)(~((uint16_t)TIM_SMCR_SMS)); +00001c f64f70f8 MOV r0,#0xfff8 +000020 4004 ANDS r4,r4,r0 +;;;1097 /* Select the External clock mode1 */ +;;;1098 tmpsmcr |= TIM_SlaveMode_External1; +000022 f0440407 ORR r4,r4,#7 +;;;1099 /* Select the Trigger selection : ETRF */ +;;;1100 tmpsmcr &= (uint16_t)(~((uint16_t)TIM_SMCR_TS)); +000026 f64f708f MOV r0,#0xff8f +00002a 4004 ANDS r4,r4,r0 +;;;1101 tmpsmcr |= TIM_TS_ETRF; +00002c f0440470 ORR r4,r4,#0x70 +;;;1102 /* Write to TIMx SMCR */ +;;;1103 TIMx->SMCR = tmpsmcr; +000030 812c STRH r4,[r5,#8] +;;;1104 } +000032 e8bd81f0 POP {r4-r8,pc} +;;;1105 + ENDP + + + AREA ||i.TIM_ETRClockMode2Config||, CODE, READONLY, ALIGN=1 + + TIM_ETRClockMode2Config PROC +;;;1122 */ +;;;1123 void TIM_ETRClockMode2Config(TIM_TypeDef* TIMx, uint16_t TIM_ExtTRGPrescaler, +000000 b5f0 PUSH {r4-r7,lr} +;;;1124 uint16_t TIM_ExtTRGPolarity, uint16_t ExtTRGFilter) +;;;1125 { +000002 4604 MOV r4,r0 +000004 460d MOV r5,r1 +000006 4616 MOV r6,r2 +000008 461f MOV r7,r3 +;;;1126 /* Check the parameters */ +;;;1127 assert_param(IS_TIM_LIST3_PERIPH(TIMx)); +;;;1128 assert_param(IS_TIM_EXT_PRESCALER(TIM_ExtTRGPrescaler)); +;;;1129 assert_param(IS_TIM_EXT_POLARITY(TIM_ExtTRGPolarity)); +;;;1130 assert_param(IS_TIM_EXT_FILTER(ExtTRGFilter)); +;;;1131 /* Configure the ETR Clock source */ +;;;1132 TIM_ETRConfig(TIMx, TIM_ExtTRGPrescaler, TIM_ExtTRGPolarity, ExtTRGFilter); +00000a 463b MOV r3,r7 +00000c 4632 MOV r2,r6 +00000e 4629 MOV r1,r5 +000010 4620 MOV r0,r4 +000012 f7fffffe BL TIM_ETRConfig +;;;1133 /* Enable the External clock mode2 */ +;;;1134 TIMx->SMCR |= TIM_SMCR_ECE; +000016 8920 LDRH r0,[r4,#8] +000018 f4404080 ORR r0,r0,#0x4000 +00001c 8120 STRH r0,[r4,#8] +;;;1135 } +00001e bdf0 POP {r4-r7,pc} +;;;1136 + ENDP + + + AREA ||i.TIM_ETRConfig||, CODE, READONLY, ALIGN=1 + + TIM_ETRConfig PROC +;;;1153 */ +;;;1154 void TIM_ETRConfig(TIM_TypeDef* TIMx, uint16_t TIM_ExtTRGPrescaler, uint16_t TIM_ExtTRGPolarity, +000000 b530 PUSH {r4,r5,lr} +;;;1155 uint16_t ExtTRGFilter) +;;;1156 { +000002 460c MOV r4,r1 +;;;1157 uint16_t tmpsmcr = 0; +000004 2100 MOVS r1,#0 +;;;1158 /* Check the parameters */ +;;;1159 assert_param(IS_TIM_LIST3_PERIPH(TIMx)); +;;;1160 assert_param(IS_TIM_EXT_PRESCALER(TIM_ExtTRGPrescaler)); +;;;1161 assert_param(IS_TIM_EXT_POLARITY(TIM_ExtTRGPolarity)); +;;;1162 assert_param(IS_TIM_EXT_FILTER(ExtTRGFilter)); +;;;1163 tmpsmcr = TIMx->SMCR; +000006 8901 LDRH r1,[r0,#8] +;;;1164 /* Reset the ETR Bits */ +;;;1165 tmpsmcr &= SMCR_ETR_Mask; +000008 b2c9 UXTB r1,r1 +;;;1166 /* Set the Prescaler, the Filter value and the Polarity */ +;;;1167 tmpsmcr |= (uint16_t)(TIM_ExtTRGPrescaler | (uint16_t)(TIM_ExtTRGPolarity | (uint16_t)(ExtTRGFilter << (uint16_t)8))); +00000a f64f75ff MOV r5,#0xffff +00000e ea052503 AND r5,r5,r3,LSL #8 +000012 4315 ORRS r5,r5,r2 +000014 4325 ORRS r5,r5,r4 +000016 4329 ORRS r1,r1,r5 +;;;1168 /* Write to TIMx SMCR */ +;;;1169 TIMx->SMCR = tmpsmcr; +000018 8101 STRH r1,[r0,#8] +;;;1170 } +00001a bd30 POP {r4,r5,pc} +;;;1171 + ENDP + + + AREA ||i.TIM_EncoderInterfaceConfig||, CODE, READONLY, ALIGN=1 + + TIM_EncoderInterfaceConfig PROC +;;;1269 */ +;;;1270 void TIM_EncoderInterfaceConfig(TIM_TypeDef* TIMx, uint16_t TIM_EncoderMode, +000000 b5f0 PUSH {r4-r7,lr} +;;;1271 uint16_t TIM_IC1Polarity, uint16_t TIM_IC2Polarity) +;;;1272 { +000002 460c MOV r4,r1 +000004 4615 MOV r5,r2 +000006 461e MOV r6,r3 +;;;1273 uint16_t tmpsmcr = 0; +000008 2100 MOVS r1,#0 +;;;1274 uint16_t tmpccmr1 = 0; +00000a 2200 MOVS r2,#0 +;;;1275 uint16_t tmpccer = 0; +00000c 2300 MOVS r3,#0 +;;;1276 +;;;1277 /* Check the parameters */ +;;;1278 assert_param(IS_TIM_LIST5_PERIPH(TIMx)); +;;;1279 assert_param(IS_TIM_ENCODER_MODE(TIM_EncoderMode)); +;;;1280 assert_param(IS_TIM_IC_POLARITY(TIM_IC1Polarity)); +;;;1281 assert_param(IS_TIM_IC_POLARITY(TIM_IC2Polarity)); +;;;1282 +;;;1283 /* Get the TIMx SMCR register value */ +;;;1284 tmpsmcr = TIMx->SMCR; +00000e 8901 LDRH r1,[r0,#8] +;;;1285 +;;;1286 /* Get the TIMx CCMR1 register value */ +;;;1287 tmpccmr1 = TIMx->CCMR1; +000010 8b02 LDRH r2,[r0,#0x18] +;;;1288 +;;;1289 /* Get the TIMx CCER register value */ +;;;1290 tmpccer = TIMx->CCER; +000012 8c03 LDRH r3,[r0,#0x20] +;;;1291 +;;;1292 /* Set the encoder Mode */ +;;;1293 tmpsmcr &= (uint16_t)(~((uint16_t)TIM_SMCR_SMS)); +000014 f64f77f8 MOV r7,#0xfff8 +000018 4039 ANDS r1,r1,r7 +;;;1294 tmpsmcr |= TIM_EncoderMode; +00001a 4321 ORRS r1,r1,r4 +;;;1295 +;;;1296 /* Select the Capture Compare 1 and the Capture Compare 2 as input */ +;;;1297 tmpccmr1 &= (uint16_t)(((uint16_t)~((uint16_t)TIM_CCMR1_CC1S)) & (uint16_t)(~((uint16_t)TIM_CCMR1_CC2S))); +00001c f64f47fc MOV r7,#0xfcfc +000020 403a ANDS r2,r2,r7 +;;;1298 tmpccmr1 |= TIM_CCMR1_CC1S_0 | TIM_CCMR1_CC2S_0; +000022 f2401701 MOV r7,#0x101 +000026 433a ORRS r2,r2,r7 +;;;1299 +;;;1300 /* Set the TI1 and the TI2 Polarities */ +;;;1301 tmpccer &= (uint16_t)(((uint16_t)~((uint16_t)TIM_CCER_CC1P)) & ((uint16_t)~((uint16_t)TIM_CCER_CC2P))); +000028 f64f77dd MOV r7,#0xffdd +00002c 403b ANDS r3,r3,r7 +;;;1302 tmpccer |= (uint16_t)(TIM_IC1Polarity | (uint16_t)(TIM_IC2Polarity << (uint16_t)4)); +00002e f64f77ff MOV r7,#0xffff +000032 ea071706 AND r7,r7,r6,LSL #4 +000036 432f ORRS r7,r7,r5 +000038 433b ORRS r3,r3,r7 +;;;1303 +;;;1304 /* Write to TIMx SMCR */ +;;;1305 TIMx->SMCR = tmpsmcr; +00003a 8101 STRH r1,[r0,#8] +;;;1306 /* Write to TIMx CCMR1 */ +;;;1307 TIMx->CCMR1 = tmpccmr1; +00003c 8302 STRH r2,[r0,#0x18] +;;;1308 /* Write to TIMx CCER */ +;;;1309 TIMx->CCER = tmpccer; +00003e 8403 STRH r3,[r0,#0x20] +;;;1310 } +000040 bdf0 POP {r4-r7,pc} +;;;1311 + ENDP + + + AREA ||i.TIM_ForcedOC1Config||, CODE, READONLY, ALIGN=1 + + TIM_ForcedOC1Config PROC +;;;1320 */ +;;;1321 void TIM_ForcedOC1Config(TIM_TypeDef* TIMx, uint16_t TIM_ForcedAction) +000000 460a MOV r2,r1 +;;;1322 { +;;;1323 uint16_t tmpccmr1 = 0; +000002 2100 MOVS r1,#0 +;;;1324 /* Check the parameters */ +;;;1325 assert_param(IS_TIM_LIST8_PERIPH(TIMx)); +;;;1326 assert_param(IS_TIM_FORCED_ACTION(TIM_ForcedAction)); +;;;1327 tmpccmr1 = TIMx->CCMR1; +000004 8b01 LDRH r1,[r0,#0x18] +;;;1328 /* Reset the OC1M Bits */ +;;;1329 tmpccmr1 &= (uint16_t)~((uint16_t)TIM_CCMR1_OC1M); +000006 f64f738f MOV r3,#0xff8f +00000a 4019 ANDS r1,r1,r3 +;;;1330 /* Configure The Forced output Mode */ +;;;1331 tmpccmr1 |= TIM_ForcedAction; +00000c 4311 ORRS r1,r1,r2 +;;;1332 /* Write to TIMx CCMR1 register */ +;;;1333 TIMx->CCMR1 = tmpccmr1; +00000e 8301 STRH r1,[r0,#0x18] +;;;1334 } +000010 4770 BX lr +;;;1335 + ENDP + + + AREA ||i.TIM_ForcedOC2Config||, CODE, READONLY, ALIGN=1 + + TIM_ForcedOC2Config PROC +;;;1344 */ +;;;1345 void TIM_ForcedOC2Config(TIM_TypeDef* TIMx, uint16_t TIM_ForcedAction) +000000 460a MOV r2,r1 +;;;1346 { +;;;1347 uint16_t tmpccmr1 = 0; +000002 2100 MOVS r1,#0 +;;;1348 /* Check the parameters */ +;;;1349 assert_param(IS_TIM_LIST6_PERIPH(TIMx)); +;;;1350 assert_param(IS_TIM_FORCED_ACTION(TIM_ForcedAction)); +;;;1351 tmpccmr1 = TIMx->CCMR1; +000004 8b01 LDRH r1,[r0,#0x18] +;;;1352 /* Reset the OC2M Bits */ +;;;1353 tmpccmr1 &= (uint16_t)~((uint16_t)TIM_CCMR1_OC2M); +000006 f64873ff MOV r3,#0x8fff +00000a 4019 ANDS r1,r1,r3 +;;;1354 /* Configure The Forced output Mode */ +;;;1355 tmpccmr1 |= (uint16_t)(TIM_ForcedAction << 8); +00000c f64f73ff MOV r3,#0xffff +000010 ea032302 AND r3,r3,r2,LSL #8 +000014 4319 ORRS r1,r1,r3 +;;;1356 /* Write to TIMx CCMR1 register */ +;;;1357 TIMx->CCMR1 = tmpccmr1; +000016 8301 STRH r1,[r0,#0x18] +;;;1358 } +000018 4770 BX lr +;;;1359 + ENDP + + + AREA ||i.TIM_ForcedOC3Config||, CODE, READONLY, ALIGN=1 + + TIM_ForcedOC3Config PROC +;;;1368 */ +;;;1369 void TIM_ForcedOC3Config(TIM_TypeDef* TIMx, uint16_t TIM_ForcedAction) +000000 460a MOV r2,r1 +;;;1370 { +;;;1371 uint16_t tmpccmr2 = 0; +000002 2100 MOVS r1,#0 +;;;1372 /* Check the parameters */ +;;;1373 assert_param(IS_TIM_LIST3_PERIPH(TIMx)); +;;;1374 assert_param(IS_TIM_FORCED_ACTION(TIM_ForcedAction)); +;;;1375 tmpccmr2 = TIMx->CCMR2; +000004 8b81 LDRH r1,[r0,#0x1c] +;;;1376 /* Reset the OC1M Bits */ +;;;1377 tmpccmr2 &= (uint16_t)~((uint16_t)TIM_CCMR2_OC3M); +000006 f64f738f MOV r3,#0xff8f +00000a 4019 ANDS r1,r1,r3 +;;;1378 /* Configure The Forced output Mode */ +;;;1379 tmpccmr2 |= TIM_ForcedAction; +00000c 4311 ORRS r1,r1,r2 +;;;1380 /* Write to TIMx CCMR2 register */ +;;;1381 TIMx->CCMR2 = tmpccmr2; +00000e 8381 STRH r1,[r0,#0x1c] +;;;1382 } +000010 4770 BX lr +;;;1383 + ENDP + + + AREA ||i.TIM_ForcedOC4Config||, CODE, READONLY, ALIGN=1 + + TIM_ForcedOC4Config PROC +;;;1392 */ +;;;1393 void TIM_ForcedOC4Config(TIM_TypeDef* TIMx, uint16_t TIM_ForcedAction) +000000 460a MOV r2,r1 +;;;1394 { +;;;1395 uint16_t tmpccmr2 = 0; +000002 2100 MOVS r1,#0 +;;;1396 /* Check the parameters */ +;;;1397 assert_param(IS_TIM_LIST3_PERIPH(TIMx)); +;;;1398 assert_param(IS_TIM_FORCED_ACTION(TIM_ForcedAction)); +;;;1399 tmpccmr2 = TIMx->CCMR2; +000004 8b81 LDRH r1,[r0,#0x1c] +;;;1400 /* Reset the OC2M Bits */ +;;;1401 tmpccmr2 &= (uint16_t)~((uint16_t)TIM_CCMR2_OC4M); +000006 f64873ff MOV r3,#0x8fff +00000a 4019 ANDS r1,r1,r3 +;;;1402 /* Configure The Forced output Mode */ +;;;1403 tmpccmr2 |= (uint16_t)(TIM_ForcedAction << 8); +00000c f64f73ff MOV r3,#0xffff +000010 ea032302 AND r3,r3,r2,LSL #8 +000014 4319 ORRS r1,r1,r3 +;;;1404 /* Write to TIMx CCMR2 register */ +;;;1405 TIMx->CCMR2 = tmpccmr2; +000016 8381 STRH r1,[r0,#0x1c] +;;;1406 } +000018 4770 BX lr +;;;1407 + ENDP + + + AREA ||i.TIM_GenerateEvent||, CODE, READONLY, ALIGN=1 + + TIM_GenerateEvent PROC +;;;914 */ +;;;915 void TIM_GenerateEvent(TIM_TypeDef* TIMx, uint16_t TIM_EventSource) +000000 8281 STRH r1,[r0,#0x14] +;;;916 { +;;;917 /* Check the parameters */ +;;;918 assert_param(IS_TIM_ALL_PERIPH(TIMx)); +;;;919 assert_param(IS_TIM_EVENT_SOURCE(TIM_EventSource)); +;;;920 +;;;921 /* Set the event sources */ +;;;922 TIMx->EGR = TIM_EventSource; +;;;923 } +000002 4770 BX lr +;;;924 + ENDP + + + AREA ||i.TIM_GetCapture1||, CODE, READONLY, ALIGN=1 + + TIM_GetCapture1 PROC +;;;2462 */ +;;;2463 uint16_t TIM_GetCapture1(TIM_TypeDef* TIMx) +000000 4601 MOV r1,r0 +;;;2464 { +;;;2465 /* Check the parameters */ +;;;2466 assert_param(IS_TIM_LIST8_PERIPH(TIMx)); +;;;2467 /* Get the Capture 1 Register value */ +;;;2468 return TIMx->CCR1; +000002 8e88 LDRH r0,[r1,#0x34] +;;;2469 } +000004 4770 BX lr +;;;2470 + ENDP + + + AREA ||i.TIM_GetCapture2||, CODE, READONLY, ALIGN=1 + + TIM_GetCapture2 PROC +;;;2475 */ +;;;2476 uint16_t TIM_GetCapture2(TIM_TypeDef* TIMx) +000000 4601 MOV r1,r0 +;;;2477 { +;;;2478 /* Check the parameters */ +;;;2479 assert_param(IS_TIM_LIST6_PERIPH(TIMx)); +;;;2480 /* Get the Capture 2 Register value */ +;;;2481 return TIMx->CCR2; +000002 8f08 LDRH r0,[r1,#0x38] +;;;2482 } +000004 4770 BX lr +;;;2483 + ENDP + + + AREA ||i.TIM_GetCapture3||, CODE, READONLY, ALIGN=1 + + TIM_GetCapture3 PROC +;;;2488 */ +;;;2489 uint16_t TIM_GetCapture3(TIM_TypeDef* TIMx) +000000 4601 MOV r1,r0 +;;;2490 { +;;;2491 /* Check the parameters */ +;;;2492 assert_param(IS_TIM_LIST3_PERIPH(TIMx)); +;;;2493 /* Get the Capture 3 Register value */ +;;;2494 return TIMx->CCR3; +000002 8f88 LDRH r0,[r1,#0x3c] +;;;2495 } +000004 4770 BX lr +;;;2496 + ENDP + + + AREA ||i.TIM_GetCapture4||, CODE, READONLY, ALIGN=1 + + TIM_GetCapture4 PROC +;;;2501 */ +;;;2502 uint16_t TIM_GetCapture4(TIM_TypeDef* TIMx) +000000 4601 MOV r1,r0 +;;;2503 { +;;;2504 /* Check the parameters */ +;;;2505 assert_param(IS_TIM_LIST3_PERIPH(TIMx)); +;;;2506 /* Get the Capture 4 Register value */ +;;;2507 return TIMx->CCR4; +000002 f8b10040 LDRH r0,[r1,#0x40] +;;;2508 } +000006 4770 BX lr +;;;2509 + ENDP + + + AREA ||i.TIM_GetCounter||, CODE, READONLY, ALIGN=1 + + TIM_GetCounter PROC +;;;2514 */ +;;;2515 uint16_t TIM_GetCounter(TIM_TypeDef* TIMx) +000000 4601 MOV r1,r0 +;;;2516 { +;;;2517 /* Check the parameters */ +;;;2518 assert_param(IS_TIM_ALL_PERIPH(TIMx)); +;;;2519 /* Get the Counter Register value */ +;;;2520 return TIMx->CNT; +000002 8c88 LDRH r0,[r1,#0x24] +;;;2521 } +000004 4770 BX lr +;;;2522 + ENDP + + + AREA ||i.TIM_GetFlagStatus||, CODE, READONLY, ALIGN=1 + + TIM_GetFlagStatus PROC +;;;2561 */ +;;;2562 FlagStatus TIM_GetFlagStatus(TIM_TypeDef* TIMx, uint16_t TIM_FLAG) +000000 4602 MOV r2,r0 +;;;2563 { +;;;2564 ITStatus bitstatus = RESET; +000002 2000 MOVS r0,#0 +;;;2565 /* Check the parameters */ +;;;2566 assert_param(IS_TIM_ALL_PERIPH(TIMx)); +;;;2567 assert_param(IS_TIM_GET_FLAG(TIM_FLAG)); +;;;2568 +;;;2569 if ((TIMx->SR & TIM_FLAG) != (uint16_t)RESET) +000004 8a13 LDRH r3,[r2,#0x10] +000006 400b ANDS r3,r3,r1 +000008 b10b CBZ r3,|L37.14| +;;;2570 { +;;;2571 bitstatus = SET; +00000a 2001 MOVS r0,#1 +00000c e000 B |L37.16| + |L37.14| +;;;2572 } +;;;2573 else +;;;2574 { +;;;2575 bitstatus = RESET; +00000e 2000 MOVS r0,#0 + |L37.16| +;;;2576 } +;;;2577 return bitstatus; +;;;2578 } +000010 4770 BX lr +;;;2579 + ENDP + + + AREA ||i.TIM_GetITStatus||, CODE, READONLY, ALIGN=1 + + TIM_GetITStatus PROC +;;;2637 */ +;;;2638 ITStatus TIM_GetITStatus(TIM_TypeDef* TIMx, uint16_t TIM_IT) +000000 b530 PUSH {r4,r5,lr} +;;;2639 { +000002 4602 MOV r2,r0 +;;;2640 ITStatus bitstatus = RESET; +000004 2000 MOVS r0,#0 +;;;2641 uint16_t itstatus = 0x0, itenable = 0x0; +000006 2300 MOVS r3,#0 +000008 2400 MOVS r4,#0 +;;;2642 /* Check the parameters */ +;;;2643 assert_param(IS_TIM_ALL_PERIPH(TIMx)); +;;;2644 assert_param(IS_TIM_GET_IT(TIM_IT)); +;;;2645 +;;;2646 itstatus = TIMx->SR & TIM_IT; +00000a 8a15 LDRH r5,[r2,#0x10] +00000c ea050301 AND r3,r5,r1 +;;;2647 +;;;2648 itenable = TIMx->DIER & TIM_IT; +000010 8995 LDRH r5,[r2,#0xc] +000012 ea050401 AND r4,r5,r1 +;;;2649 if ((itstatus != (uint16_t)RESET) && (itenable != (uint16_t)RESET)) +000016 b113 CBZ r3,|L38.30| +000018 b10c CBZ r4,|L38.30| +;;;2650 { +;;;2651 bitstatus = SET; +00001a 2001 MOVS r0,#1 +00001c e000 B |L38.32| + |L38.30| +;;;2652 } +;;;2653 else +;;;2654 { +;;;2655 bitstatus = RESET; +00001e 2000 MOVS r0,#0 + |L38.32| +;;;2656 } +;;;2657 return bitstatus; +;;;2658 } +000020 bd30 POP {r4,r5,pc} +;;;2659 + ENDP + + + AREA ||i.TIM_GetPrescaler||, CODE, READONLY, ALIGN=1 + + TIM_GetPrescaler PROC +;;;2527 */ +;;;2528 uint16_t TIM_GetPrescaler(TIM_TypeDef* TIMx) +000000 4601 MOV r1,r0 +;;;2529 { +;;;2530 /* Check the parameters */ +;;;2531 assert_param(IS_TIM_ALL_PERIPH(TIMx)); +;;;2532 /* Get the Prescaler Register value */ +;;;2533 return TIMx->PSC; +000002 8d08 LDRH r0,[r1,#0x28] +;;;2534 } +000004 4770 BX lr +;;;2535 + ENDP + + + AREA ||i.TIM_ICInit||, CODE, READONLY, ALIGN=2 + + TIM_ICInit PROC +;;;592 */ +;;;593 void TIM_ICInit(TIM_TypeDef* TIMx, TIM_ICInitTypeDef* TIM_ICInitStruct) +000000 b570 PUSH {r4-r6,lr} +;;;594 { +000002 4605 MOV r5,r0 +000004 460c MOV r4,r1 +;;;595 /* Check the parameters */ +;;;596 assert_param(IS_TIM_CHANNEL(TIM_ICInitStruct->TIM_Channel)); +;;;597 assert_param(IS_TIM_IC_SELECTION(TIM_ICInitStruct->TIM_ICSelection)); +;;;598 assert_param(IS_TIM_IC_PRESCALER(TIM_ICInitStruct->TIM_ICPrescaler)); +;;;599 assert_param(IS_TIM_IC_FILTER(TIM_ICInitStruct->TIM_ICFilter)); +;;;600 +;;;601 if((TIMx == TIM1) || (TIMx == TIM8) || (TIMx == TIM2) || (TIMx == TIM3) || +000006 4824 LDR r0,|L40.152| +000008 4285 CMP r5,r0 +00000a d00e BEQ |L40.42| +00000c 4823 LDR r0,|L40.156| +00000e 4285 CMP r5,r0 +000010 d00b BEQ |L40.42| +000012 f1b54f80 CMP r5,#0x40000000 +000016 d008 BEQ |L40.42| +000018 4821 LDR r0,|L40.160| +00001a 4285 CMP r5,r0 +00001c d005 BEQ |L40.42| +;;;602 (TIMx == TIM4) ||(TIMx == TIM5)) +00001e 4821 LDR r0,|L40.164| +000020 4285 CMP r5,r0 +000022 d002 BEQ |L40.42| +000024 4820 LDR r0,|L40.168| +000026 4285 CMP r5,r0 +000028 d100 BNE |L40.44| + |L40.42| +;;;603 { +;;;604 assert_param(IS_TIM_IC_POLARITY(TIM_ICInitStruct->TIM_ICPolarity)); +00002a e000 B |L40.46| + |L40.44| +;;;605 } +;;;606 else +;;;607 { +;;;608 assert_param(IS_TIM_IC_POLARITY_LITE(TIM_ICInitStruct->TIM_ICPolarity)); +00002c bf00 NOP + |L40.46| +;;;609 } +;;;610 if (TIM_ICInitStruct->TIM_Channel == TIM_Channel_1) +00002e 8820 LDRH r0,[r4,#0] +000030 b950 CBNZ r0,|L40.72| +;;;611 { +;;;612 assert_param(IS_TIM_LIST8_PERIPH(TIMx)); +;;;613 /* TI1 Configuration */ +;;;614 TI1_Config(TIMx, TIM_ICInitStruct->TIM_ICPolarity, +000032 8923 LDRH r3,[r4,#8] +000034 88a2 LDRH r2,[r4,#4] +000036 8861 LDRH r1,[r4,#2] +000038 4628 MOV r0,r5 +00003a f7fffffe BL TI1_Config +;;;615 TIM_ICInitStruct->TIM_ICSelection, +;;;616 TIM_ICInitStruct->TIM_ICFilter); +;;;617 /* Set the Input Capture Prescaler value */ +;;;618 TIM_SetIC1Prescaler(TIMx, TIM_ICInitStruct->TIM_ICPrescaler); +00003e 88e1 LDRH r1,[r4,#6] +000040 4628 MOV r0,r5 +000042 f7fffffe BL TIM_SetIC1Prescaler +000046 e025 B |L40.148| + |L40.72| +;;;619 } +;;;620 else if (TIM_ICInitStruct->TIM_Channel == TIM_Channel_2) +000048 8820 LDRH r0,[r4,#0] +00004a 2804 CMP r0,#4 +00004c d10a BNE |L40.100| +;;;621 { +;;;622 assert_param(IS_TIM_LIST6_PERIPH(TIMx)); +;;;623 /* TI2 Configuration */ +;;;624 TI2_Config(TIMx, TIM_ICInitStruct->TIM_ICPolarity, +00004e 8923 LDRH r3,[r4,#8] +000050 88a2 LDRH r2,[r4,#4] +000052 8861 LDRH r1,[r4,#2] +000054 4628 MOV r0,r5 +000056 f7fffffe BL TI2_Config +;;;625 TIM_ICInitStruct->TIM_ICSelection, +;;;626 TIM_ICInitStruct->TIM_ICFilter); +;;;627 /* Set the Input Capture Prescaler value */ +;;;628 TIM_SetIC2Prescaler(TIMx, TIM_ICInitStruct->TIM_ICPrescaler); +00005a 88e1 LDRH r1,[r4,#6] +00005c 4628 MOV r0,r5 +00005e f7fffffe BL TIM_SetIC2Prescaler +000062 e017 B |L40.148| + |L40.100| +;;;629 } +;;;630 else if (TIM_ICInitStruct->TIM_Channel == TIM_Channel_3) +000064 8820 LDRH r0,[r4,#0] +000066 2808 CMP r0,#8 +000068 d10a BNE |L40.128| +;;;631 { +;;;632 assert_param(IS_TIM_LIST3_PERIPH(TIMx)); +;;;633 /* TI3 Configuration */ +;;;634 TI3_Config(TIMx, TIM_ICInitStruct->TIM_ICPolarity, +00006a 8923 LDRH r3,[r4,#8] +00006c 88a2 LDRH r2,[r4,#4] +00006e 8861 LDRH r1,[r4,#2] +000070 4628 MOV r0,r5 +000072 f7fffffe BL TI3_Config +;;;635 TIM_ICInitStruct->TIM_ICSelection, +;;;636 TIM_ICInitStruct->TIM_ICFilter); +;;;637 /* Set the Input Capture Prescaler value */ +;;;638 TIM_SetIC3Prescaler(TIMx, TIM_ICInitStruct->TIM_ICPrescaler); +000076 88e1 LDRH r1,[r4,#6] +000078 4628 MOV r0,r5 +00007a f7fffffe BL TIM_SetIC3Prescaler +00007e e009 B |L40.148| + |L40.128| +;;;639 } +;;;640 else +;;;641 { +;;;642 assert_param(IS_TIM_LIST3_PERIPH(TIMx)); +;;;643 /* TI4 Configuration */ +;;;644 TI4_Config(TIMx, TIM_ICInitStruct->TIM_ICPolarity, +000080 8923 LDRH r3,[r4,#8] +000082 88a2 LDRH r2,[r4,#4] +000084 8861 LDRH r1,[r4,#2] +000086 4628 MOV r0,r5 +000088 f7fffffe BL TI4_Config +;;;645 TIM_ICInitStruct->TIM_ICSelection, +;;;646 TIM_ICInitStruct->TIM_ICFilter); +;;;647 /* Set the Input Capture Prescaler value */ +;;;648 TIM_SetIC4Prescaler(TIMx, TIM_ICInitStruct->TIM_ICPrescaler); +00008c 88e1 LDRH r1,[r4,#6] +00008e 4628 MOV r0,r5 +000090 f7fffffe BL TIM_SetIC4Prescaler + |L40.148| +;;;649 } +;;;650 } +000094 bd70 POP {r4-r6,pc} +;;;651 + ENDP + +000096 0000 DCW 0x0000 + |L40.152| + DCD 0x40012c00 + |L40.156| + DCD 0x40013400 + |L40.160| + DCD 0x40000400 + |L40.164| + DCD 0x40000800 + |L40.168| + DCD 0x40000c00 + + AREA ||i.TIM_ICStructInit||, CODE, READONLY, ALIGN=1 + + TIM_ICStructInit PROC +;;;776 */ +;;;777 void TIM_ICStructInit(TIM_ICInitTypeDef* TIM_ICInitStruct) +000000 2100 MOVS r1,#0 +;;;778 { +;;;779 /* Set the default configuration */ +;;;780 TIM_ICInitStruct->TIM_Channel = TIM_Channel_1; +000002 8001 STRH r1,[r0,#0] +;;;781 TIM_ICInitStruct->TIM_ICPolarity = TIM_ICPolarity_Rising; +000004 8041 STRH r1,[r0,#2] +;;;782 TIM_ICInitStruct->TIM_ICSelection = TIM_ICSelection_DirectTI; +000006 2101 MOVS r1,#1 +000008 8081 STRH r1,[r0,#4] +;;;783 TIM_ICInitStruct->TIM_ICPrescaler = TIM_ICPSC_DIV1; +00000a 2100 MOVS r1,#0 +00000c 80c1 STRH r1,[r0,#6] +;;;784 TIM_ICInitStruct->TIM_ICFilter = 0x00; +00000e 8101 STRH r1,[r0,#8] +;;;785 } +000010 4770 BX lr +;;;786 + ENDP + + + AREA ||i.TIM_ITConfig||, CODE, READONLY, ALIGN=1 + + TIM_ITConfig PROC +;;;877 */ +;;;878 void TIM_ITConfig(TIM_TypeDef* TIMx, uint16_t TIM_IT, FunctionalState NewState) +000000 b11a CBZ r2,|L42.10| +;;;879 { +;;;880 /* Check the parameters */ +;;;881 assert_param(IS_TIM_ALL_PERIPH(TIMx)); +;;;882 assert_param(IS_TIM_IT(TIM_IT)); +;;;883 assert_param(IS_FUNCTIONAL_STATE(NewState)); +;;;884 +;;;885 if (NewState != DISABLE) +;;;886 { +;;;887 /* Enable the Interrupt sources */ +;;;888 TIMx->DIER |= TIM_IT; +000002 8983 LDRH r3,[r0,#0xc] +000004 430b ORRS r3,r3,r1 +000006 8183 STRH r3,[r0,#0xc] +000008 e002 B |L42.16| + |L42.10| +;;;889 } +;;;890 else +;;;891 { +;;;892 /* Disable the Interrupt sources */ +;;;893 TIMx->DIER &= (uint16_t)~TIM_IT; +00000a 8983 LDRH r3,[r0,#0xc] +00000c 438b BICS r3,r3,r1 +00000e 8183 STRH r3,[r0,#0xc] + |L42.16| +;;;894 } +;;;895 } +000010 4770 BX lr +;;;896 + ENDP + + + AREA ||i.TIM_ITRxExternalClockConfig||, CODE, READONLY, ALIGN=1 + + TIM_ITRxExternalClockConfig PROC +;;;1013 */ +;;;1014 void TIM_ITRxExternalClockConfig(TIM_TypeDef* TIMx, uint16_t TIM_InputTriggerSource) +000000 b530 PUSH {r4,r5,lr} +;;;1015 { +000002 4604 MOV r4,r0 +000004 460d MOV r5,r1 +;;;1016 /* Check the parameters */ +;;;1017 assert_param(IS_TIM_LIST6_PERIPH(TIMx)); +;;;1018 assert_param(IS_TIM_INTERNAL_TRIGGER_SELECTION(TIM_InputTriggerSource)); +;;;1019 /* Select the Internal Trigger */ +;;;1020 TIM_SelectInputTrigger(TIMx, TIM_InputTriggerSource); +000006 4629 MOV r1,r5 +000008 4620 MOV r0,r4 +00000a f7fffffe BL TIM_SelectInputTrigger +;;;1021 /* Select the External clock mode1 */ +;;;1022 TIMx->SMCR |= TIM_SlaveMode_External1; +00000e 8920 LDRH r0,[r4,#8] +000010 f0400007 ORR r0,r0,#7 +000014 8120 STRH r0,[r4,#8] +;;;1023 } +000016 bd30 POP {r4,r5,pc} +;;;1024 + ENDP + + + AREA ||i.TIM_InternalClockConfig||, CODE, READONLY, ALIGN=1 + + TIM_InternalClockConfig PROC +;;;994 */ +;;;995 void TIM_InternalClockConfig(TIM_TypeDef* TIMx) +000000 8901 LDRH r1,[r0,#8] +;;;996 { +;;;997 /* Check the parameters */ +;;;998 assert_param(IS_TIM_LIST6_PERIPH(TIMx)); +;;;999 /* Disable slave mode to clock the prescaler directly with the internal clock */ +;;;1000 TIMx->SMCR &= (uint16_t)(~((uint16_t)TIM_SMCR_SMS)); +000002 f64f72f8 MOV r2,#0xfff8 +000006 4011 ANDS r1,r1,r2 +000008 8101 STRH r1,[r0,#8] +;;;1001 } +00000a 4770 BX lr +;;;1002 + ENDP + + + AREA ||i.TIM_OC1FastConfig||, CODE, READONLY, ALIGN=1 + + TIM_OC1FastConfig PROC +;;;1611 */ +;;;1612 void TIM_OC1FastConfig(TIM_TypeDef* TIMx, uint16_t TIM_OCFast) +000000 460a MOV r2,r1 +;;;1613 { +;;;1614 uint16_t tmpccmr1 = 0; +000002 2100 MOVS r1,#0 +;;;1615 /* Check the parameters */ +;;;1616 assert_param(IS_TIM_LIST8_PERIPH(TIMx)); +;;;1617 assert_param(IS_TIM_OCFAST_STATE(TIM_OCFast)); +;;;1618 /* Get the TIMx CCMR1 register value */ +;;;1619 tmpccmr1 = TIMx->CCMR1; +000004 8b01 LDRH r1,[r0,#0x18] +;;;1620 /* Reset the OC1FE Bit */ +;;;1621 tmpccmr1 &= (uint16_t)~((uint16_t)TIM_CCMR1_OC1FE); +000006 f64f73fb MOV r3,#0xfffb +00000a 4019 ANDS r1,r1,r3 +;;;1622 /* Enable or Disable the Output Compare Fast Bit */ +;;;1623 tmpccmr1 |= TIM_OCFast; +00000c 4311 ORRS r1,r1,r2 +;;;1624 /* Write to TIMx CCMR1 */ +;;;1625 TIMx->CCMR1 = tmpccmr1; +00000e 8301 STRH r1,[r0,#0x18] +;;;1626 } +000010 4770 BX lr +;;;1627 + ENDP + + + AREA ||i.TIM_OC1Init||, CODE, READONLY, ALIGN=2 + + TIM_OC1Init PROC +;;;284 */ +;;;285 void TIM_OC1Init(TIM_TypeDef* TIMx, TIM_OCInitTypeDef* TIM_OCInitStruct) +000000 b570 PUSH {r4-r6,lr} +;;;286 { +;;;287 uint16_t tmpccmrx = 0, tmpccer = 0, tmpcr2 = 0; +000002 2400 MOVS r4,#0 +000004 2200 MOVS r2,#0 +000006 2300 MOVS r3,#0 +;;;288 +;;;289 /* Check the parameters */ +;;;290 assert_param(IS_TIM_LIST8_PERIPH(TIMx)); +;;;291 assert_param(IS_TIM_OC_MODE(TIM_OCInitStruct->TIM_OCMode)); +;;;292 assert_param(IS_TIM_OUTPUT_STATE(TIM_OCInitStruct->TIM_OutputState)); +;;;293 assert_param(IS_TIM_OC_POLARITY(TIM_OCInitStruct->TIM_OCPolarity)); +;;;294 /* Disable the Channel 1: Reset the CC1E Bit */ +;;;295 TIMx->CCER &= (uint16_t)(~(uint16_t)TIM_CCER_CC1E); +000008 8c05 LDRH r5,[r0,#0x20] +00000a f64f76fe MOV r6,#0xfffe +00000e 4035 ANDS r5,r5,r6 +000010 8405 STRH r5,[r0,#0x20] +;;;296 /* Get the TIMx CCER register value */ +;;;297 tmpccer = TIMx->CCER; +000012 8c02 LDRH r2,[r0,#0x20] +;;;298 /* Get the TIMx CR2 register value */ +;;;299 tmpcr2 = TIMx->CR2; +000014 8883 LDRH r3,[r0,#4] +;;;300 +;;;301 /* Get the TIMx CCMR1 register value */ +;;;302 tmpccmrx = TIMx->CCMR1; +000016 8b04 LDRH r4,[r0,#0x18] +;;;303 +;;;304 /* Reset the Output Compare Mode Bits */ +;;;305 tmpccmrx &= (uint16_t)(~((uint16_t)TIM_CCMR1_OC1M)); +000018 f64f758f MOV r5,#0xff8f +00001c 402c ANDS r4,r4,r5 +;;;306 tmpccmrx &= (uint16_t)(~((uint16_t)TIM_CCMR1_CC1S)); +00001e 1eb5 SUBS r5,r6,#2 +000020 402c ANDS r4,r4,r5 +;;;307 +;;;308 /* Select the Output Compare Mode */ +;;;309 tmpccmrx |= TIM_OCInitStruct->TIM_OCMode; +000022 880d LDRH r5,[r1,#0] +000024 432c ORRS r4,r4,r5 +;;;310 +;;;311 /* Reset the Output Polarity level */ +;;;312 tmpccer &= (uint16_t)(~((uint16_t)TIM_CCER_CC1P)); +000026 1e75 SUBS r5,r6,#1 +000028 402a ANDS r2,r2,r5 +;;;313 /* Set the Output Compare Polarity */ +;;;314 tmpccer |= TIM_OCInitStruct->TIM_OCPolarity; +00002a 890d LDRH r5,[r1,#8] +00002c 432a ORRS r2,r2,r5 +;;;315 +;;;316 /* Set the Output State */ +;;;317 tmpccer |= TIM_OCInitStruct->TIM_OutputState; +00002e 884d LDRH r5,[r1,#2] +000030 432a ORRS r2,r2,r5 +;;;318 +;;;319 if((TIMx == TIM1) || (TIMx == TIM8)|| (TIMx == TIM15)|| +000032 4d14 LDR r5,|L46.132| +000034 42a8 CMP r0,r5 +000036 d00b BEQ |L46.80| +000038 4d13 LDR r5,|L46.136| +00003a 42a8 CMP r0,r5 +00003c d008 BEQ |L46.80| +00003e 4d13 LDR r5,|L46.140| +000040 42a8 CMP r0,r5 +000042 d005 BEQ |L46.80| +;;;320 (TIMx == TIM16)|| (TIMx == TIM17)) +000044 4d12 LDR r5,|L46.144| +000046 42a8 CMP r0,r5 +000048 d002 BEQ |L46.80| +00004a 4d12 LDR r5,|L46.148| +00004c 42a8 CMP r0,r5 +00004e d113 BNE |L46.120| + |L46.80| +;;;321 { +;;;322 assert_param(IS_TIM_OUTPUTN_STATE(TIM_OCInitStruct->TIM_OutputNState)); +;;;323 assert_param(IS_TIM_OCN_POLARITY(TIM_OCInitStruct->TIM_OCNPolarity)); +;;;324 assert_param(IS_TIM_OCNIDLE_STATE(TIM_OCInitStruct->TIM_OCNIdleState)); +;;;325 assert_param(IS_TIM_OCIDLE_STATE(TIM_OCInitStruct->TIM_OCIdleState)); +;;;326 +;;;327 /* Reset the Output N Polarity level */ +;;;328 tmpccer &= (uint16_t)(~((uint16_t)TIM_CCER_CC1NP)); +000050 f64f75f7 MOV r5,#0xfff7 +000054 402a ANDS r2,r2,r5 +;;;329 /* Set the Output N Polarity */ +;;;330 tmpccer |= TIM_OCInitStruct->TIM_OCNPolarity; +000056 894d LDRH r5,[r1,#0xa] +000058 432a ORRS r2,r2,r5 +;;;331 +;;;332 /* Reset the Output N State */ +;;;333 tmpccer &= (uint16_t)(~((uint16_t)TIM_CCER_CC1NE)); +00005a f64f75fb MOV r5,#0xfffb +00005e 402a ANDS r2,r2,r5 +;;;334 /* Set the Output N State */ +;;;335 tmpccer |= TIM_OCInitStruct->TIM_OutputNState; +000060 888d LDRH r5,[r1,#4] +000062 432a ORRS r2,r2,r5 +;;;336 +;;;337 /* Reset the Output Compare and Output Compare N IDLE State */ +;;;338 tmpcr2 &= (uint16_t)(~((uint16_t)TIM_CR2_OIS1)); +000064 f64f65ff MOV r5,#0xfeff +000068 402b ANDS r3,r3,r5 +;;;339 tmpcr2 &= (uint16_t)(~((uint16_t)TIM_CR2_OIS1N)); +00006a f64f55ff MOV r5,#0xfdff +00006e 402b ANDS r3,r3,r5 +;;;340 +;;;341 /* Set the Output Idle state */ +;;;342 tmpcr2 |= TIM_OCInitStruct->TIM_OCIdleState; +000070 898d LDRH r5,[r1,#0xc] +000072 432b ORRS r3,r3,r5 +;;;343 /* Set the Output N Idle state */ +;;;344 tmpcr2 |= TIM_OCInitStruct->TIM_OCNIdleState; +000074 89cd LDRH r5,[r1,#0xe] +000076 432b ORRS r3,r3,r5 + |L46.120| +;;;345 } +;;;346 /* Write to TIMx CR2 */ +;;;347 TIMx->CR2 = tmpcr2; +000078 8083 STRH r3,[r0,#4] +;;;348 +;;;349 /* Write to TIMx CCMR1 */ +;;;350 TIMx->CCMR1 = tmpccmrx; +00007a 8304 STRH r4,[r0,#0x18] +;;;351 +;;;352 /* Set the Capture Compare Register value */ +;;;353 TIMx->CCR1 = TIM_OCInitStruct->TIM_Pulse; +00007c 88cd LDRH r5,[r1,#6] +00007e 8685 STRH r5,[r0,#0x34] +;;;354 +;;;355 /* Write to TIMx CCER */ +;;;356 TIMx->CCER = tmpccer; +000080 8402 STRH r2,[r0,#0x20] +;;;357 } +000082 bd70 POP {r4-r6,pc} +;;;358 + ENDP + + |L46.132| + DCD 0x40012c00 + |L46.136| + DCD 0x40013400 + |L46.140| + DCD 0x40014000 + |L46.144| + DCD 0x40014400 + |L46.148| + DCD 0x40014800 + + AREA ||i.TIM_OC1NPolarityConfig||, CODE, READONLY, ALIGN=1 + + TIM_OC1NPolarityConfig PROC +;;;1833 */ +;;;1834 void TIM_OC1NPolarityConfig(TIM_TypeDef* TIMx, uint16_t TIM_OCNPolarity) +000000 460a MOV r2,r1 +;;;1835 { +;;;1836 uint16_t tmpccer = 0; +000002 2100 MOVS r1,#0 +;;;1837 /* Check the parameters */ +;;;1838 assert_param(IS_TIM_LIST2_PERIPH(TIMx)); +;;;1839 assert_param(IS_TIM_OCN_POLARITY(TIM_OCNPolarity)); +;;;1840 +;;;1841 tmpccer = TIMx->CCER; +000004 8c01 LDRH r1,[r0,#0x20] +;;;1842 /* Set or Reset the CC1NP Bit */ +;;;1843 tmpccer &= (uint16_t)~((uint16_t)TIM_CCER_CC1NP); +000006 f64f73f7 MOV r3,#0xfff7 +00000a 4019 ANDS r1,r1,r3 +;;;1844 tmpccer |= TIM_OCNPolarity; +00000c 4311 ORRS r1,r1,r2 +;;;1845 /* Write to TIMx CCER register */ +;;;1846 TIMx->CCER = tmpccer; +00000e 8401 STRH r1,[r0,#0x20] +;;;1847 } +000010 4770 BX lr +;;;1848 + ENDP + + + AREA ||i.TIM_OC1PolarityConfig||, CODE, READONLY, ALIGN=1 + + TIM_OC1PolarityConfig PROC +;;;1810 */ +;;;1811 void TIM_OC1PolarityConfig(TIM_TypeDef* TIMx, uint16_t TIM_OCPolarity) +000000 460a MOV r2,r1 +;;;1812 { +;;;1813 uint16_t tmpccer = 0; +000002 2100 MOVS r1,#0 +;;;1814 /* Check the parameters */ +;;;1815 assert_param(IS_TIM_LIST8_PERIPH(TIMx)); +;;;1816 assert_param(IS_TIM_OC_POLARITY(TIM_OCPolarity)); +;;;1817 tmpccer = TIMx->CCER; +000004 8c01 LDRH r1,[r0,#0x20] +;;;1818 /* Set or Reset the CC1P Bit */ +;;;1819 tmpccer &= (uint16_t)~((uint16_t)TIM_CCER_CC1P); +000006 f64f73fd MOV r3,#0xfffd +00000a 4019 ANDS r1,r1,r3 +;;;1820 tmpccer |= TIM_OCPolarity; +00000c 4311 ORRS r1,r1,r2 +;;;1821 /* Write to TIMx CCER register */ +;;;1822 TIMx->CCER = tmpccer; +00000e 8401 STRH r1,[r0,#0x20] +;;;1823 } +000010 4770 BX lr +;;;1824 + ENDP + + + AREA ||i.TIM_OC1PreloadConfig||, CODE, READONLY, ALIGN=1 + + TIM_OC1PreloadConfig PROC +;;;1514 */ +;;;1515 void TIM_OC1PreloadConfig(TIM_TypeDef* TIMx, uint16_t TIM_OCPreload) +000000 460a MOV r2,r1 +;;;1516 { +;;;1517 uint16_t tmpccmr1 = 0; +000002 2100 MOVS r1,#0 +;;;1518 /* Check the parameters */ +;;;1519 assert_param(IS_TIM_LIST8_PERIPH(TIMx)); +;;;1520 assert_param(IS_TIM_OCPRELOAD_STATE(TIM_OCPreload)); +;;;1521 tmpccmr1 = TIMx->CCMR1; +000004 8b01 LDRH r1,[r0,#0x18] +;;;1522 /* Reset the OC1PE Bit */ +;;;1523 tmpccmr1 &= (uint16_t)~((uint16_t)TIM_CCMR1_OC1PE); +000006 f64f73f7 MOV r3,#0xfff7 +00000a 4019 ANDS r1,r1,r3 +;;;1524 /* Enable or Disable the Output Compare Preload feature */ +;;;1525 tmpccmr1 |= TIM_OCPreload; +00000c 4311 ORRS r1,r1,r2 +;;;1526 /* Write to TIMx CCMR1 register */ +;;;1527 TIMx->CCMR1 = tmpccmr1; +00000e 8301 STRH r1,[r0,#0x18] +;;;1528 } +000010 4770 BX lr +;;;1529 + ENDP + + + AREA ||i.TIM_OC2FastConfig||, CODE, READONLY, ALIGN=1 + + TIM_OC2FastConfig PROC +;;;1637 */ +;;;1638 void TIM_OC2FastConfig(TIM_TypeDef* TIMx, uint16_t TIM_OCFast) +000000 460a MOV r2,r1 +;;;1639 { +;;;1640 uint16_t tmpccmr1 = 0; +000002 2100 MOVS r1,#0 +;;;1641 /* Check the parameters */ +;;;1642 assert_param(IS_TIM_LIST6_PERIPH(TIMx)); +;;;1643 assert_param(IS_TIM_OCFAST_STATE(TIM_OCFast)); +;;;1644 /* Get the TIMx CCMR1 register value */ +;;;1645 tmpccmr1 = TIMx->CCMR1; +000004 8b01 LDRH r1,[r0,#0x18] +;;;1646 /* Reset the OC2FE Bit */ +;;;1647 tmpccmr1 &= (uint16_t)~((uint16_t)TIM_CCMR1_OC2FE); +000006 f64f33ff MOV r3,#0xfbff +00000a 4019 ANDS r1,r1,r3 +;;;1648 /* Enable or Disable the Output Compare Fast Bit */ +;;;1649 tmpccmr1 |= (uint16_t)(TIM_OCFast << 8); +00000c f64f73ff MOV r3,#0xffff +000010 ea032302 AND r3,r3,r2,LSL #8 +000014 4319 ORRS r1,r1,r3 +;;;1650 /* Write to TIMx CCMR1 */ +;;;1651 TIMx->CCMR1 = tmpccmr1; +000016 8301 STRH r1,[r0,#0x18] +;;;1652 } +000018 4770 BX lr +;;;1653 + ENDP + + + AREA ||i.TIM_OC2Init||, CODE, READONLY, ALIGN=2 + + TIM_OC2Init PROC +;;;367 */ +;;;368 void TIM_OC2Init(TIM_TypeDef* TIMx, TIM_OCInitTypeDef* TIM_OCInitStruct) +000000 b570 PUSH {r4-r6,lr} +;;;369 { +;;;370 uint16_t tmpccmrx = 0, tmpccer = 0, tmpcr2 = 0; +000002 2400 MOVS r4,#0 +000004 2200 MOVS r2,#0 +000006 2300 MOVS r3,#0 +;;;371 +;;;372 /* Check the parameters */ +;;;373 assert_param(IS_TIM_LIST6_PERIPH(TIMx)); +;;;374 assert_param(IS_TIM_OC_MODE(TIM_OCInitStruct->TIM_OCMode)); +;;;375 assert_param(IS_TIM_OUTPUT_STATE(TIM_OCInitStruct->TIM_OutputState)); +;;;376 assert_param(IS_TIM_OC_POLARITY(TIM_OCInitStruct->TIM_OCPolarity)); +;;;377 /* Disable the Channel 2: Reset the CC2E Bit */ +;;;378 TIMx->CCER &= (uint16_t)(~((uint16_t)TIM_CCER_CC2E)); +000008 8c05 LDRH r5,[r0,#0x20] +00000a f64f76ef MOV r6,#0xffef +00000e 4035 ANDS r5,r5,r6 +000010 8405 STRH r5,[r0,#0x20] +;;;379 +;;;380 /* Get the TIMx CCER register value */ +;;;381 tmpccer = TIMx->CCER; +000012 8c02 LDRH r2,[r0,#0x20] +;;;382 /* Get the TIMx CR2 register value */ +;;;383 tmpcr2 = TIMx->CR2; +000014 8883 LDRH r3,[r0,#4] +;;;384 +;;;385 /* Get the TIMx CCMR1 register value */ +;;;386 tmpccmrx = TIMx->CCMR1; +000016 8b04 LDRH r4,[r0,#0x18] +;;;387 +;;;388 /* Reset the Output Compare mode and Capture/Compare selection Bits */ +;;;389 tmpccmrx &= (uint16_t)(~((uint16_t)TIM_CCMR1_OC2M)); +000018 f64875ff MOV r5,#0x8fff +00001c 402c ANDS r4,r4,r5 +;;;390 tmpccmrx &= (uint16_t)(~((uint16_t)TIM_CCMR1_CC2S)); +00001e f64f45ff MOV r5,#0xfcff +000022 402c ANDS r4,r4,r5 +;;;391 +;;;392 /* Select the Output Compare Mode */ +;;;393 tmpccmrx |= (uint16_t)(TIM_OCInitStruct->TIM_OCMode << 8); +000024 880d LDRH r5,[r1,#0] +000026 f64f76ff MOV r6,#0xffff +00002a ea062505 AND r5,r6,r5,LSL #8 +00002e 432c ORRS r4,r4,r5 +;;;394 +;;;395 /* Reset the Output Polarity level */ +;;;396 tmpccer &= (uint16_t)(~((uint16_t)TIM_CCER_CC2P)); +000030 f64f75df MOV r5,#0xffdf +000034 402a ANDS r2,r2,r5 +;;;397 /* Set the Output Compare Polarity */ +;;;398 tmpccer |= (uint16_t)(TIM_OCInitStruct->TIM_OCPolarity << 4); +000036 890d LDRH r5,[r1,#8] +000038 ea061505 AND r5,r6,r5,LSL #4 +00003c 432a ORRS r2,r2,r5 +;;;399 +;;;400 /* Set the Output State */ +;;;401 tmpccer |= (uint16_t)(TIM_OCInitStruct->TIM_OutputState << 4); +00003e 884d LDRH r5,[r1,#2] +000040 ea061505 AND r5,r6,r5,LSL #4 +000044 432a ORRS r2,r2,r5 +;;;402 +;;;403 if((TIMx == TIM1) || (TIMx == TIM8)) +000046 4d15 LDR r5,|L51.156| +000048 42a8 CMP r0,r5 +00004a d002 BEQ |L51.82| +00004c 4d14 LDR r5,|L51.160| +00004e 42a8 CMP r0,r5 +000050 d11d BNE |L51.142| + |L51.82| +;;;404 { +;;;405 assert_param(IS_TIM_OUTPUTN_STATE(TIM_OCInitStruct->TIM_OutputNState)); +;;;406 assert_param(IS_TIM_OCN_POLARITY(TIM_OCInitStruct->TIM_OCNPolarity)); +;;;407 assert_param(IS_TIM_OCNIDLE_STATE(TIM_OCInitStruct->TIM_OCNIdleState)); +;;;408 assert_param(IS_TIM_OCIDLE_STATE(TIM_OCInitStruct->TIM_OCIdleState)); +;;;409 +;;;410 /* Reset the Output N Polarity level */ +;;;411 tmpccer &= (uint16_t)(~((uint16_t)TIM_CCER_CC2NP)); +000052 f64f757f MOV r5,#0xff7f +000056 402a ANDS r2,r2,r5 +;;;412 /* Set the Output N Polarity */ +;;;413 tmpccer |= (uint16_t)(TIM_OCInitStruct->TIM_OCNPolarity << 4); +000058 894d LDRH r5,[r1,#0xa] +00005a f64f76ff MOV r6,#0xffff +00005e ea061505 AND r5,r6,r5,LSL #4 +000062 432a ORRS r2,r2,r5 +;;;414 +;;;415 /* Reset the Output N State */ +;;;416 tmpccer &= (uint16_t)(~((uint16_t)TIM_CCER_CC2NE)); +000064 f64f75bf MOV r5,#0xffbf +000068 402a ANDS r2,r2,r5 +;;;417 /* Set the Output N State */ +;;;418 tmpccer |= (uint16_t)(TIM_OCInitStruct->TIM_OutputNState << 4); +00006a 888d LDRH r5,[r1,#4] +00006c ea061505 AND r5,r6,r5,LSL #4 +000070 432a ORRS r2,r2,r5 +;;;419 +;;;420 /* Reset the Output Compare and Output Compare N IDLE State */ +;;;421 tmpcr2 &= (uint16_t)(~((uint16_t)TIM_CR2_OIS2)); +000072 f64f35ff MOV r5,#0xfbff +000076 402b ANDS r3,r3,r5 +;;;422 tmpcr2 &= (uint16_t)(~((uint16_t)TIM_CR2_OIS2N)); +000078 f24f75ff MOV r5,#0xf7ff +00007c 402b ANDS r3,r3,r5 +;;;423 +;;;424 /* Set the Output Idle state */ +;;;425 tmpcr2 |= (uint16_t)(TIM_OCInitStruct->TIM_OCIdleState << 2); +00007e 898d LDRH r5,[r1,#0xc] +000080 ea060585 AND r5,r6,r5,LSL #2 +000084 432b ORRS r3,r3,r5 +;;;426 /* Set the Output N Idle state */ +;;;427 tmpcr2 |= (uint16_t)(TIM_OCInitStruct->TIM_OCNIdleState << 2); +000086 89cd LDRH r5,[r1,#0xe] +000088 ea060585 AND r5,r6,r5,LSL #2 +00008c 432b ORRS r3,r3,r5 + |L51.142| +;;;428 } +;;;429 /* Write to TIMx CR2 */ +;;;430 TIMx->CR2 = tmpcr2; +00008e 8083 STRH r3,[r0,#4] +;;;431 +;;;432 /* Write to TIMx CCMR1 */ +;;;433 TIMx->CCMR1 = tmpccmrx; +000090 8304 STRH r4,[r0,#0x18] +;;;434 +;;;435 /* Set the Capture Compare Register value */ +;;;436 TIMx->CCR2 = TIM_OCInitStruct->TIM_Pulse; +000092 88cd LDRH r5,[r1,#6] +000094 8705 STRH r5,[r0,#0x38] +;;;437 +;;;438 /* Write to TIMx CCER */ +;;;439 TIMx->CCER = tmpccer; +000096 8402 STRH r2,[r0,#0x20] +;;;440 } +000098 bd70 POP {r4-r6,pc} +;;;441 + ENDP + +00009a 0000 DCW 0x0000 + |L51.156| + DCD 0x40012c00 + |L51.160| + DCD 0x40013400 + + AREA ||i.TIM_OC2NPolarityConfig||, CODE, READONLY, ALIGN=1 + + TIM_OC2NPolarityConfig PROC +;;;1880 */ +;;;1881 void TIM_OC2NPolarityConfig(TIM_TypeDef* TIMx, uint16_t TIM_OCNPolarity) +000000 460a MOV r2,r1 +;;;1882 { +;;;1883 uint16_t tmpccer = 0; +000002 2100 MOVS r1,#0 +;;;1884 /* Check the parameters */ +;;;1885 assert_param(IS_TIM_LIST1_PERIPH(TIMx)); +;;;1886 assert_param(IS_TIM_OCN_POLARITY(TIM_OCNPolarity)); +;;;1887 +;;;1888 tmpccer = TIMx->CCER; +000004 8c01 LDRH r1,[r0,#0x20] +;;;1889 /* Set or Reset the CC2NP Bit */ +;;;1890 tmpccer &= (uint16_t)~((uint16_t)TIM_CCER_CC2NP); +000006 f64f737f MOV r3,#0xff7f +00000a 4019 ANDS r1,r1,r3 +;;;1891 tmpccer |= (uint16_t)(TIM_OCNPolarity << 4); +00000c f64f73ff MOV r3,#0xffff +000010 ea031302 AND r3,r3,r2,LSL #4 +000014 4319 ORRS r1,r1,r3 +;;;1892 /* Write to TIMx CCER register */ +;;;1893 TIMx->CCER = tmpccer; +000016 8401 STRH r1,[r0,#0x20] +;;;1894 } +000018 4770 BX lr +;;;1895 + ENDP + + + AREA ||i.TIM_OC2PolarityConfig||, CODE, READONLY, ALIGN=1 + + TIM_OC2PolarityConfig PROC +;;;1857 */ +;;;1858 void TIM_OC2PolarityConfig(TIM_TypeDef* TIMx, uint16_t TIM_OCPolarity) +000000 460a MOV r2,r1 +;;;1859 { +;;;1860 uint16_t tmpccer = 0; +000002 2100 MOVS r1,#0 +;;;1861 /* Check the parameters */ +;;;1862 assert_param(IS_TIM_LIST6_PERIPH(TIMx)); +;;;1863 assert_param(IS_TIM_OC_POLARITY(TIM_OCPolarity)); +;;;1864 tmpccer = TIMx->CCER; +000004 8c01 LDRH r1,[r0,#0x20] +;;;1865 /* Set or Reset the CC2P Bit */ +;;;1866 tmpccer &= (uint16_t)~((uint16_t)TIM_CCER_CC2P); +000006 f64f73df MOV r3,#0xffdf +00000a 4019 ANDS r1,r1,r3 +;;;1867 tmpccer |= (uint16_t)(TIM_OCPolarity << 4); +00000c f64f73ff MOV r3,#0xffff +000010 ea031302 AND r3,r3,r2,LSL #4 +000014 4319 ORRS r1,r1,r3 +;;;1868 /* Write to TIMx CCER register */ +;;;1869 TIMx->CCER = tmpccer; +000016 8401 STRH r1,[r0,#0x20] +;;;1870 } +000018 4770 BX lr +;;;1871 + ENDP + + + AREA ||i.TIM_OC2PreloadConfig||, CODE, READONLY, ALIGN=1 + + TIM_OC2PreloadConfig PROC +;;;1539 */ +;;;1540 void TIM_OC2PreloadConfig(TIM_TypeDef* TIMx, uint16_t TIM_OCPreload) +000000 460a MOV r2,r1 +;;;1541 { +;;;1542 uint16_t tmpccmr1 = 0; +000002 2100 MOVS r1,#0 +;;;1543 /* Check the parameters */ +;;;1544 assert_param(IS_TIM_LIST6_PERIPH(TIMx)); +;;;1545 assert_param(IS_TIM_OCPRELOAD_STATE(TIM_OCPreload)); +;;;1546 tmpccmr1 = TIMx->CCMR1; +000004 8b01 LDRH r1,[r0,#0x18] +;;;1547 /* Reset the OC2PE Bit */ +;;;1548 tmpccmr1 &= (uint16_t)~((uint16_t)TIM_CCMR1_OC2PE); +000006 f24f73ff MOV r3,#0xf7ff +00000a 4019 ANDS r1,r1,r3 +;;;1549 /* Enable or Disable the Output Compare Preload feature */ +;;;1550 tmpccmr1 |= (uint16_t)(TIM_OCPreload << 8); +00000c f64f73ff MOV r3,#0xffff +000010 ea032302 AND r3,r3,r2,LSL #8 +000014 4319 ORRS r1,r1,r3 +;;;1551 /* Write to TIMx CCMR1 register */ +;;;1552 TIMx->CCMR1 = tmpccmr1; +000016 8301 STRH r1,[r0,#0x18] +;;;1553 } +000018 4770 BX lr +;;;1554 + ENDP + + + AREA ||i.TIM_OC3FastConfig||, CODE, READONLY, ALIGN=1 + + TIM_OC3FastConfig PROC +;;;1662 */ +;;;1663 void TIM_OC3FastConfig(TIM_TypeDef* TIMx, uint16_t TIM_OCFast) +000000 460a MOV r2,r1 +;;;1664 { +;;;1665 uint16_t tmpccmr2 = 0; +000002 2100 MOVS r1,#0 +;;;1666 /* Check the parameters */ +;;;1667 assert_param(IS_TIM_LIST3_PERIPH(TIMx)); +;;;1668 assert_param(IS_TIM_OCFAST_STATE(TIM_OCFast)); +;;;1669 /* Get the TIMx CCMR2 register value */ +;;;1670 tmpccmr2 = TIMx->CCMR2; +000004 8b81 LDRH r1,[r0,#0x1c] +;;;1671 /* Reset the OC3FE Bit */ +;;;1672 tmpccmr2 &= (uint16_t)~((uint16_t)TIM_CCMR2_OC3FE); +000006 f64f73fb MOV r3,#0xfffb +00000a 4019 ANDS r1,r1,r3 +;;;1673 /* Enable or Disable the Output Compare Fast Bit */ +;;;1674 tmpccmr2 |= TIM_OCFast; +00000c 4311 ORRS r1,r1,r2 +;;;1675 /* Write to TIMx CCMR2 */ +;;;1676 TIMx->CCMR2 = tmpccmr2; +00000e 8381 STRH r1,[r0,#0x1c] +;;;1677 } +000010 4770 BX lr +;;;1678 + ENDP + + + AREA ||i.TIM_OC3Init||, CODE, READONLY, ALIGN=2 + + TIM_OC3Init PROC +;;;449 */ +;;;450 void TIM_OC3Init(TIM_TypeDef* TIMx, TIM_OCInitTypeDef* TIM_OCInitStruct) +000000 b570 PUSH {r4-r6,lr} +;;;451 { +;;;452 uint16_t tmpccmrx = 0, tmpccer = 0, tmpcr2 = 0; +000002 2400 MOVS r4,#0 +000004 2200 MOVS r2,#0 +000006 2300 MOVS r3,#0 +;;;453 +;;;454 /* Check the parameters */ +;;;455 assert_param(IS_TIM_LIST3_PERIPH(TIMx)); +;;;456 assert_param(IS_TIM_OC_MODE(TIM_OCInitStruct->TIM_OCMode)); +;;;457 assert_param(IS_TIM_OUTPUT_STATE(TIM_OCInitStruct->TIM_OutputState)); +;;;458 assert_param(IS_TIM_OC_POLARITY(TIM_OCInitStruct->TIM_OCPolarity)); +;;;459 /* Disable the Channel 2: Reset the CC2E Bit */ +;;;460 TIMx->CCER &= (uint16_t)(~((uint16_t)TIM_CCER_CC3E)); +000008 8c05 LDRH r5,[r0,#0x20] +00000a f64f66ff MOV r6,#0xfeff +00000e 4035 ANDS r5,r5,r6 +000010 8405 STRH r5,[r0,#0x20] +;;;461 +;;;462 /* Get the TIMx CCER register value */ +;;;463 tmpccer = TIMx->CCER; +000012 8c02 LDRH r2,[r0,#0x20] +;;;464 /* Get the TIMx CR2 register value */ +;;;465 tmpcr2 = TIMx->CR2; +000014 8883 LDRH r3,[r0,#4] +;;;466 +;;;467 /* Get the TIMx CCMR2 register value */ +;;;468 tmpccmrx = TIMx->CCMR2; +000016 8b84 LDRH r4,[r0,#0x1c] +;;;469 +;;;470 /* Reset the Output Compare mode and Capture/Compare selection Bits */ +;;;471 tmpccmrx &= (uint16_t)(~((uint16_t)TIM_CCMR2_OC3M)); +000018 f64f758f MOV r5,#0xff8f +00001c 402c ANDS r4,r4,r5 +;;;472 tmpccmrx &= (uint16_t)(~((uint16_t)TIM_CCMR2_CC3S)); +00001e f64f75fc MOV r5,#0xfffc +000022 402c ANDS r4,r4,r5 +;;;473 /* Select the Output Compare Mode */ +;;;474 tmpccmrx |= TIM_OCInitStruct->TIM_OCMode; +000024 880d LDRH r5,[r1,#0] +000026 432c ORRS r4,r4,r5 +;;;475 +;;;476 /* Reset the Output Polarity level */ +;;;477 tmpccer &= (uint16_t)(~((uint16_t)TIM_CCER_CC3P)); +000028 f64f55ff MOV r5,#0xfdff +00002c 402a ANDS r2,r2,r5 +;;;478 /* Set the Output Compare Polarity */ +;;;479 tmpccer |= (uint16_t)(TIM_OCInitStruct->TIM_OCPolarity << 8); +00002e 890d LDRH r5,[r1,#8] +000030 f64f76ff MOV r6,#0xffff +000034 ea062505 AND r5,r6,r5,LSL #8 +000038 432a ORRS r2,r2,r5 +;;;480 +;;;481 /* Set the Output State */ +;;;482 tmpccer |= (uint16_t)(TIM_OCInitStruct->TIM_OutputState << 8); +00003a 884d LDRH r5,[r1,#2] +00003c ea062505 AND r5,r6,r5,LSL #8 +000040 432a ORRS r2,r2,r5 +;;;483 +;;;484 if((TIMx == TIM1) || (TIMx == TIM8)) +000042 4d15 LDR r5,|L56.152| +000044 42a8 CMP r0,r5 +000046 d002 BEQ |L56.78| +000048 4d14 LDR r5,|L56.156| +00004a 42a8 CMP r0,r5 +00004c d11d BNE |L56.138| + |L56.78| +;;;485 { +;;;486 assert_param(IS_TIM_OUTPUTN_STATE(TIM_OCInitStruct->TIM_OutputNState)); +;;;487 assert_param(IS_TIM_OCN_POLARITY(TIM_OCInitStruct->TIM_OCNPolarity)); +;;;488 assert_param(IS_TIM_OCNIDLE_STATE(TIM_OCInitStruct->TIM_OCNIdleState)); +;;;489 assert_param(IS_TIM_OCIDLE_STATE(TIM_OCInitStruct->TIM_OCIdleState)); +;;;490 +;;;491 /* Reset the Output N Polarity level */ +;;;492 tmpccer &= (uint16_t)(~((uint16_t)TIM_CCER_CC3NP)); +00004e f24f75ff MOV r5,#0xf7ff +000052 402a ANDS r2,r2,r5 +;;;493 /* Set the Output N Polarity */ +;;;494 tmpccer |= (uint16_t)(TIM_OCInitStruct->TIM_OCNPolarity << 8); +000054 894d LDRH r5,[r1,#0xa] +000056 f64f76ff MOV r6,#0xffff +00005a ea062505 AND r5,r6,r5,LSL #8 +00005e 432a ORRS r2,r2,r5 +;;;495 /* Reset the Output N State */ +;;;496 tmpccer &= (uint16_t)(~((uint16_t)TIM_CCER_CC3NE)); +000060 f64f35ff MOV r5,#0xfbff +000064 402a ANDS r2,r2,r5 +;;;497 +;;;498 /* Set the Output N State */ +;;;499 tmpccer |= (uint16_t)(TIM_OCInitStruct->TIM_OutputNState << 8); +000066 888d LDRH r5,[r1,#4] +000068 ea062505 AND r5,r6,r5,LSL #8 +00006c 432a ORRS r2,r2,r5 +;;;500 /* Reset the Output Compare and Output Compare N IDLE State */ +;;;501 tmpcr2 &= (uint16_t)(~((uint16_t)TIM_CR2_OIS3)); +00006e f64e75ff MOV r5,#0xefff +000072 402b ANDS r3,r3,r5 +;;;502 tmpcr2 &= (uint16_t)(~((uint16_t)TIM_CR2_OIS3N)); +000074 f64d75ff MOV r5,#0xdfff +000078 402b ANDS r3,r3,r5 +;;;503 /* Set the Output Idle state */ +;;;504 tmpcr2 |= (uint16_t)(TIM_OCInitStruct->TIM_OCIdleState << 4); +00007a 898d LDRH r5,[r1,#0xc] +00007c ea061505 AND r5,r6,r5,LSL #4 +000080 432b ORRS r3,r3,r5 +;;;505 /* Set the Output N Idle state */ +;;;506 tmpcr2 |= (uint16_t)(TIM_OCInitStruct->TIM_OCNIdleState << 4); +000082 89cd LDRH r5,[r1,#0xe] +000084 ea061505 AND r5,r6,r5,LSL #4 +000088 432b ORRS r3,r3,r5 + |L56.138| +;;;507 } +;;;508 /* Write to TIMx CR2 */ +;;;509 TIMx->CR2 = tmpcr2; +00008a 8083 STRH r3,[r0,#4] +;;;510 +;;;511 /* Write to TIMx CCMR2 */ +;;;512 TIMx->CCMR2 = tmpccmrx; +00008c 8384 STRH r4,[r0,#0x1c] +;;;513 +;;;514 /* Set the Capture Compare Register value */ +;;;515 TIMx->CCR3 = TIM_OCInitStruct->TIM_Pulse; +00008e 88cd LDRH r5,[r1,#6] +000090 8785 STRH r5,[r0,#0x3c] +;;;516 +;;;517 /* Write to TIMx CCER */ +;;;518 TIMx->CCER = tmpccer; +000092 8402 STRH r2,[r0,#0x20] +;;;519 } +000094 bd70 POP {r4-r6,pc} +;;;520 + ENDP + +000096 0000 DCW 0x0000 + |L56.152| + DCD 0x40012c00 + |L56.156| + DCD 0x40013400 + + AREA ||i.TIM_OC3NPolarityConfig||, CODE, READONLY, ALIGN=1 + + TIM_OC3NPolarityConfig PROC +;;;1927 */ +;;;1928 void TIM_OC3NPolarityConfig(TIM_TypeDef* TIMx, uint16_t TIM_OCNPolarity) +000000 460a MOV r2,r1 +;;;1929 { +;;;1930 uint16_t tmpccer = 0; +000002 2100 MOVS r1,#0 +;;;1931 +;;;1932 /* Check the parameters */ +;;;1933 assert_param(IS_TIM_LIST1_PERIPH(TIMx)); +;;;1934 assert_param(IS_TIM_OCN_POLARITY(TIM_OCNPolarity)); +;;;1935 +;;;1936 tmpccer = TIMx->CCER; +000004 8c01 LDRH r1,[r0,#0x20] +;;;1937 /* Set or Reset the CC3NP Bit */ +;;;1938 tmpccer &= (uint16_t)~((uint16_t)TIM_CCER_CC3NP); +000006 f24f73ff MOV r3,#0xf7ff +00000a 4019 ANDS r1,r1,r3 +;;;1939 tmpccer |= (uint16_t)(TIM_OCNPolarity << 8); +00000c f64f73ff MOV r3,#0xffff +000010 ea032302 AND r3,r3,r2,LSL #8 +000014 4319 ORRS r1,r1,r3 +;;;1940 /* Write to TIMx CCER register */ +;;;1941 TIMx->CCER = tmpccer; +000016 8401 STRH r1,[r0,#0x20] +;;;1942 } +000018 4770 BX lr +;;;1943 + ENDP + + + AREA ||i.TIM_OC3PolarityConfig||, CODE, READONLY, ALIGN=1 + + TIM_OC3PolarityConfig PROC +;;;1904 */ +;;;1905 void TIM_OC3PolarityConfig(TIM_TypeDef* TIMx, uint16_t TIM_OCPolarity) +000000 460a MOV r2,r1 +;;;1906 { +;;;1907 uint16_t tmpccer = 0; +000002 2100 MOVS r1,#0 +;;;1908 /* Check the parameters */ +;;;1909 assert_param(IS_TIM_LIST3_PERIPH(TIMx)); +;;;1910 assert_param(IS_TIM_OC_POLARITY(TIM_OCPolarity)); +;;;1911 tmpccer = TIMx->CCER; +000004 8c01 LDRH r1,[r0,#0x20] +;;;1912 /* Set or Reset the CC3P Bit */ +;;;1913 tmpccer &= (uint16_t)~((uint16_t)TIM_CCER_CC3P); +000006 f64f53ff MOV r3,#0xfdff +00000a 4019 ANDS r1,r1,r3 +;;;1914 tmpccer |= (uint16_t)(TIM_OCPolarity << 8); +00000c f64f73ff MOV r3,#0xffff +000010 ea032302 AND r3,r3,r2,LSL #8 +000014 4319 ORRS r1,r1,r3 +;;;1915 /* Write to TIMx CCER register */ +;;;1916 TIMx->CCER = tmpccer; +000016 8401 STRH r1,[r0,#0x20] +;;;1917 } +000018 4770 BX lr +;;;1918 + ENDP + + + AREA ||i.TIM_OC3PreloadConfig||, CODE, READONLY, ALIGN=1 + + TIM_OC3PreloadConfig PROC +;;;1563 */ +;;;1564 void TIM_OC3PreloadConfig(TIM_TypeDef* TIMx, uint16_t TIM_OCPreload) +000000 460a MOV r2,r1 +;;;1565 { +;;;1566 uint16_t tmpccmr2 = 0; +000002 2100 MOVS r1,#0 +;;;1567 /* Check the parameters */ +;;;1568 assert_param(IS_TIM_LIST3_PERIPH(TIMx)); +;;;1569 assert_param(IS_TIM_OCPRELOAD_STATE(TIM_OCPreload)); +;;;1570 tmpccmr2 = TIMx->CCMR2; +000004 8b81 LDRH r1,[r0,#0x1c] +;;;1571 /* Reset the OC3PE Bit */ +;;;1572 tmpccmr2 &= (uint16_t)~((uint16_t)TIM_CCMR2_OC3PE); +000006 f64f73f7 MOV r3,#0xfff7 +00000a 4019 ANDS r1,r1,r3 +;;;1573 /* Enable or Disable the Output Compare Preload feature */ +;;;1574 tmpccmr2 |= TIM_OCPreload; +00000c 4311 ORRS r1,r1,r2 +;;;1575 /* Write to TIMx CCMR2 register */ +;;;1576 TIMx->CCMR2 = tmpccmr2; +00000e 8381 STRH r1,[r0,#0x1c] +;;;1577 } +000010 4770 BX lr +;;;1578 + ENDP + + + AREA ||i.TIM_OC4FastConfig||, CODE, READONLY, ALIGN=1 + + TIM_OC4FastConfig PROC +;;;1687 */ +;;;1688 void TIM_OC4FastConfig(TIM_TypeDef* TIMx, uint16_t TIM_OCFast) +000000 460a MOV r2,r1 +;;;1689 { +;;;1690 uint16_t tmpccmr2 = 0; +000002 2100 MOVS r1,#0 +;;;1691 /* Check the parameters */ +;;;1692 assert_param(IS_TIM_LIST3_PERIPH(TIMx)); +;;;1693 assert_param(IS_TIM_OCFAST_STATE(TIM_OCFast)); +;;;1694 /* Get the TIMx CCMR2 register value */ +;;;1695 tmpccmr2 = TIMx->CCMR2; +000004 8b81 LDRH r1,[r0,#0x1c] +;;;1696 /* Reset the OC4FE Bit */ +;;;1697 tmpccmr2 &= (uint16_t)~((uint16_t)TIM_CCMR2_OC4FE); +000006 f64f33ff MOV r3,#0xfbff +00000a 4019 ANDS r1,r1,r3 +;;;1698 /* Enable or Disable the Output Compare Fast Bit */ +;;;1699 tmpccmr2 |= (uint16_t)(TIM_OCFast << 8); +00000c f64f73ff MOV r3,#0xffff +000010 ea032302 AND r3,r3,r2,LSL #8 +000014 4319 ORRS r1,r1,r3 +;;;1700 /* Write to TIMx CCMR2 */ +;;;1701 TIMx->CCMR2 = tmpccmr2; +000016 8381 STRH r1,[r0,#0x1c] +;;;1702 } +000018 4770 BX lr +;;;1703 + ENDP + + + AREA ||i.TIM_OC4Init||, CODE, READONLY, ALIGN=2 + + TIM_OC4Init PROC +;;;528 */ +;;;529 void TIM_OC4Init(TIM_TypeDef* TIMx, TIM_OCInitTypeDef* TIM_OCInitStruct) +000000 b570 PUSH {r4-r6,lr} +;;;530 { +;;;531 uint16_t tmpccmrx = 0, tmpccer = 0, tmpcr2 = 0; +000002 2200 MOVS r2,#0 +000004 2300 MOVS r3,#0 +000006 2400 MOVS r4,#0 +;;;532 +;;;533 /* Check the parameters */ +;;;534 assert_param(IS_TIM_LIST3_PERIPH(TIMx)); +;;;535 assert_param(IS_TIM_OC_MODE(TIM_OCInitStruct->TIM_OCMode)); +;;;536 assert_param(IS_TIM_OUTPUT_STATE(TIM_OCInitStruct->TIM_OutputState)); +;;;537 assert_param(IS_TIM_OC_POLARITY(TIM_OCInitStruct->TIM_OCPolarity)); +;;;538 /* Disable the Channel 2: Reset the CC4E Bit */ +;;;539 TIMx->CCER &= (uint16_t)(~((uint16_t)TIM_CCER_CC4E)); +000008 8c05 LDRH r5,[r0,#0x20] +00000a f64e76ff MOV r6,#0xefff +00000e 4035 ANDS r5,r5,r6 +000010 8405 STRH r5,[r0,#0x20] +;;;540 +;;;541 /* Get the TIMx CCER register value */ +;;;542 tmpccer = TIMx->CCER; +000012 8c03 LDRH r3,[r0,#0x20] +;;;543 /* Get the TIMx CR2 register value */ +;;;544 tmpcr2 = TIMx->CR2; +000014 8884 LDRH r4,[r0,#4] +;;;545 +;;;546 /* Get the TIMx CCMR2 register value */ +;;;547 tmpccmrx = TIMx->CCMR2; +000016 8b82 LDRH r2,[r0,#0x1c] +;;;548 +;;;549 /* Reset the Output Compare mode and Capture/Compare selection Bits */ +;;;550 tmpccmrx &= (uint16_t)(~((uint16_t)TIM_CCMR2_OC4M)); +000018 f64875ff MOV r5,#0x8fff +00001c 402a ANDS r2,r2,r5 +;;;551 tmpccmrx &= (uint16_t)(~((uint16_t)TIM_CCMR2_CC4S)); +00001e f64f45ff MOV r5,#0xfcff +000022 402a ANDS r2,r2,r5 +;;;552 +;;;553 /* Select the Output Compare Mode */ +;;;554 tmpccmrx |= (uint16_t)(TIM_OCInitStruct->TIM_OCMode << 8); +000024 880d LDRH r5,[r1,#0] +000026 f64f76ff MOV r6,#0xffff +00002a ea062505 AND r5,r6,r5,LSL #8 +00002e 432a ORRS r2,r2,r5 +;;;555 +;;;556 /* Reset the Output Polarity level */ +;;;557 tmpccer &= (uint16_t)(~((uint16_t)TIM_CCER_CC4P)); +000030 f64d75ff MOV r5,#0xdfff +000034 402b ANDS r3,r3,r5 +;;;558 /* Set the Output Compare Polarity */ +;;;559 tmpccer |= (uint16_t)(TIM_OCInitStruct->TIM_OCPolarity << 12); +000036 890d LDRH r5,[r1,#8] +000038 ea063505 AND r5,r6,r5,LSL #12 +00003c 432b ORRS r3,r3,r5 +;;;560 +;;;561 /* Set the Output State */ +;;;562 tmpccer |= (uint16_t)(TIM_OCInitStruct->TIM_OutputState << 12); +00003e 884d LDRH r5,[r1,#2] +000040 ea063505 AND r5,r6,r5,LSL #12 +000044 432b ORRS r3,r3,r5 +;;;563 +;;;564 if((TIMx == TIM1) || (TIMx == TIM8)) +000046 4d0b LDR r5,|L61.116| +000048 42a8 CMP r0,r5 +00004a d002 BEQ |L61.82| +00004c 4d0a LDR r5,|L61.120| +00004e 42a8 CMP r0,r5 +000050 d108 BNE |L61.100| + |L61.82| +;;;565 { +;;;566 assert_param(IS_TIM_OCIDLE_STATE(TIM_OCInitStruct->TIM_OCIdleState)); +;;;567 /* Reset the Output Compare IDLE State */ +;;;568 tmpcr2 &= (uint16_t)(~((uint16_t)TIM_CR2_OIS4)); +000052 f64b75ff MOV r5,#0xbfff +000056 402c ANDS r4,r4,r5 +;;;569 /* Set the Output Idle state */ +;;;570 tmpcr2 |= (uint16_t)(TIM_OCInitStruct->TIM_OCIdleState << 6); +000058 898d LDRH r5,[r1,#0xc] +00005a f64f76ff MOV r6,#0xffff +00005e ea061585 AND r5,r6,r5,LSL #6 +000062 432c ORRS r4,r4,r5 + |L61.100| +;;;571 } +;;;572 /* Write to TIMx CR2 */ +;;;573 TIMx->CR2 = tmpcr2; +000064 8084 STRH r4,[r0,#4] +;;;574 +;;;575 /* Write to TIMx CCMR2 */ +;;;576 TIMx->CCMR2 = tmpccmrx; +000066 8382 STRH r2,[r0,#0x1c] +;;;577 +;;;578 /* Set the Capture Compare Register value */ +;;;579 TIMx->CCR4 = TIM_OCInitStruct->TIM_Pulse; +000068 88cd LDRH r5,[r1,#6] +00006a f8a05040 STRH r5,[r0,#0x40] +;;;580 +;;;581 /* Write to TIMx CCER */ +;;;582 TIMx->CCER = tmpccer; +00006e 8403 STRH r3,[r0,#0x20] +;;;583 } +000070 bd70 POP {r4-r6,pc} +;;;584 + ENDP + +000072 0000 DCW 0x0000 + |L61.116| + DCD 0x40012c00 + |L61.120| + DCD 0x40013400 + + AREA ||i.TIM_OC4PolarityConfig||, CODE, READONLY, ALIGN=1 + + TIM_OC4PolarityConfig PROC +;;;1952 */ +;;;1953 void TIM_OC4PolarityConfig(TIM_TypeDef* TIMx, uint16_t TIM_OCPolarity) +000000 460a MOV r2,r1 +;;;1954 { +;;;1955 uint16_t tmpccer = 0; +000002 2100 MOVS r1,#0 +;;;1956 /* Check the parameters */ +;;;1957 assert_param(IS_TIM_LIST3_PERIPH(TIMx)); +;;;1958 assert_param(IS_TIM_OC_POLARITY(TIM_OCPolarity)); +;;;1959 tmpccer = TIMx->CCER; +000004 8c01 LDRH r1,[r0,#0x20] +;;;1960 /* Set or Reset the CC4P Bit */ +;;;1961 tmpccer &= (uint16_t)~((uint16_t)TIM_CCER_CC4P); +000006 f64d73ff MOV r3,#0xdfff +00000a 4019 ANDS r1,r1,r3 +;;;1962 tmpccer |= (uint16_t)(TIM_OCPolarity << 12); +00000c f64f73ff MOV r3,#0xffff +000010 ea033302 AND r3,r3,r2,LSL #12 +000014 4319 ORRS r1,r1,r3 +;;;1963 /* Write to TIMx CCER register */ +;;;1964 TIMx->CCER = tmpccer; +000016 8401 STRH r1,[r0,#0x20] +;;;1965 } +000018 4770 BX lr +;;;1966 + ENDP + + + AREA ||i.TIM_OC4PreloadConfig||, CODE, READONLY, ALIGN=1 + + TIM_OC4PreloadConfig PROC +;;;1587 */ +;;;1588 void TIM_OC4PreloadConfig(TIM_TypeDef* TIMx, uint16_t TIM_OCPreload) +000000 460a MOV r2,r1 +;;;1589 { +;;;1590 uint16_t tmpccmr2 = 0; +000002 2100 MOVS r1,#0 +;;;1591 /* Check the parameters */ +;;;1592 assert_param(IS_TIM_LIST3_PERIPH(TIMx)); +;;;1593 assert_param(IS_TIM_OCPRELOAD_STATE(TIM_OCPreload)); +;;;1594 tmpccmr2 = TIMx->CCMR2; +000004 8b81 LDRH r1,[r0,#0x1c] +;;;1595 /* Reset the OC4PE Bit */ +;;;1596 tmpccmr2 &= (uint16_t)~((uint16_t)TIM_CCMR2_OC4PE); +000006 f24f73ff MOV r3,#0xf7ff +00000a 4019 ANDS r1,r1,r3 +;;;1597 /* Enable or Disable the Output Compare Preload feature */ +;;;1598 tmpccmr2 |= (uint16_t)(TIM_OCPreload << 8); +00000c f64f73ff MOV r3,#0xffff +000010 ea032302 AND r3,r3,r2,LSL #8 +000014 4319 ORRS r1,r1,r3 +;;;1599 /* Write to TIMx CCMR2 register */ +;;;1600 TIMx->CCMR2 = tmpccmr2; +000016 8381 STRH r1,[r0,#0x1c] +;;;1601 } +000018 4770 BX lr +;;;1602 + ENDP + + + AREA ||i.TIM_OCStructInit||, CODE, READONLY, ALIGN=1 + + TIM_OCStructInit PROC +;;;757 */ +;;;758 void TIM_OCStructInit(TIM_OCInitTypeDef* TIM_OCInitStruct) +000000 2100 MOVS r1,#0 +;;;759 { +;;;760 /* Set the default configuration */ +;;;761 TIM_OCInitStruct->TIM_OCMode = TIM_OCMode_Timing; +000002 8001 STRH r1,[r0,#0] +;;;762 TIM_OCInitStruct->TIM_OutputState = TIM_OutputState_Disable; +000004 8041 STRH r1,[r0,#2] +;;;763 TIM_OCInitStruct->TIM_OutputNState = TIM_OutputNState_Disable; +000006 8081 STRH r1,[r0,#4] +;;;764 TIM_OCInitStruct->TIM_Pulse = 0x0000; +000008 80c1 STRH r1,[r0,#6] +;;;765 TIM_OCInitStruct->TIM_OCPolarity = TIM_OCPolarity_High; +00000a 8101 STRH r1,[r0,#8] +;;;766 TIM_OCInitStruct->TIM_OCNPolarity = TIM_OCPolarity_High; +00000c 8141 STRH r1,[r0,#0xa] +;;;767 TIM_OCInitStruct->TIM_OCIdleState = TIM_OCIdleState_Reset; +00000e 8181 STRH r1,[r0,#0xc] +;;;768 TIM_OCInitStruct->TIM_OCNIdleState = TIM_OCNIdleState_Reset; +000010 81c1 STRH r1,[r0,#0xe] +;;;769 } +000012 4770 BX lr +;;;770 + ENDP + + + AREA ||i.TIM_PWMIConfig||, CODE, READONLY, ALIGN=1 + + TIM_PWMIConfig PROC +;;;659 */ +;;;660 void TIM_PWMIConfig(TIM_TypeDef* TIMx, TIM_ICInitTypeDef* TIM_ICInitStruct) +000000 e92d41f0 PUSH {r4-r8,lr} +;;;661 { +000004 4605 MOV r5,r0 +000006 460c MOV r4,r1 +;;;662 uint16_t icoppositepolarity = TIM_ICPolarity_Rising; +000008 2600 MOVS r6,#0 +;;;663 uint16_t icoppositeselection = TIM_ICSelection_DirectTI; +00000a 2701 MOVS r7,#1 +;;;664 /* Check the parameters */ +;;;665 assert_param(IS_TIM_LIST6_PERIPH(TIMx)); +;;;666 /* Select the Opposite Input Polarity */ +;;;667 if (TIM_ICInitStruct->TIM_ICPolarity == TIM_ICPolarity_Rising) +00000c 8860 LDRH r0,[r4,#2] +00000e b908 CBNZ r0,|L65.20| +;;;668 { +;;;669 icoppositepolarity = TIM_ICPolarity_Falling; +000010 2602 MOVS r6,#2 +000012 e000 B |L65.22| + |L65.20| +;;;670 } +;;;671 else +;;;672 { +;;;673 icoppositepolarity = TIM_ICPolarity_Rising; +000014 2600 MOVS r6,#0 + |L65.22| +;;;674 } +;;;675 /* Select the Opposite Input */ +;;;676 if (TIM_ICInitStruct->TIM_ICSelection == TIM_ICSelection_DirectTI) +000016 88a0 LDRH r0,[r4,#4] +000018 2801 CMP r0,#1 +00001a d101 BNE |L65.32| +;;;677 { +;;;678 icoppositeselection = TIM_ICSelection_IndirectTI; +00001c 2702 MOVS r7,#2 +00001e e000 B |L65.34| + |L65.32| +;;;679 } +;;;680 else +;;;681 { +;;;682 icoppositeselection = TIM_ICSelection_DirectTI; +000020 2701 MOVS r7,#1 + |L65.34| +;;;683 } +;;;684 if (TIM_ICInitStruct->TIM_Channel == TIM_Channel_1) +000022 8820 LDRH r0,[r4,#0] +000024 b9a0 CBNZ r0,|L65.80| +;;;685 { +;;;686 /* TI1 Configuration */ +;;;687 TI1_Config(TIMx, TIM_ICInitStruct->TIM_ICPolarity, TIM_ICInitStruct->TIM_ICSelection, +000026 8923 LDRH r3,[r4,#8] +000028 88a2 LDRH r2,[r4,#4] +00002a 8861 LDRH r1,[r4,#2] +00002c 4628 MOV r0,r5 +00002e f7fffffe BL TI1_Config +;;;688 TIM_ICInitStruct->TIM_ICFilter); +;;;689 /* Set the Input Capture Prescaler value */ +;;;690 TIM_SetIC1Prescaler(TIMx, TIM_ICInitStruct->TIM_ICPrescaler); +000032 88e1 LDRH r1,[r4,#6] +000034 4628 MOV r0,r5 +000036 f7fffffe BL TIM_SetIC1Prescaler +;;;691 /* TI2 Configuration */ +;;;692 TI2_Config(TIMx, icoppositepolarity, icoppositeselection, TIM_ICInitStruct->TIM_ICFilter); +00003a 8923 LDRH r3,[r4,#8] +00003c 463a MOV r2,r7 +00003e 4631 MOV r1,r6 +000040 4628 MOV r0,r5 +000042 f7fffffe BL TI2_Config +;;;693 /* Set the Input Capture Prescaler value */ +;;;694 TIM_SetIC2Prescaler(TIMx, TIM_ICInitStruct->TIM_ICPrescaler); +000046 88e1 LDRH r1,[r4,#6] +000048 4628 MOV r0,r5 +00004a f7fffffe BL TIM_SetIC2Prescaler +00004e e013 B |L65.120| + |L65.80| +;;;695 } +;;;696 else +;;;697 { +;;;698 /* TI2 Configuration */ +;;;699 TI2_Config(TIMx, TIM_ICInitStruct->TIM_ICPolarity, TIM_ICInitStruct->TIM_ICSelection, +000050 8923 LDRH r3,[r4,#8] +000052 88a2 LDRH r2,[r4,#4] +000054 8861 LDRH r1,[r4,#2] +000056 4628 MOV r0,r5 +000058 f7fffffe BL TI2_Config +;;;700 TIM_ICInitStruct->TIM_ICFilter); +;;;701 /* Set the Input Capture Prescaler value */ +;;;702 TIM_SetIC2Prescaler(TIMx, TIM_ICInitStruct->TIM_ICPrescaler); +00005c 88e1 LDRH r1,[r4,#6] +00005e 4628 MOV r0,r5 +000060 f7fffffe BL TIM_SetIC2Prescaler +;;;703 /* TI1 Configuration */ +;;;704 TI1_Config(TIMx, icoppositepolarity, icoppositeselection, TIM_ICInitStruct->TIM_ICFilter); +000064 8923 LDRH r3,[r4,#8] +000066 463a MOV r2,r7 +000068 4631 MOV r1,r6 +00006a 4628 MOV r0,r5 +00006c f7fffffe BL TI1_Config +;;;705 /* Set the Input Capture Prescaler value */ +;;;706 TIM_SetIC1Prescaler(TIMx, TIM_ICInitStruct->TIM_ICPrescaler); +000070 88e1 LDRH r1,[r4,#6] +000072 4628 MOV r0,r5 +000074 f7fffffe BL TIM_SetIC1Prescaler + |L65.120| +;;;707 } +;;;708 } +000078 e8bd81f0 POP {r4-r8,pc} +;;;709 + ENDP + + + AREA ||i.TIM_PrescalerConfig||, CODE, READONLY, ALIGN=1 + + TIM_PrescalerConfig PROC +;;;1181 */ +;;;1182 void TIM_PrescalerConfig(TIM_TypeDef* TIMx, uint16_t Prescaler, uint16_t TIM_PSCReloadMode) +000000 8501 STRH r1,[r0,#0x28] +;;;1183 { +;;;1184 /* Check the parameters */ +;;;1185 assert_param(IS_TIM_ALL_PERIPH(TIMx)); +;;;1186 assert_param(IS_TIM_PRESCALER_RELOAD(TIM_PSCReloadMode)); +;;;1187 /* Set the Prescaler value */ +;;;1188 TIMx->PSC = Prescaler; +;;;1189 /* Set or reset the UG Bit */ +;;;1190 TIMx->EGR = TIM_PSCReloadMode; +000002 8282 STRH r2,[r0,#0x14] +;;;1191 } +000004 4770 BX lr +;;;1192 + ENDP + + + AREA ||i.TIM_SelectCCDMA||, CODE, READONLY, ALIGN=1 + + TIM_SelectCCDMA PROC +;;;1463 */ +;;;1464 void TIM_SelectCCDMA(TIM_TypeDef* TIMx, FunctionalState NewState) +000000 b121 CBZ r1,|L67.12| +;;;1465 { +;;;1466 /* Check the parameters */ +;;;1467 assert_param(IS_TIM_LIST4_PERIPH(TIMx)); +;;;1468 assert_param(IS_FUNCTIONAL_STATE(NewState)); +;;;1469 if (NewState != DISABLE) +;;;1470 { +;;;1471 /* Set the CCDS Bit */ +;;;1472 TIMx->CR2 |= TIM_CR2_CCDS; +000002 8882 LDRH r2,[r0,#4] +000004 f0420208 ORR r2,r2,#8 +000008 8082 STRH r2,[r0,#4] +00000a e004 B |L67.22| + |L67.12| +;;;1473 } +;;;1474 else +;;;1475 { +;;;1476 /* Reset the CCDS Bit */ +;;;1477 TIMx->CR2 &= (uint16_t)~((uint16_t)TIM_CR2_CCDS); +00000c 8882 LDRH r2,[r0,#4] +00000e f64f73f7 MOV r3,#0xfff7 +000012 401a ANDS r2,r2,r3 +000014 8082 STRH r2,[r0,#4] + |L67.22| +;;;1478 } +;;;1479 } +000016 4770 BX lr +;;;1480 + ENDP + + + AREA ||i.TIM_SelectCOM||, CODE, READONLY, ALIGN=1 + + TIM_SelectCOM PROC +;;;1438 */ +;;;1439 void TIM_SelectCOM(TIM_TypeDef* TIMx, FunctionalState NewState) +000000 b121 CBZ r1,|L68.12| +;;;1440 { +;;;1441 /* Check the parameters */ +;;;1442 assert_param(IS_TIM_LIST2_PERIPH(TIMx)); +;;;1443 assert_param(IS_FUNCTIONAL_STATE(NewState)); +;;;1444 if (NewState != DISABLE) +;;;1445 { +;;;1446 /* Set the COM Bit */ +;;;1447 TIMx->CR2 |= TIM_CR2_CCUS; +000002 8882 LDRH r2,[r0,#4] +000004 f0420204 ORR r2,r2,#4 +000008 8082 STRH r2,[r0,#4] +00000a e004 B |L68.22| + |L68.12| +;;;1448 } +;;;1449 else +;;;1450 { +;;;1451 /* Reset the COM Bit */ +;;;1452 TIMx->CR2 &= (uint16_t)~((uint16_t)TIM_CR2_CCUS); +00000c 8882 LDRH r2,[r0,#4] +00000e f64f73fb MOV r3,#0xfffb +000012 401a ANDS r2,r2,r3 +000014 8082 STRH r2,[r0,#4] + |L68.22| +;;;1453 } +;;;1454 } +000016 4770 BX lr +;;;1455 + ENDP + + + AREA ||i.TIM_SelectHallSensor||, CODE, READONLY, ALIGN=1 + + TIM_SelectHallSensor PROC +;;;2149 */ +;;;2150 void TIM_SelectHallSensor(TIM_TypeDef* TIMx, FunctionalState NewState) +000000 b121 CBZ r1,|L69.12| +;;;2151 { +;;;2152 /* Check the parameters */ +;;;2153 assert_param(IS_TIM_LIST6_PERIPH(TIMx)); +;;;2154 assert_param(IS_FUNCTIONAL_STATE(NewState)); +;;;2155 if (NewState != DISABLE) +;;;2156 { +;;;2157 /* Set the TI1S Bit */ +;;;2158 TIMx->CR2 |= TIM_CR2_TI1S; +000002 8882 LDRH r2,[r0,#4] +000004 f0420280 ORR r2,r2,#0x80 +000008 8082 STRH r2,[r0,#4] +00000a e004 B |L69.22| + |L69.12| +;;;2159 } +;;;2160 else +;;;2161 { +;;;2162 /* Reset the TI1S Bit */ +;;;2163 TIMx->CR2 &= (uint16_t)~((uint16_t)TIM_CR2_TI1S); +00000c 8882 LDRH r2,[r0,#4] +00000e f64f737f MOV r3,#0xff7f +000012 401a ANDS r2,r2,r3 +000014 8082 STRH r2,[r0,#4] + |L69.22| +;;;2164 } +;;;2165 } +000016 4770 BX lr +;;;2166 + ENDP + + + AREA ||i.TIM_SelectInputTrigger||, CODE, READONLY, ALIGN=1 + + TIM_SelectInputTrigger PROC +;;;1234 */ +;;;1235 void TIM_SelectInputTrigger(TIM_TypeDef* TIMx, uint16_t TIM_InputTriggerSource) +000000 460a MOV r2,r1 +;;;1236 { +;;;1237 uint16_t tmpsmcr = 0; +000002 2100 MOVS r1,#0 +;;;1238 /* Check the parameters */ +;;;1239 assert_param(IS_TIM_LIST6_PERIPH(TIMx)); +;;;1240 assert_param(IS_TIM_TRIGGER_SELECTION(TIM_InputTriggerSource)); +;;;1241 /* Get the TIMx SMCR register value */ +;;;1242 tmpsmcr = TIMx->SMCR; +000004 8901 LDRH r1,[r0,#8] +;;;1243 /* Reset the TS Bits */ +;;;1244 tmpsmcr &= (uint16_t)(~((uint16_t)TIM_SMCR_TS)); +000006 f64f738f MOV r3,#0xff8f +00000a 4019 ANDS r1,r1,r3 +;;;1245 /* Set the Input Trigger source */ +;;;1246 tmpsmcr |= TIM_InputTriggerSource; +00000c 4311 ORRS r1,r1,r2 +;;;1247 /* Write to TIMx SMCR */ +;;;1248 TIMx->SMCR = tmpsmcr; +00000e 8101 STRH r1,[r0,#8] +;;;1249 } +000010 4770 BX lr +;;;1250 + ENDP + + + AREA ||i.TIM_SelectMasterSlaveMode||, CODE, READONLY, ALIGN=1 + + TIM_SelectMasterSlaveMode PROC +;;;2251 */ +;;;2252 void TIM_SelectMasterSlaveMode(TIM_TypeDef* TIMx, uint16_t TIM_MasterSlaveMode) +000000 8902 LDRH r2,[r0,#8] +;;;2253 { +;;;2254 /* Check the parameters */ +;;;2255 assert_param(IS_TIM_LIST6_PERIPH(TIMx)); +;;;2256 assert_param(IS_TIM_MSM_STATE(TIM_MasterSlaveMode)); +;;;2257 /* Reset the MSM Bit */ +;;;2258 TIMx->SMCR &= (uint16_t)~((uint16_t)TIM_SMCR_MSM); +000002 f64f737f MOV r3,#0xff7f +000006 401a ANDS r2,r2,r3 +000008 8102 STRH r2,[r0,#8] +;;;2259 +;;;2260 /* Set or Reset the MSM Bit */ +;;;2261 TIMx->SMCR |= TIM_MasterSlaveMode; +00000a 8902 LDRH r2,[r0,#8] +00000c 430a ORRS r2,r2,r1 +00000e 8102 STRH r2,[r0,#8] +;;;2262 } +000010 4770 BX lr +;;;2263 + ENDP + + + AREA ||i.TIM_SelectOCxM||, CODE, READONLY, ALIGN=1 + + TIM_SelectOCxM PROC +;;;2050 */ +;;;2051 void TIM_SelectOCxM(TIM_TypeDef* TIMx, uint16_t TIM_Channel, uint16_t TIM_OCMode) +000000 b570 PUSH {r4-r6,lr} +;;;2052 { +000002 4603 MOV r3,r0 +;;;2053 uint32_t tmp = 0; +000004 2000 MOVS r0,#0 +;;;2054 uint16_t tmp1 = 0; +000006 2400 MOVS r4,#0 +;;;2055 +;;;2056 /* Check the parameters */ +;;;2057 assert_param(IS_TIM_LIST8_PERIPH(TIMx)); +;;;2058 assert_param(IS_TIM_CHANNEL(TIM_Channel)); +;;;2059 assert_param(IS_TIM_OCM(TIM_OCMode)); +;;;2060 +;;;2061 tmp = (uint32_t) TIMx; +000008 4618 MOV r0,r3 +;;;2062 tmp += CCMR_Offset; +00000a 3018 ADDS r0,r0,#0x18 +;;;2063 +;;;2064 tmp1 = CCER_CCE_Set << (uint16_t)TIM_Channel; +00000c 2501 MOVS r5,#1 +00000e 408d LSLS r5,r5,r1 +000010 b2ac UXTH r4,r5 +;;;2065 +;;;2066 /* Disable the Channel: Reset the CCxE Bit */ +;;;2067 TIMx->CCER &= (uint16_t) ~tmp1; +000012 8c1d LDRH r5,[r3,#0x20] +000014 43a5 BICS r5,r5,r4 +000016 841d STRH r5,[r3,#0x20] +;;;2068 +;;;2069 if((TIM_Channel == TIM_Channel_1) ||(TIM_Channel == TIM_Channel_3)) +000018 b109 CBZ r1,|L72.30| +00001a 2908 CMP r1,#8 +00001c d109 BNE |L72.50| + |L72.30| +;;;2070 { +;;;2071 tmp += (TIM_Channel>>1); +00001e eb000061 ADD r0,r0,r1,ASR #1 +;;;2072 +;;;2073 /* Reset the OCxM bits in the CCMRx register */ +;;;2074 *(__IO uint32_t *) tmp &= (uint32_t)~((uint32_t)TIM_CCMR1_OC1M); +000022 6805 LDR r5,[r0,#0] +000024 f0250570 BIC r5,r5,#0x70 +000028 6005 STR r5,[r0,#0] +;;;2075 +;;;2076 /* Configure the OCxM bits in the CCMRx register */ +;;;2077 *(__IO uint32_t *) tmp |= TIM_OCMode; +00002a 6805 LDR r5,[r0,#0] +00002c 4315 ORRS r5,r5,r2 +00002e 6005 STR r5,[r0,#0] +000030 e00e B |L72.80| + |L72.50| +;;;2078 } +;;;2079 else +;;;2080 { +;;;2081 tmp += (uint16_t)(TIM_Channel - (uint16_t)4)>> (uint16_t)1; +000032 1f0d SUBS r5,r1,#4 +000034 f3c5054e UBFX r5,r5,#1,#15 +000038 4428 ADD r0,r0,r5 +;;;2082 +;;;2083 /* Reset the OCxM bits in the CCMRx register */ +;;;2084 *(__IO uint32_t *) tmp &= (uint32_t)~((uint32_t)TIM_CCMR1_OC2M); +00003a 6805 LDR r5,[r0,#0] +00003c f42545e0 BIC r5,r5,#0x7000 +000040 6005 STR r5,[r0,#0] +;;;2085 +;;;2086 /* Configure the OCxM bits in the CCMRx register */ +;;;2087 *(__IO uint32_t *) tmp |= (uint16_t)(TIM_OCMode << 8); +000042 6805 LDR r5,[r0,#0] +000044 f64f76ff MOV r6,#0xffff +000048 ea062602 AND r6,r6,r2,LSL #8 +00004c 4335 ORRS r5,r5,r6 +00004e 6005 STR r5,[r0,#0] + |L72.80| +;;;2088 } +;;;2089 } +000050 bd70 POP {r4-r6,pc} +;;;2090 + ENDP + + + AREA ||i.TIM_SelectOnePulseMode||, CODE, READONLY, ALIGN=1 + + TIM_SelectOnePulseMode PROC +;;;2175 */ +;;;2176 void TIM_SelectOnePulseMode(TIM_TypeDef* TIMx, uint16_t TIM_OPMode) +000000 8802 LDRH r2,[r0,#0] +;;;2177 { +;;;2178 /* Check the parameters */ +;;;2179 assert_param(IS_TIM_ALL_PERIPH(TIMx)); +;;;2180 assert_param(IS_TIM_OPM_MODE(TIM_OPMode)); +;;;2181 /* Reset the OPM Bit */ +;;;2182 TIMx->CR1 &= (uint16_t)~((uint16_t)TIM_CR1_OPM); +000002 f64f73f7 MOV r3,#0xfff7 +000006 401a ANDS r2,r2,r3 +000008 8002 STRH r2,[r0,#0] +;;;2183 /* Configure the OPM Mode */ +;;;2184 TIMx->CR1 |= TIM_OPMode; +00000a 8802 LDRH r2,[r0,#0] +00000c 430a ORRS r2,r2,r1 +00000e 8002 STRH r2,[r0,#0] +;;;2185 } +000010 4770 BX lr +;;;2186 + ENDP + + + AREA ||i.TIM_SelectOutputTrigger||, CODE, READONLY, ALIGN=1 + + TIM_SelectOutputTrigger PROC +;;;2207 */ +;;;2208 void TIM_SelectOutputTrigger(TIM_TypeDef* TIMx, uint16_t TIM_TRGOSource) +000000 8882 LDRH r2,[r0,#4] +;;;2209 { +;;;2210 /* Check the parameters */ +;;;2211 assert_param(IS_TIM_LIST7_PERIPH(TIMx)); +;;;2212 assert_param(IS_TIM_TRGO_SOURCE(TIM_TRGOSource)); +;;;2213 /* Reset the MMS Bits */ +;;;2214 TIMx->CR2 &= (uint16_t)~((uint16_t)TIM_CR2_MMS); +000002 f64f738f MOV r3,#0xff8f +000006 401a ANDS r2,r2,r3 +000008 8082 STRH r2,[r0,#4] +;;;2215 /* Select the TRGO source */ +;;;2216 TIMx->CR2 |= TIM_TRGOSource; +00000a 8882 LDRH r2,[r0,#4] +00000c 430a ORRS r2,r2,r1 +00000e 8082 STRH r2,[r0,#4] +;;;2217 } +000010 4770 BX lr +;;;2218 + ENDP + + + AREA ||i.TIM_SelectSlaveMode||, CODE, READONLY, ALIGN=1 + + TIM_SelectSlaveMode PROC +;;;2230 */ +;;;2231 void TIM_SelectSlaveMode(TIM_TypeDef* TIMx, uint16_t TIM_SlaveMode) +000000 8902 LDRH r2,[r0,#8] +;;;2232 { +;;;2233 /* Check the parameters */ +;;;2234 assert_param(IS_TIM_LIST6_PERIPH(TIMx)); +;;;2235 assert_param(IS_TIM_SLAVE_MODE(TIM_SlaveMode)); +;;;2236 /* Reset the SMS Bits */ +;;;2237 TIMx->SMCR &= (uint16_t)~((uint16_t)TIM_SMCR_SMS); +000002 f64f73f8 MOV r3,#0xfff8 +000006 401a ANDS r2,r2,r3 +000008 8102 STRH r2,[r0,#8] +;;;2238 /* Select the Slave Mode */ +;;;2239 TIMx->SMCR |= TIM_SlaveMode; +00000a 8902 LDRH r2,[r0,#8] +00000c 430a ORRS r2,r2,r1 +00000e 8102 STRH r2,[r0,#8] +;;;2240 } +000010 4770 BX lr +;;;2241 + ENDP + + + AREA ||i.TIM_SetAutoreload||, CODE, READONLY, ALIGN=1 + + TIM_SetAutoreload PROC +;;;2283 */ +;;;2284 void TIM_SetAutoreload(TIM_TypeDef* TIMx, uint16_t Autoreload) +000000 8581 STRH r1,[r0,#0x2c] +;;;2285 { +;;;2286 /* Check the parameters */ +;;;2287 assert_param(IS_TIM_ALL_PERIPH(TIMx)); +;;;2288 /* Set the Autoreload Register value */ +;;;2289 TIMx->ARR = Autoreload; +;;;2290 } +000002 4770 BX lr +;;;2291 + ENDP + + + AREA ||i.TIM_SetClockDivision||, CODE, READONLY, ALIGN=1 + + TIM_SetClockDivision PROC +;;;2446 */ +;;;2447 void TIM_SetClockDivision(TIM_TypeDef* TIMx, uint16_t TIM_CKD) +000000 8802 LDRH r2,[r0,#0] +;;;2448 { +;;;2449 /* Check the parameters */ +;;;2450 assert_param(IS_TIM_LIST8_PERIPH(TIMx)); +;;;2451 assert_param(IS_TIM_CKD_DIV(TIM_CKD)); +;;;2452 /* Reset the CKD Bits */ +;;;2453 TIMx->CR1 &= (uint16_t)~((uint16_t)TIM_CR1_CKD); +000002 f64f43ff MOV r3,#0xfcff +000006 401a ANDS r2,r2,r3 +000008 8002 STRH r2,[r0,#0] +;;;2454 /* Set the CKD value */ +;;;2455 TIMx->CR1 |= TIM_CKD; +00000a 8802 LDRH r2,[r0,#0] +00000c 430a ORRS r2,r2,r1 +00000e 8002 STRH r2,[r0,#0] +;;;2456 } +000010 4770 BX lr +;;;2457 + ENDP + + + AREA ||i.TIM_SetCompare1||, CODE, READONLY, ALIGN=1 + + TIM_SetCompare1 PROC +;;;2297 */ +;;;2298 void TIM_SetCompare1(TIM_TypeDef* TIMx, uint16_t Compare1) +000000 8681 STRH r1,[r0,#0x34] +;;;2299 { +;;;2300 /* Check the parameters */ +;;;2301 assert_param(IS_TIM_LIST8_PERIPH(TIMx)); +;;;2302 /* Set the Capture Compare1 Register value */ +;;;2303 TIMx->CCR1 = Compare1; +;;;2304 } +000002 4770 BX lr +;;;2305 + ENDP + + + AREA ||i.TIM_SetCompare2||, CODE, READONLY, ALIGN=1 + + TIM_SetCompare2 PROC +;;;2311 */ +;;;2312 void TIM_SetCompare2(TIM_TypeDef* TIMx, uint16_t Compare2) +000000 8701 STRH r1,[r0,#0x38] +;;;2313 { +;;;2314 /* Check the parameters */ +;;;2315 assert_param(IS_TIM_LIST6_PERIPH(TIMx)); +;;;2316 /* Set the Capture Compare2 Register value */ +;;;2317 TIMx->CCR2 = Compare2; +;;;2318 } +000002 4770 BX lr +;;;2319 + ENDP + + + AREA ||i.TIM_SetCompare3||, CODE, READONLY, ALIGN=1 + + TIM_SetCompare3 PROC +;;;2325 */ +;;;2326 void TIM_SetCompare3(TIM_TypeDef* TIMx, uint16_t Compare3) +000000 8781 STRH r1,[r0,#0x3c] +;;;2327 { +;;;2328 /* Check the parameters */ +;;;2329 assert_param(IS_TIM_LIST3_PERIPH(TIMx)); +;;;2330 /* Set the Capture Compare3 Register value */ +;;;2331 TIMx->CCR3 = Compare3; +;;;2332 } +000002 4770 BX lr +;;;2333 + ENDP + + + AREA ||i.TIM_SetCompare4||, CODE, READONLY, ALIGN=1 + + TIM_SetCompare4 PROC +;;;2339 */ +;;;2340 void TIM_SetCompare4(TIM_TypeDef* TIMx, uint16_t Compare4) +000000 f8a01040 STRH r1,[r0,#0x40] +;;;2341 { +;;;2342 /* Check the parameters */ +;;;2343 assert_param(IS_TIM_LIST3_PERIPH(TIMx)); +;;;2344 /* Set the Capture Compare4 Register value */ +;;;2345 TIMx->CCR4 = Compare4; +;;;2346 } +000004 4770 BX lr +;;;2347 + ENDP + + + AREA ||i.TIM_SetCounter||, CODE, READONLY, ALIGN=1 + + TIM_SetCounter PROC +;;;2269 */ +;;;2270 void TIM_SetCounter(TIM_TypeDef* TIMx, uint16_t Counter) +000000 8481 STRH r1,[r0,#0x24] +;;;2271 { +;;;2272 /* Check the parameters */ +;;;2273 assert_param(IS_TIM_ALL_PERIPH(TIMx)); +;;;2274 /* Set the Counter Register value */ +;;;2275 TIMx->CNT = Counter; +;;;2276 } +000002 4770 BX lr +;;;2277 + ENDP + + + AREA ||i.TIM_SetIC1Prescaler||, CODE, READONLY, ALIGN=1 + + TIM_SetIC1Prescaler PROC +;;;2358 */ +;;;2359 void TIM_SetIC1Prescaler(TIM_TypeDef* TIMx, uint16_t TIM_ICPSC) +000000 8b02 LDRH r2,[r0,#0x18] +;;;2360 { +;;;2361 /* Check the parameters */ +;;;2362 assert_param(IS_TIM_LIST8_PERIPH(TIMx)); +;;;2363 assert_param(IS_TIM_IC_PRESCALER(TIM_ICPSC)); +;;;2364 /* Reset the IC1PSC Bits */ +;;;2365 TIMx->CCMR1 &= (uint16_t)~((uint16_t)TIM_CCMR1_IC1PSC); +000002 f64f73f3 MOV r3,#0xfff3 +000006 401a ANDS r2,r2,r3 +000008 8302 STRH r2,[r0,#0x18] +;;;2366 /* Set the IC1PSC value */ +;;;2367 TIMx->CCMR1 |= TIM_ICPSC; +00000a 8b02 LDRH r2,[r0,#0x18] +00000c 430a ORRS r2,r2,r1 +00000e 8302 STRH r2,[r0,#0x18] +;;;2368 } +000010 4770 BX lr +;;;2369 + ENDP + + + AREA ||i.TIM_SetIC2Prescaler||, CODE, READONLY, ALIGN=1 + + TIM_SetIC2Prescaler PROC +;;;2380 */ +;;;2381 void TIM_SetIC2Prescaler(TIM_TypeDef* TIMx, uint16_t TIM_ICPSC) +000000 8b02 LDRH r2,[r0,#0x18] +;;;2382 { +;;;2383 /* Check the parameters */ +;;;2384 assert_param(IS_TIM_LIST6_PERIPH(TIMx)); +;;;2385 assert_param(IS_TIM_IC_PRESCALER(TIM_ICPSC)); +;;;2386 /* Reset the IC2PSC Bits */ +;;;2387 TIMx->CCMR1 &= (uint16_t)~((uint16_t)TIM_CCMR1_IC2PSC); +000002 f24f33ff MOV r3,#0xf3ff +000006 401a ANDS r2,r2,r3 +000008 8302 STRH r2,[r0,#0x18] +;;;2388 /* Set the IC2PSC value */ +;;;2389 TIMx->CCMR1 |= (uint16_t)(TIM_ICPSC << 8); +00000a 8b02 LDRH r2,[r0,#0x18] +00000c f64f73ff MOV r3,#0xffff +000010 ea032301 AND r3,r3,r1,LSL #8 +000014 431a ORRS r2,r2,r3 +000016 8302 STRH r2,[r0,#0x18] +;;;2390 } +000018 4770 BX lr +;;;2391 + ENDP + + + AREA ||i.TIM_SetIC3Prescaler||, CODE, READONLY, ALIGN=1 + + TIM_SetIC3Prescaler PROC +;;;2402 */ +;;;2403 void TIM_SetIC3Prescaler(TIM_TypeDef* TIMx, uint16_t TIM_ICPSC) +000000 8b82 LDRH r2,[r0,#0x1c] +;;;2404 { +;;;2405 /* Check the parameters */ +;;;2406 assert_param(IS_TIM_LIST3_PERIPH(TIMx)); +;;;2407 assert_param(IS_TIM_IC_PRESCALER(TIM_ICPSC)); +;;;2408 /* Reset the IC3PSC Bits */ +;;;2409 TIMx->CCMR2 &= (uint16_t)~((uint16_t)TIM_CCMR2_IC3PSC); +000002 f64f73f3 MOV r3,#0xfff3 +000006 401a ANDS r2,r2,r3 +000008 8382 STRH r2,[r0,#0x1c] +;;;2410 /* Set the IC3PSC value */ +;;;2411 TIMx->CCMR2 |= TIM_ICPSC; +00000a 8b82 LDRH r2,[r0,#0x1c] +00000c 430a ORRS r2,r2,r1 +00000e 8382 STRH r2,[r0,#0x1c] +;;;2412 } +000010 4770 BX lr +;;;2413 + ENDP + + + AREA ||i.TIM_SetIC4Prescaler||, CODE, READONLY, ALIGN=1 + + TIM_SetIC4Prescaler PROC +;;;2424 */ +;;;2425 void TIM_SetIC4Prescaler(TIM_TypeDef* TIMx, uint16_t TIM_ICPSC) +000000 8b82 LDRH r2,[r0,#0x1c] +;;;2426 { +;;;2427 /* Check the parameters */ +;;;2428 assert_param(IS_TIM_LIST3_PERIPH(TIMx)); +;;;2429 assert_param(IS_TIM_IC_PRESCALER(TIM_ICPSC)); +;;;2430 /* Reset the IC4PSC Bits */ +;;;2431 TIMx->CCMR2 &= (uint16_t)~((uint16_t)TIM_CCMR2_IC4PSC); +000002 f24f33ff MOV r3,#0xf3ff +000006 401a ANDS r2,r2,r3 +000008 8382 STRH r2,[r0,#0x1c] +;;;2432 /* Set the IC4PSC value */ +;;;2433 TIMx->CCMR2 |= (uint16_t)(TIM_ICPSC << 8); +00000a 8b82 LDRH r2,[r0,#0x1c] +00000c f64f73ff MOV r3,#0xffff +000010 ea032301 AND r3,r3,r1,LSL #8 +000014 431a ORRS r2,r2,r3 +000016 8382 STRH r2,[r0,#0x1c] +;;;2434 } +000018 4770 BX lr +;;;2435 + ENDP + + + AREA ||i.TIM_TIxExternalClockConfig||, CODE, READONLY, ALIGN=1 + + TIM_TIxExternalClockConfig PROC +;;;1040 */ +;;;1041 void TIM_TIxExternalClockConfig(TIM_TypeDef* TIMx, uint16_t TIM_TIxExternalCLKSource, +000000 e92d41f0 PUSH {r4-r8,lr} +;;;1042 uint16_t TIM_ICPolarity, uint16_t ICFilter) +;;;1043 { +000004 4604 MOV r4,r0 +000006 460d MOV r5,r1 +000008 4616 MOV r6,r2 +00000a 461f MOV r7,r3 +;;;1044 /* Check the parameters */ +;;;1045 assert_param(IS_TIM_LIST6_PERIPH(TIMx)); +;;;1046 assert_param(IS_TIM_TIXCLK_SOURCE(TIM_TIxExternalCLKSource)); +;;;1047 assert_param(IS_TIM_IC_POLARITY(TIM_ICPolarity)); +;;;1048 assert_param(IS_TIM_IC_FILTER(ICFilter)); +;;;1049 /* Configure the Timer Input Clock Source */ +;;;1050 if (TIM_TIxExternalCLKSource == TIM_TIxExternalCLK1Source_TI2) +00000c 2d60 CMP r5,#0x60 +00000e d106 BNE |L87.30| +;;;1051 { +;;;1052 TI2_Config(TIMx, TIM_ICPolarity, TIM_ICSelection_DirectTI, ICFilter); +000010 463b MOV r3,r7 +000012 2201 MOVS r2,#1 +000014 4631 MOV r1,r6 +000016 4620 MOV r0,r4 +000018 f7fffffe BL TI2_Config +00001c e005 B |L87.42| + |L87.30| +;;;1053 } +;;;1054 else +;;;1055 { +;;;1056 TI1_Config(TIMx, TIM_ICPolarity, TIM_ICSelection_DirectTI, ICFilter); +00001e 463b MOV r3,r7 +000020 2201 MOVS r2,#1 +000022 4631 MOV r1,r6 +000024 4620 MOV r0,r4 +000026 f7fffffe BL TI1_Config + |L87.42| +;;;1057 } +;;;1058 /* Select the Trigger source */ +;;;1059 TIM_SelectInputTrigger(TIMx, TIM_TIxExternalCLKSource); +00002a 4629 MOV r1,r5 +00002c 4620 MOV r0,r4 +00002e f7fffffe BL TIM_SelectInputTrigger +;;;1060 /* Select the External clock mode1 */ +;;;1061 TIMx->SMCR |= TIM_SlaveMode_External1; +000032 8920 LDRH r0,[r4,#8] +000034 f0400007 ORR r0,r0,#7 +000038 8120 STRH r0,[r4,#8] +;;;1062 } +00003a e8bd81f0 POP {r4-r8,pc} +;;;1063 + ENDP + + + AREA ||i.TIM_TimeBaseInit||, CODE, READONLY, ALIGN=2 + + TIM_TimeBaseInit PROC +;;;231 */ +;;;232 void TIM_TimeBaseInit(TIM_TypeDef* TIMx, TIM_TimeBaseInitTypeDef* TIM_TimeBaseInitStruct) +000000 2200 MOVS r2,#0 +;;;233 { +;;;234 uint16_t tmpcr1 = 0; +;;;235 +;;;236 /* Check the parameters */ +;;;237 assert_param(IS_TIM_ALL_PERIPH(TIMx)); +;;;238 assert_param(IS_TIM_COUNTER_MODE(TIM_TimeBaseInitStruct->TIM_CounterMode)); +;;;239 assert_param(IS_TIM_CKD_DIV(TIM_TimeBaseInitStruct->TIM_ClockDivision)); +;;;240 +;;;241 tmpcr1 = TIMx->CR1; +000002 8802 LDRH r2,[r0,#0] +;;;242 +;;;243 if((TIMx == TIM1) || (TIMx == TIM8)|| (TIMx == TIM2) || (TIMx == TIM3)|| +000004 4b1d LDR r3,|L88.124| +000006 4298 CMP r0,r3 +000008 d00e BEQ |L88.40| +00000a 4b1d LDR r3,|L88.128| +00000c 4298 CMP r0,r3 +00000e d00b BEQ |L88.40| +000010 f1b04f80 CMP r0,#0x40000000 +000014 d008 BEQ |L88.40| +000016 4b1b LDR r3,|L88.132| +000018 4298 CMP r0,r3 +00001a d005 BEQ |L88.40| +;;;244 (TIMx == TIM4) || (TIMx == TIM5)) +00001c 4b1a LDR r3,|L88.136| +00001e 4298 CMP r0,r3 +000020 d002 BEQ |L88.40| +000022 4b1a LDR r3,|L88.140| +000024 4298 CMP r0,r3 +000026 d104 BNE |L88.50| + |L88.40| +;;;245 { +;;;246 /* Select the Counter Mode */ +;;;247 tmpcr1 &= (uint16_t)(~((uint16_t)(TIM_CR1_DIR | TIM_CR1_CMS))); +000028 f64f738f MOV r3,#0xff8f +00002c 401a ANDS r2,r2,r3 +;;;248 tmpcr1 |= (uint32_t)TIM_TimeBaseInitStruct->TIM_CounterMode; +00002e 884b LDRH r3,[r1,#2] +000030 431a ORRS r2,r2,r3 + |L88.50| +;;;249 } +;;;250 +;;;251 if((TIMx != TIM6) && (TIMx != TIM7)) +000032 4b17 LDR r3,|L88.144| +000034 4298 CMP r0,r3 +000036 d007 BEQ |L88.72| +000038 4b16 LDR r3,|L88.148| +00003a 4298 CMP r0,r3 +00003c d004 BEQ |L88.72| +;;;252 { +;;;253 /* Set the clock division */ +;;;254 tmpcr1 &= (uint16_t)(~((uint16_t)TIM_CR1_CKD)); +00003e f64f43ff MOV r3,#0xfcff +000042 401a ANDS r2,r2,r3 +;;;255 tmpcr1 |= (uint32_t)TIM_TimeBaseInitStruct->TIM_ClockDivision; +000044 88cb LDRH r3,[r1,#6] +000046 431a ORRS r2,r2,r3 + |L88.72| +;;;256 } +;;;257 +;;;258 TIMx->CR1 = tmpcr1; +000048 8002 STRH r2,[r0,#0] +;;;259 +;;;260 /* Set the Autoreload value */ +;;;261 TIMx->ARR = TIM_TimeBaseInitStruct->TIM_Period ; +00004a 888b LDRH r3,[r1,#4] +00004c 8583 STRH r3,[r0,#0x2c] +;;;262 +;;;263 /* Set the Prescaler value */ +;;;264 TIMx->PSC = TIM_TimeBaseInitStruct->TIM_Prescaler; +00004e 880b LDRH r3,[r1,#0] +000050 8503 STRH r3,[r0,#0x28] +;;;265 +;;;266 if ((TIMx == TIM1) || (TIMx == TIM8)|| (TIMx == TIM15)|| (TIMx == TIM16) || (TIMx == TIM17)) +000052 4b0a LDR r3,|L88.124| +000054 4298 CMP r0,r3 +000056 d00b BEQ |L88.112| +000058 4b09 LDR r3,|L88.128| +00005a 4298 CMP r0,r3 +00005c d008 BEQ |L88.112| +00005e 4b0e LDR r3,|L88.152| +000060 4298 CMP r0,r3 +000062 d005 BEQ |L88.112| +000064 4b0d LDR r3,|L88.156| +000066 4298 CMP r0,r3 +000068 d002 BEQ |L88.112| +00006a 4b0d LDR r3,|L88.160| +00006c 4298 CMP r0,r3 +00006e d101 BNE |L88.116| + |L88.112| +;;;267 { +;;;268 /* Set the Repetition Counter value */ +;;;269 TIMx->RCR = TIM_TimeBaseInitStruct->TIM_RepetitionCounter; +000070 7a0b LDRB r3,[r1,#8] +000072 8603 STRH r3,[r0,#0x30] + |L88.116| +;;;270 } +;;;271 +;;;272 /* Generate an update event to reload the Prescaler and the Repetition counter +;;;273 values immediately */ +;;;274 TIMx->EGR = TIM_PSCReloadMode_Immediate; +000074 2301 MOVS r3,#1 +000076 8283 STRH r3,[r0,#0x14] +;;;275 } +000078 4770 BX lr +;;;276 + ENDP + +00007a 0000 DCW 0x0000 + |L88.124| + DCD 0x40012c00 + |L88.128| + DCD 0x40013400 + |L88.132| + DCD 0x40000400 + |L88.136| + DCD 0x40000800 + |L88.140| + DCD 0x40000c00 + |L88.144| + DCD 0x40001000 + |L88.148| + DCD 0x40001400 + |L88.152| + DCD 0x40014000 + |L88.156| + DCD 0x40014400 + |L88.160| + DCD 0x40014800 + + AREA ||i.TIM_TimeBaseStructInit||, CODE, READONLY, ALIGN=1 + + TIM_TimeBaseStructInit PROC +;;;741 */ +;;;742 void TIM_TimeBaseStructInit(TIM_TimeBaseInitTypeDef* TIM_TimeBaseInitStruct) +000000 f64f71ff MOV r1,#0xffff +;;;743 { +;;;744 /* Set the default configuration */ +;;;745 TIM_TimeBaseInitStruct->TIM_Period = 0xFFFF; +000004 8081 STRH r1,[r0,#4] +;;;746 TIM_TimeBaseInitStruct->TIM_Prescaler = 0x0000; +000006 2100 MOVS r1,#0 +000008 8001 STRH r1,[r0,#0] +;;;747 TIM_TimeBaseInitStruct->TIM_ClockDivision = TIM_CKD_DIV1; +00000a 80c1 STRH r1,[r0,#6] +;;;748 TIM_TimeBaseInitStruct->TIM_CounterMode = TIM_CounterMode_Up; +00000c 8041 STRH r1,[r0,#2] +;;;749 TIM_TimeBaseInitStruct->TIM_RepetitionCounter = 0x0000; +00000e 7201 STRB r1,[r0,#8] +;;;750 } +000010 4770 BX lr +;;;751 + ENDP + + + AREA ||i.TIM_UpdateDisableConfig||, CODE, READONLY, ALIGN=1 + + TIM_UpdateDisableConfig PROC +;;;2097 */ +;;;2098 void TIM_UpdateDisableConfig(TIM_TypeDef* TIMx, FunctionalState NewState) +000000 b121 CBZ r1,|L90.12| +;;;2099 { +;;;2100 /* Check the parameters */ +;;;2101 assert_param(IS_TIM_ALL_PERIPH(TIMx)); +;;;2102 assert_param(IS_FUNCTIONAL_STATE(NewState)); +;;;2103 if (NewState != DISABLE) +;;;2104 { +;;;2105 /* Set the Update Disable Bit */ +;;;2106 TIMx->CR1 |= TIM_CR1_UDIS; +000002 8802 LDRH r2,[r0,#0] +000004 f0420202 ORR r2,r2,#2 +000008 8002 STRH r2,[r0,#0] +00000a e004 B |L90.22| + |L90.12| +;;;2107 } +;;;2108 else +;;;2109 { +;;;2110 /* Reset the Update Disable Bit */ +;;;2111 TIMx->CR1 &= (uint16_t)~((uint16_t)TIM_CR1_UDIS); +00000c 8802 LDRH r2,[r0,#0] +00000e f64f73fd MOV r3,#0xfffd +000012 401a ANDS r2,r2,r3 +000014 8002 STRH r2,[r0,#0] + |L90.22| +;;;2112 } +;;;2113 } +000016 4770 BX lr +;;;2114 + ENDP + + + AREA ||i.TIM_UpdateRequestConfig||, CODE, READONLY, ALIGN=1 + + TIM_UpdateRequestConfig PROC +;;;2125 */ +;;;2126 void TIM_UpdateRequestConfig(TIM_TypeDef* TIMx, uint16_t TIM_UpdateSource) +000000 b121 CBZ r1,|L91.12| +;;;2127 { +;;;2128 /* Check the parameters */ +;;;2129 assert_param(IS_TIM_ALL_PERIPH(TIMx)); +;;;2130 assert_param(IS_TIM_UPDATE_SOURCE(TIM_UpdateSource)); +;;;2131 if (TIM_UpdateSource != TIM_UpdateSource_Global) +;;;2132 { +;;;2133 /* Set the URS Bit */ +;;;2134 TIMx->CR1 |= TIM_CR1_URS; +000002 8802 LDRH r2,[r0,#0] +000004 f0420204 ORR r2,r2,#4 +000008 8002 STRH r2,[r0,#0] +00000a e004 B |L91.22| + |L91.12| +;;;2135 } +;;;2136 else +;;;2137 { +;;;2138 /* Reset the URS Bit */ +;;;2139 TIMx->CR1 &= (uint16_t)~((uint16_t)TIM_CR1_URS); +00000c 8802 LDRH r2,[r0,#0] +00000e f64f73fb MOV r3,#0xfffb +000012 401a ANDS r2,r2,r3 +000014 8002 STRH r2,[r0,#0] + |L91.22| +;;;2140 } +;;;2141 } +000016 4770 BX lr +;;;2142 + ENDP + + +;*** Start embedded assembler *** + +#line 1 "..\\..\\Libraries\\STM32F10x_StdPeriph_Driver\\src\\stm32f10x_tim.c" + AREA ||.rev16_text||, CODE + THUMB + EXPORT |__asm___15_stm32f10x_tim_c_c458916b____REV16| +#line 114 "..\\..\\Libraries\\CMSIS\\Include\\core_cmInstr.h" +|__asm___15_stm32f10x_tim_c_c458916b____REV16| PROC +#line 115 + + rev16 r0, r0 + bx lr + ENDP + AREA ||.revsh_text||, CODE + THUMB + EXPORT |__asm___15_stm32f10x_tim_c_c458916b____REVSH| +#line 128 +|__asm___15_stm32f10x_tim_c_c458916b____REVSH| PROC +#line 129 + + revsh r0, r0 + bx lr + ENDP + +;*** End embedded assembler *** diff --git a/Project/MDK-ARM/Flash/List/stm32f10x_usart.txt b/Project/MDK-ARM/Flash/List/stm32f10x_usart.txt new file mode 100644 index 0000000..addeb72 --- /dev/null +++ b/Project/MDK-ARM/Flash/List/stm32f10x_usart.txt @@ -0,0 +1,1316 @@ +; generated by Component: ARM Compiler 5.06 update 7 (build 960) Tool: ArmCC [4d365d] +; commandline ArmCC [--list --split_sections --debug -c --asm --interleave -o.\flash\obj\stm32f10x_usart.o --asm_dir=.\Flash\List\ --list_dir=.\Flash\List\ --depend=.\flash\obj\stm32f10x_usart.d --cpu=Cortex-M3 --apcs=interwork -O0 --diag_suppress=9931,870 -I..\..\Libraries\CMSIS\Device\ST\STM32F10x\Include -I..\..\Libraries\STM32F10x_StdPeriph_Driver\inc -I..\..\Libraries\STM32_USB-FS-Device_Driver\inc -I..\..\Libraries\CMSIS\Include -I..\..\User\bsp -I..\..\User\bsp\inc -I..\..\User\app\inc -I..\..\User -IC:\Users\w1619\AppData\Local\Arm\Packs\Keil\STM32F1xx_DFP\2.4.1\Device\Include -D__MICROLIB -D__UVISION_VERSION=538 -DSTM32F10X_HD -DUSE_STDPERIPH_DRIVER -DSTM32F10X_HD --omf_browse=.\flash\obj\stm32f10x_usart.crf ..\..\Libraries\STM32F10x_StdPeriph_Driver\src\stm32f10x_usart.c] + THUMB + + AREA ||i.USART_ClearFlag||, CODE, READONLY, ALIGN=1 + + USART_ClearFlag PROC +;;;928 */ +;;;929 void USART_ClearFlag(USART_TypeDef* USARTx, uint16_t USART_FLAG) +000000 f4017200 AND r2,r1,#0x200 +;;;930 { +;;;931 /* Check the parameters */ +;;;932 assert_param(IS_USART_ALL_PERIPH(USARTx)); +;;;933 assert_param(IS_USART_CLEAR_FLAG(USART_FLAG)); +;;;934 /* The CTS flag is not available for UART4 and UART5 */ +;;;935 if ((USART_FLAG & USART_FLAG_CTS) == USART_FLAG_CTS) +000004 f5b27f00 CMP r2,#0x200 +000008 d100 BNE |L1.12| +;;;936 { +;;;937 assert_param(IS_USART_123_PERIPH(USARTx)); +00000a bf00 NOP + |L1.12| +;;;938 } +;;;939 +;;;940 USARTx->SR = (uint16_t)~USART_FLAG; +00000c 43ca MVNS r2,r1 +00000e 8002 STRH r2,[r0,#0] +;;;941 } +000010 4770 BX lr +;;;942 + ENDP + + + AREA ||i.USART_ClearITPendingBit||, CODE, READONLY, ALIGN=1 + + USART_ClearITPendingBit PROC +;;;1036 */ +;;;1037 void USART_ClearITPendingBit(USART_TypeDef* USARTx, uint16_t USART_IT) +000000 b510 PUSH {r4,lr} +;;;1038 { +;;;1039 uint16_t bitpos = 0x00, itmask = 0x00; +000002 2200 MOVS r2,#0 +000004 2300 MOVS r3,#0 +;;;1040 /* Check the parameters */ +;;;1041 assert_param(IS_USART_ALL_PERIPH(USARTx)); +;;;1042 assert_param(IS_USART_CLEAR_IT(USART_IT)); +;;;1043 /* The CTS interrupt is not available for UART4 and UART5 */ +;;;1044 if (USART_IT == USART_IT_CTS) +000006 f640146a MOV r4,#0x96a +00000a 42a1 CMP r1,r4 +00000c d100 BNE |L2.16| +;;;1045 { +;;;1046 assert_param(IS_USART_123_PERIPH(USARTx)); +00000e bf00 NOP + |L2.16| +;;;1047 } +;;;1048 +;;;1049 bitpos = USART_IT >> 0x08; +000010 120a ASRS r2,r1,#8 +;;;1050 itmask = ((uint16_t)0x01 << (uint16_t)bitpos); +000012 2401 MOVS r4,#1 +000014 4094 LSLS r4,r4,r2 +000016 b2a3 UXTH r3,r4 +;;;1051 USARTx->SR = (uint16_t)~itmask; +000018 43dc MVNS r4,r3 +00001a 8004 STRH r4,[r0,#0] +;;;1052 } +00001c bd10 POP {r4,pc} +;;;1053 /** + ENDP + + + AREA ||i.USART_ClockInit||, CODE, READONLY, ALIGN=1 + + USART_ClockInit PROC +;;;307 */ +;;;308 void USART_ClockInit(USART_TypeDef* USARTx, USART_ClockInitTypeDef* USART_ClockInitStruct) +000000 b510 PUSH {r4,lr} +;;;309 { +000002 4602 MOV r2,r0 +;;;310 uint32_t tmpreg = 0x00; +000004 2000 MOVS r0,#0 +;;;311 /* Check the parameters */ +;;;312 assert_param(IS_USART_123_PERIPH(USARTx)); +;;;313 assert_param(IS_USART_CLOCK(USART_ClockInitStruct->USART_Clock)); +;;;314 assert_param(IS_USART_CPOL(USART_ClockInitStruct->USART_CPOL)); +;;;315 assert_param(IS_USART_CPHA(USART_ClockInitStruct->USART_CPHA)); +;;;316 assert_param(IS_USART_LASTBIT(USART_ClockInitStruct->USART_LastBit)); +;;;317 +;;;318 /*---------------------------- USART CR2 Configuration -----------------------*/ +;;;319 tmpreg = USARTx->CR2; +000006 8a10 LDRH r0,[r2,#0x10] +;;;320 /* Clear CLKEN, CPOL, CPHA and LBCL bits */ +;;;321 tmpreg &= CR2_CLOCK_CLEAR_Mask; +000008 f24f03ff MOV r3,#0xf0ff +00000c 4018 ANDS r0,r0,r3 +;;;322 /* Configure the USART Clock, CPOL, CPHA and LastBit ------------*/ +;;;323 /* Set CLKEN bit according to USART_Clock value */ +;;;324 /* Set CPOL bit according to USART_CPOL value */ +;;;325 /* Set CPHA bit according to USART_CPHA value */ +;;;326 /* Set LBCL bit according to USART_LastBit value */ +;;;327 tmpreg |= (uint32_t)USART_ClockInitStruct->USART_Clock | USART_ClockInitStruct->USART_CPOL | +00000e 880b LDRH r3,[r1,#0] +000010 884c LDRH r4,[r1,#2] +000012 4323 ORRS r3,r3,r4 +000014 888c LDRH r4,[r1,#4] +000016 4323 ORRS r3,r3,r4 +000018 88cc LDRH r4,[r1,#6] +00001a 4323 ORRS r3,r3,r4 +00001c 4318 ORRS r0,r0,r3 +;;;328 USART_ClockInitStruct->USART_CPHA | USART_ClockInitStruct->USART_LastBit; +;;;329 /* Write to USART CR2 */ +;;;330 USARTx->CR2 = (uint16_t)tmpreg; +00001e 8210 STRH r0,[r2,#0x10] +;;;331 } +000020 bd10 POP {r4,pc} +;;;332 + ENDP + + + AREA ||i.USART_ClockStructInit||, CODE, READONLY, ALIGN=1 + + USART_ClockStructInit PROC +;;;338 */ +;;;339 void USART_ClockStructInit(USART_ClockInitTypeDef* USART_ClockInitStruct) +000000 2100 MOVS r1,#0 +;;;340 { +;;;341 /* USART_ClockInitStruct members default value */ +;;;342 USART_ClockInitStruct->USART_Clock = USART_Clock_Disable; +000002 8001 STRH r1,[r0,#0] +;;;343 USART_ClockInitStruct->USART_CPOL = USART_CPOL_Low; +000004 8041 STRH r1,[r0,#2] +;;;344 USART_ClockInitStruct->USART_CPHA = USART_CPHA_1Edge; +000006 8081 STRH r1,[r0,#4] +;;;345 USART_ClockInitStruct->USART_LastBit = USART_LastBit_Disable; +000008 80c1 STRH r1,[r0,#6] +;;;346 } +00000a 4770 BX lr +;;;347 + ENDP + + + AREA ||i.USART_Cmd||, CODE, READONLY, ALIGN=1 + + USART_Cmd PROC +;;;356 */ +;;;357 void USART_Cmd(USART_TypeDef* USARTx, FunctionalState NewState) +000000 b121 CBZ r1,|L5.12| +;;;358 { +;;;359 /* Check the parameters */ +;;;360 assert_param(IS_USART_ALL_PERIPH(USARTx)); +;;;361 assert_param(IS_FUNCTIONAL_STATE(NewState)); +;;;362 +;;;363 if (NewState != DISABLE) +;;;364 { +;;;365 /* Enable the selected USART by setting the UE bit in the CR1 register */ +;;;366 USARTx->CR1 |= CR1_UE_Set; +000002 8982 LDRH r2,[r0,#0xc] +000004 f4425200 ORR r2,r2,#0x2000 +000008 8182 STRH r2,[r0,#0xc] +00000a e004 B |L5.22| + |L5.12| +;;;367 } +;;;368 else +;;;369 { +;;;370 /* Disable the selected USART by clearing the UE bit in the CR1 register */ +;;;371 USARTx->CR1 &= CR1_UE_Reset; +00000c 8982 LDRH r2,[r0,#0xc] +00000e f64d73ff MOV r3,#0xdfff +000012 401a ANDS r2,r2,r3 +000014 8182 STRH r2,[r0,#0xc] + |L5.22| +;;;372 } +;;;373 } +000016 4770 BX lr +;;;374 + ENDP + + + AREA ||i.USART_DMACmd||, CODE, READONLY, ALIGN=1 + + USART_DMACmd PROC +;;;453 */ +;;;454 void USART_DMACmd(USART_TypeDef* USARTx, uint16_t USART_DMAReq, FunctionalState NewState) +000000 b11a CBZ r2,|L6.10| +;;;455 { +;;;456 /* Check the parameters */ +;;;457 assert_param(IS_USART_ALL_PERIPH(USARTx)); +;;;458 assert_param(IS_USART_DMAREQ(USART_DMAReq)); +;;;459 assert_param(IS_FUNCTIONAL_STATE(NewState)); +;;;460 if (NewState != DISABLE) +;;;461 { +;;;462 /* Enable the DMA transfer for selected requests by setting the DMAT and/or +;;;463 DMAR bits in the USART CR3 register */ +;;;464 USARTx->CR3 |= USART_DMAReq; +000002 8a83 LDRH r3,[r0,#0x14] +000004 430b ORRS r3,r3,r1 +000006 8283 STRH r3,[r0,#0x14] +000008 e002 B |L6.16| + |L6.10| +;;;465 } +;;;466 else +;;;467 { +;;;468 /* Disable the DMA transfer for selected requests by clearing the DMAT and/or +;;;469 DMAR bits in the USART CR3 register */ +;;;470 USARTx->CR3 &= (uint16_t)~USART_DMAReq; +00000a 8a83 LDRH r3,[r0,#0x14] +00000c 438b BICS r3,r3,r1 +00000e 8283 STRH r3,[r0,#0x14] + |L6.16| +;;;471 } +;;;472 } +000010 4770 BX lr +;;;473 + ENDP + + + AREA ||i.USART_DeInit||, CODE, READONLY, ALIGN=2 + + USART_DeInit PROC +;;;135 */ +;;;136 void USART_DeInit(USART_TypeDef* USARTx) +000000 b510 PUSH {r4,lr} +;;;137 { +000002 4604 MOV r4,r0 +;;;138 /* Check the parameters */ +;;;139 assert_param(IS_USART_ALL_PERIPH(USARTx)); +;;;140 +;;;141 if (USARTx == USART1) +000004 4820 LDR r0,|L7.136| +000006 4284 CMP r4,r0 +000008 d109 BNE |L7.30| +;;;142 { +;;;143 RCC_APB2PeriphResetCmd(RCC_APB2Periph_USART1, ENABLE); +00000a 2101 MOVS r1,#1 +00000c 0388 LSLS r0,r1,#14 +00000e f7fffffe BL RCC_APB2PeriphResetCmd +;;;144 RCC_APB2PeriphResetCmd(RCC_APB2Periph_USART1, DISABLE); +000012 2100 MOVS r1,#0 +000014 f44f4080 MOV r0,#0x4000 +000018 f7fffffe BL RCC_APB2PeriphResetCmd +00001c e032 B |L7.132| + |L7.30| +;;;145 } +;;;146 else if (USARTx == USART2) +00001e 481b LDR r0,|L7.140| +000020 4284 CMP r4,r0 +000022 d109 BNE |L7.56| +;;;147 { +;;;148 RCC_APB1PeriphResetCmd(RCC_APB1Periph_USART2, ENABLE); +000024 2101 MOVS r1,#1 +000026 0448 LSLS r0,r1,#17 +000028 f7fffffe BL RCC_APB1PeriphResetCmd +;;;149 RCC_APB1PeriphResetCmd(RCC_APB1Periph_USART2, DISABLE); +00002c 2100 MOVS r1,#0 +00002e f44f3000 MOV r0,#0x20000 +000032 f7fffffe BL RCC_APB1PeriphResetCmd +000036 e025 B |L7.132| + |L7.56| +;;;150 } +;;;151 else if (USARTx == USART3) +000038 4815 LDR r0,|L7.144| +00003a 4284 CMP r4,r0 +00003c d109 BNE |L7.82| +;;;152 { +;;;153 RCC_APB1PeriphResetCmd(RCC_APB1Periph_USART3, ENABLE); +00003e 2101 MOVS r1,#1 +000040 0488 LSLS r0,r1,#18 +000042 f7fffffe BL RCC_APB1PeriphResetCmd +;;;154 RCC_APB1PeriphResetCmd(RCC_APB1Periph_USART3, DISABLE); +000046 2100 MOVS r1,#0 +000048 f44f2080 MOV r0,#0x40000 +00004c f7fffffe BL RCC_APB1PeriphResetCmd +000050 e018 B |L7.132| + |L7.82| +;;;155 } +;;;156 else if (USARTx == UART4) +000052 4810 LDR r0,|L7.148| +000054 4284 CMP r4,r0 +000056 d109 BNE |L7.108| +;;;157 { +;;;158 RCC_APB1PeriphResetCmd(RCC_APB1Periph_UART4, ENABLE); +000058 2101 MOVS r1,#1 +00005a 04c8 LSLS r0,r1,#19 +00005c f7fffffe BL RCC_APB1PeriphResetCmd +;;;159 RCC_APB1PeriphResetCmd(RCC_APB1Periph_UART4, DISABLE); +000060 2100 MOVS r1,#0 +000062 f44f2000 MOV r0,#0x80000 +000066 f7fffffe BL RCC_APB1PeriphResetCmd +00006a e00b B |L7.132| + |L7.108| +;;;160 } +;;;161 else +;;;162 { +;;;163 if (USARTx == UART5) +00006c 480a LDR r0,|L7.152| +00006e 4284 CMP r4,r0 +000070 d108 BNE |L7.132| +;;;164 { +;;;165 RCC_APB1PeriphResetCmd(RCC_APB1Periph_UART5, ENABLE); +000072 2101 MOVS r1,#1 +000074 0508 LSLS r0,r1,#20 +000076 f7fffffe BL RCC_APB1PeriphResetCmd +;;;166 RCC_APB1PeriphResetCmd(RCC_APB1Periph_UART5, DISABLE); +00007a 2100 MOVS r1,#0 +00007c f44f1080 MOV r0,#0x100000 +000080 f7fffffe BL RCC_APB1PeriphResetCmd + |L7.132| +;;;167 } +;;;168 } +;;;169 } +000084 bd10 POP {r4,pc} +;;;170 + ENDP + +000086 0000 DCW 0x0000 + |L7.136| + DCD 0x40013800 + |L7.140| + DCD 0x40004400 + |L7.144| + DCD 0x40004800 + |L7.148| + DCD 0x40004c00 + |L7.152| + DCD 0x40005000 + + AREA ||i.USART_GetFlagStatus||, CODE, READONLY, ALIGN=1 + + USART_GetFlagStatus PROC +;;;879 */ +;;;880 FlagStatus USART_GetFlagStatus(USART_TypeDef* USARTx, uint16_t USART_FLAG) +000000 4602 MOV r2,r0 +;;;881 { +;;;882 FlagStatus bitstatus = RESET; +000002 2000 MOVS r0,#0 +;;;883 /* Check the parameters */ +;;;884 assert_param(IS_USART_ALL_PERIPH(USARTx)); +;;;885 assert_param(IS_USART_FLAG(USART_FLAG)); +;;;886 /* The CTS flag is not available for UART4 and UART5 */ +;;;887 if (USART_FLAG == USART_FLAG_CTS) +000004 f5b17f00 CMP r1,#0x200 +000008 d100 BNE |L8.12| +;;;888 { +;;;889 assert_param(IS_USART_123_PERIPH(USARTx)); +00000a bf00 NOP + |L8.12| +;;;890 } +;;;891 +;;;892 if ((USARTx->SR & USART_FLAG) != (uint16_t)RESET) +00000c 8813 LDRH r3,[r2,#0] +00000e 400b ANDS r3,r3,r1 +000010 b10b CBZ r3,|L8.22| +;;;893 { +;;;894 bitstatus = SET; +000012 2001 MOVS r0,#1 +000014 e000 B |L8.24| + |L8.22| +;;;895 } +;;;896 else +;;;897 { +;;;898 bitstatus = RESET; +000016 2000 MOVS r0,#0 + |L8.24| +;;;899 } +;;;900 return bitstatus; +;;;901 } +000018 4770 BX lr +;;;902 + ENDP + + + AREA ||i.USART_GetITStatus||, CODE, READONLY, ALIGN=1 + + USART_GetITStatus PROC +;;;962 */ +;;;963 ITStatus USART_GetITStatus(USART_TypeDef* USARTx, uint16_t USART_IT) +000000 b570 PUSH {r4-r6,lr} +;;;964 { +000002 4602 MOV r2,r0 +;;;965 uint32_t bitpos = 0x00, itmask = 0x00, usartreg = 0x00; +000004 2400 MOVS r4,#0 +000006 2300 MOVS r3,#0 +000008 2500 MOVS r5,#0 +;;;966 ITStatus bitstatus = RESET; +00000a 2000 MOVS r0,#0 +;;;967 /* Check the parameters */ +;;;968 assert_param(IS_USART_ALL_PERIPH(USARTx)); +;;;969 assert_param(IS_USART_GET_IT(USART_IT)); +;;;970 /* The CTS interrupt is not available for UART4 and UART5 */ +;;;971 if (USART_IT == USART_IT_CTS) +00000c f640166a MOV r6,#0x96a +000010 42b1 CMP r1,r6 +000012 d100 BNE |L9.22| +;;;972 { +;;;973 assert_param(IS_USART_123_PERIPH(USARTx)); +000014 bf00 NOP + |L9.22| +;;;974 } +;;;975 +;;;976 /* Get the USART register index */ +;;;977 usartreg = (((uint8_t)USART_IT) >> 0x05); +000016 f3c11542 UBFX r5,r1,#5,#3 +;;;978 /* Get the interrupt position */ +;;;979 itmask = USART_IT & IT_Mask; +00001a f001031f AND r3,r1,#0x1f +;;;980 itmask = (uint32_t)0x01 << itmask; +00001e 2601 MOVS r6,#1 +000020 fa06f303 LSL r3,r6,r3 +;;;981 +;;;982 if (usartreg == 0x01) /* The IT is in CR1 register */ +000024 2d01 CMP r5,#1 +000026 d102 BNE |L9.46| +;;;983 { +;;;984 itmask &= USARTx->CR1; +000028 8996 LDRH r6,[r2,#0xc] +00002a 4033 ANDS r3,r3,r6 +00002c e006 B |L9.60| + |L9.46| +;;;985 } +;;;986 else if (usartreg == 0x02) /* The IT is in CR2 register */ +00002e 2d02 CMP r5,#2 +000030 d102 BNE |L9.56| +;;;987 { +;;;988 itmask &= USARTx->CR2; +000032 8a16 LDRH r6,[r2,#0x10] +000034 4033 ANDS r3,r3,r6 +000036 e001 B |L9.60| + |L9.56| +;;;989 } +;;;990 else /* The IT is in CR3 register */ +;;;991 { +;;;992 itmask &= USARTx->CR3; +000038 8a96 LDRH r6,[r2,#0x14] +00003a 4033 ANDS r3,r3,r6 + |L9.60| +;;;993 } +;;;994 +;;;995 bitpos = USART_IT >> 0x08; +00003c 120c ASRS r4,r1,#8 +;;;996 bitpos = (uint32_t)0x01 << bitpos; +00003e 2601 MOVS r6,#1 +000040 fa06f404 LSL r4,r6,r4 +;;;997 bitpos &= USARTx->SR; +000044 8816 LDRH r6,[r2,#0] +000046 4034 ANDS r4,r4,r6 +;;;998 if ((itmask != (uint16_t)RESET)&&(bitpos != (uint16_t)RESET)) +000048 b113 CBZ r3,|L9.80| +00004a b10c CBZ r4,|L9.80| +;;;999 { +;;;1000 bitstatus = SET; +00004c 2001 MOVS r0,#1 +00004e e000 B |L9.82| + |L9.80| +;;;1001 } +;;;1002 else +;;;1003 { +;;;1004 bitstatus = RESET; +000050 2000 MOVS r0,#0 + |L9.82| +;;;1005 } +;;;1006 +;;;1007 return bitstatus; +;;;1008 } +000052 bd70 POP {r4-r6,pc} +;;;1009 + ENDP + + + AREA ||i.USART_HalfDuplexCmd||, CODE, READONLY, ALIGN=1 + + USART_HalfDuplexCmd PROC +;;;736 */ +;;;737 void USART_HalfDuplexCmd(USART_TypeDef* USARTx, FunctionalState NewState) +000000 b121 CBZ r1,|L10.12| +;;;738 { +;;;739 /* Check the parameters */ +;;;740 assert_param(IS_USART_ALL_PERIPH(USARTx)); +;;;741 assert_param(IS_FUNCTIONAL_STATE(NewState)); +;;;742 +;;;743 if (NewState != DISABLE) +;;;744 { +;;;745 /* Enable the Half-Duplex mode by setting the HDSEL bit in the CR3 register */ +;;;746 USARTx->CR3 |= CR3_HDSEL_Set; +000002 8a82 LDRH r2,[r0,#0x14] +000004 f0420208 ORR r2,r2,#8 +000008 8282 STRH r2,[r0,#0x14] +00000a e004 B |L10.22| + |L10.12| +;;;747 } +;;;748 else +;;;749 { +;;;750 /* Disable the Half-Duplex mode by clearing the HDSEL bit in the CR3 register */ +;;;751 USARTx->CR3 &= CR3_HDSEL_Reset; +00000c 8a82 LDRH r2,[r0,#0x14] +00000e f64f73f7 MOV r3,#0xfff7 +000012 401a ANDS r2,r2,r3 +000014 8282 STRH r2,[r0,#0x14] + |L10.22| +;;;752 } +;;;753 } +000016 4770 BX lr +;;;754 + ENDP + + + AREA ||i.USART_ITConfig||, CODE, READONLY, ALIGN=1 + + USART_ITConfig PROC +;;;393 */ +;;;394 void USART_ITConfig(USART_TypeDef* USARTx, uint16_t USART_IT, FunctionalState NewState) +000000 b5f0 PUSH {r4-r7,lr} +;;;395 { +000002 4603 MOV r3,r0 +;;;396 uint32_t usartreg = 0x00, itpos = 0x00, itmask = 0x00; +000004 2400 MOVS r4,#0 +000006 2600 MOVS r6,#0 +000008 2500 MOVS r5,#0 +;;;397 uint32_t usartxbase = 0x00; +00000a 2000 MOVS r0,#0 +;;;398 /* Check the parameters */ +;;;399 assert_param(IS_USART_ALL_PERIPH(USARTx)); +;;;400 assert_param(IS_USART_CONFIG_IT(USART_IT)); +;;;401 assert_param(IS_FUNCTIONAL_STATE(NewState)); +;;;402 /* The CTS interrupt is not available for UART4 and UART5 */ +;;;403 if (USART_IT == USART_IT_CTS) +00000c f640176a MOV r7,#0x96a +000010 42b9 CMP r1,r7 +000012 d100 BNE |L11.22| +;;;404 { +;;;405 assert_param(IS_USART_123_PERIPH(USARTx)); +000014 bf00 NOP + |L11.22| +;;;406 } +;;;407 +;;;408 usartxbase = (uint32_t)USARTx; +000016 4618 MOV r0,r3 +;;;409 +;;;410 /* Get the USART register index */ +;;;411 usartreg = (((uint8_t)USART_IT) >> 0x05); +000018 f3c11442 UBFX r4,r1,#5,#3 +;;;412 +;;;413 /* Get the interrupt position */ +;;;414 itpos = USART_IT & IT_Mask; +00001c f001061f AND r6,r1,#0x1f +;;;415 itmask = (((uint32_t)0x01) << itpos); +000020 2701 MOVS r7,#1 +000022 fa07f506 LSL r5,r7,r6 +;;;416 +;;;417 if (usartreg == 0x01) /* The IT is in CR1 register */ +000026 2c01 CMP r4,#1 +000028 d101 BNE |L11.46| +;;;418 { +;;;419 usartxbase += 0x0C; +00002a 300c ADDS r0,r0,#0xc +00002c e004 B |L11.56| + |L11.46| +;;;420 } +;;;421 else if (usartreg == 0x02) /* The IT is in CR2 register */ +00002e 2c02 CMP r4,#2 +000030 d101 BNE |L11.54| +;;;422 { +;;;423 usartxbase += 0x10; +000032 3010 ADDS r0,r0,#0x10 +000034 e000 B |L11.56| + |L11.54| +;;;424 } +;;;425 else /* The IT is in CR3 register */ +;;;426 { +;;;427 usartxbase += 0x14; +000036 3014 ADDS r0,r0,#0x14 + |L11.56| +;;;428 } +;;;429 if (NewState != DISABLE) +000038 b11a CBZ r2,|L11.66| +;;;430 { +;;;431 *(__IO uint32_t*)usartxbase |= itmask; +00003a 6807 LDR r7,[r0,#0] +00003c 432f ORRS r7,r7,r5 +00003e 6007 STR r7,[r0,#0] +000040 e002 B |L11.72| + |L11.66| +;;;432 } +;;;433 else +;;;434 { +;;;435 *(__IO uint32_t*)usartxbase &= ~itmask; +000042 6807 LDR r7,[r0,#0] +000044 43af BICS r7,r7,r5 +000046 6007 STR r7,[r0,#0] + |L11.72| +;;;436 } +;;;437 } +000048 bdf0 POP {r4-r7,pc} +;;;438 + ENDP + + + AREA ||i.USART_Init||, CODE, READONLY, ALIGN=2 + + USART_Init PROC +;;;181 */ +;;;182 void USART_Init(USART_TypeDef* USARTx, USART_InitTypeDef* USART_InitStruct) +000000 e92d47f0 PUSH {r4-r10,lr} +;;;183 { +000004 b086 SUB sp,sp,#0x18 +000006 4605 MOV r5,r0 +000008 460e MOV r6,r1 +;;;184 uint32_t tmpreg = 0x00, apbclock = 0x00; +00000a 2400 MOVS r4,#0 +00000c 46a2 MOV r10,r4 +;;;185 uint32_t integerdivider = 0x00; +00000e bf00 NOP +;;;186 uint32_t fractionaldivider = 0x00; +000010 46a1 MOV r9,r4 +;;;187 uint32_t usartxbase = 0; +000012 2700 MOVS r7,#0 +;;;188 RCC_ClocksTypeDef RCC_ClocksStatus; +;;;189 /* Check the parameters */ +;;;190 assert_param(IS_USART_ALL_PERIPH(USARTx)); +;;;191 assert_param(IS_USART_BAUDRATE(USART_InitStruct->USART_BaudRate)); +;;;192 assert_param(IS_USART_WORD_LENGTH(USART_InitStruct->USART_WordLength)); +;;;193 assert_param(IS_USART_STOPBITS(USART_InitStruct->USART_StopBits)); +;;;194 assert_param(IS_USART_PARITY(USART_InitStruct->USART_Parity)); +;;;195 assert_param(IS_USART_MODE(USART_InitStruct->USART_Mode)); +;;;196 assert_param(IS_USART_HARDWARE_FLOW_CONTROL(USART_InitStruct->USART_HardwareFlowControl)); +;;;197 /* The hardware flow control is available only for USART1, USART2 and USART3 */ +;;;198 if (USART_InitStruct->USART_HardwareFlowControl != USART_HardwareFlowControl_None) +000014 89b0 LDRH r0,[r6,#0xc] +000016 b100 CBZ r0,|L12.26| +;;;199 { +;;;200 assert_param(IS_USART_123_PERIPH(USARTx)); +000018 bf00 NOP + |L12.26| +;;;201 } +;;;202 +;;;203 usartxbase = (uint32_t)USARTx; +00001a 462f MOV r7,r5 +;;;204 +;;;205 /*---------------------------- USART CR2 Configuration -----------------------*/ +;;;206 tmpreg = USARTx->CR2; +00001c 8a2c LDRH r4,[r5,#0x10] +;;;207 /* Clear STOP[13:12] bits */ +;;;208 tmpreg &= CR2_STOP_CLEAR_Mask; +00001e f64c70ff MOV r0,#0xcfff +000022 4004 ANDS r4,r4,r0 +;;;209 /* Configure the USART Stop Bits, Clock, CPOL, CPHA and LastBit ------------*/ +;;;210 /* Set STOP[13:12] bits according to USART_StopBits value */ +;;;211 tmpreg |= (uint32_t)USART_InitStruct->USART_StopBits; +000024 88f0 LDRH r0,[r6,#6] +000026 4304 ORRS r4,r4,r0 +;;;212 +;;;213 /* Write to USART CR2 */ +;;;214 USARTx->CR2 = (uint16_t)tmpreg; +000028 822c STRH r4,[r5,#0x10] +;;;215 +;;;216 /*---------------------------- USART CR1 Configuration -----------------------*/ +;;;217 tmpreg = USARTx->CR1; +00002a 89ac LDRH r4,[r5,#0xc] +;;;218 /* Clear M, PCE, PS, TE and RE bits */ +;;;219 tmpreg &= CR1_CLEAR_Mask; +00002c f64e10f3 MOV r0,#0xe9f3 +000030 4004 ANDS r4,r4,r0 +;;;220 /* Configure the USART Word Length, Parity and mode ----------------------- */ +;;;221 /* Set the M bits according to USART_WordLength value */ +;;;222 /* Set PCE and PS bits according to USART_Parity value */ +;;;223 /* Set TE and RE bits according to USART_Mode value */ +;;;224 tmpreg |= (uint32_t)USART_InitStruct->USART_WordLength | USART_InitStruct->USART_Parity | +000032 88b0 LDRH r0,[r6,#4] +000034 8931 LDRH r1,[r6,#8] +000036 4308 ORRS r0,r0,r1 +000038 8971 LDRH r1,[r6,#0xa] +00003a 4308 ORRS r0,r0,r1 +00003c 4304 ORRS r4,r4,r0 +;;;225 USART_InitStruct->USART_Mode; +;;;226 /* Write to USART CR1 */ +;;;227 USARTx->CR1 = (uint16_t)tmpreg; +00003e 81ac STRH r4,[r5,#0xc] +;;;228 +;;;229 /*---------------------------- USART CR3 Configuration -----------------------*/ +;;;230 tmpreg = USARTx->CR3; +000040 8aac LDRH r4,[r5,#0x14] +;;;231 /* Clear CTSE and RTSE bits */ +;;;232 tmpreg &= CR3_CLEAR_Mask; +000042 f64f40ff MOV r0,#0xfcff +000046 4004 ANDS r4,r4,r0 +;;;233 /* Configure the USART HFC -------------------------------------------------*/ +;;;234 /* Set CTSE and RTSE bits according to USART_HardwareFlowControl value */ +;;;235 tmpreg |= USART_InitStruct->USART_HardwareFlowControl; +000048 89b0 LDRH r0,[r6,#0xc] +00004a 4304 ORRS r4,r4,r0 +;;;236 /* Write to USART CR3 */ +;;;237 USARTx->CR3 = (uint16_t)tmpreg; +00004c 82ac STRH r4,[r5,#0x14] +;;;238 +;;;239 /*---------------------------- USART BRR Configuration -----------------------*/ +;;;240 /* Configure the USART Baud Rate -------------------------------------------*/ +;;;241 RCC_GetClocksFreq(&RCC_ClocksStatus); +00004e a801 ADD r0,sp,#4 +000050 f7fffffe BL RCC_GetClocksFreq +;;;242 if (usartxbase == USART1_BASE) +000054 481f LDR r0,|L12.212| +000056 4287 CMP r7,r0 +000058 d102 BNE |L12.96| +;;;243 { +;;;244 apbclock = RCC_ClocksStatus.PCLK2_Frequency; +00005a f8dda010 LDR r10,[sp,#0x10] +00005e e001 B |L12.100| + |L12.96| +;;;245 } +;;;246 else +;;;247 { +;;;248 apbclock = RCC_ClocksStatus.PCLK1_Frequency; +000060 f8dda00c LDR r10,[sp,#0xc] + |L12.100| +;;;249 } +;;;250 +;;;251 /* Determine the integer part */ +;;;252 if ((USARTx->CR1 & CR1_OVER8_Set) != 0) +000064 89a8 LDRH r0,[r5,#0xc] +000066 f4004000 AND r0,r0,#0x8000 +00006a b140 CBZ r0,|L12.126| +;;;253 { +;;;254 /* Integer part computing in case Oversampling mode is 8 Samples */ +;;;255 integerdivider = ((25 * apbclock) / (2 * (USART_InitStruct->USART_BaudRate))); +00006c eb0a00ca ADD r0,r10,r10,LSL #3 +000070 eb00100a ADD r0,r0,r10,LSL #4 +000074 6831 LDR r1,[r6,#0] +000076 0049 LSLS r1,r1,#1 +000078 fbb0f8f1 UDIV r8,r0,r1 +00007c e007 B |L12.142| + |L12.126| +;;;256 } +;;;257 else /* if ((USARTx->CR1 & CR1_OVER8_Set) == 0) */ +;;;258 { +;;;259 /* Integer part computing in case Oversampling mode is 16 Samples */ +;;;260 integerdivider = ((25 * apbclock) / (4 * (USART_InitStruct->USART_BaudRate))); +00007e eb0a00ca ADD r0,r10,r10,LSL #3 +000082 eb00100a ADD r0,r0,r10,LSL #4 +000086 6831 LDR r1,[r6,#0] +000088 0089 LSLS r1,r1,#2 +00008a fbb0f8f1 UDIV r8,r0,r1 + |L12.142| +;;;261 } +;;;262 tmpreg = (integerdivider / 100) << 4; +00008e 2064 MOVS r0,#0x64 +000090 fbb8f0f0 UDIV r0,r8,r0 +000094 0104 LSLS r4,r0,#4 +;;;263 +;;;264 /* Determine the fractional part */ +;;;265 fractionaldivider = integerdivider - (100 * (tmpreg >> 4)); +000096 0920 LSRS r0,r4,#4 +000098 2164 MOVS r1,#0x64 +00009a fb018910 MLS r9,r1,r0,r8 +;;;266 +;;;267 /* Implement the fractional part in the register */ +;;;268 if ((USARTx->CR1 & CR1_OVER8_Set) != 0) +00009e 89a8 LDRH r0,[r5,#0xc] +0000a0 f4004000 AND r0,r0,#0x8000 +0000a4 b140 CBZ r0,|L12.184| +;;;269 { +;;;270 tmpreg |= ((((fractionaldivider * 8) + 50) / 100)) & ((uint8_t)0x07); +0000a6 2032 MOVS r0,#0x32 +0000a8 eb0000c9 ADD r0,r0,r9,LSL #3 +0000ac fbb0f0f1 UDIV r0,r0,r1 +0000b0 f0000007 AND r0,r0,#7 +0000b4 4304 ORRS r4,r4,r0 +0000b6 e008 B |L12.202| + |L12.184| +;;;271 } +;;;272 else /* if ((USARTx->CR1 & CR1_OVER8_Set) == 0) */ +;;;273 { +;;;274 tmpreg |= ((((fractionaldivider * 16) + 50) / 100)) & ((uint8_t)0x0F); +0000b8 2032 MOVS r0,#0x32 +0000ba eb001009 ADD r0,r0,r9,LSL #4 +0000be 2164 MOVS r1,#0x64 +0000c0 fbb0f0f1 UDIV r0,r0,r1 +0000c4 f000000f AND r0,r0,#0xf +0000c8 4304 ORRS r4,r4,r0 + |L12.202| +;;;275 } +;;;276 +;;;277 /* Write to USART BRR */ +;;;278 USARTx->BRR = (uint16_t)tmpreg; +0000ca 812c STRH r4,[r5,#8] +;;;279 } +0000cc b006 ADD sp,sp,#0x18 +0000ce e8bd87f0 POP {r4-r10,pc} +;;;280 + ENDP + +0000d2 0000 DCW 0x0000 + |L12.212| + DCD 0x40013800 + + AREA ||i.USART_IrDACmd||, CODE, READONLY, ALIGN=1 + + USART_IrDACmd PROC +;;;842 */ +;;;843 void USART_IrDACmd(USART_TypeDef* USARTx, FunctionalState NewState) +000000 b121 CBZ r1,|L13.12| +;;;844 { +;;;845 /* Check the parameters */ +;;;846 assert_param(IS_USART_ALL_PERIPH(USARTx)); +;;;847 assert_param(IS_FUNCTIONAL_STATE(NewState)); +;;;848 +;;;849 if (NewState != DISABLE) +;;;850 { +;;;851 /* Enable the IrDA mode by setting the IREN bit in the CR3 register */ +;;;852 USARTx->CR3 |= CR3_IREN_Set; +000002 8a82 LDRH r2,[r0,#0x14] +000004 f0420202 ORR r2,r2,#2 +000008 8282 STRH r2,[r0,#0x14] +00000a e004 B |L13.22| + |L13.12| +;;;853 } +;;;854 else +;;;855 { +;;;856 /* Disable the IrDA mode by clearing the IREN bit in the CR3 register */ +;;;857 USARTx->CR3 &= CR3_IREN_Reset; +00000c 8a82 LDRH r2,[r0,#0x14] +00000e f64f73fd MOV r3,#0xfffd +000012 401a ANDS r2,r2,r3 +000014 8282 STRH r2,[r0,#0x14] + |L13.22| +;;;858 } +;;;859 } +000016 4770 BX lr +;;;860 + ENDP + + + AREA ||i.USART_IrDAConfig||, CODE, READONLY, ALIGN=1 + + USART_IrDAConfig PROC +;;;823 */ +;;;824 void USART_IrDAConfig(USART_TypeDef* USARTx, uint16_t USART_IrDAMode) +000000 8a82 LDRH r2,[r0,#0x14] +;;;825 { +;;;826 /* Check the parameters */ +;;;827 assert_param(IS_USART_ALL_PERIPH(USARTx)); +;;;828 assert_param(IS_USART_IRDA_MODE(USART_IrDAMode)); +;;;829 +;;;830 USARTx->CR3 &= CR3_IRLP_Mask; +000002 f64f73fb MOV r3,#0xfffb +000006 401a ANDS r2,r2,r3 +000008 8282 STRH r2,[r0,#0x14] +;;;831 USARTx->CR3 |= USART_IrDAMode; +00000a 8a82 LDRH r2,[r0,#0x14] +00000c 430a ORRS r2,r2,r1 +00000e 8282 STRH r2,[r0,#0x14] +;;;832 } +000010 4770 BX lr +;;;833 + ENDP + + + AREA ||i.USART_LINBreakDetectLengthConfig||, CODE, READONLY, ALIGN=1 + + USART_LINBreakDetectLengthConfig PROC +;;;552 */ +;;;553 void USART_LINBreakDetectLengthConfig(USART_TypeDef* USARTx, uint16_t USART_LINBreakDetectLength) +000000 8a02 LDRH r2,[r0,#0x10] +;;;554 { +;;;555 /* Check the parameters */ +;;;556 assert_param(IS_USART_ALL_PERIPH(USARTx)); +;;;557 assert_param(IS_USART_LIN_BREAK_DETECT_LENGTH(USART_LINBreakDetectLength)); +;;;558 +;;;559 USARTx->CR2 &= CR2_LBDL_Mask; +000002 f64f73df MOV r3,#0xffdf +000006 401a ANDS r2,r2,r3 +000008 8202 STRH r2,[r0,#0x10] +;;;560 USARTx->CR2 |= USART_LINBreakDetectLength; +00000a 8a02 LDRH r2,[r0,#0x10] +00000c 430a ORRS r2,r2,r1 +00000e 8202 STRH r2,[r0,#0x10] +;;;561 } +000010 4770 BX lr +;;;562 + ENDP + + + AREA ||i.USART_LINCmd||, CODE, READONLY, ALIGN=1 + + USART_LINCmd PROC +;;;571 */ +;;;572 void USART_LINCmd(USART_TypeDef* USARTx, FunctionalState NewState) +000000 b121 CBZ r1,|L16.12| +;;;573 { +;;;574 /* Check the parameters */ +;;;575 assert_param(IS_USART_ALL_PERIPH(USARTx)); +;;;576 assert_param(IS_FUNCTIONAL_STATE(NewState)); +;;;577 +;;;578 if (NewState != DISABLE) +;;;579 { +;;;580 /* Enable the LIN mode by setting the LINEN bit in the CR2 register */ +;;;581 USARTx->CR2 |= CR2_LINEN_Set; +000002 8a02 LDRH r2,[r0,#0x10] +000004 f4424280 ORR r2,r2,#0x4000 +000008 8202 STRH r2,[r0,#0x10] +00000a e004 B |L16.22| + |L16.12| +;;;582 } +;;;583 else +;;;584 { +;;;585 /* Disable the LIN mode by clearing the LINEN bit in the CR2 register */ +;;;586 USARTx->CR2 &= CR2_LINEN_Reset; +00000c 8a02 LDRH r2,[r0,#0x10] +00000e f64b73ff MOV r3,#0xbfff +000012 401a ANDS r2,r2,r3 +000014 8202 STRH r2,[r0,#0x10] + |L16.22| +;;;587 } +;;;588 } +000016 4770 BX lr +;;;589 + ENDP + + + AREA ||i.USART_OneBitMethodCmd||, CODE, READONLY, ALIGN=1 + + USART_OneBitMethodCmd PROC +;;;794 */ +;;;795 void USART_OneBitMethodCmd(USART_TypeDef* USARTx, FunctionalState NewState) +000000 b121 CBZ r1,|L17.12| +;;;796 { +;;;797 /* Check the parameters */ +;;;798 assert_param(IS_USART_ALL_PERIPH(USARTx)); +;;;799 assert_param(IS_FUNCTIONAL_STATE(NewState)); +;;;800 +;;;801 if (NewState != DISABLE) +;;;802 { +;;;803 /* Enable the one bit method by setting the ONEBITE bit in the CR3 register */ +;;;804 USARTx->CR3 |= CR3_ONEBITE_Set; +000002 8a82 LDRH r2,[r0,#0x14] +000004 f4426200 ORR r2,r2,#0x800 +000008 8282 STRH r2,[r0,#0x14] +00000a e004 B |L17.22| + |L17.12| +;;;805 } +;;;806 else +;;;807 { +;;;808 /* Disable tthe one bit method by clearing the ONEBITE bit in the CR3 register */ +;;;809 USARTx->CR3 &= CR3_ONEBITE_Reset; +00000c 8a82 LDRH r2,[r0,#0x14] +00000e f24f73ff MOV r3,#0xf7ff +000012 401a ANDS r2,r2,r3 +000014 8282 STRH r2,[r0,#0x14] + |L17.22| +;;;810 } +;;;811 } +000016 4770 BX lr +;;;812 + ENDP + + + AREA ||i.USART_OverSampling8Cmd||, CODE, READONLY, ALIGN=1 + + USART_OverSampling8Cmd PROC +;;;767 */ +;;;768 void USART_OverSampling8Cmd(USART_TypeDef* USARTx, FunctionalState NewState) +000000 b121 CBZ r1,|L18.12| +;;;769 { +;;;770 /* Check the parameters */ +;;;771 assert_param(IS_USART_ALL_PERIPH(USARTx)); +;;;772 assert_param(IS_FUNCTIONAL_STATE(NewState)); +;;;773 +;;;774 if (NewState != DISABLE) +;;;775 { +;;;776 /* Enable the 8x Oversampling mode by setting the OVER8 bit in the CR1 register */ +;;;777 USARTx->CR1 |= CR1_OVER8_Set; +000002 8982 LDRH r2,[r0,#0xc] +000004 f4424200 ORR r2,r2,#0x8000 +000008 8182 STRH r2,[r0,#0xc] +00000a e003 B |L18.20| + |L18.12| +;;;778 } +;;;779 else +;;;780 { +;;;781 /* Disable the 8x Oversampling mode by clearing the OVER8 bit in the CR1 register */ +;;;782 USARTx->CR1 &= CR1_OVER8_Reset; +00000c 8982 LDRH r2,[r0,#0xc] +00000e f3c2020e UBFX r2,r2,#0,#15 +000012 8182 STRH r2,[r0,#0xc] + |L18.20| +;;;783 } +;;;784 } +000014 4770 BX lr +;;;785 + ENDP + + + AREA ||i.USART_ReceiveData||, CODE, READONLY, ALIGN=1 + + USART_ReceiveData PROC +;;;614 */ +;;;615 uint16_t USART_ReceiveData(USART_TypeDef* USARTx) +000000 4601 MOV r1,r0 +;;;616 { +;;;617 /* Check the parameters */ +;;;618 assert_param(IS_USART_ALL_PERIPH(USARTx)); +;;;619 +;;;620 /* Receive Data */ +;;;621 return (uint16_t)(USARTx->DR & (uint16_t)0x01FF); +000002 8888 LDRH r0,[r1,#4] +000004 f3c00008 UBFX r0,r0,#0,#9 +;;;622 } +000008 4770 BX lr +;;;623 + ENDP + + + AREA ||i.USART_ReceiverWakeUpCmd||, CODE, READONLY, ALIGN=1 + + USART_ReceiverWakeUpCmd PROC +;;;523 */ +;;;524 void USART_ReceiverWakeUpCmd(USART_TypeDef* USARTx, FunctionalState NewState) +000000 b121 CBZ r1,|L20.12| +;;;525 { +;;;526 /* Check the parameters */ +;;;527 assert_param(IS_USART_ALL_PERIPH(USARTx)); +;;;528 assert_param(IS_FUNCTIONAL_STATE(NewState)); +;;;529 +;;;530 if (NewState != DISABLE) +;;;531 { +;;;532 /* Enable the USART mute mode by setting the RWU bit in the CR1 register */ +;;;533 USARTx->CR1 |= CR1_RWU_Set; +000002 8982 LDRH r2,[r0,#0xc] +000004 f0420202 ORR r2,r2,#2 +000008 8182 STRH r2,[r0,#0xc] +00000a e004 B |L20.22| + |L20.12| +;;;534 } +;;;535 else +;;;536 { +;;;537 /* Disable the USART mute mode by clearing the RWU bit in the CR1 register */ +;;;538 USARTx->CR1 &= CR1_RWU_Reset; +00000c 8982 LDRH r2,[r0,#0xc] +00000e f64f73fd MOV r3,#0xfffd +000012 401a ANDS r2,r2,r3 +000014 8182 STRH r2,[r0,#0xc] + |L20.22| +;;;539 } +;;;540 } +000016 4770 BX lr +;;;541 + ENDP + + + AREA ||i.USART_SendBreak||, CODE, READONLY, ALIGN=1 + + USART_SendBreak PROC +;;;630 */ +;;;631 void USART_SendBreak(USART_TypeDef* USARTx) +000000 8981 LDRH r1,[r0,#0xc] +;;;632 { +;;;633 /* Check the parameters */ +;;;634 assert_param(IS_USART_ALL_PERIPH(USARTx)); +;;;635 +;;;636 /* Send break characters */ +;;;637 USARTx->CR1 |= CR1_SBK_Set; +000002 f0410101 ORR r1,r1,#1 +000006 8181 STRH r1,[r0,#0xc] +;;;638 } +000008 4770 BX lr +;;;639 + ENDP + + + AREA ||i.USART_SendData||, CODE, READONLY, ALIGN=1 + + USART_SendData PROC +;;;597 */ +;;;598 void USART_SendData(USART_TypeDef* USARTx, uint16_t Data) +000000 f3c10208 UBFX r2,r1,#0,#9 +;;;599 { +;;;600 /* Check the parameters */ +;;;601 assert_param(IS_USART_ALL_PERIPH(USARTx)); +;;;602 assert_param(IS_USART_DATA(Data)); +;;;603 +;;;604 /* Transmit Data */ +;;;605 USARTx->DR = (Data & (uint16_t)0x01FF); +000004 8082 STRH r2,[r0,#4] +;;;606 } +000006 4770 BX lr +;;;607 + ENDP + + + AREA ||i.USART_SetAddress||, CODE, READONLY, ALIGN=1 + + USART_SetAddress PROC +;;;481 */ +;;;482 void USART_SetAddress(USART_TypeDef* USARTx, uint8_t USART_Address) +000000 8a02 LDRH r2,[r0,#0x10] +;;;483 { +;;;484 /* Check the parameters */ +;;;485 assert_param(IS_USART_ALL_PERIPH(USARTx)); +;;;486 assert_param(IS_USART_ADDRESS(USART_Address)); +;;;487 +;;;488 /* Clear the USART address */ +;;;489 USARTx->CR2 &= CR2_Address_Mask; +000002 f64f73f0 MOV r3,#0xfff0 +000006 401a ANDS r2,r2,r3 +000008 8202 STRH r2,[r0,#0x10] +;;;490 /* Set the USART address node */ +;;;491 USARTx->CR2 |= USART_Address; +00000a 8a02 LDRH r2,[r0,#0x10] +00000c 430a ORRS r2,r2,r1 +00000e 8202 STRH r2,[r0,#0x10] +;;;492 } +000010 4770 BX lr +;;;493 + ENDP + + + AREA ||i.USART_SetGuardTime||, CODE, READONLY, ALIGN=1 + + USART_SetGuardTime PROC +;;;646 */ +;;;647 void USART_SetGuardTime(USART_TypeDef* USARTx, uint8_t USART_GuardTime) +000000 8b02 LDRH r2,[r0,#0x18] +;;;648 { +;;;649 /* Check the parameters */ +;;;650 assert_param(IS_USART_123_PERIPH(USARTx)); +;;;651 +;;;652 /* Clear the USART Guard time */ +;;;653 USARTx->GTPR &= GTPR_LSB_Mask; +000002 b2d2 UXTB r2,r2 +000004 8302 STRH r2,[r0,#0x18] +;;;654 /* Set the USART guard time */ +;;;655 USARTx->GTPR |= (uint16_t)((uint16_t)USART_GuardTime << 0x08); +000006 8b02 LDRH r2,[r0,#0x18] +000008 ea422201 ORR r2,r2,r1,LSL #8 +00000c 8302 STRH r2,[r0,#0x18] +;;;656 } +00000e 4770 BX lr +;;;657 + ENDP + + + AREA ||i.USART_SetPrescaler||, CODE, READONLY, ALIGN=1 + + USART_SetPrescaler PROC +;;;666 */ +;;;667 void USART_SetPrescaler(USART_TypeDef* USARTx, uint8_t USART_Prescaler) +000000 8b02 LDRH r2,[r0,#0x18] +;;;668 { +;;;669 /* Check the parameters */ +;;;670 assert_param(IS_USART_ALL_PERIPH(USARTx)); +;;;671 +;;;672 /* Clear the USART prescaler */ +;;;673 USARTx->GTPR &= GTPR_MSB_Mask; +000002 f402427f AND r2,r2,#0xff00 +000006 8302 STRH r2,[r0,#0x18] +;;;674 /* Set the USART prescaler */ +;;;675 USARTx->GTPR |= USART_Prescaler; +000008 8b02 LDRH r2,[r0,#0x18] +00000a 430a ORRS r2,r2,r1 +00000c 8302 STRH r2,[r0,#0x18] +;;;676 } +00000e 4770 BX lr +;;;677 + ENDP + + + AREA ||i.USART_SmartCardCmd||, CODE, READONLY, ALIGN=1 + + USART_SmartCardCmd PROC +;;;685 */ +;;;686 void USART_SmartCardCmd(USART_TypeDef* USARTx, FunctionalState NewState) +000000 b121 CBZ r1,|L26.12| +;;;687 { +;;;688 /* Check the parameters */ +;;;689 assert_param(IS_USART_123_PERIPH(USARTx)); +;;;690 assert_param(IS_FUNCTIONAL_STATE(NewState)); +;;;691 if (NewState != DISABLE) +;;;692 { +;;;693 /* Enable the SC mode by setting the SCEN bit in the CR3 register */ +;;;694 USARTx->CR3 |= CR3_SCEN_Set; +000002 8a82 LDRH r2,[r0,#0x14] +000004 f0420220 ORR r2,r2,#0x20 +000008 8282 STRH r2,[r0,#0x14] +00000a e004 B |L26.22| + |L26.12| +;;;695 } +;;;696 else +;;;697 { +;;;698 /* Disable the SC mode by clearing the SCEN bit in the CR3 register */ +;;;699 USARTx->CR3 &= CR3_SCEN_Reset; +00000c 8a82 LDRH r2,[r0,#0x14] +00000e f64f73df MOV r3,#0xffdf +000012 401a ANDS r2,r2,r3 +000014 8282 STRH r2,[r0,#0x14] + |L26.22| +;;;700 } +;;;701 } +000016 4770 BX lr +;;;702 + ENDP + + + AREA ||i.USART_SmartCardNACKCmd||, CODE, READONLY, ALIGN=1 + + USART_SmartCardNACKCmd PROC +;;;710 */ +;;;711 void USART_SmartCardNACKCmd(USART_TypeDef* USARTx, FunctionalState NewState) +000000 b121 CBZ r1,|L27.12| +;;;712 { +;;;713 /* Check the parameters */ +;;;714 assert_param(IS_USART_123_PERIPH(USARTx)); +;;;715 assert_param(IS_FUNCTIONAL_STATE(NewState)); +;;;716 if (NewState != DISABLE) +;;;717 { +;;;718 /* Enable the NACK transmission by setting the NACK bit in the CR3 register */ +;;;719 USARTx->CR3 |= CR3_NACK_Set; +000002 8a82 LDRH r2,[r0,#0x14] +000004 f0420210 ORR r2,r2,#0x10 +000008 8282 STRH r2,[r0,#0x14] +00000a e004 B |L27.22| + |L27.12| +;;;720 } +;;;721 else +;;;722 { +;;;723 /* Disable the NACK transmission by clearing the NACK bit in the CR3 register */ +;;;724 USARTx->CR3 &= CR3_NACK_Reset; +00000c 8a82 LDRH r2,[r0,#0x14] +00000e f64f73ef MOV r3,#0xffef +000012 401a ANDS r2,r2,r3 +000014 8282 STRH r2,[r0,#0x14] + |L27.22| +;;;725 } +;;;726 } +000016 4770 BX lr +;;;727 + ENDP + + + AREA ||i.USART_StructInit||, CODE, READONLY, ALIGN=1 + + USART_StructInit PROC +;;;286 */ +;;;287 void USART_StructInit(USART_InitTypeDef* USART_InitStruct) +000000 f44f5116 MOV r1,#0x2580 +;;;288 { +;;;289 /* USART_InitStruct members default value */ +;;;290 USART_InitStruct->USART_BaudRate = 9600; +000004 6001 STR r1,[r0,#0] +;;;291 USART_InitStruct->USART_WordLength = USART_WordLength_8b; +000006 2100 MOVS r1,#0 +000008 8081 STRH r1,[r0,#4] +;;;292 USART_InitStruct->USART_StopBits = USART_StopBits_1; +00000a 80c1 STRH r1,[r0,#6] +;;;293 USART_InitStruct->USART_Parity = USART_Parity_No ; +00000c 8101 STRH r1,[r0,#8] +;;;294 USART_InitStruct->USART_Mode = USART_Mode_Rx | USART_Mode_Tx; +00000e 210c MOVS r1,#0xc +000010 8141 STRH r1,[r0,#0xa] +;;;295 USART_InitStruct->USART_HardwareFlowControl = USART_HardwareFlowControl_None; +000012 2100 MOVS r1,#0 +000014 8181 STRH r1,[r0,#0xc] +;;;296 } +000016 4770 BX lr +;;;297 + ENDP + + + AREA ||i.USART_WakeUpConfig||, CODE, READONLY, ALIGN=1 + + USART_WakeUpConfig PROC +;;;504 */ +;;;505 void USART_WakeUpConfig(USART_TypeDef* USARTx, uint16_t USART_WakeUp) +000000 8982 LDRH r2,[r0,#0xc] +;;;506 { +;;;507 /* Check the parameters */ +;;;508 assert_param(IS_USART_ALL_PERIPH(USARTx)); +;;;509 assert_param(IS_USART_WAKEUP(USART_WakeUp)); +;;;510 +;;;511 USARTx->CR1 &= CR1_WAKE_Mask; +000002 f24f73ff MOV r3,#0xf7ff +000006 401a ANDS r2,r2,r3 +000008 8182 STRH r2,[r0,#0xc] +;;;512 USARTx->CR1 |= USART_WakeUp; +00000a 8982 LDRH r2,[r0,#0xc] +00000c 430a ORRS r2,r2,r1 +00000e 8182 STRH r2,[r0,#0xc] +;;;513 } +000010 4770 BX lr +;;;514 + ENDP + + +;*** Start embedded assembler *** + +#line 1 "..\\..\\Libraries\\STM32F10x_StdPeriph_Driver\\src\\stm32f10x_usart.c" + AREA ||.rev16_text||, CODE + THUMB + EXPORT |__asm___17_stm32f10x_usart_c_9565154b____REV16| +#line 114 "..\\..\\Libraries\\CMSIS\\Include\\core_cmInstr.h" +|__asm___17_stm32f10x_usart_c_9565154b____REV16| PROC +#line 115 + + rev16 r0, r0 + bx lr + ENDP + AREA ||.revsh_text||, CODE + THUMB + EXPORT |__asm___17_stm32f10x_usart_c_9565154b____REVSH| +#line 128 +|__asm___17_stm32f10x_usart_c_9565154b____REVSH| PROC +#line 129 + + revsh r0, r0 + bx lr + ENDP + +;*** End embedded assembler *** diff --git a/Project/MDK-ARM/Flash/List/system_stm32f10x.txt b/Project/MDK-ARM/Flash/List/system_stm32f10x.txt new file mode 100644 index 0000000..563967b --- /dev/null +++ b/Project/MDK-ARM/Flash/List/system_stm32f10x.txt @@ -0,0 +1,582 @@ +; generated by Component: ARM Compiler 5.06 update 7 (build 960) Tool: ArmCC [4d365d] +; commandline ArmCC [--list --split_sections --debug -c --asm --interleave -o.\flash\obj\system_stm32f10x.o --asm_dir=.\Flash\List\ --list_dir=.\Flash\List\ --depend=.\flash\obj\system_stm32f10x.d --cpu=Cortex-M3 --apcs=interwork -O0 --diag_suppress=9931,870 -I..\..\Libraries\CMSIS\Device\ST\STM32F10x\Include -I..\..\Libraries\STM32F10x_StdPeriph_Driver\inc -I..\..\Libraries\STM32_USB-FS-Device_Driver\inc -I..\..\Libraries\CMSIS\Include -I..\..\User\bsp -I..\..\User\bsp\inc -I..\..\User\app\inc -I..\..\User -IC:\Users\w1619\AppData\Local\Arm\Packs\Keil\STM32F1xx_DFP\2.4.1\Device\Include -D__MICROLIB -D__UVISION_VERSION=538 -DSTM32F10X_HD -DUSE_STDPERIPH_DRIVER -DSTM32F10X_HD --omf_browse=.\flash\obj\system_stm32f10x.crf ..\..\User\bsp\system_stm32f10x.c] + THUMB + + AREA ||i.SetSysClock||, CODE, READONLY, ALIGN=1 + + SetSysClock PROC +;;;418 */ +;;;419 static void SetSysClock(void) +000000 b510 PUSH {r4,lr} +;;;420 { +;;;421 #ifdef SYSCLK_FREQ_HSE +;;;422 SetSysClockToHSE(); +;;;423 #elif defined SYSCLK_FREQ_24MHz +;;;424 SetSysClockTo24(); +;;;425 #elif defined SYSCLK_FREQ_36MHz +;;;426 SetSysClockTo36(); +;;;427 #elif defined SYSCLK_FREQ_48MHz +;;;428 SetSysClockTo48(); +;;;429 #elif defined SYSCLK_FREQ_56MHz +;;;430 SetSysClockTo56(); +;;;431 #elif defined SYSCLK_FREQ_72MHz +;;;432 SetSysClockTo72(); +000002 f7fffffe BL SetSysClockTo72 +;;;433 #endif +;;;434 +;;;435 /* If none of the define above is enabled, the HSI is used as System clock +;;;436 source (default after reset) */ +;;;437 } +000006 bd10 POP {r4,pc} +;;;438 + ENDP + + + AREA ||i.SetSysClockTo72||, CODE, READONLY, ALIGN=2 + + SetSysClockTo72 PROC +;;;986 */ +;;;987 static void SetSysClockTo72(void) +000000 b50c PUSH {r2,r3,lr} +;;;988 { +;;;989 __IO uint32_t StartUpCounter = 0, HSEStatus = 0; +000002 2000 MOVS r0,#0 +000004 9001 STR r0,[sp,#4] +000006 9000 STR r0,[sp,#0] +;;;990 +;;;991 /* SYSCLK, HCLK, PCLK2 and PCLK1 configuration ---------------------------*/ +;;;992 /* Enable HSE */ +;;;993 RCC->CR |= ((uint32_t)RCC_CR_HSEON); +000008 4833 LDR r0,|L2.216| +00000a 6800 LDR r0,[r0,#0] +00000c f4403080 ORR r0,r0,#0x10000 +000010 4931 LDR r1,|L2.216| +000012 6008 STR r0,[r1,#0] +;;;994 +;;;995 /* Wait till HSE is ready and if Time out is reached exit */ +;;;996 do +000014 bf00 NOP + |L2.22| +;;;997 { +;;;998 HSEStatus = RCC->CR & RCC_CR_HSERDY; +000016 4830 LDR r0,|L2.216| +000018 6800 LDR r0,[r0,#0] +00001a f4003000 AND r0,r0,#0x20000 +00001e 9000 STR r0,[sp,#0] +;;;999 StartUpCounter++; +000020 9801 LDR r0,[sp,#4] +000022 1c40 ADDS r0,r0,#1 +000024 9001 STR r0,[sp,#4] +;;;1000 } while((HSEStatus == 0) && (StartUpCounter != HSE_STARTUP_TIMEOUT)); +000026 9800 LDR r0,[sp,#0] +000028 b918 CBNZ r0,|L2.50| +00002a 9801 LDR r0,[sp,#4] +00002c f5b06fa0 CMP r0,#0x500 +000030 d1f1 BNE |L2.22| + |L2.50| +;;;1001 +;;;1002 if ((RCC->CR & RCC_CR_HSERDY) != RESET) +000032 4829 LDR r0,|L2.216| +000034 6800 LDR r0,[r0,#0] +000036 f4003000 AND r0,r0,#0x20000 +00003a b110 CBZ r0,|L2.66| +;;;1003 { +;;;1004 HSEStatus = (uint32_t)0x01; +00003c 2001 MOVS r0,#1 +00003e 9000 STR r0,[sp,#0] +000040 e001 B |L2.70| + |L2.66| +;;;1005 } +;;;1006 else +;;;1007 { +;;;1008 HSEStatus = (uint32_t)0x00; +000042 2000 MOVS r0,#0 +000044 9000 STR r0,[sp,#0] + |L2.70| +;;;1009 } +;;;1010 +;;;1011 if (HSEStatus == (uint32_t)0x01) +000046 9800 LDR r0,[sp,#0] +000048 2801 CMP r0,#1 +00004a d143 BNE |L2.212| +;;;1012 { +;;;1013 /* Enable Prefetch Buffer */ +;;;1014 FLASH->ACR |= FLASH_ACR_PRFTBE; +00004c 4823 LDR r0,|L2.220| +00004e 6800 LDR r0,[r0,#0] +000050 f0400010 ORR r0,r0,#0x10 +000054 4921 LDR r1,|L2.220| +000056 6008 STR r0,[r1,#0] +;;;1015 +;;;1016 /* Flash 2 wait state */ +;;;1017 FLASH->ACR &= (uint32_t)((uint32_t)~FLASH_ACR_LATENCY); +000058 4608 MOV r0,r1 +00005a 6800 LDR r0,[r0,#0] +00005c f0200003 BIC r0,r0,#3 +000060 6008 STR r0,[r1,#0] +;;;1018 FLASH->ACR |= (uint32_t)FLASH_ACR_LATENCY_2; +000062 4608 MOV r0,r1 +000064 6800 LDR r0,[r0,#0] +000066 f0400002 ORR r0,r0,#2 +00006a 6008 STR r0,[r1,#0] +;;;1019 +;;;1020 +;;;1021 /* HCLK = SYSCLK */ +;;;1022 RCC->CFGR |= (uint32_t)RCC_CFGR_HPRE_DIV1; +00006c 481a LDR r0,|L2.216| +00006e 6840 LDR r0,[r0,#4] +000070 4919 LDR r1,|L2.216| +000072 6048 STR r0,[r1,#4] +;;;1023 +;;;1024 /* PCLK2 = HCLK */ +;;;1025 RCC->CFGR |= (uint32_t)RCC_CFGR_PPRE2_DIV1; +000074 4608 MOV r0,r1 +000076 6840 LDR r0,[r0,#4] +000078 6048 STR r0,[r1,#4] +;;;1026 +;;;1027 /* PCLK1 = HCLK */ +;;;1028 RCC->CFGR |= (uint32_t)RCC_CFGR_PPRE1_DIV2; +00007a 4608 MOV r0,r1 +00007c 6840 LDR r0,[r0,#4] +00007e f4406080 ORR r0,r0,#0x400 +000082 6048 STR r0,[r1,#4] +;;;1029 +;;;1030 #ifdef STM32F10X_CL +;;;1031 /* Configure PLLs ------------------------------------------------------*/ +;;;1032 /* PLL2 configuration: PLL2CLK = (HSE / 5) * 8 = 40 MHz */ +;;;1033 /* PREDIV1 configuration: PREDIV1CLK = PLL2 / 5 = 8 MHz */ +;;;1034 +;;;1035 RCC->CFGR2 &= (uint32_t)~(RCC_CFGR2_PREDIV2 | RCC_CFGR2_PLL2MUL | +;;;1036 RCC_CFGR2_PREDIV1 | RCC_CFGR2_PREDIV1SRC); +;;;1037 RCC->CFGR2 |= (uint32_t)(RCC_CFGR2_PREDIV2_DIV5 | RCC_CFGR2_PLL2MUL8 | +;;;1038 RCC_CFGR2_PREDIV1SRC_PLL2 | RCC_CFGR2_PREDIV1_DIV5); +;;;1039 +;;;1040 /* Enable PLL2 */ +;;;1041 RCC->CR |= RCC_CR_PLL2ON; +;;;1042 /* Wait till PLL2 is ready */ +;;;1043 while((RCC->CR & RCC_CR_PLL2RDY) == 0) +;;;1044 { +;;;1045 } +;;;1046 +;;;1047 +;;;1048 /* PLL configuration: PLLCLK = PREDIV1 * 9 = 72 MHz */ +;;;1049 RCC->CFGR &= (uint32_t)~(RCC_CFGR_PLLXTPRE | RCC_CFGR_PLLSRC | RCC_CFGR_PLLMULL); +;;;1050 RCC->CFGR |= (uint32_t)(RCC_CFGR_PLLXTPRE_PREDIV1 | RCC_CFGR_PLLSRC_PREDIV1 | +;;;1051 RCC_CFGR_PLLMULL9); +;;;1052 #else +;;;1053 /* PLL configuration: PLLCLK = HSE * 9 = 72 MHz */ +;;;1054 RCC->CFGR &= (uint32_t)((uint32_t)~(RCC_CFGR_PLLSRC | RCC_CFGR_PLLXTPRE | +000084 4608 MOV r0,r1 +000086 6840 LDR r0,[r0,#4] +000088 f420107c BIC r0,r0,#0x3f0000 +00008c 6048 STR r0,[r1,#4] +;;;1055 RCC_CFGR_PLLMULL)); +;;;1056 RCC->CFGR |= (uint32_t)(RCC_CFGR_PLLSRC_HSE | RCC_CFGR_PLLMULL9); +00008e 4608 MOV r0,r1 +000090 6840 LDR r0,[r0,#4] +000092 f44010e8 ORR r0,r0,#0x1d0000 +000096 6048 STR r0,[r1,#4] +;;;1057 #endif /* STM32F10X_CL */ +;;;1058 +;;;1059 /* Enable PLL */ +;;;1060 RCC->CR |= RCC_CR_PLLON; +000098 4608 MOV r0,r1 +00009a 6800 LDR r0,[r0,#0] +00009c f0407080 ORR r0,r0,#0x1000000 +0000a0 6008 STR r0,[r1,#0] +;;;1061 +;;;1062 /* Wait till PLL is ready */ +;;;1063 while((RCC->CR & RCC_CR_PLLRDY) == 0) +0000a2 bf00 NOP + |L2.164| +0000a4 480c LDR r0,|L2.216| +0000a6 6800 LDR r0,[r0,#0] +0000a8 f0007000 AND r0,r0,#0x2000000 +0000ac 2800 CMP r0,#0 +0000ae d0f9 BEQ |L2.164| +;;;1064 { +;;;1065 } +;;;1066 +;;;1067 /* Select PLL as system clock source */ +;;;1068 RCC->CFGR &= (uint32_t)((uint32_t)~(RCC_CFGR_SW)); +0000b0 4809 LDR r0,|L2.216| +0000b2 6840 LDR r0,[r0,#4] +0000b4 f0200003 BIC r0,r0,#3 +0000b8 4907 LDR r1,|L2.216| +0000ba 6048 STR r0,[r1,#4] +;;;1069 RCC->CFGR |= (uint32_t)RCC_CFGR_SW_PLL; +0000bc 4608 MOV r0,r1 +0000be 6840 LDR r0,[r0,#4] +0000c0 f0400002 ORR r0,r0,#2 +0000c4 6048 STR r0,[r1,#4] +;;;1070 +;;;1071 /* Wait till PLL is used as system clock source */ +;;;1072 while ((RCC->CFGR & (uint32_t)RCC_CFGR_SWS) != (uint32_t)0x08) +0000c6 bf00 NOP + |L2.200| +0000c8 4803 LDR r0,|L2.216| +0000ca 6840 LDR r0,[r0,#4] +0000cc f000000c AND r0,r0,#0xc +0000d0 2808 CMP r0,#8 +0000d2 d1f9 BNE |L2.200| + |L2.212| +;;;1073 { +;;;1074 } +;;;1075 } +;;;1076 else +;;;1077 { /* If HSE fails to start-up, the application will have wrong clock +;;;1078 configuration. User can add here some code to deal with this error */ +;;;1079 } +;;;1080 } +0000d4 bd0c POP {r2,r3,pc} +;;;1081 #endif + ENDP + +0000d6 0000 DCW 0x0000 + |L2.216| + DCD 0x40021000 + |L2.220| + DCD 0x40022000 + + AREA ||i.SystemCoreClockUpdate||, CODE, READONLY, ALIGN=2 + + SystemCoreClockUpdate PROC +;;;305 */ +;;;306 void SystemCoreClockUpdate (void) +000000 b510 PUSH {r4,lr} +;;;307 { +;;;308 uint32_t tmp = 0, pllmull = 0, pllsource = 0; +000002 2100 MOVS r1,#0 +000004 2000 MOVS r0,#0 +000006 2200 MOVS r2,#0 +;;;309 +;;;310 #ifdef STM32F10X_CL +;;;311 uint32_t prediv1source = 0, prediv1factor = 0, prediv2factor = 0, pll2mull = 0; +;;;312 #endif /* STM32F10X_CL */ +;;;313 +;;;314 #if defined (STM32F10X_LD_VL) || defined (STM32F10X_MD_VL) || (defined STM32F10X_HD_VL) +;;;315 uint32_t prediv1factor = 0; +;;;316 #endif /* STM32F10X_LD_VL or STM32F10X_MD_VL or STM32F10X_HD_VL */ +;;;317 +;;;318 /* Get SYSCLK source -------------------------------------------------------*/ +;;;319 tmp = RCC->CFGR & RCC_CFGR_SWS; +000008 4b21 LDR r3,|L3.144| +00000a 685b LDR r3,[r3,#4] +00000c f003010c AND r1,r3,#0xc +;;;320 +;;;321 switch (tmp) +000010 b121 CBZ r1,|L3.28| +000012 2904 CMP r1,#4 +000014 d006 BEQ |L3.36| +000016 2908 CMP r1,#8 +000018 d128 BNE |L3.108| +00001a e007 B |L3.44| + |L3.28| +;;;322 { +;;;323 case 0x00: /* HSI used as system clock */ +;;;324 SystemCoreClock = HSI_VALUE; +00001c 4b1d LDR r3,|L3.148| +00001e 4c1e LDR r4,|L3.152| +000020 6023 STR r3,[r4,#0] ; SystemCoreClock +;;;325 break; +000022 e027 B |L3.116| + |L3.36| +;;;326 case 0x04: /* HSE used as system clock */ +;;;327 SystemCoreClock = HSE_VALUE; +000024 4b1b LDR r3,|L3.148| +000026 4c1c LDR r4,|L3.152| +000028 6023 STR r3,[r4,#0] ; SystemCoreClock +;;;328 break; +00002a e023 B |L3.116| + |L3.44| +;;;329 case 0x08: /* PLL used as system clock */ +;;;330 +;;;331 /* Get PLL clock source and multiplication factor ----------------------*/ +;;;332 pllmull = RCC->CFGR & RCC_CFGR_PLLMULL; +00002c 4b18 LDR r3,|L3.144| +00002e 685b LDR r3,[r3,#4] +000030 f4031070 AND r0,r3,#0x3c0000 +;;;333 pllsource = RCC->CFGR & RCC_CFGR_PLLSRC; +000034 4b16 LDR r3,|L3.144| +000036 685b LDR r3,[r3,#4] +000038 f4033280 AND r2,r3,#0x10000 +;;;334 +;;;335 #ifndef STM32F10X_CL +;;;336 pllmull = ( pllmull >> 18) + 2; +00003c 2302 MOVS r3,#2 +00003e eb034090 ADD r0,r3,r0,LSR #18 +;;;337 +;;;338 if (pllsource == 0x00) +000042 b922 CBNZ r2,|L3.78| +;;;339 { +;;;340 /* HSI oscillator clock divided by 2 selected as PLL clock entry */ +;;;341 SystemCoreClock = (HSI_VALUE >> 1) * pllmull; +000044 4b15 LDR r3,|L3.156| +000046 4343 MULS r3,r0,r3 +000048 4c13 LDR r4,|L3.152| +00004a 6023 STR r3,[r4,#0] ; SystemCoreClock +00004c e00d B |L3.106| + |L3.78| +;;;342 } +;;;343 else +;;;344 { +;;;345 #if defined (STM32F10X_LD_VL) || defined (STM32F10X_MD_VL) || (defined STM32F10X_HD_VL) +;;;346 prediv1factor = (RCC->CFGR2 & RCC_CFGR2_PREDIV1) + 1; +;;;347 /* HSE oscillator clock selected as PREDIV1 clock entry */ +;;;348 SystemCoreClock = (HSE_VALUE / prediv1factor) * pllmull; +;;;349 #else +;;;350 /* HSE selected as PLL clock entry */ +;;;351 if ((RCC->CFGR & RCC_CFGR_PLLXTPRE) != (uint32_t)RESET) +00004e 4b10 LDR r3,|L3.144| +000050 685b LDR r3,[r3,#4] +000052 f4033300 AND r3,r3,#0x20000 +000056 b123 CBZ r3,|L3.98| +;;;352 {/* HSE oscillator clock divided by 2 */ +;;;353 SystemCoreClock = (HSE_VALUE >> 1) * pllmull; +000058 4b10 LDR r3,|L3.156| +00005a 4343 MULS r3,r0,r3 +00005c 4c0e LDR r4,|L3.152| +00005e 6023 STR r3,[r4,#0] ; SystemCoreClock +000060 e003 B |L3.106| + |L3.98| +;;;354 } +;;;355 else +;;;356 { +;;;357 SystemCoreClock = HSE_VALUE * pllmull; +000062 4b0c LDR r3,|L3.148| +000064 4343 MULS r3,r0,r3 +000066 4c0c LDR r4,|L3.152| +000068 6023 STR r3,[r4,#0] ; SystemCoreClock + |L3.106| +;;;358 } +;;;359 #endif +;;;360 } +;;;361 #else +;;;362 pllmull = pllmull >> 18; +;;;363 +;;;364 if (pllmull != 0x0D) +;;;365 { +;;;366 pllmull += 2; +;;;367 } +;;;368 else +;;;369 { /* PLL multiplication factor = PLL input clock * 6.5 */ +;;;370 pllmull = 13 / 2; +;;;371 } +;;;372 +;;;373 if (pllsource == 0x00) +;;;374 { +;;;375 /* HSI oscillator clock divided by 2 selected as PLL clock entry */ +;;;376 SystemCoreClock = (HSI_VALUE >> 1) * pllmull; +;;;377 } +;;;378 else +;;;379 {/* PREDIV1 selected as PLL clock entry */ +;;;380 +;;;381 /* Get PREDIV1 clock source and division factor */ +;;;382 prediv1source = RCC->CFGR2 & RCC_CFGR2_PREDIV1SRC; +;;;383 prediv1factor = (RCC->CFGR2 & RCC_CFGR2_PREDIV1) + 1; +;;;384 +;;;385 if (prediv1source == 0) +;;;386 { +;;;387 /* HSE oscillator clock selected as PREDIV1 clock entry */ +;;;388 SystemCoreClock = (HSE_VALUE / prediv1factor) * pllmull; +;;;389 } +;;;390 else +;;;391 {/* PLL2 clock selected as PREDIV1 clock entry */ +;;;392 +;;;393 /* Get PREDIV2 division factor and PLL2 multiplication factor */ +;;;394 prediv2factor = ((RCC->CFGR2 & RCC_CFGR2_PREDIV2) >> 4) + 1; +;;;395 pll2mull = ((RCC->CFGR2 & RCC_CFGR2_PLL2MUL) >> 8 ) + 2; +;;;396 SystemCoreClock = (((HSE_VALUE / prediv2factor) * pll2mull) / prediv1factor) * pllmull; +;;;397 } +;;;398 } +;;;399 #endif /* STM32F10X_CL */ +;;;400 break; +00006a e003 B |L3.116| + |L3.108| +;;;401 +;;;402 default: +;;;403 SystemCoreClock = HSI_VALUE; +00006c 4b09 LDR r3,|L3.148| +00006e 4c0a LDR r4,|L3.152| +000070 6023 STR r3,[r4,#0] ; SystemCoreClock +;;;404 break; +000072 bf00 NOP + |L3.116| +000074 bf00 NOP ;325 +;;;405 } +;;;406 +;;;407 /* Compute HCLK clock frequency ----------------*/ +;;;408 /* Get HCLK prescaler */ +;;;409 tmp = AHBPrescTable[((RCC->CFGR & RCC_CFGR_HPRE) >> 4)]; +000076 4b06 LDR r3,|L3.144| +000078 685b LDR r3,[r3,#4] +00007a f3c31303 UBFX r3,r3,#4,#4 +00007e 4c08 LDR r4,|L3.160| +000080 5ce1 LDRB r1,[r4,r3] +;;;410 /* HCLK clock frequency */ +;;;411 SystemCoreClock >>= tmp; +000082 4b05 LDR r3,|L3.152| +000084 681b LDR r3,[r3,#0] ; SystemCoreClock +000086 40cb LSRS r3,r3,r1 +000088 4c03 LDR r4,|L3.152| +00008a 6023 STR r3,[r4,#0] ; SystemCoreClock +;;;412 } +00008c bd10 POP {r4,pc} +;;;413 + ENDP + +00008e 0000 DCW 0x0000 + |L3.144| + DCD 0x40021000 + |L3.148| + DCD 0x007a1200 + |L3.152| + DCD SystemCoreClock + |L3.156| + DCD 0x003d0900 + |L3.160| + DCD AHBPrescTable + + AREA ||i.SystemInit||, CODE, READONLY, ALIGN=2 + + SystemInit PROC +;;;211 */ +;;;212 void SystemInit (void) +000000 b510 PUSH {r4,lr} +;;;213 { +;;;214 /* Reset the RCC clock configuration to the default reset state(for debug purpose) */ +;;;215 /* Set HSION bit */ +;;;216 RCC->CR |= (uint32_t)0x00000001; +000002 4813 LDR r0,|L4.80| +000004 6800 LDR r0,[r0,#0] +000006 f0400001 ORR r0,r0,#1 +00000a 4911 LDR r1,|L4.80| +00000c 6008 STR r0,[r1,#0] +;;;217 +;;;218 /* Reset SW, HPRE, PPRE1, PPRE2, ADCPRE and MCO bits */ +;;;219 #ifndef STM32F10X_CL +;;;220 RCC->CFGR &= (uint32_t)0xF8FF0000; +00000e 4608 MOV r0,r1 +000010 6840 LDR r0,[r0,#4] +000012 4910 LDR r1,|L4.84| +000014 4008 ANDS r0,r0,r1 +000016 490e LDR r1,|L4.80| +000018 6048 STR r0,[r1,#4] +;;;221 #else +;;;222 RCC->CFGR &= (uint32_t)0xF0FF0000; +;;;223 #endif /* STM32F10X_CL */ +;;;224 +;;;225 /* Reset HSEON, CSSON and PLLON bits */ +;;;226 RCC->CR &= (uint32_t)0xFEF6FFFF; +00001a 4608 MOV r0,r1 +00001c 6800 LDR r0,[r0,#0] +00001e 490e LDR r1,|L4.88| +000020 4008 ANDS r0,r0,r1 +000022 490b LDR r1,|L4.80| +000024 6008 STR r0,[r1,#0] +;;;227 +;;;228 /* Reset HSEBYP bit */ +;;;229 RCC->CR &= (uint32_t)0xFFFBFFFF; +000026 4608 MOV r0,r1 +000028 6800 LDR r0,[r0,#0] +00002a f4202080 BIC r0,r0,#0x40000 +00002e 6008 STR r0,[r1,#0] +;;;230 +;;;231 /* Reset PLLSRC, PLLXTPRE, PLLMUL and USBPRE/OTGFSPRE bits */ +;;;232 RCC->CFGR &= (uint32_t)0xFF80FFFF; +000030 4608 MOV r0,r1 +000032 6840 LDR r0,[r0,#4] +000034 f42000fe BIC r0,r0,#0x7f0000 +000038 6048 STR r0,[r1,#4] +;;;233 +;;;234 #ifdef STM32F10X_CL +;;;235 /* Reset PLL2ON and PLL3ON bits */ +;;;236 RCC->CR &= (uint32_t)0xEBFFFFFF; +;;;237 +;;;238 /* Disable all interrupts and clear pending bits */ +;;;239 RCC->CIR = 0x00FF0000; +;;;240 +;;;241 /* Reset CFGR2 register */ +;;;242 RCC->CFGR2 = 0x00000000; +;;;243 #elif defined (STM32F10X_LD_VL) || defined (STM32F10X_MD_VL) || (defined STM32F10X_HD_VL) +;;;244 /* Disable all interrupts and clear pending bits */ +;;;245 RCC->CIR = 0x009F0000; +;;;246 +;;;247 /* Reset CFGR2 register */ +;;;248 RCC->CFGR2 = 0x00000000; +;;;249 #else +;;;250 /* Disable all interrupts and clear pending bits */ +;;;251 RCC->CIR = 0x009F0000; +00003a f44f001f MOV r0,#0x9f0000 +00003e 6088 STR r0,[r1,#8] +;;;252 #endif /* STM32F10X_CL */ +;;;253 +;;;254 #if defined (STM32F10X_HD) || (defined STM32F10X_XL) || (defined STM32F10X_HD_VL) +;;;255 #ifdef DATA_IN_ExtSRAM +;;;256 SystemInit_ExtMemCtl(); +;;;257 #endif /* DATA_IN_ExtSRAM */ +;;;258 #endif +;;;259 +;;;260 /* Configure the System clock frequency, HCLK, PCLK2 and PCLK1 prescalers */ +;;;261 /* Configure the Flash Latency cycles and enable prefetch buffer */ +;;;262 SetSysClock(); +000040 f7fffffe BL SetSysClock +;;;263 +;;;264 #ifdef VECT_TAB_SRAM +;;;265 SCB->VTOR = SRAM_BASE | VECT_TAB_OFFSET; /* Vector Table Relocation in Internal SRAM. */ +;;;266 #else +;;;267 SCB->VTOR = FLASH_BASE | VECT_TAB_OFFSET; /* Vector Table Relocation in Internal FLASH. */ +000044 f04f6000 MOV r0,#0x8000000 +000048 4904 LDR r1,|L4.92| +00004a 6008 STR r0,[r1,#0] +;;;268 #endif +;;;269 } +00004c bd10 POP {r4,pc} +;;;270 + ENDP + +00004e 0000 DCW 0x0000 + |L4.80| + DCD 0x40021000 + |L4.84| + DCD 0xf8ff0000 + |L4.88| + DCD 0xfef6ffff + |L4.92| + DCD 0xe000ed08 + + AREA ||.data||, DATA, ALIGN=2 + + SystemCoreClock + DCD 0x044aa200 + AHBPrescTable +000004 00000000 DCB 0x00,0x00,0x00,0x00 +000008 00000000 DCB 0x00,0x00,0x00,0x00 +00000c 01020304 DCB 0x01,0x02,0x03,0x04 +000010 06070809 DCB 0x06,0x07,0x08,0x09 + +;*** Start embedded assembler *** + +#line 1 "..\\..\\User\\bsp\\system_stm32f10x.c" + AREA ||.rev16_text||, CODE + THUMB + EXPORT |__asm___18_system_stm32f10x_c_5d646a67____REV16| +#line 114 "..\\..\\Libraries\\CMSIS\\Include\\core_cmInstr.h" +|__asm___18_system_stm32f10x_c_5d646a67____REV16| PROC +#line 115 + + rev16 r0, r0 + bx lr + ENDP + AREA ||.revsh_text||, CODE + THUMB + EXPORT |__asm___18_system_stm32f10x_c_5d646a67____REVSH| +#line 128 +|__asm___18_system_stm32f10x_c_5d646a67____REVSH| PROC +#line 129 + + revsh r0, r0 + bx lr + ENDP + +;*** End embedded assembler *** diff --git a/Project/MDK-ARM/Flash/Obj/output.hex b/Project/MDK-ARM/Flash/Obj/output.hex new file mode 100644 index 0000000..9fe908e --- /dev/null +++ b/Project/MDK-ARM/Flash/Obj/output.hex @@ -0,0 +1,1181 @@ +:020000040800F2 +:10800000A8810020498100082D9A00080F980008D7 +:10801000299A00089D9500085DA300080000000053 +:10802000000000000000000000000000259C000887 +:108030007D96000800000000B59A0008119D000818 +:108040006381000863810008638100086381000880 +:108050006381000863810008638100086381000870 +:108060006381000863810008638100086381000860 +:108070006381000863810008638100086381000850 +:108080006381000863810008638100086381000840 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+:10C970000000000000000102030401020304060796 +:10C98000080902040608000000A24A040000000092 +:10C99000000000000102030406070809000000006F +:04000005080081313D +:00000001FF diff --git a/Project/MDK-ARM/RTE/_Flash/RTE_Components.h b/Project/MDK-ARM/RTE/_Flash/RTE_Components.h new file mode 100644 index 0000000..c642bf9 --- /dev/null +++ b/Project/MDK-ARM/RTE/_Flash/RTE_Components.h @@ -0,0 +1,21 @@ + +/* + * Auto generated Run-Time-Environment Configuration File + * *** Do not modify ! *** + * + * Project: 'project' + * Target: 'Flash' + */ + +#ifndef RTE_COMPONENTS_H +#define RTE_COMPONENTS_H + + +/* + * Define the Device Header File: + */ +#define CMSIS_device_header "stm32f10x.h" + + + +#endif /* RTE_COMPONENTS_H */ diff --git a/Project/MDK-ARM/keilkilll.bat b/Project/MDK-ARM/keilkilll.bat new file mode 100644 index 0000000..9cd200f --- /dev/null +++ b/Project/MDK-ARM/keilkilll.bat @@ -0,0 +1,27 @@ +del *.bak /s +del *.ddk /s +del *.edk /s +del *.lst /s +del *.lnp /s +del *.mpf /s +del *.mpj /s +del *.obj /s +del *.omf /s +::del *.opt /s ::ɾJLINK +del *.plg /s +del *.rpt /s +del *.tmp /s +del *.__i /s +del *.crf /s +del *.o /s +del *.d /s +del *.axf /s +del *.tra /s +del *.dep /s +del JLinkLog.txt /s + +del *.iex /s +del *.htm /s +::del *.sct /s +del *.map /s +exit diff --git a/Project/MDK-ARM/pemicro_connection_settings.ini b/Project/MDK-ARM/pemicro_connection_settings.ini new file mode 100644 index 0000000..601ad52 --- /dev/null +++ b/Project/MDK-ARM/pemicro_connection_settings.ini @@ -0,0 +1,3 @@ +[STARTUP] +CPUTARGETTYPENAME= + diff --git a/Project/MDK-ARM/project.uvgui (来自DESKTOP-A7EBCNR的冲突副本 2019-01-09_22.44.23).microsoft b/Project/MDK-ARM/project.uvgui (来自DESKTOP-A7EBCNR的冲突副本 2019-01-09_22.44.23).microsoft new file mode 100644 index 0000000..dc33674 --- /dev/null +++ b/Project/MDK-ARM/project.uvgui (来自DESKTOP-A7EBCNR的冲突副本 2019-01-09_22.44.23).microsoft @@ -0,0 +1,1815 @@ + + + + -6.1 + +
    ### uVision Project, (C) Keil Software
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    ### uVision Project, (C) Keil Software
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    ### uVision Project, (C) Keil Software
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file mode 100644 index 0000000..1c0bd85 --- /dev/null +++ b/Project/MDK-ARM/project.uvguix.wangx @@ -0,0 +1,1846 @@ + + + + -6.1 + +
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    ### uVision Project, (C) Keil Software
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    ### uVision Project, (C) Keil Software
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    ### uVision Project, (C) Keil Software
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--diag_suppress=870 + USE_STDPERIPH_DRIVER,STM32F10X_HD + + ..\..\Libraries\CMSIS\Device\ST\STM32F10x\Include;..\..\Libraries\STM32F10x_StdPeriph_Driver\inc;..\..\Libraries\STM32_USB-FS-Device_Driver\inc;..\..\Libraries\CMSIS\Include;..\..\User\bsp;..\..\User\bsp\inc;..\..\User\app\inc + + + + 1 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + + + + + + + + + 1 + 0 + 0 + 0 + 1 + 0 + 0x8000000 + 0x20000000 + + + + + + + + + + + + + App + + + main.c + 1 + ..\..\User\app\src\main.c + + + + + BSP + + + bsp_digital_tube.c + 1 + ..\..\User\bsp\src\bsp_digital_tube.c + + + bsp_beep.c + 1 + ..\..\User\bsp\src\bsp_beep.c + + + bsp_key.c + 1 + ..\..\User\bsp\src\bsp_key.c + + + bsp_drv8880.c + 1 + ..\..\User\bsp\src\bsp_drv8880.c + + + bsp_step_moto.c + 1 + ..\..\User\bsp\src\bsp_step_moto.c + + + bsp_timer.c + 1 + ..\..\User\bsp\src\bsp_timer.c + + + bsp.c + 1 + ..\..\User\bsp\bsp.c + + + stm32f10x_it.c + 1 + ..\..\User\bsp\stm32f10x_it.c + + + stm32f10x_assert.c + 1 + ..\..\User\bsp\stm32f10x_assert.c + + + bsp_uart_fifo.c + 1 + ..\..\User\bsp\src\bsp_uart_fifo.c + + + bsp_tim_pwm.c + 1 + ..\..\User\bsp\src\bsp_tim_pwm.c + + + bsp_eeprom_24xx.c + 1 + ..\..\User\bsp\src\bsp_eeprom_24xx.c + + + bsp_i2c_gpio.c + 1 + ..\..\User\bsp\src\bsp_i2c_gpio.c + + + + + MDK-ARM + + + startup_stm32f10x_hd.s + 2 + ..\..\Libraries\CMSIS\Device\ST\STM32F10x\Source\Templates\arm\startup_stm32f10x_hd.s + + + + + StdPeriph_Driver + + + stm32f10x_gpio.c + 1 + ..\..\Libraries\STM32F10x_StdPeriph_Driver\src\stm32f10x_gpio.c + + + stm32f10x_rcc.c + 1 + ..\..\Libraries\STM32F10x_StdPeriph_Driver\src\stm32f10x_rcc.c + + + misc.c + 1 + ..\..\Libraries\STM32F10x_StdPeriph_Driver\src\misc.c + + + stm32f10x_tim.c + 1 + ..\..\Libraries\STM32F10x_StdPeriph_Driver\src\stm32f10x_tim.c + + + stm32f10x_usart.c + 1 + ..\..\Libraries\STM32F10x_StdPeriph_Driver\src\stm32f10x_usart.c + + + stm32f10x_dac.c + 1 + ..\..\Libraries\STM32F10x_StdPeriph_Driver\src\stm32f10x_dac.c + + + + + CMSIS + + + system_stm32f10x.c + 1 + ..\..\User\bsp\system_stm32f10x.c + + + + + Doc + + + 01.例程功能说明.txt + 5 + ..\..\Doc\01.例程功能说明.txt + + + 02.开发环境说明.txt + 5 + ..\..\Doc\02.开发环境说明.txt + + + + + + + CpuRAM + 0x4 + ARM-ADS + + + STM32F407IG + STMicroelectronics + IRAM(0x20000000-0x2001FFFF) IRAM2(0x10000000-0x1000FFFF) IROM(0x8000000-0x80FFFFF) CLOCK(25000000) CPUTYPE("Cortex-M4") FPU2 + + "Startup\ST\STM32F4xx\startup_stm32f4xx.s" ("STM32F4xx Startup Code") + UL2CM3(-O207 -S0 -C0 -FO7 -FD20000000 -FC800 -FN1 -FF0STM32F4xx_1024 -FS08000000 -FL0100000) + 6104 + stm32f4xx.h + + + + + + + + + + SFD\ST\STM32F4xx\STM32F40x.sfr + 0 + 0 + + + + ST\STM32F4xx\ + ST\STM32F4xx\ + + 0 + 0 + 0 + 0 + 1 + + .\CpuRAM\Obj\ + output + 1 + 0 + 1 + 1 + 0 + .\CpuRAM\List\ + 1 + 0 + 0 + + 0 + 0 + + + 0 + 0 + 0 + 0 + + + 0 + 0 + + + 0 + 0 + 0 + 0 + + + 0 + 0 + CopyHex_CpuRAM.bat + + 0 + 0 + 0 + 0 + + 0 + + + + 0 + 0 + 0 + 0 + 0 + 1 + 0 + 0 + 0 + 0 + 3 + + + 1 + + + SARMCM3.DLL + -MPU -REMAP + DCM.DLL + -pCM4 + SARMCM3.DLL + -MPU + TCM.DLL + -pCM4 + + + + 1 + 0 + 0 + 0 + 16 + + + 0 + 0 + 1 + 1 + 1 + 1 + 1 + 1 + 0 + 1 + + + 1 + 0 + 1 + 1 + 1 + 1 + 0 + 1 + 0 + 1 + + 0 + 7 + + + + + + + + + + + + + .\CpuRAM.ini + Segger\JL2CM3.dll + + + + + 1 + 0 + 0 + 0 + 1 + 4103 + + 0 + Segger\JL2CM3.dll + + + + + + 0 + + + + 0 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 0 + 1 + 1 + 0 + 1 + 1 + 0 + 0 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 0 + "Cortex-M4" + + 0 + 0 + 0 + 1 + 1 + 0 + 0 + 1 + 1 + 0 + 8 + 1 + 0 + 0 + 0 + 3 + 5 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 1 + 0 + 0 + 0 + 0 + 0 + 1 + + + 0 + 0x0 + 0x0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x20000000 + 0x20000 + + + 1 + 0x8000000 + 0x100000 + + + 0 + 0x0 + 0x0 + + + 1 + 0x0 + 0x0 + + + 1 + 0x0 + 0x0 + + + 1 + 0x0 + 0x0 + + + 1 + 0x20000000 + 0x20000 + + + 1 + 0x0 + 0x0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x10000000 + 0x10000 + + + + + + 0 + 1 + 0 + 0 + 1 + 0 + 0 + 0 + 0 + 0 + 2 + 0 + 0 + 0 + 0 + 1 + 1 + 1 + 1 + 0 + 0 + 0 + + --diag_suppress=870 + USE_STDPERIPH_DRIVER,STM32F10X_HD,VECT_TAB_SRAM + + ..\..\Libraries\CMSIS\Device\ST\STM32F10x\Include;..\..\Libraries\STM32F10x_StdPeriph_Driver\inc;..\..\Libraries\STM32_USB-FS-Device_Driver\inc;..\..\Libraries\CMSIS\Include;..\..\User\bsp;..\..\User\bsp\inc;..\..\User\app\inc;..\..\User\fonts;..\..\User\images;..\..\User\uIP\uip;..\..\User\uIP\http;..\..\User\uIP\dm9000;..\..\User\FatFS\src;..\..\User\usb_mass;..\..\User\CH376\inc + + + + 1 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + + + + + + + + + 1 + 0 + 0 + 0 + 1 + 0 + 0x8000000 + 0x20000000 + + + + + + + + + + + + + App + + + main.c + 1 + ..\..\User\app\src\main.c + + + + + BSP + + + bsp_digital_tube.c + 1 + ..\..\User\bsp\src\bsp_digital_tube.c + + + bsp_beep.c + 1 + ..\..\User\bsp\src\bsp_beep.c + + + bsp_key.c + 1 + ..\..\User\bsp\src\bsp_key.c + + + bsp_drv8880.c + 1 + ..\..\User\bsp\src\bsp_drv8880.c + + + bsp_step_moto.c + 1 + ..\..\User\bsp\src\bsp_step_moto.c + + + bsp_timer.c + 1 + ..\..\User\bsp\src\bsp_timer.c + + + bsp.c + 1 + ..\..\User\bsp\bsp.c + + + stm32f10x_it.c + 1 + ..\..\User\bsp\stm32f10x_it.c + + + stm32f10x_assert.c + 1 + ..\..\User\bsp\stm32f10x_assert.c + + + bsp_uart_fifo.c + 1 + ..\..\User\bsp\src\bsp_uart_fifo.c + + + bsp_tim_pwm.c + 1 + ..\..\User\bsp\src\bsp_tim_pwm.c + + + bsp_eeprom_24xx.c + 1 + ..\..\User\bsp\src\bsp_eeprom_24xx.c + + + bsp_i2c_gpio.c + 1 + ..\..\User\bsp\src\bsp_i2c_gpio.c + + + + + MDK-ARM + + + startup_stm32f10x_hd.s + 2 + ..\..\Libraries\CMSIS\Device\ST\STM32F10x\Source\Templates\arm\startup_stm32f10x_hd.s + + + + + StdPeriph_Driver + + + stm32f10x_gpio.c + 1 + ..\..\Libraries\STM32F10x_StdPeriph_Driver\src\stm32f10x_gpio.c + + + stm32f10x_rcc.c + 1 + ..\..\Libraries\STM32F10x_StdPeriph_Driver\src\stm32f10x_rcc.c + + + misc.c + 1 + ..\..\Libraries\STM32F10x_StdPeriph_Driver\src\misc.c + + + stm32f10x_tim.c + 1 + ..\..\Libraries\STM32F10x_StdPeriph_Driver\src\stm32f10x_tim.c + + + stm32f10x_usart.c + 1 + ..\..\Libraries\STM32F10x_StdPeriph_Driver\src\stm32f10x_usart.c + + + stm32f10x_dac.c + 1 + ..\..\Libraries\STM32F10x_StdPeriph_Driver\src\stm32f10x_dac.c + + + + + CMSIS + + + system_stm32f10x.c + 1 + ..\..\User\bsp\system_stm32f10x.c + + + + + Doc + + + 01.例程功能说明.txt + 5 + ..\..\Doc\01.例程功能说明.txt + + + 02.开发环境说明.txt + 5 + ..\..\Doc\02.开发环境说明.txt + + + + + + + +     diff --git a/Project/MDK-ARM/project.uvprojx b/Project/MDK-ARM/project.uvprojx new file mode 100644 index 0000000..a8ad233 --- /dev/null +++ b/Project/MDK-ARM/project.uvprojx @@ -0,0 +1,1100 @@ + + + + 2.1 + +
    ### uVision Project, (C) Keil Software
    + + + + Flash + 0x4 + ARM-ADS + 5060960::V5.06 update 7 (build 960)::.\ARMCC + 5060960::V5.06 update 7 (build 960)::.\ARMCC + 0 + + + STM32F103ZE + STMicroelectronics + Keil.STM32F1xx_DFP.2.4.1 + https://www.keil.com/pack/ + IRAM(0x20000000,0x00010000) IROM(0x08000000,0x00080000) CPUTYPE("Cortex-M3") CLOCK(12000000) ELITTLE + + + UL2CM3(-S0 -C0 -P0 -FD20000000 -FC1000 -FN1 -FF0STM32F10x_512 -FS08000000 -FL080000 -FP0($$Device:STM32F103ZE$Flash\STM32F10x_512.FLM)) + 0 + $$Device:STM32F103ZE$Device\Include\stm32f10x.h + + + + + + + + + + $$Device:STM32F103ZE$SVD\STM32F103xx.svd + 0 + 0 + + + + + + + 0 + 0 + 0 + 0 + 1 + + .\Flash\Obj\ + output + 1 + 0 + 1 + 1 + 1 + .\Flash\List\ + 1 + 0 + 0 + + 0 + 0 + + + 0 + 0 + 0 + 0 + + + 0 + 0 + + + 0 + 0 + 0 + 0 + + + 0 + 1 + + C:\Keil_v5\ARM\ARMCC\bin\fromelf.exe --bincombined --output=.\..\bin_file\Update.bin !L + 1 + 0 + 0 + 0 + + 0 + + + + 0 + 0 + 0 + 0 + 0 + 1 + 0 + 0 + 0 + 0 + 3 + + + 1 + + + SARMCM3.DLL + -REMAP + DCM.DLL + -pCM3 + SARMCM3.DLL + + TCM.DLL + -pCM3 + + + + 1 + 0 + 0 + 0 + 16 + + + + + 1 + 0 + 0 + 1 + 1 + 4101 + + 1 + STLink\ST-LINKIII-KEIL_SWO.dll + "" () + + + + + 0 + + + + 0 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 0 + 1 + 1 + 0 + 1 + 1 + 0 + 0 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 0 + "Cortex-M3" + + 0 + 0 + 0 + 1 + 1 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 8 + 1 + 0 + 0 + 0 + 3 + 3 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 1 + 0 + 0 + 0 + 0 + 1 + 0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x20000000 + 0x10000 + + + 1 + 0x8000000 + 0x80000 + + + 0 + 0x0 + 0x0 + + + 1 + 0x0 + 0x0 + + + 1 + 0x0 + 0x0 + + + 1 + 0x0 + 0x0 + + + 1 + 0x8008000 + 0x80000 + + + 1 + 0x0 + 0x0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x20000000 + 0x10000 + + + 0 + 0x0 + 0x0 + + + + + + 0 + 1 + 0 + 0 + 1 + 0 + 0 + 0 + 0 + 0 + 2 + 0 + 0 + 0 + 0 + 0 + 1 + 5 + 1 + 1 + 0 + 0 + 0 + + --diag_suppress=870 + USE_STDPERIPH_DRIVER,STM32F10X_HD + + ..\..\Libraries\CMSIS\Device\ST\STM32F10x\Include;..\..\Libraries\STM32F10x_StdPeriph_Driver\inc;..\..\Libraries\STM32_USB-FS-Device_Driver\inc;..\..\Libraries\CMSIS\Include;..\..\User\bsp;..\..\User\bsp\inc;..\..\User\app\inc;..\..\User + + + + 1 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 4 + + + + + + + + + 1 + 0 + 0 + 0 + 1 + 0 + 0x8000000 + 0x20000000 + + + + + + + + + + + + + App + + + main.c + 1 + ..\..\User\app\src\main.c + + + + + BSP + + + bsp_digital_tube.c + 1 + ..\..\User\bsp\src\bsp_digital_tube.c + + + bsp_beep.c + 1 + ..\..\User\bsp\src\bsp_beep.c + + + bsp_key.c + 1 + ..\..\User\bsp\src\bsp_key.c + + + bsp_drv8880.c + 1 + ..\..\User\bsp\src\bsp_drv8880.c + + + bsp_step_moto.c + 1 + ..\..\User\bsp\src\bsp_step_moto.c + + + bsp_timer.c + 1 + ..\..\User\bsp\src\bsp_timer.c + + + bsp.c + 1 + ..\..\User\bsp\bsp.c + + + stm32f10x_it.c + 1 + ..\..\User\bsp\stm32f10x_it.c + + + stm32f10x_assert.c + 1 + ..\..\User\bsp\stm32f10x_assert.c + + + bsp_tim_pwm.c + 1 + ..\..\User\bsp\src\bsp_tim_pwm.c + + + bsp_eeprom_24xx.c + 1 + ..\..\User\bsp\src\bsp_eeprom_24xx.c + + + bsp_i2c_gpio.c + 1 + ..\..\User\bsp\src\bsp_i2c_gpio.c + + + bsp_usart_dma.c + 1 + ..\..\User\bsp\src\bsp_usart_dma.c + + + + + MDK-ARM + + + startup_stm32f10x_hd.s + 2 + ..\..\Libraries\CMSIS\Device\ST\STM32F10x\Source\Templates\arm\startup_stm32f10x_hd.s + + + + + StdPeriph_Driver + + + stm32f10x_gpio.c + 1 + ..\..\Libraries\STM32F10x_StdPeriph_Driver\src\stm32f10x_gpio.c + + + stm32f10x_rcc.c + 1 + ..\..\Libraries\STM32F10x_StdPeriph_Driver\src\stm32f10x_rcc.c + + + misc.c + 1 + ..\..\Libraries\STM32F10x_StdPeriph_Driver\src\misc.c + + + stm32f10x_tim.c + 1 + ..\..\Libraries\STM32F10x_StdPeriph_Driver\src\stm32f10x_tim.c + + + stm32f10x_usart.c + 1 + ..\..\Libraries\STM32F10x_StdPeriph_Driver\src\stm32f10x_usart.c + + + stm32f10x_dac.c + 1 + ..\..\Libraries\STM32F10x_StdPeriph_Driver\src\stm32f10x_dac.c + + + stm32f10x_adc.c + 1 + ..\..\Libraries\STM32F10x_StdPeriph_Driver\src\stm32f10x_adc.c + + + stm32f10x_dma.c + 1 + ..\..\Libraries\STM32F10x_StdPeriph_Driver\src\stm32f10x_dma.c + + + + + CMSIS + + + system_stm32f10x.c + 1 + ..\..\User\bsp\system_stm32f10x.c + + + + + Doc + + + 01.例程功能说明.txt + 5 + ..\..\Doc\01.例程功能说明.txt + + + 02.开发环境说明.txt + 5 + ..\..\Doc\02.开发环境说明.txt + + + + + + + CpuRAM + 0x4 + ARM-ADS + 0 + + + STM32F407IG + STMicroelectronics + Keil.STM32F4xx_DFP.2.17.1 + https://www.keil.com/pack/ + + + + + 0 + + + + + + + + + + + + 0 + 0 + + + + ST\STM32F4xx\ + ST\STM32F4xx\ + + 0 + 0 + 0 + 0 + 1 + + .\CpuRAM\Obj\ + output + 1 + 0 + 1 + 1 + 0 + .\CpuRAM\List\ + 1 + 0 + 0 + + 0 + 0 + + + 0 + 0 + 0 + 0 + + + 0 + 0 + + + 0 + 0 + 0 + 0 + + + 0 + 0 + CopyHex_CpuRAM.bat + + 0 + 0 + 0 + 0 + + 0 + + + + 0 + 0 + 0 + 0 + 0 + 1 + 0 + 0 + 0 + 0 + 3 + + + 1 + + + + + + + + + + + + + + 1 + 0 + 0 + 0 + 16 + + + + + 1 + 0 + 0 + 0 + 1 + 4103 + + 0 + Segger\JL2CM3.dll + + + + + + 0 + + + + 0 + 1 + 1 + 1 + 1 + 1 + 1 + 1 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..\..\Libraries\CMSIS\Device\ST\STM32F10x\Include;..\..\Libraries\STM32F10x_StdPeriph_Driver\inc;..\..\Libraries\STM32_USB-FS-Device_Driver\inc;..\..\Libraries\CMSIS\Include;..\..\User\bsp;..\..\User\bsp\inc;..\..\User\app\inc;..\..\User\fonts;..\..\User\images;..\..\User\uIP\uip;..\..\User\uIP\http;..\..\User\uIP\dm9000;..\..\User\FatFS\src;..\..\User\usb_mass;..\..\User\CH376\inc + + + + 1 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 4 + + + + + + + + + 1 + 0 + 0 + 0 + 1 + 0 + 0x8000000 + 0x20000000 + + + + + + + + + + + + + App + + + main.c + 1 + ..\..\User\app\src\main.c + + + + + BSP + + + bsp_digital_tube.c + 1 + ..\..\User\bsp\src\bsp_digital_tube.c + + + bsp_beep.c + 1 + ..\..\User\bsp\src\bsp_beep.c + + + bsp_key.c + 1 + ..\..\User\bsp\src\bsp_key.c + + + bsp_drv8880.c + 1 + ..\..\User\bsp\src\bsp_drv8880.c + + + bsp_step_moto.c + 1 + ..\..\User\bsp\src\bsp_step_moto.c + + + bsp_timer.c + 1 + ..\..\User\bsp\src\bsp_timer.c + + + bsp.c + 1 + ..\..\User\bsp\bsp.c + + + stm32f10x_it.c + 1 + ..\..\User\bsp\stm32f10x_it.c + + + stm32f10x_assert.c + 1 + ..\..\User\bsp\stm32f10x_assert.c + + + bsp_tim_pwm.c + 1 + ..\..\User\bsp\src\bsp_tim_pwm.c + + + bsp_eeprom_24xx.c + 1 + ..\..\User\bsp\src\bsp_eeprom_24xx.c + + + bsp_i2c_gpio.c + 1 + ..\..\User\bsp\src\bsp_i2c_gpio.c + + + bsp_usart_dma.c + 1 + ..\..\User\bsp\src\bsp_usart_dma.c + + + + + MDK-ARM + + + startup_stm32f10x_hd.s + 2 + ..\..\Libraries\CMSIS\Device\ST\STM32F10x\Source\Templates\arm\startup_stm32f10x_hd.s + + + + + StdPeriph_Driver + + + stm32f10x_gpio.c + 1 + ..\..\Libraries\STM32F10x_StdPeriph_Driver\src\stm32f10x_gpio.c + + + stm32f10x_rcc.c + 1 + ..\..\Libraries\STM32F10x_StdPeriph_Driver\src\stm32f10x_rcc.c + + + misc.c + 1 + ..\..\Libraries\STM32F10x_StdPeriph_Driver\src\misc.c + + + stm32f10x_tim.c + 1 + ..\..\Libraries\STM32F10x_StdPeriph_Driver\src\stm32f10x_tim.c + + + stm32f10x_usart.c + 1 + ..\..\Libraries\STM32F10x_StdPeriph_Driver\src\stm32f10x_usart.c + + + stm32f10x_dac.c + 1 + ..\..\Libraries\STM32F10x_StdPeriph_Driver\src\stm32f10x_dac.c + + + stm32f10x_adc.c + 1 + ..\..\Libraries\STM32F10x_StdPeriph_Driver\src\stm32f10x_adc.c + + + stm32f10x_dma.c + 1 + ..\..\Libraries\STM32F10x_StdPeriph_Driver\src\stm32f10x_dma.c + + + + + CMSIS + + + system_stm32f10x.c + 1 + ..\..\User\bsp\system_stm32f10x.c + + + + + Doc + + + 01.例程功能说明.txt + 5 + ..\..\Doc\01.例程功能说明.txt + + + 02.开发环境说明.txt + 5 + ..\..\Doc\02.开发环境说明.txt + + + + + + + + + + + + + + + + + project + 1 + + + + +     diff --git a/Project/MDK-ARM/说明.txt b/Project/MDK-ARM/说明.txt new file mode 100644 index 0000000..b5743d2 --- /dev/null +++ b/Project/MDK-ARM/说明.txt @@ -0,0 +1,9 @@ +project.uvproj MDK uV4ļ,˫ļMDK + +project.uvopt MDK uV4ò + +CpuRAM.ini CPUڲRAMԵĽű(ıļ)ʱԶִнűļװCPUڲRAM + +CopyHex_Flash.bat ļ,ӳɹFlash\ObjµHexļƵǰĿ¼ + +CopyHex_CpuRAM.bat ļ,ӳɹCpuRAM\ObjµHexļƵǰĿ¼ \ No newline at end of file diff --git a/Project/bin_file/Update.bin b/Project/bin_file/Update.bin new file mode 100644 index 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zVZGnFTfIcDRBO4~5puk0NtM>~P~0F_qUZOZ=N_%+D^fi_ zJuGQDsV8@-YvC0c{0x#}GWhc_v(gxcUBj*NP5(&-E5Oe);|nzo7b3lPyiC(`v##j5 zWdHVpUQz~+59cbHHnkQ2N0`fWVG`$24Ts6#;jhSGW1?7Vp&Tu&9?yU!d#!|4V*Xs4 zzXx})peuI}Z0`g=4I|>c%?pax;Q#xvW=(%6#8z|6Gck`l^zXTPfOl{6{oznIWFDzbDCI%i}zX_@JO=aSyEe}lO);DPjcVfR;xq1yYEpgN4#^%in*zU8C zZFbmu@CBl_CpE6wyt?_nL?QP!Uu6>M|1~rCcLnfA2z#_Q5)&W|$V!v2BwWL0m{GGFQKP?l1quD}O0?Nc*$?mA@oHoAxLCl|NQ4fdvX(b`x}7^MW}Q z3vQTKp=rLPhMiEyKbTViC7FaltDXx!3&r~9_kI9u!26&6#n}UoC$()#Z_i`&G=g*g zH}vKv$-RB%_3kT;p`|3z#rXXx*kxx? 2100) + { + key4_adc = 2;//ǰ + } + else if(key4_adc <= 1100) + { + key4_adc = 1;// + } + else if((key4_adc > 1100)&&(key4_adc <= 2100)) + { + key4_adc = 0;// + } + return key4_adc; +} +u16 get_key5_adc(void) +{ + u16 key5_adc = 0; + u16 ad_value; + + ad_value = Get_Adc_Average(ADC_Channel_2,10); + +// electric_quantity_percent = ((ad_value*3.3/4096.0)-1.846)*100/0.52; + key5_adc = (ad_value*3.3/4096.0); + + if(key5_adc >= 2800) + { + key5_adc = 1;//ǰ + } + else if(key5_adc <= 600) + { + key5_adc = 2;// + } + else if((key5_adc > 600)&&(key5_adc < 2800)) + { + key5_adc = 0;// + } + return key5_adc; +} + +void motor_dir(uint32_t freq, uint8_t _dir, int32_t _stpes) +{ + // [r,1,1500,108288] +// freq = get_run_freq(); +// pulse = get_pulse(); + if(g_tTube.state == WORK) + { + if(_dir == 1) + { + _dir = 1; + g_tMoto.sv_pulse = g_tMoto.sv_pulse+100; + } + else if(_dir == 0) + { + _dir = 0; + g_tMoto.sv_pulse = g_tMoto.sv_pulse-100; + } + + if(g_tMoto.pv_pulse 55600) + { + g_tMoto.sv_pulse = 55600; + } + else if(g_tMoto.sv_pulse <= 55600) + { + MOTO_Start(freq, 0, 100); + } + } + else if(g_tMoto.pv_pulse>g_tMoto.sv_pulse) + { + if (g_tMoto.sv_pulse < -1600) + { + g_tMoto.sv_pulse = -1600; + } + else if(g_tMoto.sv_pulse >= -1600) + { + MOTO_Start(freq, 1, 100); + } + } + } +} +int main(void) +{ + uint8_t ucKeyCode; + uint32_t freq = 1500; + uint16_t motor_move1 = 0; + uint16_t motor_move2 = 0; + bsp_Init(); /* Ӳʼ */ + Adc_Init(); //ADCʼ + BEEP_Start(freq, 20, 1, 1); + + //g_tTube.state = WORK; + // MOTO_Stop(); + //g_tMoto.CurrentStep = 0; + + /* ѭ */ + while (1) + { + bsp_Idle(); /* CPUʱִеĺ bsp.c */ + uart_msg_idle(); + if(Flag_100ms == 1) + { + Flag_100ms = 0; + motor_move1 = get_key4_adc(); + motor_move2 = get_key5_adc(); + if(motor_move1 == 1)//key4 + { + motor_move1 = 0; + //ǰ + motor_dir(1500, 0, 3000); + } + else if(motor_move1 == 2) + { + motor_move1 = 0; + // + motor_dir(1500, 1, 3000); + } + } + /* ¼ */ + ucKeyCode = bsp_GetKey(); + + if (ucKeyCode > 0) + { + /* м */ + switch (ucKeyCode)//key6 + { + case KEY_DOWN_K6: //key6 ̰ + { + BEEP_KeyTone(); // ʾ + key1_long_task(); // ̰һлʾǶȻ + break; + } + + case KEY_DOWN_K1: //Key1 ̰ + { + BEEP_KeyTone(); // ʾ + bsp_ToogleDispMode(); // K1ʱλ + break; + } + case KEY_DOWN_K2: //Key2 ̰ + { + BEEP_KeyTone(); // ʾ + + key2_task(); // K2ʱλ + break; + } + + + case KEY_LONG_K1:// + { + //BEEP_Start(freq, 5, 5, 3); // K1 + key1_long_task(); // + break; + } + + + + default: + break; + } + } + + } +} + +void key1_long_task(void) +{ // ת٣10ÿ + if(IsKeyDown2()) + { + BEEP_Start(1500, 5, 5, 3); + // Ѿˣѣתλù + } + if(g_tTube.state == IDLE) + { + g_tTube.state = SEARCH; // ϵ󣬳K1ģʽ + if(g_tTube.disp_mode == MODE_PULSE) + { + bsp_drv8880_config_dir(DIR_CW); + MOTO_Start(1504, 1, 67680); // 67680壬λת1.25Ȧ + } // ת٣10ÿ + else if(g_tTube.disp_mode == MODE_ANGLE) + { + bsp_drv8880_config_dir(DIR_CCW); + MOTO_Start(1504,1, 67680); // 67680壬λת1.25Ȧ + } + } + else if(g_tTube.state == WORK && g_tMoto.CurrentStep != 0) + { + g_tTube.state = SEARCH; // ϵ󣬳K1ģʽ + if(g_tTube.disp_mode == MODE_PULSE) + { + bsp_drv8880_config_dir(DIR_CW); + MOTO_Start(1504, 1, 67680); // 67680壬λת1.25Ȧ + } // ת٣10ÿ + else if(g_tTube.disp_mode == MODE_ANGLE) + { + bsp_drv8880_config_dir(DIR_CCW); + MOTO_Start(1504,1, 67680); // 67680壬λת1.25Ȧ + } + } + // ת٣10ÿ +} + +void key2_task(void) +{ + DISABLE_INT(); + if(g_tTube.state == SEARCH) + { + g_tTube.state = WORK; + MOTO_Stop(); + g_tMoto.CurrentStep = 0; + } + ENABLE_INT(); +} + +uint32_t get_run_freq(void) // [r,1,1500,108288] +{ + uint32_t i=0; + i += (g_RxBuf[5]-'0')*1000; + i += (g_RxBuf[6]-'0')*100; + i += (g_RxBuf[7]-'0')*10; + i += (g_RxBuf[8]-'0')*1; + return i; +} + +uint32_t get_zero_freq(void) // [z,1,1500] +{ + uint32_t i=0; + i += (g_RxBuf[5]-'0')*1000; + i += (g_RxBuf[6]-'0')*100; + i += (g_RxBuf[7]-'0')*10; + i += (g_RxBuf[8]-'0')*1; + return i; +} + +uint32_t get_pulse(void) +{ + uint32_t i=0; + i += (g_RxBuf[10]-'0')*100000; + i += (g_RxBuf[11]-'0')*10000; + i += (g_RxBuf[12]-'0')*1000; + i += (g_RxBuf[13]-'0')*100; + i += (g_RxBuf[14]-'0')*10; + i += (g_RxBuf[15]-'0')*1; + return i; +} + +void search_zero(uint8_t dir,uint32_t freq) +{ + if(g_tMoto.Running == 1) // ˶Уֹͣ + { + MOTO_Stop(); + } + + // ת٣10ÿ + if(IsKeyDown2()) + { + BEEP_Start(1500, 5, 5, 3); + // Ѿˣѣתλù + } + if(g_tTube.state == IDLE) + { + g_tTube.state = SEARCH; // ϵ󣬳K1ģʽ + if(g_tTube.disp_mode == MODE_PULSE) + { + bsp_drv8880_config_dir(DIR_CW); + MOTO_Start(1504, 1, 67680); // 67680壬λת1.25Ȧ + } // ת٣10ÿ + else if(g_tTube.disp_mode == MODE_ANGLE) + { + bsp_drv8880_config_dir(DIR_CCW); + MOTO_Start(1504,1, 67680); // 67680壬λת1.25Ȧ + } + } + else if(g_tTube.state == WORK && g_tMoto.CurrentStep != 0) + { + g_tTube.state = SEARCH; // ϵ󣬳K1ģʽ + if(g_tTube.disp_mode == MODE_PULSE) + { + bsp_drv8880_config_dir(DIR_CW); + MOTO_Start(1504, 1, 67680); // 67680壬λת1.25Ȧ + } // ת٣10ÿ + else if(g_tTube.disp_mode == MODE_ANGLE) + { + bsp_drv8880_config_dir(DIR_CCW); + MOTO_Start(1504,1, 67680); // 67680壬λת1.25Ȧ + } + } + // ת٣10ÿ + +} + + + + +void send_sv_2_uart(void) +{ + if(g_tMoto.pv_pulse>=0) + { + printf("[w,1,%06d]",g_tMoto.pv_pulse); + } + else + { + printf("[w,0,%06d]",-g_tMoto.pv_pulse); + } +} + +void print_sys_info(void) +{ + printf("\r\n"); + printf("----------------------------->\r\n"); + printf("-> 豸ƣתƷ˿\r\n"); + printf("-> software verson: V1.1\r\n"); + printf("-> compile time: %s\r\n",__TIME__); + printf("-> compile date: %s\r\n",__DATE__); + printf("-> [ೡ¿Ƽ޹˾]\r\n"); + printf("------------------------------\r\n"); + printf("->\r\n"); + printf("1. [s] // ֹͣת\r\n"); + printf("2. [?] // ȡǰλ\r\n"); + printf("3. [MF] // ӡϵͳϢ\r\n"); + printf("4. [z,1,1500] // ,1Ϊ˳ʱת0Ϊʱת1500ΪƵ\r\n"); + printf("5. [r,1,1500,108288] // ת1Ϊ˳ʱת0Ϊʱת1500ΪƵʣ108288ΪҪת\r\n"); + printf("<-----------------------------\r\n"); +} + +void uart_msg_idle(void) +{ + uint8_t n=0; + uint32_t freq=0; + uint32_t pulse=0; + uint8_t _dir=0; + + if(g_ucRxRcvNewFlag) + { + g_ucRxRcvNewFlag = 0; + + n = strlen((char*)g_RxBuf); + if(n==3) + { + switch(g_RxBuf[1]) + { + //case '?': printf("%d\r\n",g_tTube.pulse); break; + //case '?': printf("[w,1,054050]"); break; + case '?': send_sv_2_uart(); break; + case 's': MOTO_Stop(); break; + //case 'z': search_zero(1); break; + default: break; + } + } + else if(n==4) + { + if(IS_MF_VALID) + { + print_sys_info(); + } + } + else if(n==10) // [z,1,1500] + { + freq = get_zero_freq(); + if(IS_ZERO_BUF_VALID() && freq<=1504) + { + if(g_RxBuf[3]=='1') + { + search_zero(1,freq); // ˳ʱ + } + else + { + search_zero(0,freq); // ʱ + } + } + else + { + BEEP_Start(1500, 5, 5, 3); + } + } + else if((n==17)&&(g_RxBuf[1]=='r')) + { + // [r,1,1500,108288] + freq = get_run_freq(); + pulse = get_pulse(); + g_tMoto.sv_pulse = pulse; + + if(g_RxBuf[3]=='1') + { + _dir = 1; + g_tMoto.sv_pulse = -g_tMoto.sv_pulse; + } + else if(g_RxBuf[3]=='0') + { + _dir = 0; + + } + else + { + BEEP_Start(1500, 5, 5, 3); + return ; + } + + if(g_tMoto.pv_pulseg_tMoto.sv_pulse) + { + //MOTO_Start(freq, _dir, 123); + MOTO_Start(freq, 1, 123); + } + else + { + BEEP_Start(1500, 5, 5, 3); + } + } + else + { + BEEP_Start(1500, 5, 5, 3); + } + } +} + +//-------------------------------- End of file --------------------------------- diff --git a/User/app/src/main.c b/User/app/src/main.c new file mode 100644 index 0000000..49e7e77 --- /dev/null +++ b/User/app/src/main.c @@ -0,0 +1,447 @@ +//------------------------------------------------------------------------------ +// 模块名称：main +// 文件名称：main +// 版本名称：V1.0 +// 文件说明：旋转样品杆主文件 +// 日期时间：2018年8月16日21点38分 +// 文件作者：Jackie Chan +// 修改记录： +// 版本号 日期 作者 说明 +// V1.0 2018.08.16 J.C 正式发布 +// +// 公司名称：多场低温科技有限公司 +// +//------------------------------------------------------------------------------ + +#include "bsp.h" /* 底层硬件驱动 */ +#include "bsp_key.h" +#include "stdint.h" +#include "main.h" + +uint8_t Flag_100ms = 0; +extern DIGITIAL_TUBE_T g_tTube; +extern MOTO_T g_tMoto; +#define IS_ZERO_BUF_VALID() (g_RxBuf[1] == 'z' && \ + g_RxBuf[2] == ',' && g_RxBuf[4] == ',' && \ + (g_RxBuf[3] == '1' || g_RxBuf[3] == '0')) +#define IS_MF_VALID (g_RxBuf[1] == 'M' && g_RxBuf[2] == 'F') +static void Delay_ms(uint16_t us) +{ + uint16_t i; + + /*　 + CPU主频168MHz时，在内部Flash运行, MDK工程不优化。用台式示波器观测波形。 + 循环次数为5时，SCL频率 = 1.78MHz (读耗时: 92ms, 读写正常，但是用示波器探头碰上就读写失败。时序接近临界) + 循环次数为10时，SCL频率 = 1.1MHz (读耗时: 138ms, 读速度: 118724B/s) + 循环次数为30时，SCL频率 = 440KHz， SCL高电平时间1.0us，SCL低电平时间1.2us + + 上拉电阻选择2.2K欧时，SCL上升沿时间约0.5us，如果选4.7K欧，则上升沿约1us + + 实际应用选择400KHz左右的速率即可 + */ + for (i = 0; i < (300 * us); i++) + ; +} +void key1_task(void); +void key2_task(void); +void uart_msg_idle(void); +// #include "bsp_adc.h"- +// #include "delay.h" + +// 初始化ADC +// 这里我们仅以规则通道为例 +// 我们默认将开启通道0~3 +void Adc_Init(void) +{ + ADC_InitTypeDef ADC_InitStructure; + GPIO_InitTypeDef GPIO_InitStructure; + + RCC_APB2PeriphClockCmd(RCC_APB2Periph_GPIOA | RCC_APB2Periph_ADC1, ENABLE); // 使能ADC1通道时钟 + + RCC_ADCCLKConfig(RCC_PCLK2_Div6); // 设置ADC分频因子6 72M/6=12,ADC最大时间不能超过14M + + // PA1 作为模拟通道输入引脚 + GPIO_InitStructure.GPIO_Pin = GPIO_Pin_1 | GPIO_Pin_2; + GPIO_InitStructure.GPIO_Mode = GPIO_Mode_AIN; // 模拟输入引脚 + GPIO_Init(GPIOA, &GPIO_InitStructure); + + ADC_DeInit(ADC1); // 复位ADC1,将外设 ADC1 的全部寄存器重设为缺省值 + + ADC_InitStructure.ADC_Mode = ADC_Mode_Independent; // ADC工作模式:ADC1和ADC2工作在独立模式 + ADC_InitStructure.ADC_ScanConvMode = DISABLE; // 模数转换工作在单通道模式 + ADC_InitStructure.ADC_ContinuousConvMode = DISABLE; // 模数转换工作在单次转换模式 + ADC_InitStructure.ADC_ExternalTrigConv = ADC_ExternalTrigConv_None; // 转换由软件而不是外部触发启动 + ADC_InitStructure.ADC_DataAlign = ADC_DataAlign_Right; // ADC数据右对齐 + ADC_InitStructure.ADC_NbrOfChannel = 1; // 顺序进行规则转换的ADC通道的数目 + ADC_Init(ADC1, &ADC_InitStructure); // 根据ADC_InitStruct中指定的参数初始化外设ADCx的寄存器 + + ADC_Cmd(ADC1, ENABLE); // 使能指定的ADC1 + + ADC_ResetCalibration(ADC1); // 使能复位校准 + + while (ADC_GetResetCalibrationStatus(ADC1)) + ; // 等待复位校准结束 + + ADC_StartCalibration(ADC1); // 开启AD校准 + + while (ADC_GetCalibrationStatus(ADC1)) + ; // 等待校准结束 + + // ADC_SoftwareStartConvCmd(ADC1, ENABLE); //使能指定的ADC1的软件转换启动功能 +} +// 获得ADC值 +// ch:通道值 0~3 ADC_Channel_1 +u16 Get_Adc(u8 ch) +{ + // 设置指定ADC的规则组通道，一个序列，采样时间 + ADC_RegularChannelConfig(ADC1, ch, 1, ADC_SampleTime_239Cycles5); // ADC1,ADC通道,采样时间为239.5周期 + + ADC_SoftwareStartConvCmd(ADC1, ENABLE); // 使能指定的ADC1的软件转换启动功能 + + while (!ADC_GetFlagStatus(ADC1, ADC_FLAG_EOC)) + ; // 等待转换结束 + + return ADC_GetConversionValue(ADC1); // 返回最近一次ADC1规则组的转换结果 +} + +u16 Get_Adc_Average(u8 ch, u8 times) +{ + u32 temp_val = 0; + u8 t; + for (t = 0; t < times; t++) + { + temp_val += Get_Adc(ch); + Delay_ms(5); + } + return temp_val / times; +} + +u16 get_key4_adc(void) +{ + u16 key4_adc = 0; + u16 ad_value; + + ad_value = Get_Adc_Average(ADC_Channel_1, 10); + + key4_adc = ad_value; + if (key4_adc > 3000) + { + key4_adc = 2; // 前进 + } + else if (key4_adc <= 1200) + { + key4_adc = 1; // 后退 + } + else if ((key4_adc > 1200) && (key4_adc <= 3000)) + { + key4_adc = 0; // 后退 + } + return key4_adc; +} +u16 get_key5_adc(void) +{ + u16 key5_adc = 0; + u16 ad_value; + + ad_value = Get_Adc_Average(ADC_Channel_2, 10); + + // electric_quantity_percent = ((ad_value*3.3/4096.0)-1.846)*100/0.52; + key5_adc = (ad_value * 3.3 / 4096.0); + + if (key5_adc >= 3000) + { + key5_adc = 1; // 前进 + } + else if (key5_adc <= 1200) + { + key5_adc = 2; // 后退 + } + else if ((key5_adc > 1200) && (key5_adc < 3000)) + { + key5_adc = 0; // 后退 + } + return key5_adc; +} + +void motor_dir(uint32_t freq, uint8_t _dir, int64_t _stpes) +{ + // [r,1,1500,108288] + + if (g_tTube.state == WORK) + { + if (_dir == 1) + { + _dir = 1; + if (g_tMoto.sv_pulse + 100 < INT64_MAX) + g_tMoto.sv_pulse = g_tMoto.sv_pulse + 100; + } + else if (_dir == 0) + { + _dir = 0; + if (g_tMoto.sv_pulse - 100 > INT64_MIN) + g_tMoto.sv_pulse = g_tMoto.sv_pulse - 100; + } + + if (g_tMoto.pv_pulse < g_tMoto.sv_pulse) + { + + if (g_tMoto.sv_pulse > INT64_MAX) + { + g_tMoto.sv_pulse = INT64_MAX; + } + else if (g_tMoto.sv_pulse <= INT64_MAX) + { + MOTO_Start(1500, 0, 100); + } + } + else if (g_tMoto.pv_pulse > g_tMoto.sv_pulse) + { + if (g_tMoto.sv_pulse < INT64_MIN) + { + g_tMoto.sv_pulse = INT64_MIN; + } + else if (g_tMoto.sv_pulse >= INT64_MIN) + { + MOTO_Start(1500, 1, 100); + } + } + } +} +int main(void) +{ + uint8_t ucKeyCode; + uint32_t freq = 1500; + uint16_t motor_move1 = 0; + uint32_t g_sysclk_src = 0, g_pll_mul = 0; + // uint16_t motor_move2 = 0; + + SCB->VTOR = 0x08008000; + + /* === MCO 测试: PA8 输出 PLLCLK/2，示波器测量 PA8 === */ + { + GPIO_InitTypeDef GPIO_InitStruct; + RCC_APB2PeriphClockCmd(RCC_APB2Periph_GPIOA, ENABLE); + GPIO_InitStruct.GPIO_Pin = GPIO_Pin_8; + GPIO_InitStruct.GPIO_Mode = GPIO_Mode_AF_PP; + GPIO_InitStruct.GPIO_Speed = GPIO_Speed_50MHz; + GPIO_Init(GPIOA, &GPIO_InitStruct); + RCC->CFGR = (RCC->CFGR & ~RCC_CFGR_MCO) | RCC_CFGR_MCO_PLL; + /* MCO 输出 PLL/2：72MHz 系统 = 36MHz, 48MHz 系统 = 24MHz */ + } + + /* 运行时检测实际系统时钟 */ + { + g_sysclk_src = RCC->CFGR & RCC_CFGR_SWS; + if (g_sysclk_src == 0x08) + { + g_pll_mul = (RCC->CFGR & RCC_CFGR_PLLMULL) >> 18; + g_pll_mul = g_pll_mul + 2; + } + } + + bsp_Init(); /* 硬件初始化 */ + + /* 打印调试信息（需在串口初始化后） */ + { + if (g_sysclk_src == 0x00) + printf("SYSCLK = HSI 8MHz\r\n"); + else if (g_sysclk_src == 0x04) + printf("SYSCLK = HSE\r\n"); + else if (g_sysclk_src == 0x08) + { + printf("PLL MUL = %u, PLL = 8MHz * %u = %uMHz\r\n", g_pll_mul, g_pll_mul, 8 * g_pll_mul); + } + printf("SystemCoreClock var = %lu\r\n", SystemCoreClock); + printf("RCC->CFGR = 0x%08lX, PPRE1=%lu\r\n", RCC->CFGR, (RCC->CFGR >> 8) & 0x7); + printf("TIM6 PSC = %u, ARR = %u\r\n", TIM6->PSC, TIM6->ARR); + } + + Adc_Init(); // ADC初始化 + BEEP_Start(freq, 20, 1, 1); + + g_tTube.state = WORK; + MOTO_Stop(); + + /* 主程序大循环 */ + while (1) + { + bsp_Idle(); /* CPU空闲时执行的函数，在 bsp.c */ + uart_msg_idle(); + if (Flag_100ms == 1) + { + Flag_100ms = 0; + motor_move1 = get_key4_adc(); + // motor_move2 = get_key5_adc(); + if (motor_move1 == 1) // key4 + { + motor_move1 = 0; + // 前进 + motor_dir(1500, 0, 3000); + } + else if (motor_move1 == 2) + { + motor_move1 = 0; + // 后退 + motor_dir(1500, 1, 3000); + } + } + /* 处理按键事件 */ + ucKeyCode = bsp_GetKey(); + + if (ucKeyCode > 0) + { + /* 有键按下 */ + switch (ucKeyCode) // key6 + { + case KEY_DOWN_K6: // key6 短按 + { + MOTO_ZorePos(); + break; + } + + case KEY_DOWN_K1: // Key1 短按 + { + BEEP_KeyTone(); // 按键提示音 + bsp_ToogleDispMode(); + break; + } + + default: + break; + } + } + } +} + +void send_sv_2_uart(void) +{ + float angle = g_tTube.pulse * 360.0f / STEP_PER_LAP; // 22 * 16 * 24 + printf("[w,%.2f]\r\n", angle); +} + +void print_sys_info(void) +{ + printf("\r\n"); + printf("----------------------------->\r\n"); + printf("-> 设备名称：无限旋转控制器\r\n"); + printf("-> software verson: V1.0\r\n"); + printf("-> compile time: %s\r\n", __TIME__); + printf("-> compile date: %s\r\n", __DATE__); + printf("-> [多场低温科技有限公司]\r\n"); + printf("------------------------------\r\n"); + printf("->可用命令：\r\n"); + printf("1. [s] // 停止电机转动\r\n"); + printf("2. [?] // 读取当前位置角度\r\n"); + printf("3. [z] // 设置当前位置为零点\r\n"); + printf("4. [MF] // 打印系统信息\r\n"); + printf("5. [r:10:360] // 转动命令，10为转动角速度，360为目标角度\r\n"); + printf("6. [rr:10:20] // 转动命令，10为转动角速度，20为相对转动角度\r\n"); + printf("<-----------------------------\r\n"); +} + +void uart_msg_idle(void) +{ + uint8_t n = 0; + float freq = 0; + float pulse = 0; + float angle = 0; + + if (g_ucRxRcvNewFlag) + { + g_ucRxRcvNewFlag = 0; + + n = strlen((char *)g_RxBuf); + if (n == 3) + { + switch (g_RxBuf[1]) + { + case '?': + send_sv_2_uart(); + break; + case 's': + MOTO_Stop(); + break; + case 'z': + MOTO_ZorePos(); + break; + default: + break; + } + } + else if (n == 4) + { + if (IS_MF_VALID) + { + print_sys_info(); + } + } + else if (g_RxBuf[1] == 'r') + { + // [r,10,100] // 10°/s 转到100° + if (sscanf((char *)g_RxBuf, "[r:%f:%f]", &freq, &angle) == 2) + { + if (freq < 0.01f) + freq = 0.01f; + else if (freq > MAX_SPEED) + freq = MAX_SPEED; + pulse = (angle / 360) * STEP_PER_LAP; // angle所有需要的脉冲 + freq = freq * (STEP_PER_LAP / 360.0f); // 角速度所需要的脉冲频率 + g_tMoto.sv_pulse = (int64_t)pulse; + + printf("[r] freq=%lu, angle=%f, pulse=%ld, sv_pulse=%lld\r\n", (unsigned long)freq, angle, (long)pulse, g_tMoto.sv_pulse); + printf("TIM6 before start: PSC=%u, ARR=%u\r\n", TIM6->PSC, TIM6->ARR); + + if (g_tMoto.pv_pulse < g_tMoto.sv_pulse) + { + MOTO_Start(freq, 0, 123); + } + else if (g_tMoto.pv_pulse > g_tMoto.sv_pulse) + { + MOTO_Start(freq, 1, 123); + } + else + { + BEEP_Start(1500, 5, 5, 3); + } + printf("TIM6 after start: PSC=%u, ARR=%u\r\n", TIM6->PSC, TIM6->ARR); + } + else if (sscanf((char *)g_RxBuf, "[rr:%f:%f]", &freq, &angle) == 2) + { + if (pulse < 0.01f) + pulse = 0.01f; + else if (pulse > MAX_SPEED) + pulse = MAX_SPEED; + pulse = (angle / 360) * STEP_PER_LAP; // angle所有需要的脉冲 + freq = freq * (STEP_PER_LAP / 360.0f); // 角速度所需要的脉冲频率 + g_tMoto.sv_pulse += (int64_t)pulse; + + printf("[rr] freq=%lu, angle=%f, pulse=%ld, sv_pulse=%lld\r\n", (unsigned long)freq, angle, (long)pulse, g_tMoto.sv_pulse); + printf("TIM6 before start: PSC=%u, ARR=%u\r\n", TIM6->PSC, TIM6->ARR); + + if (g_tMoto.pv_pulse < g_tMoto.sv_pulse) + { + MOTO_Start(freq, 0, 123); + } + else if (g_tMoto.pv_pulse > g_tMoto.sv_pulse) + { + MOTO_Start(freq, 1, 123); + } + else + { + BEEP_Start(1500, 5, 5, 3); + } + printf("TIM6 after start: PSC=%u, ARR=%u\r\n", TIM6->PSC, TIM6->ARR); + } + else + { + BEEP_Start(1500, 5, 5, 3); + } + } + else + { + BEEP_Start(1500, 5, 5, 3); + } + } +} + +//-------------------------------- End of file --------------------------------- diff --git a/User/bsp/bsp.c b/User/bsp/bsp.c new file mode 100644 index 0000000..c804bce --- /dev/null +++ b/User/bsp/bsp.c @@ -0,0 +1,117 @@ +/* +********************************************************************************************************* +* +* 模块名称 : BSP模块(For STM32F103) +* 文件名称 : bsp.c +* 版 本 : V1.0 +* 说 明 : 这是硬件底层驱动程序模块的主文件。主要提供 bsp_Init()函数供主程序调用。主程序的每个c文件可以在开 +* 头 添加 #include "bsp.h" 来包含所有的外设驱动模块。 +* +* 修改记录 : +* 版本号 日期 作者 说明 +* V1.0 2015-09-01 armfly 正式发布 +* +* Copyright (C), 2015-2020, 安富莱电子 www.armfly.com +* +********************************************************************************************************* +*/ + +#include "bsp.h" + +uint32_t RxCount = 0; +uint32_t TxCount = 0; + +/* +********************************************************************************************************* +* 函 数 名: bsp_Init +* 功能说明: 初始化硬件设备。只需要调用一次。该函数配置CPU寄存器和外设的寄存器并初始化一些全局变量。 +* 全局变量。 +* 形 参：无 +* 返 回 值: 无 +********************************************************************************************************* +*/ +void bsp_Init(void) +{ + /* + 由于ST固件库的启动文件已经执行了CPU系统时钟的初始化，所以不必再次重复配置系统时钟。 + 启动文件配置了CPU主时钟频率、内部Flash访问速度和可选的外部SRAM FSMC初始化。 + + 系统时钟缺省配置为72MHz，如果需要更改，可以修改 system_stm32f103.c 文件 + */ + + /* 优先级分组设置为4 */ + NVIC_PriorityGroupConfig(NVIC_PriorityGroup_4); + + bsp_InitKey(); /* 初始化按键 */ + + bsp_InitTimer(); /* 初始化系统滴答定时器 (此函数会开中断) */ + + /* 初始化串口驱动 */ + USART_Config(); + /* 配置使用DMA模式 */ + USARTx_DMA_Config(); + USART_DMACmd(DEBUG_USARTx, USART_DMAReq_Rx, ENABLE); + + BEEP_InitHard(); /* 配置蜂鸣器GPIO */ + + bsp_InitI2C(); /* 配置I2C总线 */ + bsp_InitDigitalTube(); // 初始化数码管控制端口 + + bsp_Init_Drv8880_Hard(); + bsp_InitStepMoto(); +} + +/* +********************************************************************************************************* +* 函 数 名: bsp_RunPer10ms +* 功能说明: 该函数每隔10ms被Systick中断调用1次。详见 bsp_timer.c的定时中断服务程序。一些处理时间要求不严格的 +* 任务可以放在此函数。比如：按键扫描、蜂鸣器鸣叫控制等。 +* 形 参：无 +* 返 回 值: 无 +********************************************************************************************************* +*/ +void bsp_RunPer10ms(void) +{ + bsp_KeyScan(); /* 每10ms扫描按键一次 */ + + BEEP_Pro(); /* 蜂鸣器定时处理 */ + + // bsp_FpgaPowerMainLoop(30); // 给FPAGA延迟供电，延迟时间位30*10ms +} + +/* +********************************************************************************************************* +* 函 数 名: bsp_RunPer1ms +* 功能说明: 该函数每隔1ms被Systick中断调用1次。详见 bsp_timer.c的定时中断服务程序。一些需要周期性处理的事务 +* 可以放在此函数。比如：触摸坐标扫描。 +* 形 参: 无 +* 返 回 值: 无 +********************************************************************************************************* +*/ +void bsp_RunPer1ms(void) +{ + bsp_DigitalTubeMainLoop(); +} + +/* +********************************************************************************************************* +* 函 数 名: bsp_Idle +* 功能说明: 空闲时执行的函数。一般主程序在for和while循环程序体中需要插入 CPU_IDLE() 宏来调用本函数。 +* 本函数缺省为空操作。用户可以添加喂狗、设置CPU进入休眠模式的功能。 +* 形 参：无 +* 返 回 值: 无 +********************************************************************************************************* +*/ +void bsp_Idle(void) +{ + /* --- 喂狗 */ + + /* --- 让CPU进入休眠，由Systick定时中断唤醒或者其他中断唤醒 */ + + /* 例如 emWin 图形库，可以插入图形库需要的轮询函数 */ + // GUI_Exec(); + + /* 例如 uIP 协议，可以插入uip轮询函数 */ +} + +/***************************** 安富莱电子 www.armfly.com (END OF FILE) *********************************/ diff --git a/User/bsp/bsp.h b/User/bsp/bsp.h new file mode 100644 index 0000000..b914bda --- /dev/null +++ b/User/bsp/bsp.h @@ -0,0 +1,83 @@ +/* +********************************************************************************************************* +* +* ģ : BSPģ +* ļ : bsp.h +* ˵ : ǵײģеhļĻļ Ӧóֻ #include bsp.h ɣ +* Ҫ#include ÿģ h ļ +* +* Copyright (C), 2013-2014, www.armfly.com +* +********************************************************************************************************* +*/ + +#ifndef _BSP_H_ +#define _BSP_H_ + +#define STM32_V4 +//#define STM32_X2 + +/* Ƿ˿ͺ */ +#if !defined (STM32_V4) && !defined (STM32_X2) + #error "Please define the board model : STM32_X2 or STM32_V4" +#endif + +/* BSP 汾 */ +#define __STM32F1_BSP_VERSION "1.1" + +/* CPUʱִеĺ */ +//#define CPU_IDLE() bsp_Idle() + +/* ȫжϵĺ */ +#define ENABLE_INT() __set_PRIMASK(0) /* ʹȫж */ +#define DISABLE_INT() __set_PRIMASK(1) /* ֹȫж */ + +/* ڵԽ׶Ŵ */ +#define BSP_Printf printf +//#define BSP_Printf(...) + +#include "stm32f10x.h" +#include +#include +#include + +#ifndef TRUE + #define TRUE 1 +#endif + +#ifndef FALSE + #define FALSE 0 +#endif + +//#include "bsp_led.h" +#include "bsp_timer.h" +#include "bsp_key.h" + +#include "bsp_usart_dma.h" +#include "bsp_tim_pwm.h" +#include "bsp_beep.h" + +#include "bsp_digital_tube.h" +#include "bsp_i2c_gpio.h" +#include "bsp_eeprom_24xx.h" +#include "bsp_drv8880.h" +#include "bsp_step_moto.h" +//#include "bsp_adc.h" +//#include "sys.h" /* ײӲ */ +//uint8_t Flag_100ms; +extern uint8_t Flag_100ms; +extern uint32_t RxCount ; +extern uint32_t TxCount ; + +/* ṩCļõĺ */ +void bsp_Init(void); +void bsp_Idle(void); + + +#define MAX_SPEED 400 +#define STEP_PER_LAP 8461 + + +#endif + +/***************************** www.armfly.com (END OF FILE) *********************************/ diff --git a/User/bsp/inc/bsp_beep.h b/User/bsp/inc/bsp_beep.h new file mode 100644 index 0000000..61a60b1 --- /dev/null +++ b/User/bsp/inc/bsp_beep.h @@ -0,0 +1,39 @@ +/* +********************************************************************************************************* +* +* ģ : ģ +* ļ : bsp_beep.h +* : V1.0 +* ˵ : ͷļ +* +* Copyright (C), 2012-2013, www.armfly.com +* +********************************************************************************************************* +*/ + +#ifndef __BSP_BEEP_H +#define __BSP_BEEP_H +#include + +typedef struct _BEEP_T +{ + uint8_t ucEnalbe; + uint8_t ucState; + uint16_t usBeepTime; + uint16_t usStopTime; + uint16_t usCycle; + uint16_t usCount; + uint16_t usCycleCount; + uint32_t uiFreq; +}BEEP_T; + +/* ⲿõĺ */ +void BEEP_InitHard(void); +void BEEP_Start(uint32_t _uiFreq, uint16_t _usBeepTime, uint16_t _usStopTime, uint16_t _usCycle); +void BEEP_Stop(void); +void BEEP_KeyTone(void); +void BEEP_Pro(void); + +#endif + +/***************************** www.armfly.com (END OF FILE) *********************************/ diff --git a/User/bsp/inc/bsp_channel_realy.h b/User/bsp/inc/bsp_channel_realy.h new file mode 100644 index 0000000..313a9bf --- /dev/null +++ b/User/bsp/inc/bsp_channel_realy.h @@ -0,0 +1,29 @@ +//------------------------------------------------------------------------------ +// ģƣ̵ͨѡģ +// ļƣbsp_channel_relay +// 汾ƣV1.0 +// ļ˵ͷļ +// ʱ䣺2018881952 +// ļߣJackie Chan +// ޸ļ¼ +// 汾 ˵ +// V1.0 2018.08.08 J.C ʽ +// +// ˾ƣೡ¿Ƽ޹˾ +// +//------------------------------------------------------------------------------ + +#ifndef __BSP_CHANNEL_RELAY_H__ +#define __BSP_CHANNEL_RELAY_H__ + +#include + +// õĺ +void bsp_InitChannelRelay(void); +void bsp_RealyAllOff(void); +void bsp_RelayOn(uint8_t _ch); + +#endif + +//-------------------------------- End of file --------------------------------- + diff --git a/User/bsp/inc/bsp_digital_tube.h b/User/bsp/inc/bsp_digital_tube.h new file mode 100644 index 0000000..1fff563 --- /dev/null +++ b/User/bsp/inc/bsp_digital_tube.h @@ -0,0 +1,76 @@ +//------------------------------------------------------------------------------ +// 模块名称：数码管驱动模块 +// 文件名称：bsp_digital_tube +// 版本名称：V1.0 +// 文件说明：头文件 +// 日期时间：2018年8月15日20点02分 +// 文件作者：Jackie Chan +// 修改记录： +// 版本号 日期 作者 说明 +// V1.0 2018.08.15 J.C 正式发布 +// +// 公司名称：多场低温科技有限公司 +// +//------------------------------------------------------------------------------ + +#ifndef __BSP_DIGITAL_TUBE__H__ +#define __BSP_DIGITAL_TUBE__H__ + +#include + +typedef enum +{ + NO_0 = 0, + NO_1, + NO_2, + NO_3, + NO_4, + NO_5, + NO_6, + NO_7, + NO_8, + NO_9, + NO__, + NO_NULL, +}SEG_NUM_E; + +typedef enum +{ + IDLE, // 空闲模式 + WORK, // 工作模式 + SEARCH, // 搜索模式 +}STATE_E; + +typedef enum +{ + MODE_PULSE, // 脉冲显示模式 + MODE_ANGLE, // 角度显示模式 +}MODE_E; + +typedef enum +{ + DIR_CW, // 样品杆从上往下看，顺时针旋转（+） + DIR_CCW, // 样品杆从上往下看，逆时针旋转（-） +}DIR_E; + +typedef struct +{ + char buf[9]; // 8个数码管的刷新缓冲区 + uint8_t disp_mode; // 显示模式，角度显示和脉冲数量显示 + uint8_t cnt; // 数码管轮询显示计数 + uint8_t state; // 工作状态，空闲模式、工作模式 + uint8_t dir; // 电机旋转方向，样品杆从上往下看，顺时针（+）还是逆时针（-） + int32_t pulse; // 电机转动过的脉冲数量，+表示顺时针累积脉冲，-表示逆时针累积 + int32_t tim_pulse_cnt; // 定时器计数的脉冲数量，每1ms更新到上面pluse中 + int32_t angle; // 电机转动过的角度 +}DIGITIAL_TUBE_T; + +void bsp_InitDigitalTube(void); +void bsp_DigitalTubeMainLoop(void); +void bsp_TubeTest(uint8_t _com, uint8_t _seg); +void bsp_UpdateDisplayBuf(void); +void bsp_ToogleDispMode(void); +void bsp_ToogleStateMode(void); + +#endif +//-------------------------------- End of file --------------------------------- diff --git a/User/bsp/inc/bsp_drv8880.h b/User/bsp/inc/bsp_drv8880.h new file mode 100644 index 0000000..cc313da --- /dev/null +++ b/User/bsp/inc/bsp_drv8880.h @@ -0,0 +1,45 @@ +//------------------------------------------------------------------------------ +// 模块名称：步进电机芯片DRV8880驱动模块 +// 文件名称：bsp_drv8880 +// 版本名称：V1.0 +// 文件说明：头文件 +// 日期时间：2018年8月17日16点23分 +// 文件作者：Jackie Chan +// 修改记录： +// 版本号 日期 作者 说明 +// V1.0 2018.08.17 J.C 正式发布 +// +// 公司名称：多场低温科技有限公司 +// +//------------------------------------------------------------------------------ + +#ifndef __BSP_DRV8880_H__ +#define __BSP_DRV8880_H__ + +#include "bsp.h" + +// typedef enum +// { + // DISABLE = 0, + // ENABLE = !DISABLE +// }BoolState; + +// 细分入口参数 +typedef enum +{ + STEP_FULL = 0, // Full step with 71% current + STEP_1_2_NC, // Non-circular 1/2 step + STEP_1_2, // 1/2 step + STEP_1_4, // 1/4 step + STEP_1_8, // 1/8 step + STEP_1_16 // 1/16 step +}MICRO_STEPPING_E; + +void bsp_Init_Drv8880_Hard(void); +void bsp_drv8880_enable_config(FunctionalState en); +void bsp_drv8880_microstep_config(MICRO_STEPPING_E step); +void bsp_drv8880_config_dir(DIR_E dir); + +#endif + +//-------------------------------- End of file --------------------------------- diff --git a/User/bsp/inc/bsp_eeprom_24xx.h b/User/bsp/inc/bsp_eeprom_24xx.h new file mode 100644 index 0000000..bc9707e --- /dev/null +++ b/User/bsp/inc/bsp_eeprom_24xx.h @@ -0,0 +1,56 @@ +/* +********************************************************************************************************* +* +* ģ : EEPROM 24xx02ģ +* ļ : bsp_eeprom_24xx.h +* : V1.0 +* ˵ : ͷļ +* +* ޸ļ¼ : +* 汾 ˵ +* v1.0 2012-10-12 armfly ST̼汾 V2.1.0 +* +* Copyright (C), 2012-2013, www.armfly.com +* +********************************************************************************************************* +*/ + +#ifndef _BSP_EEPROM_24XX_H +#define _BSP_EEPROM_24XX_H +#include + +//#define AT24C02 +#define AT24C128 +//#define AT24C256 + +#ifdef AT24C02 + #define EE_MODEL_NAME "AT24C02" + #define EE_DEV_ADDR 0xA0 /* 豸ַ */ + #define EE_PAGE_SIZE 8 /* ҳС(ֽ) */ + #define EE_SIZE 256 /* (ֽ) */ + #define EE_ADDR_BYTES 1 /* ַֽڸ */ +#endif + +#ifdef AT24C128 + #define EE_MODEL_NAME "AT24C128" + #define EE_DEV_ADDR 0xA0 /* 豸ַ */ + #define EE_PAGE_SIZE 64 /* ҳС(ֽ) */ + #define EE_SIZE (16*1024) /* (ֽ) */ + #define EE_ADDR_BYTES 2 /* ַֽڸ */ +#endif + +#ifdef AT24C256 + #define EE_MODEL_NAME "AT24C256" + #define EE_DEV_ADDR 0xA0 /* 豸ַ */ + #define EE_PAGE_SIZE 64 /* ҳС(ֽ) */ + #define EE_SIZE (32*1024) /* (ֽ) */ + #define EE_ADDR_BYTES 2 /* ַֽڸ */ +#endif + +uint8_t ee_CheckOk(void); +uint8_t ee_ReadBytes(uint8_t *_pReadBuf, uint16_t _usAddress, uint16_t _usSize); +uint8_t ee_WriteBytes(uint8_t *_pWriteBuf, uint16_t _usAddress, uint16_t _usSize); + +#endif + +/***************************** www.armfly.com (END OF FILE) *********************************/ diff --git a/User/bsp/inc/bsp_fpga_power.h b/User/bsp/inc/bsp_fpga_power.h new file mode 100644 index 0000000..e5a75f1 --- /dev/null +++ b/User/bsp/inc/bsp_fpga_power.h @@ -0,0 +1,29 @@ +//------------------------------------------------------------------------------ +// ģƣFPGAģ +// ļƣbsp_fpag_power.h +// 汾ƣV1.0 +// ļ˵ͷļ +// ʱ䣺2018881752 +// ļߣJackie Chan +// ޸ļ¼ +// 汾 ˵ +// V1.0 2018.08.08 J.C ʽ +// +// ˾ƣೡ¿Ƽ޹˾ +// +//------------------------------------------------------------------------------ + +#ifndef __BSP_FPGA_POWER_H__ +#define __BSP_FPGA_POWER_H__ + +#include "bsp.h" + +// õĺ +void bsp_InitFpgaPower(void); +void bsp_FpgaPowerCmd(FunctionalState _NewState); +void bsp_FpgaPowerMainLoop(uint16_t _delay_n_10ms); + +#endif + +//-------------------------------- End of file --------------------------------- + diff --git a/User/bsp/inc/bsp_i2c_gpio.h b/User/bsp/inc/bsp_i2c_gpio.h new file mode 100644 index 0000000..d01cc07 --- /dev/null +++ b/User/bsp/inc/bsp_i2c_gpio.h @@ -0,0 +1,30 @@ +/* +********************************************************************************************************* +* +* ģ : I2Cģ +* ļ : bsp_i2c_gpio.h +* : V1.0 +* ˵ : ͷļ +* +* Copyright (C), 2012-2013, www.armfly.com +* +********************************************************************************************************* +*/ + +#ifndef _BSP_I2C_GPIO_H +#define _BSP_I2C_GPIO_H + +#define I2C_WR 0 /* дbit */ +#define I2C_RD 1 /* bit */ + +void bsp_InitI2C(void); +void i2c_Start(void); +void i2c_Stop(void); +void i2c_SendByte(uint8_t _ucByte); +uint8_t i2c_ReadByte(void); +uint8_t i2c_WaitAck(void); +void i2c_Ack(void); +void i2c_NAck(void); +uint8_t i2c_CheckDevice(uint8_t _Address); + +#endif diff --git a/User/bsp/inc/bsp_key.h b/User/bsp/inc/bsp_key.h new file mode 100644 index 0000000..39a06a0 --- /dev/null +++ b/User/bsp/inc/bsp_key.h @@ -0,0 +1,177 @@ +/* +********************************************************************************************************* +* +* ģ : ģ +* ļ : bsp_key.h +* : V1.0 +* ˵ : ͷļ +* +* Copyright (C), 2013-2014, www.armfly.com +* +********************************************************************************************************* +*/ + +#ifndef __BSP_KEY_H +#define __BSP_KEY_H + +#include + +#define KEY_COUNT 3 + +/* ӦóĹ */ +#define KEY_DOWN_K6 KEY_1_DOWN +#define KEY_UP_K6 KEY_1_UP +#define KEY_LONG_K6 KEY_1_LONG + +#define KEY_DOWN_K1 KEY_2_DOWN +#define KEY_UP_K1 KEY_2_UP +#define KEY_LONG_K1 KEY_2_LONG + +#define KEY_DOWN_K2 KEY_3_DOWN +#define KEY_UP_K2 KEY_3_UP +#define KEY_LONG_K2 KEY_3_LONG + +#define KEY_DOWN_K4 KEY_4_DOWN /* */ +#define KEY_UP_K4 KEY_4_UP +#define KEY_LONG_K4 KEY_4_LONG + +#define KEY_DOWN_K5 KEY_5_DOWN /* */ +#define KEY_UP_K5 KEY_5_UP +#define KEY_LONG_K5 KEY_5_LONG + +#define KEY_DOWN_K3 KEY_6_DOWN /* */ +#define KEY_UP_K3 KEY_6_UP +#define KEY_LONG_K3 KEY_6_LONG + +#define KEY_DOWN_K7 KEY_7_DOWN /* */ +#define KEY_UP_K7 KEY_7_UP +#define KEY_LONG_K7 KEY_7_LONG + +#define KEY_DOWN_K8 KEY_8_DOWN /* ok */ +#define KEY_UP_K8 KEY_8_UP +#define KEY_LONG_K8 KEY_8_LONG + +#define SYS_DOWN_K1K2 KEY_9_DOWN /* K1 K2 ϼ */ +#define SYS_UP_K1K2 KEY_9_UP +#define SYS_LONG_K1K2 KEY_9_LONG + +#define SYS_DOWN_K2K3 KEY_10_DOWN /* K2 K3 ϼ */ +#define SYS_UP_K2K3 KEY_10_UP +#define SYS_LONG_K2K3 KEY_10_LONG + +/* ID, Ҫbsp_KeyState()ڲ */ +typedef enum +{ + KID_K1 = 0, + KID_K2, + KID_K3, + KID_K4, + KID_K5, + KID_K6, + KID_K7, + KID_K8 +}KEY_ID_E; + +/* + ˲ʱ50ms, λ10ms + ֻ⵽50ms״̬ΪЧͰ¼ + ʹ·Ӳ˲˲ҲԱ֤ɿؼ⵽¼ +*/ +#define KEY_FILTER_TIME 1 +#define KEY_LONG_TIME 100 /* λ10ms 1룬Ϊ¼ */ + +/* + ÿӦ1ȫֵĽṹ +*/ +typedef struct +{ + /* һָ룬ָжϰַµĺ */ + uint8_t (*IsKeyDownFunc)(void); /* µжϺ,1ʾ */ + + uint8_t Count; /* ˲ */ + uint16_t LongCount; /* */ + uint16_t LongTime; /* ³ʱ, 0ʾⳤ */ + uint8_t State; /* ǰ״̬»ǵ */ + uint8_t RepeatSpeed; /* */ + uint8_t RepeatCount; /* */ +}KEY_T; + +/* + ֵ, 밴´ʱÿİ¡ͳ¼ + + Ƽʹenum, #defineԭ + (1) ֵ,˳ʹ뿴 + (2) ɰDZֵظ +*/ +typedef enum +{ + KEY_NONE = 0, /* 0 ʾ¼ */ + + KEY_1_DOWN, /* 1 */ + KEY_1_UP, /* 1 */ + KEY_1_LONG, /* 1 */ //3 + + KEY_2_DOWN, /* 2 */ + KEY_2_UP, /* 2 */ + KEY_2_LONG, /* 2 *///6 + + KEY_3_DOWN, /* 3 */ + KEY_3_UP, /* 3 */ + KEY_3_LONG, /* 3 */ + + KEY_4_DOWN, /* 4 */ + KEY_4_UP, /* 4 */ + KEY_4_LONG, /* 4 */ + + KEY_5_DOWN, /* 5 */ + KEY_5_UP, /* 5 */ + KEY_5_LONG, /* 5 */ + + KEY_6_DOWN, /* 6 */ + KEY_6_UP, /* 6 */ + KEY_6_LONG, /* 6 */ + + KEY_7_DOWN, /* 7 */ + KEY_7_UP, /* 7 */ + KEY_7_LONG, /* 7 */ + + KEY_8_DOWN, /* 8 */ + KEY_8_UP, /* 8 */ + KEY_8_LONG, /* 8 */ + + /* ϼ */ + KEY_9_DOWN, /* 9 */ + KEY_9_UP, /* 9 */ + KEY_9_LONG, /* 9 */ + + KEY_10_DOWN, /* 10 */ + KEY_10_UP, /* 10 */ + KEY_10_LONG, /* 10 */ +}KEY_ENUM; + +/* FIFOõ */ +#define KEY_FIFO_SIZE 10 +typedef struct +{ + uint8_t Buf[KEY_FIFO_SIZE]; /* ֵ */ + uint8_t Read; /* ָ1 */ + uint8_t Write; /* дָ */ + uint8_t Read2; /* ָ2 */ +}KEY_FIFO_T; + +/* ⲿõĺ */ +void bsp_InitKey(void); +void bsp_KeyScan(void); +void bsp_PutKey(uint8_t _KeyCode); +uint8_t bsp_GetKey(void); +uint8_t bsp_GetKey2(void); +uint8_t bsp_GetKeyState(KEY_ID_E _ucKeyID); +void bsp_SetKeyParam(uint8_t _ucKeyID, uint16_t _LongTime, uint8_t _RepeatSpeed); +void bsp_ClearKey(void); + +uint8_t IsKeyDown2(void); +uint8_t IsKeyDown3(void); + +#endif + +/***************************** www.armfly.com (END OF FILE) *********************************/ diff --git a/User/bsp/inc/bsp_led.h b/User/bsp/inc/bsp_led.h new file mode 100644 index 0000000..f66d2c3 --- /dev/null +++ b/User/bsp/inc/bsp_led.h @@ -0,0 +1,31 @@ +/* +********************************************************************************************************* +* +* ģ : LEDָʾģ +* ļ : bsp_led.h +* : V1.0 +* ˵ : ͷļ +* +* Copyright (C), 2013-2014, www.armfly.com +* +********************************************************************************************************* +*/ + +#ifndef __BSP_LED_H +#define __BSP_LED_H + +#include + +/* ⲿõĺ */ +void bsp_InitLed(void); +void bsp_LedOn(uint8_t _no); +void bsp_LedOff(uint8_t _no); +void bsp_LedToggle(uint8_t _no); +uint8_t bsp_IsLedOn(uint8_t _no); +void bsp_LedAllOff(void); +void bsp_ChannelSelect(uint8_t _ch); +void bsp_ResSelect(uint8_t _res); + +#endif + +/***************************** www.armfly.com (END OF FILE) *********************************/ diff --git a/User/bsp/inc/bsp_res.h b/User/bsp/inc/bsp_res.h new file mode 100644 index 0000000..285788d --- /dev/null +++ b/User/bsp/inc/bsp_res.h @@ -0,0 +1,41 @@ +//------------------------------------------------------------------------------ +// ģƣѹλƿģ +// ļƣbsp_res.h +// 汾ƣV1.0 +// ļ˵ͷļ +// ʱ䣺2018881514 +// ļߣJackie Chan +// ޸ļ¼ +// 汾 ˵ +// V1.0 2018.08.08 J.C ʽ +// +// ˾ƣೡ¿Ƽ޹˾ +// +//------------------------------------------------------------------------------ + +#ifndef __BSP_RES_H__ +#define __BSP_RES_H__ + +#include + +// ѡҪbsp_KeyState()ڲ +typedef enum +{ + RES_0 = 7, + RES_10, + RES_61, + RES_100, + RES_110, + RES_151, + RES_202, + RES_212 +}RES_E; + +// õĺ +void bsp_InitRes(void); +void bsp_SelectRes(uint8_t _res); + + +#endif + +//-------------------------------- End of file --------------------------------- diff --git a/User/bsp/inc/bsp_step_moto.h b/User/bsp/inc/bsp_step_moto.h new file mode 100644 index 0000000..56a449e --- /dev/null +++ b/User/bsp/inc/bsp_step_moto.h @@ -0,0 +1,50 @@ +//------------------------------------------------------------------------------ +// ģƣģ +// ļƣbsp_step_moto +// 汾ƣV1.0 +// ļ˵ͷļ +// ʱ䣺20188232037 +// ļߣJackie Chan +// ޸ļ¼ +// 汾 ˵ +// V1.0 2018.08.23 J.C ʽ +// +// ˾ƣೡ¿Ƽ޹˾ +// +//------------------------------------------------------------------------------ + +#ifndef _BSP_STEMP_MOTO_H +#define _BSP_STEMP_MOTO_H + +#include + +typedef struct +{ + uint8_t Dir; /* 0 ʾת 1 ʾת */ + uint32_t StepFreq; /* Ƶ */ + uint32_t StepCount; /* ʣಽ */ + uint32_t AllStep; /* һתҪߵ */ + uint32_t CurrentStep; /* Ѿ߹IJ */ + uint32_t DispStep; /* ʾ߹IJʱ򲻼 */ + uint8_t Running; /* 1ʾת 0 ʾͣ */ + uint8_t Pos; /* Ȧͨ0-7 */ + int64_t pv_pulse; // ǰֵ + int64_t sv_pulse; // Զ˵趨ֵ + int64_t prev_pv_pulse;// һֵڼ +} MOTO_T; + +extern MOTO_T g_tMoto; + +void bsp_InitStepMoto(void); +void MOTO_Start(uint32_t _speed, uint8_t _dir, int32_t _stpes); +void MOTO_ZorePos(void); +void MOTO_Stop(void); +void MOTO_Pause(void); +void MOTO_ShangeSpeed(uint32_t _speed); +uint32_t MOTO_RoudToStep(void); + +extern MOTO_T g_tMoto; + +#endif + +/***************************** www.armfly.com (END OF FILE) *********************************/ diff --git a/User/bsp/inc/bsp_tim_pwm.h b/User/bsp/inc/bsp_tim_pwm.h new file mode 100644 index 0000000..27cd1bc --- /dev/null +++ b/User/bsp/inc/bsp_tim_pwm.h @@ -0,0 +1,29 @@ +/* +********************************************************************************************************* +* +* ģ : STM32F4ڲTIMPWMźţ˳ʵ +* ļ : bsp_tim_pwm.h +* : V1.0 +* ˵ : ͷļ +* +* Copyright (C), 2012-2013, www.armfly.com +* +********************************************************************************************************* +*/ + +#ifndef __BSP_TIM_PWM_H +#define __BSP_TIM_PWM_H + +#include + +void bsp_SetTIMOutPWM(GPIO_TypeDef* GPIOx, uint16_t GPIO_Pin, TIM_TypeDef* TIMx, uint8_t _ucChannel, + uint32_t _ulFreq, uint32_t _ulDutyCycle); + +void bsp_SetTIMOutPWM_N(GPIO_TypeDef* GPIOx, uint16_t GPIO_Pin, TIM_TypeDef* TIMx, uint8_t _ucChannel, + uint32_t _ulFreq, uint32_t _ulDutyCycle); + +void bsp_SetTIMforInt(TIM_TypeDef* TIMx, uint32_t _ulFreq, uint8_t _PreemptionPriority, uint8_t _SubPriority); + +#endif + +/***************************** www.armfly.com (END OF FILE) *********************************/ diff --git a/User/bsp/inc/bsp_timer.h b/User/bsp/inc/bsp_timer.h new file mode 100644 index 0000000..5fded12 --- /dev/null +++ b/User/bsp/inc/bsp_timer.h @@ -0,0 +1,55 @@ +/* +********************************************************************************************************* +* +* ģ : ʱģ +* ļ : bsp_timer.h +* : V1.3 +* ˵ : ͷļ +* +* Copyright (C), 2015-2016, www.armfly.com +* +********************************************************************************************************* +*/ + +#ifndef __BSP_TIMER_H +#define __BSP_TIMER_H + +/* + ڴ˶ɸʱȫֱ + ע⣬__IO volatileΪжϺͬʱʣпɱŻ +*/ +#define TMR_COUNT 4 /* ʱĸ ʱIDΧ 0 - 3) */ + +/* ʱṹ壬Ա volatile, CŻʱ */ +typedef enum +{ + TMR_ONCE_MODE = 0, /* һιģʽ */ + TMR_AUTO_MODE = 1 /* Զʱģʽ */ +}TMR_MODE_E; + +/* ʱṹ壬Ա volatile, CŻʱ */ +typedef struct +{ + volatile uint8_t Mode; /* ģʽ1 */ + volatile uint8_t Flag; /* ʱ־ */ + volatile uint32_t Count; /* */ + volatile uint32_t PreLoad; /* Ԥװֵ */ +}SOFT_TMR; + +/* ṩCļõĺ */ +void bsp_InitTimer(void); +void bsp_DelayMS(uint32_t n); +void bsp_DelayUS(uint32_t n); +void bsp_StartTimer(uint8_t _id, uint32_t _period); +void bsp_StartAutoTimer(uint8_t _id, uint32_t _period); +void bsp_StopTimer(uint8_t _id); +uint8_t bsp_CheckTimer(uint8_t _id); +int32_t bsp_GetRunTime(void); +int32_t bsp_CheckRunTime(int32_t _LastTime); + +void bsp_InitHardTimer(void); +void bsp_StartHardTimer(uint8_t _CC, uint32_t _uiTimeOut, void * _pCallBack); + +#endif + +/***************************** www.armfly.com (END OF FILE) *********************************/ diff --git a/User/bsp/inc/bsp_usart_dma.h b/User/bsp/inc/bsp_usart_dma.h new file mode 100644 index 0000000..4b1dc97 --- /dev/null +++ b/User/bsp/inc/bsp_usart_dma.h @@ -0,0 +1,47 @@ +/* + * @Author: Memory 1619005172@qq.com + * @Date: 2026-04-15 18:00:45 + * @LastEditors: Memory 1619005172@qq.com + * @LastEditTime: 2026-04-15 19:25:36 + * @FilePath: \MDK-ARMd:\Project\MFT\Motor\User\bsp\inc\bsp_usart_dma.h + * @Description: + */ +#ifndef __USARTDMA_H +#define __USARTDMA_H + +#include "stm32f10x.h" +#include + +// 串口工作参数宏定义 +#define DEBUG_USARTx USART1 +#define DEBUG_USART_CLK RCC_APB2Periph_USART1 +#define DEBUG_USART_APBxClkCmd RCC_APB2PeriphClockCmd +#define DEBUG_USART_BAUDRATE 115200 + +// USART GPIO 引脚宏定义 +#define DEBUG_USART_GPIO_CLK (RCC_APB2Periph_GPIOA) +#define DEBUG_USART_GPIO_APBxClkCmd RCC_APB2PeriphClockCmd + +#define DEBUG_USART_TX_GPIO_PORT GPIOA +#define DEBUG_USART_TX_GPIO_PIN GPIO_Pin_9 +#define DEBUG_USART_RX_GPIO_PORT GPIOA +#define DEBUG_USART_RX_GPIO_PIN GPIO_Pin_10 + +#define DEBUG_USART_IRQ USART1_IRQn +#define DEBUG_USART_IRQHandler USART1_IRQHandler + +// 串口对应的DMA请求通道 +#define USART_RX_DMA_CHANNEL DMA1_Channel5 +// 外设寄存器地址 +#define USART_DR_ADDRESS (USART1_BASE + 0x04) +// 一次发送的数据量 +#define RECEIVEBUFF_SIZE 64 + +void USART_Config(void); +void USARTx_DMA_Config(void); +void Usart_SendArray(USART_TypeDef *pUSARTx, uint8_t *array, uint16_t num); + +extern uint8_t g_ucRxRcvNewFlag; +extern uint8_t g_RxBuf[64]; + +#endif /* __USARTDMA_H */ diff --git a/User/bsp/src/bsp_adc.c b/User/bsp/src/bsp_adc.c new file mode 100644 index 0000000..4e7fe35 --- /dev/null +++ b/User/bsp/src/bsp_adc.c @@ -0,0 +1,93 @@ + #include "bsp_adc.h" +// #include "delay.h" + +//ʼADC +//ǽԹͨΪ +//ĬϽͨ0~3 +void Adc_Init(void) +{ + ADC_InitTypeDef ADC_InitStructure; + GPIO_InitTypeDef GPIO_InitStructure; + + RCC_APB2PeriphClockCmd(RCC_APB2Periph_GPIOC |RCC_APB2Periph_ADC1, ENABLE ); //ʹADC1ͨʱ + + + RCC_ADCCLKConfig(RCC_PCLK2_Div6); //ADCƵ6 72M/6=12,ADCʱ䲻ܳ14M + + //PA1 Ϊģͨ + GPIO_InitStructure.GPIO_Pin = GPIO_Pin_1; + GPIO_InitStructure.GPIO_Mode = GPIO_Mode_AIN; //ģ + GPIO_Init(GPIOC, &GPIO_InitStructure); + + ADC_DeInit(ADC1); //λADC1, ADC1 ȫĴΪȱʡֵ + + ADC_InitStructure.ADC_Mode = ADC_Mode_Independent; //ADCģʽ:ADC1ADC2ڶģʽ + ADC_InitStructure.ADC_ScanConvMode = DISABLE; //ģתڵͨģʽ + ADC_InitStructure.ADC_ContinuousConvMode = DISABLE; //ģתڵתģʽ + ADC_InitStructure.ADC_ExternalTrigConv = ADC_ExternalTrigConv_None; //תⲿ + ADC_InitStructure.ADC_DataAlign = ADC_DataAlign_Right; //ADCҶ + ADC_InitStructure.ADC_NbrOfChannel = 1; //˳йתADCͨĿ + ADC_Init(ADC1, &ADC_InitStructure); //ADC_InitStructָIJʼADCxļĴ + + + ADC_Cmd(ADC1, ENABLE); //ʹָADC1 + + ADC_ResetCalibration(ADC1); //ʹܸλУ׼ + + while(ADC_GetResetCalibrationStatus(ADC1)); //ȴλУ׼ + + ADC_StartCalibration(ADC1); //ADУ׼ + + while(ADC_GetCalibrationStatus(ADC1)); //ȴУ׼ + +// ADC_SoftwareStartConvCmd(ADC1, ENABLE); //ʹָADC1ת + +} +//ADCֵ +//ch:ֵͨ 0~3 ADC_Channel_1 +u16 Get_Adc(u8 ch) +{ + //ָADCĹͨһУʱ + ADC_RegularChannelConfig(ADC1, ch, 1, ADC_SampleTime_239Cycles5 ); //ADC1,ADCͨ,ʱΪ239.5 + + ADC_SoftwareStartConvCmd(ADC1, ENABLE); //ʹָADC1ת + + while(!ADC_GetFlagStatus(ADC1, ADC_FLAG_EOC ));//ȴת + + return ADC_GetConversionValue(ADC1); //һADC1ת +} + +u16 Get_Adc_Average(u8 ch,u8 times) +{ + u32 temp_val=0; + u8 t; + for(t=0;t= 100) + { + electric_quantity_percent = 100; + } + else if(electric_quantity_percent <= 0) + { + electric_quantity_percent = 0; + } + return electric_quantity_percent; +} + + + diff --git a/User/bsp/src/bsp_adc.h b/User/bsp/src/bsp_adc.h new file mode 100644 index 0000000..ebcea61 --- /dev/null +++ b/User/bsp/src/bsp_adc.h @@ -0,0 +1,10 @@ +#ifndef __BSP_ADC_H +#define __BSP_ADC_H +//#include "sys.h" + +void Adc_Init(void); +u16 Get_Adc(u8 ch); +u16 Get_Adc_Average(u8 ch,u8 times); +u8 get_electric_quantity_percent(void); + +#endif diff --git a/User/bsp/src/bsp_beep.c b/User/bsp/src/bsp_beep.c new file mode 100644 index 0000000..7ee280b --- /dev/null +++ b/User/bsp/src/bsp_beep.c @@ -0,0 +1,189 @@ +/* +********************************************************************************************************* +* +* 模块名称 : 蜂鸣器驱动模块 +* 文件名称 : bsp_beep.c +* 版 本 : V1.1 +* 说 明 : 驱动蜂鸣器. +* +* 修改记录 : +* 版本号 日期 作者 说明 +* V1.0 2014-10-20 armfly 正式发布 +* V1.1 2015-08-30 armfly 增加修改蜂鸣器频率的功能 BEEP_Start() 函数添加频率形参 +* +* Copyright (C), 2015-2016, 安富莱电子 www.armfly.com +* +********************************************************************************************************* +*/ + +#include "bsp.h" + +#define BEEP_HAVE_POWER /* 定义此行表示有源蜂鸣器，直接通过GPIO驱动, 无需PWM */ + +#ifdef BEEP_HAVE_POWER /* 有源蜂鸣器 */ + +/* PA8 */ +#define GPIO_RCC_BEEP RCC_APB2Periph_GPIOB +#define GPIO_PORT_BEEP GPIOB +#define GPIO_PIN_BEEP GPIO_Pin_8 + +#define BEEP_ENABLE() GPIO_PORT_BEEP->BSRR = GPIO_PIN_BEEP /* 使能蜂鸣器鸣叫 */ +#define BEEP_DISABLE() GPIO_PORT_BEEP->BRR = GPIO_PIN_BEEP /* 禁止蜂鸣器鸣叫 */ +#else /* 无源蜂鸣器 */ +/* PA8/TIM1_CH1 ---> TIM1_CH1 */ + +/* 1500表示频率1.5KHz，5000表示50.00%的占空比 */ +#define BEEP_ENABLE() bsp_SetTIMOutPWM(GPIOA, GPIO_Pin_8, TIM1, 1, g_tBeep.uiFreq, 5000); + +/* 禁止蜂鸣器鸣叫 */ +#define BEEP_DISABLE() bsp_SetTIMOutPWM(GPIOA, GPIO_Pin_8, TIM1, 1, 1500, 0); +#endif + +static BEEP_T g_tBeep; /* 定义蜂鸣器全局结构体变量 */ + +/* +********************************************************************************************************* +* 函 数 名: BEEP_InitHard +* 功能说明: 初始化蜂鸣器硬件 +* 形 参：无 +* 返 回 值: 无 +********************************************************************************************************* +*/ +void BEEP_InitHard(void) +{ +#ifdef BEEP_HAVE_POWER /* 有源蜂鸣器 */ + GPIO_InitTypeDef GPIO_InitStructure; + + /* 打开GPIO的时钟 */ + RCC_APB2PeriphClockCmd(GPIO_RCC_BEEP, ENABLE); + + BEEP_DISABLE(); + + GPIO_InitStructure.GPIO_Speed = GPIO_Speed_50MHz; + GPIO_InitStructure.GPIO_Mode = GPIO_Mode_Out_PP; /* 推挽输出模式 */ + GPIO_InitStructure.GPIO_Pin = GPIO_PIN_BEEP; + GPIO_Init(GPIO_PORT_BEEP, &GPIO_InitStructure); +#else + ; /* 无源蜂鸣器 */ + +#endif +} + +/* +********************************************************************************************************* +* 函 数 名: BEEP_Start +* 功能说明: 启动蜂鸣音。 +* 形 参：_uiFreq : 频率 (Hz) +* _usBeepTime : 蜂鸣时间，单位10ms; 0 表示不鸣叫 +* _usStopTime : 停止时间，单位10ms; 0 表示持续鸣叫 +* _usCycle : 鸣叫次数， 0 表示持续鸣叫 +* 返 回 值: 无 +********************************************************************************************************* +*/ +void BEEP_Start(uint32_t _uiFreq, uint16_t _usBeepTime, uint16_t _usStopTime, uint16_t _usCycle) +{ + if (_usBeepTime == 0) + { + return; + } + + g_tBeep.uiFreq = _uiFreq; + g_tBeep.usBeepTime = _usBeepTime; + g_tBeep.usStopTime = _usStopTime; + g_tBeep.usCycle = _usCycle; + g_tBeep.usCount = 0; + g_tBeep.usCycleCount = 0; + g_tBeep.ucState = 0; + g_tBeep.ucEnalbe = 1; /* 设置完全局参数后再使能发声标志 */ + + BEEP_ENABLE(); /* 开始发声 */ +} + +/* +********************************************************************************************************* +* 函 数 名: BEEP_Stop +* 功能说明: 停止蜂鸣音。 +* 形 参：无 +* 返 回 值: 无 +********************************************************************************************************* +*/ +void BEEP_Stop(void) +{ + g_tBeep.ucEnalbe = 0; + + BEEP_DISABLE(); /* 必须在清控制标志后再停止发声，避免停止后在中断中又开启 */ +} + +/* +********************************************************************************************************* +* 函 数 名: BEEP_KeyTone +* 功能说明: 发送按键音， 固定 1.5KHz +* 形 参：无 +* 返 回 值: 无 +********************************************************************************************************* +*/ +void BEEP_KeyTone(void) +{ + BEEP_Start(4300, 4, 1, 1); +} + +/* +********************************************************************************************************* +* 函 数 名: BEEP_Pro +* 功能说明: 每隔10ms调用1次该函数，用于控制蜂鸣器发声。该函数在 bsp_timer.c 中被调用。 +* 形 参：无 +* 返 回 值: 无 +********************************************************************************************************* +*/ +void BEEP_Pro(void) +{ + if ((g_tBeep.ucEnalbe == 0) || (g_tBeep.usStopTime == 0)) + { + return; + } + + if (g_tBeep.ucState == 0) + { + if (g_tBeep.usStopTime > 0) /* 间断发声 */ + { + if (++g_tBeep.usCount >= g_tBeep.usBeepTime) + { + BEEP_DISABLE(); /* 停止发声 */ + g_tBeep.usCount = 0; + g_tBeep.ucState = 1; + } + } + else + { + ; /* 不做任何处理，连续发声 */ + } + } + else if (g_tBeep.ucState == 1) + { + if (++g_tBeep.usCount >= g_tBeep.usStopTime) + { + /* 连续发声时，直到调用stop停止为止 */ + if (g_tBeep.usCycle > 0) + { + if (++g_tBeep.usCycleCount >= g_tBeep.usCycle) + { + /* 循环次数到，停止发声 */ + g_tBeep.ucEnalbe = 0; + } + + if (g_tBeep.ucEnalbe == 0) + { + g_tBeep.usStopTime = 0; + return; + } + } + + g_tBeep.usCount = 0; + g_tBeep.ucState = 0; + + BEEP_ENABLE(); /* 开始发声 */ + } + } +} + +/***************************** 安富莱电子 www.armfly.com (END OF FILE) *********************************/ diff --git a/User/bsp/src/bsp_digital_tube.c b/User/bsp/src/bsp_digital_tube.c new file mode 100644 index 0000000..ac4d65d --- /dev/null +++ b/User/bsp/src/bsp_digital_tube.c @@ -0,0 +1,454 @@ +//------------------------------------------------------------------------------ +// 模块名称：数码管驱动模块 +// 文件名称：bsp_digital_tube +// 版本名称：V1.0 +// 文件说明：8个0.2寸共阴数码管轮流刷新控制点亮。 +// 日期时间：2018年8月15日16点42分 +// 文件作者：Jackie Chan +// 修改记录： +// 版本号 日期 作者 说明 +// V1.0 2018.08.15 J.C 正式发布 +// +// 公司名称：多场低温科技有限公司 +// +//------------------------------------------------------------------------------ + +#include "bsp.h" +#include +#include +#include + +// 数码管控制引脚对应的RCC时钟 +#define RCC_ALL_TUBE (RCC_APB2Periph_GPIOC | RCC_APB2Periph_GPIOD) +// 数码管的位选，高电平有效 +#define GPIO_PORT_A GPIOD +#define GPIO_PIN_A GPIO_Pin_0 +#define GPIO_PORT_B GPIOD +#define GPIO_PIN_B GPIO_Pin_1 +#define GPIO_PORT_C GPIOD +#define GPIO_PIN_C GPIO_Pin_2 +#define GPIO_PORT_D GPIOD +#define GPIO_PIN_D GPIO_Pin_3 +#define GPIO_PORT_E GPIOD +#define GPIO_PIN_E GPIO_Pin_4 +#define GPIO_PORT_F GPIOD +#define GPIO_PIN_F GPIO_Pin_5 +#define GPIO_PORT_G GPIOD +#define GPIO_PIN_G GPIO_Pin_6 +#define GPIO_PORT_H GPIOD +#define GPIO_PIN_H GPIO_Pin_7 +// 数码管的段选，高电平有效 +#define GPIO_PORT_DS1 GPIOC +#define GPIO_PIN_DS1 GPIO_Pin_9 +#define GPIO_PORT_DS2 GPIOC +#define GPIO_PIN_DS2 GPIO_Pin_8 +#define GPIO_PORT_DS3 GPIOC +#define GPIO_PIN_DS3 GPIO_Pin_10 +#define GPIO_PORT_DS4 GPIOC +#define GPIO_PIN_DS4 GPIO_Pin_6 +#define GPIO_PORT_DS5 GPIOD +#define GPIO_PIN_DS5 GPIO_Pin_11 +#define GPIO_PORT_DS6 GPIOD +#define GPIO_PIN_DS6 GPIO_Pin_10 +#define GPIO_PORT_DS7 GPIOD +#define GPIO_PIN_DS7 GPIO_Pin_9 +#define GPIO_PORT_DS8 GPIOD +#define GPIO_PIN_DS8 GPIO_Pin_8 + +// 关闭所有段选 +#define CLOSE_ALL_TUBE_COM \ + do \ + { \ + GPIO_PORT_DS1->BRR = GPIO_PIN_DS1; \ + GPIO_PORT_DS2->BRR = GPIO_PIN_DS2; \ + GPIO_PORT_DS3->BRR = GPIO_PIN_DS3; \ + GPIO_PORT_DS4->BRR = GPIO_PIN_DS4; \ + GPIO_PORT_DS5->BRR = GPIO_PIN_DS5; \ + GPIO_PORT_DS6->BRR = GPIO_PIN_DS6; \ + GPIO_PORT_DS7->BRR = GPIO_PIN_DS7; \ + GPIO_PORT_DS8->BRR = GPIO_PIN_DS8; \ + } while (0) +// 关闭所有位选 +#define CLOSE_ALL_TUBE_SEG \ + do \ + { \ + GPIO_PORT_A->BRR = GPIO_PIN_A; \ + GPIO_PORT_B->BRR = GPIO_PIN_B; \ + GPIO_PORT_C->BRR = GPIO_PIN_C; \ + GPIO_PORT_D->BRR = GPIO_PIN_D; \ + GPIO_PORT_E->BRR = GPIO_PIN_E; \ + GPIO_PORT_F->BRR = GPIO_PIN_F; \ + GPIO_PORT_G->BRR = GPIO_PIN_G; \ + GPIO_PORT_H->BRR = GPIO_PIN_H; \ + } while (0) + +// 数码管共阴或者共阳选择，用于正确输出位选电平 +#define SEG_A 0X01 +#define SEG_B 0X01 +#define SEG_C 0X01 +#define SEG_D 0X01 +#define SEG_E 0X01 +#define SEG_F 0X01 +#define SEG_G 0X01 +#define SEG_H 0X01 +#define SEG_0 0X00 // 数码管的该段<不点亮> + +const uint8_t g_tube_table[12][7] = { + {SEG_A, SEG_B, SEG_C, SEG_D, SEG_E, SEG_F, SEG_0}, // NO_0 + {SEG_0, SEG_B, SEG_C, SEG_0, SEG_0, SEG_0, SEG_0}, // NO_1 + {SEG_A, SEG_B, SEG_0, SEG_D, SEG_E, SEG_0, SEG_G}, // NO_2 + {SEG_A, SEG_B, SEG_C, SEG_D, SEG_0, SEG_0, SEG_G}, // NO_3 + {SEG_0, SEG_B, SEG_C, SEG_0, SEG_0, SEG_F, SEG_G}, // NO_4 + {SEG_A, SEG_0, SEG_C, SEG_D, SEG_0, SEG_F, SEG_G}, // NO_5 + {SEG_A, SEG_0, SEG_C, SEG_D, SEG_E, SEG_F, SEG_G}, // NO_6 + {SEG_A, SEG_B, SEG_C, SEG_0, SEG_0, SEG_0, SEG_0}, // NO_7 + {SEG_A, SEG_B, SEG_C, SEG_D, SEG_E, SEG_F, SEG_G}, // NO_8 + {SEG_A, SEG_B, SEG_C, SEG_D, SEG_0, SEG_F, SEG_G}, // NO_9 + {SEG_0, SEG_0, SEG_0, SEG_0, SEG_0, SEG_0, SEG_G}, // NO__ + {SEG_0, SEG_0, SEG_0, SEG_0, SEG_0, SEG_0, SEG_0}, // NO_NULL +}; + +// 全局变量声明 +DIGITIAL_TUBE_T g_tTube; +extern MOTO_T g_tMoto; + +// 该文件中的所有函数声明 +void bsp_InitDigitalTube(void); +void bsp_DigitalTubeMainLoop(void); +void bsp_TubeTest(uint8_t _com, uint8_t _seg); +void bsp_InitTubeVar(void); +void bsp_UpdateDisplayBuf(void); +void bsp_ToogleWorkMode(void); +void bsp_ToogleStateMode(void); +void bsp_Pulse2Buf(void); +void bsp_Angle2Buf(void); +static void bsp_ReadDatFromEEPROM(void); + +void bsp_InitTubeVar(void) +{ + uint8_t i = 0; + + for (i = 0; i < 8; i++) + { + g_tTube.buf[i] = NO_NULL; + } + g_tTube.disp_mode = MODE_PULSE; + g_tTube.cnt = 0; + g_tTube.state = IDLE; + // g_tTube.state = WORK; + g_tTube.dir = DIR_CW; + g_tTube.pulse = 0; + g_tTube.tim_pulse_cnt = 0; + g_tTube.angle = 0; +} + +void bsp_TubeTest(uint8_t _com, uint8_t _seg) +{ + if (_seg == ' ') + _seg = NO_NULL; + if (_seg >= 12) + return; + + CLOSE_ALL_TUBE_COM; + CLOSE_ALL_TUBE_SEG; + + if (g_tube_table[_seg][0]) + { + GPIO_PORT_A->BSRR = GPIO_PIN_A; + }; + if (g_tube_table[_seg][1]) + { + GPIO_PORT_B->BSRR = GPIO_PIN_B; + }; + if (g_tube_table[_seg][2]) + { + GPIO_PORT_C->BSRR = GPIO_PIN_C; + }; + if (g_tube_table[_seg][3]) + { + GPIO_PORT_D->BSRR = GPIO_PIN_D; + }; + if (g_tube_table[_seg][4]) + { + GPIO_PORT_E->BSRR = GPIO_PIN_E; + }; + if (g_tube_table[_seg][5]) + { + GPIO_PORT_F->BSRR = GPIO_PIN_F; + }; + if (g_tube_table[_seg][6]) + { + GPIO_PORT_G->BSRR = GPIO_PIN_G; + }; + if ((_com == 5) && (g_tTube.disp_mode == MODE_ANGLE)) + { + GPIO_PORT_H->BSRR = GPIO_PIN_H; + } + + switch (_com) + { + case 0: + GPIO_PORT_DS1->BSRR = GPIO_PIN_DS1; + break; + case 1: + GPIO_PORT_DS2->BSRR = GPIO_PIN_DS2; + break; + case 2: + GPIO_PORT_DS3->BSRR = GPIO_PIN_DS3; + break; + case 3: + GPIO_PORT_DS4->BSRR = GPIO_PIN_DS4; + break; + case 4: + GPIO_PORT_DS5->BSRR = GPIO_PIN_DS5; + break; + case 5: + GPIO_PORT_DS6->BSRR = GPIO_PIN_DS6; + break; + case 6: + GPIO_PORT_DS7->BSRR = GPIO_PIN_DS7; + break; + case 7: + GPIO_PORT_DS8->BSRR = GPIO_PIN_DS8; + break; + default: + break; + } +} +void bsp_ToogleDispMode(void) +{ + uint8_t buf[5]; // PULSE: 55AA00FF; ANGLE: FF00AA55 + + switch (g_tTube.disp_mode) + { + case MODE_PULSE: + g_tTube.disp_mode = MODE_ANGLE; + break; + case MODE_ANGLE: + g_tTube.disp_mode = MODE_PULSE; + break; + default: + break; + } + + if (g_tTube.disp_mode == MODE_ANGLE) + { + buf[0] = 0xFF; + buf[1] = 0x00; + buf[2] = 0xAA; + buf[3] = 0x55; + ee_WriteBytes(buf, 0, 4); + } + else if (g_tTube.disp_mode == MODE_PULSE) + { + buf[0] = 0x55; + buf[1] = 0xAA; + buf[2] = 0x00; + buf[3] = 0xFF; + ee_WriteBytes(buf, 0, 4); + } + + bsp_UpdateDisplayBuf(); +} +void bsp_ToogleStateMode(void) +{ + switch (g_tTube.state) + { + case IDLE: + g_tTube.state = WORK; + break; + case WORK: + g_tTube.state = IDLE; + break; + default: + break; + } + bsp_UpdateDisplayBuf(); +} + +void bsp_UpdateDisplayBuf(void) +{ + uint8_t i = 0; + + // 开机或执行了搜索命令但未找到零点时的数码管显示状态 + if ((g_tTube.state == IDLE) || (g_tTube.state == SEARCH)) + { + if (g_tTube.disp_mode == MODE_PULSE) // 数码管显示[--------] + { + memset(g_tTube.buf, NO__, 8); + } + else if (g_tTube.disp_mode == MODE_ANGLE) // 数码管显示[ -.--] + { + for (i = 0; i < 5; i++) + { + g_tTube.buf[i] = NO_NULL; + } + g_tTube.buf[5] = NO__; + g_tTube.buf[6] = NO__; + g_tTube.buf[7] = NO__; + } + } + else if (g_tTube.state == WORK) // 已经找到零点后数码管的显示状态 + { + bsp_Angle2Buf(); // 数码管显示，例如[-1234567] + } +} +void bsp_Pulse2Buf(void) +{ + uint8_t i = 0; + + memset(g_tTube.buf, 0, 8); + snprintf(g_tTube.buf, 9, "%8d", g_tTube.pulse); + for (i = 0; i < 8; i++) + { + if (g_tTube.buf[i] == ' ') + { + g_tTube.buf[i] = NO_NULL; + } + else if (g_tTube.buf[i] == '-') + { + g_tTube.buf[i] = NO__; + } + else if (isdigit(g_tTube.buf[i])) + { + g_tTube.buf[i] = g_tTube.buf[i] - '0'; + } + } +} +void bsp_Angle2Buf(void) +{ + uint8_t i = 0; + float angle = (((g_tTube.pulse % STEP_PER_LAP) + STEP_PER_LAP) % STEP_PER_LAP) * 360.0f / (STEP_PER_LAP / 100.0f); + // printf("angle = %f\r\n", angle); + if (angle < 0) + { + angle -= 0.5f; // 负数向下取整 + angle += 360.0f; // 转换成整角度 + } + else + angle += 0.5f; // 正数向上取整 + + // printf("angle = %f\r\n", angle); + + memset(g_tTube.buf, 0, 8); + g_tTube.angle = angle; + snprintf(g_tTube.buf, 9, "%8d", g_tTube.angle); + for (i = 0; i < 8; i++) + { + if (g_tTube.buf[i] == ' ') + { + g_tTube.buf[i] = NO_NULL; + if (i >= 5) + { + g_tTube.buf[i] = NO_0; + } + } + else if (g_tTube.buf[i] == '-') + { + if (i >= 5) + { + g_tTube.buf[4] = NO__; + g_tTube.buf[i] = NO_0; + } + else + { + g_tTube.buf[i] = NO__; + } + } + else if (isdigit(g_tTube.buf[i])) + { + g_tTube.buf[i] = g_tTube.buf[i] - '0'; + } + } +} + +void bsp_DigitalTubeMainLoop(void) +{ + static uint8_t i = 0; + if (++i >= 50) // 该函数每1ms调用一次，每50ms刷新一次脉冲或角度值 + { + i = 0; + if (g_tTube.dir == DIR_CCW) + { + g_tTube.pulse = g_tMoto.pv_pulse; + } + else + { + g_tTube.pulse = g_tMoto.pv_pulse; + } + bsp_UpdateDisplayBuf(); + } + bsp_TubeTest(g_tTube.cnt, g_tTube.buf[g_tTube.cnt]); + if (++g_tTube.cnt >= 8) + g_tTube.cnt = 0; +} + +//------------------------------------------------------------------------------ +// 函 数 名: bsp_InitDigitalTube +// 功能说明: 配置数码管相关的GPIO, 该函数被 bsp_Init() 调用。 +// 形 参: 无 +// 返 回 值: 无 +//------------------------------------------------------------------------------ +void bsp_InitDigitalTube(void) +{ + GPIO_InitTypeDef GPIO_InitStructure; + // 打开数码管GPIO时钟 + RCC_APB2PeriphClockCmd(RCC_ALL_TUBE, ENABLE); + GPIO_InitStructure.GPIO_Speed = GPIO_Speed_50MHz; + GPIO_InitStructure.GPIO_Mode = GPIO_Mode_Out_PP; // 推挽输出模式 + + GPIO_InitStructure.GPIO_Pin = GPIO_PIN_A; // 位 a + GPIO_Init(GPIO_PORT_A, &GPIO_InitStructure); + GPIO_InitStructure.GPIO_Pin = GPIO_PIN_B; // 位 b + GPIO_Init(GPIO_PORT_B, &GPIO_InitStructure); + GPIO_InitStructure.GPIO_Pin = GPIO_PIN_C; // 位 c + GPIO_Init(GPIO_PORT_C, &GPIO_InitStructure); + GPIO_InitStructure.GPIO_Pin = GPIO_PIN_D; // 位 d + GPIO_Init(GPIO_PORT_D, &GPIO_InitStructure); + GPIO_InitStructure.GPIO_Pin = GPIO_PIN_E; // 位 e + GPIO_Init(GPIO_PORT_E, &GPIO_InitStructure); + GPIO_InitStructure.GPIO_Pin = GPIO_PIN_F; // 位 f + GPIO_Init(GPIO_PORT_F, &GPIO_InitStructure); + GPIO_InitStructure.GPIO_Pin = GPIO_PIN_G; // 位 g + GPIO_Init(GPIO_PORT_G, &GPIO_InitStructure); + GPIO_InitStructure.GPIO_Pin = GPIO_PIN_H; // 位 h + GPIO_Init(GPIO_PORT_H, &GPIO_InitStructure); + + GPIO_InitStructure.GPIO_Pin = GPIO_PIN_DS1; // 段 1 + GPIO_Init(GPIO_PORT_DS1, &GPIO_InitStructure); + GPIO_InitStructure.GPIO_Pin = GPIO_PIN_DS2; // 段 2 + GPIO_Init(GPIO_PORT_DS2, &GPIO_InitStructure); + GPIO_InitStructure.GPIO_Pin = GPIO_PIN_DS3; // 段 3 + GPIO_Init(GPIO_PORT_DS3, &GPIO_InitStructure); + GPIO_InitStructure.GPIO_Pin = GPIO_PIN_DS4; // 段 4 + GPIO_Init(GPIO_PORT_DS4, &GPIO_InitStructure); + GPIO_InitStructure.GPIO_Pin = GPIO_PIN_DS5; // 段 5 + GPIO_Init(GPIO_PORT_DS5, &GPIO_InitStructure); + GPIO_InitStructure.GPIO_Pin = GPIO_PIN_DS6; // 段 6 + GPIO_Init(GPIO_PORT_DS6, &GPIO_InitStructure); + GPIO_InitStructure.GPIO_Pin = GPIO_PIN_DS7; // 段 7 + GPIO_Init(GPIO_PORT_DS7, &GPIO_InitStructure); + GPIO_InitStructure.GPIO_Pin = GPIO_PIN_DS8; // 段 8 + GPIO_Init(GPIO_PORT_DS8, &GPIO_InitStructure); + + bsp_InitTubeVar(); + bsp_ReadDatFromEEPROM(); + bsp_UpdateDisplayBuf(); +} + +static void bsp_ReadDatFromEEPROM(void) +{ + uint8_t buf[5]; // PULSE: 55AA00FF; ANGLE: FF00AA55 + + ee_ReadBytes((uint8_t *)buf, 0, 4); + if ((buf[0] == 0X55) && (buf[1] == 0XAA) && (buf[2] == 0X00) && (buf[3] == 0XFF)) + { + g_tTube.disp_mode = MODE_PULSE; + } + else if ((buf[0] == 0XFF) && (buf[1] == 0X00) && (buf[2] == 0XAA) && (buf[3] == 0X55)) + { + g_tTube.disp_mode = MODE_ANGLE; + } +} + +//-------------------------------- End of file --------------------------------- diff --git a/User/bsp/src/bsp_drv8880.c b/User/bsp/src/bsp_drv8880.c new file mode 100644 index 0000000..2390fb0 --- /dev/null +++ b/User/bsp/src/bsp_drv8880.c @@ -0,0 +1,268 @@ +//------------------------------------------------------------------------------ +// 模块名称：步进电机芯片DRV8880驱动模块 +// 文件名称：bsp_drv8880 +// 版本名称：V1.0 +// 文件说明：控制步进电机芯片DRV8880 +// 日期时间：2018年8月17日16点23分 +// 文件作者：Jackie Chan +// 修改记录： +// 版本号 日期 作者 说明 +// V1.0 2018.08.17 J.C 正式发布 +// +// 公司名称：多场低温科技有限公司 +// +//------------------------------------------------------------------------------ + +#include "bsp.h" + +// DRV888控制引脚对应的RCC时钟 +#define RCC_ALL_MOTO (RCC_APB2Periph_GPIOB | RCC_APB2Periph_GPIOC | \ + RCC_APB2Periph_GPIOE | RCC_APB2Periph_GPIOG) + +// DRV8880控制引脚 +#define GPIO_PORT_STEP GPIOC // 脉冲输入，内部下拉，上升沿触发 +#define GPIO_PIN_STEP GPIO_Pin_7 + +#define GPIO_PORT_DIR GPIOE // 转动方向，内部下拉 +#define GPIO_PIN_DIR GPIO_Pin_10 + +#define GPIO_PORT_ENABLE GPIOE // 器件使能，内部下拉 +#define GPIO_PIN_ENABLE GPIO_Pin_11 + +#define GPIO_PORT_SLEEP GPIOB // 低电平进入睡眠模式，内部下拉 +#define GPIO_PIN_SLEEP GPIO_Pin_11 + +#define GPIO_PORT_ATE GPIOE // 高电平进入自动整定模式，内部下拉 +#define GPIO_PIN_ATE GPIO_Pin_15 + +#define GPIO_PORT_TRQ1 GPIOG // 力矩设置，内部下拉 +#define GPIO_PIN_TRQ1 GPIO_Pin_1 + +#define GPIO_PORT_TRQ0 GPIOG // 力矩设置，内部下拉 +#define GPIO_PIN_TRQ0 GPIO_Pin_0 + +#define GPIO_PORT_M1 GPIOE // 细分，三态输入引脚 +#define GPIO_PIN_M1 GPIO_Pin_8 + +#define GPIO_PORT_M0 GPIOE // 细分，三态输入引脚 +#define GPIO_PIN_M0 GPIO_Pin_7 + +#define GPIO_PORT_DECAY1 GPIOE // 衰减模式设置，自动整定时被忽略 +#define GPIO_PIN_DECAY1 GPIO_Pin_13 + +#define GPIO_PORT_DECAY0 GPIOE // 衰减模式设置，自动整定时被忽略 +#define GPIO_PIN_DECAY0 GPIO_Pin_12 + +#define GPIO_PORT_TOFF GPIOB // Off time设置，三态输入 +#define GPIO_PIN_TOFF GPIO_Pin_10 + +#define GPIO_PORT_FAULT GPIOE // 失效报警输出，开漏输出 +#define GPIO_PIN_FAULT GPIO_Pin_14 + +// 细分相关宏定义 +#define M1_ENABLE (GPIO_PORT_M1->BSRR = GPIO_PIN_M1) +#define M0_ENABLE (GPIO_PORT_M0->BSRR = GPIO_PIN_M0) +#define M1_DISABLE (GPIO_PORT_M1->BRR = GPIO_PIN_M1) +#define M0_DISABLE (GPIO_PORT_M0->BRR = GPIO_PIN_M0) +#define M0_SET_AS_INPUT() \ + { \ + GPIO_PORT_M0->CRL &= 0X0FFFFFFF; \ + GPIO_PORT_M0->CRL |= 0X40000000; \ + } +#define M0_SET_AS_OUTPUT() \ + { \ + GPIO_PORT_M0->CRL &= 0X0FFFFFFF; \ + GPIO_PORT_M0->CRL |= 0X30000000; \ + } + +// DRV8880使能相关宏定义 +#define DRV8880_ENABLE (GPIO_PORT_ENABLE->BSRR = GPIO_PIN_ENABLE) +#define DRV8880_DISABLE (GPIO_PORT_ENABLE->BRR = GPIO_PIN_ENABLE) + +// DRV8880方向控制引脚 +#define DRV8880_CW (GPIO_PORT_DIR->BRR = GPIO_PIN_DIR) // 样品杆从上往下看，顺时针旋转（+） +#define DRV8880_CCW (GPIO_PORT_DIR->BSRR = GPIO_PIN_DIR) // 样品杆从上往下看，逆时针旋转（-） + +extern DIGITIAL_TUBE_T g_tTube; + +// 供外部调用的函数声明 +void bsp_Init_Drv8880_Hard(void); +void bsp_drv8880_enable_config(FunctionalState en); +void bsp_drv8880_microstep_config(MICRO_STEPPING_E step); +void bsp_drv8880_config_dir(DIR_E dir); +// void bsp_drv8880_vref_config(uint16_t vol); // vol:0~3300,代表0~3.3V +static void bsp_dev8880_vref_init_hard(uint16_t vol); // vol:0~3300,代表0~3.3V + +void bsp_drv8880_microstep_config(MICRO_STEPPING_E step) +{ + switch (step) + { + case STEP_FULL: // M1M0: 00 + M0_SET_AS_OUTPUT(); + M1_DISABLE; + M0_DISABLE; + break; + case STEP_1_2_NC: // M1M0: 01 + M0_SET_AS_OUTPUT(); + M1_DISABLE; + M0_ENABLE; + break; + case STEP_1_2: // M1M0: 10 + M0_SET_AS_OUTPUT(); + M1_ENABLE; + M0_DISABLE; + break; + case STEP_1_4: // M1M0: 11 + M0_SET_AS_OUTPUT(); + M1_ENABLE; + M0_ENABLE; + break; + case STEP_1_8: // M1M0: 0Z + M0_SET_AS_INPUT(); + M1_DISABLE; + break; + case STEP_1_16: // M1M0: 1Z + M0_SET_AS_INPUT(); + M1_ENABLE; + break; + default: + break; + } +} +void bsp_drv8880_config_dir(DIR_E dir) +{ + switch (dir) + { + case DIR_CW: + DRV8880_CW; + g_tTube.dir = DIR_CW; + break; + case DIR_CCW: + DRV8880_CCW; + g_tTube.dir = DIR_CCW; + break; + default: + break; + } +} +void bsp_drv8880_enable_config(FunctionalState en) +{ + if (en == DISABLE) + { + DRV8880_DISABLE; + } + else + { + DRV8880_ENABLE; + } +} + +// vol:0~3300,代表0~3.3V +static void bsp_dev8880_vref_init_hard(uint16_t vol) +{ + float temp = vol; + + GPIO_InitTypeDef GPIO_InitStructure; + DAC_InitTypeDef DAC_InitType; + + RCC_APB2PeriphClockCmd(RCC_APB2Periph_GPIOA, ENABLE); // 使能PORTA通道时钟 + RCC_APB1PeriphClockCmd(RCC_APB1Periph_DAC, ENABLE); // 使能DAC通道时钟 + + GPIO_InitStructure.GPIO_Pin = GPIO_Pin_4; // 端口配置 + GPIO_InitStructure.GPIO_Mode = GPIO_Mode_AIN; // 模拟输入 + GPIO_InitStructure.GPIO_Speed = GPIO_Speed_50MHz; + GPIO_Init(GPIOA, &GPIO_InitStructure); + GPIO_SetBits(GPIOA, GPIO_Pin_4); // PA.4 输出高 + + DAC_InitType.DAC_Trigger = DAC_Trigger_None; // 不使用触发功能 TEN1=0 + DAC_InitType.DAC_WaveGeneration = DAC_WaveGeneration_None; // 不使用波形发生 + DAC_InitType.DAC_LFSRUnmask_TriangleAmplitude = DAC_LFSRUnmask_Bit0; // 屏蔽、幅值设置 + DAC_InitType.DAC_OutputBuffer = DAC_OutputBuffer_Disable; // DAC1输出缓存关闭 BOFF1=1 + DAC_Init(DAC_Channel_1, &DAC_InitType); // 初始化DAC通道1 + + DAC_Cmd(DAC_Channel_1, ENABLE); // 使能DAC1 + + DAC_SetChannel1Data(DAC_Align_12b_R, 0); // 12位右对齐数据格式设置DAC值 + + temp /= 1000; + temp = temp * 4096 / 3.3; + DAC_SetChannel1Data(DAC_Align_12b_R, temp); // 12位右对齐数据格式设置DAC值 +} + +void bsp_Init_Drv8880_Hard(void) +{ + GPIO_InitTypeDef GPIO_InitStructure; + + RCC_APB2PeriphClockCmd(RCC_ALL_MOTO, ENABLE); + + GPIO_InitStructure.GPIO_Speed = GPIO_Speed_50MHz; + GPIO_InitStructure.GPIO_Mode = GPIO_Mode_Out_PP; + + // 配置自动整定引脚为高电平，设置为自动整定模式 + GPIO_PORT_ATE->BSRR = GPIO_PIN_ATE; + GPIO_InitStructure.GPIO_Pin = GPIO_PIN_ATE; + GPIO_Init(GPIO_PORT_ATE, &GPIO_InitStructure); + + // 配置脉冲输入引脚，设置为默认低电平 + GPIO_InitStructure.GPIO_Pin = GPIO_PIN_STEP; + GPIO_Init(GPIO_PORT_STEP, &GPIO_InitStructure); + + // 配置方向引脚，设置默认为低电平 + GPIO_InitStructure.GPIO_Pin = GPIO_PIN_DIR; + GPIO_Init(GPIO_PORT_DIR, &GPIO_InitStructure); + + // 配置使能引脚，设置默认为低电平，不使能 + GPIO_InitStructure.GPIO_Pin = GPIO_PIN_ENABLE; + GPIO_Init(GPIO_PORT_ENABLE, &GPIO_InitStructure); + + // 配置睡眠引脚，设置默认为低电平，处于睡眠状态 + GPIO_InitStructure.GPIO_Pin = GPIO_PIN_SLEEP; + GPIO_Init(GPIO_PORT_SLEEP, &GPIO_InitStructure); + + // 配置细分引脚，设置默认为低电平，不细分 + GPIO_InitStructure.GPIO_Pin = GPIO_PIN_M1; + GPIO_Init(GPIO_PORT_M1, &GPIO_InitStructure); + GPIO_InitStructure.GPIO_Pin = GPIO_PIN_M0; + GPIO_Init(GPIO_PORT_M0, &GPIO_InitStructure); + + // 配置力矩引脚，设置默认为低电平，100%力矩 + GPIO_InitStructure.GPIO_Pin = GPIO_PIN_TRQ1; + GPIO_Init(GPIO_PORT_TRQ1, &GPIO_InitStructure); + GPIO_InitStructure.GPIO_Pin = GPIO_PIN_TRQ0; + GPIO_Init(GPIO_PORT_TRQ0, &GPIO_InitStructure); + + // 设置衰减模式，设置默认为低电平，为slow decay模式 + GPIO_InitStructure.GPIO_Pin = GPIO_PIN_DECAY1; + GPIO_Init(GPIO_PORT_DECAY1, &GPIO_InitStructure); + GPIO_InitStructure.GPIO_Pin = GPIO_PIN_DECAY0; + GPIO_Init(GPIO_PORT_DECAY0, &GPIO_InitStructure); + + // 设置fixed-off-time，设置默认为低电平，为20us + GPIO_InitStructure.GPIO_Pin = GPIO_PIN_TOFF; + GPIO_Init(GPIO_PORT_TOFF, &GPIO_InitStructure); + + // 设置报警输出引脚，设置为输入浮空模式 + GPIO_InitStructure.GPIO_Mode = GPIO_Mode_IN_FLOATING; + GPIO_InitStructure.GPIO_Pin = GPIO_PIN_FAULT; + GPIO_Init(GPIO_PORT_FAULT, &GPIO_InitStructure); + + // 设置细分 + bsp_drv8880_microstep_config(STEP_1_16); + + // 方向设置 + bsp_drv8880_config_dir(DIR_CCW); + + // DA输出，步进电机电流设置 0.495V + + // 设置DA输出的电压为0.495V + bsp_dev8880_vref_init_hard(1500); + + // 退出睡眠模式 + GPIO_PORT_SLEEP->BSRR = GPIO_PIN_SLEEP; + + // 暂时不使能，等待零点所搜命令 + // bsp_drv8880_enable_config(DISABLE); + bsp_drv8880_enable_config(ENABLE); +} + +//-------------------------------- End of file --------------------------------- diff --git a/User/bsp/src/bsp_eeprom_24xx.c b/User/bsp/src/bsp_eeprom_24xx.c new file mode 100644 index 0000000..1e20154 --- /dev/null +++ b/User/bsp/src/bsp_eeprom_24xx.c @@ -0,0 +1,236 @@ +/* +********************************************************************************************************* +* +* 模块名称 : 串行EEPROM 24xx驱动模块 +* 文件名称 : bsp_eeprom_24xx.c +* 版 本 : V1.0 +* 说 明 : 实现24xx系列EEPROM的读写操作。写操作采用页写模式提高写入效率。 +* +* 修改记录 : +* 版本号 日期 作者 说明 +* V1.0 2013-02-01 armfly 正式发布 +* +* Copyright (C), 2013-2014, 安富莱电子 www.armfly.com +* +********************************************************************************************************* +*/ + +/* + 应用说明：访问串行EEPROM前，请先调用一次 bsp_InitI2C()函数配置好I2C相关的GPIO. +*/ + +#include "bsp.h" +#include "demo_i2c_eeprom.h" + +/* +********************************************************************************************************* +* 函 数 名: ee_CheckOk +* 功能说明: 判断串行EERPOM是否正常 +* 形 参: 无 +* 返 回 值: 1 表示正常， 0 表示不正常 +********************************************************************************************************* +*/ +uint8_t ee_CheckOk(void) +{ + if (i2c_CheckDevice(EE_DEV_ADDR) == 0) + { + return 1; + } + else + { + /* 失败后，切记发送I2C总线停止信号 */ + i2c_Stop(); + return 0; + } +} + +/* +********************************************************************************************************* +* 函 数 名: ee_ReadBytes +* 功能说明: 从串行EEPROM指定地址处开始读取若干数据 +* 形 参: _usAddress : 起始地址 +* _usSize : 数据长度，单位为字节 +* _pReadBuf : 存放读到的数据的缓冲区指针 +* 返 回 值: 0 表示失败，1表示成功 +********************************************************************************************************* +*/ +uint8_t ee_ReadBytes(uint8_t *_pReadBuf, uint16_t _usAddress, uint16_t _usSize) +{ + uint16_t i; + + /* 采用串行EEPROM随即读取指令序列，连续读取若干字节 */ + + /* 第1步：发起I2C总线启动信号 */ + i2c_Start(); + + /* 第2步：发起控制字节，高7bit是地址，bit0是读写控制位，0表示写，1表示读 */ + i2c_SendByte(EE_DEV_ADDR | I2C_WR); /* 此处是写指令 */ + + /* 第3步：发送ACK */ + if (i2c_WaitAck() != 0) + { + goto cmd_fail; /* EEPROM器件无应答 */ + } + + /* 第4步：发送字节地址，24C02只有256字节，因此1个字节就够了，如果是24C04以上，那么此处需要连发多个地址 */ + if (EE_ADDR_BYTES == 1) + { + i2c_SendByte((uint8_t)_usAddress); + if (i2c_WaitAck() != 0) + { + goto cmd_fail; /* EEPROM器件无应答 */ + } + } + else + { + i2c_SendByte(_usAddress >> 8); + if (i2c_WaitAck() != 0) + { + goto cmd_fail; /* EEPROM器件无应答 */ + } + + i2c_SendByte(_usAddress); + if (i2c_WaitAck() != 0) + { + goto cmd_fail; /* EEPROM器件无应答 */ + } + } + + /* 第6步：重新启动I2C总线。下面开始读取数据 */ + i2c_Start(); + + /* 第7步：发起控制字节，高7bit是地址，bit0是读写控制位，0表示写，1表示读 */ + i2c_SendByte(EE_DEV_ADDR | I2C_RD); /* 此处是读指令 */ + + /* 第8步：发送ACK */ + if (i2c_WaitAck() != 0) + { + goto cmd_fail; /* EEPROM器件无应答 */ + } + + /* 第9步：循环读取数据 */ + for (i = 0; i < _usSize; i++) + { + _pReadBuf[i] = i2c_ReadByte(); /* 读1个字节 */ + + /* 每读完1个字节后，需要发送Ack， 最后一个字节不需要Ack，发Nack */ + if (i != _usSize - 1) + { + i2c_Ack(); /* 中间字节读完后，CPU产生ACK信号(驱动SDA = 0) */ + } + else + { + i2c_NAck(); /* 最后1个字节读完后，CPU产生NACK信号(驱动SDA = 1) */ + } + } + /* 发送I2C总线停止信号 */ + i2c_Stop(); + return 1; /* 执行成功 */ + +cmd_fail: /* 命令执行失败后，切记发送停止信号，避免影响I2C总线上其他设备 */ + /* 发送I2C总线停止信号 */ + i2c_Stop(); + return 0; +} + +/* +********************************************************************************************************* +* 函 数 名: ee_WriteBytes +* 功能说明: 向串行EEPROM指定地址写入若干数据，采用页写操作提高写入效率 +* 形 参: _usAddress : 起始地址 +* _usSize : 数据长度，单位为字节 +* _pWriteBuf : 存放读到的数据的缓冲区指针 +* 返 回 值: 0 表示失败，1表示成功 +********************************************************************************************************* +*/ +uint8_t ee_WriteBytes(uint8_t *_pWriteBuf, uint16_t _usAddress, uint16_t _usSize) +{ + uint16_t i, m; + uint16_t usAddr; + + /* + 写串行EEPROM不像读操作可以连续读取很多字节，每次写操作只能在同一个page。 + 对于24xx02，page size = 8 + 简单的处理方法为：按字节写操作模式，每写1个字节，都发送地址 + 为了提高连续写的效率: 本函数采用page wirte操作。 + */ + + usAddr = _usAddress; + for (i = 0; i < _usSize; i++) + { + /* 当发送第1个字节或是页面首地址时，需要重新发起启动信号和地址 */ + if ((i == 0) || (usAddr & (EE_PAGE_SIZE - 1)) == 0) + { + /*　第０步：发停止信号，启动内部写操作　*/ + i2c_Stop(); + + /* 通过检查器件应答的方式，判断内部写操作是否完成, 一般小于 10ms + CLK频率为200KHz时，查询次数为30次左右 + */ + for (m = 0; m < 1000; m++) + { + /* 第1步：发起I2C总线启动信号 */ + i2c_Start(); + + /* 第2步：发起控制字节，高7bit是地址，bit0是读写控制位，0表示写，1表示读 */ + i2c_SendByte(EE_DEV_ADDR | I2C_WR); /* 此处是写指令 */ + + /* 第3步：发送一个时钟，判断器件是否正确应答 */ + if (i2c_WaitAck() == 0) + { + break; + } + } + if (m == 1000) + { + goto cmd_fail; /* EEPROM器件写超时 */ + } + + /* 第4步：发送字节地址，24C02只有256字节，因此1个字节就够了，如果是24C04以上，那么此处需要连发多个地址 */ + if (EE_ADDR_BYTES == 1) + { + i2c_SendByte((uint8_t)usAddr); + if (i2c_WaitAck() != 0) + { + goto cmd_fail; /* EEPROM器件无应答 */ + } + } + else + { + i2c_SendByte(usAddr >> 8); + if (i2c_WaitAck() != 0) + { + goto cmd_fail; /* EEPROM器件无应答 */ + } + + i2c_SendByte(usAddr); + if (i2c_WaitAck() != 0) + { + goto cmd_fail; /* EEPROM器件无应答 */ + } + } + } + + /* 第6步：开始写入数据 */ + i2c_SendByte(_pWriteBuf[i]); + + /* 第7步：发送ACK */ + if (i2c_WaitAck() != 0) + { + goto cmd_fail; /* EEPROM器件无应答 */ + } + + usAddr++; /* 地址增1 */ + } + + /* 命令执行成功，发送I2C总线停止信号 */ + i2c_Stop(); + return 1; + +cmd_fail: /* 命令执行失败后，切记发送停止信号，避免影响I2C总线上其他设备 */ + /* 发送I2C总线停止信号 */ + i2c_Stop(); + return 0; +} + +/***************************** 安富莱电子 www.armfly.com (END OF FILE) *********************************/ diff --git a/User/bsp/src/bsp_i2c_gpio.c b/User/bsp/src/bsp_i2c_gpio.c new file mode 100644 index 0000000..22d7d09 --- /dev/null +++ b/User/bsp/src/bsp_i2c_gpio.c @@ -0,0 +1,305 @@ +/* +********************************************************************************************************* +* +* 模块名称 : I2C总线驱动模块 +* 文件名称 : bsp_i2c_gpio.c +* 版 本 : V1.0 +* 说 明 : 用gpio模拟i2c总线, 适用于STM32F4系列CPU。该模块不包括应用层命令帧，仅包括I2C总线基本操作函数。 +* +* 修改记录 : +* 版本号 日期 作者 说明 +* V1.0 2015-05-21 armfly 正式发布 +* +* Copyright (C), 2015-2016, 安富莱电子 www.armfly.com +* +********************************************************************************************************* +*/ + +/* + 应用说明： + 在访问I2C设备前，请先调用 i2c_CheckDevice() 检测I2C设备是否正常，该函数会配置GPIO +*/ + +#include "bsp.h" + +/* + 安富莱STM32-V4开发板 i2c总线GPIO: + PB6/I2C1_SCL + PB7/I2C1_SDA +*/ + +/* 定义I2C总线连接的GPIO端口, 用户只需要修改下面4行代码即可任意改变SCL和SDA的引脚 */ + +#define RCC_I2C_PORT RCC_APB2Periph_GPIOB /* GPIO端口时钟 */ + +#define PORT_I2C_SCL GPIOB /* GPIO端口 */ +#define PIN_I2C_SCL GPIO_Pin_6 /* GPIO引脚 */ + +#define PORT_I2C_SDA GPIOB /* GPIO端口 */ +#define PIN_I2C_SDA GPIO_Pin_7 /* GPIO引脚 */ + +#define I2C_SCL_PIN GPIO_Pin_6 /* 连接到SCL时钟线的GPIO */ +#define I2C_SDA_PIN GPIO_Pin_7 /* 连接到SDA数据线的GPIO */ + +/* 定义读写SCL和SDA的宏 */ +#define I2C_SCL_1() PORT_I2C_SCL->BSRR = I2C_SCL_PIN /* SCL = 1 */ +#define I2C_SCL_0() PORT_I2C_SCL->BRR = I2C_SCL_PIN /* SCL = 0 */ + +#define I2C_SDA_1() PORT_I2C_SDA->BSRR = I2C_SDA_PIN /* SDA = 1 */ +#define I2C_SDA_0() PORT_I2C_SDA->BRR = I2C_SDA_PIN /* SDA = 0 */ + +#define I2C_SDA_READ() ((PORT_I2C_SDA->IDR & I2C_SDA_PIN) != 0) /* 读SDA口线状态 */ +#define I2C_SCL_READ() ((PORT_I2C_SCL->IDR & I2C_SCL_PIN) != 0) /* 读SCL口线状态 */ + +/* +********************************************************************************************************* +* 函 数 名: bsp_InitI2C +* 功能说明: 配置I2C总线的GPIO，采用模拟IO的方式实现 +* 形 参: 无 +* 返 回 值: 无 +********************************************************************************************************* +*/ +void bsp_InitI2C(void) +{ + GPIO_InitTypeDef GPIO_InitStructure; + + RCC_APB2PeriphClockCmd(RCC_I2C_PORT, ENABLE); /* 打开GPIO时钟 */ + + GPIO_InitStructure.GPIO_Speed = GPIO_Speed_50MHz; + GPIO_InitStructure.GPIO_Mode = GPIO_Mode_Out_OD; /* 开漏输出模式 */ + + GPIO_InitStructure.GPIO_Pin = PIN_I2C_SCL; + GPIO_Init(PORT_I2C_SCL, &GPIO_InitStructure); + + GPIO_InitStructure.GPIO_Pin = PIN_I2C_SDA; + GPIO_Init(PORT_I2C_SDA, &GPIO_InitStructure); + + /* 给一个停止信号, 复位I2C总线上的所有设备到待机模式 */ + i2c_Stop(); +} + +/* +********************************************************************************************************* +* 函 数 名: i2c_Delay +* 功能说明: I2C总线位延迟，最快400KHz +* 形 参: 无 +* 返 回 值: 无 +********************************************************************************************************* +*/ +static void i2c_Delay(void) +{ + uint8_t i; + + /*　 + CPU主频168MHz时，在内部Flash运行, MDK工程不优化。用台式示波器观测波形。 + 循环次数为5时，SCL频率 = 1.78MHz (读耗时: 92ms, 读写正常，但是用示波器探头碰上就读写失败。时序接近临界) + 循环次数为10时，SCL频率 = 1.1MHz (读耗时: 138ms, 读速度: 118724B/s) + 循环次数为30时，SCL频率 = 440KHz， SCL高电平时间1.0us，SCL低电平时间1.2us + + 上拉电阻选择2.2K欧时，SCL上升沿时间约0.5us，如果选4.7K欧，则上升沿约1us + + 实际应用选择400KHz左右的速率即可 + */ + for (i = 0; i < 30; i++) + ; +} + +/* +********************************************************************************************************* +* 函 数 名: i2c_Start +* 功能说明: CPU发起I2C总线启动信号 +* 形 参: 无 +* 返 回 值: 无 +********************************************************************************************************* +*/ +void i2c_Start(void) +{ + /* 当SCL高电平时，SDA出现一个下跳沿表示I2C总线启动信号 */ + I2C_SDA_1(); + I2C_SCL_1(); + i2c_Delay(); + I2C_SDA_0(); + i2c_Delay(); + + I2C_SCL_0(); + i2c_Delay(); +} + +/* +********************************************************************************************************* +* 函 数 名: i2c_Start +* 功能说明: CPU发起I2C总线停止信号 +* 形 参: 无 +* 返 回 值: 无 +********************************************************************************************************* +*/ +void i2c_Stop(void) +{ + /* 当SCL高电平时，SDA出现一个上跳沿表示I2C总线停止信号 */ + I2C_SDA_0(); + I2C_SCL_1(); + i2c_Delay(); + I2C_SDA_1(); + i2c_Delay(); +} + +/* +********************************************************************************************************* +* 函 数 名: i2c_SendByte +* 功能说明: CPU向I2C总线设备发送8bit数据 +* 形 参: _ucByte ： 等待发送的字节 +* 返 回 值: 无 +********************************************************************************************************* +*/ +void i2c_SendByte(uint8_t _ucByte) +{ + uint8_t i; + + /* 先发送字节的高位bit7 */ + for (i = 0; i < 8; i++) + { + if (_ucByte & 0x80) + { + I2C_SDA_1(); + } + else + { + I2C_SDA_0(); + } + i2c_Delay(); + I2C_SCL_1(); + i2c_Delay(); + I2C_SCL_0(); + if (i == 7) + { + I2C_SDA_1(); // 释放总线 + } + _ucByte <<= 1; /* 左移一个bit */ + i2c_Delay(); + } +} + +/* +********************************************************************************************************* +* 函 数 名: i2c_ReadByte +* 功能说明: CPU从I2C总线设备读取8bit数据 +* 形 参: 无 +* 返 回 值: 读到的数据 +********************************************************************************************************* +*/ +uint8_t i2c_ReadByte(void) +{ + uint8_t i; + uint8_t value; + + /* 读到第1个bit为数据的bit7 */ + value = 0; + for (i = 0; i < 8; i++) + { + value <<= 1; + I2C_SCL_1(); + i2c_Delay(); + if (I2C_SDA_READ()) + { + value++; + } + I2C_SCL_0(); + i2c_Delay(); + } + return value; +} + +/* +********************************************************************************************************* +* 函 数 名: i2c_WaitAck +* 功能说明: CPU产生一个时钟，并读取器件的ACK应答信号 +* 形 参: 无 +* 返 回 值: 返回0表示正确应答，1表示无器件响应 +********************************************************************************************************* +*/ +uint8_t i2c_WaitAck(void) +{ + uint8_t re; + + I2C_SDA_1(); /* CPU释放SDA总线 */ + i2c_Delay(); + I2C_SCL_1(); /* CPU驱动SCL = 1, 此时器件会返回ACK应答 */ + i2c_Delay(); + if (I2C_SDA_READ()) /* CPU读取SDA口线状态 */ + { + re = 1; + } + else + { + re = 0; + } + I2C_SCL_0(); + i2c_Delay(); + return re; +} + +/* +********************************************************************************************************* +* 函 数 名: i2c_Ack +* 功能说明: CPU产生一个ACK信号 +* 形 参: 无 +* 返 回 值: 无 +********************************************************************************************************* +*/ +void i2c_Ack(void) +{ + I2C_SDA_0(); /* CPU驱动SDA = 0 */ + i2c_Delay(); + I2C_SCL_1(); /* CPU产生1个时钟 */ + i2c_Delay(); + I2C_SCL_0(); + i2c_Delay(); + I2C_SDA_1(); /* CPU释放SDA总线 */ +} + +/* +********************************************************************************************************* +* 函 数 名: i2c_NAck +* 功能说明: CPU产生1个NACK信号 +* 形 参: 无 +* 返 回 值: 无 +********************************************************************************************************* +*/ +void i2c_NAck(void) +{ + I2C_SDA_1(); /* CPU驱动SDA = 1 */ + i2c_Delay(); + I2C_SCL_1(); /* CPU产生1个时钟 */ + i2c_Delay(); + I2C_SCL_0(); + i2c_Delay(); +} + +/* +********************************************************************************************************* +* 函 数 名: i2c_CheckDevice +* 功能说明: 检测I2C总线设备，CPU向发送设备地址，然后读取设备应答来判断该设备是否存在 +* 形 参: _Address：设备的I2C总线地址 +* 返 回 值: 返回值 0 表示正确， 返回1表示未探测到 +********************************************************************************************************* +*/ +uint8_t i2c_CheckDevice(uint8_t _Address) +{ + uint8_t ucAck; + + if (I2C_SDA_READ() && I2C_SCL_READ()) + { + i2c_Start(); /* 发送启动信号 */ + + /* 发送设备地址+读写控制bit（0 = w， 1 = r) bit7 先传 */ + i2c_SendByte(_Address | I2C_WR); + ucAck = i2c_WaitAck(); /* 检测设备的ACK应答 */ + + i2c_Stop(); /* 发送停止信号 */ + + return ucAck; + } + return 1; /* I2C总线异常 */ +} + +/***************************** 安富莱电子 www.armfly.com (END OF FILE) *********************************/ diff --git a/User/bsp/src/bsp_key.c b/User/bsp/src/bsp_key.c new file mode 100644 index 0000000..5b1841d --- /dev/null +++ b/User/bsp/src/bsp_key.c @@ -0,0 +1,496 @@ +/* +********************************************************************************************************* +* +* 模块名称 : 独立按键驱动模块 +* 文件名称 : bsp_key.c +* 版 本 : V1.0 +* 说 明 : 扫描独立按键，具有软件滤波机制，具有按键FIFO。可以检测如下事件： +* (1) 按键按下 +* (2) 按键弹起 +* (3) 长按键 +* (4) 长按时自动连发 +* +* 修改记录 : +* 版本号 日期 作者 说明 +* V1.0 2013-02-01 armfly 正式发布 +* V1.1 2013-06-29 armfly 增加1个读指针，用于bsp_Idle() 函数读取系统控制组合键（截屏） +* 增加 K1 K2 组合键 和 K2 K3 组合键，用于系统控制 +* V1.2 2015-08-08 armfly K1，K2，K3独立按键进行排他判断，修改 IsKeyDown1()等函数 +* +* Copyright (C), 2015-2016, 安富莱电子 www.armfly.com +* +********************************************************************************************************* +*/ + +#include "bsp.h" + +/* + 该程序适用于安富莱STM32-V4开发板 + + 如果用于其它硬件，请修改GPIO定义和 IsKeyDown1 - IsKeyDown8 函数 + + 如果用户的按键个数小于8个，你可以将多余的按键全部定义为和第1个按键一样，并不影响程序功能 + #define KEY_COUNT 8 这个在 bsp_key.h 文件中定义 +*/ + +/* + 安富莱STM32-V4 按键口线分配： + K1 键 : PC13 (低电平表示按下) + K2 键 : PA0 ( --- 高电平表示按下) + K3 键 : PG8 (低电平表示按下) + 摇杆UP键 : PG15 (低电平表示按下) + 摇杆DOWN键 : PD3 (低电平表示按下) + 摇杆LEFT键 : PG14 (低电平表示按下) + 摇杆RIGHT键: PG13 (低电平表示按下) + 摇杆OK键 : PG7 (低电平表示按下) +*/ + +/* 按键口对应的RCC时钟 */ +#define RCC_ALL_KEY RCC_APB2Periph_GPIOE +#define RCC_ALL_KEY1 RCC_APB2Periph_GPIOA + +#define GPIO_PORT_K6 GPIOA +#define GPIO_PIN_K6 GPIO_Pin_3 + +#define GPIO_PORT_K1 GPIOE //(PE2) +#define GPIO_PIN_K1 GPIO_Pin_2 + +#define GPIO_PORT_K2 GPIOE //(PE3) +#define GPIO_PIN_K2 GPIO_Pin_3 + +static KEY_T s_tBtn[KEY_COUNT]; +static KEY_FIFO_T s_tKey; /* 按键FIFO变量,结构体 */ + +static void bsp_InitKeyVar(void); +static void bsp_InitKeyHard(void); +static void bsp_DetectKey(uint8_t i); + +/* +********************************************************************************************************* +* 函 数 名: IsKeyDownX +* 功能说明: 判断按键是否按下 +* 形 参: 无 +* 返 回 值: 返回值1 表示按下，0表示未按下 +********************************************************************************************************* +*/ +/* 安富莱 STM32-V4 开发板 */ +#if 0 /* 为了区分3个事件:　K1单独按下, K2单独按下， K1和K2同时按下 */ +static uint8_t IsKeyDown1(void) +{ + if ((GPIO_PORT_K1->IDR & GPIO_PIN_K1) == 0 && (GPIO_PORT_K2->IDR & GPIO_PIN_K2) == 0 + && (GPIO_PORT_K3->IDR & GPIO_PIN_K3) != 0) + return 1; + else + return 0; +} +static uint8_t IsKeyDown2(void) +{ + if ((GPIO_PORT_K1->IDR & GPIO_PIN_K1) != 0 && (GPIO_PORT_K2->IDR & GPIO_PIN_K2) != 0 + && (GPIO_PORT_K3->IDR & GPIO_PIN_K3) != 0) + return 1; + else + return 0; +} +static uint8_t IsKeyDown3(void) +{ + if ((GPIO_PORT_K1->IDR & GPIO_PIN_K1) != 0 && (GPIO_PORT_K2->IDR & GPIO_PIN_K2) == 0 + && (GPIO_PORT_K3->IDR & GPIO_PIN_K3) == 0) + return 1; + else + return 0; +} +static uint8_t IsKeyDown9(void) /* K1 K2组合键 */ +{ + if ((GPIO_PORT_K1->IDR & GPIO_PIN_K1) == 0 && (GPIO_PORT_K2->IDR & GPIO_PIN_K2) != 0 + && (GPIO_PORT_K3->IDR & GPIO_PIN_K3) != 0) + return 1; + else + return 0; +} +static uint8_t IsKeyDown10(void) /* K2 K3组合键 */ +{ + if ((GPIO_PORT_K1->IDR & GPIO_PIN_K1) != 0 && (GPIO_PORT_K2->IDR & GPIO_PIN_K2) != 0 + && (GPIO_PORT_K3->IDR & GPIO_PIN_K3) == 0) + return 1; + else + return 0; +} +#else +uint8_t IsKeyDown1(void) +{ + if ((GPIO_PORT_K6->IDR & GPIO_PIN_K6) == 0) + return 1; + else + return 0; +} // 复位键 +// 被main函数调用 +uint8_t IsKeyDown2(void) +{ + if ((GPIO_PORT_K1->IDR & GPIO_PIN_K1) == 0) + return 1; + else + return 0; +} // 模式切换键 +uint8_t IsKeyDown3(void) +{ + if ((GPIO_PORT_K2->IDR & GPIO_PIN_K2) == 0) + return 1; + else + return 0; +} // 模式切换键 +// static uint8_t IsKeyDown3(void) {if ((GPIO_PORT_K3->IDR & GPIO_PIN_K3) == 0) return 1;else return 0;} + +// static uint8_t IsKeyDown9(void) {if (IsKeyDown1() && IsKeyDown2()) return 1;else return 0;} /* K1 K2组合键 */ +// static uint8_t IsKeyDown10(void) {if (IsKeyDown2() && IsKeyDown3()) return 1;else return 0;} /* K2 K3组合键 */ +#endif + +/* 5方向摇杆 */ +// static uint8_t IsKeyDown4(void) {if ((GPIO_PORT_K4->IDR & GPIO_PIN_K4) == 0) return 1;else return 0;} +// static uint8_t IsKeyDown5(void) {if ((GPIO_PORT_K5->IDR & GPIO_PIN_K5) == 0) return 1;else return 0;} +// static uint8_t IsKeyDown6(void) {if ((GPIO_PORT_K6->IDR & GPIO_PIN_K6) == 0) return 1;else return 0;} +// static uint8_t IsKeyDown7(void) {if ((GPIO_PORT_K7->IDR & GPIO_PIN_K7) == 0) return 1;else return 0;} +// static uint8_t IsKeyDown8(void) {if ((GPIO_PORT_K8->IDR & GPIO_PIN_K8) == 0) return 1;else return 0;} + +/* +********************************************************************************************************* +* 函 数 名: bsp_InitKey +* 功能说明: 初始化按键. 该函数被 bsp_Init() 调用。 +* 形 参: 无 +* 返 回 值: 无 +********************************************************************************************************* +*/ +void bsp_InitKey(void) +{ + bsp_InitKeyVar(); /* 初始化按键变量 */ + bsp_InitKeyHard(); /* 初始化按键硬件 */ +} + +/* +********************************************************************************************************* +* 函 数 名: bsp_PutKey +* 功能说明: 将1个键值压入按键FIFO缓冲区。可用于模拟一个按键。 +* 形 参: _KeyCode : 按键代码 +* 返 回 值: 无 +********************************************************************************************************* +*/ +void bsp_PutKey(uint8_t _KeyCode) +{ + s_tKey.Buf[s_tKey.Write] = _KeyCode; + + if (++s_tKey.Write >= KEY_FIFO_SIZE) + { + s_tKey.Write = 0; + } +} + +/* +********************************************************************************************************* +* 函 数 名: bsp_GetKey +* 功能说明: 从按键FIFO缓冲区读取一个键值。 +* 形 参: 无 +* 返 回 值: 按键代码 +********************************************************************************************************* +*/ +uint8_t bsp_GetKey(void) +{ + uint8_t ret; + + if (s_tKey.Read == s_tKey.Write) + { + return KEY_NONE; + } + else + { + ret = s_tKey.Buf[s_tKey.Read]; + + if (++s_tKey.Read >= KEY_FIFO_SIZE) + { + s_tKey.Read = 0; + } + return ret; + } +} + +/* +********************************************************************************************************* +* 函 数 名: bsp_GetKey2 +* 功能说明: 从按键FIFO缓冲区读取一个键值。独立的读指针。 +* 形 参: 无 +* 返 回 值: 按键代码 +********************************************************************************************************* +*/ +uint8_t bsp_GetKey2(void) +{ + uint8_t ret; + + if (s_tKey.Read2 == s_tKey.Write) + { + return KEY_NONE; + } + else + { + ret = s_tKey.Buf[s_tKey.Read2]; + + if (++s_tKey.Read2 >= KEY_FIFO_SIZE) + { + s_tKey.Read2 = 0; + } + return ret; + } +} + +/* +********************************************************************************************************* +* 函 数 名: bsp_GetKeyState +* 功能说明: 读取按键的状态 +* 形 参: _ucKeyID : 按键ID，从0开始 +* 返 回 值: 1 表示按下， 0 表示未按下 +********************************************************************************************************* +*/ +uint8_t bsp_GetKeyState(KEY_ID_E _ucKeyID) +{ + return s_tBtn[_ucKeyID].State; +} + +/* +********************************************************************************************************* +* 函 数 名: bsp_SetKeyParam +* 功能说明: 设置按键参数 +* 形 参：_ucKeyID : 按键ID，从0开始 +* _LongTime : 长按事件时间 +* _RepeatSpeed : 连发速度 +* 返 回 值: 无 +********************************************************************************************************* +*/ +void bsp_SetKeyParam(uint8_t _ucKeyID, uint16_t _LongTime, uint8_t _RepeatSpeed) +{ + s_tBtn[_ucKeyID].LongTime = _LongTime; /* 长按时间 0 表示不检测长按键事件 */ + s_tBtn[_ucKeyID].RepeatSpeed = _RepeatSpeed; /* 按键连发的速度，0表示不支持连发 */ + s_tBtn[_ucKeyID].RepeatCount = 0; /* 连发计数器 */ +} + +/* +********************************************************************************************************* +* 函 数 名: bsp_ClearKey +* 功能说明: 清空按键FIFO缓冲区 +* 形 参：无 +* 返 回 值: 按键代码 +********************************************************************************************************* +*/ +void bsp_ClearKey(void) +{ + s_tKey.Read = s_tKey.Write; +} + +/* +********************************************************************************************************* +* 函 数 名: bsp_InitKeyHard +* 功能说明: 配置按键对应的GPIO +* 形 参: 无 +* 返 回 值: 无 +********************************************************************************************************* +*/ +static void bsp_InitKeyHard(void) +{ + GPIO_InitTypeDef GPIO_InitStructure; + + /* 第1步：打开GPIO时钟 */ + RCC_APB2PeriphClockCmd(RCC_ALL_KEY | RCC_ALL_KEY1, ENABLE); + + /* 第2步：配置所有的按键GPIO为浮动输入模式(实际上CPU复位后就是输入状态) */ + GPIO_InitStructure.GPIO_Speed = GPIO_Speed_50MHz; + GPIO_InitStructure.GPIO_Mode = GPIO_Mode_IN_FLOATING; /* 输入浮空模式 */ + + GPIO_InitStructure.GPIO_Pin = GPIO_PIN_K1; + GPIO_Init(GPIO_PORT_K1, &GPIO_InitStructure); + + GPIO_InitStructure.GPIO_Pin = GPIO_PIN_K2; + GPIO_Init(GPIO_PORT_K2, &GPIO_InitStructure); + + GPIO_InitStructure.GPIO_Pin = GPIO_PIN_K6; + GPIO_Init(GPIO_PORT_K6, &GPIO_InitStructure); + + // GPIO_InitStructure.GPIO_Pin = GPIO_PIN_K3; + // GPIO_Init(GPIO_PORT_K3, &GPIO_InitStructure); + // + // GPIO_InitStructure.GPIO_Pin = GPIO_PIN_K4; + // GPIO_Init(GPIO_PORT_K4, &GPIO_InitStructure); + // + // GPIO_InitStructure.GPIO_Pin = GPIO_PIN_K5; + // GPIO_Init(GPIO_PORT_K5, &GPIO_InitStructure); + // + // GPIO_InitStructure.GPIO_Pin = GPIO_PIN_K6; + // GPIO_Init(GPIO_PORT_K6, &GPIO_InitStructure); + // + // GPIO_InitStructure.GPIO_Pin = GPIO_PIN_K7; + // GPIO_Init(GPIO_PORT_K7, &GPIO_InitStructure); + // + // GPIO_InitStructure.GPIO_Pin = GPIO_PIN_K8; + // GPIO_Init(GPIO_PORT_K8, &GPIO_InitStructure); +} + +/* +********************************************************************************************************* +* 函 数 名: bsp_InitKeyVar +* 功能说明: 初始化按键变量 +* 形 参: 无 +* 返 回 值: 无 +********************************************************************************************************* +*/ +static void bsp_InitKeyVar(void) +{ + uint8_t i; + + /* 对按键FIFO读写指针清零 */ + s_tKey.Read = 0; + s_tKey.Write = 0; + s_tKey.Read2 = 0; + + /* 给每个按键结构体成员变量赋一组缺省值 */ + for (i = 0; i < KEY_COUNT; i++) + { + s_tBtn[i].LongTime = KEY_LONG_TIME; /* 长按时间 0 表示不检测长按键事件 */ + s_tBtn[i].Count = KEY_FILTER_TIME / 2; /* 计数器设置为滤波时间的一半 */ + s_tBtn[i].State = 0; /* 按键缺省状态，0为未按下 */ + // s_tBtn[i].KeyCodeDown = 3 * i + 1; /* 按键按下的键值代码 */ + // s_tBtn[i].KeyCodeUp = 3 * i + 2; /* 按键弹起的键值代码 */ + // s_tBtn[i].KeyCodeLong = 3 * i + 3; /* 按键被持续按下的键值代码 */ + s_tBtn[i].RepeatSpeed = 0; /* 按键连发的速度，0表示不支持连发 */ + s_tBtn[i].RepeatCount = 0; /* 连发计数器 */ + } + + /* 如果需要单独更改某个按键的参数，可以在此单独重新赋值 */ + /* 比如，我们希望按键1按下超过1秒后，自动重发相同键值 */ + // s_tBtn[KID_K7].LongTime = 40; + // s_tBtn[KID_K7].RepeatSpeed = 5; /* 每隔50ms自动发送键值 */ + // + // s_tBtn[KID_K8].LongTime = 40; + // s_tBtn[KID_K8].RepeatSpeed = 5; /* 每隔50ms自动发送键值 */ + + /* 判断按键按下的函数 */ + s_tBtn[0].IsKeyDownFunc = IsKeyDown1; + s_tBtn[1].IsKeyDownFunc = IsKeyDown2; + s_tBtn[2].IsKeyDownFunc = IsKeyDown3; + // s_tBtn[3].IsKeyDownFunc = IsKeyDown4; + // s_tBtn[4].IsKeyDownFunc = IsKeyDown5; + // s_tBtn[5].IsKeyDownFunc = IsKeyDown6; + // s_tBtn[6].IsKeyDownFunc = IsKeyDown7;// shen 0809 + // s_tBtn[7].IsKeyDownFunc = IsKeyDown8; + + /* 组合键 */ + // s_tBtn[8].IsKeyDownFunc = IsKeyDown9; + // s_tBtn[9].IsKeyDownFunc = IsKeyDown10; +} + +/* +********************************************************************************************************* +* 函 数 名: bsp_DetectKey +* 功能说明: 检测一个按键。非阻塞状态，必须被周期性的调用。 +* 形 参: 按键结构变量指针 +* 返 回 值: 无 +********************************************************************************************************* +*/ +static void bsp_DetectKey(uint8_t i) +{ + KEY_T *pBtn; + + /* + 如果没有初始化按键函数，则报错 + if (s_tBtn[i].IsKeyDownFunc == 0) + { + printf("Fault : DetectButton(), s_tBtn[i].IsKeyDownFunc undefine"); + } + */ + + pBtn = &s_tBtn[i]; + if (pBtn->IsKeyDownFunc()) + { + if (pBtn->Count < KEY_FILTER_TIME) + { + pBtn->Count = KEY_FILTER_TIME; + } + else if (pBtn->Count < 2 * KEY_FILTER_TIME) + { + pBtn->Count++; + } + else + { + if (pBtn->State == 0) + { + pBtn->State = 1; + + /* 发送按钮按下的消息 */ + bsp_PutKey((uint8_t)(3 * i + 1)); + } + + if (pBtn->LongTime > 0) + { + if (pBtn->LongCount < pBtn->LongTime) + { + /* 发送按钮持续按下的消息 */ + if (++pBtn->LongCount == pBtn->LongTime) + { + /* 键值放入按键FIFO */ + bsp_PutKey((uint8_t)(3 * i + 3)); + } + } + else + { + if (pBtn->RepeatSpeed > 0) + { + if (++pBtn->RepeatCount >= pBtn->RepeatSpeed) + { + pBtn->RepeatCount = 0; + /* 常按键后，每隔10ms发送1个按键 */ + bsp_PutKey((uint8_t)(3 * i + 1)); + } + } + } + } + } + } + else + { + if (pBtn->Count > KEY_FILTER_TIME) + { + pBtn->Count = KEY_FILTER_TIME; + } + else if (pBtn->Count != 0) + { + pBtn->Count--; + } + else + { + if (pBtn->State == 1) + { + pBtn->State = 0; + + /* 发送按钮弹起的消息 */ + bsp_PutKey((uint8_t)(3 * i + 2)); + } + } + + pBtn->LongCount = 0; + pBtn->RepeatCount = 0; + } +} + +/* +********************************************************************************************************* +* 函 数 名: bsp_KeyScan +* 功能说明: 扫描所有按键。非阻塞，被systick中断周期性的调用 +* 形 参: 无 +* 返 回 值: 无 +********************************************************************************************************* +*/ +void bsp_KeyScan(void) +{ + uint8_t i; + + for (i = 0; i < KEY_COUNT; i++) + { + bsp_DetectKey(i); + } +} + +/***************************** 安富莱电子 www.armfly.com (END OF FILE) *********************************/ diff --git a/User/bsp/src/bsp_led.c b/User/bsp/src/bsp_led.c new file mode 100644 index 0000000..81baf92 --- /dev/null +++ b/User/bsp/src/bsp_led.c @@ -0,0 +1,445 @@ +/* +********************************************************************************************************* +* +* ģ : LEDָʾģ +* ļ : bsp_led.c +* : V1.0 +* ˵ : LEDָʾ +* +* ޸ļ¼ : +* 汾 ˵ +* V1.0 2013-02-01 armfly ʽ +* +* Copyright (C), 2013-2014, www.armfly.com +* +********************************************************************************************************* +*/ + +#include "bsp.h" + +/* + óڰSTM32-V4 + + Ӳ޸GPIO + + ûLEDָʾƸС4ԽLEDȫΪ͵1LEDһӰ +*/ + + +/* ڶӦRCCʱ */ +#define RCC_ALL_LED (RCC_APB2Periph_GPIOA | RCC_APB2Periph_GPIOC | RCC_APB2Periph_GPIOD | RCC_APB2Periph_GPIOE | RCC_APB2Periph_GPIOF) + +#define GPIO_PORT_LED1 GPIOA +#define GPIO_PIN_LED1 GPIO_Pin_15 + +#define GPIO_PORT_LED2 GPIOC +#define GPIO_PIN_LED2 GPIO_Pin_10 + +#define GPIO_PORT_LED3 GPIOC +#define GPIO_PIN_LED3 GPIO_Pin_11 + +#define GPIO_PORT_LED4 GPIOC +#define GPIO_PIN_LED4 GPIO_Pin_12 + +#define GPIO_PORT_LED5 GPIOD +#define GPIO_PIN_LED5 GPIO_Pin_0 + +#define GPIO_PORT_LED6 GPIOD +#define GPIO_PIN_LED6 GPIO_Pin_1 + +#define GPIO_PORT_LED7 GPIOF +#define GPIO_PIN_LED7 GPIO_Pin_5 + +#define GPIO_PORT_LED8 GPIOF +#define GPIO_PIN_LED8 GPIO_Pin_4 + +#define GPIO_PORT_LED9 GPIOF +#define GPIO_PIN_LED9 GPIO_Pin_3 + +#define GPIO_PORT_LED10 GPIOF +#define GPIO_PIN_LED10 GPIO_Pin_2 + +#define GPIO_PORT_LED11 GPIOF +#define GPIO_PIN_LED11 GPIO_Pin_1 + +#define GPIO_PORT_LED12 GPIOF +#define GPIO_PIN_LED12 GPIO_Pin_0 + +#define GPIO_PORT_LED13 GPIOE +#define GPIO_PIN_LED13 GPIO_Pin_5 + +#define GPIO_PORT_LED14 GPIOE +#define GPIO_PIN_LED14 GPIO_Pin_4 + +/* +********************************************************************************************************* +* : bsp_InitLed +* ˵: LEDָʾصGPIO, ú bsp_Init() á +* : +* ֵ: +********************************************************************************************************* +*/ +void bsp_InitLed(void) +{ + GPIO_InitTypeDef GPIO_InitStructure; + + /* GPIOʱ */ + RCC_APB2PeriphClockCmd(RCC_ALL_LED, ENABLE); + + /* + еLEDָʾGPIOΪģʽ + ڽGPIOΪʱGPIOĴֵȱʡ0˻LED. + ҲϣģڸıGPIOΪǰȹرLEDָʾ + */ + bsp_LedOff(1); + bsp_LedOff(2); + bsp_LedOff(3); + bsp_LedOff(4); + bsp_LedOff(5); + bsp_LedOff(6); + bsp_LedOn(7); + bsp_LedOff(8); + bsp_LedOff(9); + bsp_LedOff(10); + bsp_LedOff(11); + bsp_LedOff(12); + bsp_LedOff(13); + bsp_LedOff(14); + + GPIO_InitStructure.GPIO_Speed = GPIO_Speed_50MHz; + GPIO_InitStructure.GPIO_Mode = GPIO_Mode_Out_PP; /* ģʽ */ + + RCC_APB2PeriphClockCmd(RCC_APB2Periph_GPIOA|RCC_APB2Periph_AFIO, ENABLE); + GPIO_PinRemapConfig(GPIO_Remap_SWJ_JTAGDisable, ENABLE); + + GPIO_InitStructure.GPIO_Pin = GPIO_PIN_LED1; + GPIO_Init(GPIO_PORT_LED1, &GPIO_InitStructure); + + GPIO_InitStructure.GPIO_Pin = GPIO_PIN_LED2; + GPIO_Init(GPIO_PORT_LED2, &GPIO_InitStructure); + + GPIO_InitStructure.GPIO_Pin = GPIO_PIN_LED3; + GPIO_Init(GPIO_PORT_LED3, &GPIO_InitStructure); + + GPIO_InitStructure.GPIO_Pin = GPIO_PIN_LED4; + GPIO_Init(GPIO_PORT_LED4, &GPIO_InitStructure); + + GPIO_InitStructure.GPIO_Pin = GPIO_PIN_LED5; + GPIO_Init(GPIO_PORT_LED5, &GPIO_InitStructure); + + GPIO_InitStructure.GPIO_Pin = GPIO_PIN_LED6; + GPIO_Init(GPIO_PORT_LED6, &GPIO_InitStructure); + + GPIO_InitStructure.GPIO_Pin = GPIO_PIN_LED7; + GPIO_Init(GPIO_PORT_LED7, &GPIO_InitStructure); + + GPIO_InitStructure.GPIO_Pin = GPIO_PIN_LED8; + GPIO_Init(GPIO_PORT_LED8, &GPIO_InitStructure); + + GPIO_InitStructure.GPIO_Pin = GPIO_PIN_LED9; + GPIO_Init(GPIO_PORT_LED9, &GPIO_InitStructure); + + GPIO_InitStructure.GPIO_Pin = GPIO_PIN_LED10; + GPIO_Init(GPIO_PORT_LED10, &GPIO_InitStructure); + + GPIO_InitStructure.GPIO_Pin = GPIO_PIN_LED11; + GPIO_Init(GPIO_PORT_LED11, &GPIO_InitStructure); + + GPIO_InitStructure.GPIO_Pin = GPIO_PIN_LED12; + GPIO_Init(GPIO_PORT_LED12, &GPIO_InitStructure); + + GPIO_InitStructure.GPIO_Pin = GPIO_PIN_LED13; + GPIO_Init(GPIO_PORT_LED13, &GPIO_InitStructure); + + GPIO_InitStructure.GPIO_Pin = GPIO_PIN_LED14; + GPIO_Init(GPIO_PORT_LED14, &GPIO_InitStructure); + +} + +/* +********************************************************************************************************* +* : bsp_LedOn +* ˵: ָLEDָʾơ +* : _no : ָʾţΧ 1 - 4 +* ֵ: +********************************************************************************************************* +*/ +void bsp_LedOff(uint8_t _no) +{ + _no--; + + if (_no == 0) + { + GPIO_PORT_LED1->BRR = GPIO_PIN_LED1; + } + else if (_no == 1) + { + GPIO_PORT_LED2->BRR = GPIO_PIN_LED2; + } + else if (_no == 2) + { + GPIO_PORT_LED3->BRR = GPIO_PIN_LED3; + } + else if (_no == 3) + { + GPIO_PORT_LED4->BRR = GPIO_PIN_LED4; + } + else if (_no == 4) + { + GPIO_PORT_LED5->BRR = GPIO_PIN_LED5; + } + else if (_no == 5) + { + GPIO_PORT_LED6->BRR = GPIO_PIN_LED6; + } + else if (_no == 6) + { + GPIO_PORT_LED7->BRR = GPIO_PIN_LED7; + } + else if (_no == 7) + { + GPIO_PORT_LED8->BRR = GPIO_PIN_LED8; + } + else if (_no == 8) + { + GPIO_PORT_LED9->BRR = GPIO_PIN_LED9; + } + else if (_no == 9) + { + GPIO_PORT_LED10->BRR = GPIO_PIN_LED10; + } + else if (_no == 10) + { + GPIO_PORT_LED11->BRR = GPIO_PIN_LED11; + } + else if (_no == 11) + { + GPIO_PORT_LED12->BRR = GPIO_PIN_LED12; + } + else if (_no == 12) + { + GPIO_PORT_LED13->BRR = GPIO_PIN_LED13; + } + else if (_no == 13) + { + GPIO_PORT_LED14->BRR = GPIO_PIN_LED14; + } +} + +/* +********************************************************************************************************* +* : bsp_LedOff +* ˵: ϨָLEDָʾơ +* : _no : ָʾţΧ 1 - 4 +* ֵ: +********************************************************************************************************* +*/ +void bsp_LedOn(uint8_t _no) +{ + _no--; + + if (_no == 0) + { + GPIO_PORT_LED1->BSRR = GPIO_PIN_LED1; + } + else if (_no == 1) + { + GPIO_PORT_LED2->BSRR = GPIO_PIN_LED2; + } + else if (_no == 2) + { + GPIO_PORT_LED3->BSRR = GPIO_PIN_LED3; + } + else if (_no == 3) + { + GPIO_PORT_LED4->BSRR = GPIO_PIN_LED4; + } + else if (_no == 4) + { + GPIO_PORT_LED5->BSRR = GPIO_PIN_LED5; + } + else if (_no == 5) + { + GPIO_PORT_LED6->BSRR = GPIO_PIN_LED6; + } + else if (_no == 6) + { + GPIO_PORT_LED7->BSRR = GPIO_PIN_LED7; + } + else if (_no == 7) + { + GPIO_PORT_LED8->BSRR = GPIO_PIN_LED8; + } + else if (_no == 8) + { + GPIO_PORT_LED9->BSRR = GPIO_PIN_LED9; + } + else if (_no == 9) + { + GPIO_PORT_LED10->BSRR = GPIO_PIN_LED10; + } + else if (_no == 10) + { + GPIO_PORT_LED11->BSRR = GPIO_PIN_LED11; + } + else if (_no == 11) + { + GPIO_PORT_LED12->BSRR = GPIO_PIN_LED12; + } + else if (_no == 12) + { + GPIO_PORT_LED13->BSRR = GPIO_PIN_LED13; + } + else if (_no == 13) + { + GPIO_PORT_LED14->BSRR = GPIO_PIN_LED14; + } + +} + +/* +********************************************************************************************************* +* : bsp_LedToggle +* ˵: תָLEDָʾơ +* : _no : ָʾţΧ 1 - 4 +* ֵ: +********************************************************************************************************* +*/ +void bsp_LedToggle(uint8_t _no) +{ + if (_no == 1) + { + GPIO_PORT_LED1->ODR ^= GPIO_PIN_LED1; + } + else if (_no == 2) + { + GPIO_PORT_LED2->ODR ^= GPIO_PIN_LED2; + } + else if (_no == 3) + { + GPIO_PORT_LED3->ODR ^= GPIO_PIN_LED3; + } + else if (_no == 4) + { + GPIO_PORT_LED4->ODR ^= GPIO_PIN_LED4; + } +} + +/* +********************************************************************************************************* +* : bsp_IsLedOn +* ˵: жLEDָʾǷѾ +* : _no : ָʾţΧ 1 - 4 +* ֵ: 1ʾѾ0ʾδ +********************************************************************************************************* +*/ +uint8_t bsp_IsLedOn(uint8_t _no) +{ + if (_no == 1) + { + if ((GPIO_PORT_LED1->ODR & GPIO_PIN_LED1) == 0) + { + return 1; + } + return 0; + } + else if (_no == 2) + { + if ((GPIO_PORT_LED2->ODR & GPIO_PIN_LED2) == 0) + { + return 1; + } + return 0; + } + else if (_no == 3) + { + if ((GPIO_PORT_LED3->ODR & GPIO_PIN_LED3) == 0) + { + return 1; + } + return 0; + } + else if (_no == 4) + { + if ((GPIO_PORT_LED4->ODR & GPIO_PIN_LED4) == 0) + { + return 1; + } + return 0; + } + + return 0; +} + +void bsp_LedAllOff(void) +{ + bsp_LedOff(1); + bsp_LedOff(2); + bsp_LedOff(3); + bsp_LedOff(4); + bsp_LedOff(5); + bsp_LedOff(6); + bsp_LedOff(7); + bsp_LedOff(8); + bsp_LedOff(9); + bsp_LedOff(10); + bsp_LedOff(11); + bsp_LedOff(12); + bsp_LedOff(13); + bsp_LedOff(14); +} + +static void ChannelLedAllOff(void) +{ + bsp_LedOff(1); + bsp_LedOff(2); + bsp_LedOff(3); + bsp_LedOff(4); + bsp_LedOff(5); + bsp_LedOff(6); +} + +static void ResLedAllOff(void) +{ + bsp_LedOff(7); + bsp_LedOff(8); + bsp_LedOff(9); + bsp_LedOff(10); + bsp_LedOff(11); + bsp_LedOff(12); + bsp_LedOff(13); + bsp_LedOff(14); +} + +//---------------------------------------- +// ch = 1,2,3,4,5,6 +//--------------------------------------- +void bsp_ChannelSelect(uint8_t _ch) +{ + static uint8_t s_ucOldCh=255; + + if(_ch==s_ucOldCh) + { + ChannelLedAllOff(); + bsp_RealyAllOff(); + s_ucOldCh=255; + } + else + { + s_ucOldCh = _ch; + ChannelLedAllOff(); + bsp_LedOn(_ch); + bsp_RelayOn(_ch); + } + +} + +void bsp_ResSelect(uint8_t _res) +{ + ResLedAllOff(); + //printf("_res:%d\r\n",_res); + bsp_LedOn(_res); + bsp_SelectRes(_res); +} + +/***************************** www.armfly.com (END OF FILE) *********************************/ diff --git a/User/bsp/src/bsp_res.c b/User/bsp/src/bsp_res.c new file mode 100644 index 0000000..544d37d --- /dev/null +++ b/User/bsp/src/bsp_res.c @@ -0,0 +1,162 @@ +//------------------------------------------------------------------------------ +// ģƣѹλƿģ +// ļƣbsp_res.c +// 汾ƣV1.0 +// ļ˵IOѡⲿĴС +// ʱ䣺2018881514 +// ļߣJackie Chan +// ޸ļ¼ +// 汾 ˵ +// V1.0 2018.08.08 J.C ʽ +// +// ˾ƣೡ¿Ƽ޹˾ +// +//------------------------------------------------------------------------------ + +#include "bsp.h" + +// ƴڶӦRCCʱ +#define RCC_ALL_RES (RCC_APB2Periph_GPIOB | RCC_APB2Periph_GPIOC) + +#define GPIO_PORT_RES10 GPIOC +#define GPIO_PIN_RES10 GPIO_Pin_4 + +#define GPIO_PORT_RES51_1 GPIOC +#define GPIO_PIN_RES51_1 GPIO_Pin_5 + +#define GPIO_PORT_RES51_2 GPIOB +#define GPIO_PIN_RES51_2 GPIO_Pin_0 + +#define GPIO_PORT_RES100 GPIOB +#define GPIO_PIN_RES100 GPIO_Pin_1 + + +//------------------------------------------------------------------------------ +// : bsp_InitRes +// ˵: ôصGPIO, ú bsp_Init() á +// : +// ֵ: +//------------------------------------------------------------------------------ +void bsp_InitRes(void) +{ + GPIO_InitTypeDef GPIO_InitStructure; + + // GPIOʱ + RCC_APB2PeriphClockCmd(RCC_ALL_RES, ENABLE); + + GPIO_InitStructure.GPIO_Speed = GPIO_Speed_50MHz; + GPIO_InitStructure.GPIO_Mode = GPIO_Mode_Out_PP; /* ģʽ */ + + GPIO_InitStructure.GPIO_Pin = GPIO_PIN_RES10; + GPIO_Init(GPIO_PORT_RES10, &GPIO_InitStructure); + + GPIO_InitStructure.GPIO_Pin = GPIO_PIN_RES51_1; + GPIO_Init(GPIO_PORT_RES51_1, &GPIO_InitStructure); + + GPIO_InitStructure.GPIO_Pin = GPIO_PIN_RES51_2; + GPIO_Init(GPIO_PORT_RES51_2, &GPIO_InitStructure); + + GPIO_InitStructure.GPIO_Pin = GPIO_PIN_RES100; + GPIO_Init(GPIO_PORT_RES100, &GPIO_InitStructure); +} + +//------------------------------------------------------------------------------ +// : bsp_Port10_Output +// ˵: ָĵƶ˿ڡ +// : _status : ƶ˿״̬01 +// ֵ: +//------------------------------------------------------------------------------ +void bsp_Port10_Output(uint8_t _status) +{ + if(_status==0) + { + GPIO_PORT_RES10->BRR = GPIO_PIN_RES10; + } + else if(_status==1) + { + GPIO_PORT_RES10->BSRR = GPIO_PIN_RES10; + } +} +//------------------------------------------------------------------------------ +// : bsp_Port51_1_Output +// ˵: ָĵƶ˿ڡ +// : _status : ƶ˿״̬01 +// ֵ: +//------------------------------------------------------------------------------ +void bsp_Port51_1_Output(uint8_t _status) +{ + if(_status==0) + { + GPIO_PORT_RES51_1->BRR = GPIO_PIN_RES51_1; + } + else if(_status==1) + { + GPIO_PORT_RES51_1->BSRR = GPIO_PIN_RES51_1; + } +} +//------------------------------------------------------------------------------ +// : bsp_Port51_2_Output +// ˵: ָĵƶ˿ڡ +// : _status : ƶ˿״̬01 +// ֵ: +//------------------------------------------------------------------------------ +void bsp_Port51_2_Output(uint8_t _status) +{ + if(_status==0) + { + GPIO_PORT_RES51_2->BRR = GPIO_PIN_RES51_2; + } + else if(_status==1) + { + GPIO_PORT_RES51_2->BSRR = GPIO_PIN_RES51_2; + } +} +//------------------------------------------------------------------------------ +// : bsp_Port100_Output +// ˵: ָĵƶ˿ڡ +// : _status : ƶ˿״̬01 +// ֵ: +//------------------------------------------------------------------------------ +void bsp_Port100_Output(uint8_t _status) +{ + if(_status==0) + { + GPIO_PORT_RES100->BRR = GPIO_PIN_RES100; + } + else if(_status==1) + { + GPIO_PORT_RES100->BSRR = GPIO_PIN_RES100; + } +} + +//------------------------------------------------------------------------------ +// : bsp_SelectRes +// ˵: ָĵƶ˿ϡ +// : _res : ƶ˿״̬7~14 +// ֵ: +//------------------------------------------------------------------------------ +void bsp_SelectRes(uint8_t _res) +{ + switch(_res) + { + case RES_0: + bsp_Port10_Output(0);bsp_Port51_1_Output(0);bsp_Port51_2_Output(0);bsp_Port100_Output(0); break; + case RES_10: + bsp_Port10_Output(1);bsp_Port51_1_Output(0);bsp_Port51_2_Output(0);bsp_Port100_Output(0); break; + case RES_61: + bsp_Port10_Output(1);bsp_Port51_1_Output(1);bsp_Port51_2_Output(0);bsp_Port100_Output(0); break; + case RES_100: + bsp_Port10_Output(0);bsp_Port51_1_Output(0);bsp_Port51_2_Output(0);bsp_Port100_Output(1); break; + case RES_110: + bsp_Port10_Output(1);bsp_Port51_1_Output(0);bsp_Port51_2_Output(0);bsp_Port100_Output(1); break; + case RES_151: + bsp_Port10_Output(0);bsp_Port51_1_Output(1);bsp_Port51_2_Output(0);bsp_Port100_Output(1); break; + case RES_202: + bsp_Port10_Output(0);bsp_Port51_1_Output(1);bsp_Port51_2_Output(1);bsp_Port100_Output(1); break; + case RES_212: + bsp_Port10_Output(1);bsp_Port51_1_Output(1);bsp_Port51_2_Output(1);bsp_Port100_Output(1); break; + default: break; + } +} + +//-------------------------------- End of file --------------------------------- diff --git a/User/bsp/src/bsp_step_moto.c b/User/bsp/src/bsp_step_moto.c new file mode 100644 index 0000000..a1a10a7 --- /dev/null +++ b/User/bsp/src/bsp_step_moto.c @@ -0,0 +1,250 @@ +//------------------------------------------------------------------------------ +// 模块名称：步进电机脉冲驱动模块 +// 文件名称：bsp_step_moto +// 版本名称：V1.0 +// 文件说明：控制电机转动脉冲输出文件 +// 日期时间：2018年8月23日20点37分 +// 文件作者：Jackie Chan +// 修改记录： +// 版本号 日期 作者 说明 +// V1.0 2018.08.23 J.C 正式发布 +// +// 公司名称：多场低温科技有限公司 +// +//------------------------------------------------------------------------------ + +#include "bsp.h" + +// 定义GPIO端口 +#define GPIO_PORT_STEP GPIOC // 脉冲输入，内部下拉，上升沿触发 +#define GPIO_PIN_STEP GPIO_Pin_7 +#define MOTO_STEP_0() GPIO_PORT_STEP->BRR = GPIO_PIN_STEP +#define MOTO_STEP_1() GPIO_PORT_STEP->BSRR = GPIO_PIN_STEP + +// PA6 零位信号输出引脚 +#define GPIO_PORT_ZERO_SIG GPIOA +#define GPIO_PIN_ZERO_SIG GPIO_Pin_6 +#define ZERO_SIG_TOGGLE() (GPIO_PORT_ZERO_SIG->ODR ^= GPIO_PIN_ZERO_SIG) + +extern DIGITIAL_TUBE_T g_tTube; +MOTO_T g_tMoto; + +//------------------------------------------------------------------------------ +// 函 数 名: bsp_InitStepMoto +// 功能说明: 配置步进电器驱动IO +// 形 参: 无 +// 返 回 值: 无 +//------------------------------------------------------------------------------ +void bsp_InitStepMoto(void) +{ + GPIO_InitTypeDef GPIO_InitStructure; + + // 初始化 PA6 为零位信号输出引脚 + RCC_APB2PeriphClockCmd(RCC_APB2Periph_GPIOA, ENABLE); + GPIO_InitStructure.GPIO_Pin = GPIO_PIN_ZERO_SIG; + GPIO_InitStructure.GPIO_Mode = GPIO_Mode_Out_PP; + GPIO_InitStructure.GPIO_Speed = GPIO_Speed_50MHz; + GPIO_Init(GPIO_PORT_ZERO_SIG, &GPIO_InitStructure); + GPIO_PORT_ZERO_SIG->BRR = GPIO_PIN_ZERO_SIG; // 默认输出低电平 + + g_tMoto.Dir = 0; + g_tMoto.StepFreq = 0; + g_tMoto.StepCount = 0; + g_tMoto.Running = 0; + g_tMoto.Pos = 0; + g_tMoto.pv_pulse = 0; + g_tMoto.sv_pulse = 0; + g_tMoto.prev_pv_pulse = 0; +} + +//------------------------------------------------------------------------------ +// 函 数 名: MOTO_StartWork +// 功能说明: 控制电机开始旋转 +// 形 参: _speed 旋转速度. 换相的频率。Hz +// _dir 旋转方向 0 表示正转， 1表示反转 +// _step 旋转步数 0 表示一直旋转 +// 返 回 值: 无 +//------------------------------------------------------------------------------ +void MOTO_Start(uint32_t _speed, uint8_t _dir, int32_t _stpes) +{ + bsp_drv8880_enable_config(ENABLE); + g_tMoto.Dir = _dir; + g_tMoto.StepFreq = _speed; + g_tMoto.StepCount = _stpes; + g_tMoto.AllStep = _stpes; + g_tMoto.CurrentStep = 0; + g_tMoto.Running = 1; + + // void bsp_SetTIMforInt(TIM_TypeDef* TIMx, uint32_t _ulFreq, uint8_t _PreemptionPriority, uint8_t _SubPriority) + // bsp_SetTIMforInt(TIM6, _speed*2, 2, 2); + switch (_dir) + { + case 1: + bsp_drv8880_config_dir(DIR_CW); + break; + case 0: + bsp_drv8880_config_dir(DIR_CCW); + break; + default: + break; + } + bsp_SetTIMforInt(TIM6, _speed * 2, 0, 0); +} + +//------------------------------------------------------------------------------ +// 函 数 名: MOTO_ShangeSpeed +// 功能说明: 控制电机的步进速度 +// 形 参: _speed 旋转速度. 换相的频率。Hz +// _dir 旋转方向 0 表示正转， 1表示反转 +// _step 旋转步数 0 表示一直旋转 +// 返 回 值: 无 +//------------------------------------------------------------------------------ +void MOTO_ShangeSpeed(uint32_t _speed) +{ + g_tMoto.StepFreq = _speed; + + if (g_tMoto.Running == 1) + { + // void bsp_SetTIMforInt(TIM_TypeDef* TIMx, uint32_t _ulFreq, uint8_t _PreemptionPriority, uint8_t _SubPriority) + bsp_SetTIMforInt(TIM6, _speed, 2, 2); + } +} + +void MOTO_ZorePos(void) +{ + MOTO_Stop(); + g_tMoto.sv_pulse = 0; + g_tMoto.pv_pulse = 0; + g_tMoto.prev_pv_pulse = 0; + GPIO_PORT_ZERO_SIG->BRR = GPIO_PIN_ZERO_SIG; // 归零时 PA6 输出低 + BEEP_Start(1500, 5, 5, 3); +} + +//------------------------------------------------------------------------------ +// 函 数 名: MOTO_Stop +// 功能说明: 控制电机停止运行。 +// 形 参: 无 +// 返 回 值: 无 +//------------------------------------------------------------------------------ +void MOTO_Stop(void) +{ + // void bsp_SetTIMforInt(TIM_TypeDef* TIMx, uint32_t _ulFreq, uint8_t _PreemptionPriority, uint8_t _SubPriority) + bsp_SetTIMforInt(TIM6, 0, 0, 0); + g_tMoto.Running = 0; + + MOTO_STEP_0(); + // bsp_drv8880_enable_config(DISABLE); + if (g_tTube.state == SEARCH) + { + g_tTube.state = IDLE; + } +} + +//------------------------------------------------------------------------------ +// 函 数 名: MOTO_Pause +// 功能说明: 控制电机暂停旋转。 +// 形 参: 无 +// 返 回 值: 无 +//------------------------------------------------------------------------------ +void MOTO_Pause(void) +{ + // void bsp_SetTIMforInt(TIM_TypeDef* TIMx, uint32_t _ulFreq, uint8_t _PreemptionPriority, uint8_t _SubPriority) + bsp_SetTIMforInt(TIM6, 0, 0, 0); + g_tMoto.Running = 0; + MOTO_STEP_0(); + // bsp_drv8880_enable_config(DISABLE); +} + +//------------------------------------------------------------------------------ +// 函 数 名: MOTO_RoudToStep +// 功能说明: 圈数换算为步数。28BYJ48 电机步距角度 = 5.625/64度. +// 形 参: 无 +// 返 回 值: 无 +//------------------------------------------------------------------------------ +uint32_t MOTO_RoudToStep(void) +{ + uint32_t steps; + + /* 28BYJ48 电机步距角度 = 5.625/64度. + 一圈 360度； + step = 360 / (5.625 / 64) + */ + steps = (360 * 64 * 1000 / 4) / 5625; // 4096步 + + return steps; +} + +//------------------------------------------------------------------------------ +// 函 数 名: MOTO_ISR +// 功能说明: 中断服务程序 +// 形 参: 无 +// 返 回 值: 无 +//------------------------------------------------------------------------------ +void MOTO_ISR(void) +{ + if (g_tMoto.Running == 0) + { + return; + } + // BEEP_KeyTone(); + + // g_tMoto.Pos = 0; + switch (g_tMoto.Pos) + { + case 0: + { + g_tMoto.Pos = 1; + MOTO_STEP_1(); + g_tMoto.prev_pv_pulse = g_tMoto.pv_pulse; + if (g_tMoto.pv_pulse < g_tMoto.sv_pulse) + { + g_tMoto.pv_pulse++; + } + else if (g_tMoto.pv_pulse > g_tMoto.sv_pulse) + { + g_tMoto.pv_pulse--; + } + // 检测过零点：pv_pulse 每跨越一个 STEP_PER_LAP（即每转一圈）翻转PA6 + if ((g_tMoto.prev_pv_pulse / STEP_PER_LAP) != (g_tMoto.pv_pulse / STEP_PER_LAP)) + { + ZERO_SIG_TOGGLE(); + } + break; + } + + case 1: + { + g_tMoto.Pos = 0; + MOTO_STEP_0(); + g_tMoto.CurrentStep++; + if (g_tMoto.pv_pulse == g_tMoto.sv_pulse) + { + MOTO_Stop(); + TIM_ClearITPendingBit(TIM6, TIM_IT_Update); /* 清除中断标志位 */ + } + break; + } + default: + break; + } +} + +//------------------------------------------------------------------------------ +// 函 数 名: TIM6_IRQHandler +// 功能说明: 外部中断服务程序. +// 形 参：无 +// 返 回 值: 无 +//------------------------------------------------------------------------------ +#ifndef TIM6_ISR_MOVE_OUT /* bsp.h 中定义此行，表示本函数移到 stam32fxxx_it.c。 避免重复定义 */ +void TIM6_IRQHandler(void) +{ + if (TIM_GetITStatus(TIM6, TIM_IT_Update) != RESET) + { + MOTO_ISR(); /* 中断服务程序 */ + + TIM_ClearITPendingBit(TIM6, TIM_IT_Update); /* 清除中断标志位 */ + } +} +#endif + +//-------------------------------- End of file --------------------------------- diff --git a/User/bsp/src/bsp_tim_pwm.c b/User/bsp/src/bsp_tim_pwm.c new file mode 100644 index 0000000..f0196a7 --- /dev/null +++ b/User/bsp/src/bsp_tim_pwm.c @@ -0,0 +1,671 @@ +/* + * @Author: Memory 1619005172@qq.com + * @Date: 2026-04-15 18:01:19 + * @LastEditors: Memory 1619005172@qq.com + * @LastEditTime: 2026-04-15 18:58:21 + * @FilePath: \MDK-ARMd:\Project\MFT\Motor\User\bsp\src\bsp_tim_pwm.c + * @Description: 这是默认设置,请设置`customMade`, 打开koroFileHeader查看配置 进行设置: https://github.com/OBKoro1/koro1FileHeader/wiki/%E9%85%8D%E7%BD%AE + */ +/* +********************************************************************************************************* +* +* 模块名称 : TIM基本定时中断和PWM驱动模块 +* 文件名称 : bsp_tim_pwm.c +* 版 本 : V1.1 +* 说 明 : 利用STM32F4内部TIM输出PWM信号， 并实现基本的定时中断 +* 修改记录 : +* 版本号 日期 作者 说明 +* V1.0 2013-08-16 armfly 正式发布 +* V1.1 2014-06-15 armfly 完善 bsp_SetTIMOutPWM，当占空比=0和100%时，关闭定时器，GPIO配置为输出 +* V1.2 2015-05-08 armfly 解决TIM8不能输出PWM的问题。 +* V1.3 2015-07-30 armfly 增加反相引脚输出PWM函数 bsp_SetTIMOutPWM_N(); +* +* Copyright (C), 2015-2016, 安富莱电子 www.armfly.com +* +********************************************************************************************************* +*/ + +#include "bsp.h" + +/* + 可以输出到GPIO的TIM通道: + + PA0 TIM5_CH1 + PA0 TIM5_CH2 TIM2_CH2 + PA2 TIM5_CH3 TIM2_CH3 + PA3 TIM5_CH4 TIM2_CH4 + + PA6 TIM3_CH1 + PA7 TIM3_CH2 + + PB0 TIM3_CH3 + PB1 TIM3_CH4 + + PE9 TIM1_CH1 + PE11 TIM1_CH2 + PE13 TIM1_CH3 + + PE14 TIM1_CH4 + + PD12 TIM4_CH1 + PD13 TIM4_CH2 + PD14 TIM4_CH3 + PD15 TIM4_CH4 + + PC6 TIM8_CH1 + PC7 TIM8_CH2 + PC8 TIM8_CH3 + PC9 TIM8_CH4 + + PA8 TIM1_CH1 + PA9 TIM1_CH2 + PA10 TIM1_CH3 + PA11 TIM1_CH4 + + PB3 TIM2_CH2 + PB4 TIM3_CH1 + PB5 TIM3_CH2 + + PB6 TIM4_CH1 + PB7 TIM4_CH2 + PB8 TIM4_CH3 + PB9 TIM4_CH4 + + APB1 定时器有 TIM2, TIM3 ,TIM4, TIM5, TIM6, TIM7 --- 36M + APB2 定时器有 TIM1, TIM8 ---- 72M +*/ + +/* +********************************************************************************************************* +* 函 数 名: bsp_GetRCCofGPIO +* 功能说明: 根据GPIO 得到RCC寄存器 +* 形 参：无 +* 返 回 值: GPIO外设时钟名 +********************************************************************************************************* +*/ +uint32_t bsp_GetRCCofGPIO(GPIO_TypeDef *GPIOx) +{ + uint32_t rcc = 0; + + if (GPIOx == GPIOA) + { + rcc = RCC_APB2Periph_GPIOA; + } + else if (GPIOx == GPIOB) + { + rcc = RCC_APB2Periph_GPIOB; + } + else if (GPIOx == GPIOC) + { + rcc = RCC_APB2Periph_GPIOC; + } + else if (GPIOx == GPIOD) + { + rcc = RCC_APB2Periph_GPIOD; + } + else if (GPIOx == GPIOE) + { + rcc = RCC_APB2Periph_GPIOE; + } + else if (GPIOx == GPIOF) + { + rcc = RCC_APB2Periph_GPIOF; + } + else if (GPIOx == GPIOG) + { + rcc = RCC_APB2Periph_GPIOG; + } + + return rcc; +} + +/* +********************************************************************************************************* +* 函 数 名: bsp_GetRCCofTIM +* 功能说明: 根据TIM 得到RCC寄存器 +* 形 参：无 +* 返 回 值: TIM外设时钟名 +********************************************************************************************************* +*/ +uint32_t bsp_GetRCCofTIM(TIM_TypeDef *TIMx) +{ + uint32_t rcc = 0; + + /* + APB1 定时器有 TIM2, TIM3 ,TIM4, TIM5, TIM6, TIM7, TIM12, TIM13, TIM14 + APB2 定时器有 TIM1, TIM8 ,TIM9, TIM10, TIM11 + */ + if (TIMx == TIM1) + { + rcc = RCC_APB2Periph_TIM1; + } + else if (TIMx == TIM8) + { + rcc = RCC_APB2Periph_TIM8; + } + else if (TIMx == TIM9) + { + rcc = RCC_APB2Periph_TIM9; + } + else if (TIMx == TIM10) + { + rcc = RCC_APB2Periph_TIM10; + } + else if (TIMx == TIM11) + { + rcc = RCC_APB2Periph_TIM11; + } + /* 下面是 APB1时钟 */ + else if (TIMx == TIM2) + { + rcc = RCC_APB1Periph_TIM2; + } + else if (TIMx == TIM3) + { + rcc = RCC_APB1Periph_TIM3; + } + else if (TIMx == TIM4) + { + rcc = RCC_APB1Periph_TIM4; + } + else if (TIMx == TIM5) + { + rcc = RCC_APB1Periph_TIM5; + } + else if (TIMx == TIM6) + { + rcc = RCC_APB1Periph_TIM6; + } + else if (TIMx == TIM7) + { + rcc = RCC_APB1Periph_TIM7; + } + else if (TIMx == TIM12) + { + rcc = RCC_APB1Periph_TIM12; + } + else if (TIMx == TIM13) + { + rcc = RCC_APB1Periph_TIM13; + } + else if (TIMx == TIM14) + { + rcc = RCC_APB1Periph_TIM14; + } + + return rcc; +} + +/* +********************************************************************************************************* +* 函 数 名: bsp_ConfigTimGpio +* 功能说明: 配置GPIO和TIM时钟， GPIO连接到TIM输出通道 +* 形 参: GPIOx +* GPIO_PinX +* TIMx +* _ucChannel +* 返 回 值: 无 +********************************************************************************************************* +*/ +void bsp_ConfigTimGpio(GPIO_TypeDef *GPIOx, uint16_t GPIO_PinX, TIM_TypeDef *TIMx, uint8_t _ucChannel) +{ + GPIO_InitTypeDef GPIO_InitStructure; + + /* 使能GPIO时钟 */ + RCC_APB2PeriphClockCmd(bsp_GetRCCofGPIO(GPIOx), ENABLE); + + /* 使能TIM时钟 */ + if ((TIMx == TIM1) || (TIMx == TIM8)) + { + RCC_APB2PeriphClockCmd(bsp_GetRCCofTIM(TIMx), ENABLE); + } + else + { + RCC_APB1PeriphClockCmd(bsp_GetRCCofTIM(TIMx), ENABLE); + } + + /* 配置GPIO */ + GPIO_InitStructure.GPIO_Pin = GPIO_PinX; + GPIO_InitStructure.GPIO_Mode = GPIO_Mode_AF_PP; /* 复用功能 */ + GPIO_InitStructure.GPIO_Speed = GPIO_Speed_50MHz; + GPIO_Init(GPIOx, &GPIO_InitStructure); +} + +/* +********************************************************************************************************* +* 函 数 名: bsp_ConfigGpioOut +* 功能说明: 配置GPIO为推挽输出。主要用于PWM输出，占空比为0和100的情况。 +* 形 参: GPIOx +* GPIO_PinX +* 返 回 值: 无 +********************************************************************************************************* +*/ +void bsp_ConfigGpioOut(GPIO_TypeDef *GPIOx, uint16_t GPIO_PinX) +{ + GPIO_InitTypeDef GPIO_InitStructure; + + /* 使能GPIO时钟 */ + RCC_APB2PeriphClockCmd(bsp_GetRCCofGPIO(GPIOx), ENABLE); + + /* 配置GPIO */ + GPIO_InitStructure.GPIO_Pin = GPIO_PinX; /* 带入的形参 */ + GPIO_InitStructure.GPIO_Mode = GPIO_Mode_Out_PP; /* 输出 */ + GPIO_InitStructure.GPIO_Speed = GPIO_Speed_50MHz; + GPIO_Init(GPIOx, &GPIO_InitStructure); +} + +/* +********************************************************************************************************* +* 函 数 名: bsp_SetTIMOutPWM +* 功能说明: 设置引脚输出的PWM信号的频率和占空比. 当频率为0，并且占空为0时，关闭定时器，GPIO输出0； +* 当频率为0，占空比为100%时，GPIO输出1. +* 形 参: _ulFreq : PWM信号频率，单位Hz (实际测试，最大输出频率为 168M / 4 = 42M）. 0 表示禁止输出 +* _ulDutyCycle : PWM信号占空比，单位：万分之一。如5000，表示50.00%的占空比 +* 返 回 值: 无 +********************************************************************************************************* +*/ +void bsp_SetTIMOutPWM(GPIO_TypeDef *GPIOx, uint16_t GPIO_Pin, TIM_TypeDef *TIMx, uint8_t _ucChannel, + uint32_t _ulFreq, uint32_t _ulDutyCycle) +{ + TIM_TimeBaseInitTypeDef TIM_TimeBaseStructure; + TIM_OCInitTypeDef TIM_OCInitStructure; + uint16_t usPeriod; + uint16_t usPrescaler; + uint32_t uiTIMxCLK; + + if (_ulDutyCycle == 0) + { + TIM_Cmd(TIMx, DISABLE); /* 关闭PWM输出 */ + bsp_ConfigGpioOut(GPIOx, GPIO_Pin); /* 配置GPIO为推挽输出 */ + GPIO_WriteBit(GPIOx, GPIO_Pin, Bit_RESET); /* PWM = 0 */ + return; + } + else if (_ulDutyCycle == 10000) + { + TIM_Cmd(TIMx, DISABLE); /* 关闭PWM输出 */ + + bsp_ConfigGpioOut(GPIOx, GPIO_Pin); /* 配置GPIO为推挽输出 */ + GPIO_WriteBit(GPIOx, GPIO_Pin, Bit_SET); /* PWM = 1 */ + return; + } + + bsp_ConfigTimGpio(GPIOx, GPIO_Pin, TIMx, _ucChannel); /* 使能GPIO和TIM时钟，并连接TIM通道到GPIO */ + + /*----------------------------------------------------------------------- + system_stm32f4xx.c 文件中 void SetSysClock(void) 函数对时钟的配置如下： + + HCLK = SYSCLK / 1 (AHB1Periph) + PCLK2 = HCLK / 2 (APB2Periph) + PCLK1 = HCLK / 4 (APB1Periph) + + 因为APB1 prescaler != 1, 所以 APB1上的TIMxCLK = PCLK1 x 2 = SystemCoreClock / 2; + 因为APB2 prescaler != 1, 所以 APB2上的TIMxCLK = PCLK2 x 2 = SystemCoreClock; + + APB1 定时器有 TIM2, TIM3 ,TIM4, TIM5, TIM6, TIM6, TIM12, TIM13,TIM14 + APB2 定时器有 TIM1, TIM8 ,TIM9, TIM10, TIM11 + + ----------------------------------------------------------------------- */ + if ((TIMx == TIM1) || (TIMx == TIM8) || (TIMx == TIM9) || (TIMx == TIM10) || (TIMx == TIM11)) + { + /* APB2 定时器 */ + uiTIMxCLK = SystemCoreClock; + } + else /* APB1 定时器 */ + { + uiTIMxCLK = SystemCoreClock; // SystemCoreClock / 2; + } + + if (_ulFreq < 100) + { + usPrescaler = 10000 - 1; /* 分频比 = 10000 */ + usPeriod = (uiTIMxCLK / 10000) / _ulFreq - 1; /* 自动重装的值 */ + } + else if (_ulFreq < 3000) + { + usPrescaler = 100 - 1; /* 分频比 = 100 */ + usPeriod = (uiTIMxCLK / 100) / _ulFreq - 1; /* 自动重装的值 */ + } + else /* 大于4K的频率，无需分频 */ + { + usPrescaler = 0; /* 分频比 = 1 */ + usPeriod = uiTIMxCLK / _ulFreq - 1; /* 自动重装的值 */ + } + + /* Time base configuration */ + TIM_TimeBaseStructure.TIM_Period = usPeriod; + TIM_TimeBaseStructure.TIM_Prescaler = usPrescaler; + TIM_TimeBaseStructure.TIM_ClockDivision = 0; + TIM_TimeBaseStructure.TIM_CounterMode = TIM_CounterMode_Up; + TIM_TimeBaseStructure.TIM_RepetitionCounter = 0; + TIM_TimeBaseInit(TIMx, &TIM_TimeBaseStructure); + + /* PWM1 Mode configuration: Channel1 */ + TIM_OCStructInit(&TIM_OCInitStructure); /* 初始化结构体成员 */ + + TIM_OCInitStructure.TIM_OCMode = TIM_OCMode_PWM1; + TIM_OCInitStructure.TIM_OutputState = TIM_OutputState_Enable; + TIM_OCInitStructure.TIM_Pulse = (_ulDutyCycle * usPeriod) / 10000; + TIM_OCInitStructure.TIM_OCPolarity = TIM_OCPolarity_High; + + TIM_OCInitStructure.TIM_OutputNState = TIM_OutputNState_Disable; /* only for TIM1 and TIM8. */ + TIM_OCInitStructure.TIM_OCNPolarity = TIM_OCNPolarity_High; /* only for TIM1 and TIM8. */ + TIM_OCInitStructure.TIM_OCIdleState = TIM_OCIdleState_Reset; /* only for TIM1 and TIM8. */ + TIM_OCInitStructure.TIM_OCNIdleState = TIM_OCNIdleState_Reset; /* only for TIM1 and TIM8. */ + + if (_ucChannel == 1) + { + TIM_OC1Init(TIMx, &TIM_OCInitStructure); + TIM_OC1PreloadConfig(TIMx, TIM_OCPreload_Enable); + } + else if (_ucChannel == 2) + { + TIM_OC2Init(TIMx, &TIM_OCInitStructure); + TIM_OC2PreloadConfig(TIMx, TIM_OCPreload_Enable); + } + else if (_ucChannel == 3) + { + TIM_OC3Init(TIMx, &TIM_OCInitStructure); + TIM_OC3PreloadConfig(TIMx, TIM_OCPreload_Enable); + } + else if (_ucChannel == 4) + { + TIM_OC4Init(TIMx, &TIM_OCInitStructure); + TIM_OC4PreloadConfig(TIMx, TIM_OCPreload_Enable); + } + + TIM_ARRPreloadConfig(TIMx, ENABLE); + + /* TIMx enable counter */ + TIM_Cmd(TIMx, ENABLE); + + /* 下面这句话对于TIM1和TIM8是必须的，对于TIM2-TIM6则不必要 */ + if ((TIMx == TIM1) || (TIMx == TIM8)) + { + TIM_CtrlPWMOutputs(TIMx, ENABLE); + } +} + +/* +********************************************************************************************************* +* 函 数 名: bsp_SetTIMOutPWM_N +* 功能说明: 设置TIM8_CH1N 等反相引脚输出的PWM信号的频率和占空比. 当频率为0，并且占空为0时，关闭定时器，GPIO输出0； +* 当频率为0，占空比为100%时，GPIO输出1. +* 形 参: _ulFreq : PWM信号频率，单位Hz (实际测试，最大输出频率为 168M / 4 = 42M）. 0 表示禁止输出 +* _ulDutyCycle : PWM信号占空比，单位：万分之一。如5000，表示50.00%的占空比 +* 返 回 值: 无 +********************************************************************************************************* +*/ +void bsp_SetTIMOutPWM_N(GPIO_TypeDef *GPIOx, uint16_t GPIO_Pin, TIM_TypeDef *TIMx, uint8_t _ucChannel, + uint32_t _ulFreq, uint32_t _ulDutyCycle) +{ + TIM_TimeBaseInitTypeDef TIM_TimeBaseStructure; + TIM_OCInitTypeDef TIM_OCInitStructure; + uint16_t usPeriod; + uint16_t usPrescaler; + uint32_t uiTIMxCLK; + + if (_ulDutyCycle == 0) + { + TIM_Cmd(TIMx, DISABLE); /* 关闭PWM输出 */ + bsp_ConfigGpioOut(GPIOx, GPIO_Pin); /* 配置GPIO为推挽输出 */ + GPIO_WriteBit(GPIOx, GPIO_Pin, Bit_RESET); /* PWM = 0 */ + return; + } + else if (_ulDutyCycle == 10000) + { + TIM_Cmd(TIMx, DISABLE); /* 关闭PWM输出 */ + + bsp_ConfigGpioOut(GPIOx, GPIO_Pin); /* 配置GPIO为推挽输出 */ + GPIO_WriteBit(GPIOx, GPIO_Pin, Bit_SET); /* PWM = 1 */ + return; + } + + bsp_ConfigTimGpio(GPIOx, GPIO_Pin, TIMx, _ucChannel); /* 使能GPIO和TIM时钟，并连接TIM通道到GPIO */ + + /*----------------------------------------------------------------------- + system_stm32f4xx.c 文件中 void SetSysClock(void) 函数对时钟的配置如下： + + HCLK = SYSCLK / 1 (AHB1Periph) + PCLK2 = HCLK / 2 (APB2Periph) + PCLK1 = HCLK / 4 (APB1Periph) + + 因为APB1 prescaler != 1, 所以 APB1上的TIMxCLK = PCLK1 x 2 = SystemCoreClock / 2; + 因为APB2 prescaler != 1, 所以 APB2上的TIMxCLK = PCLK2 x 2 = SystemCoreClock; + + APB1 定时器有 TIM2, TIM3 ,TIM4, TIM5, TIM6, TIM6, TIM12, TIM13,TIM14 + APB2 定时器有 TIM1, TIM8 ,TIM9, TIM10, TIM11 + + ----------------------------------------------------------------------- */ + if ((TIMx == TIM1) || (TIMx == TIM8) || (TIMx == TIM9) || (TIMx == TIM10) || (TIMx == TIM11)) + { + /* APB2 定时器 */ + uiTIMxCLK = SystemCoreClock; + } + else /* APB1 定时器 */ + { + uiTIMxCLK = SystemCoreClock; // SystemCoreClock / 2; + } + + if (_ulFreq < 100) + { + usPrescaler = 10000 - 1; /* 分频比 = 10000 */ + usPeriod = (uiTIMxCLK / 10000) / _ulFreq - 1; /* 自动重装的值 */ + } + else if (_ulFreq < 3000) + { + usPrescaler = 100 - 1; /* 分频比 = 100 */ + usPeriod = (uiTIMxCLK / 100) / _ulFreq - 1; /* 自动重装的值 */ + } + else /* 大于4K的频率，无需分频 */ + { + usPrescaler = 0; /* 分频比 = 1 */ + usPeriod = uiTIMxCLK / _ulFreq - 1; /* 自动重装的值 */ + } + + /* Time base configuration */ + TIM_TimeBaseStructure.TIM_Period = usPeriod; + TIM_TimeBaseStructure.TIM_Prescaler = usPrescaler; + TIM_TimeBaseStructure.TIM_ClockDivision = 0; + TIM_TimeBaseStructure.TIM_CounterMode = TIM_CounterMode_Up; + TIM_TimeBaseStructure.TIM_RepetitionCounter = 0; + TIM_TimeBaseInit(TIMx, &TIM_TimeBaseStructure); + + /* PWM1 Mode configuration: Channel1 */ + TIM_OCStructInit(&TIM_OCInitStructure); /* 初始化结构体成员 */ + + TIM_OCInitStructure.TIM_OCMode = TIM_OCMode_PWM1; + TIM_OCInitStructure.TIM_OutputState = TIM_OutputState_Disable; /* 和 bsp_SetTIMOutPWM_N() 不同 */ + TIM_OCInitStructure.TIM_Pulse = (_ulDutyCycle * usPeriod) / 10000; + TIM_OCInitStructure.TIM_OCPolarity = TIM_OCPolarity_High; + + TIM_OCInitStructure.TIM_OutputNState = TIM_OutputNState_Enable; /* only for TIM1 and TIM8. */ + TIM_OCInitStructure.TIM_OCNPolarity = TIM_OCNPolarity_High; /* only for TIM1 and TIM8. */ + TIM_OCInitStructure.TIM_OCIdleState = TIM_OCIdleState_Reset; /* only for TIM1 and TIM8. */ + TIM_OCInitStructure.TIM_OCNIdleState = TIM_OCNIdleState_Reset; /* only for TIM1 and TIM8. */ + + if (_ucChannel == 1) + { + TIM_OC1Init(TIMx, &TIM_OCInitStructure); + TIM_OC1PreloadConfig(TIMx, TIM_OCPreload_Enable); + } + else if (_ucChannel == 2) + { + TIM_OC2Init(TIMx, &TIM_OCInitStructure); + TIM_OC2PreloadConfig(TIMx, TIM_OCPreload_Enable); + } + else if (_ucChannel == 3) + { + TIM_OC3Init(TIMx, &TIM_OCInitStructure); + TIM_OC3PreloadConfig(TIMx, TIM_OCPreload_Enable); + } + else if (_ucChannel == 4) + { + TIM_OC4Init(TIMx, &TIM_OCInitStructure); + TIM_OC4PreloadConfig(TIMx, TIM_OCPreload_Enable); + } + + TIM_ARRPreloadConfig(TIMx, ENABLE); + + /* TIMx enable counter */ + TIM_Cmd(TIMx, ENABLE); + + /* 下面这句话对于TIM1和TIM8是必须的，对于TIM2-TIM6则不必要 */ + if ((TIMx == TIM1) || (TIMx == TIM8)) + { + TIM_CtrlPWMOutputs(TIMx, ENABLE); + } +} + +/* +********************************************************************************************************* +* 函 数 名: bsp_SetTIMforInt +* 功能说明: 配置TIM和NVIC，用于简单的定时中断. 开启定时中断。 中断服务程序由应用程序实现。 +* 形 参: TIMx : 定时器 +* _ulFreq : 定时频率 （Hz）。 0 表示关闭。 +* _PreemptionPriority : 中断优先级分组 +* _SubPriority : 子优先级 +* 返 回 值: 无 +********************************************************************************************************* +*/ +void bsp_SetTIMforInt(TIM_TypeDef *TIMx, uint32_t _ulFreq, uint8_t _PreemptionPriority, uint8_t _SubPriority) +{ + TIM_TimeBaseInitTypeDef TIM_TimeBaseStructure; + uint16_t usPeriod; + uint16_t usPrescaler; + uint32_t uiTIMxCLK; + + /* 使能TIM时钟 */ + if ((TIMx == TIM1) || (TIMx == TIM8)) + { + RCC_APB2PeriphClockCmd(bsp_GetRCCofTIM(TIMx), ENABLE); + } + else + { + RCC_APB1PeriphClockCmd(bsp_GetRCCofTIM(TIMx), ENABLE); + } + + if (_ulFreq == 0) + { + TIM_Cmd(TIMx, DISABLE); /* 关闭定时输出 */ + + /* 关闭TIM定时更新中断 (Update) */ + { + NVIC_InitTypeDef NVIC_InitStructure; /* 中断结构体在 misc.h 中定义 */ + uint8_t irq = 0; /* 中断号, 定义在 stm32f4xx.h */ + + if (TIMx == TIM1) + irq = TIM1_UP_IRQn; + else if (TIMx == TIM2) + irq = TIM2_IRQn; + else if (TIMx == TIM3) + irq = TIM3_IRQn; + else if (TIMx == TIM4) + irq = TIM4_IRQn; + else if (TIMx == TIM5) + irq = TIM5_IRQn; + else if (TIMx == TIM6) + irq = TIM6_IRQn; + else if (TIMx == TIM7) + irq = TIM7_IRQn; + else if (TIMx == TIM8) + irq = TIM8_UP_IRQn; + + NVIC_InitStructure.NVIC_IRQChannel = irq; + NVIC_InitStructure.NVIC_IRQChannelPreemptionPriority = _PreemptionPriority; + NVIC_InitStructure.NVIC_IRQChannelSubPriority = _SubPriority; + NVIC_InitStructure.NVIC_IRQChannelCmd = DISABLE; + NVIC_Init(&NVIC_InitStructure); + } + return; + } + + /*----------------------------------------------------------------------- + system_stm32f4xx.c 文件中 static void SetSysClockToHSE(void) 函数对时钟的配置如下： + + //HCLK = SYSCLK + RCC->CFGR |= (uint32_t)RCC_CFGR_HPRE_DIV1; + + //PCLK2 = HCLK + RCC->CFGR |= (uint32_t)RCC_CFGR_PPRE2_DIV1; + + //PCLK1 = HCLK + RCC->CFGR |= (uint32_t)RCC_CFGR_PPRE1_DIV1; + + APB1 定时器有 TIM2, TIM3 ,TIM4, TIM5, TIM6, TIM7, TIM12, TIM13,TIM14 + APB2 定时器有 TIM1, TIM8 ,TIM9, TIM10, TIM11 + + ----------------------------------------------------------------------- */ + if ((TIMx == TIM1) || (TIMx == TIM8) || (TIMx == TIM9) || (TIMx == TIM10) || (TIMx == TIM11)) + { + /* APB2 定时器 */ + uiTIMxCLK = SystemCoreClock; + } + else /* APB1 定时器 . */ + { + uiTIMxCLK = SystemCoreClock; // SystemCoreClock / 2; + } + + if (_ulFreq < 100) + { + usPrescaler = 10000 - 1; /* 分频比 = 1000 */ + usPeriod = (uiTIMxCLK / 10000) / _ulFreq - 1; /* 自动重装的值 */ + } + else if (_ulFreq < 3000) + { + usPrescaler = 100 - 1; /* 分频比 = 100 */ + usPeriod = (uiTIMxCLK / 100) / _ulFreq - 1; /* 自动重装的值 */ + } + else /* 大于4K的频率，无需分频 */ + { + usPrescaler = 0; /* 分频比 = 1 */ + usPeriod = uiTIMxCLK / _ulFreq - 1; /* 自动重装的值 */ + } + + /* Time base configuration */ + TIM_TimeBaseStructure.TIM_Period = usPeriod; + TIM_TimeBaseStructure.TIM_Prescaler = usPrescaler; + TIM_TimeBaseStructure.TIM_ClockDivision = 0; + TIM_TimeBaseStructure.TIM_CounterMode = TIM_CounterMode_Up; + TIM_TimeBaseStructure.TIM_RepetitionCounter = 0; + + TIM_TimeBaseInit(TIMx, &TIM_TimeBaseStructure); + + TIM_ARRPreloadConfig(TIMx, ENABLE); + + /* TIM Interrupts enable */ + TIM_ITConfig(TIMx, TIM_IT_Update, ENABLE); + + /* TIMx enable counter */ + TIM_Cmd(TIMx, ENABLE); + + /* 配置TIM定时更新中断 (Update) */ + { + NVIC_InitTypeDef NVIC_InitStructure; /* 中断结构体在 misc.h 中定义 */ + uint8_t irq = 0; /* 中断号, 定义在 stm32f4xx.h */ + + if (TIMx == TIM1) + irq = TIM1_UP_IRQn; + else if (TIMx == TIM2) + irq = TIM2_IRQn; + else if (TIMx == TIM3) + irq = TIM3_IRQn; + else if (TIMx == TIM4) + irq = TIM4_IRQn; + else if (TIMx == TIM5) + irq = TIM5_IRQn; + else if (TIMx == TIM6) + irq = TIM6_IRQn; + else if (TIMx == TIM7) + irq = TIM7_IRQn; + else if (TIMx == TIM8) + irq = TIM8_UP_IRQn; + + NVIC_InitStructure.NVIC_IRQChannel = irq; + NVIC_InitStructure.NVIC_IRQChannelPreemptionPriority = _PreemptionPriority; + NVIC_InitStructure.NVIC_IRQChannelSubPriority = _SubPriority; + NVIC_InitStructure.NVIC_IRQChannelCmd = ENABLE; + NVIC_Init(&NVIC_InitStructure); + } +} + +/***************************** 安富莱电子 www.armfly.com (END OF FILE) *********************************/ diff --git a/User/bsp/src/bsp_timer.c b/User/bsp/src/bsp_timer.c new file mode 100644 index 0000000..d1cf94a --- /dev/null +++ b/User/bsp/src/bsp_timer.c @@ -0,0 +1,673 @@ +/* +********************************************************************************************************* +* +* 模块名称 : 定时器模块 +* 文件名称 : bsp_timer.c +* 版 本 : V1.3 +* 说 明 : 配置systick定时器作为系统滴答定时器。缺省定时周期为1ms。 +* +* 实现了多个软件定时器供主程序使用(精度1ms)， 可以通过修改 TMR_COUNT 增减定时器个数 +* 实现了ms级别延迟函数（精度1ms） 和us级延迟函数 +* 实现了系统运行时间函数（1ms单位） +* +* 修改记录 : +* 版本号 日期 作者 说明 +* V1.0 2013-02-01 armfly 正式发布 +* V1.1 2013-06-21 armfly 增加us级延迟函数 bsp_DelayUS +* V1.2 2014-09-07 armfly 增加TIM4 硬件定时中断，实现us级别定时.20us - 16秒 +* V1.3 2015-04-06 armfly 增加 bsp_CheckRunTime(int32_t _LastTime) 用来计算时间差值 +* V1.4 2015-05-22 armfly 完善 bsp_InitHardTimer() ，增加条件编译选择TIM2-5 +* +* Copyright (C), 2015-2016, 安富莱电子 www.armfly.com +* +********************************************************************************************************* +*/ + +#include "bsp.h" + +/* + 定义用于硬件定时器的TIM， 可以使 TIM2 - TIM5 + TIM3 和TIM4 是16位 + TIM2 和TIM5 是16位 (103是16位, 407是32位) +*/ +#define USE_TIM2 +// #define USE_TIM3 +// #define USE_TIM4 +// #define USE_TIM5 + +#ifdef USE_TIM2 +#define TIM_HARD TIM2 +#define TIM_HARD_IRQn TIM2_IRQn +#define TIM_HARD_RCC RCC_APB1Periph_TIM2 +#endif + +#ifdef USE_TIM3 +#define TIM_HARD TIM3 +#define TIM_HARD_IRQn TIM3_IRQn +#define TIM_HARD_RCC RCC_APB1Periph_TIM3 +#endif + +#ifdef USE_TIM4 +#define TIM_HARD TIM4 +#define TIM_HARD_IRQn TIM4_IRQn +#define TIM_HARD_RCC RCC_APB1Periph_TIM4 +#endif + +#ifdef USE_TIM5 +#define TIM_HARD TIM5 +#define TIM_HARD_IRQn TIM5_IRQn +#define TIM_HARD_RCC RCC_APB1Periph_TIM5 +#endif + +/* 这2个全局变量转用于 bsp_DelayMS() 函数 */ +static volatile uint32_t s_uiDelayCount = 0; +static volatile uint8_t s_ucTimeOutFlag = 0; + +/* 定于软件定时器结构体变量 */ +static SOFT_TMR s_tTmr[TMR_COUNT]; + +/* + 全局运行时间，单位1ms + 最长可以表示 24.85天，如果你的产品连续运行时间超过这个数，则必须考虑溢出问题 +*/ +__IO int32_t g_iRunTime = 0; +uint16_t init_100ms; +static void bsp_SoftTimerDec(SOFT_TMR *_tmr); + +/* 保存 TIM定时中断到后执行的回调函数指针 */ +static void (*s_TIM_CallBack1)(void); +static void (*s_TIM_CallBack2)(void); +static void (*s_TIM_CallBack3)(void); +static void (*s_TIM_CallBack4)(void); + +/* +********************************************************************************************************* +* 函 数 名: bsp_InitTimer +* 功能说明: 配置systick中断，并初始化软件定时器变量 +* 形 参: 无 +* 返 回 值: 无 +********************************************************************************************************* +*/ +void bsp_InitTimer(void) +{ + uint8_t i; + + /* 清零所有的软件定时器 */ + for (i = 0; i < TMR_COUNT; i++) + { + s_tTmr[i].Count = 0; + s_tTmr[i].PreLoad = 0; + s_tTmr[i].Flag = 0; + s_tTmr[i].Mode = TMR_ONCE_MODE; /* 缺省是1次性工作模式 */ + } + + /* + 配置systic中断周期为1ms，并启动systick中断。 + + SystemCoreClock 是固件中定义的系统内核时钟，对于STM32F4XX,一般为 168MHz + + SysTick_Config() 函数的形参表示内核时钟多少个周期后触发一次Systick定时中断. + -- SystemCoreClock / 1000 表示定时频率为 1000Hz， 也就是定时周期为 1ms + -- SystemCoreClock / 500 表示定时频率为 500Hz， 也就是定时周期为 2ms + -- SystemCoreClock / 2000 表示定时频率为 2000Hz， 也就是定时周期为 500us + + 对于常规的应用，我们一般取定时周期1ms。对于低速CPU或者低功耗应用，可以设置定时周期为 10ms + */ + SysTick_Config(SystemCoreClock / 1000); + +#if defined(USE_TIM2) || defined(USE_TIM3) || defined(USE_TIM4) || defined(USE_TIM5) + bsp_InitHardTimer(); +#endif +} + +/* +********************************************************************************************************* +* 函 数 名: SysTick_ISR +* 功能说明: SysTick中断服务程序，每隔1ms进入1次 +* 形 参: 无 +* 返 回 值: 无 +********************************************************************************************************* +*/ +extern void bsp_RunPer1ms(void); +extern void bsp_RunPer10ms(void); +void SysTick_ISR(void) +{ + static uint8_t s_count = 0; + uint8_t i; + + /* 每隔1ms进来1次 （仅用于 bsp_DelayMS） */ + if (s_uiDelayCount > 0) + { + if (--s_uiDelayCount == 0) + { + s_ucTimeOutFlag = 1; + } + } + + /* 每隔1ms，对软件定时器的计数器进行减一操作 */ + for (i = 0; i < TMR_COUNT; i++) + { + bsp_SoftTimerDec(&s_tTmr[i]); + } + + /* 全局运行时间每1ms增1 */ + g_iRunTime++; + init_100ms++; + if (init_100ms > 100) // 100m's + { + init_100ms = 0; + Flag_100ms = 1; + } + + if (g_iRunTime == 0x7FFFFFFF) /* 这个变量是 int32_t 类型，最大数为 0x7FFFFFFF */ + { + g_iRunTime = 0; + } + + bsp_RunPer1ms(); /* 每隔1ms调用一次此函数，此函数在 bsp.c */ + + if (++s_count >= 10) + { + s_count = 0; + + bsp_RunPer10ms(); /* 每隔10ms调用一次此函数，此函数在 bsp.c */ + } +} + +/* +********************************************************************************************************* +* 函 数 名: bsp_SoftTimerDec +* 功能说明: 每隔1ms对所有定时器变量减1。必须被SysTick_ISR周期性调用。 +* 形 参: _tmr : 定时器变量指针 +* 返 回 值: 无 +********************************************************************************************************* +*/ +static void bsp_SoftTimerDec(SOFT_TMR *_tmr) +{ + if (_tmr->Count > 0) + { + /* 如果定时器变量减到1则设置定时器到达标志 */ + if (--_tmr->Count == 0) + { + _tmr->Flag = 1; + + /* 如果是自动模式，则自动重装计数器 */ + if (_tmr->Mode == TMR_AUTO_MODE) + { + _tmr->Count = _tmr->PreLoad; + } + } + } +} + +/* +********************************************************************************************************* +* 函 数 名: bsp_DelayMS +* 功能说明: ms级延迟，延迟精度为正负1ms +* 形 参: n : 延迟长度，单位1 ms。 n 应大于2 +* 返 回 值: 无 +********************************************************************************************************* +*/ +void bsp_DelayMS(uint32_t n) +{ + if (n == 0) + { + return; + } + else if (n == 1) + { + n = 2; + } + + DISABLE_INT(); /* 关中断 */ + + s_uiDelayCount = n; + s_ucTimeOutFlag = 0; + + ENABLE_INT(); /* 开中断 */ + + while (1) + { + bsp_Idle(); /* CPU空闲执行的操作， 见 bsp.c 和 bsp.h 文件 */ + + /* + 等待延迟时间到 + 注意：编译器认为 s_ucTimeOutFlag = 0，所以可能优化错误，因此 s_ucTimeOutFlag 变量必须申明为 volatile + */ + if (s_ucTimeOutFlag == 1) + { + break; + } + } +} + +/* +********************************************************************************************************* +* 函 数 名: bsp_DelayUS +* 功能说明: us级延迟。 必须在systick定时器启动后才能调用此函数。 +* 形 参: n : 延迟长度，单位1 us +* 返 回 值: 无 +********************************************************************************************************* +*/ +void bsp_DelayUS(uint32_t n) +{ + uint32_t ticks; + uint32_t told; + uint32_t tnow; + uint32_t tcnt = 0; + uint32_t reload; + + reload = SysTick->LOAD; + ticks = n * (SystemCoreClock / 1000000); /* 需要的节拍数 */ + + tcnt = 0; + told = SysTick->VAL; /* 刚进入时的计数器值 */ + + while (1) + { + tnow = SysTick->VAL; + if (tnow != told) + { + /* SYSTICK是一个递减的计数器 */ + if (tnow < told) + { + tcnt += told - tnow; + } + /* 重新装载递减 */ + else + { + tcnt += reload - tnow + told; + } + told = tnow; + + /* 时间超过/等于要延迟的时间,则退出 */ + if (tcnt >= ticks) + { + break; + } + } + } +} + +/* +********************************************************************************************************* +* 函 数 名: bsp_StartTimer +* 功能说明: 启动一个定时器，并设置定时周期。 +* 形 参: _id : 定时器ID，值域【0,TMR_COUNT-1】。用户必须自行维护定时器ID，以避免定时器ID冲突。 +* _period : 定时周期，单位1ms +* 返 回 值: 无 +********************************************************************************************************* +*/ +void bsp_StartTimer(uint8_t _id, uint32_t _period) +{ + if (_id >= TMR_COUNT) + { + /* 打印出错的源代码文件名、函数名称 */ + BSP_Printf("Error: file %s, function %s()\r\n", __FILE__, __FUNCTION__); + while (1) + ; /* 参数异常，死机等待看门狗复位 */ + } + + DISABLE_INT(); /* 关中断 */ + + s_tTmr[_id].Count = _period; /* 实时计数器初值 */ + s_tTmr[_id].PreLoad = _period; /* 计数器自动重装值，仅自动模式起作用 */ + s_tTmr[_id].Flag = 0; /* 定时时间到标志 */ + s_tTmr[_id].Mode = TMR_ONCE_MODE; /* 1次性工作模式 */ + + ENABLE_INT(); /* 开中断 */ +} + +/* +********************************************************************************************************* +* 函 数 名: bsp_StartAutoTimer +* 功能说明: 启动一个自动定时器，并设置定时周期。 +* 形 参: _id : 定时器ID，值域【0,TMR_COUNT-1】。用户必须自行维护定时器ID，以避免定时器ID冲突。 +* _period : 定时周期，单位10ms +* 返 回 值: 无 +********************************************************************************************************* +*/ +void bsp_StartAutoTimer(uint8_t _id, uint32_t _period) +{ + if (_id >= TMR_COUNT) + { + /* 打印出错的源代码文件名、函数名称 */ + BSP_Printf("Error: file %s, function %s()\r\n", __FILE__, __FUNCTION__); + while (1) + ; /* 参数异常，死机等待看门狗复位 */ + } + + DISABLE_INT(); /* 关中断 */ + + s_tTmr[_id].Count = _period; /* 实时计数器初值 */ + s_tTmr[_id].PreLoad = _period; /* 计数器自动重装值，仅自动模式起作用 */ + s_tTmr[_id].Flag = 0; /* 定时时间到标志 */ + s_tTmr[_id].Mode = TMR_AUTO_MODE; /* 自动工作模式 */ + + ENABLE_INT(); /* 开中断 */ +} + +/* +********************************************************************************************************* +* 函 数 名: bsp_StopTimer +* 功能说明: 停止一个定时器 +* 形 参: _id : 定时器ID，值域【0,TMR_COUNT-1】。用户必须自行维护定时器ID，以避免定时器ID冲突。 +* 返 回 值: 无 +********************************************************************************************************* +*/ +void bsp_StopTimer(uint8_t _id) +{ + if (_id >= TMR_COUNT) + { + /* 打印出错的源代码文件名、函数名称 */ + BSP_Printf("Error: file %s, function %s()\r\n", __FILE__, __FUNCTION__); + while (1) + ; /* 参数异常，死机等待看门狗复位 */ + } + + DISABLE_INT(); /* 关中断 */ + + s_tTmr[_id].Count = 0; /* 实时计数器初值 */ + s_tTmr[_id].Flag = 0; /* 定时时间到标志 */ + s_tTmr[_id].Mode = TMR_ONCE_MODE; /* 自动工作模式 */ + + ENABLE_INT(); /* 开中断 */ +} + +/* +********************************************************************************************************* +* 函 数 名: bsp_CheckTimer +* 功能说明: 检测定时器是否超时 +* 形 参: _id : 定时器ID，值域【0,TMR_COUNT-1】。用户必须自行维护定时器ID，以避免定时器ID冲突。 +* _period : 定时周期，单位1ms +* 返 回 值: 返回 0 表示定时未到， 1表示定时到 +********************************************************************************************************* +*/ +uint8_t bsp_CheckTimer(uint8_t _id) +{ + if (_id >= TMR_COUNT) + { + return 0; + } + + if (s_tTmr[_id].Flag == 1) + { + s_tTmr[_id].Flag = 0; + return 1; + } + else + { + return 0; + } +} + +/* +********************************************************************************************************* +* 函 数 名: bsp_GetRunTime +* 功能说明: 获取CPU运行时间，单位1ms。最长可以表示 24.85天，如果你的产品连续运行时间超过这个数，则必须考虑溢出问题 +* 形 参: 无 +* 返 回 值: CPU运行时间，单位1ms +********************************************************************************************************* +*/ +int32_t bsp_GetRunTime(void) +{ + int32_t runtime; + + DISABLE_INT(); /* 关中断 */ + + runtime = g_iRunTime; /* 这个变量在Systick中断中被改写，因此需要关中断进行保护 */ + + ENABLE_INT(); /* 开中断 */ + + return runtime; +} + +/* +********************************************************************************************************* +* 函 数 名: bsp_CheckRunTime +* 功能说明: 计算当前运行时间和给定时刻之间的差值。处理了计数器循环。 +* 形 参: _LastTime 上个时刻 +* 返 回 值: 当前时间和过去时间的差值，单位1ms +********************************************************************************************************* +*/ +int32_t bsp_CheckRunTime(int32_t _LastTime) +{ + int32_t now_time; + int32_t time_diff; + + DISABLE_INT(); /* 关中断 */ + + now_time = g_iRunTime; /* 这个变量在Systick中断中被改写，因此需要关中断进行保护 */ + + ENABLE_INT(); /* 开中断 */ + + if (now_time >= _LastTime) + { + time_diff = now_time - _LastTime; + } + else + { + time_diff = 0x7FFFFFFF - _LastTime + now_time; + } + + return time_diff; +} + +/* +********************************************************************************************************* +* 函 数 名: SysTick_Handler +* 功能说明: 系统嘀嗒定时器中断服务程序。启动文件中引用了该函数。 +* 形 参: 无 +* 返 回 值: 无 +********************************************************************************************************* +*/ +void SysTick_Handler(void) +{ + SysTick_ISR(); +} + +/* +********************************************************************************************************* +* 函 数 名: bsp_InitHardTimer +* 功能说明: 配置 TIMx，用于us级别硬件定时。TIMx将自由运行，永不停止. +* TIMx可以用TIM2 - TIM5 之间的TIM, 这些TIM有4个通道, 挂在 APB1 上，输入时钟=SystemCoreClock / 2 +* 形 参: 无 +* 返 回 值: 无 +********************************************************************************************************* +*/ +#if defined(USE_TIM2) || defined(USE_TIM3) || defined(USE_TIM4) || defined(USE_TIM5) +void bsp_InitHardTimer(void) +{ + TIM_TimeBaseInitTypeDef TIM_TimeBaseStructure; + uint32_t usPeriod; + uint16_t usPrescaler; + uint32_t uiTIMxCLK; + + /* 使能TIM时钟 */ + RCC_APB1PeriphClockCmd(TIM_HARD_RCC, ENABLE); + + /*----------------------------------------------------------------------- + system_stm32f4xx.c 文件中 void SetSysClock(void) 函数对时钟的配置如下： + + HCLK = SYSCLK / 1 (AHB1Periph) + PCLK2 = HCLK / 2 (APB2Periph) + PCLK1 = HCLK / 4 (APB1Periph) + + 因为APB1 prescaler != 1, 所以 APB1上的TIMxCLK = PCLK1 x 2 = SystemCoreClock / 2; + 因为APB2 prescaler != 1, 所以 APB2上的TIMxCLK = PCLK2 x 2 = SystemCoreClock; + + APB1 定时器有 TIM2, TIM3 ,TIM4, TIM5, TIM6, TIM7, TIM12, TIM13,TIM14 + APB2 定时器有 TIM1, TIM8 ,TIM9, TIM10, TIM11 + + ----------------------------------------------------------------------- */ + uiTIMxCLK = SystemCoreClock / 2; + + usPrescaler = uiTIMxCLK / 1000000; /* 分频到周期 1us */ + +#if defined(USE_TIM2) || defined(USE_TIM5) + // usPeriod = 0xFFFFFFFF; /* 407支持32位定时器 */ + usPeriod = 0xFFFF; /* 103支持16位 */ +#else + usPeriod = 0xFFFF; +#endif + /* Time base configuration */ + TIM_TimeBaseStructure.TIM_Period = usPeriod; + TIM_TimeBaseStructure.TIM_Prescaler = usPrescaler; + TIM_TimeBaseStructure.TIM_ClockDivision = 0; + TIM_TimeBaseStructure.TIM_CounterMode = TIM_CounterMode_Up; + + TIM_TimeBaseInit(TIM_HARD, &TIM_TimeBaseStructure); + + // TIM_ARRPreloadConfig(TIMx, ENABLE); + + /* TIMx enable counter */ + TIM_Cmd(TIM_HARD, ENABLE); + + /* 配置TIM定时中断 (Update) */ + { + NVIC_InitTypeDef NVIC_InitStructure; /* 中断结构体在 misc.h 中定义 */ + + NVIC_InitStructure.NVIC_IRQChannel = TIM_HARD_IRQn; + + NVIC_InitStructure.NVIC_IRQChannelPreemptionPriority = 4; /* 比串口优先级低 */ + NVIC_InitStructure.NVIC_IRQChannelSubPriority = 0; + NVIC_InitStructure.NVIC_IRQChannelCmd = ENABLE; + NVIC_Init(&NVIC_InitStructure); + } +} + +/* +********************************************************************************************************* +* 函 数 名: bsp_StartHardTimer +* 功能说明: 使用TIM2-5做单次定时器使用, 定时时间到后执行回调函数。可以同时启动4个定时器，互不干扰。 +* 定时精度正负10us （主要耗费在调用本函数的执行时间，函数内部进行了补偿减小误差） +* TIM2和TIM5 是16位定时器。 +* TIM3和TIM4 是16位定时器。 +* 形 参: _CC : 捕获通道几，1，2，3, 4 +* _uiTimeOut : 超时时间, 单位 1us. 对于16位定时器，最大 65.5ms; 对于32位定时器，最大 4294秒 +* _pCallBack : 定时时间到后，被执行的函数 +* 返 回 值: 无 +********************************************************************************************************* +*/ +void bsp_StartHardTimer(uint8_t _CC, uint32_t _uiTimeOut, void *_pCallBack) +{ + uint32_t cnt_now; + uint32_t cnt_tar; + + /* + 执行下面这个语句，时长 = 18us (通过逻辑分析仪测量IO翻转) + bsp_StartTimer2(3, 500, (void *)test1); + */ + if (_uiTimeOut < 5) + { + ; + } + else + { + _uiTimeOut -= 5; + } + + cnt_now = TIM_GetCounter(TIM_HARD); /* 读取当前的计数器值 */ + cnt_tar = cnt_now + _uiTimeOut; /* 计算捕获的计数器值 */ + if (_CC == 1) + { + s_TIM_CallBack1 = (void (*)(void))_pCallBack; + + TIM_SetCompare1(TIM_HARD, cnt_tar); /* 设置捕获比较计数器CC1 */ + TIM_ClearITPendingBit(TIM_HARD, TIM_IT_CC1); + TIM_ITConfig(TIM_HARD, TIM_IT_CC1, ENABLE); /* 使能CC1中断 */ + } + else if (_CC == 2) + { + s_TIM_CallBack2 = (void (*)(void))_pCallBack; + + TIM_SetCompare2(TIM_HARD, cnt_tar); /* 设置捕获比较计数器CC2 */ + TIM_ClearITPendingBit(TIM_HARD, TIM_IT_CC2); + TIM_ITConfig(TIM_HARD, TIM_IT_CC2, ENABLE); /* 使能CC2中断 */ + } + else if (_CC == 3) + { + s_TIM_CallBack3 = (void (*)(void))_pCallBack; + + TIM_SetCompare3(TIM_HARD, cnt_tar); /* 设置捕获比较计数器CC3 */ + TIM_ClearITPendingBit(TIM_HARD, TIM_IT_CC3); + TIM_ITConfig(TIM_HARD, TIM_IT_CC3, ENABLE); /* 使能CC3中断 */ + } + else if (_CC == 4) + { + s_TIM_CallBack4 = (void (*)(void))_pCallBack; + + TIM_SetCompare4(TIM_HARD, cnt_tar); /* 设置捕获比较计数器CC4 */ + TIM_ClearITPendingBit(TIM_HARD, TIM_IT_CC4); + TIM_ITConfig(TIM_HARD, TIM_IT_CC4, ENABLE); /* 使能CC4中断 */ + } + else + { + return; + } +} +#endif + +/* +********************************************************************************************************* +* 函 数 名: TIMx_IRQHandler +* 功能说明: TIM 中断服务程序 +* 形 参：无 +* 返 回 值: 无 +********************************************************************************************************* +*/ + +#ifdef USE_TIM2 +void TIM2_IRQHandler(void) +#endif + +#ifdef USE_TIM3 + void TIM3_IRQHandler(void) +#endif + +#ifdef USE_TIM4 + void TIM4_IRQHandler(void) +#endif + +#ifdef USE_TIM5 + void TIM5_IRQHandler(void) +#endif +{ + if (TIM_GetITStatus(TIM_HARD, TIM_IT_CC1)) + { + TIM_ClearITPendingBit(TIM_HARD, TIM_IT_CC1); + TIM_ITConfig(TIM_HARD, TIM_IT_CC1, DISABLE); /* 禁能CC1中断 */ + + /* 先关闭中断，再执行回调函数。因为回调函数可能需要重启定时器 */ + s_TIM_CallBack1(); + } + + if (TIM_GetITStatus(TIM_HARD, TIM_IT_CC2)) + { + TIM_ClearITPendingBit(TIM_HARD, TIM_IT_CC2); + TIM_ITConfig(TIM_HARD, TIM_IT_CC2, DISABLE); /* 禁能CC2中断 */ + + /* 先关闭中断，再执行回调函数。因为回调函数可能需要重启定时器 */ + s_TIM_CallBack2(); + } + + if (TIM_GetITStatus(TIM_HARD, TIM_IT_CC3)) + { + TIM_ClearITPendingBit(TIM_HARD, TIM_IT_CC3); + TIM_ITConfig(TIM_HARD, TIM_IT_CC3, DISABLE); /* 禁能CC3中断 */ + + /* 先关闭中断，再执行回调函数。因为回调函数可能需要重启定时器 */ + s_TIM_CallBack3(); + } + + if (TIM_GetITStatus(TIM_HARD, TIM_IT_CC4)) + { + TIM_ClearITPendingBit(TIM_HARD, TIM_IT_CC4); + TIM_ITConfig(TIM_HARD, TIM_IT_CC4, DISABLE); /* 禁能CC4中断 */ + + /* 先关闭中断，再执行回调函数。因为回调函数可能需要重启定时器 */ + s_TIM_CallBack4(); + } +} + +/***************************** 安富莱电子 www.armfly.com (END OF FILE) *********************************/ diff --git a/User/bsp/src/bsp_usart_dma.c b/User/bsp/src/bsp_usart_dma.c new file mode 100644 index 0000000..0c40c75 --- /dev/null +++ b/User/bsp/src/bsp_usart_dma.c @@ -0,0 +1,214 @@ + +#include "bsp_usart_dma.h" +#include "string.h" + +uint8_t ReceiveBuff[RECEIVEBUFF_SIZE]; +uint8_t g_ucRxRcvNewFlag; +uint8_t g_RxBuf[64]; + +/** + * @brief USART GPIO 配置,工作参数配置 + * @param 无 + * @retval 无 + */ +void USART_Config(void) +{ + GPIO_InitTypeDef GPIO_InitStructure; + USART_InitTypeDef USART_InitStructure; + NVIC_InitTypeDef NVIC_InitStruct; + // 打开串口GPIO的时钟 + DEBUG_USART_GPIO_APBxClkCmd(DEBUG_USART_GPIO_CLK, ENABLE); + + // 打开串口外设的时钟 + DEBUG_USART_APBxClkCmd(DEBUG_USART_CLK, ENABLE); + + NVIC_PriorityGroupConfig(NVIC_PriorityGroup_2); + NVIC_InitStruct.NVIC_IRQChannel = DEBUG_USART_IRQ; + NVIC_InitStruct.NVIC_IRQChannelCmd = ENABLE; + NVIC_InitStruct.NVIC_IRQChannelPreemptionPriority = 1; + NVIC_InitStruct.NVIC_IRQChannelSubPriority = 3; + NVIC_Init(&NVIC_InitStruct); + + // 将USART Tx的GPIO配置为推挽复用模式 + GPIO_InitStructure.GPIO_Pin = DEBUG_USART_TX_GPIO_PIN; + GPIO_InitStructure.GPIO_Mode = GPIO_Mode_AF_PP; + GPIO_InitStructure.GPIO_Speed = GPIO_Speed_50MHz; + GPIO_Init(DEBUG_USART_TX_GPIO_PORT, &GPIO_InitStructure); + + // 将USART Rx的GPIO配置为浮空输入模式 + GPIO_InitStructure.GPIO_Pin = DEBUG_USART_RX_GPIO_PIN; + GPIO_InitStructure.GPIO_Mode = GPIO_Mode_IN_FLOATING; + GPIO_Init(DEBUG_USART_RX_GPIO_PORT, &GPIO_InitStructure); + + // 配置串口的工作参数 + // 配置波特率 + USART_InitStructure.USART_BaudRate = DEBUG_USART_BAUDRATE; + // 配置 针数据字长 + USART_InitStructure.USART_WordLength = USART_WordLength_8b; + // 配置停止位 + USART_InitStructure.USART_StopBits = USART_StopBits_1; + // 配置校验位 + USART_InitStructure.USART_Parity = USART_Parity_No; + // 配置硬件流控制 + USART_InitStructure.USART_HardwareFlowControl = USART_HardwareFlowControl_None; + // 配置工作模式，收发一起 + USART_InitStructure.USART_Mode = USART_Mode_Rx | USART_Mode_Tx; + // 完成串口的初始化配置 + USART_Init(DEBUG_USARTx, &USART_InitStructure); + // 使能空闲中断 + USART_ITConfig(DEBUG_USARTx, USART_IT_IDLE, ENABLE); + // 使能串口 + USART_Cmd(DEBUG_USARTx, ENABLE); +} + +/***************** 发送一个字节 **********************/ +void Usart_SendByte(USART_TypeDef *pUSARTx, uint8_t ch) +{ + /* 发送一个字节数据到USART */ + USART_SendData(pUSARTx, ch); + + /* 等待发送数据寄存器为空 */ + while (USART_GetFlagStatus(pUSARTx, USART_FLAG_TXE) == RESET) + ; +} + +/****************** 发送8位的数组 ************************/ +void Usart_SendArray(USART_TypeDef *pUSARTx, uint8_t *array, uint16_t num) +{ + uint8_t i; + + for (i = 0; i < num; i++) + { + /* 发送一个字节数据到USART */ + Usart_SendByte(pUSARTx, array[i]); + } + /* 等待发送完成 */ + while (USART_GetFlagStatus(pUSARTx, USART_FLAG_TC) == RESET) + ; +} + +/***************** 发送字符串 **********************/ +void Usart_SendString(USART_TypeDef *pUSARTx, char *str) +{ + unsigned int k = 0; + do + { + Usart_SendByte(pUSARTx, *(str + k)); + k++; + } while (*(str + k) != '\0'); + + /* 等待发送完成 */ + while (USART_GetFlagStatus(pUSARTx, USART_FLAG_TC) == RESET) + { + } +} + +/***************** 发送一个16位数 **********************/ +void Usart_SendHalfWord(USART_TypeDef *pUSARTx, uint16_t ch) +{ + uint8_t temp_h, temp_l; + + /* 取出高八位 */ + temp_h = (ch & 0XFF00) >> 8; + /* 取出低八位 */ + temp_l = ch & 0XFF; + + /* 发送高八位 */ + USART_SendData(pUSARTx, temp_h); + while (USART_GetFlagStatus(pUSARTx, USART_FLAG_TXE) == RESET) + ; + + /* 发送低八位 */ + USART_SendData(pUSARTx, temp_l); + while (USART_GetFlagStatus(pUSARTx, USART_FLAG_TXE) == RESET) + ; +} + +/// 重定向c库函数printf到串口，重定向后可使用printf函数 +int fputc(int ch, FILE *f) +{ + /* 发送一个字节数据到串口 */ + USART_SendData(DEBUG_USARTx, (uint8_t)ch); + + /* 等待发送完毕 */ + while (USART_GetFlagStatus(DEBUG_USARTx, USART_FLAG_TXE) == RESET) + ; + + return (ch); +} + +/// 重定向c库函数scanf到串口，重写向后可使用scanf、getchar等函数 +int fgetc(FILE *f) +{ + /* 等待串口输入数据 */ + while (USART_GetFlagStatus(DEBUG_USARTx, USART_FLAG_RXNE) == RESET) + ; + + return (int)USART_ReceiveData(DEBUG_USARTx); +} + +/** + * @brief USARTx TX DMA 配置，内存到外设(USART1->DR) + * @param 无 + * @retval 无 + */ +void USARTx_DMA_Config(void) +{ + DMA_InitTypeDef DMA_InitStructure; + // 开启DMA时钟 + RCC_AHBPeriphClockCmd(RCC_AHBPeriph_DMA1, ENABLE); + + // 设置DMA源地址：串口数据寄存器地址*/ + DMA_InitStructure.DMA_PeripheralBaseAddr = USART_DR_ADDRESS; + // 内存地址(要传输的变量的指针) + DMA_InitStructure.DMA_MemoryBaseAddr = (u32)ReceiveBuff; + // 方向：从外设到内存 + DMA_InitStructure.DMA_DIR = DMA_DIR_PeripheralSRC; + // 传输大小 + DMA_InitStructure.DMA_BufferSize = RECEIVEBUFF_SIZE; + // 外设地址不增 + DMA_InitStructure.DMA_PeripheralInc = DMA_PeripheralInc_Disable; + // 内存地址自增 + DMA_InitStructure.DMA_MemoryInc = DMA_MemoryInc_Enable; + // 外设数据单位 + DMA_InitStructure.DMA_PeripheralDataSize = DMA_PeripheralDataSize_Byte; + // 内存数据单位 + DMA_InitStructure.DMA_MemoryDataSize = DMA_MemoryDataSize_Byte; + // DMA模式，一次或者循环模式 + // DMA_InitStructure.DMA_Mode = DMA_Mode_Normal ; + DMA_InitStructure.DMA_Mode = DMA_Mode_Circular; + // 优先级：中 + DMA_InitStructure.DMA_Priority = DMA_Priority_Medium; + // 禁止内存到内存的传输 + DMA_InitStructure.DMA_M2M = DMA_M2M_Disable; + // 配置DMA通道 + DMA_Init(USART_RX_DMA_CHANNEL, &DMA_InitStructure); + // 使能DMA + DMA_Cmd(USART_RX_DMA_CHANNEL, ENABLE); +} + +/** + * @brief 串口空闲中断. + * @param 无 + * @retval 无 + */ +void DEBUG_USART_IRQHandler(void) +{ + uint16_t t; + if (USART_GetITStatus(DEBUG_USARTx, USART_IT_IDLE) == SET) // 检查中断是否发生 + { + DMA_Cmd(USART_RX_DMA_CHANNEL, DISABLE); // 关闭DMA传输 + + t = DMA_GetCurrDataCounter(USART_RX_DMA_CHANNEL); // 获取剩余的数据数量 + memset(g_RxBuf, 0, sizeof g_RxBuf); + memcpy(g_RxBuf, ReceiveBuff, RECEIVEBUFF_SIZE - t); + memset(ReceiveBuff, 0, sizeof ReceiveBuff); + g_ucRxRcvNewFlag = 1; + + DMA_SetCurrDataCounter(USART_RX_DMA_CHANNEL, RECEIVEBUFF_SIZE); // 重新设置传输的数据数量 + DMA_Cmd(USART_RX_DMA_CHANNEL, ENABLE); // 开启DMA传输 + + USART_ReceiveData(DEBUG_USARTx); // 读取一次数据，不然会一直进中断 + USART_ClearFlag(DEBUG_USARTx, USART_FLAG_IDLE); // 清除串口空闲中断标志位 + } +} diff --git a/User/bsp/stm32f10x_assert.c b/User/bsp/stm32f10x_assert.c new file mode 100644 index 0000000..bc54e4b --- /dev/null +++ b/User/bsp/stm32f10x_assert.c @@ -0,0 +1,58 @@ +/* +********************************************************************************************************* +* +* 模块名称 : 断言模块。 +* 文件名称 : stm32f10x_assert.c +* 版 本 : V1.0 +* 说 明 : 提供断言函数,主要用于程序调试。ST固件库中的函数均可以对输入参数进行检查，提高程序的健壮性。 +* 这个文件是安富莱电子创建的文件，不属于标准库的文件，ST固件库的范例将这些函数放在main.c文件。 +* 我们认为这个和用户的具体应用无关，因此将其独立出来，使main.c文件看起来更加简洁一些。 +* 修改记录 : +* 版本号 日期 作者 说明 +* v1.0 2011-08-27 armfly ST固件库V3.4.0版本。 +* v2.0 2011-10-16 armfly ST固件库V3.5.0版本。 +* +* Copyright (C), 2010-2011, 安富莱电子 www.armfly.com +* +********************************************************************************************************* +*/ + +#include "stm32f10x.h" /* 这个文件包含了stm32f10x_conf.h, stm32f10x_conf.h文件定义了USE_FULL_ASSERT */ +#include + +/* + ST库函数使用了C编译器的断言功能，如果定义了USE_FULL_ASSERT，那么所有的ST库函数将检查函数形参 + 是否正确。如果不正确将调用 assert_failed() 函数，这个函数是一个死循环，便于用户检查代码。 + + 关键字 __LINE__ 表示源代码行号。 + 关键字__FILE__表示源代码文件名。 + + 断言功能使能后将增大代码大小，推荐用户仅在调试时使能，在正式发布软件是禁止。 + + 用户可以选择是否使能ST固件库的断言供能。使能断言的方法有两种： + (1) 在C编译器的预定义宏选项中定义USE_FULL_ASSERT。 + (2) 在本文件取消"#define USE_FULL_ASSERT 1"行的注释。 +*/ +#ifdef USE_FULL_ASSERT + +/* +********************************************************************************************************* +* 函 数 名: assert_failed +* 形 参：file : 源代码文件名称。关键字__FILE__表示源代码文件名。 +* line ：代码行号。关键字 __LINE__ 表示源代码行号 +* 返 回 值: 无 +********************************************************************************************************* +*/ +void assert_failed(uint8_t *file, uint32_t line) +{ + /* + 用户可以添加自己的代码报告源代码文件名和代码行号，比如将错误文件和行号打印到串口 + printf("Wrong parameters value: file %s on line %d\r\n", file, line) */ + */ + + /* 这是一个死循环，断言失败时程序会在此处死机，以便于用户查错 */ + while (1) + { + } +} +#endif diff --git a/User/bsp/stm32f10x_conf.h b/User/bsp/stm32f10x_conf.h new file mode 100644 index 0000000..f3bee44 --- /dev/null +++ b/User/bsp/stm32f10x_conf.h @@ -0,0 +1,72 @@ +/* +********************************************************************************************************* +* +* ģ : STM32̼ļ +* ļ : stm32f10x_conf.h +* : V3.5.0 +* ˵ : ST̼ṩļûԸҪST̼ģ顣Ϊ˷ǰй̼ +* ģ顣 +* +* ļ Libraries\CMSIS\CM3\DeviceSupport\ST\STM32F10x\stm32f10x.h +* .cļֻҪ include "stm32f10x.h"ɣصinclude stm32f10x_conf.hļ +* ޸ļ¼ : +* 汾 ˵ +* v1.0 2011-09-20 armfly ST̼V3.4.0汾 +* v2.0 2011-11-16 armfly ST̼V3.5.0汾 +* +* Copyright (C), 2010-2011, www.armfly.com +* +********************************************************************************************************* +*/ + +#ifndef __STM32F10x_CONF_H +#define __STM32F10x_CONF_H + +/* δע͵бʾӦͷļ */ +#include "stm32f10x_adc.h" +#include "stm32f10x_bkp.h" +#include "stm32f10x_can.h" +#include "stm32f10x_cec.h" +#include "stm32f10x_crc.h" +#include "stm32f10x_dac.h" +#include "stm32f10x_dbgmcu.h" +#include "stm32f10x_dma.h" +#include "stm32f10x_exti.h" +#include "stm32f10x_flash.h" +#include "stm32f10x_fsmc.h" +#include "stm32f10x_gpio.h" +#include "stm32f10x_i2c.h" +#include "stm32f10x_iwdg.h" +#include "stm32f10x_pwr.h" +#include "stm32f10x_rcc.h" +#include "stm32f10x_rtc.h" +#include "stm32f10x_sdio.h" +#include "stm32f10x_spi.h" +#include "stm32f10x_tim.h" +#include "stm32f10x_usart.h" +#include "stm32f10x_wwdg.h" +#include "misc.h" /* NVICSysTickĸ߼(CMSIS) */ + +/* + ûѡǷʹST̼ĶԹܡʹܶԵķ֣ + (1) CԤѡжUSE_FULL_ASSERT + (2) ڱļȡ"#define USE_FULL_ASSERT 1"еע͡ +*/ +/* ȡеע̼չassert_paramж */ +/* #define USE_FULL_ASSERT 1 */ + +#ifdef USE_FULL_ASSERT + /* + assert_paramںβμ顣exprfalseassert_failed()淢Դļ + кšexprtrueִκβ + + assert_failed() stm32f10x_assert.cļ(ǰļ) + */ + #define assert_param(expr) ((expr) ? (void)0 : assert_failed((uint8_t *)__FILE__, __LINE__)) + + void assert_failed(uint8_t* file, uint32_t line); +#else + #define assert_param(expr) ((void)0) +#endif + +#endif diff --git a/User/bsp/stm32f10x_it.c b/User/bsp/stm32f10x_it.c new file mode 100644 index 0000000..adcf24b --- /dev/null +++ b/User/bsp/stm32f10x_it.c @@ -0,0 +1,217 @@ +/* +********************************************************************************************************* +* +* 模块名称 : 中断模块 +* 文件名称 : stm32f10x_it.c +* 版 本 : V2.0 +* 说 明 : 本文件存放所有的中断服务函数。为了便于他人了解程序用到的中断，我们不建议将中断函数移到其他 +* 的文件。 +* +* 我们只需要添加需要的中断函数即可。一般中断函数名是固定的，除非您修改了启动文件： +* Libraries\CMSIS\CM3\DeviceSupport\ST\STM32F10x\startup\arm\startup_stm32f10x_hd.s +* +* 启动文件是汇编语言文件，定了每个中断的服务函数，这些函数使用了WEAK 关键字，表示弱定义，因此如 +* 果我们在c文件中重定义了该服务函数（必须和它同名），那么启动文件的中断函数将自动无效。这也就 +* 函数重定义的概念，这和C++中的函数重载的意义类似。 +* +* 修改记录 : +* 版本号 日期 作者 说明 +* v0.1 2009-12-27 armfly 创建该文件，ST固件库版本为V3.1.2 +* v1.0 2011-01-11 armfly ST固件库升级到V3.4.0版本。 +* v2.0 2011-10-16 armfly ST固件库升级到V3.5.0版本。 +* V2.1 2015-08-07 armfly 在异常中断那服务器程序中驱动蜂鸣器发声，提示有问题了 +* +* Copyright (C), 2010-2011, 安富莱电子 www.armfly.com +* +********************************************************************************************************* +*/ + +#include "stm32f10x_it.h" + +#define ERR_INFO "\r\nEnter HardFault_Handler, System Halt.\r\n" + +/* +********************************************************************************************************* +* Cortex-M3 内核异常中断服务程序 +********************************************************************************************************* +*/ + +/* +********************************************************************************************************* +* 函 数 名: NMI_Handler +* 功能说明: 不可屏蔽中断服务程序。 +* 形 参：无 +* 返 回 值: 无 +********************************************************************************************************* +*/ +void NMI_Handler(void) +{ +} + +/* +********************************************************************************************************* +* 函 数 名: HardFault_Handler +* 功能说明: 硬件失效中断服务程序。 +* 形 参：无 +* 返 回 值: 无 +********************************************************************************************************* +*/ +void HardFault_Handler(void) +{ +#if 0 + const char *pError = ERR_INFO; + uint8_t i; + + for (i = 0; i < sizeof(ERR_INFO); i++) + { + USART1->DR = pError[i]; + /* 等待发送结束 */ + while ((USART1->SR & USART_FLAG_TC) == (uint16_t)RESET); + } +#endif + +#if 0 /* 出现异常时，驱动蜂鸣器发声 */ + while(1) + { + uint16_t m; + + GPIOA->ODR ^= GPIO_Pin_8; + + for (m = 0; m < 10000; m++); + } +#else + + /* 当硬件失效异常发生时进入死循环 */ + while (1) + { + } +#endif +} + +/* +********************************************************************************************************* +* 函 数 名: MemManage_Handler +* 功能说明: 内存管理异常中断服务程序。 +* 形 参：无 +* 返 回 值: 无 +********************************************************************************************************* +*/ +void MemManage_Handler(void) +{ + /* 当内存管理异常发生时进入死循环 */ + while (1) + { + } +} + +/* +********************************************************************************************************* +* 函 数 名: BusFault_Handler +* 功能说明: 总线访问异常中断服务程序。 +* 形 参：无 +* 返 回 值: 无 +********************************************************************************************************* +*/ +void BusFault_Handler(void) +{ + /* 当总线异常时进入死循环 */ + while (1) + { + } +} + +/* +********************************************************************************************************* +* 函 数 名: UsageFault_Handler +* 功能说明: 未定义的指令或非法状态中断服务程序。 +* 形 参：无 +* 返 回 值: 无 +********************************************************************************************************* +*/ +void UsageFault_Handler(void) +{ + /* 当用法异常时进入死循环 */ + while (1) + { + } +} + +/* +********************************************************************************************************* +* 函 数 名: SVC_Handler +* 功能说明: 通过SWI指令的系统服务调用中断服务程序。 +* 形 参：无 +* 返 回 值: 无 +********************************************************************************************************* +*/ +void SVC_Handler(void) +{ +} + +/* +********************************************************************************************************* +* 函 数 名: DebugMon_Handler +* 功能说明: 调试监视器中断服务程序。 +* 形 参：无 +* 返 回 值: 无 +********************************************************************************************************* +*/ +void DebugMon_Handler(void) +{ +} + +/* +********************************************************************************************************* +* 函 数 名: PendSV_Handler +* 功能说明: 可挂起的系统服务调用中断服务程序。 +* 形 参：无 +* 返 回 值: 无 +********************************************************************************************************* +*/ +void PendSV_Handler(void) +{ +} + +/* +********************************************************************************************************* +* STM32F10x内部外设中断服务程序 +* 用户在此添加用到外设中断服务函数。有效的中断服务函数名请参考启动文件(startup_stm32f10x_xx.s) +********************************************************************************************************* +*/ + +/* +********************************************************************************************************* +* 函 数 名: PPP_IRQHandler +* 功能说明: 外设中断服务程序。 +* 形 参：无 +* 返 回 值: 无 +********************************************************************************************************* +*/ +/* + 因为中断服务程序往往和具体的应用有关，会用到用户功能模块的变量、函数。如果在本文件展开，会增加大量的 + 外部变量声明或者include语句。 + + 因此，我们推荐这个地方只写一个调用语句，中断服务函数的本体放到对应的用户功能模块中。 + 增加一层调用会降低代码的执行效率，不过我们宁愿损失这个效率，从而增强程序的模块化特性。 + + 增加extern关键字，直接引用用到的外部函数，避免在文件头include其他模块的头文件 +extern void ppp_ISR(void); +void PPP_IRQHandler(void) +{ + ppp_ISR(); +} +*/ +extern void can_ISR(void); +extern void USB_Istr(void); +void USB_LP_CAN1_RX0_IRQHandler(void) +{ + /* 判断CAN1的时钟是否打开 */ + if (RCC->APB1ENR & RCC_APB1Periph_CAN1) + { + } + else + { + } +} + +/***************************** 安富莱电子 www.armfly.com (END OF FILE) *********************************/ diff --git a/User/bsp/stm32f10x_it.h b/User/bsp/stm32f10x_it.h new file mode 100644 index 0000000..1e5f9aa --- /dev/null +++ b/User/bsp/stm32f10x_it.h @@ -0,0 +1,35 @@ +/* +********************************************************************************************************* +* +* ģ : жģ +* ļ : stm32f10x_it.h +* : V2.0 +* ˵ : ͷļ +* ޸ļ¼ : +* 汾 ˵ +* v1.0 2011-05-13 armfly ST̼V3.4.0汾 +* v2.0 2011-10-16 armfly ST̼V3.5.0汾 +* +* Copyright (C), 2010-2011, www.armfly.com +* +********************************************************************************************************* +*/ + +#ifndef __STM32F10x_IT_H +#define __STM32F10x_IT_H + +#include "stm32f10x.h" + +void NMI_Handler(void); +void HardFault_Handler(void); +void MemManage_Handler(void); +void BusFault_Handler(void); +void UsageFault_Handler(void); +void SVC_Handler(void); +void DebugMon_Handler(void); +void PendSV_Handler(void); +void SysTick_Handler(void); + +#endif + + diff --git a/User/bsp/system_stm32f10x.c b/User/bsp/system_stm32f10x.c new file mode 100644 index 0000000..656da89 --- /dev/null +++ b/User/bsp/system_stm32f10x.c @@ -0,0 +1,1094 @@ +/** + ****************************************************************************** + * @file system_stm32f10x.c + * @author MCD Application Team + * @version V3.5.0 + * @date 11-March-2011 + * @brief CMSIS Cortex-M3 Device Peripheral Access Layer System Source File. + * + * 1. This file provides two functions and one global variable to be called from + * user application: + * - SystemInit(): Setups the system clock (System clock source, PLL Multiplier + * factors, AHB/APBx prescalers and Flash settings). + * This function is called at startup just after reset and + * before branch to main program. This call is made inside + * the "startup_stm32f10x_xx.s" file. + * + * - SystemCoreClock variable: Contains the core clock (HCLK), it can be used + * by the user application to setup the SysTick + * timer or configure other parameters. + * + * - SystemCoreClockUpdate(): Updates the variable SystemCoreClock and must + * be called whenever the core clock is changed + * during program execution. + * + * 2. After each device reset the HSI (8 MHz) is used as system clock source. + * Then SystemInit() function is called, in "startup_stm32f10x_xx.s" file, to + * configure the system clock before to branch to main program. + * + * 3. If the system clock source selected by user fails to startup, the SystemInit() + * function will do nothing and HSI still used as system clock source. User can + * add some code to deal with this issue inside the SetSysClock() function. + * + * 4. The default value of HSE crystal is set to 8 MHz (or 25 MHz, depedning on + * the product used), refer to "HSE_VALUE" define in "stm32f10x.h" file. + * When HSE is used as system clock source, directly or through PLL, and you + * are using different crystal you have to adapt the HSE value to your own + * configuration. + * + ****************************************************************************** + * @attention + * + * THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS + * WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE + * TIME. AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY + * DIRECT, INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING + * FROM THE CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE + * CODING INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS. + * + *

    © COPYRIGHT 2011 STMicroelectronics

    + ****************************************************************************** + */ + +/** @addtogroup CMSIS + * @{ + */ + +/** @addtogroup stm32f10x_system + * @{ + */ + +/** @addtogroup STM32F10x_System_Private_Includes + * @{ + */ + +#include "stm32f10x.h" + +/** + * @} + */ + +/** @addtogroup STM32F10x_System_Private_TypesDefinitions + * @{ + */ + +/** + * @} + */ + +/** @addtogroup STM32F10x_System_Private_Defines + * @{ + */ + +/*!< Uncomment the line corresponding to the desired System clock (SYSCLK) + frequency (after reset the HSI is used as SYSCLK source) + + IMPORTANT NOTE: + ============== + 1. After each device reset the HSI is used as System clock source. + + 2. Please make sure that the selected System clock doesn't exceed your device's + maximum frequency. + + 3. If none of the define below is enabled, the HSI is used as System clock + source. + + 4. The System clock configuration functions provided within this file assume that: + - For Low, Medium and High density Value line devices an external 8MHz + crystal is used to drive the System clock. + - For Low, Medium and High density devices an external 8MHz crystal is + used to drive the System clock. + - For Connectivity line devices an external 25MHz crystal is used to drive + the System clock. + If you are using different crystal you have to adapt those functions accordingly. + */ + +#if defined (STM32F10X_LD_VL) || (defined STM32F10X_MD_VL) || (defined STM32F10X_HD_VL) +/* #define SYSCLK_FREQ_HSE HSE_VALUE */ + #define SYSCLK_FREQ_24MHz 24000000 +#else +/* #define SYSCLK_FREQ_HSE HSE_VALUE */ +/* #define SYSCLK_FREQ_24MHz 24000000 */ +/* #define SYSCLK_FREQ_36MHz 36000000 */ +/* #define SYSCLK_FREQ_48MHz 48000000 */ +/* #define SYSCLK_FREQ_56MHz 56000000 */ +#define SYSCLK_FREQ_72MHz 72000000 +#endif + +/*!< Uncomment the following line if you need to use external SRAM mounted + on STM3210E-EVAL board (STM32 High density and XL-density devices) or on + STM32100E-EVAL board (STM32 High-density value line devices) as data memory */ +#if defined (STM32F10X_HD) || (defined STM32F10X_XL) || (defined STM32F10X_HD_VL) +/* #define DATA_IN_ExtSRAM */ +#endif + +/*!< Uncomment the following line if you need to relocate your vector Table in + Internal SRAM. */ +/* #define VECT_TAB_SRAM */ +#define VECT_TAB_OFFSET 0x0 /*!< Vector Table base offset field. + This value must be a multiple of 0x200. */ + + +/** + * @} + */ + +/** @addtogroup STM32F10x_System_Private_Macros + * @{ + */ + +/** + * @} + */ + +/** @addtogroup STM32F10x_System_Private_Variables + * @{ + */ + +/******************************************************************************* +* Clock Definitions +*******************************************************************************/ +#ifdef SYSCLK_FREQ_HSE + uint32_t SystemCoreClock = SYSCLK_FREQ_HSE; /*!< System Clock Frequency (Core Clock) */ +#elif defined SYSCLK_FREQ_24MHz + uint32_t SystemCoreClock = SYSCLK_FREQ_24MHz; /*!< System Clock Frequency (Core Clock) */ +#elif defined SYSCLK_FREQ_36MHz + uint32_t SystemCoreClock = SYSCLK_FREQ_36MHz; /*!< System Clock Frequency (Core Clock) */ +#elif defined SYSCLK_FREQ_48MHz + uint32_t SystemCoreClock = SYSCLK_FREQ_48MHz; /*!< System Clock Frequency (Core Clock) */ +#elif defined SYSCLK_FREQ_56MHz + uint32_t SystemCoreClock = SYSCLK_FREQ_56MHz; /*!< System Clock Frequency (Core Clock) */ +#elif defined SYSCLK_FREQ_72MHz + uint32_t SystemCoreClock = SYSCLK_FREQ_72MHz; /*!< System Clock Frequency (Core Clock) */ +#else /*!< HSI Selected as System Clock source */ + uint32_t SystemCoreClock = HSI_VALUE; /*!< System Clock Frequency (Core Clock) */ +#endif + +__I uint8_t AHBPrescTable[16] = {0, 0, 0, 0, 0, 0, 0, 0, 1, 2, 3, 4, 6, 7, 8, 9}; +/** + * @} + */ + +/** @addtogroup STM32F10x_System_Private_FunctionPrototypes + * @{ + */ + +static void SetSysClock(void); + +#ifdef SYSCLK_FREQ_HSE + static void SetSysClockToHSE(void); +#elif defined SYSCLK_FREQ_24MHz + static void SetSysClockTo24(void); +#elif defined SYSCLK_FREQ_36MHz + static void SetSysClockTo36(void); +#elif defined SYSCLK_FREQ_48MHz + static void SetSysClockTo48(void); +#elif defined SYSCLK_FREQ_56MHz + static void SetSysClockTo56(void); +#elif defined SYSCLK_FREQ_72MHz + static void SetSysClockTo72(void); +#endif + +#ifdef DATA_IN_ExtSRAM + static void SystemInit_ExtMemCtl(void); +#endif /* DATA_IN_ExtSRAM */ + +/** + * @} + */ + +/** @addtogroup STM32F10x_System_Private_Functions + * @{ + */ + +/** + * @brief Setup the microcontroller system + * Initialize the Embedded Flash Interface, the PLL and update the + * SystemCoreClock variable. + * @note This function should be used only after reset. + * @param None + * @retval None + */ +void SystemInit (void) +{ + /* Reset the RCC clock configuration to the default reset state(for debug purpose) */ + /* Set HSION bit */ + RCC->CR |= (uint32_t)0x00000001; + + /* Reset SW, HPRE, PPRE1, PPRE2, ADCPRE and MCO bits */ +#ifndef STM32F10X_CL + RCC->CFGR &= (uint32_t)0xF8FF0000; +#else + RCC->CFGR &= (uint32_t)0xF0FF0000; +#endif /* STM32F10X_CL */ + + /* Reset HSEON, CSSON and PLLON bits */ + RCC->CR &= (uint32_t)0xFEF6FFFF; + + /* Reset HSEBYP bit */ + RCC->CR &= (uint32_t)0xFFFBFFFF; + + /* Reset PLLSRC, PLLXTPRE, PLLMUL and USBPRE/OTGFSPRE bits */ + RCC->CFGR &= (uint32_t)0xFF80FFFF; + +#ifdef STM32F10X_CL + /* Reset PLL2ON and PLL3ON bits */ + RCC->CR &= (uint32_t)0xEBFFFFFF; + + /* Disable all interrupts and clear pending bits */ + RCC->CIR = 0x00FF0000; + + /* Reset CFGR2 register */ + RCC->CFGR2 = 0x00000000; +#elif defined (STM32F10X_LD_VL) || defined (STM32F10X_MD_VL) || (defined STM32F10X_HD_VL) + /* Disable all interrupts and clear pending bits */ + RCC->CIR = 0x009F0000; + + /* Reset CFGR2 register */ + RCC->CFGR2 = 0x00000000; +#else + /* Disable all interrupts and clear pending bits */ + RCC->CIR = 0x009F0000; +#endif /* STM32F10X_CL */ + +#if defined (STM32F10X_HD) || (defined STM32F10X_XL) || (defined STM32F10X_HD_VL) + #ifdef DATA_IN_ExtSRAM + SystemInit_ExtMemCtl(); + #endif /* DATA_IN_ExtSRAM */ +#endif + + /* Configure the System clock frequency, HCLK, PCLK2 and PCLK1 prescalers */ + /* Configure the Flash Latency cycles and enable prefetch buffer */ + SetSysClock(); + +#ifdef VECT_TAB_SRAM + SCB->VTOR = SRAM_BASE | VECT_TAB_OFFSET; /* Vector Table Relocation in Internal SRAM. */ +#else + SCB->VTOR = FLASH_BASE | VECT_TAB_OFFSET; /* Vector Table Relocation in Internal FLASH. */ +#endif +} + +/** + * @brief Update SystemCoreClock variable according to Clock Register Values. + * The SystemCoreClock variable contains the core clock (HCLK), it can + * be used by the user application to setup the SysTick timer or configure + * other parameters. + * + * @note Each time the core clock (HCLK) changes, this function must be called + * to update SystemCoreClock variable value. Otherwise, any configuration + * based on this variable will be incorrect. + * + * @note - The system frequency computed by this function is not the real + * frequency in the chip. It is calculated based on the predefined + * constant and the selected clock source: + * + * - If SYSCLK source is HSI, SystemCoreClock will contain the HSI_VALUE(*) + * + * - If SYSCLK source is HSE, SystemCoreClock will contain the HSE_VALUE(**) + * + * - If SYSCLK source is PLL, SystemCoreClock will contain the HSE_VALUE(**) + * or HSI_VALUE(*) multiplied by the PLL factors. + * + * (*) HSI_VALUE is a constant defined in stm32f1xx.h file (default value + * 8 MHz) but the real value may vary depending on the variations + * in voltage and temperature. + * + * (**) HSE_VALUE is a constant defined in stm32f1xx.h file (default value + * 8 MHz or 25 MHz, depedning on the product used), user has to ensure + * that HSE_VALUE is same as the real frequency of the crystal used. + * Otherwise, this function may have wrong result. + * + * - The result of this function could be not correct when using fractional + * value for HSE crystal. + * @param None + * @retval None + */ +void SystemCoreClockUpdate (void) +{ + uint32_t tmp = 0, pllmull = 0, pllsource = 0; + +#ifdef STM32F10X_CL + uint32_t prediv1source = 0, prediv1factor = 0, prediv2factor = 0, pll2mull = 0; +#endif /* STM32F10X_CL */ + +#if defined (STM32F10X_LD_VL) || defined (STM32F10X_MD_VL) || (defined STM32F10X_HD_VL) + uint32_t prediv1factor = 0; +#endif /* STM32F10X_LD_VL or STM32F10X_MD_VL or STM32F10X_HD_VL */ + + /* Get SYSCLK source -------------------------------------------------------*/ + tmp = RCC->CFGR & RCC_CFGR_SWS; + + switch (tmp) + { + case 0x00: /* HSI used as system clock */ + SystemCoreClock = HSI_VALUE; + break; + case 0x04: /* HSE used as system clock */ + SystemCoreClock = HSE_VALUE; + break; + case 0x08: /* PLL used as system clock */ + + /* Get PLL clock source and multiplication factor ----------------------*/ + pllmull = RCC->CFGR & RCC_CFGR_PLLMULL; + pllsource = RCC->CFGR & RCC_CFGR_PLLSRC; + +#ifndef STM32F10X_CL + pllmull = ( pllmull >> 18) + 2; + + if (pllsource == 0x00) + { + /* HSI oscillator clock divided by 2 selected as PLL clock entry */ + SystemCoreClock = (HSI_VALUE >> 1) * pllmull; + } + else + { + #if defined (STM32F10X_LD_VL) || defined (STM32F10X_MD_VL) || (defined STM32F10X_HD_VL) + prediv1factor = (RCC->CFGR2 & RCC_CFGR2_PREDIV1) + 1; + /* HSE oscillator clock selected as PREDIV1 clock entry */ + SystemCoreClock = (HSE_VALUE / prediv1factor) * pllmull; + #else + /* HSE selected as PLL clock entry */ + if ((RCC->CFGR & RCC_CFGR_PLLXTPRE) != (uint32_t)RESET) + {/* HSE oscillator clock divided by 2 */ + SystemCoreClock = (HSE_VALUE >> 1) * pllmull; + } + else + { + SystemCoreClock = HSE_VALUE * pllmull; + } + #endif + } +#else + pllmull = pllmull >> 18; + + if (pllmull != 0x0D) + { + pllmull += 2; + } + else + { /* PLL multiplication factor = PLL input clock * 6.5 */ + pllmull = 13 / 2; + } + + if (pllsource == 0x00) + { + /* HSI oscillator clock divided by 2 selected as PLL clock entry */ + SystemCoreClock = (HSI_VALUE >> 1) * pllmull; + } + else + {/* PREDIV1 selected as PLL clock entry */ + + /* Get PREDIV1 clock source and division factor */ + prediv1source = RCC->CFGR2 & RCC_CFGR2_PREDIV1SRC; + prediv1factor = (RCC->CFGR2 & RCC_CFGR2_PREDIV1) + 1; + + if (prediv1source == 0) + { + /* HSE oscillator clock selected as PREDIV1 clock entry */ + SystemCoreClock = (HSE_VALUE / prediv1factor) * pllmull; + } + else + {/* PLL2 clock selected as PREDIV1 clock entry */ + + /* Get PREDIV2 division factor and PLL2 multiplication factor */ + prediv2factor = ((RCC->CFGR2 & RCC_CFGR2_PREDIV2) >> 4) + 1; + pll2mull = ((RCC->CFGR2 & RCC_CFGR2_PLL2MUL) >> 8 ) + 2; + SystemCoreClock = (((HSE_VALUE / prediv2factor) * pll2mull) / prediv1factor) * pllmull; + } + } +#endif /* STM32F10X_CL */ + break; + + default: + SystemCoreClock = HSI_VALUE; + break; + } + + /* Compute HCLK clock frequency ----------------*/ + /* Get HCLK prescaler */ + tmp = AHBPrescTable[((RCC->CFGR & RCC_CFGR_HPRE) >> 4)]; + /* HCLK clock frequency */ + SystemCoreClock >>= tmp; +} + +/** + * @brief Configures the System clock frequency, HCLK, PCLK2 and PCLK1 prescalers. + * @param None + * @retval None + */ +static void SetSysClock(void) +{ +#ifdef SYSCLK_FREQ_HSE + SetSysClockToHSE(); +#elif defined SYSCLK_FREQ_24MHz + SetSysClockTo24(); +#elif defined SYSCLK_FREQ_36MHz + SetSysClockTo36(); +#elif defined SYSCLK_FREQ_48MHz + SetSysClockTo48(); +#elif defined SYSCLK_FREQ_56MHz + SetSysClockTo56(); +#elif defined SYSCLK_FREQ_72MHz + SetSysClockTo72(); +#endif + + /* If none of the define above is enabled, the HSI is used as System clock + source (default after reset) */ +} + +/** + * @brief Setup the external memory controller. Called in startup_stm32f10x.s + * before jump to __main + * @param None + * @retval None + */ +#ifdef DATA_IN_ExtSRAM +/** + * @brief Setup the external memory controller. + * Called in startup_stm32f10x_xx.s/.c before jump to main. + * This function configures the external SRAM mounted on STM3210E-EVAL + * board (STM32 High density devices). This SRAM will be used as program + * data memory (including heap and stack). + * @param None + * @retval None + */ +void SystemInit_ExtMemCtl(void) +{ +/*!< FSMC Bank1 NOR/SRAM3 is used for the STM3210E-EVAL, if another Bank is + required, then adjust the Register Addresses */ + + /* Enable FSMC clock */ + RCC->AHBENR = 0x00000114; + + /* Enable GPIOD, GPIOE, GPIOF and GPIOG clocks */ + RCC->APB2ENR = 0x000001E0; + +/* --------------- SRAM Data lines, NOE and NWE configuration ---------------*/ +/*---------------- SRAM Address lines configuration -------------------------*/ +/*---------------- NOE and NWE configuration --------------------------------*/ +/*---------------- NE3 configuration ----------------------------------------*/ +/*---------------- NBL0, NBL1 configuration ---------------------------------*/ + + GPIOD->CRL = 0x44BB44BB; + GPIOD->CRH = 0xBBBBBBBB; + + GPIOE->CRL = 0xB44444BB; + GPIOE->CRH = 0xBBBBBBBB; + + GPIOF->CRL = 0x44BBBBBB; + GPIOF->CRH = 0xBBBB4444; + + GPIOG->CRL = 0x44BBBBBB; + GPIOG->CRH = 0x44444B44; + +/*---------------- FSMC Configuration ---------------------------------------*/ +/*---------------- Enable FSMC Bank1_SRAM Bank ------------------------------*/ + + FSMC_Bank1->BTCR[4] = 0x00001011; + FSMC_Bank1->BTCR[5] = 0x00000200; +} +#endif /* DATA_IN_ExtSRAM */ + +#ifdef SYSCLK_FREQ_HSE +/** + * @brief Selects HSE as System clock source and configure HCLK, PCLK2 + * and PCLK1 prescalers. + * @note This function should be used only after reset. + * @param None + * @retval None + */ +static void SetSysClockToHSE(void) +{ + __IO uint32_t StartUpCounter = 0, HSEStatus = 0; + + /* SYSCLK, HCLK, PCLK2 and PCLK1 configuration ---------------------------*/ + /* Enable HSE */ + RCC->CR |= ((uint32_t)RCC_CR_HSEON); + + /* Wait till HSE is ready and if Time out is reached exit */ + do + { + HSEStatus = RCC->CR & RCC_CR_HSERDY; + StartUpCounter++; + } while((HSEStatus == 0) && (StartUpCounter != HSE_STARTUP_TIMEOUT)); + + if ((RCC->CR & RCC_CR_HSERDY) != RESET) + { + HSEStatus = (uint32_t)0x01; + } + else + { + HSEStatus = (uint32_t)0x00; + } + + if (HSEStatus == (uint32_t)0x01) + { + +#if !defined STM32F10X_LD_VL && !defined STM32F10X_MD_VL && !defined STM32F10X_HD_VL + /* Enable Prefetch Buffer */ + FLASH->ACR |= FLASH_ACR_PRFTBE; + + /* Flash 0 wait state */ + FLASH->ACR &= (uint32_t)((uint32_t)~FLASH_ACR_LATENCY); + +#ifndef STM32F10X_CL + FLASH->ACR |= (uint32_t)FLASH_ACR_LATENCY_0; +#else + if (HSE_VALUE <= 24000000) + { + FLASH->ACR |= (uint32_t)FLASH_ACR_LATENCY_0; + } + else + { + FLASH->ACR |= (uint32_t)FLASH_ACR_LATENCY_1; + } +#endif /* STM32F10X_CL */ +#endif + + /* HCLK = SYSCLK */ + RCC->CFGR |= (uint32_t)RCC_CFGR_HPRE_DIV1; + + /* PCLK2 = HCLK */ + RCC->CFGR |= (uint32_t)RCC_CFGR_PPRE2_DIV1; + + /* PCLK1 = HCLK */ + RCC->CFGR |= (uint32_t)RCC_CFGR_PPRE1_DIV1; + + /* Select HSE as system clock source */ + RCC->CFGR &= (uint32_t)((uint32_t)~(RCC_CFGR_SW)); + RCC->CFGR |= (uint32_t)RCC_CFGR_SW_HSE; + + /* Wait till HSE is used as system clock source */ + while ((RCC->CFGR & (uint32_t)RCC_CFGR_SWS) != (uint32_t)0x04) + { + } + } + else + { /* If HSE fails to start-up, the application will have wrong clock + configuration. User can add here some code to deal with this error */ + } +} +#elif defined SYSCLK_FREQ_24MHz +/** + * @brief Sets System clock frequency to 24MHz and configure HCLK, PCLK2 + * and PCLK1 prescalers. + * @note This function should be used only after reset. + * @param None + * @retval None + */ +static void SetSysClockTo24(void) +{ + __IO uint32_t StartUpCounter = 0, HSEStatus = 0; + + /* SYSCLK, HCLK, PCLK2 and PCLK1 configuration ---------------------------*/ + /* Enable HSE */ + RCC->CR |= ((uint32_t)RCC_CR_HSEON); + + /* Wait till HSE is ready and if Time out is reached exit */ + do + { + HSEStatus = RCC->CR & RCC_CR_HSERDY; + StartUpCounter++; + } while((HSEStatus == 0) && (StartUpCounter != HSE_STARTUP_TIMEOUT)); + + if ((RCC->CR & RCC_CR_HSERDY) != RESET) + { + HSEStatus = (uint32_t)0x01; + } + else + { + HSEStatus = (uint32_t)0x00; + } + + if (HSEStatus == (uint32_t)0x01) + { +#if !defined STM32F10X_LD_VL && !defined STM32F10X_MD_VL && !defined STM32F10X_HD_VL + /* Enable Prefetch Buffer */ + FLASH->ACR |= FLASH_ACR_PRFTBE; + + /* Flash 0 wait state */ + FLASH->ACR &= (uint32_t)((uint32_t)~FLASH_ACR_LATENCY); + FLASH->ACR |= (uint32_t)FLASH_ACR_LATENCY_0; +#endif + + /* HCLK = SYSCLK */ + RCC->CFGR |= (uint32_t)RCC_CFGR_HPRE_DIV1; + + /* PCLK2 = HCLK */ + RCC->CFGR |= (uint32_t)RCC_CFGR_PPRE2_DIV1; + + /* PCLK1 = HCLK */ + RCC->CFGR |= (uint32_t)RCC_CFGR_PPRE1_DIV1; + +#ifdef STM32F10X_CL + /* Configure PLLs ------------------------------------------------------*/ + /* PLL configuration: PLLCLK = PREDIV1 * 6 = 24 MHz */ + RCC->CFGR &= (uint32_t)~(RCC_CFGR_PLLXTPRE | RCC_CFGR_PLLSRC | RCC_CFGR_PLLMULL); + RCC->CFGR |= (uint32_t)(RCC_CFGR_PLLXTPRE_PREDIV1 | RCC_CFGR_PLLSRC_PREDIV1 | + RCC_CFGR_PLLMULL6); + + /* PLL2 configuration: PLL2CLK = (HSE / 5) * 8 = 40 MHz */ + /* PREDIV1 configuration: PREDIV1CLK = PLL2 / 10 = 4 MHz */ + RCC->CFGR2 &= (uint32_t)~(RCC_CFGR2_PREDIV2 | RCC_CFGR2_PLL2MUL | + RCC_CFGR2_PREDIV1 | RCC_CFGR2_PREDIV1SRC); + RCC->CFGR2 |= (uint32_t)(RCC_CFGR2_PREDIV2_DIV5 | RCC_CFGR2_PLL2MUL8 | + RCC_CFGR2_PREDIV1SRC_PLL2 | RCC_CFGR2_PREDIV1_DIV10); + + /* Enable PLL2 */ + RCC->CR |= RCC_CR_PLL2ON; + /* Wait till PLL2 is ready */ + while((RCC->CR & RCC_CR_PLL2RDY) == 0) + { + } +#elif defined (STM32F10X_LD_VL) || defined (STM32F10X_MD_VL) || defined (STM32F10X_HD_VL) + /* PLL configuration: = (HSE / 2) * 6 = 24 MHz */ + RCC->CFGR &= (uint32_t)((uint32_t)~(RCC_CFGR_PLLSRC | RCC_CFGR_PLLXTPRE | RCC_CFGR_PLLMULL)); + RCC->CFGR |= (uint32_t)(RCC_CFGR_PLLSRC_PREDIV1 | RCC_CFGR_PLLXTPRE_PREDIV1_Div2 | RCC_CFGR_PLLMULL6); +#else + /* PLL configuration: = (HSE / 2) * 6 = 24 MHz */ + RCC->CFGR &= (uint32_t)((uint32_t)~(RCC_CFGR_PLLSRC | RCC_CFGR_PLLXTPRE | RCC_CFGR_PLLMULL)); + RCC->CFGR |= (uint32_t)(RCC_CFGR_PLLSRC_HSE | RCC_CFGR_PLLXTPRE_HSE_Div2 | RCC_CFGR_PLLMULL6); +#endif /* STM32F10X_CL */ + + /* Enable PLL */ + RCC->CR |= RCC_CR_PLLON; + + /* Wait till PLL is ready */ + while((RCC->CR & RCC_CR_PLLRDY) == 0) + { + } + + /* Select PLL as system clock source */ + RCC->CFGR &= (uint32_t)((uint32_t)~(RCC_CFGR_SW)); + RCC->CFGR |= (uint32_t)RCC_CFGR_SW_PLL; + + /* Wait till PLL is used as system clock source */ + while ((RCC->CFGR & (uint32_t)RCC_CFGR_SWS) != (uint32_t)0x08) + { + } + } + else + { /* If HSE fails to start-up, the application will have wrong clock + configuration. User can add here some code to deal with this error */ + } +} +#elif defined SYSCLK_FREQ_36MHz +/** + * @brief Sets System clock frequency to 36MHz and configure HCLK, PCLK2 + * and PCLK1 prescalers. + * @note This function should be used only after reset. + * @param None + * @retval None + */ +static void SetSysClockTo36(void) +{ + __IO uint32_t StartUpCounter = 0, HSEStatus = 0; + + /* SYSCLK, HCLK, PCLK2 and PCLK1 configuration ---------------------------*/ + /* Enable HSE */ + RCC->CR |= ((uint32_t)RCC_CR_HSEON); + + /* Wait till HSE is ready and if Time out is reached exit */ + do + { + HSEStatus = RCC->CR & RCC_CR_HSERDY; + StartUpCounter++; + } while((HSEStatus == 0) && (StartUpCounter != HSE_STARTUP_TIMEOUT)); + + if ((RCC->CR & RCC_CR_HSERDY) != RESET) + { + HSEStatus = (uint32_t)0x01; + } + else + { + HSEStatus = (uint32_t)0x00; + } + + if (HSEStatus == (uint32_t)0x01) + { + /* Enable Prefetch Buffer */ + FLASH->ACR |= FLASH_ACR_PRFTBE; + + /* Flash 1 wait state */ + FLASH->ACR &= (uint32_t)((uint32_t)~FLASH_ACR_LATENCY); + FLASH->ACR |= (uint32_t)FLASH_ACR_LATENCY_1; + + /* HCLK = SYSCLK */ + RCC->CFGR |= (uint32_t)RCC_CFGR_HPRE_DIV1; + + /* PCLK2 = HCLK */ + RCC->CFGR |= (uint32_t)RCC_CFGR_PPRE2_DIV1; + + /* PCLK1 = HCLK */ + RCC->CFGR |= (uint32_t)RCC_CFGR_PPRE1_DIV1; + +#ifdef STM32F10X_CL + /* Configure PLLs ------------------------------------------------------*/ + + /* PLL configuration: PLLCLK = PREDIV1 * 9 = 36 MHz */ + RCC->CFGR &= (uint32_t)~(RCC_CFGR_PLLXTPRE | RCC_CFGR_PLLSRC | RCC_CFGR_PLLMULL); + RCC->CFGR |= (uint32_t)(RCC_CFGR_PLLXTPRE_PREDIV1 | RCC_CFGR_PLLSRC_PREDIV1 | + RCC_CFGR_PLLMULL9); + + /*!< PLL2 configuration: PLL2CLK = (HSE / 5) * 8 = 40 MHz */ + /* PREDIV1 configuration: PREDIV1CLK = PLL2 / 10 = 4 MHz */ + + RCC->CFGR2 &= (uint32_t)~(RCC_CFGR2_PREDIV2 | RCC_CFGR2_PLL2MUL | + RCC_CFGR2_PREDIV1 | RCC_CFGR2_PREDIV1SRC); + RCC->CFGR2 |= (uint32_t)(RCC_CFGR2_PREDIV2_DIV5 | RCC_CFGR2_PLL2MUL8 | + RCC_CFGR2_PREDIV1SRC_PLL2 | RCC_CFGR2_PREDIV1_DIV10); + + /* Enable PLL2 */ + RCC->CR |= RCC_CR_PLL2ON; + /* Wait till PLL2 is ready */ + while((RCC->CR & RCC_CR_PLL2RDY) == 0) + { + } + +#else + /* PLL configuration: PLLCLK = (HSE / 2) * 9 = 36 MHz */ + RCC->CFGR &= (uint32_t)((uint32_t)~(RCC_CFGR_PLLSRC | RCC_CFGR_PLLXTPRE | RCC_CFGR_PLLMULL)); + RCC->CFGR |= (uint32_t)(RCC_CFGR_PLLSRC_HSE | RCC_CFGR_PLLXTPRE_HSE_Div2 | RCC_CFGR_PLLMULL9); +#endif /* STM32F10X_CL */ + + /* Enable PLL */ + RCC->CR |= RCC_CR_PLLON; + + /* Wait till PLL is ready */ + while((RCC->CR & RCC_CR_PLLRDY) == 0) + { + } + + /* Select PLL as system clock source */ + RCC->CFGR &= (uint32_t)((uint32_t)~(RCC_CFGR_SW)); + RCC->CFGR |= (uint32_t)RCC_CFGR_SW_PLL; + + /* Wait till PLL is used as system clock source */ + while ((RCC->CFGR & (uint32_t)RCC_CFGR_SWS) != (uint32_t)0x08) + { + } + } + else + { /* If HSE fails to start-up, the application will have wrong clock + configuration. User can add here some code to deal with this error */ + } +} +#elif defined SYSCLK_FREQ_48MHz +/** + * @brief Sets System clock frequency to 48MHz and configure HCLK, PCLK2 + * and PCLK1 prescalers. + * @note This function should be used only after reset. + * @param None + * @retval None + */ +static void SetSysClockTo48(void) +{ + __IO uint32_t StartUpCounter = 0, HSEStatus = 0; + + /* SYSCLK, HCLK, PCLK2 and PCLK1 configuration ---------------------------*/ + /* Enable HSE */ + RCC->CR |= ((uint32_t)RCC_CR_HSEON); + + /* Wait till HSE is ready and if Time out is reached exit */ + do + { + HSEStatus = RCC->CR & RCC_CR_HSERDY; + StartUpCounter++; + } while((HSEStatus == 0) && (StartUpCounter != HSE_STARTUP_TIMEOUT)); + + if ((RCC->CR & RCC_CR_HSERDY) != RESET) + { + HSEStatus = (uint32_t)0x01; + } + else + { + HSEStatus = (uint32_t)0x00; + } + + if (HSEStatus == (uint32_t)0x01) + { + /* Enable Prefetch Buffer */ + FLASH->ACR |= FLASH_ACR_PRFTBE; + + /* Flash 1 wait state */ + FLASH->ACR &= (uint32_t)((uint32_t)~FLASH_ACR_LATENCY); + FLASH->ACR |= (uint32_t)FLASH_ACR_LATENCY_1; + + /* HCLK = SYSCLK */ + RCC->CFGR |= (uint32_t)RCC_CFGR_HPRE_DIV1; + + /* PCLK2 = HCLK */ + RCC->CFGR |= (uint32_t)RCC_CFGR_PPRE2_DIV1; + + /* PCLK1 = HCLK */ + RCC->CFGR |= (uint32_t)RCC_CFGR_PPRE1_DIV2; + +#ifdef STM32F10X_CL + /* Configure PLLs ------------------------------------------------------*/ + /* PLL2 configuration: PLL2CLK = (HSE / 5) * 8 = 40 MHz */ + /* PREDIV1 configuration: PREDIV1CLK = PLL2 / 5 = 8 MHz */ + + RCC->CFGR2 &= (uint32_t)~(RCC_CFGR2_PREDIV2 | RCC_CFGR2_PLL2MUL | + RCC_CFGR2_PREDIV1 | RCC_CFGR2_PREDIV1SRC); + RCC->CFGR2 |= (uint32_t)(RCC_CFGR2_PREDIV2_DIV5 | RCC_CFGR2_PLL2MUL8 | + RCC_CFGR2_PREDIV1SRC_PLL2 | RCC_CFGR2_PREDIV1_DIV5); + + /* Enable PLL2 */ + RCC->CR |= RCC_CR_PLL2ON; + /* Wait till PLL2 is ready */ + while((RCC->CR & RCC_CR_PLL2RDY) == 0) + { + } + + + /* PLL configuration: PLLCLK = PREDIV1 * 6 = 48 MHz */ + RCC->CFGR &= (uint32_t)~(RCC_CFGR_PLLXTPRE | RCC_CFGR_PLLSRC | RCC_CFGR_PLLMULL); + RCC->CFGR |= (uint32_t)(RCC_CFGR_PLLXTPRE_PREDIV1 | RCC_CFGR_PLLSRC_PREDIV1 | + RCC_CFGR_PLLMULL6); +#else + /* PLL configuration: PLLCLK = HSE * 6 = 48 MHz */ + RCC->CFGR &= (uint32_t)((uint32_t)~(RCC_CFGR_PLLSRC | RCC_CFGR_PLLXTPRE | RCC_CFGR_PLLMULL)); + RCC->CFGR |= (uint32_t)(RCC_CFGR_PLLSRC_HSE | RCC_CFGR_PLLMULL6); +#endif /* STM32F10X_CL */ + + /* Enable PLL */ + RCC->CR |= RCC_CR_PLLON; + + /* Wait till PLL is ready */ + while((RCC->CR & RCC_CR_PLLRDY) == 0) + { + } + + /* Select PLL as system clock source */ + RCC->CFGR &= (uint32_t)((uint32_t)~(RCC_CFGR_SW)); + RCC->CFGR |= (uint32_t)RCC_CFGR_SW_PLL; + + /* Wait till PLL is used as system clock source */ + while ((RCC->CFGR & (uint32_t)RCC_CFGR_SWS) != (uint32_t)0x08) + { + } + } + else + { /* If HSE fails to start-up, the application will have wrong clock + configuration. User can add here some code to deal with this error */ + } +} + +#elif defined SYSCLK_FREQ_56MHz +/** + * @brief Sets System clock frequency to 56MHz and configure HCLK, PCLK2 + * and PCLK1 prescalers. + * @note This function should be used only after reset. + * @param None + * @retval None + */ +static void SetSysClockTo56(void) +{ + __IO uint32_t StartUpCounter = 0, HSEStatus = 0; + + /* SYSCLK, HCLK, PCLK2 and PCLK1 configuration ---------------------------*/ + /* Enable HSE */ + RCC->CR |= ((uint32_t)RCC_CR_HSEON); + + /* Wait till HSE is ready and if Time out is reached exit */ + do + { + HSEStatus = RCC->CR & RCC_CR_HSERDY; + StartUpCounter++; + } while((HSEStatus == 0) && (StartUpCounter != HSE_STARTUP_TIMEOUT)); + + if ((RCC->CR & RCC_CR_HSERDY) != RESET) + { + HSEStatus = (uint32_t)0x01; + } + else + { + HSEStatus = (uint32_t)0x00; + } + + if (HSEStatus == (uint32_t)0x01) + { + /* Enable Prefetch Buffer */ + FLASH->ACR |= FLASH_ACR_PRFTBE; + + /* Flash 2 wait state */ + FLASH->ACR &= (uint32_t)((uint32_t)~FLASH_ACR_LATENCY); + FLASH->ACR |= (uint32_t)FLASH_ACR_LATENCY_2; + + /* HCLK = SYSCLK */ + RCC->CFGR |= (uint32_t)RCC_CFGR_HPRE_DIV1; + + /* PCLK2 = HCLK */ + RCC->CFGR |= (uint32_t)RCC_CFGR_PPRE2_DIV1; + + /* PCLK1 = HCLK */ + RCC->CFGR |= (uint32_t)RCC_CFGR_PPRE1_DIV2; + +#ifdef STM32F10X_CL + /* Configure PLLs ------------------------------------------------------*/ + /* PLL2 configuration: PLL2CLK = (HSE / 5) * 8 = 40 MHz */ + /* PREDIV1 configuration: PREDIV1CLK = PLL2 / 5 = 8 MHz */ + + RCC->CFGR2 &= (uint32_t)~(RCC_CFGR2_PREDIV2 | RCC_CFGR2_PLL2MUL | + RCC_CFGR2_PREDIV1 | RCC_CFGR2_PREDIV1SRC); + RCC->CFGR2 |= (uint32_t)(RCC_CFGR2_PREDIV2_DIV5 | RCC_CFGR2_PLL2MUL8 | + RCC_CFGR2_PREDIV1SRC_PLL2 | RCC_CFGR2_PREDIV1_DIV5); + + /* Enable PLL2 */ + RCC->CR |= RCC_CR_PLL2ON; + /* Wait till PLL2 is ready */ + while((RCC->CR & RCC_CR_PLL2RDY) == 0) + { + } + + + /* PLL configuration: PLLCLK = PREDIV1 * 7 = 56 MHz */ + RCC->CFGR &= (uint32_t)~(RCC_CFGR_PLLXTPRE | RCC_CFGR_PLLSRC | RCC_CFGR_PLLMULL); + RCC->CFGR |= (uint32_t)(RCC_CFGR_PLLXTPRE_PREDIV1 | RCC_CFGR_PLLSRC_PREDIV1 | + RCC_CFGR_PLLMULL7); +#else + /* PLL configuration: PLLCLK = HSE * 7 = 56 MHz */ + RCC->CFGR &= (uint32_t)((uint32_t)~(RCC_CFGR_PLLSRC | RCC_CFGR_PLLXTPRE | RCC_CFGR_PLLMULL)); + RCC->CFGR |= (uint32_t)(RCC_CFGR_PLLSRC_HSE | RCC_CFGR_PLLMULL7); + +#endif /* STM32F10X_CL */ + + /* Enable PLL */ + RCC->CR |= RCC_CR_PLLON; + + /* Wait till PLL is ready */ + while((RCC->CR & RCC_CR_PLLRDY) == 0) + { + } + + /* Select PLL as system clock source */ + RCC->CFGR &= (uint32_t)((uint32_t)~(RCC_CFGR_SW)); + RCC->CFGR |= (uint32_t)RCC_CFGR_SW_PLL; + + /* Wait till PLL is used as system clock source */ + while ((RCC->CFGR & (uint32_t)RCC_CFGR_SWS) != (uint32_t)0x08) + { + } + } + else + { /* If HSE fails to start-up, the application will have wrong clock + configuration. User can add here some code to deal with this error */ + } +} + +#elif defined SYSCLK_FREQ_72MHz +/** + * @brief Sets System clock frequency to 72MHz and configure HCLK, PCLK2 + * and PCLK1 prescalers. + * @note This function should be used only after reset. + * @param None + * @retval None + */ +static void SetSysClockTo72(void) +{ + __IO uint32_t StartUpCounter = 0, HSEStatus = 0; + + /* SYSCLK, HCLK, PCLK2 and PCLK1 configuration ---------------------------*/ + /* Enable HSE */ + RCC->CR |= ((uint32_t)RCC_CR_HSEON); + + /* Wait till HSE is ready and if Time out is reached exit */ + do + { + HSEStatus = RCC->CR & RCC_CR_HSERDY; + StartUpCounter++; + } while((HSEStatus == 0) && (StartUpCounter != HSE_STARTUP_TIMEOUT)); + + if ((RCC->CR & RCC_CR_HSERDY) != RESET) + { + HSEStatus = (uint32_t)0x01; + } + else + { + HSEStatus = (uint32_t)0x00; + } + + if (HSEStatus == (uint32_t)0x01) + { + /* Enable Prefetch Buffer */ + FLASH->ACR |= FLASH_ACR_PRFTBE; + + /* Flash 2 wait state */ + FLASH->ACR &= (uint32_t)((uint32_t)~FLASH_ACR_LATENCY); + FLASH->ACR |= (uint32_t)FLASH_ACR_LATENCY_2; + + + /* HCLK = SYSCLK */ + RCC->CFGR |= (uint32_t)RCC_CFGR_HPRE_DIV1; + + /* PCLK2 = HCLK */ + RCC->CFGR |= (uint32_t)RCC_CFGR_PPRE2_DIV1; + + /* PCLK1 = HCLK */ + RCC->CFGR |= (uint32_t)RCC_CFGR_PPRE1_DIV2; + +#ifdef STM32F10X_CL + /* Configure PLLs ------------------------------------------------------*/ + /* PLL2 configuration: PLL2CLK = (HSE / 5) * 8 = 40 MHz */ + /* PREDIV1 configuration: PREDIV1CLK = PLL2 / 5 = 8 MHz */ + + RCC->CFGR2 &= (uint32_t)~(RCC_CFGR2_PREDIV2 | RCC_CFGR2_PLL2MUL | + RCC_CFGR2_PREDIV1 | RCC_CFGR2_PREDIV1SRC); + RCC->CFGR2 |= (uint32_t)(RCC_CFGR2_PREDIV2_DIV5 | RCC_CFGR2_PLL2MUL8 | + RCC_CFGR2_PREDIV1SRC_PLL2 | RCC_CFGR2_PREDIV1_DIV5); + + /* Enable PLL2 */ + RCC->CR |= RCC_CR_PLL2ON; + /* Wait till PLL2 is ready */ + while((RCC->CR & RCC_CR_PLL2RDY) == 0) + { + } + + + /* PLL configuration: PLLCLK = PREDIV1 * 9 = 72 MHz */ + RCC->CFGR &= (uint32_t)~(RCC_CFGR_PLLXTPRE | RCC_CFGR_PLLSRC | RCC_CFGR_PLLMULL); + RCC->CFGR |= (uint32_t)(RCC_CFGR_PLLXTPRE_PREDIV1 | RCC_CFGR_PLLSRC_PREDIV1 | + RCC_CFGR_PLLMULL9); +#else + /* PLL configuration: PLLCLK = HSE * 9 = 72 MHz */ + RCC->CFGR &= (uint32_t)((uint32_t)~(RCC_CFGR_PLLSRC | RCC_CFGR_PLLXTPRE | + RCC_CFGR_PLLMULL)); + RCC->CFGR |= (uint32_t)(RCC_CFGR_PLLSRC_HSE | RCC_CFGR_PLLMULL9); +#endif /* STM32F10X_CL */ + + /* Enable PLL */ + RCC->CR |= RCC_CR_PLLON; + + /* Wait till PLL is ready */ + while((RCC->CR & RCC_CR_PLLRDY) == 0) + { + } + + /* Select PLL as system clock source */ + RCC->CFGR &= (uint32_t)((uint32_t)~(RCC_CFGR_SW)); + RCC->CFGR |= (uint32_t)RCC_CFGR_SW_PLL; + + /* Wait till PLL is used as system clock source */ + while ((RCC->CFGR & (uint32_t)RCC_CFGR_SWS) != (uint32_t)0x08) + { + } + } + else + { /* If HSE fails to start-up, the application will have wrong clock + configuration. User can add here some code to deal with this error */ + } +} +#endif + +/** + * @} + */ + +/** + * @} + */ + +/** + * @} + */ +/******************* (C) COPYRIGHT 2011 STMicroelectronics *****END OF FILE****/ diff --git a/User/bsp/system_stm32f10x.h b/User/bsp/system_stm32f10x.h new file mode 100644 index 0000000..54bc1ab --- /dev/null +++ b/User/bsp/system_stm32f10x.h @@ -0,0 +1,98 @@ +/** + ****************************************************************************** + * @file system_stm32f10x.h + * @author MCD Application Team + * @version V3.5.0 + * @date 11-March-2011 + * @brief CMSIS Cortex-M3 Device Peripheral Access Layer System Header File. + ****************************************************************************** + * @attention + * + * THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS + * WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE + * TIME. AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY + * DIRECT, INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING + * FROM THE CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE + * CODING INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS. + * + *

    © COPYRIGHT 2011 STMicroelectronics

    + ****************************************************************************** + */ + +/** @addtogroup CMSIS + * @{ + */ + +/** @addtogroup stm32f10x_system + * @{ + */ + +/** + * @brief Define to prevent recursive inclusion + */ +#ifndef __SYSTEM_STM32F10X_H +#define __SYSTEM_STM32F10X_H + +#ifdef __cplusplus + extern "C" { +#endif + +/** @addtogroup STM32F10x_System_Includes + * @{ + */ + +/** + * @} + */ + + +/** @addtogroup STM32F10x_System_Exported_types + * @{ + */ + +extern uint32_t SystemCoreClock; /*!< System Clock Frequency (Core Clock) */ + +/** + * @} + */ + +/** @addtogroup STM32F10x_System_Exported_Constants + * @{ + */ + +/** + * @} + */ + +/** @addtogroup STM32F10x_System_Exported_Macros + * @{ + */ + +/** + * @} + */ + +/** @addtogroup STM32F10x_System_Exported_Functions + * @{ + */ + +extern void SystemInit(void); +extern void SystemCoreClockUpdate(void); +/** + * @} + */ + +#ifdef __cplusplus +} +#endif + +#endif /*__SYSTEM_STM32F10X_H */ + +/** + * @} + */ + +/** + * @} + */ +/******************* (C) COPYRIGHT 2011 STMicroelectronics *****END OF FILE****/ diff --git a/keilkill.bat b/keilkill.bat new file mode 100644 index 0000000..f7819f4 --- /dev/null +++ b/keilkill.bat @@ -0,0 +1,30 @@ +del *.bak /s +del *.ddk /s +del *.edk /s +del *.lst /s +del *.lnp /s +del *.mpf /s +del *.mpj /s +del *.obj /s +del *.omf /s +::del *.opt /s ::ɾJLINK +del *.plg /s +del *.rpt /s +del *.tmp /s +del *.__i /s +del *.crf /s +del *.o /s +del *.d /s +del *.axf /s +del *.tra /s +del *.dep /s +del JLinkLog.txt /s + +del *.iex /s +del *.htm /s +del *.sct /s +del *.map /s + +del *.dbgconf /s +del *.Administrator /s +exit